gcc/config/rs6000/rs6000-c.c

   1 /* Subroutines for the C front end on the PowerPC architecture.
   2    Copyright (C) 2002-2018 Free Software Foundation, Inc.
   3
   4    Contributed by Zack Weinberg <zack@codesourcery.com>
   5    and Paolo Bonzini <bonzini@gnu.org>
   6
   7    This file is part of GCC.
   8
   9    GCC is free software; you can redistribute it and/or modify it
  10    under the terms of the GNU General Public License as published
  11    by the Free Software Foundation; either version 3, or (at your
  12    option) any later version.
  13
  14    GCC is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with GCC; see the file COPYING3.  If not see
  21    <http://www.gnu.org/licenses/>.  */
  22
  23 #define IN_TARGET_CODE 1
  24
  25 #include "config.h"
  26 #include "system.h"
  27 #include "coretypes.h"
  28 #include "target.h"
  29 #include "c-family/c-common.h"
  30 #include "memmodel.h"
  31 #include "tm_p.h"
  32 #include "stringpool.h"
  33 #include "stor-layout.h"
  34 #include "c-family/c-pragma.h"
  35 #include "langhooks.h"
  36 #include "c/c-tree.h"
  37
  38
  39
  40 /* Handle the machine specific pragma longcall.  Its syntax is
  41
  42    # pragma longcall ( TOGGLE )
  43
  44    where TOGGLE is either 0 or 1.
  45
  46    rs6000_default_long_calls is set to the value of TOGGLE, changing
  47    whether or not new function declarations receive a longcall
  48    attribute by default.  */
  49
  50 #define SYNTAX_ERROR(gmsgid) do {                                       \
  51   warning (OPT_Wpragmas, gmsgid);                                       \
  52   warning (OPT_Wpragmas, "ignoring malformed #pragma longcall");        \
  53   return;                                                               \
  54 } while (0)
  55
  56 void
  57 rs6000_pragma_longcall (cpp_reader *pfile ATTRIBUTE_UNUSED)
  58 {
  59   tree x, n;
  60
  61   /* If we get here, generic code has already scanned the directive
  62      leader and the word "longcall".  */
  63
  64   if (pragma_lex (&x) != CPP_OPEN_PAREN)
  65     SYNTAX_ERROR ("missing open paren");
  66   if (pragma_lex (&n) != CPP_NUMBER)
  67     SYNTAX_ERROR ("missing number");
  68   if (pragma_lex (&x) != CPP_CLOSE_PAREN)
  69     SYNTAX_ERROR ("missing close paren");
  70
  71   if (n != integer_zero_node && n != integer_one_node)
  72     SYNTAX_ERROR ("number must be 0 or 1");
  73
  74   if (pragma_lex (&x) != CPP_EOF)
  75     warning (OPT_Wpragmas, "junk at end of #pragma longcall");
  76
  77   rs6000_default_long_calls = (n == integer_one_node);
  78 }
  79
  80 /* Handle defining many CPP flags based on TARGET_xxx.  As a general
  81    policy, rather than trying to guess what flags a user might want a
  82    #define for, it's better to define a flag for everything.  */
  83
  84 #define builtin_define(TXT) cpp_define (pfile, TXT)
  85 #define builtin_assert(TXT) cpp_assert (pfile, TXT)
  86
  87 /* Keep the AltiVec keywords handy for fast comparisons.  */
  88 static GTY(()) tree __vector_keyword;
  89 static GTY(()) tree vector_keyword;
  90 static GTY(()) tree __pixel_keyword;
  91 static GTY(()) tree pixel_keyword;
  92 static GTY(()) tree __bool_keyword;
  93 static GTY(()) tree bool_keyword;
  94 static GTY(()) tree _Bool_keyword;
  95 static GTY(()) tree __int128_type;
  96 static GTY(()) tree __uint128_type;
  97
  98 /* Preserved across calls.  */
  99 static tree expand_bool_pixel;
 100
 101 static cpp_hashnode *
 102 altivec_categorize_keyword (const cpp_token *tok)
 103 {
 104   if (tok->type == CPP_NAME)
 105     {
 106       cpp_hashnode *ident = tok->val.node.node;
 107
 108       if (ident == C_CPP_HASHNODE (vector_keyword))
 109         return C_CPP_HASHNODE (__vector_keyword);
 110
 111       if (ident == C_CPP_HASHNODE (pixel_keyword))
 112         return C_CPP_HASHNODE (__pixel_keyword);
 113
 114       if (ident == C_CPP_HASHNODE (bool_keyword))
 115         return C_CPP_HASHNODE (__bool_keyword);
 116
 117       if (ident == C_CPP_HASHNODE (_Bool_keyword))
 118         return C_CPP_HASHNODE (__bool_keyword);
 119
 120       return ident;
 121     }
 122
 123   return 0;
 124 }
 125
 126 static void
 127 init_vector_keywords (void)
 128 {
 129   /* Keywords without two leading underscores are context-sensitive, and hence
 130      implemented as conditional macros, controlled by the
 131      rs6000_macro_to_expand() function below.  If we have ISA 2.07 64-bit
 132      support, record the __int128_t and __uint128_t types.  */
 133
 134   __vector_keyword = get_identifier ("__vector");
 135   C_CPP_HASHNODE (__vector_keyword)->flags |= NODE_CONDITIONAL;
 136
 137   __pixel_keyword = get_identifier ("__pixel");
 138   C_CPP_HASHNODE (__pixel_keyword)->flags |= NODE_CONDITIONAL;
 139
 140   __bool_keyword = get_identifier ("__bool");
 141   C_CPP_HASHNODE (__bool_keyword)->flags |= NODE_CONDITIONAL;
 142
 143   vector_keyword = get_identifier ("vector");
 144   C_CPP_HASHNODE (vector_keyword)->flags |= NODE_CONDITIONAL;
 145
 146   pixel_keyword = get_identifier ("pixel");
 147   C_CPP_HASHNODE (pixel_keyword)->flags |= NODE_CONDITIONAL;
 148
 149   bool_keyword = get_identifier ("bool");
 150   C_CPP_HASHNODE (bool_keyword)->flags |= NODE_CONDITIONAL;
 151
 152   _Bool_keyword = get_identifier ("_Bool");
 153   C_CPP_HASHNODE (_Bool_keyword)->flags |= NODE_CONDITIONAL;
 154
 155   if (TARGET_VADDUQM)
 156     {
 157       __int128_type = get_identifier ("__int128_t");
 158       __uint128_type = get_identifier ("__uint128_t");
 159     }
 160 }
 161
 162 /* Helper function to find out which RID_INT_N_* code is the one for
 163    __int128, if any.  Returns RID_MAX+1 if none apply, which is safe
 164    (for our purposes, since we always expect to have __int128) to
 165    compare against.  */
 166 static int
 167 rid_int128(void)
 168 {
 169   int i;
 170
 171   for (i = 0; i < NUM_INT_N_ENTS; i ++)
 172     if (int_n_enabled_p[i]
 173         && int_n_data[i].bitsize == 128)
 174       return RID_INT_N_0 + i;
 175
 176   return RID_MAX + 1;
 177 }
 178
 179 /* Called to decide whether a conditional macro should be expanded.
 180    Since we have exactly one such macro (i.e, 'vector'), we do not
 181    need to examine the 'tok' parameter.  */
 182
 183 static cpp_hashnode *
 184 rs6000_macro_to_expand (cpp_reader *pfile, const cpp_token *tok)
 185 {
 186   cpp_hashnode *expand_this = tok->val.node.node;
 187   cpp_hashnode *ident;
 188
 189   /* If the current machine does not have altivec, don't look for the
 190      keywords.  */
 191   if (!TARGET_ALTIVEC)
 192     return NULL;
 193
 194   ident = altivec_categorize_keyword (tok);
 195
 196   if (ident != expand_this)
 197     expand_this = NULL;
 198
 199   if (ident == C_CPP_HASHNODE (__vector_keyword))
 200     {
 201       int idx = 0;
 202       do
 203         tok = cpp_peek_token (pfile, idx++);
 204       while (tok->type == CPP_PADDING);
 205       ident = altivec_categorize_keyword (tok);
 206
 207       if (ident == C_CPP_HASHNODE (__pixel_keyword))
 208         {
 209           expand_this = C_CPP_HASHNODE (__vector_keyword);
 210           expand_bool_pixel = __pixel_keyword;
 211         }
 212       else if (ident == C_CPP_HASHNODE (__bool_keyword))
 213         {
 214           expand_this = C_CPP_HASHNODE (__vector_keyword);
 215           expand_bool_pixel = __bool_keyword;
 216         }
 217       /* The boost libraries have code with Iterator::vector vector in it.  If
 218          we allow the normal handling, this module will be called recursively,
 219          and the vector will be skipped.; */
 220       else if (ident && (ident != C_CPP_HASHNODE (__vector_keyword)))
 221         {
 222           enum rid rid_code = (enum rid)(ident->rid_code);
 223           enum node_type itype = ident->type;
 224           /* If there is a function-like macro, check if it is going to be
 225              invoked with or without arguments.  Without following ( treat
 226              it like non-macro, otherwise the following cpp_get_token eats
 227              what should be preserved.  */
 228           if (itype == NT_MACRO && cpp_fun_like_macro_p (ident))
 229             {
 230               int idx2 = idx;
 231               do
 232                 tok = cpp_peek_token (pfile, idx2++);
 233               while (tok->type == CPP_PADDING);
 234               if (tok->type != CPP_OPEN_PAREN)
 235                 itype = NT_VOID;
 236             }
 237           if (itype == NT_MACRO)
 238             {
 239               do
 240                 (void) cpp_get_token (pfile);
 241               while (--idx > 0);
 242               do
 243                 tok = cpp_peek_token (pfile, idx++);
 244               while (tok->type == CPP_PADDING);
 245               ident = altivec_categorize_keyword (tok);
 246               if (ident == C_CPP_HASHNODE (__pixel_keyword))
 247                 {
 248                   expand_this = C_CPP_HASHNODE (__vector_keyword);
 249                   expand_bool_pixel = __pixel_keyword;
 250                   rid_code = RID_MAX;
 251                 }
 252               else if (ident == C_CPP_HASHNODE (__bool_keyword))
 253                 {
 254                   expand_this = C_CPP_HASHNODE (__vector_keyword);
 255                   expand_bool_pixel = __bool_keyword;
 256                   rid_code = RID_MAX;
 257                 }
 258               else if (ident)
 259                 rid_code = (enum rid)(ident->rid_code);
 260             }
 261
 262           if (rid_code == RID_UNSIGNED || rid_code == RID_LONG
 263               || rid_code == RID_SHORT || rid_code == RID_SIGNED
 264               || rid_code == RID_INT || rid_code == RID_CHAR
 265               || rid_code == RID_FLOAT
 266               || (rid_code == RID_DOUBLE && TARGET_VSX)
 267               || (rid_code == rid_int128 () && TARGET_VADDUQM))
 268             {
 269               expand_this = C_CPP_HASHNODE (__vector_keyword);
 270               /* If the next keyword is bool or pixel, it
 271                  will need to be expanded as well.  */
 272               do
 273                 tok = cpp_peek_token (pfile, idx++);
 274               while (tok->type == CPP_PADDING);
 275               ident = altivec_categorize_keyword (tok);
 276
 277               if (ident == C_CPP_HASHNODE (__pixel_keyword))
 278                 expand_bool_pixel = __pixel_keyword;
 279               else if (ident == C_CPP_HASHNODE (__bool_keyword))
 280                 expand_bool_pixel = __bool_keyword;
 281               else
 282                 {
 283                   /* Try two tokens down, too.  */
 284                   do
 285                     tok = cpp_peek_token (pfile, idx++);
 286                   while (tok->type == CPP_PADDING);
 287                   ident = altivec_categorize_keyword (tok);
 288                   if (ident == C_CPP_HASHNODE (__pixel_keyword))
 289                     expand_bool_pixel = __pixel_keyword;
 290                   else if (ident == C_CPP_HASHNODE (__bool_keyword))
 291                     expand_bool_pixel = __bool_keyword;
 292                 }
 293             }
 294
 295           /* Support vector __int128_t, but we don't need to worry about bool
 296              or pixel on this type.  */
 297           else if (TARGET_VADDUQM
 298                    && (ident == C_CPP_HASHNODE (__int128_type)
 299                        || ident == C_CPP_HASHNODE (__uint128_type)))
 300             expand_this = C_CPP_HASHNODE (__vector_keyword);
 301         }
 302     }
 303   else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__pixel_keyword))
 304     {
 305       expand_this = C_CPP_HASHNODE (__pixel_keyword);
 306       expand_bool_pixel = 0;
 307     }
 308   else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__bool_keyword))
 309     {
 310       expand_this = C_CPP_HASHNODE (__bool_keyword);
 311       expand_bool_pixel = 0;
 312     }
 313
 314   return expand_this;
 315 }
 316
 317
 318 /* Define or undefine a single macro.  */
 319
 320 static void
 321 rs6000_define_or_undefine_macro (bool define_p, const char *name)
 322 {
 323   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 324     fprintf (stderr, "#%s %s\n", (define_p) ? "define" : "undef", name);
 325
 326   if (define_p)
 327     cpp_define (parse_in, name);
 328   else
 329     cpp_undef (parse_in, name);
 330 }
 331
 332 /* Define or undefine macros based on the current target.  If the user does
 333    #pragma GCC target, we need to adjust the macros dynamically.  Note, some of
 334    the options needed for builtins have been moved to separate variables, so
 335    have both the target flags and the builtin flags as arguments.  */
 336
 337 void
 338 rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
 339                              HOST_WIDE_INT bu_mask)
 340 {
 341   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 342     fprintf (stderr,
 343              "rs6000_target_modify_macros (%s, " HOST_WIDE_INT_PRINT_HEX
 344              ", " HOST_WIDE_INT_PRINT_HEX ")\n",
 345              (define_p) ? "define" : "undef",
 346              flags, bu_mask);
 347
 348   /* Each of the flags mentioned below controls whether certain
 349      preprocessor macros will be automatically defined when
 350      preprocessing source files for compilation by this compiler.
 351      While most of these flags can be enabled or disabled
 352      explicitly by specifying certain command-line options when
 353      invoking the compiler, there are also many ways in which these
 354      flags are enabled or disabled implicitly, based on compiler
 355      defaults, configuration choices, and on the presence of certain
 356      related command-line options.  Many, but not all, of these
 357      implicit behaviors can be found in file "rs6000.c", the
 358      rs6000_option_override_internal() function.
 359
 360      In general, each of the flags may be automatically enabled in
 361      any of the following conditions:
 362
 363      1. If no -mcpu target is specified on the command line and no
 364         --with-cpu target is specified to the configure command line
 365         and the TARGET_DEFAULT macro for this default cpu host
 366         includes the flag, and the flag has not been explicitly disabled
 367         by command-line options.
 368
 369      2. If the target specified with -mcpu=target on the command line, or
 370         in the absence of a -mcpu=target command-line option, if the
 371         target specified using --with-cpu=target on the configure
 372         command line, is disqualified because the associated binary
 373         tools (e.g. the assembler) lack support for the requested cpu,
 374         and the TARGET_DEFAULT macro for this default cpu host
 375         includes the flag, and the flag has not been explicitly disabled
 376         by command-line options.
 377
 378      3. If either of the above two conditions apply except that the
 379         TARGET_DEFAULT macro is defined to equal zero, and
 380         TARGET_POWERPC64 and
 381         a) BYTES_BIG_ENDIAN and the flag to be enabled is either
 382            MASK_PPC_GFXOPT or MASK_POWERPC64 (flags for "powerpc64"
 383            target), or
 384         b) !BYTES_BIG_ENDIAN and the flag to be enabled is either
 385            MASK_POWERPC64 or it is one of the flags included in
 386            ISA_2_7_MASKS_SERVER (flags for "powerpc64le" target).
 387
 388      4. If a cpu has been requested with a -mcpu=target command-line option
 389         and this cpu has not been disqualified due to shortcomings of the
 390         binary tools, and the set of flags associated with the requested cpu
 391         include the flag to be enabled.  See rs6000-cpus.def for macro
 392         definitions that represent various ABI standards
 393         (e.g. ISA_2_1_MASKS, ISA_3_0_MASKS_SERVER) and for a list of
 394         the specific flags that are associated with each of the cpu
 395         choices that can be specified as the target of a -mcpu=target
 396         compile option, or as the the target of a --with-cpu=target
 397         configure option.  Target flags that are specified in either
 398         of these two ways are considered "implicit" since the flags
 399         are not mentioned specifically by name.
 400
 401         Additional documentation describing behavior specific to
 402         particular flags is provided below, immediately preceding the
 403         use of each relevant flag.
 404
 405      5. If there is no -mcpu=target command-line option, and the cpu
 406         requested by a --with-cpu=target command-line option has not
 407         been disqualified due to shortcomings of the binary tools, and
 408         the set of flags associated with the specified target include
 409         the flag to be enabled.  See the notes immediately above for a
 410         summary of the flags associated with particular cpu
 411         definitions.  */
 412
 413   /* rs6000_isa_flags based options.  */
 414   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
 415   if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
 416     rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
 417   if ((flags & OPTION_MASK_PPC_GFXOPT) != 0)
 418     rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
 419   if ((flags & OPTION_MASK_POWERPC64) != 0)
 420     rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
 421   if ((flags & OPTION_MASK_MFCRF) != 0)
 422     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
 423   if ((flags & OPTION_MASK_POPCNTB) != 0)
 424     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
 425   if ((flags & OPTION_MASK_FPRND) != 0)
 426     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
 427   if ((flags & OPTION_MASK_CMPB) != 0)
 428     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
 429   if ((flags & OPTION_MASK_MFPGPR) != 0)
 430     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X");
 431   if ((flags & OPTION_MASK_POPCNTD) != 0)
 432     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
 433   /* Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
 434      turned on in the following condition:
 435      1. TARGET_P8_VECTOR is enabled and OPTION_MASK_DIRECT_MOVE is not
 436         explicitly disabled.
 437         Hereafter, the OPTION_MASK_DIRECT_MOVE flag is considered to
 438         have been turned on explicitly.
 439      Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
 440      turned off in any of the following conditions:
 441      1. TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX is explicitly
 442         disabled and OPTION_MASK_DIRECT_MOVE was not explicitly
 443         enabled.
 444      2. TARGET_VSX is off.  */
 445   if ((flags & OPTION_MASK_DIRECT_MOVE) != 0)
 446     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
 447   if ((flags & OPTION_MASK_MODULO) != 0)
 448     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
 449   if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
 450     rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
 451   if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
 452     rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__");
 453   /* Note that the OPTION_MASK_ALTIVEC flag is automatically turned on
 454      in any of the following conditions:
 455      1. The command line specifies either -maltivec=le or -maltivec=be.
 456      2. The operating system is Darwin and it is configured for 64
 457         bit.  (See darwin_rs6000_override_options.)
 458      3. The operating system is Darwin and the operating system
 459         version is 10.5 or higher and the user has not explicitly
 460         disabled ALTIVEC by specifying -mcpu=G3 or -mno-altivec and
 461         the compiler is not producing code for integration within the
 462         kernel.  (See darwin_rs6000_override_options.)
 463      Note that the OPTION_MASK_ALTIVEC flag is automatically turned
 464      off in any of the following conditions:
 465      1. The operating system does not support saving of AltiVec
 466         registers (OS_MISSING_ALTIVEC).
 467      2. If an inner context (as introduced by
 468         __attribute__((__target__())) or #pragma GCC target()
 469         requests a target that normally enables the
 470         OPTION_MASK_ALTIVEC flag but the outer-most "main target"
 471         does not support the rs6000_altivec_abi, this flag is
 472         turned off for the inner context unless OPTION_MASK_ALTIVEC
 473         was explicitly enabled for the inner context.  */
 474   if ((flags & OPTION_MASK_ALTIVEC) != 0)
 475     {
 476       const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__";
 477       rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__");
 478       rs6000_define_or_undefine_macro (define_p, vec_str);
 479
 480           /* Define this when supporting context-sensitive keywords.  */
 481       if (!flag_iso)
 482         rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__");
 483     }
 484   /* Note that the OPTION_MASK_VSX flag is automatically turned on in
 485      the following conditions:
 486      1. TARGET_P8_VECTOR is explicitly turned on and the OPTION_MASK_VSX
 487         was not explicitly turned off.  Hereafter, the OPTION_MASK_VSX
 488         flag is considered to have been explicitly turned on.
 489      Note that the OPTION_MASK_VSX flag is automatically turned off in
 490      the following conditions:
 491      1. The operating system does not support saving of AltiVec
 492         registers (OS_MISSING_ALTIVEC).
 493      2. If any of the options TARGET_HARD_FLOAT, TARGET_SINGLE_FLOAT,
 494         or TARGET_DOUBLE_FLOAT are turned off.  Hereafter, the
 495         OPTION_MASK_VSX flag is considered to have been turned off
 496         explicitly.
 497      3. If TARGET_PAIRED_FLOAT was enabled.  Hereafter, the
 498         OPTION_MASK_VSX flag is considered to have been turned off
 499         explicitly.
 500      4. If TARGET_AVOID_XFORM is turned on explicitly at the outermost
 501         compilation context, or if it is turned on by any means in an
 502         inner compilation context.  Hereafter, the OPTION_MASK_VSX
 503         flag is considered to have been turned off explicitly.
 504      5. If TARGET_ALTIVEC was explicitly disabled.  Hereafter, the
 505         OPTION_MASK_VSX flag is considered to have been turned off
 506         explicitly.
 507      6. If an inner context (as introduced by
 508         __attribute__((__target__())) or #pragma GCC target()
 509         requests a target that normally enables the
 510         OPTION_MASK_VSX flag but the outer-most "main target"
 511         does not support the rs6000_altivec_abi, this flag is
 512         turned off for the inner context unless OPTION_MASK_VSX
 513         was explicitly enabled for the inner context.  */
 514   if ((flags & OPTION_MASK_VSX) != 0)
 515     rs6000_define_or_undefine_macro (define_p, "__VSX__");
 516   if ((flags & OPTION_MASK_HTM) != 0)
 517     {
 518       rs6000_define_or_undefine_macro (define_p, "__HTM__");
 519       /* Tell the user that our HTM insn patterns act as memory barriers.  */
 520       rs6000_define_or_undefine_macro (define_p, "__TM_FENCE__");
 521     }
 522   /* Note that the OPTION_MASK_P8_VECTOR flag is automatically turned
 523      on in the following conditions:
 524      1. TARGET_P9_VECTOR is explicitly turned on and
 525         OPTION_MASK_P8_VECTOR is not explicitly turned off.
 526         Hereafter, the OPTION_MASK_P8_VECTOR flag is considered to
 527         have been turned off explicitly.
 528      Note that the OPTION_MASK_P8_VECTOR flag is automatically turned
 529      off in the following conditions:
 530      1. If any of TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX
 531         were turned off explicitly and OPTION_MASK_P8_VECTOR flag was
 532         not turned on explicitly.
 533      2. If TARGET_ALTIVEC is turned off.  Hereafter, the
 534         OPTION_MASK_P8_VECTOR flag is considered to have been turned off
 535         explicitly.
 536      3. If TARGET_VSX is turned off and OPTION_MASK_P8_VECTOR was not
 537         explicitly enabled.  If TARGET_VSX is explicitly enabled, the
 538         OPTION_MASK_P8_VECTOR flag is hereafter also considered to
 539         have been turned off explicitly.  */
 540   if ((flags & OPTION_MASK_P8_VECTOR) != 0)
 541     rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__");
 542   /* Note that the OPTION_MASK_P9_VECTOR flag is automatically turned
 543      off in the following conditions:
 544      1. If TARGET_P8_VECTOR is turned off and OPTION_MASK_P9_VECTOR is
 545         not turned on explicitly. Hereafter, if OPTION_MASK_P8_VECTOR
 546         was turned on explicitly, the OPTION_MASK_P9_VECTOR flag is
 547         also considered to have been turned off explicitly.
 548      Note that the OPTION_MASK_P9_VECTOR is automatically turned on
 549      in the following conditions:
 550      1. If TARGET_P9_MINMAX was turned on explicitly.
 551         Hereafter, THE OPTION_MASK_P9_VECTOR flag is considered to
 552         have been turned on explicitly.  */
 553   if ((flags & OPTION_MASK_P9_VECTOR) != 0)
 554     rs6000_define_or_undefine_macro (define_p, "__POWER9_VECTOR__");
 555   /* Note that the OPTION_MASK_QUAD_MEMORY flag is automatically
 556      turned off in the following conditions:
 557      1. If TARGET_POWERPC64 is turned off.
 558      2. If WORDS_BIG_ENDIAN is false (non-atomic quad memory
 559         load/store are disabled on little endian).  */
 560   if ((flags & OPTION_MASK_QUAD_MEMORY) != 0)
 561     rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY__");
 562   /* Note that the OPTION_MASK_QUAD_MEMORY_ATOMIC flag is automatically
 563      turned off in the following conditions:
 564      1. If TARGET_POWERPC64 is turned off.
 565      Note that the OPTION_MASK_QUAD_MEMORY_ATOMIC flag is
 566      automatically turned on in the following conditions:
 567      1. If TARGET_QUAD_MEMORY and this flag was not explicitly
 568         disabled.  */
 569   if ((flags & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
 570     rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY_ATOMIC__");
 571   /* Note that the OPTION_MASK_CRYPTO flag is automatically turned off
 572      in the following conditions:
 573      1. If any of TARGET_HARD_FLOAT or TARGET_ALTIVEC or TARGET_VSX
 574         are turned off explicitly and OPTION_MASK_CRYPTO is not turned
 575         on explicitly.
 576      2. If TARGET_ALTIVEC is turned off.  */
 577   if ((flags & OPTION_MASK_CRYPTO) != 0)
 578     rs6000_define_or_undefine_macro (define_p, "__CRYPTO__");
 579   if ((flags & OPTION_MASK_FLOAT128_KEYWORD) != 0)
 580     {
 581       rs6000_define_or_undefine_macro (define_p, "__FLOAT128__");
 582       if (define_p)
 583         rs6000_define_or_undefine_macro (true, "__float128=__ieee128");
 584       else
 585         rs6000_define_or_undefine_macro (false, "__float128");
 586     }
 587   /* OPTION_MASK_FLOAT128_HARDWARE can be turned on if -mcpu=power9 is used or
 588      via the target attribute/pragma.  */
 589   if ((flags & OPTION_MASK_FLOAT128_HW) != 0)
 590     rs6000_define_or_undefine_macro (define_p, "__FLOAT128_HARDWARE__");
 591
 592   /* options from the builtin masks.  */
 593   /* Note that RS6000_BTM_PAIRED is enabled only if
 594      TARGET_PAIRED_FLOAT is enabled (e.g. -mpaired).  */
 595   if ((bu_mask & RS6000_BTM_PAIRED) != 0)
 596     rs6000_define_or_undefine_macro (define_p, "__PAIRED__");
 597   /* Note that RS6000_BTM_CELL is enabled only if (rs6000_cpu ==
 598      PROCESSOR_CELL) (e.g. -mcpu=cell).  */
 599   if ((bu_mask & RS6000_BTM_CELL) != 0)
 600     rs6000_define_or_undefine_macro (define_p, "__PPU__");
 601 }
 602
 603 void
 604 rs6000_cpu_cpp_builtins (cpp_reader *pfile)
 605 {
 606   /* Define all of the common macros.  */
 607   rs6000_target_modify_macros (true, rs6000_isa_flags,
 608                                rs6000_builtin_mask_calculate ());
 609
 610   if (TARGET_FRE)
 611     builtin_define ("__RECIP__");
 612   if (TARGET_FRES)
 613     builtin_define ("__RECIPF__");
 614   if (TARGET_FRSQRTE)
 615     builtin_define ("__RSQRTE__");
 616   if (TARGET_FRSQRTES)
 617     builtin_define ("__RSQRTEF__");
 618   if (TARGET_FLOAT128_TYPE)
 619     builtin_define ("__FLOAT128_TYPE__");
 620   if (TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (TFmode))
 621     builtin_define ("__ibm128=long double");
 622 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
 623   builtin_define ("__BUILTIN_CPU_SUPPORTS__");
 624 #endif
 625
 626   if (TARGET_EXTRA_BUILTINS && cpp_get_options (pfile)->lang != CLK_ASM)
 627     {
 628       /* Define the AltiVec syntactic elements.  */
 629       builtin_define ("__vector=__attribute__((altivec(vector__)))");
 630       builtin_define ("__pixel=__attribute__((altivec(pixel__))) unsigned short");
 631       builtin_define ("__bool=__attribute__((altivec(bool__))) unsigned");
 632
 633       if (!flag_iso)
 634         {
 635           builtin_define ("vector=vector");
 636           builtin_define ("pixel=pixel");
 637           builtin_define ("bool=bool");
 638           builtin_define ("_Bool=_Bool");
 639           init_vector_keywords ();
 640
 641           /* Enable context-sensitive macros.  */
 642           cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand;
 643         }
 644     }
 645   if (!TARGET_HARD_FLOAT || !TARGET_DOUBLE_FLOAT)
 646     builtin_define ("_SOFT_DOUBLE");
 647   /* Used by lwarx/stwcx. errata work-around.  */
 648   if (rs6000_cpu == PROCESSOR_PPC405)
 649     builtin_define ("__PPC405__");
 650   /* Used by libstdc++.  */
 651   if (TARGET_NO_LWSYNC)
 652     builtin_define ("__NO_LWSYNC__");
 653
 654   if (TARGET_EXTRA_BUILTINS)
 655     {
 656       /* For the VSX builtin functions identical to Altivec functions, just map
 657          the altivec builtin into the vsx version (the altivec functions
 658          generate VSX code if -mvsx).  */
 659       builtin_define ("__builtin_vsx_xxland=__builtin_vec_and");
 660       builtin_define ("__builtin_vsx_xxlandc=__builtin_vec_andc");
 661       builtin_define ("__builtin_vsx_xxlnor=__builtin_vec_nor");
 662       builtin_define ("__builtin_vsx_xxlor=__builtin_vec_or");
 663       builtin_define ("__builtin_vsx_xxlxor=__builtin_vec_xor");
 664       builtin_define ("__builtin_vsx_xxsel=__builtin_vec_sel");
 665       builtin_define ("__builtin_vsx_vperm=__builtin_vec_perm");
 666
 667       /* Also map the a and m versions of the multiply/add instructions to the
 668          builtin for people blindly going off the instruction manual.  */
 669       builtin_define ("__builtin_vsx_xvmaddadp=__builtin_vsx_xvmadddp");
 670       builtin_define ("__builtin_vsx_xvmaddmdp=__builtin_vsx_xvmadddp");
 671       builtin_define ("__builtin_vsx_xvmaddasp=__builtin_vsx_xvmaddsp");
 672       builtin_define ("__builtin_vsx_xvmaddmsp=__builtin_vsx_xvmaddsp");
 673       builtin_define ("__builtin_vsx_xvmsubadp=__builtin_vsx_xvmsubdp");
 674       builtin_define ("__builtin_vsx_xvmsubmdp=__builtin_vsx_xvmsubdp");
 675       builtin_define ("__builtin_vsx_xvmsubasp=__builtin_vsx_xvmsubsp");
 676       builtin_define ("__builtin_vsx_xvmsubmsp=__builtin_vsx_xvmsubsp");
 677       builtin_define ("__builtin_vsx_xvnmaddadp=__builtin_vsx_xvnmadddp");
 678       builtin_define ("__builtin_vsx_xvnmaddmdp=__builtin_vsx_xvnmadddp");
 679       builtin_define ("__builtin_vsx_xvnmaddasp=__builtin_vsx_xvnmaddsp");
 680       builtin_define ("__builtin_vsx_xvnmaddmsp=__builtin_vsx_xvnmaddsp");
 681       builtin_define ("__builtin_vsx_xvnmsubadp=__builtin_vsx_xvnmsubdp");
 682       builtin_define ("__builtin_vsx_xvnmsubmdp=__builtin_vsx_xvnmsubdp");
 683       builtin_define ("__builtin_vsx_xvnmsubasp=__builtin_vsx_xvnmsubsp");
 684       builtin_define ("__builtin_vsx_xvnmsubmsp=__builtin_vsx_xvnmsubsp");
 685     }
 686
 687   /* Map the old _Float128 'q' builtins into the new 'f128' builtins.  */
 688   if (TARGET_FLOAT128_TYPE)
 689     {
 690       builtin_define ("__builtin_fabsq=__builtin_fabsf128");
 691       builtin_define ("__builtin_copysignq=__builtin_copysignf128");
 692       builtin_define ("__builtin_nanq=__builtin_nanf128");
 693       builtin_define ("__builtin_nansq=__builtin_nansf128");
 694       builtin_define ("__builtin_infq=__builtin_inff128");
 695       builtin_define ("__builtin_huge_valq=__builtin_huge_valf128");
 696     }
 697
 698   /* Tell users they can use __builtin_bswap{16,64}.  */
 699   builtin_define ("__HAVE_BSWAP__");
 700
 701   /* May be overridden by target configuration.  */
 702   RS6000_CPU_CPP_ENDIAN_BUILTINS();
 703
 704   if (TARGET_LONG_DOUBLE_128)
 705     {
 706       builtin_define ("__LONG_DOUBLE_128__");
 707       builtin_define ("__LONGDOUBLE128");
 708
 709       if (TARGET_IEEEQUAD)
 710         {
 711           /* Older versions of GLIBC used __attribute__((__KC__)) to create the
 712              IEEE 128-bit floating point complex type for C++ (which does not
 713              support _Float128 _Complex).  If the default for long double is
 714              IEEE 128-bit mode, the library would need to use
 715              __attribute__((__TC__)) instead.  Defining __KF__ and __KC__
 716              is a stop-gap to build with the older libraries, until we
 717              get an updated library.  */
 718           builtin_define ("__LONG_DOUBLE_IEEE128__");
 719           builtin_define ("__KF__=__TF__");
 720           builtin_define ("__KC__=__TC__");
 721         }
 722       else
 723         builtin_define ("__LONG_DOUBLE_IBM128__");
 724     }
 725
 726   switch (TARGET_CMODEL)
 727     {
 728       /* Deliberately omit __CMODEL_SMALL__ since that was the default
 729          before --mcmodel support was added.  */
 730     case CMODEL_MEDIUM:
 731       builtin_define ("__CMODEL_MEDIUM__");
 732       break;
 733     case CMODEL_LARGE:
 734       builtin_define ("__CMODEL_LARGE__");
 735       break;
 736     default:
 737       break;
 738     }
 739
 740   switch (rs6000_current_abi)
 741     {
 742     case ABI_V4:
 743       builtin_define ("_CALL_SYSV");
 744       break;
 745     case ABI_AIX:
 746       builtin_define ("_CALL_AIXDESC");
 747       builtin_define ("_CALL_AIX");
 748       builtin_define ("_CALL_ELF=1");
 749       break;
 750     case ABI_ELFv2:
 751       builtin_define ("_CALL_ELF=2");
 752       break;
 753     case ABI_DARWIN:
 754       builtin_define ("_CALL_DARWIN");
 755       break;
 756     default:
 757       break;
 758     }
 759
 760   /* Vector element order.  */
 761   if (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2))
 762     builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_BIG_ENDIAN__");
 763   else
 764     builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_LITTLE_ENDIAN__");
 765
 766   /* Let the compiled code know if 'f' class registers will not be available.  */
 767   if (TARGET_SOFT_FLOAT)
 768     builtin_define ("__NO_FPRS__");
 769
 770   /* Whether aggregates passed by value are aligned to a 16 byte boundary
 771      if their alignment is 16 bytes or larger.  */
 772   if ((TARGET_MACHO && rs6000_darwin64_abi)
 773       || DEFAULT_ABI == ABI_ELFv2
 774       || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
 775     builtin_define ("__STRUCT_PARM_ALIGN__=16");
 776
 777   /* Generate defines for Xilinx FPU. */
 778   if (rs6000_xilinx_fpu)
 779     {
 780       builtin_define ("_XFPU");
 781       if (rs6000_single_float && ! rs6000_double_float)
 782         {
 783           if (rs6000_simple_fpu)
 784             builtin_define ("_XFPU_SP_LITE");
 785           else
 786             builtin_define ("_XFPU_SP_FULL");
 787         }
 788       if (rs6000_double_float)
 789         {
 790           if (rs6000_simple_fpu)
 791             builtin_define ("_XFPU_DP_LITE");
 792           else
 793             builtin_define ("_XFPU_DP_FULL");
 794         }
 795     }
 796 }
 797
 798 \f
 799 struct altivec_builtin_types
 800 {
 801   enum rs6000_builtins code;
 802   enum rs6000_builtins overloaded_code;
 803   signed char ret_type;
 804   signed char op1;
 805   signed char op2;
 806   signed char op3;
 807 };
 808
 809 const struct altivec_builtin_types altivec_overloaded_builtins[] = {
 810   /* Unary AltiVec/VSX builtins.  */
 811   { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V16QI,
 812     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
 813   { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V8HI,
 814     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
 815   { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI,
 816     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
 817   { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI,
 818     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
 819   { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF,
 820     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 821   { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP,
 822     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 823   { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V16QI,
 824     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
 825   { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V8HI,
 826     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
 827   { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V4SI,
 828     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
 829   { ALTIVEC_BUILTIN_VEC_CEIL, ALTIVEC_BUILTIN_VRFIP,
 830     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 831   { ALTIVEC_BUILTIN_VEC_CEIL, VSX_BUILTIN_XVRDPIP,
 832     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 833   { ALTIVEC_BUILTIN_VEC_EXPTE, ALTIVEC_BUILTIN_VEXPTEFP,
 834     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 835   { ALTIVEC_BUILTIN_VEC_FLOOR, VSX_BUILTIN_XVRDPIM,
 836     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 837   { ALTIVEC_BUILTIN_VEC_FLOOR, ALTIVEC_BUILTIN_VRFIM,
 838     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 839   { ALTIVEC_BUILTIN_VEC_LOGE, ALTIVEC_BUILTIN_VLOGEFP,
 840     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 841   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 842     RS6000_BTI_void, RS6000_BTI_V4SI, 0, 0 },
 843   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 844     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, 0, 0 },
 845   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 846     RS6000_BTI_void, RS6000_BTI_bool_V4SI, 0, 0 },
 847   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 848     RS6000_BTI_void, RS6000_BTI_V8HI, 0, 0 },
 849   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 850     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, 0, 0 },
 851   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 852     RS6000_BTI_void, RS6000_BTI_bool_V8HI, 0, 0 },
 853   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 854     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, 0, 0 },
 855   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 856     RS6000_BTI_void, RS6000_BTI_V16QI, 0, 0 },
 857   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 858     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, 0, 0 },
 859   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 860     RS6000_BTI_void, RS6000_BTI_bool_V16QI, 0, 0 },
 861   { ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VREFP,
 862     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 863   { ALTIVEC_BUILTIN_VEC_RE, VSX_BUILTIN_XVREDP,
 864     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 865   { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN,
 866     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 867   { ALTIVEC_BUILTIN_VEC_ROUND, VSX_BUILTIN_XVRDPI,
 868     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 869   { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP,
 870     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
 871   { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF,
 872     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
 873   { ALTIVEC_BUILTIN_VEC_RSQRT, ALTIVEC_BUILTIN_VRSQRTFP,
 874     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 875   { ALTIVEC_BUILTIN_VEC_RSQRT, VSX_BUILTIN_RSQRT_2DF,
 876     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 877   { ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VRSQRTEFP,
 878     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 879   { ALTIVEC_BUILTIN_VEC_RSQRTE, VSX_BUILTIN_XVRSQRTEDP,
 880     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 881   { ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VRFIZ,
 882     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 883   { ALTIVEC_BUILTIN_VEC_TRUNC, VSX_BUILTIN_XVRDPIZ,
 884     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 885   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
 886     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
 887   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
 888     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
 889   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
 890     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
 891   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
 892     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
 893   { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
 894     RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
 895   { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
 896     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
 897   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,
 898     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
 899   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,
 900     RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
 901   { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
 902     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
 903   { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
 904     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
 905   { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
 906     RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
 907   { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
 908     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
 909   { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
 910     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
 911   { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
 912     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
 913   { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
 914     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
 915   { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
 916     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
 917   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
 918     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
 919   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
 920     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
 921   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX,
 922     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
 923   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
 924     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
 925   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
 926     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
 927   { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
 928     RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
 929   { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
 930     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
 931   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX,
 932     RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
 933   { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
 934     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
 935   { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
 936     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
 937   { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
 938     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
 939   { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
 940     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
 941   { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
 942     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
 943   { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
 944     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
 945
 946   /* Binary AltiVec/VSX builtins.  */
 947   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 948     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
 949   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 950     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
 951   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 952     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
 953   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 954     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
 955   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 956     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
 957   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 958     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
 959   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 960     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
 961   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 962     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
 963   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 964     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
 965   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 966     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
 967   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 968     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
 969   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 970     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
 971   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 972     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
 973   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 974     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
 975   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 976     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
 977   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 978     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
 979   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 980     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
 981   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 982     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
 983   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 984     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
 985   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 986     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
 987   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 988     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
 989   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 990     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
 991   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 992     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
 993   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 994     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
 995   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP,
 996     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
 997   { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP,
 998     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
 999   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
1000     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
1001   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
1002     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
1003     RS6000_BTI_unsigned_V1TI, 0 },
1004   { ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP,
1005     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1006   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1007     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1008   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1009     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1010   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1011     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1012   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1013     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1014   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1015     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1016   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1017     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1018   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1019     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1020   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1021     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1022   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1023     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1024   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1025     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1026   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1027     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1028   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1029     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1030   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1031     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1032   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1033     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1034   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1035     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1036   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1037     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1038   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1039     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1040   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1041     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1042   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1043     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1044   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1045     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1046   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1047     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1048   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1049     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1050   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1051     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1052   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1053     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1054   { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
1055     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1056   { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
1057     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
1058     RS6000_BTI_unsigned_V4SI, 0 },
1059   { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
1060     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
1061     RS6000_BTI_unsigned_V1TI, 0 },
1062   { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
1063     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
1064   { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
1065     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
1066     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
1067   { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
1068     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
1069   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1070     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1071   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1072     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1073   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1074     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1075   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1076     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1077   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1078     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1079   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1080     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1081   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1082     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1083   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1084     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1085   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1086     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1087   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1088     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1089   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1090     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1091   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1092     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1093   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1094     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1095   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1096     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1097   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1098     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1099   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1100     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1101   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1102     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1103   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1104     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1105   { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1106     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1107   { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1108     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1109   { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1110     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1111   { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1112     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1113   { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1114     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1115   { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1116     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1117   { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1118     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1119   { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1120     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1121   { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1122     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1123   { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1124     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1125   { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1126     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1127   { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1128     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1129   { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1130     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1131   { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1132     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1133   { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1134     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1135   { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1136     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1137   { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1138     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1139   { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1140     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1141   { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1142     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1143   { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1144     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1145   { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1146     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1147   { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1148     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1149   { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1150     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1151   { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1152     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1153   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1154     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1155   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1156     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
1157   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1158     RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
1159   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1160     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1161   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1162     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
1163   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1164     RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
1165   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1166     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1167   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1168     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1169   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1170     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1171   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1172     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1173   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1174     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1175   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1176     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1177   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1178     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1179   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1180     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1181   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1182     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1183   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1184     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1185   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1186     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1187   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1188     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1189   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1190     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1191   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1192     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1193   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1194     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1195   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1196     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1197   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1198     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1199   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1200     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1201   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1202     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1203   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1204     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1205   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1206     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1207   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1208     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1209   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1210     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1211   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1212     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1213   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1214     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1215   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1216     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1217   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1218     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1219   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1220     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1221   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1222     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1223   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1224     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
1225   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1226     RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
1227   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1228     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1229   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1230     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
1231   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1232     RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
1233   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1234     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1235   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1236     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1237   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1238     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1239   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1240     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1241   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1242     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1243   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1244     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1245   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1246     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1247   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1248     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1249   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1250     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1251   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1252     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1253   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1254     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1255   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1256     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1257   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1258     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1259   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1260     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1261   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1262     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1263   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1264     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1265   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1266     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1267   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1268     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1269   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1270     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1271   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1272     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1273   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1274     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1275   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1276     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1277   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1278     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1279   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1280     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1281   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1282     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1283   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1284     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1285   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1286     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1287   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1288     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1289   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUB,
1290     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1291   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSB,
1292     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1293   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUH,
1294     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1295   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSH,
1296     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1297   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUW,
1298     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1299   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSW,
1300     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1301   { ALTIVEC_BUILTIN_VEC_VAVGSW, ALTIVEC_BUILTIN_VAVGSW,
1302     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1303   { ALTIVEC_BUILTIN_VEC_VAVGUW, ALTIVEC_BUILTIN_VAVGUW,
1304     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1305   { ALTIVEC_BUILTIN_VEC_VAVGSH, ALTIVEC_BUILTIN_VAVGSH,
1306     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1307   { ALTIVEC_BUILTIN_VEC_VAVGUH, ALTIVEC_BUILTIN_VAVGUH,
1308     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1309   { ALTIVEC_BUILTIN_VEC_VAVGSB, ALTIVEC_BUILTIN_VAVGSB,
1310     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1311   { ALTIVEC_BUILTIN_VEC_VAVGUB, ALTIVEC_BUILTIN_VAVGUB,
1312     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1313   { ALTIVEC_BUILTIN_VEC_CMPB, ALTIVEC_BUILTIN_VCMPBFP,
1314     RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1315   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1316     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1317   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1318     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1319   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1320     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1321   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1322     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1323   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1324     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1325   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1326     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1327   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1328     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1329   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1330     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1331   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1332     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1333   { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1334     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1335   { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1336     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1337   { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1338     RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1339   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP,
1340     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1341   { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP,
1342     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1343   { ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VCMPEQFP,
1344     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1345
1346   { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
1347     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1348   { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
1349     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1350
1351   { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
1352     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1353   { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
1354     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1355
1356   { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
1357     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1358   { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
1359     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1360
1361   { ALTIVEC_BUILTIN_VEC_CMPGE, ALTIVEC_BUILTIN_VCMPGEFP,
1362     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1363   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_XVCMPGEDP,
1364     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1365   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_16QI,
1366     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
1367   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U16QI,
1368     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
1369     RS6000_BTI_unsigned_V16QI, 0},
1370   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_8HI,
1371     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
1372   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U8HI,
1373     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
1374     RS6000_BTI_unsigned_V8HI, 0},
1375   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_4SI,
1376     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
1377   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U4SI,
1378     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
1379     RS6000_BTI_unsigned_V4SI, 0},
1380   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_2DI,
1381     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
1382   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U2DI,
1383     RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
1384     RS6000_BTI_unsigned_V2DI, 0},
1385   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUB,
1386     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1387   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSB,
1388     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1389   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUH,
1390     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1391   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSH,
1392     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1393   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUW,
1394     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1395   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW,
1396     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1397   { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD,
1398     RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1399   { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD,
1400     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1401   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP,
1402     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1403   { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP,
1404     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1405   { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP,
1406     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1407   { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
1408     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1409   { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
1410     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1411   { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
1412     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1413   { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
1414     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1415   { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
1416     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1417   { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
1418     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1419   { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
1420     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1421   { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
1422     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1423   { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
1424     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1425   { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
1426     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1427   { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
1428     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1429   { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
1430     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1431   { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP,
1432     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1433   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_XVCMPGEDP,
1434     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1435   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_16QI,
1436     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
1437   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U16QI,
1438     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
1439     RS6000_BTI_unsigned_V16QI, 0},
1440   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_8HI,
1441     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
1442   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U8HI,
1443     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
1444     RS6000_BTI_unsigned_V8HI, 0},
1445   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_4SI,
1446     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
1447   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U4SI,
1448     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
1449     RS6000_BTI_unsigned_V4SI, 0},
1450   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_2DI,
1451     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
1452   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U2DI,
1453     RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
1454     RS6000_BTI_unsigned_V2DI, 0},
1455   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUB,
1456     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1457   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSB,
1458     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1459   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUH,
1460     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1461   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSH,
1462     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1463   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUW,
1464     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1465   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW,
1466     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1467   { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD,
1468     RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1469   { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD,
1470     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1471   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP,
1472     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1473   { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP,
1474     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1475   { ALTIVEC_BUILTIN_VEC_COPYSIGN, VSX_BUILTIN_CPSGNDP,
1476     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1477   { ALTIVEC_BUILTIN_VEC_COPYSIGN, ALTIVEC_BUILTIN_COPYSIGN_V4SF,
1478     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1479   { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFUX,
1480     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
1481   { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX,
1482     RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
1483   { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE,
1484     RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0},
1485   { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE,
1486     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0},
1487   { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX,
1488     RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
1489   { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX,
1490     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
1491   { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS,
1492     RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
1493   { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE,
1494     RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
1495   { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS,
1496     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
1497   { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE,
1498     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
1499   { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP,
1500     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1501   { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP,
1502     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1503   { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_DIV_V2DI,
1504     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1505   { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI,
1506     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1507   { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVSXDDP,
1508     RS6000_BTI_V2DF, RS6000_BTI_V2DI, 0, 0 },
1509   { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVUXDDP,
1510     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1511
1512   { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SI,
1513     RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1514   { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_UNS_DOUBLEE_V4SI,
1515     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1516   { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SF,
1517     RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1518
1519   { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SI,
1520     RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1521   { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_UNS_DOUBLEO_V4SI,
1522     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1523   { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SF,
1524     RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1525
1526   { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SI,
1527     RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1528   { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_UNS_DOUBLEH_V4SI,
1529     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1530   { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SF,
1531     RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1532
1533   { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SI,
1534     RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1535   { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_UNS_DOUBLEL_V4SI,
1536     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1537   { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SF,
1538     RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1539
1540   { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVSXWSP_V4SF,
1541     RS6000_BTI_V4SF, RS6000_BTI_V4SI, 0, 0 },
1542   { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVUXWSP_V4SF,
1543     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1544   { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DF,
1545     RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1546   { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DI,
1547     RS6000_BTI_V4SF, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1548   { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_UNS_FLOAT2_V2DI,
1549     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI,
1550     RS6000_BTI_unsigned_V2DI, 0 },
1551   { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DF,
1552     RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 },
1553   { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DI,
1554     RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 },
1555   { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_UNS_FLOATE_V2DI,
1556     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1557   { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DF,
1558     RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 },
1559   { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DI,
1560     RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 },
1561   { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_UNS_FLOATO_V2DI,
1562     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1563
1564   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1565     RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 },
1566   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1567     RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V1TI, 0 },
1568   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1569     RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
1570   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1571     RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
1572
1573   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
1574     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1575   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1576     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1577   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1578     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1579     ~RS6000_BTI_unsigned_V2DI, 0 },
1580   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1581     RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1582   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
1583     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1584   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
1585     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1586   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1587     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1588   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1589     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1590   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1591     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1592   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1593     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1594   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1595     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1596   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1597     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1598   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1599     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1600   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1601     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1602   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1603     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1604   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1605     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1606   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1607     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1608   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1609     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1610   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1611     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1612   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1613     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1614   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1615     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1616   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1617     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1618   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1619     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1620   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1621     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1622   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1623     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1624   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1625     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1626   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1627     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1628   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1629     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1630   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1631     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1632   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1633     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1634   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1635     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1636   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1637     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1638   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1639     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1640   { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1641     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1642   { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1643     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1644   { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1645     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1646   { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1647     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1648   { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1649     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1650   { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1651     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1652   { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1653     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1654   { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1655     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1656   { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1657     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1658
1659   /*     vector float vec_ldl (int, vector float *);
1660          vector float vec_ldl (int, float *); */
1661   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1662     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1663   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1664     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1665
1666   /*     vector bool int vec_ldl (int, vector bool int *);
1667          vector bool int vec_ldl (int, bool int *);
1668               vector int vec_ldl (int, vector int *);
1669               vector int vec_ldl (int, int *);
1670      vector unsigned int vec_ldl (int, vector unsigned int *);
1671      vector unsigned int vec_ldl (int, unsigned int *); */
1672   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1673     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1674   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1675     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_int, 0 },
1676   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1677     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1678   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1679     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1680   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1681     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1682   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1683     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1684
1685   /*     vector bool short vec_ldl (int, vector bool short *);
1686          vector bool short vec_ldl (int, bool short *);
1687               vector pixel vec_ldl (int, vector pixel *);
1688               vector short vec_ldl (int, vector short *);
1689               vector short vec_ldl (int, short *);
1690      vector unsigned short vec_ldl (int, vector unsigned short *);
1691      vector unsigned short vec_ldl (int, unsigned short *); */
1692   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1693     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1694   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1695     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_short, 0 },
1696   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1697     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1698   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1699     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1700   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1701     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1702   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1703     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1704   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1705     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1706
1707   /*     vector bool char vec_ldl (int, vector bool char *);
1708          vector bool char vec_ldl (int, bool char *);
1709               vector char vec_ldl (int, vector char *);
1710               vector char vec_ldl (int, char *);
1711      vector unsigned char vec_ldl (int, vector unsigned char *);
1712      vector unsigned char vec_ldl (int, unsigned char *); */
1713   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1714     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1715   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1716     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_char, 0 },
1717   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1718     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1719   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1720     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1721   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1722     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1723     ~RS6000_BTI_unsigned_V16QI, 0 },
1724   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1725     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1726
1727   /*     vector double vec_ldl (int, vector double *);
1728          vector double vec_ldl (int, double *); */
1729   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
1730     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1731   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
1732     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1733
1734   /*          vector long long vec_ldl (int, vector long long *);
1735               vector long long vec_ldl (int, long long *);
1736      vector unsigned long long vec_ldl (int, vector unsigned long long *);
1737      vector unsigned long long vec_ldl (int, unsigned long long *);
1738          vector bool long long vec_ldl (int, vector bool long long *);
1739          vector bool long long vec_ldl (int, bool long long *); */
1740   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1741     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1742   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1743     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1744   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1745     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1746     ~RS6000_BTI_unsigned_V2DI, 0 },
1747   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1748     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1749     ~RS6000_BTI_unsigned_long_long, 0 },
1750   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1751     RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1752   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1753     RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_long_long, 0 },
1754
1755   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1756     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1757   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1758     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1759   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1760     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1761   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1762     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1763   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1764     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1765   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1766     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1767   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1768     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1769   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1770     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1771   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1772     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1773   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1774     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1775   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1776     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1777   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1778     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1779   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1780     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1781   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1782     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1783     ~RS6000_BTI_unsigned_long_long, 0 },
1784   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1785     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1786   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1787     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1788   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1789     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1790   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1791     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1792   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1793     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1794   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1795     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1796   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1797     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1798   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1799     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1800   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1801     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1802   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1803     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1804   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1805     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1806   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1807     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1808   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1809     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1810   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1811     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1812     ~RS6000_BTI_unsigned_long_long, 0 },
1813   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1814     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1815   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1816     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1817   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1818     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1819   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1820     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1821   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1822     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1823   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1824     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1825   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1826     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1827   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1828     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1829   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1830     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1831   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1832     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1833   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1834     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1835   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1836     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1837   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1838     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1839   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1840     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1841   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1842     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1843   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1844     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1845   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1846     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1847   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1848     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1849   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1850     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1851   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1852     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1853   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1854     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1855   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1856     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1857   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1858     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1859   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1860     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1861   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1862     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1863   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1864     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1865   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1866     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1867   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1868     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1869   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1870     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1871   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1872     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1873   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1874     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1875   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1876     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1877   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1878     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1879   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1880     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1881   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1882     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1883   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1884     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1885   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1886     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1887   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1888     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1889   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1890     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1891   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1892     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1893   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1894     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1895   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1896     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1897   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1898     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1899   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1900     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1901   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1902     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1903   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1904     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1905   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1906     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1907   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1908     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1909   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1910     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1911   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1912     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1913   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1914     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1915   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1916     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1917   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1918     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1919   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1920     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1921   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1922     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1923   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1924     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1925   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1926     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1927   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1928     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1929   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1930     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1931   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1932     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1933   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1934     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1935   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1936     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1937   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1938     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1939   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1940     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1941   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1942     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1943   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1944     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1945   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1946     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1947   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1948     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1949   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1950     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1951   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1952     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1953   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1954     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1955   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1956     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1957   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1958     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1959   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1960     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1961   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1962     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1963   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1964     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1965   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1966     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1967   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1968     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1969   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1970     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1971   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1972     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1973   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1974     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1975   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1976     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1977   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1978     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1979   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1980     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1981   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1982     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1983   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1984     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1985   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1986     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1987   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1988     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1989   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1990     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1991   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1992     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1993   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1994     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1995   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1996     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1997   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1998     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1999   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
2000     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2001   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
2002     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2003   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
2004     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2005   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP,
2006     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2007   { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP,
2008     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2009   { ALTIVEC_BUILTIN_VEC_VMAXFP, ALTIVEC_BUILTIN_VMAXFP,
2010     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2011   { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
2012     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2013   { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
2014     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2015   { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
2016     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2017   { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
2018     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2019   { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
2020     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2021   { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
2022     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2023   { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
2024     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2025   { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
2026     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2027   { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
2028     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2029   { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
2030     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2031   { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
2032     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2033   { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
2034     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2035   { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
2036     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2037   { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
2038     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2039   { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
2040     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2041   { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
2042     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2043   { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
2044     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2045   { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
2046     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2047   { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
2048     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2049   { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
2050     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2051   { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
2052     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2053   { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
2054     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2055   { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
2056     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2057   { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
2058     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2059   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
2060     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2061   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
2062     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2063   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
2064     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2065   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
2066     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2067   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
2068     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2069   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
2070     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2071   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
2072     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2073   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
2074     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2075   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
2076     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2077   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
2078     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2079   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
2080     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2081   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DF,
2082     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2083   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2084     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2085   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2086     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2087   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2088     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2089   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2090     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2091   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2092     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2093   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2094     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2095   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2096     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2097   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2098     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2099   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2100     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2101   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2102     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2103   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2104     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2105   { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2106     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2107   { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2108     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2109   { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2110     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2111   { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2112     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2113   { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
2114     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2115   { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
2116     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2117   { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
2118     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2119   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
2120     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2121   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
2122     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2123   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
2124     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2125   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2126     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2127   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2128     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2129   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2130     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2131   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2132     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2133   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2134     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2135   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2136     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2137   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2138     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2139   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2140     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2141   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DF,
2142     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2143   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2144     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2145   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2146     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2147   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2148     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2149   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2150     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2151   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2152     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2153   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2154     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2155   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2156     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2157   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2158     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2159   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2160     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2161   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2162     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2163   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2164     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2165   { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2166     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2167   { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2168     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2169   { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2170     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2171   { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2172     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2173   { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2174     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2175   { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2176     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2177   { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2178     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2179   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2180     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2181   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2182     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2183   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2184     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2185   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2186     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2187   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2188     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2189   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2190     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2191   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2192     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2193   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2194     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2195   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2196     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2197   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2198     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2199   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2200     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2201   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2202     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2203   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2204     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2205   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2206     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2207   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2208     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2209   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2210     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2211   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2212     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2213   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2214     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2215   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2216     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2217   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2218     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2219   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2220     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2221   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2222     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2223   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2224     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2225   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2226     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2227   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP,
2228     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2229   { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP,
2230     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2231   { ALTIVEC_BUILTIN_VEC_VMINFP, ALTIVEC_BUILTIN_VMINFP,
2232     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2233   { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2234     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2235   { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2236     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2237   { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2238     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2239   { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2240     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2241   { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2242     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2243   { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2244     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2245   { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2246     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2247   { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2248     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2249   { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2250     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2251   { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2252     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2253   { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2254     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2255   { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2256     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2257   { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2258     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2259   { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2260     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2261   { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2262     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2263   { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2264     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2265   { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2266     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2267   { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2268     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2269   { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2270     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2271   { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2272     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2273   { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2274     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2275   { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2276     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2277   { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2278     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2279   { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2280     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2281   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB,
2282     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2283   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB,
2284     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2285   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH,
2286     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2287   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
2288     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2289   { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULESW,
2290     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2291   { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULEUW,
2292     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
2293     RS6000_BTI_unsigned_V4SI, 0 },
2294   { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB,
2295     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2296   { ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VMULESB,
2297     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2298   { ALTIVEC_BUILTIN_VEC_VMULEUH, ALTIVEC_BUILTIN_VMULEUH,
2299     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2300   { ALTIVEC_BUILTIN_VEC_VMULESH, ALTIVEC_BUILTIN_VMULESH,
2301     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2302   { ALTIVEC_BUILTIN_VEC_VMULEUW, P8V_BUILTIN_VMULEUW,
2303     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2304   { ALTIVEC_BUILTIN_VEC_VMULESW, P8V_BUILTIN_VMULESW,
2305     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2306   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUB,
2307     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2308   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSB,
2309     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2310   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH,
2311     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2312   { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOSW,
2313     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2314   { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOUW,
2315     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
2316     RS6000_BTI_unsigned_V4SI, 0 },
2317   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
2318     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2319   { ALTIVEC_BUILTIN_VEC_VMULOSH, ALTIVEC_BUILTIN_VMULOSH,
2320     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2321   { ALTIVEC_BUILTIN_VEC_VMULOUH, ALTIVEC_BUILTIN_VMULOUH,
2322     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2323   { ALTIVEC_BUILTIN_VEC_VMULOSB, ALTIVEC_BUILTIN_VMULOSB,
2324     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2325   { ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VMULOUB,
2326     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2327   { ALTIVEC_BUILTIN_VEC_VMULOUW, P8V_BUILTIN_VMULOUW,
2328     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2329   { ALTIVEC_BUILTIN_VEC_VMULOSW, P8V_BUILTIN_VMULOSW,
2330     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2331
2332   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V16QI,
2333     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
2334   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V8HI,
2335     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
2336   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SI,
2337     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
2338   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V2DI,
2339     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
2340   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SF,
2341     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2342   { ALTIVEC_BUILTIN_VEC_NABS, VSX_BUILTIN_XVNABSDP,
2343     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2344   { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRDPI,
2345     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2346   { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI,
2347     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2348
2349   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2350     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2351   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2352     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2353   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2354     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2355   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2356     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2357   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2358     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2359   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2360     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2361   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2362     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2363   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2364     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2365   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2366     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2367   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2368     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2369   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2370     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2371   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2372     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2373   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2374     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2375   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2376     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2377   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2378     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2379   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2380     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2381   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2382     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2383   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2384     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2385   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2386     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2387   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2388     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
2389   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2390     RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
2391   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2392     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2393   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2394     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
2395   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2396     RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
2397   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2398     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2399   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2400     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2401   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2402     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2403   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2404     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2405   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2406     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2407   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2408     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2409   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2410     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2411   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2412     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2413   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2414     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2415   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2416     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2417   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2418     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2419   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2420     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2421   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2422     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2423   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2424     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2425   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2426     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2427   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2428     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2429   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2430     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2431   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2432     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2433   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2434     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2435   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2436     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2437   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2438     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2439   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2440     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2441   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2442     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2443   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2444     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2445   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2446     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2447   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2448     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2449   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2450     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2451   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2452     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2453   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2454     RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2455   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2456     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2457   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2458     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2459   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2460     RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2461   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2462     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2463   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2464     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2465   { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2466     RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2467   { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2468     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2469   { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2470     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2471   { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2472     RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2473
2474   { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V16QI,
2475     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
2476   { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V8HI,
2477     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
2478   { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SI,
2479     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
2480   { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DI,
2481     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
2482   { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SF,
2483     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2484   { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DF,
2485     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2486
2487   { P9V_BUILTIN_VEC_CONVERT_4F32_8I16, P9V_BUILTIN_CONVERT_4F32_8I16,
2488     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2489
2490   { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI,
2491     RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2492   { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI,
2493     RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2494   { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI,
2495     RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2496   { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI,
2497     RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2498   { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI,
2499     RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2500   { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI,
2501     RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2502   { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI,
2503     RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2504   { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI,
2505     RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2506   { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI,
2507     RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2508   { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI,
2509     RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2510   { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI,
2511     RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2512   { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI,
2513     RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2514   { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI,
2515     RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2516   { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI,
2517     RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2518   { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI,
2519     RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2520   { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI,
2521     RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2522   { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI,
2523     RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2524   { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI,
2525     RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2526
2527   { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2528     P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI,
2529     RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2530   { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2531     P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI, RS6000_BTI_UINTSI,
2532     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2533   { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2534     P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI,
2535     RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2536   { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2537     P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI,
2538     RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2539   { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2540     P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI,
2541     RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2542   { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2543     P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI,
2544     RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2545
2546   { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2547     RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2548   { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2549     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2550   { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2551     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2552   { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2553     RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2554   { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2555     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2556   { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2557     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2558   { ALTIVEC_BUILTIN_VEC_PACKPX, ALTIVEC_BUILTIN_VPKPX,
2559     RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2560   { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUHUS,
2561     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2562   { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSHSS,
2563     RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2564   { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUWUS,
2565     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2566   { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS,
2567     RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2568   { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
2569     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2570   { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
2571     RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2572   { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
2573     RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2574   { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
2575     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2576   { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,
2577     RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2578   { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,
2579     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2580   { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUHUS,
2581     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2582   { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSHUS,
2583     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2584   { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUWUS,
2585     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2586   { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS,
2587     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2588   { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,
2589     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2590   { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,
2591     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2592   { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS,
2593     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2594   { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS,
2595     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2596   { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRDPIC,
2597     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2598   { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRSPIC,
2599     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2600   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2601     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2602   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2603     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2604   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2605     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2606   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2607     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2608   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2609     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2610   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2611     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2612   { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2613     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2614   { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2615     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2616   { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2617     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2618   { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2619     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2620   { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2621     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2622   { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2623     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2624   { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2625     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2626   { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2627     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2628   { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLWMI,
2629     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2630     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
2631   { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLDMI,
2632     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2633     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
2634   { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLWNM,
2635     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2636     RS6000_BTI_unsigned_V4SI, 0 },
2637   { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLDNM,
2638     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2639     RS6000_BTI_unsigned_V2DI, 0 },
2640   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2641     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2642   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2643     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2644   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2645     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2646   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2647     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2648   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2649     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2650   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2651     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2652   { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2653     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2654   { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2655     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2656   { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP,
2657     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2658   { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP,
2659     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2660   { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2661     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2662   { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2663     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2664   { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2665     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2666   { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2667     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2668   { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2669     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2670   { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2671     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2672   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2673     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2674   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2675     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2676   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2677     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2678   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2679     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2680   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2681     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2682   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2683     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2684   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2685     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2686   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2687     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2688   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2689     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2690   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2691     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2692   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2693     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2694   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2695     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2696   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2697     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2698   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2699     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2700   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2701     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2702   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2703     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2704   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2705     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2706   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2707     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2708   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2709     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2710   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2711     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2712   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2713     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2714   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2715     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2716   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2717     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2718   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2719     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2720   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2721     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2722   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2723     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2724   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2725     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2726   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2727     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2728   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2729     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2730   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2731     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2732
2733   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2734     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2735   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2736     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2737   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2738     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2739   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2740     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2741   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2742     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V8HI, 0 },
2743
2744   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2745     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2746   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2747     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2748   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2749     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2750   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2751     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2752   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2753     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2754   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2755     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2756   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2757     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2758   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2759     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2760   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2761     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2762   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2763     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2764   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2765     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2766   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2767     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2768   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2769     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2770   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2771     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2772   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2773     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2774   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2775     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2776   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2777     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 },
2778   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2779     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2780   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2781     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 },
2782   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2783     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2784   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2785     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2786   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2787     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2788   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2789     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2790   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2791     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2792   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2793     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2794   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2795     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2796   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2797     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2798   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2799     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2800   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2801     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2802   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2803     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2804   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2805     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2806   { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DF,
2807     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
2808   { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2809     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0 },
2810   { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2811     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 },
2812   { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2813     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 0 },
2814   { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2815     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2816   { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2817     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2818   { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2819     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2820   { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2821     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2822   { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2823     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2824   { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2825     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2826   { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2827     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2828   { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2829     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2830   { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2831     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2832   { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2833     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2834   { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2835     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2836   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2837     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2838   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2839     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2840   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2841     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2842   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2843     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2844   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2845     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2846   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2847     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2848   { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2849     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2850   { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2851     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2852   { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2853     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2854   { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2855     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2856   { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2857     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2858   { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2859     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2860   { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2861     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2862   { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2863     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2864   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2865     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2866   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2867     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2868   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2869     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2870   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2871     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2872   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2873     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2874   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2875     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2876   { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2877     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2878   { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2879     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2880   { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2881     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2882   { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2883     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2884   { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2885     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2886   { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2887     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2888   { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2889     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2890   { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2891     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2892   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2893     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2894   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2895     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2896   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2897     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2898   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2899     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2900   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2901     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2902   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2903     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2904   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2905     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2906   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2907     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2908   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2909     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2910   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2911     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2912   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2913     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2914   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2915     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2916   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2917     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2918   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2919     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2920   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2921     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2922   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2923     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2924   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2925     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2926   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2927     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2928   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2929     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2930   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2931     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2932   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2933     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2934   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2935     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2936   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2937     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2938   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2939     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2940   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2941     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2942   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2943     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2944   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2945     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2946   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2947     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2948   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2949     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2950   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2951     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2952   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2953     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2954   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2955     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2956   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2957     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2958   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2959     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2960   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2961     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2962   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2963     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2964   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2965     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2966   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2967     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2968   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2969     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2970   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2971     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2972   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2973     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2974   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2975     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2976   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2977     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2978   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2979     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2980   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2981     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2982   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2983     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2984   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2985     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2986   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2987     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2988   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2989     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 },
2990   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2991     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2992   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2993     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 },
2994   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2995     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2996
2997   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2998     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2999   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
3000     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3001   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
3002     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3003   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
3004     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3005   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
3006     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
3007   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
3008     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3009   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
3010     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
3011   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
3012     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
3013   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
3014     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
3015   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
3016     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3017   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
3018     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3019   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
3020     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3021   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
3022     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
3023   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
3024     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
3025   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
3026     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3027   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
3028     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3029   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
3030     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
3031   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
3032     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3033   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
3034     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
3035   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
3036     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
3037   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
3038     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
3039   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
3040     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
3041   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
3042     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
3043   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
3044     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
3045   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP,
3046     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
3047   { ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP,
3048     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
3049   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
3050     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
3051   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
3052     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
3053     RS6000_BTI_unsigned_V1TI, 0 },
3054   { ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP,
3055     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
3056   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3057     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
3058   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3059     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
3060   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3061     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3062   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3063     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
3064   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3065     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3066   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3067     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3068   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3069     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
3070   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3071     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3072   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3073     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
3074   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3075     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3076   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3077     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
3078   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3079     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3080   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3081     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
3082   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3083     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
3084   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3085     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3086   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3087     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3088   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3089     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3090   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3091     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3092   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3093     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
3094   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3095     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3096   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3097     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3098   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3099     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3100   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3101     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3102   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3103     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
3104
3105   { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW,
3106     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3107   { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW,
3108     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3109   { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ,
3110     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
3111     RS6000_BTI_unsigned_V1TI, 0 },
3112   { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ,
3113     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
3114
3115   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
3116     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3117   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
3118     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
3119   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
3120     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3121   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
3122     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3123   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
3124     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3125   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
3126     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3127   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
3128     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3129   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
3130     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3131   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
3132     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3133   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
3134     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
3135   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
3136     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
3137   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
3138     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
3139   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
3140     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3141   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
3142     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
3143   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
3144     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3145   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
3146     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
3147   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
3148     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
3149   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
3150     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3151   { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
3152     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3153   { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
3154     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
3155   { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
3156     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
3157   { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
3158     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3159   { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
3160     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
3161   { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
3162     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3163   { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
3164     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3165   { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
3166     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
3167   { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
3168     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
3169   { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
3170     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
3171   { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
3172     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
3173   { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3174     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3175   { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3176     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
3177   { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3178     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3179   { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3180     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3181   { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3182     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3183   { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
3184     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3185   { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
3186     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3187   { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
3188     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3189   { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3190     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3191   { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3192     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
3193   { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3194     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3195   { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3196     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3197   { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3198     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
3199   { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4UBS,
3200     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
3201   { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SBS,
3202     RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
3203   { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SHS,
3204     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
3205   { ALTIVEC_BUILTIN_VEC_VSUM4SHS, ALTIVEC_BUILTIN_VSUM4SHS,
3206     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
3207   { ALTIVEC_BUILTIN_VEC_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SBS,
3208     RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
3209   { ALTIVEC_BUILTIN_VEC_VSUM4UBS, ALTIVEC_BUILTIN_VSUM4UBS,
3210     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
3211   { ALTIVEC_BUILTIN_VEC_SUM2S, ALTIVEC_BUILTIN_VSUM2SWS,
3212     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3213   { ALTIVEC_BUILTIN_VEC_SUMS, ALTIVEC_BUILTIN_VSUMSWS,
3214     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3215
3216   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF,
3217     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3218   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF,
3219     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
3220   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
3221     RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
3222   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
3223     RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 },
3224   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
3225     RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
3226   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3227     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3228   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3229     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
3230   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3231     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
3232   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3233     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3234     ~RS6000_BTI_unsigned_V2DI, 0 },
3235   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3236     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3237     ~RS6000_BTI_unsigned_long_long, 0 },
3238   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3239     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
3240
3241   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF,
3242     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3243   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF,
3244     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3245   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
3246     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
3247   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
3248     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3249   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
3250     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
3251   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
3252     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3253   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
3254     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
3255   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
3256     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3257   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
3258     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
3259   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
3260     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3261   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
3262     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
3263   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
3264     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3265   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
3266     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3267     ~RS6000_BTI_unsigned_V16QI, 0 },
3268   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
3269     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
3270
3271   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF,
3272     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3273   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF,
3274     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
3275   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI,
3276     RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
3277   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI,
3278     RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
3279   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
3280     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3281   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
3282     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
3283   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
3284     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3285     ~RS6000_BTI_unsigned_V2DI, 0 },
3286   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
3287     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3288     ~RS6000_BTI_unsigned_long_long, 0 },
3289   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF,
3290     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3291   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF,
3292     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3293   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
3294     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
3295   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
3296     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3297   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
3298     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
3299   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
3300     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3301   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
3302     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
3303   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
3304     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3305   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
3306     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
3307   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
3308     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3309   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
3310     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
3311   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
3312     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3313   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
3314     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3315     ~RS6000_BTI_unsigned_V16QI, 0 },
3316   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
3317     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
3318   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3319     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
3320   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3321     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
3322   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3323     RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
3324   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3325     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
3326   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3327     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
3328   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3329     RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
3330   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3331     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
3332   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3333     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
3334   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3335     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
3336   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3337     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
3338   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3339     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
3340   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3341     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
3342   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3343     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
3344   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3345     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
3346   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3347     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
3348   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3349     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
3350   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3351     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3352   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3353     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3354   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3355     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
3356   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3357     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3358   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3359     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
3360   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3361     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
3362   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3363     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
3364   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3365     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
3366   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3367     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3368   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3369     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3370   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3371     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3372   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3373     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3374   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3375     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
3376   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3377     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3378   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3379     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3380   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3381     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3382   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3383     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
3384   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3385     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3386
3387   /* Ternary AltiVec/VSX builtins.  */
3388   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3389     RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3390   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3391     RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3392   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3393     RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3394   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3395     RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3396   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3397     RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3398   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3399     RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3400   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3401     RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3402   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3403     RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3404   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3405     RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3406   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3407     RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3408   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3409     RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3410   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3411     RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3412   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3413     RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3414   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3415     RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3416   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3417     RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3418   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3419     RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3420   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3421     RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3422   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3423     RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3424   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3425     RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3426   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3427     RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3428   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3429     RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3430   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3431     RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3432   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3433     RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3434   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3435     RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3436   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3437     RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3438   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3439     RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3440   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3441     RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3442   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3443     RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3444   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3445     RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3446   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3447     RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3448   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3449     RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3450   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3451     RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3452   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3453     RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3454   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3455     RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3456   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3457     RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3458   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3459     RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3460   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3461     RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3462   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3463     RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3464   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3465     RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3466   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3467     RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3468   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3469     RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3470   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3471     RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3472   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3473     RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3474   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3475     RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3476   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3477     RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3478   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3479     RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3480   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3481     RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3482   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3483     RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3484   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3485     RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3486   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3487     RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3488   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3489     RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3490   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3491     RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3492   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3493     RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3494   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3495     RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3496   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3497     RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3498   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3499     RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3500   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3501     RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3502   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3503     RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3504   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3505     RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3506   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3507     RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3508   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3509     RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3510   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3511     RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3512   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3513     RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3514   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3515     RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3516   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3517     RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3518   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3519     RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3520   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3521     RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3522   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3523     RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3524   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3525     RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3526   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3527     RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3528   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3529     RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3530   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3531     RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3532   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3533     RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3534   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3535     RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3536   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3537     RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3538   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3539     RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3540   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3541     RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3542   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3543     RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3544   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3545     RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3546   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3547     RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3548   { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMADDFP,
3549     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3550   { ALTIVEC_BUILTIN_VEC_MADD, VSX_BUILTIN_XVMADDDP,
3551     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3552   { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3553     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3554   { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3555     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3556   { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3557     RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3558   { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3559     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3560   { ALTIVEC_BUILTIN_VEC_MADDS, ALTIVEC_BUILTIN_VMHADDSHS,
3561     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3562   { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3563     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3564   { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3565     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3566   { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3567     RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3568   { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3569     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3570   { ALTIVEC_BUILTIN_VEC_MRADDS, ALTIVEC_BUILTIN_VMHRADDSHS,
3571     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3572   { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBSP,
3573     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3574   { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBDP,
3575     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3576   { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUBM,
3577     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3578   { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMMBM,
3579     RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3580   { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUHM,
3581     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3582   { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMSHM,
3583     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3584   { ALTIVEC_BUILTIN_VEC_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMSHM,
3585     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3586   { ALTIVEC_BUILTIN_VEC_VMSUMUHM, ALTIVEC_BUILTIN_VMSUMUHM,
3587     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3588   { ALTIVEC_BUILTIN_VEC_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMMBM,
3589     RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3590   { ALTIVEC_BUILTIN_VEC_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMUBM,
3591     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3592   { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMUHS,
3593     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3594   { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMSHS,
3595     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3596   { ALTIVEC_BUILTIN_VEC_VMSUMSHS, ALTIVEC_BUILTIN_VMSUMSHS,
3597     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3598   { ALTIVEC_BUILTIN_VEC_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMUHS,
3599     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3600   { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDSP,
3601     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3602   { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDDP,
3603     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3604   { ALTIVEC_BUILTIN_VEC_NMSUB, ALTIVEC_BUILTIN_VNMSUBFP,
3605     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3606   { ALTIVEC_BUILTIN_VEC_NMSUB, VSX_BUILTIN_XVNMSUBDP,
3607     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3608   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DF,
3609     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V16QI },
3610   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3611     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI },
3612   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3613     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI },
3614   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3615     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3616     RS6000_BTI_unsigned_V16QI },
3617   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF,
3618     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI },
3619   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3620     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI },
3621   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3622     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI },
3623   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3624     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI },
3625   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3626     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI },
3627   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3628     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI },
3629   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3630     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI },
3631   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3632     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI },
3633   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3634     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3635   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3636     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3637   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3638     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3639   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3640     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3641   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3642     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3643
3644   { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3645     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
3646     RS6000_BTI_bool_V16QI },
3647   { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3648     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
3649   { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3650     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3651     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3652
3653   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3654     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI },
3655   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3656     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI },
3657   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3658     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DI },
3659   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3660     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3661   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3662     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
3663   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3664     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI },
3665   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3666     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
3667   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3668     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
3669   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3670     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
3671   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3672     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI },
3673   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3674     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3675     RS6000_BTI_bool_V2DI },
3676   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3677     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3678     RS6000_BTI_unsigned_V2DI },
3679   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3680     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI },
3681   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3682     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI },
3683   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3684     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3685   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3686     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SI },
3687   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3688     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
3689   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3690     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI },
3691   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3692     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
3693   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3694     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
3695   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3696     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
3697   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3698     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
3699   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3700     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
3701   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3702     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI },
3703   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3704     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
3705   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3706     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3707   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3708     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
3709   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3710     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
3711   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3712     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
3713   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3714     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3715   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3716     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
3717   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3718     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3719   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3720     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3721   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3722     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3723   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SF,
3724     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
3725   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3726     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
3727   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3728     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI },
3729   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3730     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI },
3731   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3732     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
3733   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3734     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI },
3735   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3736     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI },
3737   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3738     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI },
3739   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3740     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
3741   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3742     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
3743   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3744     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI },
3745   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF,
3746     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
3747   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3748     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI },
3749   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3750     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
3751   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3752     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI },
3753
3754   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3755     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
3756     RS6000_BTI_INTSI },
3757   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3758     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3759     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
3760   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3761     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
3762     RS6000_BTI_INTSI },
3763   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3764     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3765     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI },
3766   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3767     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
3768     RS6000_BTI_INTSI },
3769   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3770     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3771     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI },
3772   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3773     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
3774     RS6000_BTI_INTSI },
3775   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3776     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3777     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI },
3778
3779   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
3780     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3781   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3782     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3783   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3784     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3785     ~RS6000_BTI_unsigned_V2DI },
3786   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3787     RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3788     ~RS6000_BTI_bool_V2DI },
3789   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
3790     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3791   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
3792     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3793   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3794     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3795   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3796     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3797   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3798     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3799   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3800     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3801   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3802     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3803   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3804     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3805   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3806     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3807   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3808     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3809   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3810     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3811   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3812     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3813   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3814     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3815   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3816     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3817   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3818     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3819   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3820     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3821   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3822     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3823   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3824     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3825   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3826     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3827   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3828     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3829   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3830     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3831   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3832     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3833   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3834     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3835   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3836     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3837   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3838     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3839   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3840     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3841   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3842     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3843   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3844     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3845   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3846     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3847   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3848     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3849   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3850     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3851   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3852     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3853   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3854     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3855   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3856     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3857   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3858     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3859   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3860     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3861   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3862     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3863   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3864     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3865   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3866     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3867   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3868     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3869   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3870     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3871   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3872     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3873   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3874     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3875   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3876     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3877   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3878     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3879   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3880     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3881   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3882     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3883   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3884     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3885   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3886     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3887   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3888     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3889   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3890     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3891   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3892     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3893   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3894     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3895   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3896     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3897   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3898     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3899   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3900     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3901   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3902     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3903   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3904     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3905   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3906     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3907   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
3908     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3909   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
3910     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3911   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3912     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3913   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3914     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3915   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3916     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3917   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3918     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3919   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3920     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3921   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3922     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3923   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3924     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3925   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3926     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3927   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3928     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3929   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3930     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3931   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3932     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3933   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3934     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3935   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3936     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3937   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3938     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3939   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3940     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3941   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3942     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3943   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3944     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3945   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3946     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3947   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3948     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3949   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3950     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3951   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3952     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3953   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3954     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3955   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
3956     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3957   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
3958     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3959   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3960     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3961   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3962     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3963     ~RS6000_BTI_unsigned_V2DI },
3964   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3965     RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3966     ~RS6000_BTI_bool_V2DI },
3967   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3968     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3969   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3970     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3971   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3972     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3973   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3974     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3975   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3976     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3977   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3978     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3979   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3980     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3981   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3982     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3983   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3984     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3985   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3986     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3987   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3988     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3989   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3990     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3991   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3992     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3993   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3994     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3995   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3996     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3997   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3998     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3999   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
4000     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
4001   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
4002     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
4003   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4004     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4005   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4006     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4007   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4008     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
4009   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4010     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4011   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4012     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4013   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4014     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
4015   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4016     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
4017   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4018     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
4019   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4020     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
4021   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4022     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4023   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4024     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4025   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4026     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
4027   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4028     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
4029   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4030     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
4031   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4032     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4033   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4034     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4035   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4036     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
4037   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4038     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
4039   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4040     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4041   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4042     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4043   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4044     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
4045   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4046     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4047   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4048     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4049   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4050     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
4051   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4052     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
4053   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4054     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
4055   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4056     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
4057   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4058     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4059   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4060     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4061   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4062     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
4063   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4064     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
4065   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4066     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
4067   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4068     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4069   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4070     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4071   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4072     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
4073   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4074     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
4075   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4076     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4077   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4078     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4079   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4080     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
4081   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4082     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4083   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4084     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4085   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4086     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
4087   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4088     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
4089   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4090     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
4091   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4092     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
4093   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4094     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4095   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4096     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4097   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4098     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
4099   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4100     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
4101   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4102     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
4103   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4104     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4105   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4106     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4107   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4108     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
4109   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4110     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
4111   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DF,
4112     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
4113   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
4114     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
4115   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
4116     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4117     ~RS6000_BTI_unsigned_V2DI },
4118   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
4119     RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
4120     ~RS6000_BTI_bool_V2DI },
4121   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF,
4122     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4123   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF,
4124     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4125   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4126     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4127   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4128     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4129   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4130     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
4131   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4132     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
4133   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4134     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
4135   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4136     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
4137   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4138     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4139   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4140     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4141   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4142     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4143   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4144     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
4145   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4146     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
4147   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4148     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
4149   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4150     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
4151   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4152     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4153   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4154     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4155   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4156     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4157   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4158     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
4159   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4160     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
4161   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4162     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
4163   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4164     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
4165   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4166     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4167   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4168     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
4169   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF,
4170     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
4171   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF,
4172     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
4173   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI,
4174     RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI },
4175   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI,
4176     RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI },
4177   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
4178     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
4179   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
4180     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI,
4181     ~RS6000_BTI_long_long },
4182   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
4183     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4184     ~RS6000_BTI_unsigned_V2DI },
4185   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
4186     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4187     ~RS6000_BTI_unsigned_long_long },
4188   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF,
4189     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4190   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF,
4191     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4192   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
4193     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4194   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
4195     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4196   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
4197     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4198     ~RS6000_BTI_unsigned_V4SI },
4199   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
4200     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4201     ~RS6000_BTI_UINTSI },
4202   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
4203     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4204   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
4205     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4206   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
4207     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4208     ~RS6000_BTI_unsigned_V8HI },
4209   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
4210     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4211     ~RS6000_BTI_UINTHI },
4212   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
4213     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4214   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
4215     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4216   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
4217     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4218     ~RS6000_BTI_unsigned_V16QI },
4219   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
4220     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4221     ~RS6000_BTI_UINTQI },
4222   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
4223     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
4224   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
4225     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4226     RS6000_BTI_INTSI },
4227   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
4228     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
4229   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
4230     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4231     RS6000_BTI_INTSI },
4232   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
4233     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
4234   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
4235     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4236     RS6000_BTI_INTSI },
4237   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
4238     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
4239   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
4240     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4241     RS6000_BTI_INTSI },
4242   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SF,
4243     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
4244   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DF,
4245     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
4246
4247   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DF,
4248     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
4249   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
4250     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
4251   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
4252     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4253     RS6000_BTI_INTSI },
4254   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SF,
4255     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
4256   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
4257     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
4258   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
4259     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4260     RS6000_BTI_INTSI },
4261   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
4262     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
4263   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
4264     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4265     RS6000_BTI_INTSI },
4266   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
4267     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
4268   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
4269     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4270     RS6000_BTI_INTSI },
4271
4272   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
4273     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
4274   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
4275     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
4276   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4277     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
4278   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4279     RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
4280   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4281     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
4282   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4283     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
4284   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4285     RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
4286   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4287     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4288     ~RS6000_BTI_unsigned_V2DI, 0 },
4289   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4290     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long, 0 },
4291   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4292     RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
4293   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
4294     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
4295   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
4296     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
4297   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4298     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
4299   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4300     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
4301   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4302     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
4303   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4304     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
4305   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4306     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4307     ~RS6000_BTI_unsigned_V4SI, 0 },
4308   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4309     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
4310   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4311     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4312     ~RS6000_BTI_unsigned_long, 0 },
4313   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4314     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
4315   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4316     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
4317   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4318     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
4319   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4320     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
4321   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4322     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4323     ~RS6000_BTI_unsigned_V8HI, 0 },
4324   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4325     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
4326   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4327     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
4328   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4329     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
4330   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4331     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
4332   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4333     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4334     ~RS6000_BTI_unsigned_V16QI, 0 },
4335   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4336     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
4337
4338   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
4339     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
4340   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
4341     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
4342   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4343     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTDI,
4344     ~RS6000_BTI_long_long },
4345   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4346     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTDI,
4347     ~RS6000_BTI_unsigned_long_long },
4348   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI,
4349     RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_INTTI },
4350   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI,
4351     RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_UINTTI },
4352   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4353     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
4354   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4355     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4356     ~RS6000_BTI_unsigned_V2DI },
4357   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4358     RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
4359     ~RS6000_BTI_bool_V2DI },
4360   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
4361     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4362   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
4363     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4364   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4365     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4366   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4367     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4368   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4369     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4370     ~RS6000_BTI_unsigned_V4SI },
4371   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4372     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4373     ~RS6000_BTI_UINTSI },
4374   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4375     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4376     ~RS6000_BTI_bool_V4SI },
4377   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4378     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4379     ~RS6000_BTI_UINTSI },
4380   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4381     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4382     ~RS6000_BTI_INTSI },
4383   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4384     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4385   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4386     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4387   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4388     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4389     ~RS6000_BTI_unsigned_V8HI },
4390   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4391     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4392     ~RS6000_BTI_UINTHI },
4393   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4394     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4395     ~RS6000_BTI_bool_V8HI },
4396   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4397     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4398     ~RS6000_BTI_UINTHI },
4399   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4400     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4401     ~RS6000_BTI_INTHI },
4402   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4403     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4404   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4405     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4406   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4407     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4408     ~RS6000_BTI_unsigned_V16QI },
4409   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4410     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4411     ~RS6000_BTI_UINTQI },
4412   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4413     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4414     ~RS6000_BTI_bool_V16QI },
4415   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4416     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4417     ~RS6000_BTI_UINTQI },
4418   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4419     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4420     ~RS6000_BTI_INTQI },
4421   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4422     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI,
4423     ~RS6000_BTI_pixel_V8HI },
4424
4425   /* Predicates.  */
4426   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4427     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4428   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4429     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4430   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4431     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4432   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4433     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4434   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4435     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4436   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4437     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4438   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4439     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4440   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4441     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4442   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4443     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4444   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4445     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4446   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4447     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4448   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4449     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4450   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4451     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4452   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4453     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4454   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4455     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4456   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4457     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4458   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4459     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4460   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4461     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4462   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4463     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4464   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4465     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4466   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4467     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4468   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4469     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4470   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4471     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4472   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4473     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4474   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P,
4475     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4476   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P,
4477     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4478
4479
4480   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4481     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4482   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4483     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4484   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4485     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4486   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4487     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4488   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4489     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4490   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4491     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4492   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4493     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
4494   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4495     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4496   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4497     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4498   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4499     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4500   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4501     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4502   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4503     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4504   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4505     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4506   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4507     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
4508   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4509     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI },
4510   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4511     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4512   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4513     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4514   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4515     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4516   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4517     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4518   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4519     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4520   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4521     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4522   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4523     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
4524   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4525     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4526   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4527     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4528   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4529     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4530   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4531     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4532   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4533     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4534   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4535     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4536   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4537     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI },
4538   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P,
4539     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4540   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P,
4541     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4542
4543
4544   /* cmpge is the same as cmpgt for all cases except floating point.
4545      There is further code to deal with this special case in
4546      altivec_build_resolved_builtin.  */
4547   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4548     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4549   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4550     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4551   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4552     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4553   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4554     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4555   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4556     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4557   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4558     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4559   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4560     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4561   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4562     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4563   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4564     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4565   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4566     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4567   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4568     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4569   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4570     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4571   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4572     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4573   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4574     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4575   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4576     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4577   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4578     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4579   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4580     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4581   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4582     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4583   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4584     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4585   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4586     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4587   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4588     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4589   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4590     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4591   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4592     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4593   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4594     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4595   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P,
4596     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4597   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P,
4598     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4599
4600   /* Power8 vector overloaded functions.  */
4601   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4602     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4603   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4604     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4605   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4606     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4607   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4608     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4609   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4610     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4611     RS6000_BTI_unsigned_V16QI, 0 },
4612   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4613     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4614     RS6000_BTI_bool_V16QI, 0 },
4615   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4616     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4617     RS6000_BTI_unsigned_V16QI, 0 },
4618   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4619     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4620   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4621     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4622   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4623     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4624   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4625     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4626   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4627     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4628     RS6000_BTI_unsigned_V8HI, 0 },
4629   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4630     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4631     RS6000_BTI_bool_V8HI, 0 },
4632   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4633     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4634     RS6000_BTI_unsigned_V8HI, 0 },
4635   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4636     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4637   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4638     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4639   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4640     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4641   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4642     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4643   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4644     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4645     RS6000_BTI_unsigned_V4SI, 0 },
4646   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4647     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4648     RS6000_BTI_bool_V4SI, 0 },
4649   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4650     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4651     RS6000_BTI_unsigned_V4SI, 0 },
4652   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4653     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4654   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4655     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4656   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4657     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4658   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4659     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4660   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4661     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4662     RS6000_BTI_unsigned_V2DI, 0 },
4663   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4664     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4665     RS6000_BTI_bool_V2DI, 0 },
4666   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4667     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4668     RS6000_BTI_unsigned_V2DI, 0 },
4669   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF,
4670     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4671   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF,
4672     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4673
4674   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4675     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4676   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4677     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4678   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4679     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4680   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4681     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4682     RS6000_BTI_unsigned_V16QI, 0 },
4683   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4684     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4685     RS6000_BTI_bool_V16QI, 0 },
4686   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4687     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4688     RS6000_BTI_unsigned_V16QI, 0 },
4689   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4690     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4691   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4692     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4693   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4694     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4695   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4696     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4697   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4698     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4699     RS6000_BTI_unsigned_V8HI, 0 },
4700   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4701     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4702     RS6000_BTI_bool_V8HI, 0 },
4703   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4704     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4705     RS6000_BTI_unsigned_V8HI, 0 },
4706   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4707     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4708   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4709     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4710   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4711     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4712   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4713     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4714   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4715     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4716     RS6000_BTI_unsigned_V4SI, 0 },
4717   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4718     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4719     RS6000_BTI_bool_V4SI, 0 },
4720   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4721     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4722     RS6000_BTI_unsigned_V4SI, 0 },
4723   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4724     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4725   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4726     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4727   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4728     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4729   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4730     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4731   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4732     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4733     RS6000_BTI_unsigned_V2DI, 0 },
4734   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4735     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4736     RS6000_BTI_bool_V2DI, 0 },
4737   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4738     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4739     RS6000_BTI_unsigned_V2DI, 0 },
4740   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4741     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4742   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF,
4743     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4744   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF,
4745     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4746
4747   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4748     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4749   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4750     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4751   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4752     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4753   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4754     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4755     RS6000_BTI_unsigned_V16QI, 0 },
4756   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4757     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4758     RS6000_BTI_bool_V16QI, 0 },
4759   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4760     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4761     RS6000_BTI_unsigned_V16QI, 0 },
4762   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4763     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4764   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4765     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4766   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4767     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4768   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4769     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4770   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4771     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4772     RS6000_BTI_unsigned_V8HI, 0 },
4773   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4774     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4775     RS6000_BTI_bool_V8HI, 0 },
4776   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4777     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4778     RS6000_BTI_unsigned_V8HI, 0 },
4779   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4780     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4781   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4782     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4783   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4784     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4785   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4786     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4787   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4788     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4789     RS6000_BTI_unsigned_V4SI, 0 },
4790   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4791     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4792     RS6000_BTI_bool_V4SI, 0 },
4793   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4794     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4795     RS6000_BTI_unsigned_V4SI, 0 },
4796   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4797     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4798   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4799     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4800   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4801     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4802   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4803     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4804   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4805     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4806     RS6000_BTI_unsigned_V2DI, 0 },
4807   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4808     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4809     RS6000_BTI_bool_V2DI, 0 },
4810   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4811     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4812     RS6000_BTI_unsigned_V2DI, 0 },
4813   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4814     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4815   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF,
4816     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4817   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF,
4818     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4819
4820   { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4821     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4822   { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4823     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4824     RS6000_BTI_unsigned_V1TI, 0 },
4825
4826   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4827     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4828   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4829     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4830   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4831     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4832   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4833     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4834   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4835     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4836   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4837     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4838
4839   { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4840     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4841   { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4842     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4843     RS6000_BTI_unsigned_V1TI, 0 },
4844
4845   { P9V_BUILTIN_VEC_VBPERM, P9V_BUILTIN_VBPERMD,
4846     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4847     RS6000_BTI_unsigned_V16QI, 0 },
4848   { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ,
4849     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4850     RS6000_BTI_unsigned_V16QI, 0 },
4851   { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ2,
4852     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4853     RS6000_BTI_unsigned_V16QI, 0 },
4854
4855   { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4856     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4857     RS6000_BTI_unsigned_V16QI, 0 },
4858   { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4859     RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4860   { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4861     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
4862     RS6000_BTI_unsigned_V16QI, 0 },
4863   { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4864     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4865     RS6000_BTI_unsigned_V16QI, 0 },
4866
4867   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4868     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4869   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4870     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4871   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4872     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4873   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4874     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4875   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4876     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4877   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4878     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4879   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4880     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4881   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4882     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4883
4884   { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4885     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4886   { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4887     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4888
4889   { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4890     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4891   { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4892     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4893
4894   { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4895     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4896   { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4897     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4898
4899   { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4900     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4901   { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4902     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4903
4904   { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_TD,
4905     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4906   { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_DD,
4907     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4908
4909   { P9_BUILTIN_DFP_TSTSFI_LT_TD, MISC_BUILTIN_TSTSFI_LT_TD,
4910     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4911   { P9_BUILTIN_DFP_TSTSFI_LT_DD, MISC_BUILTIN_TSTSFI_LT_DD,
4912     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4913
4914   { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_TD,
4915     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4916   { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_DD,
4917     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4918
4919   { P9_BUILTIN_DFP_TSTSFI_EQ_TD, MISC_BUILTIN_TSTSFI_EQ_TD,
4920     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4921   { P9_BUILTIN_DFP_TSTSFI_EQ_DD, MISC_BUILTIN_TSTSFI_EQ_DD,
4922     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4923
4924   { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_TD,
4925     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4926   { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_DD,
4927     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4928
4929   { P9_BUILTIN_DFP_TSTSFI_GT_TD, MISC_BUILTIN_TSTSFI_GT_TD,
4930     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4931   { P9_BUILTIN_DFP_TSTSFI_GT_DD, MISC_BUILTIN_TSTSFI_GT_DD,
4932     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4933
4934   { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_TD,
4935     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4936   { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_DD,
4937     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4938
4939   { P9_BUILTIN_DFP_TSTSFI_OV_TD, MISC_BUILTIN_TSTSFI_OV_TD,
4940     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4941   { P9_BUILTIN_DFP_TSTSFI_OV_DD, MISC_BUILTIN_TSTSFI_OV_DD,
4942     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4943
4944   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4945     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4946   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4947     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4948   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4949     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4950   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4951     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4952   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4953     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4954   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4955     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4956   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4957     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4958   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4959     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4960
4961   { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4962     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4963   { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4964     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4965
4966   { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4967     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4968   { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4969     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4970
4971   { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4972     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4973   { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4974     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4975
4976   { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4977     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4978   { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4979     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4980
4981   { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUB,
4982     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4983     RS6000_BTI_unsigned_V16QI, 0 },
4984   { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUH,
4985     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4986     RS6000_BTI_unsigned_V8HI, 0 },
4987   { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUW,
4988     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4989     RS6000_BTI_unsigned_V4SI, 0 },
4990
4991   { P9V_BUILTIN_VEC_VADUB, P9V_BUILTIN_VADUB,
4992     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4993     RS6000_BTI_unsigned_V16QI, 0 },
4994
4995   { P9V_BUILTIN_VEC_VADUH, P9V_BUILTIN_VADUH,
4996     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4997     RS6000_BTI_unsigned_V8HI, 0 },
4998
4999   { P9V_BUILTIN_VEC_VADUW, P9V_BUILTIN_VADUW,
5000     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5001     RS6000_BTI_unsigned_V4SI, 0 },
5002
5003   { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESSP,
5004     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
5005   { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESDP,
5006     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
5007
5008   { P9V_BUILTIN_VEC_VESSP, P9V_BUILTIN_VESSP,
5009     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
5010   { P9V_BUILTIN_VEC_VESDP, P9V_BUILTIN_VESDP,
5011     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
5012
5013   { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEESP,
5014     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
5015   { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEEDP,
5016     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
5017
5018   { P9V_BUILTIN_VEC_VEESP, P9V_BUILTIN_VEESP,
5019     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
5020   { P9V_BUILTIN_VEC_VEEDP, P9V_BUILTIN_VEEDP,
5021     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
5022
5023   { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCSP,
5024     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
5025   { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCDP,
5026     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
5027
5028   { P9V_BUILTIN_VEC_VTDCSP, P9V_BUILTIN_VTDCSP,
5029     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
5030   { P9V_BUILTIN_VEC_VTDCDP, P9V_BUILTIN_VTDCDP,
5031     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
5032
5033   { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
5034     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
5035   { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
5036     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
5037
5038   { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
5039     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5040   { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
5041     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
5042
5043   { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
5044     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
5045   { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
5046     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
5047
5048   { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
5049     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5050   { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
5051     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
5052
5053   { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCSP,
5054     RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
5055   { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCDP,
5056     RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
5057   { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCQP,
5058     RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 },
5059
5060   { P9V_BUILTIN_VEC_VSTDCSP, P9V_BUILTIN_VSTDCSP,
5061     RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
5062   { P9V_BUILTIN_VEC_VSTDCDP, P9V_BUILTIN_VSTDCDP,
5063     RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
5064   { P9V_BUILTIN_VEC_VSTDCQP, P9V_BUILTIN_VSTDCQP,
5065     RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 },
5066
5067   { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNSP,
5068     RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
5069   { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNDP,
5070     RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
5071   { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNQP,
5072     RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 },
5073
5074   { P9V_BUILTIN_VEC_VSTDCNSP, P9V_BUILTIN_VSTDCNSP,
5075     RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
5076   { P9V_BUILTIN_VEC_VSTDCNDP, P9V_BUILTIN_VSTDCNDP,
5077     RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
5078   { P9V_BUILTIN_VEC_VSTDCNQP, P9V_BUILTIN_VSTDCNQP,
5079     RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 },
5080
5081   { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEDP,
5082     RS6000_BTI_UINTSI, RS6000_BTI_double, 0, 0 },
5083   { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEQP,
5084     RS6000_BTI_UINTDI, RS6000_BTI_ieee128_float, 0, 0 },
5085
5086   { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESDP,
5087     RS6000_BTI_UINTDI, RS6000_BTI_double, 0, 0 },
5088   { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESQP,
5089     RS6000_BTI_UINTTI, RS6000_BTI_ieee128_float, 0, 0 },
5090
5091   { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDP,
5092     RS6000_BTI_double, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
5093   { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDPF,
5094     RS6000_BTI_double, RS6000_BTI_double, RS6000_BTI_UINTDI, 0 },
5095
5096   { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQP,
5097     RS6000_BTI_ieee128_float, RS6000_BTI_UINTTI, RS6000_BTI_UINTDI, 0 },
5098   { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQPF,
5099     RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, RS6000_BTI_UINTDI, 0 },
5100
5101   { P9V_BUILTIN_VEC_VSCEDPGT, P9V_BUILTIN_VSCEDPGT,
5102     RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
5103   { P9V_BUILTIN_VEC_VSCEDPLT, P9V_BUILTIN_VSCEDPLT,
5104     RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
5105   { P9V_BUILTIN_VEC_VSCEDPEQ, P9V_BUILTIN_VSCEDPEQ,
5106     RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
5107   { P9V_BUILTIN_VEC_VSCEDPUO, P9V_BUILTIN_VSCEDPUO,
5108     RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
5109
5110   { P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_XL_LEN_R,
5111     RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
5112     RS6000_BTI_unsigned_long_long, 0 },
5113
5114   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5115     RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
5116     RS6000_BTI_unsigned_long_long, 0 },
5117   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5118     RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
5119     RS6000_BTI_unsigned_long_long, 0 },
5120
5121   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5122     RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
5123     RS6000_BTI_unsigned_long_long, 0 },
5124   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5125     RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
5126     RS6000_BTI_unsigned_long_long, 0 },
5127
5128   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5129     RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
5130     RS6000_BTI_unsigned_long_long, 0 },
5131   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5132     RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
5133     RS6000_BTI_unsigned_long_long, 0 },
5134
5135   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5136     RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
5137     RS6000_BTI_unsigned_long_long, 0 },
5138   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5139     RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
5140     RS6000_BTI_unsigned_long_long, 0 },
5141
5142   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5143     RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
5144     RS6000_BTI_unsigned_long_long, 0 },
5145   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5146     RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
5147     RS6000_BTI_unsigned_long_long, 0 },
5148
5149   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5150     RS6000_BTI_V2DF, ~RS6000_BTI_double,
5151     RS6000_BTI_unsigned_long_long, 0 },
5152   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5153     RS6000_BTI_V4SF, ~RS6000_BTI_float,
5154     RS6000_BTI_unsigned_long_long, 0 },
5155   /* At an appropriate future time, add support for the
5156      RS6000_BTI_Float16 (exact name to be determined) type here.  */
5157
5158   { P9V_BUILTIN_VEC_XST_LEN_R, P9V_BUILTIN_XST_LEN_R,
5159     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI,
5160     ~RS6000_BTI_UINTQI, RS6000_BTI_unsigned_long_long},
5161
5162   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5163     RS6000_BTI_void, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
5164     RS6000_BTI_unsigned_long_long },
5165   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5166     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
5167     RS6000_BTI_unsigned_long_long },
5168
5169   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5170     RS6000_BTI_void, RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
5171     RS6000_BTI_unsigned_long_long },
5172   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5173     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
5174     RS6000_BTI_unsigned_long_long },
5175
5176   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5177     RS6000_BTI_void, RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
5178     RS6000_BTI_unsigned_long_long },
5179   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5180     RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
5181     RS6000_BTI_unsigned_long_long },
5182
5183   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5184     RS6000_BTI_void, RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
5185     RS6000_BTI_unsigned_long_long },
5186   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5187     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
5188     RS6000_BTI_unsigned_long_long },
5189
5190   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5191     RS6000_BTI_void, RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
5192     RS6000_BTI_unsigned_long_long },
5193   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5194     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
5195     RS6000_BTI_unsigned_long_long },
5196
5197   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5198     RS6000_BTI_void, RS6000_BTI_V2DF, ~RS6000_BTI_double,
5199     RS6000_BTI_unsigned_long_long },
5200   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5201     RS6000_BTI_void, RS6000_BTI_V4SF, ~RS6000_BTI_float,
5202     RS6000_BTI_unsigned_long_long },
5203   /* At an appropriate future time, add support for the
5204      RS6000_BTI_Float16 (exact name to be determined) type here.  */
5205
5206   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
5207     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
5208     RS6000_BTI_bool_V16QI, 0 },
5209   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
5210     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
5211     RS6000_BTI_V16QI, 0 },
5212   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
5213     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
5214     RS6000_BTI_unsigned_V16QI, 0 },
5215
5216   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
5217     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI,
5218     RS6000_BTI_bool_V8HI, 0 },
5219   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
5220     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
5221     RS6000_BTI_V8HI, 0 },
5222   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
5223     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
5224     RS6000_BTI_unsigned_V8HI, 0 },
5225
5226   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
5227     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI,
5228     RS6000_BTI_bool_V4SI, 0 },
5229   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
5230     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
5231     RS6000_BTI_V4SI, 0 },
5232   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
5233     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
5234     RS6000_BTI_unsigned_V4SI, 0 },
5235
5236   /* The following 2 entries have been deprecated.  */
5237   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5238     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5239     RS6000_BTI_unsigned_V16QI, 0 },
5240   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5241     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5242     RS6000_BTI_bool_V16QI, 0 },
5243   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5244     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5245     RS6000_BTI_unsigned_V16QI, 0 },
5246
5247   /* The following 2 entries have been deprecated.  */
5248   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5249     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5250     RS6000_BTI_V16QI, 0 },
5251   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5252     RS6000_BTI_INTSI, RS6000_BTI_V16QI,
5253     RS6000_BTI_bool_V16QI, 0 },
5254   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5255     RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
5256   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5257     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5258     RS6000_BTI_bool_V16QI, 0 },
5259
5260   /* The following 2 entries have been deprecated.  */
5261   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5262     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5263     RS6000_BTI_unsigned_V8HI, 0 },
5264   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5265     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5266     RS6000_BTI_bool_V8HI, 0 },
5267   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5268     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5269     RS6000_BTI_unsigned_V8HI, 0 },
5270   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5271     RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
5272
5273   /* The following 2 entries have been deprecated.  */
5274   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5275     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5276     RS6000_BTI_V8HI, 0 },
5277   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5278     RS6000_BTI_INTSI, RS6000_BTI_V8HI,
5279     RS6000_BTI_bool_V8HI, 0 },
5280   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5281     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5282     RS6000_BTI_bool_V8HI, 0 },
5283   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5284     RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
5285     RS6000_BTI_pixel_V8HI, 0 },
5286
5287   /* The following 2 entries have been deprecated.  */
5288   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5289     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5290     RS6000_BTI_unsigned_V4SI, 0 },
5291   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5292     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5293     RS6000_BTI_bool_V4SI, 0 },
5294   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5295     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5296     RS6000_BTI_unsigned_V4SI, 0 },
5297
5298   /* The following 2 entries have been deprecated.  */
5299   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5300     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5301     RS6000_BTI_V4SI, 0 },
5302   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5303     RS6000_BTI_INTSI, RS6000_BTI_V4SI,
5304     RS6000_BTI_bool_V4SI, 0 },
5305   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5306     RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5307   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5308     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5309     RS6000_BTI_bool_V4SI, 0 },
5310
5311   /* The following 2 entries have been deprecated.  */
5312   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5313     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5314     RS6000_BTI_unsigned_V2DI, 0 },
5315   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5316     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5317     RS6000_BTI_bool_V2DI, 0 },
5318   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5319     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5320     RS6000_BTI_unsigned_V2DI, 0
5321   },
5322
5323   /* The following 2 entries have been deprecated.  */
5324   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5325     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5326     RS6000_BTI_V2DI, 0 },
5327   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5328     RS6000_BTI_INTSI, RS6000_BTI_V2DI,
5329     RS6000_BTI_bool_V2DI, 0 },
5330   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5331     RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5332   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5333     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5334     RS6000_BTI_bool_V2DI, 0 },
5335
5336   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEFP_P,
5337     RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5338   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEDP_P,
5339     RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5340
5341   /* The following 2 entries have been deprecated.  */
5342   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5343     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5344     RS6000_BTI_unsigned_V16QI, 0 },
5345   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5346     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5347     RS6000_BTI_bool_V16QI, 0 },
5348   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5349     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5350     RS6000_BTI_unsigned_V16QI, 0 },
5351
5352   /* The following 2 entries have been deprecated.  */
5353   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5354     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5355     RS6000_BTI_V16QI, 0 },
5356   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5357     RS6000_BTI_INTSI, RS6000_BTI_V16QI,
5358     RS6000_BTI_bool_V16QI, 0 },
5359   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5360     RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
5361   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5362     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5363     RS6000_BTI_bool_V16QI, 0 },
5364
5365   /* The following 2 entries have been deprecated.  */
5366   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5367     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5368     RS6000_BTI_unsigned_V8HI, 0 },
5369   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5370     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5371     RS6000_BTI_bool_V8HI, 0 },
5372   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5373     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5374     RS6000_BTI_unsigned_V8HI, 0 },
5375   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5376     RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
5377
5378   /* The following 2 entries have been deprecated.  */
5379   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5380     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5381     RS6000_BTI_V8HI, 0 },
5382   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5383     RS6000_BTI_INTSI, RS6000_BTI_V8HI,
5384     RS6000_BTI_bool_V8HI, 0 },
5385   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5386     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5387     RS6000_BTI_bool_V8HI, 0 },
5388   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5389     RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
5390     RS6000_BTI_pixel_V8HI, 0 },
5391
5392   /* The following 2 entries have been deprecated.  */
5393   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5394     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5395     RS6000_BTI_unsigned_V4SI, 0 },
5396   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5397     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5398     RS6000_BTI_bool_V4SI, 0 },
5399   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5400     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5401     RS6000_BTI_unsigned_V4SI, 0 },
5402
5403   /* The following 2 entries have been deprecated.  */
5404   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5405     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5406     RS6000_BTI_V4SI, 0 },
5407   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5408     RS6000_BTI_INTSI, RS6000_BTI_V4SI,
5409     RS6000_BTI_bool_V4SI, 0 },
5410   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5411     RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5412   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5413     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5414     RS6000_BTI_bool_V4SI, 0 },
5415
5416   /* The following 2 entries have been deprecated.  */
5417   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5418     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5419     RS6000_BTI_unsigned_V2DI, 0 },
5420   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5421     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5422     RS6000_BTI_bool_V2DI, 0 },
5423   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5424     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5425     RS6000_BTI_unsigned_V2DI, 0
5426   },
5427
5428   /* The following 2 entries have been deprecated.  */
5429   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5430     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5431     RS6000_BTI_V2DI, 0 },
5432   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5433     RS6000_BTI_INTSI, RS6000_BTI_V2DI,
5434     RS6000_BTI_bool_V2DI, 0 },
5435   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5436     RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5437   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5438     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5439     RS6000_BTI_bool_V2DI, 0 },
5440
5441   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEFP_P,
5442     RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5443   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEDP_P,
5444     RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5445
5446   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
5447     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5448     RS6000_BTI_unsigned_V16QI },
5449   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
5450     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
5451
5452   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
5453     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5454     RS6000_BTI_unsigned_V8HI },
5455   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
5456     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
5457
5458   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
5459     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5460     RS6000_BTI_unsigned_V4SI },
5461   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
5462     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
5463
5464   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
5465     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
5466     RS6000_BTI_V16QI, 0 },
5467   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
5468     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
5469     RS6000_BTI_unsigned_V16QI, 0 },
5470
5471   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
5472     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
5473     RS6000_BTI_V8HI, 0 },
5474   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
5475     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
5476     RS6000_BTI_unsigned_V8HI, 0 },
5477
5478   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5479     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
5480     RS6000_BTI_V4SI, 0 },
5481   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5482     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
5483     RS6000_BTI_unsigned_V4SI, 0 },
5484
5485   { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB,
5486     RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5487   { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB,
5488     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5489
5490   { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI,
5491     RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5492   { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI,
5493     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5494   { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V8HI,
5495     RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
5496   { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V4SI,
5497     RS6000_BTI_INTSI, RS6000_BTI_V4SI, 0, 0 },
5498
5499   { P9V_BUILTIN_VEC_EXTRACT4B, P9V_BUILTIN_EXTRACT4B,
5500     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
5501
5502   { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTH, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTH,
5503     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
5504   { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTL, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTL,
5505     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
5506
5507   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5508     RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5509     RS6000_BTI_V16QI, 0 },
5510   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5511     RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5512     RS6000_BTI_unsigned_V16QI, 0 },
5513
5514   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5515     RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5516     RS6000_BTI_V8HI, 0 },
5517   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5518     RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5519     RS6000_BTI_unsigned_V8HI, 0 },
5520
5521   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5522     RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5523     RS6000_BTI_V4SI, 0 },
5524   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5525     RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5526     RS6000_BTI_unsigned_V4SI, 0 },
5527   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5528     RS6000_BTI_float, RS6000_BTI_UINTSI,
5529     RS6000_BTI_V4SF, 0 },
5530
5531   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5532     RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5533     RS6000_BTI_V16QI, 0 },
5534   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5535     RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5536     RS6000_BTI_unsigned_V16QI, 0 },
5537
5538   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5539     RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5540     RS6000_BTI_V8HI, 0 },
5541   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5542     RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5543     RS6000_BTI_unsigned_V8HI, 0 },
5544
5545   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5546     RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5547     RS6000_BTI_V4SI, 0 },
5548   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5549     RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5550     RS6000_BTI_unsigned_V4SI, 0 },
5551   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5552     RS6000_BTI_float, RS6000_BTI_UINTSI,
5553     RS6000_BTI_V4SF, 0 },
5554
5555   { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5556     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5557   { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5558     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5559
5560   { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B,
5561     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI,
5562     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
5563   { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B,
5564     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI,
5565     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
5566
5567   { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5568     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5569   { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5570     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5571     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5572
5573   { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5574     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5575   { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5576     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5577     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5578
5579   { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5580     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5581   { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5582     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5583     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5584
5585   { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5586     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5587   { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5588     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5589     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5590
5591   { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5592     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5593   { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5594     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5595   { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5596     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5597
5598   { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5599     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5600   { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5601     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5602   { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5603     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5604
5605   { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5606     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5607     RS6000_BTI_unsigned_V2DI, 0 },
5608   { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5609     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5610     RS6000_BTI_bool_V2DI, 0 },
5611   { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5612     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5613     RS6000_BTI_unsigned_V2DI, 0 },
5614
5615   { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5616     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5617     RS6000_BTI_unsigned_V2DI, 0 },
5618   { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5619     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5620     RS6000_BTI_bool_V2DI, 0 },
5621   { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5622     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5623     RS6000_BTI_unsigned_V2DI, 0 },
5624
5625   { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5626     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5627   { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5628     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5629     RS6000_BTI_unsigned_V2DI, 0 },
5630   { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5631     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5632   { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SF,
5633     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5634   { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DF,
5635     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5636   { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5637     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5638   { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5639     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5640     RS6000_BTI_unsigned_V4SI, 0 },
5641   { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5642     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5643
5644   { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5645     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5646   { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5647     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5648     RS6000_BTI_unsigned_V4SI, 0 },
5649   { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5650     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5651   { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5652     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5653   { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5654     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5655   { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5656     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5657     RS6000_BTI_unsigned_V2DI, 0 },
5658   { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5659     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5660   { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DF,
5661     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5662   { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SF,
5663     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5664
5665   { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMB,
5666     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI,
5667     RS6000_BTI_unsigned_V16QI, 0 },
5668   { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMH,
5669     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI,
5670     RS6000_BTI_unsigned_V8HI, 0 },
5671   { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMW,
5672     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
5673     RS6000_BTI_unsigned_V4SI, 0 },
5674   { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMD,
5675     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI,
5676     RS6000_BTI_unsigned_V2DI, 0 },
5677
5678   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5679     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5680   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5681     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5682   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5683     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5684   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5685     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5686   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5687     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5688   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5689     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5690   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5691     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5692   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5693     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5694
5695   { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5696     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5697   { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5698     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5699
5700   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB,
5701     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0, 0 },
5702   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB,
5703     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5704
5705   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH,
5706     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0, 0 },
5707   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH,
5708     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5709
5710   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW,
5711     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 },
5712   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW,
5713     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5714
5715   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD,
5716     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 },
5717   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD,
5718     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5719
5720   { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5721     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5722   { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5723     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5724
5725   { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5726     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5727   { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5728     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5729
5730   { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5731     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5732   { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5733     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5734
5735   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5736     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5737   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5738     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5739   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5740     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5741   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5742     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5743   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5744     RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5745   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5746     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5747   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5748     RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5749   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5750     RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5751
5752   { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5753     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5754   { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5755     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5756
5757   { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5758     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5759   { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5760     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5761
5762   { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5763     RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5764   { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5765     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5766   { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5767     RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5768   { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5769     RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5770
5771   { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW,
5772     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 },
5773   { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW,
5774     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5775   { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD,
5776     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 },
5777   { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD,
5778     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5779   { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ,
5780     RS6000_BTI_unsigned_V1TI, RS6000_BTI_V1TI, 0, 0 },
5781   { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ,
5782     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5783
5784   { P9_BUILTIN_CMPRB, P9_BUILTIN_SCALAR_CMPRB,
5785     RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5786   { P9_BUILTIN_CMPRB2, P9_BUILTIN_SCALAR_CMPRB2,
5787     RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5788   { P9_BUILTIN_CMPEQB, P9_BUILTIN_SCALAR_CMPEQB,
5789     RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTDI, 0 },
5790
5791   { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5792     RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5793   { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5794     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5795   { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5796     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5797
5798   { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS,
5799     RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5800
5801   { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS,
5802     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5803
5804   { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS,
5805     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5806
5807   { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5808     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5809   { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5810     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5811
5812   { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5813     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5814   { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5815     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5816
5817   { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5818     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5819   { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5820     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5821
5822   { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5823     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5824   { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5825     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5826
5827   { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5828     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5829   { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5830     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5831     RS6000_BTI_unsigned_V1TI, 0 },
5832
5833   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5834     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5835   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5836     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5837   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5838     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5839   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5840     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5841   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5842     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
5843   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5844     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5845
5846   { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5847     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5848   { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5849     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5850     RS6000_BTI_unsigned_V1TI, 0 },
5851
5852   { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB_32,
5853     RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, 0 },
5854   { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB,
5855     RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
5856
5857   { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5858     RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5859   { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5860     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5861
5862   { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5863     RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5864   { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5865     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5866
5867   { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV,
5868     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5869     RS6000_BTI_unsigned_V16QI, 0 },
5870   { P9V_BUILTIN_VEC_VSRV, P9V_BUILTIN_VSRV,
5871     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5872     RS6000_BTI_unsigned_V16QI, 0 },
5873
5874   { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI,
5875     RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5876   { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI,
5877     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5878   { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5879     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 },
5880   { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5881     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5882   { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5883     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5884   { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5885     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
5886   { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5887     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5888   { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5889     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5890   { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5891     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
5892   { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5893     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5894   { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5895     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5896   { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5897     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
5898   { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5899     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5900   { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5901     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5902   { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DF,
5903     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5904   { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SF,
5905     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
5906
5907   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5908     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5909   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5910     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5911   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5912     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5913   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5914     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5915   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5916     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 },
5917   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5918     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
5919   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5920     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
5921   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5922     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
5923   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DF,
5924     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5925   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SF,
5926     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
5927   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5928     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5929   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5930     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5931   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5932     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5933   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5934     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5935
5936   { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V4SF,
5937     RS6000_BTI_V4SI, RS6000_BTI_V4SF, 0, 0 },
5938   { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V2DF,
5939     RS6000_BTI_V2DI, RS6000_BTI_V2DF, 0, 0 },
5940   { VSX_BUILTIN_VEC_VSIGNEDE, VSX_BUILTIN_VEC_VSIGNEDE_V2DF,
5941     RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
5942   { VSX_BUILTIN_VEC_VSIGNEDO, VSX_BUILTIN_VEC_VSIGNEDO_V2DF,
5943     RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
5944   { P8V_BUILTIN_VEC_VSIGNED2, P8V_BUILTIN_VEC_VSIGNED2_V2DF,
5945     RS6000_BTI_V4SI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5946
5947   { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V4SF,
5948     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
5949   { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V2DF,
5950     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
5951   { VSX_BUILTIN_VEC_VUNSIGNEDE, VSX_BUILTIN_VEC_VUNSIGNEDE_V2DF,
5952     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
5953   { VSX_BUILTIN_VEC_VUNSIGNEDO, VSX_BUILTIN_VEC_VUNSIGNEDO_V2DF,
5954     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
5955   { P8V_BUILTIN_VEC_VUNSIGNED2, P8V_BUILTIN_VEC_VUNSIGNED2_V2DF,
5956     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF,
5957     RS6000_BTI_V2DF, 0 },
5958
5959   /* Crypto builtins.  */
5960   { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,
5961     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5962     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
5963   { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI,
5964     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5965     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
5966   { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI,
5967     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5968     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
5969   { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI,
5970     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5971     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
5972
5973   { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB,
5974     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5975     RS6000_BTI_unsigned_V16QI, 0 },
5976   { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH,
5977     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5978     RS6000_BTI_unsigned_V8HI, 0 },
5979   { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW,
5980     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5981     RS6000_BTI_unsigned_V4SI, 0 },
5982   { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD,
5983     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5984     RS6000_BTI_unsigned_V2DI, 0 },
5985
5986   { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW,
5987     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5988     RS6000_BTI_INTSI, RS6000_BTI_INTSI },
5989   { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD,
5990     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5991     RS6000_BTI_INTSI, RS6000_BTI_INTSI },
5992
5993   { (enum rs6000_builtins) 0, (enum rs6000_builtins) 0, 0, 0, 0, 0 }
5994 };
5995 \f
5996
5997 /* Convert a type stored into a struct altivec_builtin_types as ID,
5998    into a tree.  The types are in rs6000_builtin_types: negative values
5999    create a pointer type for the type associated to ~ID.  Note it is
6000    a logical NOT, rather than a negation, otherwise you cannot represent
6001    a pointer type for ID 0.  */
6002
6003 static inline tree
6004 rs6000_builtin_type (int id)
6005 {
6006   tree t;
6007   t = rs6000_builtin_types[id < 0 ? ~id : id];
6008   return id < 0 ? build_pointer_type (t) : t;
6009 }
6010
6011 /* Check whether the type of an argument, T, is compatible with a type ID
6012    stored into a struct altivec_builtin_types.  Integer types are considered
6013    compatible; otherwise, the language hook lang_hooks.types_compatible_p makes
6014    the decision.  Also allow long double and _Float128 to be compatible if
6015    -mabi=ieeelongdouble.  */
6016
6017 static inline bool
6018 is_float128_p (tree t)
6019 {
6020   return (t == float128_type_node
6021           || (TARGET_IEEEQUAD
6022               && TARGET_LONG_DOUBLE_128
6023               && t == long_double_type_node));
6024 }
6025
6026 static inline bool
6027 rs6000_builtin_type_compatible (tree t, int id)
6028 {
6029   tree builtin_type;
6030   builtin_type = rs6000_builtin_type (id);
6031   if (t == error_mark_node)
6032     return false;
6033   if (INTEGRAL_TYPE_P (t) && INTEGRAL_TYPE_P (builtin_type))
6034     return true;
6035   else if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
6036            && is_float128_p (t) && is_float128_p (builtin_type))
6037     return true;
6038   else
6039     return lang_hooks.types_compatible_p (t, builtin_type);
6040 }
6041
6042
6043 /* In addition to calling fold_convert for EXPR of type TYPE, also
6044    call c_fully_fold to remove any C_MAYBE_CONST_EXPRs that could be
6045    hiding there (PR47197).  */
6046
6047 static tree
6048 fully_fold_convert (tree type, tree expr)
6049 {
6050   tree result = fold_convert (type, expr);
6051   bool maybe_const = true;
6052
6053   if (!c_dialect_cxx ())
6054     result = c_fully_fold (result, false, &maybe_const);
6055
6056   return result;
6057 }
6058
6059 /* Build a tree for a function call to an Altivec non-overloaded builtin.
6060    The overloaded builtin that matched the types and args is described
6061    by DESC.  The N arguments are given in ARGS, respectively.
6062
6063    Actually the only thing it does is calling fold_convert on ARGS, with
6064    a small exception for vec_{all,any}_{ge,le} predicates. */
6065
6066 static tree
6067 altivec_build_resolved_builtin (tree *args, int n,
6068                                 const struct altivec_builtin_types *desc)
6069 {
6070   tree impl_fndecl = rs6000_builtin_decls[desc->overloaded_code];
6071   tree ret_type = rs6000_builtin_type (desc->ret_type);
6072   tree argtypes = TYPE_ARG_TYPES (TREE_TYPE (impl_fndecl));
6073   tree arg_type[3];
6074   tree call;
6075
6076   int i;
6077   for (i = 0; i < n; i++)
6078     arg_type[i] = TREE_VALUE (argtypes), argtypes = TREE_CHAIN (argtypes);
6079
6080   /* The AltiVec overloading implementation is overall gross, but this
6081      is particularly disgusting.  The vec_{all,any}_{ge,le} builtins
6082      are completely different for floating-point vs. integer vector
6083      types, because the former has vcmpgefp, but the latter should use
6084      vcmpgtXX.
6085
6086      In practice, the second and third arguments are swapped, and the
6087      condition (LT vs. EQ, which is recognizable by bit 1 of the first
6088      argument) is reversed.  Patch the arguments here before building
6089      the resolved CALL_EXPR.  */
6090   if (desc->code == ALTIVEC_BUILTIN_VEC_VCMPGE_P
6091       && desc->overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P
6092       && desc->overloaded_code != VSX_BUILTIN_XVCMPGEDP_P)
6093     {
6094       tree t;
6095       t = args[2], args[2] = args[1], args[1] = t;
6096       t = arg_type[2], arg_type[2] = arg_type[1], arg_type[1] = t;
6097
6098       args[0] = fold_build2 (BIT_XOR_EXPR, TREE_TYPE (args[0]), args[0],
6099                              build_int_cst (NULL_TREE, 2));
6100     }
6101
6102   switch (n)
6103     {
6104     case 0:
6105       call = build_call_expr (impl_fndecl, 0);
6106       break;
6107     case 1:
6108       call = build_call_expr (impl_fndecl, 1,
6109                               fully_fold_convert (arg_type[0], args[0]));
6110       break;
6111     case 2:
6112       call = build_call_expr (impl_fndecl, 2,
6113                               fully_fold_convert (arg_type[0], args[0]),
6114                               fully_fold_convert (arg_type[1], args[1]));
6115       break;
6116     case 3:
6117       call = build_call_expr (impl_fndecl, 3,
6118                               fully_fold_convert (arg_type[0], args[0]),
6119                               fully_fold_convert (arg_type[1], args[1]),
6120                               fully_fold_convert (arg_type[2], args[2]));
6121       break;
6122     default:
6123       gcc_unreachable ();
6124     }
6125   return fold_convert (ret_type, call);
6126 }
6127
6128 /* Implementation of the resolve_overloaded_builtin target hook, to
6129    support Altivec's overloaded builtins.  */
6130
6131 tree
6132 altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
6133                                     void *passed_arglist)
6134 {
6135   vec<tree, va_gc> *arglist = static_cast<vec<tree, va_gc> *> (passed_arglist);
6136   unsigned int nargs = vec_safe_length (arglist);
6137   enum rs6000_builtins fcode
6138     = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
6139   tree fnargs = TYPE_ARG_TYPES (TREE_TYPE (fndecl));
6140   tree types[3], args[3];
6141   const struct altivec_builtin_types *desc;
6142   unsigned int n;
6143
6144   if (!rs6000_overloaded_builtin_p (fcode))
6145     return NULL_TREE;
6146
6147   if (TARGET_DEBUG_BUILTIN)
6148     fprintf (stderr, "altivec_resolve_overloaded_builtin, code = %4d, %s\n",
6149              (int)fcode, IDENTIFIER_POINTER (DECL_NAME (fndecl)));
6150
6151   /* vec_lvsl and vec_lvsr are deprecated for use with LE element order.  */
6152   if (fcode == ALTIVEC_BUILTIN_VEC_LVSL && !VECTOR_ELT_ORDER_BIG)
6153     warning (OPT_Wdeprecated,
6154              "vec_lvsl is deprecated for little endian; use "
6155              "assignment for unaligned loads and stores");
6156   else if (fcode == ALTIVEC_BUILTIN_VEC_LVSR && !VECTOR_ELT_ORDER_BIG)
6157     warning (OPT_Wdeprecated,
6158              "vec_lvsr is deprecated for little endian; use "
6159              "assignment for unaligned loads and stores");
6160
6161   if (fcode == ALTIVEC_BUILTIN_VEC_MUL)
6162     {
6163       /* vec_mul needs to be special cased because there are no instructions
6164          for it for the {un}signed char, {un}signed short, and {un}signed int
6165          types.  */
6166       if (nargs != 2)
6167         {
6168           error ("builtin %qs only accepts 2 arguments", "vec_mul");
6169           return error_mark_node;
6170         }
6171
6172       tree arg0 = (*arglist)[0];
6173       tree arg0_type = TREE_TYPE (arg0);
6174       tree arg1 = (*arglist)[1];
6175       tree arg1_type = TREE_TYPE (arg1);
6176
6177       /* Both arguments must be vectors and the types must be compatible.  */
6178       if (TREE_CODE (arg0_type) != VECTOR_TYPE)
6179         goto bad;
6180       if (!lang_hooks.types_compatible_p (arg0_type, arg1_type))
6181         goto bad;
6182
6183       switch (TYPE_MODE (TREE_TYPE (arg0_type)))
6184         {
6185           case E_QImode:
6186           case E_HImode:
6187           case E_SImode:
6188           case E_DImode:
6189           case E_TImode:
6190             {
6191               /* For scalar types just use a multiply expression.  */
6192               return fold_build2_loc (loc, MULT_EXPR, TREE_TYPE (arg0), arg0,
6193                                       fold_convert (TREE_TYPE (arg0), arg1));
6194             }
6195           case E_SFmode:
6196             {
6197               /* For floats use the xvmulsp instruction directly.  */
6198               tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULSP];
6199               return build_call_expr (call, 2, arg0, arg1);
6200             }
6201           case E_DFmode:
6202             {
6203               /* For doubles use the xvmuldp instruction directly.  */
6204               tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULDP];
6205               return build_call_expr (call, 2, arg0, arg1);
6206             }
6207           /* Other types are errors.  */
6208           default:
6209             goto bad;
6210         }
6211     }
6212
6213   if (fcode == ALTIVEC_BUILTIN_VEC_CMPNE)
6214     {
6215       /* vec_cmpne needs to be special cased because there are no instructions
6216          for it (prior to power 9).  */
6217       if (nargs != 2)
6218         {
6219           error ("builtin %qs only accepts 2 arguments", "vec_cmpne");
6220           return error_mark_node;
6221         }
6222
6223       tree arg0 = (*arglist)[0];
6224       tree arg0_type = TREE_TYPE (arg0);
6225       tree arg1 = (*arglist)[1];
6226       tree arg1_type = TREE_TYPE (arg1);
6227
6228       /* Both arguments must be vectors and the types must be compatible.  */
6229       if (TREE_CODE (arg0_type) != VECTOR_TYPE)
6230         goto bad;
6231       if (!lang_hooks.types_compatible_p (arg0_type, arg1_type))
6232         goto bad;
6233
6234       /* Power9 instructions provide the most efficient implementation of
6235          ALTIVEC_BUILTIN_VEC_CMPNE if the mode is not DImode or TImode
6236          or SFmode or DFmode.  */
6237       if (!TARGET_P9_VECTOR
6238           || (TYPE_MODE (TREE_TYPE (arg0_type)) == DImode)
6239           || (TYPE_MODE (TREE_TYPE (arg0_type)) == TImode)
6240           || (TYPE_MODE (TREE_TYPE (arg0_type)) == SFmode)
6241           || (TYPE_MODE (TREE_TYPE (arg0_type)) == DFmode))
6242         {
6243           switch (TYPE_MODE (TREE_TYPE (arg0_type)))
6244             {
6245               /* vec_cmpneq (va, vb) == vec_nor (vec_cmpeq (va, vb),
6246                  vec_cmpeq (va, vb)).  */
6247               /* Note:  vec_nand also works but opt changes vec_nand's
6248                  to vec_nor's anyway.  */
6249             case E_QImode:
6250             case E_HImode:
6251             case E_SImode:
6252             case E_DImode:
6253             case E_TImode:
6254             case E_SFmode:
6255             case E_DFmode:
6256               {
6257                 /* call = vec_cmpeq (va, vb)
6258                    result = vec_nor (call, call).  */
6259                 vec<tree, va_gc> *params = make_tree_vector ();
6260                 vec_safe_push (params, arg0);
6261                 vec_safe_push (params, arg1);
6262                 tree call = altivec_resolve_overloaded_builtin
6263                   (loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_CMPEQ],
6264                    params);
6265                 /* Use save_expr to ensure that operands used more than once
6266                    that may have side effects (like calls) are only evaluated
6267                    once.  */
6268                 call = save_expr (call);
6269                 params = make_tree_vector ();
6270                 vec_safe_push (params, call);
6271                 vec_safe_push (params, call);
6272                 return altivec_resolve_overloaded_builtin
6273                   (loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_NOR], params);
6274               }
6275               /* Other types are errors.  */
6276             default:
6277               goto bad;
6278             }
6279         }
6280       /* else, fall through and process the Power9 alternative below */
6281     }
6282
6283   if (fcode == ALTIVEC_BUILTIN_VEC_ADDE
6284       || fcode == ALTIVEC_BUILTIN_VEC_SUBE)
6285     {
6286       /* vec_adde needs to be special cased because there is no instruction
6287           for the {un}signed int version.  */
6288       if (nargs != 3)
6289         {
6290           const char *name = fcode == ALTIVEC_BUILTIN_VEC_ADDE ?
6291             "vec_adde": "vec_sube";
6292           error ("builtin %qs only accepts 3 arguments", name);
6293           return error_mark_node;
6294         }
6295
6296       tree arg0 = (*arglist)[0];
6297       tree arg0_type = TREE_TYPE (arg0);
6298       tree arg1 = (*arglist)[1];
6299       tree arg1_type = TREE_TYPE (arg1);
6300       tree arg2 = (*arglist)[2];
6301       tree arg2_type = TREE_TYPE (arg2);
6302
6303       /* All 3 arguments must be vectors of (signed or unsigned) (int or
6304          __int128) and the types must be compatible.  */
6305       if (TREE_CODE (arg0_type) != VECTOR_TYPE)
6306         goto bad;
6307       if (!lang_hooks.types_compatible_p (arg0_type, arg1_type)
6308           || !lang_hooks.types_compatible_p (arg1_type, arg2_type))
6309         goto bad;
6310
6311       switch (TYPE_MODE (TREE_TYPE (arg0_type)))
6312         {
6313           /* For {un}signed ints,
6314              vec_adde (va, vb, carryv) == vec_add (vec_add (va, vb),
6315                                                    vec_and (carryv, 1)).
6316              vec_sube (va, vb, carryv) == vec_sub (vec_sub (va, vb),
6317                                                    vec_and (carryv, 1)).  */
6318           case E_SImode:
6319             {
6320               tree add_sub_builtin;
6321
6322               vec<tree, va_gc> *params = make_tree_vector ();
6323               vec_safe_push (params, arg0);
6324               vec_safe_push (params, arg1);
6325
6326               if (fcode == ALTIVEC_BUILTIN_VEC_ADDE)
6327                 add_sub_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADD];
6328               else
6329                 add_sub_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUB];
6330
6331               tree call = altivec_resolve_overloaded_builtin (loc,
6332                                                               add_sub_builtin,
6333                                                               params);
6334               tree const1 = build_int_cstu (TREE_TYPE (arg0_type), 1);
6335               tree ones_vector = build_vector_from_val (arg0_type, const1);
6336               tree and_expr = fold_build2_loc (loc, BIT_AND_EXPR, arg0_type,
6337                                                arg2, ones_vector);
6338               params = make_tree_vector ();
6339               vec_safe_push (params, call);
6340               vec_safe_push (params, and_expr);
6341               return altivec_resolve_overloaded_builtin (loc, add_sub_builtin,
6342                                                          params);
6343             }
6344           /* For {un}signed __int128s use the vaddeuqm instruction
6345                 directly.  */
6346           case E_TImode:
6347             {
6348                tree bii;
6349
6350                if (fcode == ALTIVEC_BUILTIN_VEC_ADDE)
6351                  bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VADDEUQM];
6352
6353                else
6354                  bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VSUBEUQM];
6355
6356                return altivec_resolve_overloaded_builtin (loc, bii, arglist);
6357             }
6358
6359           /* Types other than {un}signed int and {un}signed __int128
6360                 are errors.  */
6361           default:
6362             goto bad;
6363         }
6364     }
6365
6366   if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC
6367       || fcode == ALTIVEC_BUILTIN_VEC_SUBEC)
6368     {
6369       /* vec_addec and vec_subec needs to be special cased because there is
6370          no instruction for the {un}signed int version.  */
6371       if (nargs != 3)
6372         {
6373           const char *name = fcode == ALTIVEC_BUILTIN_VEC_ADDEC ?
6374             "vec_addec": "vec_subec";
6375           error ("builtin %qs only accepts 3 arguments", name);
6376           return error_mark_node;
6377         }
6378
6379       tree arg0 = (*arglist)[0];
6380       tree arg0_type = TREE_TYPE (arg0);
6381       tree arg1 = (*arglist)[1];
6382       tree arg1_type = TREE_TYPE (arg1);
6383       tree arg2 = (*arglist)[2];
6384       tree arg2_type = TREE_TYPE (arg2);
6385
6386       /* All 3 arguments must be vectors of (signed or unsigned) (int or
6387          __int128) and the types must be compatible.  */
6388       if (TREE_CODE (arg0_type) != VECTOR_TYPE)
6389         goto bad;
6390       if (!lang_hooks.types_compatible_p (arg0_type, arg1_type)
6391           || !lang_hooks.types_compatible_p (arg1_type, arg2_type))
6392         goto bad;
6393
6394       switch (TYPE_MODE (TREE_TYPE (arg0_type)))
6395         {
6396           /* For {un}signed ints,
6397               vec_addec (va, vb, carryv) ==
6398                                 vec_or (vec_addc (va, vb),
6399                                         vec_addc (vec_add (va, vb),
6400                                                   vec_and (carryv, 0x1))).  */
6401           case E_SImode:
6402             {
6403             /* Use save_expr to ensure that operands used more than once
6404                 that may have side effects (like calls) are only evaluated
6405                 once.  */
6406             tree as_builtin;
6407             tree as_c_builtin;
6408
6409             arg0 = save_expr (arg0);
6410             arg1 = save_expr (arg1);
6411             vec<tree, va_gc> *params = make_tree_vector ();
6412             vec_safe_push (params, arg0);
6413             vec_safe_push (params, arg1);
6414
6415             if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC)
6416               as_c_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADDC];
6417             else
6418               as_c_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUBC];
6419
6420             tree call1 = altivec_resolve_overloaded_builtin (loc, as_c_builtin,
6421                                                              params);
6422             params = make_tree_vector ();
6423             vec_safe_push (params, arg0);
6424             vec_safe_push (params, arg1);
6425
6426
6427             if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC)
6428               as_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADD];
6429             else
6430               as_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUB];
6431
6432             tree call2 = altivec_resolve_overloaded_builtin (loc, as_builtin,
6433                                                              params);
6434             tree const1 = build_int_cstu (TREE_TYPE (arg0_type), 1);
6435             tree ones_vector = build_vector_from_val (arg0_type, const1);
6436             tree and_expr = fold_build2_loc (loc, BIT_AND_EXPR, arg0_type,
6437                                              arg2, ones_vector);
6438             params = make_tree_vector ();
6439             vec_safe_push (params, call2);
6440             vec_safe_push (params, and_expr);
6441             call2 = altivec_resolve_overloaded_builtin (loc, as_c_builtin,
6442                                                         params);
6443             params = make_tree_vector ();
6444             vec_safe_push (params, call1);
6445             vec_safe_push (params, call2);
6446             tree or_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_OR];
6447             return altivec_resolve_overloaded_builtin (loc, or_builtin,
6448                                                        params);
6449             }
6450           /* For {un}signed __int128s use the vaddecuq/vsubbecuq
6451              instructions.  */
6452           case E_TImode:
6453             {
6454                tree bii;
6455
6456                if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC)
6457                  bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VADDECUQ];
6458
6459                else
6460                  bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VSUBECUQ];
6461
6462                return altivec_resolve_overloaded_builtin (loc, bii, arglist);
6463             }
6464           /* Types other than {un}signed int and {un}signed __int128
6465                 are errors.  */
6466           default:
6467             goto bad;
6468         }
6469     }
6470
6471   /* For now treat vec_splats and vec_promote as the same.  */
6472   if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS
6473       || fcode == ALTIVEC_BUILTIN_VEC_PROMOTE)
6474     {
6475       tree type, arg;
6476       int size;
6477       int i;
6478       bool unsigned_p;
6479       vec<constructor_elt, va_gc> *vec;
6480       const char *name = fcode == ALTIVEC_BUILTIN_VEC_SPLATS ? "vec_splats": "vec_promote";
6481
6482       if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS && nargs != 1)
6483         {
6484           error ("builtin %qs only accepts 1 argument", name);
6485           return error_mark_node;
6486         }
6487       if (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE && nargs != 2)
6488         {
6489           error ("builtin %qs only accepts 2 arguments", name);
6490           return error_mark_node;
6491         }
6492       /* Ignore promote's element argument.  */
6493       if (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE
6494           && !INTEGRAL_TYPE_P (TREE_TYPE ((*arglist)[1])))
6495         goto bad;
6496
6497       arg = (*arglist)[0];
6498       type = TREE_TYPE (arg);
6499       if (!SCALAR_FLOAT_TYPE_P (type)
6500           && !INTEGRAL_TYPE_P (type))
6501         goto bad;
6502       unsigned_p = TYPE_UNSIGNED (type);
6503       switch (TYPE_MODE (type))
6504         {
6505           case E_TImode:
6506             type = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
6507             size = 1;
6508             break;
6509           case E_DImode:
6510             type = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
6511             size = 2;
6512             break;
6513           case E_SImode:
6514             type = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
6515             size = 4;
6516             break;
6517           case E_HImode:
6518             type = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
6519             size = 8;
6520             break;
6521           case E_QImode:
6522             type = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
6523             size = 16;
6524             break;
6525           case E_SFmode: type = V4SF_type_node; size = 4; break;
6526           case E_DFmode: type = V2DF_type_node; size = 2; break;
6527           default:
6528             goto bad;
6529         }
6530       arg = save_expr (fold_convert (TREE_TYPE (type), arg));
6531       vec_alloc (vec, size);
6532       for(i = 0; i < size; i++)
6533         {
6534           constructor_elt elt = {NULL_TREE, arg};
6535           vec->quick_push (elt);
6536         }
6537         return build_constructor (type, vec);
6538     }
6539
6540   /* For now use pointer tricks to do the extraction, unless we are on VSX
6541      extracting a double from a constant offset.  */
6542   if (fcode == ALTIVEC_BUILTIN_VEC_EXTRACT)
6543     {
6544       tree arg1;
6545       tree arg1_type;
6546       tree arg2;
6547       tree arg1_inner_type;
6548       tree decl, stmt;
6549       tree innerptrtype;
6550       machine_mode mode;
6551
6552       /* No second argument. */
6553       if (nargs != 2)
6554         {
6555           error ("builtin %qs only accepts 2 arguments", "vec_extract");
6556           return error_mark_node;
6557         }
6558
6559       arg2 = (*arglist)[1];
6560       arg1 = (*arglist)[0];
6561       arg1_type = TREE_TYPE (arg1);
6562
6563       if (TREE_CODE (arg1_type) != VECTOR_TYPE)
6564         goto bad;
6565       if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))
6566         goto bad;
6567
6568       /* If we are targeting little-endian, but -maltivec=be has been
6569          specified to override the element order, adjust the element
6570          number accordingly.  */
6571       if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2)
6572         {
6573           unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1;
6574           arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2),
6575                                   build_int_cstu (TREE_TYPE (arg2), last_elem),
6576                                   arg2);
6577         }
6578
6579       /* See if we can optimize vec_extracts with the current VSX instruction
6580          set.  */
6581       mode = TYPE_MODE (arg1_type);
6582       if (VECTOR_MEM_VSX_P (mode))
6583
6584         {
6585           tree call = NULL_TREE;
6586           int nunits = GET_MODE_NUNITS (mode);
6587
6588           arg2 = fold_for_warn (arg2);
6589
6590           /* If the second argument is an integer constant, if the value is in
6591              the expected range, generate the built-in code if we can.  We need
6592              64-bit and direct move to extract the small integer vectors.  */
6593           if (TREE_CODE (arg2) == INTEGER_CST
6594               && wi::ltu_p (wi::to_wide (arg2), nunits))
6595             {
6596               switch (mode)
6597                 {
6598                 default:
6599                   break;
6600
6601                 case E_V1TImode:
6602                   call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V1TI];
6603                   break;
6604
6605                 case E_V2DFmode:
6606                   call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
6607                   break;
6608
6609                 case E_V2DImode:
6610                   call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
6611                   break;
6612
6613                 case E_V4SFmode:
6614                   call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF];
6615                   break;
6616
6617                 case E_V4SImode:
6618                   if (TARGET_DIRECT_MOVE_64BIT)
6619                     call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI];
6620                   break;
6621
6622                 case E_V8HImode:
6623                   if (TARGET_DIRECT_MOVE_64BIT)
6624                     call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI];
6625                   break;
6626
6627                 case E_V16QImode:
6628                   if (TARGET_DIRECT_MOVE_64BIT)
6629                     call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI];
6630                   break;
6631                 }
6632             }
6633
6634           /* If the second argument is variable, we can optimize it if we are
6635              generating 64-bit code on a machine with direct move.  */
6636           else if (TREE_CODE (arg2) != INTEGER_CST && TARGET_DIRECT_MOVE_64BIT)
6637             {
6638               switch (mode)
6639                 {
6640                 default:
6641                   break;
6642
6643                 case E_V2DFmode:
6644                   call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
6645                   break;
6646
6647                 case E_V2DImode:
6648                   call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
6649                   break;
6650
6651                 case E_V4SFmode:
6652                   call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF];
6653                   break;
6654
6655                 case E_V4SImode:
6656                   call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI];
6657                   break;
6658
6659                 case E_V8HImode:
6660                   call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI];
6661                   break;
6662
6663                 case E_V16QImode:
6664                   call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI];
6665                   break;
6666                 }
6667             }
6668
6669           if (call)
6670             return build_call_expr (call, 2, arg1, arg2);
6671         }
6672
6673       /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2). */
6674       arg1_inner_type = TREE_TYPE (arg1_type);
6675       arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2,
6676                               build_int_cst (TREE_TYPE (arg2),
6677                                              TYPE_VECTOR_SUBPARTS (arg1_type)
6678                                              - 1), 0);
6679       decl = build_decl (loc, VAR_DECL, NULL_TREE, arg1_type);
6680       DECL_EXTERNAL (decl) = 0;
6681       TREE_PUBLIC (decl) = 0;
6682       DECL_CONTEXT (decl) = current_function_decl;
6683       TREE_USED (decl) = 1;
6684       TREE_TYPE (decl) = arg1_type;
6685       TREE_READONLY (decl) = TYPE_READONLY (arg1_type);
6686       if (c_dialect_cxx ())
6687         {
6688           stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1,
6689                          NULL_TREE, NULL_TREE);
6690           SET_EXPR_LOCATION (stmt, loc);
6691         }
6692       else
6693         {
6694           DECL_INITIAL (decl) = arg1;
6695           stmt = build1 (DECL_EXPR, arg1_type, decl);
6696           TREE_ADDRESSABLE (decl) = 1;
6697           SET_EXPR_LOCATION (stmt, loc);
6698           stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt);
6699         }
6700
6701       innerptrtype = build_pointer_type (arg1_inner_type);
6702
6703       stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0);
6704       stmt = convert (innerptrtype, stmt);
6705       stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1);
6706       stmt = build_indirect_ref (loc, stmt, RO_NULL);
6707
6708       /* PR83660: We mark this as having side effects so that
6709          downstream in fold_build_cleanup_point_expr () it will get a
6710          CLEANUP_POINT_EXPR.  If it does not we can run into an ICE
6711          later in gimplify_cleanup_point_expr ().  Potentially this
6712          causes missed optimization because the actually is no side
6713          effect.  */
6714       if (c_dialect_cxx ())
6715         TREE_SIDE_EFFECTS (stmt) = 1;
6716
6717       return stmt;
6718     }
6719
6720   /* For now use pointer tricks to do the insertion, unless we are on VSX
6721      inserting a double to a constant offset..  */
6722   if (fcode == ALTIVEC_BUILTIN_VEC_INSERT)
6723     {
6724       tree arg0;
6725       tree arg1;
6726       tree arg2;
6727       tree arg1_type;
6728       tree arg1_inner_type;
6729       tree decl, stmt;
6730       tree innerptrtype;
6731       machine_mode mode;
6732
6733       /* No second or third arguments. */
6734       if (nargs != 3)
6735         {
6736           error ("builtin %qs only accepts 3 arguments", "vec_insert");
6737           return error_mark_node;
6738         }
6739
6740       arg0 = (*arglist)[0];
6741       arg1 = (*arglist)[1];
6742       arg1_type = TREE_TYPE (arg1);
6743       arg2 = fold_for_warn ((*arglist)[2]);
6744
6745       if (TREE_CODE (arg1_type) != VECTOR_TYPE)
6746         goto bad;
6747       if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))
6748         goto bad;
6749
6750       /* If we are targeting little-endian, but -maltivec=be has been
6751          specified to override the element order, adjust the element
6752          number accordingly.  */
6753       if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2)
6754         {
6755           unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1;
6756           arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2),
6757                                   build_int_cstu (TREE_TYPE (arg2), last_elem),
6758                                   arg2);
6759         }
6760
6761       /* If we can use the VSX xxpermdi instruction, use that for insert.  */
6762       mode = TYPE_MODE (arg1_type);
6763       if ((mode == V2DFmode || mode == V2DImode) && VECTOR_UNIT_VSX_P (mode)
6764           && TREE_CODE (arg2) == INTEGER_CST
6765           && wi::ltu_p (wi::to_wide (arg2), 2))
6766         {
6767           tree call = NULL_TREE;
6768
6769           if (mode == V2DFmode)
6770             call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V2DF];
6771           else if (mode == V2DImode)
6772             call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V2DI];
6773
6774           /* Note, __builtin_vec_insert_<xxx> has vector and scalar types
6775              reversed.  */
6776           if (call)
6777             return build_call_expr (call, 3, arg1, arg0, arg2);
6778         }
6779       else if (mode == V1TImode && VECTOR_UNIT_VSX_P (mode)
6780                && TREE_CODE (arg2) == INTEGER_CST
6781                && wi::eq_p (wi::to_wide (arg2), 0))
6782         {
6783           tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V1TI];
6784
6785           /* Note, __builtin_vec_insert_<xxx> has vector and scalar types
6786              reversed.  */
6787           return build_call_expr (call, 3, arg1, arg0, arg2);
6788         }
6789
6790       /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2) = arg0. */
6791       arg1_inner_type = TREE_TYPE (arg1_type);
6792       arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2,
6793                               build_int_cst (TREE_TYPE (arg2),
6794                                              TYPE_VECTOR_SUBPARTS (arg1_type)
6795                                              - 1), 0);
6796       decl = build_decl (loc, VAR_DECL, NULL_TREE, arg1_type);
6797       DECL_EXTERNAL (decl) = 0;
6798       TREE_PUBLIC (decl) = 0;
6799       DECL_CONTEXT (decl) = current_function_decl;
6800       TREE_USED (decl) = 1;
6801       TREE_TYPE (decl) = arg1_type;
6802       TREE_READONLY (decl) = TYPE_READONLY (arg1_type);
6803       if (c_dialect_cxx ())
6804         {
6805           stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1,
6806                          NULL_TREE, NULL_TREE);
6807           SET_EXPR_LOCATION (stmt, loc);
6808         }
6809       else
6810         {
6811           DECL_INITIAL (decl) = arg1;
6812           stmt = build1 (DECL_EXPR, arg1_type, decl);
6813           TREE_ADDRESSABLE (decl) = 1;
6814           SET_EXPR_LOCATION (stmt, loc);
6815           stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt);
6816         }
6817
6818       innerptrtype = build_pointer_type (arg1_inner_type);
6819
6820       stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0);
6821       stmt = convert (innerptrtype, stmt);
6822       stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1);
6823       stmt = build_indirect_ref (loc, stmt, RO_NULL);
6824       stmt = build2 (MODIFY_EXPR, TREE_TYPE (stmt), stmt,
6825                      convert (TREE_TYPE (stmt), arg0));
6826       stmt = build2 (COMPOUND_EXPR, arg1_type, stmt, decl);
6827       return stmt;
6828     }
6829
6830   for (n = 0;
6831        !VOID_TYPE_P (TREE_VALUE (fnargs)) && n < nargs;
6832        fnargs = TREE_CHAIN (fnargs), n++)
6833     {
6834       tree decl_type = TREE_VALUE (fnargs);
6835       tree arg = (*arglist)[n];
6836       tree type;
6837
6838       if (arg == error_mark_node)
6839         return error_mark_node;
6840
6841       if (n >= 3)
6842         abort ();
6843
6844       arg = default_conversion (arg);
6845
6846       /* The C++ front-end converts float * to const void * using
6847          NOP_EXPR<const void *> (NOP_EXPR<void *> (x)).  */
6848       type = TREE_TYPE (arg);
6849       if (POINTER_TYPE_P (type)
6850           && TREE_CODE (arg) == NOP_EXPR
6851           && lang_hooks.types_compatible_p (TREE_TYPE (arg),
6852                                             const_ptr_type_node)
6853           && lang_hooks.types_compatible_p (TREE_TYPE (TREE_OPERAND (arg, 0)),
6854                                             ptr_type_node))
6855         {
6856           arg = TREE_OPERAND (arg, 0);
6857           type = TREE_TYPE (arg);
6858         }
6859
6860       /* Remove the const from the pointers to simplify the overload
6861          matching further down.  */
6862       if (POINTER_TYPE_P (decl_type)
6863           && POINTER_TYPE_P (type)
6864           && TYPE_QUALS (TREE_TYPE (type)) != 0)
6865         {
6866           if (TYPE_READONLY (TREE_TYPE (type))
6867               && !TYPE_READONLY (TREE_TYPE (decl_type)))
6868             warning (0, "passing arg %d of %qE discards qualifiers from "
6869                         "pointer target type", n + 1, fndecl);
6870           type = build_pointer_type (build_qualified_type (TREE_TYPE (type),
6871                                                            0));
6872           arg = fold_convert (type, arg);
6873         }
6874
6875       args[n] = arg;
6876       types[n] = type;
6877     }
6878
6879   /* If the number of arguments did not match the prototype, return NULL
6880      and the generic code will issue the appropriate error message.  */
6881   if (!VOID_TYPE_P (TREE_VALUE (fnargs)) || n < nargs)
6882     return NULL;
6883
6884   if (n == 0)
6885     abort ();
6886
6887   if (fcode == ALTIVEC_BUILTIN_VEC_STEP)
6888     {
6889       if (TREE_CODE (types[0]) != VECTOR_TYPE)
6890         goto bad;
6891
6892       return build_int_cst (NULL_TREE, TYPE_VECTOR_SUBPARTS (types[0]));
6893     }
6894
6895   {
6896     bool unsupported_builtin = false;
6897     enum rs6000_builtins overloaded_code;
6898     tree result = NULL;
6899     for (desc = altivec_overloaded_builtins;
6900          desc->code && desc->code != fcode; desc++)
6901       continue;
6902
6903     /* Need to special case __builtin_cmp because the overloaded forms
6904        of this function take (unsigned int, unsigned int) or (unsigned
6905        long long int, unsigned long long int).  Since C conventions
6906        allow the respective argument types to be implicitly coerced into
6907        each other, the default handling does not provide adequate
6908        discrimination between the desired forms of the function.  */
6909     if (fcode == P6_OV_BUILTIN_CMPB)
6910       {
6911         machine_mode arg1_mode = TYPE_MODE (types[0]);
6912         machine_mode arg2_mode = TYPE_MODE (types[1]);
6913
6914         if (nargs != 2)
6915           {
6916             error ("builtin %qs only accepts 2 arguments", "__builtin_cmpb");
6917             return error_mark_node;
6918           }
6919
6920         /* If any supplied arguments are wider than 32 bits, resolve to
6921            64-bit variant of built-in function.  */
6922         if ((GET_MODE_PRECISION (arg1_mode) > 32)
6923             || (GET_MODE_PRECISION (arg2_mode) > 32))
6924           {
6925             /* Assure all argument and result types are compatible with
6926                the built-in function represented by P6_BUILTIN_CMPB.  */
6927             overloaded_code = P6_BUILTIN_CMPB;
6928           }
6929         else
6930           {
6931             /* Assure all argument and result types are compatible with
6932                the built-in function represented by P6_BUILTIN_CMPB_32.  */
6933             overloaded_code = P6_BUILTIN_CMPB_32;
6934           }
6935
6936         while (desc->code && desc->code == fcode
6937                && desc->overloaded_code != overloaded_code)
6938           desc++;
6939
6940         if (desc->code && (desc->code == fcode)
6941             && rs6000_builtin_type_compatible (types[0], desc->op1)
6942             && rs6000_builtin_type_compatible (types[1], desc->op2))
6943           {
6944             if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
6945               {
6946                 result = altivec_build_resolved_builtin (args, n, desc);
6947                 /* overloaded_code is set above */
6948                 if (!rs6000_builtin_is_supported_p (overloaded_code))
6949                   unsupported_builtin = true;
6950                 else
6951                   return result;
6952               }
6953             else
6954               unsupported_builtin = true;
6955           }
6956       }
6957     else if (fcode == P9V_BUILTIN_VEC_VSIEDP)
6958       {
6959         machine_mode arg1_mode = TYPE_MODE (types[0]);
6960
6961         if (nargs != 2)
6962           {
6963             error ("builtin %qs only accepts 2 arguments",
6964                    "scalar_insert_exp");
6965             return error_mark_node;
6966           }
6967
6968         /* If supplied first argument is wider than 64 bits, resolve to
6969            128-bit variant of built-in function.  */
6970         if (GET_MODE_PRECISION (arg1_mode) > 64)
6971           {
6972             /* If first argument is of float variety, choose variant
6973                that expects __ieee128 argument.  Otherwise, expect
6974                __int128 argument.  */
6975             if (GET_MODE_CLASS (arg1_mode) == MODE_FLOAT)
6976               overloaded_code = P9V_BUILTIN_VSIEQPF;
6977             else
6978               overloaded_code = P9V_BUILTIN_VSIEQP;
6979           }
6980         else
6981           {
6982             /* If first argument is of float variety, choose variant
6983                that expects double argument.  Otherwise, expect
6984                long long int argument.  */
6985             if (GET_MODE_CLASS (arg1_mode) == MODE_FLOAT)
6986               overloaded_code = P9V_BUILTIN_VSIEDPF;
6987             else
6988               overloaded_code = P9V_BUILTIN_VSIEDP;
6989           }
6990         while (desc->code && desc->code == fcode
6991                && desc->overloaded_code != overloaded_code)
6992           desc++;
6993
6994         if (desc->code && (desc->code == fcode)
6995             && rs6000_builtin_type_compatible (types[0], desc->op1)
6996             && rs6000_builtin_type_compatible (types[1], desc->op2))
6997           {
6998             if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
6999               {
7000                 result = altivec_build_resolved_builtin (args, n, desc);
7001                 /* overloaded_code is set above.  */
7002                 if (!rs6000_builtin_is_supported_p (overloaded_code))
7003                   unsupported_builtin = true;
7004                 else
7005                   return result;
7006               }
7007             else
7008               unsupported_builtin = true;
7009           }
7010       }
7011     else
7012       {
7013         /* For arguments after the last, we have RS6000_BTI_NOT_OPAQUE in
7014            the opX fields.  */
7015         for (; desc->code == fcode; desc++)
7016           {
7017             if ((desc->op1 == RS6000_BTI_NOT_OPAQUE
7018                  || rs6000_builtin_type_compatible (types[0], desc->op1))
7019                 && (desc->op2 == RS6000_BTI_NOT_OPAQUE
7020                     || rs6000_builtin_type_compatible (types[1], desc->op2))
7021                 && (desc->op3 == RS6000_BTI_NOT_OPAQUE
7022                     || rs6000_builtin_type_compatible (types[2], desc->op3)))
7023               {
7024                 if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
7025                   {
7026                     result = altivec_build_resolved_builtin (args, n, desc);
7027                     if (!rs6000_builtin_is_supported_p (desc->overloaded_code))
7028                       {
7029                         /* Allow loop to continue in case a different
7030                            definition is supported.  */
7031                         overloaded_code = desc->overloaded_code;
7032                         unsupported_builtin = true;
7033                       }
7034                     else
7035                       return result;
7036                   }
7037                 else
7038                   unsupported_builtin = true;
7039               }
7040           }
7041       }
7042
7043     if (unsupported_builtin)
7044       {
7045         const char *name = rs6000_overloaded_builtin_name (fcode);
7046         if (result != NULL)
7047           {
7048             const char *internal_name
7049               = rs6000_overloaded_builtin_name (overloaded_code);
7050             /* An error message making reference to the name of the
7051                non-overloaded function has already been issued.  Add
7052                clarification of the previous message.  */
7053             rich_location richloc (line_table, input_location);
7054             inform (&richloc, "builtin %qs requires builtin %qs",
7055                     name, internal_name);
7056           }
7057         else
7058           error ("builtin function %qs not supported in this compiler "
7059                  "configuration", name);
7060         /* If an error-representing  result tree was returned from
7061            altivec_build_resolved_builtin above, use it.  */
7062         return (result != NULL) ? result : error_mark_node;
7063       }
7064   }
7065  bad:
7066   {
7067     const char *name = rs6000_overloaded_builtin_name (fcode);
7068     error ("invalid parameter combination for AltiVec intrinsic %qs", name);
7069     return error_mark_node;
7070   }
7071 }