| blob | 4a57557fe8cf16481fa5a56d621cf8b970d3a0de |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
106 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
138 /* Number of attempts to combine instructions in this function. */
142 /* Number of attempts that got as far as substitution in this function. */
146 /* Number of instructions combined with added SETs in this function. */
150 /* Number of instructions combined in this function. */
154 /* Totals over entire compilation. */
158 /* combine_instructions may try to replace the right hand side of the
159 second instruction with the value of an associated REG_EQUAL note
160 before throwing it at try_combine. That is problematic when there
161 is a REG_DEAD note for a register used in the old right hand side
162 and can cause distribute_notes to do wrong things. This is the
163 second instruction if it has been so modified, null otherwise. */
167 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
171 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
174 \f
176 /* Record last point of death of (hard or pseudo) register n. */
179 /* Record last point of modification of (hard or pseudo) register n. */
182 /* The next group of fields allows the recording of the last value assigned
183 to (hard or pseudo) register n. We use this information to see if an
184 operation being processed is redundant given a prior operation performed
185 on the register. For example, an `and' with a constant is redundant if
186 all the zero bits are already known to be turned off.
188 We use an approach similar to that used by cse, but change it in the
189 following ways:
191 (1) We do not want to reinitialize at each label.
192 (2) It is useful, but not critical, to know the actual value assigned
193 to a register. Often just its form is helpful.
195 Therefore, we maintain the following fields:
197 last_set_value the last value assigned
198 last_set_label records the value of label_tick when the
199 register was assigned
200 last_set_table_tick records the value of label_tick when a
201 value using the register is assigned
202 last_set_invalid set to nonzero when it is not valid
203 to use the value of this register in some
204 register's value
206 To understand the usage of these tables, it is important to understand
207 the distinction between the value in last_set_value being valid and
208 the register being validly contained in some other expression in the
209 table.
211 (The next two parameters are out of date).
213 reg_stat[i].last_set_value is valid if it is nonzero, and either
214 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
216 Register I may validly appear in any expression returned for the value
217 of another register if reg_n_sets[i] is 1. It may also appear in the
218 value for register J if reg_stat[j].last_set_invalid is zero, or
219 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
221 If an expression is found in the table containing a register which may
222 not validly appear in an expression, the register is replaced by
223 something that won't match, (clobber (const_int 0)). */
225 /* Record last value assigned to (hard or pseudo) register n. */
227 rtx last_set_value;
229 /* Record the value of label_tick when an expression involving register n
230 is placed in last_set_value. */
234 /* Record the value of label_tick when the value for register n is placed in
235 last_set_value. */
239 /* These fields are maintained in parallel with last_set_value and are
240 used to store the mode in which the register was last set, the bits
241 that were known to be zero when it was last set, and the number of
242 sign bits copies it was known to have when it was last set. */
248 /* Set nonzero if references to register n in expressions should not be
249 used. last_set_invalid is set nonzero when this register is being
250 assigned to and last_set_table_tick == label_tick. */
254 /* Some registers that are set more than once and used in more than one
255 basic block are nevertheless always set in similar ways. For example,
256 a QImode register may be loaded from memory in two places on a machine
257 where byte loads zero extend.
259 We record in the following fields if a register has some leading bits
260 that are always equal to the sign bit, and what we know about the
261 nonzero bits of a register, specifically which bits are known to be
262 zero.
264 If an entry is zero, it means that we don't know anything special. */
270 /* Record the value of the label_tick when the last truncation
271 happened. The field truncated_to_mode is only valid if
272 truncation_label == label_tick. */
276 /* Record the last truncation seen for this register. If truncation
277 is not a nop to this mode we might be able to save an explicit
278 truncation if we know that value already contains a truncated
279 value. */
287 /* One plus the highest pseudo for which we track REG_N_SETS.
288 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
289 but during combine_split_insns new pseudos can be created. As we don't have
290 updated DF information in that case, it is hard to initialize the array
291 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
292 so instead of growing the arrays, just assume all newly created pseudos
293 during combine might be set multiple times. */
297 /* Record the luid of the last insn that invalidated memory
298 (anything that writes memory, and subroutine calls, but not pushes). */
302 /* Record the luid of the last CALL_INSN
303 so we can tell whether a potential combination crosses any calls. */
307 /* When `subst' is called, this is the insn that is being modified
308 (by combining in a previous insn). The PATTERN of this insn
309 is still the old pattern partially modified and it should not be
310 looked at, but this may be used to examine the successors of the insn
311 to judge whether a simplification is valid. */
315 /* This is the lowest LUID that `subst' is currently dealing with.
316 get_last_value will not return a value if the register was set at or
317 after this LUID. If not for this mechanism, we could get confused if
318 I2 or I1 in try_combine were an insn that used the old value of a register
319 to obtain a new value. In that case, we might erroneously get the
320 new value of the register when we wanted the old one. */
324 /* This contains any hard registers that are used in newpat; reg_dead_at_p
325 must consider all these registers to be always live. */
329 /* This is an insn to which a LOG_LINKS entry has been added. If this
330 insn is the earlier than I2 or I3, combine should rescan starting at
331 that location. */
335 /* Basic block in which we are performing combines. */
339 \f
340 /* Length of the currently allocated uid_insn_cost array. */
344 /* The following array records the insn_rtx_cost for every insn
345 in the instruction stream. */
349 /* The following array records the LOG_LINKS for every insn in the
350 instruction stream as struct insn_link pointers. */
356 };
360 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
361 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
363 #define FOR_EACH_LOG_LINK(L, INSN) \
364 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
366 /* Links for LOG_LINKS are allocated from this obstack. */
370 /* Allocate a link. */
374 {
382 }
384 /* Incremented for each basic block. */
388 /* Reset to label_tick for each extended basic block in scanning order. */
392 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
393 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
397 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
398 be safely used. It is zero while computing them and after combine has
399 completed. This former test prevents propagating values based on
400 previously set values, which can be incorrect if a variable is modified
401 in a loop. */
405 \f
406 /* Record one modification to rtl structure
407 to be undone by storing old_contents into *where. */
411 struct undo
412 {
417 };
419 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
420 num_undo says how many are currently recorded.
422 other_insn is nonzero if we have modified some other insn in the process
423 of working on subst_insn. It must be verified too. */
425 struct undobuf
426 {
430 };
434 /* Number of times the pseudo being substituted for
435 was found and replaced. */
440 machine_mode,
444 machine_mode,
516 \f
518 /* It is not safe to use ordinary gen_lowpart in combine.
519 See comments in gen_lowpart_for_combine. */
520 #undef RTL_HOOKS_GEN_LOWPART
521 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
523 /* Our implementation of gen_lowpart never emits a new pseudo. */
524 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
525 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
527 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
528 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
530 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
531 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
533 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
534 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
538 \f
539 /* Convenience wrapper for the canonicalize_comparison target hook.
540 Target hooks cannot use enum rtx_code. */
544 {
548 }
550 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
551 PATTERN can not be split. Otherwise, it returns an insn sequence.
552 This is a wrapper around split_insns which ensures that the
553 reg_stat vector is made larger if the splitter creates a new
554 register. */
558 {
567 }
569 /* This is used by find_single_use to locate an rtx in LOC that
570 contains exactly one use of DEST, which is typically either a REG
571 or CC0. It returns a pointer to the innermost rtx expression
572 containing DEST. Appearances of DEST that are being used to
573 totally replace it are not counted. */
577 {
586 {
590 CASE_CONST_ANY:
595 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
596 of a REG that occupies all of the REG, the insn uses DEST if
597 it is mentioned in the destination or the source. Otherwise, we
598 need just check the source. */
618 }
620 /* If it wasn't one of the common cases above, check each expression and
621 vector of this code. Look for a unique usage of DEST. */
625 {
627 {
632 else
638 /* Duplicate usage. */
640 }
642 {
646 {
652 else
659 }
660 }
661 }
664 }
667 /* See if DEST, produced in INSN, is used only a single time in the
668 sequel. If so, return a pointer to the innermost rtx expression in which
669 it is used.
671 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
673 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
674 care about REG_DEAD notes or LOG_LINKS.
676 Otherwise, we find the single use by finding an insn that has a
677 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
678 only referenced once in that insn, we know that it must be the first
679 and last insn referencing DEST. */
683 {
684 basic_block bb;
690 {
700 }
710 {
716 {
721 }
722 }
725 }
726 \f
727 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
728 insn. The substitution can be undone by undo_all. If INTO is already
729 set to NEWVAL, do not record this change. Because computing NEWVAL might
730 also call SUBST, we have to compute it before we put anything into
731 the undo table. */
733 static void
735 {
742 /* We'd like to catch as many invalid transformations here as
743 possible. Unfortunately, there are way too many mode changes
744 that are perfectly valid, so we'd waste too much effort for
745 little gain doing the checks here. Focus on catching invalid
746 transformations involving integer constants. */
749 {
750 /* Sanity check that we're replacing oldval with a CONST_INT
751 that is a valid sign-extension for the original mode. */
755 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
756 CONST_INT is not valid, because after the replacement, the
757 original mode would be gone. Unfortunately, we can't tell
758 when do_SUBST is called to replace the operand thereof, so we
759 perform this test on oldval instead, checking whether an
760 invalid replacement took place before we got here. */
765 }
769 else
778 }
780 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
782 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
783 for the value of a HOST_WIDE_INT value (including CONST_INT) is
784 not safe. */
786 static void
788 {
797 else
806 }
808 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
810 /* Similar to SUBST, but just substitute the mode. This is used when
811 changing the mode of a pseudo-register, so that any other
812 references to the entry in the regno_reg_rtx array will change as
813 well. */
815 static void
817 {
826 else
835 }
837 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
839 #if !HAVE_cc0
840 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
842 static void
844 {
853 else
862 }
864 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
865 #endif
866 \f
867 /* Subroutine of try_combine. Determine whether the replacement patterns
868 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
869 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
870 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
871 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
872 of all the instructions can be estimated and the replacements are more
873 expensive than the original sequence. */
875 static bool
878 {
883 /* Lookup the original insn_rtx_costs. */
888 {
891 {
895 }
896 else
897 {
901 }
902 }
903 else
904 {
907 }
909 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
910 correct that. */
915 /* Calculate the replacement insn_rtx_costs. */
918 {
922 }
923 else
924 {
927 }
930 {
936 {
939 }
940 else
942 }
944 /* Disallow this combination if both new_cost and old_cost are greater than
945 zero, and new_cost is greater than old cost. */
949 {
968 else
970 }
975 /* Update the uid_insn_cost array with the replacement costs. */
979 {
983 }
986 }
989 /* Delete any insns that copy a register to itself. */
991 static void
993 {
995 basic_block bb;
998 {
1000 {
1003 {
1008 }
1009 }
1010 }
1011 }
1013 \f
1014 /* Return false if we do not want to (or cannot) combine DEF. */
1015 static bool
1017 {
1018 /* Do not consider if it is pre/post modification in MEM. */
1024 /* Do not combine frame pointer adjustments. */
1027 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1030 #endif
1036 }
1038 /* Return false if we do not want to (or cannot) combine USE. */
1039 static bool
1041 {
1042 /* Do not consider the usage of the stack pointer by function call. */
1047 }
1049 /* Fill in log links field for all insns. */
1051 static void
1053 {
1054 basic_block bb;
1061 /* Pass through each block from the end, recording the uses of each
1062 register and establishing log links when def is encountered.
1063 Note that we do not clear next_use array in order to save time,
1064 so we have to test whether the use is in the same basic block as def.
1066 There are a few cases below when we do not consider the definition or
1067 usage -- these are taken from original flow.c did. Don't ask me why it is
1068 done this way; I don't know and if it works, I don't want to know. */
1071 {
1073 {
1077 /* Log links are created only once. */
1081 {
1097 /* flow.c claimed:
1099 We don't build a LOG_LINK for hard registers contained
1100 in ASM_OPERANDs. If these registers get replaced,
1101 we might wind up changing the semantics of the insn,
1102 even if reload can make what appear to be valid
1103 assignments later. */
1108 /* Don't add duplicate links between instructions. */
1117 }
1122 }
1123 }
1126 }
1128 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1129 true if we found a LOG_LINK that proves that A feeds B. This only works
1130 if there are no instructions between A and B which could have a link
1131 depending on A, since in that case we would not record a link for B.
1132 We also check the implicit dependency created by a cc0 setter/user
1133 pair. */
1135 static bool
1137 {
1145 }
1146 \f
1147 /* Main entry point for combiner. F is the first insn of the function.
1148 NREGS is the first unused pseudo-reg number.
1150 Return nonzero if the combiner has turned an indirect jump
1151 instruction into a direct jump. */
1152 static int
1154 {
1156 #if HAVE_cc0
1158 #endif
1161 basic_block last_bb;
1181 /* Allocate array for insn info. */
1189 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1190 problems when, for example, we have j <<= 1 in a loop. */
1195 /* Scan all SETs and see if we can deduce anything about what
1196 bits are known to be zero for some registers and how many copies
1197 of the sign bit are known to exist for those registers.
1199 Also set any known values so that we can use it while searching
1200 for what bits are known to be set. */
1203 /* Allow the entry block and the first block to fall into the same EBB.
1204 Conceptually the incoming promotions are assigned to the entry block. */
1209 {
1214 label_tick++;
1222 {
1223 #ifdef AUTO_INC_DEC
1224 rtx links;
1225 #endif
1231 insn);
1234 #ifdef AUTO_INC_DEC
1238 insn);
1239 #endif
1241 /* Record the current insn_rtx_cost of this instruction. */
1244 optimize_this_for_speed_p);
1248 }
1249 }
1253 /* Now scan all the insns in forward order. */
1261 {
1267 label_tick++;
1277 {
1291 /* See if we know about function return values before this
1292 insn based upon SUBREG flags. */
1295 /* See if we can find hardregs and subreg of pseudos in
1296 narrower modes. This could help turning TRUNCATEs
1297 into SUBREGs. */
1300 /* Try this insn with each insn it links back to. */
1306 {
1309 }
1311 /* Try each sequence of three linked insns ending with this one. */
1315 {
1318 /* If the linked insn has been replaced by a note, then there
1319 is no point in pursuing this chain any further. */
1327 {
1330 }
1331 }
1333 #if HAVE_cc0
1334 /* Try to combine a jump insn that uses CC0
1335 with a preceding insn that sets CC0, and maybe with its
1336 logical predecessor as well.
1337 This is how we make decrement-and-branch insns.
1338 We need this special code because data flow connections
1339 via CC0 do not get entered in LOG_LINKS. */
1345 {
1356 }
1358 /* Do the same for an insn that explicitly references CC0. */
1365 {
1376 }
1378 /* Finally, see if any of the insns that this insn links to
1379 explicitly references CC0. If so, try this insn, that insn,
1380 and its predecessor if it sets CC0. */
1392 #endif
1394 /* Try combining an insn with two different insns whose results it
1395 uses. */
1405 {
1408 }
1410 /* Try four-instruction combinations. */
1413 {
1417 /* If the linked insn has been replaced by a note, then there
1418 is no point in pursuing this chain any further. */
1423 {
1427 /* I0 -> I1 -> I2 -> I3. */
1433 {
1436 }
1437 /* I0, I1 -> I2, I2 -> I3. */
1444 {
1447 }
1448 }
1451 {
1455 /* I0 -> I2; I1, I2 -> I3. */
1461 {
1464 }
1465 /* I0 -> I1; I1, I2 -> I3. */
1471 {
1474 }
1475 }
1476 }
1478 /* Try this insn with each REG_EQUAL note it links back to. */
1480 {
1486 /* Avoid using a register that may already been marked
1487 dead by an earlier instruction. */
1492 {
1493 /* Temporarily replace the set's source with the
1494 contents of the REG_EQUAL note. The insn will
1495 be deleted or recognized by try_combine. */
1503 last_combined_insn);
1506 {
1509 }
1511 }
1512 }
1517 retry:
1518 ;
1519 }
1520 }
1527 /* Clean up. */
1533 {
1536 {
1539 }
1541 }
1551 /* Make recognizer allow volatile MEMs again. */
1555 }
1557 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1559 static void
1561 {
1567 }
1568 \f
1569 /* Set up any promoted values for incoming argument registers. */
1571 static void
1573 {
1574 tree arg;
1579 {
1584 /* Only continue if the incoming argument is in a register. */
1588 /* Determine, if possible, whether all call sites of the current
1589 function lie within the current compilation unit. (This does
1590 take into account the exporting of a function via taking its
1591 address, and so forth.) */
1594 /* The mode and signedness of the argument before any promotions happen
1595 (equal to the mode of the pseudo holding it at that stage). */
1599 /* The mode and signedness of the argument after any source language and
1600 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1604 /* The mode and signedness of the argument as it is actually passed,
1605 see assign_parm_setup_reg in function.c. */
1609 /* The mode of the register in which the argument is being passed. */
1612 /* Eliminate sign extensions in the callee when:
1613 (a) A mode promotion has occurred; */
1616 /* (b) The mode of the register is the same as the mode of
1617 the argument as it is passed; */
1620 /* (c) There's no language level extension; */
1622 ;
1623 /* (c.1) All callers are from the current compilation unit. If that's
1624 the case we don't have to rely on an ABI, we only have to know
1625 what we're generating right now, and we know that we will do the
1626 mode1 to mode2 promotion with the given sign. */
1629 /* (c.2) The combination of the two promotions is useful. This is
1630 true when the signs match, or if the first promotion is unsigned.
1631 In the later case, (sign_extend (zero_extend x)) is the same as
1632 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1638 /* Record that the value was promoted from mode1 to mode3,
1639 so that any sign extension at the head of the current
1640 function may be eliminated. */
1644 }
1645 }
1647 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1648 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1649 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1650 because some machines (maybe most) will actually do the sign-extension and
1651 this is the conservative approach.
1653 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1654 kludge. */
1656 static rtx
1658 {
1666 }
1667 #endif
1669 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1670 and SET. */
1672 static void
1674 rtx x)
1675 {
1684 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1688 #endif
1690 /* Don't call nonzero_bits if it cannot change anything. */
1692 {
1697 }
1699 /* Don't call num_sign_bit_copies if it cannot change anything. */
1701 {
1704 {
1708 }
1711 }
1712 }
1714 /* Called via note_stores. If X is a pseudo that is narrower than
1715 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1717 If we are setting only a portion of X and we can't figure out what
1718 portion, assume all bits will be used since we don't know what will
1719 be happening.
1721 Similarly, set how many bits of X are known to be copies of the sign bit
1722 at all locations in the function. This is the smallest number implied
1723 by any set of X. */
1725 static void
1727 {
1732 /* If this register is undefined at the start of the file, we can't
1733 say what its contents were. */
1734 && ! REGNO_REG_SET_P
1737 {
1741 {
1745 }
1747 /* If this register is being initialized using itself, and the
1748 register is uninitialized in this basic block, and there are
1749 no LOG_LINKS which set the register, then part of the
1750 register is uninitialized. In that case we can't assume
1751 anything about the number of nonzero bits.
1753 ??? We could do better if we checked this in
1754 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1755 could avoid making assumptions about the insn which initially
1756 sets the register, while still using the information in other
1757 insns. We would have to be careful to check every insn
1758 involved in the combination. */
1764 {
1771 {
1775 }
1776 }
1778 /* If this is a complex assignment, see if we can convert it into a
1779 simple assignment. */
1782 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1783 set what we know about X. */
1789 else
1790 {
1793 }
1794 }
1795 }
1796 \f
1797 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1798 optionally insns that were previously combined into I3 or that will be
1799 combined into the merger of INSN and I3. The order is PRED, PRED2,
1800 INSN, SUCC, SUCC2, I3.
1802 Return 0 if the combination is not allowed for any reason.
1804 If the combination is allowed, *PDEST will be set to the single
1805 destination of INSN and *PSRC to the single source, and this function
1806 will return 1. */
1808 static int
1812 {
1817 #ifdef AUTO_INC_DEC
1818 rtx link;
1819 #endif
1824 {
1826 {
1831 }
1836 }
1840 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1841 or a PARALLEL consisting of such a SET and CLOBBERs.
1843 If INSN has CLOBBER parallel parts, ignore them for our processing.
1844 By definition, these happen during the execution of the insn. When it
1845 is merged with another insn, all bets are off. If they are, in fact,
1846 needed and aren't also supplied in I3, they may be added by
1847 recog_for_combine. Otherwise, it won't match.
1849 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1850 note.
1852 Get the source and destination of INSN. If more than one, can't
1853 combine. */
1859 {
1861 {
1865 {
1866 /* This is important to combine floating point insns
1867 for the SH4 port. */
1869 /* Combining an isolated USE doesn't make sense.
1870 We depend here on combinable_i3pat to reject them. */
1871 /* The code below this loop only verifies that the inputs of
1872 the SET in INSN do not change. We call reg_set_between_p
1873 to verify that the REG in the USE does not change between
1874 I3 and INSN.
1875 If the USE in INSN was for a pseudo register, the matching
1876 insn pattern will likely match any register; combining this
1877 with any other USE would only be safe if we knew that the
1878 used registers have identical values, or if there was
1879 something to tell them apart, e.g. different modes. For
1880 now, we forgo such complicated tests and simply disallow
1881 combining of USES of pseudo registers with any other USE. */
1884 {
1889 do
1890 {
1900 }
1902 }
1905 /* We can ignore CLOBBERs. */
1910 /* Ignore SETs whose result isn't used but not those that
1911 have side-effects. */
1917 /* If we have already found a SET, this is a second one and
1918 so we cannot combine with this insn. */
1926 /* Anything else means we can't combine. */
1928 }
1929 }
1932 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1933 so don't do anything with it. */
1936 }
1937 else
1943 /* The simplification in expand_field_assignment may call back to
1944 get_last_value, so set safe guard here. */
1950 /* Do not eliminate user-specified register if it is in an
1951 asm input because we may break the register asm usage defined
1952 in GCC manual if allow to do so.
1953 Be aware that this may cover more cases than we expect but this
1954 should be harmless. */
1959 /* Don't eliminate a store in the stack pointer. */
1961 /* Don't combine with an insn that sets a register to itself if it has
1962 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1964 /* Can't merge an ASM_OPERANDS. */
1966 /* Can't merge a function call. */
1968 /* Don't eliminate a function call argument. */
1974 /* Don't substitute into an incremented register. */
1978 /* Don't substitute into a non-local goto, this confuses CFG. */
1980 /* Make sure that DEST is not used after SUCC but before I3. */
1981 || (!all_adjacent
1982 && ((succ2
1986 /* Make sure that the value that is to be substituted for the register
1987 does not use any registers whose values alter in between. However,
1988 If the insns are adjacent, a use can't cross a set even though we
1989 think it might (this can happen for a sequence of insns each setting
1990 the same destination; last_set of that register might point to
1991 a NOTE). If INSN has a REG_EQUIV note, the register is always
1992 equivalent to the memory so the substitution is valid even if there
1993 are intervening stores. Also, don't move a volatile asm or
1994 UNSPEC_VOLATILE across any other insns. */
1995 || (! all_adjacent
2001 /* Don't combine across a CALL_INSN, because that would possibly
2002 change whether the life span of some REGs crosses calls or not,
2003 and it is a pain to update that information.
2004 Exception: if source is a constant, moving it later can't hurt.
2005 Accept that as a special case. */
2009 /* DEST must either be a REG or CC0. */
2011 {
2012 /* If register alignment is being enforced for multi-word items in all
2013 cases except for parameters, it is possible to have a register copy
2014 insn referencing a hard register that is not allowed to contain the
2015 mode being copied and which would not be valid as an operand of most
2016 insns. Eliminate this problem by not combining with such an insn.
2018 Also, on some machines we don't want to extend the life of a hard
2019 register. */
2024 /* Don't extend the life of a hard register unless it is
2025 user variable (if we have few registers) or it can't
2026 fit into the desired register (meaning something special
2027 is going on).
2028 Also avoid substituting a return register into I3, because
2029 reload can't handle a conflict with constraints of other
2030 inputs. */
2034 }
2042 {
2045 /* If the clobber represents an earlyclobber operand, we must not
2046 substitute an expression containing the clobbered register.
2047 As we do not analyze the constraint strings here, we have to
2048 make the conservative assumption. However, if the register is
2049 a fixed hard reg, the clobber cannot represent any operand;
2050 we leave it up to the machine description to either accept or
2051 reject use-and-clobber patterns. */
2057 }
2059 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2060 or not), reject, unless nothing volatile comes between it and I3 */
2063 {
2064 /* Make sure neither succ nor succ2 contains a volatile reference. */
2069 /* We'll check insns between INSN and I3 below. */
2070 }
2072 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2073 to be an explicit register variable, and was chosen for a reason. */
2079 /* If INSN contains volatile references (specifically volatile MEMs),
2080 we cannot combine across any other volatile references.
2081 Even if INSN doesn't contain volatile references, any intervening
2082 volatile insn might affect machine state. */
2085 ? volatile_refs_p
2092 /* If INSN contains an autoincrement or autodecrement, make sure that
2093 register is not used between there and I3, and not already used in
2094 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2095 Also insist that I3 not be a jump; if it were one
2096 and the incremented register were spilled, we would lose. */
2098 #ifdef AUTO_INC_DEC
2113 #endif
2115 /* Don't combine an insn that follows a CC0-setting insn.
2116 An insn that uses CC0 must not be separated from the one that sets it.
2117 We do, however, allow I2 to follow a CC0-setting insn if that insn
2118 is passed as I1; in that case it will be deleted also.
2119 We also allow combining in this case if all the insns are adjacent
2120 because that would leave the two CC0 insns adjacent as well.
2121 It would be more logical to test whether CC0 occurs inside I1 or I2,
2122 but that would be much slower, and this ought to be equivalent. */
2125 {
2130 }
2132 /* If we get here, we have passed all the tests and the combination is
2133 to be allowed. */
2139 }
2140 \f
2141 /* LOC is the location within I3 that contains its pattern or the component
2142 of a PARALLEL of the pattern. We validate that it is valid for combining.
2144 One problem is if I3 modifies its output, as opposed to replacing it
2145 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2146 doing so would produce an insn that is not equivalent to the original insns.
2148 Consider:
2150 (set (reg:DI 101) (reg:DI 100))
2151 (set (subreg:SI (reg:DI 101) 0) <foo>)
2153 This is NOT equivalent to:
2155 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2156 (set (reg:DI 101) (reg:DI 100))])
2158 Not only does this modify 100 (in which case it might still be valid
2159 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2161 We can also run into a problem if I2 sets a register that I1
2162 uses and I1 gets directly substituted into I3 (not via I2). In that
2163 case, we would be getting the wrong value of I2DEST into I3, so we
2164 must reject the combination. This case occurs when I2 and I1 both
2165 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2166 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2167 of a SET must prevent combination from occurring. The same situation
2168 can occur for I0, in which case I0_NOT_IN_SRC is set.
2170 Before doing the above check, we first try to expand a field assignment
2171 into a set of logical operations.
2173 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2174 we place a register that is both set and used within I3. If more than one
2175 such register is detected, we fail.
2177 Return 1 if the combination is valid, zero otherwise. */
2179 static int
2182 {
2186 {
2191 rtx subdest;
2198 /* Check for the case where I3 modifies its output, as discussed
2199 above. We don't want to prevent pseudos from being combined
2200 into the address of a MEM, so only prevent the combination if
2201 i1 or i2 set the same MEM. */
2211 /* This is the same test done in can_combine_p except we can't test
2212 all_adjacent; we don't have to, since this instruction will stay
2213 in place, thus we are not considering increasing the lifetime of
2214 INNER_DEST.
2216 Also, if this insn sets a function argument, combining it with
2217 something that might need a spill could clobber a previous
2218 function argument; the all_adjacent test in can_combine_p also
2219 checks this; here, we do a more specific test for this case. */
2229 /* If DEST is used in I3, it is being killed in this insn, so
2230 record that for later. We have to consider paradoxical
2231 subregs here, since they kill the whole register, but we
2232 ignore partial subregs, STRICT_LOW_PART, etc.
2233 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2234 STACK_POINTER_REGNUM, since these are always considered to be
2235 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2245 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2247 #endif
2252 {
2257 }
2258 }
2261 {
2268 }
2271 }
2272 \f
2273 /* Return 1 if X is an arithmetic expression that contains a multiplication
2274 and division. We don't count multiplications by powers of two here. */
2276 static int
2278 {
2280 {
2296 }
2297 }
2298 \f
2299 /* Determine whether INSN can be used in a combination. Return nonzero if
2300 not. This is used in try_combine to detect early some cases where we
2301 can't perform combinations. */
2303 static int
2305 {
2306 rtx set;
2309 /* If this isn't really an insn, we can't do anything.
2310 This can occur when flow deletes an insn that it has merged into an
2311 auto-increment address. */
2315 /* Never combine loads and stores involving hard regs that are likely
2316 to be spilled. The register allocator can usually handle such
2317 reg-reg moves by tying. If we allow the combiner to make
2318 substitutions of likely-spilled regs, reload might die.
2319 As an exception, we allow combinations involving fixed regs; these are
2320 not available to the register allocator so there's no risk involved. */
2341 }
2343 struct likely_spilled_retval_info
2344 {
2347 };
2349 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2350 hard registers that are known to be written to / clobbered in full. */
2351 static void
2353 {
2370 else
2373 }
2375 /* Return nonzero iff part of the return value is live during INSN, and
2376 it is likely spilled. This can happen when more than one insn is needed
2377 to copy the return value, e.g. when we consider to combine into the
2378 second copy insn for a complex value. */
2380 static int
2382 {
2384 rtx reg;
2387 /* We assume here that no machine mode needs more than
2388 32 hard registers when the value overlaps with a register
2389 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2404 /* Disregard parts of the return value that are set later. */
2413 /* Check if any of the (probably) live return value registers is
2414 likely spilled. */
2415 nregs --;
2416 do
2417 {
2423 }
2425 /* Adjust INSN after we made a change to its destination.
2427 Changing the destination can invalidate notes that say something about
2428 the results of the insn and a LOG_LINK pointing to the insn. */
2430 static void
2432 {
2433 /* For notes, be conservative and simply remove them. */
2436 /* The new insn will have a destination that was previously the destination
2437 of an insn just above it. Call distribute_links to make a LOG_LINK from
2438 the next use of that destination. */
2454 }
2456 /* Return TRUE if combine can reuse reg X in mode MODE.
2457 ADDED_SETS is nonzero if the original set is still required. */
2458 static bool
2460 {
2467 /* Allow hard registers if the new mode is legal, and occupies no more
2468 registers than the old mode. */
2473 /* Or a pseudo that is only used once. */
2476 && !added_sets
2478 }
2481 /* Check whether X, the destination of a set, refers to part of
2482 the register specified by REG. */
2484 static bool
2486 {
2487 /* Check that reg is an integer mode register. */
2498 }
2500 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2501 Note that the INSN should be deleted *after* removing dead edges, so
2502 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2503 but not for a (set (pc) (label_ref FOO)). */
2505 static void
2507 {
2515 {
2520 /* Remove barriers from the footer if there are any. */
2523 {
2526 else
2530 }
2533 }
2534 }
2536 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2537 by an arbitrary number of CLOBBERs. */
2538 static bool
2540 {
2558 }
2560 #if !HAVE_cc0
2561 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2562 CLOBBERs), can be split into individual SETs in that order, without
2563 changing semantics. */
2564 static bool
2566 {
2574 {
2583 }
2586 }
2587 #endif
2589 /* Try to combine the insns I0, I1 and I2 into I3.
2590 Here I0, I1 and I2 appear earlier than I3.
2591 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2592 I3.
2594 If we are combining more than two insns and the resulting insn is not
2595 recognized, try splitting it into two insns. If that happens, I2 and I3
2596 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2597 Otherwise, I0, I1 and I2 are pseudo-deleted.
2599 Return 0 if the combination does not work. Then nothing is changed.
2600 If we did the combination, return the insn at which combine should
2601 resume scanning.
2603 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2604 new direct jump instruction.
2606 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2607 been I3 passed to an earlier try_combine within the same basic
2608 block. */
2613 {
2614 /* New patterns for I3 and I2, respectively. */
2618 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2619 dead. */
2621 /* Total number of SETs to put into I3. */
2623 /* Nonzero if I2's or I1's body now appears in I3. */
2625 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2627 /* Contains I3 if the destination of I3 is used in its source, which means
2628 that the old life of I3 is being killed. If that usage is placed into
2629 I2 and not in I3, a REG_DEAD note must be made. */
2631 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2633 /* Copy of SET_SRC of I1 and I0, if needed. */
2635 /* Set if I2DEST was reused as a scratch register. */
2637 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2639 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2644 /* Notes that must be added to REG_NOTES in I3 and I2. */
2646 /* Notes that we substituted I3 into I2 instead of the normal case. */
2648 /* Notes that I1, I2 or I3 is a MULT operation. */
2655 rtx temp_expr;
2658 rtx new_other_notes;
2661 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2662 never be). */
2666 /* Only try four-insn combinations when there's high likelihood of
2667 success. Look for simple insns, such as loads of constants or
2668 binary operations involving a constant. */
2670 {
2680 {
2683 rtx src;
2688 {
2691 }
2693 ngood++;
2696 nshift++;
2697 }
2699 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2700 are likely manipulating its value. Ideally we'll be able to combine
2701 all four insns into a bitfield insertion of some kind.
2703 Note the source in I0 might be inside a sign/zero extension and the
2704 memory modes in I0 and I3 might be different. So extract the address
2705 from the destination of I3 and search for it in the source of I0.
2707 In the event that there's a match but the source/dest do not actually
2708 refer to the same memory, the worst that happens is we try some
2709 combinations that we wouldn't have otherwise. */
2711 /* Ensure the source of SET0 is a MEM, possibly buried inside
2712 an extension. */
2718 /* Ensure the destination of SET3 is a MEM. */
2720 /* Would it be better to extract the base address for the MEM
2721 in SET3 and look for that? I don't have cases where it matters
2722 but I could envision such cases. */
2728 }
2730 /* Exit early if one of the insns involved can't be used for
2731 combinations. */
2742 combine_attempts++;
2745 /* Reset the hard register usage information. */
2749 {
2756 else
2759 }
2761 /* If multiple insns feed into one of I2 or I3, they can be in any
2762 order. To simplify the code below, reorder them in sequence. */
2772 /* First check for one important special case that the code below will
2773 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2774 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2775 we may be able to replace that destination with the destination of I3.
2776 This occurs in the common code where we compute both a quotient and
2777 remainder into a structure, in which case we want to do the computation
2778 directly into the structure to avoid register-register copies.
2780 Note that this case handles both multiple sets in I2 and also cases
2781 where I2 has a number of CLOBBERs inside the PARALLEL.
2783 We make very conservative checks below and only try to handle the
2784 most common cases of this. For example, we only handle the case
2785 where I2 and I3 are adjacent to avoid making difficult register
2786 usage tests. */
2794 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2795 below would need to check what is inside (and reg_overlap_mentioned_p
2796 doesn't support those codes anyway). Don't allow those destinations;
2797 the resulting insn isn't likely to be recognized anyway. */
2803 {
2806 /* Make sure that the destination of I3,
2807 which we are going to substitute into one output of I2,
2808 is not used within another output of I2. We must avoid making this:
2809 (parallel [(set (mem (reg 69)) ...)
2810 (set (reg 69) ...)])
2811 which is not well-defined as to order of actions.
2812 (Besides, reload can't handle output reloads for this.)
2814 The problem can also happen if the dest of I3 is a memory ref,
2815 if another dest in I2 is an indirect memory ref. */
2823 /* Make sure this PARALLEL is not an asm. We do not allow combining
2824 that usually (see can_combine_p), so do not here either. */
2834 {
2835 combine_merges++;
2845 /* Replace the dest in I2 with our dest and make the resulting
2846 insn the new pattern for I3. Then skip to where we validate
2847 the pattern. Everything was set up above. */
2852 }
2853 }
2855 /* If I2 is setting a pseudo to a constant and I3 is setting some
2856 sub-part of it to another constant, merge them by making a new
2857 constant. */
2864 {
2870 {
2873 {
2879 }
2880 }
2881 else
2882 {
2887 }
2890 {
2891 /* If this is the low part, we're done. */
2893 ;
2894 /* Handle the case where inner is twice the size of outer. */
2898 /* Otherwise give up for now. */
2899 else
2901 }
2904 {
2908 wide_int o
2913 combine_merges++;
2920 /* Replace the source in I2 with the new constant and make the
2921 resulting insn the new pattern for I3. Then skip to where we
2922 validate the pattern. Everything was set up above. */
2928 /* The dest of I3 has been replaced with the dest of I2. */
2931 }
2932 }
2934 #if !HAVE_cc0
2935 /* If we have no I1 and I2 looks like:
2936 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2937 (set Y OP)])
2938 make up a dummy I1 that is
2939 (set Y OP)
2940 and change I2 to be
2941 (set (reg:CC X) (compare:CC Y (const_int 0)))
2943 (We can ignore any trailing CLOBBERs.)
2945 This undoes a previous combination and allows us to match a branch-and-
2946 decrement insn. */
2958 {
2959 /* We make I1 with the same INSN_UID as I2. This gives it
2960 the same DF_INSN_LUID for value tracking. Our fake I1 will
2961 never appear in the insn stream so giving it the same INSN_UID
2962 as I2 will not cause a problem. */
2975 }
2977 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2978 make those two SETs separate I1 and I2 insns, and make an I0 that is
2979 the original I1. */
2985 {
2986 /* If there is no I1, there is no I0 either. */
2989 /* We make I1 with the same INSN_UID as I2. This gives it
2990 the same DF_INSN_LUID for value tracking. Our fake I1 will
2991 never appear in the insn stream so giving it the same INSN_UID
2992 as I2 will not cause a problem. */
3000 }
3001 #endif
3003 /* Verify that I2 and I1 are valid for combining. */
3009 {
3012 }
3014 /* Record whether I2DEST is used in I2SRC and similarly for the other
3015 cases. Knowing this will help in register status updating below. */
3026 /* For the earlier insns, determine which of the subsequent ones they
3027 feed. */
3034 /* Ensure that I3's pattern can be the destination of combines. */
3040 {
3043 }
3045 /* See if any of the insns is a MULT operation. Unless one is, we will
3046 reject a combination that is, since it must be slower. Be conservative
3047 here. */
3055 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3056 We used to do this EXCEPT in one case: I3 has a post-inc in an
3057 output operand. However, that exception can give rise to insns like
3058 mov r3,(r3)+
3059 which is a famous insn on the PDP-11 where the value of r3 used as the
3060 source was model-dependent. Avoid this sort of thing. */
3062 #if 0
3068 /* It's not the exception. */
3069 #endif
3070 #ifdef AUTO_INC_DEC
3071 {
3072 rtx link;
3078 {
3081 }
3082 }
3083 #endif
3085 /* See if the SETs in I1 or I2 need to be kept around in the merged
3086 instruction: whenever the value set there is still needed past I3.
3087 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3089 For the SET in I1, we have two cases: if I1 and I2 independently feed
3090 into I3, the set in I1 needs to be kept around unless I1DEST dies
3091 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3092 in I1 needs to be kept around unless I1DEST dies or is set in either
3093 I2 or I3. The same considerations apply to I0. */
3100 else
3108 else
3111 /* We are about to copy insns for the case where they need to be kept
3112 around. Check that they can be copied in the merged instruction. */
3118 {
3121 }
3123 /* If the set in I2 needs to be kept around, we must make a copy of
3124 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3125 PATTERN (I2), we are only substituting for the original I1DEST, not into
3126 an already-substituted copy. This also prevents making self-referential
3127 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3128 I2DEST. */
3131 {
3134 else
3136 }
3139 {
3142 else
3144 }
3147 {
3150 else
3152 }
3154 combine_merges++;
3156 /* Substitute in the latest insn for the regs set by the earlier ones. */
3162 /* Many machines that don't use CC0 have insns that can both perform an
3163 arithmetic operation and set the condition code. These operations will
3164 be represented as a PARALLEL with the first element of the vector
3165 being a COMPARE of an arithmetic operation with the constant zero.
3166 The second element of the vector will set some pseudo to the result
3167 of the same arithmetic operation. If we simplify the COMPARE, we won't
3168 match such a pattern and so will generate an extra insn. Here we test
3169 for this case, where both the comparison and the operation result are
3170 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3171 I2SRC. Later we will make the PARALLEL that contains I2. */
3177 {
3178 rtx newpat_dest;
3192 {
3197 }
3199 /* Do the rest only if op1 is const0_rtx, which may be the
3200 result of simplification. */
3202 {
3203 /* If a single use of the CC is found, prepare to modify it
3204 when SELECT_CC_MODE returns a new CC-class mode, or when
3205 the above simplify_compare_const() returned a new comparison
3206 operator. undobuf.other_insn is assigned the CC use insn
3207 when modifying it. */
3209 {
3210 #ifdef SELECT_CC_MODE
3211 machine_mode new_mode
3216 {
3221 else
3222 {
3225 }
3226 }
3227 #endif
3228 /* Cases for modifying the CC-using comparison. */
3230 /* ??? Do we need to verify the zero rtx? */
3232 {
3233 /* Replace cc_use_loc with entire new RTX. */
3238 }
3240 {
3241 /* Just replace the CC reg with a new mode. */
3244 }
3245 }
3247 /* Now we modify the current newpat:
3248 First, SET_DEST(newpat) is updated if the CC mode has been
3249 altered. For targets without SELECT_CC_MODE, this should be
3250 optimized away. */
3253 /* This is always done to propagate i2src into newpat. */
3256 /* Create new version of i2pat if needed; the below PARALLEL
3257 creation needs this to work correctly. */
3261 }
3262 }
3265 {
3266 /* It is possible that the source of I2 or I1 may be performing
3267 an unneeded operation, such as a ZERO_EXTEND of something
3268 that is known to have the high part zero. Handle that case
3269 by letting subst look at the inner insns.
3271 Another way to do this would be to have a function that tries
3272 to simplify a single insn instead of merging two or more
3273 insns. We don't do this because of the potential of infinite
3274 loops and because of the potential extra memory required.
3275 However, doing it the way we are is a bit of a kludge and
3276 doesn't catch all cases.
3278 But only do this if -fexpensive-optimizations since it slows
3279 things down and doesn't usually win.
3281 This is not done in the COMPARE case above because the
3282 unmodified I2PAT is used in the PARALLEL and so a pattern
3283 with a modified I2SRC would not match. */
3286 {
3287 /* Pass pc_rtx so no substitutions are done, just
3288 simplifications. */
3290 {
3293 }
3297 }
3302 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3303 copy of I2SRC each time we substitute it, in order to avoid creating
3304 self-referential RTL when we will be substituting I1SRC for I1DEST
3305 later. Likewise if I0 feeds into I2, either directly or indirectly
3306 through I1, and I0DEST is in I0SRC. */
3313 /* Record whether I2's body now appears within I3's body. */
3315 }
3317 /* If we already got a failure, don't try to do more. Otherwise, try to
3318 substitute I1 if we have it. */
3321 {
3322 /* Check that an autoincrement side-effect on I1 has not been lost.
3323 This happens if I1DEST is mentioned in I2 and dies there, and
3324 has disappeared from the new pattern. */
3326 && i1_feeds_i2_n
3329 /* Before we can do this substitution, we must redo the test done
3330 above (see detailed comments there) that ensures I1DEST isn't
3331 mentioned in any SETs in NEWPAT that are field assignments. */
3334 {
3337 }
3342 /* If the following substitution will modify I1SRC, make a copy of it
3343 for the case where it is substituted for I1DEST in I2PAT later. */
3347 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3348 copy of I1SRC each time we substitute it, in order to avoid creating
3349 self-referential RTL when we will be substituting I0SRC for I0DEST
3350 later. */
3355 /* Record whether I1's body now appears within I3's body. */
3357 }
3359 /* Likewise for I0 if we have it. */
3362 {
3369 {
3372 }
3374 /* If the following substitution will modify I0SRC, make a copy of it
3375 for the case where it is substituted for I0DEST in I1PAT later. */
3378 /* And a copy for I0DEST in I2PAT substitution. */
3387 }
3389 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3390 to count all the ways that I2SRC and I1SRC can be used. */
3401 /* Fail if we tried to make a new register. */
3403 /* Fail if we couldn't do something and have a CLOBBER. */
3405 /* Fail if this new pattern is a MULT and we didn't have one before
3406 at the outer level. */
3409 {
3412 }
3414 /* If the actions of the earlier insns must be kept
3415 in addition to substituting them into the latest one,
3416 we must make a new PARALLEL for the latest insn
3417 to hold additional the SETs. */
3420 {
3422 combine_extras++;
3425 {
3431 }
3432 else
3433 {
3438 }
3444 {
3450 }
3452 {
3461 }
3462 }
3464 validate_replacement:
3466 /* Note which hard regs this insn has as inputs. */
3469 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3470 consider splitting this pattern, we might need these clobbers. */
3473 {
3479 }
3481 /* We have recognized nothing yet. */
3484 /* See if this is a PARALLEL of two SETs where one SET's destination is
3485 a register that is unused and this isn't marked as an instruction that
3486 might trap in an EH region. In that case, we just need the other SET.
3487 We prefer this over the PARALLEL.
3489 This can occur when simplifying a divmod insn. We *must* test for this
3490 case here because the code below that splits two independent SETs doesn't
3491 handle this case correctly when it updates the register status.
3493 It's pointless doing this if we originally had two sets, one from
3494 i3, and one from i2. Combining then splitting the parallel results
3495 in the original i2 again plus an invalid insn (which we delete).
3496 The net effect is only to move instructions around, which makes
3497 debug info less accurate. */
3502 {
3513 {
3516 }
3525 {
3531 }
3535 }
3537 /* Is the result of combination a valid instruction? */
3541 /* If we were combining three insns and the result is a simple SET
3542 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3543 insns. There are two ways to do this. It can be split using a
3544 machine-specific method (like when you have an addition of a large
3545 constant) or by combine in the function find_split_point. */
3549 {
3553 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3554 use I2DEST as a scratch register will help. In the latter case,
3555 convert I2DEST to the mode of the source of NEWPAT if we can. */
3559 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3560 inputs of NEWPAT. */
3562 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3563 possible to try that as a scratch reg. This would require adding
3564 more code to make it work though. */
3567 {
3570 /* First try to split using the original register as a
3571 scratch register. */
3575 i2dest)));
3578 /* If that didn't work, try changing the mode of I2DEST if
3579 we can. */
3584 {
3586 rtx ni2dest;
3590 else
3591 {
3594 }
3596 parallel = (gen_rtx_PARALLEL
3600 ni2dest))));
3605 {
3613 }
3614 }
3617 }
3619 /* If recog_for_combine has discarded clobbers, try to use them
3620 again for the split. */
3622 {
3625 }
3628 {
3633 }
3637 {
3647 /* If I2 or I3 has multiple SETs, we won't know how to track
3648 register status, so don't use these insns. If I2's destination
3649 is used between I2 and I3, we also can't use these insns. */
3659 /* It is possible that both insns now set the destination of I3.
3660 If so, we must show an extra use of it. */
3663 {
3682 }
3683 }
3685 /* If we can split it and use I2DEST, go ahead and see if that
3686 helps things be recognized. Verify that none of the registers
3687 are set between I2 and I3. */
3691 /* We need I2DEST in the proper mode. If it is a hard register
3692 or the only use of a pseudo, we can change its mode.
3693 Make sure we don't change a hard register to have a mode that
3694 isn't valid for it, or change the number of registers. */
3701 /* We can't overwrite I2DEST if its value is still used by
3702 NEWPAT. */
3704 {
3713 /* *SPLIT may be part of I2SRC, so make sure we have the
3714 original expression around for later debug processing.
3715 We should not need I2SRC any more in other cases. */
3718 else
3721 /* Get NEWDEST as a register in the proper mode. We have already
3722 validated that we can do this. */
3724 {
3727 else
3728 {
3731 }
3732 }
3734 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3735 an ASHIFT. This can occur if it was inside a PLUS and hence
3736 appeared to be a memory address. This is a kludge. */
3741 {
3744 /* Update split_code because we may not have a multiply
3745 anymore. */
3747 }
3749 #ifdef INSN_SCHEDULING
3750 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3751 be written as a ZERO_EXTEND. */
3753 {
3754 #ifdef LOAD_EXTEND_OP
3755 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3756 what it really is. */
3761 else
3762 #endif
3765 }
3766 #endif
3768 /* Attempt to split binary operators using arithmetic identities. */
3772 {
3779 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3781 {
3786 }
3787 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3794 {
3800 /* Split both "((X op Y) op X) op Y" and
3801 "((X op Y) op Y) op X" as "T op T" where T is
3802 "X op Y". */
3805 {
3810 }
3811 /* Split "((X op X) op Y) op Y)" as "T op T" where
3812 T is "X op Y". */
3814 {
3820 }
3821 }
3822 }
3825 {
3828 }
3832 /* recog_for_combine might have added CLOBBERs to newi2pat.
3833 Make sure NEWPAT does not depend on the clobbered regs. */
3837 {
3840 {
3843 }
3844 }
3846 /* If the split point was a MULT and we didn't have one before,
3847 don't use one now. */
3850 }
3851 }
3853 /* Check for a case where we loaded from memory in a narrow mode and
3854 then sign extended it, but we need both registers. In that case,
3855 we have a PARALLEL with both loads from the same memory location.
3856 We can split this into a load from memory followed by a register-register
3857 copy. This saves at least one insn, more if register allocation can
3858 eliminate the copy.
3860 We cannot do this if the destination of the first assignment is a
3861 condition code register or cc0. We eliminate this case by making sure
3862 the SET_DEST and SET_SRC have the same mode.
3864 We cannot do this if the destination of the second assignment is
3865 a register that we have already assumed is zero-extended. Similarly
3866 for a SUBREG of such a register. */
3901 {
3902 rtx ni2dest;
3916 }
3918 /* Similarly, check for a case where we have a PARALLEL of two independent
3919 SETs but we started with three insns. In this case, we can do the sets
3920 as two separate insns. This case occurs when some SET allows two
3921 other insns to combine, but the destination of that SET is still live.
3923 Also do this if we started with two insns and (at least) one of the
3924 resulting sets is a noop; this noop will be deleted later. */
3943 {
3947 /* Normally, it doesn't matter which of the two is done first,
3948 but the one that references cc0 can't be the second, and
3949 one which uses any regs/memory set in between i2 and i3 can't
3950 be first. The PARALLEL might also have been pre-existing in i3,
3951 so we need to make sure that we won't wrongly hoist a SET to i2
3952 that would conflict with a death note present in there. */
3960 /* If I3 is a jump, ensure that set0 is a jump so that
3961 we do not create invalid RTL. */
3963 )
3964 {
3967 }
3975 /* If I3 is a jump, ensure that set1 is a jump so that
3976 we do not create invalid RTL. */
3978 )
3979 {
3982 }
3983 else
3984 {
3987 }
3992 {
3993 /* recog_for_combine might have added CLOBBERs to newi2pat.
3994 Make sure NEWPAT does not depend on the clobbered regs. */
3996 {
3999 {
4002 {
4005 }
4006 }
4007 }
4010 }
4011 }
4013 /* If it still isn't recognized, fail and change things back the way they
4014 were. */
4016 /* Is the result a reasonable ASM_OPERANDS? */
4018 {
4021 }
4023 /* If we had to change another insn, make sure it is valid also. */
4025 {
4033 {
4036 }
4037 }
4039 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4040 they are adjacent to each other or not. */
4042 {
4046 {
4049 }
4050 }
4052 /* Only allow this combination if insn_rtx_costs reports that the
4053 replacement instructions are cheaper than the originals. */
4055 {
4058 }
4061 {
4066 {
4071 /* Temporarily revert mode back. */
4075 {
4076 /* If we used i2dest as a scratch register with a
4077 different mode, substitute it for the original
4078 i2src while its original mode is temporarily
4079 restored, and then clear i2scratch so that we don't
4080 do it again later. */
4082 this_basic_block);
4084 /* Put back the new mode. */
4086 }
4087 else
4088 {
4093 {
4096 }
4097 else
4098 {
4105 }
4107 /* We're dealing with a reg that changed mode but not
4108 meaning, so we want to turn it into a subreg for
4109 the new mode. However, because of REG sharing and
4110 because its mode had already changed, we have to do
4111 it in two steps. First, replace any debug uses of
4112 reg, with its original mode temporarily restored,
4113 with this copy we have created; then, replace the
4114 copy with the SUBREG of the original shared reg,
4115 once again changed to the new mode. */
4117 this_basic_block);
4121 this_basic_block);
4122 }
4123 }
4124 }
4126 /* If we will be able to accept this, we have made a
4127 change to the destination of I3. This requires us to
4128 do a few adjustments. */
4131 {
4134 }
4136 /* We now know that we can do this combination. Merge the insns and
4137 update the status of registers and LOG_LINKS. */
4140 {
4145 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4146 ensure that they are still valid. Then add any non-duplicate
4147 notes added by recog_for_combine. */
4149 {
4159 }
4163 NULL_RTX);
4164 }
4167 {
4170 rtx ni2dest;
4172 /* I3 now uses what used to be its destination and which is now
4173 I2's destination. This requires us to do a few adjustments. */
4177 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4178 so we still will.
4180 However, some later insn might be using I2's dest and have
4181 a LOG_LINK pointing at I3. We must remove this link.
4182 The simplest way to remove the link is to point it at I1,
4183 which we know will be a NOTE. */
4185 /* newi2pat is usually a SET here; however, recog_for_combine might
4186 have added some clobbers. */
4189 else
4196 {
4198 {
4204 }
4205 }
4206 }
4208 {
4213 /* Compute which registers we expect to eliminate. newi2pat may be setting
4214 either i3dest or i2dest, so we must check it. */
4217 || !i2dest_killed
4219 /* For i1, we need to compute both local elimination and global
4220 elimination information with respect to newi2pat because i1dest
4221 may be the same as i3dest, in which case newi2pat may be setting
4222 i1dest. Global information is used when distributing REG_DEAD
4223 note for i2 and i3, in which case it does matter if newi2pat sets
4224 i1dest or not.
4226 Local information is used when distributing REG_DEAD note for i1,
4227 in which case it doesn't matter if newi2pat sets i1dest or not.
4228 See PR62151, if we have four insns combination:
4229 i0: r0 <- i0src
4230 i1: r1 <- i1src (using r0)
4231 REG_DEAD (r0)
4232 i2: r0 <- i2src (using r1)
4233 i3: r3 <- i3src (using r0)
4234 ix: using r0
4235 From i1's point of view, r0 is eliminated, no matter if it is set
4236 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4237 should be discarded.
4239 Note local information only affects cases in forms like "I1->I2->I3",
4240 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4241 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4242 i0dest anyway. */
4244 || !i1dest_killed
4249 /* Same case as i1. */
4256 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4257 clear them. */
4265 /* Ensure that we do not have something that should not be shared but
4266 occurs multiple times in the new insns. Check this by first
4267 resetting all the `used' flags and then copying anything is shared. */
4291 {
4298 {
4299 /* I2SRC must still be meaningful at this point. Some splitting
4300 operations can invalidate I2SRC, but those operations do not
4301 apply to calls. */
4304 }
4312 }
4317 /* We had one special case above where I2 had more than one set and
4318 we replaced a destination of one of those sets with the destination
4319 of I3. In that case, we have to update LOG_LINKS of insns later
4320 in this basic block. Note that this (expensive) case is rare.
4322 Also, in this case, we must pretend that all REG_NOTEs for I2
4323 actually came from I3, so that REG_UNUSED notes from I2 will be
4324 properly handled. */
4327 {
4336 temp_insn
4346 {
4351 }
4352 else
4355 }
4363 {
4366 this_basic_block);
4369 }
4370 else
4371 {
4374 this_basic_block);
4376 }
4379 {
4384 this_basic_block);
4386 }
4389 {
4394 this_basic_block);
4396 }
4398 /* Get death notes for everything that is now used in either I3 or
4399 I2 and used to die in a previous insn. If we built two new
4400 patterns, move from I1 to I2 then I2 to I3 so that we get the
4401 proper movement on registers that I2 modifies. */
4407 else
4413 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4430 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4431 know these are REG_UNUSED and want them to go to the desired insn,
4432 so we always pass it as i3. */
4436 NULL_RTX);
4440 NULL_RTX);
4442 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4443 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4444 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4445 in that case, it might delete I2. Similarly for I2 and I1.
4446 Show an additional death due to the REG_DEAD note we make here. If
4447 we discard it in distribute_notes, we will decrement it again. */
4450 {
4455 else
4458 }
4461 {
4466 else
4469 }
4472 {
4477 else
4480 }
4483 {
4488 else
4491 }
4499 {
4504 /* The insn that used to set this register doesn't exist, and
4505 this life of the register may not exist either. See if one of
4506 I3's links points to an insn that sets I2DEST. If it does,
4507 that is now the last known value for I2DEST. If we don't update
4508 this and I2 set the register to a value that depended on its old
4509 contents, we will get confused. If this insn is used, thing
4510 will be set correctly in combine_instructions. */
4518 /* If the reg formerly set in I2 died only once and that was in I3,
4519 zero its use count so it won't make `reload' do any work. */
4522 && ! i2dest_in_i2src
4525 }
4528 {
4541 && ! i1dest_in_i1src
4544 }
4547 {
4560 && ! i0dest_in_i0src
4563 }
4565 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4566 been made to this insn. The order is important, because newi2pat
4567 can affect nonzero_bits of newpat. */
4571 }
4574 {
4576 {
4579 }
4581 }
4584 {
4586 {
4589 }
4591 }
4594 {
4596 {
4599 }
4601 }
4604 {
4606 {
4609 }
4611 }
4614 {
4616 {
4619 }
4621 }
4623 /* Set new_direct_jump_p if a new return or simple jump instruction
4624 has been created. Adjust the CFG accordingly. */
4626 {
4630 }
4635 {
4638 }
4640 /* A noop might also need cleaning up of CFG, if it comes from the
4641 simplification of a jump. */
4646 {
4649 }
4656 {
4659 }
4661 combine_successes++;
4668 else
4670 }
4671 \f
4672 /* Get a marker for undoing to the current state. */
4676 {
4678 }
4680 /* Undo the modifications up to the marker. */
4682 static void
4684 {
4688 {
4693 {
4708 }
4712 }
4715 }
4717 /* Undo all the modifications recorded in undobuf. */
4719 static void
4721 {
4723 }
4725 /* We've committed to accepting the changes we made. Move all
4726 of the undos to the free list. */
4728 static void
4730 {
4734 {
4738 }
4740 }
4741 \f
4742 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4743 where we have an arithmetic expression and return that point. LOC will
4744 be inside INSN.
4746 try_combine will call this function to see if an insn can be split into
4747 two insns. */
4751 {
4760 /* First special-case some codes. */
4762 {
4764 #ifdef INSN_SCHEDULING
4765 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4766 point. */
4769 #endif
4773 #ifdef HAVE_lo_sum
4774 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4775 using LO_SUM and HIGH. */
4778 {
4786 }
4787 #endif
4789 /* If we have a PLUS whose second operand is a constant and the
4790 address is not valid, perhaps will can split it up using
4791 the machine-specific way to split large constants. We use
4792 the first pseudo-reg (one of the virtual regs) as a placeholder;
4793 it will not remain in the result. */
4798 {
4801 subst_insn);
4803 /* This should have produced two insns, each of which sets our
4804 placeholder. If the source of the second is a valid address,
4805 we can make put both sources together and make a split point
4806 in the middle. */
4819 && memory_address_addr_space_p
4822 {
4826 /* Replace the placeholder in SRC2 with SRC1. If we can
4827 find where in SRC2 it was placed, that can become our
4828 split point and we can replace this address with SRC2.
4829 Just try two obvious places. */
4840 {
4843 }
4844 }
4846 /* If that didn't work, perhaps the first operand is complex and
4847 needs to be computed separately, so make a split point there.
4848 This will occur on machines that just support REG + CONST
4849 and have a constant moved through some previous computation. */
4855 }
4857 /* If we have a PLUS whose first operand is complex, try computing it
4858 separately by making a split there. */
4869 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4870 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4871 we need to put the operand into a register. So split at that
4872 point. */
4882 /* See if we can split SET_SRC as it stands. */
4887 /* See if we can split SET_DEST as it stands. */
4892 /* See if this is a bitfield assignment with everything constant. If
4893 so, this is an IOR of an AND, so split it into that. */
4903 {
4909 unsigned HOST_WIDE_INT mask
4911 rtx or_mask;
4920 else
4921 {
4927 or_mask));
4928 }
4935 }
4937 /* Otherwise, see if this is an operation that we can split into two.
4938 If so, try to split that. */
4942 {
4944 /* If we are AND'ing with a large constant that is only a single
4945 bit and the result is only being used in a context where we
4946 need to know if it is zero or nonzero, replace it with a bit
4947 extraction. This will avoid the large constant, which might
4948 have taken more than one insn to make. If the constant were
4949 not a valid argument to the AND but took only one insn to make,
4950 this is no worse, but if it took more than one insn, it will
4951 be better. */
4961 {
4966 {
4969 }
4970 }
4974 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4975 is known to be on, this can be converted into a NEG of a shift. */
4981 {
4993 }
4999 /* We can't optimize if either mode is a partial integer
5000 mode as we don't know how many bits are significant
5001 in those modes. */
5015 {
5023 }
5028 }
5032 {
5035 /* For unsigned, we have a choice of a shift followed by an
5036 AND or two shifts. Use two shifts for field sizes where the
5037 constant might be too large. We assume here that we can
5038 always at least get 8-bit constants in an AND insn, which is
5039 true for every current RISC. */
5042 {
5043 unsigned HOST_WIDE_INT mask
5047 gen_rtx_LSHIFTRT
5055 }
5056 else
5057 {
5059 gen_rtx_fmt_ee
5070 }
5071 }
5073 /* See if this is a simple operation with a constant as the second
5074 operand. It might be that this constant is out of range and hence
5075 could be used as a split point. */
5083 /* Finally, see if this is a simple operation with its first operand
5084 not in a register. The operation might require this operand in a
5085 register, so return it as a split point. We can always do this
5086 because if the first operand were another operation, we would have
5087 already found it as a split point. */
5096 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5097 it is better to write this as (not (ior A B)) so we can split it.
5098 Similarly for IOR. */
5100 {
5108 }
5110 /* Many RISC machines have a large set of logical insns. If the
5111 second operand is a NOT, put it first so we will try to split the
5112 other operand first. */
5114 {
5118 }
5123 /* Canonicalization can produce (minus A (mult B C)), where C is a
5124 constant. It may be better to try splitting (plus (mult B -C) A)
5125 instead if this isn't a multiply by a power of two. */
5129 {
5137 mode)),
5140 }
5142 /* Split at a multiply-accumulate instruction. However if this is
5143 the SET_SRC, we likely do not have such an instruction and it's
5144 worthless to try this split. */
5152 }
5154 /* Otherwise, select our actions depending on our rtx class. */
5156 {
5162 /* ... fall through ... */
5170 /* ... fall through ... */
5172 /* Some machines have (and (shift ...) ...) insns. If X is not
5173 an AND, but XEXP (X, 0) is, use it as our split point. */
5183 /* Otherwise, we don't have a split point. */
5185 }
5186 }
5187 \f
5188 /* Throughout X, replace FROM with TO, and return the result.
5189 The result is TO if X is FROM;
5190 otherwise the result is X, but its contents may have been modified.
5191 If they were modified, a record was made in undobuf so that
5192 undo_all will (among other things) return X to its original state.
5194 If the number of changes necessary is too much to record to undo,
5195 the excess changes are not made, so the result is invalid.
5196 The changes already made can still be undone.
5197 undobuf.num_undo is incremented for such changes, so by testing that
5198 the caller can tell whether the result is valid.
5200 `n_occurrences' is incremented each time FROM is replaced.
5202 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5204 IN_COND is nonzero if we are at the top level of a condition.
5206 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5207 by copying if `n_occurrences' is nonzero. */
5209 static rtx
5211 {
5216 rtx new_rtx;
5218 /* Two expressions are equal if they are identical copies of a shared
5219 RTX or if they are both registers with the same register number
5220 and mode. */
5222 #define COMBINE_RTX_EQUAL_P(X,Y) \
5223 ((X) == (Y) \
5224 || (REG_P (X) && REG_P (Y) \
5225 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5227 /* Do not substitute into clobbers of regs -- this will never result in
5228 valid RTL. */
5233 {
5234 n_occurrences++;
5236 }
5238 /* If X and FROM are the same register but different modes, they
5239 will not have been seen as equal above. However, the log links code
5240 will make a LOG_LINKS entry for that case. If we do nothing, we
5241 will try to rerecognize our original insn and, when it succeeds,
5242 we will delete the feeding insn, which is incorrect.
5244 So force this insn not to match in this (rare) case. */
5249 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5250 of which may contain things that can be combined. */
5254 /* It is possible to have a subexpression appear twice in the insn.
5255 Suppose that FROM is a register that appears within TO.
5256 Then, after that subexpression has been scanned once by `subst',
5257 the second time it is scanned, TO may be found. If we were
5258 to scan TO here, we would find FROM within it and create a
5259 self-referent rtl structure which is completely wrong. */
5263 /* Parallel asm_operands need special attention because all of the
5264 inputs are shared across the arms. Furthermore, unsharing the
5265 rtl results in recognition failures. Failure to handle this case
5266 specially can result in circular rtl.
5268 Solve this by doing a normal pass across the first entry of the
5269 parallel, and only processing the SET_DESTs of the subsequent
5270 entries. Ug. */
5275 {
5278 /* If this substitution failed, this whole thing fails. */
5286 {
5292 {
5295 /* If this substitution failed, this whole thing fails. */
5301 }
5302 }
5303 }
5304 else
5305 {
5309 /* We don't need to process a SET_DEST that is a register, CC0,
5310 or PC, so set up to skip this common case. All other cases
5311 where we want to suppress replacing something inside a
5312 SET_SRC are handled via the IN_DEST operand. */
5319 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5320 constant. */
5325 {
5327 {
5330 {
5332 {
5335 n_occurrences++;
5336 }
5337 else
5338 {
5340 unique_copy);
5342 /* If this substitution failed, this whole thing
5343 fails. */
5347 }
5350 }
5351 }
5353 {
5354 /* If this is a register being set, ignore it. */
5361 ;
5364 {
5365 /* In general, don't install a subreg involving two
5366 modes not tieable. It can worsen register
5367 allocation, and can even make invalid reload
5368 insns, since the reg inside may need to be copied
5369 from in the outside mode, and that may be invalid
5370 if it is an fp reg copied in integer mode.
5372 We allow two exceptions to this: It is valid if
5373 it is inside another SUBREG and the mode of that
5374 SUBREG and the mode of the inside of TO is
5375 tieable and it is valid if X is a SET that copies
5376 FROM to CC0. */
5384 #if HAVE_cc0
5386 #endif
5387 )
5399 n_occurrences++;
5400 }
5401 else
5402 /* If we are in a SET_DEST, suppress most cases unless we
5403 have gone inside a MEM, in which case we want to
5404 simplify the address. We assume here that things that
5405 are actually part of the destination have their inner
5406 parts in the first expression. This is true for SUBREG,
5407 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5408 things aside from REG and MEM that should appear in a
5409 SET_DEST. */
5411 (((in_dest
5417 unique_copy);
5419 /* If we found that we will have to reject this combination,
5420 indicate that by returning the CLOBBER ourselves, rather than
5421 an expression containing it. This will speed things up as
5422 well as prevent accidents where two CLOBBERs are considered
5423 to be equal, thus producing an incorrect simplification. */
5429 {
5437 }
5440 {
5444 }
5445 else
5447 }
5448 }
5449 }
5451 /* Check if we are loading something from the constant pool via float
5452 extension; in this case we would undo compress_float_constant
5453 optimization and degenerate constant load to an immediate value. */
5457 {
5461 }
5463 /* Try to simplify X. If the simplification changed the code, it is likely
5464 that further simplification will help, so loop, but limit the number
5465 of repetitions that will be performed. */
5468 {
5469 /* If X is sufficiently simple, don't bother trying to do anything
5470 with it. */
5479 /* We no longer know the original mode of operand 0 since we
5480 have changed the form of X) */
5482 }
5485 }
5486 \f
5487 /* Simplify X, a piece of RTL. We just operate on the expression at the
5488 outer level; call `subst' to simplify recursively. Return the new
5489 expression.
5491 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5492 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5493 of a condition. */
5495 static rtx
5498 {
5501 rtx temp;
5504 /* If this is a commutative operation, put a constant last and a complex
5505 expression first. We don't need to do this for comparisons here. */
5508 {
5512 }
5514 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5515 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5516 things. Check for cases where both arms are testing the same
5517 condition.
5519 Don't do anything if all operands are very simple. */
5532 {
5537 /* If everything is a comparison, what we have is highly unlikely
5538 to be simpler, so don't use it. */
5541 {
5548 /* Simplify the alternative arms; this may collapse the true and
5549 false arms to store-flag values. Be careful to use copy_rtx
5550 here since true_rtx or false_rtx might share RTL with x as a
5551 result of the if_then_else_cond call above. */
5555 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5556 is unlikely to be simpler. */
5559 {
5562 /* Restarting if we generate a store-flag expression will cause
5563 us to loop. Just drop through in this case. */
5565 /* If the result values are STORE_FLAG_VALUE and zero, we can
5566 just make the comparison operation. */
5577 /* Likewise, we can make the negate of a comparison operation
5578 if the result values are - STORE_FLAG_VALUE and zero. */
5586 mode);
5597 mode);
5598 else
5601 mode,
5602 VOIDmode,
5603 cond,
5604 cop1),
5609 }
5610 }
5611 }
5613 /* Try to fold this expression in case we have constants that weren't
5614 present before. */
5617 {
5625 {
5628 {
5632 }
5635 }
5648 }
5651 {
5656 }
5658 /* First see if we can apply the inverse distributive law. */
5661 {
5665 }
5667 /* If CODE is an associative operation not otherwise handled, see if we
5668 can associate some operands. This can win if they are constants or
5669 if they are logically related (i.e. (a & b) & a). */
5675 {
5677 {
5681 rtx inner;
5683 /* Make sure we pass the constant operand if any as the second
5684 one if this is a commutative operation. */
5686 {
5690 }
5696 /* For commutative operations, try the other pair if that one
5697 didn't simplify. */
5699 {
5704 }
5708 }
5709 }
5711 /* A little bit of algebraic simplification here. */
5713 {
5715 /* Ensure that our address has any ASHIFTs converted to MULT in case
5716 address-recognizing predicates are called later. */
5725 /* See if this can be moved to simplify_subreg. */
5728 /* Don't call gen_lowpart if the inner mode
5729 is VOIDmode and we cannot simplify it, as SUBREG without
5730 inner mode is invalid. */
5737 {
5738 rtx temp;
5744 /* If op is known to have all lower bits zero, the result is zero. */
5754 }
5756 /* Don't change the mode of the MEM if that would change the meaning
5757 of the address. */
5764 /* Note that we cannot do any narrowing for non-constants since
5765 we might have been counting on using the fact that some bits were
5766 zero. We now do this in the SET. */
5773 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5774 replaced by (lshiftrt X C). This will convert
5775 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5783 /* If X has only a single bit that might be nonzero, say, bit I, convert
5784 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5785 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5786 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5787 or a SUBREG of one since we'd be making the expression more
5788 complex if it was just a register. */
5794 {
5795 rtx temp1 = simplify_shift_const
5801 /* If all we did was surround TEMP with the two shifts, we
5802 haven't improved anything, so don't use it. Otherwise,
5803 we are better off with TEMP1. */
5808 }
5812 /* We can't handle truncation to a partial integer mode here
5813 because we don't know the real bitsize of the partial
5814 integer mode. */
5823 /* We can truncate a constant value and return it. */
5827 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5828 whose value is a comparison can be replaced with a subreg if
5829 STORE_FLAG_VALUE permits. */
5838 /* (const (const X)) can become (const X). Do it this way rather than
5839 returning the inner CONST since CONST can be shared with a
5840 REG_EQUAL note. */
5845 #ifdef HAVE_lo_sum
5847 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5848 can add in an offset. find_split_point will split this address up
5849 again if it doesn't match. */
5854 #endif
5857 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5858 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5859 bit-field and can be replaced by either a sign_extend or a
5860 sign_extract. The `and' may be a zero_extend and the two
5861 <c>, -<c> constants may be reversed. */
5876 return simplify_shift_const
5883 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5884 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5885 the bitsize of the mode - 1. This allows simplification of
5886 "a = (b & 8) == 0;" */
5898 /* If we are adding two things that have no bits in common, convert
5899 the addition into an IOR. This will often be further simplified,
5900 for example in cases like ((a & 1) + (a & 2)), which can
5901 become a & 3. */
5906 {
5907 /* Try to simplify the expression further. */
5911 /* If we could, great. If not, do not go ahead with the IOR
5912 replacement, since PLUS appears in many special purpose
5913 address arithmetic instructions. */
5921 }
5925 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5926 (and <foo> (const_int pow2-1)) */
5936 /* If we have (mult (plus A B) C), apply the distributive law and then
5937 the inverse distributive law to see if things simplify. This
5938 occurs mostly in addresses, often when unrolling loops. */
5941 {
5945 }
5947 /* Try simplify a*(b/c) as (a*b)/c. */
5950 {
5956 }
5960 /* If this is a divide by a power of two, treat it as a shift if
5961 its first operand is a shift. */
5979 /* If the first operand is a condition code, we can't do anything
5980 with it. */
5984 {
5992 /* Simplify our comparison, if possible. */
5995 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5996 if only the low-order bit is possibly nonzero in X (such as when
5997 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5998 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5999 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6000 (plus X 1).
6002 Remove any ZERO_EXTRACT we made when thinking this was a
6003 comparison. It may now be simpler to use, e.g., an AND. If a
6004 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6005 the call to make_compound_operation in the SET case.
6007 Don't apply these optimizations if the caller would
6008 prefer a comparison rather than a value.
6009 E.g., for the condition in an IF_THEN_ELSE most targets need
6010 an explicit comparison. */
6013 ;
6029 {
6033 mode);
6034 }
6041 {
6045 const1_rtx);
6046 }
6054 {
6057 }
6059 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6060 those above. */
6062 ;
6078 {
6082 mode);
6083 }
6091 {
6095 mode);
6096 }
6098 /* If X is 0/1, (eq X 0) is X-1. */
6104 {
6107 }
6109 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6110 one bit that might be nonzero, we can convert (ne x 0) to
6111 (ashift x c) where C puts the bit in the sign bit. Remove any
6112 AND with STORE_FLAG_VALUE when we are done, since we are only
6113 going to test the sign bit. */
6120 {
6126 else
6128 }
6130 /* If the code changed, return a whole new comparison.
6131 We also need to avoid using SUBST in cases where
6132 simplify_comparison has widened a comparison with a CONST_INT,
6133 since in that case the wider CONST_INT may fail the sanity
6134 checks in do_SUBST. */
6141 /* Otherwise, keep this operation, but maybe change its operands.
6142 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6145 }
6155 /* If we are processing SET_DEST, we are done. */
6173 /* If this is a shift by a constant amount, simplify it. */
6189 }
6192 }
6193 \f
6194 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6196 static rtx
6198 {
6205 rtx temp;
6208 rtx reversed;
6210 /* Simplify storing of the truth value. */
6215 /* Also when the truth value has to be reversed. */
6221 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6222 in it is being compared against certain values. Get the true and false
6223 comparisons and see if that says anything about the value of each arm. */
6229 {
6230 HOST_WIDE_INT nzb;
6236 /* If FALSE_CODE is EQ, swap the codes and arms. */
6239 {
6242 }
6244 /* If we are comparing against zero and the expression being tested has
6245 only a single bit that might be nonzero, that is its value when it is
6246 not equal to zero. Similarly if it is known to be -1 or 0. */
6250 {
6253 }
6257 {
6260 }
6262 /* Now simplify an arm if we know the value of the register in the
6263 branch and it is used in the arm. Be careful due to the potential
6264 of locally-shared RTL. */
6281 }
6283 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6284 reversed, do so to avoid needing two sets of patterns for
6285 subtract-and-branch insns. Similarly if we have a constant in the true
6286 arm, the false arm is the same as the first operand of the comparison, or
6287 the false arm is more complicated than the true arm. */
6300 {
6309 /* It is possible that the conditional has been simplified out. */
6312 }
6314 /* If the two arms are identical, we don't need the comparison. */
6319 /* Convert a == b ? b : a to "a". */
6331 /* Look for cases where we have (abs x) or (neg (abs X)). */
6334 && comparison_p
6341 {
6347 return
6350 mode);
6353 }
6355 /* Look for MIN or MAX. */
6358 && comparison_p
6363 {
6378 }
6380 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6381 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6382 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6383 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6384 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6385 neither 1 or -1, but it isn't worth checking for. */
6388 && comparison_p
6391 {
6407 /* If an identity-zero op is commutative, check whether there
6408 would be a match if we swapped the operands. */
6428 {
6432 }
6444 {
6448 }
6464 {
6468 }
6480 {
6484 }
6487 {
6493 const_true_rtx));
6501 }
6502 }
6504 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6505 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6506 negation of a single bit, we can convert this operation to a shift. We
6507 can actually do this more generally, but it doesn't seem worth it. */
6516 return
6520 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6530 }
6531 \f
6532 /* Simplify X, a SET expression. Return the new expression. */
6534 static rtx
6536 {
6539 machine_mode mode
6544 /* (set (pc) (return)) gets written as (return). */
6548 /* Now that we know for sure which bits of SRC we are using, see if we can
6549 simplify the expression for the object knowing that we only need the
6550 low-order bits. */
6553 {
6556 }
6558 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6559 the comparison result and try to simplify it unless we already have used
6560 undobuf.other_insn. */
6568 {
6577 {
6580 {
6583 }
6584 }
6585 else
6593 {
6597 }
6598 else
6599 {
6604 /* Attempt to simplify CC user. */
6606 {
6610 }
6612 /* Convert X into a no-op move. */
6616 }
6618 /* Simplify our comparison, if possible. */
6621 #ifdef SELECT_CC_MODE
6622 /* If this machine has CC modes other than CCmode, check to see if we
6623 need to use a different CC mode here. */
6632 else
6635 /* If the mode changed, we have to change SET_DEST, the mode in the
6636 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6637 a hard register, just build new versions with the proper mode. If it
6638 is a pseudo, we lose unless it is only time we set the pseudo, in
6639 which case we can safely change its mode. */
6641 {
6643 {
6645 rtx new_dest;
6649 else
6650 {
6653 }
6660 }
6661 }
6664 /* If the code changed, we have to build a new comparison in
6665 undobuf.other_insn. */
6667 {
6676 /* If the only change we made was to change an EQ into an NE or
6677 vice versa, OP0 has only one bit that might be nonzero, and OP1
6678 is zero, check if changing the user of the condition code will
6679 produce a valid insn. If it won't, we can keep the original code
6680 in that insn by surrounding our operation with an XOR. */
6687 {
6692 {
6699 }
6700 }
6701 }
6706 /* Don't generate a compare of a CC with 0, just use that CC. */
6708 {
6711 }
6712 /* Otherwise, if we didn't previously have the same COMPARE we
6713 want, create it from scratch. */
6716 {
6719 }
6720 }
6721 else
6722 {
6723 /* Get SET_SRC in a form where we have placed back any
6724 compound expressions. Then do the checks below. */
6727 }
6729 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6730 and X being a REG or (subreg (reg)), we may be able to convert this to
6731 (set (subreg:m2 x) (op)).
6733 We can always do this if M1 is narrower than M2 because that means that
6734 we only care about the low bits of the result.
6736 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6737 perform a narrower operation than requested since the high-order bits will
6738 be undefined. On machine where it is defined, this transformation is safe
6739 as long as M1 and M2 have the same number of words. */
6747 #ifndef WORD_REGISTER_OPERATIONS
6750 #endif
6751 #ifdef CANNOT_CHANGE_MODE_CLASS
6756 #endif
6760 {
6763 dest));
6767 }
6769 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6770 in SRC. */
6776 {
6780 /* Here we make sure that we don't have a sign bit on. */
6783 {
6786 }
6787 }
6789 #ifdef LOAD_EXTEND_OP
6790 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6791 would require a paradoxical subreg. Replace the subreg with a
6792 zero_extend to avoid the reload that would otherwise be required. */
6800 {
6806 }
6807 #endif
6809 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6810 are comparing an item known to be 0 or -1 against 0, use a logical
6811 operation instead. Check for one of the arms being an IOR of the other
6812 arm with some value. We compute three terms to be IOR'ed together. In
6813 practice, at most two will be nonzero. Then we do the IOR's. */
6821 && (!HAVE_conditional_move
6827 {
6853 false_rtx);
6859 term3));
6862 }
6864 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6865 whole thing fail. */
6870 else
6871 /* Convert this into a field assignment operation, if possible. */
6873 }
6874 \f
6875 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6876 result. */
6878 static rtx
6880 {
6886 {
6888 /* We can call simplify_and_const_int only if we don't lose
6889 any (sign) bits when converting INTVAL (op1) to
6890 "unsigned HOST_WIDE_INT". */
6894 {
6901 }
6903 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6904 apply the distributive law and then the inverse distributive
6905 law to see if things simplify. */
6907 {
6911 }
6913 {
6917 }
6921 /* If we have (ior (and A B) C), apply the distributive law and then
6922 the inverse distributive law to see if things simplify. */
6925 {
6929 }
6932 {
6936 }
6941 }
6944 }
6945 \f
6946 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6947 operations" because they can be replaced with two more basic operations.
6948 ZERO_EXTEND is also considered "compound" because it can be replaced with
6949 an AND operation, which is simpler, though only one operation.
6951 The function expand_compound_operation is called with an rtx expression
6952 and will convert it to the appropriate shifts and AND operations,
6953 simplifying at each stage.
6955 The function make_compound_operation is called to convert an expression
6956 consisting of shifts and ANDs into the equivalent compound expression.
6957 It is the inverse of this function, loosely speaking. */
6959 static rtx
6961 {
6965 rtx tem;
6968 {
6972 /* We can't necessarily use a const_int for a multiword mode;
6973 it depends on implicitly extending the value.
6974 Since we don't know the right way to extend it,
6975 we can't tell whether the implicit way is right.
6977 Even for a mode that is no wider than a const_int,
6978 we can't win, because we need to sign extend one of its bits through
6979 the rest of it, and we don't know which bit. */
6983 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6984 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6985 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6986 reloaded. If not for that, MEM's would very rarely be safe.
6988 Reject MODEs bigger than a word, because we might not be able
6989 to reference a two-register group starting with an arbitrary register
6990 (and currently gen_lowpart might crash for a SUBREG). */
6995 /* Reject MODEs that aren't scalar integers because turning vector
6996 or complex modes into shifts causes problems. */
7002 /* If the inner object has VOIDmode (the only way this can happen
7003 is if it is an ASM_OPERANDS), we can't do anything since we don't
7004 know how much masking to do. */
7013 /* ... fall through ... */
7016 /* If the operand is a CLOBBER, just return it. */
7025 /* Reject MODEs that aren't scalar integers because turning vector
7026 or complex modes into shifts causes problems. */
7034 /* This should stay within the object being extracted, fail otherwise. */
7045 }
7046 /* Convert sign extension to zero extension, if we know that the high
7047 bit is not set, as this is easier to optimize. It will be converted
7048 back to cheaper alternative in make_extraction. */
7056 {
7060 /* Make sure this is a profitable operation. */
7067 else
7069 }
7071 /* We can optimize some special cases of ZERO_EXTEND. */
7073 {
7074 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7075 know that the last value didn't have any inappropriate bits
7076 set. */
7084 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7093 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7094 is a comparison and STORE_FLAG_VALUE permits. This is like
7095 the first case, but it works even when GET_MODE (x) is larger
7096 than HOST_WIDE_INT. */
7105 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7115 }
7117 /* If we reach here, we want to return a pair of shifts. The inner
7118 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7119 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7120 logical depending on the value of UNSIGNEDP.
7122 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7123 converted into an AND of a shift.
7125 We must check for the case where the left shift would have a negative
7126 count. This can happen in a case like (x >> 31) & 255 on machines
7127 that can't shift by a constant. On those machines, we would first
7128 combine the shift with the AND to produce a variable-position
7129 extraction. Then the constant of 31 would be substituted in
7130 to produce such a position. */
7134 {
7143 }
7150 else
7151 /* Any other cases we can't handle. */
7154 /* If we couldn't do this for some reason, return the original
7155 expression. */
7160 }
7161 \f
7162 /* X is a SET which contains an assignment of one object into
7163 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7164 or certain SUBREGS). If possible, convert it into a series of
7165 logical operations.
7167 We half-heartedly support variable positions, but do not at all
7168 support variable lengths. */
7170 static const_rtx
7172 {
7173 rtx inner;
7177 machine_mode compute_mode;
7179 /* Loop until we find something we can't simplify. */
7181 {
7184 {
7188 }
7191 {
7196 /* A constant position should stay within the width of INNER. */
7202 {
7210 /* If position is ADJUST - X, new position is X. */
7212 else
7213 {
7218 pos);
7219 }
7220 }
7221 }
7223 /* A SUBREG between two modes that occupy the same numbers of words
7224 can be done by moving the SUBREG to the source. */
7226 /* We need SUBREGs to compute nonzero_bits properly. */
7227 && nonzero_sign_valid
7232 {
7234 gen_lowpart
7238 }
7239 else
7247 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7249 {
7250 machine_mode imode;
7252 /* Don't do anything for vector or complex integral types. */
7256 /* Try to find an integral mode to pun with. */
7263 }
7265 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7269 /* Now compute the equivalent expression. Make a copy of INNER
7270 for the SET_DEST in case it is a MEM into which we will substitute;
7271 we don't want shared RTL in that case. */
7273 compute_mode);
7277 compute_mode,
7279 compute_mode),
7280 inner);
7285 mask),
7286 pos);
7291 }
7294 }
7295 \f
7296 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7297 it is an RTX that represents the (variable) starting position; otherwise,
7298 POS is the (constant) starting bit position. Both are counted from the LSB.
7300 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7302 IN_DEST is nonzero if this is a reference in the destination of a SET.
7303 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7304 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7305 be used.
7307 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7308 ZERO_EXTRACT should be built even for bits starting at bit 0.
7310 MODE is the desired mode of the result (if IN_DEST == 0).
7312 The result is an RTX for the extraction or NULL_RTX if the target
7313 can't handle it. */
7315 static rtx
7319 {
7320 /* This mode describes the size of the storage area
7321 to fetch the overall value from. Within that, we
7322 ignore the POS lowest bits, etc. */
7324 machine_mode inner_mode;
7325 machine_mode wanted_inner_mode;
7332 HOST_WIDE_INT orig_pos;
7338 {
7339 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7340 consider just the QI as the memory to extract from.
7341 The subreg adds or removes high bits; its mode is
7342 irrelevant to the meaning of this extraction,
7343 since POS and LEN count from the lsb. */
7347 }
7352 {
7353 /* We're extracting the least significant bits of an rtx
7354 (ashift X (const_int C)), where LEN > C. Extract the
7355 least significant (LEN - C) bits of X, giving an rtx
7356 whose mode is MODE, then shift it left C times. */
7362 }
7368 /* See if this can be done without an extraction. We never can if the
7369 width of the field is not the same as that of some integer mode. For
7370 registers, we can only avoid the extraction if the position is at the
7371 low-order bit and this is either not in the destination or we have the
7372 appropriate STRICT_LOW_PART operation available.
7374 For MEM, we can avoid an extract if the field starts on an appropriate
7375 boundary and we can change the mode of the memory reference. */
7384 && (! in_dest
7388 && (pos
7391 /* We can't do this if we are widening INNER_MODE (it
7392 may not be aligned, for one thing). */
7398 {
7399 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7400 field. If the original and current mode are the same, we need not
7401 adjust the offset. Otherwise, we do if bytes big endian.
7403 If INNER is not a MEM, get a piece consisting of just the field
7404 of interest (in this case POS % BITS_PER_WORD must be 0). */
7407 {
7408 HOST_WIDE_INT offset;
7410 /* POS counts from lsb, but make OFFSET count in memory order. */
7413 else
7417 }
7419 {
7421 {
7422 /* We can't call gen_lowpart in a DEST since we
7423 always want a SUBREG (see below) and it would sometimes
7424 return a new hard register. */
7426 {
7441 /* Avoid creating invalid subregs, for example when
7442 simplifying (x>>32)&255. */
7447 }
7448 else
7450 }
7451 else
7453 }
7454 else
7456 len >= HOST_BITS_PER_WIDE_INT
7461 /* If this extraction is going into the destination of a SET,
7462 make a STRICT_LOW_PART unless we made a MEM. */
7477 /* If we know that no extraneous bits are set, and that the high
7478 bit is not set, convert the extraction to the cheaper of
7479 sign and zero extension, that are equivalent in these cases. */
7485 {
7489 /* Prefer ZERO_EXTENSION, since it gives more information to
7490 backends. */
7495 }
7497 /* Otherwise, sign- or zero-extend unless we already are in the
7498 proper mode. */
7502 }
7504 /* Unless this is a COMPARE or we have a funny memory reference,
7505 don't do anything with zero-extending field extracts starting at
7506 the low-order bit since they are simple AND operations. */
7511 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7512 if the position is not a constant and the length is not 1. In all
7513 other cases, we would only be going outside our object in cases when
7514 an original shift would have been undefined. */
7523 /* If INNER is not from memory, we want it to have the mode of a register
7524 extraction pattern's structure operand, or word_mode if there is no
7525 such pattern. The same applies to extraction_mode and pos_mode
7526 and their respective operands.
7528 For memory, assume that the desired extraction_mode and pos_mode
7529 are the same as for a register operation, since at present we don't
7530 have named patterns for aligned memory structures. */
7534 {
7538 }
7540 /* Never narrow an object, since that might not be safe. */
7548 else
7549 {
7550 /* Be careful not to go beyond the extracted object and maintain the
7551 natural alignment of the memory. */
7555 {
7558 }
7559 }
7564 {
7565 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7566 BITS_BIG_ENDIAN style. If position is constant, compute new
7567 position. Otherwise, build subtraction.
7568 Note that POS is relative to the mode of the original argument.
7569 If it's a MEM we need to recompute POS relative to that.
7570 However, if we're extracting from (or inserting into) a register,
7571 we want to recompute POS relative to wanted_inner_mode. */
7578 else
7579 pos_rtx
7582 pos_rtx);
7583 /* POS may be less than 0 now, but we check for that below.
7584 Note that it can only be less than 0 if !MEM_P (inner). */
7585 }
7587 /* If INNER has a wider mode, and this is a constant extraction, try to
7588 make it smaller and adjust the byte to point to the byte containing
7589 the value. */
7592 && ! pos_rtx
7597 {
7600 /* The computations below will be correct if the machine is big
7601 endian in both bits and bytes or little endian in bits and bytes.
7602 If it is mixed, we must adjust. */
7604 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7605 adjust OFFSET to compensate. */
7610 /* We can now move to the desired byte. */
7621 }
7623 /* If INNER is not memory, get it into the proper mode. If we are changing
7624 its mode, POS must be a constant and smaller than the size of the new
7625 mode. */
7627 {
7628 /* On the LHS, don't create paradoxical subregs implicitely truncating
7629 the register unless TRULY_NOOP_TRUNCATION. */
7632 wanted_inner_mode))
7644 pos_rtx
7650 }
7652 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7653 have to zero extend. Otherwise, we can just use a SUBREG. */
7656 {
7660 /* If we know that no extraneous bits are set, and that the high
7661 bit is not set, convert extraction to cheaper one - either
7662 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7663 cases. */
7671 {
7675 /* Prefer ZERO_EXTENSION, since it gives more information to
7676 backends. */
7680 }
7682 }
7684 /* Make POS_RTX unless we already have it and it is correct. If we don't
7685 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7686 be a CONST_INT. */
7693 /* Make the required operation. See if we can use existing rtx. */
7700 }
7701 \f
7702 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7703 with any other operations in X. Return X without that shift if so. */
7705 static rtx
7707 {
7710 rtx tem;
7713 {
7715 /* This is the shift itself. If it is wide enough, we will return
7716 either the value being shifted if the shift count is equal to
7717 COUNT or a shift for the difference. */
7731 /* If we can safely shift this constant and we find the inner shift,
7732 make a new operation. */
7737 {
7741 }
7746 }
7749 }
7750 \f
7751 /* Look at the expression rooted at X. Look for expressions
7752 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7753 Form these expressions.
7755 Return the new rtx, usually just X.
7757 Also, for machines like the VAX that don't have logical shift insns,
7758 try to convert logical to arithmetic shift operations in cases where
7759 they are equivalent. This undoes the canonicalizations to logical
7760 shifts done elsewhere.
7762 We try, as much as possible, to re-use rtl expressions to save memory.
7764 IN_CODE says what kind of expression we are processing. Normally, it is
7765 SET. In a memory address it is MEM. When processing the arguments of
7766 a comparison or a COMPARE against zero, it is COMPARE. */
7768 rtx
7770 {
7778 rtx tem;
7781 /* Select the code to be used in recursive calls. Once we are inside an
7782 address, we stay there. If we have a comparison, set to COMPARE,
7783 but once inside, go back to our default of SET. */
7790 /* Process depending on the code of this operation. If NEW is set
7791 nonzero, it will be returned. */
7794 {
7796 /* Convert shifts by constants into multiplications if inside
7797 an address. */
7802 {
7808 {
7811 }
7814 }
7824 {
7828 }
7831 {
7835 mode));
7837 }
7838 else
7839 {
7843 }
7854 {
7858 }
7861 {
7865 mode));
7867 }
7868 else
7869 {
7873 }
7877 /* If the second operand is not a constant, we can't do anything
7878 with it. */
7882 /* If the constant is a power of two minus one and the first operand
7883 is a logical right shift, make an extraction. */
7886 {
7890 }
7892 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7897 {
7899 next_code);
7903 }
7904 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7910 {
7911 /* Apply the distributive law, and then try to make extractions. */
7918 }
7920 /* If we are have (and (rotate X C) M) and C is larger than the number
7921 of bits in M, this is an extraction. */
7927 {
7933 }
7935 /* On machines without logical shifts, if the operand of the AND is
7936 a logical shift and our mask turns off all the propagated sign
7937 bits, we can replace the logical shift with an arithmetic shift. */
7945 {
7952 make_compound_operation
7955 }
7957 /* If the constant is one less than a power of two, this might be
7958 representable by an extraction even if no shift is present.
7959 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7960 we are in a COMPARE. */
7964 next_code),
7967 /* If we are in a comparison and this is an AND with a power of two,
7968 convert this into the appropriate bit extract. */
7973 next_code),
7979 /* If the sign bit is known to be zero, replace this with an
7980 arithmetic shift. */
7985 {
7988 next_code),
7991 }
7993 /* ... fall through ... */
7999 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8000 this is a SIGN_EXTRACT. */
8007 {
8014 }
8016 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8017 If so, try to merge the shifts into a SIGN_EXTEND. We could
8018 also do this for some cases of SIGN_EXTRACT, but it doesn't
8019 seem worth the effort; the case checked for occurs on Alpha. */
8035 /* Call ourselves recursively on the inner expression. If we are
8036 narrowing the object and it has a different RTL code from
8037 what it originally did, do this SUBREG as a force_to_mode. */
8038 {
8042 /* If in_code is COMPARE, it isn't always safe to pass it through
8043 to the recursive make_compound_operation call. */
8047 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8048 is (const_int 0), rather than
8049 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8059 simplified
8067 {
8068 rtx newer
8071 /* If we have something other than a SUBREG, we might have
8072 done an expansion, so rerun ourselves. */
8076 /* force_to_mode can expand compounds. If it just re-expanded the
8077 compound, use gen_lowpart to convert to the desired mode. */
8079 /* Likewise if it re-expanded the compound only partially.
8080 This happens for SUBREG of ZERO_EXTRACT if they extract
8081 the same number of bits. */
8090 }
8094 }
8099 }
8102 {
8105 }
8107 /* Now recursively process each operand of this operation. We need to
8108 handle ZERO_EXTEND specially so that we don't lose track of the
8109 inner mode. */
8111 {
8119 }
8124 {
8127 }
8130 {
8133 }
8135 maybe_swap:
8136 /* If this is a commutative operation, the changes to the operands
8137 may have made it noncanonical. */
8140 {
8144 }
8147 }
8148 \f
8149 /* Given M see if it is a value that would select a field of bits
8150 within an item, but not the entire word. Return -1 if not.
8151 Otherwise, return the starting position of the field, where 0 is the
8152 low-order bit.
8154 *PLEN is set to the length of the field. */
8156 static int
8158 {
8159 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8164 /* Now shift off the low-order zero bits and see if we have a
8165 power of two minus 1. */
8173 }
8174 \f
8175 /* If X refers to a register that equals REG in value, replace these
8176 references with REG. */
8177 static rtx
8179 {
8187 {
8223 {
8227 else
8229 }
8231 /* fall through */
8238 {
8241 {
8243 {
8246 }
8248 }
8249 }
8251 {
8254 {
8257 {
8259 {
8262 }
8264 }
8265 }
8266 }
8269 }
8272 }
8274 /* Return X converted to MODE. If the value is already truncated to
8275 MODE we can just return a subreg even though in the general case we
8276 would need an explicit truncation. */
8278 static rtx
8280 {
8285 {
8286 /* Bit-cast X into an integer mode. */
8291 }
8294 }
8296 /* See if X can be simplified knowing that we will only refer to it in
8297 MODE and will only refer to those bits that are nonzero in MASK.
8298 If other bits are being computed or if masking operations are done
8299 that select a superset of the bits in MASK, they can sometimes be
8300 ignored.
8302 Return a possibly simplified expression, but always convert X to
8303 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8305 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8306 are all off in X. This is used when X will be complemented, by either
8307 NOT, NEG, or XOR. */
8309 static rtx
8312 {
8315 machine_mode op_mode;
8319 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8320 code below will do the wrong thing since the mode of such an
8321 expression is VOIDmode.
8323 Also do nothing if X is a CLOBBER; this can happen if X was
8324 the return value from a call to gen_lowpart. */
8328 /* We want to perform the operation in its present mode unless we know
8329 that the operation is valid in MODE, in which case we do the operation
8330 in MODE. */
8335 /* It is not valid to do a right-shift in a narrower mode
8336 than the one it came in with. */
8341 /* Truncate MASK to fit OP_MODE. */
8345 /* When we have an arithmetic operation, or a shift whose count we
8346 do not know, we need to assume that all bits up to the highest-order
8347 bit in MASK will be needed. This is how we form such a mask. */
8350 else
8354 /* Determine what bits of X are guaranteed to be (non)zero. */
8357 /* If none of the bits in X are needed, return a zero. */
8361 /* If X is a CONST_INT, return a new one. Do this here since the
8362 test below will fail. */
8364 {
8367 else
8368 {
8371 }
8372 }
8374 /* If X is narrower than MODE and we want all the bits in X's mode, just
8375 get X in the proper mode. */
8380 /* We can ignore the effect of a SUBREG if it narrows the mode or
8381 if the constant masks to zero all the bits the mode doesn't have. */
8391 /* The arithmetic simplifications here only work for scalar integer modes. */
8396 {
8398 /* If X is a (clobber (const_int)), return it since we know we are
8399 generating something that won't match. */
8412 /* Similarly for a truncate. */
8416 /* If this is an AND with a constant, convert it into an AND
8417 whose constant is the AND of that constant with MASK. If it
8418 remains an AND of MASK, delete it since it is redundant. */
8421 {
8425 /* If X is still an AND, see if it is an AND with a mask that
8426 is just some low-order bits. If so, and it is MASK, we don't
8427 need it. */
8434 /* If it remains an AND, try making another AND with the bits
8435 in the mode mask that aren't in MASK turned on. If the
8436 constant in the AND is wide enough, this might make a
8437 cheaper constant. */
8442 {
8443 unsigned HOST_WIDE_INT cval
8446 rtx y;
8453 }
8456 }
8461 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8462 low-order bits (as in an alignment operation) and FOO is already
8463 aligned to that boundary, mask C1 to that boundary as well.
8464 This may eliminate that PLUS and, later, the AND. */
8466 {
8470 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8471 number, sign extend it. */
8484 }
8486 /* ... fall through ... */
8489 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8490 most significant bit in MASK since carries from those bits will
8491 affect the bits we are interested in. */
8496 /* If X is (minus C Y) where C's least set bit is larger than any bit
8497 in the mask, then we may replace with (neg Y). */
8500 {
8504 }
8506 /* Similarly, if C contains every bit in the fuller_mask, then we may
8507 replace with (not Y). */
8510 {
8514 }
8521 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8522 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8523 operation which may be a bitfield extraction. Ensure that the
8524 constant we form is not wider than the mode of X. */
8536 {
8545 }
8547 binop:
8548 /* For most binary operations, just propagate into the operation and
8549 change the mode if we have an operation of that mode. */
8554 /* If we ended up truncating both operands, truncate the result of the
8555 operation instead. */
8558 {
8561 }
8571 /* For left shifts, do the same, but just for the first operand.
8572 However, we cannot do anything with shifts where we cannot
8573 guarantee that the counts are smaller than the size of the mode
8574 because such a count will have a different meaning in a
8575 wider mode. */
8585 /* If the shift count is a constant and we can do arithmetic in
8586 the mode of the shift, refine which bits we need. Otherwise, use the
8587 conservative form of the mask. */
8593 else
8605 /* Here we can only do something if the shift count is a constant,
8606 this shift constant is valid for the host, and we can do arithmetic
8607 in OP_MODE. */
8613 {
8617 /* Select the mask of the bits we need for the shift operand. */
8620 /* We can only change the mode of the shift if we can do arithmetic
8621 in the mode of the shift and INNER_MASK is no wider than the
8622 width of X's mode. */
8630 }
8632 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8633 shift and AND produces only copies of the sign bit (C2 is one less
8634 than a power of two), we can do this with just a shift. */
8638 /* The shift puts one of the sign bit copies in the least significant
8639 bit. */
8644 /* Number of bits left after the shift must be more than the mask
8645 needs. */
8648 /* Must be more sign bit copies than the mask needs. */
8658 /* If we are just looking for the sign bit, we don't need this shift at
8659 all, even if it has a variable count. */
8663 /* If this is a shift by a constant, get a mask that contains those bits
8664 that are not copies of the sign bit. We then have two cases: If
8665 MASK only includes those bits, this can be a logical shift, which may
8666 allow simplifications. If MASK is a single-bit field not within
8667 those bits, we are requesting a copy of the sign bit and hence can
8668 shift the sign bit to the appropriate location. */
8672 {
8675 /* If the considered data is wider than HOST_WIDE_INT, we can't
8676 represent a mask for all its bits in a single scalar.
8677 But we only care about the lower bits, so calculate these. */
8680 {
8683 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8684 is the number of bits a full-width mask would have set.
8685 We need only shift if these are fewer than nonzero can
8686 hold. If not, we must keep all bits set in nonzero. */
8691 + HOST_BITS_PER_WIDE_INT
8693 }
8694 else
8695 {
8698 }
8701 {
8706 }
8709 {
8710 x = simplify_shift_const
8716 }
8717 }
8719 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8720 even if the shift count isn't a constant. */
8725 shiftrt:
8727 /* If this is a zero- or sign-extension operation that just affects bits
8728 we don't care about, remove it. Be sure the call above returned
8729 something that is still a shift. */
8739 next_select);
8745 /* If the shift count is constant and we can do computations
8746 in the mode of X, compute where the bits we care about are.
8747 Otherwise, we can't do anything. Don't change the mode of
8748 the shift or propagate MODE into the shift, though. */
8751 {
8761 }
8765 /* If we just want the low-order bit, the NEG isn't needed since it
8766 won't change the low-order bit. */
8770 /* We need any bits less significant than the most significant bit in
8771 MASK since carries from those bits will affect the bits we are
8772 interested in. */
8777 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8778 same as the XOR case above. Ensure that the constant we form is not
8779 wider than the mode of X. */
8787 {
8796 }
8798 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8799 use the full mask inside the NOT. */
8802 unop:
8805 next_select));
8811 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8812 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8813 which is equal to STORE_FLAG_VALUE. */
8825 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8826 written in a narrower mode. We play it safe and do not do so. */
8842 }
8844 /* Ensure we return a value of the proper mode. */
8846 }
8847 \f
8848 /* Return nonzero if X is an expression that has one of two values depending on
8849 whether some other value is zero or nonzero. In that case, we return the
8850 value that is being tested, *PTRUE is set to the value if the rtx being
8851 returned has a nonzero value, and *PFALSE is set to the other alternative.
8853 If we return zero, we set *PTRUE and *PFALSE to X. */
8855 static rtx
8857 {
8863 /* If we are comparing a value against zero, we are done. */
8866 {
8870 }
8872 /* If this is a unary operation whose operand has one of two values, apply
8873 our opcode to compute those values. */
8876 {
8881 }
8883 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8884 make can't possibly match and would suppress other optimizations. */
8886 ;
8888 /* If this is a binary operation, see if either side has only one of two
8889 values. If either one does or if both do and they are conditional on
8890 the same value, compute the new true and false values. */
8892 {
8898 {
8899 /* If if_then_else_cond returned zero, then true/false are the
8900 same rtl. We must copy one of them to prevent invalid rtl
8901 sharing. */
8908 {
8913 }
8914 else
8915 {
8918 }
8921 }
8923 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8924 operands is zero when the other is nonzero, and vice-versa,
8925 and STORE_FLAG_VALUE is 1 or -1. */
8931 {
8948 {
8955 const_true_rtx);
8957 }
8958 }
8960 /* Similarly for MULT, AND and UMIN, except that for these the result
8961 is always zero. */
8965 {
8979 {
8982 }
8983 }
8984 }
8987 {
8988 /* If we have IF_THEN_ELSE already, extract the condition and
8989 canonicalize it if it is NE or EQ. */
8995 {
8998 }
8999 else
9001 }
9003 /* If X is a SUBREG, we can narrow both the true and false values
9004 if the inner expression, if there is a condition. */
9008 {
9014 {
9018 }
9019 }
9021 /* If X is a constant, this isn't special and will cause confusions
9022 if we treat it as such. Likewise if it is equivalent to a constant. */
9025 ;
9027 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9028 will be least confusing to the rest of the compiler. */
9030 {
9033 }
9035 /* If X is known to be either 0 or -1, those are the true and
9036 false values when testing X. */
9040 {
9043 }
9045 /* Likewise for 0 or a single bit. */
9048 {
9051 }
9053 /* Otherwise fail; show no condition with true and false values the same. */
9056 }
9057 \f
9058 /* Return the value of expression X given the fact that condition COND
9059 is known to be true when applied to REG as its first operand and VAL
9060 as its second. X is known to not be shared and so can be modified in
9061 place.
9063 We only handle the simplest cases, and specifically those cases that
9064 arise with IF_THEN_ELSE expressions. */
9066 static rtx
9068 {
9076 /* If either operand of the condition is a floating point value,
9077 then we have to avoid collapsing an EQ comparison. */
9087 /* If X is (abs REG) and we know something about REG's relationship
9088 with zero, we may be able to simplify this. */
9092 {
9101 }
9103 /* The only other cases we handle are MIN, MAX, and comparisons if the
9104 operands are the same as REG and VAL. */
9107 {
9109 {
9112 }
9115 {
9117 {
9125 else
9127 }
9130 {
9133 /* Do not reverse the condition when it is NE or EQ.
9134 This is because we cannot conclude anything about
9135 the value of 'SMAX (x, y)' when x is not equal to y,
9136 but we can when x equals y. */
9142 {
9153 }
9154 }
9155 }
9156 }
9158 {
9163 {
9164 /* We must simplify subreg here, before we lose track of the
9165 original inner_mode. */
9170 else
9172 }
9175 }
9176 /* We don't have to handle SIGN_EXTEND here, because even in the
9177 case of replacing something with a modeless CONST_INT, a
9178 CONST_INT is already (supposed to be) a valid sign extension for
9179 its narrower mode, which implies it's already properly
9180 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9181 story is different. */
9183 {
9188 {
9189 /* We must simplify the zero_extend here, before we lose
9190 track of the original inner_mode. */
9195 else
9197 }
9200 }
9204 {
9211 }
9214 }
9215 \f
9216 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9217 assignment as a field assignment. */
9219 static int
9221 {
9223 {
9228 /* For big endian, adjust the memory offset. */
9233 else
9235 }
9243 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9244 Note that all SUBREGs of MEM are paradoxical; otherwise they
9245 would have been rewritten. */
9258 /* We used to see if get_last_value of X and Y were the same but that's
9259 not correct. In one direction, we'll cause the assignment to have
9260 the wrong destination and in the case, we'll import a register into this
9261 insn that might have already have been dead. So fail if none of the
9262 above cases are true. */
9264 }
9265 \f
9266 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9267 Return that assignment if so.
9269 We only handle the most common cases. */
9271 static rtx
9273 {
9276 rtx assign;
9278 HOST_WIDE_INT c1;
9279 HOST_WIDE_INT pos;
9281 rtx other;
9282 machine_mode mode;
9284 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9285 a clear of a one-bit field. We will have changed it to
9286 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9287 for a SUBREG. */
9293 {
9299 }
9309 {
9316 }
9318 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9319 one-bit field. */
9323 {
9329 }
9331 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9332 SRC is an AND with all bits of that field set, then we can discard
9333 the AND. */
9338 {
9345 else
9348 /* Complete overlap. We can remove the source AND. */
9352 /* Partial overlap. We can reduce the source AND. */
9354 {
9359 }
9360 }
9362 /* The other case we handle is assignments into a constant-position
9363 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9364 a mask that has all one bits except for a group of zero bits and
9365 OTHER is known to have zeros where C1 has ones, this is such an
9366 assignment. Compute the position and length from C1. Shift OTHER
9367 to the appropriate position, force it to the required mode, and
9368 make the extraction. Check for the AND in both operands. */
9370 /* One or more SUBREGs might obscure the constant-position field
9371 assignment. The first one we are likely to encounter is an outer
9372 narrowing SUBREG, which we can just strip for the purposes of
9373 identifying the constant-field assignment. */
9387 /* The second SUBREG that might get in the way is a paradoxical
9388 SUBREG around the first operand of the AND. We want to
9389 pretend the operand is as wide as the destination here. We
9390 do this by adjusting the MEM to wider mode for the sole
9391 purpose of the call to rtx_equal_for_field_assignment_p. Also
9392 note this trick only works for MEMs. */
9404 /* The second SUBREG that might get in the way is a paradoxical
9405 SUBREG around the first operand of the AND. We want to
9406 pretend the operand is as wide as the destination here. We
9407 do this by adjusting the MEM to wider mode for the sole
9408 purpose of the call to rtx_equal_for_field_assignment_p. Also
9409 note this trick only works for MEMs. */
9417 else
9430 /* The mode to use for the source is the mode of the assignment, or of
9431 what is inside a possible STRICT_LOW_PART. */
9435 /* Shift OTHER right POS places and make it the source, restricting it
9436 to the proper length and mode. */
9441 dest);
9448 /* If SRC is masked by an AND that does not make a difference in
9449 the value being stored, strip it. */
9460 }
9461 \f
9462 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9463 if so. */
9465 static rtx
9467 {
9471 rtx tem;
9473 /* Distributivity is not true for floating point as it can change the
9474 value. So we don't do it unless -funsafe-math-optimizations. */
9479 /* The outer operation can only be one of the following: */
9487 /* If either operand is a primitive we can't do anything, so get out
9488 fast. */
9498 /* See if the inner and outer operations distribute. */
9500 {
9505 /* These all distribute except over PLUS. */
9516 /* This is also a multiply, so it distributes over everything. */
9519 /* This used to handle SUBREG, but this turned out to be counter-
9520 productive, since (subreg (op ...)) usually is not handled by
9521 insn patterns, and this "optimization" therefore transformed
9522 recognizable patterns into unrecognizable ones. Therefore the
9523 SUBREG case was removed from here.
9525 It is possible that distributing SUBREG over arithmetic operations
9526 leads to an intermediate result than can then be optimized further,
9527 e.g. by moving the outer SUBREG to the other side of a SET as done
9528 in simplify_set. This seems to have been the original intent of
9529 handling SUBREGs here.
9531 However, with current GCC this does not appear to actually happen,
9532 at least on major platforms. If some case is found where removing
9533 the SUBREG case here prevents follow-on optimizations, distributing
9534 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9538 }
9540 /* Set LHS and RHS to the inner operands (A and B in the example
9541 above) and set OTHER to the common operand (C in the example).
9542 There is only one way to do this unless the inner operation is
9543 commutative. */
9555 else
9558 /* Form the new inner operation, seeing if it simplifies first. */
9561 /* There is one exception to the general way of distributing:
9562 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9564 {
9567 }
9569 /* We may be able to continuing distributing the result, so call
9570 ourselves recursively on the inner operation before forming the
9571 outer operation, which we return. */
9574 }
9576 /* See if X is of the form (* (+ A B) C), and if so convert to
9577 (+ (* A C) (* B C)) and try to simplify.
9579 Most of the time, this results in no change. However, if some of
9580 the operands are the same or inverses of each other, simplifications
9581 will result.
9583 For example, (and (ior A B) (not B)) can occur as the result of
9584 expanding a bit field assignment. When we apply the distributive
9585 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9586 which then simplifies to (and (A (not B))).
9588 Note that no checks happen on the validity of applying the inverse
9589 distributive law. This is pointless since we can do it in the
9590 few places where this routine is called.
9592 N is the index of the term that is decomposed (the arithmetic operation,
9593 i.e. (+ A B) in the first example above). !N is the index of the term that
9594 is distributed, i.e. of C in the first example above. */
9595 static rtx
9597 {
9598 machine_mode mode;
9602 /* Distributivity is not true for floating point as it can change the
9603 value. So we don't do it unless -funsafe-math-optimizations. */
9620 /* Special case (and (xor B C) (not A)), which is equivalent to
9621 (xor (ior A B) (ior A C)) */
9623 {
9626 }
9629 {
9630 /* Distribute the second term. */
9633 }
9634 else
9635 {
9636 /* Distribute the first term. */
9639 }
9649 }
9650 \f
9651 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9652 in MODE. Return an equivalent form, if different from (and VAROP
9653 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9655 static rtx
9658 {
9661 rtx orig_varop;
9669 /* Simplify VAROP knowing that we will be only looking at some of the
9670 bits in it.
9672 Note by passing in CONSTOP, we guarantee that the bits not set in
9673 CONSTOP are not significant and will never be examined. We must
9674 ensure that is the case by explicitly masking out those bits
9675 before returning. */
9678 /* If VAROP is a CLOBBER, we will fail so return it. */
9682 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9683 to VAROP and return the new constant. */
9687 /* See what bits may be nonzero in VAROP. Unlike the general case of
9688 a call to nonzero_bits, here we don't care about bits outside
9689 MODE. */
9693 /* Turn off all bits in the constant that are known to already be zero.
9694 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9695 which is tested below. */
9699 /* If we don't have any bits left, return zero. */
9703 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9704 a power of two, we can replace this with an ASHIFT. */
9709 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9710 or XOR, then try to apply the distributive law. This may eliminate
9711 operations if either branch can be simplified because of the AND.
9712 It may also make some cases more complex, but those cases probably
9713 won't match a pattern either with or without this. */
9716 return
9717 gen_lowpart
9719 apply_distributive_law
9724 constop),
9728 constop))));
9730 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9731 the AND and see if one of the operands simplifies to zero. If so, we
9732 may eliminate it. */
9736 {
9745 }
9747 /* Make a SUBREG if necessary. If we can't make it, fail. */
9752 /* If we are only masking insignificant bits, return VAROP. */
9759 /* Otherwise, return an AND. */
9761 }
9764 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9765 in MODE.
9767 Return an equivalent form, if different from X. Otherwise, return X. If
9768 X is zero, we are to always construct the equivalent form. */
9770 static rtx
9773 {
9784 }
9785 \f
9786 /* Given a REG, X, compute which bits in X can be nonzero.
9787 We don't care about bits outside of those defined in MODE.
9789 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9790 a shift, AND, or zero_extract, we can do better. */
9792 static rtx
9794 const_rtx known_x ATTRIBUTE_UNUSED,
9795 machine_mode known_mode ATTRIBUTE_UNUSED,
9798 {
9799 rtx tem;
9802 /* If X is a register whose nonzero bits value is current, use it.
9803 Otherwise, if X is a register whose value we can find, use that
9804 value. Otherwise, use the previously-computed global nonzero bits
9805 for this register. */
9819 && !REGNO_REG_SET_P
9822 {
9826 /* We don't know anything about the upper bits. */
9831 }
9836 {
9837 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9840 #endif
9842 }
9844 {
9848 /* We don't know anything about the upper bits. */
9852 }
9855 }
9857 /* Return the number of bits at the high-order end of X that are known to
9858 be equal to the sign bit. X will be used in mode MODE; if MODE is
9859 VOIDmode, X will be used in its own mode. The returned value will always
9860 be between 1 and the number of bits in MODE. */
9862 static rtx
9864 const_rtx known_x ATTRIBUTE_UNUSED,
9865 machine_mode known_mode
9866 ATTRIBUTE_UNUSED,
9869 {
9870 rtx tem;
9883 && !REGNO_REG_SET_P
9886 {
9889 }
9900 }
9901 \f
9902 /* Return the number of "extended" bits there are in X, when interpreted
9903 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9904 unsigned quantities, this is the number of high-order zero bits.
9905 For signed quantities, this is the number of copies of the sign bit
9906 minus 1. In both case, this function returns the number of "spare"
9907 bits. For example, if two quantities for which this function returns
9908 at least 1 are added, the addition is known not to overflow.
9910 This function will always return 0 unless called during combine, which
9911 implies that it must be called from a define_split. */
9913 unsigned int
9915 {
9925 }
9927 /* This function is called from `simplify_shift_const' to merge two
9928 outer operations. Specifically, we have already found that we need
9929 to perform operation *POP0 with constant *PCONST0 at the outermost
9930 position. We would now like to also perform OP1 with constant CONST1
9931 (with *POP0 being done last).
9933 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9934 the resulting operation. *PCOMP_P is set to 1 if we would need to
9935 complement the innermost operand, otherwise it is unchanged.
9937 MODE is the mode in which the operation will be done. No bits outside
9938 the width of this mode matter. It is assumed that the width of this mode
9939 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9941 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9942 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9943 result is simply *PCONST0.
9945 If the resulting operation cannot be expressed as one operation, we
9946 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9948 static int
9949 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
9950 {
9957 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9961 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9962 if OP0 is SET. */
9971 {
9973 {
9991 }
9992 }
9994 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9998 /* If the two constants aren't the same, we can't do anything. The
9999 remaining six cases can all be done. */
10003 else
10005 {
10008 /* (a & b) | b == b */
10011 /* (a ^ b) | b == a | b */
10012 {;}
10017 /* (a & b) ^ b == (~a) & b */
10020 /* (a | b) ^ b == a & ~b */
10026 /* (a | b) & b == b */
10029 /* (a ^ b) & b) == (~a) & b */
10034 }
10036 /* Check for NO-OP cases. */
10049 /* ??? Slightly redundant with the above mask, but not entirely.
10050 Moving this above means we'd have to sign-extend the mode mask
10051 for the final test. */
10056 }
10057 \f
10058 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10059 the shift in. The original shift operation CODE is performed on OP in
10060 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10061 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10062 result of the shift is subject to operation OUTER_CODE with operand
10063 OUTER_CONST. */
10065 static machine_mode
10069 {
10074 /* In general we can't perform in wider mode for right shift and rotate. */
10076 {
10078 /* We can still widen if the bits brought in from the left are identical
10079 to the sign bit of ORIG_MODE. */
10087 /* Similarly here but with zero bits. */
10092 /* We can also widen if the bits brought in will be masked off. This
10093 operation is performed in ORIG_MODE. */
10095 {
10101 }
10102 /* fall through */
10112 }
10113 }
10115 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10116 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10117 if we cannot simplify it. Otherwise, return a simplified value.
10119 The shift is normally computed in the widest mode we find in VAROP, as
10120 long as it isn't a different number of words than RESULT_MODE. Exceptions
10121 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10123 static rtx
10126 {
10132 unsigned int mode_words
10134 /* We form (outer_op (code varop count) (outer_const)). */
10140 /* Make sure and truncate the "natural" shift on the way in. We don't
10141 want to do this inside the loop as it makes it more difficult to
10142 combine shifts. */
10146 /* If we were given an invalid count, don't do anything except exactly
10147 what was requested. */
10154 /* Unless one of the branches of the `if' in this loop does a `continue',
10155 we will `break' the loop after the `if'. */
10158 {
10159 /* If we have an operand of (clobber (const_int 0)), fail. */
10163 /* Convert ROTATERT to ROTATE. */
10165 {
10170 else
10172 }
10177 /* Handle cases where the count is greater than the size of the mode
10178 minus 1. For ASHIFT, use the size minus one as the count (this can
10179 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10180 take the count modulo the size. For other shifts, the result is
10181 zero.
10183 Since these shifts are being produced by the compiler by combining
10184 multiple operations, each of which are defined, we know what the
10185 result is supposed to be. */
10188 {
10193 else
10194 {
10195 /* We can't simply return zero because there may be an
10196 outer op. */
10200 }
10201 }
10203 /* If we discovered we had to complement VAROP, leave. Making a NOT
10204 here would cause an infinite loop. */
10208 /* An arithmetic right shift of a quantity known to be -1 or 0
10209 is a no-op. */
10213 {
10216 }
10218 /* If we are doing an arithmetic right shift and discarding all but
10219 the sign bit copies, this is equivalent to doing a shift by the
10220 bitsize minus one. Convert it into that shift because it will often
10221 allow other simplifications. */
10228 /* We simplify the tests below and elsewhere by converting
10229 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10230 `make_compound_operation' will convert it to an ASHIFTRT for
10231 those machines (such as VAX) that don't have an LSHIFTRT. */
10248 {
10255 {
10258 }
10262 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10263 minus the width of a smaller mode, we can do this with a
10264 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10271 {
10280 }
10284 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10285 the same number of words as what we've seen so far. Then store
10286 the widest mode in MODE. */
10292 == mode_words
10295 {
10300 }
10304 /* Some machines use MULT instead of ASHIFT because MULT
10305 is cheaper. But it is still better on those machines to
10306 merge two shifts into one. */
10309 {
10310 varop
10316 }
10320 /* Similar, for when divides are cheaper. */
10323 {
10324 varop
10330 }
10334 /* If we are extracting just the sign bit of an arithmetic
10335 right shift, that shift is not needed. However, the sign
10336 bit of a wider mode may be different from what would be
10337 interpreted as the sign bit in a narrower mode, so, if
10338 the result is narrower, don't discard the shift. */
10343 {
10346 }
10348 /* ... fall through ... */
10353 /* Here we have two nested shifts. The result is usually the
10354 AND of a new shift with a mask. We compute the result below. */
10361 {
10365 rtx mask_rtx;
10367 /* We have one common special case. We can't do any merging if
10368 the inner code is an ASHIFTRT of a smaller mode. However, if
10369 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10370 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10371 we can convert it to
10372 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10373 This simplifies certain SIGN_EXTEND operations. */
10377 {
10378 /* C3 has the low-order C1 bits zero. */
10390 }
10392 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10393 than C1 high-order bits equal to the sign bit, we can convert
10394 this to either an ASHIFT or an ASHIFTRT depending on the
10395 two counts.
10397 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10403 {
10407 {
10410 }
10413 }
10415 /* There are some cases we can't do. If CODE is ASHIFTRT,
10416 we can only do this if FIRST_CODE is also ASHIFTRT.
10418 We can't do the case when CODE is ROTATE and FIRST_CODE is
10419 ASHIFTRT.
10421 If the mode of this shift is not the mode of the outer shift,
10422 we can't do this if either shift is a right shift or ROTATE.
10424 Finally, we can't do any of these if the mode is too wide
10425 unless the codes are the same.
10427 Handle the case where the shift codes are the same
10428 first. */
10431 {
10440 }
10451 /* To compute the mask to apply after the shift, shift the
10452 nonzero bits of the inner shift the same way the
10453 outer shift will. */
10456 result_mode);
10458 mask_rtx
10462 /* Give up if we can't compute an outer operation to use. */
10470 /* If the shifts are in the same direction, we add the
10471 counts. Otherwise, we subtract them. */
10475 else
10478 /* If COUNT is positive, the new shift is usually CODE,
10479 except for the two exceptions below, in which case it is
10480 FIRST_CODE. If the count is negative, FIRST_CODE should
10481 always be used */
10491 }
10493 /* If we have (A << B << C) for any shift, we can convert this to
10494 (A << C << B). This wins if A is a constant. Only try this if
10495 B is not a constant. */
10500 {
10507 }
10514 /* Make this fit the case below. */
10521 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10522 with C the size of VAROP - 1 and the shift is logical if
10523 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10524 we have an (le X 0) operation. If we have an arithmetic shift
10525 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10526 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10534 {
10537 const0_rtx);
10543 }
10545 /* If we have (shift (logical)), move the logical to the outside
10546 to allow it to possibly combine with another logical and the
10547 shift to combine with another shift. This also canonicalizes to
10548 what a ZERO_EXTRACT looks like. Also, some machines have
10549 (and (shift)) insns. */
10552 /* We can't do this if we have (ashiftrt (xor)) and the
10553 constant has its sign bit set in shift_mode with shift_mode
10554 wider than result_mode. */
10558 shift_mode))
10566 {
10569 }
10571 /* If we can't do that, try to simplify the shift in each arm of the
10572 logical expression, make a new logical expression, and apply
10573 the inverse distributive law. This also can't be done for
10574 (ashiftrt (xor)) where we've widened the shift and the constant
10575 changes the sign bit. */
10580 shift_mode)))
10581 {
10593 }
10597 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10598 says that the sign bit can be tested, FOO has mode MODE, C is
10599 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10600 that may be nonzero. */
10610 {
10614 }
10618 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10619 than the number of bits in the mode is equivalent to A. */
10623 {
10627 }
10629 /* NEG commutes with ASHIFT since it is multiplication. Move the
10630 NEG outside to allow shifts to combine. */
10634 {
10637 }
10641 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10642 is one less than the number of bits in the mode is
10643 equivalent to (xor A 1). */
10650 {
10654 }
10656 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10657 that might be nonzero in BAR are those being shifted out and those
10658 bits are known zero in FOO, we can replace the PLUS with FOO.
10659 Similarly in the other operand order. This code occurs when
10660 we are computing the size of a variable-size array. */
10667 {
10670 }
10678 result_mode)))
10679 {
10682 }
10684 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10694 {
10697 }
10699 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10700 signbit', and attempt to change the PLUS to an XOR and move it to
10701 the outer operation as is done above in the AND/IOR/XOR case
10702 leg for shift(logical). See details in logical handling above
10703 for reasoning in doing so. */
10714 {
10717 }
10722 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10723 with C the size of VAROP - 1 and the shift is logical if
10724 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10725 we have a (gt X 0) operation. If the shift is arithmetic with
10726 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10727 we have a (neg (gt X 0)) operation. */
10736 {
10739 const0_rtx);
10745 }
10749 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10750 if the truncate does not affect the value. */
10757 {
10760 varop_inner
10763 GEN_INT
10768 }
10773 }
10776 }
10781 /* We have now finished analyzing the shift. The result should be
10782 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10783 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10784 to the result of the shift. OUTER_CONST is the relevant constant,
10785 but we must turn off all bits turned off in the shift. */
10793 /* Make a SUBREG if necessary. If we can't make it, fail. */
10798 /* If we have an outer operation and we just made a shift, it is
10799 possible that we could have simplified the shift were it not
10800 for the outer operation. So try to do the simplification
10801 recursively. */
10805 else
10811 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10812 turn off all the bits that the shift would have turned off. */
10817 /* Do the remainder of the processing in RESULT_MODE. */
10820 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10821 operation. */
10826 {
10834 {
10835 /* This means that we have determined that the result is
10836 equivalent to a constant. This should be rare. */
10839 }
10842 else
10845 }
10848 }
10850 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10851 The result of the shift is RESULT_MODE. If we cannot simplify it,
10852 return X or, if it is NULL, synthesize the expression with
10853 simplify_gen_binary. Otherwise, return a simplified value.
10855 The shift is normally computed in the widest mode we find in VAROP, as
10856 long as it isn't a different number of words than RESULT_MODE. Exceptions
10857 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10859 static rtx
10862 {
10872 }
10874 \f
10875 /* A subroutine of recog_for_combine. See there for arguments and
10876 return value. */
10878 static int
10880 {
10882 rtx pat_without_clobbers;
10890 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10891 we use to indicate that something didn't match. If we find such a
10892 thing, force rejection. */
10906 {
10909 else
10912 }
10914 /* If it isn't, there is the possibility that we previously had an insn
10915 that clobbered some register as a side effect, but the combined
10916 insn doesn't need to do that. So try once more without the clobbers
10917 unless this represents an ASM insn. */
10921 {
10926 {
10929 pos++;
10930 }
10940 {
10943 else
10946 }
10947 }
10954 /* Recognize all noop sets, these will be killed by followup pass. */
10958 /* If we had any clobbers to add, make a new pattern than contains
10959 them. Then check to make sure that all of them are dead. */
10961 {
10971 else
10978 {
10983 {
10987 }
10988 }
10990 }
10994 {
11001 /* Allow targets to reject combined insn. */
11003 {
11006 dump_file);
11008 /* Callers expect recog_for_combine to strip
11009 clobbers from the pattern on failure. */
11014 }
11019 }
11025 }
11027 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11028 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11029 Return whether anything was so changed. */
11031 static bool
11033 {
11038 {
11047 {
11055 }
11060 {
11063 }
11064 else
11069 mask--;
11075 }
11078 }
11080 /* Like recog, but we receive the address of a pointer to a new pattern.
11081 We try to match the rtx that the pointer points to.
11082 If that fails, we may try to modify or replace the pattern,
11083 storing the replacement into the same pointer object.
11085 Modifications include deletion or addition of CLOBBERs. If the
11086 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11087 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11088 (and undo if that fails).
11090 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11091 the CLOBBERs are placed.
11093 The value is the final insn code from the pattern ultimately matched,
11094 or -1. */
11096 static int
11098 {
11110 {
11113 {
11117 }
11118 }
11121 {
11126 }
11129 }
11130 \f
11131 /* Like gen_lowpart_general but for use by combine. In combine it
11132 is not possible to create any new pseudoregs. However, it is
11133 safe to create invalid memory addresses, because combine will
11134 try to recognize them and all they will do is make the combine
11135 attempt fail.
11137 If for some reason this cannot do its job, an rtx
11138 (clobber (const_int 0)) is returned.
11139 An insn containing that will not be recognized. */
11141 static rtx
11143 {
11147 rtx result;
11152 /* We can only support MODE being wider than a word if X is a
11153 constant integer or has a mode the same size. */
11158 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11159 won't know what to do. So we will strip off the SUBREG here and
11160 process normally. */
11162 {
11165 /* For use in case we fall down into the address adjustments
11166 further below, we need to adjust the known mode and size of
11167 x; imode and isize, since we just adjusted x. */
11174 }
11182 {
11185 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11186 address. */
11191 /* If we want to refer to something bigger than the original memref,
11192 generate a paradoxical subreg instead. That will force a reload
11193 of the original memref X. */
11200 /* Adjust the address so that the address-after-the-data is
11201 unchanged. */
11206 }
11208 /* If X is a comparison operator, rewrite it in a new mode. This
11209 probably won't match, but may allow further simplifications. */
11213 /* If we couldn't simplify X any other way, just enclose it in a
11214 SUBREG. Normally, this SUBREG won't match, but some patterns may
11215 include an explicit SUBREG or we may simplify it further in combine. */
11216 else
11217 {
11219 rtx res;
11223 {
11228 }
11232 }
11234 fail:
11236 }
11237 \f
11238 /* Try to simplify a comparison between OP0 and a constant OP1,
11239 where CODE is the comparison code that will be tested, into a
11240 (CODE OP0 const0_rtx) form.
11242 The result is a possibly different comparison code to use.
11243 *POP1 may be updated. */
11245 static enum rtx_code
11248 {
11252 /* Get the constant we are comparing against and turn off all bits
11253 not on in our mode. */
11257 /* If we are comparing against a constant power of two and the value
11258 being compared can only have that single bit nonzero (e.g., it was
11259 `and'ed with that bit), we can replace this with a comparison
11260 with zero. */
11268 {
11271 }
11273 /* Similarly, if we are comparing a value known to be either -1 or
11274 0 with -1, change it to the opposite comparison against zero. */
11279 {
11282 }
11284 /* Do some canonicalizations based on the comparison code. We prefer
11285 comparisons against zero and then prefer equality comparisons.
11286 If we can reduce the size of a constant, we will do that too. */
11288 {
11290 /* < C is equivalent to <= (C - 1) */
11292 {
11295 /* ... fall through to LE case below. */
11296 }
11297 else
11301 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11303 {
11306 }
11308 /* If we are doing a <= 0 comparison on a value known to have
11309 a zero sign bit, we can replace this with == 0. */
11319 /* >= C is equivalent to > (C - 1). */
11321 {
11324 /* ... fall through to GT below. */
11325 }
11326 else
11330 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11332 {
11335 }
11337 /* If we are doing a > 0 comparison on a value known to have
11338 a zero sign bit, we can replace this with != 0. */
11348 /* < C is equivalent to <= (C - 1). */
11350 {
11353 /* ... fall through ... */
11354 }
11355 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11359 {
11363 }
11364 else
11368 /* unsigned <= 0 is equivalent to == 0 */
11371 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11375 {
11378 }
11382 /* >= C is equivalent to > (C - 1). */
11384 {
11387 /* ... fall through ... */
11388 }
11390 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11394 {
11398 }
11399 else
11403 /* unsigned > 0 is equivalent to != 0 */
11406 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11410 {
11413 }
11418 }
11422 }
11423 \f
11424 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11425 comparison code that will be tested.
11427 The result is a possibly different comparison code to use. *POP0 and
11428 *POP1 may be updated.
11430 It is possible that we might detect that a comparison is either always
11431 true or always false. However, we do not perform general constant
11432 folding in combine, so this knowledge isn't useful. Such tautologies
11433 should have been detected earlier. Hence we ignore all such cases. */
11435 static enum rtx_code
11437 {
11444 /* Try a few ways of applying the same transformation to both operands. */
11446 {
11447 #ifndef WORD_REGISTER_OPERATIONS
11448 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11449 so check specially. */
11464 - (GET_MODE_PRECISION
11466 {
11469 }
11470 #endif
11472 /* If both operands are the same constant shift, see if we can ignore the
11473 shift. We can if the shift is a rotate or if the bits shifted out of
11474 this shift are known to be zero for both inputs and if the type of
11475 comparison is compatible with the shift. */
11488 {
11501 else
11503 }
11505 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11506 SUBREGs are of the same mode, and, in both cases, the AND would
11507 be redundant if the comparison was done in the narrower mode,
11508 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11509 and the operand's possibly nonzero bits are 0xffffff01; in that case
11510 if we only care about QImode, we don't need the AND). This case
11511 occurs if the output mode of an scc insn is not SImode and
11512 STORE_FLAG_VALUE == 1 (e.g., the 386).
11514 Similarly, check for a case where the AND's are ZERO_EXTEND
11515 operations from some narrower mode even though a SUBREG is not
11516 present. */
11521 {
11538 {
11542 /* The resulting comparison is always unsigned since we masked
11543 off the original sign bit. */
11547 }
11554 {
11560 }
11564 }
11566 /* If both operands are NOT, we can strip off the outer operation
11567 and adjust the comparison code for swapped operands; similarly for
11568 NEG, except that this must be an equality comparison. */
11574 else
11576 }
11578 /* If the first operand is a constant, swap the operands and adjust the
11579 comparison code appropriately, but don't do this if the second operand
11580 is already a constant integer. */
11582 {
11585 }
11587 /* We now enter a loop during which we will try to simplify the comparison.
11588 For the most part, we only are concerned with comparisons with zero,
11589 but some things may really be comparisons with zero but not start
11590 out looking that way. */
11593 {
11600 HOST_WIDE_INT const_op;
11602 /* We only want to handle integral modes. This catches VOIDmode,
11603 CCmode, and the floating-point modes. An exception is that we
11604 can handle VOIDmode if OP0 is a COMPARE or a comparison
11605 operation. */
11612 /* Try to simplify the compare to constant, possibly changing the
11613 comparison op, and/or changing op1 to zero. */
11617 /* Compute some predicates to simplify code below. */
11624 /* If this is a sign bit comparison and we can do arithmetic in
11625 MODE, say that we will only be needing the sign bit of OP0. */
11632 /* Now try cases based on the opcode of OP0. If none of the cases
11633 does a "continue", we exit this loop immediately after the
11634 switch. */
11637 {
11639 /* If we are extracting a single bit from a variable position in
11640 a constant that has only a single bit set and are comparing it
11641 with zero, we can convert this into an equality comparison
11642 between the position and the location of the single bit. */
11643 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11644 have already reduced the shift count modulo the word size. */
11650 {
11658 /* Result is nonzero iff shift count is equal to I. */
11661 }
11663 /* ... fall through ... */
11668 {
11671 }
11675 /* If testing for equality, we can take the NOT of the constant. */
11678 {
11682 }
11684 /* If just looking at the sign bit, reverse the sense of the
11685 comparison. */
11687 {
11691 }
11695 /* If testing for equality, we can take the NEG of the constant. */
11698 {
11702 }
11704 /* The remaining cases only apply to comparisons with zero. */
11708 /* When X is ABS or is known positive,
11709 (neg X) is < 0 if and only if X != 0. */
11717 {
11721 }
11723 /* If we have NEG of something whose two high-order bits are the
11724 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11726 {
11730 }
11734 /* If we are testing equality and our count is a constant, we
11735 can perform the inverse operation on our RHS. */
11739 {
11743 }
11745 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11746 a particular bit. Convert it to an AND of a constant of that
11747 bit. This will be converted into a ZERO_EXTRACT. */
11751 {
11758 }
11760 /* Fall through. */
11763 /* ABS is ignorable inside an equality comparison with zero. */
11765 {
11768 }
11772 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11773 (compare FOO CONST) if CONST fits in FOO's mode and we
11774 are either testing inequality or have an unsigned
11775 comparison with ZERO_EXTEND or a signed comparison with
11776 SIGN_EXTEND. But don't do it if we don't have a compare
11777 insn of the given mode, since we'd have to revert it
11778 later on, and then we wouldn't know whether to sign- or
11779 zero-extend. */
11782 && ! unsigned_comparison_p
11786 {
11789 }
11793 /* Check for the case where we are comparing A - C1 with C2, that is
11795 (subreg:MODE (plus (A) (-C1))) op (C2)
11797 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11798 comparison in the wider mode. One of the following two conditions
11799 must be true in order for this to be valid:
11801 1. The mode extension results in the same bit pattern being added
11802 on both sides and the comparison is equality or unsigned. As
11803 C2 has been truncated to fit in MODE, the pattern can only be
11804 all 0s or all 1s.
11806 2. The mode extension results in the sign bit being copied on
11807 each side.
11809 The difficulty here is that we have predicates for A but not for
11810 (A - C1) so we need to check that C1 is within proper bounds so
11811 as to perturbate A as little as possible. */
11818 {
11827 /* (A - C1) zero-extends if it is positive and sign-extends
11828 if it is negative, C2 both zero- and sign-extends. */
11832 /* (A - C1) sign-extends if it is positive and 1-extends
11833 if it is negative, C2 both sign- and 1-extends. */
11840 /* (A - C1) always sign-extends, like C2. */
11844 {
11847 }
11848 }
11850 /* If the inner mode is narrower and we are extracting the low part,
11851 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11855 else
11858 /* ... fall through ... */
11868 {
11871 }
11875 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11876 this for equality comparisons due to pathological cases involving
11877 overflows. */
11881 {
11885 }
11887 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11890 {
11894 }
11898 /* We used to optimize signed comparisons against zero, but that
11899 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11900 arrive here as equality comparisons, or (GEU, LTU) are
11901 optimized away. No need to special-case them. */
11903 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11904 (eq B (minus A C)), whichever simplifies. We can only do
11905 this for equality comparisons due to pathological cases involving
11906 overflows. */
11910 {
11914 }
11919 {
11923 }
11925 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11926 of bits in X minus 1, is one iff X > 0. */
11931 {
11935 }
11939 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11940 if C is zero or B is a constant. */
11944 {
11948 }
11956 /* We can't do anything if OP0 is a condition code value, rather
11957 than an actual data value. */
11963 /* Get the two operands being compared. */
11966 else
11969 /* Check for the cases where we simply want the result of the
11970 earlier test or the opposite of that result. */
11974 {
11978 else
11982 {
11987 }
11988 }
11992 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11993 iff X <= 0. */
11997 {
12001 }
12005 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12006 will be converted to a ZERO_EXTRACT later. */
12010 {
12015 }
12017 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12018 zero and X is a comparison and C1 and C2 describe only bits set
12019 in STORE_FLAG_VALUE, we can compare with X. */
12027 {
12034 {
12037 }
12038 }
12040 /* If we are doing an equality comparison of an AND of a bit equal
12041 to the sign bit, replace this with a LT or GE comparison of
12042 the underlying value. */
12049 {
12053 }
12055 /* If this AND operation is really a ZERO_EXTEND from a narrower
12056 mode, the constant fits within that mode, and this is either an
12057 equality or unsigned comparison, try to do this comparison in
12058 the narrower mode.
12060 Note that in:
12062 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12063 -> (ne:DI (reg:SI 4) (const_int 0))
12065 unless TRULY_NOOP_TRUNCATION allows it or the register is
12066 known to hold a value of the required mode the
12067 transformation is invalid. */
12078 {
12081 }
12083 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
12084 fits in both M1 and M2 and the SUBREG is either paradoxical
12085 or represents the low part, permute the SUBREG and the AND
12086 and try again. */
12088 {
12091 /* Require an integral mode, to avoid creating something like
12092 (AND:SF ...). */
12094 /* It is unsafe to commute the AND into the SUBREG if the
12095 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12096 not defined. As originally written the upper bits
12097 have a defined value due to the AND operation.
12098 However, if we commute the AND inside the SUBREG then
12099 they no longer have defined values and the meaning of
12100 the code has been changed. */
12102 #ifdef WORD_REGISTER_OPERATIONS
12105 #endif
12115 {
12121 }
12122 }
12124 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12128 {
12133 }
12135 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12136 (eq (and (lshiftrt X) 1) 0).
12137 Also handle the case where (not X) is expressed using xor. */
12141 {
12153 {
12154 op0
12159 }
12160 }
12164 /* If we have (compare (ashift FOO N) (const_int C)) and
12165 the high order N bits of FOO (N+1 if an inequality comparison)
12166 are known to be zero, we can do this by comparing FOO with C
12167 shifted right N bits so long as the low-order N bits of C are
12168 zero. */
12180 {
12181 /* We must perform a logical shift, not an arithmetic one,
12182 as we want the top N bits of C to be zero. */
12189 }
12191 /* If we are doing a sign bit comparison, it means we are testing
12192 a particular bit. Convert it to the appropriate AND. */
12195 {
12202 }
12204 /* If this an equality comparison with zero and we are shifting
12205 the low bit to the sign bit, we can convert this to an AND of the
12206 low-order bit. */
12210 {
12213 }
12217 /* If this is an equality comparison with zero, we can do this
12218 as a logical shift, which might be much simpler. */
12221 {
12226 }
12228 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12229 do the comparison in a narrower mode. */
12239 {
12242 }
12244 /* Likewise if OP0 is a PLUS of a sign extension with a
12245 constant, which is usually represented with the PLUS
12246 between the shifts. */
12258 {
12266 new_const);
12268 }
12270 /* ... fall through ... */
12272 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12273 the low order N bits of FOO are known to be zero, we can do this
12274 by comparing FOO with C shifted left N bits so long as no
12275 overflow occurs. Even if the low order N bits of FOO aren't known
12276 to be zero, if the comparison is >= or < we can use the same
12277 optimization and for > or <= by setting all the low
12278 order N bits in the comparison constant. */
12289 {
12290 unsigned HOST_WIDE_INT low_bits
12295 {
12296 /* If the shift was logical, then we must make the condition
12297 unsigned. */
12305 const_op
12310 }
12311 }
12313 /* If we are using this shift to extract just the sign bit, we
12314 can replace this with an LT or GE comparison. */
12319 {
12323 }
12328 }
12331 }
12333 /* Now make any compound operations involved in this comparison. Then,
12334 check for an outmost SUBREG on OP0 that is not doing anything or is
12335 paradoxical. The latter transformation must only be performed when
12336 it is known that the "extra" bits will be the same in op0 and op1 or
12337 that they don't matter. There are three cases to consider:
12339 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12340 care bits and we can assume they have any convenient value. So
12341 making the transformation is safe.
12343 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12344 In this case the upper bits of op0 are undefined. We should not make
12345 the simplification in that case as we do not know the contents of
12346 those bits.
12348 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12349 UNKNOWN. In that case we know those bits are zeros or ones. We must
12350 also be sure that they are the same as the upper bits of op1.
12352 We can never remove a SUBREG for a non-equality comparison because
12353 the sign bit is in a different place in the underlying object. */
12362 {
12364 {
12365 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12366 implemented. */
12368 {
12371 }
12372 }
12378 {
12384 }
12385 }
12387 /* We now do the opposite procedure: Some machines don't have compare
12388 insns in all modes. If OP0's mode is an integer mode smaller than a
12389 word and we can't do a compare in that mode, see if there is a larger
12390 mode for which we can do the compare. There are a number of cases in
12391 which we can use the wider mode. */
12401 {
12404 /* If this is a test for negative, we can make an explicit
12405 test of the sign bit. Test this first so we can use
12406 a paradoxical subreg to extend OP0. */
12410 {
12411 unsigned HOST_WIDE_INT sign
12418 }
12420 /* If the only nonzero bits in OP0 and OP1 are those in the
12421 narrower mode and this is an equality or unsigned comparison,
12422 we can use the wider mode. Similarly for sign-extended
12423 values, in which case it is true for all comparisons. */
12440 {
12441 /* If OP0 is an AND and we don't have an AND in MODE either,
12442 make a new AND in the proper mode. */
12450 else
12451 {
12453 {
12456 }
12457 else
12458 {
12461 }
12463 }
12464 }
12465 }
12467 /* We may have changed the comparison operands. Re-canonicalize. */
12469 {
12472 }
12474 /* If this machine only supports a subset of valid comparisons, see if we
12475 can convert an unsupported one into a supported one. */
12482 }
12483 \f
12484 /* Utility function for record_value_for_reg. Count number of
12485 rtxs in X. */
12486 static int
12488 {
12495 {
12515 }
12526 }
12527 \f
12528 /* Utility function for following routine. Called when X is part of a value
12529 being stored into last_set_value. Sets last_set_table_tick
12530 for each register mentioned. Similar to mention_regs in cse.c */
12532 static void
12534 {
12540 {
12546 {
12549 }
12552 }
12556 {
12557 /* Check for identical subexpressions. If x contains
12558 identical subexpression we only have to traverse one of
12559 them. */
12561 {
12562 /* Note that at this point x1 has already been
12563 processed. */
12567 /* If x0 and x1 are identical then there is no need to
12568 process x0. */
12572 /* If x0 is identical to a subexpression of x1 then while
12573 processing x1, x0 has already been processed. Thus we
12574 are done with x. */
12579 /* If x1 is identical to a subexpression of x0 then we
12580 still have to process the rest of x0. */
12583 {
12586 }
12587 }
12590 }
12594 }
12596 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12597 are saying that the register is clobbered and we no longer know its
12598 value. If INSN is zero, don't update reg_stat[].last_set; this is
12599 only permitted with VALUE also zero and is used to invalidate the
12600 register. */
12602 static void
12604 {
12610 /* If VALUE contains REG and we have a previous value for REG, substitute
12611 the previous value. */
12613 {
12614 rtx tem;
12616 /* Set things up so get_last_value is allowed to see anything set up to
12617 our insn. */
12621 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12622 it isn't going to be useful and will take a lot of time to process,
12623 so just use the CLOBBER. */
12626 {
12632 {
12633 /* If there are two or more occurrences of REG in VALUE,
12634 prevent the value from growing too much. */
12637 }
12640 }
12641 }
12643 /* For each register modified, show we don't know its value, that
12644 we don't know about its bitwise content, that its value has been
12645 updated, and that we don't know the location of the death of the
12646 register. */
12648 {
12660 }
12662 /* Mark registers that are being referenced in this value. */
12666 /* Now update the status of each register being set.
12667 If someone is using this register in this block, set this register
12668 to invalid since we will get confused between the two lives in this
12669 basic block. This makes using this register always invalid. In cse, we
12670 scan the table to invalidate all entries using this register, but this
12671 is too much work for us. */
12674 {
12680 else
12682 }
12684 /* The value being assigned might refer to X (like in "x++;"). In that
12685 case, we must replace it with (clobber (const_int 0)) to prevent
12686 infinite loops. */
12689 {
12693 }
12695 /* For the main register being modified, update the value, the mode, the
12696 nonzero bits, and the number of sign bit copies. */
12701 {
12709 rsp->last_set_sign_bit_copies
12711 }
12712 }
12714 /* Called via note_stores from record_dead_and_set_regs to handle one
12715 SET or CLOBBER in an insn. DATA is the instruction in which the
12716 set is occurring. */
12718 static void
12720 {
12727 {
12731 }
12734 {
12735 /* If we are setting the whole register, we know its value. Otherwise
12736 show that we don't know the value. We can handle SUBREG in
12737 some cases. */
12748 else
12750 }
12752 /* Ignore pushes, they clobber nothing. */
12755 }
12757 /* Update the records of when each REG was most recently set or killed
12758 for the things done by INSN. This is the last thing done in processing
12759 INSN in the combiner loop.
12761 We update reg_stat[], in particular fields last_set, last_set_value,
12762 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12763 last_death, and also the similar information mem_last_set (which insn
12764 most recently modified memory) and last_call_luid (which insn was the
12765 most recent subroutine call). */
12767 static void
12769 {
12770 rtx link;
12774 {
12777 {
12782 {
12787 }
12788 }
12791 }
12794 {
12795 hard_reg_set_iterator hrsi;
12797 {
12809 }
12813 /* We can't combine into a call pattern. Remember, though, that
12814 the return value register is set at this LUID. We could
12815 still replace a register with the return value from the
12816 wrong subroutine call! */
12818 }
12819 else
12821 }
12823 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12824 register present in the SUBREG, so for each such SUBREG go back and
12825 adjust nonzero and sign bit information of the registers that are
12826 known to have some zero/sign bits set.
12828 This is needed because when combine blows the SUBREGs away, the
12829 information on zero/sign bits is lost and further combines can be
12830 missed because of that. */
12832 static void
12834 {
12836 rtx set;
12844 {
12853 {
12856 }
12860 {
12863 }
12866 {
12869 }
12870 else
12872 }
12873 }
12875 /* Check if X, a register, is known to contain a value already
12876 truncated to MODE. In this case we can use a subreg to refer to
12877 the truncated value even though in the generic case we would need
12878 an explicit truncation. */
12880 static bool
12882 {
12894 }
12896 /* If X is a hard reg or a subreg record the mode that the register is
12897 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12898 to turn a truncate into a subreg using this information. Return true
12899 if traversing X is complete. */
12901 static bool
12903 {
12904 machine_mode truncated_mode;
12908 {
12919 }
12920 /* ??? For hard-regs we now record everything. We might be able to
12921 optimize this using last_set_mode. */
12924 else
12932 {
12935 }
12938 }
12940 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12941 the modes they are used in. This can help truning TRUNCATEs into
12942 SUBREGs. */
12944 static void
12946 {
12951 }
12953 /* Scan X for promoted SUBREGs. For each one found,
12954 note what it implies to the registers used in it. */
12956 static void
12958 {
12963 else
12964 {
12970 {
12980 }
12981 }
12982 }
12983 \f
12984 /* Verify that all the registers and memory references mentioned in *LOC are
12985 still valid. *LOC was part of a value set in INSN when label_tick was
12986 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12987 the invalid references with (clobber (const_int 0)) and return 1. This
12988 replacement is useful because we often can get useful information about
12989 the form of a value (e.g., if it was produced by a shift that always
12990 produces -1 or 0) even though we don't know exactly what registers it
12991 was produced from. */
12993 static int
12995 {
13002 {
13008 {
13011 /* If this is a pseudo-register that was only set once and not
13012 live at the beginning of the function, it is always valid. */
13016 && (!REGNO_REG_SET_P
13018 regno)))
13020 {
13024 }
13025 }
13028 }
13029 /* If this is a memory reference, make sure that there were no stores after
13030 it that might have clobbered the value. We don't have alias info, so we
13031 assume any store invalidates it. Moreover, we only have local UIDs, so
13032 we also assume that there were stores in the intervening basic blocks. */
13035 {
13039 }
13042 {
13044 {
13045 /* Check for identical subexpressions. If x contains
13046 identical subexpression we only have to traverse one of
13047 them. */
13049 {
13050 /* Note that at this point x0 has already been checked
13051 and found valid. */
13055 /* If x0 and x1 are identical then x is also valid. */
13059 /* If x1 is identical to a subexpression of x0 then
13060 while checking x0, x1 has already been checked. Thus
13061 it is valid and so as x. */
13066 /* If x0 is identical to a subexpression of x1 then x is
13067 valid iff the rest of x1 is valid. */
13070 return
13074 }
13079 }
13085 }
13087 /* If we haven't found a reason for it to be invalid, it is valid. */
13089 }
13091 /* Get the last value assigned to X, if known. Some registers
13092 in the value may be replaced with (clobber (const_int 0)) if their value
13093 is known longer known reliably. */
13095 static rtx
13097 {
13099 rtx value;
13102 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13103 then convert it to the desired mode. If this is a paradoxical SUBREG,
13104 we cannot predict what values the "extra" bits might have. */
13118 /* If we don't have a value, or if it isn't for this basic block and
13119 it's either a hard register, set more than once, or it's a live
13120 at the beginning of the function, return 0.
13122 Because if it's not live at the beginning of the function then the reg
13123 is always set before being used (is never used without being set).
13124 And, if it's set only once, and it's always set before use, then all
13125 uses must have the same last value, even if it's not from this basic
13126 block. */
13133 || REGNO_REG_SET_P
13137 /* If the value was set in a later insn than the ones we are processing,
13138 we can't use it even if the register was only set once. */
13143 /* If the value has all its registers valid, return it. */
13147 /* Otherwise, make a copy and replace any invalid register with
13148 (clobber (const_int 0)). If that fails for some reason, return 0. */
13155 }
13156 \f
13157 /* Return nonzero if expression X refers to a REG or to memory
13158 that is set in an instruction more recent than FROM_LUID. */
13160 static int
13162 {
13168 {
13172 #ifdef PUSH_ROUNDING
13173 /* Don't allow uses of the stack pointer to be moved,
13174 because we don't know whether the move crosses a push insn. */
13177 #endif
13179 {
13185 }
13187 }
13195 {
13197 {
13202 }
13206 }
13208 }
13209 \f
13210 /* Define three variables used for communication between the following
13211 routines. */
13216 /* Function called via note_stores from reg_dead_at_p.
13218 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13219 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13221 static void
13223 {
13233 }
13235 /* Return nonzero if REG is known to be dead at INSN.
13237 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13238 referencing REG, it is dead. If we hit a SET referencing REG, it is
13239 live. Otherwise, see if it is live or dead at the start of the basic
13240 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13241 must be assumed to be always live. */
13243 static int
13245 {
13246 basic_block block;
13249 /* Set variables for reg_dead_at_p_1. */
13255 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13256 we allow the machine description to decide whether use-and-clobber
13257 patterns are OK. */
13259 {
13263 }
13265 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13266 beginning of basic block. */
13269 {
13271 {
13281 }
13287 }
13289 /* Look at live-in sets for the basic block that we were in. */
13295 }
13296 \f
13297 /* Note hard registers in X that are used. */
13299 static void
13301 {
13307 {
13311 CASE_CONST_ANY:
13316 /* CC0 must die in the insn after it is set, so we don't need to take
13317 special note of it here. */
13322 /* If we are clobbering a MEM, mark any hard registers inside the
13323 address as used. */
13330 /* A hard reg in a wide mode may really be multiple registers.
13331 If so, mark all of them just like the first. */
13333 {
13334 /* None of this applies to the stack, frame or arg pointers. */
13336 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
13338 #endif
13345 }
13349 {
13350 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13351 the address. */
13363 }
13368 }
13370 /* Recursively scan the operands of this expression. */
13372 {
13376 {
13380 {
13385 }
13386 }
13387 }
13388 }
13389 \f
13390 /* Remove register number REGNO from the dead registers list of INSN.
13392 Return the note used to record the death, if there was one. */
13394 rtx
13396 {
13403 }
13405 /* For each register (hardware or pseudo) used within expression X, if its
13406 death is in an instruction with luid between FROM_LUID (inclusive) and
13407 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13408 list headed by PNOTES.
13410 That said, don't move registers killed by maybe_kill_insn.
13412 This is done when X is being merged by combination into TO_INSN. These
13413 notes will then be distributed as needed. */
13415 static void
13418 {
13424 {
13428 /* Don't move the register if it gets killed in between from and to. */
13437 {
13440 /* It is possible for the call above to return 0. This can occur
13441 when last_death points to I2 or I1 that we combined with.
13442 In that case make a new note.
13444 We must also check for the case where X is a hard register
13445 and NOTE is a death note for a range of hard registers
13446 including X. In that case, we must put REG_DEAD notes for
13447 the remaining registers in place of NOTE. */
13452 {
13461 }
13463 /* If we didn't find any note, or if we found a REG_DEAD note that
13464 covers only part of the given reg, and we have a multi-reg hard
13465 register, then to be safe we must check for REG_DEAD notes
13466 for each register other than the first. They could have
13467 their own REG_DEAD notes lying around. */
13474 {
13481 else
13487 }
13490 {
13493 }
13494 else
13496 }
13499 }
13502 {
13507 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13508 that accesses one word of a multi-word item, some
13509 piece of everything register in the expression is used by
13510 this insn, so remove any old death. */
13511 /* ??? So why do we test for equality of the sizes? */
13520 {
13523 }
13525 /* If this is some other SUBREG, we know it replaces the entire
13526 value, so use that as the destination. */
13530 /* If this is a MEM, adjust deaths of anything used in the address.
13531 For a REG (the only other possibility), the entire value is
13532 being replaced so the old value is not used in this insn. */
13538 }
13547 {
13549 {
13554 }
13557 }
13558 }
13559 \f
13560 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13561 pattern of an insn. X must be a REG. */
13563 static int
13565 {
13569 {
13571 rtx target;
13578 else
13595 }
13603 }
13604 \f
13605 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13606 as appropriate. I3 and I2 are the insns resulting from the combination
13607 insns including FROM (I2 may be zero).
13609 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13610 not need REG_DEAD notes because they are being substituted for. This
13611 saves searching in the most common cases.
13613 Each note in the list is either ignored or placed on some insns, depending
13614 on the type of note. */
13616 static void
13619 {
13621 rtx tem_note;
13625 {
13630 {
13633 /* Doesn't matter much where we put this, as long as it's somewhere.
13634 It is preferable to keep these notes on branches, which is most
13635 likely to be i3. */
13642 else
13643 {
13646 }
13650 /* These notes must remain with the call or trapping instruction. */
13655 else
13656 {
13662 /* ??? Otherwise assume we've combined things such that we
13663 can now prove that the instructions can't trap. Drop the
13664 note in this case. */
13665 }
13669 /* ??? How to distribute between i3-i1. Assume i3 contains the
13670 entire adjustment. Assert i3 contains at least some adjust. */
13672 {
13674 /* fixup_args_size_notes looks at REG_NORETURN note,
13675 so ensure the note is placed there first. */
13677 {
13681 {
13687 }
13688 }
13690 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13691 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13694 && !ACCUMULATE_OUTGOING_ARGS
13696 }
13703 /* These notes must remain with the call. It should not be
13704 possible for both I2 and I3 to be a call. */
13707 else
13708 {
13711 }
13715 /* Any clobbers for i3 may still exist, and so we must process
13716 REG_UNUSED notes from that insn.
13718 Any clobbers from i2 or i1 can only exist if they were added by
13719 recog_for_combine. In that case, recog_for_combine created the
13720 necessary REG_UNUSED notes. Trying to keep any original
13721 REG_UNUSED notes from these insns can cause incorrect output
13722 if it is for the same register as the original i3 dest.
13723 In that case, we will notice that the register is set in i3,
13724 and then add a REG_UNUSED note for the destination of i3, which
13725 is wrong. However, it is possible to have REG_UNUSED notes from
13726 i2 or i1 for register which were both used and clobbered, so
13727 we keep notes from i2 or i1 if they will turn into REG_DEAD
13728 notes. */
13730 /* If this register is set or clobbered in I3, put the note there
13731 unless there is one already. */
13733 {
13741 }
13742 /* Otherwise, if this register is used by I3, then this register
13743 now dies here, so we must put a REG_DEAD note here unless there
13744 is one already. */
13750 {
13753 }
13759 /* These notes say something about results of an insn. We can
13760 only support them if they used to be on I3 in which case they
13761 remain on I3. Otherwise they are ignored.
13763 If the note refers to an expression that is not a constant, we
13764 must also ignore the note since we cannot tell whether the
13765 equivalence is still true. It might be possible to do
13766 slightly better than this (we only have a problem if I2DEST
13767 or I1DEST is present in the expression), but it doesn't
13768 seem worth the trouble. */
13776 /* These notes say something about how a register is used. They must
13777 be present on any use of the register in I2 or I3. */
13782 {
13785 else
13787 }
13792 /* This can show up in several ways -- either directly in the
13793 pattern, or hidden off in the constant pool with (or without?)
13794 a REG_EQUAL note. */
13795 /* ??? Ignore the without-reg_equal-note problem for now. */
13807 {
13810 else
13812 }
13814 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13815 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13816 there. */
13821 {
13828 }
13834 {
13842 }
13846 /* This note says something about the value of a register prior
13847 to the execution of an insn. It is too much trouble to see
13848 if the note is still correct in all situations. It is better
13849 to simply delete it. */
13853 /* If we replaced the right hand side of FROM_INSN with a
13854 REG_EQUAL note, the original use of the dying register
13855 will not have been combined into I3 and I2. In such cases,
13856 FROM_INSN is guaranteed to be the first of the combined
13857 instructions, so we simply need to search back before
13858 FROM_INSN for the previous use or set of this register,
13859 then alter the notes there appropriately.
13861 If the register is used as an input in I3, it dies there.
13862 Similarly for I2, if it is nonzero and adjacent to I3.
13864 If the register is not used as an input in either I3 or I2
13865 and it is not one of the registers we were supposed to eliminate,
13866 there are two possibilities. We might have a non-adjacent I2
13867 or we might have somehow eliminated an additional register
13868 from a computation. For example, we might have had A & B where
13869 we discover that B will always be zero. In this case we will
13870 eliminate the reference to A.
13872 In both cases, we must search to see if we can find a previous
13873 use of A and put the death note there. */
13879 else
13880 {
13891 && !(i2mod
13893 i2mod_old_rhs)))
13898 /* If the new I2 sets the same register that is marked dead
13899 in the note, the note now should not be put on I2, as the
13900 note refers to a previous incarnation of the reg. */
13903 }
13906 {
13910 {
13912 {
13916 }
13918 /* If the register is being set at TEM_INSN, see if that is all
13919 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13920 into a REG_UNUSED note instead. Don't delete sets to
13921 global register vars. */
13925 {
13936 ;
13938 /* Verify that it was the set, and not a clobber that
13939 modified the register.
13941 CC0 targets must be careful to maintain setter/user
13942 pairs. If we cannot delete the setter due to side
13943 effects, mark the user with an UNUSED note instead
13944 of deleting it. */
13948 #if HAVE_cc0
13952 #endif
13953 )
13954 {
13955 /* Move the notes and links of TEM_INSN elsewhere.
13956 This might delete other dead insns recursively.
13957 First set the pattern to something that won't use
13958 any register. */
13972 /* Delete the setter too. */
13974 {
13987 }
13988 }
13989 else
13990 {
13993 /* If there isn't already a REG_UNUSED note, put one
13994 here. Do not place a REG_DEAD note, even if
13995 the register is also used here; that would not
13996 match the algorithm used in lifetime analysis
13997 and can cause the consistency check in the
13998 scheduler to fail. */
14003 }
14004 }
14008 {
14011 /* If we are doing a 3->2 combination, and we have a
14012 register which formerly died in i3 and was not used
14013 by i2, which now no longer dies in i3 and is used in
14014 i2 but does not die in i2, and place is between i2
14015 and i3, then we may need to move a link from place to
14016 i2. */
14018 && from_insn
14021 {
14025 }
14027 }
14031 }
14033 }
14035 /* If the register is set or already dead at PLACE, we needn't do
14036 anything with this note if it is still a REG_DEAD note.
14037 We check here if it is set at all, not if is it totally replaced,
14038 which is what `dead_or_set_p' checks, so also check for it being
14039 set partially. */
14042 {
14048 {
14049 /* Unless the register previously died in PLACE, clear
14050 last_death. [I no longer understand why this is
14051 being done.] */
14055 }
14056 else
14059 /* If this is a death note for a hard reg that is occupying
14060 multiple registers, ensure that we are still using all
14061 parts of the object. If we find a piece of the object
14062 that is unused, we must arrange for an appropriate REG_DEAD
14063 note to be added for it. However, we can't just emit a USE
14064 and tag the note to it, since the register might actually
14065 be dead; so we recourse, and the recursive call then finds
14066 the previous insn that used this register. */
14069 {
14078 {
14081 }
14084 {
14085 /* Put only REG_DEAD notes for pieces that are
14086 not already dead or set. */
14090 {
14097 {
14099 NULL_RTX);
14103 NULL_RTX);
14104 }
14109 {
14111 {
14115 }
14119 {
14122 }
14123 }
14124 }
14127 }
14128 }
14129 }
14133 /* Any other notes should not be present at this point in the
14134 compilation. */
14136 }
14139 {
14142 }
14146 }
14147 }
14148 \f
14149 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14150 I3, I2, and I1 to new locations. This is also called to add a link
14151 pointing at I3 when I3's destination is changed. */
14153 static void
14155 {
14159 {
14166 /* If the insn that this link points to is a NOTE, ignore it. */
14175 {
14178 {
14194 }
14197 }
14198 else
14208 /* A LOG_LINK is defined as being placed on the first insn that uses
14209 a register and points to the insn that sets the register. Start
14210 searching at the next insn after the target of the link and stop
14211 when we reach a set of the register or the end of the basic block.
14213 Note that this correctly handles the link that used to point from
14214 I3 to I2. Also note that not much searching is typically done here
14215 since most links don't point very far away. */
14224 {
14228 }
14231 {
14234 }
14238 /* If we found a place to put the link, place it there unless there
14239 is already a link to the same insn as LINK at that point. */
14242 {
14250 {
14254 /* Set added_links_insn to the earliest insn we added a
14255 link to. */
14259 }
14260 }
14261 }
14262 }
14263 \f
14264 /* Check for any register or memory mentioned in EQUIV that is not
14265 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14266 of EXPR where some registers may have been replaced by constants. */
14268 static bool
14270 {
14273 {
14278 }
14280 }
14281 \f
14282 DEBUG_FUNCTION void
14284 {
14285 fprintf
14287 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14289 }
14291 void
14293 {
14294 fprintf
14296 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14298 }
14299 \f
14300 /* Try combining insns through substitution. */
14301 static unsigned int
14303 {
14313 rebuild_jump_labels_after_combine
14316 /* Combining insns may have turned an indirect jump into a
14317 direct jump. Rebuild the JUMP_LABEL fields of jumping
14318 instructions. */
14320 {
14325 }
14329 }
14334 {
14344 };
14347 {
14351 {}
14353 /* opt_pass methods: */
14356 {
14358 }
14364 rtl_opt_pass *
14366 {
14368 }