| blob | 6ef0cc7501840cb61104f973f9ab130477065cfe |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2018 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
24 #define INCLUDE_STRING
75 /* This file should be included last. */
78 /* Defined for convenience. */
79 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
81 /* Classifies an address.
83 ADDRESS_REG_IMM
84 A simple base register plus immediate offset.
86 ADDRESS_REG_WB
87 A base register indexed by immediate offset with writeback.
89 ADDRESS_REG_REG
90 A base register indexed by (optionally scaled) register.
92 ADDRESS_REG_UXTW
93 A base register indexed by (optionally scaled) zero-extended register.
95 ADDRESS_REG_SXTW
96 A base register indexed by (optionally scaled) sign-extended register.
98 ADDRESS_LO_SUM
99 A LO_SUM rtx with a base register and "LO12" symbol relocation.
101 ADDRESS_SYMBOLIC:
102 A constant symbolic address, in pc-relative literal pool. */
105 ADDRESS_REG_IMM,
106 ADDRESS_REG_WB,
107 ADDRESS_REG_REG,
108 ADDRESS_REG_UXTW,
109 ADDRESS_REG_SXTW,
110 ADDRESS_LO_SUM,
111 ADDRESS_SYMBOLIC
112 };
116 rtx base;
117 rtx offset;
118 poly_int64 const_offset;
121 };
123 /* Information about a legitimate vector immediate operand. */
124 struct simd_immediate_info
125 {
136 /* The mode of the elements. */
137 scalar_mode elt_mode;
139 /* The value of each element if all elements are the same, or the
140 first value if the constant is a series. */
141 rtx value;
143 /* The value of the step if the constant is a series, null otherwise. */
144 rtx step;
146 /* The instruction to use to move the immediate into a vector. */
147 insn_type insn;
149 /* The kind of shift modifier to use, and the number of bits to shift.
150 This is (LSL, 0) if no shift is needed. */
151 modifier_type modifier;
153 };
155 /* Construct a floating-point immediate in which each element has mode
156 ELT_MODE_IN and value VALUE_IN. */
157 inline simd_immediate_info
161 {}
163 /* Construct an integer immediate in which each element has mode ELT_MODE_IN
164 and value VALUE_IN. The other parameters are as for the structure
165 fields. */
166 inline simd_immediate_info
173 {}
175 /* Construct an integer immediate in which each element has mode ELT_MODE_IN
176 and where element I is equal to VALUE_IN + I * STEP_IN. */
177 inline simd_immediate_info
181 {}
183 /* The current code model. */
186 /* The number of 64-bit elements in an SVE vector. */
187 poly_uint16 aarch64_sve_vg;
189 #ifdef HAVE_AS_TLS
190 #undef TARGET_HAVE_TLS
191 #define TARGET_HAVE_TLS 1
192 #endif
196 const_tree,
205 const_tree type,
211 /* Major revision number of the ARM Architecture implemented by the target. */
214 /* The processor for which instructions should be scheduled. */
217 /* Mask to specify which instruction scheduling options should be used. */
220 /* Global flag for PC relative loads. */
223 /* Global flag for whether frame pointer is enabled. */
226 /* Support for command line parsing of boolean flags in the tuning
227 structures. */
228 struct aarch64_flag_desc
229 {
232 };
234 #define AARCH64_FUSION_PAIR(name, internal_name) \
235 { name, AARCH64_FUSE_##internal_name },
237 {
242 };
244 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
245 { name, AARCH64_EXTRA_TUNE_##internal_name },
247 {
252 };
254 /* Tuning parameters. */
257 {
258 {
263 },
270 };
273 {
274 {
279 },
286 };
289 {
290 {
295 },
302 };
305 {
306 {
311 },
318 };
321 {
322 {
327 },
334 };
337 {
339 /* Avoid the use of slow int<->fp moves for spilling by setting
340 their cost higher than memmov_cost. */
344 };
347 {
349 /* Avoid the use of slow int<->fp moves for spilling by setting
350 their cost higher than memmov_cost. */
354 };
357 {
359 /* Avoid the use of slow int<->fp moves for spilling by setting
360 their cost higher than memmov_cost. */
364 };
367 {
369 /* Avoid the use of slow int<->fp moves for spilling by setting
370 their cost higher than memmov_cost (actual, 4 and 9). */
374 };
377 {
382 };
385 {
387 /* Avoid the use of slow int<->fp moves for spilling by setting
388 their cost higher than memmov_cost. */
392 };
395 {
397 /* Avoid the use of int<->fp moves for spilling. */
401 };
404 {
406 /* Avoid the use of int<->fp moves for spilling. */
410 };
412 /* Generic costs for vector insn classes. */
414 {
430 };
432 /* ThunderX costs for vector insn classes. */
434 {
450 };
452 /* Generic costs for vector insn classes. */
454 {
470 };
473 {
489 };
491 /* Generic costs for vector insn classes. */
493 {
509 };
511 /* Costs for vector insn classes for Vulcan. */
513 {
529 };
531 /* Generic costs for branch instructions. */
533 {
536 };
538 /* Generic approximation modes. */
540 {
543 AARCH64_APPROX_NONE /* recip_sqrt */
544 };
546 /* Approximation modes for Exynos M1. */
548 {
551 AARCH64_APPROX_ALL /* recip_sqrt */
552 };
554 /* Approximation modes for X-Gene 1. */
556 {
559 AARCH64_APPROX_ALL /* recip_sqrt */
560 };
562 /* Generic prefetch settings (which disable prefetch). */
564 {
572 };
575 {
583 };
586 {
594 };
597 {
605 };
608 {
616 };
619 {
627 };
630 {
651 &generic_prefetch_tune
652 };
655 {
677 &generic_prefetch_tune
678 };
681 {
703 &generic_prefetch_tune
704 };
707 {
729 &generic_prefetch_tune
730 };
733 {
755 &generic_prefetch_tune
756 };
759 {
781 &generic_prefetch_tune
782 };
787 {
808 &exynosm1_prefetch_tune
809 };
812 {
833 &thunderxt88_prefetch_tune
834 };
837 {
857 (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW
859 &thunderx_prefetch_tune
860 };
863 {
884 &generic_prefetch_tune
885 };
888 {
910 &qdf24xx_prefetch_tune
911 };
913 /* Tuning structure for the Qualcomm Saphira core. Default to falkor values
914 for now. */
916 {
938 &generic_prefetch_tune
939 };
942 {
964 &thunderx2t99_prefetch_tune
965 };
967 /* Support for fine-grained override of the tuning structures. */
968 struct aarch64_tuning_override_function
969 {
972 };
977 static const struct aarch64_tuning_override_function
978 aarch64_tuning_override_functions[] =
979 {
983 };
985 /* A processor implementing AArch64. */
986 struct processor
987 {
995 };
997 /* Architectures implementing AArch64. */
999 {
1000 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
1001 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
1004 };
1006 /* Processor cores implementing AArch64. */
1008 {
1009 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
1010 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
1011 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
1012 FLAGS, &COSTS##_tunings},
1017 };
1020 /* Target specification. These are populated by the -march, -mtune, -mcpu
1021 handling code or by target attributes. */
1026 /* The current tuning set. */
1029 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
1031 /* An ISA extension in the co-processor and main instruction set space. */
1032 struct aarch64_option_extension
1033 {
1037 };
1040 {
1044 }
1045 aarch64_cc;
1047 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
1049 /* The condition codes of the processor, and the inverse function. */
1051 {
1054 };
1056 /* Generate code to enable conditional branches in functions over 1 MiB. */
1060 {
1077 }
1079 void
1081 {
1086 else
1089 else
1093 else
1096 }
1098 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
1099 The register allocator chooses POINTER_AND_FP_REGS if FP_REGS and
1100 GENERAL_REGS have the same cost - even if POINTER_AND_FP_REGS has a much
1101 higher cost. POINTER_AND_FP_REGS is also used if the cost of both FP_REGS
1102 and GENERAL_REGS is lower than the memory cost (in this case the best class
1103 is the lowest cost one). Using POINTER_AND_FP_REGS irrespectively of its
1104 cost results in bad allocations with many redundant int<->FP moves which
1105 are expensive on various cores.
1106 To avoid this we don't allow POINTER_AND_FP_REGS as the allocno class, but
1107 force a decision between FP_REGS and GENERAL_REGS. We use the allocno class
1108 if it isn't POINTER_AND_FP_REGS. Similarly, use the best class if it isn't
1109 POINTER_AND_FP_REGS. Otherwise set the allocno class depending on the mode.
1110 The result of this is that it is no longer inefficient to have a higher
1111 memory move cost than the register move cost.
1112 */
1114 static reg_class_t
1116 reg_class_t best_class)
1117 {
1118 machine_mode mode;
1130 }
1132 static unsigned int
1134 {
1138 }
1140 /* Return the reassociation width of treeop OPC with mode MODE. */
1141 static int
1143 {
1148 /* Avoid reassociating floating point addition so we emit more FMAs. */
1152 }
1154 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
1155 unsigned
1157 {
1169 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
1170 equivalent DWARF register. */
1172 }
1174 /* Return true if MODE is any of the Advanced SIMD structure modes. */
1175 static bool
1177 {
1180 }
1182 /* Return true if MODE is an SVE predicate mode. */
1183 static bool
1185 {
1191 }
1193 /* Three mutually-exclusive flags describing a vector or predicate type. */
1197 /* Can be used in combination with VEC_ADVSIMD or VEC_SVE_DATA to indicate
1198 a structure of 2, 3 or 4 vectors. */
1200 /* Useful combinations of the above. */
1204 /* Return a set of flags describing the vector properties of mode MODE.
1205 Ignore modes that are not supported by the current target. */
1206 static unsigned int
1208 {
1224 {
1226 {
1233 }
1235 /* This includes V1DF but not V1DI (which doesn't exist). */
1240 }
1243 }
1245 /* Return true if MODE is any of the data vector modes, including
1246 structure modes. */
1247 static bool
1249 {
1251 }
1253 /* Return true if MODE is an SVE data vector mode; either a single vector
1254 or a structure of vectors. */
1255 static bool
1257 {
1259 }
1261 /* Implement target hook TARGET_ARRAY_MODE. */
1262 static opt_machine_mode
1264 {
1271 }
1273 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1274 static bool
1277 {
1285 }
1287 /* Return the SVE predicate mode to use for elements that have
1288 ELEM_NBYTES bytes, if such a mode exists. */
1290 opt_machine_mode
1292 {
1294 {
1303 }
1305 }
1307 /* Implement TARGET_VECTORIZE_GET_MASK_MODE. */
1309 static opt_machine_mode
1311 {
1313 {
1315 machine_mode pred_mode;
1318 }
1321 }
1323 /* Implement TARGET_PREFERRED_ELSE_VALUE. Prefer to use the first
1324 arithmetic operand as the else value if the else value doesn't matter,
1325 since that exactly matches the SVE destructive merging form. */
1327 static tree
1329 {
1331 }
1333 /* Implement TARGET_HARD_REGNO_NREGS. */
1335 static unsigned int
1337 {
1338 /* ??? Logically we should only need to provide a value when
1339 HARD_REGNO_MODE_OK says that the combination is valid,
1340 but at the moment we need to handle all modes. Just ignore
1341 any runtime parts for registers that can't store them. */
1344 {
1357 }
1359 }
1361 /* Implement TARGET_HARD_REGNO_MODE_OK. */
1363 static bool
1365 {
1370 /* This must have the same size as _Unwind_Word. */
1381 /* The purpose of comparing with ptr_mode is to support the
1382 global register variable associated with the stack pointer
1383 register via the syntax of asm ("wsp") in ILP32. */
1393 {
1396 else
1398 }
1401 }
1403 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
1404 the lower 64 bits of a 128-bit register. Tell the compiler the callee
1405 clobbers the top 64 bits when restoring the bottom 64 bits. */
1407 static bool
1409 {
1411 }
1413 /* Implement REGMODE_NATURAL_SIZE. */
1414 poly_uint64
1416 {
1417 /* The natural size for SVE data modes is one SVE data vector,
1418 and similarly for predicates. We can't independently modify
1419 anything smaller than that. */
1420 /* ??? For now, only do this for variable-width SVE registers.
1421 Doing it for constant-sized registers breaks lower-subreg.c. */
1422 /* ??? And once that's fixed, we should probably have similar
1423 code for Advanced SIMD. */
1425 {
1431 }
1433 }
1435 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1436 machine_mode
1438 machine_mode mode)
1439 {
1440 /* The predicate mode determines which bits are significant and
1441 which are "don't care". Decreasing the number of lanes would
1442 lose data while increasing the number of lanes would make bits
1443 unnecessarily significant. */
1448 else
1450 }
1452 /* Implement TARGET_CONSTANT_ALIGNMENT. Make strings word-aligned so
1453 that strcpy from constants will be faster. */
1455 static HOST_WIDE_INT
1457 {
1461 }
1463 /* Return true if calls to DECL should be treated as
1464 long-calls (ie called via a register). */
1465 static bool
1467 {
1469 }
1471 /* Return true if calls to symbol-ref SYM should be treated as
1472 long-calls (ie called via a register). */
1473 bool
1475 {
1477 }
1479 /* Return true if calls to symbol-ref SYM should not go through
1480 plt stubs. */
1482 bool
1484 {
1488 && decl
1489 && (!flag_plt
1495 }
1497 /* Return true if the offsets to a zero/sign-extract operation
1498 represent an expression that matches an extend operation. The
1499 operands represent the paramters from
1501 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1502 bool
1504 rtx extract_imm)
1505 {
1522 }
1524 /* Emit an insn that's a simple single-set. Both the operands must be
1525 known to be valid. */
1528 {
1530 }
1532 /* X and Y are two things to compare using CODE. Emit the compare insn and
1533 return the rtx for register 0 in the proper mode. */
1534 rtx
1536 {
1542 }
1544 /* Build the SYMBOL_REF for __tls_get_addr. */
1548 rtx
1550 {
1554 }
1556 /* Return the TLS model to use for ADDR. */
1558 static enum tls_model
1560 {
1563 {
1564 poly_int64 addend;
1568 }
1573 }
1575 /* We'll allow lo_sum's in addresses in our legitimate addresses
1576 so that combine would take care of combining addresses where
1577 necessary, but for generation purposes, we'll generate the address
1578 as :
1579 RTL Absolute
1580 tmp = hi (symbol_ref); adrp x1, foo
1581 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1582 nop
1584 PIC TLS
1585 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1586 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1587 bl __tls_get_addr
1588 nop
1590 Load TLS symbol, depending on TLS mechanism and TLS access model.
1592 Global Dynamic - Traditional TLS:
1593 adrp tmp, :tlsgd:imm
1594 add dest, tmp, #:tlsgd_lo12:imm
1595 bl __tls_get_addr
1597 Global Dynamic - TLS Descriptors:
1598 adrp dest, :tlsdesc:imm
1599 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1600 add dest, dest, #:tlsdesc_lo12:imm
1601 blr tmp
1602 mrs tp, tpidr_el0
1603 add dest, dest, tp
1605 Initial Exec:
1606 mrs tp, tpidr_el0
1607 adrp tmp, :gottprel:imm
1608 ldr dest, [tmp, #:gottprel_lo12:imm]
1609 add dest, dest, tp
1611 Local Exec:
1612 mrs tp, tpidr_el0
1613 add t0, tp, #:tprel_hi12:imm, lsl #12
1614 add t0, t0, #:tprel_lo12_nc:imm
1615 */
1617 static void
1620 {
1622 {
1624 {
1625 /* In ILP32, the mode of dest can be either SImode or DImode. */
1637 }
1644 {
1647 rtx insn;
1648 rtx mem;
1650 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1651 here before rtl expand. Tree IVOPT will generate rtl pattern to
1652 decide rtx costs, in which case pic_offset_table_rtx is not
1653 initialized. For that case no need to generate the first adrp
1654 instruction as the final cost for global variable access is
1655 one instruction. */
1657 {
1658 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1659 using the page base as GOT base, the first page may be wasted,
1660 in the worst scenario, there is only 28K space for GOT).
1662 The generate instruction sequence for accessing global variable
1663 is:
1665 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1667 Only one instruction needed. But we must initialize
1668 pic_offset_table_rtx properly. We generate initialize insn for
1669 every global access, and allow CSE to remove all redundant.
1671 The final instruction sequences will look like the following
1672 for multiply global variables access.
1674 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1676 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1677 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1678 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1679 ... */
1688 }
1691 {
1694 else
1698 }
1699 else
1700 {
1705 }
1707 /* The operand is expected to be MEM. Whenever the related insn
1708 pattern changed, above code which calculate mem should be
1709 updated. */
1715 }
1718 {
1719 /* In ILP32, the mode of dest can be either SImode or DImode,
1720 while the got entry is always of SImode size. The mode of
1721 dest depends on how dest is used: if dest is assigned to a
1722 pointer (e.g. in the memory), it has SImode; it may have
1723 DImode if dest is dereferenced to access the memeory.
1724 This is why we have to handle three different ldr_got_small
1725 patterns here (two patterns for ILP32). */
1727 rtx insn;
1728 rtx mem;
1737 {
1740 else
1744 }
1745 else
1746 {
1751 }
1758 }
1761 {
1769 else
1777 }
1780 {
1783 rtx tp;
1787 /* In ILP32, the got entry is always of SImode size. Unlike
1788 small GOT, the dest is fixed at reg 0. */
1791 else
1802 }
1805 {
1806 /* In ILP32, the mode of dest can be either SImode or DImode,
1807 while the got entry is always of SImode size. The mode of
1808 dest depends on how dest is used: if dest is assigned to a
1809 pointer (e.g. in the memory), it has SImode; it may have
1810 DImode if dest is dereferenced to access the memeory.
1811 This is why we have to handle three different tlsie_small
1812 patterns here (two patterns for ILP32). */
1818 {
1821 else
1822 {
1825 }
1826 }
1827 else
1828 {
1831 }
1837 }
1843 {
1851 {
1874 }
1879 }
1886 {
1891 {
1894 else
1895 {
1898 }
1899 }
1900 else
1901 {
1904 }
1909 }
1913 }
1914 }
1916 /* Emit a move from SRC to DEST. Assume that the move expanders can
1917 handle all moves if !can_create_pseudo_p (). The distinction is
1918 important because, unlike emit_move_insn, the move expanders know
1919 how to force Pmode objects into the constant pool even when the
1920 constant pool address is not itself legitimate. */
1921 static rtx
1923 {
1927 }
1929 /* Apply UNOPTAB to OP and store the result in DEST. */
1931 static void
1933 {
1937 }
1939 /* Apply BINOPTAB to OP0 and OP1 and store the result in DEST. */
1941 static void
1943 {
1945 OPTAB_DIRECT);
1948 }
1950 /* Split a 128-bit move operation into two 64-bit move operations,
1951 taking care to handle partial overlap of register to register
1952 copies. Special cases are needed when moving between GP regs and
1953 FP regs. SRC can be a register, constant or memory; DST a register
1954 or memory. If either operand is memory it must not have any side
1955 effects. */
1956 void
1958 {
1969 {
1973 /* Handle FP <-> GP regs. */
1975 {
1980 {
1983 }
1984 else
1985 {
1988 }
1990 }
1992 {
1997 {
2000 }
2001 else
2002 {
2005 }
2007 }
2008 }
2015 /* At most one pairing may overlap. */
2017 {
2020 }
2021 else
2022 {
2025 }
2026 }
2028 bool
2030 {
2033 }
2035 /* Split a complex SIMD combine. */
2037 void
2039 {
2051 {
2075 }
2079 }
2081 /* Split a complex SIMD move. */
2083 void
2085 {
2092 {
2098 {
2122 }
2126 }
2127 }
2129 bool
2132 {
2136 }
2139 static rtx
2141 {
2144 else
2145 {
2149 }
2150 }
2152 /* Return true if we can move VALUE into a register using a single
2153 CNT[BHWD] instruction. */
2155 static bool
2157 {
2159 /* The coefficient must be [1, 16] * {2, 4, 8, 16}. */
2164 }
2166 /* Likewise for rtx X. */
2168 bool
2170 {
2171 poly_int64 value;
2173 }
2175 /* Return the asm string for an instruction with a CNT-like vector size
2176 operand (a vector pattern followed by a multiplier in the range [1, 16]).
2177 PREFIX is the mnemonic without the size suffix and OPERANDS is the
2178 first part of the operands template (the part that comes before the
2179 vector size itself). FACTOR is the number of quadwords.
2180 NELTS_PER_VQ, if nonzero, is the number of elements in each quadword.
2181 If it is zero, we can use any element size. */
2187 {
2191 /* There is some overlap in the ranges of the four CNT instructions.
2192 Here we always use the smallest possible element size, so that the
2193 multiplier is 1 whereever possible. */
2204 else
2209 }
2211 /* Return the asm string for an instruction with a CNT-like vector size
2212 operand (a vector pattern followed by a multiplier in the range [1, 16]).
2213 PREFIX is the mnemonic without the size suffix and OPERANDS is the
2214 first part of the operands template (the part that comes before the
2215 vector size itself). X is the value of the vector size operand,
2216 as a polynomial integer rtx. */
2220 rtx x)
2221 {
2226 }
2228 /* Return true if we can add VALUE to a register using a single ADDVL
2229 or ADDPL instruction. */
2231 static bool
2233 {
2237 /* FACTOR counts VG / 2, so a value of 2 is one predicate width
2238 and a value of 16 is one vector width. */
2241 }
2243 /* Likewise for rtx X. */
2245 bool
2247 {
2248 poly_int64 value;
2251 }
2253 /* Return the asm string for adding ADDVL or ADDPL immediate X to operand 1
2254 and storing the result in operand 0. */
2258 {
2263 /* Use INC or DEC if possible. */
2265 {
2272 }
2277 else
2280 }
2282 /* Return true if X is a valid immediate for an SVE vector INC or DEC
2283 instruction. If it is, store the number of elements in each vector
2284 quadword in *NELTS_PER_VQ_OUT (if nonnull) and store the multiplication
2285 factor in *FACTOR_OUT (if nonnull). */
2287 bool
2290 {
2291 rtx elt;
2292 poly_int64 value;
2300 /* There's no vector INCB. */
2307 /* The coefficient must be [1, 16] * NELTS_PER_VQ. */
2317 }
2319 /* Return true if X is a valid immediate for an SVE vector INC or DEC
2320 instruction. */
2322 bool
2324 {
2326 }
2328 /* Return the asm template for an SVE vector INC or DEC instruction.
2329 OPERANDS gives the operands before the vector count and X is the
2330 value of the vector count operand itself. */
2334 {
2341 nelts_per_vq);
2342 else
2344 nelts_per_vq);
2345 }
2347 static int
2349 scalar_int_mode mode)
2350 {
2359 {
2363 }
2365 /* Check to see if the low 32 bits are either 0xffffXXXX or 0xXXXXffff
2366 (with XXXX non-zero). In that case check to see if the move can be done in
2367 a smaller mode. */
2372 {
2376 /* Check if we have to emit a second instruction by checking to see
2377 if any of the upper 32 bits of the original DI mode value is set. */
2388 }
2391 {
2393 {
2398 else
2401 }
2403 }
2405 /* Remaining cases are all for DImode. */
2414 {
2415 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
2416 For a 64-bit bitmask try whether changing 16 bits to all ones or
2417 zeroes creates a valid bitmask. To check any repeated bitmask,
2418 try using 16 bits from the other 32-bit half of val. */
2421 {
2432 }
2434 {
2436 {
2440 }
2442 }
2443 }
2445 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
2446 are emitted by the initial mov. If one_match > zero_match, skip set bits,
2447 otherwise skip zero bits. */
2459 {
2465 num_insns ++;
2466 }
2469 }
2471 /* Return whether imm is a 128-bit immediate which is simple enough to
2472 expand inline. */
2473 bool
2475 {
2486 }
2489 /* Return the number of temporary registers that aarch64_add_offset_1
2490 would need to add OFFSET to a register. */
2492 static unsigned int
2494 {
2496 }
2498 /* A subroutine of aarch64_add_offset. Set DEST to SRC + OFFSET for
2499 a non-polynomial OFFSET. MODE is the mode of the addition.
2500 FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should
2501 be set and CFA adjustments added to the generated instructions.
2503 TEMP1, if nonnull, is a register of mode MODE that can be used as a
2504 temporary if register allocation is already complete. This temporary
2505 register may overlap DEST but must not overlap SRC. If TEMP1 is known
2506 to hold abs (OFFSET), EMIT_MOVE_IMM can be set to false to avoid emitting
2507 the immediate again.
2509 Since this function may be used to adjust the stack pointer, we must
2510 ensure that it cannot cause transient stack deallocation (for example
2511 by first incrementing SP and then decrementing when adjusting by a
2512 large immediate). */
2514 static void
2518 {
2526 {
2528 {
2531 }
2533 }
2535 /* Single instruction adjustment. */
2537 {
2541 }
2543 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits
2544 and either:
2546 a) the offset cannot be loaded by a 16-bit move or
2547 b) there is no spare register into which we can move it. */
2551 {
2560 }
2562 /* Emit a move immediate if required and an addition/subtraction. */
2564 {
2567 }
2572 {
2576 }
2577 }
2579 /* Return the number of temporary registers that aarch64_add_offset
2580 would need to move OFFSET into a register or add OFFSET to a register;
2581 ADD_P is true if we want the latter rather than the former. */
2583 static unsigned int
2585 {
2586 /* This follows the same structure as aarch64_add_offset. */
2595 /* Need one register for the ADDVL/ADDPL result. */
2598 {
2601 /* Need one register for the CNT result and one for the multiplication
2602 factor. If necessary, the second temporary can be reused for the
2603 constant part of the offset. */
2605 /* Need one register for the CNT result (which might then
2606 be shifted). */
2608 }
2610 }
2612 /* If X can be represented as a poly_int64, return the number
2613 of temporaries that are required to add it to a register.
2614 Return -1 otherwise. */
2616 int
2618 {
2619 poly_int64 offset;
2623 }
2625 /* Set DEST to SRC + OFFSET. MODE is the mode of the addition.
2626 FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should
2627 be set and CFA adjustments added to the generated instructions.
2629 TEMP1, if nonnull, is a register of mode MODE that can be used as a
2630 temporary if register allocation is already complete. This temporary
2631 register may overlap DEST if !FRAME_RELATED_P but must not overlap SRC.
2632 If TEMP1 is known to hold abs (OFFSET), EMIT_MOVE_IMM can be set to
2633 false to avoid emitting the immediate again.
2635 TEMP2, if nonnull, is a second temporary register that doesn't
2636 overlap either DEST or REG.
2638 Since this function may be used to adjust the stack pointer, we must
2639 ensure that it cannot cause transient stack deallocation (for example
2640 by first incrementing SP and then decrementing when adjusting by a
2641 large immediate). */
2643 static void
2647 {
2651 || !frame_related_p
2655 /* Try using ADDVL or ADDPL to add the whole value. */
2657 {
2662 }
2664 /* Coefficient 1 is multiplied by the number of 128-bit blocks in an
2665 SVE vector register, over and above the minimum size of 128 bits.
2666 This is equivalent to half the value returned by CNTD with a
2667 vector shape of ALL. */
2671 /* Try using ADDVL or ADDPL to add the VG-based part. */
2675 {
2678 {
2682 }
2683 else
2684 {
2689 }
2690 }
2691 /* Otherwise use a CNT-based sequence. */
2693 {
2694 /* Use a subtraction if we have a negative factor. */
2697 {
2700 }
2702 /* Calculate CNTD * FACTOR / 2. First try to fold the division
2703 into the multiplication. */
2704 rtx val;
2707 /* Use a right shift by 1. */
2709 else
2713 {
2715 {
2716 /* "CNTB Xn, ALL, MUL #FACTOR" is out of range, so calculate
2717 the value with the minimum multiplier and shift it into
2718 position. */
2722 }
2724 }
2725 else
2726 {
2727 /* Use CNTD, then multiply it by FACTOR. */
2731 /* Go back to using a negative multiplication factor if we have
2732 no register from which to subtract. */
2734 {
2737 }
2741 }
2744 {
2745 /* Multiply by 1 << SHIFT. */
2748 }
2750 {
2751 /* Divide by 2. */
2754 }
2756 /* Calculate SRC +/- CNTD * FACTOR / 2. */
2758 {
2761 }
2763 {
2766 }
2769 {
2772 {
2776 poly_offset)));
2777 }
2781 }
2782 else
2783 {
2787 }
2790 }
2794 }
2796 /* Like aarch64_add_offset, but the offset is given as an rtx rather
2797 than a poly_int64. */
2799 void
2802 {
2805 }
2807 /* Add DELTA to the stack pointer, marking the instructions frame-related.
2808 TEMP1 is available as a temporary if nonnull. EMIT_MOVE_IMM is false
2809 if TEMP1 already contains abs (DELTA). */
2813 {
2816 }
2818 /* Subtract DELTA from the stack pointer, marking the instructions
2819 frame-related if FRAME_RELATED_P. TEMP1 is available as a temporary
2820 if nonnull. */
2824 {
2827 }
2829 /* Set DEST to (vec_series BASE STEP). */
2831 static void
2833 {
2837 /* Each operand can be a register or an immediate in the range [-16, 15]. */
2844 }
2846 /* Try to duplicate SRC into SVE register DEST, given that SRC is an
2847 integer of mode INT_MODE. Return true on success. */
2849 static bool
2851 rtx src)
2852 {
2853 /* If the constant is smaller than 128 bits, we can do the move
2854 using a vector of SRC_MODEs. */
2856 {
2863 }
2865 /* Use LD1RQ[BHWD] to load the 128 bits from memory. */
2870 /* Make sure that the address is legitimate. */
2872 {
2875 }
2884 }
2886 /* Expand a move of general CONST_VECTOR SRC into DEST, given that it
2887 isn't a simple duplicate or series. */
2889 static void
2891 {
2898 {
2899 /* The constant is a repeating seqeuence of at least two elements,
2900 where the repeating elements occupy no more than 128 bits.
2901 Get an integer representation of the replicated value. */
2902 scalar_int_mode int_mode;
2904 /* For now, always use LD1RQ to load the value on big-endian
2905 targets, since the handling of smaller integers includes a
2906 subreg that is semantically an element reverse. */
2908 else
2909 {
2913 }
2918 }
2920 /* Expand each pattern individually. */
2921 rtx_vector_builder builder;
2924 {
2929 }
2931 /* Use permutes to interleave the separate vectors. */
2933 {
2936 {
2941 }
2942 }
2944 }
2946 /* Set DEST to immediate IMM. For SVE vector modes, GEN_VEC_DUPLICATE
2947 is a pattern that can be used to set DEST to a replicated scalar
2948 element. */
2950 void
2953 {
2956 /* Check on what type of symbol it is. */
2957 scalar_int_mode int_mode;
2963 {
2964 rtx mem;
2965 poly_int64 offset;
2966 HOST_WIDE_INT const_offset;
2969 /* If we have (const (plus symbol offset)), separate out the offset
2970 before we start classifying the symbol. */
2973 /* We must always add an offset involving VL separately, rather than
2974 folding it into the relocation. */
2976 {
2979 else
2980 {
2981 /* Do arithmetic on 32-bit values if the result is smaller
2982 than that. */
2984 {
2985 /* It is invalid to do symbol calculations in modes
2986 narrower than SImode. */
2990 }
2992 {
2996 }
2997 else
3000 }
3002 }
3006 {
3010 {
3016 }
3021 /* If we aren't generating PC relative literals, then
3022 we need to expand the literal pool access carefully.
3023 This is something that needs to be done in a number
3024 of places, so could well live as a separate function. */
3026 {
3033 }
3050 {
3056 }
3057 /* FALLTHRU */
3070 }
3071 }
3074 {
3082 {
3083 /* If the constant is out of range of an SVE vector move,
3084 load it from memory if we can, otherwise move it into
3085 a register and use a DUP. */
3091 {
3094 }
3096 }
3100 else
3101 {
3105 }
3108 }
3112 }
3114 /* Emit an SVE predicated move from SRC to DEST. PRED is a predicate
3115 that is known to contain PTRUE. */
3117 void
3119 {
3122 UNSPEC_MERGE_PTRUE)));
3123 }
3125 /* Expand a pre-RA SVE data move from SRC to DEST in which at least one
3126 operand is in memory. In this case we need to use the predicated LD1
3127 and ST1 instead of LDR and STR, both for correctness on big-endian
3128 targets and because LD1 and ST1 support a wider range of addressing modes.
3129 PRED_MODE is the mode of the predicate.
3131 See the comment at the head of aarch64-sve.md for details about the
3132 big-endian handling. */
3134 void
3136 {
3141 {
3145 else
3148 }
3150 }
3152 /* Called only on big-endian targets. See whether an SVE vector move
3153 from SRC to DEST is effectively a REV[BHW] instruction, because at
3154 least one operand is a subreg of an SVE vector that has wider or
3155 narrower elements. Return true and emit the instruction if so.
3157 For example:
3159 (set (reg:VNx8HI R1) (subreg:VNx8HI (reg:VNx16QI R2) 0))
3161 represents a VIEW_CONVERT between the following vectors, viewed
3162 in memory order:
3164 R2: { [0].high, [0].low, [1].high, [1].low, ... }
3165 R1: { [0], [1], [2], [3], ... }
3167 The high part of lane X in R2 should therefore correspond to lane X*2
3168 of R1, but the register representations are:
3170 msb lsb
3171 R2: ...... [1].high [1].low [0].high [0].low
3172 R1: ...... [3] [2] [1] [0]
3174 where the low part of lane X in R2 corresponds to lane X*2 in R1.
3175 We therefore need a reverse operation to swap the high and low values
3176 around.
3178 This is purely an optimization. Without it we would spill the
3179 subreg operand to the stack in one mode and reload it in the
3180 other mode, which has the same effect as the REV. */
3182 bool
3184 {
3191 /* The optimization handles two single SVE REGs with different element
3192 sizes. */
3201 /* Generate *aarch64_sve_mov<mode>_subreg_be. */
3204 UNSPEC_REV_SUBREG);
3207 }
3209 /* Return a copy of X with mode MODE, without changing its other
3210 attributes. Unlike gen_lowpart, this doesn't care whether the
3211 mode change is valid. */
3213 static rtx
3215 {
3222 }
3224 /* Split a *aarch64_sve_mov<mode>_subreg_be pattern with the given
3225 operands. */
3227 void
3229 {
3230 /* Decide which REV operation we need. The mode with narrower elements
3231 determines the mode of the operands and the mode with the wider
3232 elements determines the reverse width. */
3247 else
3251 /* Emit:
3253 (set DEST (unspec [PTRUE (unspec [SRC] UNSPEC_REV<nn>)]
3254 UNSPEC_MERGE_PTRUE))
3256 with the appropriate modes. */
3262 UNSPEC_MERGE_PTRUE);
3264 }
3266 static bool
3268 tree exp ATTRIBUTE_UNUSED)
3269 {
3270 /* Currently, always true. */
3272 }
3274 /* Implement TARGET_PASS_BY_REFERENCE. */
3276 static bool
3278 machine_mode mode,
3279 const_tree type,
3281 {
3282 HOST_WIDE_INT size;
3283 machine_mode dummymode;
3286 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
3289 else
3290 /* No frontends can create types with variable-sized modes, so we
3291 shouldn't be asked to pass or return them. */
3294 /* Aggregates are passed by reference based on their size. */
3296 {
3298 }
3300 /* Variable sized arguments are always returned by reference. */
3304 /* Can this be a candidate to be passed in fp/simd register(s)? */
3307 NULL))
3310 /* Arguments which are variable sized or larger than 2 registers are
3311 passed by reference unless they are a homogenous floating point
3312 aggregate. */
3314 }
3316 /* Return TRUE if VALTYPE is padded to its least significant bits. */
3317 static bool
3319 {
3320 machine_mode dummy_mode;
3323 /* Never happens in little-endian mode. */
3327 /* Only composite types smaller than or equal to 16 bytes can
3328 be potentially returned in registers. */
3334 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
3335 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
3336 is always passed/returned in the least significant bits of fp/simd
3337 register(s). */
3343 }
3345 /* Implement TARGET_FUNCTION_VALUE.
3346 Define how to find the value returned by a function. */
3348 static rtx
3351 {
3352 machine_mode mode;
3355 machine_mode ag_mode;
3362 {
3366 {
3369 }
3370 }
3374 {
3376 {
3379 }
3380 else
3381 {
3383 rtx par;
3387 {
3392 }
3394 }
3395 }
3396 else
3398 }
3400 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
3401 Return true if REGNO is the number of a hard register in which the values
3402 of called function may come back. */
3404 static bool
3406 {
3407 /* Maximum of 16 bytes can be returned in the general registers. Examples
3408 of 16-byte return values are: 128-bit integers and 16-byte small
3409 structures (excluding homogeneous floating-point aggregates). */
3413 /* Up to four fp/simd registers can return a function value, e.g. a
3414 homogeneous floating-point aggregate having four members. */
3419 }
3421 /* Implement TARGET_RETURN_IN_MEMORY.
3423 If the type T of the result of a function is such that
3424 void func (T arg)
3425 would require that arg be passed as a value in a register (or set of
3426 registers) according to the parameter passing rules, then the result
3427 is returned in the same registers as would be used for such an
3428 argument. */
3430 static bool
3432 {
3433 HOST_WIDE_INT size;
3434 machine_mode ag_mode;
3440 /* Simple scalar types always returned in registers. */
3444 type,
3447 NULL))
3450 /* Types larger than 2 registers returned in memory. */
3453 }
3455 static bool
3458 {
3461 type,
3463 nregs,
3464 NULL);
3465 }
3467 /* Given MODE and TYPE of a function argument, return the alignment in
3468 bits. The idea is to suppress any stronger alignment requested by
3469 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
3470 This is a helper function for local use only. */
3472 static unsigned int
3474 {
3495 }
3497 /* Layout a function argument according to the AAPCS64 rules. The rule
3498 numbers refer to the rule numbers in the AAPCS64. */
3500 static void
3502 const_tree type,
3504 {
3508 HOST_WIDE_INT size;
3510 /* We need to do this once per argument. */
3516 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
3519 else
3520 /* No frontends can create types with variable-sized modes, so we
3521 shouldn't be asked to pass or return them. */
3527 mode,
3528 type,
3531 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
3532 The following code thus handles passing by SIMD/FP registers first. */
3536 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
3537 and homogenous short-vector aggregates (HVA). */
3539 {
3544 {
3547 {
3550 }
3551 else
3552 {
3553 rtx par;
3557 {
3560 rtx offset = gen_int_mode
3564 }
3566 }
3568 }
3569 else
3570 {
3571 /* C.3 NSRN is set to 8. */
3574 }
3575 }
3580 /* C6 - C9. though the sign and zero extension semantics are
3581 handled elsewhere. This is the case where the argument fits
3582 entirely general registers. */
3584 {
3588 /* C.8 if the argument has an alignment of 16 then the NGRN is
3589 rounded up to the next even number. */
3592 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
3593 comparison is there because for > 16 * BITS_PER_UNIT
3594 alignment nregs should be > 2 and therefore it should be
3595 passed by reference rather than value. */
3597 {
3600 }
3602 /* NREGS can be 0 when e.g. an empty structure is to be passed.
3603 A reg is still generated for it, but the caller should be smart
3604 enough not to use it. */
3607 else
3608 {
3609 rtx par;
3614 {
3619 }
3621 }
3625 }
3627 /* C.11 */
3630 /* The argument is passed on stack; record the needed number of words for
3631 this argument and align the total size if necessary. */
3632 on_stack:
3639 }
3641 /* Implement TARGET_FUNCTION_ARG. */
3643 static rtx
3646 {
3655 }
3657 void
3659 const_tree fntype ATTRIBUTE_UNUSED,
3660 rtx libname ATTRIBUTE_UNUSED,
3661 const_tree fndecl ATTRIBUTE_UNUSED,
3663 {
3677 {
3684 }
3686 }
3688 static void
3690 machine_mode mode,
3691 const_tree type,
3693 {
3696 {
3706 }
3707 }
3709 bool
3711 {
3714 }
3716 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
3717 PARM_BOUNDARY bits of alignment, but will be given anything up
3718 to STACK_BOUNDARY bits if the type requires it. This makes sure
3719 that both before and after the layout of each argument, the Next
3720 Stacked Argument Address (NSAA) will have a minimum alignment of
3721 8 bytes. */
3723 static unsigned int
3725 {
3728 }
3730 /* Implement TARGET_GET_RAW_RESULT_MODE and TARGET_GET_RAW_ARG_MODE. */
3732 static fixed_size_mode
3734 {
3736 /* Don't use the SVE part of the register for __builtin_apply and
3737 __builtin_return. The SVE registers aren't used by the normal PCS,
3738 so using them there would be a waste of time. The PCS extensions
3739 for SVE types are fundamentally incompatible with the
3740 __builtin_return/__builtin_apply interface. */
3743 }
3745 /* Implement TARGET_FUNCTION_ARG_PADDING.
3747 Small aggregate types are placed in the lowest memory address.
3749 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
3751 static pad_direction
3753 {
3754 /* On little-endian targets, the least significant byte of every stack
3755 argument is passed at the lowest byte address of the stack slot. */
3759 /* Otherwise, integral, floating-point and pointer types are padded downward:
3760 the least significant byte of a stack argument is passed at the highest
3761 byte address of the stack slot. */
3768 /* Everything else padded upward, i.e. data in first byte of stack slot. */
3770 }
3772 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
3774 It specifies padding for the last (may also be the only)
3775 element of a block move between registers and memory. If
3776 assuming the block is in the memory, padding upward means that
3777 the last element is padded after its highest significant byte,
3778 while in downward padding, the last element is padded at the
3779 its least significant byte side.
3781 Small aggregates and small complex types are always padded
3782 upwards.
3784 We don't need to worry about homogeneous floating-point or
3785 short-vector aggregates; their move is not affected by the
3786 padding direction determined here. Regardless of endianness,
3787 each element of such an aggregate is put in the least
3788 significant bits of a fp/simd register.
3790 Return !BYTES_BIG_ENDIAN if the least significant byte of the
3791 register has useful data, and return the opposite if the most
3792 significant byte does. */
3794 bool
3797 {
3799 /* Small composite types are always padded upward. */
3801 {
3802 HOST_WIDE_INT size;
3805 else
3806 /* No frontends can create types with variable-sized modes, so we
3807 shouldn't be asked to pass or return them. */
3811 }
3813 /* Otherwise, use the default padding. */
3815 }
3817 static scalar_int_mode
3819 {
3821 }
3823 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
3825 /* We use the 12-bit shifted immediate arithmetic instructions so values
3826 must be multiple of (1 << 12), i.e. 4096. */
3827 #define ARITH_FACTOR 4096
3829 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
3830 #error Cannot use simple address calculation for stack probing
3831 #endif
3833 /* The pair of scratch registers used for stack probing. */
3834 #define PROBE_STACK_FIRST_REG 9
3835 #define PROBE_STACK_SECOND_REG 10
3837 /* Emit code to probe a range of stack addresses from FIRST to FIRST+POLY_SIZE,
3838 inclusive. These are offsets from the current stack pointer. */
3840 static void
3842 {
3843 HOST_WIDE_INT size;
3845 {
3848 }
3852 /* See the same assertion on PROBE_INTERVAL above. */
3855 /* See if we have a constant small number of probes to generate. If so,
3856 that's the easy case. */
3858 {
3865 }
3867 /* The run-time loop is made up of 8 insns in the generic case while the
3868 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
3870 {
3875 stack_pointer_rtx,
3879 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
3880 it exceeds SIZE. If only two probes are needed, this will not
3881 generate any code. Then probe at FIRST + SIZE. */
3883 {
3887 }
3891 {
3896 }
3897 else
3899 }
3901 /* Otherwise, do the same as above, but in a loop. Note that we must be
3902 extra careful with variables wrapping around because we might be at
3903 the very top (or the very bottom) of the address space and we have
3904 to be able to handle this case properly; in particular, we use an
3905 equality test for the loop condition. */
3906 else
3907 {
3910 /* Step 1: round SIZE to the previous multiple of the interval. */
3915 /* Step 2: compute initial and final value of the loop counter. */
3917 /* TEST_ADDR = SP + FIRST. */
3921 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
3924 {
3928 }
3929 else
3933 /* Step 3: the loop
3935 do
3936 {
3937 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
3938 probe at TEST_ADDR
3939 }
3940 while (TEST_ADDR != LAST_ADDR)
3942 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
3943 until it is equal to ROUNDED_SIZE. */
3948 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
3949 that SIZE is equal to ROUNDED_SIZE. */
3952 {
3956 {
3961 }
3962 else
3964 }
3965 }
3967 /* Make sure nothing is scheduled before we are done. */
3969 }
3971 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
3972 absolute addresses. */
3976 {
3983 /* Loop. */
3986 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
3991 /* Probe at TEST_ADDR. */
3994 /* Test if TEST_ADDR == LAST_ADDR. */
3998 /* Branch. */
4004 }
4006 /* Determine whether a frame chain needs to be generated. */
4007 static bool
4009 {
4010 /* Force a frame chain for EH returns so the return address is at FP+8. */
4014 /* A leaf function cannot have calls or write LR. */
4017 /* Don't use a frame chain in leaf functions if leaf frame pointers
4018 are disabled. */
4023 }
4025 /* Mark the registers that need to be saved by the callee and calculate
4026 the size of the callee-saved registers area and frame record (both FP
4027 and LR may be omitted). */
4028 static void
4030 {
4039 #define SLOT_NOT_REQUIRED (-2)
4040 #define SLOT_REQUIRED (-1)
4045 /* First mark all the registers that really need to be saved... */
4052 /* ... that includes the eh data registers (if needed)... */
4058 /* ... and any callee saved register that dataflow says is live. */
4068 {
4071 }
4074 {
4075 /* FP and LR are placed in the linkage record. */
4081 }
4083 /* Now assign stack slots for them. */
4086 {
4093 }
4101 {
4102 /* If there is an alignment gap between integer and fp callee-saves,
4103 allocate the last fp register to it if possible. */
4105 {
4108 }
4117 }
4123 HOST_WIDE_INT varargs_and_saved_regs_size
4131 /* Both these values are already aligned. */
4155 {
4156 /* Simple, small frame with no outgoing arguments:
4157 stp reg1, reg2, [sp, -frame_size]!
4158 stp reg3, reg4, [sp, 16] */
4160 }
4165 max_push_offset)))
4166 {
4167 /* Frame with small outgoing arguments:
4168 sub sp, sp, frame_size
4169 stp reg1, reg2, [sp, outgoing_args_size]
4170 stp reg3, reg4, [sp, outgoing_args_size + 16] */
4174 }
4177 {
4178 /* Frame with large outgoing arguments but a small local area:
4179 stp reg1, reg2, [sp, -hard_fp_offset]!
4180 stp reg3, reg4, [sp, 16]
4181 sub sp, sp, outgoing_args_size */
4185 }
4186 else
4187 {
4188 /* Frame with large local area and outgoing arguments using frame pointer:
4189 sub sp, sp, hard_fp_offset
4190 stp x29, x30, [sp, 0]
4191 add x29, sp, 0
4192 stp reg3, reg4, [sp, 16]
4193 sub sp, sp, outgoing_args_size */
4197 }
4200 }
4202 /* Return true if the register REGNO is saved on entry to
4203 the current function. */
4205 static bool
4207 {
4209 }
4211 /* Return the next register up from REGNO up to LIMIT for the callee
4212 to save. */
4214 static unsigned
4216 {
4218 regno ++;
4220 }
4222 /* Push the register number REGNO of mode MODE to the stack with write-back
4223 adjusting the stack by ADJUSTMENT. */
4225 static void
4227 HOST_WIDE_INT adjustment)
4228 {
4239 }
4241 /* Generate and return an instruction to store the pair of registers
4242 REG and REG2 of mode MODE to location BASE with write-back adjusting
4243 the stack location BASE by ADJUSTMENT. */
4245 static rtx
4247 HOST_WIDE_INT adjustment)
4248 {
4250 {
4261 }
4262 }
4264 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
4265 stack pointer by ADJUSTMENT. */
4267 static void
4269 {
4284 }
4286 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
4287 adjusting it by ADJUSTMENT afterwards. */
4289 static rtx
4291 HOST_WIDE_INT adjustment)
4292 {
4294 {
4303 }
4304 }
4306 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
4307 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
4308 into CFI_OPS. */
4310 static void
4313 {
4320 {
4324 }
4325 else
4326 {
4331 }
4332 }
4334 /* Generate and return a store pair instruction of mode MODE to store
4335 register REG1 to MEM1 and register REG2 to MEM2. */
4337 static rtx
4339 rtx reg2)
4340 {
4342 {
4351 }
4352 }
4354 /* Generate and regurn a load pair isntruction of mode MODE to load register
4355 REG1 from MEM1 and register REG2 from MEM2. */
4357 static rtx
4359 rtx mem2)
4360 {
4362 {
4371 }
4372 }
4374 /* Return TRUE if return address signing should be enabled for the current
4375 function, otherwise return FALSE. */
4377 bool
4379 {
4380 /* This function should only be called after frame laid out. */
4383 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
4384 if it's LR is pushed onto stack. */
4388 }
4390 /* Emit code to save the callee-saved registers from register number START
4391 to LIMIT to the stack at the location starting at offset START_OFFSET,
4392 skipping any write-back candidates if SKIP_WB is true. */
4394 static void
4397 {
4405 {
4407 poly_int64 offset;
4420 offset));
4429 {
4431 rtx mem2;
4435 offset));
4437 reg2));
4439 /* The first part of a frame-related parallel insn is
4440 always assumed to be relevant to the frame
4441 calculations; subsequent parts, are only
4442 frame-related if explicitly marked. */
4445 }
4446 else
4450 }
4451 }
4453 /* Emit code to restore the callee registers of mode MODE from register
4454 number START up to and including LIMIT. Restore from the stack offset
4455 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
4456 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
4458 static void
4462 {
4466 poly_int64 offset;
4471 {
4492 {
4494 rtx mem2;
4502 }
4503 else
4506 }
4507 }
4509 /* Return true if OFFSET is a signed 4-bit value multiplied by the size
4510 of MODE. */
4514 {
4515 HOST_WIDE_INT multiple;
4518 }
4520 /* Return true if OFFSET is a unsigned 6-bit value multiplied by the size
4521 of MODE. */
4525 {
4526 HOST_WIDE_INT multiple;
4529 }
4531 /* Return true if OFFSET is a signed 7-bit value multiplied by the size
4532 of MODE. */
4534 bool
4536 {
4537 HOST_WIDE_INT multiple;
4540 }
4542 /* Return true if OFFSET is a signed 9-bit value. */
4546 poly_int64 offset)
4547 {
4548 HOST_WIDE_INT const_offset;
4551 }
4553 /* Return true if OFFSET is a signed 9-bit value multiplied by the size
4554 of MODE. */
4558 {
4559 HOST_WIDE_INT multiple;
4562 }
4564 /* Return true if OFFSET is an unsigned 12-bit value multiplied by the size
4565 of MODE. */
4569 {
4570 HOST_WIDE_INT multiple;
4573 }
4575 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
4577 static sbitmap
4579 {
4585 /* The registers we need saved to the frame. */
4588 {
4593 /* Check that we can access the stack slot of the register with one
4594 direct load with no adjustments needed. */
4597 }
4599 /* Don't mess with the hard frame pointer. */
4605 /* If aarch64_layout_frame has chosen registers to store/restore with
4606 writeback don't interfere with them to avoid having to output explicit
4607 stack adjustment instructions. */
4617 }
4619 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
4621 static sbitmap
4623 {
4631 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
4637 {
4641 /* If there is a callee-save at an adjacent offset, add it too
4642 to increase the use of LDP/STP. */
4647 {
4651 }
4652 }
4655 }
4657 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
4658 Nothing to do for aarch64. */
4660 static void
4662 {
4663 }
4665 /* Return the next set bit in BMP from START onwards. Return the total number
4666 of bits in BMP if no set bit is found at or after START. */
4668 static unsigned int
4670 {
4681 }
4683 /* Do the work for aarch64_emit_prologue_components and
4684 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
4685 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
4686 for these components or the epilogue sequence. That is, it determines
4687 whether we should emit stores or loads and what kind of CFA notes to attach
4688 to the insns. Otherwise the logic for the two sequences is very
4689 similar. */
4691 static void
4693 {
4695 ? HARD_FRAME_POINTER_REGNUM
4703 {
4704 /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
4705 so DFmode for the vector registers is enough. */
4717 /* No more registers to handle after REGNO.
4718 Emit a single save/restore and exit. */
4720 {
4725 else
4728 }
4731 /* The next register is not of the same class or its offset is not
4732 mergeable with the current one into a pair. */
4737 {
4742 else
4747 }
4749 /* REGNO2 can be saved/restored in a pair with REGNO. */
4761 else
4766 {
4769 }
4770 else
4771 {
4774 }
4777 }
4778 }
4780 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
4782 static void
4784 {
4786 }
4788 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
4790 static void
4792 {
4794 }
4796 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
4798 static void
4800 {
4804 }
4806 /* Add a REG_CFA_EXPRESSION note to INSN to say that register REG
4807 is saved at BASE + OFFSET. */
4809 static void
4812 {
4816 }
4818 /* AArch64 stack frames generated by this compiler look like:
4820 +-------------------------------+
4821 | |
4822 | incoming stack arguments |
4823 | |
4824 +-------------------------------+
4825 | | <-- incoming stack pointer (aligned)
4826 | callee-allocated save area |
4827 | for register varargs |
4828 | |
4829 +-------------------------------+
4830 | local variables | <-- frame_pointer_rtx
4831 | |
4832 +-------------------------------+
4833 | padding0 | \
4834 +-------------------------------+ |
4835 | callee-saved registers | | frame.saved_regs_size
4836 +-------------------------------+ |
4837 | LR' | |
4838 +-------------------------------+ |
4839 | FP' | / <- hard_frame_pointer_rtx (aligned)
4840 +-------------------------------+
4841 | dynamic allocation |
4842 +-------------------------------+
4843 | padding |
4844 +-------------------------------+
4845 | outgoing stack arguments | <-- arg_pointer
4846 | |
4847 +-------------------------------+
4848 | | <-- stack_pointer_rtx (aligned)
4850 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
4851 but leave frame_pointer_rtx and hard_frame_pointer_rtx
4852 unchanged. */
4854 /* Generate the prologue instructions for entry into a function.
4855 Establish the stack frame by decreasing the stack pointer with a
4856 properly calculated size and, if necessary, create a frame record
4857 filled with the values of LR and previous frame pointer. The
4858 current FP is also set up if it is in use. */
4860 void
4862 {
4875 /* Sign return address for functions. */
4877 {
4881 }
4887 {
4889 {
4893 (frame_size
4895 }
4898 }
4909 {
4912 {
4917 }
4922 {
4923 /* Variable-sized frames need to describe the save slot
4924 address using DW_CFA_expression rather than DW_CFA_offset.
4925 This means that, without taking further action, the
4926 locations of the registers that we've already saved would
4927 remain based on the stack pointer even after we redefine
4928 the CFA based on the frame pointer. We therefore need new
4929 DW_CFA_expressions to re-express the save slots with addresses
4930 based on the frame pointer. */
4934 /* Add an explicit CFA definition if this was previously
4935 implicit. */
4937 {
4939 callee_offset);
4942 }
4944 /* Change the save slot expressions for the registers that
4945 we've already saved. */
4950 reg_offset);
4951 }
4953 }
4960 }
4962 /* Return TRUE if we can use a simple_return insn.
4964 This function checks whether the callee saved stack is empty, which
4965 means no restore actions are need. The pro_and_epilogue will use
4966 this to check whether shrink-wrapping opt is feasible. */
4968 bool
4970 {
4980 }
4982 /* Generate the epilogue instructions for returning from a function.
4983 This is almost exactly the reverse of the prolog sequence, except
4984 that we need to insert barriers to avoid scheduling loads that read
4985 from a deallocated stack, and we optimize the unwind records by
4986 emitting them all together if possible. */
4987 void
4989 {
5000 /* A stack clash protection prologue may not have left IP0_REGNUM or
5001 IP1_REGNUM in a usable state. The same is true for allocations
5002 with an SVE component, since we then need both temporary registers
5003 for each allocation. */
5008 /* We need to add memory barrier to prevent read from deallocated stack. */
5009 bool need_barrier_p
5013 /* Emit a barrier to prevent loads from a deallocated stack. */
5017 {
5020 }
5022 /* Restore the stack pointer from the frame pointer if it may not
5023 be the same as the stack pointer. */
5028 /* If writeback is used when restoring callee-saves, the CFA
5029 is restored on the instruction doing the writeback. */
5033 else
5049 {
5050 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
5056 }
5062 {
5063 /* Emit delayed restores and reset the CFA to be SP. */
5068 }
5070 /* We prefer to emit the combined return/authenticate instruction RETAA,
5071 however there are three cases in which we must instead emit an explicit
5072 authentication instruction.
5074 1) Sibcalls don't return in a normal way, so if we're about to call one
5075 we must authenticate.
5077 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
5078 generating code for !TARGET_ARMV8_3 we can't use it and must
5079 explicitly authenticate.
5081 3) On an eh_return path we make extra stack adjustments to update the
5082 canonical frame address to be the exception handler's CFA. We want
5083 to authenticate using the CFA of the function which calls eh_return.
5084 */
5087 {
5091 }
5093 /* Stack adjustment for exception handler. */
5095 {
5096 /* We need to unwind the stack by the offset computed by
5097 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
5098 to be SP; letting the CFA move during this adjustment
5099 is just as correct as retaining the CFA from the body
5100 of the function. Therefore, do nothing special. */
5102 }
5107 }
5109 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
5110 normally or return to a previous frame after unwinding.
5112 An EH return uses a single shared return sequence. The epilogue is
5113 exactly like a normal epilogue except that it has an extra input
5114 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
5115 that must be applied after the frame has been destroyed. An extra label
5116 is inserted before the epilogue which initializes this register to zero,
5117 and this is the entry point for a normal return.
5119 An actual EH return updates the return address, initializes the stack
5120 adjustment and jumps directly into the epilogue (bypassing the zeroing
5121 of the adjustment). Since the return address is typically saved on the
5122 stack when a function makes a call, the saved LR must be updated outside
5123 the epilogue.
5125 This poses problems as the store is generated well before the epilogue,
5126 so the offset of LR is not known yet. Also optimizations will remove the
5127 store as it appears dead, even after the epilogue is generated (as the
5128 base or offset for loading LR is different in many cases).
5130 To avoid these problems this implementation forces the frame pointer
5131 in eh_return functions so that the location of LR is fixed and known early.
5132 It also marks the store volatile, so no optimization is permitted to
5133 remove the store. */
5134 rtx
5136 {
5140 /* Mark the store volatile, so no optimization is permitted to remove it. */
5143 }
5145 /* Output code to add DELTA to the first argument, and then jump
5146 to FUNCTION. Used for C++ multiple inheritance. */
5147 static void
5149 HOST_WIDE_INT delta,
5150 HOST_WIDE_INT vcall_offset,
5151 tree function)
5152 {
5153 /* The this pointer is always in x0. Note that this differs from
5154 Arm where the this pointer maybe bumped to r1 if r0 is required
5155 to return a pointer to an aggregate. On AArch64 a result value
5156 pointer will be in x8. */
5170 else
5171 {
5176 {
5180 else
5183 }
5187 else
5194 else
5195 {
5197 Pmode);
5199 }
5203 else
5209 }
5211 /* Generate a tail call to the target function. */
5213 {
5216 }
5228 /* Stop pretending to be a post-reload pass. */
5230 }
5232 static bool
5234 {
5239 {
5243 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
5244 TLS offsets, not real symbol references. */
5247 }
5249 }
5252 /* Return true if val can be encoded as a 12-bit unsigned immediate with
5253 a left shift of 0 or 12 bits. */
5254 bool
5256 {
5259 );
5260 }
5263 /* Return true if val is an immediate that can be loaded into a
5264 register by a MOVZ instruction. */
5265 static bool
5267 {
5269 {
5273 }
5274 else
5275 {
5276 /* Ignore sign extension. */
5278 }
5281 }
5283 /* VAL is a value with the inner mode of MODE. Replicate it to fill a
5284 64-bit (DImode) integer. */
5286 static unsigned HOST_WIDE_INT
5288 {
5291 {
5295 }
5297 }
5299 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
5302 {
5308 };
5311 /* Return true if val is a valid bitmask immediate. */
5313 bool
5315 {
5319 /* Check for a single sequence of one bits and return quickly if so.
5320 The special cases of all ones and all zeroes returns false. */
5327 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
5331 /* Invert if the immediate doesn't start with a zero bit - this means we
5332 only need to search for sequences of one bits. */
5336 /* Find the first set bit and set tmp to val with the first sequence of one
5337 bits removed. Return success if there is a single sequence of ones. */
5344 /* Find the next set bit and compute the difference in bit position. */
5349 /* Check the bit position difference is a power of 2, and that the first
5350 sequence of one bits fits within 'bits' bits. */
5354 /* Check the sequence of one bits is repeated 64/bits times. */
5356 }
5358 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
5359 Assumed precondition: VAL_IN Is not zero. */
5361 unsigned HOST_WIDE_INT
5363 {
5370 }
5372 /* Create constant where bits outside of lowest bit set to highest bit set
5373 are set to 1. */
5375 unsigned HOST_WIDE_INT
5377 {
5379 }
5381 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
5383 bool
5385 {
5386 scalar_int_mode int_mode;
5399 }
5401 /* Return true if val is an immediate that can be loaded into a
5402 register in a single instruction. */
5403 bool
5405 {
5406 scalar_int_mode int_mode;
5413 }
5415 static bool
5417 {
5423 /* There's no way to calculate VL-based values using relocations. */
5431 {
5435 else
5436 /* Avoid generating a 64-bit relocation in ILP32; leave
5437 to aarch64_expand_mov_immediate to handle it properly. */
5439 }
5442 }
5444 /* Implement TARGET_CASE_VALUES_THRESHOLD.
5445 The expansion for a table switch is quite expensive due to the number
5446 of instructions, the table lookup and hard to predict indirect jump.
5447 When optimizing for speed, and -O3 enabled, use the per-core tuning if
5448 set, otherwise use tables for > 16 cases as a tradeoff between size and
5449 performance. When optimizing for size, use the default setting. */
5451 static unsigned int
5453 {
5454 /* Use the specified limit for the number of cases before using jump
5455 tables at higher optimization levels. */
5459 else
5461 }
5463 /* Return true if register REGNO is a valid index register.
5464 STRICT_P is true if REG_OK_STRICT is in effect. */
5466 bool
5468 {
5470 {
5478 }
5480 }
5482 /* Return true if register REGNO is a valid base register for mode MODE.
5483 STRICT_P is true if REG_OK_STRICT is in effect. */
5485 bool
5487 {
5489 {
5497 }
5499 /* The fake registers will be eliminated to either the stack or
5500 hard frame pointer, both of which are usually valid base registers.
5501 Reload deals with the cases where the eliminated form isn't valid. */
5506 }
5508 /* Return true if X is a valid base register for mode MODE.
5509 STRICT_P is true if REG_OK_STRICT is in effect. */
5511 static bool
5513 {
5520 }
5522 /* Return true if address offset is a valid index. If it is, fill in INFO
5523 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
5525 static bool
5528 {
5530 rtx index;
5533 /* (reg:P) */
5536 {
5540 }
5541 /* (sign_extend:DI (reg:SI)) */
5546 {
5551 }
5552 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
5559 {
5564 }
5565 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
5572 {
5577 }
5578 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
5585 {
5593 }
5594 /* (and:DI (mult:DI (reg:DI) (const_int scale))
5595 (const_int 0xffffffff<<shift)) */
5602 {
5608 }
5609 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
5616 {
5624 }
5625 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
5626 (const_int 0xffffffff<<shift)) */
5633 {
5639 }
5640 /* (mult:P (reg:P) (const_int scale)) */
5645 {
5649 }
5650 /* (ashift:P (reg:P) (const_int shift)) */
5655 {
5659 }
5660 else
5669 {
5673 }
5674 else
5675 {
5680 }
5684 {
5689 }
5692 }
5694 /* Return true if MODE is one of the modes for which we
5695 support LDP/STP operations. */
5697 static bool
5699 {
5707 }
5709 /* Return true if REGNO is a virtual pointer register, or an eliminable
5710 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
5711 include stack_pointer or hard_frame_pointer. */
5712 static bool
5714 {
5719 }
5721 /* Return true if X is a valid address of type TYPE for machine mode MODE.
5722 If it is, fill in INFO appropriately. STRICT_P is true if
5723 REG_OK_STRICT is in effect. */
5725 static bool
5729 {
5732 poly_int64 offset;
5734 HOST_WIDE_INT const_size;
5736 /* On BE, we use load/store pair for all large int mode load/stores.
5737 TI/TFmode may also use a load/store pair. */
5750 /* For SVE, only accept [Rn], [Rn, Rm, LSL #shift] and
5751 [Rn, #offset, MUL VL]. */
5756 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
5757 REG addressing. */
5759 && !BYTES_BIG_ENDIAN
5767 {
5784 {
5791 }
5796 {
5802 /* TImode and TFmode values are allowed in both pairs of X
5803 registers and individual Q registers. The available
5804 address modes are:
5805 X,X: 7-bit signed scaled offset
5806 Q: 9-bit signed offset
5807 We conservatively require an offset representable in either mode.
5808 When performing the check for pairs of X registers i.e. LDP/STP
5809 pass down DImode since that is the natural size of the LDP/STP
5810 instruction memory accesses. */
5816 /* A 7bit offset check because OImode will emit a ldp/stp
5817 instruction (only big endian will get here).
5818 For ldp/stp instructions, the offset is scaled for the size of a
5819 single element of the pair. */
5823 /* Three 9/12 bit offsets checks because CImode will emit three
5824 ldr/str instructions (only big endian will get here). */
5831 /* Two 7bit offsets checks because XImode will emit two ldp/stp
5832 instructions (only big endian will get here). */
5838 /* Make "m" use the LD1 offset range for SVE data modes, so
5839 that pre-RTL optimizers like ivopts will work to that
5840 instead of the wider LDR/STR range. */
5847 {
5848 poly_int64 end_offset = (offset
5855 end_offset)));
5856 }
5866 else
5869 }
5872 {
5873 /* Look for base + (scaled/extended) index register. */
5876 {
5879 }
5882 {
5885 }
5886 }
5907 {
5911 /* TImode and TFmode values are allowed in both pairs of X
5912 registers and individual Q registers. The available
5913 address modes are:
5914 X,X: 7-bit signed scaled offset
5915 Q: 9-bit signed offset
5916 We conservatively require an offset representable in either mode.
5917 */
5927 else
5929 }
5935 /* load literal: pc-relative constant pool entry. Only supported
5936 for SI mode or larger. */
5942 {
5950 }
5959 {
5965 {
5966 /* The symbol and offset must be aligned to the access size. */
5972 {
5976 }
5982 else
5991 }
5992 }
5997 }
5998 }
6000 /* Return true if the address X is valid for a PRFM instruction.
6001 STRICT_P is true if we should do strict checking with
6002 aarch64_classify_address. */
6004 bool
6006 {
6009 /* PRFM accepts the same addresses as DImode... */
6014 /* ... except writeback forms. */
6016 }
6018 bool
6020 {
6021 rtx offset;
6025 }
6027 /* Classify the base of symbolic expression X. */
6029 enum aarch64_symbol_type
6031 {
6032 rtx offset;
6036 }
6039 /* Return TRUE if X is a legitimate address for accessing memory in
6040 mode MODE. */
6041 static bool
6043 {
6047 }
6049 /* Return TRUE if X is a legitimate address of type TYPE for accessing
6050 memory in mode MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
6051 bool
6053 aarch64_addr_query_type type)
6054 {
6058 }
6060 /* Implement TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT. */
6062 static bool
6064 poly_int64 orig_offset,
6065 machine_mode mode)
6066 {
6067 HOST_WIDE_INT size;
6069 {
6072 /* A general SVE offset is A * VQ + B. Remove the A component from
6073 coefficient 0 in order to get the constant B. */
6076 /* Split an out-of-range address displacement into a base and
6077 offset. Use 4KB range for 1- and 2-byte accesses and a 16KB
6078 range otherwise to increase opportunities for sharing the base
6079 address of different sizes. Unaligned accesses use the signed
6080 9-bit range, TImode/TFmode use the intersection of signed
6081 scaled 7-bit and signed 9-bit offset. */
6086 else
6092 /* Split the offset into second_offset and the rest. */
6096 }
6097 else
6098 {
6099 /* Get the mode we should use as the basis of the range. For structure
6100 modes this is the mode of one vector. */
6102 machine_mode step_mode
6105 /* Get the "mul vl" multiplier we'd like to use. */
6109 /* LDR supports a 9-bit range, but the move patterns for
6110 structure modes require all vectors to be in range of the
6111 same base. The simplest way of accomodating that while still
6112 promoting reuse of anchor points between different modes is
6113 to use an 8-bit range unconditionally. */
6115 else
6116 /* Predicates are only handled singly, so we might as well use
6117 the full range. */
6122 /* Convert the "mul vl" multiplier into a byte offset. */
6127 /* Split the offset into second_offset and the rest. */
6131 }
6132 }
6134 /* Return the binary representation of floating point constant VALUE in INTVAL.
6135 If the value cannot be converted, return false without setting INTVAL.
6136 The conversion is done in the given MODE. */
6137 bool
6139 {
6141 /* We make a general exception for 0. */
6143 {
6146 }
6148 scalar_float_mode mode;
6152 /* Only support up to DF mode. */
6164 {
6168 }
6169 else
6174 }
6176 /* Return TRUE if rtx X is an immediate constant that can be moved using a
6177 single MOV(+MOVK) followed by an FMOV. */
6178 bool
6180 {
6185 /* Determine whether it's cheaper to write float constants as
6186 mov/movk pairs over ldr/adrp pairs. */
6192 {
6194 ? SImode
6199 }
6202 }
6204 /* Return TRUE if rtx X is immediate constant 0.0 */
6205 bool
6207 {
6214 }
6216 /* Return TRUE if rtx X is immediate constant that fits in a single
6217 MOVI immediate operation. */
6218 bool
6220 {
6224 machine_mode vmode;
6225 scalar_int_mode imode;
6230 {
6234 /* We make a general exception for 0. */
6239 }
6243 else
6246 /* use a 64 bit mode for everything except for DI/DF mode, where we use
6247 a 128 bit vector mode. */
6254 }
6257 /* Return the fixed registers used for condition codes. */
6259 static bool
6261 {
6265 }
6267 /* This function is used by the call expanders of the machine description.
6268 RESULT is the register in which the result is returned. It's NULL for
6269 "call" and "sibcall".
6270 MEM is the location of the function call.
6271 SIBCALL indicates whether this function call is normal call or sibling call.
6272 It will generate different pattern accordingly. */
6274 void
6276 {
6278 rtvec vec;
6279 machine_mode mode;
6286 /* Decide if we should generate indirect calls by loading the
6287 address of the callee into a register before performing
6288 the branch-and-link. */
6302 else
6309 }
6311 /* Emit call insn with PAT and do aarch64-specific handling. */
6313 void
6315 {
6321 }
6323 machine_mode
6325 {
6326 /* All floating point compares return CCFP if it is an equality
6327 comparison, and CCFPE otherwise. */
6329 {
6331 {
6352 }
6353 }
6355 /* Equality comparisons of short modes against zero can be performed
6356 using the TST instruction with the appropriate bitmask. */
6362 /* Similarly, comparisons of zero_extends from shorter modes can
6363 be performed using an ANDS with an immediate mask. */
6379 /* A compare with a shifted operand. Because of canonicalization,
6380 the comparison will have to be swapped when we emit the assembly
6381 code. */
6389 /* Similarly for a negated operand, but we can only do this for
6390 equalities. */
6397 /* A test for unsigned overflow. */
6404 /* For everything else, return CCmode. */
6406 }
6408 static int
6411 int
6413 {
6420 }
6422 static int
6424 {
6426 {
6430 {
6444 }
6449 {
6461 }
6466 {
6478 }
6483 {
6489 }
6494 {
6498 }
6503 {
6507 }
6512 }
6515 }
6517 bool
6519 HOST_WIDE_INT minval,
6520 HOST_WIDE_INT maxval)
6521 {
6522 rtx elt;
6526 }
6528 bool
6530 {
6532 }
6534 /* Return true if VEC is a constant in which every element is in the range
6535 [MINVAL, MAXVAL]. The elements do not need to have the same value. */
6537 static bool
6539 HOST_WIDE_INT minval,
6540 HOST_WIDE_INT maxval)
6541 {
6553 {
6558 }
6560 }
6562 /* N Z C V. */
6563 #define AARCH64_CC_V 1
6564 #define AARCH64_CC_C (1 << 1)
6565 #define AARCH64_CC_Z (1 << 2)
6566 #define AARCH64_CC_N (1 << 3)
6568 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
6570 {
6587 };
6589 /* Print floating-point vector immediate operand X to F, negating it
6590 first if NEGATE is true. Return true on success, false if it isn't
6591 a constant we can handle. */
6593 static bool
6595 {
6596 rtx elt;
6605 /* We only handle the SVE single-bit immediates here. */
6612 else
6616 }
6618 /* Return the equivalent letter for size. */
6619 static char
6621 {
6623 {
6629 }
6630 }
6632 /* Print operand X to file F in a target specific manner according to CODE.
6633 The acceptable formatting commands given by CODE are:
6634 'c': An integer or symbol address without a preceding #
6635 sign.
6636 'C': Take the duplicated element in a vector constant
6637 and print it in hex.
6638 'D': Take the duplicated element in a vector constant
6639 and print it as an unsigned integer, in decimal.
6640 'e': Print the sign/zero-extend size as a character 8->b,
6641 16->h, 32->w.
6642 'p': Prints N such that 2^N == X (X must be power of 2 and
6643 const int).
6644 'P': Print the number of non-zero bits in X (a const_int).
6645 'H': Print the higher numbered register of a pair (TImode)
6646 of regs.
6647 'm': Print a condition (eq, ne, etc).
6648 'M': Same as 'm', but invert condition.
6649 'N': Take the duplicated element in a vector constant
6650 and print the negative of it in decimal.
6651 'b/h/s/d/q': Print a scalar FP/SIMD register name.
6652 'S/T/U/V': Print a FP/SIMD register name for a register list.
6653 The register printed is the FP/SIMD register name
6654 of X + 0/1/2/3 for S/T/U/V.
6655 'R': Print a scalar FP/SIMD register name + 1.
6656 'X': Print bottom 16 bits of integer constant in hex.
6657 'w/x': Print a general register name or the zero register
6658 (32-bit or 64-bit).
6659 '0': Print a normal operand, if it's a general register,
6660 then we assume DImode.
6661 'k': Print NZCV for conditional compare instructions.
6662 'A': Output address constant representing the first
6663 argument of X, specifying a relocation offset
6664 if appropriate.
6665 'L': Output constant address specified by X
6666 with a relocation offset if appropriate.
6667 'G': Prints address of X, specifying a PC relative
6668 relocation mode if appropriate.
6669 'y': Output address of LDP or STP - this is used for
6670 some LDP/STPs which don't use a PARALLEL in their
6671 pattern (so the mode needs to be adjusted).
6672 'z': Output address of a typical LDP or STP. */
6674 static void
6676 {
6677 rtx elt;
6679 {
6682 {
6694 {
6697 }
6698 /* Fall through. */
6702 }
6706 {
6711 {
6714 }
6717 {
6730 }
6731 }
6735 {
6739 {
6742 }
6745 }
6750 {
6753 }
6760 {
6763 }
6770 {
6772 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
6774 {
6778 }
6781 {
6784 }
6791 }
6796 {
6799 }
6805 ;
6806 else
6807 {
6810 }
6819 {
6820 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
6822 }
6831 {
6832 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
6834 }
6842 {
6843 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
6845 }
6851 {
6854 }
6859 {
6860 /* Print a replicated constant in hex. */
6862 {
6865 }
6868 }
6872 {
6873 /* Print a replicated constant in decimal, treating it as
6874 unsigned. */
6876 {
6879 }
6882 }
6889 {
6892 }
6895 {
6898 }
6901 {
6904 }
6906 /* Fall through */
6910 {
6913 }
6916 {
6919 {
6922 else
6923 {
6924 char suffix
6929 }
6930 }
6931 else
6950 {
6953 }
6954 /* fall through */
6958 {
6961 }
6967 ;
6968 else
6969 {
6972 }
6976 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
6977 be getting CONST_DOUBLEs holding integers. */
6980 {
6983 }
6985 {
6986 #define buf_size 20
6994 #undef buf_size
6995 }
7001 }
7009 {
7036 }
7042 {
7077 }
7083 {
7089 }
7094 {
7095 HOST_WIDE_INT cond_code;
7098 {
7101 }
7106 }
7111 {
7116 {
7119 }
7122 /* LDP/STP which uses a single double-width memory operand.
7123 Adjust the mode to appear like a typical LDP/STP.
7124 Currently this is supported for 16-byte accesses only. */
7129 }
7135 }
7136 }
7138 /* Print address 'x' of a memory access with mode 'mode'.
7139 'op' is the context required by aarch64_classify_address. It can either be
7140 MEM for a normal memory access or PARALLEL for LDP/STP. */
7141 static bool
7143 aarch64_addr_query_type type)
7144 {
7148 /* Check all addresses are Pmode - including ILP32. */
7154 {
7159 {
7160 HOST_WIDE_INT vnum
7165 }
7167 {
7168 HOST_WIDE_INT vnum
7173 }
7174 else
7183 else
7192 else
7201 else
7207 /* Writeback is only supported for fixed-width modes. */
7210 {
7233 }
7245 }
7248 }
7250 /* Print address 'x' of a LDP/STP with mode 'mode'. */
7251 static bool
7253 {
7255 }
7257 /* Print address 'x' of a memory access with mode 'mode'. */
7258 static void
7260 {
7263 }
7265 bool
7267 {
7274 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
7275 referencing instruction, but they are constant offsets, not
7276 symbols. */
7282 {
7284 {
7290 }
7293 }
7296 }
7298 /* Implement REGNO_REG_CLASS. */
7300 enum reg_class
7302 {
7320 }
7322 /* OFFSET is an address offset for mode MODE, which has SIZE bytes.
7323 If OFFSET is out of range, return an offset of an anchor point
7324 that is in range. Return 0 otherwise. */
7326 static HOST_WIDE_INT
7328 machine_mode mode)
7329 {
7330 /* Does it look like we'll need a 16-byte load/store-pair operation? */
7334 /* For offsets that aren't a multiple of the access size, the limit is
7335 -256...255. */
7337 {
7338 /* BLKmode typically uses LDP of X-registers. */
7342 }
7344 /* Small negative offsets are supported. */
7351 /* Use 12-bit offset by access size. */
7353 }
7355 static rtx
7357 {
7358 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
7359 where mask is selected by alignment and size of the offset.
7360 We try to pick as large a range for the offset as possible to
7361 maximize the chance of a CSE. However, for aligned addresses
7362 we limit the range to 4k so that structures with different sized
7363 elements are likely to use the same base. We need to be careful
7364 not to split a CONST for some forms of address expression, otherwise
7365 it will generate sub-optimal code. */
7368 {
7374 {
7378 /* Force any scaling into a temp for CSE. */
7382 /* Let the pointer register be in op0. */
7386 /* If the pointer is virtual or frame related, then we know that
7387 virtual register instantiation or register elimination is going
7388 to apply a second constant. We want the two constants folded
7389 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
7391 {
7395 }
7397 /* Otherwise, in order to encourage CSE (and thence loop strength
7398 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
7402 }
7404 HOST_WIDE_INT size;
7406 {
7408 mode);
7410 {
7414 }
7415 }
7416 }
7419 }
7421 /* Return the reload icode required for a constant pool in mode. */
7422 static enum insn_code
7424 {
7426 {
7462 }
7465 }
7466 static reg_class_t
7468 reg_class_t rclass,
7469 machine_mode mode,
7471 {
7472 /* Use aarch64_sve_reload_be for SVE reloads that cannot be handled
7473 directly by the *aarch64_sve_mov<mode>_be move pattern. See the
7474 comment at the head of aarch64-sve.md for more details about the
7475 big-endian handling. */
7481 {
7484 }
7486 /* If we have to disable direct literal pool loads and stores because the
7487 function is too big, then we need a scratch register. */
7492 {
7495 }
7497 /* Without the TARGET_SIMD instructions we cannot move a Q register
7498 to a Q register directly. We need a scratch. */
7502 {
7508 }
7510 /* A TFmode or TImode memory access should be handled via an FP_REGS
7511 because AArch64 has richer addressing modes for LDR/STR instructions
7512 than LDP/STP instructions. */
7521 }
7523 static bool
7525 {
7528 /* If we need a frame pointer, ARG_POINTER_REGNUM and FRAME_POINTER_REGNUM
7529 can only eliminate to HARD_FRAME_POINTER_REGNUM. */
7533 }
7535 poly_int64
7537 {
7541 {
7548 }
7551 {
7555 }
7558 }
7560 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
7561 previous frame. */
7563 rtx
7565 {
7569 }
7572 static void
7574 {
7576 {
7579 }
7580 else
7581 {
7584 }
7589 }
7591 static void
7593 {
7597 /* Don't need to copy the trailing D-words, we fill those in below. */
7609 /* XXX We should really define a "clear_cache" pattern and use
7610 gen_clear_cache(). */
7615 ptr_mode);
7616 }
7618 static unsigned char
7620 {
7621 /* ??? Logically we should only need to provide a value when
7622 HARD_REGNO_MODE_OK says that at least one register in REGCLASS
7623 can hold MODE, but at the moment we need to handle all modes.
7624 Just ignore any runtime parts for registers that can't store them. */
7628 {
7654 }
7656 }
7658 static reg_class_t
7660 {
7665 {
7671 }
7673 /* Register eliminiation can result in a request for
7674 SP+constant->FP_REGS. We cannot support such operations which
7675 use SP as source and an FP_REG as destination, so reject out
7676 right now. */
7678 {
7681 /* Look through a possible SUBREG introduced by ILP32. */
7687 POINTER_REGS));
7689 }
7692 }
7694 void
7696 {
7698 }
7700 static void
7702 {
7705 else
7706 {
7708 /* While priority is known to be in range [0, 65535], so 18 bytes
7709 would be enough, the compiler might not know that. To avoid
7710 -Wformat-truncation false positive, use a larger size. */
7717 }
7718 }
7720 static void
7722 {
7725 else
7726 {
7728 /* While priority is known to be in range [0, 65535], so 18 bytes
7729 would be enough, the compiler might not know that. To avoid
7730 -Wformat-truncation false positive, use a larger size. */
7737 }
7738 }
7742 {
7748 {
7749 {
7752 },
7753 {
7756 },
7757 {
7760 },
7761 /* We assume that DImode is only generated when not optimizing and
7762 that we don't really need 64-bit address offsets. That would
7763 imply an object file with 8GB of code in a single function! */
7764 {
7767 }
7768 };
7777 /* Need to implement table size reduction, by chaning the code below. */
7787 }
7790 /* Return size in bits of an arithmetic operand which is shifted/scaled and
7791 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
7792 operator. */
7794 int
7796 {
7798 {
7801 {
7805 }
7806 }
7808 }
7810 /* Constant pools are per function only when PC relative
7811 literal loads are true or we are in the large memory
7812 model. */
7816 {
7819 }
7821 static bool
7823 {
7824 /* We can't use blocks for constants when we're using a per-function
7825 constant pool. */
7827 }
7829 /* Select appropriate section for constants depending
7830 on where we place literal pools. */
7834 rtx x,
7836 {
7841 }
7843 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
7844 void
7846 HOST_WIDE_INT offset)
7847 {
7848 /* When using per-function literal pools, we must ensure that any code
7849 section is aligned to the minimal instruction length, lest we get
7850 errors from the assembler re "unaligned instructions". */
7853 }
7855 /* Costs. */
7857 /* Helper function for rtx cost calculation. Strip a shift expression
7858 from X. Returns the inner operand if successful, or the original
7859 expression on failure. */
7860 static rtx
7862 {
7865 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
7866 we can convert both to ROR during final output. */
7881 }
7883 /* Helper function for rtx cost calculation. Strip an extend
7884 expression from X. Returns the inner operand if successful, or the
7885 original expression on failure. We deal with a number of possible
7886 canonicalization variations here. If STRIP_SHIFT is true, then
7887 we can strip off a shift also. */
7888 static rtx
7890 {
7891 scalar_int_mode mode;
7897 /* Zero and sign extraction of a widened value. */
7905 /* It can also be represented (for zero-extend) as an AND with an
7906 immediate. */
7915 /* Now handle extended register, as this may also have an optional
7916 left shift by 1..4. */
7931 }
7933 /* Return true iff CODE is a shift supported in combination
7934 with arithmetic instructions. */
7936 static bool
7938 {
7940 }
7943 /* Return true iff X is a cheap shift without a sign extend. */
7945 static bool
7947 {
7973 }
7975 /* Helper function for rtx cost calculation. Calculate the cost of
7976 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
7977 Return the calculated cost of the expression, recursing manually in to
7978 operands where needed. */
7980 static int
7982 {
7998 /* Integer multiply/fma. */
8000 {
8001 /* The multiply will be canonicalized as a shift, cost it as such. */
8005 {
8009 {
8011 {
8012 /* If the shift is considered cheap,
8013 then don't add any cost. */
8015 ;
8017 /* ARITH + shift-by-register. */
8020 /* ARITH + extended register. We don't have a cost field
8021 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
8023 else
8024 /* ARITH + shift-by-immediate. */
8026 }
8027 else
8028 /* LSL (immediate). */
8031 }
8032 /* Strip extends as we will have costed them in the case above. */
8039 }
8041 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
8042 compound and let the below cases handle it. After all, MNEG is a
8043 special-case alias of MSUB. */
8045 {
8048 }
8050 /* Integer multiplies or FMAs have zero/sign extending variants. */
8055 {
8060 {
8062 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
8064 else
8065 /* MUL/SMULL/UMULL. */
8067 }
8070 }
8072 /* This is either an integer multiply or a MADD. In both cases
8073 we want to recurse and cost the operands. */
8078 {
8080 /* MADD/MSUB. */
8082 else
8083 /* MUL. */
8085 }
8088 }
8089 else
8090 {
8092 {
8093 /* Floating-point FMA/FMUL can also support negations of the
8094 operands, unless the rounding mode is upward or downward in
8095 which case FNMUL is different than FMUL with operand negation. */
8099 {
8104 }
8107 /* FMADD/FNMADD/FNMSUB/FMSUB. */
8109 else
8110 /* FMUL/FNMUL. */
8112 }
8117 }
8118 }
8120 static int
8122 machine_mode mode,
8123 addr_space_t as ATTRIBUTE_UNUSED,
8125 {
8133 {
8135 {
8136 /* This is a CONST or SYMBOL ref which will be split
8137 in a different way depending on the code model in use.
8138 Cost it through the generic infrastructure. */
8140 /* Divide through by the cost of one instruction to
8141 bring it to the same units as the address costs. */
8143 /* The cost is then the cost of preparing the address,
8144 followed by an immediate (possibly 0) offset. */
8146 }
8147 else
8148 {
8149 /* This is most likely a jump table from a case
8150 statement. */
8152 }
8153 }
8156 {
8168 else
8187 }
8191 {
8192 /* For the sake of calculating the cost of the shifted register
8193 component, we can treat same sized modes in the same way. */
8200 else
8201 /* We can't tell, or this is a 128-bit vector. */
8203 }
8206 }
8208 /* Return the cost of a branch. If SPEED_P is true then the compiler is
8209 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
8210 to be taken. */
8212 int
8214 {
8215 /* When optimizing for speed, use the cost of unpredictable branches. */
8221 else
8223 }
8225 /* Return true if the RTX X in mode MODE is a zero or sign extract
8226 usable in an ADD or SUB (extended register) instruction. */
8227 static bool
8229 {
8230 /* Catch add with a sign extract.
8231 This is add_<optab><mode>_multp2. */
8234 {
8245 op1))
8246 {
8248 }
8249 }
8250 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
8251 No shift. */
8257 }
8259 static bool
8261 {
8263 {
8275 }
8276 }
8278 /* Return true iff X is an rtx that will match an extr instruction
8279 i.e. as described in the *extr<mode>5_insn family of patterns.
8280 OP0 and OP1 will be set to the operands of the shifts involved
8281 on success and will be NULL_RTX otherwise. */
8283 static bool
8285 {
8287 scalar_int_mode mode;
8302 {
8303 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
8315 {
8319 }
8320 }
8323 }
8325 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
8326 storing it in *COST. Result is true if the total cost of the operation
8327 has now been calculated. */
8328 static bool
8330 {
8331 rtx inner;
8332 rtx comparator;
8336 {
8340 }
8341 else
8342 {
8346 }
8349 {
8350 /* Conditional branch. */
8353 else
8354 {
8356 {
8358 {
8359 /* TBZ/TBNZ/CBZ/CBNZ. */
8361 /* TBZ/TBNZ. */
8364 else
8365 /* CBZ/CBNZ. */
8369 }
8370 }
8372 {
8373 /* TBZ/TBNZ. */
8376 }
8377 }
8378 }
8380 {
8381 /* CCMP. */
8383 {
8384 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
8388 {
8395 else
8397 }
8399 }
8401 /* It's a conditional operation based on the status flags,
8402 so it must be some flavor of CSEL. */
8404 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
8410 {
8411 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
8414 }
8419 }
8421 /* We don't know what this is, cost all operands. */
8423 }
8425 /* Check whether X is a bitfield operation of the form shift + extend that
8426 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
8427 operand to which the bitfield operation is applied. Otherwise return
8428 NULL_RTX. */
8430 static rtx
8432 {
8446 {
8464 }
8467 }
8469 /* Return true if the mask and a shift amount from an RTX of the form
8470 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
8471 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
8473 bool
8475 rtx shft_amnt)
8476 {
8481 }
8483 /* Calculate the cost of calculating X, storing it in *COST. Result
8484 is true if the total cost of the operation has now been calculated. */
8485 static bool
8488 {
8493 scalar_int_mode int_mode;
8495 /* By default, assume that everything has equivalent cost to the
8496 cheapest instruction. Any additional costs are applied as a delta
8497 above this default. */
8501 {
8503 /* The cost depends entirely on the operands to SET. */
8509 {
8512 {
8526 }
8535 /* Fall through. */
8537 /* The cost is one per vector-register copied. */
8539 {
8542 }
8543 /* const0_rtx is in general free, but we will use an
8544 instruction to set a register to 0. */
8546 {
8547 /* The cost is 1 per register copied. */
8550 }
8551 else
8552 /* Cost is just the cost of the RHS of the set. */
8558 /* Bit-field insertion. Strip any redundant widening of
8559 the RHS to meet the width of the target. */
8570 {
8571 /* MOV immediate is assumed to always be cheap. */
8573 }
8574 else
8575 {
8576 /* BFM. */
8580 }
8585 /* We can't make sense of this, assume default cost. */
8588 }
8592 /* If an instruction can incorporate a constant within the
8593 instruction, the instruction's expression avoids calling
8594 rtx_cost() on the constant. If rtx_cost() is called on a
8595 constant, then it is usually because the constant must be
8596 moved into a register by one or more instructions.
8598 The exception is constant 0, which can be expressed
8599 as XZR/WZR and is therefore free. The exception to this is
8600 if we have (set (reg) (const0_rtx)) in which case we must cost
8601 the move. However, we can catch that when we cost the SET, so
8602 we don't need to consider that here. */
8605 else
8606 {
8607 /* To an approximation, building any other constant is
8608 proportionally expensive to the number of instructions
8609 required to build that constant. This is true whether we
8610 are compiling for SPEED or otherwise. */
8615 }
8620 /* First determine number of instructions to do the move
8621 as an integer constant. */
8625 {
8631 ? SImode
8637 }
8640 {
8641 /* mov[df,sf]_aarch64. */
8643 /* FMOV (scalar immediate). */
8646 {
8647 /* This will be a load from memory. */
8650 else
8652 }
8653 else
8654 /* Otherwise this is +0.0. We get this using MOVI d0, #0
8655 or MOV v0.s[0], wzr - neither of which are modeled by the
8656 cost tables. Just use the default cost. */
8657 {
8658 }
8659 }
8665 {
8666 /* For loads we want the base cost of a load, plus an
8667 approximation for the additional cost of the addressing
8668 mode. */
8682 }
8690 {
8692 {
8693 /* FNEG. */
8695 }
8697 }
8700 {
8703 {
8704 /* CSETM. */
8707 }
8709 /* Cost this as SUB wzr, X. */
8713 }
8716 {
8717 /* Support (neg(fma...)) as a single instruction only if
8718 sign of zeros is unimportant. This matches the decision
8719 making in aarch64.md. */
8721 {
8722 /* FNMADD. */
8725 }
8727 {
8728 /* FNMUL. */
8731 }
8733 /* FNEG. */
8736 }
8743 {
8746 else
8748 }
8758 {
8762 }
8765 {
8766 /* TODO: A write to the CC flags possibly costs extra, this
8767 needs encoding in the cost tables. */
8770 /* ANDS. */
8772 {
8775 }
8778 {
8779 /* ADDS (and CMN alias). */
8782 }
8785 {
8786 /* SUBS. */
8789 }
8794 {
8795 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
8796 Handle it here directly rather than going to cost_logic
8797 since we know the immediate generated for the TST is valid
8798 so we can avoid creating an intermediate rtx for it only
8799 for costing purposes. */
8806 }
8809 {
8810 /* CMN. */
8817 }
8819 /* CMP.
8821 Compare can freely swap the order of operands, and
8822 canonicalization puts the more complex operation first.
8823 But the integer MINUS logic expects the shift/extend
8824 operation in op1. */
8827 {
8830 }
8832 }
8835 {
8836 /* FCMP. */
8841 {
8843 /* FCMP supports constant 0.0 for no extra cost. */
8845 }
8847 }
8850 {
8851 /* Vector compare. */
8856 {
8857 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
8858 cost. */
8860 }
8862 }
8866 {
8870 cost_minus:
8873 /* Detect valid immediates. */
8879 {
8881 /* SUB(S) (immediate). */
8884 }
8886 /* Look for SUB (extended register). */
8889 {
8897 }
8901 /* Cost this as an FMA-alike operation. */
8905 {
8908 speed);
8910 }
8915 {
8917 {
8918 /* Vector SUB. */
8920 }
8922 {
8923 /* SUB(S). */
8925 }
8927 {
8928 /* FSUB. */
8930 }
8931 }
8933 }
8936 {
8937 rtx new_op0;
8942 cost_plus:
8945 {
8946 /* CSINC. */
8950 }
8955 {
8959 /* ADD (immediate). */
8962 }
8966 /* Look for ADD (extended register). */
8969 {
8977 }
8979 /* Strip any extend, leave shifts behind as we will
8980 cost them through mult_cost. */
8985 {
8987 speed);
8989 }
8994 {
8996 {
8997 /* Vector ADD. */
8999 }
9001 {
9002 /* ADD. */
9004 }
9006 {
9007 /* FADD. */
9009 }
9010 }
9012 }
9018 {
9021 else
9023 }
9028 {
9032 {
9035 else
9037 }
9039 }
9042 {
9049 }
9050 /* Fall through. */
9053 cost_logic:
9058 {
9062 }
9070 {
9071 /* This is a UBFM/SBFM. */
9076 }
9079 {
9081 {
9082 /* We have a mask + shift version of a UBFIZ
9083 i.e. the *andim_ashift<mode>_bfiz pattern. */
9087 {
9094 }
9096 {
9097 /* We possibly get the immediate for free, this is not
9098 modelled. */
9105 }
9106 }
9107 else
9108 {
9111 /* Handle ORN, EON, or BIC. */
9117 /* If we had a shift on op0 then this is a logical-shift-
9118 by-register/immediate operation. Otherwise, this is just
9119 a logical operation. */
9121 {
9123 {
9124 /* Shift by immediate. */
9127 else
9129 }
9130 else
9132 }
9134 /* In both cases we want to cost both operands. */
9141 }
9142 }
9150 {
9151 /* Vector NOT. */
9154 }
9156 /* MVN-shifted-reg. */
9158 {
9165 }
9166 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
9167 Handle the second form here taking care that 'a' in the above can
9168 be a shift. */
9170 {
9179 {
9182 else
9184 }
9187 }
9188 /* MVN. */
9197 /* If a value is written in SI mode, then zero extended to DI
9198 mode, the operation will in general be free as a write to
9199 a 'w' register implicitly zeroes the upper bits of an 'x'
9200 register. However, if this is
9202 (set (reg) (zero_extend (reg)))
9204 we must cost the explicit register move. */
9208 {
9211 /* If OP_COST is non-zero, then the cost of the zero extend
9212 is effectively the cost of the inner operation. Otherwise
9213 we have a MOV instruction and we take the cost from the MOV
9214 itself. This is true independently of whether we are
9215 optimizing for space or time. */
9220 }
9222 {
9223 /* All loads can zero extend to any size for free. */
9226 }
9230 {
9235 }
9238 {
9240 {
9241 /* UMOV. */
9243 }
9244 else
9245 {
9246 /* We generate an AND instead of UXTB/UXTH. */
9248 }
9249 }
9254 {
9255 /* LDRSH. */
9257 {
9264 }
9266 }
9270 {
9275 }
9278 {
9281 else
9283 }
9291 {
9293 {
9295 {
9296 /* Vector shift (immediate). */
9298 }
9299 else
9300 {
9301 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
9302 aliases. */
9304 }
9305 }
9307 /* We can incorporate zero/sign extend for free. */
9314 }
9315 else
9316 {
9318 {
9320 /* Vector shift (register). */
9322 }
9323 else
9324 {
9326 /* LSLV. */
9333 {
9335 /* We already demanded XEXP (op1, 0) to be REG_P, so
9336 don't recurse into it. */
9338 }
9339 }
9341 }
9351 {
9352 /* ASR (immediate) and friends. */
9354 {
9357 else
9359 }
9363 }
9364 else
9365 {
9367 {
9369 /* Vector shift (register). */
9371 }
9372 else
9373 {
9375 /* ASR (register) and friends. */
9382 {
9384 /* We already demanded XEXP (op1, 0) to be REG_P, so
9385 don't recurse into it. */
9387 }
9388 }
9390 }
9396 {
9397 /* LDR. */
9400 }
9403 {
9404 /* ADRP, followed by ADD. */
9408 }
9411 {
9412 /* ADR. */
9415 }
9418 {
9419 /* One extra load instruction, after accessing the GOT. */
9423 }
9428 /* ADRP/ADD (immediate). */
9435 /* UBFX/SBFX. */
9437 {
9440 else
9442 }
9444 /* We can trust that the immediates used will be correct (there
9445 are no by-register forms), so we need only cost op0. */
9451 /* aarch64_rtx_mult_cost always handles recursion to its
9452 operands. */
9456 /* We can expand signed mod by power of 2 using a NEGS, two parallel
9457 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
9458 an unconditional negate. This case should only ever be reached through
9459 the set_smod_pow2_cheap check in expmed.c. */
9463 {
9464 /* We expand to 4 instructions. Reset the baseline. */
9472 }
9474 /* Fall-through. */
9477 {
9478 /* Slighly prefer UMOD over SMOD. */
9485 }
9492 {
9496 /* There is no integer SQRT, so only DIV and UDIV can get
9497 here. */
9499 /* Slighly prefer UDIV over SDIV. */
9501 else
9503 }
9529 {
9532 else
9534 }
9536 /* FMSUB, FNMADD, and FNMSUB are free. */
9543 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
9544 and the by-element operand as operand 0. */
9548 /* Catch vector-by-element operations. The by-element operand can
9549 either be (vec_duplicate (vec_select (x))) or just
9550 (vec_select (x)), depending on whether we are multiplying by
9551 a vector or a scalar.
9553 Canonicalization is not very good in these cases, FMA4 will put the
9554 by-element operand as operand 0, FNMA4 will have it as operand 1. */
9565 /* If the remaining parameters are not registers,
9566 get the cost to put them into registers. */
9580 {
9582 {
9583 /*Vector truncate. */
9585 }
9586 else
9588 }
9593 {
9595 {
9596 /*Vector conversion. */
9598 }
9599 else
9601 }
9607 /* Strip the rounding part. They will all be implemented
9608 by the fcvt* family of instructions anyway. */
9610 {
9619 }
9622 {
9625 else
9627 }
9629 /* We can combine fmul by a power of 2 followed by a fcvt into a single
9630 fixed-point fcvt. */
9635 {
9639 }
9646 {
9647 /* ABS (vector). */
9650 }
9652 {
9655 /* FABD, which is analogous to FADD. */
9657 {
9664 }
9665 /* Simple FABS is analogous to FNEG. */
9668 }
9669 else
9670 {
9671 /* Integer ABS will either be split to
9672 two arithmetic instructions, or will be an ABS
9673 (scalar), which we don't model. */
9677 }
9683 {
9686 else
9687 {
9688 /* FMAXNM/FMINNM/FMAX/FMIN.
9689 TODO: This may not be accurate for all implementations, but
9690 we do not model this in the cost tables. */
9692 }
9693 }
9697 /* The floating point round to integer frint* instructions. */
9699 {
9704 }
9707 {
9712 }
9717 /* Decompose <su>muldi3_highpart. */
9719 mode == DImode
9720 /* (lshiftrt:TI */
9723 /* (mult:TI */
9725 /* (ANY_EXTEND:TI (reg:DI))
9726 (ANY_EXTEND:TI (reg:DI))) */
9733 /* (const_int 64) */
9736 {
9737 /* UMULH/SMULH. */
9745 }
9747 /* Fall through. */
9750 }
9758 }
9760 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
9761 calculated for X. This cost is stored in *COST. Returns true
9762 if the total cost of X was calculated. */
9763 static bool
9766 {
9771 {
9776 }
9779 }
9781 static int
9784 {
9790 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
9797 /* Moving between GPR and stack cost is the same as GP2GP. */
9802 /* To/From the stack register, we move via the gprs. */
9808 {
9809 /* 128-bit operations on general registers require 2 instructions. */
9817 /* When AdvSIMD instructions are disabled it is not possible to move
9818 a 128-bit value directly between Q registers. This is handled in
9819 secondary reload. A general register is used as a scratch to move
9820 the upper DI value and the lower DI value is moved directly,
9821 hence the cost is the sum of three moves. */
9826 }
9836 }
9838 static int
9840 reg_class_t rclass ATTRIBUTE_UNUSED,
9842 {
9844 }
9846 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
9847 to optimize 1.0/sqrt. */
9849 static bool
9851 {
9853 && flag_unsafe_math_optimizations
9857 }
9859 /* Function to decide when to use the approximate reciprocal square root
9860 builtin. */
9862 static tree
9864 {
9870 }
9874 /* Select reciprocal square root initial estimate insn depending on machine
9875 mode. */
9877 static rsqrte_type
9879 {
9881 {
9888 }
9889 }
9893 /* Select reciprocal square root series step insn depending on machine mode. */
9895 static rsqrts_type
9897 {
9899 {
9906 }
9907 }
9909 /* Emit instruction sequence to compute either the approximate square root
9910 or its approximate reciprocal, depending on the flag RECP, and return
9911 whether the sequence was emitted or not. */
9913 bool
9915 {
9919 {
9922 }
9925 {
9932 || flag_trapping_math
9933 || !flag_unsafe_math_optimizations
9936 }
9937 else
9938 /* Caller assumes we cannot fail. */
9944 /* When calculating the approximate square root, compare the
9945 argument with 0.0 and create a mask. */
9951 /* Estimate the approximate reciprocal square root. */
9955 /* Iterate over the series twice for SF and thrice for DF. */
9958 /* Optionally iterate over the series once less for faster performance
9959 while sacrificing the accuracy. */
9962 iterations--;
9964 /* Iterate over the series to calculate the approximate reciprocal square
9965 root. */
9968 {
9976 }
9979 {
9980 /* Qualify the approximate reciprocal square root when the argument is
9981 0.0 by squashing the intermediary result to 0.0. */
9987 /* Calculate the approximate square root. */
9989 }
9991 /* Finalize the approximation. */
9995 }
9999 /* Select reciprocal initial estimate insn depending on machine mode. */
10001 static recpe_type
10003 {
10005 {
10012 }
10013 }
10017 /* Select reciprocal series step insn depending on machine mode. */
10019 static recps_type
10021 {
10023 {
10030 }
10031 }
10033 /* Emit the instruction sequence to compute the approximation for the division
10034 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
10036 bool
10038 {
10049 || flag_trapping_math
10050 || !flag_unsafe_math_optimizations
10058 /* Estimate the approximate reciprocal. */
10062 /* Iterate over the series twice for SF and thrice for DF. */
10065 /* Optionally iterate over the series once less for faster performance,
10066 while sacrificing the accuracy. */
10068 iterations--;
10070 /* Iterate over the series to calculate the approximate reciprocal. */
10073 {
10078 }
10081 {
10082 /* As the approximate reciprocal of DEN is already calculated, only
10083 calculate the approximate division when NUM is not 1.0. */
10086 }
10088 /* Finalize the approximation. */
10091 }
10093 /* Return the number of instructions that can be issued per cycle. */
10094 static int
10096 {
10098 }
10100 static int
10102 {
10106 }
10109 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
10110 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
10111 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
10113 static int
10116 {
10118 }
10121 /* Vectorizer cost model target hooks. */
10123 /* Implement targetm.vectorize.builtin_vectorization_cost. */
10124 static int
10126 tree vectype,
10128 {
10137 {
10188 }
10189 }
10191 /* Implement targetm.vectorize.add_stmt_cost. */
10192 static unsigned
10196 {
10201 {
10206 /* Statements in an inner loop relative to the loop being
10207 vectorized are weighted more heavily. The value here is
10208 arbitrary and could potentially be improved with analysis. */
10214 }
10217 }
10221 /* Parse the TO_PARSE string and put the architecture struct that it
10222 selects into RES and the architectural features into ISA_FLAGS.
10223 Return an aarch64_parse_opt_result describing the parse result.
10224 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
10226 static enum aarch64_parse_opt_result
10229 {
10241 else
10248 /* Loop through the list of supported ARCHes to find a match. */
10250 {
10252 {
10256 {
10257 /* TO_PARSE string contains at least one extension. */
10258 enum aarch64_parse_opt_result ext_res
10263 }
10264 /* Extension parsing was successful. Confirm the result
10265 arch and ISA flags. */
10269 }
10270 }
10272 /* ARCH name not found in list. */
10274 }
10276 /* Parse the TO_PARSE string and put the result tuning in RES and the
10277 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
10278 describing the parse result. If there is an error parsing, RES and
10279 ISA_FLAGS are left unchanged. */
10281 static enum aarch64_parse_opt_result
10284 {
10296 else
10303 /* Loop through the list of supported CPUs to find a match. */
10305 {
10307 {
10312 {
10313 /* TO_PARSE string contains at least one extension. */
10314 enum aarch64_parse_opt_result ext_res
10319 }
10320 /* Extension parsing was successfull. Confirm the result
10321 cpu and ISA flags. */
10325 }
10326 }
10328 /* CPU name not found in list. */
10330 }
10332 /* Parse the TO_PARSE string and put the cpu it selects into RES.
10333 Return an aarch64_parse_opt_result describing the parse result.
10334 If the parsing fails the RES does not change. */
10336 static enum aarch64_parse_opt_result
10338 {
10344 /* Loop through the list of supported CPUs to find a match. */
10346 {
10348 {
10351 }
10352 }
10354 /* CPU name not found in list. */
10356 }
10358 /* Parse TOKEN, which has length LENGTH to see if it is an option
10359 described in FLAG. If it is, return the index bit for that fusion type.
10360 If not, error (printing OPTION_NAME) and return zero. */
10362 static unsigned int
10367 {
10369 {
10373 }
10377 }
10379 /* Parse OPTION which is a comma-separated list of flags to enable.
10380 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
10381 default state we inherit from the CPU tuning structures. OPTION_NAME
10382 gives the top-level option we are parsing in the -moverride string,
10383 for use in error messages. */
10385 static unsigned int
10390 {
10397 {
10400 token_length,
10401 flags,
10402 option_name);
10403 /* If we find "none" (or, for simplicity's sake, an error) anywhere
10404 in the token stream, reset the supported operations. So:
10406 adrp+add.cmp+branch.none.adrp+add
10408 would have the result of turning on only adrp+add fusion. */
10414 }
10416 /* We ended with a comma, print something. */
10418 {
10421 }
10423 /* We still have one more token to parse. */
10426 token_length,
10427 flags,
10428 option_name);
10434 }
10436 /* Support for overriding instruction fusion. */
10438 static void
10441 {
10443 aarch64_fusible_pairs,
10446 }
10448 /* Support for overriding other tuning flags. */
10450 static void
10453 {
10454 tune->extra_tuning_flags
10456 aarch64_tuning_flags,
10459 }
10461 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
10462 we understand. If it is, extract the option string and handoff to
10463 the appropriate function. */
10465 void
10469 {
10475 {
10478 }
10480 /* Get the length of the option name. */
10482 /* Skip the '=' to get to the option string. */
10483 option_part++;
10486 {
10488 {
10491 }
10492 }
10496 }
10498 /* A checking mechanism for the implementation of the tls size. */
10500 static void
10502 {
10507 {
10509 /* Both the default and maximum TLS size allowed under tiny is 1M which
10510 needs two instructions to address, so we clamp the size to 24. */
10515 /* The maximum TLS size allowed under small is 4G. */
10520 /* The maximum TLS size allowed under large is 16E.
10521 FIXME: 16E should be 64bit, we only support 48bit offset now. */
10527 }
10530 }
10532 /* Parse STRING looking for options in the format:
10533 string :: option:string
10534 option :: name=substring
10535 name :: {a-z}
10536 substring :: defined by option. */
10538 static void
10541 {
10552 {
10554 /* Make this substring look like a string. */
10558 }
10560 /* One last option to parse. */
10563 }
10566 static void
10568 {
10569 /* PR 70044: We have to be careful about being called multiple times for the
10570 same function. This means all changes should be repeatable. */
10572 /* Set aarch64_use_frame_pointer based on -fno-omit-frame-pointer.
10573 Disable the frame pointer flag so the mid-end will not use a frame
10574 pointer in leaf functions in order to support -fomit-leaf-frame-pointer.
10575 Set x_flag_omit_frame_pointer to the special value 2 to differentiate
10576 between -fomit-frame-pointer (1) and -fno-omit-frame-pointer (2). */
10581 /* If not optimizing for size, set the default
10582 alignment to what the target wants. */
10584 {
10591 }
10593 /* We default to no pc-relative literal loads. */
10597 /* If -mpc-relative-literal-loads is set on the command line, this
10598 implies that the user asked for PC relative literal loads. */
10602 /* In the tiny memory model it makes no sense to disallow PC relative
10603 literal pool loads. */
10608 /* When enabling the lower precision Newton series for the square root, also
10609 enable it for the reciprocal square root, since the latter is an
10610 intermediary step for the former. */
10613 }
10615 /* 'Unpack' up the internal tuning structs and update the options
10616 in OPTS. The caller must have set up selected_tune and selected_arch
10617 as all the other target-specific codegen decisions are
10618 derived from them. */
10620 void
10622 {
10625 /* Make a copy of the tuning parameters attached to the core, which
10626 we may later overwrite. */
10634 /* This target defaults to strict volatile bitfields. */
10643 {
10655 }
10657 /* We don't mind passing in global_options_set here as we don't use
10658 the *options_set structs anyway. */
10660 queue_depth,
10664 /* Set up parameters to be used in prefetching algorithm. Do not
10665 override the defaults unless we are tuning for a core we have
10666 researched values for. */
10698 /* Use the alternative scheduling-pressure algorithm by default. */
10703 /* Enable sw prefetching at specified optimization level for
10704 CPUS that have prefetch. Lower optimization level threshold by 1
10705 when profiling is enabled. */
10713 }
10715 /* Print a hint with a suggestion for a core or architecture name that
10716 most closely resembles what the user passed in STR. ARCH is true if
10717 the user is asking for an architecture name. ARCH is false if the user
10718 is asking for a core name. */
10720 static void
10722 {
10728 #ifdef HAVE_LOCAL_CPU_DETECT
10729 /* Add also "native" as possible value. */
10732 #endif
10739 else
10743 }
10745 /* Print a hint with a suggestion for a core name that most closely resembles
10746 what the user passed in STR. */
10750 {
10752 }
10754 /* Print a hint with a suggestion for an architecture name that most closely
10755 resembles what the user passed in STR. */
10759 {
10761 }
10763 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
10764 specified in STR and throw errors if appropriate. Put the results if
10765 they are valid in RES and ISA_FLAGS. Return whether the option is
10766 valid. */
10768 static bool
10771 {
10772 enum aarch64_parse_opt_result parse_res
10779 {
10792 }
10795 }
10797 /* Validate a command-line -march option. Parse the arch and extensions
10798 (if any) specified in STR and throw errors if appropriate. Put the
10799 results, if they are valid, in RES and ISA_FLAGS. Return whether the
10800 option is valid. */
10802 static bool
10805 {
10806 enum aarch64_parse_opt_result parse_res
10813 {
10826 }
10829 }
10831 /* Validate a command-line -mtune option. Parse the cpu
10832 specified in STR and throw errors if appropriate. Put the
10833 result, if it is valid, in RES. Return whether the option is
10834 valid. */
10836 static bool
10838 {
10839 enum aarch64_parse_opt_result parse_res
10846 {
10856 }
10858 }
10860 /* Return the CPU corresponding to the enum CPU.
10861 If it doesn't specify a cpu, return the default. */
10865 {
10869 /* The & 0x3f is to extract the bottom 6 bits that encode the
10870 default cpu as selected by the --with-cpu GCC configure option
10871 in config.gcc.
10872 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
10873 flags mechanism should be reworked to make it more sane. */
10875 }
10877 /* Return the architecture corresponding to the enum ARCH.
10878 If it doesn't specify a valid architecture, return the default. */
10882 {
10889 }
10891 /* Return the VG value associated with -msve-vector-bits= value VALUE. */
10893 static poly_uint16
10895 {
10896 /* For now generate vector-length agnostic code for -msve-vector-bits=128.
10897 This ensures we can clearly distinguish SVE and Advanced SIMD modes when
10898 deciding which .md file patterns to use and when deciding whether
10899 something is a legitimate address or constant. */
10902 else
10904 }
10906 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
10907 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
10908 tuning structs. In particular it must set selected_tune and
10909 aarch64_isa_flags that define the available ISA features and tuning
10910 decisions. It must also set selected_arch as this will be used to
10911 output the .arch asm tags for each function. */
10913 static void
10915 {
10928 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
10929 If either of -march or -mtune is given, they override their
10930 respective component of -mcpu. */
10942 /* If the user did not specify a processor, choose the default
10943 one for them. This will be the CPU set during configuration using
10944 --with-cpu, otherwise it is "generic". */
10946 {
10948 {
10952 }
10953 else
10954 {
10955 /* Get default configure-time CPU. */
10958 }
10962 }
10963 /* If both -mcpu and -march are specified check that they are architecturally
10964 compatible, warn if they're not and prefer the -march ISA flags. */
10966 {
10968 {
10972 }
10977 }
10978 else
10979 {
10980 /* -mcpu but no -march. */
10987 }
10989 /* Set the arch as well as we will need it when outputing
10990 the .arch directive in assembly. */
10992 {
10995 }
11000 #ifndef HAVE_AS_MABI_OPTION
11001 /* The compiler may have been configured with 2.23.* binutils, which does
11002 not have support for ILP32. */
11005 #endif
11007 /* Convert -msve-vector-bits to a VG count. */
11013 /* Make sure we properly set up the explicit options. */
11024 /* Save these options as the default ones in case we push and pop them later
11025 while processing functions with potential target attributes. */
11026 target_option_default_node = target_option_current_node
11028 }
11030 /* Implement targetm.override_options_after_change. */
11032 static void
11034 {
11036 }
11040 {
11044 }
11046 void
11048 {
11050 }
11052 /* A checking mechanism for the implementation of the various code models. */
11053 static void
11055 {
11057 {
11059 {
11064 #ifdef HAVE_AS_SMALL_PIC_RELOCS
11066 ? AARCH64_CMODEL_SMALL_PIC
11068 #else
11070 #endif
11078 }
11079 }
11080 else
11082 }
11084 /* Implement TARGET_OPTION_SAVE. */
11086 static void
11088 {
11090 }
11092 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
11093 using the information saved in PTR. */
11095 static void
11097 {
11105 }
11107 /* Implement TARGET_OPTION_PRINT. */
11109 static void
11111 {
11122 }
11126 void
11128 {
11130 }
11132 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
11133 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
11134 make sure optab availability predicates are recomputed when necessary. */
11136 void
11138 {
11143 else
11145 }
11147 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
11148 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
11149 of the function, if such exists. This function may be called multiple
11150 times on a single function so use aarch64_previous_fndecl to avoid
11151 setting up identical state. */
11153 static void
11155 {
11159 tree old_tree = (aarch64_previous_fndecl
11165 /* If current function has no attributes but the previous one did,
11166 use the default node. */
11170 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
11171 the default have been handled by aarch64_save_restore_target_globals from
11172 aarch64_pragma_target_parse. */
11178 /* First set the target options. */
11182 }
11184 /* Enum describing the various ways we can handle attributes.
11185 In many cases we can reuse the generic option handling machinery. */
11187 enum aarch64_attr_opt_type
11188 {
11192 aarch64_attr_custom /* Attribute requires a custom handling function. */
11193 };
11195 /* All the information needed to handle a target attribute.
11196 NAME is the name of the attribute.
11197 ATTR_TYPE specifies the type of behavior of the attribute as described
11198 in the definition of enum aarch64_attr_opt_type.
11199 ALLOW_NEG is true if the attribute supports a "no-" form.
11200 HANDLER is the function that takes the attribute string as an argument
11201 It is needed only when the ATTR_TYPE is aarch64_attr_custom.
11202 OPT_NUM is the enum specifying the option that the attribute modifies.
11203 This is needed for attributes that mirror the behavior of a command-line
11204 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
11205 aarch64_attr_enum. */
11207 struct aarch64_attribute_info
11208 {
11214 };
11216 /* Handle the ARCH_STR argument to the arch= target attribute. */
11218 static bool
11220 {
11222 enum aarch64_parse_opt_result parse_res
11226 {
11231 }
11234 {
11247 }
11250 }
11252 /* Handle the argument CPU_STR to the cpu= target attribute. */
11254 static bool
11256 {
11258 enum aarch64_parse_opt_result parse_res
11262 {
11270 }
11273 {
11286 }
11289 }
11291 /* Handle the argument STR to the tune= target attribute. */
11293 static bool
11295 {
11297 enum aarch64_parse_opt_result parse_res
11301 {
11306 }
11309 {
11316 }
11319 }
11321 /* Parse an architecture extensions target attribute string specified in STR.
11322 For example "+fp+nosimd". Show any errors if needed. Return TRUE
11323 if successful. Update aarch64_isa_flags to reflect the ISA features
11324 modified. */
11326 static bool
11328 {
11332 /* We allow "+nothing" in the beginning to clear out all architectural
11333 features if the user wants to handpick specific features. */
11335 {
11338 }
11343 {
11346 }
11349 {
11360 }
11363 }
11365 /* The target attributes that we support. On top of these we also support just
11366 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
11367 handled explicitly in aarch64_process_one_target_attr. */
11370 {
11372 OPT_mgeneral_regs_only },
11374 OPT_mfix_cortex_a53_835769 },
11376 OPT_mfix_cortex_a53_843419 },
11380 OPT_momit_leaf_frame_pointer },
11383 OPT_march_ },
11386 OPT_mtune_ },
11388 OPT_msign_return_address_ },
11390 };
11392 /* Parse ARG_STR which contains the definition of one target attribute.
11393 Show appropriate errors if any or return true if the attribute is valid. */
11395 static bool
11397 {
11403 {
11406 }
11411 /* Skip leading whitespace. */
11413 str_to_check++;
11415 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
11416 It is easier to detect and handle it explicitly here rather than going
11417 through the machinery for the rest of the target attributes in this
11418 function. */
11423 {
11426 }
11429 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
11430 and point ARG to "foo". */
11432 {
11434 arg++;
11435 }
11439 {
11440 /* If the names don't match up, or the user has given an argument
11441 to an attribute that doesn't accept one, or didn't give an argument
11442 to an attribute that expects one, fail to match. */
11451 {
11454 }
11456 /* If the name matches but the attribute does not allow "no-" versions
11457 then we can't match. */
11459 {
11462 }
11465 {
11466 /* Has a custom handler registered.
11467 For example, cpu=, arch=, tune=. */
11474 /* Either set or unset a boolean option. */
11476 {
11484 }
11485 /* Set or unset a bit in the target_flags. aarch64_handle_option
11486 should know what mask to apply given the option number. */
11488 {
11490 /* We only need to specify the option number.
11491 aarch64_handle_option will know which mask to apply. */
11497 }
11498 /* Use the option setting machinery to set an option to an enum. */
11500 {
11507 {
11510 global_dc);
11511 }
11512 else
11513 {
11515 }
11517 }
11520 }
11521 }
11523 /* If we reached here we either have found an attribute and validated
11524 it or didn't match any. If we matched an attribute but its arguments
11525 were malformed we will have returned false already. */
11527 }
11529 /* Count how many times the character C appears in
11530 NULL-terminated string STR. */
11532 static unsigned int
11534 {
11537 {
11539 res++;
11541 str++;
11542 }
11545 }
11547 /* Parse the tree in ARGS that contains the target attribute information
11548 and update the global target options space. */
11550 bool
11552 {
11554 {
11555 do
11556 {
11559 {
11562 }
11567 }
11570 {
11573 }
11580 {
11583 }
11585 /* Used to catch empty spaces between commas i.e.
11586 attribute ((target ("attr1,,attr2"))). */
11589 /* Handle multiple target attributes separated by ','. */
11594 {
11595 num_attrs++;
11597 {
11600 }
11603 }
11606 {
11609 }
11612 }
11614 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
11615 process attribute ((target ("..."))). */
11617 static bool
11619 {
11622 tree old_optimize;
11626 /* If what we're processing is the current pragma string then the
11627 target option node is already stored in target_option_current_node
11628 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
11629 having to re-parse the string. This is especially useful to keep
11630 arm_neon.h compile times down since that header contains a lot
11631 of intrinsics enclosed in pragmas. */
11633 {
11636 }
11642 /* If the function changed the optimization levels as well as setting
11643 target options, start with the optimizations specified. */
11648 /* Save the current target options to restore at the end. */
11651 /* If fndecl already has some target attributes applied to it, unpack
11652 them so that we add this attribute on top of them, rather than
11653 overwriting them. */
11655 {
11661 }
11662 else
11668 /* Set up any additional state. */
11670 {
11672 /* Initialize SIMD builtins if we haven't already.
11673 Set current_target_pragma to NULL for the duration so that
11674 the builtin initialization code doesn't try to tag the functions
11675 being built with the attributes specified by any current pragma, thus
11676 going into an infinite recursion. */
11678 {
11683 }
11685 }
11686 else
11692 {
11697 }
11705 }
11707 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
11708 tri-bool options (yes, no, don't care) and the default value is
11709 DEF, determine whether to reject inlining. */
11711 static bool
11714 {
11715 /* If the callee doesn't care, always allow inlining. */
11719 /* If the caller doesn't care, always allow inlining. */
11723 /* Otherwise, allow inlining if either the callee and caller values
11724 agree, or if the callee is using the default value. */
11726 }
11728 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
11729 to inline CALLEE into CALLER based on target-specific info.
11730 Make sure that the caller and callee have compatible architectural
11731 features. Then go through the other possible target attributes
11732 and see if they can block inlining. Try not to reject always_inline
11733 callees unless they are incompatible architecturally. */
11735 static bool
11737 {
11749 /* Callee's ISA flags should be a subset of the caller's. */
11754 /* Allow non-strict aligned functions inlining into strict
11755 aligned ones. */
11765 /* If the architectural features match up and the callee is always_inline
11766 then the other attributes don't matter. */
11778 /* Honour explicit requests to workaround errata. */
11791 /* If the user explicitly specified -momit-leaf-frame-pointer for the
11792 caller and calle and they don't match up, reject inlining. */
11799 /* If the callee has specific tuning overrides, respect them. */
11804 /* If the user specified tuning override strings for the
11805 caller and callee and they don't match up, reject inlining.
11806 We just do a string compare here, we don't analyze the meaning
11807 of the string, as it would be too costly for little gain. */
11815 }
11817 /* Return true if SYMBOL_REF X binds locally. */
11819 static bool
11821 {
11825 }
11827 /* Return true if SYMBOL_REF X is thread local */
11828 static bool
11830 {
11838 }
11840 /* Classify a TLS symbol into one of the TLS kinds. */
11841 enum aarch64_symbol_type
11843 {
11847 {
11854 {
11860 }
11871 else
11880 }
11881 }
11883 /* Return the correct method for accessing X + OFFSET, where X is either
11884 a SYMBOL_REF or LABEL_REF. */
11886 enum aarch64_symbol_type
11888 {
11890 {
11892 {
11907 }
11908 }
11911 {
11916 {
11918 /* When we retrieve symbol + offset address, we have to make sure
11919 the offset does not cause overflow of the final address. But
11920 we have no way of knowing the address of symbol at compile time
11921 so we can't accurately say if the distance between the PC and
11922 symbol + offset is outside the addressible range of +/-1M in the
11923 TINY code model. So we rely on images not being greater than
11924 1M and cap the offset at 1M and anything beyond 1M will have to
11925 be loaded using an alternative mechanism. Furthermore if the
11926 symbol is a weak reference to something that isn't known to
11927 resolve to a symbol in this module, then force to memory. */
11935 /* Same reasoning as the tiny code model, but the offset cap here is
11936 4G. */
11957 /* This is alright even in PIC code as the constant
11958 pool reference is always PC relative and within
11959 the same translation unit. */
11962 else
11967 }
11968 }
11970 /* By default push everything into the constant pool. */
11972 }
11974 bool
11976 {
11978 }
11980 bool
11982 {
11990 }
11992 /* Implement TARGET_LEGITIMATE_CONSTANT_P hook. Return true for constants
11993 that should be rematerialized rather than spilled. */
11995 static bool
11997 {
11998 /* Support CSE and rematerialization of common constants. */
12004 /* Do not allow vector struct mode constants for Advanced SIMD.
12005 We could support 0 and -1 easily, but they need support in
12006 aarch64-simd.md. */
12011 /* Only accept variable-length vector constants if they can be
12012 handled directly.
12014 ??? It would be possible to handle rematerialization of other
12015 constants via secondary reloads. */
12022 /* Accept polynomial constants that can be calculated by using the
12023 destination of a move as the sole temporary. Constants that
12024 require a second temporary cannot be rematerialized (they can't be
12025 forced to memory and also aren't legitimate constants). */
12026 poly_int64 offset;
12030 /* If an offset is being added to something else, we need to allow the
12031 base to be moved into the destination register, meaning that there
12032 are no free temporaries for the offset. */
12037 /* Do not allow const (plus (anchor_symbol, const_int)). */
12041 /* Treat symbols as constants. Avoid TLS symbols as they are complex,
12042 so spilling them is better than rematerialization. */
12046 /* Label references are always constant. */
12051 }
12053 rtx
12055 {
12061 /* Can return in any reg. */
12064 }
12066 /* On AAPCS systems, this is the "struct __va_list". */
12069 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
12070 Return the type to use as __builtin_va_list.
12072 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
12074 struct __va_list
12075 {
12076 void *__stack;
12077 void *__gr_top;
12078 void *__vr_top;
12079 int __gr_offs;
12080 int __vr_offs;
12081 }; */
12083 static tree
12085 {
12086 tree va_list_name;
12089 /* Create the type. */
12091 /* Give it the required name. */
12093 TYPE_DECL,
12095 va_list_type);
12100 /* Create the fields. */
12103 ptr_type_node);
12106 ptr_type_node);
12109 ptr_type_node);
12112 integer_type_node);
12115 integer_type_node);
12117 /* Tell tree-stdarg pass about our internal offset fields.
12118 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
12119 purpose to identify whether the code is updating va_list internal
12120 offset fields through irregular way. */
12142 /* Compute its layout. */
12146 }
12148 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
12149 static void
12151 {
12155 tree t;
12169 {
12172 }
12181 NULL_TREE);
12183 NULL_TREE);
12185 NULL_TREE);
12187 NULL_TREE);
12189 NULL_TREE);
12191 /* Emit code to initialize STACK, which points to the next varargs stack
12192 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
12193 by named arguments. STACK is 8-byte aligned. */
12200 /* Emit code to initialize GRTOP, the top of the GR save area.
12201 virtual_incoming_args_rtx should have been 16 byte aligned. */
12206 /* Emit code to initialize VRTOP, the top of the VR save area.
12207 This address is gr_save_area_bytes below GRTOP, rounded
12208 down to the next 16-byte boundary. */
12218 /* Emit code to initialize GROFF, the offset from GRTOP of the
12219 next GPR argument. */
12224 /* Likewise emit code to initialize VROFF, the offset from FTOP
12225 of the next VR argument. */
12229 }
12231 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
12233 static tree
12236 {
12237 tree addr;
12243 machine_mode mode;
12270 type,
12274 {
12275 /* No frontends can create types with variable-sized modes, so we
12276 shouldn't be asked to pass or return them. */
12279 /* TYPE passed in fp/simd registers. */
12291 {
12294 }
12297 {
12299 }
12300 }
12301 else
12302 {
12303 /* TYPE passed in general registers. */
12316 {
12318 }
12319 }
12321 /* Get a local temporary for the field value. */
12324 /* Emit code to branch if off >= 0. */
12330 {
12331 /* Emit: offs = (offs + 15) & -16. */
12337 }
12338 else
12341 /* Update ap.__[g|v]r_offs */
12346 /* String up. */
12350 /* [cond2] if (ap.__[g|v]r_offs > 0) */
12355 /* String up: make sure the assignment happens before the use. */
12359 /* Prepare the trees handling the argument that is passed on the stack;
12360 the top level node will store in ON_STACK. */
12363 {
12364 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
12369 }
12370 else
12372 /* Advance ap.__stack */
12377 /* String up roundup and advance. */
12380 /* String up with arg */
12382 /* Big-endianness related address adjustment. */
12385 {
12389 }
12394 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
12404 {
12405 /* type ha; // treat as "struct {ftype field[n];}"
12406 ... [computing offs]
12407 for (i = 0; i <nregs; ++i, offs += 16)
12408 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
12409 return ha; */
12413 /* Declare a local variable. */
12417 /* Establish the base type. */
12419 {
12438 {
12442 }
12446 }
12448 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
12456 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
12458 {
12468 }
12472 }
12482 }
12484 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
12486 static void
12490 {
12492 CUMULATIVE_ARGS local_cum;
12496 /* The caller has advanced CUM up to, but not beyond, the last named
12497 argument. Advance a local copy of CUM past the last "real" named
12498 argument, to find out how many registers are left over. */
12502 /* Found out how many registers we need to save.
12503 Honor tree-stdvar analysis results. */
12512 {
12515 }
12518 {
12520 {
12523 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
12531 }
12533 {
12534 /* We can't use move_block_from_reg, because it will use
12535 the wrong mode, storing D regs only. */
12539 /* Set OFF to the offset from virtual_incoming_args_rtx of
12540 the first vector register. The VR save area lies below
12541 the GR one, and is aligned to 16 bytes. */
12548 {
12556 }
12557 }
12558 }
12560 /* We don't save the size into *PRETEND_SIZE because we want to avoid
12561 any complication of having crtl->args.pretend_args_size changed. */
12566 }
12568 static void
12570 {
12573 {
12575 {
12578 }
12579 }
12582 {
12585 }
12586 }
12588 /* Walk down the type tree of TYPE counting consecutive base elements.
12589 If *MODEP is VOIDmode, then set it to the first valid floating point
12590 type. If a non-floating point type is found, or if a floating point
12591 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
12592 otherwise return the count in the sub-tree. */
12593 static int
12595 {
12596 machine_mode mode;
12597 HOST_WIDE_INT size;
12600 {
12630 /* Use V2SImode and V4SImode as representatives of all 64-bit
12631 and 128-bit vector types. */
12634 {
12643 }
12648 /* Vector modes are considered to be opaque: two vectors are
12649 equivalent for the purposes of being homogeneous aggregates
12650 if they are the same size. */
12657 {
12661 /* Can't handle incomplete types nor sizes that are not
12662 fixed. */
12669 || !index
12680 /* There must be no padding. */
12686 }
12689 {
12692 tree field;
12694 /* Can't handle incomplete types nor sizes that are not
12695 fixed. */
12701 {
12709 }
12711 /* There must be no padding. */
12717 }
12721 {
12722 /* These aren't very interesting except in a degenerate case. */
12725 tree field;
12727 /* Can't handle incomplete types nor sizes that are not
12728 fixed. */
12734 {
12742 }
12744 /* There must be no padding. */
12750 }
12754 }
12757 }
12759 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
12760 type as described in AAPCS64 \S 4.1.2.
12762 See the comment above aarch64_composite_type_p for the notes on MODE. */
12764 static bool
12766 machine_mode mode)
12767 {
12777 }
12779 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
12780 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
12781 array types. The C99 floating-point complex types are also considered
12782 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
12783 types, which are GCC extensions and out of the scope of AAPCS64, are
12784 treated as composite types here as well.
12786 Note that MODE itself is not sufficient in determining whether a type
12787 is such a composite type or not. This is because
12788 stor-layout.c:compute_record_mode may have already changed the MODE
12789 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
12790 structure with only one field may have its MODE set to the mode of the
12791 field. Also an integer mode whose size matches the size of the
12792 RECORD_TYPE type may be used to substitute the original mode
12793 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
12794 solely relied on. */
12796 static bool
12798 machine_mode mode)
12799 {
12812 }
12814 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
12815 shall be passed or returned in simd/fp register(s) (providing these
12816 parameter passing registers are available).
12818 Upon successful return, *COUNT returns the number of needed registers,
12819 *BASE_MODE returns the mode of the individual register and when IS_HAF
12820 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
12821 floating-point aggregate or a homogeneous short-vector aggregate. */
12823 static bool
12825 const_tree type,
12829 {
12837 {
12840 }
12842 {
12846 }
12848 {
12852 {
12855 }
12856 else
12858 }
12859 else
12864 }
12866 /* Implement TARGET_STRUCT_VALUE_RTX. */
12868 static rtx
12871 {
12873 }
12875 /* Implements target hook vector_mode_supported_p. */
12876 static bool
12878 {
12881 }
12883 /* Return appropriate SIMD container
12884 for MODE within a vector of WIDTH bits. */
12885 static machine_mode
12887 {
12890 {
12907 }
12911 {
12914 {
12931 }
12932 else
12934 {
12947 }
12948 }
12950 }
12952 /* Return 128-bit container as the preferred SIMD mode for MODE. */
12953 static machine_mode
12955 {
12958 }
12960 /* Return a list of possible vector sizes for the vectorizer
12961 to iterate over. */
12962 static void
12964 {
12969 }
12971 /* Implement TARGET_MANGLE_TYPE. */
12975 {
12976 /* The AArch64 ABI documents say that "__va_list" has to be
12977 managled as if it is in the "std" namespace. */
12981 /* Half-precision float. */
12985 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
12986 builtin types. */
12990 /* Use the default mangling. */
12992 }
12994 /* Find the first rtx_insn before insn that will generate an assembly
12995 instruction. */
12999 {
13003 do
13004 {
13006 }
13010 }
13012 static bool
13014 {
13016 /* A number of these may be AArch32 only. */
13021 };
13024 {
13027 }
13030 }
13032 /* Check if there is a register dependency between a load and the insn
13033 for which we hold recog_data. */
13035 static bool
13037 {
13038 rtx load_reg;
13048 {
13054 }
13056 }
13059 /* When working around the Cortex-A53 erratum 835769,
13060 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
13061 instruction and has a preceding memory instruction such that a NOP
13062 should be inserted between them. */
13064 bool
13066 {
13069 rtx body;
13082 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
13083 Restore recog state to INSN to avoid state corruption. */
13091 /* If the previous insn is a memory op and there is no dependency between
13092 it and the DImode madd, emit a NOP between them. If body is NULL then we
13093 have a complex memory operation, probably a load/store pair.
13094 Be conservative for now and emit a NOP. */
13101 }
13104 /* Implement FINAL_PRESCAN_INSN. */
13106 void
13108 {
13111 }
13114 /* Return true if BASE_OR_STEP is a valid immediate operand for an SVE INDEX
13115 instruction. */
13117 bool
13119 {
13122 }
13124 /* Return true if X is a valid immediate for the SVE ADD and SUB
13125 instructions. Negate X first if NEGATE_P is true. */
13127 bool
13129 {
13130 rtx elt;
13144 }
13146 /* Return true if X is a valid immediate operand for an SVE logical
13147 instruction such as AND. */
13149 bool
13151 {
13152 rtx elt;
13158 }
13160 /* Return true if X is a valid immediate for the SVE DUP and CPY
13161 instructions. */
13163 bool
13165 {
13166 rtx elt;
13176 }
13178 /* Return true if X is a valid immediate operand for an SVE CMP instruction.
13179 SIGNED_P says whether the operand is signed rather than unsigned. */
13181 bool
13183 {
13184 rtx elt;
13188 && (signed_p
13191 }
13193 /* Return true if X is a valid immediate operand for an SVE FADD or FSUB
13194 instruction. Negate X first if NEGATE_P is true. */
13196 bool
13198 {
13199 rtx elt;
13200 REAL_VALUE_TYPE r;
13216 }
13218 /* Return true if X is a valid immediate operand for an SVE FMUL
13219 instruction. */
13221 bool
13223 {
13224 rtx elt;
13226 /* GCC will never generate a multiply with an immediate of 2, so there is no
13227 point testing for it (even though it is a valid constant). */
13231 }
13233 /* Return true if replicating VAL32 is a valid 2-byte or 4-byte immediate
13234 for the Advanced SIMD operation described by WHICH and INSN. If INFO
13235 is nonnull, use it to describe valid immediates. */
13236 static bool
13241 {
13242 /* Try a 4-byte immediate with LSL. */
13245 {
13250 }
13252 /* Try a 2-byte immediate with LSL. */
13257 {
13262 }
13264 /* Try a 4-byte immediate with MSL, except for cases that MVN
13265 can handle. */
13268 {
13271 {
13276 }
13277 }
13280 }
13282 /* Return true if replicating VAL64 is a valid immediate for the
13283 Advanced SIMD operation described by WHICH. If INFO is nonnull,
13284 use it to describe valid immediates. */
13285 static bool
13289 {
13295 {
13306 /* Try using a replicated byte. */
13310 {
13314 }
13315 }
13317 /* Try using a bit-to-bytemask. */
13319 {
13322 {
13326 }
13328 {
13332 }
13333 }
13335 }
13337 /* Return true if replicating VAL64 gives a valid immediate for an SVE MOV
13338 instruction. If INFO is nonnull, use it to describe valid immediates. */
13340 static bool
13343 {
13347 {
13351 {
13356 }
13357 }
13360 {
13361 /* DUP with no shift. */
13365 }
13367 {
13368 /* DUP with LSL #8. */
13372 }
13374 {
13375 /* DUPM. */
13379 }
13381 }
13383 /* Return true if OP is a valid SIMD immediate for the operation
13384 described by WHICH. If INFO is nonnull, use it to describe valid
13385 immediates. */
13386 bool
13389 {
13403 {
13412 }
13416 else
13419 /* Handle PFALSE and PTRUE. */
13424 scalar_float_mode elt_float_mode;
13427 {
13431 {
13435 }
13436 }
13444 /* Expand the vector constant out into a byte vector, with the least
13445 significant byte of the register first. */
13449 {
13450 /* The vector is provided in gcc endian-neutral fashion.
13451 For aarch64_be Advanced SIMD, it must be laid out in the vector
13452 register in reverse order. */
13464 {
13467 }
13468 }
13470 /* The immediate must repeat every eight bytes. */
13476 /* Get the repeating 8-byte value as an integer. No endian correction
13477 is needed here because bytes is already in lsb-first order. */
13485 else
13487 }
13489 /* Check whether X is a VEC_SERIES-like constant that starts at 0 and
13490 has a step in the range of INDEX. Return the index expression if so,
13491 otherwise return null. */
13492 rtx
13494 {
13501 }
13503 /* Check of immediate shift constants are within range. */
13504 bool
13506 {
13510 else
13512 }
13514 /* Return the bitmask CONST_INT to select the bits required by a zero extract
13515 operation of width WIDTH at bit position POS. */
13517 rtx
13519 {
13523 unsigned HOST_WIDE_INT mask
13526 }
13528 bool
13530 {
13549 }
13551 /* Return a const_int vector of VAL. */
13552 rtx
13554 {
13557 }
13559 /* Check OP is a legal scalar immediate for the MOVI instruction. */
13561 bool
13563 {
13564 machine_mode vmode;
13569 }
13571 /* Construct and return a PARALLEL RTX vector with elements numbering the
13572 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
13573 the vector - from the perspective of the architecture. This does not
13574 line up with GCC's perspective on lane numbers, so we end up with
13575 different masks depending on our target endian-ness. The diagram
13576 below may help. We must draw the distinction when building masks
13577 which select one half of the vector. An instruction selecting
13578 architectural low-lanes for a big-endian target, must be described using
13579 a mask selecting GCC high-lanes.
13581 Big-Endian Little-Endian
13583 GCC 0 1 2 3 3 2 1 0
13584 | x | x | x | x | | x | x | x | x |
13585 Architecture 3 2 1 0 3 2 1 0
13587 Low Mask: { 2, 3 } { 0, 1 }
13588 High Mask: { 0, 1 } { 2, 3 }
13590 MODE Is the mode of the vector and NUNITS is the number of units in it. */
13592 rtx
13594 {
13599 rtx t1;
13604 else
13612 }
13614 /* Check OP for validity as a PARALLEL RTX vector with elements
13615 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
13616 from the perspective of the architecture. See the diagram above
13617 aarch64_simd_vect_par_cnst_half for more details. */
13619 bool
13622 {
13636 {
13643 }
13645 }
13647 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
13648 HIGH (exclusive). */
13649 void
13651 const_tree exp)
13652 {
13653 HOST_WIDE_INT lane;
13658 {
13661 else
13663 }
13664 }
13666 /* Peform endian correction on lane number N, which indexes a vector
13667 of mode MODE, and return the result as an SImode rtx. */
13669 rtx
13671 {
13673 }
13675 /* Return TRUE if OP is a valid vector addressing mode. */
13677 bool
13679 {
13682 }
13684 /* Return true if OP is a valid MEM operand for an SVE LD1R instruction. */
13686 bool
13688 {
13690 scalar_mode mode;
13697 }
13699 /* Return true if OP is a valid MEM operand for an SVE LDR instruction.
13700 The conditions for STR are the same. */
13701 bool
13703 {
13710 }
13712 /* Return true if OP is a valid MEM operand for an SVE_STRUCT mode.
13713 We need to be able to access the individual pieces, so the range
13714 is different from LD[234] and ST[234]. */
13715 bool
13717 {
13724 ADDR_QUERY_ANY)
13732 }
13734 /* Emit a register copy from operand to operand, taking care not to
13735 early-clobber source registers in the process.
13737 COUNT is the number of components into which the copy needs to be
13738 decomposed. */
13739 void
13742 {
13752 else
13756 }
13758 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
13759 one of VSTRUCT modes: OI, CI, or XI. */
13760 int
13762 {
13763 /* This is only used (and only meaningful) for Advanced SIMD, not SVE. */
13765 }
13767 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
13768 alignment of a vector to 128 bits. SVE predicates have an alignment of
13769 16 bits. */
13770 static HOST_WIDE_INT
13772 {
13774 /* ??? Checking the mode isn't ideal, but VECTOR_BOOLEAN_TYPE_P can
13775 be set for non-predicate vectors of booleans. Modes are the most
13776 direct way we have of identifying real SVE predicate types. */
13780 }
13782 /* Implement target hook TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT. */
13783 static HOST_WIDE_INT
13785 {
13787 {
13788 /* If the length of the vector is fixed, try to align to that length,
13789 otherwise don't try to align at all. */
13790 HOST_WIDE_INT result;
13794 }
13796 }
13798 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
13799 static bool
13801 {
13805 /* For fixed-length vectors, check that the vectorizer will aim for
13806 full-vector alignment. This isn't true for generic GCC vectors
13807 that are wider than the ABI maximum of 128 bits. */
13813 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
13815 }
13817 /* Return true if the vector misalignment factor is supported by the
13818 target. */
13819 static bool
13823 {
13825 {
13826 /* Return if movmisalign pattern is not supported for this mode. */
13830 /* Misalignment factor is unknown at compile time. */
13833 }
13835 is_packed);
13836 }
13838 /* If VALS is a vector constant that can be loaded into a register
13839 using DUP, generate instructions to do so and return an RTX to
13840 assign to the register. Otherwise return NULL_RTX. */
13841 static rtx
13843 {
13846 rtx x;
13851 /* We can load this constant by using DUP and a constant in a
13852 single ARM register. This will be cheaper than a vector
13853 load. */
13856 }
13859 /* Generate code to load VALS, which is a PARALLEL containing only
13860 constants (for vec_init) or CONST_VECTOR, efficiently into a
13861 register. Returns an RTX to copy into the register, or NULL_RTX
13862 for a PARALLEL that can not be converted into a CONST_VECTOR. */
13863 static rtx
13865 {
13867 rtx const_dup;
13875 {
13876 /* A CONST_VECTOR must contain only CONST_INTs and
13877 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
13878 Only store valid constants in a CONST_VECTOR. */
13881 {
13884 n_const++;
13885 }
13888 }
13889 else
13894 /* Load using MOVI/MVNI. */
13897 /* Loaded using DUP. */
13900 /* Load from constant pool. We can not take advantage of single-cycle
13901 LD1 because we need a PC-relative addressing mode. */
13903 else
13904 /* A PARALLEL containing something not valid inside CONST_VECTOR.
13905 We can not construct an initializer. */
13907 }
13909 /* Expand a vector initialisation sequence, such that TARGET is
13910 initialised to contain VALS. */
13912 void
13914 {
13917 /* The number of vector elements. */
13919 /* The number of vector elements which are not constant. */
13922 /* The first element of vals. */
13926 /* Count the number of variable elements to initialise. */
13928 {
13932 else
13936 }
13938 /* No variable elements, hand off to aarch64_simd_make_constant which knows
13939 how best to handle this. */
13941 {
13944 {
13947 }
13948 }
13950 /* Splat a single non-constant element if we can. */
13952 {
13956 }
13961 /* If there are only variable elements, try to optimize
13962 the insertion using dup for the most common element
13963 followed by insertions. */
13965 /* The algorithm will fill matches[*][0] with the earliest matching element,
13966 and matches[X][1] with the count of duplicate elements (if X is the
13967 earliest element which has duplicates). */
13970 {
13973 {
13975 {
13977 {
13981 }
13982 }
13983 }
13988 {
13991 }
13993 /* Create a duplicate of the most common element, unless all elements
13994 are equally useless to us, in which case just immediately set the
13995 vector register using the first element. */
13998 {
13999 /* For vectors of two 64-bit elements, we can do even better. */
14004 {
14007 /* Combine can pick up this case, but handling it directly
14008 here leaves clearer RTL.
14010 This is load_pair_lanes<mode>, and also gives us a clean-up
14011 for store_pair_lanes<mode>. */
14014 && !STRICT_ALIGNMENT
14019 {
14020 rtx t;
14023 else
14027 }
14028 }
14029 /* The subreg-move sequence below will move into lane zero of the
14030 vector register. For big-endian we want that position to hold
14031 the last element of VALS. */
14035 }
14036 else
14037 {
14040 }
14042 /* Insert the rest. */
14044 {
14050 }
14052 }
14054 /* Initialise a vector which is part-variable. We want to first try
14055 to build those lanes which are constant in the most efficient way we
14056 can. */
14058 {
14061 /* Load constant part of vector. We really don't care what goes into the
14062 parts we will overwrite, but we're more likely to be able to load the
14063 constant efficiently if it has fewer, larger, repeating parts
14064 (see aarch64_simd_valid_immediate). */
14066 {
14072 {
14073 /* Look in the copied vector, as more elements are const. */
14076 {
14079 }
14080 }
14082 }
14084 }
14086 /* Insert the variable lanes directly. */
14088 {
14094 }
14095 }
14097 static unsigned HOST_WIDE_INT
14099 {
14103 }
14105 /* Select a format to encode pointers in exception handling data. */
14106 int
14108 {
14111 {
14117 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
14118 for everything. */
14122 /* No assumptions here. 8-byte relocs required. */
14125 }
14127 }
14129 /* The last .arch and .tune assembly strings that we printed. */
14133 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
14134 by the function fndecl. */
14136 void
14138 tree fndecl)
14139 {
14145 else
14156 /* Only update the assembler .arch string if it is distinct from the last
14157 such string we printed. */
14160 {
14163 }
14165 /* Print the cpu name we're tuning for in the comments, might be
14166 useful to readers of the generated asm. Do it only when it changes
14167 from function to function and verbose assembly is requested. */
14172 {
14176 }
14178 /* Don't forget the type directive for ELF. */
14181 }
14183 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
14185 static void
14187 {
14204 }
14206 /* Emit load exclusive. */
14208 static void
14211 {
14215 {
14222 }
14225 }
14227 /* Emit store exclusive. */
14229 static void
14232 {
14236 {
14243 }
14246 }
14248 /* Mark the previous jump instruction as unlikely. */
14250 static void
14252 {
14255 }
14257 /* Expand a compare and swap pattern. */
14259 void
14261 {
14266 gen_cas_fn gen;
14268 {
14269 gen_aarch64_compare_and_swapqi,
14270 gen_aarch64_compare_and_swaphi,
14271 gen_aarch64_compare_and_swapsi,
14272 gen_aarch64_compare_and_swapdi
14273 };
14275 {
14276 gen_aarch64_compare_and_swapqi_lse,
14277 gen_aarch64_compare_and_swaphi_lse,
14278 gen_aarch64_compare_and_swapsi_lse,
14279 gen_aarch64_compare_and_swapdi_lse
14280 };
14293 /* Normally the succ memory model must be stronger than fail, but in the
14294 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
14295 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
14302 {
14305 /* For short modes, we're going to perform the comparison in SImode,
14306 so do the zero-extension now. */
14310 /* Fall through. */
14314 /* Force the value into a register if needed. */
14321 }
14324 {
14331 }
14334 else
14345 }
14347 /* Test whether the target supports using a atomic load-operate instruction.
14348 CODE is the operation and AFTER is TRUE if the data in memory after the
14349 operation should be returned and FALSE if the data before the operation
14350 should be returned. Returns FALSE if the operation isn't supported by the
14351 architecture. */
14353 bool
14355 {
14360 {
14370 }
14371 }
14373 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
14374 sequence implementing an atomic operation. */
14376 static void
14378 {
14385 {
14387 }
14388 }
14390 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
14391 for the data in memory. EXPECTED is the value expected to be in memory.
14392 DESIRED is the value to store to memory. MEM is the memory location. MODEL
14393 is the memory ordering to use. */
14395 void
14398 rtx model)
14399 {
14401 machine_mode mode;
14406 {
14413 }
14415 /* Move the expected value into the CAS destination register. */
14418 /* Emit the CAS. */
14421 /* Compare the expected value with the value loaded by the CAS, to establish
14422 whether the swap was made. */
14424 }
14426 /* Split a compare and swap pattern. */
14428 void
14430 {
14432 machine_mode mode;
14437 rtx model_rtx;
14449 /* When OLDVAL is zero and we want the strong version we can emit a tighter
14450 loop:
14451 .label1:
14452 LD[A]XR rval, [mem]
14453 CBNZ rval, .label2
14454 ST[L]XR scratch, newval, [mem]
14455 CBNZ scratch, .label1
14456 .label2:
14457 CMP rval, 0. */
14462 {
14465 }
14468 /* The initial load can be relaxed for a __sync operation since a final
14469 barrier will be emitted to stop code hoisting. */
14473 else
14477 {
14482 }
14483 else
14484 {
14490 }
14495 {
14500 }
14501 else
14502 {
14506 }
14509 /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
14510 to set the condition flags. If this is not used it will be removed by
14511 later passes. */
14513 {
14517 }
14518 /* Emit any final barrier needed for a __sync operation. */
14521 }
14523 /* Emit a BIC instruction. */
14525 static void
14527 {
14532 {
14537 }
14540 }
14542 /* Emit an atomic swap. */
14544 static void
14547 {
14551 {
14558 }
14561 }
14563 /* Operations supported by aarch64_emit_atomic_load_op. */
14565 enum aarch64_atomic_load_op_code
14566 {
14570 AARCH64_LDOP_BIC /* A & ~B */
14571 };
14573 /* Emit an atomic load-operate. */
14575 static void
14579 {
14582 {
14583 gen_aarch64_atomic_loadaddqi,
14584 gen_aarch64_atomic_loadaddhi,
14585 gen_aarch64_atomic_loadaddsi,
14586 gen_aarch64_atomic_loadadddi
14587 };
14589 {
14590 gen_aarch64_atomic_loadeorqi,
14591 gen_aarch64_atomic_loadeorhi,
14592 gen_aarch64_atomic_loadeorsi,
14593 gen_aarch64_atomic_loadeordi
14594 };
14596 {
14597 gen_aarch64_atomic_loadsetqi,
14598 gen_aarch64_atomic_loadsethi,
14599 gen_aarch64_atomic_loadsetsi,
14600 gen_aarch64_atomic_loadsetdi
14601 };
14603 {
14604 gen_aarch64_atomic_loadclrqi,
14605 gen_aarch64_atomic_loadclrhi,
14606 gen_aarch64_atomic_loadclrsi,
14607 gen_aarch64_atomic_loadclrdi
14608 };
14609 aarch64_atomic_load_op_fn gen;
14613 {
14620 }
14623 {
14630 }
14633 }
14635 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
14636 location to store the data read from memory. OUT_RESULT is the location to
14637 store the result of the operation. MEM is the memory location to read and
14638 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
14639 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
14640 be NULL. */
14642 void
14645 {
14649 aarch64_atomic_load_op_code ldop_code;
14650 rtx src;
14651 rtx x;
14659 /* Make sure the value is in a register, putting it into a destination
14660 register if it needs to be manipulated. */
14663 {
14666 }
14667 else
14671 /* Preprocess the data for the operation as necessary. If the operation is
14672 a SET then emit a swap instruction and finish. */
14674 {
14680 /* Negate the value and treat it as a PLUS. */
14681 {
14682 rtx neg_src;
14684 /* Resize the value if necessary. */
14693 }
14694 /* Fall-through. */
14708 {
14709 rtx not_src;
14711 /* Resize the value if necessary. */
14720 }
14725 /* The operation can't be done with atomic instructions. */
14727 }
14731 /* If necessary, calculate the data in memory after the update by redoing the
14732 operation from values in registers. */
14737 {
14741 }
14746 {
14762 }
14767 }
14769 /* Split an atomic operation. */
14771 void
14774 {
14780 rtx x;
14782 /* Split the atomic operation into a sequence. */
14790 else
14794 /* The initial load can be relaxed for a __sync operation since a final
14795 barrier will be emitted to stop code hoisting. */
14799 else
14803 {
14817 {
14820 }
14821 /* Fall through. */
14827 }
14837 /* Emit any final barrier needed for a __sync operation. */
14840 }
14842 static void
14844 {
14845 /* Half-precision float operations. The compiler handles all operations
14846 with NULL libfuncs by converting to SFmode. */
14848 /* Conversions. */
14852 /* Arithmetic. */
14859 /* Comparisons. */
14867 }
14869 /* Target hook for c_mode_for_suffix. */
14870 static machine_mode
14872 {
14877 }
14879 /* We can only represent floating point constants which will fit in
14880 "quarter-precision" values. These values are characterised by
14881 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
14882 by:
14884 (-1)^s * (n/16) * 2^r
14886 Where:
14887 's' is the sign bit.
14888 'n' is an integer in the range 16 <= n <= 31.
14889 'r' is an integer in the range -3 <= r <= 4. */
14891 /* Return true iff X can be represented by a quarter-precision
14892 floating point immediate operand X. Note, we cannot represent 0.0. */
14893 bool
14895 {
14896 /* This represents our current view of how many bits
14897 make up the mantissa. */
14907 /* We don't support HFmode constants yet. */
14913 /* We cannot represent infinities, NaNs or +/-zero. We won't
14914 know if we have +zero until we analyse the mantissa, but we
14915 can reject the other invalid values. */
14920 /* Extract exponent. */
14924 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
14925 highest (sign) bit, with a fixed binary point at bit point_pos.
14926 m1 holds the low part of the mantissa, m2 the high part.
14927 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
14928 bits for the mantissa, this can fail (low bits will be lost). */
14932 /* If the low part of the mantissa has bits set we cannot represent
14933 the value. */
14936 /* We have rejected the lower HOST_WIDE_INT, so update our
14937 understanding of how many bits lie in the mantissa and
14938 look only at the high HOST_WIDE_INT. */
14942 /* We can only represent values with a mantissa of the form 1.xxxx. */
14947 /* Having filtered unrepresentable values, we may now remove all
14948 but the highest 5 bits. */
14951 /* We cannot represent the value 0.0, so reject it. This is handled
14952 elsewhere. */
14956 /* Then, as bit 4 is always set, we can mask it off, leaving
14957 the mantissa in the range [0, 15]. */
14961 /* GCC internally does not use IEEE754-like encoding (where normalized
14962 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
14963 Our mantissa values are shifted 4 places to the left relative to
14964 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
14965 by 5 places to correct for GCC's representation. */
14969 }
14971 /* Returns the string with the instruction for AdvSIMD MOVI, MVNI, ORR or BIC
14972 immediate with a CONST_VECTOR of MODE and WIDTH. WHICH selects whether to
14973 output MOVI/MVNI, ORR or BIC immediate. */
14977 {
14987 /* This will return true to show const_vector is legal for use as either
14988 a AdvSIMD MOVI instruction (or, implicitly, MVNI), ORR or BIC immediate.
14989 It will also update INFO to show how the immediate should be generated.
14990 WHICH selects whether to check for MOVI/MVNI, ORR or BIC. */
14998 {
15000 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
15001 move immediate path. */
15004 else
15005 {
15014 else
15018 }
15019 }
15024 {
15034 else
15038 }
15039 else
15040 {
15041 /* For AARCH64_CHECK_BIC and AARCH64_CHECK_ORR. */
15047 else
15051 }
15053 }
15057 {
15059 /* If a floating point number was passed and we desire to use it in an
15060 integer mode do the conversion to integer. */
15062 {
15067 }
15069 machine_mode vmode;
15070 /* use a 64 bit mode for everything except for DI/DF mode, where we use
15071 a 128 bit vector mode. */
15077 }
15079 /* Return the output string to use for moving immediate CONST_VECTOR
15080 into an SVE register. */
15084 {
15095 {
15100 }
15103 {
15106 else
15107 {
15117 }
15118 }
15123 }
15125 /* Return the asm format for a PTRUE instruction whose destination has
15126 mode MODE. SUFFIX is the element size suffix. */
15130 {
15135 else
15138 }
15140 /* Split operands into moves from op[1] + op[2] into op[0]. */
15142 void
15144 {
15155 {
15156 /* No-op move. Can't split to nothing; emit something. */
15159 }
15161 /* Preserve register attributes for variable tracking. */
15166 /* Special case of reversed high/low parts. */
15169 {
15173 }
15175 {
15176 /* Try to avoid unnecessary moves if part of the result
15177 is in the right place already. */
15182 }
15183 else
15184 {
15189 }
15190 }
15192 /* vec_perm support. */
15194 struct expand_vec_perm_d
15195 {
15197 vec_perm_indices perm;
15198 machine_mode vmode;
15202 };
15204 /* Generate a variable permutation. */
15206 static void
15208 {
15219 {
15221 {
15222 /* Expand the argument to a V16QI mode by duplicating it. */
15226 }
15227 else
15228 {
15230 }
15231 }
15232 else
15233 {
15234 rtx pair;
15237 {
15241 }
15242 else
15243 {
15247 }
15248 }
15249 }
15251 /* Expand a vec_perm with the operands given by TARGET, OP0, OP1 and SEL.
15252 NELT is the number of elements in the vector. */
15254 void
15257 {
15260 rtx mask;
15262 /* The TBL instruction does not use a modulo index, so we must take care
15263 of that ourselves. */
15268 /* For big-endian, we also need to reverse the index within the vector
15269 (but not which vector). */
15271 {
15272 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
15277 }
15279 }
15281 /* Generate (set TARGET (unspec [OP0 OP1] CODE)). */
15283 static void
15285 {
15289 }
15291 /* Expand an SVE vec_perm with the given operands. */
15293 void
15295 {
15298 /* Enforced by the pattern condition. */
15301 /* Note: vec_perm indices are supposed to wrap when they go beyond the
15302 size of the two value vectors, i.e. the upper bits of the indices
15303 are effectively ignored. SVE TBL instead produces 0 for any
15304 out-of-range indices, so we need to modulo all the vec_perm indices
15305 to ensure they are all in range. */
15308 /* Check if the sel only references the first values vector. */
15311 {
15314 }
15316 /* Check if the two values vectors are the same. */
15318 {
15324 }
15326 /* Run TBL on for each value vector and combine the results. */
15333 {
15338 }
15345 else
15347 }
15349 /* Recognize patterns suitable for the TRN instructions. */
15350 static bool
15352 {
15353 HOST_WIDE_INT odd;
15361 /* Note that these are little-endian tests.
15362 We correct for big-endian later. */
15369 /* Success! */
15375 /* We don't need a big-endian lane correction for SVE; see the comment
15376 at the head of aarch64-sve.md for details. */
15378 {
15381 }
15387 }
15389 /* Recognize patterns suitable for the UZP instructions. */
15390 static bool
15392 {
15393 HOST_WIDE_INT odd;
15400 /* Note that these are little-endian tests.
15401 We correct for big-endian later. */
15407 /* Success! */
15413 /* We don't need a big-endian lane correction for SVE; see the comment
15414 at the head of aarch64-sve.md for details. */
15416 {
15419 }
15425 }
15427 /* Recognize patterns suitable for the ZIP instructions. */
15428 static bool
15430 {
15439 /* Note that these are little-endian tests.
15440 We correct for big-endian later. */
15448 /* Success! */
15454 /* We don't need a big-endian lane correction for SVE; see the comment
15455 at the head of aarch64-sve.md for details. */
15457 {
15460 }
15466 }
15468 /* Recognize patterns for the EXT insn. */
15470 static bool
15472 {
15473 HOST_WIDE_INT location;
15474 rtx offset;
15476 /* The first element always refers to the first vector.
15477 Check if the extracted indices are increasing by one. */
15483 /* Success! */
15487 /* The case where (location == 0) is a no-op for both big- and little-endian,
15488 and is removed by the mid-end at optimization levels -O1 and higher.
15490 We don't need a big-endian lane correction for SVE; see the comment
15491 at the head of aarch64-sve.md for details. */
15493 {
15494 /* After setup, we want the high elements of the first vector (stored
15495 at the LSB end of the register), and the low elements of the second
15496 vector (stored at the MSB end of the register). So swap. */
15498 /* location != 0 (above), so safe to assume (nelt - location) < nelt.
15499 to_constant () is safe since this is restricted to Advanced SIMD
15500 vectors. */
15502 }
15508 UNSPEC_EXT));
15510 }
15512 /* Recognize patterns for the REV{64,32,16} insns, which reverse elements
15513 within each 64-bit, 32-bit or 16-bit granule. */
15515 static bool
15517 {
15518 HOST_WIDE_INT diff;
15520 machine_mode pred_mode;
15529 {
15532 }
15534 {
15537 }
15539 {
15542 }
15543 else
15551 /* Success! */
15557 {
15560 UNSPEC_MERGE_PTRUE);
15561 }
15564 }
15566 /* Recognize patterns for the REV insn, which reverses elements within
15567 a full vector. */
15569 static bool
15571 {
15580 /* Success! */
15587 }
15589 static bool
15591 {
15593 rtx in0;
15594 HOST_WIDE_INT elt;
15596 rtx lane;
15606 /* Success! */
15610 /* The generic preparation in aarch64_expand_vec_perm_const_1
15611 swaps the operand order and the permute indices if it finds
15612 d->perm[0] to be in the second operand. Thus, we can always
15613 use d->op0 and need not do any extra arithmetic to get the
15614 correct lane number. */
15622 }
15624 static bool
15626 {
15630 /* Make sure that the indices are constant. */
15639 /* Generic code will try constant permutation twice. Once with the
15640 original mode and again with the elements lowered to QImode.
15641 So wait and don't do the selector expansion ourselves. */
15645 /* to_constant is safe since this routine is specific to Advanced SIMD
15646 vectors. */
15649 /* If big-endian and two vectors we end up with a weird mixed-endian
15650 mode on NEON. Reverse the index within each word but not the word
15651 itself. to_constant is safe because we checked is_constant above. */
15661 }
15663 /* Try to implement D using an SVE TBL instruction. */
15665 static bool
15667 {
15670 /* Permuting two variable-length vectors could overflow the
15671 index range. */
15682 }
15684 static bool
15686 {
15687 /* The pattern matching functions above are written to look for a small
15688 number to begin the sequence (0, 1, N/2). If we begin with an index
15689 from the second operand, we can swap the operands. */
15692 {
15695 }
15701 {
15720 }
15722 }
15724 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
15726 static bool
15729 {
15732 /* Check whether the mask can be applied to a single vector. */
15736 {
15739 }
15741 {
15744 }
15745 else
15765 }
15767 /* Generate a byte permute mask for a register of mode MODE,
15768 which has NUNITS units. */
15770 rtx
15772 {
15773 /* We have to reverse each vector because we dont have
15774 a permuted load that can reverse-load according to ABI rules. */
15775 rtx mask;
15788 }
15790 /* Return true if X is a valid second operand for the SVE instruction
15791 that implements integer comparison OP_CODE. */
15793 static bool
15795 {
15800 {
15815 }
15816 }
15818 /* Use predicated SVE instructions to implement the equivalent of:
15820 (set TARGET OP)
15822 given that PTRUE is an all-true predicate of the appropriate mode. */
15824 static void
15826 {
15829 UNSPEC_MERGE_PTRUE);
15832 }
15834 /* Likewise, but also clobber the condition codes. */
15836 static void
15838 {
15841 UNSPEC_MERGE_PTRUE);
15844 }
15846 /* Return the UNSPEC_COND_* code for comparison CODE. */
15848 static unsigned int
15850 {
15852 {
15867 }
15868 }
15870 /* Emit:
15872 (set TARGET (unspec [PRED OP0 OP1] UNSPEC_COND_<X>))
15874 where <X> is the operation associated with comparison CODE. This form
15875 of instruction is used when (and (CODE OP0 OP1) PRED) would have different
15876 semantics, such as when PRED might not be all-true and when comparing
15877 inactive lanes could have side effects. */
15879 static void
15882 {
15887 }
15889 /* Expand an SVE integer comparison using the SVE equivalent of:
15891 (set TARGET (CODE OP0 OP1)). */
15893 void
15895 {
15905 }
15907 /* Emit the SVE equivalent of:
15909 (set TMP1 (CODE1 OP0 OP1))
15910 (set TMP2 (CODE2 OP0 OP1))
15911 (set TARGET (ior:PRED_MODE TMP1 TMP2))
15913 PTRUE is an all-true predicate with the same mode as TARGET. */
15915 static void
15918 {
15927 }
15929 /* Emit the SVE equivalent of:
15931 (set TMP (CODE OP0 OP1))
15932 (set TARGET (not TMP))
15934 PTRUE is an all-true predicate with the same mode as TARGET. */
15936 static void
15939 {
15945 }
15947 /* Expand an SVE floating-point comparison using the SVE equivalent of:
15949 (set TARGET (CODE OP0 OP1))
15951 If CAN_INVERT_P is true, the caller can also handle inverted results;
15952 return true if the result is in fact inverted. */
15954 bool
15957 {
15963 {
15965 /* UNORDERED has no immediate form. */
15967 /* fall through */
15974 {
15975 /* There is native support for the comparison. */
15979 }
15982 /* This is a trapping operation (LT or GT). */
15988 {
15989 /* This would trap for signaling NaNs. */
15993 }
15994 /* fall through */
16000 {
16001 /* Work out which elements are ordered. */
16006 /* Test the opposite condition for the ordered elements,
16007 then invert the result. */
16010 else
16013 {
16017 }
16022 }
16026 /* ORDERED has no immediate form. */
16032 }
16034 /* There is native support for the inverse comparison. */
16037 {
16041 }
16044 }
16046 /* Expand an SVE vcond pattern with operands OPS. DATA_MODE is the mode
16047 of the data being selected and CMP_MODE is the mode of the values being
16048 compared. */
16050 void
16053 {
16054 machine_mode pred_mode
16059 {
16063 }
16064 else
16069 }
16071 /* Implement TARGET_MODES_TIEABLE_P. In principle we should always return
16072 true. However due to issues with register allocation it is preferable
16073 to avoid tieing integer scalar and FP scalar modes. Executing integer
16074 operations in general registers is better than treating them as scalar
16075 vector operations. This reduces latency and avoids redundant int<->FP
16076 moves. So tie modes if they are either the same class, or vector modes
16077 with other vector modes, vector structs or any scalar mode. */
16079 static bool
16081 {
16085 /* We specifically want to allow elements of "structure" modes to
16086 be tieable to the structure. This more general condition allows
16087 other rarer situations too. The reason we don't extend this to
16088 predicate modes is that there are no predicate structure modes
16089 nor any specific instructions for extracting part of a predicate
16090 register. */
16095 /* Also allow any scalar modes with vectors. */
16101 }
16103 /* Return a new RTX holding the result of moving POINTER forward by
16104 AMOUNT bytes. */
16106 static rtx
16108 {
16113 }
16115 /* Return a new RTX holding the result of moving POINTER forward by the
16116 size of the mode it points to. */
16118 static rtx
16120 {
16122 }
16124 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
16125 MODE bytes. */
16127 static void
16129 machine_mode mode)
16130 {
16133 /* "Cast" the pointers to the correct mode. */
16136 /* Emit the memcpy. */
16139 /* Move the pointers forward. */
16142 }
16144 /* Expand movmem, as if from a __builtin_memcpy. Return true if
16145 we succeed, otherwise return false. */
16147 bool
16149 {
16153 rtx base;
16157 /* When optimizing for size, give a better estimate of the length of a
16158 memcpy call, but use the default otherwise. Moves larger than 8 bytes
16159 will always require an even number of instructions to do now. And each
16160 operation requires both a load+store, so devide the max number by 2. */
16163 /* We can't do anything smart if the amount to copy is not constant. */
16169 /* Try to keep the number of instructions low. For all cases we will do at
16170 most two moves for the residual amount, since we'll always overlap the
16171 remainder. */
16181 /* Convert n to bits to make the rest of the code simpler. */
16185 {
16186 /* Find the largest mode in which to do the copy in without over reading
16187 or writing. */
16188 opt_scalar_int_mode mode_iter;
16200 /* Do certain trailing copies as overlapping if it's going to be
16201 cheaper. i.e. less instructions to do so. For instance doing a 15
16202 byte copy it's more efficient to do two overlapping 8 byte copies than
16203 8 + 6 + 1. */
16207 {
16211 }
16212 }
16215 }
16217 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
16218 SImode stores. Handle the case when the constant has identical
16219 bottom and top halves. This is beneficial when the two stores can be
16220 merged into an STP and we avoid synthesising potentially expensive
16221 immediates twice. Return true if such a split is possible. */
16223 bool
16225 {
16234 unsigned int orig_cost
16236 unsigned int lo_cost
16239 /* We want to transform:
16240 MOV x1, 49370
16241 MOVK x1, 0x140, lsl 16
16242 MOVK x1, 0xc0da, lsl 32
16243 MOVK x1, 0x140, lsl 48
16244 STR x1, [x0]
16245 into:
16246 MOV w1, 49370
16247 MOVK w1, 0x140, lsl 16
16248 STP w1, w1, [x0]
16249 So we want to perform this only when we save two instructions
16250 or more. When optimizing for size, however, accept any code size
16251 savings we can. */
16266 /* Don't emit an explicit store pair as this may not be always profitable.
16267 Let the sched-fusion logic decide whether to merge them. */
16272 }
16274 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
16276 static unsigned HOST_WIDE_INT
16278 {
16280 }
16282 static rtx
16285 {
16289 insn_code icode;
16300 {
16328 }
16333 {
16336 }
16345 {
16348 }
16354 }
16356 static rtx
16359 {
16363 insn_code icode;
16375 {
16403 }
16408 {
16411 }
16419 {
16424 }
16435 {
16438 }
16444 }
16446 #undef TARGET_GEN_CCMP_FIRST
16447 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
16449 #undef TARGET_GEN_CCMP_NEXT
16450 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
16452 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
16453 instruction fusion of some sort. */
16455 static bool
16457 {
16459 }
16462 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
16463 should be kept together during scheduling. */
16465 static bool
16467 {
16468 rtx set_dest;
16471 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
16478 {
16479 /* We are trying to match:
16480 prev (mov) == (set (reg r0) (const_int imm16))
16481 curr (movk) == (set (zero_extract (reg r0)
16482 (const_int 16)
16483 (const_int 16))
16484 (const_int imm16_1)) */
16496 {
16498 }
16499 }
16502 {
16504 /* We're trying to match:
16505 prev (adrp) == (set (reg r1)
16506 (high (symbol_ref ("SYM"))))
16507 curr (add) == (set (reg r0)
16508 (lo_sum (reg r1)
16509 (symbol_ref ("SYM"))))
16510 Note that r0 need not necessarily be the same as r1, especially
16511 during pre-regalloc scheduling. */
16515 {
16523 }
16524 }
16527 {
16529 /* We're trying to match:
16530 prev (movk) == (set (zero_extract (reg r0)
16531 (const_int 16)
16532 (const_int 32))
16533 (const_int imm16_1))
16534 curr (movk) == (set (zero_extract (reg r0)
16535 (const_int 16)
16536 (const_int 48))
16537 (const_int imm16_2)) */
16553 }
16555 {
16556 /* We're trying to match:
16557 prev (adrp) == (set (reg r0)
16558 (high (symbol_ref ("SYM"))))
16559 curr (ldr) == (set (reg r1)
16560 (mem (lo_sum (reg r0)
16561 (symbol_ref ("SYM")))))
16562 or
16563 curr (ldr) == (set (reg r1)
16564 (zero_extend (mem
16565 (lo_sum (reg r0)
16566 (symbol_ref ("SYM")))))) */
16569 {
16582 }
16583 }
16591 {
16595 rtx cc_reg_1;
16600 && prev
16602 {
16603 /* FIXME: this misses some which is considered simple arthematic
16604 instructions for ThunderX. Simple shifts are missed here. */
16610 }
16611 }
16614 && curr_set
16617 {
16618 /* We're trying to match:
16619 prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
16620 curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0)
16621 (const_int 0))
16622 (label_ref ("SYM"))
16623 (pc)) */
16630 {
16631 /* Fuse ALU operations followed by conditional branch instruction. */
16633 {
16654 }
16655 }
16656 }
16659 }
16661 /* Return true iff the instruction fusion described by OP is enabled. */
16663 bool
16665 {
16667 }
16669 /* If MEM is in the form of [base+offset], extract the two parts
16670 of address and set to BASE and OFFSET, otherwise return false
16671 after clearing BASE and OFFSET. */
16673 bool
16675 {
16676 rtx addr;
16683 {
16687 }
16691 {
16695 }
16701 }
16703 /* Types for scheduling fusion. */
16704 enum sched_fusion_type
16705 {
16707 SCHED_FUSION_LD_SIGN_EXTEND,
16708 SCHED_FUSION_LD_ZERO_EXTEND,
16709 SCHED_FUSION_LD,
16710 SCHED_FUSION_ST,
16711 SCHED_FUSION_NUM
16712 };
16714 /* If INSN is a load or store of address in the form of [base+offset],
16715 extract the two parts and set to BASE and OFFSET. Return scheduling
16716 fusion type this INSN is. */
16718 static enum sched_fusion_type
16720 {
16738 {
16743 }
16745 {
16750 }
16755 {
16758 }
16759 else
16766 }
16768 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
16770 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
16771 and PRI are only calculated for these instructions. For other instruction,
16772 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
16773 type instruction fusion can be added by returning different priorities.
16775 It's important that irrelevant instructions get the largest FUSION_PRI. */
16777 static void
16780 {
16790 {
16794 }
16796 /* Set FUSION_PRI according to fusion type and base register. */
16799 /* Calculate PRI. */
16802 /* INSN with smaller offset goes first. */
16806 else
16811 }
16813 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
16814 Adjust priority of sha1h instructions so they are scheduled before
16815 other SHA1 instructions. */
16817 static int
16819 {
16823 {
16828 }
16831 }
16833 /* Given OPERANDS of consecutive load/store, check if we can merge
16834 them into ldp/stp. LOAD is true if they are load instructions.
16835 MODE is the mode of memory operands. */
16837 bool
16839 machine_mode mode)
16840 {
16846 {
16854 }
16855 else
16856 {
16861 }
16863 /* The mems cannot be volatile. */
16867 /* If we have SImode and slow unaligned ldp,
16868 check the alignment to be at least 8 byte. */
16872 && !optimize_size
16876 /* Check if the addresses are in the form of [base+offset]. */
16884 /* Check if the bases are same. */
16888 /* The operands must be of the same size. */
16894 /* We should only be trying this for fixed-sized modes. There is no
16895 SVE LDP/STP instruction. */
16897 /* Check if the offsets are consecutive. */
16901 /* Check if the addresses are clobbered by load. */
16903 {
16907 /* In increasing order, the last load can clobber the address. */
16910 }
16912 /* One of the memory accesses must be a mempair operand.
16913 If it is not the first one, they need to be swapped by the
16914 peephole. */
16921 else
16926 else
16929 /* Check if the registers are of same class. */
16934 }
16936 /* Given OPERANDS of consecutive load/store that can be merged,
16937 swap them if they are not in ascending order. */
16938 void
16940 {
16945 {
16948 }
16949 else
16950 {
16953 }
16962 {
16963 /* Irrespective of whether this is a load or a store,
16964 we do the same swap. */
16967 }
16968 }
16970 /* Taking X and Y to be HOST_WIDE_INT pointers, return the result of a
16971 comparison between the two. */
16972 int
16974 {
16977 }
16979 /* Taking X and Y to be pairs of RTX, one pointing to a MEM rtx and the
16980 other pointing to a REG rtx containing an offset, compare the offsets
16981 of the two pairs.
16983 Return:
16985 1 iff offset (X) > offset (Y)
16986 0 iff offset (X) == offset (Y)
16987 -1 iff offset (X) < offset (Y) */
16988 int
16990 {
16997 else
17002 else
17005 /* Extract the offsets. */
17012 }
17014 /* Given OPERANDS of consecutive load/store, check if we can merge
17015 them into ldp/stp by adjusting the offset. LOAD is true if they
17016 are load instructions. MODE is the mode of memory operands.
17018 Given below consecutive stores:
17020 str w1, [xb, 0x100]
17021 str w1, [xb, 0x104]
17022 str w1, [xb, 0x108]
17023 str w1, [xb, 0x10c]
17025 Though the offsets are out of the range supported by stp, we can
17026 still pair them after adjusting the offset, like:
17028 add scratch, xb, 0x100
17029 stp w1, w1, [scratch]
17030 stp w1, w1, [scratch, 0x8]
17032 The peephole patterns detecting this opportunity should guarantee
17033 the scratch register is avaliable. */
17035 bool
17037 scalar_mode mode)
17038 {
17045 {
17057 /* Do not attempt to merge the loads if the loads clobber each other. */
17062 }
17063 else
17064 {
17073 }
17074 /* Skip if memory operand is by itslef valid for ldp/stp. */
17078 /* The mems cannot be volatile. */
17083 /* Check if the addresses are in the form of [base+offset]. */
17097 /* Check if the bases are same. */
17109 /* Check if the offsets can be put in the right order to do a ldp/stp. */
17116 /* Check that offsets are within range of each other. The ldp/stp
17117 instructions have 7 bit immediate offsets, so use 0x80. */
17121 /* The offsets must be aligned with respect to each other. */
17125 /* Check if the addresses are clobbered by load. */
17132 /* If we have SImode and slow unaligned ldp,
17133 check the alignment to be at least 8 byte. */
17137 && !optimize_size
17143 else
17148 else
17153 else
17158 else
17161 /* Check if the registers are of same class. */
17166 }
17168 /* Given OPERANDS of consecutive load/store, this function pairs them
17169 into LDP/STP after adjusting the offset. It depends on the fact
17170 that the operands can be sorted so the offsets are correct for STP.
17171 MODE is the mode of memory operands. CODE is the rtl operator
17172 which should be applied to all memory operands, it's SIGN_EXTEND,
17173 ZERO_EXTEND or UNKNOWN. */
17175 bool
17178 {
17185 /* We make changes on a copy as we may still bail out. */
17189 /* Sort the operands. */
17193 {
17198 }
17199 else
17200 {
17206 }
17213 /* Adjust offset so it can fit in LDP/STP instruction. */
17221 /* The base offset is optimally half way between the two STP/LDP offsets. */
17224 else
17225 /* However, due to issues with negative LDP/STP offset generation for
17226 larger modes, for DF, DI and vector modes. we must not use negative
17227 addresses smaller than 9 signed unadjusted bits can store. This
17228 provides the most range in this case. */
17231 /* Adjust the base so that it is aligned with the addresses but still
17232 optimal. */
17234 /* Fix the offset, bearing in mind we want to make it bigger not
17235 smaller. */
17238 /* The negative range of LDP/STP is one larger than the positive range. */
17241 /* Check if base offset is too big or too small. We can attempt to resolve
17242 this issue by setting it to the maximum value and seeing if the offsets
17243 still fit. */
17245 {
17247 /* We must still make sure that the base offset is aligned with respect
17248 to the address. But it may may not be made any bigger. */
17250 }
17252 /* Likewise for the case where the base is too small. */
17254 {
17257 }
17259 /* Offset of the first STP/LDP. */
17262 /* Offset of the second STP/LDP. */
17265 /* The offsets must be within the range of the LDP/STP instructions. */
17284 {
17289 }
17291 {
17296 }
17299 {
17308 }
17309 else
17310 {
17319 }
17321 /* Emit adjusting instruction. */
17323 /* Emit ldp/stp instructions. */
17331 }
17333 /* Implement TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE. Assume for now that
17334 it isn't worth branching around empty masked ops (including masked
17335 stores). */
17337 static bool
17339 {
17341 }
17343 /* Return 1 if pseudo register should be created and used to hold
17344 GOT address for PIC code. */
17346 bool
17348 {
17350 }
17352 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
17354 static int
17356 {
17358 {
17365 }
17368 }
17371 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
17372 return the log2 of that value. Otherwise return -1. */
17374 int
17376 {
17391 }
17393 /* If X is a vector of equal CONST_DOUBLE values and that value is
17394 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
17396 int
17398 {
17416 }
17418 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
17419 to float.
17421 __fp16 always promotes through this hook.
17422 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
17423 through the generic excess precision logic rather than here. */
17425 static tree
17427 {
17433 }
17435 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
17437 static bool
17439 optimization_type opt_type)
17440 {
17442 {
17448 }
17449 }
17451 /* Implement the TARGET_DWARF_POLY_INDETERMINATE_VALUE hook. */
17453 static unsigned int
17456 {
17457 /* Polynomial invariant 1 == (VG / 2) - 1. */
17462 }
17464 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
17465 if MODE is HFmode, and punt to the generic implementation otherwise. */
17467 static bool
17469 {
17473 }
17475 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
17476 if MODE is HFmode, and punt to the generic implementation otherwise. */
17478 static bool
17480 {
17484 }
17486 /* Set the value of FLT_EVAL_METHOD.
17487 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
17489 0: evaluate all operations and constants, whose semantic type has at
17490 most the range and precision of type float, to the range and
17491 precision of float; evaluate all other operations and constants to
17492 the range and precision of the semantic type;
17494 N, where _FloatN is a supported interchange floating type
17495 evaluate all operations and constants, whose semantic type has at
17496 most the range and precision of _FloatN type, to the range and
17497 precision of the _FloatN type; evaluate all other operations and
17498 constants to the range and precision of the semantic type;
17500 If we have the ARMv8.2-A extensions then we support _Float16 in native
17501 precision, so we should set this to 16. Otherwise, we support the type,
17502 but want to evaluate expressions in float precision, so set this to
17503 0. */
17505 static enum flt_eval_method
17507 {
17509 {
17512 /* We can calculate either in 16-bit range and precision or
17513 32-bit range and precision. Make that decision based on whether
17514 we have native support for the ARMv8.2-A 16-bit floating-point
17515 instructions or not. */
17517 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
17523 }
17525 }
17527 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
17528 scheduled for speculative execution. Reject the long-running division
17529 and square-root instructions. */
17531 static bool
17533 {
17535 {
17553 }
17554 }
17556 /* Implement TARGET_COMPUTE_PRESSURE_CLASSES. */
17558 static int
17560 {
17564 /* PR_REGS isn't a useful pressure class because many predicate pseudo
17565 registers need to go in PR_LO_REGS at some point during their
17566 lifetime. Splitting it into two halves has the effect of making
17567 all predicates count against PR_LO_REGS, so that we try whenever
17568 possible to restrict the number of live predicates to 8. This
17569 greatly reduces the amount of spilling in certain loops. */
17573 }
17575 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
17577 static bool
17580 {
17582 {
17586 /* Don't allow changes between SVE data modes and non-SVE modes.
17587 See the comment at the head of aarch64-sve.md for details. */
17591 /* Don't allow changes in element size: lane 0 of the new vector
17592 would not then be lane 0 of the old vector. See the comment
17593 above aarch64_maybe_expand_sve_subreg_move for a more detailed
17594 description.
17596 In the worst case, this forces a register to be spilled in
17597 one mode and reloaded in the other, which handles the
17598 endianness correctly. */
17601 }
17603 }
17605 /* Implement TARGET_EARLY_REMAT_MODES. */
17607 static void
17609 {
17610 /* SVE values are not normally live across a call, so it should be
17611 worth doing early rematerialization even in VL-specific mode. */
17613 {
17618 }
17619 }
17621 /* Target-specific selftests. */
17623 #if CHECKING_P
17627 /* Selftest for the RTL loader.
17628 Verify that the RTL loader copes with a dump from
17629 print_rtx_function. This is essentially just a test that class
17630 function_reader can handle a real dump, but it also verifies
17631 that lookup_reg_by_dump_name correctly handles hard regs.
17632 The presence of hard reg names in the dump means that the test is
17633 target-specific, hence it is in this file. */
17635 static void
17637 {
17649 /* Verify crtl->return_rtx. */
17653 }
17655 /* Run all target-specific selftests. */
17657 static void
17659 {
17661 }
17667 #undef TARGET_ADDRESS_COST
17668 #define TARGET_ADDRESS_COST aarch64_address_cost
17670 /* This hook will determines whether unnamed bitfields affect the alignment
17671 of the containing structure. The hook returns true if the structure
17672 should inherit the alignment requirements of an unnamed bitfield's
17673 type. */
17674 #undef TARGET_ALIGN_ANON_BITFIELD
17675 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
17677 #undef TARGET_ASM_ALIGNED_DI_OP
17680 #undef TARGET_ASM_ALIGNED_HI_OP
17683 #undef TARGET_ASM_ALIGNED_SI_OP
17686 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
17687 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
17688 hook_bool_const_tree_hwi_hwi_const_tree_true
17690 #undef TARGET_ASM_FILE_START
17691 #define TARGET_ASM_FILE_START aarch64_start_file
17693 #undef TARGET_ASM_OUTPUT_MI_THUNK
17694 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
17696 #undef TARGET_ASM_SELECT_RTX_SECTION
17697 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
17699 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
17700 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
17702 #undef TARGET_BUILD_BUILTIN_VA_LIST
17703 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
17705 #undef TARGET_CALLEE_COPIES
17706 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
17708 #undef TARGET_CAN_ELIMINATE
17709 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
17711 #undef TARGET_CAN_INLINE_P
17712 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
17714 #undef TARGET_CANNOT_FORCE_CONST_MEM
17715 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
17717 #undef TARGET_CASE_VALUES_THRESHOLD
17718 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
17720 #undef TARGET_CONDITIONAL_REGISTER_USAGE
17721 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
17723 /* Only the least significant bit is used for initialization guard
17724 variables. */
17725 #undef TARGET_CXX_GUARD_MASK_BIT
17726 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
17728 #undef TARGET_C_MODE_FOR_SUFFIX
17729 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
17731 #ifdef TARGET_BIG_ENDIAN_DEFAULT
17732 #undef TARGET_DEFAULT_TARGET_FLAGS
17733 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
17734 #endif
17736 #undef TARGET_CLASS_MAX_NREGS
17737 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
17739 #undef TARGET_BUILTIN_DECL
17740 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
17742 #undef TARGET_BUILTIN_RECIPROCAL
17743 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
17745 #undef TARGET_C_EXCESS_PRECISION
17746 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
17748 #undef TARGET_EXPAND_BUILTIN
17749 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
17751 #undef TARGET_EXPAND_BUILTIN_VA_START
17752 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
17754 #undef TARGET_FOLD_BUILTIN
17755 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
17757 #undef TARGET_FUNCTION_ARG
17758 #define TARGET_FUNCTION_ARG aarch64_function_arg
17760 #undef TARGET_FUNCTION_ARG_ADVANCE
17761 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
17763 #undef TARGET_FUNCTION_ARG_BOUNDARY
17764 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
17766 #undef TARGET_FUNCTION_ARG_PADDING
17767 #define TARGET_FUNCTION_ARG_PADDING aarch64_function_arg_padding
17769 #undef TARGET_GET_RAW_RESULT_MODE
17770 #define TARGET_GET_RAW_RESULT_MODE aarch64_get_reg_raw_mode
17771 #undef TARGET_GET_RAW_ARG_MODE
17772 #define TARGET_GET_RAW_ARG_MODE aarch64_get_reg_raw_mode
17774 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
17775 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
17777 #undef TARGET_FUNCTION_VALUE
17778 #define TARGET_FUNCTION_VALUE aarch64_function_value
17780 #undef TARGET_FUNCTION_VALUE_REGNO_P
17781 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
17783 #undef TARGET_GIMPLE_FOLD_BUILTIN
17784 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
17786 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
17787 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
17789 #undef TARGET_INIT_BUILTINS
17790 #define TARGET_INIT_BUILTINS aarch64_init_builtins
17792 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
17793 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
17794 aarch64_ira_change_pseudo_allocno_class
17796 #undef TARGET_LEGITIMATE_ADDRESS_P
17797 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
17799 #undef TARGET_LEGITIMATE_CONSTANT_P
17800 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
17802 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
17803 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
17804 aarch64_legitimize_address_displacement
17806 #undef TARGET_LIBGCC_CMP_RETURN_MODE
17807 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
17809 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
17810 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
17811 aarch64_libgcc_floating_mode_supported_p
17813 #undef TARGET_MANGLE_TYPE
17814 #define TARGET_MANGLE_TYPE aarch64_mangle_type
17816 #undef TARGET_MEMORY_MOVE_COST
17817 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
17819 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
17820 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
17822 #undef TARGET_MUST_PASS_IN_STACK
17823 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
17825 /* This target hook should return true if accesses to volatile bitfields
17826 should use the narrowest mode possible. It should return false if these
17827 accesses should use the bitfield container type. */
17828 #undef TARGET_NARROW_VOLATILE_BITFIELD
17829 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
17831 #undef TARGET_OPTION_OVERRIDE
17832 #define TARGET_OPTION_OVERRIDE aarch64_override_options
17834 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
17835 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
17836 aarch64_override_options_after_change
17838 #undef TARGET_OPTION_SAVE
17839 #define TARGET_OPTION_SAVE aarch64_option_save
17841 #undef TARGET_OPTION_RESTORE
17842 #define TARGET_OPTION_RESTORE aarch64_option_restore
17844 #undef TARGET_OPTION_PRINT
17845 #define TARGET_OPTION_PRINT aarch64_option_print
17847 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
17848 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
17850 #undef TARGET_SET_CURRENT_FUNCTION
17851 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
17853 #undef TARGET_PASS_BY_REFERENCE
17854 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
17856 #undef TARGET_PREFERRED_RELOAD_CLASS
17857 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
17859 #undef TARGET_SCHED_REASSOCIATION_WIDTH
17860 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
17862 #undef TARGET_PROMOTED_TYPE
17863 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
17865 #undef TARGET_SECONDARY_RELOAD
17866 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
17868 #undef TARGET_SHIFT_TRUNCATION_MASK
17869 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
17871 #undef TARGET_SETUP_INCOMING_VARARGS
17872 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
17874 #undef TARGET_STRUCT_VALUE_RTX
17875 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
17877 #undef TARGET_REGISTER_MOVE_COST
17878 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
17880 #undef TARGET_RETURN_IN_MEMORY
17881 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
17883 #undef TARGET_RETURN_IN_MSB
17884 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
17886 #undef TARGET_RTX_COSTS
17887 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
17889 #undef TARGET_SCALAR_MODE_SUPPORTED_P
17890 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
17892 #undef TARGET_SCHED_ISSUE_RATE
17893 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
17895 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
17896 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
17897 aarch64_sched_first_cycle_multipass_dfa_lookahead
17899 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
17900 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
17901 aarch64_first_cycle_multipass_dfa_lookahead_guard
17903 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
17904 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
17905 aarch64_get_separate_components
17907 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
17908 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
17909 aarch64_components_for_bb
17911 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
17912 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
17913 aarch64_disqualify_components
17915 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
17916 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
17917 aarch64_emit_prologue_components
17919 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
17920 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
17921 aarch64_emit_epilogue_components
17923 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
17924 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
17925 aarch64_set_handled_components
17927 #undef TARGET_TRAMPOLINE_INIT
17928 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
17930 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
17931 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
17933 #undef TARGET_VECTOR_MODE_SUPPORTED_P
17934 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
17936 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
17937 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
17938 aarch64_builtin_support_vector_misalignment
17940 #undef TARGET_ARRAY_MODE
17941 #define TARGET_ARRAY_MODE aarch64_array_mode
17943 #undef TARGET_ARRAY_MODE_SUPPORTED_P
17944 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
17946 #undef TARGET_VECTORIZE_ADD_STMT_COST
17947 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
17949 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
17950 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
17951 aarch64_builtin_vectorization_cost
17953 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
17954 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
17956 #undef TARGET_VECTORIZE_BUILTINS
17957 #define TARGET_VECTORIZE_BUILTINS
17959 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
17960 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
17961 aarch64_builtin_vectorized_function
17963 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
17964 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
17965 aarch64_autovectorize_vector_sizes
17967 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
17968 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
17969 aarch64_atomic_assign_expand_fenv
17971 /* Section anchor support. */
17973 #undef TARGET_MIN_ANCHOR_OFFSET
17974 #define TARGET_MIN_ANCHOR_OFFSET -256
17976 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
17977 byte offset; we can do much more for larger data types, but have no way
17978 to determine the size of the access. We assume accesses are aligned. */
17979 #undef TARGET_MAX_ANCHOR_OFFSET
17980 #define TARGET_MAX_ANCHOR_OFFSET 4095
17982 #undef TARGET_VECTOR_ALIGNMENT
17983 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
17985 #undef TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT
17986 #define TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT \
17987 aarch64_vectorize_preferred_vector_alignment
17988 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
17989 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
17990 aarch64_simd_vector_alignment_reachable
17992 /* vec_perm support. */
17994 #undef TARGET_VECTORIZE_VEC_PERM_CONST
17995 #define TARGET_VECTORIZE_VEC_PERM_CONST \
17996 aarch64_vectorize_vec_perm_const
17998 #undef TARGET_VECTORIZE_GET_MASK_MODE
17999 #define TARGET_VECTORIZE_GET_MASK_MODE aarch64_get_mask_mode
18000 #undef TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE
18001 #define TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE \
18002 aarch64_empty_mask_is_expensive
18003 #undef TARGET_PREFERRED_ELSE_VALUE
18004 #define TARGET_PREFERRED_ELSE_VALUE \
18005 aarch64_preferred_else_value
18007 #undef TARGET_INIT_LIBFUNCS
18008 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
18010 #undef TARGET_FIXED_CONDITION_CODE_REGS
18011 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
18013 #undef TARGET_FLAGS_REGNUM
18014 #define TARGET_FLAGS_REGNUM CC_REGNUM
18016 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
18017 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
18019 #undef TARGET_ASAN_SHADOW_OFFSET
18020 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
18022 #undef TARGET_LEGITIMIZE_ADDRESS
18023 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
18025 #undef TARGET_SCHED_CAN_SPECULATE_INSN
18026 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
18028 #undef TARGET_CAN_USE_DOLOOP_P
18029 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
18031 #undef TARGET_SCHED_ADJUST_PRIORITY
18032 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
18034 #undef TARGET_SCHED_MACRO_FUSION_P
18035 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
18037 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
18038 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
18040 #undef TARGET_SCHED_FUSION_PRIORITY
18041 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
18043 #undef TARGET_UNSPEC_MAY_TRAP_P
18044 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
18046 #undef TARGET_USE_PSEUDO_PIC_REG
18047 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
18049 #undef TARGET_PRINT_OPERAND
18050 #define TARGET_PRINT_OPERAND aarch64_print_operand
18052 #undef TARGET_PRINT_OPERAND_ADDRESS
18053 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
18055 #undef TARGET_OPTAB_SUPPORTED_P
18056 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
18058 #undef TARGET_OMIT_STRUCT_RETURN_REG
18059 #define TARGET_OMIT_STRUCT_RETURN_REG true
18061 #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
18062 #define TARGET_DWARF_POLY_INDETERMINATE_VALUE \
18063 aarch64_dwarf_poly_indeterminate_value
18065 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
18066 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
18067 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
18069 #undef TARGET_HARD_REGNO_NREGS
18070 #define TARGET_HARD_REGNO_NREGS aarch64_hard_regno_nregs
18071 #undef TARGET_HARD_REGNO_MODE_OK
18072 #define TARGET_HARD_REGNO_MODE_OK aarch64_hard_regno_mode_ok
18074 #undef TARGET_MODES_TIEABLE_P
18075 #define TARGET_MODES_TIEABLE_P aarch64_modes_tieable_p
18077 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
18078 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
18079 aarch64_hard_regno_call_part_clobbered
18081 #undef TARGET_CONSTANT_ALIGNMENT
18082 #define TARGET_CONSTANT_ALIGNMENT aarch64_constant_alignment
18084 #undef TARGET_COMPUTE_PRESSURE_CLASSES
18085 #define TARGET_COMPUTE_PRESSURE_CLASSES aarch64_compute_pressure_classes
18087 #undef TARGET_CAN_CHANGE_MODE_CLASS
18088 #define TARGET_CAN_CHANGE_MODE_CLASS aarch64_can_change_mode_class
18090 #undef TARGET_SELECT_EARLY_REMAT_MODES
18091 #define TARGET_SELECT_EARLY_REMAT_MODES aarch64_select_early_remat_modes
18093 #if CHECKING_P
18094 #undef TARGET_RUN_TARGET_SELFTESTS
18095 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests