1 /* IRA hard register and memory cost calculation for allocnos or pseudos.
2 Copyright (C) 2006-2015 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
30 #include "insn-config.h"
41 #include "addresses.h"
44 #include "diagnostic-core.h"
49 #include "alloc-pool.h"
52 /* The flags is set up every time when we calculate pseudo register
53 classes through function ira_set_pseudo_classes. */
54 static bool pseudo_classes_defined_p
= false;
56 /* TRUE if we work with allocnos. Otherwise we work with pseudos. */
57 static bool allocno_p
;
59 /* Number of elements in array `costs'. */
60 static int cost_elements_num
;
62 /* The `costs' struct records the cost of using hard registers of each
63 class considered for the calculation and of using memory for each
68 /* Costs for register classes start here. We process only some
73 #define max_struct_costs_size \
74 (this_target_ira_int->x_max_struct_costs_size)
76 (this_target_ira_int->x_init_cost)
78 (this_target_ira_int->x_temp_costs)
80 (this_target_ira_int->x_op_costs)
81 #define this_op_costs \
82 (this_target_ira_int->x_this_op_costs)
84 /* Costs of each class for each allocno or pseudo. */
85 static struct costs
*costs
;
87 /* Accumulated costs of each class for each allocno. */
88 static struct costs
*total_allocno_costs
;
90 /* It is the current size of struct costs. */
91 static int struct_costs_size
;
93 /* Return pointer to structure containing costs of allocno or pseudo
94 with given NUM in array ARR. */
95 #define COSTS(arr, num) \
96 ((struct costs *) ((char *) (arr) + (num) * struct_costs_size))
98 /* Return index in COSTS when processing reg with REGNO. */
99 #define COST_INDEX(regno) (allocno_p \
100 ? ALLOCNO_NUM (ira_curr_regno_allocno_map[regno]) \
103 /* Record register class preferences of each allocno or pseudo. Null
104 value means no preferences. It happens on the 1st iteration of the
106 static enum reg_class
*pref
;
108 /* Allocated buffers for pref. */
109 static enum reg_class
*pref_buffer
;
111 /* Record allocno class of each allocno with the same regno. */
112 static enum reg_class
*regno_aclass
;
114 /* Record cost gains for not allocating a register with an invariant
116 static int *regno_equiv_gains
;
118 /* Execution frequency of the current insn. */
119 static int frequency
;
123 /* Info about reg classes whose costs are calculated for a pseudo. */
126 /* Number of the cost classes in the subsequent array. */
128 /* Container of the cost classes. */
129 enum reg_class classes
[N_REG_CLASSES
];
130 /* Map reg class -> index of the reg class in the previous array.
131 -1 if it is not a cost class. */
132 int index
[N_REG_CLASSES
];
133 /* Map hard regno index of first class in array CLASSES containing
134 the hard regno, -1 otherwise. */
135 int hard_regno_index
[FIRST_PSEUDO_REGISTER
];
138 /* Types of pointers to the structure above. */
139 typedef struct cost_classes
*cost_classes_t
;
140 typedef const struct cost_classes
*const_cost_classes_t
;
142 /* Info about cost classes for each pseudo. */
143 static cost_classes_t
*regno_cost_classes
;
145 /* Helper for cost_classes hashing. */
147 struct cost_classes_hasher
: pointer_hash
<cost_classes
>
149 static inline hashval_t
hash (const cost_classes
*);
150 static inline bool equal (const cost_classes
*, const cost_classes
*);
151 static inline void remove (cost_classes
*);
154 /* Returns hash value for cost classes info HV. */
156 cost_classes_hasher::hash (const cost_classes
*hv
)
158 return iterative_hash (&hv
->classes
, sizeof (enum reg_class
) * hv
->num
, 0);
161 /* Compares cost classes info HV1 and HV2. */
163 cost_classes_hasher::equal (const cost_classes
*hv1
, const cost_classes
*hv2
)
165 return (hv1
->num
== hv2
->num
166 && memcmp (hv1
->classes
, hv2
->classes
,
167 sizeof (enum reg_class
) * hv1
->num
) == 0);
170 /* Delete cost classes info V from the hash table. */
172 cost_classes_hasher::remove (cost_classes
*v
)
177 /* Hash table of unique cost classes. */
178 static hash_table
<cost_classes_hasher
> *cost_classes_htab
;
180 /* Map allocno class -> cost classes for pseudo of given allocno
182 static cost_classes_t cost_classes_aclass_cache
[N_REG_CLASSES
];
184 /* Map mode -> cost classes for pseudo of give mode. */
185 static cost_classes_t cost_classes_mode_cache
[MAX_MACHINE_MODE
];
187 /* Cost classes that include all classes in ira_important_classes. */
188 static cost_classes all_cost_classes
;
190 /* Use the array of classes in CLASSES_PTR to fill out the rest of
193 complete_cost_classes (cost_classes_t classes_ptr
)
195 for (int i
= 0; i
< N_REG_CLASSES
; i
++)
196 classes_ptr
->index
[i
] = -1;
197 for (int i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
198 classes_ptr
->hard_regno_index
[i
] = -1;
199 for (int i
= 0; i
< classes_ptr
->num
; i
++)
201 enum reg_class cl
= classes_ptr
->classes
[i
];
202 classes_ptr
->index
[cl
] = i
;
203 for (int j
= ira_class_hard_regs_num
[cl
] - 1; j
>= 0; j
--)
205 unsigned int hard_regno
= ira_class_hard_regs
[cl
][j
];
206 if (classes_ptr
->hard_regno_index
[hard_regno
] < 0)
207 classes_ptr
->hard_regno_index
[hard_regno
] = i
;
212 /* Initialize info about the cost classes for each pseudo. */
214 initiate_regno_cost_classes (void)
216 int size
= sizeof (cost_classes_t
) * max_reg_num ();
218 regno_cost_classes
= (cost_classes_t
*) ira_allocate (size
);
219 memset (regno_cost_classes
, 0, size
);
220 memset (cost_classes_aclass_cache
, 0,
221 sizeof (cost_classes_t
) * N_REG_CLASSES
);
222 memset (cost_classes_mode_cache
, 0,
223 sizeof (cost_classes_t
) * MAX_MACHINE_MODE
);
224 cost_classes_htab
= new hash_table
<cost_classes_hasher
> (200);
225 all_cost_classes
.num
= ira_important_classes_num
;
226 for (int i
= 0; i
< ira_important_classes_num
; i
++)
227 all_cost_classes
.classes
[i
] = ira_important_classes
[i
];
228 complete_cost_classes (&all_cost_classes
);
231 /* Create new cost classes from cost classes FROM and set up members
232 index and hard_regno_index. Return the new classes. The function
233 implements some common code of two functions
234 setup_regno_cost_classes_by_aclass and
235 setup_regno_cost_classes_by_mode. */
236 static cost_classes_t
237 setup_cost_classes (cost_classes_t from
)
239 cost_classes_t classes_ptr
;
241 classes_ptr
= (cost_classes_t
) ira_allocate (sizeof (struct cost_classes
));
242 classes_ptr
->num
= from
->num
;
243 for (int i
= 0; i
< from
->num
; i
++)
244 classes_ptr
->classes
[i
] = from
->classes
[i
];
245 complete_cost_classes (classes_ptr
);
249 /* Return a version of FULL that only considers registers in REGS that are
250 valid for mode MODE. Both FULL and the returned class are globally
252 static cost_classes_t
253 restrict_cost_classes (cost_classes_t full
, machine_mode mode
,
254 const HARD_REG_SET
®s
)
256 static struct cost_classes narrow
;
257 int map
[N_REG_CLASSES
];
259 for (int i
= 0; i
< full
->num
; i
++)
261 /* Assume that we'll drop the class. */
264 /* Ignore classes that are too small for the mode. */
265 enum reg_class cl
= full
->classes
[i
];
266 if (!contains_reg_of_mode
[cl
][mode
])
269 /* Calculate the set of registers in CL that belong to REGS and
270 are valid for MODE. */
271 HARD_REG_SET valid_for_cl
;
272 COPY_HARD_REG_SET (valid_for_cl
, reg_class_contents
[cl
]);
273 AND_HARD_REG_SET (valid_for_cl
, regs
);
274 AND_COMPL_HARD_REG_SET (valid_for_cl
,
275 ira_prohibited_class_mode_regs
[cl
][mode
]);
276 AND_COMPL_HARD_REG_SET (valid_for_cl
, ira_no_alloc_regs
);
277 if (hard_reg_set_empty_p (valid_for_cl
))
280 /* Don't use this class if the set of valid registers is a subset
281 of an existing class. For example, suppose we have two classes
282 GR_REGS and FR_REGS and a union class GR_AND_FR_REGS. Suppose
283 that the mode changes allowed by FR_REGS are not as general as
284 the mode changes allowed by GR_REGS.
286 In this situation, the mode changes for GR_AND_FR_REGS could
287 either be seen as the union or the intersection of the mode
288 changes allowed by the two subclasses. The justification for
289 the union-based definition would be that, if you want a mode
290 change that's only allowed by GR_REGS, you can pick a register
291 from the GR_REGS subclass. The justification for the
292 intersection-based definition would be that every register
293 from the class would allow the mode change.
295 However, if we have a register that needs to be in GR_REGS,
296 using GR_AND_FR_REGS with the intersection-based definition
297 would be too pessimistic, since it would bring in restrictions
298 that only apply to FR_REGS. Conversely, if we have a register
299 that needs to be in FR_REGS, using GR_AND_FR_REGS with the
300 union-based definition would lose the extra restrictions
301 placed on FR_REGS. GR_AND_FR_REGS is therefore only useful
302 for cases where GR_REGS and FP_REGS are both valid. */
304 for (pos
= 0; pos
< narrow
.num
; ++pos
)
306 enum reg_class cl2
= narrow
.classes
[pos
];
307 if (hard_reg_set_subset_p (valid_for_cl
, reg_class_contents
[cl2
]))
311 if (pos
== narrow
.num
)
313 /* If several classes are equivalent, prefer to use the one
314 that was chosen as the allocno class. */
315 enum reg_class cl2
= ira_allocno_class_translate
[cl
];
316 if (ira_class_hard_regs_num
[cl
] == ira_class_hard_regs_num
[cl2
])
318 narrow
.classes
[narrow
.num
++] = cl
;
321 if (narrow
.num
== full
->num
)
324 cost_classes
**slot
= cost_classes_htab
->find_slot (&narrow
, INSERT
);
327 cost_classes_t classes
= setup_cost_classes (&narrow
);
328 /* Map equivalent classes to the representative that we chose above. */
329 for (int i
= 0; i
< ira_important_classes_num
; i
++)
331 enum reg_class cl
= ira_important_classes
[i
];
332 int index
= full
->index
[cl
];
334 classes
->index
[cl
] = map
[index
];
341 /* Setup cost classes for pseudo REGNO whose allocno class is ACLASS.
342 This function is used when we know an initial approximation of
343 allocno class of the pseudo already, e.g. on the second iteration
344 of class cost calculation or after class cost calculation in
345 register-pressure sensitive insn scheduling or register-pressure
346 sensitive loop-invariant motion. */
348 setup_regno_cost_classes_by_aclass (int regno
, enum reg_class aclass
)
350 static struct cost_classes classes
;
351 cost_classes_t classes_ptr
;
355 HARD_REG_SET temp
, temp2
;
358 if ((classes_ptr
= cost_classes_aclass_cache
[aclass
]) == NULL
)
360 COPY_HARD_REG_SET (temp
, reg_class_contents
[aclass
]);
361 AND_COMPL_HARD_REG_SET (temp
, ira_no_alloc_regs
);
362 /* We exclude classes from consideration which are subsets of
363 ACLASS only if ACLASS is an uniform class. */
364 exclude_p
= ira_uniform_class_p
[aclass
];
366 for (i
= 0; i
< ira_important_classes_num
; i
++)
368 cl
= ira_important_classes
[i
];
371 /* Exclude non-uniform classes which are subsets of
373 COPY_HARD_REG_SET (temp2
, reg_class_contents
[cl
]);
374 AND_COMPL_HARD_REG_SET (temp2
, ira_no_alloc_regs
);
375 if (hard_reg_set_subset_p (temp2
, temp
) && cl
!= aclass
)
378 classes
.classes
[classes
.num
++] = cl
;
380 slot
= cost_classes_htab
->find_slot (&classes
, INSERT
);
383 classes_ptr
= setup_cost_classes (&classes
);
386 classes_ptr
= cost_classes_aclass_cache
[aclass
] = (cost_classes_t
) *slot
;
388 if (regno_reg_rtx
[regno
] != NULL_RTX
)
390 /* Restrict the classes to those that are valid for REGNO's mode
391 (which might for example exclude singleton classes if the mode
392 requires two registers). Also restrict the classes to those that
393 are valid for subregs of REGNO. */
394 const HARD_REG_SET
*valid_regs
= valid_mode_changes_for_regno (regno
);
396 valid_regs
= ®_class_contents
[ALL_REGS
];
397 classes_ptr
= restrict_cost_classes (classes_ptr
,
398 PSEUDO_REGNO_MODE (regno
),
401 regno_cost_classes
[regno
] = classes_ptr
;
404 /* Setup cost classes for pseudo REGNO with MODE. Usage of MODE can
405 decrease number of cost classes for the pseudo, if hard registers
406 of some important classes can not hold a value of MODE. So the
407 pseudo can not get hard register of some important classes and cost
408 calculation for such important classes is only wasting CPU
411 setup_regno_cost_classes_by_mode (int regno
, machine_mode mode
)
413 if (const HARD_REG_SET
*valid_regs
= valid_mode_changes_for_regno (regno
))
414 regno_cost_classes
[regno
] = restrict_cost_classes (&all_cost_classes
,
418 if (cost_classes_mode_cache
[mode
] == NULL
)
419 cost_classes_mode_cache
[mode
]
420 = restrict_cost_classes (&all_cost_classes
, mode
,
421 reg_class_contents
[ALL_REGS
]);
422 regno_cost_classes
[regno
] = cost_classes_mode_cache
[mode
];
426 /* Finalize info about the cost classes for each pseudo. */
428 finish_regno_cost_classes (void)
430 ira_free (regno_cost_classes
);
431 delete cost_classes_htab
;
432 cost_classes_htab
= NULL
;
437 /* Compute the cost of loading X into (if TO_P is TRUE) or from (if
438 TO_P is FALSE) a register of class RCLASS in mode MODE. X must not
439 be a pseudo register. */
441 copy_cost (rtx x
, machine_mode mode
, reg_class_t rclass
, bool to_p
,
442 secondary_reload_info
*prev_sri
)
444 secondary_reload_info sri
;
445 reg_class_t secondary_class
= NO_REGS
;
447 /* If X is a SCRATCH, there is actually nothing to move since we are
448 assuming optimal allocation. */
449 if (GET_CODE (x
) == SCRATCH
)
452 /* Get the class we will actually use for a reload. */
453 rclass
= targetm
.preferred_reload_class (x
, rclass
);
455 /* If we need a secondary reload for an intermediate, the cost is
456 that to load the input into the intermediate register, then to
458 sri
.prev_sri
= prev_sri
;
460 secondary_class
= targetm
.secondary_reload (to_p
, x
, rclass
, mode
, &sri
);
462 if (secondary_class
!= NO_REGS
)
464 ira_init_register_move_cost_if_necessary (mode
);
465 return (ira_register_move_cost
[mode
][(int) secondary_class
][(int) rclass
]
467 + copy_cost (x
, mode
, secondary_class
, to_p
, &sri
));
470 /* For memory, use the memory move cost, for (hard) registers, use
471 the cost to move between the register classes, and use 2 for
472 everything else (constants). */
473 if (MEM_P (x
) || rclass
== NO_REGS
)
474 return sri
.extra_cost
475 + ira_memory_move_cost
[mode
][(int) rclass
][to_p
!= 0];
478 reg_class_t x_class
= REGNO_REG_CLASS (REGNO (x
));
480 ira_init_register_move_cost_if_necessary (mode
);
481 return (sri
.extra_cost
482 + ira_register_move_cost
[mode
][(int) x_class
][(int) rclass
]);
485 /* If this is a constant, we may eventually want to call rtx_cost
487 return sri
.extra_cost
+ COSTS_N_INSNS (1);
492 /* Record the cost of using memory or hard registers of various
493 classes for the operands in INSN.
495 N_ALTS is the number of alternatives.
496 N_OPS is the number of operands.
497 OPS is an array of the operands.
498 MODES are the modes of the operands, in case any are VOIDmode.
499 CONSTRAINTS are the constraints to use for the operands. This array
500 is modified by this procedure.
502 This procedure works alternative by alternative. For each
503 alternative we assume that we will be able to allocate all allocnos
504 to their ideal register class and calculate the cost of using that
505 alternative. Then we compute, for each operand that is a
506 pseudo-register, the cost of having the allocno allocated to each
507 register class and using it in that alternative. To this cost is
508 added the cost of the alternative.
510 The cost of each class for this insn is its lowest cost among all
513 record_reg_classes (int n_alts
, int n_ops
, rtx
*ops
,
514 machine_mode
*modes
, const char **constraints
,
515 rtx_insn
*insn
, enum reg_class
*pref
)
519 int insn_allows_mem
[MAX_RECOG_OPERANDS
];
520 move_table
*move_in_cost
, *move_out_cost
;
521 short (*mem_cost
)[2];
523 for (i
= 0; i
< n_ops
; i
++)
524 insn_allows_mem
[i
] = 0;
526 /* Process each alternative, each time minimizing an operand's cost
527 with the cost for each operand in that alternative. */
528 alternative_mask preferred
= get_preferred_alternatives (insn
);
529 for (alt
= 0; alt
< n_alts
; alt
++)
531 enum reg_class classes
[MAX_RECOG_OPERANDS
];
532 int allows_mem
[MAX_RECOG_OPERANDS
];
533 enum reg_class rclass
;
535 int alt_cost
= 0, op_cost_add
;
537 if (!TEST_BIT (preferred
, alt
))
539 for (i
= 0; i
< recog_data
.n_operands
; i
++)
540 constraints
[i
] = skip_alternative (constraints
[i
]);
545 for (i
= 0; i
< n_ops
; i
++)
548 const char *p
= constraints
[i
];
550 machine_mode mode
= modes
[i
];
554 /* Initially show we know nothing about the register class. */
555 classes
[i
] = NO_REGS
;
558 /* If this operand has no constraints at all, we can
559 conclude nothing about it since anything is valid. */
562 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
563 memset (this_op_costs
[i
], 0, struct_costs_size
);
567 /* If this alternative is only relevant when this operand
568 matches a previous operand, we do different things
569 depending on whether this operand is a allocno-reg or not.
570 We must process any modifiers for the operand before we
571 can make this test. */
572 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
575 if (p
[0] >= '0' && p
[0] <= '0' + i
)
577 /* Copy class and whether memory is allowed from the
578 matching alternative. Then perform any needed cost
579 computations and/or adjustments. */
581 classes
[i
] = classes
[j
];
582 allows_mem
[i
] = allows_mem
[j
];
584 insn_allows_mem
[i
] = 1;
586 if (! REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
588 /* If this matches the other operand, we have no
589 added cost and we win. */
590 if (rtx_equal_p (ops
[j
], op
))
592 /* If we can put the other operand into a register,
593 add to the cost of this alternative the cost to
594 copy this operand to the register used for the
596 else if (classes
[j
] != NO_REGS
)
598 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1, NULL
);
602 else if (! REG_P (ops
[j
])
603 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
605 /* This op is an allocno but the one it matches is
608 /* If we can't put the other operand into a
609 register, this alternative can't be used. */
611 if (classes
[j
] == NO_REGS
)
613 /* Otherwise, add to the cost of this alternative
614 the cost to copy the other operand to the hard
615 register used for this operand. */
617 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1, NULL
);
621 /* The costs of this operand are not the same as the
622 other operand since move costs are not symmetric.
623 Moreover, if we cannot tie them, this alternative
624 needs to do a copy, which is one insn. */
625 struct costs
*pp
= this_op_costs
[i
];
626 int *pp_costs
= pp
->cost
;
627 cost_classes_t cost_classes_ptr
628 = regno_cost_classes
[REGNO (op
)];
629 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
630 bool in_p
= recog_data
.operand_type
[i
] != OP_OUT
;
631 bool out_p
= recog_data
.operand_type
[i
] != OP_IN
;
632 enum reg_class op_class
= classes
[i
];
634 ira_init_register_move_cost_if_necessary (mode
);
638 if (op_class
== NO_REGS
)
640 mem_cost
= ira_memory_move_cost
[mode
];
641 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
643 rclass
= cost_classes
[k
];
644 pp_costs
[k
] = mem_cost
[rclass
][0] * frequency
;
649 move_out_cost
= ira_may_move_out_cost
[mode
];
650 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
652 rclass
= cost_classes
[k
];
654 = move_out_cost
[op_class
][rclass
] * frequency
;
661 if (op_class
== NO_REGS
)
663 mem_cost
= ira_memory_move_cost
[mode
];
664 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
666 rclass
= cost_classes
[k
];
667 pp_costs
[k
] = mem_cost
[rclass
][1] * frequency
;
672 move_in_cost
= ira_may_move_in_cost
[mode
];
673 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
675 rclass
= cost_classes
[k
];
677 = move_in_cost
[rclass
][op_class
] * frequency
;
683 if (op_class
== NO_REGS
)
685 mem_cost
= ira_memory_move_cost
[mode
];
686 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
688 rclass
= cost_classes
[k
];
689 pp_costs
[k
] = ((mem_cost
[rclass
][0]
690 + mem_cost
[rclass
][1])
696 move_in_cost
= ira_may_move_in_cost
[mode
];
697 move_out_cost
= ira_may_move_out_cost
[mode
];
698 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
700 rclass
= cost_classes
[k
];
701 pp_costs
[k
] = ((move_in_cost
[rclass
][op_class
]
702 + move_out_cost
[op_class
][rclass
])
708 /* If the alternative actually allows memory, make
709 things a bit cheaper since we won't need an extra
712 = ((out_p
? ira_memory_move_cost
[mode
][op_class
][0] : 0)
713 + (in_p
? ira_memory_move_cost
[mode
][op_class
][1] : 0)
714 - allows_mem
[i
]) * frequency
;
716 /* If we have assigned a class to this allocno in
717 our first pass, add a cost to this alternative
718 corresponding to what we would add if this
719 allocno were not in the appropriate class. */
722 enum reg_class pref_class
= pref
[COST_INDEX (REGNO (op
))];
724 if (pref_class
== NO_REGS
)
727 ? ira_memory_move_cost
[mode
][op_class
][0] : 0)
729 ? ira_memory_move_cost
[mode
][op_class
][1]
731 else if (ira_reg_class_intersect
732 [pref_class
][op_class
] == NO_REGS
)
734 += ira_register_move_cost
[mode
][pref_class
][op_class
];
736 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
737 && ! find_reg_note (insn
, REG_DEAD
, op
))
744 /* Scan all the constraint letters. See if the operand
745 matches any of the constraints. Collect the valid
746 register classes and see if this operand accepts
753 /* Ignore the next letter for this pass. */
768 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))))
770 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
771 classes
[i
] = ira_reg_class_subunion
[classes
[i
]][GENERAL_REGS
];
775 enum constraint_num cn
= lookup_constraint (p
);
777 switch (get_constraint_type (cn
))
780 cl
= reg_class_for_constraint (cn
);
782 classes
[i
] = ira_reg_class_subunion
[classes
[i
]][cl
];
787 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
792 /* Every MEM can be reloaded to fit. */
793 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
799 /* Every address can be reloaded to fit. */
801 if (address_operand (op
, GET_MODE (op
))
802 || constraint_satisfied_p (op
, cn
))
804 /* We know this operand is an address, so we
805 want it to be allocated to a hard register
806 that can be the base of an address,
807 i.e. BASE_REG_CLASS. */
809 = ira_reg_class_subunion
[classes
[i
]]
810 [base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
815 if (constraint_satisfied_p (op
, cn
))
821 p
+= CONSTRAINT_LEN (c
, p
);
828 /* How we account for this operand now depends on whether it
829 is a pseudo register or not. If it is, we first check if
830 any register classes are valid. If not, we ignore this
831 alternative, since we want to assume that all allocnos get
832 allocated for register preferencing. If some register
833 class is valid, compute the costs of moving the allocno
835 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
837 if (classes
[i
] == NO_REGS
&& ! allows_mem
[i
])
839 /* We must always fail if the operand is a REG, but
840 we did not find a suitable class and memory is
843 Otherwise we may perform an uninitialized read
844 from this_op_costs after the `continue' statement
850 unsigned int regno
= REGNO (op
);
851 struct costs
*pp
= this_op_costs
[i
];
852 int *pp_costs
= pp
->cost
;
853 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
854 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
855 bool in_p
= recog_data
.operand_type
[i
] != OP_OUT
;
856 bool out_p
= recog_data
.operand_type
[i
] != OP_IN
;
857 enum reg_class op_class
= classes
[i
];
859 ira_init_register_move_cost_if_necessary (mode
);
863 if (op_class
== NO_REGS
)
865 mem_cost
= ira_memory_move_cost
[mode
];
866 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
868 rclass
= cost_classes
[k
];
869 pp_costs
[k
] = mem_cost
[rclass
][0] * frequency
;
874 move_out_cost
= ira_may_move_out_cost
[mode
];
875 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
877 rclass
= cost_classes
[k
];
879 = move_out_cost
[op_class
][rclass
] * frequency
;
886 if (op_class
== NO_REGS
)
888 mem_cost
= ira_memory_move_cost
[mode
];
889 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
891 rclass
= cost_classes
[k
];
892 pp_costs
[k
] = mem_cost
[rclass
][1] * frequency
;
897 move_in_cost
= ira_may_move_in_cost
[mode
];
898 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
900 rclass
= cost_classes
[k
];
902 = move_in_cost
[rclass
][op_class
] * frequency
;
908 if (op_class
== NO_REGS
)
910 mem_cost
= ira_memory_move_cost
[mode
];
911 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
913 rclass
= cost_classes
[k
];
914 pp_costs
[k
] = ((mem_cost
[rclass
][0]
915 + mem_cost
[rclass
][1])
921 move_in_cost
= ira_may_move_in_cost
[mode
];
922 move_out_cost
= ira_may_move_out_cost
[mode
];
923 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
925 rclass
= cost_classes
[k
];
926 pp_costs
[k
] = ((move_in_cost
[rclass
][op_class
]
927 + move_out_cost
[op_class
][rclass
])
933 if (op_class
== NO_REGS
)
934 /* Although we don't need insn to reload from
935 memory, still accessing memory is usually more
936 expensive than a register. */
937 pp
->mem_cost
= frequency
;
939 /* If the alternative actually allows memory, make
940 things a bit cheaper since we won't need an
941 extra insn to load it. */
943 = ((out_p
? ira_memory_move_cost
[mode
][op_class
][0] : 0)
944 + (in_p
? ira_memory_move_cost
[mode
][op_class
][1] : 0)
945 - allows_mem
[i
]) * frequency
;
946 /* If we have assigned a class to this allocno in
947 our first pass, add a cost to this alternative
948 corresponding to what we would add if this
949 allocno were not in the appropriate class. */
952 enum reg_class pref_class
= pref
[COST_INDEX (REGNO (op
))];
954 if (pref_class
== NO_REGS
)
956 if (op_class
!= NO_REGS
)
959 ? ira_memory_move_cost
[mode
][op_class
][0]
962 ? ira_memory_move_cost
[mode
][op_class
][1]
965 else if (op_class
== NO_REGS
)
968 ? ira_memory_move_cost
[mode
][pref_class
][1]
971 ? ira_memory_move_cost
[mode
][pref_class
][0]
973 else if (ira_reg_class_intersect
[pref_class
][op_class
]
975 alt_cost
+= (ira_register_move_cost
976 [mode
][pref_class
][op_class
]);
981 /* Otherwise, if this alternative wins, either because we
982 have already determined that or if we have a hard
983 register of the proper class, there is no cost for this
985 else if (win
|| (REG_P (op
)
986 && reg_fits_class_p (op
, classes
[i
],
990 /* If registers are valid, the cost of this alternative
991 includes copying the object to and/or from a
993 else if (classes
[i
] != NO_REGS
)
995 if (recog_data
.operand_type
[i
] != OP_OUT
)
996 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1, NULL
);
998 if (recog_data
.operand_type
[i
] != OP_IN
)
999 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0, NULL
);
1001 /* The only other way this alternative can be used is if
1002 this is a constant that could be placed into memory. */
1003 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
1004 alt_cost
+= ira_memory_move_cost
[mode
][classes
[i
]][1];
1012 op_cost_add
= alt_cost
* frequency
;
1013 /* Finally, update the costs with the information we've
1014 calculated about this alternative. */
1015 for (i
= 0; i
< n_ops
; i
++)
1016 if (REG_P (ops
[i
]) && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1018 struct costs
*pp
= op_costs
[i
], *qq
= this_op_costs
[i
];
1019 int *pp_costs
= pp
->cost
, *qq_costs
= qq
->cost
;
1020 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
1021 cost_classes_t cost_classes_ptr
1022 = regno_cost_classes
[REGNO (ops
[i
])];
1024 pp
->mem_cost
= MIN (pp
->mem_cost
,
1025 (qq
->mem_cost
+ op_cost_add
) * scale
);
1027 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1029 = MIN (pp_costs
[k
], (qq_costs
[k
] + op_cost_add
) * scale
);
1034 for (i
= 0; i
< n_ops
; i
++)
1039 if (! REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
1041 a
= ira_curr_regno_allocno_map
[REGNO (op
)];
1042 if (! ALLOCNO_BAD_SPILL_P (a
) && insn_allows_mem
[i
] == 0)
1043 ALLOCNO_BAD_SPILL_P (a
) = true;
1050 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
1052 ok_for_index_p_nonstrict (rtx reg
)
1054 unsigned regno
= REGNO (reg
);
1056 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
1059 /* A version of regno_ok_for_base_p for use here, when all
1060 pseudo-registers should count as OK. Arguments as for
1061 regno_ok_for_base_p. */
1063 ok_for_base_p_nonstrict (rtx reg
, machine_mode mode
, addr_space_t as
,
1064 enum rtx_code outer_code
, enum rtx_code index_code
)
1066 unsigned regno
= REGNO (reg
);
1068 if (regno
>= FIRST_PSEUDO_REGISTER
)
1070 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
1073 /* Record the pseudo registers we must reload into hard registers in a
1074 subexpression of a memory address, X.
1076 If CONTEXT is 0, we are looking at the base part of an address,
1077 otherwise we are looking at the index part.
1079 MODE and AS are the mode and address space of the memory reference;
1080 OUTER_CODE and INDEX_CODE give the context that the rtx appears in.
1081 These four arguments are passed down to base_reg_class.
1083 SCALE is twice the amount to multiply the cost by (it is twice so
1084 we can represent half-cost adjustments). */
1086 record_address_regs (machine_mode mode
, addr_space_t as
, rtx x
,
1087 int context
, enum rtx_code outer_code
,
1088 enum rtx_code index_code
, int scale
)
1090 enum rtx_code code
= GET_CODE (x
);
1091 enum reg_class rclass
;
1094 rclass
= INDEX_REG_CLASS
;
1096 rclass
= base_reg_class (mode
, as
, outer_code
, index_code
);
1109 /* When we have an address that is a sum, we must determine
1110 whether registers are "base" or "index" regs. If there is a
1111 sum of two registers, we must choose one to be the "base".
1112 Luckily, we can use the REG_POINTER to make a good choice
1113 most of the time. We only need to do this on machines that
1114 can have two registers in an address and where the base and
1115 index register classes are different.
1117 ??? This code used to set REGNO_POINTER_FLAG in some cases,
1118 but that seems bogus since it should only be set when we are
1119 sure the register is being used as a pointer. */
1121 rtx arg0
= XEXP (x
, 0);
1122 rtx arg1
= XEXP (x
, 1);
1123 enum rtx_code code0
= GET_CODE (arg0
);
1124 enum rtx_code code1
= GET_CODE (arg1
);
1126 /* Look inside subregs. */
1127 if (code0
== SUBREG
)
1128 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
1129 if (code1
== SUBREG
)
1130 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
1132 /* If this machine only allows one register per address, it
1133 must be in the first operand. */
1134 if (MAX_REGS_PER_ADDRESS
== 1)
1135 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
);
1137 /* If index and base registers are the same on this machine,
1138 just record registers in any non-constant operands. We
1139 assume here, as well as in the tests below, that all
1140 addresses are in canonical form. */
1141 else if (INDEX_REG_CLASS
1142 == base_reg_class (VOIDmode
, as
, PLUS
, SCRATCH
))
1144 record_address_regs (mode
, as
, arg0
, context
, PLUS
, code1
, scale
);
1145 if (! CONSTANT_P (arg1
))
1146 record_address_regs (mode
, as
, arg1
, context
, PLUS
, code0
, scale
);
1149 /* If the second operand is a constant integer, it doesn't
1150 change what class the first operand must be. */
1151 else if (CONST_SCALAR_INT_P (arg1
))
1152 record_address_regs (mode
, as
, arg0
, context
, PLUS
, code1
, scale
);
1153 /* If the second operand is a symbolic constant, the first
1154 operand must be an index register. */
1155 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
1156 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
);
1157 /* If both operands are registers but one is already a hard
1158 register of index or reg-base class, give the other the
1159 class that the hard register is not. */
1160 else if (code0
== REG
&& code1
== REG
1161 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
1162 && (ok_for_base_p_nonstrict (arg0
, mode
, as
, PLUS
, REG
)
1163 || ok_for_index_p_nonstrict (arg0
)))
1164 record_address_regs (mode
, as
, arg1
,
1165 ok_for_base_p_nonstrict (arg0
, mode
, as
,
1168 else if (code0
== REG
&& code1
== REG
1169 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
1170 && (ok_for_base_p_nonstrict (arg1
, mode
, as
, PLUS
, REG
)
1171 || ok_for_index_p_nonstrict (arg1
)))
1172 record_address_regs (mode
, as
, arg0
,
1173 ok_for_base_p_nonstrict (arg1
, mode
, as
,
1176 /* If one operand is known to be a pointer, it must be the
1177 base with the other operand the index. Likewise if the
1178 other operand is a MULT. */
1179 else if ((code0
== REG
&& REG_POINTER (arg0
)) || code1
== MULT
)
1181 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
);
1182 record_address_regs (mode
, as
, arg1
, 1, PLUS
, code0
, scale
);
1184 else if ((code1
== REG
&& REG_POINTER (arg1
)) || code0
== MULT
)
1186 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
);
1187 record_address_regs (mode
, as
, arg1
, 0, PLUS
, code0
, scale
);
1189 /* Otherwise, count equal chances that each might be a base or
1190 index register. This case should be rare. */
1193 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
/ 2);
1194 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
/ 2);
1195 record_address_regs (mode
, as
, arg1
, 0, PLUS
, code0
, scale
/ 2);
1196 record_address_regs (mode
, as
, arg1
, 1, PLUS
, code0
, scale
/ 2);
1201 /* Double the importance of an allocno that is incremented or
1202 decremented, since it would take two extra insns if it ends
1203 up in the wrong place. */
1206 record_address_regs (mode
, as
, XEXP (x
, 0), 0, code
,
1207 GET_CODE (XEXP (XEXP (x
, 1), 1)), 2 * scale
);
1208 if (REG_P (XEXP (XEXP (x
, 1), 1)))
1209 record_address_regs (mode
, as
, XEXP (XEXP (x
, 1), 1), 1, code
, REG
,
1217 /* Double the importance of an allocno that is incremented or
1218 decremented, since it would take two extra insns if it ends
1219 up in the wrong place. */
1220 record_address_regs (mode
, as
, XEXP (x
, 0), 0, code
, SCRATCH
, 2 * scale
);
1228 int k
, regno
, add_cost
;
1229 cost_classes_t cost_classes_ptr
;
1230 enum reg_class
*cost_classes
;
1231 move_table
*move_in_cost
;
1233 if (REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1238 ALLOCNO_BAD_SPILL_P (ira_curr_regno_allocno_map
[regno
]) = true;
1239 pp
= COSTS (costs
, COST_INDEX (regno
));
1240 add_cost
= (ira_memory_move_cost
[Pmode
][rclass
][1] * scale
) / 2;
1241 if (INT_MAX
- add_cost
< pp
->mem_cost
)
1242 pp
->mem_cost
= INT_MAX
;
1244 pp
->mem_cost
+= add_cost
;
1245 cost_classes_ptr
= regno_cost_classes
[regno
];
1246 cost_classes
= cost_classes_ptr
->classes
;
1247 pp_costs
= pp
->cost
;
1248 ira_init_register_move_cost_if_necessary (Pmode
);
1249 move_in_cost
= ira_may_move_in_cost
[Pmode
];
1250 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1252 i
= cost_classes
[k
];
1253 add_cost
= (move_in_cost
[i
][rclass
] * scale
) / 2;
1254 if (INT_MAX
- add_cost
< pp_costs
[k
])
1255 pp_costs
[k
] = INT_MAX
;
1257 pp_costs
[k
] += add_cost
;
1264 const char *fmt
= GET_RTX_FORMAT (code
);
1266 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1268 record_address_regs (mode
, as
, XEXP (x
, i
), context
, code
, SCRATCH
,
1276 /* Calculate the costs of insn operands. */
1278 record_operand_costs (rtx_insn
*insn
, enum reg_class
*pref
)
1280 const char *constraints
[MAX_RECOG_OPERANDS
];
1281 machine_mode modes
[MAX_RECOG_OPERANDS
];
1282 rtx ops
[MAX_RECOG_OPERANDS
];
1286 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1288 constraints
[i
] = recog_data
.constraints
[i
];
1289 modes
[i
] = recog_data
.operand_mode
[i
];
1292 /* If we get here, we are set up to record the costs of all the
1293 operands for this insn. Start by initializing the costs. Then
1294 handle any address registers. Finally record the desired classes
1295 for any allocnos, doing it twice if some pair of operands are
1297 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1299 memcpy (op_costs
[i
], init_cost
, struct_costs_size
);
1301 ops
[i
] = recog_data
.operand
[i
];
1302 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
1303 recog_data
.operand
[i
] = SUBREG_REG (recog_data
.operand
[i
]);
1305 if (MEM_P (recog_data
.operand
[i
]))
1306 record_address_regs (GET_MODE (recog_data
.operand
[i
]),
1307 MEM_ADDR_SPACE (recog_data
.operand
[i
]),
1308 XEXP (recog_data
.operand
[i
], 0),
1309 0, MEM
, SCRATCH
, frequency
* 2);
1310 else if (constraints
[i
][0] == 'p'
1311 || (insn_extra_address_constraint
1312 (lookup_constraint (constraints
[i
]))))
1313 record_address_regs (VOIDmode
, ADDR_SPACE_GENERIC
,
1314 recog_data
.operand
[i
], 0, ADDRESS
, SCRATCH
,
1318 /* Check for commutative in a separate loop so everything will have
1319 been initialized. We must do this even if one operand is a
1320 constant--see addsi3 in m68k.md. */
1321 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
1322 if (constraints
[i
][0] == '%')
1324 const char *xconstraints
[MAX_RECOG_OPERANDS
];
1327 /* Handle commutative operands by swapping the constraints.
1328 We assume the modes are the same. */
1329 for (j
= 0; j
< recog_data
.n_operands
; j
++)
1330 xconstraints
[j
] = constraints
[j
];
1332 xconstraints
[i
] = constraints
[i
+1];
1333 xconstraints
[i
+1] = constraints
[i
];
1334 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1335 recog_data
.operand
, modes
,
1336 xconstraints
, insn
, pref
);
1338 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1339 recog_data
.operand
, modes
,
1340 constraints
, insn
, pref
);
1342 /* If this insn is a single set copying operand 1 to operand 0 and
1343 one operand is an allocno with the other a hard reg or an allocno
1344 that prefers a hard register that is in its own register class
1345 then we may want to adjust the cost of that register class to -1.
1347 Avoid the adjustment if the source does not die to avoid
1348 stressing of register allocator by preferencing two colliding
1349 registers into single class.
1351 Also avoid the adjustment if a copy between hard registers of the
1352 class is expensive (ten times the cost of a default copy is
1353 considered arbitrarily expensive). This avoids losing when the
1354 preferred class is very expensive as the source of a copy
1356 if ((set
= single_set (insn
)) != NULL_RTX
1357 /* In rare cases the single set insn might have less 2 operands
1358 as the source can be a fixed special reg. */
1359 && recog_data
.n_operands
> 1
1360 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
))
1362 int regno
, other_regno
;
1363 rtx dest
= SET_DEST (set
);
1364 rtx src
= SET_SRC (set
);
1366 if (GET_CODE (dest
) == SUBREG
1367 && (GET_MODE_SIZE (GET_MODE (dest
))
1368 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))))
1369 dest
= SUBREG_REG (dest
);
1370 if (GET_CODE (src
) == SUBREG
1371 && (GET_MODE_SIZE (GET_MODE (src
))
1372 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))))
1373 src
= SUBREG_REG (src
);
1374 if (REG_P (src
) && REG_P (dest
)
1375 && find_regno_note (insn
, REG_DEAD
, REGNO (src
))
1376 && (((regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
1377 && (other_regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
)
1378 || ((regno
= REGNO (dest
)) >= FIRST_PSEUDO_REGISTER
1379 && (other_regno
= REGNO (src
)) < FIRST_PSEUDO_REGISTER
)))
1381 machine_mode mode
= GET_MODE (src
);
1382 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1383 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1387 i
= regno
== (int) REGNO (src
) ? 1 : 0;
1388 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1390 rclass
= cost_classes
[k
];
1391 if (TEST_HARD_REG_BIT (reg_class_contents
[rclass
], other_regno
)
1392 && (reg_class_size
[(int) rclass
]
1393 == ira_reg_class_max_nregs
[(int) rclass
][(int) mode
]))
1395 if (reg_class_size
[rclass
] == 1)
1396 op_costs
[i
]->cost
[k
] = -frequency
;
1400 nr
< hard_regno_nregs
[other_regno
][mode
];
1402 if (! TEST_HARD_REG_BIT (reg_class_contents
[rclass
],
1406 if (nr
== hard_regno_nregs
[other_regno
][mode
])
1407 op_costs
[i
]->cost
[k
] = -frequency
;
1417 /* Process one insn INSN. Scan it and record each time it would save
1418 code to put a certain allocnos in a certain class. Return the last
1419 insn processed, so that the scan can be continued from there. */
1421 scan_one_insn (rtx_insn
*insn
)
1423 enum rtx_code pat_code
;
1428 if (!NONDEBUG_INSN_P (insn
))
1431 pat_code
= GET_CODE (PATTERN (insn
));
1432 if (pat_code
== USE
|| pat_code
== CLOBBER
|| pat_code
== ASM_INPUT
)
1435 counted_mem
= false;
1436 set
= single_set (insn
);
1437 extract_insn (insn
);
1439 /* If this insn loads a parameter from its stack slot, then it
1440 represents a savings, rather than a cost, if the parameter is
1441 stored in memory. Record this fact.
1443 Similarly if we're loading other constants from memory (constant
1444 pool, TOC references, small data areas, etc) and this is the only
1445 assignment to the destination pseudo.
1447 Don't do this if SET_SRC (set) isn't a general operand, if it is
1448 a memory requiring special instructions to load it, decreasing
1449 mem_cost might result in it being loaded using the specialized
1450 instruction into a register, then stored into stack and loaded
1451 again from the stack. See PR52208.
1453 Don't do this if SET_SRC (set) has side effect. See PR56124. */
1454 if (set
!= 0 && REG_P (SET_DEST (set
)) && MEM_P (SET_SRC (set
))
1455 && (note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
)) != NULL_RTX
1456 && ((MEM_P (XEXP (note
, 0))
1457 && !side_effects_p (SET_SRC (set
)))
1458 || (CONSTANT_P (XEXP (note
, 0))
1459 && targetm
.legitimate_constant_p (GET_MODE (SET_DEST (set
)),
1461 && REG_N_SETS (REGNO (SET_DEST (set
))) == 1))
1462 && general_operand (SET_SRC (set
), GET_MODE (SET_SRC (set
))))
1464 enum reg_class cl
= GENERAL_REGS
;
1465 rtx reg
= SET_DEST (set
);
1466 int num
= COST_INDEX (REGNO (reg
));
1468 COSTS (costs
, num
)->mem_cost
1469 -= ira_memory_move_cost
[GET_MODE (reg
)][cl
][1] * frequency
;
1470 record_address_regs (GET_MODE (SET_SRC (set
)),
1471 MEM_ADDR_SPACE (SET_SRC (set
)),
1472 XEXP (SET_SRC (set
), 0), 0, MEM
, SCRATCH
,
1477 record_operand_costs (insn
, pref
);
1479 /* Now add the cost for each operand to the total costs for its
1481 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1482 if (REG_P (recog_data
.operand
[i
])
1483 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
1485 int regno
= REGNO (recog_data
.operand
[i
]);
1486 struct costs
*p
= COSTS (costs
, COST_INDEX (regno
));
1487 struct costs
*q
= op_costs
[i
];
1488 int *p_costs
= p
->cost
, *q_costs
= q
->cost
;
1489 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1492 /* If the already accounted for the memory "cost" above, don't
1496 add_cost
= q
->mem_cost
;
1497 if (add_cost
> 0 && INT_MAX
- add_cost
< p
->mem_cost
)
1498 p
->mem_cost
= INT_MAX
;
1500 p
->mem_cost
+= add_cost
;
1502 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1504 add_cost
= q_costs
[k
];
1505 if (add_cost
> 0 && INT_MAX
- add_cost
< p_costs
[k
])
1506 p_costs
[k
] = INT_MAX
;
1508 p_costs
[k
] += add_cost
;
1517 /* Print allocnos costs to file F. */
1519 print_allocno_costs (FILE *f
)
1523 ira_allocno_iterator ai
;
1525 ira_assert (allocno_p
);
1527 FOR_EACH_ALLOCNO (a
, ai
)
1531 int regno
= ALLOCNO_REGNO (a
);
1532 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1533 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1535 i
= ALLOCNO_NUM (a
);
1536 fprintf (f
, " a%d(r%d,", i
, regno
);
1537 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1538 fprintf (f
, "b%d", bb
->index
);
1540 fprintf (f
, "l%d", ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
1541 fprintf (f
, ") costs:");
1542 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1544 rclass
= cost_classes
[k
];
1545 fprintf (f
, " %s:%d", reg_class_names
[rclass
],
1546 COSTS (costs
, i
)->cost
[k
]);
1547 if (flag_ira_region
== IRA_REGION_ALL
1548 || flag_ira_region
== IRA_REGION_MIXED
)
1549 fprintf (f
, ",%d", COSTS (total_allocno_costs
, i
)->cost
[k
]);
1551 fprintf (f
, " MEM:%i", COSTS (costs
, i
)->mem_cost
);
1552 if (flag_ira_region
== IRA_REGION_ALL
1553 || flag_ira_region
== IRA_REGION_MIXED
)
1554 fprintf (f
, ",%d", COSTS (total_allocno_costs
, i
)->mem_cost
);
1559 /* Print pseudo costs to file F. */
1561 print_pseudo_costs (FILE *f
)
1565 cost_classes_t cost_classes_ptr
;
1566 enum reg_class
*cost_classes
;
1568 ira_assert (! allocno_p
);
1570 for (regno
= max_reg_num () - 1; regno
>= FIRST_PSEUDO_REGISTER
; regno
--)
1572 if (REG_N_REFS (regno
) <= 0)
1574 cost_classes_ptr
= regno_cost_classes
[regno
];
1575 cost_classes
= cost_classes_ptr
->classes
;
1576 fprintf (f
, " r%d costs:", regno
);
1577 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1579 rclass
= cost_classes
[k
];
1580 fprintf (f
, " %s:%d", reg_class_names
[rclass
],
1581 COSTS (costs
, regno
)->cost
[k
]);
1583 fprintf (f
, " MEM:%i\n", COSTS (costs
, regno
)->mem_cost
);
1587 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1590 process_bb_for_costs (basic_block bb
)
1594 frequency
= REG_FREQ_FROM_BB (bb
);
1597 FOR_BB_INSNS (bb
, insn
)
1598 insn
= scan_one_insn (insn
);
1601 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1604 process_bb_node_for_costs (ira_loop_tree_node_t loop_tree_node
)
1608 bb
= loop_tree_node
->bb
;
1610 process_bb_for_costs (bb
);
1613 /* Find costs of register classes and memory for allocnos or pseudos
1614 and their best costs. Set up preferred, alternative and allocno
1615 classes for pseudos. */
1617 find_costs_and_classes (FILE *dump_file
)
1619 int i
, k
, start
, max_cost_classes_num
;
1622 enum reg_class
*regno_best_class
, new_class
;
1626 = (enum reg_class
*) ira_allocate (max_reg_num ()
1627 * sizeof (enum reg_class
));
1628 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1629 regno_best_class
[i
] = NO_REGS
;
1630 if (!resize_reg_info () && allocno_p
1631 && pseudo_classes_defined_p
&& flag_expensive_optimizations
)
1634 ira_allocno_iterator ai
;
1637 max_cost_classes_num
= 1;
1638 FOR_EACH_ALLOCNO (a
, ai
)
1640 pref
[ALLOCNO_NUM (a
)] = reg_preferred_class (ALLOCNO_REGNO (a
));
1641 setup_regno_cost_classes_by_aclass
1642 (ALLOCNO_REGNO (a
), pref
[ALLOCNO_NUM (a
)]);
1643 max_cost_classes_num
1644 = MAX (max_cost_classes_num
,
1645 regno_cost_classes
[ALLOCNO_REGNO (a
)]->num
);
1652 max_cost_classes_num
= ira_important_classes_num
;
1653 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1654 if (regno_reg_rtx
[i
] != NULL_RTX
)
1655 setup_regno_cost_classes_by_mode (i
, PSEUDO_REGNO_MODE (i
));
1657 setup_regno_cost_classes_by_aclass (i
, ALL_REGS
);
1661 /* Clear the flag for the next compiled function. */
1662 pseudo_classes_defined_p
= false;
1663 /* Normally we scan the insns once and determine the best class to
1664 use for each allocno. However, if -fexpensive-optimizations are
1665 on, we do so twice, the second time using the tentative best
1666 classes to guide the selection. */
1667 for (pass
= start
; pass
<= flag_expensive_optimizations
; pass
++)
1669 if ((!allocno_p
|| internal_flag_ira_verbose
> 0) && dump_file
)
1671 "\nPass %i for finding pseudo/allocno costs\n\n", pass
);
1675 max_cost_classes_num
= 1;
1676 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1678 setup_regno_cost_classes_by_aclass (i
, regno_best_class
[i
]);
1679 max_cost_classes_num
1680 = MAX (max_cost_classes_num
, regno_cost_classes
[i
]->num
);
1685 = sizeof (struct costs
) + sizeof (int) * (max_cost_classes_num
- 1);
1686 /* Zero out our accumulation of the cost of each class for each
1688 memset (costs
, 0, cost_elements_num
* struct_costs_size
);
1692 /* Scan the instructions and record each time it would save code
1693 to put a certain allocno in a certain class. */
1694 ira_traverse_loop_tree (true, ira_loop_tree_root
,
1695 process_bb_node_for_costs
, NULL
);
1697 memcpy (total_allocno_costs
, costs
,
1698 max_struct_costs_size
* ira_allocnos_num
);
1704 FOR_EACH_BB_FN (bb
, cfun
)
1705 process_bb_for_costs (bb
);
1711 /* Now for each allocno look at how desirable each class is and
1712 find which class is preferred. */
1713 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1715 ira_allocno_t a
, parent_a
;
1716 int rclass
, a_num
, parent_a_num
, add_cost
;
1717 ira_loop_tree_node_t parent
;
1718 int best_cost
, allocno_cost
;
1719 enum reg_class best
, alt_class
;
1720 cost_classes_t cost_classes_ptr
= regno_cost_classes
[i
];
1721 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1722 int *i_costs
= temp_costs
->cost
;
1724 int equiv_savings
= regno_equiv_gains
[i
];
1728 if (regno_reg_rtx
[i
] == NULL_RTX
)
1730 memcpy (temp_costs
, COSTS (costs
, i
), struct_costs_size
);
1731 i_mem_cost
= temp_costs
->mem_cost
;
1735 if (ira_regno_allocno_map
[i
] == NULL
)
1737 memset (temp_costs
, 0, struct_costs_size
);
1739 /* Find cost of all allocnos with the same regno. */
1740 for (a
= ira_regno_allocno_map
[i
];
1742 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1744 int *a_costs
, *p_costs
;
1746 a_num
= ALLOCNO_NUM (a
);
1747 if ((flag_ira_region
== IRA_REGION_ALL
1748 || flag_ira_region
== IRA_REGION_MIXED
)
1749 && (parent
= ALLOCNO_LOOP_TREE_NODE (a
)->parent
) != NULL
1750 && (parent_a
= parent
->regno_allocno_map
[i
]) != NULL
1751 /* There are no caps yet. */
1752 && bitmap_bit_p (ALLOCNO_LOOP_TREE_NODE
1753 (a
)->border_allocnos
,
1756 /* Propagate costs to upper levels in the region
1758 parent_a_num
= ALLOCNO_NUM (parent_a
);
1759 a_costs
= COSTS (total_allocno_costs
, a_num
)->cost
;
1760 p_costs
= COSTS (total_allocno_costs
, parent_a_num
)->cost
;
1761 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1763 add_cost
= a_costs
[k
];
1764 if (add_cost
> 0 && INT_MAX
- add_cost
< p_costs
[k
])
1765 p_costs
[k
] = INT_MAX
;
1767 p_costs
[k
] += add_cost
;
1769 add_cost
= COSTS (total_allocno_costs
, a_num
)->mem_cost
;
1771 && (INT_MAX
- add_cost
1772 < COSTS (total_allocno_costs
,
1773 parent_a_num
)->mem_cost
))
1774 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
1777 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
1780 if (i
>= first_moveable_pseudo
&& i
< last_moveable_pseudo
)
1781 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
= 0;
1783 a_costs
= COSTS (costs
, a_num
)->cost
;
1784 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1786 add_cost
= a_costs
[k
];
1787 if (add_cost
> 0 && INT_MAX
- add_cost
< i_costs
[k
])
1788 i_costs
[k
] = INT_MAX
;
1790 i_costs
[k
] += add_cost
;
1792 add_cost
= COSTS (costs
, a_num
)->mem_cost
;
1793 if (add_cost
> 0 && INT_MAX
- add_cost
< i_mem_cost
)
1794 i_mem_cost
= INT_MAX
;
1796 i_mem_cost
+= add_cost
;
1799 if (i
>= first_moveable_pseudo
&& i
< last_moveable_pseudo
)
1801 else if (equiv_savings
< 0)
1802 i_mem_cost
= -equiv_savings
;
1803 else if (equiv_savings
> 0)
1806 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1807 i_costs
[k
] += equiv_savings
;
1810 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1812 alt_class
= NO_REGS
;
1813 /* Find best common class for all allocnos with the same
1815 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1817 rclass
= cost_classes
[k
];
1818 if (i_costs
[k
] < best_cost
)
1820 best_cost
= i_costs
[k
];
1821 best
= (enum reg_class
) rclass
;
1823 else if (i_costs
[k
] == best_cost
)
1824 best
= ira_reg_class_subunion
[best
][rclass
];
1825 if (pass
== flag_expensive_optimizations
1826 /* We still prefer registers to memory even at this
1827 stage if their costs are the same. We will make
1828 a final decision during assigning hard registers
1829 when we have all info including more accurate
1830 costs which might be affected by assigning hard
1831 registers to other pseudos because the pseudos
1832 involved in moves can be coalesced. */
1833 && i_costs
[k
] <= i_mem_cost
1834 && (reg_class_size
[reg_class_subunion
[alt_class
][rclass
]]
1835 > reg_class_size
[alt_class
]))
1836 alt_class
= reg_class_subunion
[alt_class
][rclass
];
1838 alt_class
= ira_allocno_class_translate
[alt_class
];
1839 if (best_cost
> i_mem_cost
1840 && ! non_spilled_static_chain_regno_p (i
))
1841 regno_aclass
[i
] = NO_REGS
;
1842 else if (!optimize
&& !targetm
.class_likely_spilled_p (best
))
1843 /* Registers in the alternative class are likely to need
1844 longer or slower sequences than registers in the best class.
1845 When optimizing we make some effort to use the best class
1846 over the alternative class where possible, but at -O0 we
1847 effectively give the alternative class equal weight.
1848 We then run the risk of using slower alternative registers
1849 when plenty of registers from the best class are still free.
1850 This is especially true because live ranges tend to be very
1851 short in -O0 code and so register pressure tends to be low.
1853 Avoid that by ignoring the alternative class if the best
1854 class has plenty of registers. */
1855 regno_aclass
[i
] = best
;
1858 /* Make the common class the biggest class of best and
1861 = ira_reg_class_superunion
[best
][alt_class
];
1862 ira_assert (regno_aclass
[i
] != NO_REGS
1863 && ira_reg_allocno_class_p
[regno_aclass
[i
]]);
1866 = (reg_class
) (targetm
.ira_change_pseudo_allocno_class
1867 (i
, regno_aclass
[i
]))) != regno_aclass
[i
])
1869 regno_aclass
[i
] = new_class
;
1870 if (hard_reg_set_subset_p (reg_class_contents
[new_class
],
1871 reg_class_contents
[best
]))
1873 if (hard_reg_set_subset_p (reg_class_contents
[new_class
],
1874 reg_class_contents
[alt_class
]))
1875 alt_class
= new_class
;
1877 if (pass
== flag_expensive_optimizations
)
1879 if (best_cost
> i_mem_cost
1880 /* Do not assign NO_REGS to static chain pointer
1881 pseudo when non-local goto is used. */
1882 && ! non_spilled_static_chain_regno_p (i
))
1883 best
= alt_class
= NO_REGS
;
1884 else if (best
== alt_class
)
1885 alt_class
= NO_REGS
;
1886 setup_reg_classes (i
, best
, alt_class
, regno_aclass
[i
]);
1887 if ((!allocno_p
|| internal_flag_ira_verbose
> 2)
1888 && dump_file
!= NULL
)
1890 " r%d: preferred %s, alternative %s, allocno %s\n",
1891 i
, reg_class_names
[best
], reg_class_names
[alt_class
],
1892 reg_class_names
[regno_aclass
[i
]]);
1894 regno_best_class
[i
] = best
;
1897 pref
[i
] = (best_cost
> i_mem_cost
1898 && ! non_spilled_static_chain_regno_p (i
)
1902 for (a
= ira_regno_allocno_map
[i
];
1904 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1906 enum reg_class aclass
= regno_aclass
[i
];
1907 int a_num
= ALLOCNO_NUM (a
);
1908 int *total_a_costs
= COSTS (total_allocno_costs
, a_num
)->cost
;
1909 int *a_costs
= COSTS (costs
, a_num
)->cost
;
1911 if (aclass
== NO_REGS
)
1915 /* Finding best class which is subset of the common
1917 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1918 allocno_cost
= best_cost
;
1920 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1922 rclass
= cost_classes
[k
];
1923 if (! ira_class_subset_p
[rclass
][aclass
])
1925 if (total_a_costs
[k
] < best_cost
)
1927 best_cost
= total_a_costs
[k
];
1928 allocno_cost
= a_costs
[k
];
1929 best
= (enum reg_class
) rclass
;
1931 else if (total_a_costs
[k
] == best_cost
)
1933 best
= ira_reg_class_subunion
[best
][rclass
];
1934 allocno_cost
= MAX (allocno_cost
, a_costs
[k
]);
1937 ALLOCNO_CLASS_COST (a
) = allocno_cost
;
1939 if (internal_flag_ira_verbose
> 2 && dump_file
!= NULL
1940 && (pass
== 0 || pref
[a_num
] != best
))
1942 fprintf (dump_file
, " a%d (r%d,", a_num
, i
);
1943 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1944 fprintf (dump_file
, "b%d", bb
->index
);
1946 fprintf (dump_file
, "l%d",
1947 ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
1948 fprintf (dump_file
, ") best %s, allocno %s\n",
1949 reg_class_names
[best
],
1950 reg_class_names
[aclass
]);
1953 if (pass
== flag_expensive_optimizations
&& best
!= aclass
1954 && ira_class_hard_regs_num
[best
] > 0
1955 && (ira_reg_class_max_nregs
[best
][ALLOCNO_MODE (a
)]
1956 >= ira_class_hard_regs_num
[best
]))
1958 int ind
= cost_classes_ptr
->index
[aclass
];
1960 ira_assert (ind
>= 0);
1961 ira_init_register_move_cost_if_necessary (ALLOCNO_MODE (a
));
1962 ira_add_allocno_pref (a
, ira_class_hard_regs
[best
][0],
1963 (a_costs
[ind
] - ALLOCNO_CLASS_COST (a
))
1964 / (ira_register_move_cost
1965 [ALLOCNO_MODE (a
)][best
][aclass
]));
1966 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1967 if (ira_class_subset_p
[cost_classes
[k
]][best
])
1968 a_costs
[k
] = a_costs
[ind
];
1973 if (internal_flag_ira_verbose
> 4 && dump_file
)
1976 print_allocno_costs (dump_file
);
1978 print_pseudo_costs (dump_file
);
1979 fprintf (dump_file
,"\n");
1982 ira_free (regno_best_class
);
1987 /* Process moves involving hard regs to modify allocno hard register
1988 costs. We can do this only after determining allocno class. If a
1989 hard register forms a register class, then moves with the hard
1990 register are already taken into account in class costs for the
1993 process_bb_node_for_hard_reg_moves (ira_loop_tree_node_t loop_tree_node
)
1995 int i
, freq
, src_regno
, dst_regno
, hard_regno
, a_regno
;
1997 ira_allocno_t a
, curr_a
;
1998 ira_loop_tree_node_t curr_loop_tree_node
;
1999 enum reg_class rclass
;
2004 bb
= loop_tree_node
->bb
;
2007 freq
= REG_FREQ_FROM_BB (bb
);
2010 FOR_BB_INSNS (bb
, insn
)
2012 if (!NONDEBUG_INSN_P (insn
))
2014 set
= single_set (insn
);
2015 if (set
== NULL_RTX
)
2017 dst
= SET_DEST (set
);
2018 src
= SET_SRC (set
);
2019 if (! REG_P (dst
) || ! REG_P (src
))
2021 dst_regno
= REGNO (dst
);
2022 src_regno
= REGNO (src
);
2023 if (dst_regno
>= FIRST_PSEUDO_REGISTER
2024 && src_regno
< FIRST_PSEUDO_REGISTER
)
2026 hard_regno
= src_regno
;
2027 a
= ira_curr_regno_allocno_map
[dst_regno
];
2030 else if (src_regno
>= FIRST_PSEUDO_REGISTER
2031 && dst_regno
< FIRST_PSEUDO_REGISTER
)
2033 hard_regno
= dst_regno
;
2034 a
= ira_curr_regno_allocno_map
[src_regno
];
2039 rclass
= ALLOCNO_CLASS (a
);
2040 if (! TEST_HARD_REG_BIT (reg_class_contents
[rclass
], hard_regno
))
2042 i
= ira_class_hard_reg_index
[rclass
][hard_regno
];
2045 a_regno
= ALLOCNO_REGNO (a
);
2046 for (curr_loop_tree_node
= ALLOCNO_LOOP_TREE_NODE (a
);
2047 curr_loop_tree_node
!= NULL
;
2048 curr_loop_tree_node
= curr_loop_tree_node
->parent
)
2049 if ((curr_a
= curr_loop_tree_node
->regno_allocno_map
[a_regno
]) != NULL
)
2050 ira_add_allocno_pref (curr_a
, hard_regno
, freq
);
2053 enum reg_class hard_reg_class
;
2056 mode
= ALLOCNO_MODE (a
);
2057 hard_reg_class
= REGNO_REG_CLASS (hard_regno
);
2058 ira_init_register_move_cost_if_necessary (mode
);
2059 cost
= (to_p
? ira_register_move_cost
[mode
][hard_reg_class
][rclass
]
2060 : ira_register_move_cost
[mode
][rclass
][hard_reg_class
]) * freq
;
2061 ira_allocate_and_set_costs (&ALLOCNO_HARD_REG_COSTS (a
), rclass
,
2062 ALLOCNO_CLASS_COST (a
));
2063 ira_allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a
),
2065 ALLOCNO_HARD_REG_COSTS (a
)[i
] -= cost
;
2066 ALLOCNO_CONFLICT_HARD_REG_COSTS (a
)[i
] -= cost
;
2067 ALLOCNO_CLASS_COST (a
) = MIN (ALLOCNO_CLASS_COST (a
),
2068 ALLOCNO_HARD_REG_COSTS (a
)[i
]);
2073 /* After we find hard register and memory costs for allocnos, define
2074 its class and modify hard register cost because insns moving
2075 allocno to/from hard registers. */
2077 setup_allocno_class_and_costs (void)
2079 int i
, j
, n
, regno
, hard_regno
, num
;
2081 enum reg_class aclass
, rclass
;
2083 ira_allocno_iterator ai
;
2084 cost_classes_t cost_classes_ptr
;
2086 ira_assert (allocno_p
);
2087 FOR_EACH_ALLOCNO (a
, ai
)
2089 i
= ALLOCNO_NUM (a
);
2090 regno
= ALLOCNO_REGNO (a
);
2091 aclass
= regno_aclass
[regno
];
2092 cost_classes_ptr
= regno_cost_classes
[regno
];
2093 ira_assert (pref
[i
] == NO_REGS
|| aclass
!= NO_REGS
);
2094 ALLOCNO_MEMORY_COST (a
) = COSTS (costs
, i
)->mem_cost
;
2095 ira_set_allocno_class (a
, aclass
);
2096 if (aclass
== NO_REGS
)
2098 if (optimize
&& ALLOCNO_CLASS (a
) != pref
[i
])
2100 n
= ira_class_hard_regs_num
[aclass
];
2101 ALLOCNO_HARD_REG_COSTS (a
)
2102 = reg_costs
= ira_allocate_cost_vector (aclass
);
2103 for (j
= n
- 1; j
>= 0; j
--)
2105 hard_regno
= ira_class_hard_regs
[aclass
][j
];
2106 if (TEST_HARD_REG_BIT (reg_class_contents
[pref
[i
]], hard_regno
))
2107 reg_costs
[j
] = ALLOCNO_CLASS_COST (a
);
2110 rclass
= REGNO_REG_CLASS (hard_regno
);
2111 num
= cost_classes_ptr
->index
[rclass
];
2114 num
= cost_classes_ptr
->hard_regno_index
[hard_regno
];
2115 ira_assert (num
>= 0);
2117 reg_costs
[j
] = COSTS (costs
, i
)->cost
[num
];
2123 ira_traverse_loop_tree (true, ira_loop_tree_root
,
2124 process_bb_node_for_hard_reg_moves
, NULL
);
2129 /* Function called once during compiler work. */
2131 ira_init_costs_once (void)
2136 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2139 this_op_costs
[i
] = NULL
;
2144 /* Free allocated temporary cost vectors. */
2146 target_ira_int::free_ira_costs ()
2152 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2154 free (x_op_costs
[i
]);
2155 free (x_this_op_costs
[i
]);
2156 x_op_costs
[i
] = x_this_op_costs
[i
] = NULL
;
2158 free (x_temp_costs
);
2159 x_temp_costs
= NULL
;
2162 /* This is called each time register related information is
2165 ira_init_costs (void)
2169 this_target_ira_int
->free_ira_costs ();
2170 max_struct_costs_size
2171 = sizeof (struct costs
) + sizeof (int) * (ira_important_classes_num
- 1);
2172 /* Don't use ira_allocate because vectors live through several IRA
2174 init_cost
= (struct costs
*) xmalloc (max_struct_costs_size
);
2175 init_cost
->mem_cost
= 1000000;
2176 for (i
= 0; i
< ira_important_classes_num
; i
++)
2177 init_cost
->cost
[i
] = 1000000;
2178 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2180 op_costs
[i
] = (struct costs
*) xmalloc (max_struct_costs_size
);
2181 this_op_costs
[i
] = (struct costs
*) xmalloc (max_struct_costs_size
);
2183 temp_costs
= (struct costs
*) xmalloc (max_struct_costs_size
);
2188 /* Common initialization function for ira_costs and
2189 ira_set_pseudo_classes. */
2193 init_subregs_of_mode ();
2194 costs
= (struct costs
*) ira_allocate (max_struct_costs_size
2195 * cost_elements_num
);
2196 pref_buffer
= (enum reg_class
*) ira_allocate (sizeof (enum reg_class
)
2197 * cost_elements_num
);
2198 regno_aclass
= (enum reg_class
*) ira_allocate (sizeof (enum reg_class
)
2200 regno_equiv_gains
= (int *) ira_allocate (sizeof (int) * max_reg_num ());
2201 memset (regno_equiv_gains
, 0, sizeof (int) * max_reg_num ());
2204 /* Common finalization function for ira_costs and
2205 ira_set_pseudo_classes. */
2209 finish_subregs_of_mode ();
2210 ira_free (regno_equiv_gains
);
2211 ira_free (regno_aclass
);
2212 ira_free (pref_buffer
);
2216 /* Entry function which defines register class, memory and hard
2217 register costs for each allocno. */
2222 cost_elements_num
= ira_allocnos_num
;
2224 total_allocno_costs
= (struct costs
*) ira_allocate (max_struct_costs_size
2225 * ira_allocnos_num
);
2226 initiate_regno_cost_classes ();
2227 calculate_elim_costs_all_insns ();
2228 find_costs_and_classes (ira_dump_file
);
2229 setup_allocno_class_and_costs ();
2230 finish_regno_cost_classes ();
2232 ira_free (total_allocno_costs
);
2235 /* Entry function which defines classes for pseudos.
2236 Set pseudo_classes_defined_p only if DEFINE_PSEUDO_CLASSES is true. */
2238 ira_set_pseudo_classes (bool define_pseudo_classes
, FILE *dump_file
)
2241 internal_flag_ira_verbose
= flag_ira_verbose
;
2242 cost_elements_num
= max_reg_num ();
2244 initiate_regno_cost_classes ();
2245 find_costs_and_classes (dump_file
);
2246 finish_regno_cost_classes ();
2247 if (define_pseudo_classes
)
2248 pseudo_classes_defined_p
= true;
2255 /* Change hard register costs for allocnos which lives through
2256 function calls. This is called only when we found all intersected
2257 calls during building allocno live ranges. */
2259 ira_tune_allocno_costs (void)
2262 int cost
, min_cost
, *reg_costs
;
2263 enum reg_class aclass
, rclass
;
2266 ira_allocno_iterator ai
;
2267 ira_allocno_object_iterator oi
;
2270 HARD_REG_SET
*crossed_calls_clobber_regs
;
2272 FOR_EACH_ALLOCNO (a
, ai
)
2274 aclass
= ALLOCNO_CLASS (a
);
2275 if (aclass
== NO_REGS
)
2277 mode
= ALLOCNO_MODE (a
);
2278 n
= ira_class_hard_regs_num
[aclass
];
2280 if (ALLOCNO_CALLS_CROSSED_NUM (a
)
2281 != ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
))
2283 ira_allocate_and_set_costs
2284 (&ALLOCNO_HARD_REG_COSTS (a
), aclass
,
2285 ALLOCNO_CLASS_COST (a
));
2286 reg_costs
= ALLOCNO_HARD_REG_COSTS (a
);
2287 for (j
= n
- 1; j
>= 0; j
--)
2289 regno
= ira_class_hard_regs
[aclass
][j
];
2291 FOR_EACH_ALLOCNO_OBJECT (a
, obj
, oi
)
2293 if (ira_hard_reg_set_intersection_p (regno
, mode
,
2294 OBJECT_CONFLICT_HARD_REGS
2303 rclass
= REGNO_REG_CLASS (regno
);
2305 crossed_calls_clobber_regs
2306 = &(ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a
));
2307 if (ira_hard_reg_set_intersection_p (regno
, mode
,
2308 *crossed_calls_clobber_regs
)
2309 && (ira_hard_reg_set_intersection_p (regno
, mode
,
2311 || HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
2312 cost
+= (ALLOCNO_CALL_FREQ (a
)
2313 * (ira_memory_move_cost
[mode
][rclass
][0]
2314 + ira_memory_move_cost
[mode
][rclass
][1]));
2315 #ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER
2316 cost
+= ((ira_memory_move_cost
[mode
][rclass
][0]
2317 + ira_memory_move_cost
[mode
][rclass
][1])
2319 * IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno
) / 2);
2321 if (INT_MAX
- cost
< reg_costs
[j
])
2322 reg_costs
[j
] = INT_MAX
;
2324 reg_costs
[j
] += cost
;
2325 if (min_cost
> reg_costs
[j
])
2326 min_cost
= reg_costs
[j
];
2329 if (min_cost
!= INT_MAX
)
2330 ALLOCNO_CLASS_COST (a
) = min_cost
;
2332 /* Some targets allow pseudos to be allocated to unaligned sequences
2333 of hard registers. However, selecting an unaligned sequence can
2334 unnecessarily restrict later allocations. So increase the cost of
2335 unaligned hard regs to encourage the use of aligned hard regs. */
2337 const int nregs
= ira_reg_class_max_nregs
[aclass
][ALLOCNO_MODE (a
)];
2341 ira_allocate_and_set_costs
2342 (&ALLOCNO_HARD_REG_COSTS (a
), aclass
, ALLOCNO_CLASS_COST (a
));
2343 reg_costs
= ALLOCNO_HARD_REG_COSTS (a
);
2344 for (j
= n
- 1; j
>= 0; j
--)
2346 regno
= ira_non_ordered_class_hard_regs
[aclass
][j
];
2347 if ((regno
% nregs
) != 0)
2349 int index
= ira_class_hard_reg_index
[aclass
][regno
];
2350 ira_assert (index
!= -1);
2351 reg_costs
[index
] += ALLOCNO_FREQ (a
);
2359 /* Add COST to the estimated gain for eliminating REGNO with its
2360 equivalence. If COST is zero, record that no such elimination is
2364 ira_adjust_equiv_reg_cost (unsigned regno
, int cost
)
2367 regno_equiv_gains
[regno
] = 0;
2369 regno_equiv_gains
[regno
] += cost
;
2373 ira_costs_c_finalize (void)
2375 this_target_ira_int
->free_ira_costs ();