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Turn FUNCTION_ARG_PADDING into a target hook
[official-gcc.git] / gcc / config / c6x / c6x.h
blobd0b98f8ce8c3638882d7af93007c3f8f02c287a9
1 /* Target Definitions for TI C6X.
2 Copyright (C) 2010-2017 Free Software Foundation, Inc.
3 Contributed by Andrew Jenner <andrew@codesourcery.com>
4 Contributed by Bernd Schmidt <bernds@codesourcery.com>
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 3, or (at your
11 option) any later version.
12
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #ifndef GCC_C6X_H
23 #define GCC_C6X_H
24
25 /* Feature bit definitions that enable specific insns. */
26 #define C6X_INSNS_C62X 1
27 #define C6X_INSNS_C64X 2
28 #define C6X_INSNS_C64XP 4
29 #define C6X_INSNS_C67X 8
30 #define C6X_INSNS_C67XP 16
31 #define C6X_INSNS_C674X 32
32 #define C6X_INSNS_ATOMIC 64
33 #define C6X_INSNS_ALL_CPU_BITS 127
34
35 #define C6X_DEFAULT_INSN_MASK \
36 (C6X_INSNS_C62X | C6X_INSNS_C64X | C6X_INSNS_C64XP)
37
38 /* A mask of allowed insn types, as defined above. */
39 extern unsigned long c6x_insn_mask;
40
41 /* Value of -march= */
42 extern c6x_cpu_t c6x_arch;
43 #define C6X_DEFAULT_ARCH C6X_CPU_C64XP
44
45 /* True if the target has C64x instructions. */
46 #define TARGET_INSNS_64 ((c6x_insn_mask & C6X_INSNS_C64X) != 0)
47 /* True if the target has C64x+ instructions. */
48 #define TARGET_INSNS_64PLUS ((c6x_insn_mask & C6X_INSNS_C64XP) != 0)
49 /* True if the target has C67x instructions. */
50 #define TARGET_INSNS_67 ((c6x_insn_mask & C6X_INSNS_C67X) != 0)
51 /* True if the target has C67x+ instructions. */
52 #define TARGET_INSNS_67PLUS ((c6x_insn_mask & C6X_INSNS_C67XP) != 0)
53
54 /* True if the target supports doubleword loads. */
55 #define TARGET_LDDW (TARGET_INSNS_64 || TARGET_INSNS_67)
56 /* True if the target supports doubleword loads. */
57 #define TARGET_STDW TARGET_INSNS_64
58 /* True if the target supports the MPY32 family of instructions. */
59 #define TARGET_MPY32 TARGET_INSNS_64PLUS
60 /* True if the target has floating point hardware. */
61 #define TARGET_FP TARGET_INSNS_67
62 /* True if the target has C67x+ floating point extensions. */
63 #define TARGET_FP_EXT TARGET_INSNS_67PLUS
64
65 #define TARGET_DEFAULT 0
66
67 /* Run-time Target. */
68
69 #define TARGET_CPU_CPP_BUILTINS() \
70 do \
71 { \
72 builtin_assert ("machine=tic6x"); \
73 builtin_assert ("cpu=tic6x"); \
74 builtin_define ("__TMS320C6X__"); \
75 builtin_define ("_TMS320C6X"); \
76 \
77 if (TARGET_DSBT) \
78 builtin_define ("__DSBT__"); \
79 \
80 if (TARGET_BIG_ENDIAN) \
81 builtin_define ("_BIG_ENDIAN"); \
82 else \
83 builtin_define ("_LITTLE_ENDIAN"); \
84 \
85 switch (c6x_arch) \
86 { \
87 case unk_isa: \
88 break; \
89 case C6X_CPU_C62X: \
90 builtin_define ("_TMS320C6200"); \
91 break; \
92 \
93 case C6X_CPU_C64XP: \
94 builtin_define ("_TMS320C6400_PLUS"); \
95 /* fall through */ \
96 case C6X_CPU_C64X: \
97 builtin_define ("_TMS320C6400"); \
98 break; \
99 \
100 case C6X_CPU_C67XP: \
101 builtin_define ("_TMS320C6700_PLUS"); \
102 /* fall through */ \
103 case C6X_CPU_C67X: \
104 builtin_define ("_TMS320C6700"); \
105 break; \
106 \
107 case C6X_CPU_C674X: \
108 builtin_define ("_TMS320C6740"); \
109 builtin_define ("_TMS320C6700_PLUS"); \
110 builtin_define ("_TMS320C6700"); \
111 builtin_define ("_TMS320C6400_PLUS"); \
112 builtin_define ("_TMS320C6400"); \
113 break; \
114 } \
115 } while (0)
116
117 #define OPTION_DEFAULT_SPECS \
118 {"arch", "%{!march=*:-march=%(VALUE)}" }
119
120 /* Storage Layout. */
121
122 #define BITS_BIG_ENDIAN 0
123 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
124 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
125
126 #define REG_WORDS_BIG_ENDIAN 0
127
128 #define UNITS_PER_WORD 4
129 #define PARM_BOUNDARY 8
130 #define STACK_BOUNDARY 64
131 #define FUNCTION_BOUNDARY 32
132 #define BIGGEST_ALIGNMENT 64
133 #define STRICT_ALIGNMENT 1
134
135 /* The ABI requires static arrays must be at least 8 byte aligned.
136 Really only externally visible arrays must be aligned this way, as
137 only those are directly visible from another compilation unit. But
138 we don't have that information available here. */
139 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
140 (((ALIGN) < BITS_PER_UNIT * 8 && TREE_CODE (TYPE) == ARRAY_TYPE) \
141 ? BITS_PER_UNIT * 8 : (ALIGN))
142
143 /* Type Layout. */
144
145 #define DEFAULT_SIGNED_CHAR 1
146
147 #undef SIZE_TYPE
148 #define SIZE_TYPE "unsigned int"
149 #undef PTRDIFF_TYPE
150 #define PTRDIFF_TYPE "int"
151
152 /* Registers. */
153
154 #define FIRST_PSEUDO_REGISTER 67
155 #define FIXED_REGISTERS \
156 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
157 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
158 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
159 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
160 1, 1, 1}
161 #define CALL_USED_REGISTERS \
162 { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
163 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
164 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, \
165 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
166 1, 1, 1}
167
168 /* This lists call-used non-predicate registers first, followed by call-used
169 registers, followed by predicate registers. We want to avoid allocating
170 the predicate registers for other uses as much as possible. */
171 #define REG_ALLOC_ORDER \
172 { \
173 REG_A0, REG_A3, REG_A4, REG_A5, REG_A6, REG_A7, REG_A8, REG_A9, \
174 REG_A16, REG_A17, REG_A18, REG_A19, REG_A20, REG_A21, REG_A22, REG_A23, \
175 REG_A24, REG_A25, REG_A26, REG_A27, REG_A28, REG_A29, REG_A30, REG_A31, \
176 REG_B4, REG_B5, REG_B6, REG_B7, REG_B8, REG_B9, REG_B16, \
177 REG_B17, REG_B18, REG_B19, REG_B20, REG_B21, REG_B22, REG_B23, REG_B24, \
178 REG_B25, REG_B26, REG_B27, REG_B28, REG_B29, REG_B30, REG_B31, \
179 REG_A10, REG_A11, REG_A12, REG_A13, REG_A14, REG_A15, \
180 REG_B3, REG_B10, REG_B11, REG_B12, REG_B13, REG_B14, REG_B15, \
181 REG_A1, REG_A2, REG_B0, REG_B1, REG_B2, REG_ILC \
182 }
183
184 #define HARD_REGNO_NREGS(regno, mode) \
185 ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) \
186 / UNITS_PER_WORD)
187
188
189 /* Register Classes. */
190
191 enum reg_class
192 {
193 NO_REGS,
194 PREDICATE_A_REGS,
195 PREDICATE_B_REGS,
196 PREDICATE_REGS,
197 PICREG,
198 SPREG,
199 CALL_USED_B_REGS,
200 NONPREDICATE_A_REGS,
201 NONPREDICATE_B_REGS,
202 NONPREDICATE_REGS,
203 A_REGS,
204 B_REGS,
205 GENERAL_REGS,
206 ALL_REGS,
207 LIM_REG_CLASSES
208 };
209
210 #define N_REG_CLASSES (int) LIM_REG_CLASSES
211
212 #define REG_CLASS_NAMES { \
213 "NO_REGS", \
214 "PREDICATE_A_REGS", \
215 "PREDICATE_B_REGS", \
216 "PREDICATE_REGS", \
217 "PICREG", \
218 "SPREG", \
219 "CALL_USED_B_REGS", \
220 "NONPREDICATE_A_REGS", \
221 "NONPREDICATE_B_REGS", \
222 "NONPREDICATE_REGS", \
223 "A_REGS", \
224 "B_REGS", \
225 "GENERAL_REGS", \
226 "ALL_REGS" }
227
228 #define REG_CLASS_CONTENTS \
229 { \
230 /* NO_REGS. */ \
231 { 0x00000000, 0x00000000, 0 }, \
232 /* PREDICATE_A_REGS. */ \
233 { 0x00000006, 0x00000000, 0 }, \
234 /* PREDICATE_B_REGS. */ \
235 { 0x00000000, 0x00000007, 0 }, \
236 /* PREDICATE_REGS. */ \
237 { 0x00000006, 0x00000007, 0 }, \
238 /* PICREG. */ \
239 { 0x00000000, 0x00004000, 0 }, \
240 /* SPREG. */ \
241 { 0x00000000, 0x00008000, 0 }, \
242 /* CALL_USED_B_REGS. */ \
243 { 0x00000000, 0xFFFF03FF, 0 }, \
244 /* NONPREDICATE_A_REGS. */ \
245 { 0xFFFFFFF9, 0x00000000, 0 }, \
246 /* NONPREDICATE_B_REGS. */ \
247 { 0x00000000, 0xFFFFFFF8, 0 }, \
248 /* NONPREDICATE_REGS. */ \
249 { 0xFFFFFFF9, 0xFFFFFFF8, 0 }, \
250 /* A_REGS. */ \
251 { 0xFFFFFFFF, 0x00000000, 3 }, \
252 /* B_REGS. */ \
253 { 0x00000000, 0xFFFFFFFF, 3 }, \
254 /* GENERAL_REGS. */ \
255 { 0xFFFFFFFF, 0xFFFFFFFF, 3 }, \
256 /* ALL_REGS. */ \
257 { 0xFFFFFFFF, 0xFFFFFFFF, 7 }, \
258 }
259
260 #define A_REGNO_P(N) ((N) <= REG_A31)
261 #define B_REGNO_P(N) ((N) >= REG_B0 && (N) <= REG_B31)
262
263 #define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X)))
264 #define CROSS_OPERANDS(X0,X1) \
265 (A_REG_P (X0) == A_REG_P (X1) ? CROSS_N : CROSS_Y)
266
267 #define REGNO_REG_CLASS(reg) \
268 ((reg) >= REG_A1 && (reg) <= REG_A2 ? PREDICATE_A_REGS \
269 : (reg) == REG_A0 && TARGET_INSNS_64 ? PREDICATE_A_REGS \
270 : (reg) >= REG_B0 && (reg) <= REG_B2 ? PREDICATE_B_REGS \
271 : A_REGNO_P (reg) ? NONPREDICATE_A_REGS \
272 : call_used_regs[reg] ? CALL_USED_B_REGS : B_REGS)
273
274 #define BASE_REG_CLASS ALL_REGS
275 #define INDEX_REG_CLASS ALL_REGS
276
277 #define REGNO_OK_FOR_BASE_STRICT_P(X) \
278 ((X) < FIRST_PSEUDO_REGISTER \
279 || (reg_renumber[X] >= 0 && reg_renumber[X] < FIRST_PSEUDO_REGISTER))
280 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X) 1
281
282 #define REGNO_OK_FOR_INDEX_STRICT_P(X) \
283 ((X) < FIRST_PSEUDO_REGISTER \
284 || (reg_renumber[X] >= 0 && reg_renumber[X] < FIRST_PSEUDO_REGISTER))
285 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(X) 1
286
287 #ifdef REG_OK_STRICT
288 #define REGNO_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_STRICT_P (X)
289 #define REGNO_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_STRICT_P (X)
290 #else
291 #define REGNO_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_NONSTRICT_P (X)
292 #define REGNO_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_NONSTRICT_P (X)
293 #endif
294
295 #define CLASS_MAX_NREGS(class, mode) \
296 ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
297
298 #define REGNO_OK_FOR_INDIRECT_JUMP_P(REGNO, MODE) B_REGNO_P (REGNO)
299
300 /* Stack and Calling. */
301
302 /* SP points to 4 bytes below the first word of the frame. */
303 #define STACK_POINTER_OFFSET 4
304 /* Likewise for AP (which is the incoming stack pointer). */
305 #define FIRST_PARM_OFFSET(fundecl) 4
306 #define STARTING_FRAME_OFFSET 0
307 #define FRAME_GROWS_DOWNWARD 1
308 #define STACK_GROWS_DOWNWARD 1
309
310 #define STACK_POINTER_REGNUM REG_B15
311 #define HARD_FRAME_POINTER_REGNUM REG_A15
312 /* These two always get eliminated in favour of the stack pointer
313 or the hard frame pointer. */
314 #define FRAME_POINTER_REGNUM REG_FRAME
315 #define ARG_POINTER_REGNUM REG_ARGP
316
317 #define PIC_OFFSET_TABLE_REGNUM REG_B14
318
319 /* We keep the stack pointer constant rather than using push/pop
320 instructions. */
321 #define ACCUMULATE_OUTGOING_ARGS 1
322
323 /* Before the prologue, the return address is in the B3 register. */
324 #define RETURN_ADDR_REGNO REG_B3
325 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNO)
326 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (RETURN_ADDR_REGNO)
327
328 #define RETURN_ADDR_RTX(COUNT, FRAME) c6x_return_addr_rtx (COUNT)
329
330 #define INCOMING_FRAME_SP_OFFSET 0
331 #define ARG_POINTER_CFA_OFFSET(fundecl) 0
332
333 #define STATIC_CHAIN_REGNUM REG_A2
334
335 struct c6x_args {
336 /* Number of arguments to pass in registers. */
337 int nregs;
338 /* Number of arguments passed in registers so far. */
339 int count;
340 };
341
342 #define CUMULATIVE_ARGS struct c6x_args
343
344 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
345 c6x_init_cumulative_args (&cum, fntype, libname, n_named_args)
346
347 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
348 (c6x_block_reg_pad_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD)
349
350 #define FUNCTION_ARG_REGNO_P(r) \
351 (((r) >= REG_A4 && (r) <= REG_A13) || ((r) >= REG_B4 && (r) <= REG_B13))
352
353 #define DEFAULT_PCC_STRUCT_RETURN 0
354
355 #define FUNCTION_PROFILER(file, labelno) \
356 fatal_error (input_location, \
357 "profiling is not yet implemented for this architecture")
358
359
360 /* Trampolines. */
361 #define TRAMPOLINE_SIZE 32
362 #define TRAMPOLINE_ALIGNMENT 256
363 \f
364 #define ELIMINABLE_REGS \
365 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
366 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
367 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
368 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
369
370 /* Define the offset between two registers, one to be eliminated, and the other
371 its replacement, at the start of a routine. */
372
373 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
374 ((OFFSET) = c6x_initial_elimination_offset ((FROM), (TO)))
375 \f
376 /* Addressing Modes. */
377
378 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P(x) && GET_CODE(x) != CONST_DOUBLE)
379 #define MAX_REGS_PER_ADDRESS 2
380
381 #define HAVE_PRE_DECREMENT 1
382 #define HAVE_POST_DECREMENT 1
383 #define HAVE_PRE_INCREMENT 1
384 #define HAVE_POST_INCREMENT 1
385
386 /* Register forms are available, but due to scaling we currently don't
387 support them. */
388 #define HAVE_PRE_MODIFY_DISP 1
389 #define HAVE_POST_MODIFY_DISP 1
390
391 #define LEGITIMATE_PIC_OPERAND_P(X) \
392 (!symbolic_operand (X, SImode))
393 \f
394 struct GTY(()) machine_function
395 {
396 /* True if we expanded a sibling call. */
397 int contains_sibcall;
398 };
399 \f
400 /* Costs. */
401 #define NO_FUNCTION_CSE 1
402
403 #define SLOW_BYTE_ACCESS 0
404
405 #define BRANCH_COST(speed_p, predictable_p) 6
406
407 \f
408 /* Model costs for the vectorizer. */
409
410 /* Cost of conditional branch. */
411 #ifndef TARG_COND_BRANCH_COST
412 #define TARG_COND_BRANCH_COST 6
413 #endif
414
415 /* Cost of any scalar operation, excluding load and store. */
416 #ifndef TARG_SCALAR_STMT_COST
417 #define TARG_SCALAR_STMT_COST 1
418 #endif
419
420 /* Cost of scalar load. */
421 #undef TARG_SCALAR_LOAD_COST
422 #define TARG_SCALAR_LOAD_COST 2 /* load + rotate */
423
424 /* Cost of scalar store. */
425 #undef TARG_SCALAR_STORE_COST
426 #define TARG_SCALAR_STORE_COST 10
427
428 /* Cost of any vector operation, excluding load, store,
429 or vector to scalar operation. */
430 #undef TARG_VEC_STMT_COST
431 #define TARG_VEC_STMT_COST 1
432
433 /* Cost of vector to scalar operation. */
434 #undef TARG_VEC_TO_SCALAR_COST
435 #define TARG_VEC_TO_SCALAR_COST 1
436
437 /* Cost of scalar to vector operation. */
438 #undef TARG_SCALAR_TO_VEC_COST
439 #define TARG_SCALAR_TO_VEC_COST 1
440
441 /* Cost of aligned vector load. */
442 #undef TARG_VEC_LOAD_COST
443 #define TARG_VEC_LOAD_COST 1
444
445 /* Cost of misaligned vector load. */
446 #undef TARG_VEC_UNALIGNED_LOAD_COST
447 #define TARG_VEC_UNALIGNED_LOAD_COST 2
448
449 /* Cost of vector store. */
450 #undef TARG_VEC_STORE_COST
451 #define TARG_VEC_STORE_COST 1
452
453 /* Cost of vector permutation. */
454 #ifndef TARG_VEC_PERMUTE_COST
455 #define TARG_VEC_PERMUTE_COST 1
456 #endif
457
458 /* ttype entries (the only interesting data references used) are
459 sb-relative got-indirect (aka .ehtype). */
460 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \
461 (((code) == 0 && (data) == 1) ? (DW_EH_PE_datarel | DW_EH_PE_indirect) \
462 : DW_EH_PE_absptr)
463
464 /* This should be the same as the definition in elfos.h, plus the call
465 to output special unwinding directives. */
466 #undef ASM_DECLARE_FUNCTION_NAME
467 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
468 do \
469 { \
470 c6x_output_file_unwind (FILE); \
471 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "function"); \
472 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
473 ASM_OUTPUT_LABEL (FILE, NAME); \
474 } \
475 while (0)
476
477 /* This should be the same as the definition in elfos.h, plus the call
478 to output special unwinding directives. */
479 #undef ASM_DECLARE_FUNCTION_SIZE
480 #define ASM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
481 c6x_function_end (STREAM, NAME)
482
483 /* Arbitrarily choose A4/A5. */
484 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N) + 4 : INVALID_REGNUM)
485
486 /* The register that holds the return address in exception handlers. */
487 #define C6X_EH_STACKADJ_REGNUM 3
488 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, C6X_EH_STACKADJ_REGNUM)
489
490
491 /* Assembler Format. */
492
493 #define DWARF2_ASM_LINE_DEBUG_INFO 1
494
495 #undef ASM_APP_ON
496 #define ASM_APP_ON "\t; #APP \n"
497 #undef ASM_APP_OFF
498 #define ASM_APP_OFF "\t; #NO_APP \n"
499
500 #define ASM_OUTPUT_COMMON(stream, name, size, rounded)
501 #define ASM_OUTPUT_LOCAL(stream, name, size, rounded)
502
503 #define GLOBAL_ASM_OP "\t.global\t"
504
505 #define REGISTER_NAMES \
506 { \
507 "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", \
508 "A8", "A9", "A10", "A11", "A12", "A13", "A14", "A15", \
509 "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23", \
510 "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31", \
511 "B0", "B1", "B2", "B3", "B4", "B5", "B6", "B7", \
512 "B8", "B9", "B10", "B11", "B12", "B13", "B14", "B15", \
513 "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23", \
514 "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31", \
515 "FP", "ARGP", "ILC" }
516
517 #define DBX_REGISTER_NUMBER(N) (dbx_register_map[(N)])
518
519 extern unsigned const dbx_register_map[FIRST_PSEUDO_REGISTER];
520
521 #define FINAL_PRESCAN_INSN c6x_final_prescan_insn
522
523 #define TEXT_SECTION_ASM_OP ".text;"
524 #define DATA_SECTION_ASM_OP ".data;"
525
526 #define ASM_OUTPUT_ALIGN(stream, power) \
527 do \
528 { \
529 if (power) \
530 fprintf ((stream), "\t.align\t%d\n", power); \
531 } \
532 while (0)
533
534 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
535 do { char __buf[256]; \
536 fprintf (FILE, "\t.long\t"); \
537 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
538 assemble_name (FILE, __buf); \
539 fputc ('\n', FILE); \
540 } while (0)
541
542 /* Determine whether to place EXP (an expression or a decl) should be
543 placed into one of the small data sections. */
544 #define PLACE_IN_SDATA_P(EXP) \
545 (c6x_sdata_mode == C6X_SDATA_NONE ? false \
546 : c6x_sdata_mode == C6X_SDATA_ALL ? true \
547 : !AGGREGATE_TYPE_P (TREE_TYPE (EXP)))
548
549 #define SCOMMON_ASM_OP "\t.scomm\t"
550
551 #undef ASM_OUTPUT_ALIGNED_DECL_COMMON
552 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(FILE, DECL, NAME, SIZE, ALIGN) \
553 do \
554 { \
555 if (DECL != NULL && PLACE_IN_SDATA_P (DECL)) \
556 fprintf ((FILE), "%s", SCOMMON_ASM_OP); \
557 else \
558 fprintf ((FILE), "%s", COMMON_ASM_OP); \
559 assemble_name ((FILE), (NAME)); \
560 fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\
561 } \
562 while (0)
563
564 /* This says how to output assembler code to declare an
565 uninitialized internal linkage data object. */
566
567 #undef ASM_OUTPUT_ALIGNED_DECL_LOCAL
568 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(FILE, DECL, NAME, SIZE, ALIGN) \
569 do { \
570 if (PLACE_IN_SDATA_P (DECL)) \
571 switch_to_section (sbss_section); \
572 else \
573 switch_to_section (bss_section); \
574 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \
575 if (!flag_inhibit_size_directive) \
576 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
577 ASM_OUTPUT_ALIGN ((FILE), exact_log2((ALIGN) / BITS_PER_UNIT)); \
578 ASM_OUTPUT_LABEL(FILE, NAME); \
579 ASM_OUTPUT_SKIP((FILE), (SIZE) ? (SIZE) : 1); \
580 } while (0)
581
582 #define CASE_VECTOR_PC_RELATIVE flag_pic
583 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
584
585 #define ADDR_VEC_ALIGN(VEC) (JUMP_TABLES_IN_TEXT_SECTION ? 5 : 2)
586
587 /* This is how to output an element of a case-vector that is relative. */
588 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
589 do { char buf[100]; \
590 fputs ("\t.long ", FILE); \
591 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
592 assemble_name (FILE, buf); \
593 putc ('-', FILE); \
594 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
595 assemble_name (FILE, buf); \
596 putc ('\n', FILE); \
597 } while (0)
598
599 /* Misc. */
600
601 #define CASE_VECTOR_MODE SImode
602 #define MOVE_MAX 4
603 #define MOVE_RATIO(SPEED) 4
604 #define TRULY_NOOP_TRUNCATION(outprec, inprec) 1
605 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
606 #define Pmode SImode
607 #define FUNCTION_MODE QImode
608
609 #define CPU_UNITS_QUERY 1
610
611 extern int c6x_initial_flag_pic;
612
613 #endif /* GCC_C6X_H */
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