| blob | 65a8df1a1ff47952a2047d78957e445b4f18b7df |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #define INCLUDE_STRING
71 /* This file should be included last. */
74 /* Defined for convenience. */
75 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
77 /* Classifies an address.
79 ADDRESS_REG_IMM
80 A simple base register plus immediate offset.
82 ADDRESS_REG_WB
83 A base register indexed by immediate offset with writeback.
85 ADDRESS_REG_REG
86 A base register indexed by (optionally scaled) register.
88 ADDRESS_REG_UXTW
89 A base register indexed by (optionally scaled) zero-extended register.
91 ADDRESS_REG_SXTW
92 A base register indexed by (optionally scaled) sign-extended register.
94 ADDRESS_LO_SUM
95 A LO_SUM rtx with a base register and "LO12" symbol relocation.
97 ADDRESS_SYMBOLIC:
98 A constant symbolic address, in pc-relative literal pool. */
101 ADDRESS_REG_IMM,
102 ADDRESS_REG_WB,
103 ADDRESS_REG_REG,
104 ADDRESS_REG_UXTW,
105 ADDRESS_REG_SXTW,
106 ADDRESS_LO_SUM,
107 ADDRESS_SYMBOLIC
108 };
112 rtx base;
113 rtx offset;
116 };
118 struct simd_immediate_info
119 {
120 rtx value;
125 };
127 /* The current code model. */
130 #ifdef HAVE_AS_TLS
131 #undef TARGET_HAVE_TLS
132 #define TARGET_HAVE_TLS 1
133 #endif
137 const_tree,
148 const_tree type,
151 static machine_mode
154 /* Major revision number of the ARM Architecture implemented by the target. */
157 /* The processor for which instructions should be scheduled. */
160 /* Mask to specify which instruction scheduling options should be used. */
163 /* Global flag for PC relative loads. */
166 /* Support for command line parsing of boolean flags in the tuning
167 structures. */
168 struct aarch64_flag_desc
169 {
172 };
174 #define AARCH64_FUSION_PAIR(name, internal_name) \
175 { name, AARCH64_FUSE_##internal_name },
177 {
182 };
184 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
185 { name, AARCH64_EXTRA_TUNE_##internal_name },
187 {
192 };
194 /* Tuning parameters. */
197 {
198 {
203 },
210 };
213 {
214 {
219 },
226 };
229 {
230 {
235 },
242 };
245 {
246 {
251 },
258 };
261 {
263 /* Avoid the use of slow int<->fp moves for spilling by setting
264 their cost higher than memmov_cost. */
268 };
271 {
273 /* Avoid the use of slow int<->fp moves for spilling by setting
274 their cost higher than memmov_cost. */
278 };
281 {
283 /* Avoid the use of slow int<->fp moves for spilling by setting
284 their cost higher than memmov_cost. */
288 };
291 {
293 /* Avoid the use of slow int<->fp moves for spilling by setting
294 their cost higher than memmov_cost (actual, 4 and 9). */
298 };
301 {
306 };
309 {
311 /* Avoid the use of slow int<->fp moves for spilling by setting
312 their cost higher than memmov_cost. */
316 };
319 {
321 /* Avoid the use of int<->fp moves for spilling. */
325 };
328 {
330 /* Avoid the use of int<->fp moves for spilling. */
334 };
336 /* Generic costs for vector insn classes. */
338 {
354 };
356 /* ThunderX costs for vector insn classes. */
358 {
374 };
376 /* Generic costs for vector insn classes. */
378 {
394 };
397 {
413 };
415 /* Generic costs for vector insn classes. */
417 {
433 };
435 /* Costs for vector insn classes for Vulcan. */
437 {
453 };
455 /* Generic costs for branch instructions. */
457 {
460 };
462 /* Generic approximation modes. */
464 {
467 AARCH64_APPROX_NONE /* recip_sqrt */
468 };
470 /* Approximation modes for Exynos M1. */
472 {
475 AARCH64_APPROX_ALL /* recip_sqrt */
476 };
478 /* Approximation modes for X-Gene 1. */
480 {
483 AARCH64_APPROX_ALL /* recip_sqrt */
484 };
486 /* Generic prefetch settings (which disable prefetch). */
488 {
494 };
497 {
503 };
506 {
512 };
515 {
521 };
524 {
530 };
533 {
539 };
542 {
563 &generic_prefetch_tune
564 };
567 {
589 &generic_prefetch_tune
590 };
593 {
615 &generic_prefetch_tune
616 };
619 {
641 &generic_prefetch_tune
642 };
645 {
667 &generic_prefetch_tune
668 };
671 {
693 &generic_prefetch_tune
694 };
699 {
720 &exynosm1_prefetch_tune
721 };
724 {
745 &thunderxt88_prefetch_tune
746 };
749 {
769 (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW
771 &thunderx_prefetch_tune
772 };
775 {
796 &generic_prefetch_tune
797 };
800 {
822 &qdf24xx_prefetch_tune
823 };
826 {
848 &thunderx2t99_prefetch_tune
849 };
851 /* Support for fine-grained override of the tuning structures. */
852 struct aarch64_tuning_override_function
853 {
856 };
861 static const struct aarch64_tuning_override_function
862 aarch64_tuning_override_functions[] =
863 {
867 };
869 /* A processor implementing AArch64. */
870 struct processor
871 {
879 };
881 /* Architectures implementing AArch64. */
883 {
884 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
885 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
888 };
890 /* Processor cores implementing AArch64. */
892 {
893 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
894 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
895 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
896 FLAGS, &COSTS##_tunings},
901 };
904 /* Target specification. These are populated by the -march, -mtune, -mcpu
905 handling code or by target attributes. */
910 /* The current tuning set. */
913 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
915 /* An ISA extension in the co-processor and main instruction set space. */
916 struct aarch64_option_extension
917 {
921 };
924 {
928 }
929 aarch64_cc;
931 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
933 /* The condition codes of the processor, and the inverse function. */
935 {
938 };
940 /* Generate code to enable conditional branches in functions over 1 MiB. */
944 {
961 }
963 void
965 {
969 else
971 }
973 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
974 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
975 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
976 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
977 cost (in this case the best class is the lowest cost one). Using ALL_REGS
978 irrespectively of its cost results in bad allocations with many redundant
979 int<->FP moves which are expensive on various cores.
980 To avoid this we don't allow ALL_REGS as the allocno class, but force a
981 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
982 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
983 Otherwise set the allocno class depending on the mode.
984 The result of this is that it is no longer inefficient to have a higher
985 memory move cost than the register move cost.
986 */
988 static reg_class_t
990 reg_class_t best_class)
991 {
992 machine_mode mode;
1002 }
1004 static unsigned int
1006 {
1010 }
1012 static int
1014 machine_mode mode)
1015 {
1023 }
1025 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
1026 unsigned
1028 {
1036 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
1037 equivalent DWARF register. */
1039 }
1041 /* Return TRUE if MODE is any of the large INT modes. */
1042 static bool
1044 {
1046 }
1048 /* Return TRUE if MODE is any of the vector modes. */
1049 static bool
1051 {
1054 }
1056 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1057 static bool
1060 {
1068 }
1070 /* Implement HARD_REGNO_NREGS. */
1072 int
1074 {
1076 {
1082 }
1084 }
1086 /* Implement TARGET_HARD_REGNO_MODE_OK. */
1088 static bool
1090 {
1095 /* The purpose of comparing with ptr_mode is to support the
1096 global register variable associated with the stack pointer
1097 register via the syntax of asm ("wsp") in ILP32. */
1107 {
1109 return
1111 else
1113 }
1116 }
1118 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
1119 the lower 64 bits of a 128-bit register. Tell the compiler the callee
1120 clobbers the top 64 bits when restoring the bottom 64 bits. */
1122 static bool
1124 {
1126 }
1128 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1129 machine_mode
1131 machine_mode mode)
1132 {
1133 /* Handle modes that fit within single registers. */
1135 {
1138 else
1140 }
1141 /* Fall back to generic for multi-reg and very large modes. */
1142 else
1144 }
1146 /* Return true if calls to DECL should be treated as
1147 long-calls (ie called via a register). */
1148 static bool
1150 {
1152 }
1154 /* Return true if calls to symbol-ref SYM should be treated as
1155 long-calls (ie called via a register). */
1156 bool
1158 {
1160 }
1162 /* Return true if calls to symbol-ref SYM should not go through
1163 plt stubs. */
1165 bool
1167 {
1171 && decl
1172 && (!flag_plt
1178 }
1180 /* Return true if the offsets to a zero/sign-extract operation
1181 represent an expression that matches an extend operation. The
1182 operands represent the paramters from
1184 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1185 bool
1187 rtx extract_imm)
1188 {
1205 }
1207 /* Emit an insn that's a simple single-set. Both the operands must be
1208 known to be valid. */
1211 {
1213 }
1215 /* X and Y are two things to compare using CODE. Emit the compare insn and
1216 return the rtx for register 0 in the proper mode. */
1217 rtx
1219 {
1225 }
1227 /* Build the SYMBOL_REF for __tls_get_addr. */
1231 rtx
1233 {
1237 }
1239 /* Return the TLS model to use for ADDR. */
1241 static enum tls_model
1243 {
1248 {
1252 }
1257 }
1259 /* We'll allow lo_sum's in addresses in our legitimate addresses
1260 so that combine would take care of combining addresses where
1261 necessary, but for generation purposes, we'll generate the address
1262 as :
1263 RTL Absolute
1264 tmp = hi (symbol_ref); adrp x1, foo
1265 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1266 nop
1268 PIC TLS
1269 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1270 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1271 bl __tls_get_addr
1272 nop
1274 Load TLS symbol, depending on TLS mechanism and TLS access model.
1276 Global Dynamic - Traditional TLS:
1277 adrp tmp, :tlsgd:imm
1278 add dest, tmp, #:tlsgd_lo12:imm
1279 bl __tls_get_addr
1281 Global Dynamic - TLS Descriptors:
1282 adrp dest, :tlsdesc:imm
1283 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1284 add dest, dest, #:tlsdesc_lo12:imm
1285 blr tmp
1286 mrs tp, tpidr_el0
1287 add dest, dest, tp
1289 Initial Exec:
1290 mrs tp, tpidr_el0
1291 adrp tmp, :gottprel:imm
1292 ldr dest, [tmp, #:gottprel_lo12:imm]
1293 add dest, dest, tp
1295 Local Exec:
1296 mrs tp, tpidr_el0
1297 add t0, tp, #:tprel_hi12:imm, lsl #12
1298 add t0, t0, #:tprel_lo12_nc:imm
1299 */
1301 static void
1304 {
1306 {
1308 {
1309 /* In ILP32, the mode of dest can be either SImode or DImode. */
1321 }
1328 {
1331 rtx insn;
1332 rtx mem;
1334 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1335 here before rtl expand. Tree IVOPT will generate rtl pattern to
1336 decide rtx costs, in which case pic_offset_table_rtx is not
1337 initialized. For that case no need to generate the first adrp
1338 instruction as the final cost for global variable access is
1339 one instruction. */
1341 {
1342 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1343 using the page base as GOT base, the first page may be wasted,
1344 in the worst scenario, there is only 28K space for GOT).
1346 The generate instruction sequence for accessing global variable
1347 is:
1349 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1351 Only one instruction needed. But we must initialize
1352 pic_offset_table_rtx properly. We generate initialize insn for
1353 every global access, and allow CSE to remove all redundant.
1355 The final instruction sequences will look like the following
1356 for multiply global variables access.
1358 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1360 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1361 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1362 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1363 ... */
1372 }
1375 {
1378 else
1382 }
1383 else
1384 {
1389 }
1391 /* The operand is expected to be MEM. Whenever the related insn
1392 pattern changed, above code which calculate mem should be
1393 updated. */
1399 }
1402 {
1403 /* In ILP32, the mode of dest can be either SImode or DImode,
1404 while the got entry is always of SImode size. The mode of
1405 dest depends on how dest is used: if dest is assigned to a
1406 pointer (e.g. in the memory), it has SImode; it may have
1407 DImode if dest is dereferenced to access the memeory.
1408 This is why we have to handle three different ldr_got_small
1409 patterns here (two patterns for ILP32). */
1411 rtx insn;
1412 rtx mem;
1421 {
1424 else
1428 }
1429 else
1430 {
1435 }
1442 }
1445 {
1453 else
1461 }
1464 {
1467 rtx tp;
1471 /* In ILP32, the got entry is always of SImode size. Unlike
1472 small GOT, the dest is fixed at reg 0. */
1475 else
1485 }
1488 {
1489 /* In ILP32, the mode of dest can be either SImode or DImode,
1490 while the got entry is always of SImode size. The mode of
1491 dest depends on how dest is used: if dest is assigned to a
1492 pointer (e.g. in the memory), it has SImode; it may have
1493 DImode if dest is dereferenced to access the memeory.
1494 This is why we have to handle three different tlsie_small
1495 patterns here (two patterns for ILP32). */
1501 {
1504 else
1505 {
1508 }
1509 }
1510 else
1511 {
1514 }
1519 }
1525 {
1533 {
1556 }
1560 }
1567 {
1572 {
1575 else
1576 {
1579 }
1580 }
1581 else
1582 {
1585 }
1589 }
1593 }
1594 }
1596 /* Emit a move from SRC to DEST. Assume that the move expanders can
1597 handle all moves if !can_create_pseudo_p (). The distinction is
1598 important because, unlike emit_move_insn, the move expanders know
1599 how to force Pmode objects into the constant pool even when the
1600 constant pool address is not itself legitimate. */
1601 static rtx
1603 {
1607 }
1609 /* Split a 128-bit move operation into two 64-bit move operations,
1610 taking care to handle partial overlap of register to register
1611 copies. Special cases are needed when moving between GP regs and
1612 FP regs. SRC can be a register, constant or memory; DST a register
1613 or memory. If either operand is memory it must not have any side
1614 effects. */
1615 void
1617 {
1628 {
1632 /* Handle FP <-> GP regs. */
1634 {
1639 {
1642 }
1643 else
1644 {
1647 }
1649 }
1651 {
1656 {
1659 }
1660 else
1661 {
1664 }
1666 }
1667 }
1674 /* At most one pairing may overlap. */
1676 {
1679 }
1680 else
1681 {
1684 }
1685 }
1687 bool
1689 {
1692 }
1694 /* Split a complex SIMD combine. */
1696 void
1698 {
1710 {
1734 }
1738 }
1740 /* Split a complex SIMD move. */
1742 void
1744 {
1751 {
1757 {
1781 }
1785 }
1786 }
1788 bool
1791 {
1795 }
1798 static rtx
1800 {
1803 else
1804 {
1807 }
1808 }
1811 static rtx
1813 {
1815 {
1816 rtx high;
1817 /* Load the full offset into a register. This
1818 might be improvable in the future. */
1824 }
1826 }
1828 static int
1830 machine_mode mode)
1831 {
1840 {
1844 }
1846 /* Check to see if the low 32 bits are either 0xffffXXXX or 0xXXXXffff
1847 (with XXXX non-zero). In that case check to see if the move can be done in
1848 a smaller mode. */
1853 {
1857 /* Check if we have to emit a second instruction by checking to see
1858 if any of the upper 32 bits of the original DI mode value is set. */
1869 }
1872 {
1874 {
1879 else
1882 }
1884 }
1886 /* Remaining cases are all for DImode. */
1895 {
1896 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1897 For a 64-bit bitmask try whether changing 16 bits to all ones or
1898 zeroes creates a valid bitmask. To check any repeated bitmask,
1899 try using 16 bits from the other 32-bit half of val. */
1902 {
1913 }
1915 {
1917 {
1921 }
1923 }
1924 }
1926 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1927 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1928 otherwise skip zero bits. */
1940 {
1946 num_insns ++;
1947 }
1950 }
1953 void
1955 {
1960 /* Check on what type of symbol it is. */
1964 {
1968 /* If we have (const (plus symbol offset)), separate out the offset
1969 before we start classifying the symbol. */
1974 {
1978 {
1984 }
1989 /* If we aren't generating PC relative literals, then
1990 we need to expand the literal pool access carefully.
1991 This is something that needs to be done in a number
1992 of places, so could well live as a separate function. */
1994 {
2001 }
2018 {
2024 }
2025 /* FALLTHRU */
2038 }
2039 }
2042 {
2045 else
2046 {
2050 }
2053 }
2056 }
2058 /* Add DELTA to REGNUM in mode MODE. SCRATCHREG can be used to hold a
2059 temporary value if necessary. FRAME_RELATED_P should be true if
2060 the RTX_FRAME_RELATED flag should be set and CFA adjustments added
2061 to the generated instructions. If SCRATCHREG is known to hold
2062 abs (delta), EMIT_MOVE_IMM can be set to false to avoid emitting the
2063 immediate again.
2065 Since this function may be used to adjust the stack pointer, we must
2066 ensure that it cannot cause transient stack deallocation (for example
2067 by first incrementing SP and then decrementing when adjusting by a
2068 large immediate). */
2070 static void
2074 {
2082 /* Single instruction adjustment. */
2084 {
2088 }
2090 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits.
2091 Only do this if mdelta is not a 16-bit move as adjusting using a move
2092 is better. */
2094 {
2103 }
2105 /* Emit a move immediate if required and an addition/subtraction. */
2112 {
2116 }
2117 }
2121 HOST_WIDE_INT delta)
2122 {
2124 }
2128 {
2131 }
2135 {
2138 }
2140 static bool
2142 tree exp ATTRIBUTE_UNUSED)
2143 {
2144 /* Currently, always true. */
2146 }
2148 /* Implement TARGET_PASS_BY_REFERENCE. */
2150 static bool
2152 machine_mode mode,
2153 const_tree type,
2155 {
2156 HOST_WIDE_INT size;
2157 machine_mode dummymode;
2160 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
2164 /* Aggregates are passed by reference based on their size. */
2166 {
2168 }
2170 /* Variable sized arguments are always returned by reference. */
2174 /* Can this be a candidate to be passed in fp/simd register(s)? */
2177 NULL))
2180 /* Arguments which are variable sized or larger than 2 registers are
2181 passed by reference unless they are a homogenous floating point
2182 aggregate. */
2184 }
2186 /* Return TRUE if VALTYPE is padded to its least significant bits. */
2187 static bool
2189 {
2190 machine_mode dummy_mode;
2193 /* Never happens in little-endian mode. */
2197 /* Only composite types smaller than or equal to 16 bytes can
2198 be potentially returned in registers. */
2204 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
2205 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
2206 is always passed/returned in the least significant bits of fp/simd
2207 register(s). */
2213 }
2215 /* Implement TARGET_FUNCTION_VALUE.
2216 Define how to find the value returned by a function. */
2218 static rtx
2221 {
2222 machine_mode mode;
2225 machine_mode ag_mode;
2232 {
2236 {
2239 }
2240 }
2244 {
2246 {
2249 }
2250 else
2251 {
2253 rtx par;
2257 {
2262 }
2264 }
2265 }
2266 else
2268 }
2270 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
2271 Return true if REGNO is the number of a hard register in which the values
2272 of called function may come back. */
2274 static bool
2276 {
2277 /* Maximum of 16 bytes can be returned in the general registers. Examples
2278 of 16-byte return values are: 128-bit integers and 16-byte small
2279 structures (excluding homogeneous floating-point aggregates). */
2283 /* Up to four fp/simd registers can return a function value, e.g. a
2284 homogeneous floating-point aggregate having four members. */
2289 }
2291 /* Implement TARGET_RETURN_IN_MEMORY.
2293 If the type T of the result of a function is such that
2294 void func (T arg)
2295 would require that arg be passed as a value in a register (or set of
2296 registers) according to the parameter passing rules, then the result
2297 is returned in the same registers as would be used for such an
2298 argument. */
2300 static bool
2302 {
2303 HOST_WIDE_INT size;
2304 machine_mode ag_mode;
2310 /* Simple scalar types always returned in registers. */
2314 type,
2317 NULL))
2320 /* Types larger than 2 registers returned in memory. */
2323 }
2325 static bool
2328 {
2331 type,
2333 nregs,
2334 NULL);
2335 }
2337 /* Given MODE and TYPE of a function argument, return the alignment in
2338 bits. The idea is to suppress any stronger alignment requested by
2339 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
2340 This is a helper function for local use only. */
2342 static unsigned int
2344 {
2365 }
2367 /* Layout a function argument according to the AAPCS64 rules. The rule
2368 numbers refer to the rule numbers in the AAPCS64. */
2370 static void
2372 const_tree type,
2374 {
2378 HOST_WIDE_INT size;
2380 /* We need to do this once per argument. */
2386 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
2387 size
2389 UNITS_PER_WORD);
2393 mode,
2394 type,
2397 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
2398 The following code thus handles passing by SIMD/FP registers first. */
2402 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
2403 and homogenous short-vector aggregates (HVA). */
2405 {
2410 {
2413 {
2416 }
2417 else
2418 {
2419 rtx par;
2423 {
2426 tmp = gen_rtx_EXPR_LIST
2430 }
2432 }
2434 }
2435 else
2436 {
2437 /* C.3 NSRN is set to 8. */
2440 }
2441 }
2446 /* C6 - C9. though the sign and zero extension semantics are
2447 handled elsewhere. This is the case where the argument fits
2448 entirely general registers. */
2450 {
2454 /* C.8 if the argument has an alignment of 16 then the NGRN is
2455 rounded up to the next even number. */
2458 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
2459 comparison is there because for > 16 * BITS_PER_UNIT
2460 alignment nregs should be > 2 and therefore it should be
2461 passed by reference rather than value. */
2463 {
2466 }
2468 /* NREGS can be 0 when e.g. an empty structure is to be passed.
2469 A reg is still generated for it, but the caller should be smart
2470 enough not to use it. */
2473 else
2474 {
2475 rtx par;
2480 {
2485 }
2487 }
2491 }
2493 /* C.11 */
2496 /* The argument is passed on stack; record the needed number of words for
2497 this argument and align the total size if necessary. */
2498 on_stack:
2505 }
2507 /* Implement TARGET_FUNCTION_ARG. */
2509 static rtx
2512 {
2521 }
2523 void
2525 const_tree fntype ATTRIBUTE_UNUSED,
2526 rtx libname ATTRIBUTE_UNUSED,
2527 const_tree fndecl ATTRIBUTE_UNUSED,
2529 {
2543 {
2550 }
2552 }
2554 static void
2556 machine_mode mode,
2557 const_tree type,
2559 {
2562 {
2572 }
2573 }
2575 bool
2577 {
2580 }
2582 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2583 PARM_BOUNDARY bits of alignment, but will be given anything up
2584 to STACK_BOUNDARY bits if the type requires it. This makes sure
2585 that both before and after the layout of each argument, the Next
2586 Stacked Argument Address (NSAA) will have a minimum alignment of
2587 8 bytes. */
2589 static unsigned int
2591 {
2594 }
2596 /* Implement TARGET_FUNCTION_ARG_PADDING.
2598 Small aggregate types are placed in the lowest memory address.
2600 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2602 static pad_direction
2604 {
2605 /* On little-endian targets, the least significant byte of every stack
2606 argument is passed at the lowest byte address of the stack slot. */
2610 /* Otherwise, integral, floating-point and pointer types are padded downward:
2611 the least significant byte of a stack argument is passed at the highest
2612 byte address of the stack slot. */
2619 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2621 }
2623 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2625 It specifies padding for the last (may also be the only)
2626 element of a block move between registers and memory. If
2627 assuming the block is in the memory, padding upward means that
2628 the last element is padded after its highest significant byte,
2629 while in downward padding, the last element is padded at the
2630 its least significant byte side.
2632 Small aggregates and small complex types are always padded
2633 upwards.
2635 We don't need to worry about homogeneous floating-point or
2636 short-vector aggregates; their move is not affected by the
2637 padding direction determined here. Regardless of endianness,
2638 each element of such an aggregate is put in the least
2639 significant bits of a fp/simd register.
2641 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2642 register has useful data, and return the opposite if the most
2643 significant byte does. */
2645 bool
2648 {
2650 /* Small composite types are always padded upward. */
2652 {
2657 }
2659 /* Otherwise, use the default padding. */
2661 }
2663 static scalar_int_mode
2665 {
2667 }
2669 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
2671 /* We use the 12-bit shifted immediate arithmetic instructions so values
2672 must be multiple of (1 << 12), i.e. 4096. */
2673 #define ARITH_FACTOR 4096
2675 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
2676 #error Cannot use simple address calculation for stack probing
2677 #endif
2679 /* The pair of scratch registers used for stack probing. */
2680 #define PROBE_STACK_FIRST_REG 9
2681 #define PROBE_STACK_SECOND_REG 10
2683 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
2684 inclusive. These are offsets from the current stack pointer. */
2686 static void
2688 {
2691 /* See the same assertion on PROBE_INTERVAL above. */
2694 /* See if we have a constant small number of probes to generate. If so,
2695 that's the easy case. */
2697 {
2704 }
2706 /* The run-time loop is made up of 8 insns in the generic case while the
2707 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
2709 {
2714 stack_pointer_rtx,
2718 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
2719 it exceeds SIZE. If only two probes are needed, this will not
2720 generate any code. Then probe at FIRST + SIZE. */
2722 {
2726 }
2730 {
2735 }
2736 else
2738 }
2740 /* Otherwise, do the same as above, but in a loop. Note that we must be
2741 extra careful with variables wrapping around because we might be at
2742 the very top (or the very bottom) of the address space and we have
2743 to be able to handle this case properly; in particular, we use an
2744 equality test for the loop condition. */
2745 else
2746 {
2749 /* Step 1: round SIZE to the previous multiple of the interval. */
2754 /* Step 2: compute initial and final value of the loop counter. */
2756 /* TEST_ADDR = SP + FIRST. */
2760 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
2763 {
2767 }
2768 else
2769 {
2772 }
2774 /* Step 3: the loop
2776 do
2777 {
2778 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
2779 probe at TEST_ADDR
2780 }
2781 while (TEST_ADDR != LAST_ADDR)
2783 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
2784 until it is equal to ROUNDED_SIZE. */
2789 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
2790 that SIZE is equal to ROUNDED_SIZE. */
2793 {
2797 {
2802 }
2803 else
2805 }
2806 }
2808 /* Make sure nothing is scheduled before we are done. */
2810 }
2812 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
2813 absolute addresses. */
2817 {
2824 /* Loop. */
2827 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
2832 /* Probe at TEST_ADDR. */
2835 /* Test if TEST_ADDR == LAST_ADDR. */
2839 /* Branch. */
2845 }
2847 static bool
2849 {
2850 /* In aarch64_override_options_after_change
2851 flag_omit_leaf_frame_pointer turns off the frame pointer by
2852 default. Turn it back on now if we've not got a leaf
2853 function. */
2858 /* Force a frame pointer for EH returns so the return address is at FP+8. */
2863 }
2865 /* Mark the registers that need to be saved by the callee and calculate
2866 the size of the callee-saved registers area and frame record (both FP
2867 and LR may be omitted). */
2868 static void
2870 {
2877 #define SLOT_NOT_REQUIRED (-2)
2878 #define SLOT_REQUIRED (-1)
2883 /* First mark all the registers that really need to be saved... */
2890 /* ... that includes the eh data registers (if needed)... */
2896 /* ... and any callee saved register that dataflow says is live. */
2906 {
2909 }
2912 {
2913 /* FP and LR are placed in the linkage record. */
2919 }
2921 /* Now assign stack slots for them. */
2924 {
2931 }
2939 {
2940 /* If there is an alignment gap between integer and fp callee-saves,
2941 allocate the last fp register to it if possible. */
2943 {
2946 }
2955 }
2961 HOST_WIDE_INT varargs_and_saved_regs_size
2988 {
2989 /* Simple, small frame with no outgoing arguments:
2990 stp reg1, reg2, [sp, -frame_size]!
2991 stp reg3, reg4, [sp, 16] */
2993 }
2998 {
2999 /* Frame with small outgoing arguments:
3000 sub sp, sp, frame_size
3001 stp reg1, reg2, [sp, outgoing_args_size]
3002 stp reg3, reg4, [sp, outgoing_args_size + 16] */
3006 }
3008 {
3009 /* Frame with large outgoing arguments but a small local area:
3010 stp reg1, reg2, [sp, -hard_fp_offset]!
3011 stp reg3, reg4, [sp, 16]
3012 sub sp, sp, outgoing_args_size */
3016 }
3019 {
3020 /* Frame with large local area and outgoing arguments (this pushes the
3021 callee-saves first, followed by the locals and outgoing area):
3022 stp reg1, reg2, [sp, -varargs_and_saved_regs_size]!
3023 stp reg3, reg4, [sp, 16]
3024 sub sp, sp, frame_size - varargs_and_saved_regs_size */
3030 }
3031 else
3032 {
3033 /* Frame with large local area and outgoing arguments using frame pointer:
3034 sub sp, sp, hard_fp_offset
3035 stp x29, x30, [sp, 0]
3036 add x29, sp, 0
3037 stp reg3, reg4, [sp, 16]
3038 sub sp, sp, outgoing_args_size */
3042 }
3045 }
3047 /* Return true if the register REGNO is saved on entry to
3048 the current function. */
3050 static bool
3052 {
3054 }
3056 /* Return the next register up from REGNO up to LIMIT for the callee
3057 to save. */
3059 static unsigned
3061 {
3063 regno ++;
3065 }
3067 /* Push the register number REGNO of mode MODE to the stack with write-back
3068 adjusting the stack by ADJUSTMENT. */
3070 static void
3072 HOST_WIDE_INT adjustment)
3073 {
3084 }
3086 /* Generate and return an instruction to store the pair of registers
3087 REG and REG2 of mode MODE to location BASE with write-back adjusting
3088 the stack location BASE by ADJUSTMENT. */
3090 static rtx
3092 HOST_WIDE_INT adjustment)
3093 {
3095 {
3106 }
3107 }
3109 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
3110 stack pointer by ADJUSTMENT. */
3112 static void
3114 {
3129 }
3131 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
3132 adjusting it by ADJUSTMENT afterwards. */
3134 static rtx
3136 HOST_WIDE_INT adjustment)
3137 {
3139 {
3148 }
3149 }
3151 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
3152 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
3153 into CFI_OPS. */
3155 static void
3158 {
3165 {
3169 }
3170 else
3171 {
3176 }
3177 }
3179 /* Generate and return a store pair instruction of mode MODE to store
3180 register REG1 to MEM1 and register REG2 to MEM2. */
3182 static rtx
3184 rtx reg2)
3185 {
3187 {
3196 }
3197 }
3199 /* Generate and regurn a load pair isntruction of mode MODE to load register
3200 REG1 from MEM1 and register REG2 from MEM2. */
3202 static rtx
3204 rtx mem2)
3205 {
3207 {
3216 }
3217 }
3219 /* Return TRUE if return address signing should be enabled for the current
3220 function, otherwise return FALSE. */
3222 bool
3224 {
3225 /* This function should only be called after frame laid out. */
3228 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
3229 if it's LR is pushed onto stack. */
3233 }
3235 /* Emit code to save the callee-saved registers from register number START
3236 to LIMIT to the stack at the location starting at offset START_OFFSET,
3237 skipping any write-back candidates if SKIP_WB is true. */
3239 static void
3242 {
3250 {
3252 HOST_WIDE_INT offset;
3265 offset));
3274 {
3276 rtx mem2;
3280 offset));
3282 reg2));
3284 /* The first part of a frame-related parallel insn is
3285 always assumed to be relevant to the frame
3286 calculations; subsequent parts, are only
3287 frame-related if explicitly marked. */
3290 }
3291 else
3295 }
3296 }
3298 /* Emit code to restore the callee registers of mode MODE from register
3299 number START up to and including LIMIT. Restore from the stack offset
3300 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
3301 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
3303 static void
3307 {
3311 HOST_WIDE_INT offset;
3316 {
3337 {
3339 rtx mem2;
3347 }
3348 else
3351 }
3352 }
3356 HOST_WIDE_INT offset)
3357 {
3359 }
3363 {
3367 }
3369 bool
3371 {
3375 }
3377 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
3379 static sbitmap
3381 {
3387 /* The registers we need saved to the frame. */
3390 {
3395 /* Check that we can access the stack slot of the register with one
3396 direct load with no adjustments needed. */
3399 }
3401 /* Don't mess with the hard frame pointer. */
3407 /* If aarch64_layout_frame has chosen registers to store/restore with
3408 writeback don't interfere with them to avoid having to output explicit
3409 stack adjustment instructions. */
3419 }
3421 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
3423 static sbitmap
3425 {
3433 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
3442 }
3444 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
3445 Nothing to do for aarch64. */
3447 static void
3449 {
3450 }
3452 /* Return the next set bit in BMP from START onwards. Return the total number
3453 of bits in BMP if no set bit is found at or after START. */
3455 static unsigned int
3457 {
3468 }
3470 /* Do the work for aarch64_emit_prologue_components and
3471 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
3472 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
3473 for these components or the epilogue sequence. That is, it determines
3474 whether we should emit stores or loads and what kind of CFA notes to attach
3475 to the insns. Otherwise the logic for the two sequences is very
3476 similar. */
3478 static void
3480 {
3482 ? HARD_FRAME_POINTER_REGNUM
3490 {
3491 /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
3492 so DFmode for the vector registers is enough. */
3504 /* No more registers to handle after REGNO.
3505 Emit a single save/restore and exit. */
3507 {
3512 else
3515 }
3518 /* The next register is not of the same class or its offset is not
3519 mergeable with the current one into a pair. */
3524 {
3529 else
3534 }
3536 /* REGNO2 can be saved/restored in a pair with REGNO. */
3548 else
3553 {
3556 }
3557 else
3558 {
3561 }
3564 }
3565 }
3567 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
3569 static void
3571 {
3573 }
3575 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
3577 static void
3579 {
3581 }
3583 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
3585 static void
3587 {
3591 }
3593 /* AArch64 stack frames generated by this compiler look like:
3595 +-------------------------------+
3596 | |
3597 | incoming stack arguments |
3598 | |
3599 +-------------------------------+
3600 | | <-- incoming stack pointer (aligned)
3601 | callee-allocated save area |
3602 | for register varargs |
3603 | |
3604 +-------------------------------+
3605 | local variables | <-- frame_pointer_rtx
3606 | |
3607 +-------------------------------+
3608 | padding0 | \
3609 +-------------------------------+ |
3610 | callee-saved registers | | frame.saved_regs_size
3611 +-------------------------------+ |
3612 | LR' | |
3613 +-------------------------------+ |
3614 | FP' | / <- hard_frame_pointer_rtx (aligned)
3615 +-------------------------------+
3616 | dynamic allocation |
3617 +-------------------------------+
3618 | padding |
3619 +-------------------------------+
3620 | outgoing stack arguments | <-- arg_pointer
3621 | |
3622 +-------------------------------+
3623 | | <-- stack_pointer_rtx (aligned)
3625 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
3626 but leave frame_pointer_rtx and hard_frame_pointer_rtx
3627 unchanged. */
3629 /* Generate the prologue instructions for entry into a function.
3630 Establish the stack frame by decreasing the stack pointer with a
3631 properly calculated size and, if necessary, create a frame record
3632 filled with the values of LR and previous frame pointer. The
3633 current FP is also set up if it is in use. */
3635 void
3637 {
3649 /* Sign return address for functions. */
3651 {
3655 }
3661 {
3663 {
3667 }
3670 }
3678 {
3683 stack_pointer_rtx,
3687 }
3694 }
3696 /* Return TRUE if we can use a simple_return insn.
3698 This function checks whether the callee saved stack is empty, which
3699 means no restore actions are need. The pro_and_epilogue will use
3700 this to check whether shrink-wrapping opt is feasible. */
3702 bool
3704 {
3714 }
3716 /* Generate the epilogue instructions for returning from a function.
3717 This is almost exactly the reverse of the prolog sequence, except
3718 that we need to insert barriers to avoid scheduling loads that read
3719 from a deallocated stack, and we optimize the unwind records by
3720 emitting them all together if possible. */
3721 void
3723 {
3735 /* We need to add memory barrier to prevent read from deallocated stack. */
3739 /* Emit a barrier to prevent loads from a deallocated stack. */
3742 {
3745 }
3747 /* Restore the stack pointer from the frame pointer if it may not
3748 be the same as the stack pointer. */
3750 {
3752 hard_frame_pointer_rtx,
3754 /* If writeback is used when restoring callee-saves, the CFA
3755 is restored on the instruction doing the writeback. */
3757 }
3758 else
3773 {
3774 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
3780 }
3785 {
3786 /* Emit delayed restores and reset the CFA to be SP. */
3791 }
3793 /* We prefer to emit the combined return/authenticate instruction RETAA,
3794 however there are three cases in which we must instead emit an explicit
3795 authentication instruction.
3797 1) Sibcalls don't return in a normal way, so if we're about to call one
3798 we must authenticate.
3800 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
3801 generating code for !TARGET_ARMV8_3 we can't use it and must
3802 explicitly authenticate.
3804 3) On an eh_return path we make extra stack adjustments to update the
3805 canonical frame address to be the exception handler's CFA. We want
3806 to authenticate using the CFA of the function which calls eh_return.
3807 */
3810 {
3814 }
3816 /* Stack adjustment for exception handler. */
3818 {
3819 /* We need to unwind the stack by the offset computed by
3820 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
3821 to be SP; letting the CFA move during this adjustment
3822 is just as correct as retaining the CFA from the body
3823 of the function. Therefore, do nothing special. */
3825 }
3830 }
3832 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
3833 normally or return to a previous frame after unwinding.
3835 An EH return uses a single shared return sequence. The epilogue is
3836 exactly like a normal epilogue except that it has an extra input
3837 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
3838 that must be applied after the frame has been destroyed. An extra label
3839 is inserted before the epilogue which initializes this register to zero,
3840 and this is the entry point for a normal return.
3842 An actual EH return updates the return address, initializes the stack
3843 adjustment and jumps directly into the epilogue (bypassing the zeroing
3844 of the adjustment). Since the return address is typically saved on the
3845 stack when a function makes a call, the saved LR must be updated outside
3846 the epilogue.
3848 This poses problems as the store is generated well before the epilogue,
3849 so the offset of LR is not known yet. Also optimizations will remove the
3850 store as it appears dead, even after the epilogue is generated (as the
3851 base or offset for loading LR is different in many cases).
3853 To avoid these problems this implementation forces the frame pointer
3854 in eh_return functions so that the location of LR is fixed and known early.
3855 It also marks the store volatile, so no optimization is permitted to
3856 remove the store. */
3857 rtx
3859 {
3863 /* Mark the store volatile, so no optimization is permitted to remove it. */
3866 }
3868 /* Output code to add DELTA to the first argument, and then jump
3869 to FUNCTION. Used for C++ multiple inheritance. */
3870 static void
3872 HOST_WIDE_INT delta,
3873 HOST_WIDE_INT vcall_offset,
3874 tree function)
3875 {
3876 /* The this pointer is always in x0. Note that this differs from
3877 Arm where the this pointer maybe bumped to r1 if r0 is required
3878 to return a pointer to an aggregate. On AArch64 a result value
3879 pointer will be in x8. */
3889 else
3890 {
3899 {
3903 else
3905 }
3909 else
3916 else
3917 {
3919 Pmode);
3921 }
3925 else
3931 }
3933 /* Generate a tail call to the target function. */
3935 {
3938 }
3950 /* Stop pretending to be a post-reload pass. */
3952 }
3954 static bool
3956 {
3961 {
3965 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3966 TLS offsets, not real symbol references. */
3969 }
3971 }
3974 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3975 a left shift of 0 or 12 bits. */
3976 bool
3978 {
3981 );
3982 }
3985 /* Return true if val is an immediate that can be loaded into a
3986 register by a MOVZ instruction. */
3987 static bool
3989 {
3991 {
3995 }
3996 else
3997 {
3998 /* Ignore sign extension. */
4000 }
4003 }
4005 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
4008 {
4014 };
4017 /* Return true if val is a valid bitmask immediate. */
4019 bool
4021 {
4025 /* Check for a single sequence of one bits and return quickly if so.
4026 The special cases of all ones and all zeroes returns false. */
4033 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
4037 /* Invert if the immediate doesn't start with a zero bit - this means we
4038 only need to search for sequences of one bits. */
4042 /* Find the first set bit and set tmp to val with the first sequence of one
4043 bits removed. Return success if there is a single sequence of ones. */
4050 /* Find the next set bit and compute the difference in bit position. */
4055 /* Check the bit position difference is a power of 2, and that the first
4056 sequence of one bits fits within 'bits' bits. */
4060 /* Check the sequence of one bits is repeated 64/bits times. */
4062 }
4064 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
4065 Assumed precondition: VAL_IN Is not zero. */
4067 unsigned HOST_WIDE_INT
4069 {
4076 }
4078 /* Create constant where bits outside of lowest bit set to highest bit set
4079 are set to 1. */
4081 unsigned HOST_WIDE_INT
4083 {
4085 }
4087 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
4089 bool
4091 {
4101 }
4103 /* Return true if val is an immediate that can be loaded into a
4104 register in a single instruction. */
4105 bool
4107 {
4111 }
4113 static bool
4115 {
4123 {
4127 else
4128 /* Avoid generating a 64-bit relocation in ILP32; leave
4129 to aarch64_expand_mov_immediate to handle it properly. */
4131 }
4134 }
4136 /* Implement TARGET_CASE_VALUES_THRESHOLD.
4137 The expansion for a table switch is quite expensive due to the number
4138 of instructions, the table lookup and hard to predict indirect jump.
4139 When optimizing for speed, and -O3 enabled, use the per-core tuning if
4140 set, otherwise use tables for > 16 cases as a tradeoff between size and
4141 performance. When optimizing for size, use the default setting. */
4143 static unsigned int
4145 {
4146 /* Use the specified limit for the number of cases before using jump
4147 tables at higher optimization levels. */
4151 else
4153 }
4155 /* Return true if register REGNO is a valid index register.
4156 STRICT_P is true if REG_OK_STRICT is in effect. */
4158 bool
4160 {
4162 {
4170 }
4172 }
4174 /* Return true if register REGNO is a valid base register for mode MODE.
4175 STRICT_P is true if REG_OK_STRICT is in effect. */
4177 bool
4179 {
4181 {
4189 }
4191 /* The fake registers will be eliminated to either the stack or
4192 hard frame pointer, both of which are usually valid base registers.
4193 Reload deals with the cases where the eliminated form isn't valid. */
4198 }
4200 /* Return true if X is a valid base register for mode MODE.
4201 STRICT_P is true if REG_OK_STRICT is in effect. */
4203 static bool
4205 {
4212 }
4214 /* Return true if address offset is a valid index. If it is, fill in INFO
4215 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
4217 static bool
4220 {
4222 rtx index;
4225 /* (reg:P) */
4228 {
4232 }
4233 /* (sign_extend:DI (reg:SI)) */
4238 {
4243 }
4244 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
4251 {
4256 }
4257 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
4264 {
4269 }
4270 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
4277 {
4285 }
4286 /* (and:DI (mult:DI (reg:DI) (const_int scale))
4287 (const_int 0xffffffff<<shift)) */
4294 {
4300 }
4301 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
4308 {
4316 }
4317 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
4318 (const_int 0xffffffff<<shift)) */
4325 {
4331 }
4332 /* (mult:P (reg:P) (const_int scale)) */
4337 {
4341 }
4342 /* (ashift:P (reg:P) (const_int shift)) */
4347 {
4351 }
4352 else
4365 {
4370 }
4373 }
4375 /* Return true if MODE is one of the modes for which we
4376 support LDP/STP operations. */
4378 static bool
4380 {
4385 }
4387 /* Return true if REGNO is a virtual pointer register, or an eliminable
4388 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
4389 include stack_pointer or hard_frame_pointer. */
4390 static bool
4392 {
4397 }
4399 /* Return true if X is a valid address for machine mode MODE. If it is,
4400 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
4401 effect. OUTER_CODE is PARALLEL for a load/store pair. */
4403 static bool
4407 {
4411 /* On BE, we use load/store pair for all large int mode load/stores.
4412 TI/TFmode may also use a load/store pair. */
4416 || (BYTES_BIG_ENDIAN
4420 !load_store_pair_p
4424 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
4425 REG addressing. */
4431 {
4447 {
4453 }
4458 {
4465 /* TImode and TFmode values are allowed in both pairs of X
4466 registers and individual Q registers. The available
4467 address modes are:
4468 X,X: 7-bit signed scaled offset
4469 Q: 9-bit signed offset
4470 We conservatively require an offset representable in either mode.
4471 When performing the check for pairs of X registers i.e. LDP/STP
4472 pass down DImode since that is the natural size of the LDP/STP
4473 instruction memory accesses. */
4479 /* A 7bit offset check because OImode will emit a ldp/stp
4480 instruction (only big endian will get here).
4481 For ldp/stp instructions, the offset is scaled for the size of a
4482 single element of the pair. */
4486 /* Three 9/12 bit offsets checks because CImode will emit three
4487 ldr/str instructions (only big endian will get here). */
4494 /* Two 7bit offsets checks because XImode will emit two ldp/stp
4495 instructions (only big endian will get here). */
4504 else
4507 }
4510 {
4511 /* Look for base + (scaled/extended) index register. */
4514 {
4517 }
4520 {
4523 }
4524 }
4545 {
4546 HOST_WIDE_INT offset;
4550 /* TImode and TFmode values are allowed in both pairs of X
4551 registers and individual Q registers. The available
4552 address modes are:
4553 X,X: 7-bit signed scaled offset
4554 Q: 9-bit signed offset
4555 We conservatively require an offset representable in either mode.
4556 */
4564 else
4566 }
4572 /* load literal: pc-relative constant pool entry. Only supported
4573 for SI mode or larger. */
4577 {
4585 }
4594 {
4599 {
4600 /* The symbol and offset must be aligned to the access size. */
4607 {
4611 }
4617 else
4626 }
4627 }
4632 }
4633 }
4635 /* Return true if the address X is valid for a PRFM instruction.
4636 STRICT_P is true if we should do strict checking with
4637 aarch64_classify_address. */
4639 bool
4641 {
4644 /* PRFM accepts the same addresses as DImode... */
4649 /* ... except writeback forms. */
4651 }
4653 bool
4655 {
4656 rtx offset;
4660 }
4662 /* Classify the base of symbolic expression X. */
4664 enum aarch64_symbol_type
4666 {
4667 rtx offset;
4671 }
4674 /* Return TRUE if X is a legitimate address for accessing memory in
4675 mode MODE. */
4676 static bool
4678 {
4682 }
4684 /* Return TRUE if X is a legitimate address for accessing memory in
4685 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
4686 pair operation. */
4687 bool
4690 {
4694 }
4696 /* Split an out-of-range address displacement into a base and offset.
4697 Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise
4698 to increase opportunities for sharing the base address of different sizes.
4699 For unaligned accesses and TI/TF mode use the signed 9-bit range. */
4700 static bool
4702 {
4713 }
4715 /* Return the binary representation of floating point constant VALUE in INTVAL.
4716 If the value cannot be converted, return false without setting INTVAL.
4717 The conversion is done in the given MODE. */
4718 bool
4720 {
4722 /* We make a general exception for 0. */
4724 {
4727 }
4733 /* Only support up to DF mode. */
4745 {
4749 }
4750 else
4755 }
4757 /* Return TRUE if rtx X is an immediate constant that can be moved using a
4758 single MOV(+MOVK) followed by an FMOV. */
4759 bool
4761 {
4766 /* Determine whether it's cheaper to write float constants as
4767 mov/movk pairs over ldr/adrp pairs. */
4773 {
4775 ? SImode
4780 }
4783 }
4785 /* Return TRUE if rtx X is immediate constant 0.0 */
4786 bool
4788 {
4795 }
4797 /* Return TRUE if rtx X is immediate constant that fits in a single
4798 MOVI immediate operation. */
4799 bool
4801 {
4810 {
4814 /* We make a general exception for 0. */
4819 }
4822 {
4825 }
4826 else
4829 /* use a 64 bit mode for everything except for DI/DF mode, where we use
4830 a 128 bit vector mode. */
4837 }
4840 /* Return the fixed registers used for condition codes. */
4842 static bool
4844 {
4848 }
4850 /* This function is used by the call expanders of the machine description.
4851 RESULT is the register in which the result is returned. It's NULL for
4852 "call" and "sibcall".
4853 MEM is the location of the function call.
4854 SIBCALL indicates whether this function call is normal call or sibling call.
4855 It will generate different pattern accordingly. */
4857 void
4859 {
4861 rtvec vec;
4862 machine_mode mode;
4869 /* Decide if we should generate indirect calls by loading the
4870 address of the callee into a register before performing
4871 the branch-and-link. */
4885 else
4892 }
4894 /* Emit call insn with PAT and do aarch64-specific handling. */
4896 void
4898 {
4904 }
4906 machine_mode
4908 {
4909 /* All floating point compares return CCFP if it is an equality
4910 comparison, and CCFPE otherwise. */
4912 {
4914 {
4935 }
4936 }
4938 /* Equality comparisons of short modes against zero can be performed
4939 using the TST instruction with the appropriate bitmask. */
4945 /* Similarly, comparisons of zero_extends from shorter modes can
4946 be performed using an ANDS with an immediate mask. */
4962 /* A compare with a shifted operand. Because of canonicalization,
4963 the comparison will have to be swapped when we emit the assembly
4964 code. */
4972 /* Similarly for a negated operand, but we can only do this for
4973 equalities. */
4980 /* A test for unsigned overflow. */
4987 /* For everything else, return CCmode. */
4989 }
4991 static int
4994 int
4996 {
5003 }
5005 static int
5007 {
5009 {
5013 {
5027 }
5032 {
5044 }
5049 {
5061 }
5066 {
5072 }
5077 {
5081 }
5086 {
5090 }
5095 }
5098 }
5100 bool
5102 HOST_WIDE_INT minval,
5103 HOST_WIDE_INT maxval)
5104 {
5105 HOST_WIDE_INT firstval;
5122 }
5124 bool
5126 {
5128 }
5131 /* N Z C V. */
5132 #define AARCH64_CC_V 1
5133 #define AARCH64_CC_C (1 << 1)
5134 #define AARCH64_CC_Z (1 << 2)
5135 #define AARCH64_CC_N (1 << 3)
5137 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
5139 {
5156 };
5158 /* Print operand X to file F in a target specific manner according to CODE.
5159 The acceptable formatting commands given by CODE are:
5160 'c': An integer or symbol address without a preceding #
5161 sign.
5162 'e': Print the sign/zero-extend size as a character 8->b,
5163 16->h, 32->w.
5164 'p': Prints N such that 2^N == X (X must be power of 2 and
5165 const int).
5166 'P': Print the number of non-zero bits in X (a const_int).
5167 'H': Print the higher numbered register of a pair (TImode)
5168 of regs.
5169 'm': Print a condition (eq, ne, etc).
5170 'M': Same as 'm', but invert condition.
5171 'b/h/s/d/q': Print a scalar FP/SIMD register name.
5172 'S/T/U/V': Print a FP/SIMD register name for a register list.
5173 The register printed is the FP/SIMD register name
5174 of X + 0/1/2/3 for S/T/U/V.
5175 'R': Print a scalar FP/SIMD register name + 1.
5176 'X': Print bottom 16 bits of integer constant in hex.
5177 'w/x': Print a general register name or the zero register
5178 (32-bit or 64-bit).
5179 '0': Print a normal operand, if it's a general register,
5180 then we assume DImode.
5181 'k': Print NZCV for conditional compare instructions.
5182 'A': Output address constant representing the first
5183 argument of X, specifying a relocation offset
5184 if appropriate.
5185 'L': Output constant address specified by X
5186 with a relocation offset if appropriate.
5187 'G': Prints address of X, specifying a PC relative
5188 relocation mode if appropriate. */
5190 static void
5192 {
5194 {
5197 {
5209 {
5212 }
5213 /* Fall through. */
5217 }
5221 {
5226 {
5229 }
5232 {
5245 }
5246 }
5250 {
5254 {
5257 }
5260 }
5265 {
5268 }
5275 {
5278 }
5285 {
5287 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
5289 {
5293 }
5296 {
5299 }
5306 }
5315 {
5316 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5318 }
5327 {
5328 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5330 }
5336 {
5337 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5339 }
5345 {
5348 }
5356 {
5359 }
5362 {
5365 }
5368 {
5371 }
5373 /* Fall through */
5377 {
5380 }
5383 {
5390 /* Check all memory references are Pmode - even with ILP32. */
5406 {
5409 HOST_WIDE_INT_MIN,
5410 HOST_WIDE_INT_MAX));
5412 }
5414 {
5416 }
5417 else
5422 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
5423 be getting CONST_DOUBLEs holding integers. */
5426 {
5429 }
5431 {
5432 #define buf_size 20
5440 #undef buf_size
5441 }
5447 }
5455 {
5482 }
5488 {
5523 }
5529 {
5535 }
5540 {
5541 HOST_WIDE_INT cond_code;
5544 {
5547 }
5552 }
5558 }
5559 }
5561 static void
5563 {
5568 {
5572 else
5581 else
5590 else
5599 else
5606 {
5633 }
5644 }
5647 }
5649 bool
5651 {
5658 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
5659 referencing instruction, but they are constant offsets, not
5660 symbols. */
5666 {
5668 {
5674 }
5677 }
5680 }
5682 /* Implement REGNO_REG_CLASS. */
5684 enum reg_class
5686 {
5701 }
5703 static rtx
5705 {
5706 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
5707 where mask is selected by alignment and size of the offset.
5708 We try to pick as large a range for the offset as possible to
5709 maximize the chance of a CSE. However, for aligned addresses
5710 we limit the range to 4k so that structures with different sized
5711 elements are likely to use the same base. We need to be careful
5712 not to split a CONST for some forms of address expression, otherwise
5713 it will generate sub-optimal code. */
5716 {
5722 {
5726 /* Force any scaling into a temp for CSE. */
5730 /* Let the pointer register be in op0. */
5734 /* If the pointer is virtual or frame related, then we know that
5735 virtual register instantiation or register elimination is going
5736 to apply a second constant. We want the two constants folded
5737 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
5739 {
5743 }
5745 /* Otherwise, in order to encourage CSE (and thence loop strength
5746 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
5750 }
5752 /* Does it look like we'll need a 16-byte load/store-pair operation? */
5753 HOST_WIDE_INT base_offset;
5756 /* For offsets aren't a multiple of the access size, the limit is
5757 -256...255. */
5759 {
5762 /* BLKmode typically uses LDP of X-registers. */
5765 }
5766 /* Small negative offsets are supported. */
5771 /* Use 12-bit offset by access size. */
5772 else
5776 {
5780 }
5781 }
5784 }
5786 /* Return the reload icode required for a constant pool in mode. */
5787 static enum insn_code
5789 {
5791 {
5827 }
5830 }
5831 static reg_class_t
5833 reg_class_t rclass,
5834 machine_mode mode,
5836 {
5838 /* If we have to disable direct literal pool loads and stores because the
5839 function is too big, then we need a scratch register. */
5844 {
5847 }
5849 /* Without the TARGET_SIMD instructions we cannot move a Q register
5850 to a Q register directly. We need a scratch. */
5854 {
5860 }
5862 /* A TFmode or TImode memory access should be handled via an FP_REGS
5863 because AArch64 has richer addressing modes for LDR/STR instructions
5864 than LDP/STP instructions. */
5873 }
5875 static bool
5877 {
5878 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
5879 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5882 {
5894 }
5895 else
5896 {
5897 /* If we decided that we didn't need a leaf frame pointer but then used
5898 LR in the function, then we'll want a frame pointer after all, so
5899 prevent this elimination to ensure a frame pointer is used. */
5901 && flag_omit_leaf_frame_pointer
5904 }
5907 }
5909 HOST_WIDE_INT
5911 {
5915 {
5922 }
5925 {
5929 }
5932 }
5934 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
5935 previous frame. */
5937 rtx
5939 {
5943 }
5946 static void
5948 {
5950 {
5953 }
5954 else
5955 {
5958 }
5963 }
5965 static void
5967 {
5971 /* Don't need to copy the trailing D-words, we fill those in below. */
5983 /* XXX We should really define a "clear_cache" pattern and use
5984 gen_clear_cache(). */
5989 ptr_mode);
5990 }
5992 static unsigned char
5994 {
5996 {
6003 return
6015 }
6017 }
6019 static reg_class_t
6021 {
6026 {
6032 }
6034 /* Register eliminiation can result in a request for
6035 SP+constant->FP_REGS. We cannot support such operations which
6036 use SP as source and an FP_REG as destination, so reject out
6037 right now. */
6039 {
6042 /* Look through a possible SUBREG introduced by ILP32. */
6048 POINTER_REGS));
6050 }
6053 }
6055 void
6057 {
6059 }
6061 static void
6063 {
6066 else
6067 {
6069 /* While priority is known to be in range [0, 65535], so 18 bytes
6070 would be enough, the compiler might not know that. To avoid
6071 -Wformat-truncation false positive, use a larger size. */
6078 }
6079 }
6081 static void
6083 {
6086 else
6087 {
6089 /* While priority is known to be in range [0, 65535], so 18 bytes
6090 would be enough, the compiler might not know that. To avoid
6091 -Wformat-truncation false positive, use a larger size. */
6098 }
6099 }
6103 {
6109 {
6110 {
6113 },
6114 {
6117 },
6118 {
6121 },
6122 /* We assume that DImode is only generated when not optimizing and
6123 that we don't really need 64-bit address offsets. That would
6124 imply an object file with 8GB of code in a single function! */
6125 {
6128 }
6129 };
6137 /* Need to implement table size reduction, by chaning the code below. */
6147 }
6150 /* Return size in bits of an arithmetic operand which is shifted/scaled and
6151 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
6152 operator. */
6154 int
6156 {
6158 {
6161 {
6165 }
6166 }
6168 }
6170 /* Constant pools are per function only when PC relative
6171 literal loads are true or we are in the large memory
6172 model. */
6176 {
6179 }
6181 static bool
6183 {
6184 /* Fixme:: In an ideal world this would work similar
6185 to the logic in aarch64_select_rtx_section but this
6186 breaks bootstrap in gcc go. For now we workaround
6187 this by returning false here. */
6189 }
6191 /* Select appropriate section for constants depending
6192 on where we place literal pools. */
6196 rtx x,
6198 {
6203 }
6205 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
6206 void
6208 HOST_WIDE_INT offset)
6209 {
6210 /* When using per-function literal pools, we must ensure that any code
6211 section is aligned to the minimal instruction length, lest we get
6212 errors from the assembler re "unaligned instructions". */
6215 }
6217 /* Costs. */
6219 /* Helper function for rtx cost calculation. Strip a shift expression
6220 from X. Returns the inner operand if successful, or the original
6221 expression on failure. */
6222 static rtx
6224 {
6227 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
6228 we can convert both to ROR during final output. */
6243 }
6245 /* Helper function for rtx cost calculation. Strip an extend
6246 expression from X. Returns the inner operand if successful, or the
6247 original expression on failure. We deal with a number of possible
6248 canonicalization variations here. If STRIP_SHIFT is true, then
6249 we can strip off a shift also. */
6250 static rtx
6252 {
6255 /* Zero and sign extraction of a widened value. */
6263 /* It can also be represented (for zero-extend) as an AND with an
6264 immediate. */
6273 /* Now handle extended register, as this may also have an optional
6274 left shift by 1..4. */
6289 }
6291 /* Return true iff CODE is a shift supported in combination
6292 with arithmetic instructions. */
6294 static bool
6296 {
6298 }
6301 /* Return true iff X is a cheap shift without a sign extend. */
6303 static bool
6305 {
6331 }
6333 /* Helper function for rtx cost calculation. Calculate the cost of
6334 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
6335 Return the calculated cost of the expression, recursing manually in to
6336 operands where needed. */
6338 static int
6340 {
6356 /* Integer multiply/fma. */
6358 {
6359 /* The multiply will be canonicalized as a shift, cost it as such. */
6363 {
6367 {
6369 {
6370 /* If the shift is considered cheap,
6371 then don't add any cost. */
6373 ;
6375 /* ARITH + shift-by-register. */
6378 /* ARITH + extended register. We don't have a cost field
6379 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
6381 else
6382 /* ARITH + shift-by-immediate. */
6384 }
6385 else
6386 /* LSL (immediate). */
6389 }
6390 /* Strip extends as we will have costed them in the case above. */
6397 }
6399 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
6400 compound and let the below cases handle it. After all, MNEG is a
6401 special-case alias of MSUB. */
6403 {
6406 }
6408 /* Integer multiplies or FMAs have zero/sign extending variants. */
6413 {
6418 {
6420 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
6422 else
6423 /* MUL/SMULL/UMULL. */
6425 }
6428 }
6430 /* This is either an integer multiply or a MADD. In both cases
6431 we want to recurse and cost the operands. */
6436 {
6438 /* MADD/MSUB. */
6440 else
6441 /* MUL. */
6443 }
6446 }
6447 else
6448 {
6450 {
6451 /* Floating-point FMA/FMUL can also support negations of the
6452 operands, unless the rounding mode is upward or downward in
6453 which case FNMUL is different than FMUL with operand negation. */
6457 {
6462 }
6465 /* FMADD/FNMADD/FNMSUB/FMSUB. */
6467 else
6468 /* FMUL/FNMUL. */
6470 }
6475 }
6476 }
6478 static int
6480 machine_mode mode,
6481 addr_space_t as ATTRIBUTE_UNUSED,
6483 {
6491 {
6493 {
6494 /* This is a CONST or SYMBOL ref which will be split
6495 in a different way depending on the code model in use.
6496 Cost it through the generic infrastructure. */
6498 /* Divide through by the cost of one instruction to
6499 bring it to the same units as the address costs. */
6501 /* The cost is then the cost of preparing the address,
6502 followed by an immediate (possibly 0) offset. */
6504 }
6505 else
6506 {
6507 /* This is most likely a jump table from a case
6508 statement. */
6510 }
6511 }
6514 {
6526 else
6545 }
6549 {
6550 /* For the sake of calculating the cost of the shifted register
6551 component, we can treat same sized modes in the same way. */
6553 {
6566 /* We can't tell, or this is a 128-bit vector. */
6570 }
6571 }
6574 }
6576 /* Return the cost of a branch. If SPEED_P is true then the compiler is
6577 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
6578 to be taken. */
6580 int
6582 {
6583 /* When optimizing for speed, use the cost of unpredictable branches. */
6589 else
6591 }
6593 /* Return true if the RTX X in mode MODE is a zero or sign extract
6594 usable in an ADD or SUB (extended register) instruction. */
6595 static bool
6597 {
6598 /* Catch add with a sign extract.
6599 This is add_<optab><mode>_multp2. */
6602 {
6613 op1))
6614 {
6616 }
6617 }
6618 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
6619 No shift. */
6625 }
6627 static bool
6629 {
6631 {
6643 }
6644 }
6646 /* Return true iff X is an rtx that will match an extr instruction
6647 i.e. as described in the *extr<mode>5_insn family of patterns.
6648 OP0 and OP1 will be set to the operands of the shifts involved
6649 on success and will be NULL_RTX otherwise. */
6651 static bool
6653 {
6668 {
6669 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
6681 {
6685 }
6686 }
6689 }
6691 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
6692 storing it in *COST. Result is true if the total cost of the operation
6693 has now been calculated. */
6694 static bool
6696 {
6697 rtx inner;
6698 rtx comparator;
6702 {
6706 }
6707 else
6708 {
6712 }
6715 {
6716 /* Conditional branch. */
6719 else
6720 {
6722 {
6724 {
6725 /* TBZ/TBNZ/CBZ/CBNZ. */
6727 /* TBZ/TBNZ. */
6730 else
6731 /* CBZ/CBNZ. */
6735 }
6736 }
6738 {
6739 /* TBZ/TBNZ. */
6742 }
6743 }
6744 }
6746 {
6747 /* CCMP. */
6749 {
6750 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
6754 {
6761 else
6763 }
6765 }
6767 /* It's a conditional operation based on the status flags,
6768 so it must be some flavor of CSEL. */
6770 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
6776 {
6777 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
6780 }
6785 }
6787 /* We don't know what this is, cost all operands. */
6789 }
6791 /* Check whether X is a bitfield operation of the form shift + extend that
6792 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
6793 operand to which the bitfield operation is applied. Otherwise return
6794 NULL_RTX. */
6796 static rtx
6798 {
6812 {
6830 }
6833 }
6835 /* Return true if the mask and a shift amount from an RTX of the form
6836 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
6837 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
6839 bool
6841 {
6846 }
6848 /* Calculate the cost of calculating X, storing it in *COST. Result
6849 is true if the total cost of the operation has now been calculated. */
6850 static bool
6853 {
6858 scalar_int_mode int_mode;
6860 /* By default, assume that everything has equivalent cost to the
6861 cheapest instruction. Any additional costs are applied as a delta
6862 above this default. */
6866 {
6868 /* The cost depends entirely on the operands to SET. */
6874 {
6877 {
6891 }
6900 /* Fall through. */
6902 /* The cost is one per vector-register copied. */
6904 {
6908 }
6909 /* const0_rtx is in general free, but we will use an
6910 instruction to set a register to 0. */
6912 {
6913 /* The cost is 1 per register copied. */
6917 }
6918 else
6919 /* Cost is just the cost of the RHS of the set. */
6925 /* Bit-field insertion. Strip any redundant widening of
6926 the RHS to meet the width of the target. */
6937 {
6938 /* MOV immediate is assumed to always be cheap. */
6940 }
6941 else
6942 {
6943 /* BFM. */
6947 }
6952 /* We can't make sense of this, assume default cost. */
6955 }
6959 /* If an instruction can incorporate a constant within the
6960 instruction, the instruction's expression avoids calling
6961 rtx_cost() on the constant. If rtx_cost() is called on a
6962 constant, then it is usually because the constant must be
6963 moved into a register by one or more instructions.
6965 The exception is constant 0, which can be expressed
6966 as XZR/WZR and is therefore free. The exception to this is
6967 if we have (set (reg) (const0_rtx)) in which case we must cost
6968 the move. However, we can catch that when we cost the SET, so
6969 we don't need to consider that here. */
6972 else
6973 {
6974 /* To an approximation, building any other constant is
6975 proportionally expensive to the number of instructions
6976 required to build that constant. This is true whether we
6977 are compiling for SPEED or otherwise. */
6980 }
6985 /* First determine number of instructions to do the move
6986 as an integer constant. */
6990 {
6996 ? SImode
7002 }
7005 {
7006 /* mov[df,sf]_aarch64. */
7008 /* FMOV (scalar immediate). */
7011 {
7012 /* This will be a load from memory. */
7015 else
7017 }
7018 else
7019 /* Otherwise this is +0.0. We get this using MOVI d0, #0
7020 or MOV v0.s[0], wzr - neither of which are modeled by the
7021 cost tables. Just use the default cost. */
7022 {
7023 }
7024 }
7030 {
7031 /* For loads we want the base cost of a load, plus an
7032 approximation for the additional cost of the addressing
7033 mode. */
7047 }
7055 {
7057 {
7058 /* FNEG. */
7060 }
7062 }
7065 {
7068 {
7069 /* CSETM. */
7072 }
7074 /* Cost this as SUB wzr, X. */
7078 }
7081 {
7082 /* Support (neg(fma...)) as a single instruction only if
7083 sign of zeros is unimportant. This matches the decision
7084 making in aarch64.md. */
7086 {
7087 /* FNMADD. */
7090 }
7092 {
7093 /* FNMUL. */
7096 }
7098 /* FNEG. */
7101 }
7108 {
7111 else
7113 }
7123 {
7127 }
7130 {
7131 /* TODO: A write to the CC flags possibly costs extra, this
7132 needs encoding in the cost tables. */
7135 /* ANDS. */
7137 {
7140 }
7143 {
7144 /* ADDS (and CMN alias). */
7147 }
7150 {
7151 /* SUBS. */
7154 }
7159 {
7160 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
7161 Handle it here directly rather than going to cost_logic
7162 since we know the immediate generated for the TST is valid
7163 so we can avoid creating an intermediate rtx for it only
7164 for costing purposes. */
7171 }
7174 {
7175 /* CMN. */
7182 }
7184 /* CMP.
7186 Compare can freely swap the order of operands, and
7187 canonicalization puts the more complex operation first.
7188 But the integer MINUS logic expects the shift/extend
7189 operation in op1. */
7192 {
7195 }
7197 }
7200 {
7201 /* FCMP. */
7206 {
7208 /* FCMP supports constant 0.0 for no extra cost. */
7210 }
7212 }
7215 {
7216 /* Vector compare. */
7221 {
7222 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
7223 cost. */
7225 }
7227 }
7231 {
7235 cost_minus:
7238 /* Detect valid immediates. */
7244 {
7246 /* SUB(S) (immediate). */
7249 }
7251 /* Look for SUB (extended register). */
7253 {
7261 }
7265 /* Cost this as an FMA-alike operation. */
7269 {
7272 speed);
7274 }
7279 {
7281 {
7282 /* Vector SUB. */
7284 }
7286 {
7287 /* SUB(S). */
7289 }
7291 {
7292 /* FSUB. */
7294 }
7295 }
7297 }
7300 {
7301 rtx new_op0;
7306 cost_plus:
7309 {
7310 /* CSINC. */
7314 }
7319 {
7323 /* ADD (immediate). */
7326 }
7330 /* Look for ADD (extended register). */
7332 {
7340 }
7342 /* Strip any extend, leave shifts behind as we will
7343 cost them through mult_cost. */
7348 {
7350 speed);
7352 }
7357 {
7359 {
7360 /* Vector ADD. */
7362 }
7364 {
7365 /* ADD. */
7367 }
7369 {
7370 /* FADD. */
7372 }
7373 }
7375 }
7381 {
7384 else
7386 }
7391 {
7395 {
7398 else
7400 }
7402 }
7405 {
7412 }
7413 /* Fall through. */
7416 cost_logic:
7421 {
7425 }
7433 {
7434 /* This is a UBFM/SBFM. */
7439 }
7442 {
7444 {
7445 /* We have a mask + shift version of a UBFIZ
7446 i.e. the *andim_ashift<mode>_bfiz pattern. */
7450 {
7457 }
7459 {
7460 /* We possibly get the immediate for free, this is not
7461 modelled. */
7468 }
7469 }
7470 else
7471 {
7474 /* Handle ORN, EON, or BIC. */
7480 /* If we had a shift on op0 then this is a logical-shift-
7481 by-register/immediate operation. Otherwise, this is just
7482 a logical operation. */
7484 {
7486 {
7487 /* Shift by immediate. */
7490 else
7492 }
7493 else
7495 }
7497 /* In both cases we want to cost both operands. */
7504 }
7505 }
7513 {
7514 /* Vector NOT. */
7517 }
7519 /* MVN-shifted-reg. */
7521 {
7528 }
7529 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
7530 Handle the second form here taking care that 'a' in the above can
7531 be a shift. */
7533 {
7542 {
7545 else
7547 }
7550 }
7551 /* MVN. */
7560 /* If a value is written in SI mode, then zero extended to DI
7561 mode, the operation will in general be free as a write to
7562 a 'w' register implicitly zeroes the upper bits of an 'x'
7563 register. However, if this is
7565 (set (reg) (zero_extend (reg)))
7567 we must cost the explicit register move. */
7571 {
7574 /* If OP_COST is non-zero, then the cost of the zero extend
7575 is effectively the cost of the inner operation. Otherwise
7576 we have a MOV instruction and we take the cost from the MOV
7577 itself. This is true independently of whether we are
7578 optimizing for space or time. */
7583 }
7585 {
7586 /* All loads can zero extend to any size for free. */
7589 }
7593 {
7598 }
7601 {
7603 {
7604 /* UMOV. */
7606 }
7607 else
7608 {
7609 /* We generate an AND instead of UXTB/UXTH. */
7611 }
7612 }
7617 {
7618 /* LDRSH. */
7620 {
7627 }
7629 }
7633 {
7638 }
7641 {
7644 else
7646 }
7654 {
7656 {
7658 {
7659 /* Vector shift (immediate). */
7661 }
7662 else
7663 {
7664 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
7665 aliases. */
7667 }
7668 }
7670 /* We can incorporate zero/sign extend for free. */
7677 }
7678 else
7679 {
7681 {
7683 /* Vector shift (register). */
7685 }
7686 else
7687 {
7689 /* LSLV. */
7695 {
7697 /* We already demanded XEXP (op1, 0) to be REG_P, so
7698 don't recurse into it. */
7700 }
7701 }
7703 }
7713 {
7714 /* ASR (immediate) and friends. */
7716 {
7719 else
7721 }
7725 }
7726 else
7727 {
7729 {
7731 /* Vector shift (register). */
7733 }
7734 else
7735 {
7737 /* ASR (register) and friends. */
7743 {
7745 /* We already demanded XEXP (op1, 0) to be REG_P, so
7746 don't recurse into it. */
7748 }
7749 }
7751 }
7757 {
7758 /* LDR. */
7761 }
7764 {
7765 /* ADRP, followed by ADD. */
7769 }
7772 {
7773 /* ADR. */
7776 }
7779 {
7780 /* One extra load instruction, after accessing the GOT. */
7784 }
7789 /* ADRP/ADD (immediate). */
7796 /* UBFX/SBFX. */
7798 {
7801 else
7803 }
7805 /* We can trust that the immediates used will be correct (there
7806 are no by-register forms), so we need only cost op0. */
7812 /* aarch64_rtx_mult_cost always handles recursion to its
7813 operands. */
7817 /* We can expand signed mod by power of 2 using a NEGS, two parallel
7818 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
7819 an unconditional negate. This case should only ever be reached through
7820 the set_smod_pow2_cheap check in expmed.c. */
7824 {
7825 /* We expand to 4 instructions. Reset the baseline. */
7833 }
7835 /* Fall-through. */
7838 {
7839 /* Slighly prefer UMOD over SMOD. */
7846 }
7853 {
7857 /* There is no integer SQRT, so only DIV and UDIV can get
7858 here. */
7860 /* Slighly prefer UDIV over SDIV. */
7862 else
7864 }
7890 {
7893 else
7895 }
7897 /* FMSUB, FNMADD, and FNMSUB are free. */
7904 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
7905 and the by-element operand as operand 0. */
7909 /* Catch vector-by-element operations. The by-element operand can
7910 either be (vec_duplicate (vec_select (x))) or just
7911 (vec_select (x)), depending on whether we are multiplying by
7912 a vector or a scalar.
7914 Canonicalization is not very good in these cases, FMA4 will put the
7915 by-element operand as operand 0, FNMA4 will have it as operand 1. */
7926 /* If the remaining parameters are not registers,
7927 get the cost to put them into registers. */
7941 {
7943 {
7944 /*Vector truncate. */
7946 }
7947 else
7949 }
7954 {
7956 {
7957 /*Vector conversion. */
7959 }
7960 else
7962 }
7968 /* Strip the rounding part. They will all be implemented
7969 by the fcvt* family of instructions anyway. */
7971 {
7980 }
7983 {
7986 else
7988 }
7990 /* We can combine fmul by a power of 2 followed by a fcvt into a single
7991 fixed-point fcvt. */
7996 {
8000 }
8007 {
8008 /* ABS (vector). */
8011 }
8013 {
8016 /* FABD, which is analogous to FADD. */
8018 {
8025 }
8026 /* Simple FABS is analogous to FNEG. */
8029 }
8030 else
8031 {
8032 /* Integer ABS will either be split to
8033 two arithmetic instructions, or will be an ABS
8034 (scalar), which we don't model. */
8038 }
8044 {
8047 else
8048 {
8049 /* FMAXNM/FMINNM/FMAX/FMIN.
8050 TODO: This may not be accurate for all implementations, but
8051 we do not model this in the cost tables. */
8053 }
8054 }
8058 /* The floating point round to integer frint* instructions. */
8060 {
8065 }
8068 {
8073 }
8078 /* Decompose <su>muldi3_highpart. */
8080 mode == DImode
8081 /* (lshiftrt:TI */
8084 /* (mult:TI */
8086 /* (ANY_EXTEND:TI (reg:DI))
8087 (ANY_EXTEND:TI (reg:DI))) */
8094 /* (const_int 64) */
8097 {
8098 /* UMULH/SMULH. */
8106 }
8108 /* Fall through. */
8111 }
8119 }
8121 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
8122 calculated for X. This cost is stored in *COST. Returns true
8123 if the total cost of X was calculated. */
8124 static bool
8127 {
8132 {
8137 }
8140 }
8142 static int
8145 {
8151 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
8158 /* Moving between GPR and stack cost is the same as GP2GP. */
8163 /* To/From the stack register, we move via the gprs. */
8169 {
8170 /* 128-bit operations on general registers require 2 instructions. */
8178 /* When AdvSIMD instructions are disabled it is not possible to move
8179 a 128-bit value directly between Q registers. This is handled in
8180 secondary reload. A general register is used as a scratch to move
8181 the upper DI value and the lower DI value is moved directly,
8182 hence the cost is the sum of three moves. */
8187 }
8197 }
8199 static int
8201 reg_class_t rclass ATTRIBUTE_UNUSED,
8203 {
8205 }
8207 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
8208 to optimize 1.0/sqrt. */
8210 static bool
8212 {
8214 && flag_unsafe_math_optimizations
8218 }
8220 /* Function to decide when to use the approximate reciprocal square root
8221 builtin. */
8223 static tree
8225 {
8231 }
8235 /* Select reciprocal square root initial estimate insn depending on machine
8236 mode. */
8238 static rsqrte_type
8240 {
8242 {
8249 }
8250 }
8254 /* Select reciprocal square root series step insn depending on machine mode. */
8256 static rsqrts_type
8258 {
8260 {
8267 }
8268 }
8270 /* Emit instruction sequence to compute either the approximate square root
8271 or its approximate reciprocal, depending on the flag RECP, and return
8272 whether the sequence was emitted or not. */
8274 bool
8276 {
8280 {
8283 }
8285 machine_mode mmsk
8289 {
8296 || flag_trapping_math
8297 || !flag_unsafe_math_optimizations
8300 }
8301 else
8302 /* Caller assumes we cannot fail. */
8308 /* When calculating the approximate square root, compare the
8309 argument with 0.0 and create a mask. */
8315 /* Estimate the approximate reciprocal square root. */
8319 /* Iterate over the series twice for SF and thrice for DF. */
8322 /* Optionally iterate over the series once less for faster performance
8323 while sacrificing the accuracy. */
8326 iterations--;
8328 /* Iterate over the series to calculate the approximate reciprocal square
8329 root. */
8332 {
8340 }
8343 {
8344 /* Qualify the approximate reciprocal square root when the argument is
8345 0.0 by squashing the intermediary result to 0.0. */
8351 /* Calculate the approximate square root. */
8353 }
8355 /* Finalize the approximation. */
8359 }
8363 /* Select reciprocal initial estimate insn depending on machine mode. */
8365 static recpe_type
8367 {
8369 {
8376 }
8377 }
8381 /* Select reciprocal series step insn depending on machine mode. */
8383 static recps_type
8385 {
8387 {
8394 }
8395 }
8397 /* Emit the instruction sequence to compute the approximation for the division
8398 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
8400 bool
8402 {
8413 || flag_trapping_math
8414 || !flag_unsafe_math_optimizations
8419 /* Estimate the approximate reciprocal. */
8423 /* Iterate over the series twice for SF and thrice for DF. */
8426 /* Optionally iterate over the series once less for faster performance,
8427 while sacrificing the accuracy. */
8429 iterations--;
8431 /* Iterate over the series to calculate the approximate reciprocal. */
8434 {
8439 }
8442 {
8443 /* As the approximate reciprocal of DEN is already calculated, only
8444 calculate the approximate division when NUM is not 1.0. */
8447 }
8449 /* Finalize the approximation. */
8452 }
8454 /* Return the number of instructions that can be issued per cycle. */
8455 static int
8457 {
8459 }
8461 static int
8463 {
8467 }
8470 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
8471 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
8472 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
8474 static int
8477 {
8479 }
8482 /* Vectorizer cost model target hooks. */
8484 /* Implement targetm.vectorize.builtin_vectorization_cost. */
8485 static int
8487 tree vectype,
8489 {
8498 {
8547 }
8548 }
8550 /* Implement targetm.vectorize.add_stmt_cost. */
8551 static unsigned
8555 {
8560 {
8565 /* Statements in an inner loop relative to the loop being
8566 vectorized are weighted more heavily. The value here is
8567 arbitrary and could potentially be improved with analysis. */
8573 }
8576 }
8580 /* Parse the TO_PARSE string and put the architecture struct that it
8581 selects into RES and the architectural features into ISA_FLAGS.
8582 Return an aarch64_parse_opt_result describing the parse result.
8583 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
8585 static enum aarch64_parse_opt_result
8588 {
8600 else
8607 /* Loop through the list of supported ARCHes to find a match. */
8609 {
8611 {
8615 {
8616 /* TO_PARSE string contains at least one extension. */
8617 enum aarch64_parse_opt_result ext_res
8622 }
8623 /* Extension parsing was successful. Confirm the result
8624 arch and ISA flags. */
8628 }
8629 }
8631 /* ARCH name not found in list. */
8633 }
8635 /* Parse the TO_PARSE string and put the result tuning in RES and the
8636 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
8637 describing the parse result. If there is an error parsing, RES and
8638 ISA_FLAGS are left unchanged. */
8640 static enum aarch64_parse_opt_result
8643 {
8655 else
8662 /* Loop through the list of supported CPUs to find a match. */
8664 {
8666 {
8671 {
8672 /* TO_PARSE string contains at least one extension. */
8673 enum aarch64_parse_opt_result ext_res
8678 }
8679 /* Extension parsing was successfull. Confirm the result
8680 cpu and ISA flags. */
8684 }
8685 }
8687 /* CPU name not found in list. */
8689 }
8691 /* Parse the TO_PARSE string and put the cpu it selects into RES.
8692 Return an aarch64_parse_opt_result describing the parse result.
8693 If the parsing fails the RES does not change. */
8695 static enum aarch64_parse_opt_result
8697 {
8703 /* Loop through the list of supported CPUs to find a match. */
8705 {
8707 {
8710 }
8711 }
8713 /* CPU name not found in list. */
8715 }
8717 /* Parse TOKEN, which has length LENGTH to see if it is an option
8718 described in FLAG. If it is, return the index bit for that fusion type.
8719 If not, error (printing OPTION_NAME) and return zero. */
8721 static unsigned int
8726 {
8728 {
8732 }
8736 }
8738 /* Parse OPTION which is a comma-separated list of flags to enable.
8739 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
8740 default state we inherit from the CPU tuning structures. OPTION_NAME
8741 gives the top-level option we are parsing in the -moverride string,
8742 for use in error messages. */
8744 static unsigned int
8749 {
8756 {
8759 token_length,
8760 flags,
8761 option_name);
8762 /* If we find "none" (or, for simplicity's sake, an error) anywhere
8763 in the token stream, reset the supported operations. So:
8765 adrp+add.cmp+branch.none.adrp+add
8767 would have the result of turning on only adrp+add fusion. */
8773 }
8775 /* We ended with a comma, print something. */
8777 {
8780 }
8782 /* We still have one more token to parse. */
8785 token_length,
8786 flags,
8787 option_name);
8793 }
8795 /* Support for overriding instruction fusion. */
8797 static void
8800 {
8802 aarch64_fusible_pairs,
8805 }
8807 /* Support for overriding other tuning flags. */
8809 static void
8812 {
8813 tune->extra_tuning_flags
8815 aarch64_tuning_flags,
8818 }
8820 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
8821 we understand. If it is, extract the option string and handoff to
8822 the appropriate function. */
8824 void
8828 {
8834 {
8837 }
8839 /* Get the length of the option name. */
8841 /* Skip the '=' to get to the option string. */
8842 option_part++;
8845 {
8847 {
8850 }
8851 }
8855 }
8857 /* A checking mechanism for the implementation of the tls size. */
8859 static void
8861 {
8866 {
8868 /* Both the default and maximum TLS size allowed under tiny is 1M which
8869 needs two instructions to address, so we clamp the size to 24. */
8874 /* The maximum TLS size allowed under small is 4G. */
8879 /* The maximum TLS size allowed under large is 16E.
8880 FIXME: 16E should be 64bit, we only support 48bit offset now. */
8886 }
8889 }
8891 /* Parse STRING looking for options in the format:
8892 string :: option:string
8893 option :: name=substring
8894 name :: {a-z}
8895 substring :: defined by option. */
8897 static void
8900 {
8911 {
8913 /* Make this substring look like a string. */
8917 }
8919 /* One last option to parse. */
8922 }
8925 static void
8927 {
8928 /* The logic here is that if we are disabling all frame pointer generation
8929 then we do not need to disable leaf frame pointer generation as a
8930 separate operation. But if we are *only* disabling leaf frame pointer
8931 generation then we set flag_omit_frame_pointer to true, but in
8932 aarch64_frame_pointer_required we return false only for leaf functions.
8934 PR 70044: We have to be careful about being called multiple times for the
8935 same function. Once we have decided to set flag_omit_frame_pointer just
8936 so that we can omit leaf frame pointers, we must then not interpret a
8937 second call as meaning that all frame pointer generation should be
8938 omitted. We do this by setting flag_omit_frame_pointer to a special,
8939 non-zero value. */
8948 /* If not optimizing for size, set the default
8949 alignment to what the target wants. */
8951 {
8958 }
8960 /* We default to no pc-relative literal loads. */
8964 /* If -mpc-relative-literal-loads is set on the command line, this
8965 implies that the user asked for PC relative literal loads. */
8969 /* This is PR70113. When building the Linux kernel with
8970 CONFIG_ARM64_ERRATUM_843419, support for relocations
8971 R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADR_PREL_PG_HI21_NC is
8972 removed from the kernel to avoid loading objects with possibly
8973 offending sequences. Without -mpc-relative-literal-loads we would
8974 generate such relocations, preventing the kernel build from
8975 succeeding. */
8980 /* In the tiny memory model it makes no sense to disallow PC relative
8981 literal pool loads. */
8986 /* When enabling the lower precision Newton series for the square root, also
8987 enable it for the reciprocal square root, since the latter is an
8988 intermediary step for the former. */
8991 }
8993 /* 'Unpack' up the internal tuning structs and update the options
8994 in OPTS. The caller must have set up selected_tune and selected_arch
8995 as all the other target-specific codegen decisions are
8996 derived from them. */
8998 void
9000 {
9003 /* Make a copy of the tuning parameters attached to the core, which
9004 we may later overwrite. */
9012 /* This target defaults to strict volatile bitfields. */
9021 {
9033 }
9035 /* We don't mind passing in global_options_set here as we don't use
9036 the *options_set structs anyway. */
9038 queue_depth,
9042 /* Set up parameters to be used in prefetching algorithm. Do not
9043 override the defaults unless we are tuning for a core we have
9044 researched values for. */
9066 /* Enable sw prefetching at specified optimization level for
9067 CPUS that have prefetch. Lower optimization level threshold by 1
9068 when profiling is enabled. */
9076 }
9078 /* Print a hint with a suggestion for a core or architecture name that
9079 most closely resembles what the user passed in STR. ARCH is true if
9080 the user is asking for an architecture name. ARCH is false if the user
9081 is asking for a core name. */
9083 static void
9085 {
9096 }
9098 /* Print a hint with a suggestion for a core name that most closely resembles
9099 what the user passed in STR. */
9103 {
9105 }
9107 /* Print a hint with a suggestion for an architecture name that most closely
9108 resembles what the user passed in STR. */
9112 {
9114 }
9116 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
9117 specified in STR and throw errors if appropriate. Put the results if
9118 they are valid in RES and ISA_FLAGS. Return whether the option is
9119 valid. */
9121 static bool
9124 {
9125 enum aarch64_parse_opt_result parse_res
9132 {
9145 }
9148 }
9150 /* Validate a command-line -march option. Parse the arch and extensions
9151 (if any) specified in STR and throw errors if appropriate. Put the
9152 results, if they are valid, in RES and ISA_FLAGS. Return whether the
9153 option is valid. */
9155 static bool
9158 {
9159 enum aarch64_parse_opt_result parse_res
9166 {
9179 }
9182 }
9184 /* Validate a command-line -mtune option. Parse the cpu
9185 specified in STR and throw errors if appropriate. Put the
9186 result, if it is valid, in RES. Return whether the option is
9187 valid. */
9189 static bool
9191 {
9192 enum aarch64_parse_opt_result parse_res
9199 {
9209 }
9211 }
9213 /* Return the CPU corresponding to the enum CPU.
9214 If it doesn't specify a cpu, return the default. */
9218 {
9222 /* The & 0x3f is to extract the bottom 6 bits that encode the
9223 default cpu as selected by the --with-cpu GCC configure option
9224 in config.gcc.
9225 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
9226 flags mechanism should be reworked to make it more sane. */
9228 }
9230 /* Return the architecture corresponding to the enum ARCH.
9231 If it doesn't specify a valid architecture, return the default. */
9235 {
9242 }
9244 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
9245 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
9246 tuning structs. In particular it must set selected_tune and
9247 aarch64_isa_flags that define the available ISA features and tuning
9248 decisions. It must also set selected_arch as this will be used to
9249 output the .arch asm tags for each function. */
9251 static void
9253 {
9266 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
9267 If either of -march or -mtune is given, they override their
9268 respective component of -mcpu. */
9280 /* If the user did not specify a processor, choose the default
9281 one for them. This will be the CPU set during configuration using
9282 --with-cpu, otherwise it is "generic". */
9284 {
9286 {
9290 }
9291 else
9292 {
9293 /* Get default configure-time CPU. */
9296 }
9300 }
9301 /* If both -mcpu and -march are specified check that they are architecturally
9302 compatible, warn if they're not and prefer the -march ISA flags. */
9304 {
9306 {
9310 }
9315 }
9316 else
9317 {
9318 /* -mcpu but no -march. */
9325 }
9327 /* Set the arch as well as we will need it when outputing
9328 the .arch directive in assembly. */
9330 {
9333 }
9338 #ifndef HAVE_AS_MABI_OPTION
9339 /* The compiler may have been configured with 2.23.* binutils, which does
9340 not have support for ILP32. */
9343 #endif
9348 /* Make sure we properly set up the explicit options. */
9359 /* Save these options as the default ones in case we push and pop them later
9360 while processing functions with potential target attributes. */
9361 target_option_default_node = target_option_current_node
9363 }
9365 /* Implement targetm.override_options_after_change. */
9367 static void
9369 {
9371 }
9375 {
9379 }
9381 void
9383 {
9385 }
9387 /* A checking mechanism for the implementation of the various code models. */
9388 static void
9390 {
9392 {
9394 {
9399 #ifdef HAVE_AS_SMALL_PIC_RELOCS
9401 ? AARCH64_CMODEL_SMALL_PIC
9403 #else
9405 #endif
9413 }
9414 }
9415 else
9417 }
9419 /* Implement TARGET_OPTION_SAVE. */
9421 static void
9423 {
9425 }
9427 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
9428 using the information saved in PTR. */
9430 static void
9432 {
9440 }
9442 /* Implement TARGET_OPTION_PRINT. */
9444 static void
9446 {
9457 }
9461 void
9463 {
9465 }
9467 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
9468 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
9469 make sure optab availability predicates are recomputed when necessary. */
9471 void
9473 {
9478 else
9480 }
9482 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
9483 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
9484 of the function, if such exists. This function may be called multiple
9485 times on a single function so use aarch64_previous_fndecl to avoid
9486 setting up identical state. */
9488 static void
9490 {
9494 tree old_tree = (aarch64_previous_fndecl
9500 /* If current function has no attributes but the previous one did,
9501 use the default node. */
9505 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
9506 the default have been handled by aarch64_save_restore_target_globals from
9507 aarch64_pragma_target_parse. */
9513 /* First set the target options. */
9517 }
9519 /* Enum describing the various ways we can handle attributes.
9520 In many cases we can reuse the generic option handling machinery. */
9522 enum aarch64_attr_opt_type
9523 {
9527 aarch64_attr_custom /* Attribute requires a custom handling function. */
9528 };
9530 /* All the information needed to handle a target attribute.
9531 NAME is the name of the attribute.
9532 ATTR_TYPE specifies the type of behavior of the attribute as described
9533 in the definition of enum aarch64_attr_opt_type.
9534 ALLOW_NEG is true if the attribute supports a "no-" form.
9535 HANDLER is the function that takes the attribute string and whether
9536 it is a pragma or attribute and handles the option. It is needed only
9537 when the ATTR_TYPE is aarch64_attr_custom.
9538 OPT_NUM is the enum specifying the option that the attribute modifies.
9539 This is needed for attributes that mirror the behavior of a command-line
9540 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
9541 aarch64_attr_enum. */
9543 struct aarch64_attribute_info
9544 {
9550 };
9552 /* Handle the ARCH_STR argument to the arch= target attribute.
9553 PRAGMA_OR_ATTR is used in potential error messages. */
9555 static bool
9557 {
9559 enum aarch64_parse_opt_result parse_res
9563 {
9568 }
9571 {
9585 }
9588 }
9590 /* Handle the argument CPU_STR to the cpu= target attribute.
9591 PRAGMA_OR_ATTR is used in potential error messages. */
9593 static bool
9595 {
9597 enum aarch64_parse_opt_result parse_res
9601 {
9609 }
9612 {
9626 }
9629 }
9631 /* Handle the argument STR to the tune= target attribute.
9632 PRAGMA_OR_ATTR is used in potential error messages. */
9634 static bool
9636 {
9638 enum aarch64_parse_opt_result parse_res
9642 {
9647 }
9650 {
9657 }
9660 }
9662 /* Parse an architecture extensions target attribute string specified in STR.
9663 For example "+fp+nosimd". Show any errors if needed. Return TRUE
9664 if successful. Update aarch64_isa_flags to reflect the ISA features
9665 modified.
9666 PRAGMA_OR_ATTR is used in potential error messages. */
9668 static bool
9670 {
9674 /* We allow "+nothing" in the beginning to clear out all architectural
9675 features if the user wants to handpick specific features. */
9677 {
9680 }
9685 {
9688 }
9691 {
9704 }
9707 }
9709 /* The target attributes that we support. On top of these we also support just
9710 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
9711 handled explicitly in aarch64_process_one_target_attr. */
9714 {
9716 OPT_mgeneral_regs_only },
9718 OPT_mfix_cortex_a53_835769 },
9720 OPT_mfix_cortex_a53_843419 },
9724 OPT_momit_leaf_frame_pointer },
9727 OPT_march_ },
9730 OPT_mtune_ },
9732 OPT_msign_return_address_ },
9734 };
9736 /* Parse ARG_STR which contains the definition of one target attribute.
9737 Show appropriate errors if any or return true if the attribute is valid.
9738 PRAGMA_OR_ATTR holds the string to use in error messages about whether
9739 we're processing a target attribute or pragma. */
9741 static bool
9743 {
9749 {
9752 }
9757 /* Skip leading whitespace. */
9759 str_to_check++;
9761 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
9762 It is easier to detect and handle it explicitly here rather than going
9763 through the machinery for the rest of the target attributes in this
9764 function. */
9769 {
9772 }
9775 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
9776 and point ARG to "foo". */
9778 {
9780 arg++;
9781 }
9785 {
9786 /* If the names don't match up, or the user has given an argument
9787 to an attribute that doesn't accept one, or didn't give an argument
9788 to an attribute that expects one, fail to match. */
9797 {
9801 }
9803 /* If the name matches but the attribute does not allow "no-" versions
9804 then we can't match. */
9806 {
9810 }
9813 {
9814 /* Has a custom handler registered.
9815 For example, cpu=, arch=, tune=. */
9822 /* Either set or unset a boolean option. */
9824 {
9832 }
9833 /* Set or unset a bit in the target_flags. aarch64_handle_option
9834 should know what mask to apply given the option number. */
9836 {
9838 /* We only need to specify the option number.
9839 aarch64_handle_option will know which mask to apply. */
9845 }
9846 /* Use the option setting machinery to set an option to an enum. */
9848 {
9855 {
9858 global_dc);
9859 }
9860 else
9861 {
9864 }
9866 }
9869 }
9870 }
9872 /* If we reached here we either have found an attribute and validated
9873 it or didn't match any. If we matched an attribute but its arguments
9874 were malformed we will have returned false already. */
9876 }
9878 /* Count how many times the character C appears in
9879 NULL-terminated string STR. */
9881 static unsigned int
9883 {
9886 {
9888 res++;
9890 str++;
9891 }
9894 }
9896 /* Parse the tree in ARGS that contains the target attribute information
9897 and update the global target options space. PRAGMA_OR_ATTR is a string
9898 to be used in error messages, specifying whether this is processing
9899 a target attribute or a target pragma. */
9901 bool
9903 {
9905 {
9906 do
9907 {
9910 {
9913 }
9918 }
9921 {
9924 }
9931 {
9934 }
9936 /* Used to catch empty spaces between commas i.e.
9937 attribute ((target ("attr1,,attr2"))). */
9940 /* Handle multiple target attributes separated by ','. */
9945 {
9946 num_attrs++;
9948 {
9951 }
9954 }
9957 {
9961 }
9964 }
9966 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
9967 process attribute ((target ("..."))). */
9969 static bool
9971 {
9974 tree old_optimize;
9978 /* If what we're processing is the current pragma string then the
9979 target option node is already stored in target_option_current_node
9980 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
9981 having to re-parse the string. This is especially useful to keep
9982 arm_neon.h compile times down since that header contains a lot
9983 of intrinsics enclosed in pragmas. */
9985 {
9988 }
9994 /* If the function changed the optimization levels as well as setting
9995 target options, start with the optimizations specified. */
10000 /* Save the current target options to restore at the end. */
10003 /* If fndecl already has some target attributes applied to it, unpack
10004 them so that we add this attribute on top of them, rather than
10005 overwriting them. */
10007 {
10013 }
10014 else
10021 /* Set up any additional state. */
10023 {
10025 /* Initialize SIMD builtins if we haven't already.
10026 Set current_target_pragma to NULL for the duration so that
10027 the builtin initialization code doesn't try to tag the functions
10028 being built with the attributes specified by any current pragma, thus
10029 going into an infinite recursion. */
10031 {
10036 }
10038 }
10039 else
10045 {
10050 }
10058 }
10060 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
10061 tri-bool options (yes, no, don't care) and the default value is
10062 DEF, determine whether to reject inlining. */
10064 static bool
10067 {
10068 /* If the callee doesn't care, always allow inlining. */
10072 /* If the caller doesn't care, always allow inlining. */
10076 /* Otherwise, allow inlining if either the callee and caller values
10077 agree, or if the callee is using the default value. */
10079 }
10081 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
10082 to inline CALLEE into CALLER based on target-specific info.
10083 Make sure that the caller and callee have compatible architectural
10084 features. Then go through the other possible target attributes
10085 and see if they can block inlining. Try not to reject always_inline
10086 callees unless they are incompatible architecturally. */
10088 static bool
10090 {
10094 /* If callee has no option attributes, then it is ok to inline. */
10105 /* Callee's ISA flags should be a subset of the caller's. */
10110 /* Allow non-strict aligned functions inlining into strict
10111 aligned ones. */
10121 /* If the architectural features match up and the callee is always_inline
10122 then the other attributes don't matter. */
10134 /* Honour explicit requests to workaround errata. */
10147 /* If the user explicitly specified -momit-leaf-frame-pointer for the
10148 caller and calle and they don't match up, reject inlining. */
10155 /* If the callee has specific tuning overrides, respect them. */
10160 /* If the user specified tuning override strings for the
10161 caller and callee and they don't match up, reject inlining.
10162 We just do a string compare here, we don't analyze the meaning
10163 of the string, as it would be too costly for little gain. */
10171 }
10173 /* Return true if SYMBOL_REF X binds locally. */
10175 static bool
10177 {
10181 }
10183 /* Return true if SYMBOL_REF X is thread local */
10184 static bool
10186 {
10194 }
10196 /* Classify a TLS symbol into one of the TLS kinds. */
10197 enum aarch64_symbol_type
10199 {
10203 {
10210 {
10216 }
10227 else
10236 }
10237 }
10239 /* Return the method that should be used to access SYMBOL_REF or
10240 LABEL_REF X. */
10242 enum aarch64_symbol_type
10244 {
10246 {
10248 {
10263 }
10264 }
10267 {
10272 {
10274 /* When we retrieve symbol + offset address, we have to make sure
10275 the offset does not cause overflow of the final address. But
10276 we have no way of knowing the address of symbol at compile time
10277 so we can't accurately say if the distance between the PC and
10278 symbol + offset is outside the addressible range of +/-1M in the
10279 TINY code model. So we rely on images not being greater than
10280 1M and cap the offset at 1M and anything beyond 1M will have to
10281 be loaded using an alternative mechanism. Furthermore if the
10282 symbol is a weak reference to something that isn't known to
10283 resolve to a symbol in this module, then force to memory. */
10291 /* Same reasoning as the tiny code model, but the offset cap here is
10292 4G. */
10313 /* This is alright even in PIC code as the constant
10314 pool reference is always PC relative and within
10315 the same translation unit. */
10318 else
10323 }
10324 }
10326 /* By default push everything into the constant pool. */
10328 }
10330 bool
10332 {
10334 }
10336 bool
10338 {
10346 }
10348 /* Return true if X holds either a quarter-precision or
10349 floating-point +0.0 constant. */
10350 static bool
10352 {
10356 /* This call determines which constants can be used in mov<mode>
10357 as integer moves instead of constant loads. */
10362 }
10364 static bool
10366 {
10367 /* Do not allow vector struct mode constants. We could support
10368 0 and -1 easily, but they need support in aarch64-simd.md. */
10372 /* For these cases we never want to use a literal load.
10373 As such we have to prevent the compiler from forcing these
10374 to memory. */
10387 /* Treat symbols as constants. Avoid TLS symbols as they are complex,
10388 so spilling them is better than rematerialization. */
10393 }
10395 rtx
10397 {
10403 /* Can return in any reg. */
10406 }
10408 /* On AAPCS systems, this is the "struct __va_list". */
10411 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
10412 Return the type to use as __builtin_va_list.
10414 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
10416 struct __va_list
10417 {
10418 void *__stack;
10419 void *__gr_top;
10420 void *__vr_top;
10421 int __gr_offs;
10422 int __vr_offs;
10423 }; */
10425 static tree
10427 {
10428 tree va_list_name;
10431 /* Create the type. */
10433 /* Give it the required name. */
10435 TYPE_DECL,
10437 va_list_type);
10442 /* Create the fields. */
10445 ptr_type_node);
10448 ptr_type_node);
10451 ptr_type_node);
10454 integer_type_node);
10457 integer_type_node);
10459 /* Tell tree-stdarg pass about our internal offset fields.
10460 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
10461 purpose to identify whether the code is updating va_list internal
10462 offset fields through irregular way. */
10484 /* Compute its layout. */
10488 }
10490 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
10491 static void
10493 {
10497 tree t;
10511 {
10514 }
10523 NULL_TREE);
10525 NULL_TREE);
10527 NULL_TREE);
10529 NULL_TREE);
10531 NULL_TREE);
10533 /* Emit code to initialize STACK, which points to the next varargs stack
10534 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
10535 by named arguments. STACK is 8-byte aligned. */
10542 /* Emit code to initialize GRTOP, the top of the GR save area.
10543 virtual_incoming_args_rtx should have been 16 byte aligned. */
10548 /* Emit code to initialize VRTOP, the top of the VR save area.
10549 This address is gr_save_area_bytes below GRTOP, rounded
10550 down to the next 16-byte boundary. */
10560 /* Emit code to initialize GROFF, the offset from GRTOP of the
10561 next GPR argument. */
10566 /* Likewise emit code to initialize VROFF, the offset from FTOP
10567 of the next VR argument. */
10571 }
10573 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
10575 static tree
10578 {
10579 tree addr;
10585 machine_mode mode;
10612 type,
10616 {
10617 /* TYPE passed in fp/simd registers. */
10629 {
10632 }
10635 {
10637 }
10638 }
10639 else
10640 {
10641 /* TYPE passed in general registers. */
10654 {
10656 }
10657 }
10659 /* Get a local temporary for the field value. */
10662 /* Emit code to branch if off >= 0. */
10668 {
10669 /* Emit: offs = (offs + 15) & -16. */
10675 }
10676 else
10679 /* Update ap.__[g|v]r_offs */
10684 /* String up. */
10688 /* [cond2] if (ap.__[g|v]r_offs > 0) */
10693 /* String up: make sure the assignment happens before the use. */
10697 /* Prepare the trees handling the argument that is passed on the stack;
10698 the top level node will store in ON_STACK. */
10701 {
10702 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
10710 }
10711 else
10713 /* Advance ap.__stack */
10721 /* String up roundup and advance. */
10724 /* String up with arg */
10726 /* Big-endianness related address adjustment. */
10729 {
10733 }
10738 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
10748 {
10749 /* type ha; // treat as "struct {ftype field[n];}"
10750 ... [computing offs]
10751 for (i = 0; i <nregs; ++i, offs += 16)
10752 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
10753 return ha; */
10757 /* Declare a local variable. */
10761 /* Establish the base type. */
10763 {
10782 {
10786 }
10790 }
10792 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
10800 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
10802 {
10812 }
10816 }
10826 }
10828 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
10830 static void
10834 {
10836 CUMULATIVE_ARGS local_cum;
10840 /* The caller has advanced CUM up to, but not beyond, the last named
10841 argument. Advance a local copy of CUM past the last "real" named
10842 argument, to find out how many registers are left over. */
10846 /* Found out how many registers we need to save.
10847 Honor tree-stdvar analysis results. */
10856 {
10859 }
10862 {
10864 {
10867 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
10875 }
10877 {
10878 /* We can't use move_block_from_reg, because it will use
10879 the wrong mode, storing D regs only. */
10883 /* Set OFF to the offset from virtual_incoming_args_rtx of
10884 the first vector register. The VR save area lies below
10885 the GR one, and is aligned to 16 bytes. */
10892 {
10900 }
10901 }
10902 }
10904 /* We don't save the size into *PRETEND_SIZE because we want to avoid
10905 any complication of having crtl->args.pretend_args_size changed. */
10910 }
10912 static void
10914 {
10917 {
10919 {
10922 }
10923 }
10924 }
10926 /* Walk down the type tree of TYPE counting consecutive base elements.
10927 If *MODEP is VOIDmode, then set it to the first valid floating point
10928 type. If a non-floating point type is found, or if a floating point
10929 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
10930 otherwise return the count in the sub-tree. */
10931 static int
10933 {
10934 machine_mode mode;
10935 HOST_WIDE_INT size;
10938 {
10968 /* Use V2SImode and V4SImode as representatives of all 64-bit
10969 and 128-bit vector types. */
10972 {
10981 }
10986 /* Vector modes are considered to be opaque: two vectors are
10987 equivalent for the purposes of being homogeneous aggregates
10988 if they are the same size. */
10995 {
10999 /* Can't handle incomplete types nor sizes that are not
11000 fixed. */
11007 || !index
11018 /* There must be no padding. */
11023 }
11026 {
11029 tree field;
11031 /* Can't handle incomplete types nor sizes that are not
11032 fixed. */
11038 {
11046 }
11048 /* There must be no padding. */
11053 }
11057 {
11058 /* These aren't very interesting except in a degenerate case. */
11061 tree field;
11063 /* Can't handle incomplete types nor sizes that are not
11064 fixed. */
11070 {
11078 }
11080 /* There must be no padding. */
11085 }
11089 }
11092 }
11094 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
11095 type as described in AAPCS64 \S 4.1.2.
11097 See the comment above aarch64_composite_type_p for the notes on MODE. */
11099 static bool
11101 machine_mode mode)
11102 {
11112 }
11114 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
11115 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
11116 array types. The C99 floating-point complex types are also considered
11117 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
11118 types, which are GCC extensions and out of the scope of AAPCS64, are
11119 treated as composite types here as well.
11121 Note that MODE itself is not sufficient in determining whether a type
11122 is such a composite type or not. This is because
11123 stor-layout.c:compute_record_mode may have already changed the MODE
11124 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
11125 structure with only one field may have its MODE set to the mode of the
11126 field. Also an integer mode whose size matches the size of the
11127 RECORD_TYPE type may be used to substitute the original mode
11128 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
11129 solely relied on. */
11131 static bool
11133 machine_mode mode)
11134 {
11147 }
11149 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
11150 shall be passed or returned in simd/fp register(s) (providing these
11151 parameter passing registers are available).
11153 Upon successful return, *COUNT returns the number of needed registers,
11154 *BASE_MODE returns the mode of the individual register and when IS_HAF
11155 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
11156 floating-point aggregate or a homogeneous short-vector aggregate. */
11158 static bool
11160 const_tree type,
11164 {
11172 {
11175 }
11177 {
11181 }
11183 {
11187 {
11190 }
11191 else
11193 }
11194 else
11199 }
11201 /* Implement TARGET_STRUCT_VALUE_RTX. */
11203 static rtx
11206 {
11208 }
11210 /* Implements target hook vector_mode_supported_p. */
11211 static bool
11213 {
11225 }
11227 /* Return appropriate SIMD container
11228 for MODE within a vector of WIDTH bits. */
11229 static machine_mode
11231 {
11234 {
11237 {
11254 }
11255 else
11257 {
11270 }
11271 }
11273 }
11275 /* Return 128-bit container as the preferred SIMD mode for MODE. */
11276 static machine_mode
11278 {
11280 }
11282 /* Return the bitmask of possible vector sizes for the vectorizer
11283 to iterate over. */
11284 static unsigned int
11286 {
11288 }
11290 /* Implement TARGET_MANGLE_TYPE. */
11294 {
11295 /* The AArch64 ABI documents say that "__va_list" has to be
11296 managled as if it is in the "std" namespace. */
11300 /* Half-precision float. */
11304 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
11305 builtin types. */
11309 /* Use the default mangling. */
11311 }
11313 /* Find the first rtx_insn before insn that will generate an assembly
11314 instruction. */
11318 {
11322 do
11323 {
11325 }
11329 }
11331 static bool
11333 {
11335 /* A number of these may be AArch32 only. */
11340 };
11343 {
11346 }
11349 }
11351 /* Check if there is a register dependency between a load and the insn
11352 for which we hold recog_data. */
11354 static bool
11356 {
11357 rtx load_reg;
11367 {
11373 }
11375 }
11378 /* When working around the Cortex-A53 erratum 835769,
11379 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
11380 instruction and has a preceding memory instruction such that a NOP
11381 should be inserted between them. */
11383 bool
11385 {
11388 rtx body;
11401 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
11402 Restore recog state to INSN to avoid state corruption. */
11410 /* If the previous insn is a memory op and there is no dependency between
11411 it and the DImode madd, emit a NOP between them. If body is NULL then we
11412 have a complex memory operation, probably a load/store pair.
11413 Be conservative for now and emit a NOP. */
11420 }
11423 /* Implement FINAL_PRESCAN_INSN. */
11425 void
11427 {
11430 }
11433 /* Return the equivalent letter for size. */
11434 static char
11436 {
11438 {
11444 }
11445 }
11447 /* Return true iff x is a uniform vector of floating-point
11448 constants, and the constant can be represented in
11449 quarter-precision form. Note, as aarch64_float_const_representable
11450 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
11451 static bool
11453 {
11454 rtx elt;
11458 }
11460 /* Return true for valid and false for invalid. */
11461 bool
11464 {
11465 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
11466 matches = 1; \
11467 for (i = 0; i < idx; i += (STRIDE)) \
11468 if (!(TEST)) \
11469 matches = 0; \
11470 if (matches) \
11471 { \
11472 immtype = (CLASS); \
11473 elsize = (ELSIZE); \
11474 eshift = (SHIFT); \
11475 emvn = (NEG); \
11476 break; \
11477 }
11487 {
11493 {
11495 scalar_float_mode elt_mode
11502 }
11505 }
11507 /* Splat vector constant out into a byte vector. */
11509 {
11510 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
11511 it must be laid out in the vector register in reverse order. */
11519 {
11522 }
11524 }
11526 /* Sanity check. */
11529 do
11530 {
11579 }
11586 {
11596 /* Un-invert bytes of recognized vector, if necessary. */
11602 {
11603 /* FIXME: Broken on 32-bit H_W_I hosts. */
11612 }
11613 else
11614 {
11618 /* Construct 'abcdefgh' because the assembler cannot handle
11619 generic constants. */
11624 }
11625 }
11628 #undef CHECK
11629 }
11631 /* Check of immediate shift constants are within range. */
11632 bool
11634 {
11638 else
11640 }
11642 /* Return true if X is a uniform vector where all elements
11643 are either the floating-point constant 0.0 or the
11644 integer constant 0. */
11645 bool
11647 {
11649 }
11652 /* Return the bitmask CONST_INT to select the bits required by a zero extract
11653 operation of width WIDTH at bit position POS. */
11655 rtx
11657 {
11661 unsigned HOST_WIDE_INT mask
11664 }
11666 bool
11668 {
11681 }
11683 /* Return a const_int vector of VAL. */
11684 rtx
11686 {
11697 }
11699 /* Check OP is a legal scalar immediate for the MOVI instruction. */
11701 bool
11703 {
11704 machine_mode vmode;
11710 }
11712 /* Construct and return a PARALLEL RTX vector with elements numbering the
11713 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
11714 the vector - from the perspective of the architecture. This does not
11715 line up with GCC's perspective on lane numbers, so we end up with
11716 different masks depending on our target endian-ness. The diagram
11717 below may help. We must draw the distinction when building masks
11718 which select one half of the vector. An instruction selecting
11719 architectural low-lanes for a big-endian target, must be described using
11720 a mask selecting GCC high-lanes.
11722 Big-Endian Little-Endian
11724 GCC 0 1 2 3 3 2 1 0
11725 | x | x | x | x | | x | x | x | x |
11726 Architecture 3 2 1 0 3 2 1 0
11728 Low Mask: { 2, 3 } { 0, 1 }
11729 High Mask: { 0, 1 } { 2, 3 }
11730 */
11732 rtx
11734 {
11740 rtx t1;
11745 else
11753 }
11755 /* Check OP for validity as a PARALLEL RTX vector with elements
11756 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
11757 from the perspective of the architecture. See the diagram above
11758 aarch64_simd_vect_par_cnst_half for more details. */
11760 bool
11763 {
11776 {
11783 }
11785 }
11787 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
11788 HIGH (exclusive). */
11789 void
11791 const_tree exp)
11792 {
11793 HOST_WIDE_INT lane;
11798 {
11801 else
11803 }
11804 }
11806 /* Return TRUE if OP is a valid vector addressing mode. */
11807 bool
11809 {
11812 }
11814 /* Emit a register copy from operand to operand, taking care not to
11815 early-clobber source registers in the process.
11817 COUNT is the number of components into which the copy needs to be
11818 decomposed. */
11819 void
11822 {
11832 else
11836 }
11838 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
11839 one of VSTRUCT modes: OI, CI, or XI. */
11840 int
11842 {
11844 }
11846 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
11847 alignment of a vector to 128 bits. */
11848 static HOST_WIDE_INT
11850 {
11853 }
11855 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
11856 static bool
11858 {
11862 /* We guarantee alignment for vectors up to 128-bits. */
11867 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
11869 }
11871 /* Return true if the vector misalignment factor is supported by the
11872 target. */
11873 static bool
11877 {
11879 {
11880 /* Return if movmisalign pattern is not supported for this mode. */
11885 {
11886 /* Misalignment factor is unknown at compile time but we know
11887 it's word aligned. */
11889 {
11894 }
11896 }
11897 }
11899 is_packed);
11900 }
11902 /* If VALS is a vector constant that can be loaded into a register
11903 using DUP, generate instructions to do so and return an RTX to
11904 assign to the register. Otherwise return NULL_RTX. */
11905 static rtx
11907 {
11910 rtx x;
11915 /* We can load this constant by using DUP and a constant in a
11916 single ARM register. This will be cheaper than a vector
11917 load. */
11920 }
11923 /* Generate code to load VALS, which is a PARALLEL containing only
11924 constants (for vec_init) or CONST_VECTOR, efficiently into a
11925 register. Returns an RTX to copy into the register, or NULL_RTX
11926 for a PARALLEL that can not be converted into a CONST_VECTOR. */
11927 static rtx
11929 {
11931 rtx const_dup;
11940 {
11941 /* A CONST_VECTOR must contain only CONST_INTs and
11942 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
11943 Only store valid constants in a CONST_VECTOR. */
11945 {
11948 n_const++;
11949 }
11952 }
11953 else
11958 /* Load using MOVI/MVNI. */
11961 /* Loaded using DUP. */
11964 /* Load from constant pool. We can not take advantage of single-cycle
11965 LD1 because we need a PC-relative addressing mode. */
11967 else
11968 /* A PARALLEL containing something not valid inside CONST_VECTOR.
11969 We can not construct an initializer. */
11971 }
11973 /* Expand a vector initialisation sequence, such that TARGET is
11974 initialised to contain VALS. */
11976 void
11978 {
11981 /* The number of vector elements. */
11983 /* The number of vector elements which are not constant. */
11986 /* The first element of vals. */
11990 /* Count the number of variable elements to initialise. */
11992 {
11996 else
12000 }
12002 /* No variable elements, hand off to aarch64_simd_make_constant which knows
12003 how best to handle this. */
12005 {
12008 {
12011 }
12012 }
12014 /* Splat a single non-constant element if we can. */
12016 {
12020 }
12025 /* If there are only variable elements, try to optimize
12026 the insertion using dup for the most common element
12027 followed by insertions. */
12029 /* The algorithm will fill matches[*][0] with the earliest matching element,
12030 and matches[X][1] with the count of duplicate elements (if X is the
12031 earliest element which has duplicates). */
12034 {
12037 {
12039 {
12041 {
12045 }
12046 }
12047 }
12052 {
12055 }
12057 /* Create a duplicate of the most common element. */
12061 /* Insert the rest. */
12063 {
12069 }
12071 }
12073 /* Initialise a vector which is part-variable. We want to first try
12074 to build those lanes which are constant in the most efficient way we
12075 can. */
12077 {
12080 /* Load constant part of vector. We really don't care what goes into the
12081 parts we will overwrite, but we're more likely to be able to load the
12082 constant efficiently if it has fewer, larger, repeating parts
12083 (see aarch64_simd_valid_immediate). */
12085 {
12091 {
12092 /* Look in the copied vector, as more elements are const. */
12095 {
12098 }
12099 }
12101 }
12103 }
12105 /* Insert the variable lanes directly. */
12107 {
12113 }
12114 }
12116 static unsigned HOST_WIDE_INT
12118 {
12119 return
12120 (!SHIFT_COUNT_TRUNCATED
12123 }
12125 /* Select a format to encode pointers in exception handling data. */
12126 int
12128 {
12131 {
12137 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
12138 for everything. */
12142 /* No assumptions here. 8-byte relocs required. */
12145 }
12147 }
12149 /* The last .arch and .tune assembly strings that we printed. */
12153 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
12154 by the function fndecl. */
12156 void
12158 tree fndecl)
12159 {
12165 else
12176 /* Only update the assembler .arch string if it is distinct from the last
12177 such string we printed. */
12180 {
12183 }
12185 /* Print the cpu name we're tuning for in the comments, might be
12186 useful to readers of the generated asm. Do it only when it changes
12187 from function to function and verbose assembly is requested. */
12192 {
12196 }
12198 /* Don't forget the type directive for ELF. */
12201 }
12203 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
12205 static void
12207 {
12224 }
12226 /* Emit load exclusive. */
12228 static void
12231 {
12235 {
12242 }
12245 }
12247 /* Emit store exclusive. */
12249 static void
12252 {
12256 {
12263 }
12266 }
12268 /* Mark the previous jump instruction as unlikely. */
12270 static void
12272 {
12275 }
12277 /* Expand a compare and swap pattern. */
12279 void
12281 {
12286 gen_cas_fn gen;
12288 {
12289 gen_aarch64_compare_and_swapqi,
12290 gen_aarch64_compare_and_swaphi,
12291 gen_aarch64_compare_and_swapsi,
12292 gen_aarch64_compare_and_swapdi
12293 };
12295 {
12296 gen_aarch64_compare_and_swapqi_lse,
12297 gen_aarch64_compare_and_swaphi_lse,
12298 gen_aarch64_compare_and_swapsi_lse,
12299 gen_aarch64_compare_and_swapdi_lse
12300 };
12313 /* Normally the succ memory model must be stronger than fail, but in the
12314 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
12315 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
12322 {
12325 /* For short modes, we're going to perform the comparison in SImode,
12326 so do the zero-extension now. */
12330 /* Fall through. */
12334 /* Force the value into a register if needed. */
12341 }
12344 {
12351 }
12354 else
12365 }
12367 /* Test whether the target supports using a atomic load-operate instruction.
12368 CODE is the operation and AFTER is TRUE if the data in memory after the
12369 operation should be returned and FALSE if the data before the operation
12370 should be returned. Returns FALSE if the operation isn't supported by the
12371 architecture. */
12373 bool
12375 {
12380 {
12390 }
12391 }
12393 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
12394 sequence implementing an atomic operation. */
12396 static void
12398 {
12405 {
12407 }
12408 }
12410 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
12411 for the data in memory. EXPECTED is the value expected to be in memory.
12412 DESIRED is the value to store to memory. MEM is the memory location. MODEL
12413 is the memory ordering to use. */
12415 void
12418 rtx model)
12419 {
12421 machine_mode mode;
12426 {
12433 }
12435 /* Move the expected value into the CAS destination register. */
12438 /* Emit the CAS. */
12441 /* Compare the expected value with the value loaded by the CAS, to establish
12442 whether the swap was made. */
12444 }
12446 /* Split a compare and swap pattern. */
12448 void
12450 {
12452 machine_mode mode;
12457 rtx model_rtx;
12469 /* When OLDVAL is zero and we want the strong version we can emit a tighter
12470 loop:
12471 .label1:
12472 LD[A]XR rval, [mem]
12473 CBNZ rval, .label2
12474 ST[L]XR scratch, newval, [mem]
12475 CBNZ scratch, .label1
12476 .label2:
12477 CMP rval, 0. */
12482 {
12485 }
12488 /* The initial load can be relaxed for a __sync operation since a final
12489 barrier will be emitted to stop code hoisting. */
12493 else
12497 {
12502 }
12503 else
12504 {
12510 }
12515 {
12520 }
12521 else
12522 {
12526 }
12529 /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
12530 to set the condition flags. If this is not used it will be removed by
12531 later passes. */
12533 {
12537 }
12538 /* Emit any final barrier needed for a __sync operation. */
12541 }
12543 /* Emit a BIC instruction. */
12545 static void
12547 {
12552 {
12557 }
12560 }
12562 /* Emit an atomic swap. */
12564 static void
12567 {
12571 {
12578 }
12581 }
12583 /* Operations supported by aarch64_emit_atomic_load_op. */
12585 enum aarch64_atomic_load_op_code
12586 {
12590 AARCH64_LDOP_BIC /* A & ~B */
12591 };
12593 /* Emit an atomic load-operate. */
12595 static void
12599 {
12602 {
12603 gen_aarch64_atomic_loadaddqi,
12604 gen_aarch64_atomic_loadaddhi,
12605 gen_aarch64_atomic_loadaddsi,
12606 gen_aarch64_atomic_loadadddi
12607 };
12609 {
12610 gen_aarch64_atomic_loadeorqi,
12611 gen_aarch64_atomic_loadeorhi,
12612 gen_aarch64_atomic_loadeorsi,
12613 gen_aarch64_atomic_loadeordi
12614 };
12616 {
12617 gen_aarch64_atomic_loadsetqi,
12618 gen_aarch64_atomic_loadsethi,
12619 gen_aarch64_atomic_loadsetsi,
12620 gen_aarch64_atomic_loadsetdi
12621 };
12623 {
12624 gen_aarch64_atomic_loadclrqi,
12625 gen_aarch64_atomic_loadclrhi,
12626 gen_aarch64_atomic_loadclrsi,
12627 gen_aarch64_atomic_loadclrdi
12628 };
12629 aarch64_atomic_load_op_fn gen;
12633 {
12640 }
12643 {
12650 }
12653 }
12655 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
12656 location to store the data read from memory. OUT_RESULT is the location to
12657 store the result of the operation. MEM is the memory location to read and
12658 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
12659 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
12660 be NULL. */
12662 void
12665 {
12669 aarch64_atomic_load_op_code ldop_code;
12670 rtx src;
12671 rtx x;
12679 /* Make sure the value is in a register, putting it into a destination
12680 register if it needs to be manipulated. */
12683 {
12686 }
12687 else
12691 /* Preprocess the data for the operation as necessary. If the operation is
12692 a SET then emit a swap instruction and finish. */
12694 {
12700 /* Negate the value and treat it as a PLUS. */
12701 {
12702 rtx neg_src;
12704 /* Resize the value if necessary. */
12713 }
12714 /* Fall-through. */
12728 {
12729 rtx not_src;
12731 /* Resize the value if necessary. */
12740 }
12745 /* The operation can't be done with atomic instructions. */
12747 }
12751 /* If necessary, calculate the data in memory after the update by redoing the
12752 operation from values in registers. */
12757 {
12761 }
12766 {
12782 }
12787 }
12789 /* Split an atomic operation. */
12791 void
12794 {
12800 rtx x;
12802 /* Split the atomic operation into a sequence. */
12810 else
12814 /* The initial load can be relaxed for a __sync operation since a final
12815 barrier will be emitted to stop code hoisting. */
12819 else
12823 {
12837 {
12840 }
12841 /* Fall through. */
12847 }
12857 /* Emit any final barrier needed for a __sync operation. */
12860 }
12862 static void
12864 {
12865 /* Half-precision float operations. The compiler handles all operations
12866 with NULL libfuncs by converting to SFmode. */
12868 /* Conversions. */
12872 /* Arithmetic. */
12879 /* Comparisons. */
12887 }
12889 /* Target hook for c_mode_for_suffix. */
12890 static machine_mode
12892 {
12897 }
12899 /* We can only represent floating point constants which will fit in
12900 "quarter-precision" values. These values are characterised by
12901 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
12902 by:
12904 (-1)^s * (n/16) * 2^r
12906 Where:
12907 's' is the sign bit.
12908 'n' is an integer in the range 16 <= n <= 31.
12909 'r' is an integer in the range -3 <= r <= 4. */
12911 /* Return true iff X can be represented by a quarter-precision
12912 floating point immediate operand X. Note, we cannot represent 0.0. */
12913 bool
12915 {
12916 /* This represents our current view of how many bits
12917 make up the mantissa. */
12927 /* We don't support HFmode constants yet. */
12933 /* We cannot represent infinities, NaNs or +/-zero. We won't
12934 know if we have +zero until we analyse the mantissa, but we
12935 can reject the other invalid values. */
12940 /* Extract exponent. */
12944 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
12945 highest (sign) bit, with a fixed binary point at bit point_pos.
12946 m1 holds the low part of the mantissa, m2 the high part.
12947 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
12948 bits for the mantissa, this can fail (low bits will be lost). */
12952 /* If the low part of the mantissa has bits set we cannot represent
12953 the value. */
12956 /* We have rejected the lower HOST_WIDE_INT, so update our
12957 understanding of how many bits lie in the mantissa and
12958 look only at the high HOST_WIDE_INT. */
12962 /* We can only represent values with a mantissa of the form 1.xxxx. */
12967 /* Having filtered unrepresentable values, we may now remove all
12968 but the highest 5 bits. */
12971 /* We cannot represent the value 0.0, so reject it. This is handled
12972 elsewhere. */
12976 /* Then, as bit 4 is always set, we can mask it off, leaving
12977 the mantissa in the range [0, 15]. */
12981 /* GCC internally does not use IEEE754-like encoding (where normalized
12982 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
12983 Our mantissa values are shifted 4 places to the left relative to
12984 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
12985 by 5 places to correct for GCC's representation. */
12989 }
12993 machine_mode mode,
12995 {
13005 /* This will return true to show const_vector is legal for use as either
13006 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
13007 also update INFO to show how the immediate should be generated. */
13016 {
13018 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
13019 move immediate path. */
13022 else
13023 {
13032 else
13036 }
13037 }
13050 else
13054 }
13058 {
13060 /* If a floating point number was passed and we desire to use it in an
13061 integer mode do the conversion to integer. */
13063 {
13068 }
13070 machine_mode vmode;
13071 /* use a 64 bit mode for everything except for DI/DF mode, where we use
13072 a 128 bit vector mode. */
13079 }
13081 /* Split operands into moves from op[1] + op[2] into op[0]. */
13083 void
13085 {
13096 {
13097 /* No-op move. Can't split to nothing; emit something. */
13100 }
13102 /* Preserve register attributes for variable tracking. */
13107 /* Special case of reversed high/low parts. */
13110 {
13114 }
13116 {
13117 /* Try to avoid unnecessary moves if part of the result
13118 is in the right place already. */
13123 }
13124 else
13125 {
13130 }
13131 }
13133 /* vec_perm support. */
13135 #define MAX_VECT_LEN 16
13137 struct expand_vec_perm_d
13138 {
13141 machine_mode vmode;
13145 };
13147 /* Generate a variable permutation. */
13149 static void
13151 {
13162 {
13164 {
13165 /* Expand the argument to a V16QI mode by duplicating it. */
13169 }
13170 else
13171 {
13173 }
13174 }
13175 else
13176 {
13177 rtx pair;
13180 {
13184 }
13185 else
13186 {
13190 }
13191 }
13192 }
13194 void
13196 {
13200 rtx mask;
13202 /* The TBL instruction does not use a modulo index, so we must take care
13203 of that ourselves. */
13208 /* For big-endian, we also need to reverse the index within the vector
13209 (but not which vector). */
13211 {
13212 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
13217 }
13219 }
13221 /* Recognize patterns suitable for the TRN instructions. */
13222 static bool
13224 {
13233 /* Note that these are little-endian tests.
13234 We correct for big-endian later. */
13239 else
13244 {
13249 }
13251 /* Success! */
13258 {
13261 }
13265 {
13267 {
13282 }
13283 }
13284 else
13285 {
13287 {
13302 }
13303 }
13307 }
13309 /* Recognize patterns suitable for the UZP instructions. */
13310 static bool
13312 {
13321 /* Note that these are little-endian tests.
13322 We correct for big-endian later. */
13327 else
13332 {
13336 }
13338 /* Success! */
13345 {
13348 }
13352 {
13354 {
13369 }
13370 }
13371 else
13372 {
13374 {
13389 }
13390 }
13394 }
13396 /* Recognize patterns suitable for the ZIP instructions. */
13397 static bool
13399 {
13408 /* Note that these are little-endian tests.
13409 We correct for big-endian later. */
13412 /* Do Nothing. */
13413 ;
13416 else
13421 {
13428 }
13430 /* Success! */
13437 {
13440 }
13444 {
13446 {
13461 }
13462 }
13463 else
13464 {
13466 {
13481 }
13482 }
13486 }
13488 /* Recognize patterns for the EXT insn. */
13490 static bool
13492 {
13495 rtx offset;
13499 /* Check if the extracted indices are increasing by one. */
13501 {
13504 {
13505 /* We'll pass the same vector in twice, so allow indices to wrap. */
13507 }
13510 }
13513 {
13528 }
13530 /* Success! */
13534 /* The case where (location == 0) is a no-op for both big- and little-endian,
13535 and is removed by the mid-end at optimization levels -O1 and higher. */
13538 {
13539 /* After setup, we want the high elements of the first vector (stored
13540 at the LSB end of the register), and the low elements of the second
13541 vector (stored at the MSB end of the register). So swap. */
13543 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
13545 }
13550 }
13552 /* Recognize patterns for the REV insns. */
13554 static bool
13556 {
13565 {
13568 {
13573 }
13577 {
13584 }
13588 {
13601 }
13605 }
13609 {
13610 /* This is guaranteed to be true as the value of diff
13611 is 7, 3, 1 and we should have enough elements in the
13612 queue to generate this. Getting a vector mask with a
13613 value of diff other than these values implies that
13614 something is wrong by the time we get here. */
13618 }
13620 /* Success! */
13626 }
13628 static bool
13630 {
13633 rtx in0;
13636 rtx lane;
13640 {
13643 }
13645 /* The generic preparation in aarch64_expand_vec_perm_const_1
13646 swaps the operand order and the permute indices if it finds
13647 d->perm[0] to be in the second operand. Thus, we can always
13648 use d->op0 and need not do any extra arithmetic to get the
13649 correct lane number. */
13654 {
13669 }
13673 }
13675 static bool
13677 {
13685 /* Generic code will try constant permutation twice. Once with the
13686 original mode and again with the elements lowered to QImode.
13687 So wait and don't do the selector expansion ourselves. */
13692 {
13695 /* If big-endian and two vectors we end up with a weird mixed-endian
13696 mode on NEON. Reverse the index within each word but not the word
13697 itself. */
13700 }
13706 }
13708 static bool
13710 {
13711 /* The pattern matching functions above are written to look for a small
13712 number to begin the sequence (0, 1, N/2). If we begin with an index
13713 from the second operand, we can swap the operands. */
13715 {
13723 }
13726 {
13740 }
13742 }
13744 /* Expand a vec_perm_const pattern. */
13746 bool
13748 {
13762 {
13767 }
13770 {
13779 /* The elements of PERM do not suggest that only the first operand
13780 is used, but both operands are identical. Allow easier matching
13781 of the permutation by folding the permutation into the single
13782 input vector. */
13783 /* Fall Through. */
13795 }
13798 }
13800 static bool
13803 {
13813 /* Calculate whether all elements are in one vector. */
13815 {
13819 }
13821 /* If all elements are from the second vector, reindex as if from the
13822 first vector. */
13827 /* Check whether the mask can be applied to a single vector. */
13840 }
13842 rtx
13844 {
13845 /* We have to reverse each vector because we dont have
13846 a permuted load that can reverse-load according to ABI rules. */
13847 rtx mask;
13861 }
13863 /* Implement TARGET_MODES_TIEABLE_P. In principle we should always return
13864 true. However due to issues with register allocation it is preferable
13865 to avoid tieing integer scalar and FP scalar modes. Executing integer
13866 operations in general registers is better than treating them as scalar
13867 vector operations. This reduces latency and avoids redundant int<->FP
13868 moves. So tie modes if they are either the same class, or vector modes
13869 with other vector modes, vector structs or any scalar mode. */
13871 static bool
13873 {
13877 /* We specifically want to allow elements of "structure" modes to
13878 be tieable to the structure. This more general condition allows
13879 other rarer situations too. */
13883 /* Also allow any scalar modes with vectors. */
13889 }
13891 /* Return a new RTX holding the result of moving POINTER forward by
13892 AMOUNT bytes. */
13894 static rtx
13896 {
13901 }
13903 /* Return a new RTX holding the result of moving POINTER forward by the
13904 size of the mode it points to. */
13906 static rtx
13908 {
13912 }
13914 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
13915 MODE bytes. */
13917 static void
13919 machine_mode mode)
13920 {
13923 /* "Cast" the pointers to the correct mode. */
13926 /* Emit the memcpy. */
13929 /* Move the pointers forward. */
13932 }
13934 /* Expand movmem, as if from a __builtin_memcpy. Return true if
13935 we succeed, otherwise return false. */
13937 bool
13939 {
13943 rtx base;
13946 /* When optimizing for size, give a better estimate of the length of a
13947 memcpy call, but use the default otherwise. */
13950 /* We can't do anything smart if the amount to copy is not constant. */
13956 /* Try to keep the number of instructions low. For cases below 16 bytes we
13957 need to make at most two moves. For cases above 16 bytes it will be one
13958 move for each 16 byte chunk, then at most two additional moves. */
13968 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
13969 1-byte chunk. */
13971 {
13973 {
13976 }
13982 }
13984 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
13985 4-byte chunk, partially overlapping with the previously copied chunk. */
13987 {
13991 {
13997 }
13999 }
14001 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
14002 them, then (if applicable) an 8-byte chunk. */
14004 {
14006 {
14009 }
14010 else
14011 {
14014 }
14015 }
14017 /* Finish the final bytes of the copy. We can always do this in one
14018 instruction. We either copy the exact amount we need, or partially
14019 overlap with the previous chunk we copied and copy 8-bytes. */
14028 else
14029 {
14031 {
14035 }
14036 else
14037 {
14043 }
14044 }
14047 }
14049 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
14050 SImode stores. Handle the case when the constant has identical
14051 bottom and top halves. This is beneficial when the two stores can be
14052 merged into an STP and we avoid synthesising potentially expensive
14053 immediates twice. Return true if such a split is possible. */
14055 bool
14057 {
14066 unsigned int orig_cost
14068 unsigned int lo_cost
14071 /* We want to transform:
14072 MOV x1, 49370
14073 MOVK x1, 0x140, lsl 16
14074 MOVK x1, 0xc0da, lsl 32
14075 MOVK x1, 0x140, lsl 48
14076 STR x1, [x0]
14077 into:
14078 MOV w1, 49370
14079 MOVK w1, 0x140, lsl 16
14080 STP w1, w1, [x0]
14081 So we want to perform this only when we save two instructions
14082 or more. When optimizing for size, however, accept any code size
14083 savings we can. */
14098 /* Don't emit an explicit store pair as this may not be always profitable.
14099 Let the sched-fusion logic decide whether to merge them. */
14104 }
14106 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
14108 static unsigned HOST_WIDE_INT
14110 {
14112 }
14114 static bool
14119 {
14120 /* STORE_BY_PIECES can be used when copying a constant string, but
14121 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
14122 For now we always fail this and let the move_by_pieces code copy
14123 the string from read-only memory. */
14128 }
14130 static rtx
14133 {
14137 insn_code icode;
14148 {
14176 }
14181 {
14184 }
14193 {
14196 }
14202 }
14204 static rtx
14207 {
14211 insn_code icode;
14223 {
14251 }
14256 {
14259 }
14267 {
14272 }
14283 {
14286 }
14292 }
14294 #undef TARGET_GEN_CCMP_FIRST
14295 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
14297 #undef TARGET_GEN_CCMP_NEXT
14298 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
14300 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
14301 instruction fusion of some sort. */
14303 static bool
14305 {
14307 }
14310 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
14311 should be kept together during scheduling. */
14313 static bool
14315 {
14316 rtx set_dest;
14319 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
14326 {
14327 /* We are trying to match:
14328 prev (mov) == (set (reg r0) (const_int imm16))
14329 curr (movk) == (set (zero_extract (reg r0)
14330 (const_int 16)
14331 (const_int 16))
14332 (const_int imm16_1)) */
14344 {
14346 }
14347 }
14350 {
14352 /* We're trying to match:
14353 prev (adrp) == (set (reg r1)
14354 (high (symbol_ref ("SYM"))))
14355 curr (add) == (set (reg r0)
14356 (lo_sum (reg r1)
14357 (symbol_ref ("SYM"))))
14358 Note that r0 need not necessarily be the same as r1, especially
14359 during pre-regalloc scheduling. */
14363 {
14371 }
14372 }
14375 {
14377 /* We're trying to match:
14378 prev (movk) == (set (zero_extract (reg r0)
14379 (const_int 16)
14380 (const_int 32))
14381 (const_int imm16_1))
14382 curr (movk) == (set (zero_extract (reg r0)
14383 (const_int 16)
14384 (const_int 48))
14385 (const_int imm16_2)) */
14401 }
14403 {
14404 /* We're trying to match:
14405 prev (adrp) == (set (reg r0)
14406 (high (symbol_ref ("SYM"))))
14407 curr (ldr) == (set (reg r1)
14408 (mem (lo_sum (reg r0)
14409 (symbol_ref ("SYM")))))
14410 or
14411 curr (ldr) == (set (reg r1)
14412 (zero_extend (mem
14413 (lo_sum (reg r0)
14414 (symbol_ref ("SYM")))))) */
14417 {
14430 }
14431 }
14439 {
14443 rtx cc_reg_1;
14448 && prev
14450 {
14451 /* FIXME: this misses some which is considered simple arthematic
14452 instructions for ThunderX. Simple shifts are missed here. */
14458 }
14459 }
14462 && curr_set
14465 {
14466 /* We're trying to match:
14467 prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
14468 curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0)
14469 (const_int 0))
14470 (label_ref ("SYM"))
14471 (pc)) */
14478 {
14479 /* Fuse ALU operations followed by conditional branch instruction. */
14481 {
14502 }
14503 }
14504 }
14507 }
14509 /* Return true iff the instruction fusion described by OP is enabled. */
14511 bool
14513 {
14515 }
14517 /* If MEM is in the form of [base+offset], extract the two parts
14518 of address and set to BASE and OFFSET, otherwise return false
14519 after clearing BASE and OFFSET. */
14521 bool
14523 {
14524 rtx addr;
14531 {
14535 }
14539 {
14543 }
14549 }
14551 /* Types for scheduling fusion. */
14552 enum sched_fusion_type
14553 {
14555 SCHED_FUSION_LD_SIGN_EXTEND,
14556 SCHED_FUSION_LD_ZERO_EXTEND,
14557 SCHED_FUSION_LD,
14558 SCHED_FUSION_ST,
14559 SCHED_FUSION_NUM
14560 };
14562 /* If INSN is a load or store of address in the form of [base+offset],
14563 extract the two parts and set to BASE and OFFSET. Return scheduling
14564 fusion type this INSN is. */
14566 static enum sched_fusion_type
14568 {
14586 {
14591 }
14593 {
14598 }
14603 {
14606 }
14607 else
14614 }
14616 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
14618 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
14619 and PRI are only calculated for these instructions. For other instruction,
14620 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
14621 type instruction fusion can be added by returning different priorities.
14623 It's important that irrelevant instructions get the largest FUSION_PRI. */
14625 static void
14628 {
14638 {
14642 }
14644 /* Set FUSION_PRI according to fusion type and base register. */
14647 /* Calculate PRI. */
14650 /* INSN with smaller offset goes first. */
14654 else
14659 }
14661 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
14662 Adjust priority of sha1h instructions so they are scheduled before
14663 other SHA1 instructions. */
14665 static int
14667 {
14671 {
14676 }
14679 }
14681 /* Given OPERANDS of consecutive load/store, check if we can merge
14682 them into ldp/stp. LOAD is true if they are load instructions.
14683 MODE is the mode of memory operands. */
14685 bool
14687 machine_mode mode)
14688 {
14694 {
14702 }
14703 else
14704 {
14709 }
14711 /* The mems cannot be volatile. */
14715 /* If we have SImode and slow unaligned ldp,
14716 check the alignment to be at least 8 byte. */
14720 && !optimize_size
14724 /* Check if the addresses are in the form of [base+offset]. */
14732 /* Check if the bases are same. */
14739 /* Check if the offsets are consecutive. */
14743 /* Check if the addresses are clobbered by load. */
14745 {
14749 /* In increasing order, the last load can clobber the address. */
14752 }
14756 else
14761 else
14764 /* Check if the registers are of same class. */
14769 }
14771 /* Given OPERANDS of consecutive load/store, check if we can merge
14772 them into ldp/stp by adjusting the offset. LOAD is true if they
14773 are load instructions. MODE is the mode of memory operands.
14775 Given below consecutive stores:
14777 str w1, [xb, 0x100]
14778 str w1, [xb, 0x104]
14779 str w1, [xb, 0x108]
14780 str w1, [xb, 0x10c]
14782 Though the offsets are out of the range supported by stp, we can
14783 still pair them after adjusting the offset, like:
14785 add scratch, xb, 0x100
14786 stp w1, w1, [scratch]
14787 stp w1, w1, [scratch, 0x8]
14789 The peephole patterns detecting this opportunity should guarantee
14790 the scratch register is avaliable. */
14792 bool
14794 machine_mode mode)
14795 {
14802 {
14815 }
14816 else
14817 {
14826 }
14827 /* Skip if memory operand is by itslef valid for ldp/stp. */
14831 /* The mems cannot be volatile. */
14836 /* Check if the addresses are in the form of [base+offset]. */
14850 /* Check if the bases are same. */
14861 /* Check if the offsets are consecutive. */
14870 /* Check if the addresses are clobbered by load. */
14872 {
14878 /* In increasing order, the last load can clobber the address. */
14881 }
14883 /* If we have SImode and slow unaligned ldp,
14884 check the alignment to be at least 8 byte. */
14888 && !optimize_size
14894 else
14899 else
14904 else
14909 else
14912 /* Check if the registers are of same class. */
14917 }
14919 /* Given OPERANDS of consecutive load/store, this function pairs them
14920 into ldp/stp after adjusting the offset. It depends on the fact
14921 that addresses of load/store instructions are in increasing order.
14922 MODE is the mode of memory operands. CODE is the rtl operator
14923 which should be applied to all memory operands, it's SIGN_EXTEND,
14924 ZERO_EXTEND or UNKNOWN. */
14926 bool
14929 {
14935 {
14940 }
14941 else
14942 {
14948 }
14953 /* Adjust offset thus it can fit in ldp/stp instruction. */
14961 /* Further adjust to make sure all offsets are OK. */
14963 {
14966 }
14968 /* Make sure the adjustment can be done with ADD/SUB instructions. */
14973 {
14976 }
14978 /* Create new memory references. */
14982 /* Check if the adjusted address is OK for ldp/stp. */
15001 {
15006 }
15008 {
15013 }
15016 {
15021 }
15022 else
15023 {
15028 }
15030 /* Emit adjusting instruction. */
15032 /* Emit ldp/stp instructions. */
15040 }
15042 /* Return 1 if pseudo register should be created and used to hold
15043 GOT address for PIC code. */
15045 bool
15047 {
15049 }
15051 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
15053 static int
15055 {
15057 {
15064 }
15067 }
15070 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
15071 return the log2 of that value. Otherwise return -1. */
15073 int
15075 {
15090 }
15092 /* If X is a vector of equal CONST_DOUBLE values and that value is
15093 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
15095 int
15097 {
15113 }
15115 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
15116 to float.
15118 __fp16 always promotes through this hook.
15119 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
15120 through the generic excess precision logic rather than here. */
15122 static tree
15124 {
15130 }
15132 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
15134 static bool
15136 optimization_type opt_type)
15137 {
15139 {
15145 }
15146 }
15148 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
15149 if MODE is HFmode, and punt to the generic implementation otherwise. */
15151 static bool
15153 {
15157 }
15159 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
15160 if MODE is HFmode, and punt to the generic implementation otherwise. */
15162 static bool
15164 {
15168 }
15170 /* Set the value of FLT_EVAL_METHOD.
15171 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
15173 0: evaluate all operations and constants, whose semantic type has at
15174 most the range and precision of type float, to the range and
15175 precision of float; evaluate all other operations and constants to
15176 the range and precision of the semantic type;
15178 N, where _FloatN is a supported interchange floating type
15179 evaluate all operations and constants, whose semantic type has at
15180 most the range and precision of _FloatN type, to the range and
15181 precision of the _FloatN type; evaluate all other operations and
15182 constants to the range and precision of the semantic type;
15184 If we have the ARMv8.2-A extensions then we support _Float16 in native
15185 precision, so we should set this to 16. Otherwise, we support the type,
15186 but want to evaluate expressions in float precision, so set this to
15187 0. */
15189 static enum flt_eval_method
15191 {
15193 {
15196 /* We can calculate either in 16-bit range and precision or
15197 32-bit range and precision. Make that decision based on whether
15198 we have native support for the ARMv8.2-A 16-bit floating-point
15199 instructions or not. */
15201 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
15207 }
15209 }
15211 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
15212 scheduled for speculative execution. Reject the long-running division
15213 and square-root instructions. */
15215 static bool
15217 {
15219 {
15237 }
15238 }
15240 /* Target-specific selftests. */
15242 #if CHECKING_P
15246 /* Selftest for the RTL loader.
15247 Verify that the RTL loader copes with a dump from
15248 print_rtx_function. This is essentially just a test that class
15249 function_reader can handle a real dump, but it also verifies
15250 that lookup_reg_by_dump_name correctly handles hard regs.
15251 The presence of hard reg names in the dump means that the test is
15252 target-specific, hence it is in this file. */
15254 static void
15256 {
15268 /* Verify crtl->return_rtx. */
15272 }
15274 /* Run all target-specific selftests. */
15276 static void
15278 {
15280 }
15286 #undef TARGET_ADDRESS_COST
15287 #define TARGET_ADDRESS_COST aarch64_address_cost
15289 /* This hook will determines whether unnamed bitfields affect the alignment
15290 of the containing structure. The hook returns true if the structure
15291 should inherit the alignment requirements of an unnamed bitfield's
15292 type. */
15293 #undef TARGET_ALIGN_ANON_BITFIELD
15294 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
15296 #undef TARGET_ASM_ALIGNED_DI_OP
15299 #undef TARGET_ASM_ALIGNED_HI_OP
15302 #undef TARGET_ASM_ALIGNED_SI_OP
15305 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
15306 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
15307 hook_bool_const_tree_hwi_hwi_const_tree_true
15309 #undef TARGET_ASM_FILE_START
15310 #define TARGET_ASM_FILE_START aarch64_start_file
15312 #undef TARGET_ASM_OUTPUT_MI_THUNK
15313 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
15315 #undef TARGET_ASM_SELECT_RTX_SECTION
15316 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
15318 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
15319 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
15321 #undef TARGET_BUILD_BUILTIN_VA_LIST
15322 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
15324 #undef TARGET_CALLEE_COPIES
15325 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
15327 #undef TARGET_CAN_ELIMINATE
15328 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
15330 #undef TARGET_CAN_INLINE_P
15331 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
15333 #undef TARGET_CANNOT_FORCE_CONST_MEM
15334 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
15336 #undef TARGET_CASE_VALUES_THRESHOLD
15337 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
15339 #undef TARGET_CONDITIONAL_REGISTER_USAGE
15340 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
15342 /* Only the least significant bit is used for initialization guard
15343 variables. */
15344 #undef TARGET_CXX_GUARD_MASK_BIT
15345 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
15347 #undef TARGET_C_MODE_FOR_SUFFIX
15348 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
15350 #ifdef TARGET_BIG_ENDIAN_DEFAULT
15351 #undef TARGET_DEFAULT_TARGET_FLAGS
15352 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
15353 #endif
15355 #undef TARGET_CLASS_MAX_NREGS
15356 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
15358 #undef TARGET_BUILTIN_DECL
15359 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
15361 #undef TARGET_BUILTIN_RECIPROCAL
15362 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
15364 #undef TARGET_C_EXCESS_PRECISION
15365 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
15367 #undef TARGET_EXPAND_BUILTIN
15368 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
15370 #undef TARGET_EXPAND_BUILTIN_VA_START
15371 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
15373 #undef TARGET_FOLD_BUILTIN
15374 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
15376 #undef TARGET_FUNCTION_ARG
15377 #define TARGET_FUNCTION_ARG aarch64_function_arg
15379 #undef TARGET_FUNCTION_ARG_ADVANCE
15380 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
15382 #undef TARGET_FUNCTION_ARG_BOUNDARY
15383 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
15385 #undef TARGET_FUNCTION_ARG_PADDING
15386 #define TARGET_FUNCTION_ARG_PADDING aarch64_function_arg_padding
15388 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
15389 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
15391 #undef TARGET_FUNCTION_VALUE
15392 #define TARGET_FUNCTION_VALUE aarch64_function_value
15394 #undef TARGET_FUNCTION_VALUE_REGNO_P
15395 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
15397 #undef TARGET_FRAME_POINTER_REQUIRED
15398 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
15400 #undef TARGET_GIMPLE_FOLD_BUILTIN
15401 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
15403 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
15404 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
15406 #undef TARGET_INIT_BUILTINS
15407 #define TARGET_INIT_BUILTINS aarch64_init_builtins
15409 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
15410 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
15411 aarch64_ira_change_pseudo_allocno_class
15413 #undef TARGET_LEGITIMATE_ADDRESS_P
15414 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
15416 #undef TARGET_LEGITIMATE_CONSTANT_P
15417 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
15419 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
15420 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
15421 aarch64_legitimize_address_displacement
15423 #undef TARGET_LIBGCC_CMP_RETURN_MODE
15424 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
15426 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
15427 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
15428 aarch64_libgcc_floating_mode_supported_p
15430 #undef TARGET_MANGLE_TYPE
15431 #define TARGET_MANGLE_TYPE aarch64_mangle_type
15433 #undef TARGET_MEMORY_MOVE_COST
15434 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
15436 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
15437 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
15439 #undef TARGET_MUST_PASS_IN_STACK
15440 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
15442 /* This target hook should return true if accesses to volatile bitfields
15443 should use the narrowest mode possible. It should return false if these
15444 accesses should use the bitfield container type. */
15445 #undef TARGET_NARROW_VOLATILE_BITFIELD
15446 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
15448 #undef TARGET_OPTION_OVERRIDE
15449 #define TARGET_OPTION_OVERRIDE aarch64_override_options
15451 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
15452 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
15453 aarch64_override_options_after_change
15455 #undef TARGET_OPTION_SAVE
15456 #define TARGET_OPTION_SAVE aarch64_option_save
15458 #undef TARGET_OPTION_RESTORE
15459 #define TARGET_OPTION_RESTORE aarch64_option_restore
15461 #undef TARGET_OPTION_PRINT
15462 #define TARGET_OPTION_PRINT aarch64_option_print
15464 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
15465 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
15467 #undef TARGET_SET_CURRENT_FUNCTION
15468 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
15470 #undef TARGET_PASS_BY_REFERENCE
15471 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
15473 #undef TARGET_PREFERRED_RELOAD_CLASS
15474 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
15476 #undef TARGET_SCHED_REASSOCIATION_WIDTH
15477 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
15479 #undef TARGET_PROMOTED_TYPE
15480 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
15482 #undef TARGET_SECONDARY_RELOAD
15483 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
15485 #undef TARGET_SHIFT_TRUNCATION_MASK
15486 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
15488 #undef TARGET_SETUP_INCOMING_VARARGS
15489 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
15491 #undef TARGET_STRUCT_VALUE_RTX
15492 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
15494 #undef TARGET_REGISTER_MOVE_COST
15495 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
15497 #undef TARGET_RETURN_IN_MEMORY
15498 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
15500 #undef TARGET_RETURN_IN_MSB
15501 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
15503 #undef TARGET_RTX_COSTS
15504 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
15506 #undef TARGET_SCALAR_MODE_SUPPORTED_P
15507 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
15509 #undef TARGET_SCHED_ISSUE_RATE
15510 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
15512 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
15513 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
15514 aarch64_sched_first_cycle_multipass_dfa_lookahead
15516 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
15517 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
15518 aarch64_first_cycle_multipass_dfa_lookahead_guard
15520 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
15521 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
15522 aarch64_get_separate_components
15524 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
15525 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
15526 aarch64_components_for_bb
15528 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
15529 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
15530 aarch64_disqualify_components
15532 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
15533 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
15534 aarch64_emit_prologue_components
15536 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
15537 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
15538 aarch64_emit_epilogue_components
15540 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
15541 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
15542 aarch64_set_handled_components
15544 #undef TARGET_TRAMPOLINE_INIT
15545 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
15547 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
15548 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
15550 #undef TARGET_VECTOR_MODE_SUPPORTED_P
15551 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
15553 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
15554 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
15555 aarch64_builtin_support_vector_misalignment
15557 #undef TARGET_ARRAY_MODE_SUPPORTED_P
15558 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
15560 #undef TARGET_VECTORIZE_ADD_STMT_COST
15561 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
15563 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
15564 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
15565 aarch64_builtin_vectorization_cost
15567 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
15568 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
15570 #undef TARGET_VECTORIZE_BUILTINS
15571 #define TARGET_VECTORIZE_BUILTINS
15573 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
15574 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
15575 aarch64_builtin_vectorized_function
15577 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
15578 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
15579 aarch64_autovectorize_vector_sizes
15581 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
15582 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
15583 aarch64_atomic_assign_expand_fenv
15585 /* Section anchor support. */
15587 #undef TARGET_MIN_ANCHOR_OFFSET
15588 #define TARGET_MIN_ANCHOR_OFFSET -256
15590 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
15591 byte offset; we can do much more for larger data types, but have no way
15592 to determine the size of the access. We assume accesses are aligned. */
15593 #undef TARGET_MAX_ANCHOR_OFFSET
15594 #define TARGET_MAX_ANCHOR_OFFSET 4095
15596 #undef TARGET_VECTOR_ALIGNMENT
15597 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
15599 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
15600 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
15601 aarch64_simd_vector_alignment_reachable
15603 /* vec_perm support. */
15605 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
15606 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
15607 aarch64_vectorize_vec_perm_const_ok
15609 #undef TARGET_INIT_LIBFUNCS
15610 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
15612 #undef TARGET_FIXED_CONDITION_CODE_REGS
15613 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
15615 #undef TARGET_FLAGS_REGNUM
15616 #define TARGET_FLAGS_REGNUM CC_REGNUM
15618 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
15619 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
15621 #undef TARGET_ASAN_SHADOW_OFFSET
15622 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
15624 #undef TARGET_LEGITIMIZE_ADDRESS
15625 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
15627 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
15628 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
15629 aarch64_use_by_pieces_infrastructure_p
15631 #undef TARGET_SCHED_CAN_SPECULATE_INSN
15632 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
15634 #undef TARGET_CAN_USE_DOLOOP_P
15635 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
15637 #undef TARGET_SCHED_ADJUST_PRIORITY
15638 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
15640 #undef TARGET_SCHED_MACRO_FUSION_P
15641 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
15643 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
15644 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
15646 #undef TARGET_SCHED_FUSION_PRIORITY
15647 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
15649 #undef TARGET_UNSPEC_MAY_TRAP_P
15650 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
15652 #undef TARGET_USE_PSEUDO_PIC_REG
15653 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
15655 #undef TARGET_PRINT_OPERAND
15656 #define TARGET_PRINT_OPERAND aarch64_print_operand
15658 #undef TARGET_PRINT_OPERAND_ADDRESS
15659 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
15661 #undef TARGET_OPTAB_SUPPORTED_P
15662 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
15664 #undef TARGET_OMIT_STRUCT_RETURN_REG
15665 #define TARGET_OMIT_STRUCT_RETURN_REG true
15667 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
15668 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
15669 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
15671 #undef TARGET_HARD_REGNO_MODE_OK
15672 #define TARGET_HARD_REGNO_MODE_OK aarch64_hard_regno_mode_ok
15674 #undef TARGET_MODES_TIEABLE_P
15675 #define TARGET_MODES_TIEABLE_P aarch64_modes_tieable_p
15677 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
15678 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
15679 aarch64_hard_regno_call_part_clobbered
15681 #if CHECKING_P
15682 #undef TARGET_RUN_TARGET_SELFTESTS
15683 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests