1 /* Analyze RTL for GNU compiler.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
32 #include "insn-config.h"
34 #include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */
36 #include "addresses.h"
39 /* Forward declarations */
40 static void set_of_1 (rtx
, const_rtx
, void *);
41 static bool covers_regno_p (const_rtx
, unsigned int);
42 static bool covers_regno_no_parallel_p (const_rtx
, unsigned int);
43 static int computed_jump_p_1 (const_rtx
);
44 static void parms_set (rtx
, const_rtx
, void *);
46 static unsigned HOST_WIDE_INT
cached_nonzero_bits (const_rtx
, machine_mode
,
47 const_rtx
, machine_mode
,
48 unsigned HOST_WIDE_INT
);
49 static unsigned HOST_WIDE_INT
nonzero_bits1 (const_rtx
, machine_mode
,
50 const_rtx
, machine_mode
,
51 unsigned HOST_WIDE_INT
);
52 static unsigned int cached_num_sign_bit_copies (const_rtx
, machine_mode
, const_rtx
,
55 static unsigned int num_sign_bit_copies1 (const_rtx
, machine_mode
, const_rtx
,
56 machine_mode
, unsigned int);
58 rtx_subrtx_bound_info rtx_all_subrtx_bounds
[NUM_RTX_CODE
];
59 rtx_subrtx_bound_info rtx_nonconst_subrtx_bounds
[NUM_RTX_CODE
];
61 /* Truncation narrows the mode from SOURCE mode to DESTINATION mode.
62 If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is
63 SIGN_EXTEND then while narrowing we also have to enforce the
64 representation and sign-extend the value to mode DESTINATION_REP.
66 If the value is already sign-extended to DESTINATION_REP mode we
67 can just switch to DESTINATION mode on it. For each pair of
68 integral modes SOURCE and DESTINATION, when truncating from SOURCE
69 to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION]
70 contains the number of high-order bits in SOURCE that have to be
71 copies of the sign-bit so that we can do this mode-switch to
75 num_sign_bit_copies_in_rep
[MAX_MODE_INT
+ 1][MAX_MODE_INT
+ 1];
77 /* Store X into index I of ARRAY. ARRAY is known to have at least I
78 elements. Return the new base of ARRAY. */
81 typename
T::value_type
*
82 generic_subrtx_iterator
<T
>::add_single_to_queue (array_type
&array
,
84 size_t i
, value_type x
)
86 if (base
== array
.stack
)
93 gcc_checking_assert (i
== LOCAL_ELEMS
);
94 /* A previous iteration might also have moved from the stack to the
95 heap, in which case the heap array will already be big enough. */
96 if (vec_safe_length (array
.heap
) <= i
)
97 vec_safe_grow (array
.heap
, i
+ 1);
98 base
= array
.heap
->address ();
99 memcpy (base
, array
.stack
, sizeof (array
.stack
));
100 base
[LOCAL_ELEMS
] = x
;
103 unsigned int length
= array
.heap
->length ();
106 gcc_checking_assert (base
== array
.heap
->address ());
112 gcc_checking_assert (i
== length
);
113 vec_safe_push (array
.heap
, x
);
114 return array
.heap
->address ();
118 /* Add the subrtxes of X to worklist ARRAY, starting at END. Return the
119 number of elements added to the worklist. */
121 template <typename T
>
123 generic_subrtx_iterator
<T
>::add_subrtxes_to_queue (array_type
&array
,
125 size_t end
, rtx_type x
)
127 enum rtx_code code
= GET_CODE (x
);
128 const char *format
= GET_RTX_FORMAT (code
);
129 size_t orig_end
= end
;
130 if (__builtin_expect (INSN_P (x
), false))
132 /* Put the pattern at the top of the queue, since that's what
133 we're likely to want most. It also allows for the SEQUENCE
135 for (int i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; --i
)
136 if (format
[i
] == 'e')
138 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
139 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
142 base
= add_single_to_queue (array
, base
, end
++, subx
);
146 for (int i
= 0; format
[i
]; ++i
)
147 if (format
[i
] == 'e')
149 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
150 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
153 base
= add_single_to_queue (array
, base
, end
++, subx
);
155 else if (format
[i
] == 'E')
157 unsigned int length
= GET_NUM_ELEM (x
->u
.fld
[i
].rt_rtvec
);
158 rtx
*vec
= x
->u
.fld
[i
].rt_rtvec
->elem
;
159 if (__builtin_expect (end
+ length
<= LOCAL_ELEMS
, true))
160 for (unsigned int j
= 0; j
< length
; j
++)
161 base
[end
++] = T::get_value (vec
[j
]);
163 for (unsigned int j
= 0; j
< length
; j
++)
164 base
= add_single_to_queue (array
, base
, end
++,
165 T::get_value (vec
[j
]));
166 if (code
== SEQUENCE
&& end
== length
)
167 /* If the subrtxes of the sequence fill the entire array then
168 we know that no other parts of a containing insn are queued.
169 The caller is therefore iterating over the sequence as a
170 PATTERN (...), so we also want the patterns of the
172 for (unsigned int j
= 0; j
< length
; j
++)
174 typename
T::rtx_type x
= T::get_rtx (base
[j
]);
176 base
[j
] = T::get_value (PATTERN (x
));
179 return end
- orig_end
;
182 template <typename T
>
184 generic_subrtx_iterator
<T
>::free_array (array_type
&array
)
186 vec_free (array
.heap
);
189 template <typename T
>
190 const size_t generic_subrtx_iterator
<T
>::LOCAL_ELEMS
;
192 template class generic_subrtx_iterator
<const_rtx_accessor
>;
193 template class generic_subrtx_iterator
<rtx_var_accessor
>;
194 template class generic_subrtx_iterator
<rtx_ptr_accessor
>;
196 /* Return 1 if the value of X is unstable
197 (would be different at a different point in the program).
198 The frame pointer, arg pointer, etc. are considered stable
199 (within one function) and so is anything marked `unchanging'. */
202 rtx_unstable_p (const_rtx x
)
204 const RTX_CODE code
= GET_CODE (x
);
211 return !MEM_READONLY_P (x
) || rtx_unstable_p (XEXP (x
, 0));
220 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
221 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
222 /* The arg pointer varies if it is not a fixed register. */
223 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
225 /* ??? When call-clobbered, the value is stable modulo the restore
226 that must happen after a call. This currently screws up local-alloc
227 into believing that the restore is not needed. */
228 if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
&& x
== pic_offset_table_rtx
)
233 if (MEM_VOLATILE_P (x
))
242 fmt
= GET_RTX_FORMAT (code
);
243 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
246 if (rtx_unstable_p (XEXP (x
, i
)))
249 else if (fmt
[i
] == 'E')
252 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
253 if (rtx_unstable_p (XVECEXP (x
, i
, j
)))
260 /* Return 1 if X has a value that can vary even between two
261 executions of the program. 0 means X can be compared reliably
262 against certain constants or near-constants.
263 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
264 zero, we are slightly more conservative.
265 The frame pointer and the arg pointer are considered constant. */
268 rtx_varies_p (const_rtx x
, bool for_alias
)
281 return !MEM_READONLY_P (x
) || rtx_varies_p (XEXP (x
, 0), for_alias
);
290 /* Note that we have to test for the actual rtx used for the frame
291 and arg pointers and not just the register number in case we have
292 eliminated the frame and/or arg pointer and are using it
294 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
295 /* The arg pointer varies if it is not a fixed register. */
296 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
298 if (x
== pic_offset_table_rtx
299 /* ??? When call-clobbered, the value is stable modulo the restore
300 that must happen after a call. This currently screws up
301 local-alloc into believing that the restore is not needed, so we
302 must return 0 only if we are called from alias analysis. */
303 && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
|| for_alias
))
308 /* The operand 0 of a LO_SUM is considered constant
309 (in fact it is related specifically to operand 1)
310 during alias analysis. */
311 return (! for_alias
&& rtx_varies_p (XEXP (x
, 0), for_alias
))
312 || rtx_varies_p (XEXP (x
, 1), for_alias
);
315 if (MEM_VOLATILE_P (x
))
324 fmt
= GET_RTX_FORMAT (code
);
325 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
328 if (rtx_varies_p (XEXP (x
, i
), for_alias
))
331 else if (fmt
[i
] == 'E')
334 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
335 if (rtx_varies_p (XVECEXP (x
, i
, j
), for_alias
))
342 /* Compute an approximation for the offset between the register
343 FROM and TO for the current function, as it was at the start
347 get_initial_register_offset (int from
, int to
)
349 static const struct elim_table_t
353 } table
[] = ELIMINABLE_REGS
;
354 HOST_WIDE_INT offset1
, offset2
;
360 /* It is not safe to call INITIAL_ELIMINATION_OFFSET
361 before the reload pass. We need to give at least
362 an estimation for the resulting frame size. */
363 if (! reload_completed
)
365 offset1
= crtl
->outgoing_args_size
+ get_frame_size ();
366 #if !STACK_GROWS_DOWNWARD
369 if (to
== STACK_POINTER_REGNUM
)
371 else if (from
== STACK_POINTER_REGNUM
)
377 for (i
= 0; i
< ARRAY_SIZE (table
); i
++)
378 if (table
[i
].from
== from
)
380 if (table
[i
].to
== to
)
382 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
386 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
388 if (table
[j
].to
== to
389 && table
[j
].from
== table
[i
].to
)
391 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
393 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
395 return offset1
+ offset2
;
397 if (table
[j
].from
== to
398 && table
[j
].to
== table
[i
].to
)
400 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
402 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
404 return offset1
- offset2
;
408 else if (table
[i
].to
== from
)
410 if (table
[i
].from
== to
)
412 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
416 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
418 if (table
[j
].to
== to
419 && table
[j
].from
== table
[i
].from
)
421 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
423 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
425 return - offset1
+ offset2
;
427 if (table
[j
].from
== to
428 && table
[j
].to
== table
[i
].from
)
430 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
432 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
434 return - offset1
- offset2
;
439 /* If the requested register combination was not found,
440 try a different more simple combination. */
441 if (from
== ARG_POINTER_REGNUM
)
442 return get_initial_register_offset (HARD_FRAME_POINTER_REGNUM
, to
);
443 else if (to
== ARG_POINTER_REGNUM
)
444 return get_initial_register_offset (from
, HARD_FRAME_POINTER_REGNUM
);
445 else if (from
== HARD_FRAME_POINTER_REGNUM
)
446 return get_initial_register_offset (FRAME_POINTER_REGNUM
, to
);
447 else if (to
== HARD_FRAME_POINTER_REGNUM
)
448 return get_initial_register_offset (from
, FRAME_POINTER_REGNUM
);
453 /* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE
454 bytes can cause a trap. MODE is the mode of the MEM (not that of X) and
455 UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory
456 references on strict alignment machines. */
459 rtx_addr_can_trap_p_1 (const_rtx x
, HOST_WIDE_INT offset
, HOST_WIDE_INT size
,
460 machine_mode mode
, bool unaligned_mems
)
462 enum rtx_code code
= GET_CODE (x
);
464 /* The offset must be a multiple of the mode size if we are considering
465 unaligned memory references on strict alignment machines. */
466 if (STRICT_ALIGNMENT
&& unaligned_mems
&& GET_MODE_SIZE (mode
) != 0)
468 HOST_WIDE_INT actual_offset
= offset
;
470 #ifdef SPARC_STACK_BOUNDARY_HACK
471 /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
472 the real alignment of %sp. However, when it does this, the
473 alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */
474 if (SPARC_STACK_BOUNDARY_HACK
475 && (x
== stack_pointer_rtx
|| x
== hard_frame_pointer_rtx
))
476 actual_offset
-= STACK_POINTER_OFFSET
;
479 if (actual_offset
% GET_MODE_SIZE (mode
) != 0)
486 if (SYMBOL_REF_WEAK (x
))
488 if (!CONSTANT_POOL_ADDRESS_P (x
))
491 HOST_WIDE_INT decl_size
;
496 size
= GET_MODE_SIZE (mode
);
500 /* If the size of the access or of the symbol is unknown,
502 decl
= SYMBOL_REF_DECL (x
);
504 /* Else check that the access is in bounds. TODO: restructure
505 expr_size/tree_expr_size/int_expr_size and just use the latter. */
508 else if (DECL_P (decl
) && DECL_SIZE_UNIT (decl
))
509 decl_size
= (tree_fits_shwi_p (DECL_SIZE_UNIT (decl
))
510 ? tree_to_shwi (DECL_SIZE_UNIT (decl
))
512 else if (TREE_CODE (decl
) == STRING_CST
)
513 decl_size
= TREE_STRING_LENGTH (decl
);
514 else if (TYPE_SIZE_UNIT (TREE_TYPE (decl
)))
515 decl_size
= int_size_in_bytes (TREE_TYPE (decl
));
519 return (decl_size
<= 0 ? offset
!= 0 : offset
+ size
> decl_size
);
528 /* Stack references are assumed not to trap, but we need to deal with
529 nonsensical offsets. */
530 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
531 || x
== stack_pointer_rtx
532 /* The arg pointer varies if it is not a fixed register. */
533 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
536 HOST_WIDE_INT red_zone_size
= RED_ZONE_SIZE
;
538 HOST_WIDE_INT red_zone_size
= 0;
540 HOST_WIDE_INT stack_boundary
= PREFERRED_STACK_BOUNDARY
542 HOST_WIDE_INT low_bound
, high_bound
;
545 size
= GET_MODE_SIZE (mode
);
549 if (x
== frame_pointer_rtx
)
551 if (FRAME_GROWS_DOWNWARD
)
553 high_bound
= STARTING_FRAME_OFFSET
;
554 low_bound
= high_bound
- get_frame_size ();
558 low_bound
= STARTING_FRAME_OFFSET
;
559 high_bound
= low_bound
+ get_frame_size ();
562 else if (x
== hard_frame_pointer_rtx
)
564 HOST_WIDE_INT sp_offset
565 = get_initial_register_offset (STACK_POINTER_REGNUM
,
566 HARD_FRAME_POINTER_REGNUM
);
567 HOST_WIDE_INT ap_offset
568 = get_initial_register_offset (ARG_POINTER_REGNUM
,
569 HARD_FRAME_POINTER_REGNUM
);
571 #if STACK_GROWS_DOWNWARD
572 low_bound
= sp_offset
- red_zone_size
- stack_boundary
;
573 high_bound
= ap_offset
574 + FIRST_PARM_OFFSET (current_function_decl
)
575 #if !ARGS_GROW_DOWNWARD
580 high_bound
= sp_offset
+ red_zone_size
+ stack_boundary
;
581 low_bound
= ap_offset
582 + FIRST_PARM_OFFSET (current_function_decl
)
583 #if ARGS_GROW_DOWNWARD
589 else if (x
== stack_pointer_rtx
)
591 HOST_WIDE_INT ap_offset
592 = get_initial_register_offset (ARG_POINTER_REGNUM
,
593 STACK_POINTER_REGNUM
);
595 #if STACK_GROWS_DOWNWARD
596 low_bound
= - red_zone_size
- stack_boundary
;
597 high_bound
= ap_offset
598 + FIRST_PARM_OFFSET (current_function_decl
)
599 #if !ARGS_GROW_DOWNWARD
604 high_bound
= red_zone_size
+ stack_boundary
;
605 low_bound
= ap_offset
606 + FIRST_PARM_OFFSET (current_function_decl
)
607 #if ARGS_GROW_DOWNWARD
615 /* We assume that accesses are safe to at least the
617 Examples are varargs and __builtin_return_address. */
618 #if ARGS_GROW_DOWNWARD
619 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
621 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
622 - crtl
->args
.size
- stack_boundary
;
624 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
626 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
627 + crtl
->args
.size
+ stack_boundary
;
631 if (offset
>= low_bound
&& offset
<= high_bound
- size
)
635 /* All of the virtual frame registers are stack references. */
636 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
637 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
642 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
643 mode
, unaligned_mems
);
646 /* An address is assumed not to trap if:
647 - it is the pic register plus a constant. */
648 if (XEXP (x
, 0) == pic_offset_table_rtx
&& CONSTANT_P (XEXP (x
, 1)))
651 /* - or it is an address that can't trap plus a constant integer. */
652 if (CONST_INT_P (XEXP (x
, 1))
653 && !rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
+ INTVAL (XEXP (x
, 1)),
654 size
, mode
, unaligned_mems
))
661 return rtx_addr_can_trap_p_1 (XEXP (x
, 1), offset
, size
,
662 mode
, unaligned_mems
);
669 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
670 mode
, unaligned_mems
);
676 /* If it isn't one of the case above, it can cause a trap. */
680 /* Return nonzero if the use of X as an address in a MEM can cause a trap. */
683 rtx_addr_can_trap_p (const_rtx x
)
685 return rtx_addr_can_trap_p_1 (x
, 0, 0, VOIDmode
, false);
688 /* Return true if X is an address that is known to not be zero. */
691 nonzero_address_p (const_rtx x
)
693 const enum rtx_code code
= GET_CODE (x
);
698 return flag_delete_null_pointer_checks
&& !SYMBOL_REF_WEAK (x
);
704 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
705 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
706 || x
== stack_pointer_rtx
707 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
709 /* All of the virtual frame registers are stack references. */
710 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
711 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
716 return nonzero_address_p (XEXP (x
, 0));
719 /* Handle PIC references. */
720 if (XEXP (x
, 0) == pic_offset_table_rtx
721 && CONSTANT_P (XEXP (x
, 1)))
726 /* Similar to the above; allow positive offsets. Further, since
727 auto-inc is only allowed in memories, the register must be a
729 if (CONST_INT_P (XEXP (x
, 1))
730 && INTVAL (XEXP (x
, 1)) > 0)
732 return nonzero_address_p (XEXP (x
, 0));
735 /* Similarly. Further, the offset is always positive. */
742 return nonzero_address_p (XEXP (x
, 0));
745 return nonzero_address_p (XEXP (x
, 1));
751 /* If it isn't one of the case above, might be zero. */
755 /* Return 1 if X refers to a memory location whose address
756 cannot be compared reliably with constant addresses,
757 or if X refers to a BLKmode memory object.
758 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
759 zero, we are slightly more conservative. */
762 rtx_addr_varies_p (const_rtx x
, bool for_alias
)
773 return GET_MODE (x
) == BLKmode
|| rtx_varies_p (XEXP (x
, 0), for_alias
);
775 fmt
= GET_RTX_FORMAT (code
);
776 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
779 if (rtx_addr_varies_p (XEXP (x
, i
), for_alias
))
782 else if (fmt
[i
] == 'E')
785 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
786 if (rtx_addr_varies_p (XVECEXP (x
, i
, j
), for_alias
))
792 /* Return the CALL in X if there is one. */
795 get_call_rtx_from (rtx x
)
799 if (GET_CODE (x
) == PARALLEL
)
800 x
= XVECEXP (x
, 0, 0);
801 if (GET_CODE (x
) == SET
)
803 if (GET_CODE (x
) == CALL
&& MEM_P (XEXP (x
, 0)))
808 /* Return the value of the integer term in X, if one is apparent;
810 Only obvious integer terms are detected.
811 This is used in cse.c with the `related_value' field. */
814 get_integer_term (const_rtx x
)
816 if (GET_CODE (x
) == CONST
)
819 if (GET_CODE (x
) == MINUS
820 && CONST_INT_P (XEXP (x
, 1)))
821 return - INTVAL (XEXP (x
, 1));
822 if (GET_CODE (x
) == PLUS
823 && CONST_INT_P (XEXP (x
, 1)))
824 return INTVAL (XEXP (x
, 1));
828 /* If X is a constant, return the value sans apparent integer term;
830 Only obvious integer terms are detected. */
833 get_related_value (const_rtx x
)
835 if (GET_CODE (x
) != CONST
)
838 if (GET_CODE (x
) == PLUS
839 && CONST_INT_P (XEXP (x
, 1)))
841 else if (GET_CODE (x
) == MINUS
842 && CONST_INT_P (XEXP (x
, 1)))
847 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
848 to somewhere in the same object or object_block as SYMBOL. */
851 offset_within_block_p (const_rtx symbol
, HOST_WIDE_INT offset
)
855 if (GET_CODE (symbol
) != SYMBOL_REF
)
863 if (CONSTANT_POOL_ADDRESS_P (symbol
)
864 && offset
< (int) GET_MODE_SIZE (get_pool_mode (symbol
)))
867 decl
= SYMBOL_REF_DECL (symbol
);
868 if (decl
&& offset
< int_size_in_bytes (TREE_TYPE (decl
)))
872 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol
)
873 && SYMBOL_REF_BLOCK (symbol
)
874 && SYMBOL_REF_BLOCK_OFFSET (symbol
) >= 0
875 && ((unsigned HOST_WIDE_INT
) offset
+ SYMBOL_REF_BLOCK_OFFSET (symbol
)
876 < (unsigned HOST_WIDE_INT
) SYMBOL_REF_BLOCK (symbol
)->size
))
882 /* Split X into a base and a constant offset, storing them in *BASE_OUT
883 and *OFFSET_OUT respectively. */
886 split_const (rtx x
, rtx
*base_out
, rtx
*offset_out
)
888 if (GET_CODE (x
) == CONST
)
891 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
893 *base_out
= XEXP (x
, 0);
894 *offset_out
= XEXP (x
, 1);
899 *offset_out
= const0_rtx
;
902 /* Return the number of places FIND appears within X. If COUNT_DEST is
903 zero, we do not count occurrences inside the destination of a SET. */
906 count_occurrences (const_rtx x
, const_rtx find
, int count_dest
)
910 const char *format_ptr
;
929 count
= count_occurrences (XEXP (x
, 0), find
, count_dest
);
931 count
+= count_occurrences (XEXP (x
, 1), find
, count_dest
);
935 if (MEM_P (find
) && rtx_equal_p (x
, find
))
940 if (SET_DEST (x
) == find
&& ! count_dest
)
941 return count_occurrences (SET_SRC (x
), find
, count_dest
);
948 format_ptr
= GET_RTX_FORMAT (code
);
951 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
953 switch (*format_ptr
++)
956 count
+= count_occurrences (XEXP (x
, i
), find
, count_dest
);
960 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
961 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
, count_dest
);
969 /* Return TRUE if OP is a register or subreg of a register that
970 holds an unsigned quantity. Otherwise, return FALSE. */
973 unsigned_reg_p (rtx op
)
977 && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op
))))
980 if (GET_CODE (op
) == SUBREG
981 && SUBREG_PROMOTED_SIGN (op
))
988 /* Nonzero if register REG appears somewhere within IN.
989 Also works if REG is not a register; in this case it checks
990 for a subexpression of IN that is Lisp "equal" to REG. */
993 reg_mentioned_p (const_rtx reg
, const_rtx in
)
1005 if (GET_CODE (in
) == LABEL_REF
)
1006 return reg
== label_ref_label (in
);
1008 code
= GET_CODE (in
);
1012 /* Compare registers by number. */
1014 return REG_P (reg
) && REGNO (in
) == REGNO (reg
);
1016 /* These codes have no constituent expressions
1024 /* These are kept unique for a given value. */
1031 if (GET_CODE (reg
) == code
&& rtx_equal_p (reg
, in
))
1034 fmt
= GET_RTX_FORMAT (code
);
1036 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1041 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
1042 if (reg_mentioned_p (reg
, XVECEXP (in
, i
, j
)))
1045 else if (fmt
[i
] == 'e'
1046 && reg_mentioned_p (reg
, XEXP (in
, i
)))
1052 /* Return 1 if in between BEG and END, exclusive of BEG and END, there is
1053 no CODE_LABEL insn. */
1056 no_labels_between_p (const rtx_insn
*beg
, const rtx_insn
*end
)
1061 for (p
= NEXT_INSN (beg
); p
!= end
; p
= NEXT_INSN (p
))
1067 /* Nonzero if register REG is used in an insn between
1068 FROM_INSN and TO_INSN (exclusive of those two). */
1071 reg_used_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1072 const rtx_insn
*to_insn
)
1076 if (from_insn
== to_insn
)
1079 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1080 if (NONDEBUG_INSN_P (insn
)
1081 && (reg_overlap_mentioned_p (reg
, PATTERN (insn
))
1082 || (CALL_P (insn
) && find_reg_fusage (insn
, USE
, reg
))))
1087 /* Nonzero if the old value of X, a register, is referenced in BODY. If X
1088 is entirely replaced by a new value and the only use is as a SET_DEST,
1089 we do not consider it a reference. */
1092 reg_referenced_p (const_rtx x
, const_rtx body
)
1096 switch (GET_CODE (body
))
1099 if (reg_overlap_mentioned_p (x
, SET_SRC (body
)))
1102 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
1103 of a REG that occupies all of the REG, the insn references X if
1104 it is mentioned in the destination. */
1105 if (GET_CODE (SET_DEST (body
)) != CC0
1106 && GET_CODE (SET_DEST (body
)) != PC
1107 && !REG_P (SET_DEST (body
))
1108 && ! (GET_CODE (SET_DEST (body
)) == SUBREG
1109 && REG_P (SUBREG_REG (SET_DEST (body
)))
1110 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (body
))))
1111 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
1112 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (body
)))
1113 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
1114 && reg_overlap_mentioned_p (x
, SET_DEST (body
)))
1119 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1120 if (reg_overlap_mentioned_p (x
, ASM_OPERANDS_INPUT (body
, i
)))
1127 return reg_overlap_mentioned_p (x
, body
);
1130 return reg_overlap_mentioned_p (x
, TRAP_CONDITION (body
));
1133 return reg_overlap_mentioned_p (x
, XEXP (body
, 0));
1136 case UNSPEC_VOLATILE
:
1137 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1138 if (reg_overlap_mentioned_p (x
, XVECEXP (body
, 0, i
)))
1143 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1144 if (reg_referenced_p (x
, XVECEXP (body
, 0, i
)))
1149 if (MEM_P (XEXP (body
, 0)))
1150 if (reg_overlap_mentioned_p (x
, XEXP (XEXP (body
, 0), 0)))
1155 if (reg_overlap_mentioned_p (x
, COND_EXEC_TEST (body
)))
1157 return reg_referenced_p (x
, COND_EXEC_CODE (body
));
1164 /* Nonzero if register REG is set or clobbered in an insn between
1165 FROM_INSN and TO_INSN (exclusive of those two). */
1168 reg_set_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1169 const rtx_insn
*to_insn
)
1171 const rtx_insn
*insn
;
1173 if (from_insn
== to_insn
)
1176 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1177 if (INSN_P (insn
) && reg_set_p (reg
, insn
))
1182 /* Return true if REG is set or clobbered inside INSN. */
1185 reg_set_p (const_rtx reg
, const_rtx insn
)
1187 /* After delay slot handling, call and branch insns might be in a
1188 sequence. Check all the elements there. */
1189 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
1191 for (int i
= 0; i
< XVECLEN (PATTERN (insn
), 0); ++i
)
1192 if (reg_set_p (reg
, XVECEXP (PATTERN (insn
), 0, i
)))
1198 /* We can be passed an insn or part of one. If we are passed an insn,
1199 check if a side-effect of the insn clobbers REG. */
1201 && (FIND_REG_INC_NOTE (insn
, reg
)
1204 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
1205 && overlaps_hard_reg_set_p (regs_invalidated_by_call
,
1206 GET_MODE (reg
), REGNO (reg
)))
1208 || find_reg_fusage (insn
, CLOBBER
, reg
)))))
1211 return set_of (reg
, insn
) != NULL_RTX
;
1214 /* Similar to reg_set_between_p, but check all registers in X. Return 0
1215 only if none of them are modified between START and END. Return 1 if
1216 X contains a MEM; this routine does use memory aliasing. */
1219 modified_between_p (const_rtx x
, const rtx_insn
*start
, const rtx_insn
*end
)
1221 const enum rtx_code code
= GET_CODE (x
);
1242 if (modified_between_p (XEXP (x
, 0), start
, end
))
1244 if (MEM_READONLY_P (x
))
1246 for (insn
= NEXT_INSN (start
); insn
!= end
; insn
= NEXT_INSN (insn
))
1247 if (memory_modified_in_insn_p (x
, insn
))
1252 return reg_set_between_p (x
, start
, end
);
1258 fmt
= GET_RTX_FORMAT (code
);
1259 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1261 if (fmt
[i
] == 'e' && modified_between_p (XEXP (x
, i
), start
, end
))
1264 else if (fmt
[i
] == 'E')
1265 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1266 if (modified_between_p (XVECEXP (x
, i
, j
), start
, end
))
1273 /* Similar to reg_set_p, but check all registers in X. Return 0 only if none
1274 of them are modified in INSN. Return 1 if X contains a MEM; this routine
1275 does use memory aliasing. */
1278 modified_in_p (const_rtx x
, const_rtx insn
)
1280 const enum rtx_code code
= GET_CODE (x
);
1297 if (modified_in_p (XEXP (x
, 0), insn
))
1299 if (MEM_READONLY_P (x
))
1301 if (memory_modified_in_insn_p (x
, insn
))
1306 return reg_set_p (x
, insn
);
1312 fmt
= GET_RTX_FORMAT (code
);
1313 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1315 if (fmt
[i
] == 'e' && modified_in_p (XEXP (x
, i
), insn
))
1318 else if (fmt
[i
] == 'E')
1319 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1320 if (modified_in_p (XVECEXP (x
, i
, j
), insn
))
1327 /* Helper function for set_of. */
1335 set_of_1 (rtx x
, const_rtx pat
, void *data1
)
1337 struct set_of_data
*const data
= (struct set_of_data
*) (data1
);
1338 if (rtx_equal_p (x
, data
->pat
)
1339 || (!MEM_P (x
) && reg_overlap_mentioned_p (data
->pat
, x
)))
1343 /* Give an INSN, return a SET or CLOBBER expression that does modify PAT
1344 (either directly or via STRICT_LOW_PART and similar modifiers). */
1346 set_of (const_rtx pat
, const_rtx insn
)
1348 struct set_of_data data
;
1349 data
.found
= NULL_RTX
;
1351 note_stores (INSN_P (insn
) ? PATTERN (insn
) : insn
, set_of_1
, &data
);
1355 /* Add all hard register in X to *PSET. */
1357 find_all_hard_regs (const_rtx x
, HARD_REG_SET
*pset
)
1359 subrtx_iterator::array_type array
;
1360 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
1362 const_rtx x
= *iter
;
1363 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1364 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1368 /* This function, called through note_stores, collects sets and
1369 clobbers of hard registers in a HARD_REG_SET, which is pointed to
1372 record_hard_reg_sets (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
1374 HARD_REG_SET
*pset
= (HARD_REG_SET
*)data
;
1375 if (REG_P (x
) && HARD_REGISTER_P (x
))
1376 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1379 /* Examine INSN, and compute the set of hard registers written by it.
1380 Store it in *PSET. Should only be called after reload. */
1382 find_all_hard_reg_sets (const rtx_insn
*insn
, HARD_REG_SET
*pset
, bool implicit
)
1386 CLEAR_HARD_REG_SET (*pset
);
1387 note_stores (PATTERN (insn
), record_hard_reg_sets
, pset
);
1391 IOR_HARD_REG_SET (*pset
, call_used_reg_set
);
1393 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
1394 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1396 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1397 if (REG_NOTE_KIND (link
) == REG_INC
)
1398 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1401 /* Like record_hard_reg_sets, but called through note_uses. */
1403 record_hard_reg_uses (rtx
*px
, void *data
)
1405 find_all_hard_regs (*px
, (HARD_REG_SET
*) data
);
1408 /* Given an INSN, return a SET expression if this insn has only a single SET.
1409 It may also have CLOBBERs, USEs, or SET whose output
1410 will not be used, which we ignore. */
1413 single_set_2 (const rtx_insn
*insn
, const_rtx pat
)
1416 int set_verified
= 1;
1419 if (GET_CODE (pat
) == PARALLEL
)
1421 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1423 rtx sub
= XVECEXP (pat
, 0, i
);
1424 switch (GET_CODE (sub
))
1431 /* We can consider insns having multiple sets, where all
1432 but one are dead as single set insns. In common case
1433 only single set is present in the pattern so we want
1434 to avoid checking for REG_UNUSED notes unless necessary.
1436 When we reach set first time, we just expect this is
1437 the single set we are looking for and only when more
1438 sets are found in the insn, we check them. */
1441 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (set
))
1442 && !side_effects_p (set
))
1448 set
= sub
, set_verified
= 0;
1449 else if (!find_reg_note (insn
, REG_UNUSED
, SET_DEST (sub
))
1450 || side_effects_p (sub
))
1462 /* Given an INSN, return nonzero if it has more than one SET, else return
1466 multiple_sets (const_rtx insn
)
1471 /* INSN must be an insn. */
1472 if (! INSN_P (insn
))
1475 /* Only a PARALLEL can have multiple SETs. */
1476 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
1478 for (i
= 0, found
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1479 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, i
)) == SET
)
1481 /* If we have already found a SET, then return now. */
1489 /* Either zero or one SET. */
1493 /* Return nonzero if the destination of SET equals the source
1494 and there are no side effects. */
1497 set_noop_p (const_rtx set
)
1499 rtx src
= SET_SRC (set
);
1500 rtx dst
= SET_DEST (set
);
1502 if (dst
== pc_rtx
&& src
== pc_rtx
)
1505 if (MEM_P (dst
) && MEM_P (src
))
1506 return rtx_equal_p (dst
, src
) && !side_effects_p (dst
);
1508 if (GET_CODE (dst
) == ZERO_EXTRACT
)
1509 return rtx_equal_p (XEXP (dst
, 0), src
)
1510 && !BITS_BIG_ENDIAN
&& XEXP (dst
, 2) == const0_rtx
1511 && !side_effects_p (src
);
1513 if (GET_CODE (dst
) == STRICT_LOW_PART
)
1514 dst
= XEXP (dst
, 0);
1516 if (GET_CODE (src
) == SUBREG
&& GET_CODE (dst
) == SUBREG
)
1518 if (SUBREG_BYTE (src
) != SUBREG_BYTE (dst
))
1520 src
= SUBREG_REG (src
);
1521 dst
= SUBREG_REG (dst
);
1524 /* It is a NOOP if destination overlaps with selected src vector
1526 if (GET_CODE (src
) == VEC_SELECT
1527 && REG_P (XEXP (src
, 0)) && REG_P (dst
)
1528 && HARD_REGISTER_P (XEXP (src
, 0))
1529 && HARD_REGISTER_P (dst
))
1532 rtx par
= XEXP (src
, 1);
1533 rtx src0
= XEXP (src
, 0);
1534 int c0
= INTVAL (XVECEXP (par
, 0, 0));
1535 HOST_WIDE_INT offset
= GET_MODE_UNIT_SIZE (GET_MODE (src0
)) * c0
;
1537 for (i
= 1; i
< XVECLEN (par
, 0); i
++)
1538 if (INTVAL (XVECEXP (par
, 0, i
)) != c0
+ i
)
1541 simplify_subreg_regno (REGNO (src0
), GET_MODE (src0
),
1542 offset
, GET_MODE (dst
)) == (int) REGNO (dst
);
1545 return (REG_P (src
) && REG_P (dst
)
1546 && REGNO (src
) == REGNO (dst
));
1549 /* Return nonzero if an insn consists only of SETs, each of which only sets a
1553 noop_move_p (const rtx_insn
*insn
)
1555 rtx pat
= PATTERN (insn
);
1557 if (INSN_CODE (insn
) == NOOP_MOVE_INSN_CODE
)
1560 /* Insns carrying these notes are useful later on. */
1561 if (find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1564 /* Check the code to be executed for COND_EXEC. */
1565 if (GET_CODE (pat
) == COND_EXEC
)
1566 pat
= COND_EXEC_CODE (pat
);
1568 if (GET_CODE (pat
) == SET
&& set_noop_p (pat
))
1571 if (GET_CODE (pat
) == PARALLEL
)
1574 /* If nothing but SETs of registers to themselves,
1575 this insn can also be deleted. */
1576 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1578 rtx tem
= XVECEXP (pat
, 0, i
);
1580 if (GET_CODE (tem
) == USE
1581 || GET_CODE (tem
) == CLOBBER
)
1584 if (GET_CODE (tem
) != SET
|| ! set_noop_p (tem
))
1594 /* Return nonzero if register in range [REGNO, ENDREGNO)
1595 appears either explicitly or implicitly in X
1596 other than being stored into.
1598 References contained within the substructure at LOC do not count.
1599 LOC may be zero, meaning don't ignore anything. */
1602 refers_to_regno_p (unsigned int regno
, unsigned int endregno
, const_rtx x
,
1606 unsigned int x_regno
;
1611 /* The contents of a REG_NONNEG note is always zero, so we must come here
1612 upon repeat in case the last REG_NOTE is a REG_NONNEG note. */
1616 code
= GET_CODE (x
);
1621 x_regno
= REGNO (x
);
1623 /* If we modifying the stack, frame, or argument pointer, it will
1624 clobber a virtual register. In fact, we could be more precise,
1625 but it isn't worth it. */
1626 if ((x_regno
== STACK_POINTER_REGNUM
1627 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1628 && x_regno
== ARG_POINTER_REGNUM
)
1629 || x_regno
== FRAME_POINTER_REGNUM
)
1630 && regno
>= FIRST_VIRTUAL_REGISTER
&& regno
<= LAST_VIRTUAL_REGISTER
)
1633 return endregno
> x_regno
&& regno
< END_REGNO (x
);
1636 /* If this is a SUBREG of a hard reg, we can see exactly which
1637 registers are being modified. Otherwise, handle normally. */
1638 if (REG_P (SUBREG_REG (x
))
1639 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
)
1641 unsigned int inner_regno
= subreg_regno (x
);
1642 unsigned int inner_endregno
1643 = inner_regno
+ (inner_regno
< FIRST_PSEUDO_REGISTER
1644 ? subreg_nregs (x
) : 1);
1646 return endregno
> inner_regno
&& regno
< inner_endregno
;
1652 if (&SET_DEST (x
) != loc
1653 /* Note setting a SUBREG counts as referring to the REG it is in for
1654 a pseudo but not for hard registers since we can
1655 treat each word individually. */
1656 && ((GET_CODE (SET_DEST (x
)) == SUBREG
1657 && loc
!= &SUBREG_REG (SET_DEST (x
))
1658 && REG_P (SUBREG_REG (SET_DEST (x
)))
1659 && REGNO (SUBREG_REG (SET_DEST (x
))) >= FIRST_PSEUDO_REGISTER
1660 && refers_to_regno_p (regno
, endregno
,
1661 SUBREG_REG (SET_DEST (x
)), loc
))
1662 || (!REG_P (SET_DEST (x
))
1663 && refers_to_regno_p (regno
, endregno
, SET_DEST (x
), loc
))))
1666 if (code
== CLOBBER
|| loc
== &SET_SRC (x
))
1675 /* X does not match, so try its subexpressions. */
1677 fmt
= GET_RTX_FORMAT (code
);
1678 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1680 if (fmt
[i
] == 'e' && loc
!= &XEXP (x
, i
))
1688 if (refers_to_regno_p (regno
, endregno
, XEXP (x
, i
), loc
))
1691 else if (fmt
[i
] == 'E')
1694 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1695 if (loc
!= &XVECEXP (x
, i
, j
)
1696 && refers_to_regno_p (regno
, endregno
, XVECEXP (x
, i
, j
), loc
))
1703 /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
1704 we check if any register number in X conflicts with the relevant register
1705 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
1706 contains a MEM (we don't bother checking for memory addresses that can't
1707 conflict because we expect this to be a rare case. */
1710 reg_overlap_mentioned_p (const_rtx x
, const_rtx in
)
1712 unsigned int regno
, endregno
;
1714 /* If either argument is a constant, then modifying X can not
1715 affect IN. Here we look at IN, we can profitably combine
1716 CONSTANT_P (x) with the switch statement below. */
1717 if (CONSTANT_P (in
))
1721 switch (GET_CODE (x
))
1723 case STRICT_LOW_PART
:
1726 /* Overly conservative. */
1731 regno
= REGNO (SUBREG_REG (x
));
1732 if (regno
< FIRST_PSEUDO_REGISTER
)
1733 regno
= subreg_regno (x
);
1734 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
1735 ? subreg_nregs (x
) : 1);
1740 endregno
= END_REGNO (x
);
1742 return refers_to_regno_p (regno
, endregno
, in
, (rtx
*) 0);
1752 fmt
= GET_RTX_FORMAT (GET_CODE (in
));
1753 for (i
= GET_RTX_LENGTH (GET_CODE (in
)) - 1; i
>= 0; i
--)
1756 if (reg_overlap_mentioned_p (x
, XEXP (in
, i
)))
1759 else if (fmt
[i
] == 'E')
1762 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; --j
)
1763 if (reg_overlap_mentioned_p (x
, XVECEXP (in
, i
, j
)))
1773 return reg_mentioned_p (x
, in
);
1779 /* If any register in here refers to it we return true. */
1780 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1781 if (XEXP (XVECEXP (x
, 0, i
), 0) != 0
1782 && reg_overlap_mentioned_p (XEXP (XVECEXP (x
, 0, i
), 0), in
))
1788 gcc_assert (CONSTANT_P (x
));
1793 /* Call FUN on each register or MEM that is stored into or clobbered by X.
1794 (X would be the pattern of an insn). DATA is an arbitrary pointer,
1795 ignored by note_stores, but passed to FUN.
1797 FUN receives three arguments:
1798 1. the REG, MEM, CC0 or PC being stored in or clobbered,
1799 2. the SET or CLOBBER rtx that does the store,
1800 3. the pointer DATA provided to note_stores.
1802 If the item being stored in or clobbered is a SUBREG of a hard register,
1803 the SUBREG will be passed. */
1806 note_stores (const_rtx x
, void (*fun
) (rtx
, const_rtx
, void *), void *data
)
1810 if (GET_CODE (x
) == COND_EXEC
)
1811 x
= COND_EXEC_CODE (x
);
1813 if (GET_CODE (x
) == SET
|| GET_CODE (x
) == CLOBBER
)
1815 rtx dest
= SET_DEST (x
);
1817 while ((GET_CODE (dest
) == SUBREG
1818 && (!REG_P (SUBREG_REG (dest
))
1819 || REGNO (SUBREG_REG (dest
)) >= FIRST_PSEUDO_REGISTER
))
1820 || GET_CODE (dest
) == ZERO_EXTRACT
1821 || GET_CODE (dest
) == STRICT_LOW_PART
)
1822 dest
= XEXP (dest
, 0);
1824 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
1825 each of whose first operand is a register. */
1826 if (GET_CODE (dest
) == PARALLEL
)
1828 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
1829 if (XEXP (XVECEXP (dest
, 0, i
), 0) != 0)
1830 (*fun
) (XEXP (XVECEXP (dest
, 0, i
), 0), x
, data
);
1833 (*fun
) (dest
, x
, data
);
1836 else if (GET_CODE (x
) == PARALLEL
)
1837 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1838 note_stores (XVECEXP (x
, 0, i
), fun
, data
);
1841 /* Like notes_stores, but call FUN for each expression that is being
1842 referenced in PBODY, a pointer to the PATTERN of an insn. We only call
1843 FUN for each expression, not any interior subexpressions. FUN receives a
1844 pointer to the expression and the DATA passed to this function.
1846 Note that this is not quite the same test as that done in reg_referenced_p
1847 since that considers something as being referenced if it is being
1848 partially set, while we do not. */
1851 note_uses (rtx
*pbody
, void (*fun
) (rtx
*, void *), void *data
)
1856 switch (GET_CODE (body
))
1859 (*fun
) (&COND_EXEC_TEST (body
), data
);
1860 note_uses (&COND_EXEC_CODE (body
), fun
, data
);
1864 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1865 note_uses (&XVECEXP (body
, 0, i
), fun
, data
);
1869 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1870 note_uses (&PATTERN (XVECEXP (body
, 0, i
)), fun
, data
);
1874 (*fun
) (&XEXP (body
, 0), data
);
1878 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1879 (*fun
) (&ASM_OPERANDS_INPUT (body
, i
), data
);
1883 (*fun
) (&TRAP_CONDITION (body
), data
);
1887 (*fun
) (&XEXP (body
, 0), data
);
1891 case UNSPEC_VOLATILE
:
1892 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1893 (*fun
) (&XVECEXP (body
, 0, i
), data
);
1897 if (MEM_P (XEXP (body
, 0)))
1898 (*fun
) (&XEXP (XEXP (body
, 0), 0), data
);
1903 rtx dest
= SET_DEST (body
);
1905 /* For sets we replace everything in source plus registers in memory
1906 expression in store and operands of a ZERO_EXTRACT. */
1907 (*fun
) (&SET_SRC (body
), data
);
1909 if (GET_CODE (dest
) == ZERO_EXTRACT
)
1911 (*fun
) (&XEXP (dest
, 1), data
);
1912 (*fun
) (&XEXP (dest
, 2), data
);
1915 while (GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
)
1916 dest
= XEXP (dest
, 0);
1919 (*fun
) (&XEXP (dest
, 0), data
);
1924 /* All the other possibilities never store. */
1925 (*fun
) (pbody
, data
);
1930 /* Return nonzero if X's old contents don't survive after INSN.
1931 This will be true if X is (cc0) or if X is a register and
1932 X dies in INSN or because INSN entirely sets X.
1934 "Entirely set" means set directly and not through a SUBREG, or
1935 ZERO_EXTRACT, so no trace of the old contents remains.
1936 Likewise, REG_INC does not count.
1938 REG may be a hard or pseudo reg. Renumbering is not taken into account,
1939 but for this use that makes no difference, since regs don't overlap
1940 during their lifetimes. Therefore, this function may be used
1941 at any time after deaths have been computed.
1943 If REG is a hard reg that occupies multiple machine registers, this
1944 function will only return 1 if each of those registers will be replaced
1948 dead_or_set_p (const_rtx insn
, const_rtx x
)
1950 unsigned int regno
, end_regno
;
1953 /* Can't use cc0_rtx below since this file is used by genattrtab.c. */
1954 if (GET_CODE (x
) == CC0
)
1957 gcc_assert (REG_P (x
));
1960 end_regno
= END_REGNO (x
);
1961 for (i
= regno
; i
< end_regno
; i
++)
1962 if (! dead_or_set_regno_p (insn
, i
))
1968 /* Return TRUE iff DEST is a register or subreg of a register and
1969 doesn't change the number of words of the inner register, and any
1970 part of the register is TEST_REGNO. */
1973 covers_regno_no_parallel_p (const_rtx dest
, unsigned int test_regno
)
1975 unsigned int regno
, endregno
;
1977 if (GET_CODE (dest
) == SUBREG
1978 && (((GET_MODE_SIZE (GET_MODE (dest
))
1979 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
1980 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
1981 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)))
1982 dest
= SUBREG_REG (dest
);
1987 regno
= REGNO (dest
);
1988 endregno
= END_REGNO (dest
);
1989 return (test_regno
>= regno
&& test_regno
< endregno
);
1992 /* Like covers_regno_no_parallel_p, but also handles PARALLELs where
1993 any member matches the covers_regno_no_parallel_p criteria. */
1996 covers_regno_p (const_rtx dest
, unsigned int test_regno
)
1998 if (GET_CODE (dest
) == PARALLEL
)
2000 /* Some targets place small structures in registers for return
2001 values of functions, and those registers are wrapped in
2002 PARALLELs that we may see as the destination of a SET. */
2005 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
2007 rtx inner
= XEXP (XVECEXP (dest
, 0, i
), 0);
2008 if (inner
!= NULL_RTX
2009 && covers_regno_no_parallel_p (inner
, test_regno
))
2016 return covers_regno_no_parallel_p (dest
, test_regno
);
2019 /* Utility function for dead_or_set_p to check an individual register. */
2022 dead_or_set_regno_p (const_rtx insn
, unsigned int test_regno
)
2026 /* See if there is a death note for something that includes TEST_REGNO. */
2027 if (find_regno_note (insn
, REG_DEAD
, test_regno
))
2031 && find_regno_fusage (insn
, CLOBBER
, test_regno
))
2034 pattern
= PATTERN (insn
);
2036 /* If a COND_EXEC is not executed, the value survives. */
2037 if (GET_CODE (pattern
) == COND_EXEC
)
2040 if (GET_CODE (pattern
) == SET
)
2041 return covers_regno_p (SET_DEST (pattern
), test_regno
);
2042 else if (GET_CODE (pattern
) == PARALLEL
)
2046 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
2048 rtx body
= XVECEXP (pattern
, 0, i
);
2050 if (GET_CODE (body
) == COND_EXEC
)
2051 body
= COND_EXEC_CODE (body
);
2053 if ((GET_CODE (body
) == SET
|| GET_CODE (body
) == CLOBBER
)
2054 && covers_regno_p (SET_DEST (body
), test_regno
))
2062 /* Return the reg-note of kind KIND in insn INSN, if there is one.
2063 If DATUM is nonzero, look for one whose datum is DATUM. */
2066 find_reg_note (const_rtx insn
, enum reg_note kind
, const_rtx datum
)
2070 gcc_checking_assert (insn
);
2072 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2073 if (! INSN_P (insn
))
2077 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2078 if (REG_NOTE_KIND (link
) == kind
)
2083 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2084 if (REG_NOTE_KIND (link
) == kind
&& datum
== XEXP (link
, 0))
2089 /* Return the reg-note of kind KIND in insn INSN which applies to register
2090 number REGNO, if any. Return 0 if there is no such reg-note. Note that
2091 the REGNO of this NOTE need not be REGNO if REGNO is a hard register;
2092 it might be the case that the note overlaps REGNO. */
2095 find_regno_note (const_rtx insn
, enum reg_note kind
, unsigned int regno
)
2099 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2100 if (! INSN_P (insn
))
2103 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2104 if (REG_NOTE_KIND (link
) == kind
2105 /* Verify that it is a register, so that scratch and MEM won't cause a
2107 && REG_P (XEXP (link
, 0))
2108 && REGNO (XEXP (link
, 0)) <= regno
2109 && END_REGNO (XEXP (link
, 0)) > regno
)
2114 /* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and
2118 find_reg_equal_equiv_note (const_rtx insn
)
2125 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2126 if (REG_NOTE_KIND (link
) == REG_EQUAL
2127 || REG_NOTE_KIND (link
) == REG_EQUIV
)
2129 /* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on
2130 insns that have multiple sets. Checking single_set to
2131 make sure of this is not the proper check, as explained
2132 in the comment in set_unique_reg_note.
2134 This should be changed into an assert. */
2135 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
2142 /* Check whether INSN is a single_set whose source is known to be
2143 equivalent to a constant. Return that constant if so, otherwise
2147 find_constant_src (const rtx_insn
*insn
)
2151 set
= single_set (insn
);
2154 x
= avoid_constant_pool_reference (SET_SRC (set
));
2159 note
= find_reg_equal_equiv_note (insn
);
2160 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2161 return XEXP (note
, 0);
2166 /* Return true if DATUM, or any overlap of DATUM, of kind CODE is found
2167 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2170 find_reg_fusage (const_rtx insn
, enum rtx_code code
, const_rtx datum
)
2172 /* If it's not a CALL_INSN, it can't possibly have a
2173 CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */
2183 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
2185 link
= XEXP (link
, 1))
2186 if (GET_CODE (XEXP (link
, 0)) == code
2187 && rtx_equal_p (datum
, XEXP (XEXP (link
, 0), 0)))
2192 unsigned int regno
= REGNO (datum
);
2194 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2195 to pseudo registers, so don't bother checking. */
2197 if (regno
< FIRST_PSEUDO_REGISTER
)
2199 unsigned int end_regno
= END_REGNO (datum
);
2202 for (i
= regno
; i
< end_regno
; i
++)
2203 if (find_regno_fusage (insn
, code
, i
))
2211 /* Return true if REGNO, or any overlap of REGNO, of kind CODE is found
2212 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2215 find_regno_fusage (const_rtx insn
, enum rtx_code code
, unsigned int regno
)
2219 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2220 to pseudo registers, so don't bother checking. */
2222 if (regno
>= FIRST_PSEUDO_REGISTER
2226 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
2230 if (GET_CODE (op
= XEXP (link
, 0)) == code
2231 && REG_P (reg
= XEXP (op
, 0))
2232 && REGNO (reg
) <= regno
2233 && END_REGNO (reg
) > regno
)
2241 /* Return true if KIND is an integer REG_NOTE. */
2244 int_reg_note_p (enum reg_note kind
)
2246 return kind
== REG_BR_PROB
;
2249 /* Allocate a register note with kind KIND and datum DATUM. LIST is
2250 stored as the pointer to the next register note. */
2253 alloc_reg_note (enum reg_note kind
, rtx datum
, rtx list
)
2257 gcc_checking_assert (!int_reg_note_p (kind
));
2262 case REG_LABEL_TARGET
:
2263 case REG_LABEL_OPERAND
:
2265 /* These types of register notes use an INSN_LIST rather than an
2266 EXPR_LIST, so that copying is done right and dumps look
2268 note
= alloc_INSN_LIST (datum
, list
);
2269 PUT_REG_NOTE_KIND (note
, kind
);
2273 note
= alloc_EXPR_LIST (kind
, datum
, list
);
2280 /* Add register note with kind KIND and datum DATUM to INSN. */
2283 add_reg_note (rtx insn
, enum reg_note kind
, rtx datum
)
2285 REG_NOTES (insn
) = alloc_reg_note (kind
, datum
, REG_NOTES (insn
));
2288 /* Add an integer register note with kind KIND and datum DATUM to INSN. */
2291 add_int_reg_note (rtx insn
, enum reg_note kind
, int datum
)
2293 gcc_checking_assert (int_reg_note_p (kind
));
2294 REG_NOTES (insn
) = gen_rtx_INT_LIST ((machine_mode
) kind
,
2295 datum
, REG_NOTES (insn
));
2298 /* Add a register note like NOTE to INSN. */
2301 add_shallow_copy_of_reg_note (rtx_insn
*insn
, rtx note
)
2303 if (GET_CODE (note
) == INT_LIST
)
2304 add_int_reg_note (insn
, REG_NOTE_KIND (note
), XINT (note
, 0));
2306 add_reg_note (insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
2309 /* Duplicate NOTE and return the copy. */
2311 duplicate_reg_note (rtx note
)
2313 reg_note kind
= REG_NOTE_KIND (note
);
2315 if (GET_CODE (note
) == INT_LIST
)
2316 return gen_rtx_INT_LIST ((machine_mode
) kind
, XINT (note
, 0), NULL_RTX
);
2317 else if (GET_CODE (note
) == EXPR_LIST
)
2318 return alloc_reg_note (kind
, copy_insn_1 (XEXP (note
, 0)), NULL_RTX
);
2320 return alloc_reg_note (kind
, XEXP (note
, 0), NULL_RTX
);
2323 /* Remove register note NOTE from the REG_NOTES of INSN. */
2326 remove_note (rtx_insn
*insn
, const_rtx note
)
2330 if (note
== NULL_RTX
)
2333 if (REG_NOTES (insn
) == note
)
2334 REG_NOTES (insn
) = XEXP (note
, 1);
2336 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2337 if (XEXP (link
, 1) == note
)
2339 XEXP (link
, 1) = XEXP (note
, 1);
2343 switch (REG_NOTE_KIND (note
))
2347 df_notes_rescan (insn
);
2354 /* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes. */
2357 remove_reg_equal_equiv_notes (rtx_insn
*insn
)
2361 loc
= ®_NOTES (insn
);
2364 enum reg_note kind
= REG_NOTE_KIND (*loc
);
2365 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
2366 *loc
= XEXP (*loc
, 1);
2368 loc
= &XEXP (*loc
, 1);
2372 /* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO. */
2375 remove_reg_equal_equiv_notes_for_regno (unsigned int regno
)
2382 /* This loop is a little tricky. We cannot just go down the chain because
2383 it is being modified by some actions in the loop. So we just iterate
2384 over the head. We plan to drain the list anyway. */
2385 while ((eq_use
= DF_REG_EQ_USE_CHAIN (regno
)) != NULL
)
2387 rtx_insn
*insn
= DF_REF_INSN (eq_use
);
2388 rtx note
= find_reg_equal_equiv_note (insn
);
2390 /* This assert is generally triggered when someone deletes a REG_EQUAL
2391 or REG_EQUIV note by hacking the list manually rather than calling
2395 remove_note (insn
, note
);
2399 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2400 return 1 if it is found. A simple equality test is used to determine if
2404 in_insn_list_p (const rtx_insn_list
*listp
, const rtx_insn
*node
)
2408 for (x
= listp
; x
; x
= XEXP (x
, 1))
2409 if (node
== XEXP (x
, 0))
2415 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2416 remove that entry from the list if it is found.
2418 A simple equality test is used to determine if NODE matches. */
2421 remove_node_from_expr_list (const_rtx node
, rtx_expr_list
**listp
)
2423 rtx_expr_list
*temp
= *listp
;
2424 rtx_expr_list
*prev
= NULL
;
2428 if (node
== temp
->element ())
2430 /* Splice the node out of the list. */
2432 XEXP (prev
, 1) = temp
->next ();
2434 *listp
= temp
->next ();
2440 temp
= temp
->next ();
2444 /* Search LISTP (an INSN_LIST) for an entry whose first operand is NODE and
2445 remove that entry from the list if it is found.
2447 A simple equality test is used to determine if NODE matches. */
2450 remove_node_from_insn_list (const rtx_insn
*node
, rtx_insn_list
**listp
)
2452 rtx_insn_list
*temp
= *listp
;
2453 rtx_insn_list
*prev
= NULL
;
2457 if (node
== temp
->insn ())
2459 /* Splice the node out of the list. */
2461 XEXP (prev
, 1) = temp
->next ();
2463 *listp
= temp
->next ();
2469 temp
= temp
->next ();
2473 /* Nonzero if X contains any volatile instructions. These are instructions
2474 which may cause unpredictable machine state instructions, and thus no
2475 instructions or register uses should be moved or combined across them.
2476 This includes only volatile asms and UNSPEC_VOLATILE instructions. */
2479 volatile_insn_p (const_rtx x
)
2481 const RTX_CODE code
= GET_CODE (x
);
2499 case UNSPEC_VOLATILE
:
2504 if (MEM_VOLATILE_P (x
))
2511 /* Recursively scan the operands of this expression. */
2514 const char *const fmt
= GET_RTX_FORMAT (code
);
2517 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2521 if (volatile_insn_p (XEXP (x
, i
)))
2524 else if (fmt
[i
] == 'E')
2527 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2528 if (volatile_insn_p (XVECEXP (x
, i
, j
)))
2536 /* Nonzero if X contains any volatile memory references
2537 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
2540 volatile_refs_p (const_rtx x
)
2542 const RTX_CODE code
= GET_CODE (x
);
2558 case UNSPEC_VOLATILE
:
2564 if (MEM_VOLATILE_P (x
))
2571 /* Recursively scan the operands of this expression. */
2574 const char *const fmt
= GET_RTX_FORMAT (code
);
2577 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2581 if (volatile_refs_p (XEXP (x
, i
)))
2584 else if (fmt
[i
] == 'E')
2587 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2588 if (volatile_refs_p (XVECEXP (x
, i
, j
)))
2596 /* Similar to above, except that it also rejects register pre- and post-
2600 side_effects_p (const_rtx x
)
2602 const RTX_CODE code
= GET_CODE (x
);
2619 /* Reject CLOBBER with a non-VOID mode. These are made by combine.c
2620 when some combination can't be done. If we see one, don't think
2621 that we can simplify the expression. */
2622 return (GET_MODE (x
) != VOIDmode
);
2631 case UNSPEC_VOLATILE
:
2637 if (MEM_VOLATILE_P (x
))
2644 /* Recursively scan the operands of this expression. */
2647 const char *fmt
= GET_RTX_FORMAT (code
);
2650 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2654 if (side_effects_p (XEXP (x
, i
)))
2657 else if (fmt
[i
] == 'E')
2660 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2661 if (side_effects_p (XVECEXP (x
, i
, j
)))
2669 /* Return nonzero if evaluating rtx X might cause a trap.
2670 FLAGS controls how to consider MEMs. A nonzero means the context
2671 of the access may have changed from the original, such that the
2672 address may have become invalid. */
2675 may_trap_p_1 (const_rtx x
, unsigned flags
)
2681 /* We make no distinction currently, but this function is part of
2682 the internal target-hooks ABI so we keep the parameter as
2683 "unsigned flags". */
2684 bool code_changed
= flags
!= 0;
2688 code
= GET_CODE (x
);
2691 /* Handle these cases quickly. */
2703 return targetm
.unspec_may_trap_p (x
, flags
);
2705 case UNSPEC_VOLATILE
:
2711 return MEM_VOLATILE_P (x
);
2713 /* Memory ref can trap unless it's a static var or a stack slot. */
2715 /* Recognize specific pattern of stack checking probes. */
2716 if (flag_stack_check
2717 && MEM_VOLATILE_P (x
)
2718 && XEXP (x
, 0) == stack_pointer_rtx
)
2720 if (/* MEM_NOTRAP_P only relates to the actual position of the memory
2721 reference; moving it out of context such as when moving code
2722 when optimizing, might cause its address to become invalid. */
2724 || !MEM_NOTRAP_P (x
))
2726 HOST_WIDE_INT size
= MEM_SIZE_KNOWN_P (x
) ? MEM_SIZE (x
) : 0;
2727 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), 0, size
,
2728 GET_MODE (x
), code_changed
);
2733 /* Division by a non-constant might trap. */
2738 if (HONOR_SNANS (x
))
2740 if (SCALAR_FLOAT_MODE_P (GET_MODE (x
)))
2741 return flag_trapping_math
;
2742 if (!CONSTANT_P (XEXP (x
, 1)) || (XEXP (x
, 1) == const0_rtx
))
2747 /* An EXPR_LIST is used to represent a function call. This
2748 certainly may trap. */
2757 /* Some floating point comparisons may trap. */
2758 if (!flag_trapping_math
)
2760 /* ??? There is no machine independent way to check for tests that trap
2761 when COMPARE is used, though many targets do make this distinction.
2762 For instance, sparc uses CCFPE for compares which generate exceptions
2763 and CCFP for compares which do not generate exceptions. */
2766 /* But often the compare has some CC mode, so check operand
2768 if (HONOR_NANS (XEXP (x
, 0))
2769 || HONOR_NANS (XEXP (x
, 1)))
2775 if (HONOR_SNANS (x
))
2777 /* Often comparison is CC mode, so check operand modes. */
2778 if (HONOR_SNANS (XEXP (x
, 0))
2779 || HONOR_SNANS (XEXP (x
, 1)))
2784 /* Conversion of floating point might trap. */
2785 if (flag_trapping_math
&& HONOR_NANS (XEXP (x
, 0)))
2792 /* These operations don't trap even with floating point. */
2796 /* Any floating arithmetic may trap. */
2797 if (SCALAR_FLOAT_MODE_P (GET_MODE (x
)) && flag_trapping_math
)
2801 fmt
= GET_RTX_FORMAT (code
);
2802 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2806 if (may_trap_p_1 (XEXP (x
, i
), flags
))
2809 else if (fmt
[i
] == 'E')
2812 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2813 if (may_trap_p_1 (XVECEXP (x
, i
, j
), flags
))
2820 /* Return nonzero if evaluating rtx X might cause a trap. */
2823 may_trap_p (const_rtx x
)
2825 return may_trap_p_1 (x
, 0);
2828 /* Same as above, but additionally return nonzero if evaluating rtx X might
2829 cause a fault. We define a fault for the purpose of this function as a
2830 erroneous execution condition that cannot be encountered during the normal
2831 execution of a valid program; the typical example is an unaligned memory
2832 access on a strict alignment machine. The compiler guarantees that it
2833 doesn't generate code that will fault from a valid program, but this
2834 guarantee doesn't mean anything for individual instructions. Consider
2835 the following example:
2837 struct S { int d; union { char *cp; int *ip; }; };
2839 int foo(struct S *s)
2847 on a strict alignment machine. In a valid program, foo will never be
2848 invoked on a structure for which d is equal to 1 and the underlying
2849 unique field of the union not aligned on a 4-byte boundary, but the
2850 expression *s->ip might cause a fault if considered individually.
2852 At the RTL level, potentially problematic expressions will almost always
2853 verify may_trap_p; for example, the above dereference can be emitted as
2854 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register.
2855 However, suppose that foo is inlined in a caller that causes s->cp to
2856 point to a local character variable and guarantees that s->d is not set
2857 to 1; foo may have been effectively translated into pseudo-RTL as:
2860 (set (reg:SI) (mem:SI (%fp - 7)))
2862 (set (reg:QI) (mem:QI (%fp - 7)))
2864 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a
2865 memory reference to a stack slot, but it will certainly cause a fault
2866 on a strict alignment machine. */
2869 may_trap_or_fault_p (const_rtx x
)
2871 return may_trap_p_1 (x
, 1);
2874 /* Return nonzero if X contains a comparison that is not either EQ or NE,
2875 i.e., an inequality. */
2878 inequality_comparisons_p (const_rtx x
)
2882 const enum rtx_code code
= GET_CODE (x
);
2910 len
= GET_RTX_LENGTH (code
);
2911 fmt
= GET_RTX_FORMAT (code
);
2913 for (i
= 0; i
< len
; i
++)
2917 if (inequality_comparisons_p (XEXP (x
, i
)))
2920 else if (fmt
[i
] == 'E')
2923 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2924 if (inequality_comparisons_p (XVECEXP (x
, i
, j
)))
2932 /* Replace any occurrence of FROM in X with TO. The function does
2933 not enter into CONST_DOUBLE for the replace.
2935 Note that copying is not done so X must not be shared unless all copies
2938 ALL_REGS is true if we want to replace all REGs equal to FROM, not just
2939 those pointer-equal ones. */
2942 replace_rtx (rtx x
, rtx from
, rtx to
, bool all_regs
)
2950 /* Allow this function to make replacements in EXPR_LISTs. */
2957 && REGNO (x
) == REGNO (from
))
2959 gcc_assert (GET_MODE (x
) == GET_MODE (from
));
2962 else if (GET_CODE (x
) == SUBREG
)
2964 rtx new_rtx
= replace_rtx (SUBREG_REG (x
), from
, to
, all_regs
);
2966 if (CONST_INT_P (new_rtx
))
2968 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
2969 GET_MODE (SUBREG_REG (x
)),
2974 SUBREG_REG (x
) = new_rtx
;
2978 else if (GET_CODE (x
) == ZERO_EXTEND
)
2980 rtx new_rtx
= replace_rtx (XEXP (x
, 0), from
, to
, all_regs
);
2982 if (CONST_INT_P (new_rtx
))
2984 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
2985 new_rtx
, GET_MODE (XEXP (x
, 0)));
2989 XEXP (x
, 0) = new_rtx
;
2994 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
2995 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
2998 XEXP (x
, i
) = replace_rtx (XEXP (x
, i
), from
, to
, all_regs
);
2999 else if (fmt
[i
] == 'E')
3000 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3001 XVECEXP (x
, i
, j
) = replace_rtx (XVECEXP (x
, i
, j
),
3002 from
, to
, all_regs
);
3008 /* Replace occurrences of the OLD_LABEL in *LOC with NEW_LABEL. Also track
3009 the change in LABEL_NUSES if UPDATE_LABEL_NUSES. */
3012 replace_label (rtx
*loc
, rtx old_label
, rtx new_label
, bool update_label_nuses
)
3014 /* Handle jump tables specially, since ADDR_{DIFF_,}VECs can be long. */
3016 if (JUMP_TABLE_DATA_P (x
))
3019 rtvec vec
= XVEC (x
, GET_CODE (x
) == ADDR_DIFF_VEC
);
3020 int len
= GET_NUM_ELEM (vec
);
3021 for (int i
= 0; i
< len
; ++i
)
3023 rtx ref
= RTVEC_ELT (vec
, i
);
3024 if (XEXP (ref
, 0) == old_label
)
3026 XEXP (ref
, 0) = new_label
;
3027 if (update_label_nuses
)
3029 ++LABEL_NUSES (new_label
);
3030 --LABEL_NUSES (old_label
);
3037 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
3038 field. This is not handled by the iterator because it doesn't
3039 handle unprinted ('0') fields. */
3040 if (JUMP_P (x
) && JUMP_LABEL (x
) == old_label
)
3041 JUMP_LABEL (x
) = new_label
;
3043 subrtx_ptr_iterator::array_type array
;
3044 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
3049 if (GET_CODE (x
) == SYMBOL_REF
3050 && CONSTANT_POOL_ADDRESS_P (x
))
3052 rtx c
= get_pool_constant (x
);
3053 if (rtx_referenced_p (old_label
, c
))
3055 /* Create a copy of constant C; replace the label inside
3056 but do not update LABEL_NUSES because uses in constant pool
3058 rtx new_c
= copy_rtx (c
);
3059 replace_label (&new_c
, old_label
, new_label
, false);
3061 /* Add the new constant NEW_C to constant pool and replace
3062 the old reference to constant by new reference. */
3063 rtx new_mem
= force_const_mem (get_pool_mode (x
), new_c
);
3064 *loc
= replace_rtx (x
, x
, XEXP (new_mem
, 0));
3068 if ((GET_CODE (x
) == LABEL_REF
3069 || GET_CODE (x
) == INSN_LIST
)
3070 && XEXP (x
, 0) == old_label
)
3072 XEXP (x
, 0) = new_label
;
3073 if (update_label_nuses
)
3075 ++LABEL_NUSES (new_label
);
3076 --LABEL_NUSES (old_label
);
3084 replace_label_in_insn (rtx_insn
*insn
, rtx old_label
, rtx new_label
,
3085 bool update_label_nuses
)
3087 rtx insn_as_rtx
= insn
;
3088 replace_label (&insn_as_rtx
, old_label
, new_label
, update_label_nuses
);
3089 gcc_checking_assert (insn_as_rtx
== insn
);
3092 /* Return true if X is referenced in BODY. */
3095 rtx_referenced_p (const_rtx x
, const_rtx body
)
3097 subrtx_iterator::array_type array
;
3098 FOR_EACH_SUBRTX (iter
, array
, body
, ALL
)
3099 if (const_rtx y
= *iter
)
3101 /* Check if a label_ref Y refers to label X. */
3102 if (GET_CODE (y
) == LABEL_REF
3104 && label_ref_label (y
) == x
)
3107 if (rtx_equal_p (x
, y
))
3110 /* If Y is a reference to pool constant traverse the constant. */
3111 if (GET_CODE (y
) == SYMBOL_REF
3112 && CONSTANT_POOL_ADDRESS_P (y
))
3113 iter
.substitute (get_pool_constant (y
));
3118 /* If INSN is a tablejump return true and store the label (before jump table) to
3119 *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */
3122 tablejump_p (const rtx_insn
*insn
, rtx_insn
**labelp
,
3123 rtx_jump_table_data
**tablep
)
3128 rtx target
= JUMP_LABEL (insn
);
3129 if (target
== NULL_RTX
|| ANY_RETURN_P (target
))
3132 rtx_insn
*label
= as_a
<rtx_insn
*> (target
);
3133 rtx_insn
*table
= next_insn (label
);
3134 if (table
== NULL_RTX
|| !JUMP_TABLE_DATA_P (table
))
3140 *tablep
= as_a
<rtx_jump_table_data
*> (table
);
3144 /* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or
3145 constant that is not in the constant pool and not in the condition
3146 of an IF_THEN_ELSE. */
3149 computed_jump_p_1 (const_rtx x
)
3151 const enum rtx_code code
= GET_CODE (x
);
3168 return ! (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
3169 && CONSTANT_POOL_ADDRESS_P (XEXP (x
, 0)));
3172 return (computed_jump_p_1 (XEXP (x
, 1))
3173 || computed_jump_p_1 (XEXP (x
, 2)));
3179 fmt
= GET_RTX_FORMAT (code
);
3180 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3183 && computed_jump_p_1 (XEXP (x
, i
)))
3186 else if (fmt
[i
] == 'E')
3187 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3188 if (computed_jump_p_1 (XVECEXP (x
, i
, j
)))
3195 /* Return nonzero if INSN is an indirect jump (aka computed jump).
3197 Tablejumps and casesi insns are not considered indirect jumps;
3198 we can recognize them by a (use (label_ref)). */
3201 computed_jump_p (const rtx_insn
*insn
)
3206 rtx pat
= PATTERN (insn
);
3208 /* If we have a JUMP_LABEL set, we're not a computed jump. */
3209 if (JUMP_LABEL (insn
) != NULL
)
3212 if (GET_CODE (pat
) == PARALLEL
)
3214 int len
= XVECLEN (pat
, 0);
3215 int has_use_labelref
= 0;
3217 for (i
= len
- 1; i
>= 0; i
--)
3218 if (GET_CODE (XVECEXP (pat
, 0, i
)) == USE
3219 && (GET_CODE (XEXP (XVECEXP (pat
, 0, i
), 0))
3222 has_use_labelref
= 1;
3226 if (! has_use_labelref
)
3227 for (i
= len
- 1; i
>= 0; i
--)
3228 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
3229 && SET_DEST (XVECEXP (pat
, 0, i
)) == pc_rtx
3230 && computed_jump_p_1 (SET_SRC (XVECEXP (pat
, 0, i
))))
3233 else if (GET_CODE (pat
) == SET
3234 && SET_DEST (pat
) == pc_rtx
3235 && computed_jump_p_1 (SET_SRC (pat
)))
3243 /* MEM has a PRE/POST-INC/DEC/MODIFY address X. Extract the operands of
3244 the equivalent add insn and pass the result to FN, using DATA as the
3248 for_each_inc_dec_find_inc_dec (rtx mem
, for_each_inc_dec_fn fn
, void *data
)
3250 rtx x
= XEXP (mem
, 0);
3251 switch (GET_CODE (x
))
3256 int size
= GET_MODE_SIZE (GET_MODE (mem
));
3257 rtx r1
= XEXP (x
, 0);
3258 rtx c
= gen_int_mode (size
, GET_MODE (r1
));
3259 return fn (mem
, x
, r1
, r1
, c
, data
);
3265 int size
= GET_MODE_SIZE (GET_MODE (mem
));
3266 rtx r1
= XEXP (x
, 0);
3267 rtx c
= gen_int_mode (-size
, GET_MODE (r1
));
3268 return fn (mem
, x
, r1
, r1
, c
, data
);
3274 rtx r1
= XEXP (x
, 0);
3275 rtx add
= XEXP (x
, 1);
3276 return fn (mem
, x
, r1
, add
, NULL
, data
);
3284 /* Traverse *LOC looking for MEMs that have autoinc addresses.
3285 For each such autoinc operation found, call FN, passing it
3286 the innermost enclosing MEM, the operation itself, the RTX modified
3287 by the operation, two RTXs (the second may be NULL) that, once
3288 added, represent the value to be held by the modified RTX
3289 afterwards, and DATA. FN is to return 0 to continue the
3290 traversal or any other value to have it returned to the caller of
3291 for_each_inc_dec. */
3294 for_each_inc_dec (rtx x
,
3295 for_each_inc_dec_fn fn
,
3298 subrtx_var_iterator::array_type array
;
3299 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
3304 && GET_RTX_CLASS (GET_CODE (XEXP (mem
, 0))) == RTX_AUTOINC
)
3306 int res
= for_each_inc_dec_find_inc_dec (mem
, fn
, data
);
3309 iter
.skip_subrtxes ();
3316 /* Searches X for any reference to REGNO, returning the rtx of the
3317 reference found if any. Otherwise, returns NULL_RTX. */
3320 regno_use_in (unsigned int regno
, rtx x
)
3326 if (REG_P (x
) && REGNO (x
) == regno
)
3329 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3330 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3334 if ((tem
= regno_use_in (regno
, XEXP (x
, i
))))
3337 else if (fmt
[i
] == 'E')
3338 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3339 if ((tem
= regno_use_in (regno
, XVECEXP (x
, i
, j
))))
3346 /* Return a value indicating whether OP, an operand of a commutative
3347 operation, is preferred as the first or second operand. The more
3348 positive the value, the stronger the preference for being the first
3352 commutative_operand_precedence (rtx op
)
3354 enum rtx_code code
= GET_CODE (op
);
3356 /* Constants always become the second operand. Prefer "nice" constants. */
3357 if (code
== CONST_INT
)
3359 if (code
== CONST_WIDE_INT
)
3361 if (code
== CONST_DOUBLE
)
3363 if (code
== CONST_FIXED
)
3365 op
= avoid_constant_pool_reference (op
);
3366 code
= GET_CODE (op
);
3368 switch (GET_RTX_CLASS (code
))
3371 if (code
== CONST_INT
)
3373 if (code
== CONST_WIDE_INT
)
3375 if (code
== CONST_DOUBLE
)
3377 if (code
== CONST_FIXED
)
3382 /* SUBREGs of objects should come second. */
3383 if (code
== SUBREG
&& OBJECT_P (SUBREG_REG (op
)))
3388 /* Complex expressions should be the first, so decrease priority
3389 of objects. Prefer pointer objects over non pointer objects. */
3390 if ((REG_P (op
) && REG_POINTER (op
))
3391 || (MEM_P (op
) && MEM_POINTER (op
)))
3395 case RTX_COMM_ARITH
:
3396 /* Prefer operands that are themselves commutative to be first.
3397 This helps to make things linear. In particular,
3398 (and (and (reg) (reg)) (not (reg))) is canonical. */
3402 /* If only one operand is a binary expression, it will be the first
3403 operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
3404 is canonical, although it will usually be further simplified. */
3408 /* Then prefer NEG and NOT. */
3409 if (code
== NEG
|| code
== NOT
)
3418 /* Return 1 iff it is necessary to swap operands of commutative operation
3419 in order to canonicalize expression. */
3422 swap_commutative_operands_p (rtx x
, rtx y
)
3424 return (commutative_operand_precedence (x
)
3425 < commutative_operand_precedence (y
));
3428 /* Return 1 if X is an autoincrement side effect and the register is
3429 not the stack pointer. */
3431 auto_inc_p (const_rtx x
)
3433 switch (GET_CODE (x
))
3441 /* There are no REG_INC notes for SP. */
3442 if (XEXP (x
, 0) != stack_pointer_rtx
)
3450 /* Return nonzero if IN contains a piece of rtl that has the address LOC. */
3452 loc_mentioned_in_p (rtx
*loc
, const_rtx in
)
3461 code
= GET_CODE (in
);
3462 fmt
= GET_RTX_FORMAT (code
);
3463 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3467 if (loc
== &XEXP (in
, i
) || loc_mentioned_in_p (loc
, XEXP (in
, i
)))
3470 else if (fmt
[i
] == 'E')
3471 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
3472 if (loc
== &XVECEXP (in
, i
, j
)
3473 || loc_mentioned_in_p (loc
, XVECEXP (in
, i
, j
)))
3479 /* Helper function for subreg_lsb. Given a subreg's OUTER_MODE, INNER_MODE,
3480 and SUBREG_BYTE, return the bit offset where the subreg begins
3481 (counting from the least significant bit of the operand). */
3484 subreg_lsb_1 (machine_mode outer_mode
,
3485 machine_mode inner_mode
,
3486 unsigned int subreg_byte
)
3488 unsigned int bitpos
;
3492 /* A paradoxical subreg begins at bit position 0. */
3493 if (GET_MODE_PRECISION (outer_mode
) > GET_MODE_PRECISION (inner_mode
))
3496 if (WORDS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
3497 /* If the subreg crosses a word boundary ensure that
3498 it also begins and ends on a word boundary. */
3499 gcc_assert (!((subreg_byte
% UNITS_PER_WORD
3500 + GET_MODE_SIZE (outer_mode
)) > UNITS_PER_WORD
3501 && (subreg_byte
% UNITS_PER_WORD
3502 || GET_MODE_SIZE (outer_mode
) % UNITS_PER_WORD
)));
3504 if (WORDS_BIG_ENDIAN
)
3505 word
= (GET_MODE_SIZE (inner_mode
)
3506 - (subreg_byte
+ GET_MODE_SIZE (outer_mode
))) / UNITS_PER_WORD
;
3508 word
= subreg_byte
/ UNITS_PER_WORD
;
3509 bitpos
= word
* BITS_PER_WORD
;
3511 if (BYTES_BIG_ENDIAN
)
3512 byte
= (GET_MODE_SIZE (inner_mode
)
3513 - (subreg_byte
+ GET_MODE_SIZE (outer_mode
))) % UNITS_PER_WORD
;
3515 byte
= subreg_byte
% UNITS_PER_WORD
;
3516 bitpos
+= byte
* BITS_PER_UNIT
;
3521 /* Given a subreg X, return the bit offset where the subreg begins
3522 (counting from the least significant bit of the reg). */
3525 subreg_lsb (const_rtx x
)
3527 return subreg_lsb_1 (GET_MODE (x
), GET_MODE (SUBREG_REG (x
)),
3531 /* Fill in information about a subreg of a hard register.
3532 xregno - A regno of an inner hard subreg_reg (or what will become one).
3533 xmode - The mode of xregno.
3534 offset - The byte offset.
3535 ymode - The mode of a top level SUBREG (or what may become one).
3536 info - Pointer to structure to fill in.
3538 Rather than considering one particular inner register (and thus one
3539 particular "outer" register) in isolation, this function really uses
3540 XREGNO as a model for a sequence of isomorphic hard registers. Thus the
3541 function does not check whether adding INFO->offset to XREGNO gives
3542 a valid hard register; even if INFO->offset + XREGNO is out of range,
3543 there might be another register of the same type that is in range.
3544 Likewise it doesn't check whether HARD_REGNO_MODE_OK accepts the new
3545 register, since that can depend on things like whether the final
3546 register number is even or odd. Callers that want to check whether
3547 this particular subreg can be replaced by a simple (reg ...) should
3548 use simplify_subreg_regno. */
3551 subreg_get_info (unsigned int xregno
, machine_mode xmode
,
3552 unsigned int offset
, machine_mode ymode
,
3553 struct subreg_info
*info
)
3555 int nregs_xmode
, nregs_ymode
;
3556 int mode_multiple
, nregs_multiple
;
3557 int offset_adj
, y_offset
, y_offset_adj
;
3558 int regsize_xmode
, regsize_ymode
;
3561 gcc_assert (xregno
< FIRST_PSEUDO_REGISTER
);
3565 /* If there are holes in a non-scalar mode in registers, we expect
3566 that it is made up of its units concatenated together. */
3567 if (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
))
3569 machine_mode xmode_unit
;
3571 nregs_xmode
= HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode
);
3572 xmode_unit
= GET_MODE_INNER (xmode
);
3573 gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode_unit
));
3574 gcc_assert (nregs_xmode
3575 == (GET_MODE_NUNITS (xmode
)
3576 * HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode_unit
)));
3577 gcc_assert (hard_regno_nregs
[xregno
][xmode
]
3578 == (hard_regno_nregs
[xregno
][xmode_unit
]
3579 * GET_MODE_NUNITS (xmode
)));
3581 /* You can only ask for a SUBREG of a value with holes in the middle
3582 if you don't cross the holes. (Such a SUBREG should be done by
3583 picking a different register class, or doing it in memory if
3584 necessary.) An example of a value with holes is XCmode on 32-bit
3585 x86 with -m128bit-long-double; it's represented in 6 32-bit registers,
3586 3 for each part, but in memory it's two 128-bit parts.
3587 Padding is assumed to be at the end (not necessarily the 'high part')
3589 if ((offset
/ GET_MODE_SIZE (xmode_unit
) + 1
3590 < GET_MODE_NUNITS (xmode
))
3591 && (offset
/ GET_MODE_SIZE (xmode_unit
)
3592 != ((offset
+ GET_MODE_SIZE (ymode
) - 1)
3593 / GET_MODE_SIZE (xmode_unit
))))
3595 info
->representable_p
= false;
3600 nregs_xmode
= hard_regno_nregs
[xregno
][xmode
];
3602 nregs_ymode
= hard_regno_nregs
[xregno
][ymode
];
3604 /* Paradoxical subregs are otherwise valid. */
3607 && GET_MODE_PRECISION (ymode
) > GET_MODE_PRECISION (xmode
))
3609 info
->representable_p
= true;
3610 /* If this is a big endian paradoxical subreg, which uses more
3611 actual hard registers than the original register, we must
3612 return a negative offset so that we find the proper highpart
3614 if (GET_MODE_SIZE (ymode
) > UNITS_PER_WORD
3615 ? REG_WORDS_BIG_ENDIAN
: BYTES_BIG_ENDIAN
)
3616 info
->offset
= nregs_xmode
- nregs_ymode
;
3619 info
->nregs
= nregs_ymode
;
3623 /* If registers store different numbers of bits in the different
3624 modes, we cannot generally form this subreg. */
3625 if (!HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
)
3626 && !HARD_REGNO_NREGS_HAS_PADDING (xregno
, ymode
)
3627 && (GET_MODE_SIZE (xmode
) % nregs_xmode
) == 0
3628 && (GET_MODE_SIZE (ymode
) % nregs_ymode
) == 0)
3630 regsize_xmode
= GET_MODE_SIZE (xmode
) / nregs_xmode
;
3631 regsize_ymode
= GET_MODE_SIZE (ymode
) / nregs_ymode
;
3632 if (!rknown
&& regsize_xmode
> regsize_ymode
&& nregs_ymode
> 1)
3634 info
->representable_p
= false;
3636 = (GET_MODE_SIZE (ymode
) + regsize_xmode
- 1) / regsize_xmode
;
3637 info
->offset
= offset
/ regsize_xmode
;
3640 if (!rknown
&& regsize_ymode
> regsize_xmode
&& nregs_xmode
> 1)
3642 info
->representable_p
= false;
3644 = (GET_MODE_SIZE (ymode
) + regsize_xmode
- 1) / regsize_xmode
;
3645 info
->offset
= offset
/ regsize_xmode
;
3648 /* It's not valid to extract a subreg of mode YMODE at OFFSET that
3649 would go outside of XMODE. */
3651 && GET_MODE_SIZE (ymode
) + offset
> GET_MODE_SIZE (xmode
))
3653 info
->representable_p
= false;
3654 info
->nregs
= nregs_ymode
;
3655 info
->offset
= offset
/ regsize_xmode
;
3658 /* Quick exit for the simple and common case of extracting whole
3659 subregisters from a multiregister value. */
3660 /* ??? It would be better to integrate this into the code below,
3661 if we can generalize the concept enough and figure out how
3662 odd-sized modes can coexist with the other weird cases we support. */
3664 && WORDS_BIG_ENDIAN
== REG_WORDS_BIG_ENDIAN
3665 && regsize_xmode
== regsize_ymode
3666 && (offset
% regsize_ymode
) == 0)
3668 info
->representable_p
= true;
3669 info
->nregs
= nregs_ymode
;
3670 info
->offset
= offset
/ regsize_ymode
;
3671 gcc_assert (info
->offset
+ info
->nregs
<= nregs_xmode
);
3676 /* Lowpart subregs are otherwise valid. */
3677 if (!rknown
&& offset
== subreg_lowpart_offset (ymode
, xmode
))
3679 info
->representable_p
= true;
3682 if (offset
== 0 || nregs_xmode
== nregs_ymode
)
3685 info
->nregs
= nregs_ymode
;
3690 /* This should always pass, otherwise we don't know how to verify
3691 the constraint. These conditions may be relaxed but
3692 subreg_regno_offset would need to be redesigned. */
3693 gcc_assert ((GET_MODE_SIZE (xmode
) % GET_MODE_SIZE (ymode
)) == 0);
3694 gcc_assert ((nregs_xmode
% nregs_ymode
) == 0);
3696 if (WORDS_BIG_ENDIAN
!= REG_WORDS_BIG_ENDIAN
3697 && GET_MODE_SIZE (xmode
) > UNITS_PER_WORD
)
3699 HOST_WIDE_INT xsize
= GET_MODE_SIZE (xmode
);
3700 HOST_WIDE_INT ysize
= GET_MODE_SIZE (ymode
);
3701 HOST_WIDE_INT off_low
= offset
& (ysize
- 1);
3702 HOST_WIDE_INT off_high
= offset
& ~(ysize
- 1);
3703 offset
= (xsize
- ysize
- off_high
) | off_low
;
3705 /* The XMODE value can be seen as a vector of NREGS_XMODE
3706 values. The subreg must represent a lowpart of given field.
3707 Compute what field it is. */
3708 offset_adj
= offset
;
3709 offset_adj
-= subreg_lowpart_offset (ymode
,
3710 mode_for_size (GET_MODE_BITSIZE (xmode
)
3714 /* Size of ymode must not be greater than the size of xmode. */
3715 mode_multiple
= GET_MODE_SIZE (xmode
) / GET_MODE_SIZE (ymode
);
3716 gcc_assert (mode_multiple
!= 0);
3718 y_offset
= offset
/ GET_MODE_SIZE (ymode
);
3719 y_offset_adj
= offset_adj
/ GET_MODE_SIZE (ymode
);
3720 nregs_multiple
= nregs_xmode
/ nregs_ymode
;
3722 gcc_assert ((offset_adj
% GET_MODE_SIZE (ymode
)) == 0);
3723 gcc_assert ((mode_multiple
% nregs_multiple
) == 0);
3727 info
->representable_p
= (!(y_offset_adj
% (mode_multiple
/ nregs_multiple
)));
3730 info
->offset
= (y_offset
/ (mode_multiple
/ nregs_multiple
)) * nregs_ymode
;
3731 info
->nregs
= nregs_ymode
;
3734 /* This function returns the regno offset of a subreg expression.
3735 xregno - A regno of an inner hard subreg_reg (or what will become one).
3736 xmode - The mode of xregno.
3737 offset - The byte offset.
3738 ymode - The mode of a top level SUBREG (or what may become one).
3739 RETURN - The regno offset which would be used. */
3741 subreg_regno_offset (unsigned int xregno
, machine_mode xmode
,
3742 unsigned int offset
, machine_mode ymode
)
3744 struct subreg_info info
;
3745 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3749 /* This function returns true when the offset is representable via
3750 subreg_offset in the given regno.
3751 xregno - A regno of an inner hard subreg_reg (or what will become one).
3752 xmode - The mode of xregno.
3753 offset - The byte offset.
3754 ymode - The mode of a top level SUBREG (or what may become one).
3755 RETURN - Whether the offset is representable. */
3757 subreg_offset_representable_p (unsigned int xregno
, machine_mode xmode
,
3758 unsigned int offset
, machine_mode ymode
)
3760 struct subreg_info info
;
3761 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3762 return info
.representable_p
;
3765 /* Return the number of a YMODE register to which
3767 (subreg:YMODE (reg:XMODE XREGNO) OFFSET)
3769 can be simplified. Return -1 if the subreg can't be simplified.
3771 XREGNO is a hard register number. */
3774 simplify_subreg_regno (unsigned int xregno
, machine_mode xmode
,
3775 unsigned int offset
, machine_mode ymode
)
3777 struct subreg_info info
;
3778 unsigned int yregno
;
3780 #ifdef CANNOT_CHANGE_MODE_CLASS
3781 /* Give the backend a chance to disallow the mode change. */
3782 if (GET_MODE_CLASS (xmode
) != MODE_COMPLEX_INT
3783 && GET_MODE_CLASS (xmode
) != MODE_COMPLEX_FLOAT
3784 && REG_CANNOT_CHANGE_MODE_P (xregno
, xmode
, ymode
)
3785 /* We can use mode change in LRA for some transformations. */
3786 && ! lra_in_progress
)
3790 /* We shouldn't simplify stack-related registers. */
3791 if ((!reload_completed
|| frame_pointer_needed
)
3792 && xregno
== FRAME_POINTER_REGNUM
)
3795 if (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
3796 && xregno
== ARG_POINTER_REGNUM
)
3799 if (xregno
== STACK_POINTER_REGNUM
3800 /* We should convert hard stack register in LRA if it is
3802 && ! lra_in_progress
)
3805 /* Try to get the register offset. */
3806 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3807 if (!info
.representable_p
)
3810 /* Make sure that the offsetted register value is in range. */
3811 yregno
= xregno
+ info
.offset
;
3812 if (!HARD_REGISTER_NUM_P (yregno
))
3815 /* See whether (reg:YMODE YREGNO) is valid.
3817 ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid.
3818 This is a kludge to work around how complex FP arguments are passed
3819 on IA-64 and should be fixed. See PR target/49226. */
3820 if (!HARD_REGNO_MODE_OK (yregno
, ymode
)
3821 && HARD_REGNO_MODE_OK (xregno
, xmode
))
3824 return (int) yregno
;
3827 /* Return the final regno that a subreg expression refers to. */
3829 subreg_regno (const_rtx x
)
3832 rtx subreg
= SUBREG_REG (x
);
3833 int regno
= REGNO (subreg
);
3835 ret
= regno
+ subreg_regno_offset (regno
,
3843 /* Return the number of registers that a subreg expression refers
3846 subreg_nregs (const_rtx x
)
3848 return subreg_nregs_with_regno (REGNO (SUBREG_REG (x
)), x
);
3851 /* Return the number of registers that a subreg REG with REGNO
3852 expression refers to. This is a copy of the rtlanal.c:subreg_nregs
3853 changed so that the regno can be passed in. */
3856 subreg_nregs_with_regno (unsigned int regno
, const_rtx x
)
3858 struct subreg_info info
;
3859 rtx subreg
= SUBREG_REG (x
);
3861 subreg_get_info (regno
, GET_MODE (subreg
), SUBREG_BYTE (x
), GET_MODE (x
),
3866 /* If loads from memories of mode MODE always sign or zero extend,
3867 return SIGN_EXTEND or ZERO_EXTEND as appropriate. Return UNKNOWN
3871 load_extend_op (machine_mode mode
)
3873 if (SCALAR_INT_MODE_P (mode
)
3874 && GET_MODE_PRECISION (mode
) < BITS_PER_WORD
)
3875 return LOAD_EXTEND_OP (mode
);
3879 struct parms_set_data
3885 /* Helper function for noticing stores to parameter registers. */
3887 parms_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
3889 struct parms_set_data
*const d
= (struct parms_set_data
*) data
;
3890 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
3891 && TEST_HARD_REG_BIT (d
->regs
, REGNO (x
)))
3893 CLEAR_HARD_REG_BIT (d
->regs
, REGNO (x
));
3898 /* Look backward for first parameter to be loaded.
3899 Note that loads of all parameters will not necessarily be
3900 found if CSE has eliminated some of them (e.g., an argument
3901 to the outer function is passed down as a parameter).
3902 Do not skip BOUNDARY. */
3904 find_first_parameter_load (rtx_insn
*call_insn
, rtx_insn
*boundary
)
3906 struct parms_set_data parm
;
3908 rtx_insn
*before
, *first_set
;
3910 /* Since different machines initialize their parameter registers
3911 in different orders, assume nothing. Collect the set of all
3912 parameter registers. */
3913 CLEAR_HARD_REG_SET (parm
.regs
);
3915 for (p
= CALL_INSN_FUNCTION_USAGE (call_insn
); p
; p
= XEXP (p
, 1))
3916 if (GET_CODE (XEXP (p
, 0)) == USE
3917 && REG_P (XEXP (XEXP (p
, 0), 0))
3918 && !STATIC_CHAIN_REG_P (XEXP (XEXP (p
, 0), 0)))
3920 gcc_assert (REGNO (XEXP (XEXP (p
, 0), 0)) < FIRST_PSEUDO_REGISTER
);
3922 /* We only care about registers which can hold function
3924 if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p
, 0), 0))))
3927 SET_HARD_REG_BIT (parm
.regs
, REGNO (XEXP (XEXP (p
, 0), 0)));
3931 first_set
= call_insn
;
3933 /* Search backward for the first set of a register in this set. */
3934 while (parm
.nregs
&& before
!= boundary
)
3936 before
= PREV_INSN (before
);
3938 /* It is possible that some loads got CSEed from one call to
3939 another. Stop in that case. */
3940 if (CALL_P (before
))
3943 /* Our caller needs either ensure that we will find all sets
3944 (in case code has not been optimized yet), or take care
3945 for possible labels in a way by setting boundary to preceding
3947 if (LABEL_P (before
))
3949 gcc_assert (before
== boundary
);
3953 if (INSN_P (before
))
3955 int nregs_old
= parm
.nregs
;
3956 note_stores (PATTERN (before
), parms_set
, &parm
);
3957 /* If we found something that did not set a parameter reg,
3958 we're done. Do not keep going, as that might result
3959 in hoisting an insn before the setting of a pseudo
3960 that is used by the hoisted insn. */
3961 if (nregs_old
!= parm
.nregs
)
3970 /* Return true if we should avoid inserting code between INSN and preceding
3971 call instruction. */
3974 keep_with_call_p (const rtx_insn
*insn
)
3978 if (INSN_P (insn
) && (set
= single_set (insn
)) != NULL
)
3980 if (REG_P (SET_DEST (set
))
3981 && REGNO (SET_DEST (set
)) < FIRST_PSEUDO_REGISTER
3982 && fixed_regs
[REGNO (SET_DEST (set
))]
3983 && general_operand (SET_SRC (set
), VOIDmode
))
3985 if (REG_P (SET_SRC (set
))
3986 && targetm
.calls
.function_value_regno_p (REGNO (SET_SRC (set
)))
3987 && REG_P (SET_DEST (set
))
3988 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
3990 /* There may be a stack pop just after the call and before the store
3991 of the return register. Search for the actual store when deciding
3992 if we can break or not. */
3993 if (SET_DEST (set
) == stack_pointer_rtx
)
3995 /* This CONST_CAST is okay because next_nonnote_insn just
3996 returns its argument and we assign it to a const_rtx
3999 = next_nonnote_insn (const_cast<rtx_insn
*> (insn
));
4000 if (i2
&& keep_with_call_p (i2
))
4007 /* Return true if LABEL is a target of JUMP_INSN. This applies only
4008 to non-complex jumps. That is, direct unconditional, conditional,
4009 and tablejumps, but not computed jumps or returns. It also does
4010 not apply to the fallthru case of a conditional jump. */
4013 label_is_jump_target_p (const_rtx label
, const rtx_insn
*jump_insn
)
4015 rtx tmp
= JUMP_LABEL (jump_insn
);
4016 rtx_jump_table_data
*table
;
4021 if (tablejump_p (jump_insn
, NULL
, &table
))
4023 rtvec vec
= table
->get_labels ();
4024 int i
, veclen
= GET_NUM_ELEM (vec
);
4026 for (i
= 0; i
< veclen
; ++i
)
4027 if (XEXP (RTVEC_ELT (vec
, i
), 0) == label
)
4031 if (find_reg_note (jump_insn
, REG_LABEL_TARGET
, label
))
4038 /* Return an estimate of the cost of computing rtx X.
4039 One use is in cse, to decide which expression to keep in the hash table.
4040 Another is in rtl generation, to pick the cheapest way to multiply.
4041 Other uses like the latter are expected in the future.
4043 X appears as operand OPNO in an expression with code OUTER_CODE.
4044 SPEED specifies whether costs optimized for speed or size should
4048 rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer_code
,
4049 int opno
, bool speed
)
4060 if (GET_MODE (x
) != VOIDmode
)
4061 mode
= GET_MODE (x
);
4063 /* A size N times larger than UNITS_PER_WORD likely needs N times as
4064 many insns, taking N times as long. */
4065 factor
= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
4069 /* Compute the default costs of certain things.
4070 Note that targetm.rtx_costs can override the defaults. */
4072 code
= GET_CODE (x
);
4076 /* Multiplication has time-complexity O(N*N), where N is the
4077 number of units (translated from digits) when using
4078 schoolbook long multiplication. */
4079 total
= factor
* factor
* COSTS_N_INSNS (5);
4085 /* Similarly, complexity for schoolbook long division. */
4086 total
= factor
* factor
* COSTS_N_INSNS (7);
4089 /* Used in combine.c as a marker. */
4093 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
4094 the mode for the factor. */
4095 mode
= GET_MODE (SET_DEST (x
));
4096 factor
= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
4101 total
= factor
* COSTS_N_INSNS (1);
4111 /* If we can't tie these modes, make this expensive. The larger
4112 the mode, the more expensive it is. */
4113 if (! MODES_TIEABLE_P (mode
, GET_MODE (SUBREG_REG (x
))))
4114 return COSTS_N_INSNS (2 + factor
);
4118 if (targetm
.rtx_costs (x
, mode
, outer_code
, opno
, &total
, speed
))
4123 /* Sum the costs of the sub-rtx's, plus cost of this operation,
4124 which is already in total. */
4126 fmt
= GET_RTX_FORMAT (code
);
4127 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4129 total
+= rtx_cost (XEXP (x
, i
), mode
, code
, i
, speed
);
4130 else if (fmt
[i
] == 'E')
4131 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
4132 total
+= rtx_cost (XVECEXP (x
, i
, j
), mode
, code
, i
, speed
);
4137 /* Fill in the structure C with information about both speed and size rtx
4138 costs for X, which is operand OPNO in an expression with code OUTER. */
4141 get_full_rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer
, int opno
,
4142 struct full_rtx_costs
*c
)
4144 c
->speed
= rtx_cost (x
, mode
, outer
, opno
, true);
4145 c
->size
= rtx_cost (x
, mode
, outer
, opno
, false);
4149 /* Return cost of address expression X.
4150 Expect that X is properly formed address reference.
4152 SPEED parameter specify whether costs optimized for speed or size should
4156 address_cost (rtx x
, machine_mode mode
, addr_space_t as
, bool speed
)
4158 /* We may be asked for cost of various unusual addresses, such as operands
4159 of push instruction. It is not worthwhile to complicate writing
4160 of the target hook by such cases. */
4162 if (!memory_address_addr_space_p (mode
, x
, as
))
4165 return targetm
.address_cost (x
, mode
, as
, speed
);
4168 /* If the target doesn't override, compute the cost as with arithmetic. */
4171 default_address_cost (rtx x
, machine_mode
, addr_space_t
, bool speed
)
4173 return rtx_cost (x
, Pmode
, MEM
, 0, speed
);
4177 unsigned HOST_WIDE_INT
4178 nonzero_bits (const_rtx x
, machine_mode mode
)
4180 return cached_nonzero_bits (x
, mode
, NULL_RTX
, VOIDmode
, 0);
4184 num_sign_bit_copies (const_rtx x
, machine_mode mode
)
4186 return cached_num_sign_bit_copies (x
, mode
, NULL_RTX
, VOIDmode
, 0);
4189 /* Return true if nonzero_bits1 might recurse into both operands
4193 nonzero_bits_binary_arith_p (const_rtx x
)
4195 if (!ARITHMETIC_P (x
))
4197 switch (GET_CODE (x
))
4219 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
4220 It avoids exponential behavior in nonzero_bits1 when X has
4221 identical subexpressions on the first or the second level. */
4223 static unsigned HOST_WIDE_INT
4224 cached_nonzero_bits (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4225 machine_mode known_mode
,
4226 unsigned HOST_WIDE_INT known_ret
)
4228 if (x
== known_x
&& mode
== known_mode
)
4231 /* Try to find identical subexpressions. If found call
4232 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
4233 precomputed value for the subexpression as KNOWN_RET. */
4235 if (nonzero_bits_binary_arith_p (x
))
4237 rtx x0
= XEXP (x
, 0);
4238 rtx x1
= XEXP (x
, 1);
4240 /* Check the first level. */
4242 return nonzero_bits1 (x
, mode
, x0
, mode
,
4243 cached_nonzero_bits (x0
, mode
, known_x
,
4244 known_mode
, known_ret
));
4246 /* Check the second level. */
4247 if (nonzero_bits_binary_arith_p (x0
)
4248 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4249 return nonzero_bits1 (x
, mode
, x1
, mode
,
4250 cached_nonzero_bits (x1
, mode
, known_x
,
4251 known_mode
, known_ret
));
4253 if (nonzero_bits_binary_arith_p (x1
)
4254 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4255 return nonzero_bits1 (x
, mode
, x0
, mode
,
4256 cached_nonzero_bits (x0
, mode
, known_x
,
4257 known_mode
, known_ret
));
4260 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
4263 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
4264 We don't let nonzero_bits recur into num_sign_bit_copies, because that
4265 is less useful. We can't allow both, because that results in exponential
4266 run time recursion. There is a nullstone testcase that triggered
4267 this. This macro avoids accidental uses of num_sign_bit_copies. */
4268 #define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior
4270 /* Given an expression, X, compute which bits in X can be nonzero.
4271 We don't care about bits outside of those defined in MODE.
4273 For most X this is simply GET_MODE_MASK (GET_MODE (X)), but if X is
4274 an arithmetic operation, we can do better. */
4276 static unsigned HOST_WIDE_INT
4277 nonzero_bits1 (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4278 machine_mode known_mode
,
4279 unsigned HOST_WIDE_INT known_ret
)
4281 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
4282 unsigned HOST_WIDE_INT inner_nz
;
4284 machine_mode inner_mode
;
4285 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
4287 /* For floating-point and vector values, assume all bits are needed. */
4288 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
)
4289 || VECTOR_MODE_P (GET_MODE (x
)) || VECTOR_MODE_P (mode
))
4292 /* If X is wider than MODE, use its mode instead. */
4293 if (GET_MODE_PRECISION (GET_MODE (x
)) > mode_width
)
4295 mode
= GET_MODE (x
);
4296 nonzero
= GET_MODE_MASK (mode
);
4297 mode_width
= GET_MODE_PRECISION (mode
);
4300 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
4301 /* Our only callers in this case look for single bit values. So
4302 just return the mode mask. Those tests will then be false. */
4305 /* If MODE is wider than X, but both are a single word for both the host
4306 and target machines, we can compute this from which bits of the
4307 object might be nonzero in its own mode, taking into account the fact
4308 that on many CISC machines, accessing an object in a wider mode
4309 causes the high-order bits to become undefined. So they are
4310 not known to be zero. */
4312 if (!WORD_REGISTER_OPERATIONS
4313 && GET_MODE (x
) != VOIDmode
4314 && GET_MODE (x
) != mode
4315 && GET_MODE_PRECISION (GET_MODE (x
)) <= BITS_PER_WORD
4316 && GET_MODE_PRECISION (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
4317 && GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (GET_MODE (x
)))
4319 nonzero
&= cached_nonzero_bits (x
, GET_MODE (x
),
4320 known_x
, known_mode
, known_ret
);
4321 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
4325 /* Please keep nonzero_bits_binary_arith_p above in sync with
4326 the code in the switch below. */
4327 code
= GET_CODE (x
);
4331 #if defined(POINTERS_EXTEND_UNSIGNED)
4332 /* If pointers extend unsigned and this is a pointer in Pmode, say that
4333 all the bits above ptr_mode are known to be zero. */
4334 /* As we do not know which address space the pointer is referring to,
4335 we can do this only if the target does not support different pointer
4336 or address modes depending on the address space. */
4337 if (target_default_pointer_address_modes_p ()
4338 && POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
4340 && !targetm
.have_ptr_extend ())
4341 nonzero
&= GET_MODE_MASK (ptr_mode
);
4344 /* Include declared information about alignment of pointers. */
4345 /* ??? We don't properly preserve REG_POINTER changes across
4346 pointer-to-integer casts, so we can't trust it except for
4347 things that we know must be pointers. See execute/960116-1.c. */
4348 if ((x
== stack_pointer_rtx
4349 || x
== frame_pointer_rtx
4350 || x
== arg_pointer_rtx
)
4351 && REGNO_POINTER_ALIGN (REGNO (x
)))
4353 unsigned HOST_WIDE_INT alignment
4354 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
4356 #ifdef PUSH_ROUNDING
4357 /* If PUSH_ROUNDING is defined, it is possible for the
4358 stack to be momentarily aligned only to that amount,
4359 so we pick the least alignment. */
4360 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
4361 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
4365 nonzero
&= ~(alignment
- 1);
4369 unsigned HOST_WIDE_INT nonzero_for_hook
= nonzero
;
4370 rtx new_rtx
= rtl_hooks
.reg_nonzero_bits (x
, mode
, known_x
,
4371 known_mode
, known_ret
,
4375 nonzero_for_hook
&= cached_nonzero_bits (new_rtx
, mode
, known_x
,
4376 known_mode
, known_ret
);
4378 return nonzero_for_hook
;
4382 /* If X is negative in MODE, sign-extend the value. */
4383 if (SHORT_IMMEDIATES_SIGN_EXTEND
&& INTVAL (x
) > 0
4384 && mode_width
< BITS_PER_WORD
4385 && (UINTVAL (x
) & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
4387 return UINTVAL (x
) | (HOST_WIDE_INT_M1U
<< mode_width
);
4392 /* In many, if not most, RISC machines, reading a byte from memory
4393 zeros the rest of the register. Noticing that fact saves a lot
4394 of extra zero-extends. */
4395 if (load_extend_op (GET_MODE (x
)) == ZERO_EXTEND
)
4396 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
4400 case UNEQ
: case LTGT
:
4401 case GT
: case GTU
: case UNGT
:
4402 case LT
: case LTU
: case UNLT
:
4403 case GE
: case GEU
: case UNGE
:
4404 case LE
: case LEU
: case UNLE
:
4405 case UNORDERED
: case ORDERED
:
4406 /* If this produces an integer result, we know which bits are set.
4407 Code here used to clear bits outside the mode of X, but that is
4409 /* Mind that MODE is the mode the caller wants to look at this
4410 operation in, and not the actual operation mode. We can wind
4411 up with (subreg:DI (gt:V4HI x y)), and we don't have anything
4412 that describes the results of a vector compare. */
4413 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
4414 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
4415 nonzero
= STORE_FLAG_VALUE
;
4420 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4421 and num_sign_bit_copies. */
4422 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
4423 == GET_MODE_PRECISION (GET_MODE (x
)))
4427 if (GET_MODE_PRECISION (GET_MODE (x
)) < mode_width
)
4428 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
4433 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4434 and num_sign_bit_copies. */
4435 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
4436 == GET_MODE_PRECISION (GET_MODE (x
)))
4442 nonzero
&= (cached_nonzero_bits (XEXP (x
, 0), mode
,
4443 known_x
, known_mode
, known_ret
)
4444 & GET_MODE_MASK (mode
));
4448 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4449 known_x
, known_mode
, known_ret
);
4450 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4451 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4455 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
4456 Otherwise, show all the bits in the outer mode but not the inner
4458 inner_nz
= cached_nonzero_bits (XEXP (x
, 0), mode
,
4459 known_x
, known_mode
, known_ret
);
4460 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4462 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4463 if (val_signbit_known_set_p (GET_MODE (XEXP (x
, 0)), inner_nz
))
4464 inner_nz
|= (GET_MODE_MASK (mode
)
4465 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
4468 nonzero
&= inner_nz
;
4472 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4473 known_x
, known_mode
, known_ret
)
4474 & cached_nonzero_bits (XEXP (x
, 1), mode
,
4475 known_x
, known_mode
, known_ret
);
4479 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
4481 unsigned HOST_WIDE_INT nonzero0
4482 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4483 known_x
, known_mode
, known_ret
);
4485 /* Don't call nonzero_bits for the second time if it cannot change
4487 if ((nonzero
& nonzero0
) != nonzero
)
4489 | cached_nonzero_bits (XEXP (x
, 1), mode
,
4490 known_x
, known_mode
, known_ret
);
4494 case PLUS
: case MINUS
:
4496 case DIV
: case UDIV
:
4497 case MOD
: case UMOD
:
4498 /* We can apply the rules of arithmetic to compute the number of
4499 high- and low-order zero bits of these operations. We start by
4500 computing the width (position of the highest-order nonzero bit)
4501 and the number of low-order zero bits for each value. */
4503 unsigned HOST_WIDE_INT nz0
4504 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4505 known_x
, known_mode
, known_ret
);
4506 unsigned HOST_WIDE_INT nz1
4507 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4508 known_x
, known_mode
, known_ret
);
4509 int sign_index
= GET_MODE_PRECISION (GET_MODE (x
)) - 1;
4510 int width0
= floor_log2 (nz0
) + 1;
4511 int width1
= floor_log2 (nz1
) + 1;
4512 int low0
= ctz_or_zero (nz0
);
4513 int low1
= ctz_or_zero (nz1
);
4514 unsigned HOST_WIDE_INT op0_maybe_minusp
4515 = nz0
& (HOST_WIDE_INT_1U
<< sign_index
);
4516 unsigned HOST_WIDE_INT op1_maybe_minusp
4517 = nz1
& (HOST_WIDE_INT_1U
<< sign_index
);
4518 unsigned int result_width
= mode_width
;
4524 result_width
= MAX (width0
, width1
) + 1;
4525 result_low
= MIN (low0
, low1
);
4528 result_low
= MIN (low0
, low1
);
4531 result_width
= width0
+ width1
;
4532 result_low
= low0
+ low1
;
4537 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4538 result_width
= width0
;
4543 result_width
= width0
;
4548 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4549 result_width
= MIN (width0
, width1
);
4550 result_low
= MIN (low0
, low1
);
4555 result_width
= MIN (width0
, width1
);
4556 result_low
= MIN (low0
, low1
);
4562 if (result_width
< mode_width
)
4563 nonzero
&= (HOST_WIDE_INT_1U
<< result_width
) - 1;
4566 nonzero
&= ~((HOST_WIDE_INT_1U
<< result_low
) - 1);
4571 if (CONST_INT_P (XEXP (x
, 1))
4572 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
4573 nonzero
&= (HOST_WIDE_INT_1U
<< INTVAL (XEXP (x
, 1))) - 1;
4577 /* If this is a SUBREG formed for a promoted variable that has
4578 been zero-extended, we know that at least the high-order bits
4579 are zero, though others might be too. */
4580 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
4581 nonzero
= GET_MODE_MASK (GET_MODE (x
))
4582 & cached_nonzero_bits (SUBREG_REG (x
), GET_MODE (x
),
4583 known_x
, known_mode
, known_ret
);
4585 /* If the inner mode is a single word for both the host and target
4586 machines, we can compute this from which bits of the inner
4587 object might be nonzero. */
4588 inner_mode
= GET_MODE (SUBREG_REG (x
));
4589 if (GET_MODE_PRECISION (inner_mode
) <= BITS_PER_WORD
4590 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
)
4592 nonzero
&= cached_nonzero_bits (SUBREG_REG (x
), mode
,
4593 known_x
, known_mode
, known_ret
);
4595 /* On many CISC machines, accessing an object in a wider mode
4596 causes the high-order bits to become undefined. So they are
4597 not known to be zero. */
4599 if ((!WORD_REGISTER_OPERATIONS
4600 /* If this is a typical RISC machine, we only have to worry
4601 about the way loads are extended. */
4602 || ((extend_op
= load_extend_op (inner_mode
)) == SIGN_EXTEND
4603 ? val_signbit_known_set_p (inner_mode
, nonzero
)
4604 : extend_op
!= ZERO_EXTEND
)
4605 || (!MEM_P (SUBREG_REG (x
)) && !REG_P (SUBREG_REG (x
))))
4606 && GET_MODE_PRECISION (GET_MODE (x
))
4607 > GET_MODE_PRECISION (inner_mode
))
4609 |= (GET_MODE_MASK (GET_MODE (x
)) & ~GET_MODE_MASK (inner_mode
));
4617 /* The nonzero bits are in two classes: any bits within MODE
4618 that aren't in GET_MODE (x) are always significant. The rest of the
4619 nonzero bits are those that are significant in the operand of
4620 the shift when shifted the appropriate number of bits. This
4621 shows that high-order bits are cleared by the right shift and
4622 low-order bits by left shifts. */
4623 if (CONST_INT_P (XEXP (x
, 1))
4624 && INTVAL (XEXP (x
, 1)) >= 0
4625 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
4626 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (GET_MODE (x
)))
4628 machine_mode inner_mode
= GET_MODE (x
);
4629 unsigned int width
= GET_MODE_PRECISION (inner_mode
);
4630 int count
= INTVAL (XEXP (x
, 1));
4631 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
4632 unsigned HOST_WIDE_INT op_nonzero
4633 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4634 known_x
, known_mode
, known_ret
);
4635 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
4636 unsigned HOST_WIDE_INT outer
= 0;
4638 if (mode_width
> width
)
4639 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
4641 if (code
== LSHIFTRT
)
4643 else if (code
== ASHIFTRT
)
4647 /* If the sign bit may have been nonzero before the shift, we
4648 need to mark all the places it could have been copied to
4649 by the shift as possibly nonzero. */
4650 if (inner
& (HOST_WIDE_INT_1U
<< (width
- 1 - count
)))
4651 inner
|= ((HOST_WIDE_INT_1U
<< count
) - 1)
4654 else if (code
== ASHIFT
)
4657 inner
= ((inner
<< (count
% width
)
4658 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
4660 nonzero
&= (outer
| inner
);
4666 /* This is at most the number of bits in the mode. */
4667 nonzero
= ((unsigned HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
4671 /* If CLZ has a known value at zero, then the nonzero bits are
4672 that value, plus the number of bits in the mode minus one. */
4673 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4675 |= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4681 /* If CTZ has a known value at zero, then the nonzero bits are
4682 that value, plus the number of bits in the mode minus one. */
4683 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4685 |= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4691 /* This is at most the number of bits in the mode minus 1. */
4692 nonzero
= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4701 unsigned HOST_WIDE_INT nonzero_true
4702 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4703 known_x
, known_mode
, known_ret
);
4705 /* Don't call nonzero_bits for the second time if it cannot change
4707 if ((nonzero
& nonzero_true
) != nonzero
)
4708 nonzero
&= nonzero_true
4709 | cached_nonzero_bits (XEXP (x
, 2), mode
,
4710 known_x
, known_mode
, known_ret
);
4721 /* See the macro definition above. */
4722 #undef cached_num_sign_bit_copies
4725 /* Return true if num_sign_bit_copies1 might recurse into both operands
4729 num_sign_bit_copies_binary_arith_p (const_rtx x
)
4731 if (!ARITHMETIC_P (x
))
4733 switch (GET_CODE (x
))
4751 /* The function cached_num_sign_bit_copies is a wrapper around
4752 num_sign_bit_copies1. It avoids exponential behavior in
4753 num_sign_bit_copies1 when X has identical subexpressions on the
4754 first or the second level. */
4757 cached_num_sign_bit_copies (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4758 machine_mode known_mode
,
4759 unsigned int known_ret
)
4761 if (x
== known_x
&& mode
== known_mode
)
4764 /* Try to find identical subexpressions. If found call
4765 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
4766 the precomputed value for the subexpression as KNOWN_RET. */
4768 if (num_sign_bit_copies_binary_arith_p (x
))
4770 rtx x0
= XEXP (x
, 0);
4771 rtx x1
= XEXP (x
, 1);
4773 /* Check the first level. */
4776 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4777 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4781 /* Check the second level. */
4782 if (num_sign_bit_copies_binary_arith_p (x0
)
4783 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4785 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
4786 cached_num_sign_bit_copies (x1
, mode
, known_x
,
4790 if (num_sign_bit_copies_binary_arith_p (x1
)
4791 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4793 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4794 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4799 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
4802 /* Return the number of bits at the high-order end of X that are known to
4803 be equal to the sign bit. X will be used in mode MODE; if MODE is
4804 VOIDmode, X will be used in its own mode. The returned value will always
4805 be between 1 and the number of bits in MODE. */
4808 num_sign_bit_copies1 (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4809 machine_mode known_mode
,
4810 unsigned int known_ret
)
4812 enum rtx_code code
= GET_CODE (x
);
4813 machine_mode inner_mode
;
4814 int num0
, num1
, result
;
4815 unsigned HOST_WIDE_INT nonzero
;
4817 /* If we weren't given a mode, use the mode of X. If the mode is still
4818 VOIDmode, we don't know anything. Likewise if one of the modes is
4821 if (mode
== VOIDmode
)
4822 mode
= GET_MODE (x
);
4824 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
))
4825 || VECTOR_MODE_P (GET_MODE (x
)) || VECTOR_MODE_P (mode
))
4828 /* For a smaller mode, just ignore the high bits. */
4829 unsigned int bitwidth
= GET_MODE_PRECISION (mode
);
4830 if (bitwidth
< GET_MODE_PRECISION (GET_MODE (x
)))
4832 num0
= cached_num_sign_bit_copies (x
, GET_MODE (x
),
4833 known_x
, known_mode
, known_ret
);
4835 num0
- (int) (GET_MODE_PRECISION (GET_MODE (x
)) - bitwidth
));
4838 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_PRECISION (GET_MODE (x
)))
4840 /* If this machine does not do all register operations on the entire
4841 register and MODE is wider than the mode of X, we can say nothing
4842 at all about the high-order bits. */
4843 if (!WORD_REGISTER_OPERATIONS
)
4846 /* Likewise on machines that do, if the mode of the object is smaller
4847 than a word and loads of that size don't sign extend, we can say
4848 nothing about the high order bits. */
4849 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
4850 && load_extend_op (GET_MODE (x
)) != SIGN_EXTEND
)
4854 /* Please keep num_sign_bit_copies_binary_arith_p above in sync with
4855 the code in the switch below. */
4860 #if defined(POINTERS_EXTEND_UNSIGNED)
4861 /* If pointers extend signed and this is a pointer in Pmode, say that
4862 all the bits above ptr_mode are known to be sign bit copies. */
4863 /* As we do not know which address space the pointer is referring to,
4864 we can do this only if the target does not support different pointer
4865 or address modes depending on the address space. */
4866 if (target_default_pointer_address_modes_p ()
4867 && ! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
4868 && mode
== Pmode
&& REG_POINTER (x
)
4869 && !targetm
.have_ptr_extend ())
4870 return GET_MODE_PRECISION (Pmode
) - GET_MODE_PRECISION (ptr_mode
) + 1;
4874 unsigned int copies_for_hook
= 1, copies
= 1;
4875 rtx new_rtx
= rtl_hooks
.reg_num_sign_bit_copies (x
, mode
, known_x
,
4876 known_mode
, known_ret
,
4880 copies
= cached_num_sign_bit_copies (new_rtx
, mode
, known_x
,
4881 known_mode
, known_ret
);
4883 if (copies
> 1 || copies_for_hook
> 1)
4884 return MAX (copies
, copies_for_hook
);
4886 /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */
4891 /* Some RISC machines sign-extend all loads of smaller than a word. */
4892 if (load_extend_op (GET_MODE (x
)) == SIGN_EXTEND
)
4893 return MAX (1, ((int) bitwidth
4894 - (int) GET_MODE_PRECISION (GET_MODE (x
)) + 1));
4898 /* If the constant is negative, take its 1's complement and remask.
4899 Then see how many zero bits we have. */
4900 nonzero
= UINTVAL (x
) & GET_MODE_MASK (mode
);
4901 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
4902 && (nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
4903 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
4905 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
4908 /* If this is a SUBREG for a promoted object that is sign-extended
4909 and we are looking at it in a wider mode, we know that at least the
4910 high-order bits are known to be sign bit copies. */
4912 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_SIGNED_P (x
))
4914 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
4915 known_x
, known_mode
, known_ret
);
4916 return MAX ((int) bitwidth
4917 - (int) GET_MODE_PRECISION (GET_MODE (x
)) + 1,
4921 /* For a smaller object, just ignore the high bits. */
4922 inner_mode
= GET_MODE (SUBREG_REG (x
));
4923 if (bitwidth
<= GET_MODE_PRECISION (inner_mode
))
4925 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
,
4926 known_x
, known_mode
, known_ret
);
4928 MAX (1, num0
- (int) (GET_MODE_PRECISION (inner_mode
) - bitwidth
));
4931 /* For paradoxical SUBREGs on machines where all register operations
4932 affect the entire register, just look inside. Note that we are
4933 passing MODE to the recursive call, so the number of sign bit copies
4934 will remain relative to that mode, not the inner mode. */
4936 /* This works only if loads sign extend. Otherwise, if we get a
4937 reload for the inner part, it may be loaded from the stack, and
4938 then we lose all sign bit copies that existed before the store
4941 if (WORD_REGISTER_OPERATIONS
4942 && load_extend_op (inner_mode
) == SIGN_EXTEND
4943 && paradoxical_subreg_p (x
)
4944 && (MEM_P (SUBREG_REG (x
)) || REG_P (SUBREG_REG (x
))))
4945 return cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
4946 known_x
, known_mode
, known_ret
);
4950 if (CONST_INT_P (XEXP (x
, 1)))
4951 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
4955 return (bitwidth
- GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
4956 + cached_num_sign_bit_copies (XEXP (x
, 0), VOIDmode
,
4957 known_x
, known_mode
, known_ret
));
4960 /* For a smaller object, just ignore the high bits. */
4961 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), VOIDmode
,
4962 known_x
, known_mode
, known_ret
);
4963 return MAX (1, (num0
- (int) (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
4967 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4968 known_x
, known_mode
, known_ret
);
4970 case ROTATE
: case ROTATERT
:
4971 /* If we are rotating left by a number of bits less than the number
4972 of sign bit copies, we can just subtract that amount from the
4974 if (CONST_INT_P (XEXP (x
, 1))
4975 && INTVAL (XEXP (x
, 1)) >= 0
4976 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
4978 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4979 known_x
, known_mode
, known_ret
);
4980 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
4981 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
4986 /* In general, this subtracts one sign bit copy. But if the value
4987 is known to be positive, the number of sign bit copies is the
4988 same as that of the input. Finally, if the input has just one bit
4989 that might be nonzero, all the bits are copies of the sign bit. */
4990 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4991 known_x
, known_mode
, known_ret
);
4992 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
4993 return num0
> 1 ? num0
- 1 : 1;
4995 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5000 && ((HOST_WIDE_INT_1U
<< (bitwidth
- 1)) & nonzero
))
5005 case IOR
: case AND
: case XOR
:
5006 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
5007 /* Logical operations will preserve the number of sign-bit copies.
5008 MIN and MAX operations always return one of the operands. */
5009 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5010 known_x
, known_mode
, known_ret
);
5011 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5012 known_x
, known_mode
, known_ret
);
5014 /* If num1 is clearing some of the top bits then regardless of
5015 the other term, we are guaranteed to have at least that many
5016 high-order zero bits. */
5019 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5020 && CONST_INT_P (XEXP (x
, 1))
5021 && (UINTVAL (XEXP (x
, 1))
5022 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) == 0)
5025 /* Similarly for IOR when setting high-order bits. */
5028 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5029 && CONST_INT_P (XEXP (x
, 1))
5030 && (UINTVAL (XEXP (x
, 1))
5031 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5034 return MIN (num0
, num1
);
5036 case PLUS
: case MINUS
:
5037 /* For addition and subtraction, we can have a 1-bit carry. However,
5038 if we are subtracting 1 from a positive number, there will not
5039 be such a carry. Furthermore, if the positive number is known to
5040 be 0 or 1, we know the result is either -1 or 0. */
5042 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
5043 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
5045 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5046 if (((HOST_WIDE_INT_1U
<< (bitwidth
- 1)) & nonzero
) == 0)
5047 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
5048 : bitwidth
- floor_log2 (nonzero
) - 1);
5051 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5052 known_x
, known_mode
, known_ret
);
5053 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5054 known_x
, known_mode
, known_ret
);
5055 result
= MAX (1, MIN (num0
, num1
) - 1);
5060 /* The number of bits of the product is the sum of the number of
5061 bits of both terms. However, unless one of the terms if known
5062 to be positive, we must allow for an additional bit since negating
5063 a negative number can remove one sign bit copy. */
5065 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5066 known_x
, known_mode
, known_ret
);
5067 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5068 known_x
, known_mode
, known_ret
);
5070 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
5072 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5073 || (((nonzero_bits (XEXP (x
, 0), mode
)
5074 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5075 && ((nonzero_bits (XEXP (x
, 1), mode
)
5076 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1)))
5080 return MAX (1, result
);
5083 /* The result must be <= the first operand. If the first operand
5084 has the high bit set, we know nothing about the number of sign
5086 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5088 else if ((nonzero_bits (XEXP (x
, 0), mode
)
5089 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5092 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5093 known_x
, known_mode
, known_ret
);
5096 /* The result must be <= the second operand. If the second operand
5097 has (or just might have) the high bit set, we know nothing about
5098 the number of sign bit copies. */
5099 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5101 else if ((nonzero_bits (XEXP (x
, 1), mode
)
5102 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5105 return cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5106 known_x
, known_mode
, known_ret
);
5109 /* Similar to unsigned division, except that we have to worry about
5110 the case where the divisor is negative, in which case we have
5112 result
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5113 known_x
, known_mode
, known_ret
);
5115 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5116 || (nonzero_bits (XEXP (x
, 1), mode
)
5117 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0))
5123 result
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5124 known_x
, known_mode
, known_ret
);
5126 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5127 || (nonzero_bits (XEXP (x
, 1), mode
)
5128 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0))
5134 /* Shifts by a constant add to the number of bits equal to the
5136 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5137 known_x
, known_mode
, known_ret
);
5138 if (CONST_INT_P (XEXP (x
, 1))
5139 && INTVAL (XEXP (x
, 1)) > 0
5140 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (GET_MODE (x
)))
5141 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
5146 /* Left shifts destroy copies. */
5147 if (!CONST_INT_P (XEXP (x
, 1))
5148 || INTVAL (XEXP (x
, 1)) < 0
5149 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
5150 || INTVAL (XEXP (x
, 1)) >= GET_MODE_PRECISION (GET_MODE (x
)))
5153 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5154 known_x
, known_mode
, known_ret
);
5155 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
5158 num0
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5159 known_x
, known_mode
, known_ret
);
5160 num1
= cached_num_sign_bit_copies (XEXP (x
, 2), mode
,
5161 known_x
, known_mode
, known_ret
);
5162 return MIN (num0
, num1
);
5164 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
5165 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
5166 case GEU
: case GTU
: case LEU
: case LTU
:
5167 case UNORDERED
: case ORDERED
:
5168 /* If the constant is negative, take its 1's complement and remask.
5169 Then see how many zero bits we have. */
5170 nonzero
= STORE_FLAG_VALUE
;
5171 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
5172 && (nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5173 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
5175 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
5181 /* If we haven't been able to figure it out by one of the above rules,
5182 see if some of the high-order bits are known to be zero. If so,
5183 count those bits and return one less than that amount. If we can't
5184 safely compute the mask for this mode, always return BITWIDTH. */
5186 bitwidth
= GET_MODE_PRECISION (mode
);
5187 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5190 nonzero
= nonzero_bits (x
, mode
);
5191 return nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))
5192 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1;
5195 /* Calculate the rtx_cost of a single instruction. A return value of
5196 zero indicates an instruction pattern without a known cost. */
5199 insn_rtx_cost (rtx pat
, bool speed
)
5204 /* Extract the single set rtx from the instruction pattern.
5205 We can't use single_set since we only have the pattern. */
5206 if (GET_CODE (pat
) == SET
)
5208 else if (GET_CODE (pat
) == PARALLEL
)
5211 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
5213 rtx x
= XVECEXP (pat
, 0, i
);
5214 if (GET_CODE (x
) == SET
)
5227 cost
= set_src_cost (SET_SRC (set
), GET_MODE (SET_DEST (set
)), speed
);
5228 return cost
> 0 ? cost
: COSTS_N_INSNS (1);
5231 /* Returns estimate on cost of computing SEQ. */
5234 seq_cost (const rtx_insn
*seq
, bool speed
)
5239 for (; seq
; seq
= NEXT_INSN (seq
))
5241 set
= single_set (seq
);
5243 cost
+= set_rtx_cost (set
, speed
);
5251 /* Given an insn INSN and condition COND, return the condition in a
5252 canonical form to simplify testing by callers. Specifically:
5254 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
5255 (2) Both operands will be machine operands; (cc0) will have been replaced.
5256 (3) If an operand is a constant, it will be the second operand.
5257 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
5258 for GE, GEU, and LEU.
5260 If the condition cannot be understood, or is an inequality floating-point
5261 comparison which needs to be reversed, 0 will be returned.
5263 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
5265 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5266 insn used in locating the condition was found. If a replacement test
5267 of the condition is desired, it should be placed in front of that
5268 insn and we will be sure that the inputs are still valid.
5270 If WANT_REG is nonzero, we wish the condition to be relative to that
5271 register, if possible. Therefore, do not canonicalize the condition
5272 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
5273 to be a compare to a CC mode register.
5275 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
5279 canonicalize_condition (rtx_insn
*insn
, rtx cond
, int reverse
,
5280 rtx_insn
**earliest
,
5281 rtx want_reg
, int allow_cc_mode
, int valid_at_insn_p
)
5284 rtx_insn
*prev
= insn
;
5288 int reverse_code
= 0;
5290 basic_block bb
= BLOCK_FOR_INSN (insn
);
5292 code
= GET_CODE (cond
);
5293 mode
= GET_MODE (cond
);
5294 op0
= XEXP (cond
, 0);
5295 op1
= XEXP (cond
, 1);
5298 code
= reversed_comparison_code (cond
, insn
);
5299 if (code
== UNKNOWN
)
5305 /* If we are comparing a register with zero, see if the register is set
5306 in the previous insn to a COMPARE or a comparison operation. Perform
5307 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
5310 while ((GET_RTX_CLASS (code
) == RTX_COMPARE
5311 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
5312 && op1
== CONST0_RTX (GET_MODE (op0
))
5315 /* Set nonzero when we find something of interest. */
5318 /* If comparison with cc0, import actual comparison from compare
5322 if ((prev
= prev_nonnote_insn (prev
)) == 0
5323 || !NONJUMP_INSN_P (prev
)
5324 || (set
= single_set (prev
)) == 0
5325 || SET_DEST (set
) != cc0_rtx
)
5328 op0
= SET_SRC (set
);
5329 op1
= CONST0_RTX (GET_MODE (op0
));
5334 /* If this is a COMPARE, pick up the two things being compared. */
5335 if (GET_CODE (op0
) == COMPARE
)
5337 op1
= XEXP (op0
, 1);
5338 op0
= XEXP (op0
, 0);
5341 else if (!REG_P (op0
))
5344 /* Go back to the previous insn. Stop if it is not an INSN. We also
5345 stop if it isn't a single set or if it has a REG_INC note because
5346 we don't want to bother dealing with it. */
5348 prev
= prev_nonnote_nondebug_insn (prev
);
5351 || !NONJUMP_INSN_P (prev
)
5352 || FIND_REG_INC_NOTE (prev
, NULL_RTX
)
5353 /* In cfglayout mode, there do not have to be labels at the
5354 beginning of a block, or jumps at the end, so the previous
5355 conditions would not stop us when we reach bb boundary. */
5356 || BLOCK_FOR_INSN (prev
) != bb
)
5359 set
= set_of (op0
, prev
);
5362 && (GET_CODE (set
) != SET
5363 || !rtx_equal_p (SET_DEST (set
), op0
)))
5366 /* If this is setting OP0, get what it sets it to if it looks
5370 machine_mode inner_mode
= GET_MODE (SET_DEST (set
));
5371 #ifdef FLOAT_STORE_FLAG_VALUE
5372 REAL_VALUE_TYPE fsfv
;
5375 /* ??? We may not combine comparisons done in a CCmode with
5376 comparisons not done in a CCmode. This is to aid targets
5377 like Alpha that have an IEEE compliant EQ instruction, and
5378 a non-IEEE compliant BEQ instruction. The use of CCmode is
5379 actually artificial, simply to prevent the combination, but
5380 should not affect other platforms.
5382 However, we must allow VOIDmode comparisons to match either
5383 CCmode or non-CCmode comparison, because some ports have
5384 modeless comparisons inside branch patterns.
5386 ??? This mode check should perhaps look more like the mode check
5387 in simplify_comparison in combine. */
5388 if (((GET_MODE_CLASS (mode
) == MODE_CC
)
5389 != (GET_MODE_CLASS (inner_mode
) == MODE_CC
))
5391 && inner_mode
!= VOIDmode
)
5393 if (GET_CODE (SET_SRC (set
)) == COMPARE
5396 && val_signbit_known_set_p (inner_mode
,
5398 #ifdef FLOAT_STORE_FLAG_VALUE
5400 && SCALAR_FLOAT_MODE_P (inner_mode
)
5401 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5402 REAL_VALUE_NEGATIVE (fsfv
)))
5405 && COMPARISON_P (SET_SRC (set
))))
5407 else if (((code
== EQ
5409 && val_signbit_known_set_p (inner_mode
,
5411 #ifdef FLOAT_STORE_FLAG_VALUE
5413 && SCALAR_FLOAT_MODE_P (inner_mode
)
5414 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5415 REAL_VALUE_NEGATIVE (fsfv
)))
5418 && COMPARISON_P (SET_SRC (set
)))
5423 else if ((code
== EQ
|| code
== NE
)
5424 && GET_CODE (SET_SRC (set
)) == XOR
)
5425 /* Handle sequences like:
5428 ...(eq|ne op0 (const_int 0))...
5432 (eq op0 (const_int 0)) reduces to (eq X Y)
5433 (ne op0 (const_int 0)) reduces to (ne X Y)
5435 This is the form used by MIPS16, for example. */
5441 else if (reg_set_p (op0
, prev
))
5442 /* If this sets OP0, but not directly, we have to give up. */
5447 /* If the caller is expecting the condition to be valid at INSN,
5448 make sure X doesn't change before INSN. */
5449 if (valid_at_insn_p
)
5450 if (modified_in_p (x
, prev
) || modified_between_p (x
, prev
, insn
))
5452 if (COMPARISON_P (x
))
5453 code
= GET_CODE (x
);
5456 code
= reversed_comparison_code (x
, prev
);
5457 if (code
== UNKNOWN
)
5462 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5468 /* If constant is first, put it last. */
5469 if (CONSTANT_P (op0
))
5470 code
= swap_condition (code
), tem
= op0
, op0
= op1
, op1
= tem
;
5472 /* If OP0 is the result of a comparison, we weren't able to find what
5473 was really being compared, so fail. */
5475 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5478 /* Canonicalize any ordered comparison with integers involving equality
5479 if we can do computations in the relevant mode and we do not
5482 if (GET_MODE_CLASS (GET_MODE (op0
)) != MODE_CC
5483 && CONST_INT_P (op1
)
5484 && GET_MODE (op0
) != VOIDmode
5485 && GET_MODE_PRECISION (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
)
5487 HOST_WIDE_INT const_val
= INTVAL (op1
);
5488 unsigned HOST_WIDE_INT uconst_val
= const_val
;
5489 unsigned HOST_WIDE_INT max_val
5490 = (unsigned HOST_WIDE_INT
) GET_MODE_MASK (GET_MODE (op0
));
5495 if ((unsigned HOST_WIDE_INT
) const_val
!= max_val
>> 1)
5496 code
= LT
, op1
= gen_int_mode (const_val
+ 1, GET_MODE (op0
));
5499 /* When cross-compiling, const_val might be sign-extended from
5500 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
5502 if ((const_val
& max_val
)
5503 != (HOST_WIDE_INT_1U
5504 << (GET_MODE_PRECISION (GET_MODE (op0
)) - 1)))
5505 code
= GT
, op1
= gen_int_mode (const_val
- 1, GET_MODE (op0
));
5509 if (uconst_val
< max_val
)
5510 code
= LTU
, op1
= gen_int_mode (uconst_val
+ 1, GET_MODE (op0
));
5514 if (uconst_val
!= 0)
5515 code
= GTU
, op1
= gen_int_mode (uconst_val
- 1, GET_MODE (op0
));
5523 /* Never return CC0; return zero instead. */
5527 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5530 /* Given a jump insn JUMP, return the condition that will cause it to branch
5531 to its JUMP_LABEL. If the condition cannot be understood, or is an
5532 inequality floating-point comparison which needs to be reversed, 0 will
5535 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5536 insn used in locating the condition was found. If a replacement test
5537 of the condition is desired, it should be placed in front of that
5538 insn and we will be sure that the inputs are still valid. If EARLIEST
5539 is null, the returned condition will be valid at INSN.
5541 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
5542 compare CC mode register.
5544 VALID_AT_INSN_P is the same as for canonicalize_condition. */
5547 get_condition (rtx_insn
*jump
, rtx_insn
**earliest
, int allow_cc_mode
,
5548 int valid_at_insn_p
)
5554 /* If this is not a standard conditional jump, we can't parse it. */
5556 || ! any_condjump_p (jump
))
5558 set
= pc_set (jump
);
5560 cond
= XEXP (SET_SRC (set
), 0);
5562 /* If this branches to JUMP_LABEL when the condition is false, reverse
5565 = GET_CODE (XEXP (SET_SRC (set
), 2)) == LABEL_REF
5566 && label_ref_label (XEXP (SET_SRC (set
), 2)) == JUMP_LABEL (jump
);
5568 return canonicalize_condition (jump
, cond
, reverse
, earliest
, NULL_RTX
,
5569 allow_cc_mode
, valid_at_insn_p
);
5572 /* Initialize the table NUM_SIGN_BIT_COPIES_IN_REP based on
5573 TARGET_MODE_REP_EXTENDED.
5575 Note that we assume that the property of
5576 TARGET_MODE_REP_EXTENDED(B, C) is sticky to the integral modes
5577 narrower than mode B. I.e., if A is a mode narrower than B then in
5578 order to be able to operate on it in mode B, mode A needs to
5579 satisfy the requirements set by the representation of mode B. */
5582 init_num_sign_bit_copies_in_rep (void)
5584 machine_mode mode
, in_mode
;
5586 for (in_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); in_mode
!= VOIDmode
;
5587 in_mode
= GET_MODE_WIDER_MODE (mode
))
5588 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= in_mode
;
5589 mode
= GET_MODE_WIDER_MODE (mode
))
5593 /* Currently, it is assumed that TARGET_MODE_REP_EXTENDED
5594 extends to the next widest mode. */
5595 gcc_assert (targetm
.mode_rep_extended (mode
, in_mode
) == UNKNOWN
5596 || GET_MODE_WIDER_MODE (mode
) == in_mode
);
5598 /* We are in in_mode. Count how many bits outside of mode
5599 have to be copies of the sign-bit. */
5600 for (i
= mode
; i
!= in_mode
; i
= GET_MODE_WIDER_MODE (i
))
5602 machine_mode wider
= GET_MODE_WIDER_MODE (i
);
5604 if (targetm
.mode_rep_extended (i
, wider
) == SIGN_EXTEND
5605 /* We can only check sign-bit copies starting from the
5606 top-bit. In order to be able to check the bits we
5607 have already seen we pretend that subsequent bits
5608 have to be sign-bit copies too. */
5609 || num_sign_bit_copies_in_rep
[in_mode
][mode
])
5610 num_sign_bit_copies_in_rep
[in_mode
][mode
]
5611 += GET_MODE_PRECISION (wider
) - GET_MODE_PRECISION (i
);
5616 /* Suppose that truncation from the machine mode of X to MODE is not a
5617 no-op. See if there is anything special about X so that we can
5618 assume it already contains a truncated value of MODE. */
5621 truncated_to_mode (machine_mode mode
, const_rtx x
)
5623 /* This register has already been used in MODE without explicit
5625 if (REG_P (x
) && rtl_hooks
.reg_truncated_to_mode (mode
, x
))
5628 /* See if we already satisfy the requirements of MODE. If yes we
5629 can just switch to MODE. */
5630 if (num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
]
5631 && (num_sign_bit_copies (x
, GET_MODE (x
))
5632 >= num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
] + 1))
5638 /* Return true if RTX code CODE has a single sequence of zero or more
5639 "e" operands and no rtvec operands. Initialize its rtx_all_subrtx_bounds
5640 entry in that case. */
5643 setup_reg_subrtx_bounds (unsigned int code
)
5645 const char *format
= GET_RTX_FORMAT ((enum rtx_code
) code
);
5647 for (; format
[i
] != 'e'; ++i
)
5650 /* No subrtxes. Leave start and count as 0. */
5652 if (format
[i
] == 'E' || format
[i
] == 'V')
5656 /* Record the sequence of 'e's. */
5657 rtx_all_subrtx_bounds
[code
].start
= i
;
5660 while (format
[i
] == 'e');
5661 rtx_all_subrtx_bounds
[code
].count
= i
- rtx_all_subrtx_bounds
[code
].start
;
5662 /* rtl-iter.h relies on this. */
5663 gcc_checking_assert (rtx_all_subrtx_bounds
[code
].count
<= 3);
5665 for (; format
[i
]; ++i
)
5666 if (format
[i
] == 'E' || format
[i
] == 'V' || format
[i
] == 'e')
5672 /* Initialize rtx_all_subrtx_bounds. */
5677 for (i
= 0; i
< NUM_RTX_CODE
; i
++)
5679 if (!setup_reg_subrtx_bounds (i
))
5680 rtx_all_subrtx_bounds
[i
].count
= UCHAR_MAX
;
5681 if (GET_RTX_CLASS (i
) != RTX_CONST_OBJ
)
5682 rtx_nonconst_subrtx_bounds
[i
] = rtx_all_subrtx_bounds
[i
];
5685 init_num_sign_bit_copies_in_rep ();
5688 /* Check whether this is a constant pool constant. */
5690 constant_pool_constant_p (rtx x
)
5692 x
= avoid_constant_pool_reference (x
);
5693 return CONST_DOUBLE_P (x
);
5696 /* If M is a bitmask that selects a field of low-order bits within an item but
5697 not the entire word, return the length of the field. Return -1 otherwise.
5698 M is used in machine mode MODE. */
5701 low_bitmask_len (machine_mode mode
, unsigned HOST_WIDE_INT m
)
5703 if (mode
!= VOIDmode
)
5705 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
5707 m
&= GET_MODE_MASK (mode
);
5710 return exact_log2 (m
+ 1);
5713 /* Return the mode of MEM's address. */
5716 get_address_mode (rtx mem
)
5720 gcc_assert (MEM_P (mem
));
5721 mode
= GET_MODE (XEXP (mem
, 0));
5722 if (mode
!= VOIDmode
)
5724 return targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (mem
));
5727 /* Split up a CONST_DOUBLE or integer constant rtx
5728 into two rtx's for single words,
5729 storing in *FIRST the word that comes first in memory in the target
5730 and in *SECOND the other.
5732 TODO: This function needs to be rewritten to work on any size
5736 split_double (rtx value
, rtx
*first
, rtx
*second
)
5738 if (CONST_INT_P (value
))
5740 if (HOST_BITS_PER_WIDE_INT
>= (2 * BITS_PER_WORD
))
5742 /* In this case the CONST_INT holds both target words.
5743 Extract the bits from it into two word-sized pieces.
5744 Sign extend each half to HOST_WIDE_INT. */
5745 unsigned HOST_WIDE_INT low
, high
;
5746 unsigned HOST_WIDE_INT mask
, sign_bit
, sign_extend
;
5747 unsigned bits_per_word
= BITS_PER_WORD
;
5749 /* Set sign_bit to the most significant bit of a word. */
5751 sign_bit
<<= bits_per_word
- 1;
5753 /* Set mask so that all bits of the word are set. We could
5754 have used 1 << BITS_PER_WORD instead of basing the
5755 calculation on sign_bit. However, on machines where
5756 HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a
5757 compiler warning, even though the code would never be
5759 mask
= sign_bit
<< 1;
5762 /* Set sign_extend as any remaining bits. */
5763 sign_extend
= ~mask
;
5765 /* Pick the lower word and sign-extend it. */
5766 low
= INTVAL (value
);
5771 /* Pick the higher word, shifted to the least significant
5772 bits, and sign-extend it. */
5773 high
= INTVAL (value
);
5774 high
>>= bits_per_word
- 1;
5777 if (high
& sign_bit
)
5778 high
|= sign_extend
;
5780 /* Store the words in the target machine order. */
5781 if (WORDS_BIG_ENDIAN
)
5783 *first
= GEN_INT (high
);
5784 *second
= GEN_INT (low
);
5788 *first
= GEN_INT (low
);
5789 *second
= GEN_INT (high
);
5794 /* The rule for using CONST_INT for a wider mode
5795 is that we regard the value as signed.
5796 So sign-extend it. */
5797 rtx high
= (INTVAL (value
) < 0 ? constm1_rtx
: const0_rtx
);
5798 if (WORDS_BIG_ENDIAN
)
5810 else if (GET_CODE (value
) == CONST_WIDE_INT
)
5812 /* All of this is scary code and needs to be converted to
5813 properly work with any size integer. */
5814 gcc_assert (CONST_WIDE_INT_NUNITS (value
) == 2);
5815 if (WORDS_BIG_ENDIAN
)
5817 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
5818 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
5822 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
5823 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
5826 else if (!CONST_DOUBLE_P (value
))
5828 if (WORDS_BIG_ENDIAN
)
5830 *first
= const0_rtx
;
5836 *second
= const0_rtx
;
5839 else if (GET_MODE (value
) == VOIDmode
5840 /* This is the old way we did CONST_DOUBLE integers. */
5841 || GET_MODE_CLASS (GET_MODE (value
)) == MODE_INT
)
5843 /* In an integer, the words are defined as most and least significant.
5844 So order them by the target's convention. */
5845 if (WORDS_BIG_ENDIAN
)
5847 *first
= GEN_INT (CONST_DOUBLE_HIGH (value
));
5848 *second
= GEN_INT (CONST_DOUBLE_LOW (value
));
5852 *first
= GEN_INT (CONST_DOUBLE_LOW (value
));
5853 *second
= GEN_INT (CONST_DOUBLE_HIGH (value
));
5860 /* Note, this converts the REAL_VALUE_TYPE to the target's
5861 format, splits up the floating point double and outputs
5862 exactly 32 bits of it into each of l[0] and l[1] --
5863 not necessarily BITS_PER_WORD bits. */
5864 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (value
), l
);
5866 /* If 32 bits is an entire word for the target, but not for the host,
5867 then sign-extend on the host so that the number will look the same
5868 way on the host that it would on the target. See for instance
5869 simplify_unary_operation. The #if is needed to avoid compiler
5872 #if HOST_BITS_PER_LONG > 32
5873 if (BITS_PER_WORD
< HOST_BITS_PER_LONG
&& BITS_PER_WORD
== 32)
5875 if (l
[0] & ((long) 1 << 31))
5876 l
[0] |= ((unsigned long) (-1) << 32);
5877 if (l
[1] & ((long) 1 << 31))
5878 l
[1] |= ((unsigned long) (-1) << 32);
5882 *first
= GEN_INT (l
[0]);
5883 *second
= GEN_INT (l
[1]);
5887 /* Return true if X is a sign_extract or zero_extract from the least
5891 lsb_bitfield_op_p (rtx x
)
5893 if (GET_RTX_CLASS (GET_CODE (x
)) == RTX_BITFIELD_OPS
)
5895 machine_mode mode
= GET_MODE (XEXP (x
, 0));
5896 HOST_WIDE_INT len
= INTVAL (XEXP (x
, 1));
5897 HOST_WIDE_INT pos
= INTVAL (XEXP (x
, 2));
5899 return (pos
== (BITS_BIG_ENDIAN
? GET_MODE_PRECISION (mode
) - len
: 0));
5904 /* Strip outer address "mutations" from LOC and return a pointer to the
5905 inner value. If OUTER_CODE is nonnull, store the code of the innermost
5906 stripped expression there.
5908 "Mutations" either convert between modes or apply some kind of
5909 extension, truncation or alignment. */
5912 strip_address_mutations (rtx
*loc
, enum rtx_code
*outer_code
)
5916 enum rtx_code code
= GET_CODE (*loc
);
5917 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
5918 /* Things like SIGN_EXTEND, ZERO_EXTEND and TRUNCATE can be
5919 used to convert between pointer sizes. */
5920 loc
= &XEXP (*loc
, 0);
5921 else if (lsb_bitfield_op_p (*loc
))
5922 /* A [SIGN|ZERO]_EXTRACT from the least significant bit effectively
5923 acts as a combined truncation and extension. */
5924 loc
= &XEXP (*loc
, 0);
5925 else if (code
== AND
&& CONST_INT_P (XEXP (*loc
, 1)))
5926 /* (and ... (const_int -X)) is used to align to X bytes. */
5927 loc
= &XEXP (*loc
, 0);
5928 else if (code
== SUBREG
5929 && !OBJECT_P (SUBREG_REG (*loc
))
5930 && subreg_lowpart_p (*loc
))
5931 /* (subreg (operator ...) ...) inside and is used for mode
5933 loc
= &SUBREG_REG (*loc
);
5941 /* Return true if CODE applies some kind of scale. The scaled value is
5942 is the first operand and the scale is the second. */
5945 binary_scale_code_p (enum rtx_code code
)
5947 return (code
== MULT
5949 /* Needed by ARM targets. */
5953 || code
== ROTATERT
);
5956 /* If *INNER can be interpreted as a base, return a pointer to the inner term
5957 (see address_info). Return null otherwise. */
5960 get_base_term (rtx
*inner
)
5962 if (GET_CODE (*inner
) == LO_SUM
)
5963 inner
= strip_address_mutations (&XEXP (*inner
, 0));
5966 || GET_CODE (*inner
) == SUBREG
5967 || GET_CODE (*inner
) == SCRATCH
)
5972 /* If *INNER can be interpreted as an index, return a pointer to the inner term
5973 (see address_info). Return null otherwise. */
5976 get_index_term (rtx
*inner
)
5978 /* At present, only constant scales are allowed. */
5979 if (binary_scale_code_p (GET_CODE (*inner
)) && CONSTANT_P (XEXP (*inner
, 1)))
5980 inner
= strip_address_mutations (&XEXP (*inner
, 0));
5983 || GET_CODE (*inner
) == SUBREG
5984 || GET_CODE (*inner
) == SCRATCH
)
5989 /* Set the segment part of address INFO to LOC, given that INNER is the
5993 set_address_segment (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
5995 gcc_assert (!info
->segment
);
5996 info
->segment
= loc
;
5997 info
->segment_term
= inner
;
6000 /* Set the base part of address INFO to LOC, given that INNER is the
6004 set_address_base (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6006 gcc_assert (!info
->base
);
6008 info
->base_term
= inner
;
6011 /* Set the index part of address INFO to LOC, given that INNER is the
6015 set_address_index (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6017 gcc_assert (!info
->index
);
6019 info
->index_term
= inner
;
6022 /* Set the displacement part of address INFO to LOC, given that INNER
6023 is the constant term. */
6026 set_address_disp (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6028 gcc_assert (!info
->disp
);
6030 info
->disp_term
= inner
;
6033 /* INFO->INNER describes a {PRE,POST}_{INC,DEC} address. Set up the
6034 rest of INFO accordingly. */
6037 decompose_incdec_address (struct address_info
*info
)
6039 info
->autoinc_p
= true;
6041 rtx
*base
= &XEXP (*info
->inner
, 0);
6042 set_address_base (info
, base
, base
);
6043 gcc_checking_assert (info
->base
== info
->base_term
);
6045 /* These addresses are only valid when the size of the addressed
6047 gcc_checking_assert (info
->mode
!= VOIDmode
);
6050 /* INFO->INNER describes a {PRE,POST}_MODIFY address. Set up the rest
6051 of INFO accordingly. */
6054 decompose_automod_address (struct address_info
*info
)
6056 info
->autoinc_p
= true;
6058 rtx
*base
= &XEXP (*info
->inner
, 0);
6059 set_address_base (info
, base
, base
);
6060 gcc_checking_assert (info
->base
== info
->base_term
);
6062 rtx plus
= XEXP (*info
->inner
, 1);
6063 gcc_assert (GET_CODE (plus
) == PLUS
);
6065 info
->base_term2
= &XEXP (plus
, 0);
6066 gcc_checking_assert (rtx_equal_p (*info
->base_term
, *info
->base_term2
));
6068 rtx
*step
= &XEXP (plus
, 1);
6069 rtx
*inner_step
= strip_address_mutations (step
);
6070 if (CONSTANT_P (*inner_step
))
6071 set_address_disp (info
, step
, inner_step
);
6073 set_address_index (info
, step
, inner_step
);
6076 /* Treat *LOC as a tree of PLUS operands and store pointers to the summed
6077 values in [PTR, END). Return a pointer to the end of the used array. */
6080 extract_plus_operands (rtx
*loc
, rtx
**ptr
, rtx
**end
)
6083 if (GET_CODE (x
) == PLUS
)
6085 ptr
= extract_plus_operands (&XEXP (x
, 0), ptr
, end
);
6086 ptr
= extract_plus_operands (&XEXP (x
, 1), ptr
, end
);
6090 gcc_assert (ptr
!= end
);
6096 /* Evaluate the likelihood of X being a base or index value, returning
6097 positive if it is likely to be a base, negative if it is likely to be
6098 an index, and 0 if we can't tell. Make the magnitude of the return
6099 value reflect the amount of confidence we have in the answer.
6101 MODE, AS, OUTER_CODE and INDEX_CODE are as for ok_for_base_p_1. */
6104 baseness (rtx x
, machine_mode mode
, addr_space_t as
,
6105 enum rtx_code outer_code
, enum rtx_code index_code
)
6107 /* Believe *_POINTER unless the address shape requires otherwise. */
6108 if (REG_P (x
) && REG_POINTER (x
))
6110 if (MEM_P (x
) && MEM_POINTER (x
))
6113 if (REG_P (x
) && HARD_REGISTER_P (x
))
6115 /* X is a hard register. If it only fits one of the base
6116 or index classes, choose that interpretation. */
6117 int regno
= REGNO (x
);
6118 bool base_p
= ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
6119 bool index_p
= REGNO_OK_FOR_INDEX_P (regno
);
6120 if (base_p
!= index_p
)
6121 return base_p
? 1 : -1;
6126 /* INFO->INNER describes a normal, non-automodified address.
6127 Fill in the rest of INFO accordingly. */
6130 decompose_normal_address (struct address_info
*info
)
6132 /* Treat the address as the sum of up to four values. */
6134 size_t n_ops
= extract_plus_operands (info
->inner
, ops
,
6135 ops
+ ARRAY_SIZE (ops
)) - ops
;
6137 /* If there is more than one component, any base component is in a PLUS. */
6139 info
->base_outer_code
= PLUS
;
6141 /* Try to classify each sum operand now. Leave those that could be
6142 either a base or an index in OPS. */
6145 for (size_t in
= 0; in
< n_ops
; ++in
)
6148 rtx
*inner
= strip_address_mutations (loc
);
6149 if (CONSTANT_P (*inner
))
6150 set_address_disp (info
, loc
, inner
);
6151 else if (GET_CODE (*inner
) == UNSPEC
)
6152 set_address_segment (info
, loc
, inner
);
6155 /* The only other possibilities are a base or an index. */
6156 rtx
*base_term
= get_base_term (inner
);
6157 rtx
*index_term
= get_index_term (inner
);
6158 gcc_assert (base_term
|| index_term
);
6160 set_address_index (info
, loc
, index_term
);
6161 else if (!index_term
)
6162 set_address_base (info
, loc
, base_term
);
6165 gcc_assert (base_term
== index_term
);
6167 inner_ops
[out
] = base_term
;
6173 /* Classify the remaining OPS members as bases and indexes. */
6176 /* If we haven't seen a base or an index yet, assume that this is
6177 the base. If we were confident that another term was the base
6178 or index, treat the remaining operand as the other kind. */
6180 set_address_base (info
, ops
[0], inner_ops
[0]);
6182 set_address_index (info
, ops
[0], inner_ops
[0]);
6186 /* In the event of a tie, assume the base comes first. */
6187 if (baseness (*inner_ops
[0], info
->mode
, info
->as
, PLUS
,
6189 >= baseness (*inner_ops
[1], info
->mode
, info
->as
, PLUS
,
6190 GET_CODE (*ops
[0])))
6192 set_address_base (info
, ops
[0], inner_ops
[0]);
6193 set_address_index (info
, ops
[1], inner_ops
[1]);
6197 set_address_base (info
, ops
[1], inner_ops
[1]);
6198 set_address_index (info
, ops
[0], inner_ops
[0]);
6202 gcc_assert (out
== 0);
6205 /* Describe address *LOC in *INFO. MODE is the mode of the addressed value,
6206 or VOIDmode if not known. AS is the address space associated with LOC.
6207 OUTER_CODE is MEM if *LOC is a MEM address and ADDRESS otherwise. */
6210 decompose_address (struct address_info
*info
, rtx
*loc
, machine_mode mode
,
6211 addr_space_t as
, enum rtx_code outer_code
)
6213 memset (info
, 0, sizeof (*info
));
6216 info
->addr_outer_code
= outer_code
;
6218 info
->inner
= strip_address_mutations (loc
, &outer_code
);
6219 info
->base_outer_code
= outer_code
;
6220 switch (GET_CODE (*info
->inner
))
6226 decompose_incdec_address (info
);
6231 decompose_automod_address (info
);
6235 decompose_normal_address (info
);
6240 /* Describe address operand LOC in INFO. */
6243 decompose_lea_address (struct address_info
*info
, rtx
*loc
)
6245 decompose_address (info
, loc
, VOIDmode
, ADDR_SPACE_GENERIC
, ADDRESS
);
6248 /* Describe the address of MEM X in INFO. */
6251 decompose_mem_address (struct address_info
*info
, rtx x
)
6253 gcc_assert (MEM_P (x
));
6254 decompose_address (info
, &XEXP (x
, 0), GET_MODE (x
),
6255 MEM_ADDR_SPACE (x
), MEM
);
6258 /* Update INFO after a change to the address it describes. */
6261 update_address (struct address_info
*info
)
6263 decompose_address (info
, info
->outer
, info
->mode
, info
->as
,
6264 info
->addr_outer_code
);
6267 /* Return the scale applied to *INFO->INDEX_TERM, or 0 if the index is
6268 more complicated than that. */
6271 get_index_scale (const struct address_info
*info
)
6273 rtx index
= *info
->index
;
6274 if (GET_CODE (index
) == MULT
6275 && CONST_INT_P (XEXP (index
, 1))
6276 && info
->index_term
== &XEXP (index
, 0))
6277 return INTVAL (XEXP (index
, 1));
6279 if (GET_CODE (index
) == ASHIFT
6280 && CONST_INT_P (XEXP (index
, 1))
6281 && info
->index_term
== &XEXP (index
, 0))
6282 return HOST_WIDE_INT_1
<< INTVAL (XEXP (index
, 1));
6284 if (info
->index
== info
->index_term
)
6290 /* Return the "index code" of INFO, in the form required by
6294 get_index_code (const struct address_info
*info
)
6297 return GET_CODE (*info
->index
);
6300 return GET_CODE (*info
->disp
);
6305 /* Return true if RTL X contains a SYMBOL_REF. */
6308 contains_symbol_ref_p (const_rtx x
)
6310 subrtx_iterator::array_type array
;
6311 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6312 if (SYMBOL_REF_P (*iter
))
6318 /* Return true if RTL X contains a SYMBOL_REF or LABEL_REF. */
6321 contains_symbolic_reference_p (const_rtx x
)
6323 subrtx_iterator::array_type array
;
6324 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6325 if (SYMBOL_REF_P (*iter
) || GET_CODE (*iter
) == LABEL_REF
)
6331 /* Return true if X contains a thread-local symbol. */
6334 tls_referenced_p (const_rtx x
)
6336 if (!targetm
.have_tls
)
6339 subrtx_iterator::array_type array
;
6340 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6341 if (GET_CODE (*iter
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (*iter
) != 0)