| blob | 8f71378244ac6806d968f832cd9567e33b6a93ff |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 91-96, 1997 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
10 ;; any later version.
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 \f
24 ;; Define an insn type attribute. This is used in function unit delay
25 ;; computations.
26 (define_attr "type" "integer,load,store,fpload,fpstore,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
27 (const_string "integer"))
29 ;; Length (in bytes).
30 (define_attr "length" ""
31 (if_then_else (eq_attr "type" "branch")
32 (if_then_else (and (ge (minus (pc) (match_dup 0))
33 (const_int -32768))
34 (lt (minus (pc) (match_dup 0))
35 (const_int 32767)))
36 (const_int 8)
37 (const_int 12))
38 (const_int 4)))
40 ;; Processor type -- this attribute must exactly match the processor_type
41 ;; enumeration in rs6000.h.
43 (define_attr "cpu" "rios1,rios2,mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"
44 (const (symbol_ref "rs6000_cpu_attr")))
46 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
47 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
49 ; Load/Store Unit -- pure PowerPC only
50 ; (POWER and 601 use Integer Unit)
51 (define_function_unit "lsu" 1 0
52 (and (eq_attr "type" "load")
53 (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc620"))
54 2 1)
56 (define_function_unit "lsu" 1 0
57 (and (eq_attr "type" "store,fpstore")
58 (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc620"))
59 1 1)
61 (define_function_unit "lsu" 1 0
62 (and (eq_attr "type" "fpload")
63 (eq_attr "cpu" "mpccore,ppc603"))
64 2 1)
66 (define_function_unit "lsu" 1 0
67 (and (eq_attr "type" "fpload")
68 (eq_attr "cpu" "ppc604,ppc620"))
69 3 1)
71 (define_function_unit "iu" 1 0
72 (and (eq_attr "type" "load")
73 (eq_attr "cpu" "rios1,ppc403,ppc601"))
74 2 1)
76 (define_function_unit "iu" 1 0
77 (and (eq_attr "type" "store,fpstore")
78 (eq_attr "cpu" "rios1,ppc403,ppc601"))
79 1 1)
81 (define_function_unit "fpu" 1 0
82 (and (eq_attr "type" "fpstore")
83 (eq_attr "cpu" "rios1,ppc601"))
84 0 1)
86 (define_function_unit "iu" 1 0
87 (and (eq_attr "type" "fpload")
88 (eq_attr "cpu" "rios1"))
89 2 1)
91 (define_function_unit "iu" 1 0
92 (and (eq_attr "type" "fpload")
93 (eq_attr "cpu" "ppc601"))
94 3 1)
96 (define_function_unit "iu2" 2 0
97 (and (eq_attr "type" "load,fpload")
98 (eq_attr "cpu" "rios2"))
99 2 1)
101 (define_function_unit "iu2" 2 0
102 (and (eq_attr "type" "store,fpstore")
103 (eq_attr "cpu" "rios2"))
104 1 1)
106 ; Integer Unit (RIOS1, PPC601, PPC603)
107 (define_function_unit "iu" 1 0
108 (and (eq_attr "type" "integer")
109 (eq_attr "cpu" "rios1,mpccore,ppc403,ppc601,ppc603"))
110 1 1)
112 (define_function_unit "iu" 1 0
113 (and (eq_attr "type" "imul")
114 (eq_attr "cpu" "ppc403"))
115 4 4)
117 (define_function_unit "iu" 1 0
118 (and (eq_attr "type" "imul")
119 (eq_attr "cpu" "rios1,ppc601,ppc603"))
120 5 5)
122 (define_function_unit "iu" 1 0
123 (and (eq_attr "type" "idiv")
124 (eq_attr "cpu" "rios1"))
125 19 19)
127 (define_function_unit "iu" 1 0
128 (and (eq_attr "type" "idiv")
129 (eq_attr "cpu" "ppc403"))
130 33 33)
132 (define_function_unit "iu" 1 0
133 (and (eq_attr "type" "idiv")
134 (eq_attr "cpu" "ppc601"))
135 36 36)
137 (define_function_unit "iu" 1 0
138 (and (eq_attr "type" "idiv")
139 (eq_attr "cpu" "ppc603"))
140 37 36)
142 ; RIOS2 has two integer units: a primary one which can perform all
143 ; operations and a secondary one which is fed in lock step with the first
144 ; and can perform "simple" integer operations.
145 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
146 ; for the complex insns.
147 (define_function_unit "iu2" 2 0
148 (and (eq_attr "type" "integer")
149 (eq_attr "cpu" "rios2"))
150 1 1)
152 (define_function_unit "iu2" 2 0
153 (and (eq_attr "type" "imul")
154 (eq_attr "cpu" "rios2"))
155 2 2)
157 (define_function_unit "iu2" 2 0
158 (and (eq_attr "type" "idiv")
159 (eq_attr "cpu" "rios2"))
160 13 13)
162 (define_function_unit "imuldiv" 1 0
163 (and (eq_attr "type" "imul")
164 (eq_attr "cpu" "rios2"))
165 2 2)
167 (define_function_unit "imuldiv" 1 0
168 (and (eq_attr "type" "idiv")
169 (eq_attr "cpu" "rios2"))
170 13 13)
172 ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions
173 ; Divide latency varies greatly from 2-11, use 6 as average
174 (define_function_unit "imuldiv" 1 0
175 (and (eq_attr "type" "imul")
176 (eq_attr "cpu" "mpccore"))
177 2 1)
179 (define_function_unit "imuldiv" 1 0
180 (and (eq_attr "type" "idiv")
181 (eq_attr "cpu" "mpccore"))
182 6 6)
184 ; PPC604 has two units that perform integer operations
185 ; and one unit for divide/multiply operations (and move
186 ; from/to spr).
187 (define_function_unit "iu2" 2 0
188 (and (eq_attr "type" "integer")
189 (eq_attr "cpu" "ppc604,ppc620"))
190 1 1)
192 (define_function_unit "imuldiv" 1 0
193 (and (eq_attr "type" "imul")
194 (eq_attr "cpu" "ppc604,ppc620"))
195 4 2)
197 (define_function_unit "imuldiv" 1 0
198 (and (eq_attr "type" "idiv")
199 (eq_attr "cpu" "ppc604,ppc620"))
200 20 19)
202 ; compare is done on integer unit, but feeds insns which
203 ; execute on the branch unit.
204 (define_function_unit "iu" 1 0
205 (and (eq_attr "type" "compare")
206 (eq_attr "cpu" "rios1"))
207 4 1)
209 (define_function_unit "iu" 1 0
210 (and (eq_attr "type" "delayed_compare")
211 (eq_attr "cpu" "rios1"))
212 5 1)
214 (define_function_unit "iu" 1 0
215 (and (eq_attr "type" "compare,delayed_compare")
216 (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"))
217 3 1)
219 (define_function_unit "iu2" 2 0
220 (and (eq_attr "type" "compare,delayed_compare")
221 (eq_attr "cpu" "rios2"))
222 3 1)
224 (define_function_unit "iu2" 2 0
225 (and (eq_attr "type" "compare,delayed_compare")
226 (eq_attr "cpu" "ppc604,ppc620"))
227 1 1)
229 ; fp compare uses fp unit
230 (define_function_unit "fpu" 1 0
231 (and (eq_attr "type" "fpcompare")
232 (eq_attr "cpu" "rios1"))
233 9 1)
235 ; rios1 and rios2 have different fpcompare delays
236 (define_function_unit "fpu2" 2 0
237 (and (eq_attr "type" "fpcompare")
238 (eq_attr "cpu" "rios2"))
239 5 1)
241 ; on ppc601 and ppc603, fpcompare takes also 2 cycles from
242 ; the integer unit
243 ; here we do not define delays, just occupy the unit. The dependencies
244 ; will be assigned by the fpcompare definition in the fpu.
245 (define_function_unit "iu" 1 0
246 (and (eq_attr "type" "fpcompare")
247 (eq_attr "cpu" "ppc601,ppc603"))
248 0 2)
250 ; fp compare uses fp unit
251 (define_function_unit "fpu" 1 0
252 (and (eq_attr "type" "fpcompare")
253 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
254 5 1)
256 (define_function_unit "fpu" 1 0
257 (and (eq_attr "type" "fpcompare")
258 (eq_attr "cpu" "mpccore"))
259 1 1)
261 (define_function_unit "bpu" 1 0
262 (and (eq_attr "type" "mtjmpr")
263 (eq_attr "cpu" "rios1,rios2"))
264 5 1)
266 (define_function_unit "bpu" 1 0
267 (and (eq_attr "type" "mtjmpr")
268 (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"))
269 4 1)
271 ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines.
272 (define_function_unit "bpu" 1 0
273 (eq_attr "type" "jmpreg")
274 1 1)
276 (define_function_unit "bpu" 1 0
277 (eq_attr "type" "branch")
278 1 1)
280 ; Floating Point Unit
281 (define_function_unit "fpu" 1 0
282 (and (eq_attr "type" "fp,dmul")
283 (eq_attr "cpu" "rios1"))
284 2 1)
286 (define_function_unit "fpu" 1 0
287 (and (eq_attr "type" "fp")
288 (eq_attr "cpu" "mpccore"))
289 4 4)
291 (define_function_unit "fpu" 1 0
292 (and (eq_attr "type" "fp")
293 (eq_attr "cpu" "ppc601"))
294 4 1)
296 (define_function_unit "fpu" 1 0
297 (and (eq_attr "type" "fp")
298 (eq_attr "cpu" "ppc603,ppc604,ppc620"))
299 3 1)
301 (define_function_unit "fpu" 1 0
302 (and (eq_attr "type" "dmul")
303 (eq_attr "cpu" "mpccore"))
304 5 5)
306 (define_function_unit "fpu" 1 0
307 (and (eq_attr "type" "dmul")
308 (eq_attr "cpu" "ppc601"))
309 5 2)
311 ; is this true?
312 (define_function_unit "fpu" 1 0
313 (and (eq_attr "type" "dmul")
314 (eq_attr "cpu" "ppc603"))
315 4 2)
317 (define_function_unit "fpu" 1 0
318 (and (eq_attr "type" "dmul")
319 (eq_attr "cpu" "ppc604,ppc620"))
320 3 1)
322 (define_function_unit "fpu" 1 0
323 (and (eq_attr "type" "sdiv,ddiv")
324 (eq_attr "cpu" "rios1"))
325 19 19)
327 (define_function_unit "fpu" 1 0
328 (and (eq_attr "type" "sdiv")
329 (eq_attr "cpu" "ppc601"))
330 17 17)
332 (define_function_unit "fpu" 1 0
333 (and (eq_attr "type" "sdiv")
334 (eq_attr "cpu" "mpccore"))
335 10 10)
337 (define_function_unit "fpu" 1 0
338 (and (eq_attr "type" "sdiv")
339 (eq_attr "cpu" "ppc603,ppc604,ppc620"))
340 18 18)
342 (define_function_unit "fpu" 1 0
343 (and (eq_attr "type" "ddiv")
344 (eq_attr "cpu" "mpccore"))
345 17 17)
347 (define_function_unit "fpu" 1 0
348 (and (eq_attr "type" "ddiv")
349 (eq_attr "cpu" "ppc601,ppc604,ppc620"))
350 31 31)
352 (define_function_unit "fpu" 1 0
353 (and (eq_attr "type" "ddiv")
354 (eq_attr "cpu" "ppc603"))
355 33 33)
357 (define_function_unit "fpu" 1 0
358 (and (eq_attr "type" "ssqrt")
359 (eq_attr "cpu" "ppc620"))
360 31 31)
362 (define_function_unit "fpu" 1 0
363 (and (eq_attr "type" "dsqrt")
364 (eq_attr "cpu" "ppc620"))
365 31 31)
367 ; RIOS2 has two symmetric FPUs.
368 (define_function_unit "fpu2" 2 0
369 (and (eq_attr "type" "fp")
370 (eq_attr "cpu" "rios2"))
371 2 1)
373 (define_function_unit "fpu2" 2 0
374 (and (eq_attr "type" "dmul")
375 (eq_attr "cpu" "rios2"))
376 2 1)
378 (define_function_unit "fpu2" 2 0
379 (and (eq_attr "type" "sdiv,ddiv")
380 (eq_attr "cpu" "rios2"))
381 17 17)
383 (define_function_unit "fpu2" 2 0
384 (and (eq_attr "type" "ssqrt,dsqrt")
385 (eq_attr "cpu" "rios2"))
386 26 26)
388 \f
389 ;; Start with fixed-point load and store insns. Here we put only the more
390 ;; complex forms. Basic data transfer is done later.
392 (define_expand "zero_extendqidi2"
393 [(set (match_operand:DI 0 "gpc_reg_operand" "")
394 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
395 "TARGET_POWERPC64"
396 "")
398 (define_insn ""
399 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
400 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
401 "TARGET_POWERPC64"
402 "@
403 lbz%U1%X1 %0,%1
404 rldicl %0,%1,0,56"
405 [(set_attr "type" "load,*")])
407 (define_insn ""
408 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
409 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
410 (const_int 0)))
411 (clobber (match_scratch:DI 2 "=r"))]
412 "TARGET_POWERPC64"
413 "rldicl. %2,%1,0,56"
414 [(set_attr "type" "compare")])
416 (define_insn ""
417 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
418 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
419 (const_int 0)))
420 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
421 (zero_extend:DI (match_dup 1)))]
422 "TARGET_POWERPC64"
423 "rldicl. %0,%1,0,56"
424 [(set_attr "type" "compare")])
426 (define_insn "extendqidi2"
427 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
428 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
429 "TARGET_POWERPC64"
430 "extsb %0,%1")
432 (define_insn ""
433 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
434 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
435 (const_int 0)))
436 (clobber (match_scratch:DI 2 "=r"))]
437 "TARGET_POWERPC64"
438 "extsb. %2,%1"
439 [(set_attr "type" "compare")])
441 (define_insn ""
442 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
443 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
444 (const_int 0)))
445 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
446 (sign_extend:DI (match_dup 1)))]
447 "TARGET_POWERPC64"
448 "extsb. %0,%1"
449 [(set_attr "type" "compare")])
451 (define_expand "zero_extendhidi2"
452 [(set (match_operand:DI 0 "gpc_reg_operand" "")
453 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
454 "TARGET_POWERPC64"
455 "")
457 (define_insn ""
458 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
459 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
460 "TARGET_POWERPC64"
461 "@
462 lhz%U1%X1 %0,%1
463 rldicl %0,%1,0,48"
464 [(set_attr "type" "load,*")])
466 (define_insn ""
467 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
468 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
469 (const_int 0)))
470 (clobber (match_scratch:DI 2 "=r"))]
471 "TARGET_POWERPC64"
472 "rldicl. %2,%1,0,48"
473 [(set_attr "type" "compare")])
475 (define_insn ""
476 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
477 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
478 (const_int 0)))
479 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
480 (zero_extend:DI (match_dup 1)))]
481 "TARGET_POWERPC64"
482 "rldicl. %0,%1,0,48"
483 [(set_attr "type" "compare")])
485 (define_expand "extendhidi2"
486 [(set (match_operand:DI 0 "gpc_reg_operand" "")
487 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
488 "TARGET_POWERPC64"
489 "")
491 (define_insn ""
492 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
493 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
494 "TARGET_POWERPC64"
495 "@
496 lha%U1%X1 %0,%1
497 extsh %0,%1"
498 [(set_attr "type" "load,*")])
500 (define_insn ""
501 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
502 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
503 (const_int 0)))
504 (clobber (match_scratch:DI 2 "=r"))]
505 "TARGET_POWERPC64"
506 "extsh. %2,%1"
507 [(set_attr "type" "compare")])
509 (define_insn ""
510 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
511 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
512 (const_int 0)))
513 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
514 (sign_extend:DI (match_dup 1)))]
515 "TARGET_POWERPC64"
516 "extsh. %0,%1"
517 [(set_attr "type" "compare")])
519 (define_expand "zero_extendsidi2"
520 [(set (match_operand:DI 0 "gpc_reg_operand" "")
521 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
522 "TARGET_POWERPC64"
523 "")
525 (define_insn ""
526 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
527 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
528 "TARGET_POWERPC64"
529 "@
530 lwz%U1%X1 %0,%1
531 rldicl %0,%1,0,32"
532 [(set_attr "type" "load,*")])
534 (define_insn ""
535 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
536 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
537 (const_int 0)))
538 (clobber (match_scratch:DI 2 "=r"))]
539 "TARGET_POWERPC64"
540 "rldicl. %2,%1,0,32"
541 [(set_attr "type" "compare")])
543 (define_insn ""
544 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
545 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
546 (const_int 0)))
547 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
548 (zero_extend:DI (match_dup 1)))]
549 "TARGET_POWERPC64"
550 "rldicl. %0,%1,0,32"
551 [(set_attr "type" "compare")])
553 (define_expand "extendsidi2"
554 [(set (match_operand:DI 0 "gpc_reg_operand" "")
555 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
556 "TARGET_POWERPC64"
557 "")
559 (define_insn ""
560 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
561 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
562 "TARGET_POWERPC64"
563 "@
564 lwa%U1%X1 %0,%1
565 extsw %0,%1"
566 [(set_attr "type" "load,*")])
568 (define_insn ""
569 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
570 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
571 (const_int 0)))
572 (clobber (match_scratch:DI 2 "=r"))]
573 "TARGET_POWERPC64"
574 "extsw. %2,%1"
575 [(set_attr "type" "compare")])
577 (define_insn ""
578 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
579 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
580 (const_int 0)))
581 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
582 (sign_extend:DI (match_dup 1)))]
583 "TARGET_POWERPC64"
584 "extsw. %0,%1"
585 [(set_attr "type" "compare")])
587 (define_expand "zero_extendqisi2"
588 [(set (match_operand:SI 0 "gpc_reg_operand" "")
589 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
590 ""
591 "")
593 (define_insn ""
594 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
595 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
596 ""
597 "@
598 lbz%U1%X1 %0,%1
599 {rlinm|rlwinm} %0,%1,0,0xff"
600 [(set_attr "type" "load,*")])
602 (define_insn ""
603 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
604 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
605 (const_int 0)))
606 (clobber (match_scratch:SI 2 "=r"))]
607 ""
608 "{andil.|andi.} %2,%1,0xff"
609 [(set_attr "type" "compare")])
611 (define_insn ""
612 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
613 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
614 (const_int 0)))
615 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
616 (zero_extend:SI (match_dup 1)))]
617 ""
618 "{andil.|andi.} %0,%1,0xff"
619 [(set_attr "type" "compare")])
621 (define_expand "extendqisi2"
622 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
623 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
624 ""
625 "
626 {
627 if (TARGET_POWERPC)
628 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
629 else if (TARGET_POWER)
630 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
631 else
632 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
633 DONE;
634 }")
636 (define_insn "extendqisi2_ppc"
637 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
638 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
639 "TARGET_POWERPC"
640 "extsb %0,%1")
642 (define_insn ""
643 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
644 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
645 (const_int 0)))
646 (clobber (match_scratch:SI 2 "=r"))]
647 "TARGET_POWERPC"
648 "extsb. %2,%1"
649 [(set_attr "type" "compare")])
651 (define_insn ""
652 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
653 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
654 (const_int 0)))
655 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
656 (sign_extend:SI (match_dup 1)))]
657 "TARGET_POWERPC"
658 "extsb. %0,%1"
659 [(set_attr "type" "compare")])
661 (define_expand "extendqisi2_power"
662 [(parallel [(set (match_dup 2)
663 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
664 (const_int 24)))
665 (clobber (scratch:SI))])
666 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
667 (ashiftrt:SI (match_dup 2)
668 (const_int 24)))
669 (clobber (scratch:SI))])]
670 "TARGET_POWER"
671 "
672 { operands[1] = gen_lowpart (SImode, operands[1]);
673 operands[2] = gen_reg_rtx (SImode); }")
675 (define_expand "extendqisi2_no_power"
676 [(set (match_dup 2)
677 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
678 (const_int 24)))
679 (set (match_operand:SI 0 "gpc_reg_operand" "")
680 (ashiftrt:SI (match_dup 2)
681 (const_int 24)))]
682 "! TARGET_POWER && ! TARGET_POWERPC"
683 "
684 { operands[1] = gen_lowpart (SImode, operands[1]);
685 operands[2] = gen_reg_rtx (SImode); }")
687 (define_expand "zero_extendqihi2"
688 [(set (match_operand:HI 0 "gpc_reg_operand" "")
689 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
690 ""
691 "")
693 (define_insn ""
694 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
695 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
696 ""
697 "@
698 lbz%U1%X1 %0,%1
699 {rlinm|rlwinm} %0,%1,0,0xff"
700 [(set_attr "type" "load,*")])
702 (define_insn ""
703 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
704 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
705 (const_int 0)))
706 (clobber (match_scratch:HI 2 "=r"))]
707 ""
708 "{andil.|andi.} %2,%1,0xff"
709 [(set_attr "type" "compare")])
711 (define_insn ""
712 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
713 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
714 (const_int 0)))
715 (set (match_operand:HI 0 "gpc_reg_operand" "=r")
716 (zero_extend:HI (match_dup 1)))]
717 ""
718 "{andil.|andi.} %0,%1,0xff"
719 [(set_attr "type" "compare")])
721 (define_expand "extendqihi2"
722 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
723 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
724 ""
725 "
726 {
727 if (TARGET_POWERPC)
728 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
729 else if (TARGET_POWER)
730 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
731 else
732 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
733 DONE;
734 }")
736 (define_insn "extendqihi2_ppc"
737 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
738 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
739 "TARGET_POWERPC"
740 "extsb %0,%1")
742 (define_insn ""
743 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
744 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
745 (const_int 0)))
746 (clobber (match_scratch:HI 2 "=r"))]
747 "TARGET_POWERPC"
748 "extsb. %2,%1"
749 [(set_attr "type" "compare")])
751 (define_insn ""
752 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
753 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
754 (const_int 0)))
755 (set (match_operand:HI 0 "gpc_reg_operand" "=r")
756 (sign_extend:HI (match_dup 1)))]
757 "TARGET_POWERPC"
758 "extsb. %0,%1"
759 [(set_attr "type" "compare")])
761 (define_expand "extendqihi2_power"
762 [(parallel [(set (match_dup 2)
763 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
764 (const_int 24)))
765 (clobber (scratch:SI))])
766 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
767 (ashiftrt:SI (match_dup 2)
768 (const_int 24)))
769 (clobber (scratch:SI))])]
770 "TARGET_POWER"
771 "
772 { operands[0] = gen_lowpart (SImode, operands[0]);
773 operands[1] = gen_lowpart (SImode, operands[1]);
774 operands[2] = gen_reg_rtx (SImode); }")
776 (define_expand "extendqihi2_no_power"
777 [(set (match_dup 2)
778 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
779 (const_int 24)))
780 (set (match_operand:HI 0 "gpc_reg_operand" "")
781 (ashiftrt:SI (match_dup 2)
782 (const_int 24)))]
783 "! TARGET_POWER && ! TARGET_POWERPC"
784 "
785 { operands[0] = gen_lowpart (SImode, operands[0]);
786 operands[1] = gen_lowpart (SImode, operands[1]);
787 operands[2] = gen_reg_rtx (SImode); }")
789 (define_expand "zero_extendhisi2"
790 [(set (match_operand:SI 0 "gpc_reg_operand" "")
791 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
792 ""
793 "")
795 (define_insn ""
796 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
797 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
798 ""
799 "@
800 lhz%U1%X1 %0,%1
801 {rlinm|rlwinm} %0,%1,0,0xffff"
802 [(set_attr "type" "load,*")])
804 (define_insn ""
805 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
806 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
807 (const_int 0)))
808 (clobber (match_scratch:SI 2 "=r"))]
809 ""
810 "{andil.|andi.} %2,%1,0xffff"
811 [(set_attr "type" "compare")])
813 (define_insn ""
814 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
815 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
816 (const_int 0)))
817 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
818 (zero_extend:SI (match_dup 1)))]
819 ""
820 "{andil.|andi.} %0,%1,0xffff"
821 [(set_attr "type" "compare")])
823 (define_expand "extendhisi2"
824 [(set (match_operand:SI 0 "gpc_reg_operand" "")
825 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
826 ""
827 "")
829 (define_insn ""
830 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
831 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
832 ""
833 "@
834 lha%U1%X1 %0,%1
835 {exts|extsh} %0,%1"
836 [(set_attr "type" "load,*")])
838 (define_insn ""
839 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
840 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
841 (const_int 0)))
842 (clobber (match_scratch:SI 2 "=r"))]
843 ""
844 "{exts.|extsh.} %2,%1"
845 [(set_attr "type" "compare")])
847 (define_insn ""
848 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
849 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
850 (const_int 0)))
851 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
852 (sign_extend:SI (match_dup 1)))]
853 ""
854 "{exts.|extsh.} %0,%1"
855 [(set_attr "type" "compare")])
856 \f
857 ;; Fixed-point arithmetic insns.
859 ;; Discourage ai/addic because of carry but provide it in an alternative
860 ;; allowing register zero as source.
861 (define_expand "addsi3"
862 [(set (match_operand:SI 0 "gpc_reg_operand" "")
863 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
864 (match_operand:SI 2 "reg_or_cint_operand" "")))]
865 ""
866 "
867 {
868 if (GET_CODE (operands[2]) == CONST_INT && !add_operand (operands[2], SImode))
869 {
870 rtx tmp = ((reload_in_progress || reload_completed
871 || rtx_equal_p (operands[0], operands[1]))
872 ? operands[0] : gen_reg_rtx (SImode));
874 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
875 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
877 if (low & 0x8000)
878 high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
880 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (high)));
881 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
882 DONE;
883 }
884 }")
886 (define_insn "*addsi3_internal1"
887 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
888 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
889 (match_operand:SI 2 "add_operand" "r,I,I,J")))]
890 ""
891 "@
892 {cax|add} %0,%1,%2
893 {cal %0,%2(%1)|addi %0,%1,%2}
894 {ai|addic} %0,%1,%2
895 {cau|addis} %0,%1,%v2"
896 [(set_attr "length" "4,4,4,4")])
898 (define_insn "*addsi3_internal2"
899 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
900 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
901 (match_operand:SI 2 "reg_or_short_operand" "r,I"))
902 (const_int 0)))
903 (clobber (match_scratch:SI 3 "=r,r"))]
904 ""
905 "@
906 {cax.|add.} %3,%1,%2
907 {ai.|addic.} %3,%1,%2"
908 [(set_attr "type" "compare")])
910 (define_insn "*addsi3_internal3"
911 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
912 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
913 (match_operand:SI 2 "reg_or_short_operand" "r,I"))
914 (const_int 0)))
915 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
916 (plus:SI (match_dup 1) (match_dup 2)))]
917 ""
918 "@
919 {cax.|add.} %0,%1,%2
920 {ai.|addic.} %0,%1,%2"
921 [(set_attr "type" "compare")])
923 ;; Split an add that we can't do in one insn into two insns, each of which
924 ;; does one 16-bit part. This is used by combine. Note that the low-order
925 ;; add should be last in case the result gets used in an address.
927 (define_split
928 [(set (match_operand:SI 0 "gpc_reg_operand" "")
929 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
930 (match_operand:SI 2 "non_add_cint_operand" "")))]
931 ""
932 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
933 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
934 "
935 {
936 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
937 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
939 if (low & 0x8000)
940 high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
942 operands[3] = GEN_INT (high);
943 operands[4] = GEN_INT (low);
944 }")
946 (define_insn "one_cmplsi2"
947 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
948 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
949 ""
950 "nor %0,%1,%1")
952 (define_insn ""
953 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
954 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
955 (const_int 0)))
956 (clobber (match_scratch:SI 2 "=r"))]
957 ""
958 "nor. %2,%1,%1"
959 [(set_attr "type" "compare")])
961 (define_insn ""
962 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
963 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
964 (const_int 0)))
965 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
966 (not:SI (match_dup 1)))]
967 ""
968 "nor. %0,%1,%1"
969 [(set_attr "type" "compare")])
971 (define_insn ""
972 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
973 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
974 (match_operand:SI 2 "gpc_reg_operand" "r")))]
975 "! TARGET_POWERPC"
976 "{sf%I1|subf%I1c} %0,%2,%1")
978 (define_insn ""
979 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
980 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
981 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
982 "TARGET_POWERPC"
983 "@
984 subf %0,%2,%1
985 subfic %0,%2,%1")
987 (define_insn ""
988 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
989 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
990 (match_operand:SI 2 "gpc_reg_operand" "r"))
991 (const_int 0)))
992 (clobber (match_scratch:SI 3 "=r"))]
993 "! TARGET_POWERPC"
994 "{sf.|subfc.} %3,%2,%1"
995 [(set_attr "type" "compare")])
997 (define_insn ""
998 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
999 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1000 (match_operand:SI 2 "gpc_reg_operand" "r"))
1001 (const_int 0)))
1002 (clobber (match_scratch:SI 3 "=r"))]
1003 "TARGET_POWERPC"
1004 "subf. %3,%2,%1"
1005 [(set_attr "type" "compare")])
1007 (define_insn ""
1008 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1009 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1010 (match_operand:SI 2 "gpc_reg_operand" "r"))
1011 (const_int 0)))
1012 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1013 (minus:SI (match_dup 1) (match_dup 2)))]
1014 "! TARGET_POWERPC"
1015 "{sf.|subfc.} %0,%2,%1"
1016 [(set_attr "type" "compare")])
1018 (define_insn ""
1019 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1020 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1021 (match_operand:SI 2 "gpc_reg_operand" "r"))
1022 (const_int 0)))
1023 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1024 (minus:SI (match_dup 1) (match_dup 2)))]
1025 "TARGET_POWERPC"
1026 "subf. %0,%2,%1"
1027 [(set_attr "type" "compare")])
1029 (define_expand "subsi3"
1030 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1031 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1032 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1033 ""
1034 "
1035 {
1036 if (GET_CODE (operands[2]) == CONST_INT)
1037 {
1038 emit_insn (gen_addsi3 (operands[0], operands[1],
1039 negate_rtx (SImode, operands[2])));
1040 DONE;
1041 }
1042 }")
1044 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1045 ;; instruction and some auxiliary computations. Then we just have a single
1046 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1047 ;; combine.
1049 (define_expand "sminsi3"
1050 [(set (match_dup 3)
1051 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1052 (match_operand:SI 2 "reg_or_short_operand" ""))
1053 (const_int 0)
1054 (minus:SI (match_dup 2) (match_dup 1))))
1055 (set (match_operand:SI 0 "gpc_reg_operand" "")
1056 (minus:SI (match_dup 2) (match_dup 3)))]
1057 "TARGET_POWER"
1058 "
1059 { operands[3] = gen_reg_rtx (SImode); }")
1061 (define_split
1062 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1063 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1064 (match_operand:SI 2 "reg_or_short_operand" "")))
1065 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1066 "TARGET_POWER"
1067 [(set (match_dup 3)
1068 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1069 (const_int 0)
1070 (minus:SI (match_dup 2) (match_dup 1))))
1071 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1072 "")
1074 (define_expand "smaxsi3"
1075 [(set (match_dup 3)
1076 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1077 (match_operand:SI 2 "reg_or_short_operand" ""))
1078 (const_int 0)
1079 (minus:SI (match_dup 2) (match_dup 1))))
1080 (set (match_operand:SI 0 "gpc_reg_operand" "")
1081 (plus:SI (match_dup 3) (match_dup 1)))]
1082 "TARGET_POWER"
1083 "
1084 { operands[3] = gen_reg_rtx (SImode); }")
1086 (define_split
1087 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1088 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1089 (match_operand:SI 2 "reg_or_short_operand" "")))
1090 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1091 "TARGET_POWER"
1092 [(set (match_dup 3)
1093 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1094 (const_int 0)
1095 (minus:SI (match_dup 2) (match_dup 1))))
1096 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1097 "")
1099 (define_expand "uminsi3"
1100 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1101 (match_dup 5)))
1102 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1103 (match_dup 5)))
1104 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1105 (const_int 0)
1106 (minus:SI (match_dup 4) (match_dup 3))))
1107 (set (match_operand:SI 0 "gpc_reg_operand" "")
1108 (minus:SI (match_dup 2) (match_dup 3)))]
1109 "TARGET_POWER"
1110 "
1111 {
1112 operands[3] = gen_reg_rtx (SImode);
1113 operands[4] = gen_reg_rtx (SImode);
1114 operands[5] = GEN_INT (-2147483647 - 1);
1115 }")
1117 (define_expand "umaxsi3"
1118 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1119 (match_dup 5)))
1120 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1121 (match_dup 5)))
1122 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1123 (const_int 0)
1124 (minus:SI (match_dup 4) (match_dup 3))))
1125 (set (match_operand:SI 0 "gpc_reg_operand" "")
1126 (plus:SI (match_dup 3) (match_dup 1)))]
1127 "TARGET_POWER"
1128 "
1129 {
1130 operands[3] = gen_reg_rtx (SImode);
1131 operands[4] = gen_reg_rtx (SImode);
1132 operands[5] = GEN_INT (-2147483647 - 1);
1133 }")
1135 (define_insn ""
1136 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1137 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1138 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1139 (const_int 0)
1140 (minus:SI (match_dup 2) (match_dup 1))))]
1141 "TARGET_POWER"
1142 "doz%I2 %0,%1,%2")
1144 (define_insn ""
1145 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1146 (compare:CC
1147 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1148 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1149 (const_int 0)
1150 (minus:SI (match_dup 2) (match_dup 1)))
1151 (const_int 0)))
1152 (clobber (match_scratch:SI 3 "=r"))]
1153 "TARGET_POWER"
1154 "doz%I2. %3,%1,%2"
1155 [(set_attr "type" "delayed_compare")])
1157 (define_insn ""
1158 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1159 (compare:CC
1160 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1161 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1162 (const_int 0)
1163 (minus:SI (match_dup 2) (match_dup 1)))
1164 (const_int 0)))
1165 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1166 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1167 (const_int 0)
1168 (minus:SI (match_dup 2) (match_dup 1))))]
1169 "TARGET_POWER"
1170 "doz%I2. %0,%1,%2"
1171 [(set_attr "type" "delayed_compare")])
1173 ;; We don't need abs with condition code because such comparisons should
1174 ;; never be done.
1175 (define_expand "abssi2"
1176 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1177 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1178 ""
1179 "
1180 {
1181 if (!TARGET_POWER)
1182 {
1183 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1184 DONE;
1185 }
1186 }")
1188 (define_insn "abssi2_power"
1189 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1190 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1191 "TARGET_POWER"
1192 "abs %0,%1")
1194 (define_insn "abssi2_nopower"
1195 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1196 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1197 (clobber (match_scratch:SI 2 "=&r,&r"))]
1198 "!TARGET_POWER"
1199 "*
1200 {
1201 return (TARGET_POWERPC)
1202 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\"
1203 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\";
1204 }"
1205 [(set_attr "length" "12")])
1207 (define_split
1208 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1209 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1210 (clobber (match_scratch:SI 2 "=&r,&r"))]
1211 "!TARGET_POWER && reload_completed"
1212 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1213 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1214 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1215 "")
1217 (define_insn ""
1218 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1219 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1220 "TARGET_POWER"
1221 "nabs %0,%1")
1223 (define_insn ""
1224 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1225 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1226 (clobber (match_scratch:SI 2 "=&r,&r"))]
1227 "!TARGET_POWER"
1228 "*
1229 {
1230 return (TARGET_POWERPC)
1231 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\"
1232 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\";
1233 }"
1234 [(set_attr "length" "12")])
1236 (define_split
1237 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1238 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1239 (clobber (match_scratch:SI 2 "=&r,&r"))]
1240 "!TARGET_POWER && reload_completed"
1241 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1242 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1243 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1244 "")
1246 (define_insn "negsi2"
1247 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1248 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1249 ""
1250 "neg %0,%1")
1252 (define_insn ""
1253 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1254 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1255 (const_int 0)))
1256 (clobber (match_scratch:SI 2 "=r"))]
1257 ""
1258 "neg. %2,%1"
1259 [(set_attr "type" "compare")])
1261 (define_insn ""
1262 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
1263 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1264 (const_int 0)))
1265 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1266 (neg:SI (match_dup 1)))]
1267 ""
1268 "neg. %0,%1"
1269 [(set_attr "type" "compare")])
1271 (define_insn "ffssi2"
1272 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
1273 (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1274 ""
1275 "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32"
1276 [(set_attr "length" "16")])
1278 (define_expand "mulsi3"
1279 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1280 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1281 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1282 ""
1283 "
1284 {
1285 if (TARGET_POWER)
1286 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1287 else
1288 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1289 DONE;
1290 }")
1292 (define_insn "mulsi3_mq"
1293 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1294 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1295 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1296 (clobber (match_scratch:SI 3 "=q,q"))]
1297 "TARGET_POWER"
1298 "@
1299 {muls|mullw} %0,%1,%2
1300 {muli|mulli} %0,%1,%2"
1301 [(set_attr "type" "imul")])
1303 (define_insn "mulsi3_no_mq"
1304 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1305 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1306 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1307 "! TARGET_POWER"
1308 "@
1309 {muls|mullw} %0,%1,%2
1310 {muli|mulli} %0,%1,%2"
1311 [(set_attr "type" "imul")])
1313 (define_insn ""
1314 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1315 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1316 (match_operand:SI 2 "gpc_reg_operand" "r"))
1317 (const_int 0)))
1318 (clobber (match_scratch:SI 3 "=r"))
1319 (clobber (match_scratch:SI 4 "=q"))]
1320 "TARGET_POWER"
1321 "{muls.|mullw.} %3,%1,%2"
1322 [(set_attr "type" "delayed_compare")])
1324 (define_insn ""
1325 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1326 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1327 (match_operand:SI 2 "gpc_reg_operand" "r"))
1328 (const_int 0)))
1329 (clobber (match_scratch:SI 3 "=r"))]
1330 "! TARGET_POWER"
1331 "{muls.|mullw.} %3,%1,%2"
1332 [(set_attr "type" "delayed_compare")])
1334 (define_insn ""
1335 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1336 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1337 (match_operand:SI 2 "gpc_reg_operand" "r"))
1338 (const_int 0)))
1339 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1340 (mult:SI (match_dup 1) (match_dup 2)))
1341 (clobber (match_scratch:SI 4 "=q"))]
1342 "TARGET_POWER"
1343 "{muls.|mullw.} %0,%1,%2"
1344 [(set_attr "type" "delayed_compare")])
1346 (define_insn ""
1347 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1348 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1349 (match_operand:SI 2 "gpc_reg_operand" "r"))
1350 (const_int 0)))
1351 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1352 (mult:SI (match_dup 1) (match_dup 2)))]
1353 "! TARGET_POWER"
1354 "{muls.|mullw.} %0,%1,%2"
1355 [(set_attr "type" "delayed_compare")])
1357 ;; Operand 1 is divided by operand 2; quotient goes to operand
1358 ;; 0 and remainder to operand 3.
1359 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1361 (define_expand "divmodsi4"
1362 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1363 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1364 (match_operand:SI 2 "gpc_reg_operand" "")))
1365 (set (match_operand:SI 3 "gpc_reg_operand" "")
1366 (mod:SI (match_dup 1) (match_dup 2)))])]
1367 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1368 "
1369 {
1370 if (! TARGET_POWER && ! TARGET_POWERPC)
1371 {
1372 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
1373 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
1374 emit_insn (gen_divss_call ());
1375 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
1376 emit_move_insn (operands[3], gen_rtx (REG, SImode, 4));
1377 DONE;
1378 }
1379 }")
1381 (define_insn ""
1382 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1383 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1384 (match_operand:SI 2 "gpc_reg_operand" "r")))
1385 (set (match_operand:SI 3 "gpc_reg_operand" "=q")
1386 (mod:SI (match_dup 1) (match_dup 2)))]
1387 "TARGET_POWER"
1388 "divs %0,%1,%2"
1389 [(set_attr "type" "idiv")])
1391 (define_expand "udivsi3"
1392 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1393 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1394 (match_operand:SI 2 "gpc_reg_operand" "")))]
1395 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1396 "
1397 {
1398 if (! TARGET_POWER && ! TARGET_POWERPC)
1399 {
1400 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
1401 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
1402 emit_insn (gen_quous_call ());
1403 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
1404 DONE;
1405 }
1406 else if (TARGET_POWER)
1407 {
1408 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1409 DONE;
1410 }
1411 }")
1413 (define_insn "udivsi3_mq"
1414 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1415 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1416 (match_operand:SI 2 "gpc_reg_operand" "r")))
1417 (clobber (match_scratch:SI 3 "=q"))]
1418 "TARGET_POWERPC && TARGET_POWER"
1419 "divwu %0,%1,%2"
1420 [(set_attr "type" "idiv")])
1422 (define_insn "*udivsi3_no_mq"
1423 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1424 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1425 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1426 "TARGET_POWERPC && ! TARGET_POWER"
1427 "divwu %0,%1,%2"
1428 [(set_attr "type" "idiv")])
1430 ;; For powers of two we can do srai/aze for divide and then adjust for
1431 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1432 ;; used; for PowerPC, force operands into register and do a normal divide;
1433 ;; for AIX common-mode, use quoss call on register operands.
1434 (define_expand "divsi3"
1435 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1436 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1437 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1438 ""
1439 "
1440 {
1441 if (GET_CODE (operands[2]) == CONST_INT
1442 && exact_log2 (INTVAL (operands[2])) >= 0)
1443 ;
1444 else if (TARGET_POWERPC)
1445 {
1446 operands[2] = force_reg (SImode, operands[2]);
1447 if (TARGET_POWER)
1448 {
1449 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1450 DONE;
1451 }
1452 }
1453 else if (TARGET_POWER)
1454 FAIL;
1455 else
1456 {
1457 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
1458 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
1459 emit_insn (gen_quoss_call ());
1460 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
1461 DONE;
1462 }
1463 }")
1465 (define_insn "divsi3_mq"
1466 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1467 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1468 (match_operand:SI 2 "gpc_reg_operand" "r")))
1469 (clobber (match_scratch:SI 3 "=q"))]
1470 "TARGET_POWERPC && TARGET_POWER"
1471 "divw %0,%1,%2"
1472 [(set_attr "type" "idiv")])
1474 (define_insn "*divsi3_no_mq"
1475 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1476 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1477 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1478 "TARGET_POWERPC && ! TARGET_POWER"
1479 "divw %0,%1,%2"
1480 [(set_attr "type" "idiv")])
1482 (define_expand "modsi3"
1483 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1484 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1485 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1486 ""
1487 "
1488 {
1489 int i = exact_log2 (INTVAL (operands[2]));
1490 rtx temp1;
1491 rtx temp2;
1493 if (GET_CODE (operands[2]) != CONST_INT || i < 0)
1494 FAIL;
1496 temp1 = gen_reg_rtx (SImode);
1497 temp2 = gen_reg_rtx (SImode);
1499 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
1500 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1501 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1502 DONE;
1503 }")
1505 (define_insn ""
1506 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1507 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1508 (match_operand:SI 2 "const_int_operand" "N")))]
1509 "exact_log2 (INTVAL (operands[2])) >= 0"
1510 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
1511 [(set_attr "length" "8")])
1513 (define_insn ""
1514 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1515 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1516 (match_operand:SI 2 "const_int_operand" "N"))
1517 (const_int 0)))
1518 (clobber (match_scratch:SI 3 "=r"))]
1519 "exact_log2 (INTVAL (operands[2])) >= 0"
1520 "{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3"
1521 [(set_attr "type" "compare")
1522 (set_attr "length" "8")])
1524 (define_insn ""
1525 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1526 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1527 (match_operand:SI 2 "const_int_operand" "N"))
1528 (const_int 0)))
1529 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1530 (div:SI (match_dup 1) (match_dup 2)))]
1531 "exact_log2 (INTVAL (operands[2])) >= 0"
1532 "{srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0"
1533 [(set_attr "type" "compare")
1534 (set_attr "length" "8")])
1536 (define_insn ""
1537 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1538 (udiv:SI
1539 (plus:DI (ashift:DI
1540 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1541 (const_int 32))
1542 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
1543 (match_operand:SI 3 "gpc_reg_operand" "r")))
1544 (set (match_operand:SI 2 "register_operand" "=*q")
1545 (umod:SI
1546 (plus:DI (ashift:DI
1547 (zero_extend:DI (match_dup 1)) (const_int 32))
1548 (zero_extend:DI (match_dup 4)))
1549 (match_dup 3)))]
1550 "TARGET_POWER"
1551 "div %0,%1,%3"
1552 [(set_attr "type" "idiv")])
1554 ;; To do unsigned divide we handle the cases of the divisor looking like a
1555 ;; negative number. If it is a constant that is less than 2**31, we don't
1556 ;; have to worry about the branches. So make a few subroutines here.
1557 ;;
1558 ;; First comes the normal case.
1559 (define_expand "udivmodsi4_normal"
1560 [(set (match_dup 4) (const_int 0))
1561 (parallel [(set (match_operand:SI 0 "" "")
1562 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1563 (const_int 32))
1564 (zero_extend:DI (match_operand:SI 1 "" "")))
1565 (match_operand:SI 2 "" "")))
1566 (set (match_operand:SI 3 "" "")
1567 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1568 (const_int 32))
1569 (zero_extend:DI (match_dup 1)))
1570 (match_dup 2)))])]
1571 "TARGET_POWER"
1572 "
1573 { operands[4] = gen_reg_rtx (SImode); }")
1575 ;; This handles the branches.
1576 (define_expand "udivmodsi4_tests"
1577 [(set (match_operand:SI 0 "" "") (const_int 0))
1578 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
1579 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
1580 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
1581 (label_ref (match_operand:SI 4 "" "")) (pc)))
1582 (set (match_dup 0) (const_int 1))
1583 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
1584 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
1585 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
1586 (label_ref (match_dup 4)) (pc)))]
1587 "TARGET_POWER"
1588 "
1589 { operands[5] = gen_reg_rtx (CCUNSmode);
1590 operands[6] = gen_reg_rtx (CCmode);
1591 }")
1593 (define_expand "udivmodsi4"
1594 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1595 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1596 (match_operand:SI 2 "reg_or_cint_operand" "")))
1597 (set (match_operand:SI 3 "gpc_reg_operand" "")
1598 (umod:SI (match_dup 1) (match_dup 2)))])]
1599 ""
1600 "
1601 {
1602 rtx label = 0;
1604 if (! TARGET_POWER)
1605 if (! TARGET_POWERPC)
1606 {
1607 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
1608 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
1609 emit_insn (gen_divus_call ());
1610 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
1611 emit_move_insn (operands[3], gen_rtx (REG, SImode, 4));
1612 DONE;
1613 }
1614 else
1615 FAIL;
1617 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
1618 {
1619 operands[2] = force_reg (SImode, operands[2]);
1620 label = gen_label_rtx ();
1621 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
1622 operands[3], label));
1623 }
1624 else
1625 operands[2] = force_reg (SImode, operands[2]);
1627 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
1628 operands[3]));
1629 if (label)
1630 emit_label (label);
1632 DONE;
1633 }")
1635 ;; AIX architecture-independent common-mode multiply (DImode),
1636 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
1637 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
1638 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
1639 ;; assumed unused if generating common-mode, so ignore.
1640 (define_insn "mulh_call"
1641 [(set (reg:SI 3)
1642 (truncate:SI
1643 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
1644 (sign_extend:DI (reg:SI 4)))
1645 (const_int 32))))
1646 (clobber (match_scratch:SI 0 "=l"))]
1647 "! TARGET_POWER && ! TARGET_POWERPC"
1648 "bla __mulh"
1649 [(set_attr "type" "imul")])
1651 (define_insn "mull_call"
1652 [(set (reg:DI 3)
1653 (mult:DI (sign_extend:DI (reg:SI 3))
1654 (sign_extend:DI (reg:SI 4))))
1655 (clobber (match_scratch:SI 0 "=l"))
1656 (clobber (reg:SI 0))]
1657 "! TARGET_POWER && ! TARGET_POWERPC"
1658 "bla __mull"
1659 [(set_attr "type" "imul")])
1661 (define_insn "divss_call"
1662 [(set (reg:SI 3)
1663 (div:SI (reg:SI 3) (reg:SI 4)))
1664 (set (reg:SI 4)
1665 (mod:SI (reg:SI 3) (reg:SI 4)))
1666 (clobber (match_scratch:SI 0 "=l"))
1667 (clobber (reg:SI 0))]
1668 "! TARGET_POWER && ! TARGET_POWERPC"
1669 "bla __divss"
1670 [(set_attr "type" "idiv")])
1672 (define_insn "divus_call"
1673 [(set (reg:SI 3)
1674 (udiv:SI (reg:SI 3) (reg:SI 4)))
1675 (set (reg:SI 4)
1676 (umod:SI (reg:SI 3) (reg:SI 4)))
1677 (clobber (match_scratch:SI 0 "=l"))
1678 (clobber (reg:SI 0))
1679 (clobber (match_scratch:CC 1 "=x"))
1680 (clobber (reg:CC 69))]
1681 "! TARGET_POWER && ! TARGET_POWERPC"
1682 "bla __divus"
1683 [(set_attr "type" "idiv")])
1685 (define_insn "quoss_call"
1686 [(set (reg:SI 3)
1687 (div:SI (reg:SI 3) (reg:SI 4)))
1688 (clobber (match_scratch:SI 0 "=l"))]
1689 "! TARGET_POWER && ! TARGET_POWERPC"
1690 "bla __quoss"
1691 [(set_attr "type" "idiv")])
1693 (define_insn "quous_call"
1694 [(set (reg:SI 3)
1695 (udiv:SI (reg:SI 3) (reg:SI 4)))
1696 (clobber (match_scratch:SI 0 "=l"))
1697 (clobber (reg:SI 0))
1698 (clobber (match_scratch:CC 1 "=x"))
1699 (clobber (reg:CC 69))]
1700 "! TARGET_POWER && ! TARGET_POWERPC"
1701 "bla __quous"
1702 [(set_attr "type" "idiv")])
1703 \f
1704 ;; Logical instructions
1705 (define_insn "andsi3"
1706 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1707 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1708 (match_operand:SI 2 "and_operand" "?r,L,K,J")))
1709 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
1710 ""
1711 "@
1712 and %0,%1,%2
1713 {rlinm|rlwinm} %0,%1,0,%m2,%M2
1714 {andil.|andi.} %0,%1,%b2
1715 {andiu.|andis.} %0,%1,%u2"
1716 [(set_attr "length" "4,4,4,4")])
1718 (define_insn "*andsi3_internal2"
1719 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
1720 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1721 (match_operand:SI 2 "and_operand" "r,K,J,L"))
1722 (const_int 0)))
1723 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1724 ""
1725 "@
1726 and. %3,%1,%2
1727 {andil.|andi.} %3,%1,%b2
1728 {andiu.|andis.} %3,%1,%u2
1729 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2"
1730 [(set_attr "type" "compare,compare,compare,delayed_compare")])
1732 (define_insn "*andsi3_internal3"
1733 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x")
1734 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1735 (match_operand:SI 2 "and_operand" "r,K,J,L"))
1736 (const_int 0)))
1737 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1738 (and:SI (match_dup 1) (match_dup 2)))]
1739 ""
1740 "@
1741 and. %0,%1,%2
1742 {andil.|andi.} %0,%1,%b2
1743 {andiu.|andis.} %0,%1,%u2
1744 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2"
1745 [(set_attr "type" "compare,compare,compare,delayed_compare")])
1747 (define_expand "iorsi3"
1748 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1749 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
1750 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1751 ""
1752 "
1753 {
1754 if (GET_CODE (operands[2]) == CONST_INT
1755 && !logical_operand (operands[2], SImode))
1756 {
1757 HOST_WIDE_INT value = INTVAL (operands[2]);
1758 rtx tmp = ((reload_in_progress || reload_completed
1759 || rtx_equal_p (operands[0], operands[1]))
1760 ? operands[0] : gen_reg_rtx (SImode));
1762 emit_insn (gen_iorsi3 (tmp, operands[1], GEN_INT (value & 0xffff0000)));
1763 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0x0000ffff)));
1764 DONE;
1765 }
1766 }")
1768 (define_insn "*iorsi3_internal1"
1769 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1770 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
1771 (match_operand:SI 2 "logical_operand" "r,K,J")))]
1772 ""
1773 "@
1774 or %0,%1,%2
1775 {oril|ori} %0,%1,%b2
1776 {oriu|oris} %0,%1,%u2"
1777 [(set_attr "length" "4,4,4")])
1779 (define_insn "*iorsi3_internal2"
1780 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1781 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1782 (match_operand:SI 2 "gpc_reg_operand" "r"))
1783 (const_int 0)))
1784 (clobber (match_scratch:SI 3 "=r"))]
1785 ""
1786 "or. %3,%1,%2"
1787 [(set_attr "type" "compare")])
1789 (define_insn "*iorsi3_internal3"
1790 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1791 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1792 (match_operand:SI 2 "gpc_reg_operand" "r"))
1793 (const_int 0)))
1794 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1795 (ior:SI (match_dup 1) (match_dup 2)))]
1796 ""
1797 "or. %0,%1,%2"
1798 [(set_attr "type" "compare")])
1800 (define_expand "xorsi3"
1801 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1802 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1803 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1804 ""
1805 "
1806 {
1807 if (GET_CODE (operands[2]) == CONST_INT
1808 && !logical_operand (operands[2], SImode))
1809 {
1810 HOST_WIDE_INT value = INTVAL (operands[2]);
1811 rtx tmp = ((reload_in_progress || reload_completed
1812 || rtx_equal_p (operands[0], operands[1]))
1813 ? operands[0] : gen_reg_rtx (SImode));
1815 emit_insn (gen_xorsi3 (tmp, operands[1], GEN_INT (value & 0xffff0000)));
1816 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0x0000ffff)));
1817 DONE;
1818 }
1819 }")
1821 (define_insn "*xorsi3_internal1"
1822 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1823 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
1824 (match_operand:SI 2 "logical_operand" "r,K,J")))]
1825 ""
1826 "@
1827 xor %0,%1,%2
1828 {xoril|xori} %0,%1,%b2
1829 {xoriu|xoris} %0,%1,%u2"
1830 [(set_attr "length" "4,4,4")])
1832 (define_insn "*xorsi3_internal2"
1833 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1834 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1835 (match_operand:SI 2 "gpc_reg_operand" "r"))
1836 (const_int 0)))
1837 (clobber (match_scratch:SI 3 "=r"))]
1838 ""
1839 "xor. %3,%1,%2"
1840 [(set_attr "type" "compare")])
1842 (define_insn "*xorsi3_internal3"
1843 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1844 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1845 (match_operand:SI 2 "gpc_reg_operand" "r"))
1846 (const_int 0)))
1847 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1848 (xor:SI (match_dup 1) (match_dup 2)))]
1849 ""
1850 "xor. %0,%1,%2"
1851 [(set_attr "type" "compare")])
1853 (define_insn "*eqv_internal1"
1854 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1855 (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1856 (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1857 ""
1858 "eqv %0,%1,%2")
1860 (define_insn "*eqv_internal2"
1861 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1862 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1863 (match_operand:SI 2 "gpc_reg_operand" "r")))
1864 (const_int 0)))
1865 (clobber (match_scratch:SI 3 "=r"))]
1866 ""
1867 "eqv. %3,%1,%2"
1868 [(set_attr "type" "compare")])
1870 (define_insn "*eqv_internal3"
1871 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1872 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1873 (match_operand:SI 2 "gpc_reg_operand" "r")))
1874 (const_int 0)))
1875 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1876 (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
1877 ""
1878 "eqv. %0,%1,%2"
1879 [(set_attr "type" "compare")])
1881 (define_insn "*andc_internal1"
1882 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1883 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1884 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1885 ""
1886 "andc %0,%2,%1")
1888 (define_insn "*andc_internal2"
1889 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1890 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1891 (match_operand:SI 2 "gpc_reg_operand" "r"))
1892 (const_int 0)))
1893 (clobber (match_scratch:SI 3 "=r"))]
1894 ""
1895 "andc. %3,%2,%1"
1896 [(set_attr "type" "compare")])
1898 (define_insn "*andc_internal3"
1899 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1900 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1901 (match_operand:SI 2 "gpc_reg_operand" "r"))
1902 (const_int 0)))
1903 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1904 (and:SI (not:SI (match_dup 1)) (match_dup 2)))]
1905 ""
1906 "andc. %0,%2,%1"
1907 [(set_attr "type" "compare")])
1909 (define_insn "*iorc_internal1"
1910 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1911 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1912 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1913 ""
1914 "orc %0,%2,%1")
1916 (define_insn "*iorc_internal2"
1917 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1918 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1919 (match_operand:SI 2 "gpc_reg_operand" "r"))
1920 (const_int 0)))
1921 (clobber (match_scratch:SI 3 "=r"))]
1922 ""
1923 "orc. %3,%2,%1"
1924 [(set_attr "type" "compare")])
1926 (define_insn "*iorc_internal3"
1927 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1928 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1929 (match_operand:SI 2 "gpc_reg_operand" "r"))
1930 (const_int 0)))
1931 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1932 (ior:SI (not:SI (match_dup 1)) (match_dup 2)))]
1933 ""
1934 "orc. %0,%2,%1"
1935 [(set_attr "type" "compare")])
1937 (define_insn "*nand_internal1"
1938 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1939 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1940 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1941 ""
1942 "nand %0,%1,%2")
1944 (define_insn "*nand_internal2"
1945 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1946 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1947 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1948 (const_int 0)))
1949 (clobber (match_scratch:SI 3 "=r"))]
1950 ""
1951 "nand. %3,%1,%2"
1952 [(set_attr "type" "compare")])
1954 (define_insn "*nand_internal3"
1955 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1956 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1957 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1958 (const_int 0)))
1959 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1960 (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
1961 ""
1962 "nand. %0,%1,%2"
1963 [(set_attr "type" "compare")])
1965 (define_insn "*nor_internal1"
1966 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1967 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1968 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1969 ""
1970 "nor %0,%1,%2")
1972 (define_insn "*nor_internal2"
1973 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1974 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1975 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1976 (const_int 0)))
1977 (clobber (match_scratch:SI 3 "=r"))]
1978 ""
1979 "nor. %3,%1,%2"
1980 [(set_attr "type" "compare")])
1982 (define_insn "*nor_internal3"
1983 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1984 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1985 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1986 (const_int 0)))
1987 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1988 (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
1989 ""
1990 "nor. %0,%1,%2"
1991 [(set_attr "type" "compare")])
1993 ;; maskir insn. We need four forms because things might be in arbitrary
1994 ;; orders. Don't define forms that only set CR fields because these
1995 ;; would modify an input register.
1997 (define_insn "*maskir_internal1"
1998 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1999 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2000 (match_operand:SI 1 "gpc_reg_operand" "0"))
2001 (and:SI (match_dup 2)
2002 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2003 "TARGET_POWER"
2004 "maskir %0,%3,%2")
2006 (define_insn "*maskir_internal2"
2007 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2008 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2009 (match_operand:SI 1 "gpc_reg_operand" "0"))
2010 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2011 (match_dup 2))))]
2012 "TARGET_POWER"
2013 "maskir %0,%3,%2")
2015 (define_insn "*maskir_internal3"
2016 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2017 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2018 (match_operand:SI 3 "gpc_reg_operand" "r"))
2019 (and:SI (not:SI (match_dup 2))
2020 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2021 "TARGET_POWER"
2022 "maskir %0,%3,%2")
2024 (define_insn "*maskir_internal4"
2025 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2026 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2027 (match_operand:SI 2 "gpc_reg_operand" "r"))
2028 (and:SI (not:SI (match_dup 2))
2029 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2030 "TARGET_POWER"
2031 "maskir %0,%3,%2")
2033 (define_insn "*maskir_internal5"
2034 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2035 (compare:CC
2036 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2037 (match_operand:SI 1 "gpc_reg_operand" "0"))
2038 (and:SI (match_dup 2)
2039 (match_operand:SI 3 "gpc_reg_operand" "r")))
2040 (const_int 0)))
2041 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2042 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2043 (and:SI (match_dup 2) (match_dup 3))))]
2044 "TARGET_POWER"
2045 "maskir. %0,%3,%2"
2046 [(set_attr "type" "compare")])
2048 (define_insn "*maskir_internal6"
2049 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2050 (compare:CC
2051 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2052 (match_operand:SI 1 "gpc_reg_operand" "0"))
2053 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2054 (match_dup 2)))
2055 (const_int 0)))
2056 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2057 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2058 (and:SI (match_dup 3) (match_dup 2))))]
2059 "TARGET_POWER"
2060 "maskir. %0,%3,%2"
2061 [(set_attr "type" "compare")])
2063 (define_insn "*maskir_internal7"
2064 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2065 (compare:CC
2066 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2067 (match_operand:SI 3 "gpc_reg_operand" "r"))
2068 (and:SI (not:SI (match_dup 2))
2069 (match_operand:SI 1 "gpc_reg_operand" "0")))
2070 (const_int 0)))
2071 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2072 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2073 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2074 "TARGET_POWER"
2075 "maskir. %0,%3,%2"
2076 [(set_attr "type" "compare")])
2078 (define_insn "*maskir_internal8"
2079 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2080 (compare:CC
2081 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2082 (match_operand:SI 2 "gpc_reg_operand" "r"))
2083 (and:SI (not:SI (match_dup 2))
2084 (match_operand:SI 1 "gpc_reg_operand" "0")))
2085 (const_int 0)))
2086 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2087 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2088 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2089 "TARGET_POWER"
2090 "maskir. %0,%3,%2"
2091 [(set_attr "type" "compare")])
2092 \f
2093 ;; Rotate and shift insns, in all their variants. These support shifts,
2094 ;; field inserts and extracts, and various combinations thereof.
2095 (define_expand "insv"
2096 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2097 (match_operand:SI 1 "const_int_operand" "i")
2098 (match_operand:SI 2 "const_int_operand" "i"))
2099 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2100 ""
2101 "
2102 {
2103 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2104 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2105 compiler if the address of the structure is taken later. */
2106 if (GET_CODE (operands[0]) == SUBREG
2107 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2108 FAIL;
2109 }")
2111 (define_insn ""
2112 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2113 (match_operand:SI 1 "const_int_operand" "i")
2114 (match_operand:SI 2 "const_int_operand" "i"))
2115 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2116 ""
2117 "*
2118 {
2119 int start = INTVAL (operands[2]) & 31;
2120 int size = INTVAL (operands[1]) & 31;
2122 operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size);
2123 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
2124 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2125 }")
2127 (define_insn ""
2128 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2129 (match_operand:SI 1 "const_int_operand" "i")
2130 (match_operand:SI 2 "const_int_operand" "i"))
2131 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2132 (match_operand:SI 4 "const_int_operand" "i")))]
2133 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2134 "*
2135 {
2136 int shift = INTVAL (operands[4]) & 31;
2137 int start = INTVAL (operands[2]) & 31;
2138 int size = INTVAL (operands[1]) & 31;
2140 operands[4] = gen_rtx (CONST_INT, VOIDmode, shift - start - size);
2141 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
2142 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2143 }")
2145 (define_insn ""
2146 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2147 (match_operand:SI 1 "const_int_operand" "i")
2148 (match_operand:SI 2 "const_int_operand" "i"))
2149 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2150 (match_operand:SI 4 "const_int_operand" "i")))]
2151 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2152 "*
2153 {
2154 int shift = INTVAL (operands[4]) & 31;
2155 int start = INTVAL (operands[2]) & 31;
2156 int size = INTVAL (operands[1]) & 31;
2158 operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - shift - start - size);
2159 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
2160 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2161 }")
2163 (define_insn ""
2164 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2165 (match_operand:SI 1 "const_int_operand" "i")
2166 (match_operand:SI 2 "const_int_operand" "i"))
2167 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2168 (match_operand:SI 4 "const_int_operand" "i")))]
2169 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2170 "*
2171 {
2172 int shift = INTVAL (operands[4]) & 31;
2173 int start = INTVAL (operands[2]) & 31;
2174 int size = INTVAL (operands[1]) & 31;
2176 operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - shift - start - size);
2177 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
2178 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2179 }")
2181 (define_insn ""
2182 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2183 (match_operand:SI 1 "const_int_operand" "i")
2184 (match_operand:SI 2 "const_int_operand" "i"))
2185 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2186 (match_operand:SI 4 "const_int_operand" "i")
2187 (match_operand:SI 5 "const_int_operand" "i")))]
2188 "INTVAL (operands[4]) >= INTVAL (operands[1])"
2189 "*
2190 {
2191 int extract_start = INTVAL (operands[5]) & 31;
2192 int extract_size = INTVAL (operands[4]) & 31;
2193 int insert_start = INTVAL (operands[2]) & 31;
2194 int insert_size = INTVAL (operands[1]) & 31;
2196 /* Align extract field with insert field */
2197 operands[5] = gen_rtx (CONST_INT, VOIDmode,
2198 extract_start + extract_size - insert_start - insert_size);
2199 operands[1] = gen_rtx (CONST_INT, VOIDmode, insert_start + insert_size - 1);
2200 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
2201 }")
2203 (define_insn ""
2204 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
2205 (match_operand:DI 1 "const_int_operand" "i")
2206 (match_operand:DI 2 "const_int_operand" "i"))
2207 (match_operand:DI 3 "gpc_reg_operand" "r"))]
2208 "TARGET_POWERPC64"
2209 "*
2210 {
2211 int start = INTVAL (operands[2]) & 63;
2212 int size = INTVAL (operands[1]) & 63;
2214 operands[2] = gen_rtx (CONST_INT, VOIDmode, 64 - start - size);
2215 return \"rldimi %0,%3,%H2,%H1\";
2216 }")
2218 (define_expand "extzv"
2219 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2220 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2221 (match_operand:SI 2 "const_int_operand" "i")
2222 (match_operand:SI 3 "const_int_operand" "i")))]
2223 ""
2224 "
2225 {
2226 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2227 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2228 compiler if the address of the structure is taken later. */
2229 if (GET_CODE (operands[0]) == SUBREG
2230 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2231 FAIL;
2232 }")
2234 (define_insn ""
2235 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2236 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2237 (match_operand:SI 2 "const_int_operand" "i")
2238 (match_operand:SI 3 "const_int_operand" "i")))]
2239 ""
2240 "*
2241 {
2242 int start = INTVAL (operands[3]) & 31;
2243 int size = INTVAL (operands[2]) & 31;
2245 if (start + size >= 32)
2246 operands[3] = const0_rtx;
2247 else
2248 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2249 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
2250 }")
2252 (define_insn ""
2253 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2254 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2255 (match_operand:SI 2 "const_int_operand" "i")
2256 (match_operand:SI 3 "const_int_operand" "i"))
2257 (const_int 0)))
2258 (clobber (match_scratch:SI 4 "=r"))]
2259 ""
2260 "*
2261 {
2262 int start = INTVAL (operands[3]) & 31;
2263 int size = INTVAL (operands[2]) & 31;
2265 /* If the bitfield being tested fits in the upper or lower half of a
2266 word, it is possible to use andiu. or andil. to test it. This is
2267 useful because the condition register set-use delay is smaller for
2268 andi[ul]. than for rlinm. This doesn't work when the starting bit
2269 position is 0 because the LT and GT bits may be set wrong. */
2271 if ((start > 0 && start + size <= 16) || start >= 16)
2272 {
2273 operands[3] = gen_rtx (CONST_INT, VOIDmode,
2274 ((1 << (16 - (start & 15)))
2275 - (1 << (16 - (start & 15) - size))));
2276 if (start < 16)
2277 return \"{andiu.|andis.} %4,%1,%3\";
2278 else
2279 return \"{andil.|andi.} %4,%1,%3\";
2280 }
2282 if (start + size >= 32)
2283 operands[3] = const0_rtx;
2284 else
2285 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2286 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
2287 }"
2288 [(set_attr "type" "compare")])
2290 (define_insn ""
2291 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2292 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2293 (match_operand:SI 2 "const_int_operand" "i")
2294 (match_operand:SI 3 "const_int_operand" "i"))
2295 (const_int 0)))
2296 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2297 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
2298 ""
2299 "*
2300 {
2301 int start = INTVAL (operands[3]) & 31;
2302 int size = INTVAL (operands[2]) & 31;
2304 if (start >= 16 && start + size == 32)
2305 {
2306 operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1);
2307 return \"{andil.|andi.} %0,%1,%3\";
2308 }
2310 if (start + size >= 32)
2311 operands[3] = const0_rtx;
2312 else
2313 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2314 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
2315 }"
2316 [(set_attr "type" "delayed_compare")])
2318 (define_insn ""
2319 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2320 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
2321 (match_operand:DI 2 "const_int_operand" "i")
2322 (match_operand:DI 3 "const_int_operand" "i")))]
2323 "TARGET_POWERPC64"
2324 "*
2325 {
2326 int start = INTVAL (operands[3]) & 63;
2327 int size = INTVAL (operands[2]) & 63;
2329 if (start + size >= 64)
2330 operands[3] = const0_rtx;
2331 else
2332 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2333 operands[2] = gen_rtx (CONST_INT, VOIDmode, 64 - size);
2334 return \"rldicl %0,%1,%3,%2\";
2335 }")
2337 (define_insn ""
2338 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
2339 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
2340 (match_operand:DI 2 "const_int_operand" "i")
2341 (match_operand:DI 3 "const_int_operand" "i"))
2342 (const_int 0)))
2343 (clobber (match_scratch:DI 4 "=r"))]
2344 "TARGET_POWERPC64"
2345 "*
2346 {
2347 int start = INTVAL (operands[3]) & 63;
2348 int size = INTVAL (operands[2]) & 63;
2350 if (start + size >= 64)
2351 operands[3] = const0_rtx;
2352 else
2353 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2354 operands[2] = gen_rtx (CONST_INT, VOIDmode, 64 - size);
2355 return \"rldicl. %4,%1,%3,%2\";
2356 }")
2358 (define_insn ""
2359 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
2360 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
2361 (match_operand:DI 2 "const_int_operand" "i")
2362 (match_operand:DI 3 "const_int_operand" "i"))
2363 (const_int 0)))
2364 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
2365 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
2366 "TARGET_POWERPC64"
2367 "*
2368 {
2369 int start = INTVAL (operands[3]) & 63;
2370 int size = INTVAL (operands[2]) & 63;
2372 if (start + size >= 64)
2373 operands[3] = const0_rtx;
2374 else
2375 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2376 operands[2] = gen_rtx (CONST_INT, VOIDmode, 64 - size);
2377 return \"rldicl. %0,%1,%3,%2\";
2378 }")
2380 (define_insn "rotlsi3"
2381 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2382 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2383 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2384 ""
2385 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
2387 (define_insn ""
2388 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2389 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2390 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2391 (const_int 0)))
2392 (clobber (match_scratch:SI 3 "=r"))]
2393 ""
2394 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff"
2395 [(set_attr "type" "delayed_compare")])
2397 (define_insn ""
2398 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2399 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2400 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2401 (const_int 0)))
2402 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2403 (rotate:SI (match_dup 1) (match_dup 2)))]
2404 ""
2405 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff"
2406 [(set_attr "type" "delayed_compare")])
2408 (define_insn ""
2409 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2410 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2411 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2412 (match_operand:SI 3 "mask_operand" "L")))]
2413 ""
2414 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
2416 (define_insn ""
2417 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2418 (compare:CC (and:SI
2419 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2420 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2421 (match_operand:SI 3 "mask_operand" "L"))
2422 (const_int 0)))
2423 (clobber (match_scratch:SI 4 "=r"))]
2424 ""
2425 "{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3"
2426 [(set_attr "type" "delayed_compare")])
2428 (define_insn ""
2429 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2430 (compare:CC (and:SI
2431 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2432 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2433 (match_operand:SI 3 "mask_operand" "L"))
2434 (const_int 0)))
2435 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2436 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
2437 ""
2438 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3"
2439 [(set_attr "type" "delayed_compare")])
2441 (define_insn ""
2442 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2443 (zero_extend:SI
2444 (subreg:QI
2445 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2446 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
2447 ""
2448 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
2450 (define_insn ""
2451 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2452 (compare:CC (zero_extend:SI
2453 (subreg:QI
2454 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2455 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2456 (const_int 0)))
2457 (clobber (match_scratch:SI 3 "=r"))]
2458 ""
2459 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff"
2460 [(set_attr "type" "delayed_compare")])
2462 (define_insn ""
2463 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2464 (compare:CC (zero_extend:SI
2465 (subreg:QI
2466 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2467 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2468 (const_int 0)))
2469 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2470 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
2471 ""
2472 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff"
2473 [(set_attr "type" "delayed_compare")])
2475 (define_insn ""
2476 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2477 (zero_extend:SI
2478 (subreg:HI
2479 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2480 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
2481 ""
2482 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
2484 (define_insn ""
2485 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2486 (compare:CC (zero_extend:SI
2487 (subreg:HI
2488 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2489 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2490 (const_int 0)))
2491 (clobber (match_scratch:SI 3 "=r"))]
2492 ""
2493 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff"
2494 [(set_attr "type" "delayed_compare")])
2496 (define_insn ""
2497 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2498 (compare:CC (zero_extend:SI
2499 (subreg:HI
2500 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2501 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2502 (const_int 0)))
2503 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2504 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
2505 ""
2506 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff"
2507 [(set_attr "type" "delayed_compare")])
2509 ;; Note that we use "sle." instead of "sl." so that we can set
2510 ;; SHIFT_COUNT_TRUNCATED.
2512 (define_expand "ashlsi3"
2513 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2514 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2515 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2516 ""
2517 "
2518 {
2519 if (TARGET_POWER)
2520 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
2521 else
2522 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
2523 DONE;
2524 }")
2526 (define_insn "ashlsi3_power"
2527 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2528 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2529 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
2530 (clobber (match_scratch:SI 3 "=q,X"))]
2531 "TARGET_POWER"
2532 "@
2533 sle %0,%1,%2
2534 {sli|slwi} %0,%1,%h2"
2535 [(set_attr "length" "8")])
2537 (define_insn "ashlsi3_no_power"
2538 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2539 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2540 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2541 "! TARGET_POWER"
2542 "{sl|slw}%I2 %0,%1,%h2"
2543 [(set_attr "length" "8")])
2545 (define_insn ""
2546 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
2547 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2548 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2549 (const_int 0)))
2550 (clobber (match_scratch:SI 3 "=r,r"))
2551 (clobber (match_scratch:SI 4 "=q,X"))]
2552 "TARGET_POWER"
2553 "@
2554 sle. %3,%1,%2
2555 {sli.|slwi.} %3,%1,%h2"
2556 [(set_attr "type" "delayed_compare")])
2558 (define_insn ""
2559 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2560 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2561 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2562 (const_int 0)))
2563 (clobber (match_scratch:SI 3 "=r"))]
2564 "! TARGET_POWER"
2565 "{sl|slw}%I2. %3,%1,%h2"
2566 [(set_attr "type" "delayed_compare")])
2568 (define_insn ""
2569 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
2570 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2571 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2572 (const_int 0)))
2573 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2574 (ashift:SI (match_dup 1) (match_dup 2)))
2575 (clobber (match_scratch:SI 4 "=q,X"))]
2576 "TARGET_POWER"
2577 "@
2578 sle. %0,%1,%2
2579 {sli.|slwi.} %0,%1,%h2"
2580 [(set_attr "type" "delayed_compare")])
2582 (define_insn ""
2583 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2584 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2585 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2586 (const_int 0)))
2587 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2588 (ashift:SI (match_dup 1) (match_dup 2)))]
2589 "! TARGET_POWER"
2590 "{sl|slw}%I2. %0,%1,%h2"
2591 [(set_attr "type" "delayed_compare")])
2593 (define_insn ""
2594 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2595 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2596 (match_operand:SI 2 "const_int_operand" "i"))
2597 (match_operand:SI 3 "mask_operand" "L")))]
2598 "includes_lshift_p (operands[2], operands[3])"
2599 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
2601 (define_insn ""
2602 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2603 (compare:CC
2604 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2605 (match_operand:SI 2 "const_int_operand" "i"))
2606 (match_operand:SI 3 "mask_operand" "L"))
2607 (const_int 0)))
2608 (clobber (match_scratch:SI 4 "=r"))]
2609 "includes_lshift_p (operands[2], operands[3])"
2610 "{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3"
2611 [(set_attr "type" "delayed_compare")])
2613 (define_insn ""
2614 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2615 (compare:CC
2616 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2617 (match_operand:SI 2 "const_int_operand" "i"))
2618 (match_operand:SI 3 "mask_operand" "L"))
2619 (const_int 0)))
2620 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2621 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
2622 "includes_lshift_p (operands[2], operands[3])"
2623 "{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3"
2624 [(set_attr "type" "delayed_compare")])
2626 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
2627 ;; "sli x,x,0".
2628 (define_expand "lshrsi3"
2629 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2630 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2631 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2632 ""
2633 "
2634 {
2635 if (TARGET_POWER)
2636 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
2637 else
2638 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
2639 DONE;
2640 }")
2642 (define_insn "lshrsi3_power"
2643 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2644 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
2645 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
2646 (clobber (match_scratch:SI 3 "=q,X,X"))]
2647 "TARGET_POWER"
2648 "@
2649 sre %0,%1,%2
2650 mr %0,%1
2651 {s%A2i|s%A2wi} %0,%1,%h2")
2653 (define_insn "lshrsi3_no_power"
2654 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2655 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2656 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
2657 "! TARGET_POWER"
2658 "@
2659 mr %0,%1
2660 {sr|srw}%I2 %0,%1,%h2")
2662 (define_insn ""
2663 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x")
2664 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
2665 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))
2666 (const_int 0)))
2667 (clobber (match_scratch:SI 3 "=r,X,r"))
2668 (clobber (match_scratch:SI 4 "=q,X,X"))]
2669 "TARGET_POWER"
2670 "@
2671 sre. %3,%1,%2
2672 mr. %1,%1
2673 {s%A2i.|s%A2wi.} %3,%1,%h2"
2674 [(set_attr "type" "delayed_compare")])
2676 (define_insn ""
2677 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
2678 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2679 (match_operand:SI 2 "reg_or_cint_operand" "O,ri"))
2680 (const_int 0)))
2681 (clobber (match_scratch:SI 3 "=X,r"))]
2682 "! TARGET_POWER"
2683 "@
2684 mr. %1,%1
2685 {sr|srw}%I2. %3,%1,%h2"
2686 [(set_attr "type" "delayed_compare")])
2688 (define_insn ""
2689 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x")
2690 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
2691 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))
2692 (const_int 0)))
2693 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2694 (lshiftrt:SI (match_dup 1) (match_dup 2)))
2695 (clobber (match_scratch:SI 4 "=q,X,X"))]
2696 "TARGET_POWER"
2697 "@
2698 sre. %0,%1,%2
2699 mr. %0,%1
2700 {s%A2i.|s%A2wi.} %0,%1,%h2"
2701 [(set_attr "type" "delayed_compare")])
2703 (define_insn ""
2704 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
2705 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2706 (match_operand:SI 2 "reg_or_cint_operand" "O,ri"))
2707 (const_int 0)))
2708 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2709 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
2710 "! TARGET_POWER"
2711 "@
2712 mr. %0,%1
2713 {sr|srw}%I2. %0,%1,%h2"
2714 [(set_attr "type" "delayed_compare")])
2716 (define_insn ""
2717 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2718 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2719 (match_operand:SI 2 "const_int_operand" "i"))
2720 (match_operand:SI 3 "mask_operand" "L")))]
2721 "includes_rshift_p (operands[2], operands[3])"
2722 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
2724 (define_insn ""
2725 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2726 (compare:CC
2727 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2728 (match_operand:SI 2 "const_int_operand" "i"))
2729 (match_operand:SI 3 "mask_operand" "L"))
2730 (const_int 0)))
2731 (clobber (match_scratch:SI 4 "=r"))]
2732 "includes_rshift_p (operands[2], operands[3])"
2733 "{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3"
2734 [(set_attr "type" "delayed_compare")])
2736 (define_insn ""
2737 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2738 (compare:CC
2739 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2740 (match_operand:SI 2 "const_int_operand" "i"))
2741 (match_operand:SI 3 "mask_operand" "L"))
2742 (const_int 0)))
2743 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2744 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
2745 "includes_rshift_p (operands[2], operands[3])"
2746 "{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3"
2747 [(set_attr "type" "delayed_compare")])
2749 (define_insn ""
2750 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2751 (zero_extend:SI
2752 (subreg:QI
2753 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2754 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
2755 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
2756 "{rlinm|rlwinm} %0,%1,%s2,0xff")
2758 (define_insn ""
2759 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2760 (compare:CC
2761 (zero_extend:SI
2762 (subreg:QI
2763 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2764 (match_operand:SI 2 "const_int_operand" "i")) 0))
2765 (const_int 0)))
2766 (clobber (match_scratch:SI 3 "=r"))]
2767 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
2768 "{rlinm.|rlwinm.} %3,%1,%s2,0xff"
2769 [(set_attr "type" "delayed_compare")])
2771 (define_insn ""
2772 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2773 (compare:CC
2774 (zero_extend:SI
2775 (subreg:QI
2776 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2777 (match_operand:SI 2 "const_int_operand" "i")) 0))
2778 (const_int 0)))
2779 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2780 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
2781 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
2782 "{rlinm.|rlwinm.} %0,%1,%s2,0xff"
2783 [(set_attr "type" "delayed_compare")])
2785 (define_insn ""
2786 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2787 (zero_extend:SI
2788 (subreg:HI
2789 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2790 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
2791 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
2792 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
2794 (define_insn ""
2795 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2796 (compare:CC
2797 (zero_extend:SI
2798 (subreg:HI
2799 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2800 (match_operand:SI 2 "const_int_operand" "i")) 0))
2801 (const_int 0)))
2802 (clobber (match_scratch:SI 3 "=r"))]
2803 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
2804 "{rlinm.|rlwinm.} %3,%1,%s2,0xffff"
2805 [(set_attr "type" "delayed_compare")])
2807 (define_insn ""
2808 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2809 (compare:CC
2810 (zero_extend:SI
2811 (subreg:HI
2812 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2813 (match_operand:SI 2 "const_int_operand" "i")) 0))
2814 (const_int 0)))
2815 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2816 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
2817 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
2818 "{rlinm.|rlwinm.} %0,%1,%s2,0xffff"
2819 [(set_attr "type" "delayed_compare")])
2821 (define_insn ""
2822 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2823 (const_int 1)
2824 (match_operand:SI 1 "gpc_reg_operand" "r"))
2825 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2826 (const_int 31)))]
2827 "TARGET_POWER"
2828 "rrib %0,%1,%2")
2830 (define_insn ""
2831 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2832 (const_int 1)
2833 (match_operand:SI 1 "gpc_reg_operand" "r"))
2834 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2835 (const_int 31)))]
2836 "TARGET_POWER"
2837 "rrib %0,%1,%2")
2839 (define_insn ""
2840 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2841 (const_int 1)
2842 (match_operand:SI 1 "gpc_reg_operand" "r"))
2843 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2844 (const_int 1)
2845 (const_int 0)))]
2846 "TARGET_POWER"
2847 "rrib %0,%1,%2")
2849 (define_expand "ashrsi3"
2850 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2851 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
2852 (match_operand:SI 2 "reg_or_cint_operand" "")))]
2853 ""
2854 "
2855 {
2856 if (TARGET_POWER)
2857 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
2858 else
2859 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
2860 DONE;
2861 }")
2863 (define_insn "ashrsi3_power"
2864 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2865 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2866 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
2867 (clobber (match_scratch:SI 3 "=q,X"))]
2868 "TARGET_POWER"
2869 "@
2870 srea %0,%1,%2
2871 {srai|srawi} %0,%1,%h2")
2873 (define_insn "ashrsi3_no_power"
2874 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2875 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2876 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2877 "! TARGET_POWER"
2878 "{sra|sraw}%I2 %0,%1,%h2")
2880 (define_insn ""
2881 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
2882 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2883 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2884 (const_int 0)))
2885 (clobber (match_scratch:SI 3 "=r,r"))
2886 (clobber (match_scratch:SI 4 "=q,X"))]
2887 "TARGET_POWER"
2888 "@
2889 srea. %3,%1,%2
2890 {srai.|srawi.} %3,%1,%h2"
2891 [(set_attr "type" "delayed_compare")])
2893 (define_insn ""
2894 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2895 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2896 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2897 (const_int 0)))
2898 (clobber (match_scratch:SI 3 "=r"))]
2899 "! TARGET_POWER"
2900 "{sra|sraw}%I2. %3,%1,%h2"
2901 [(set_attr "type" "delayed_compare")])
2903 (define_insn ""
2904 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
2905 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2906 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2907 (const_int 0)))
2908 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2909 (ashiftrt:SI (match_dup 1) (match_dup 2)))
2910 (clobber (match_scratch:SI 4 "=q,X"))]
2911 "TARGET_POWER"
2912 "@
2913 srea. %0,%1,%2
2914 {srai.|srawi.} %0,%1,%h2"
2915 [(set_attr "type" "delayed_compare")])
2917 (define_insn ""
2918 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2919 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2920 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2921 (const_int 0)))
2922 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2923 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
2924 "! TARGET_POWER"
2925 "{sra|sraw}%I2. %0,%1,%h2"
2926 [(set_attr "type" "delayed_compare")])
2927 \f
2928 ;; Floating-point insns, excluding normal data motion.
2929 ;;
2930 ;; PowerPC has a full set of single-precision floating point instructions.
2931 ;;
2932 ;; For the POWER architecture, we pretend that we have both SFmode and
2933 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
2934 ;; The only conversions we will do will be when storing to memory. In that
2935 ;; case, we will use the "frsp" instruction before storing.
2936 ;;
2937 ;; Note that when we store into a single-precision memory location, we need to
2938 ;; use the frsp insn first. If the register being stored isn't dead, we
2939 ;; need a scratch register for the frsp. But this is difficult when the store
2940 ;; is done by reload. It is not incorrect to do the frsp on the register in
2941 ;; this case, we just lose precision that we would have otherwise gotten but
2942 ;; is not guaranteed. Perhaps this should be tightened up at some point.
2944 (define_insn "extendsfdf2"
2945 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
2946 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
2947 "TARGET_HARD_FLOAT"
2948 "*
2949 {
2950 if (REGNO (operands[0]) == REGNO (operands[1]))
2951 return \"\";
2952 else
2953 return \"fmr %0,%1\";
2954 }"
2955 [(set_attr "type" "fp")])
2957 (define_insn "truncdfsf2"
2958 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2959 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
2960 "TARGET_HARD_FLOAT"
2961 "frsp %0,%1"
2962 [(set_attr "type" "fp")])
2964 (define_insn "aux_truncdfsf2"
2965 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2966 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))]
2967 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2968 "frsp %0,%1"
2969 [(set_attr "type" "fp")])
2971 (define_insn "negsf2"
2972 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2973 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
2974 "TARGET_HARD_FLOAT"
2975 "fneg %0,%1"
2976 [(set_attr "type" "fp")])
2978 (define_insn "abssf2"
2979 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2980 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
2981 "TARGET_HARD_FLOAT"
2982 "fabs %0,%1"
2983 [(set_attr "type" "fp")])
2985 (define_insn ""
2986 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2987 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
2988 "TARGET_HARD_FLOAT"
2989 "fnabs %0,%1"
2990 [(set_attr "type" "fp")])
2992 (define_expand "addsf3"
2993 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2994 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
2995 (match_operand:SF 2 "gpc_reg_operand" "")))]
2996 "TARGET_HARD_FLOAT"
2997 "")
2999 (define_insn ""
3000 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3001 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3002 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3003 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3004 "fadds %0,%1,%2"
3005 [(set_attr "type" "fp")])
3007 (define_insn ""
3008 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3009 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3010 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3011 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3012 "{fa|fadd} %0,%1,%2"
3013 [(set_attr "type" "fp")])
3015 (define_expand "subsf3"
3016 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3017 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
3018 (match_operand:SF 2 "gpc_reg_operand" "")))]
3019 "TARGET_HARD_FLOAT"
3020 "")
3022 (define_insn ""
3023 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3024 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
3025 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3026 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3027 "fsubs %0,%1,%2"
3028 [(set_attr "type" "fp")])
3030 (define_insn ""
3031 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3032 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
3033 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3034 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3035 "{fs|fsub} %0,%1,%2"
3036 [(set_attr "type" "fp")])
3038 (define_expand "mulsf3"
3039 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3040 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
3041 (match_operand:SF 2 "gpc_reg_operand" "")))]
3042 "TARGET_HARD_FLOAT"
3043 "")
3045 (define_insn ""
3046 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3047 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3048 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3049 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3050 "fmuls %0,%1,%2"
3051 [(set_attr "type" "fp")])
3053 (define_insn ""
3054 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3055 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3056 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3057 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3058 "{fm|fmul} %0,%1,%2"
3059 [(set_attr "type" "dmul")])
3061 (define_expand "divsf3"
3062 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3063 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
3064 (match_operand:SF 2 "gpc_reg_operand" "")))]
3065 "TARGET_HARD_FLOAT"
3066 "")
3068 (define_insn ""
3069 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3070 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
3071 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3072 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3073 "fdivs %0,%1,%2"
3074 [(set_attr "type" "sdiv")])
3076 (define_insn ""
3077 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3078 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
3079 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3080 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3081 "{fd|fdiv} %0,%1,%2"
3082 [(set_attr "type" "ddiv")])
3084 (define_insn ""
3085 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3086 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3087 (match_operand:SF 2 "gpc_reg_operand" "f"))
3088 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3089 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3090 "fmadds %0,%1,%2,%3"
3091 [(set_attr "type" "fp")])
3093 (define_insn ""
3094 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3095 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3096 (match_operand:SF 2 "gpc_reg_operand" "f"))
3097 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3098 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3099 "{fma|fmadd} %0,%1,%2,%3"
3100 [(set_attr "type" "dmul")])
3102 (define_insn ""
3103 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3104 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3105 (match_operand:SF 2 "gpc_reg_operand" "f"))
3106 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3107 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3108 "fmsubs %0,%1,%2,%3"
3109 [(set_attr "type" "fp")])
3111 (define_insn ""
3112 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3113 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3114 (match_operand:SF 2 "gpc_reg_operand" "f"))
3115 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3116 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3117 "{fms|fmsub} %0,%1,%2,%3"
3118 [(set_attr "type" "dmul")])
3120 (define_insn ""
3121 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3122 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3123 (match_operand:SF 2 "gpc_reg_operand" "f"))
3124 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
3125 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3126 "fnmadds %0,%1,%2,%3"
3127 [(set_attr "type" "fp")])
3129 (define_insn ""
3130 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3131 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3132 (match_operand:SF 2 "gpc_reg_operand" "f"))
3133 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
3134 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3135 "{fnma|fnmadd} %0,%1,%2,%3"
3136 [(set_attr "type" "dmul")])
3138 (define_insn ""
3139 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3140 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3141 (match_operand:SF 2 "gpc_reg_operand" "f"))
3142 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
3143 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3144 "fnmsubs %0,%1,%2,%3"
3145 [(set_attr "type" "fp")])
3147 (define_insn ""
3148 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3149 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3150 (match_operand:SF 2 "gpc_reg_operand" "f"))
3151 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
3152 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3153 "{fnms|fnmsub} %0,%1,%2,%3"
3154 [(set_attr "type" "dmul")])
3156 (define_expand "sqrtsf2"
3157 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3158 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
3159 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
3160 "")
3162 (define_insn ""
3163 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3164 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
3165 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT"
3166 "fsqrts %0,%1"
3167 [(set_attr "type" "ssqrt")])
3169 (define_insn ""
3170 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3171 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
3172 "TARGET_POWER2 && TARGET_HARD_FLOAT"
3173 "fsqrt %0,%1"
3174 [(set_attr "type" "dsqrt")])
3176 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
3177 ;; fsel instruction and some auxiliary computations. Then we just have a
3178 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
3179 ;; combine.
3180 (define_expand "maxsf3"
3181 [(set (match_dup 3)
3182 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
3183 (match_operand:SF 2 "gpc_reg_operand" "")))
3184 (set (match_operand:SF 0 "gpc_reg_operand" "")
3185 (if_then_else:SF (ge (match_dup 3)
3186 (const_int 0))
3187 (match_dup 1)
3188 (match_dup 2)))]
3189 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3190 "
3191 { operands[3] = gen_reg_rtx (SFmode); }")
3193 (define_split
3194 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3195 (smax:SF (match_operand:SF 1 "gpc_reg_operand" "")
3196 (match_operand:SF 2 "gpc_reg_operand" "")))
3197 (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
3198 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3199 [(set (match_dup 3)
3200 (minus:SF (match_dup 1) (match_dup 2)))
3201 (set (match_dup 0)
3202 (if_then_else:SF (ge (match_dup 3)
3203 (const_int 0))
3204 (match_dup 1)
3205 (match_dup 2)))]
3206 "")
3208 (define_expand "minsf3"
3209 [(set (match_dup 3)
3210 (minus:SF (match_operand:SF 2 "gpc_reg_operand" "")
3211 (match_operand:SF 1 "gpc_reg_operand" "")))
3212 (set (match_operand:SF 0 "gpc_reg_operand" "")
3213 (if_then_else:SF (ge (match_dup 3)
3214 (const_int 0))
3215 (match_dup 1)
3216 (match_dup 2)))]
3217 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3218 "
3219 { operands[3] = gen_reg_rtx (SFmode); }")
3221 (define_split
3222 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3223 (smin:SF (match_operand:SF 1 "gpc_reg_operand" "")
3224 (match_operand:SF 2 "gpc_reg_operand" "")))
3225 (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
3226 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3227 [(set (match_dup 3)
3228 (minus:SF (match_dup 2) (match_dup 1)))
3229 (set (match_dup 0)
3230 (if_then_else:SF (ge (match_dup 3)
3231 (const_int 0))
3232 (match_dup 1)
3233 (match_dup 2)))]
3234 "")
3236 (define_expand "movsfcc"
3237 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3238 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3239 (match_operand:SF 2 "gpc_reg_operand" "f")
3240 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3241 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3242 "
3243 {
3244 rtx temp, op0, op1;
3245 enum rtx_code code = GET_CODE (operands[1]);
3246 if (! rs6000_compare_fp_p)
3247 FAIL;
3248 switch (code)
3249 {
3250 case GE: case EQ: case NE:
3251 op0 = rs6000_compare_op0;
3252 op1 = rs6000_compare_op1;
3253 break;
3254 case GT:
3255 op0 = rs6000_compare_op1;
3256 op1 = rs6000_compare_op0;
3257 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3258 break;
3259 case LE:
3260 op0 = rs6000_compare_op1;
3261 op1 = rs6000_compare_op0;
3262 break;
3263 case LT:
3264 op0 = rs6000_compare_op0;
3265 op1 = rs6000_compare_op1;
3266 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3267 break;
3268 default:
3269 FAIL;
3270 }
3271 if (GET_MODE (rs6000_compare_op0) == DFmode)
3272 {
3273 temp = gen_reg_rtx (DFmode);
3274 emit_insn (gen_subdf3 (temp, op0, op1));
3275 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[2], operands[3]));
3276 if (code == EQ)
3277 {
3278 emit_insn (gen_negdf2 (temp, temp));
3279 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[0], operands[3]));
3280 }
3281 if (code == NE)
3282 {
3283 emit_insn (gen_negdf2 (temp, temp));
3284 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[3], operands[0]));
3285 }
3286 }
3287 else
3288 {
3289 temp = gen_reg_rtx (SFmode);
3290 emit_insn (gen_subsf3 (temp, op0, op1));
3291 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[2], operands[3]));
3292 if (code == EQ)
3293 {
3294 emit_insn (gen_negsf2 (temp, temp));
3295 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[0], operands[3]));
3296 }
3297 if (code == NE)
3298 {
3299 emit_insn (gen_negsf2 (temp, temp));
3300 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[3], operands[0]));
3301 }
3302 }
3303 DONE;
3304 }")
3306 (define_insn "fselsfsf4"
3307 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3308 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
3309 (const_int 0))
3310 (match_operand:SF 2 "gpc_reg_operand" "f")
3311 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3312 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3313 "fsel %0,%1,%2,%3"
3314 [(set_attr "type" "fp")])
3316 (define_insn "fseldfsf4"
3317 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3318 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
3319 (const_int 0))
3320 (match_operand:SF 2 "gpc_reg_operand" "f")
3321 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3322 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3323 "fsel %0,%1,%2,%3"
3324 [(set_attr "type" "fp")])
3326 (define_insn "negdf2"
3327 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3328 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3329 "TARGET_HARD_FLOAT"
3330 "fneg %0,%1"
3331 [(set_attr "type" "fp")])
3333 (define_insn "absdf2"
3334 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3335 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3336 "TARGET_HARD_FLOAT"
3337 "fabs %0,%1"
3338 [(set_attr "type" "fp")])
3340 (define_insn ""
3341 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3342 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
3343 "TARGET_HARD_FLOAT"
3344 "fnabs %0,%1"
3345 [(set_attr "type" "fp")])
3347 (define_insn "adddf3"
3348 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3349 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3350 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3351 "TARGET_HARD_FLOAT"
3352 "{fa|fadd} %0,%1,%2"
3353 [(set_attr "type" "fp")])
3355 (define_insn "subdf3"
3356 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3357 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
3358 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3359 "TARGET_HARD_FLOAT"
3360 "{fs|fsub} %0,%1,%2"
3361 [(set_attr "type" "fp")])
3363 (define_insn "muldf3"
3364 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3365 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3366 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3367 "TARGET_HARD_FLOAT"
3368 "{fm|fmul} %0,%1,%2"
3369 [(set_attr "type" "dmul")])
3371 (define_insn "divdf3"
3372 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3373 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
3374 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3375 "TARGET_HARD_FLOAT"
3376 "{fd|fdiv} %0,%1,%2"
3377 [(set_attr "type" "ddiv")])
3379 (define_insn ""
3380 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3381 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3382 (match_operand:DF 2 "gpc_reg_operand" "f"))
3383 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3384 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3385 "{fma|fmadd} %0,%1,%2,%3"
3386 [(set_attr "type" "dmul")])
3388 (define_insn ""
3389 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3390 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3391 (match_operand:DF 2 "gpc_reg_operand" "f"))
3392 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3393 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3394 "{fms|fmsub} %0,%1,%2,%3"
3395 [(set_attr "type" "dmul")])
3397 (define_insn ""
3398 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3399 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3400 (match_operand:DF 2 "gpc_reg_operand" "f"))
3401 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
3402 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3403 "{fnma|fnmadd} %0,%1,%2,%3"
3404 [(set_attr "type" "dmul")])
3406 (define_insn ""
3407 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3408 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3409 (match_operand:DF 2 "gpc_reg_operand" "f"))
3410 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
3411 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3412 "{fnms|fnmsub} %0,%1,%2,%3"
3413 [(set_attr "type" "dmul")])
3415 (define_insn "sqrtdf2"
3416 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3417 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3418 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
3419 "fsqrt %0,%1"
3420 [(set_attr "type" "dsqrt")])
3422 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
3423 ;; fsel instruction and some auxiliary computations. Then we just have a
3424 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
3425 ;; combine.
3427 (define_expand "maxdf3"
3428 [(set (match_dup 3)
3429 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
3430 (match_operand:DF 2 "gpc_reg_operand" "")))
3431 (set (match_operand:DF 0 "gpc_reg_operand" "")
3432 (if_then_else:DF (ge (match_dup 3)
3433 (const_int 0))
3434 (match_dup 1)
3435 (match_dup 2)))]
3436 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3437 "
3438 { operands[3] = gen_reg_rtx (DFmode); }")
3440 (define_split
3441 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3442 (smax:DF (match_operand:DF 1 "gpc_reg_operand" "")
3443 (match_operand:DF 2 "gpc_reg_operand" "")))
3444 (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
3445 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3446 [(set (match_dup 3)
3447 (minus:DF (match_dup 1) (match_dup 2)))
3448 (set (match_dup 0)
3449 (if_then_else:DF (ge (match_dup 3)
3450 (const_int 0))
3451 (match_dup 1)
3452 (match_dup 2)))]
3453 "")
3455 (define_expand "mindf3"
3456 [(set (match_dup 3)
3457 (minus:DF (match_operand:DF 2 "gpc_reg_operand" "")
3458 (match_operand:DF 1 "gpc_reg_operand" "")))
3459 (set (match_operand:DF 0 "gpc_reg_operand" "")
3460 (if_then_else:DF (ge (match_dup 3)
3461 (const_int 0))
3462 (match_dup 1)
3463 (match_dup 2)))]
3464 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3465 "
3466 { operands[3] = gen_reg_rtx (DFmode); }")
3468 (define_split
3469 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3470 (smin:DF (match_operand:DF 1 "gpc_reg_operand" "")
3471 (match_operand:DF 2 "gpc_reg_operand" "")))
3472 (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
3473 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3474 [(set (match_dup 3)
3475 (minus:DF (match_dup 2) (match_dup 1)))
3476 (set (match_dup 0)
3477 (if_then_else:DF (ge (match_dup 3)
3478 (const_int 0))
3479 (match_dup 1)
3480 (match_dup 2)))]
3481 "")
3483 (define_expand "movdfcc"
3484 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3485 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3486 (match_operand:DF 2 "gpc_reg_operand" "f")
3487 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3488 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3489 "
3490 {
3491 rtx temp, op0, op1;
3492 enum rtx_code code = GET_CODE (operands[1]);
3493 if (! rs6000_compare_fp_p)
3494 FAIL;
3495 switch (code)
3496 {
3497 case GE: case EQ: case NE:
3498 op0 = rs6000_compare_op0;
3499 op1 = rs6000_compare_op1;
3500 break;
3501 case GT:
3502 op0 = rs6000_compare_op1;
3503 op1 = rs6000_compare_op0;
3504 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3505 break;
3506 case LE:
3507 op0 = rs6000_compare_op1;
3508 op1 = rs6000_compare_op0;
3509 break;
3510 case LT:
3511 op0 = rs6000_compare_op0;
3512 op1 = rs6000_compare_op1;
3513 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3514 break;
3515 default:
3516 FAIL;
3517 }
3518 if (GET_MODE (rs6000_compare_op0) == DFmode)
3519 {
3520 temp = gen_reg_rtx (DFmode);
3521 emit_insn (gen_subdf3 (temp, op0, op1));
3522 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[2], operands[3]));
3523 if (code == EQ)
3524 {
3525 emit_insn (gen_negdf2 (temp, temp));
3526 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[0], operands[3]));
3527 }
3528 if (code == NE)
3529 {
3530 emit_insn (gen_negdf2 (temp, temp));
3531 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[3], operands[0]));
3532 }
3533 }
3534 else
3535 {
3536 temp = gen_reg_rtx (SFmode);
3537 emit_insn (gen_subsf3 (temp, op0, op1));
3538 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[2], operands[3]));
3539 if (code == EQ)
3540 {
3541 emit_insn (gen_negsf2 (temp, temp));
3542 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[0], operands[3]));
3543 }
3544 if (code == NE)
3545 {
3546 emit_insn (gen_negsf2 (temp, temp));
3547 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[3], operands[0]));
3548 }
3549 }
3550 DONE;
3551 }")
3553 (define_insn "fseldfdf4"
3554 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3555 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
3556 (const_int 0))
3557 (match_operand:DF 2 "gpc_reg_operand" "f")
3558 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3559 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3560 "fsel %0,%1,%2,%3"
3561 [(set_attr "type" "fp")])
3563 (define_insn "fselsfdf4"
3564 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3565 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
3566 (const_int 0))
3567 (match_operand:DF 2 "gpc_reg_operand" "f")
3568 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3569 "TARGET_PPC_GFXOPT"
3570 "fsel %0,%1,%2,%3"
3571 [(set_attr "type" "fp")])
3572 \f
3573 ;; Conversions to and from floating-point.
3575 (define_expand "floatsidf2"
3576 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
3577 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
3578 (use (match_dup 2))
3579 (use (match_dup 3))
3580 (clobber (match_dup 4))
3581 (clobber (match_dup 5))
3582 (clobber (reg:DF 76))])]
3583 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3584 "
3585 {
3586 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
3587 operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode));
3588 operands[4] = gen_reg_rtx (SImode);
3589 operands[5] = gen_reg_rtx (Pmode);
3590 }")
3592 (define_insn "*floatsidf2_internal"
3593 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
3594 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
3595 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
3596 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
3597 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
3598 (clobber (match_operand:SI 5 "gpc_reg_operand" "=b"))
3599 (clobber (reg:DF 76))]
3600 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3601 "#"
3602 [(set_attr "length" "24")])
3604 (define_split
3605 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3606 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
3607 (use (match_operand:SI 2 "gpc_reg_operand" ""))
3608 (use (match_operand:DF 3 "gpc_reg_operand" ""))
3609 (clobber (match_operand:SI 4 "gpc_reg_operand" ""))
3610 (clobber (match_operand:SI 5 "gpc_reg_operand" ""))
3611 (clobber (reg:DF 76))]
3612 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3613 [(set (match_dup 4)
3614 (xor:SI (match_dup 1)
3615 (match_dup 6)))
3616 (set (match_dup 5)
3617 (unspec [(const_int 0)] 11))
3618 (set (match_dup 7)
3619 (unspec [(match_dup 4)
3620 (match_dup 5)] 12)) ;; low word
3621 (set (match_dup 7)
3622 (unspec [(match_dup 2)
3623 (match_dup 5)
3624 (match_dup 7)] 13)) ;; high word
3625 (set (match_dup 0)
3626 (unspec [(match_dup 7)
3627 (match_dup 5)] 14))
3628 (set (match_dup 0)
3629 (minus:DF (match_dup 0)
3630 (match_dup 3)))]
3631 "
3632 {
3633 operands[6] = GEN_INT (0x80000000);
3634 operands[7] = gen_rtx (REG, DFmode, FPMEM_REGNUM);
3635 }")
3637 (define_expand "floatunssidf2"
3638 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
3639 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
3640 (use (match_dup 2))
3641 (use (match_dup 3))
3642 (clobber (match_dup 4))
3643 (clobber (reg:DF 76))])]
3644 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3645 "
3646 {
3647 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
3648 operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode));
3649 operands[4] = gen_reg_rtx (Pmode);
3650 }")
3652 (define_insn "*floatunssidf2_internal"
3653 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
3654 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
3655 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
3656 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
3657 (clobber (match_operand:SI 4 "gpc_reg_operand" "=b"))
3658 (clobber (reg:DF 76))]
3659 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3660 "#"
3661 [(set_attr "length" "20")])
3663 (define_split
3664 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3665 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
3666 (use (match_operand:SI 2 "gpc_reg_operand" ""))
3667 (use (match_operand:DF 3 "gpc_reg_operand" ""))
3668 (clobber (match_operand:SI 4 "gpc_reg_operand" "=b"))
3669 (clobber (reg:DF 76))]
3670 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3671 [(set (match_dup 4)
3672 (unspec [(const_int 0)] 11))
3673 (set (match_dup 5)
3674 (unspec [(match_dup 1)
3675 (match_dup 4)] 12)) ;; low word
3676 (set (match_dup 5)
3677 (unspec [(match_dup 2)
3678 (match_dup 4)
3679 (match_dup 5)] 13)) ;; high word
3680 (set (match_dup 0)
3681 (unspec [(match_dup 5)
3682 (reg:SI 1)] 14))
3683 (set (match_dup 0)
3684 (minus:DF (match_dup 0)
3685 (match_dup 3)))]
3686 "operands[5] = gen_rtx (REG, DFmode, FPMEM_REGNUM);")
3688 ;; Load up scratch register with base address + offset if needed
3689 (define_insn "*floatsidf2_loadaddr"
3690 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
3691 (unspec [(const_int 0)] 11))]
3692 "TARGET_HARD_FLOAT"
3693 "*
3694 {
3695 if (rs6000_fpmem_offset > 32760)
3696 {
3697 rtx xop[3];
3699 xop[0] = operands[0];
3700 xop[1] = (frame_pointer_needed) ? frame_pointer_rtx : stack_pointer_rtx;
3701 xop[2] = GEN_INT ((rs6000_fpmem_offset >> 16) + ((rs6000_fpmem_offset & 0x8000) >> 15));
3702 output_asm_insn (\"{cau|addis} %0,%1,%2\", xop);
3703 }
3704 else if (rs6000_fpmem_offset < 0)
3705 abort ();
3707 return \"\";
3708 }"
3709 [(set_attr "length" "4")])
3711 (define_insn "*floatsidf2_store1"
3712 [(set (reg:DF 76)
3713 (unspec [(match_operand:SI 0 "gpc_reg_operand" "r")
3714 (match_operand:SI 1 "gpc_reg_operand" "r")] 12))]
3715 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3716 "*
3717 {
3718 rtx indx;
3720 if (rs6000_fpmem_offset > 32760)
3721 indx = operands[1];
3722 else if (frame_pointer_needed)
3723 indx = frame_pointer_rtx;
3724 else
3725 indx = stack_pointer_rtx;
3727 operands[2] = gen_rtx (MEM, SImode,
3728 gen_rtx (PLUS, Pmode,
3729 indx,
3730 GEN_INT ((((rs6000_fpmem_offset & 0xffff) ^ 0x8000) - 0x8000)
3731 + ((WORDS_BIG_ENDIAN != 0) * 4))));
3733 return \"{st|stw} %0,%2\";
3734 }"
3735 [(set_attr "type" "store")])
3737 (define_insn "*floatsidf2_store2"
3738 [(set (reg:DF 76)
3739 (unspec [(match_operand:SI 0 "gpc_reg_operand" "r")
3740 (match_operand:SI 1 "gpc_reg_operand" "r")
3741 (reg:DF 76)] 13))]
3742 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3743 "*
3744 {
3745 rtx indx;
3747 if (rs6000_fpmem_offset > 32760)
3748 indx = operands[1];
3749 else if (frame_pointer_needed)
3750 indx = frame_pointer_rtx;
3751 else
3752 indx = stack_pointer_rtx;
3754 operands[2] = gen_rtx (MEM, SImode,
3755 gen_rtx (PLUS, Pmode,
3756 indx,
3757 GEN_INT ((((rs6000_fpmem_offset & 0xffff) ^ 0x8000) - 0x8000)
3758 + ((WORDS_BIG_ENDIAN == 0) * 4))));
3760 return \"{st|stw} %0,%2\";
3761 }"
3762 [(set_attr "type" "store")])
3764 (define_insn "*floatsidf2_load"
3765 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3766 (unspec [(reg:DF 76)
3767 (match_operand:SI 1 "gpc_reg_operand" "b")] 14))]
3768 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3769 "*
3770 {
3771 rtx indx;
3772 HOST_WIDE_INT offset = rs6000_fpmem_offset;
3774 if (rs6000_fpmem_offset > 32760)
3775 {
3776 indx = operands[1];
3777 offset = (((offset & 0xffff) ^ 0x8000) - 0x8000);
3778 }
3779 else if (frame_pointer_needed)
3780 indx = frame_pointer_rtx;
3781 else
3782 indx = stack_pointer_rtx;
3784 operands[2] = gen_rtx (MEM, SImode,
3785 gen_rtx (PLUS, Pmode, indx, GEN_INT (offset)));
3787 return \"lfd %0,%2\";
3788 }"
3789 [(set_attr "type" "fpload")])
3791 (define_expand "fix_truncdfsi2"
3792 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
3793 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
3794 (clobber (match_dup 2))
3795 (clobber (match_dup 3))
3796 (clobber (match_dup 4))])]
3797 "TARGET_HARD_FLOAT"
3798 "
3799 {
3800 if (!TARGET_POWER2 && !TARGET_POWERPC)
3801 {
3802 emit_insn (gen_trunc_call (operands[0], operands[1],
3803 gen_rtx (SYMBOL_REF, Pmode, RS6000_ITRUNC)));
3804 DONE;
3805 }
3807 operands[2] = gen_reg_rtx (DImode);
3808 operands[3] = gen_reg_rtx (Pmode);
3809 operands[4] = gen_rtx (REG, DImode, FPMEM_REGNUM);
3810 }")
3812 (define_insn "*fix_truncdfsi2_internal"
3813 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3814 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
3815 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
3816 (clobber (match_operand:SI 3 "gpc_reg_operand" "=b"))
3817 (clobber (reg:DI 76))]
3818 "TARGET_HARD_FLOAT"
3819 "#"
3820 [(set_attr "length" "12")])
3822 (define_split
3823 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3824 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
3825 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
3826 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))
3827 (clobber (reg:DI 76))]
3828 "TARGET_HARD_FLOAT"
3829 [(set (match_dup 2)
3830 (sign_extend:DI (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))))
3831 (set (match_dup 3)
3832 (unspec [(const_int 0)] 11))
3833 (set (match_dup 4)
3834 (unspec [(match_dup 2)
3835 (match_dup 3)] 15))
3836 (set (match_operand:SI 0 "gpc_reg_operand" "")
3837 (unspec [(match_dup 4)
3838 (match_dup 3)] 16))]
3839 "operands[4] = gen_rtx (REG, DImode, FPMEM_REGNUM);")
3841 (define_insn "*fctiwz"
3842 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
3843 (sign_extend:DI (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))))]
3844 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
3845 "{fcirz|fctiwz} %0,%1"
3846 [(set_attr "type" "fp")])
3848 (define_insn "*fix_truncdfsi2_store"
3849 [(set (reg:DI 76)
3850 (unspec [(match_operand:DI 0 "gpc_reg_operand" "f")
3851 (match_operand:SI 1 "gpc_reg_operand" "b")] 15))]
3852 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
3853 "*
3854 {
3855 rtx indx;
3857 if (rs6000_fpmem_offset > 32760)
3858 indx = operands[1];
3859 else if (frame_pointer_needed)
3860 indx = frame_pointer_rtx;
3861 else
3862 indx = stack_pointer_rtx;
3864 operands[2] = gen_rtx (MEM, DFmode,
3865 gen_rtx (PLUS, Pmode,
3866 indx,
3867 GEN_INT ((((rs6000_fpmem_offset & 0xffff)
3868 ^ 0x8000) - 0x8000))));
3870 return \"stfd %0,%w2\";
3871 }"
3872 [(set_attr "type" "fpstore")])
3874 (define_insn "*fix_truncdfsi2_load"
3875 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3876 (unspec [(reg:DI 76)
3877 (match_operand:SI 1 "gpc_reg_operand" "b")] 16))]
3878 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
3879 "*
3880 {
3881 rtx indx;
3883 if (rs6000_fpmem_offset > 32760)
3884 indx = operands[1];
3885 else if (frame_pointer_needed)
3886 indx = frame_pointer_rtx;
3887 else
3888 indx = stack_pointer_rtx;
3890 operands[2] = gen_rtx (MEM, DFmode,
3891 gen_rtx (PLUS, Pmode,
3892 indx,
3893 GEN_INT ((((rs6000_fpmem_offset & 0xffff) ^ 0x8000) - 0x8000)
3894 + ((WORDS_BIG_ENDIAN) ? 4 : 0))));
3896 return \"{l|lwz} %0,%2\";
3897 }"
3898 [(set_attr "type" "load")])
3900 (define_expand "fixuns_truncdfsi2"
3901 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3902 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
3903 "! TARGET_POWER2 && ! TARGET_POWERPC && TARGET_HARD_FLOAT"
3904 "
3905 {
3906 emit_insn (gen_trunc_call (operands[0], operands[1],
3907 gen_rtx (SYMBOL_REF, Pmode, RS6000_UITRUNC)));
3908 DONE;
3909 }")
3911 (define_expand "trunc_call"
3912 [(parallel [(set (match_operand:SI 0 "" "")
3913 (fix:SI (match_operand:DF 1 "" "")))
3914 (use (match_operand:SI 2 "" ""))])]
3915 "TARGET_HARD_FLOAT"
3916 "
3917 {
3918 rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]);
3919 rtx first = XVECEXP (insns, 0, 0);
3920 rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
3922 REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
3923 REG_NOTES (first));
3924 REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last));
3926 emit_insn (insns);
3927 DONE;
3928 }")
3930 (define_expand "trunc_call_rtl"
3931 [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" ""))
3932 (use (reg:DF 33))
3933 (parallel [(set (reg:SI 3)
3934 (call (mem:SI (match_operand 2 "" "")) (const_int 0)))
3935 (use (const_int 0))
3936 (clobber (scratch:SI))])
3937 (set (match_operand:SI 0 "gpc_reg_operand" "")
3938 (reg:SI 3))]
3939 "TARGET_HARD_FLOAT"
3940 "
3941 {
3942 rs6000_trunc_used = 1;
3943 }")
3945 (define_insn "floatdidf2"
3946 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3947 (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))]
3948 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3949 "fcfid %0,%1"
3950 [(set_attr "type" "fp")])
3952 (define_insn "fix_truncdfdi2"
3953 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
3954 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
3955 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3956 "fctidz %0,%1"
3957 [(set_attr "type" "fp")])
3958 \f
3959 ;; Define the DImode operations that can be done in a small number
3960 ;; of instructions. The & constraints are to prevent the register
3961 ;; allocator from allocating registers that overlap with the inputs
3962 ;; (for example, having an input in 7,8 and an output in 6,7). We
3963 ;; also allow for the the output being the same as one of the inputs.
3965 (define_insn "*adddi3_noppc64"
3966 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
3967 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
3968 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
3969 "! TARGET_POWERPC64"
3970 "*
3971 {
3972 if (WORDS_BIG_ENDIAN)
3973 return (GET_CODE (operands[2])) != CONST_INT
3974 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
3975 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
3976 else
3977 return (GET_CODE (operands[2])) != CONST_INT
3978 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
3979 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
3980 }"
3981 [(set_attr "length" "8")])
3983 (define_insn "*subdi3_noppc64"
3984 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
3985 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
3986 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
3987 "! TARGET_POWERPC64"
3988 "*
3989 {
3990 if (WORDS_BIG_ENDIAN)
3991 return (GET_CODE (operands[1]) != CONST_INT)
3992 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
3993 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
3994 else
3995 return (GET_CODE (operands[1]) != CONST_INT)
3996 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
3997 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
3998 }"
3999 [(set_attr "length" "8")])
4001 (define_insn "*negdi2_noppc64"
4002 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4003 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
4004 "! TARGET_POWERPC64"
4005 "*
4006 {
4007 return (WORDS_BIG_ENDIAN)
4008 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
4009 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
4010 }"
4011 [(set_attr "length" "8")])
4013 (define_expand "mulsidi3"
4014 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4015 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
4016 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
4017 ""
4018 "
4019 {
4020 if (! TARGET_POWER && ! TARGET_POWERPC)
4021 {
4022 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
4023 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
4024 emit_insn (gen_mull_call ());
4025 if (WORDS_BIG_ENDIAN)
4026 emit_move_insn (operands[0], gen_rtx (REG, DImode, 3));
4027 else
4028 {
4029 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
4030 gen_rtx (REG, SImode, 3));
4031 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
4032 gen_rtx (REG, SImode, 4));
4033 }
4034 DONE;
4035 }
4036 else if (TARGET_POWER)
4037 {
4038 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
4039 DONE;
4040 }
4041 }")
4043 (define_insn "mulsidi3_mq"
4044 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4045 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
4046 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
4047 (clobber (match_scratch:SI 3 "=q"))]
4048 "TARGET_POWER"
4049 "mul %0,%1,%2\;mfmq %L0"
4050 [(set_attr "type" "imul")
4051 (set_attr "length" "8")])
4053 (define_insn "*mulsidi3_no_mq"
4054 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
4055 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
4056 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
4057 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
4058 "*
4059 {
4060 return (WORDS_BIG_ENDIAN)
4061 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
4062 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
4063 }"
4064 [(set_attr "type" "imul")
4065 (set_attr "length" "8")])
4067 (define_split
4068 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4069 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
4070 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
4071 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
4072 [(set (match_dup 3)
4073 (truncate:SI
4074 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
4075 (sign_extend:DI (match_dup 2)))
4076 (const_int 32))))
4077 (set (match_dup 4)
4078 (mult:SI (match_dup 1)
4079 (match_dup 2)))]
4080 "
4081 {
4082 int endian = (WORDS_BIG_ENDIAN == 0);
4083 operands[3] = operand_subword (operands[0], endian, 0, DImode);
4084 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
4085 }")
4087 (define_expand "umulsidi3"
4088 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4089 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
4090 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
4091 "TARGET_POWERPC && ! TARGET_POWERPC64"
4092 "
4093 {
4094 if (TARGET_POWER)
4095 {
4096 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
4097 DONE;
4098 }
4099 }")
4101 (define_insn "umulsidi3_mq"
4102 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
4103 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
4104 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
4105 (clobber (match_scratch:SI 3 "=q"))]
4106 "TARGET_POWERPC && TARGET_POWER"
4107 "*
4108 {
4109 return (WORDS_BIG_ENDIAN)
4110 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
4111 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
4112 }"
4113 [(set_attr "type" "imul")
4114 (set_attr "length" "8")])
4116 (define_insn "*umulsidi3_no_mq"
4117 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
4118 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
4119 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
4120 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
4121 "*
4122 {
4123 return (WORDS_BIG_ENDIAN)
4124 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
4125 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
4126 }"
4127 [(set_attr "type" "imul")
4128 (set_attr "length" "8")])
4130 (define_split
4131 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4132 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
4133 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
4134 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
4135 [(set (match_dup 3)
4136 (truncate:SI
4137 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
4138 (zero_extend:DI (match_dup 2)))
4139 (const_int 32))))
4140 (set (match_dup 4)
4141 (mult:SI (match_dup 1)
4142 (match_dup 2)))]
4143 "
4144 {
4145 int endian = (WORDS_BIG_ENDIAN == 0);
4146 operands[3] = operand_subword (operands[0], endian, 0, DImode);
4147 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
4148 }")
4150 (define_expand "smulsi3_highpart"
4151 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4152 (truncate:SI
4153 (lshiftrt:DI (mult:DI (sign_extend:DI
4154 (match_operand:SI 1 "gpc_reg_operand" "%r"))
4155 (sign_extend:DI
4156 (match_operand:SI 2 "gpc_reg_operand" "r")))
4157 (const_int 32))))]
4158 ""
4159 "
4160 {
4161 if (! TARGET_POWER && ! TARGET_POWERPC)
4162 {
4163 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
4164 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
4165 emit_insn (gen_mulh_call ());
4166 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
4167 DONE;
4168 }
4169 else if (TARGET_POWER)
4170 {
4171 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
4172 DONE;
4173 }
4174 }")
4176 (define_insn "smulsi3_highpart_mq"
4177 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4178 (truncate:SI
4179 (lshiftrt:DI (mult:DI (sign_extend:DI
4180 (match_operand:SI 1 "gpc_reg_operand" "%r"))
4181 (sign_extend:DI
4182 (match_operand:SI 2 "gpc_reg_operand" "r")))
4183 (const_int 32))))
4184 (clobber (match_scratch:SI 3 "=q"))]
4185 "TARGET_POWER"
4186 "mul %0,%1,%2"
4187 [(set_attr "type" "imul")])
4189 (define_insn "*smulsi3_highpart_no_mq"
4190 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4191 (truncate:SI
4192 (lshiftrt:DI (mult:DI (sign_extend:DI
4193 (match_operand:SI 1 "gpc_reg_operand" "%r"))
4194 (sign_extend:DI
4195 (match_operand:SI 2 "gpc_reg_operand" "r")))
4196 (const_int 32))))]
4197 "TARGET_POWERPC && ! TARGET_POWER"
4198 "mulhw %0,%1,%2"
4199 [(set_attr "type" "imul")])
4201 (define_expand "umulsi3_highpart"
4202 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4203 (truncate:SI
4204 (lshiftrt:DI (mult:DI (zero_extend:DI
4205 (match_operand:SI 1 "gpc_reg_operand" ""))
4206 (zero_extend:DI
4207 (match_operand:SI 2 "gpc_reg_operand" "")))
4208 (const_int 32))))]
4209 "TARGET_POWERPC"
4210 "
4211 {
4212 if (TARGET_POWER)
4213 {
4214 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
4215 DONE;
4216 }
4217 }")
4219 (define_insn "umulsi3_highpart_mq"
4220 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4221 (truncate:SI
4222 (lshiftrt:DI (mult:DI (zero_extend:DI
4223 (match_operand:SI 1 "gpc_reg_operand" "%r"))
4224 (zero_extend:DI
4225 (match_operand:SI 2 "gpc_reg_operand" "r")))
4226 (const_int 32))))
4227 (clobber (match_scratch:SI 3 "=q"))]
4228 "TARGET_POWERPC && TARGET_POWER"
4229 "mulhwu %0,%1,%2"
4230 [(set_attr "type" "imul")])
4232 (define_insn "*umulsi3_highpart_no_mq"
4233 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4234 (truncate:SI
4235 (lshiftrt:DI (mult:DI (zero_extend:DI
4236 (match_operand:SI 1 "gpc_reg_operand" "%r"))
4237 (zero_extend:DI
4238 (match_operand:SI 2 "gpc_reg_operand" "r")))
4239 (const_int 32))))]
4240 "TARGET_POWERPC && ! TARGET_POWER"
4241 "mulhwu %0,%1,%2"
4242 [(set_attr "type" "imul")])
4244 ;; If operands 0 and 2 are in the same register, we have a problem. But
4245 ;; operands 0 and 1 (the usual case) can be in the same register. That's
4246 ;; why we have the strange constraints below.
4247 (define_insn "ashldi3_power"
4248 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
4249 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
4250 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
4251 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
4252 "TARGET_POWER"
4253 "@
4254 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
4255 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
4256 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
4257 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
4258 [(set_attr "length" "8")])
4260 (define_insn "lshrdi3_power"
4261 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
4262 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
4263 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
4264 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
4265 "TARGET_POWER"
4266 "@
4267 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
4268 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
4269 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
4270 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
4271 [(set_attr "length" "8")])
4273 ;; Shift by a variable amount is too complex to be worth open-coding. We
4274 ;; just handle shifts by constants.
4275 (define_insn "ashrdi3_power"
4276 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4277 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
4278 (match_operand:SI 2 "const_int_operand" "M,i")))
4279 (clobber (match_scratch:SI 3 "=X,q"))]
4280 "TARGET_POWER"
4281 "@
4282 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
4283 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
4284 [(set_attr "length" "8")])
4285 \f
4286 ;; PowerPC64 DImode operations.
4288 (define_expand "adddi3"
4289 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4290 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
4291 (match_operand:DI 2 "add_operand" "")))]
4292 ""
4293 "
4294 {
4295 if (! TARGET_POWERPC64 && non_short_cint_operand (operands[2], DImode))
4296 FAIL;
4297 }")
4299 ;; Discourage ai/addic because of carry but provide it in an alternative
4300 ;; allowing register zero as source.
4302 (define_insn ""
4303 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
4304 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
4305 (match_operand:DI 2 "add_operand" "r,I,I,J")))]
4306 "TARGET_POWERPC64"
4307 "@
4308 add %0,%1,%2
4309 addi %0,%1,%2
4310 addic %0,%1,%2
4311 addis %0,%1,%v2")
4313 (define_insn ""
4314 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4315 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
4316 (match_operand:DI 2 "reg_or_short_operand" "r,I"))
4317 (const_int 0)))
4318 (clobber (match_scratch:DI 3 "=r,r"))]
4319 "TARGET_POWERPC64"
4320 "@
4321 add. %3,%1,%2
4322 addic. %3,%1,%2"
4323 [(set_attr "type" "compare")])
4325 (define_insn ""
4326 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
4327 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
4328 (match_operand:DI 2 "reg_or_short_operand" "r,I"))
4329 (const_int 0)))
4330 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4331 (plus:DI (match_dup 1) (match_dup 2)))]
4332 "TARGET_POWERPC64"
4333 "@
4334 add. %0,%1,%2
4335 addic. %0,%1,%2"
4336 [(set_attr "type" "compare")])
4338 ;; Split an add that we can't do in one insn into two insns, each of which
4339 ;; does one 16-bit part. This is used by combine. Note that the low-order
4340 ;; add should be last in case the result gets used in an address.
4342 (define_split
4343 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4344 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
4345 (match_operand:DI 2 "non_add_cint_operand" "")))]
4346 "TARGET_POWERPC64"
4347 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
4348 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
4349 "
4350 {
4351 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
4352 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
4354 if (low & 0x8000)
4355 high+=0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
4357 operands[3] = GEN_INT (high);
4358 operands[4] = GEN_INT (low);
4359 }")
4361 (define_insn "one_cmpldi2"
4362 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4363 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
4364 "TARGET_POWERPC64"
4365 "nor %0,%1,%1")
4367 (define_insn ""
4368 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4369 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4370 (const_int 0)))
4371 (clobber (match_scratch:DI 2 "=r"))]
4372 "TARGET_POWERPC64"
4373 "nor. %2,%1,%1"
4374 [(set_attr "type" "compare")])
4376 (define_insn ""
4377 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
4378 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4379 (const_int 0)))
4380 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4381 (not:DI (match_dup 1)))]
4382 "TARGET_POWERPC64"
4383 "nor. %0,%1,%1"
4384 [(set_attr "type" "compare")])
4386 (define_insn ""
4387 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4388 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
4389 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
4390 "TARGET_POWERPC64"
4391 "@
4392 subf %0,%2,%1
4393 subfic %0,%2,%1")
4395 (define_insn ""
4396 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4397 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4398 (match_operand:DI 2 "gpc_reg_operand" "r"))
4399 (const_int 0)))
4400 (clobber (match_scratch:DI 3 "=r"))]
4401 "TARGET_POWERPC64"
4402 "subf. %3,%2,%1"
4403 [(set_attr "type" "compare")])
4405 (define_insn ""
4406 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4407 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4408 (match_operand:DI 2 "gpc_reg_operand" "r"))
4409 (const_int 0)))
4410 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4411 (minus:DI (match_dup 1) (match_dup 2)))]
4412 "TARGET_POWERPC64"
4413 "subf. %0,%2,%1"
4414 [(set_attr "type" "compare")])
4416 (define_expand "subdi3"
4417 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4418 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
4419 (match_operand:DI 2 "reg_or_cint_operand" "")))]
4420 ""
4421 "
4422 {
4423 if (GET_CODE (operands[2]) == CONST_INT)
4424 {
4425 emit_insn (gen_adddi3 (operands[0], operands[1],
4426 negate_rtx (DImode, operands[2])));
4427 DONE;
4428 }
4429 }")
4431 (define_insn "absdi2"
4432 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4433 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
4434 (clobber (match_scratch:DI 2 "=&r,&r"))]
4435 "TARGET_POWERPC64"
4436 "sradi %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0"
4437 [(set_attr "length" "12")])
4439 (define_split
4440 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4441 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
4442 (clobber (match_scratch:DI 2 "=&r,&r"))]
4443 "TARGET_POWERPC64 && reload_completed"
4444 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 31)))
4445 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
4446 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
4447 "")
4449 (define_insn ""
4450 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4451 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
4452 (clobber (match_scratch:DI 2 "=&r,&r"))]
4453 "TARGET_POWERPC64"
4454 "sradi %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2"
4455 [(set_attr "length" "12")])
4457 (define_split
4458 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4459 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
4460 (clobber (match_scratch:DI 2 "=&r,&r"))]
4461 "TARGET_POWERPC64 && reload_completed"
4462 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 31)))
4463 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
4464 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
4465 "")
4467 (define_expand "negdi2"
4468 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4469 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
4470 ""
4471 "")
4473 (define_insn ""
4474 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4475 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
4476 "TARGET_POWERPC64"
4477 "neg %0,%1")
4479 (define_insn ""
4480 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4481 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4482 (const_int 0)))
4483 (clobber (match_scratch:DI 2 "=r"))]
4484 "TARGET_POWERPC64"
4485 "neg. %2,%1"
4486 [(set_attr "type" "compare")])
4488 (define_insn ""
4489 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
4490 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4491 (const_int 0)))
4492 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4493 (neg:DI (match_dup 1)))]
4494 "TARGET_POWERPC64"
4495 "neg. %0,%1"
4496 [(set_attr "type" "compare")])
4498 (define_insn "ffsdi2"
4499 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
4500 (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
4501 "TARGET_POWERPC64"
4502 "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64"
4503 [(set_attr "length" "16")])
4505 (define_insn "muldi3"
4506 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4507 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4508 (match_operand:DI 2 "gpc_reg_operand" "r")))]
4509 "TARGET_POWERPC64"
4510 "mulld %0,%1,%2"
4511 [(set_attr "type" "imul")])
4513 (define_insn "smuldi3_highpart"
4514 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4515 (truncate:DI
4516 (lshiftrt:TI (mult:TI (sign_extend:TI
4517 (match_operand:DI 1 "gpc_reg_operand" "%r"))
4518 (sign_extend:TI
4519 (match_operand:DI 2 "gpc_reg_operand" "r")))
4520 (const_int 64))))]
4521 "TARGET_POWERPC64"
4522 "mulhd %0,%1,%2"
4523 [(set_attr "type" "imul")])
4525 (define_insn "umuldi3_highpart"
4526 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4527 (truncate:DI
4528 (lshiftrt:TI (mult:TI (zero_extend:TI
4529 (match_operand:DI 1 "gpc_reg_operand" "%r"))
4530 (zero_extend:TI
4531 (match_operand:DI 2 "gpc_reg_operand" "r")))
4532 (const_int 64))))]
4533 "TARGET_POWERPC64"
4534 "mulhdu %0,%1,%2"
4535 [(set_attr "type" "imul")])
4537 (define_expand "divdi3"
4538 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4539 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
4540 (match_operand:DI 2 "reg_or_cint_operand" "")))]
4541 "TARGET_POWERPC64"
4542 "
4543 {
4544 if (GET_CODE (operands[2]) == CONST_INT
4545 && exact_log2 (INTVAL (operands[2])) >= 0)
4546 ;
4547 else
4548 operands[2] = force_reg (DImode, operands[2]);
4549 }")
4551 (define_expand "moddi3"
4552 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
4553 (use (match_operand:DI 1 "gpc_reg_operand" ""))
4554 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
4555 "TARGET_POWERPC64"
4556 "
4557 {
4558 int i = exact_log2 (INTVAL (operands[2]));
4559 rtx temp1;
4560 rtx temp2;
4562 if (GET_CODE (operands[2]) != CONST_INT || i < 0)
4563 FAIL;
4565 temp1 = gen_reg_rtx (DImode);
4566 temp2 = gen_reg_rtx (DImode);
4568 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
4569 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
4570 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
4571 DONE;
4572 }")
4574 (define_insn ""
4575 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4576 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4577 (match_operand:DI 2 "const_int_operand" "N")))]
4578 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
4579 "sradi %0,%1,%p2\;addze %0,%0"
4580 [(set_attr "length" "8")])
4582 (define_insn ""
4583 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4584 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4585 (match_operand:DI 2 "const_int_operand" "N"))
4586 (const_int 0)))
4587 (clobber (match_scratch:DI 3 "=r"))]
4588 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
4589 "sradi %3,%1,%p2\;addze. %3,%3"
4590 [(set_attr "type" "compare")
4591 (set_attr "length" "8")])
4593 (define_insn ""
4594 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4595 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4596 (match_operand:DI 2 "const_int_operand" "N"))
4597 (const_int 0)))
4598 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4599 (div:DI (match_dup 1) (match_dup 2)))]
4600 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
4601 "sradi %0,%1,%p2\;addze. %0,%0"
4602 [(set_attr "type" "compare")
4603 (set_attr "length" "8")])
4605 (define_insn ""
4606 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4607 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4608 (match_operand:DI 2 "gpc_reg_operand" "r")))]
4609 "TARGET_POWERPC64"
4610 "divd %0,%1,%2"
4611 [(set_attr "type" "idiv")])
4613 (define_insn "udivdi3"
4614 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4615 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4616 (match_operand:DI 2 "gpc_reg_operand" "r")))]
4617 "TARGET_POWERPC64"
4618 "divdu %0,%1,%2"
4619 [(set_attr "type" "idiv")])
4621 (define_insn "rotldi3"
4622 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4623 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4624 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
4625 "TARGET_POWERPC64"
4626 "rld%I2cl %0,%1,%H2,0")
4628 (define_insn ""
4629 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4630 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4631 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
4632 (const_int 0)))
4633 (clobber (match_scratch:DI 3 "=r"))]
4634 "TARGET_POWERPC64"
4635 "rld%I2cl. %3,%1,%H2,0"
4636 [(set_attr "type" "delayed_compare")])
4638 (define_insn ""
4639 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4640 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4641 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
4642 (const_int 0)))
4643 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4644 (rotate:DI (match_dup 1) (match_dup 2)))]
4645 "TARGET_POWERPC64"
4646 "rld%I2cl. %0,%1,%H2,0"
4647 [(set_attr "type" "delayed_compare")])
4649 (define_expand "ashldi3"
4650 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4651 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
4652 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4653 "TARGET_POWERPC64 || TARGET_POWER"
4654 "
4655 {
4656 if (TARGET_POWERPC64)
4657 ;
4658 else if (TARGET_POWER)
4659 {
4660 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
4661 DONE;
4662 }
4663 else
4664 FAIL;
4665 }")
4667 (define_insn ""
4668 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4669 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4670 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4671 "TARGET_POWERPC64"
4672 "sld%I2 %0,%1,%H2"
4673 [(set_attr "length" "8")])
4675 (define_insn ""
4676 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4677 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4678 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4679 (const_int 0)))
4680 (clobber (match_scratch:DI 3 "=r"))]
4681 "TARGET_POWERPC64"
4682 "sld%I2. %3,%1,%H2"
4683 [(set_attr "type" "delayed_compare")])
4685 (define_insn ""
4686 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4687 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4688 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4689 (const_int 0)))
4690 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4691 (ashift:DI (match_dup 1) (match_dup 2)))]
4692 "TARGET_POWERPC64"
4693 "sld%I2. %0,%1,%H2"
4694 [(set_attr "type" "delayed_compare")])
4696 (define_expand "lshrdi3"
4697 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4698 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
4699 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4700 "TARGET_POWERPC64 || TARGET_POWER"
4701 "
4702 {
4703 if (TARGET_POWERPC64)
4704 ;
4705 else if (TARGET_POWER)
4706 {
4707 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
4708 DONE;
4709 }
4710 else
4711 FAIL;
4712 }")
4714 (define_insn ""
4715 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4716 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4717 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4718 "TARGET_POWERPC64"
4719 "srd%I2 %0,%1,%H2")
4721 (define_insn ""
4722 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4723 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4724 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4725 (const_int 0)))
4726 (clobber (match_scratch:DI 3 "=r"))]
4727 "TARGET_POWERPC64"
4728 "srd%I2. %3,%1,%H2"
4729 [(set_attr "type" "delayed_compare")])
4731 (define_insn ""
4732 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4733 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4734 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4735 (const_int 0)))
4736 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4737 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
4738 "TARGET_POWERPC64"
4739 "srd%I2. %0,%1,%H2"
4740 [(set_attr "type" "delayed_compare")])
4742 (define_expand "ashrdi3"
4743 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4744 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
4745 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4746 "TARGET_POWERPC64 || TARGET_POWER"
4747 "
4748 {
4749 if (TARGET_POWERPC64)
4750 ;
4751 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
4752 {
4753 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
4754 DONE;
4755 }
4756 else
4757 FAIL;
4758 }")
4760 (define_insn ""
4761 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4762 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4763 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4764 "TARGET_POWERPC64"
4765 "srad%I2 %0,%1,%H2")
4767 (define_insn ""
4768 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4769 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4770 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4771 (const_int 0)))
4772 (clobber (match_scratch:DI 3 "=r"))]
4773 "TARGET_POWERPC64"
4774 "srad%I2. %3,%1,%H2"
4775 [(set_attr "type" "delayed_compare")])
4777 (define_insn ""
4778 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4779 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4780 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4781 (const_int 0)))
4782 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4783 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
4784 "TARGET_POWERPC64"
4785 "srad%I2. %0,%1,%H2"
4786 [(set_attr "type" "delayed_compare")])
4788 (define_insn "anddi3"
4789 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
4790 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
4791 (match_operand:DI 2 "and_operand" "?r,K,J")))
4792 (clobber (match_scratch:CC 3 "=X,x,x"))]
4793 "TARGET_POWERPC64"
4794 "@
4795 and %0,%1,%2
4796 andi. %0,%1,%b2
4797 andis. %0,%1,%u2")
4799 (define_insn ""
4800 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x")
4801 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
4802 (match_operand:DI 2 "and_operand" "r,K,J"))
4803 (const_int 0)))
4804 (clobber (match_scratch:DI 3 "=r,r,r"))]
4805 "TARGET_POWERPC64"
4806 "@
4807 and. %3,%1,%2
4808 andi. %3,%1,%b2
4809 andis. %3,%1,%u2"
4810 [(set_attr "type" "compare,compare,compare")])
4812 (define_insn ""
4813 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x")
4814 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
4815 (match_operand:DI 2 "and_operand" "r,K,J"))
4816 (const_int 0)))
4817 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
4818 (and:DI (match_dup 1) (match_dup 2)))]
4819 "TARGET_POWERPC64"
4820 "@
4821 and. %0,%1,%2
4822 andi. %0,%1,%b2
4823 andis. %0,%1,%u2"
4824 [(set_attr "type" "compare,compare,compare")])
4826 ;; Take a AND with a constant that cannot be done in a single insn and try to
4827 ;; split it into two insns. This does not verify that the insns are valid
4828 ;; since this need not be done as combine will do it.
4830 (define_split
4831 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4832 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
4833 (match_operand:DI 2 "non_and_cint_operand" "")))]
4834 "TARGET_POWERPC64"
4835 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
4836 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
4837 "
4838 {
4839 int maskval = INTVAL (operands[2]);
4840 int i, transitions, last_bit_value;
4841 int orig = maskval, first_c = maskval, second_c;
4843 /* We know that MASKVAL must have more than 2 bit-transitions. Start at
4844 the low-order bit and count for the third transition. When we get there,
4845 make a first mask that has everything to the left of that position
4846 a one. Then make the second mask to turn off whatever else is needed. */
4848 for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++)
4849 {
4850 if (((maskval >>= 1) & 1) != last_bit_value)
4851 last_bit_value ^= 1, transitions++;
4853 if (transitions > 2)
4854 {
4855 first_c |= (~0) << i;
4856 break;
4857 }
4858 }
4860 second_c = orig | ~ first_c;
4862 operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c);
4863 operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c);
4864 }")
4866 (define_insn "iordi3"
4867 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
4868 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
4869 (match_operand:DI 2 "logical_operand" "r,K,J")))]
4870 "TARGET_POWERPC64"
4871 "@
4872 or %0,%1,%2
4873 ori %0,%1,%b2
4874 oris %0,%1,%u2")
4876 (define_insn ""
4877 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4878 (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4879 (match_operand:DI 2 "gpc_reg_operand" "r"))
4880 (const_int 0)))
4881 (clobber (match_scratch:DI 3 "=r"))]
4882 "TARGET_POWERPC64"
4883 "or. %3,%1,%2"
4884 [(set_attr "type" "compare")])
4886 (define_insn ""
4887 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4888 (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4889 (match_operand:DI 2 "gpc_reg_operand" "r"))
4890 (const_int 0)))
4891 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4892 (ior:DI (match_dup 1) (match_dup 2)))]
4893 "TARGET_POWERPC64"
4894 "or. %0,%1,%2"
4895 [(set_attr "type" "compare")])
4897 ;; Split an IOR that we can't do in one insn into two insns, each of which
4898 ;; does one 16-bit part. This is used by combine.
4900 (define_split
4901 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4902 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
4903 (match_operand:DI 2 "non_logical_cint_operand" "")))]
4904 "TARGET_POWERPC64"
4905 [(set (match_dup 0) (ior:DI (match_dup 1) (match_dup 3)))
4906 (set (match_dup 0) (ior:DI (match_dup 0) (match_dup 4)))]
4907 "
4908 {
4909 operands[3] = gen_rtx (CONST_INT, VOIDmode,
4910 INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
4911 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
4912 }")
4914 (define_insn "xordi3"
4915 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
4916 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
4917 (match_operand:DI 2 "logical_operand" "r,K,J")))]
4918 "TARGET_POWERPC64"
4919 "@
4920 xor %0,%1,%2
4921 xori %0,%1,%b2
4922 xoris %0,%1,%u2")
4924 (define_insn ""
4925 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4926 (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4927 (match_operand:DI 2 "gpc_reg_operand" "r"))
4928 (const_int 0)))
4929 (clobber (match_scratch:DI 3 "=r"))]
4930 "TARGET_POWERPC64"
4931 "xor. %3,%1,%2"
4932 [(set_attr "type" "compare")])
4934 (define_insn ""
4935 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4936 (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4937 (match_operand:DI 2 "gpc_reg_operand" "r"))
4938 (const_int 0)))
4939 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4940 (xor:DI (match_dup 1) (match_dup 2)))]
4941 "TARGET_POWERPC64"
4942 "xor. %0,%1,%2"
4943 [(set_attr "type" "compare")])
4945 ;; Split an XOR that we can't do in one insn into two insns, each of which
4946 ;; does one 16-bit part. This is used by combine.
4948 (define_split
4949 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4950 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
4951 (match_operand:DI 2 "non_logical_cint_operand" "")))]
4952 "TARGET_POWERPC64"
4953 [(set (match_dup 0) (xor:DI (match_dup 1) (match_dup 3)))
4954 (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 4)))]
4955 "
4956 {
4957 operands[3] = gen_rtx (CONST_INT, VOIDmode,
4958 INTVAL (operands[2]) & 0xffff0000);
4959 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
4960 }")
4962 (define_insn ""
4963 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4964 (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4965 (match_operand:DI 2 "gpc_reg_operand" "r"))))]
4966 "TARGET_POWERPC64"
4967 "eqv %0,%1,%2")
4969 (define_insn ""
4970 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4971 (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4972 (match_operand:DI 2 "gpc_reg_operand" "r")))
4973 (const_int 0)))
4974 (clobber (match_scratch:DI 3 "=r"))]
4975 "TARGET_POWERPC64"
4976 "eqv. %3,%1,%2"
4977 [(set_attr "type" "compare")])
4979 (define_insn ""
4980 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4981 (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4982 (match_operand:DI 2 "gpc_reg_operand" "r")))
4983 (const_int 0)))
4984 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4985 (not:DI (xor:DI (match_dup 1) (match_dup 2))))]
4986 "TARGET_POWERPC64"
4987 "eqv. %0,%1,%2"
4988 [(set_attr "type" "compare")])
4990 (define_insn ""
4991 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4992 (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4993 (match_operand:DI 2 "gpc_reg_operand" "r")))]
4994 "TARGET_POWERPC64"
4995 "andc %0,%2,%1")
4997 (define_insn ""
4998 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4999 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
5000 (match_operand:DI 2 "gpc_reg_operand" "r"))
5001 (const_int 0)))
5002 (clobber (match_scratch:DI 3 "=r"))]
5003 "TARGET_POWERPC64"
5004 "andc. %3,%2,%1"
5005 [(set_attr "type" "compare")])
5007 (define_insn ""
5008 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5009 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
5010 (match_operand:DI 2 "gpc_reg_operand" "r"))
5011 (const_int 0)))
5012 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5013 (and:DI (not:DI (match_dup 1)) (match_dup 2)))]
5014 "TARGET_POWERPC64"
5015 "andc. %0,%2,%1"
5016 [(set_attr "type" "compare")])
5018 (define_insn ""
5019 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5020 (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
5021 (match_operand:DI 2 "gpc_reg_operand" "r")))]
5022 "TARGET_POWERPC64"
5023 "orc %0,%2,%1")
5025 (define_insn ""
5026 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5027 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
5028 (match_operand:DI 2 "gpc_reg_operand" "r"))
5029 (const_int 0)))
5030 (clobber (match_scratch:DI 3 "=r"))]
5031 "TARGET_POWERPC64"
5032 "orc. %3,%2,%1"
5033 [(set_attr "type" "compare")])
5035 (define_insn ""
5036 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5037 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
5038 (match_operand:DI 2 "gpc_reg_operand" "r"))
5039 (const_int 0)))
5040 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5041 (ior:DI (not:DI (match_dup 1)) (match_dup 2)))]
5042 "TARGET_POWERPC64"
5043 "orc. %0,%2,%1"
5044 [(set_attr "type" "compare")])
5046 (define_insn ""
5047 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5048 (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
5049 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))]
5050 "TARGET_POWERPC64"
5051 "nand %0,%1,%2")
5053 (define_insn ""
5054 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5055 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
5056 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
5057 (const_int 0)))
5058 (clobber (match_scratch:DI 3 "=r"))]
5059 "TARGET_POWERPC64"
5060 "nand. %3,%1,%2"
5061 [(set_attr "type" "compare")])
5063 (define_insn ""
5064 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5065 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
5066 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
5067 (const_int 0)))
5068 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5069 (ior:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))]
5070 "TARGET_POWERPC64"
5071 "nand. %0,%1,%2"
5072 [(set_attr "type" "compare")])
5074 (define_insn ""
5075 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5076 (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
5077 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))]
5078 "TARGET_POWERPC64"
5079 "nor %0,%1,%2")
5081 (define_insn ""
5082 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5083 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
5084 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
5085 (const_int 0)))
5086 (clobber (match_scratch:DI 3 "=r"))]
5087 "TARGET_POWERPC64"
5088 "nor. %3,%1,%2"
5089 [(set_attr "type" "compare")])
5091 (define_insn ""
5092 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5093 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
5094 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
5095 (const_int 0)))
5096 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5097 (and:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))]
5098 "TARGET_POWERPC64"
5099 "nor. %0,%1,%2"
5100 [(set_attr "type" "compare")])
5101 \f
5102 ;; Now define ways of moving data around.
5104 ;; Elf specific ways of loading addresses for non-PIC code.
5105 ;; The output of this could be r0, but we limit it to base
5106 ;; registers, since almost all uses of this will need it
5107 ;; in a base register shortly.
5108 (define_insn "elf_high"
5109 [(set (match_operand:SI 0 "register_operand" "=b")
5110 (high:SI (match_operand 1 "" "")))]
5111 "TARGET_ELF && !TARGET_64BIT"
5112 "{cau|addis} %0,0,%1@ha")
5114 (define_insn "elf_low"
5115 [(set (match_operand:SI 0 "register_operand" "=r")
5116 (lo_sum:SI (match_operand:SI 1 "register_operand" "b")
5117 (match_operand 2 "" "")))]
5118 "TARGET_ELF && !TARGET_64BIT"
5119 "{cal %0,%a2@l(%1)|addi %0,%1,%2@l}")
5121 ;; Set up a register with a value from the GOT table
5123 (define_expand "movsi_got"
5124 [(set (match_operand:SI 0 "register_operand" "")
5125 (unspec [(match_operand:SI 1 "got_operand" "")
5126 (match_dup 2)] 8))]
5127 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1"
5128 "
5129 {
5130 if (GET_CODE (operands[1]) == CONST)
5131 {
5132 rtx offset = const0_rtx;
5133 HOST_WIDE_INT value;
5135 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
5136 value = INTVAL (offset);
5137 if (value != 0)
5138 {
5139 rtx tmp = ((reload_in_progress || reload_completed)
5140 ? operands[0]
5141 : gen_reg_rtx (Pmode));
5142 emit_insn (gen_movsi_got (tmp, operands[1]));
5143 emit_insn (gen_addsi3 (operands[0], tmp, offset));
5144 DONE;
5145 }
5146 }
5148 operands[2] = rs6000_got_register (operands[1]);
5149 }")
5151 (define_insn "*movsi_got_internal"
5152 [(set (match_operand:SI 0 "register_operand" "=r")
5153 (unspec [(match_operand:SI 1 "got_no_const_operand" "")
5154 (match_operand:SI 2 "register_operand" "b")] 8))]
5155 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1"
5156 "{l|lwz} %0,%a1@got(%2)"
5157 [(set_attr "type" "load")])
5159 ;; Sometimes, though, the GOT `register' will be on the stack. Deal with
5160 ;; this case specially.
5161 ;; Force final to split this insn (if it hasn't been split already) to
5162 ;; avoid having to create a suitable output template.
5163 (define_insn "*movsi_got_internal_mem"
5164 [(set (match_operand:SI 0 "register_operand" "=r")
5165 (unspec [(match_operand:SI 1 "got_no_const_operand" "")
5166 (match_operand:SI 2 "memory_operand" "m")] 8))]
5167 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
5168 && flag_pic == 1
5169 && (reload_in_progress || reload_completed)"
5170 "#"
5171 [(set_attr "type" "load")
5172 (set_attr "length" "8")])
5174 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
5175 ;; didn't get allocated to a hard register.
5176 (define_split
5177 [(set (match_operand:SI 0 "register_operand" "=r")
5178 (unspec [(match_operand:SI 1 "got_no_const_operand" "")
5179 (match_operand:SI 2 "memory_operand" "m")] 8))]
5180 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
5181 && flag_pic == 1
5182 && (reload_in_progress || reload_completed)"
5183 [(set (match_dup 0) (match_dup 2))
5184 (set (match_dup 0) (unspec [(match_dup 1)(match_dup 0)] 8))]
5185 "")
5187 ;; For SI, we special-case integers that can't be loaded in one insn. We
5188 ;; do the load 16-bits at a time. We could do this by loading from memory,
5189 ;; and this is even supposed to be faster, but it is simpler not to get
5190 ;; integers in the TOC.
5191 (define_expand "movsi"
5192 [(set (match_operand:SI 0 "general_operand" "")
5193 (match_operand:SI 1 "any_operand" ""))]
5194 ""
5195 "
5196 {
5197 if (GET_CODE (operands[0]) != REG)
5198 operands[1] = force_reg (SImode, operands[1]);
5200 /* Convert a move of a CONST_DOUBLE into a CONST_INT */
5201 if (GET_CODE (operands[1]) == CONST_DOUBLE)
5202 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
5204 /* Use default pattern for address of ELF small data */
5205 if (TARGET_ELF
5206 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
5207 && (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
5208 && small_data_operand (operands[1], SImode))
5209 {
5210 emit_insn (gen_rtx (SET, VOIDmode, operands[0], operands[1]));
5211 DONE;
5212 }
5214 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
5215 && flag_pic == 1 && got_operand (operands[1], SImode))
5216 {
5217 emit_insn (gen_movsi_got (operands[0], operands[1]));
5218 DONE;
5219 }
5221 if (TARGET_ELF && TARGET_NO_TOC && !TARGET_64BIT
5222 && !flag_pic
5223 && CONSTANT_P (operands[1])
5224 && GET_CODE (operands[1]) != HIGH
5225 && GET_CODE (operands[1]) != CONST_INT)
5226 {
5227 rtx target = (reload_completed || reload_in_progress)
5228 ? operands[0] : gen_reg_rtx (SImode);
5230 /* If this is a function address on -mcall-aixdesc or -mcall-nt,
5231 convert it to the address of the descriptor. */
5232 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
5233 && GET_CODE (operands[1]) == SYMBOL_REF
5234 && XSTR (operands[1], 0)[0] == '.')
5235 {
5236 char *name = XSTR (operands[1], 0);
5237 rtx new_ref;
5238 while (*name == '.')
5239 name++;
5240 new_ref = gen_rtx (SYMBOL_REF, Pmode, name);
5241 CONSTANT_POOL_ADDRESS_P (new_ref) = CONSTANT_POOL_ADDRESS_P (operands[1]);
5242 SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]);
5243 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
5244 operands[1] = new_ref;
5245 }
5247 emit_insn (gen_elf_high (target, operands[1]));
5248 emit_insn (gen_elf_low (operands[0], target, operands[1]));
5249 DONE;
5250 }
5252 if (GET_CODE (operands[1]) == CONST
5253 && DEFAULT_ABI == ABI_NT
5254 && !side_effects_p (operands[0]))
5255 {
5256 rtx const_term = const0_rtx;
5257 rtx sym = eliminate_constant_term (XEXP (operands[1], 0), &const_term);
5258 if (sym && GET_CODE (const_term) == CONST_INT
5259 && (GET_CODE (sym) == SYMBOL_REF || GET_CODE (sym) == LABEL_REF))
5260 {
5261 unsigned HOST_WIDE_INT value = INTVAL (const_term);
5262 int new_reg_p = (flag_expensive_optimizations
5263 && !reload_completed
5264 && !reload_in_progress);
5265 rtx tmp1 = (new_reg_p && value != 0) ? gen_reg_rtx (SImode) : operands[0];
5267 emit_insn (gen_movsi (tmp1, sym));
5268 if (INTVAL (const_term) != 0)
5269 emit_insn (gen_addsi3 (operands[0], tmp1, GEN_INT (value)));
5270 DONE;
5271 }
5272 else
5273 fatal_insn (\"bad address\", operands[1]);
5274 }
5276 if ((!TARGET_WINDOWS_NT || DEFAULT_ABI != ABI_NT)
5277 && CONSTANT_P (operands[1])
5278 && GET_CODE (operands[1]) != CONST_INT
5279 && GET_CODE (operands[1]) != HIGH
5280 && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]))
5281 {
5282 /* Emit a USE operation so that the constant isn't deleted if
5283 expensive optimizations are turned on because nobody
5284 references it. This should only be done for operands that
5285 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
5286 This should not be done for operands that contain LABEL_REFs.
5287 For now, we just handle the obvious case. */
5288 if (GET_CODE (operands[1]) != LABEL_REF)
5289 emit_insn (gen_rtx (USE, VOIDmode, operands[1]));
5291 /* If we are to limit the number of things we put in the TOC and
5292 this is a symbol plus a constant we can add in one insn,
5293 just put the symbol in the TOC and add the constant. Don't do
5294 this if reload is in progress. */
5295 if (GET_CODE (operands[1]) == CONST
5296 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
5297 && GET_CODE (XEXP (operands[1], 0)) == PLUS
5298 && add_operand (XEXP (XEXP (operands[1], 0), 1), SImode)
5299 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
5300 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
5301 && ! side_effects_p (operands[0]))
5302 {
5303 rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[1], 0), 0));
5304 rtx other = XEXP (XEXP (operands[1], 0), 1);
5306 emit_insn (gen_addsi3 (operands[0], force_reg (SImode, sym), other));
5307 DONE;
5308 }
5310 operands[1] = force_const_mem (SImode, operands[1]);
5311 if (! memory_address_p (SImode, XEXP (operands[1], 0))
5312 && ! reload_in_progress)
5313 operands[1] = change_address (operands[1], SImode,
5314 XEXP (operands[1], 0));
5315 }
5316 }")
5318 (define_insn ""
5319 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
5320 (match_operand:SI 1 "input_operand" "r,S,T,U,m,r,I,J,n,R,*h,r,r,0"))]
5321 "gpc_reg_operand (operands[0], SImode)
5322 || gpc_reg_operand (operands[1], SImode)"
5323 "@
5324 mr %0,%1
5325 {l|lwz} %0,[toc]%1(2)
5326 {l|lwz} %0,[toc]%l1(2)
5327 {cal|la} %0,%a1
5328 {l%U1%X1|lwz%U1%X1} %0,%1
5329 {st%U0%X0|stw%U0%X0} %1,%0
5330 {lil|li} %0,%1
5331 {liu|lis} %0,%v1
5332 #
5333 {cal|la} %0,%1(%*)
5334 mf%1 %0
5335 mt%0 %1
5336 mt%0 %1
5337 cror 0,0,0"
5338 [(set_attr "type" "*,load,load,*,load,store,*,*,*,*,*,*,mtjmpr,*")
5339 (set_attr "length" "4,4,4,4,4,4,4,4,8,4,4,4,4,4")])
5341 ;; Split a load of a large constant into the appropriate two-insn
5342 ;; sequence.
5344 (define_split
5345 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5346 (match_operand:SI 1 "const_int_operand" ""))]
5347 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
5348 && (INTVAL (operands[1]) & 0xffff) != 0"
5349 [(set (match_dup 0)
5350 (match_dup 2))
5351 (set (match_dup 0)
5352 (ior:SI (match_dup 0)
5353 (match_dup 3)))]
5354 "
5355 {
5356 operands[2] = gen_rtx (CONST_INT, VOIDmode,
5357 INTVAL (operands[1]) & 0xffff0000);
5358 operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff);
5359 }")
5361 (define_insn ""
5362 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
5363 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
5364 (const_int 0)))
5365 (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
5366 ""
5367 "mr. %0,%1"
5368 [(set_attr "type" "compare")])
5369 \f
5370 (define_expand "movhi"
5371 [(set (match_operand:HI 0 "general_operand" "")
5372 (match_operand:HI 1 "any_operand" ""))]
5373 ""
5374 "
5375 {
5376 if (GET_CODE (operands[0]) != REG)
5377 operands[1] = force_reg (HImode, operands[1]);
5379 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
5380 {
5381 operands[1] = force_const_mem (HImode, operands[1]);
5382 if (! memory_address_p (HImode, XEXP (operands[1], 0))
5383 && ! reload_in_progress)
5384 operands[1] = change_address (operands[1], HImode,
5385 XEXP (operands[1], 0));
5386 }
5387 }")
5389 (define_insn ""
5390 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
5391 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
5392 "gpc_reg_operand (operands[0], HImode)
5393 || gpc_reg_operand (operands[1], HImode)"
5394 "@
5395 mr %0,%1
5396 lhz%U1%X1 %0,%1
5397 sth%U0%X0 %1,%0
5398 {lil|li} %0,%w1
5399 mf%1 %0
5400 mt%0 %1
5401 mt%0 %1
5402 cror 0,0,0"
5403 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
5405 (define_expand "movqi"
5406 [(set (match_operand:QI 0 "general_operand" "")
5407 (match_operand:QI 1 "any_operand" ""))]
5408 ""
5409 "
5410 {
5411 if (GET_CODE (operands[0]) != REG)
5412 operands[1] = force_reg (QImode, operands[1]);
5414 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
5415 {
5416 operands[1] = force_const_mem (QImode, operands[1]);
5417 if (! memory_address_p (QImode, XEXP (operands[1], 0))
5418 && ! reload_in_progress)
5419 operands[1] = change_address (operands[1], QImode,
5420 XEXP (operands[1], 0));
5421 }
5422 }")
5424 (define_insn ""
5425 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
5426 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
5427 "gpc_reg_operand (operands[0], QImode)
5428 || gpc_reg_operand (operands[1], QImode)"
5429 "@
5430 mr %0,%1
5431 lbz%U1%X1 %0,%1
5432 stb%U0%X0 %1,%0
5433 {lil|li} %0,%1
5434 mf%1 %0
5435 mt%0 %1
5436 mt%0 %1
5437 cror 0,0,0"
5438 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
5439 \f
5440 ;; Here is how to move condition codes around. When we store CC data in
5441 ;; an integer register or memory, we store just the high-order 4 bits.
5442 ;; This lets us not shift in the most common case of CR0.
5443 (define_expand "movcc"
5444 [(set (match_operand:CC 0 "nonimmediate_operand" "")
5445 (match_operand:CC 1 "nonimmediate_operand" ""))]
5446 ""
5447 "")
5449 (define_insn ""
5450 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
5451 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
5452 "register_operand (operands[0], CCmode)
5453 || register_operand (operands[1], CCmode)"
5454 "@
5455 mcrf %0,%1
5456 mtcrf 128,%1
5457 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
5458 mfcr %0
5459 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
5460 mr %0,%1
5461 {l%U1%X1|lwz%U1%X1} %0,%1
5462 {st%U0%U1|stw%U0%U1} %1,%0"
5463 [(set_attr "type" "*,*,*,compare,*,*,load,store")
5464 (set_attr "length" "*,*,12,*,8,*,*,*")])
5465 \f
5466 ;; For floating-point, we normally deal with the floating-point registers
5467 ;; unless -msoft-float is used. The sole exception is that parameter passing
5468 ;; can produce floating-point values in fixed-point registers. Unless the
5469 ;; value is a simple constant or already in memory, we deal with this by
5470 ;; allocating memory and copying the value explicitly via that memory location.
5471 (define_expand "movsf"
5472 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5473 (match_operand:SF 1 "any_operand" ""))]
5474 ""
5475 "
5476 {
5477 /* If we are called from reload, we might be getting a SUBREG of a hard
5478 reg. So expand it. */
5479 if (GET_CODE (operands[0]) == SUBREG
5480 && GET_CODE (SUBREG_REG (operands[0])) == REG
5481 && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
5482 operands[0] = alter_subreg (operands[0]);
5483 if (GET_CODE (operands[1]) == SUBREG
5484 && GET_CODE (SUBREG_REG (operands[1])) == REG
5485 && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
5486 operands[1] = alter_subreg (operands[1]);
5488 if (TARGET_SOFT_FLOAT && GET_CODE (operands[0]) == MEM)
5489 operands[1] = force_reg (SFmode, operands[1]);
5491 else if (TARGET_HARD_FLOAT)
5492 {
5493 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
5494 {
5495 /* If this is a store to memory or another integer register do the
5496 move directly. Otherwise store to a temporary stack slot and
5497 load from there into a floating point register. */
5499 if (GET_CODE (operands[0]) == MEM
5500 || (GET_CODE (operands[0]) == REG
5501 && (REGNO (operands[0]) < 32
5502 || (reload_in_progress
5503 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))))
5504 {
5505 emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
5506 operand_subword (operands[1], 0, 0, SFmode));
5507 DONE;
5508 }
5509 else
5510 {
5511 rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
5513 emit_move_insn (stack_slot, operands[1]);
5514 emit_move_insn (operands[0], stack_slot);
5515 DONE;
5516 }
5517 }
5519 if (GET_CODE (operands[0]) == MEM)
5520 {
5521 /* If operands[1] is a register, it may have double-precision data
5522 in it, so truncate it to single precision. We need not do
5523 this for POWERPC. */
5524 if (! TARGET_POWERPC && TARGET_HARD_FLOAT
5525 && GET_CODE (operands[1]) == REG)
5526 {
5527 rtx newreg
5528 = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
5529 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
5530 operands[1] = newreg;
5531 }
5533 operands[1] = force_reg (SFmode, operands[1]);
5534 }
5536 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
5537 {
5538 if (GET_CODE (operands[1]) == MEM
5539 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
5540 || GET_CODE (operands[1]) == CONST_DOUBLE
5541 #endif
5542 || (GET_CODE (operands[1]) == REG
5543 && (REGNO (operands[1]) < 32
5544 || (reload_in_progress
5545 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))))
5546 {
5547 emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
5548 operand_subword (operands[1], 0, 0, SFmode));
5549 DONE;
5550 }
5551 else
5552 {
5553 rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
5555 emit_move_insn (stack_slot, operands[1]);
5556 emit_move_insn (operands[0], stack_slot);
5557 DONE;
5558 }
5559 }
5560 }
5562 if (CONSTANT_P (operands[1]) && TARGET_HARD_FLOAT)
5563 {
5564 operands[1] = force_const_mem (SFmode, operands[1]);
5565 if (! memory_address_p (SFmode, XEXP (operands[1], 0))
5566 && ! reload_in_progress)
5567 operands[1] = change_address (operands[1], SFmode,
5568 XEXP (operands[1], 0));
5569 }
5570 }")
5572 (define_split
5573 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5574 (match_operand:SF 1 "const_double_operand" ""))]
5575 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], SFmode) <= 1
5576 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
5577 || (GET_CODE (operands[0]) == SUBREG
5578 && GET_CODE (SUBREG_REG (operands[0])) == REG
5579 && REGNO (SUBREG_REG (operands[0])) <= 31))"
5580 [(set (match_dup 2) (match_dup 3))]
5581 "
5582 {
5583 long l;
5584 REAL_VALUE_TYPE rv;
5586 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
5587 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5589 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
5590 operands[3] = GEN_INT(l);
5591 }")
5593 (define_split
5594 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5595 (match_operand:SF 1 "const_double_operand" ""))]
5596 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], SFmode) == 2
5597 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
5598 || (GET_CODE (operands[0]) == SUBREG
5599 && GET_CODE (SUBREG_REG (operands[0])) == REG
5600 && REGNO (SUBREG_REG (operands[0])) <= 31))"
5601 [(set (match_dup 2) (match_dup 3))
5602 (set (match_dup 2) (ior:SI (match_dup 2) (match_dup 4)))]
5603 "
5604 {
5605 long l;
5606 REAL_VALUE_TYPE rv;
5608 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
5609 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5611 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
5612 operands[3] = GEN_INT(l & 0xffff0000);
5613 operands[4] = GEN_INT(l & 0x0000ffff);
5614 }")
5616 (define_insn "*movsf_hardfloat"
5617 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,!r,!r")
5618 (match_operand:SF 1 "input_operand" "f,m,f,G,Fn"))]
5619 "(gpc_reg_operand (operands[0], SFmode)
5620 || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT"
5621 "@
5622 fmr %0,%1
5623 lfs%U1%X1 %0,%1
5624 stfs%U0%X0 %1,%0
5625 #
5626 #"
5627 [(set_attr "type" "fp,fpload,fpstore,*,*")
5628 (set_attr "length" "4,4,4,4,8")])
5630 (define_insn "*movsf_softfloat"
5631 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r")
5632 (match_operand:SF 1 "input_operand" "r,m,r,I,J,R,G,Fn"))]
5633 "(gpc_reg_operand (operands[0], SFmode)
5634 || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT"
5635 "@
5636 mr %0,%1
5637 {l%U1%X1|lwz%U1%X1} %0,%1
5638 {st%U0%X0|stw%U0%X0} %1,%0
5639 {lil|li} %0,%1
5640 {liu|lis} %0,%v1
5641 {cal|la} %0,%1(%*)
5642 #
5643 #"
5644 [(set_attr "type" "*,load,store,*,*,*,*,*")
5645 (set_attr "length" "4,4,4,4,4,4,4,8")])
5647 \f
5648 (define_expand "movdf"
5649 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5650 (match_operand:DF 1 "any_operand" ""))]
5651 ""
5652 "
5653 {
5654 if (GET_CODE (operands[0]) != REG)
5655 operands[1] = force_reg (DFmode, operands[1]);
5657 /* Stores between FPR and any non-FPR registers must go through a
5658 temporary stack slot. */
5660 if (TARGET_POWERPC64
5661 && GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
5662 && ((FP_REGNO_P (REGNO (operands[0]))
5663 && ! FP_REGNO_P (REGNO (operands[1])))
5664 || (FP_REGNO_P (REGNO (operands[1]))
5665 && ! FP_REGNO_P (REGNO (operands[0])))))
5666 {
5667 rtx stack_slot = assign_stack_temp (DFmode, 8, 0);
5669 emit_move_insn (stack_slot, operands[1]);
5670 emit_move_insn (operands[0], stack_slot);
5671 DONE;
5672 }
5674 if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode))
5675 {
5676 operands[1] = force_const_mem (DFmode, operands[1]);
5677 if (! memory_address_p (DFmode, XEXP (operands[1], 0))
5678 && ! reload_in_progress)
5679 operands[1] = change_address (operands[1], DFmode,
5680 XEXP (operands[1], 0));
5681 }
5682 }")
5684 (define_split
5685 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5686 (match_operand:DF 1 "const_int_operand" ""))]
5687 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DFmode) <= 1
5688 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
5689 || (GET_CODE (operands[0]) == SUBREG
5690 && GET_CODE (SUBREG_REG (operands[0])) == REG
5691 && REGNO (SUBREG_REG (operands[0])) <= 31))"
5692 [(set (match_dup 2) (match_dup 4))
5693 (set (match_dup 3) (match_dup 1))]
5694 "
5695 {
5696 int endian = (WORDS_BIG_ENDIAN == 0);
5697 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
5698 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
5699 operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx;
5700 }")
5702 (define_split
5703 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5704 (match_operand:DF 1 "const_int_operand" ""))]
5705 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DFmode) >= 2
5706 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
5707 || (GET_CODE (operands[0]) == SUBREG
5708 && GET_CODE (SUBREG_REG (operands[0])) == REG
5709 && REGNO (SUBREG_REG (operands[0])) <= 31))"
5710 [(set (match_dup 3) (match_dup 5))
5711 (set (match_dup 2) (match_dup 4))
5712 (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 6)))]
5713 "
5714 {
5715 HOST_WIDE_INT value = INTVAL (operands[1]);
5716 int endian = (WORDS_BIG_ENDIAN == 0);
5717 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
5718 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
5719 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
5720 operands[5] = GEN_INT (value & 0xffff0000);
5721 operands[6] = GEN_INT (value & 0x0000ffff);
5722 }")
5724 (define_split
5725 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5726 (match_operand:DF 1 "const_double_operand" ""))]
5727 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DFmode) <= 2
5728 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
5729 || (GET_CODE (operands[0]) == SUBREG
5730 && GET_CODE (SUBREG_REG (operands[0])) == REG
5731 && REGNO (SUBREG_REG (operands[0])) <= 31))"
5732 [(set (match_dup 2) (match_dup 4))
5733 (set (match_dup 3) (match_dup 5))]
5734 "
5735 {
5736 int endian = (WORDS_BIG_ENDIAN == 0);
5737 long l[2];
5738 REAL_VALUE_TYPE rv;
5740 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
5741 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
5743 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
5744 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
5745 operands[4] = GEN_INT (l[endian]);
5746 operands[5] = GEN_INT (l[1 - endian]);
5747 }")
5749 (define_split
5750 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5751 (match_operand:DF 1 "const_double_operand" ""))]
5752 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DFmode) == 3
5753 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
5754 || (GET_CODE (operands[0]) == SUBREG
5755 && GET_CODE (SUBREG_REG (operands[0])) == REG
5756 && REGNO (SUBREG_REG (operands[0])) <= 31))"
5757 [(set (match_dup 2) (match_dup 4))
5758 (set (match_dup 3) (match_dup 5))
5759 (set (match_dup 2) (ior:SI (match_dup 2) (match_dup 6)))]
5760 "
5761 {
5762 HOST_WIDE_INT high;
5763 HOST_WIDE_INT low;
5764 int endian = (WORDS_BIG_ENDIAN == 0);
5765 long l[2];
5766 REAL_VALUE_TYPE rv;
5767 rtx high_reg = operand_subword (operands[0], endian, 0, DFmode);
5768 rtx low_reg = operand_subword (operands[0], 1 - endian, 0, DFmode);
5770 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
5771 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
5772 high = l[endian];
5773 low = l[1 - endian];
5775 if (((unsigned HOST_WIDE_INT) (low + 0x8000) < 0x10000)
5776 || (low & 0xffff) == 0)
5777 {
5778 operands[2] = high_reg;
5779 operands[3] = low_reg;
5780 operands[4] = GEN_INT (high & 0xffff0000);
5781 operands[5] = GEN_INT (low);
5782 operands[6] = GEN_INT (high & 0x0000ffff);
5783 }
5784 else
5785 {
5786 operands[2] = low_reg;
5787 operands[3] = high_reg;
5788 operands[4] = GEN_INT (low & 0xffff0000);
5789 operands[5] = GEN_INT (high);
5790 operands[6] = GEN_INT (low & 0x0000ffff);
5791 }
5792 }")
5794 (define_split
5795 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5796 (match_operand:DF 1 "const_double_operand" ""))]
5797 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DFmode) >= 4
5798 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
5799 || (GET_CODE (operands[0]) == SUBREG
5800 && GET_CODE (SUBREG_REG (operands[0])) == REG
5801 && REGNO (SUBREG_REG (operands[0])) <= 31))"
5802 [(set (match_dup 2) (match_dup 4))
5803 (set (match_dup 3) (match_dup 5))
5804 (set (match_dup 2) (ior:SI (match_dup 2) (match_dup 6)))
5805 (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 7)))]
5806 "
5807 {
5808 HOST_WIDE_INT high;
5809 HOST_WIDE_INT low;
5810 long l[2];
5811 REAL_VALUE_TYPE rv;
5812 int endian = (WORDS_BIG_ENDIAN == 0);
5814 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
5815 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
5816 high = l[endian];
5817 low = l[1 - endian];
5819 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
5820 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
5821 operands[4] = GEN_INT (high & 0xffff0000);
5822 operands[5] = GEN_INT (low & 0xffff0000);
5823 operands[6] = GEN_INT (high & 0x0000ffff);
5824 operands[7] = GEN_INT (low & 0x0000ffff);
5825 }")
5827 (define_split
5828 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5829 (match_operand:DF 1 "easy_fp_constant" ""))]
5830 "TARGET_64BIT && reload_completed
5831 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
5832 || (GET_CODE (operands[0]) == SUBREG
5833 && GET_CODE (SUBREG_REG (operands[0])) == REG
5834 && REGNO (SUBREG_REG (operands[0])) <= 31))"
5835 [(set (match_dup 2) (subreg:DI (match_dup 1) 0))]
5836 "
5837 { operands[2] = gen_lowpart (DImode, operands[0]); }")
5839 ;; Don't have reload use general registers to load a constant. First,
5840 ;; it might not work if the output operand has is the equivalent of
5841 ;; a non-offsettable memref, but also it is less efficient than loading
5842 ;; the constant into an FP register, since it will probably be used there.
5843 ;; The "??" is a kludge until we can figure out a more reasonable way
5844 ;; of handling these non-offsettable values.
5845 (define_insn "*movdf_hardfloat32"
5846 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,!r,!r,f,f,m")
5847 (match_operand:DF 1 "input_operand" "r,o,r,G,H,F,f,m,f"))]
5848 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT
5849 && (register_operand (operands[0], DFmode)
5850 || register_operand (operands[1], DFmode))"
5851 "*
5852 {
5853 switch (which_alternative)
5854 {
5855 case 0:
5856 /* We normally copy the low-numbered register first. However, if
5857 the first register operand 0 is the same as the second register of
5858 operand 1, we must copy in the opposite order. */
5859 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
5860 return \"mr %L0,%L1\;mr %0,%1\";
5861 else
5862 return \"mr %0,%1\;mr %L0,%L1\";
5863 case 1:
5864 /* If the low-address word is used in the address, we must load it
5865 last. Otherwise, load it first. Note that we cannot have
5866 auto-increment in that case since the address register is known to be
5867 dead. */
5868 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
5869 operands [1], 0))
5870 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
5871 else
5872 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
5873 case 2:
5874 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
5875 case 3:
5876 case 4:
5877 case 5:
5878 return \"#\";
5879 case 6:
5880 return \"fmr %0,%1\";
5881 case 7:
5882 return \"lfd%U1%X1 %0,%1\";
5883 case 8:
5884 return \"stfd%U0%X0 %1,%0\";
5885 }
5886 }"
5887 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
5888 (set_attr "length" "8,8,8,8,12,16,*,*,*")])
5890 (define_insn "*movdf_softfloat32"
5891 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r,r,r")
5892 (match_operand:DF 1 "input_operand" "r,o,r,G,H,F"))]
5893 "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT
5894 && (register_operand (operands[0], DFmode)
5895 || register_operand (operands[1], DFmode))"
5896 "*
5897 {
5898 switch (which_alternative)
5899 {
5900 case 0:
5901 /* We normally copy the low-numbered register first. However, if
5902 the first register operand 0 is the same as the second register of
5903 operand 1, we must copy in the opposite order. */
5904 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
5905 return \"mr %L0,%L1\;mr %0,%1\";
5906 else
5907 return \"mr %0,%1\;mr %L0,%L1\";
5908 case 1:
5909 /* If the low-address word is used in the address, we must load it
5910 last. Otherwise, load it first. Note that we cannot have
5911 auto-increment in that case since the address register is known to be
5912 dead. */
5913 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
5914 operands [1], 0))
5915 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
5916 else
5917 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
5918 case 2:
5919 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
5920 case 3:
5921 case 4:
5922 case 5:
5923 return \"#\";
5924 }
5925 }"
5926 [(set_attr "type" "*,load,store,*,*,*")
5927 (set_attr "length" "8,8,8,8,12,16")])
5929 (define_insn "*movdf_hardfloat64"
5930 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,!r,!r,f,f,m")
5931 (match_operand:DF 1 "input_operand" "r,o,r,G,H,F,f,m,f"))]
5932 "TARGET_POWERPC64 && TARGET_HARD_FLOAT
5933 && (register_operand (operands[0], DFmode)
5934 || register_operand (operands[1], DFmode))"
5935 "@
5936 mr %0,%1
5937 ld%U1%X1 %0,%1
5938 std%U0%X0 %1,%0
5939 #
5940 #
5941 #
5942 fmr %0,%1
5943 lfd%U1%X1 %0,%1
5944 stfd%U0%X0 %1,%0"
5945 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
5946 (set_attr "length" "4,4,4,8,12,16,4,4,4")])
5948 (define_insn "*movdf_softfloat64"
5949 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r,r,r")
5950 (match_operand:DF 1 "input_operand" "r,o,r,G,H,F"))]
5951 "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
5952 && (register_operand (operands[0], DFmode)
5953 || register_operand (operands[1], DFmode))"
5954 "@
5955 mr %0,%1
5956 ld%U1%X1 %0,%1
5957 std%U0%X0 %1,%0
5958 #
5959 #
5960 #"
5961 [(set_attr "type" "*,load,store,*,*,*")
5962 (set_attr "length" "*,*,*,8,12,16")])
5963 \f
5964 ;; Next come the multi-word integer load and store and the load and store
5965 ;; multiple insns.
5966 (define_expand "movdi"
5967 [(set (match_operand:DI 0 "general_operand" "")
5968 (match_operand:DI 1 "any_operand" ""))]
5969 ""
5970 "
5971 {
5972 if (GET_CODE (operands[0]) != REG)
5973 operands[1] = force_reg (DImode, operands[1]);
5975 if (TARGET_64BIT
5976 && (GET_CODE (operands[1]) == CONST_DOUBLE
5977 || GET_CODE (operands[1]) == CONST_INT))
5978 {
5979 HOST_WIDE_INT low;
5980 HOST_WIDE_INT high;
5982 if (GET_CODE (operands[1]) == CONST_DOUBLE)
5983 {
5984 low = CONST_DOUBLE_LOW (operands[1]);
5985 high = CONST_DOUBLE_HIGH (operands[1]);
5986 }
5987 else
5988 #if HOST_BITS_PER_WIDE_INT == 32
5989 {
5990 low = INTVAL (operands[1]);
5991 high = (low < 0) ? ~0 : 0;
5992 }
5993 #else
5994 {
5995 low = INTVAL (operands[1]) & 0xffffffff;
5996 high = (HOST_WIDE_INT) INTVAL (operands[1]) >> 32;
5997 }
5998 #endif
6000 if (high)
6001 {
6002 emit_move_insn (operands[0], GEN_INT (high));
6003 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT(32)));
6004 if (low)
6005 {
6006 HOST_WIDE_INT low_low = low & 0xffff;
6007 HOST_WIDE_INT low_high = low & (~ (HOST_WIDE_INT) 0xffff);
6008 if (low_high)
6009 emit_insn (gen_iordi3 (operands[0], operands[0],
6010 GEN_INT (low_high)));
6011 if (low_low)
6012 emit_insn (gen_iordi3 (operands[0], operands[0],
6013 GEN_INT (low_low)));
6014 }
6015 DONE;
6016 }
6017 }
6019 /* Stores between FPR and any non-FPR registers must go through a
6020 temporary stack slot. */
6022 if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
6023 && ((FP_REGNO_P (REGNO (operands[0]))
6024 && ! FP_REGNO_P (REGNO (operands[1])))
6025 || (FP_REGNO_P (REGNO (operands[1]))
6026 && ! FP_REGNO_P (REGNO (operands[0])))))
6027 {
6028 rtx stack_slot = assign_stack_temp (DImode, 8, 0);
6030 emit_move_insn (stack_slot, operands[1]);
6031 emit_move_insn (operands[0], stack_slot);
6032 DONE;
6033 }
6034 }")
6036 (define_insn "*movdi_32"
6037 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
6038 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
6039 "TARGET_32BIT
6040 && (gpc_reg_operand (operands[0], DImode)
6041 || gpc_reg_operand (operands[1], DImode))"
6042 "*
6043 {
6044 switch (which_alternative)
6045 {
6046 case 0:
6047 /* We normally copy the low-numbered register first. However, if
6048 the first register operand 0 is the same as the second register of
6049 operand 1, we must copy in the opposite order. */
6050 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
6051 return \"mr %L0,%L1\;mr %0,%1\";
6052 else
6053 return \"mr %0,%1\;mr %L0,%L1\";
6054 case 1:
6055 /* If the low-address word is used in the address, we must load it
6056 last. Otherwise, load it first. Note that we cannot have
6057 auto-increment in that case since the address register is known to be
6058 dead. */
6059 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
6060 operands [1], 0))
6061 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
6062 else
6063 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
6064 case 2:
6065 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
6066 case 3:
6067 return \"fmr %0,%1\";
6068 case 4:
6069 return \"lfd%U1%X1 %0,%1\";
6070 case 5:
6071 return \"stfd%U0%X0 %1,%0\";
6072 case 6:
6073 case 7:
6074 case 8:
6075 case 9:
6076 case 10:
6077 return \"#\";
6078 }
6079 }"
6080 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")
6081 (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")])
6083 (define_split
6084 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6085 (match_operand:DI 1 "const_int_operand" ""))]
6086 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DImode) <= 1"
6087 [(set (match_dup 2) (match_dup 4))
6088 (set (match_dup 3) (match_dup 1))]
6089 "
6090 {
6091 operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
6092 operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
6093 operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx;
6094 }")
6096 (define_split
6097 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6098 (match_operand:DI 1 "const_int_operand" ""))]
6099 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DImode) >= 2"
6100 [(set (match_dup 3) (match_dup 5))
6101 (set (match_dup 2) (match_dup 4))
6102 (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 6)))]
6103 "
6104 {
6105 HOST_WIDE_INT value = INTVAL (operands[1]);
6106 operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
6107 operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
6108 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
6109 operands[5] = GEN_INT (value & 0xffff0000);
6110 operands[6] = GEN_INT (value & 0x0000ffff);
6111 }")
6113 (define_split
6114 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6115 (match_operand:DI 1 "const_double_operand" ""))]
6116 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DImode) <= 2"
6117 [(set (match_dup 2) (match_dup 4))
6118 (set (match_dup 3) (match_dup 5))]
6119 "
6120 {
6121 operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
6122 operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
6123 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
6124 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
6125 }")
6127 (define_split
6128 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6129 (match_operand:DI 1 "const_double_operand" ""))]
6130 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DImode) == 3"
6131 [(set (match_dup 2) (match_dup 4))
6132 (set (match_dup 3) (match_dup 5))
6133 (set (match_dup 2) (ior:SI (match_dup 2) (match_dup 6)))]
6134 "
6135 {
6136 HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[1]);
6137 HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[1]);
6138 rtx high_reg = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
6139 rtx low_reg = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
6141 if (((unsigned HOST_WIDE_INT) (low + 0x8000) < 0x10000)
6142 || (low & 0xffff) == 0)
6143 {
6144 operands[2] = high_reg;
6145 operands[3] = low_reg;
6146 operands[4] = GEN_INT (high & 0xffff0000);
6147 operands[5] = GEN_INT (low);
6148 operands[6] = GEN_INT (high & 0x0000ffff);
6149 }
6150 else
6151 {
6152 operands[2] = low_reg;
6153 operands[3] = high_reg;
6154 operands[4] = GEN_INT (low & 0xffff0000);
6155 operands[5] = GEN_INT (high);
6156 operands[6] = GEN_INT (low & 0x0000ffff);
6157 }
6158 }")
6160 (define_split
6161 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6162 (match_operand:DI 1 "const_double_operand" ""))]
6163 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DImode) >= 4"
6164 [(set (match_dup 2) (match_dup 4))
6165 (set (match_dup 3) (match_dup 5))
6166 (set (match_dup 2) (ior:SI (match_dup 2) (match_dup 6)))
6167 (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 7)))]
6168 "
6169 {
6170 HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[1]);
6171 HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[1]);
6173 operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
6174 operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
6175 operands[4] = GEN_INT (high & 0xffff0000);
6176 operands[5] = GEN_INT (low & 0xffff0000);
6177 operands[6] = GEN_INT (high & 0x0000ffff);
6178 operands[7] = GEN_INT (low & 0x0000ffff);
6179 }")
6181 (define_insn "*movdi_64"
6182 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
6183 (match_operand:DI 1 "input_operand" "r,m,r,I,J,nF,R,f,m,f,*h,r,0"))]
6184 "TARGET_64BIT
6185 && (gpc_reg_operand (operands[0], DImode)
6186 || gpc_reg_operand (operands[1], DImode))"
6187 "@
6188 mr %0,%1
6189 ld%U1%X1 %0,%1
6190 std%U0%X0 %1,%0
6191 li %0,%1
6192 lis %0,%v1
6193 #
6194 {cal|la} %0,%1(%*)
6195 fmr %0,%1
6196 lfd%U1%X1 %0,%1
6197 stfd%U0%X0 %1,%0
6198 mf%1 %0
6199 mt%0 %1
6200 cror 0,0,0"
6201 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*")
6202 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
6204 ;; Split a load of a large constant into the appropriate five-instruction
6205 ;; sequence. The expansion in movdi tries to perform the minimum number of
6206 ;; steps, but here we have to handle anything in a constant number of insns.
6208 (define_split
6209 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6210 (match_operand:DI 1 "const_double_operand" ""))]
6211 "TARGET_64BIT && num_insns_constant (operands[1], DImode) > 1"
6212 [(set (match_dup 0)
6213 (match_dup 2))
6214 (set (match_dup 0)
6215 (ior:DI (match_dup 0)
6216 (match_dup 3)))
6217 (set (match_dup 0)
6218 (ashift:DI (match_dup 0)
6219 (const_int 32)))
6220 (set (match_dup 0)
6221 (ior:DI (match_dup 0)
6222 (match_dup 4)))
6223 (set (match_dup 0)
6224 (ior:DI (match_dup 0)
6225 (match_dup 5)))]
6226 "
6227 {
6228 HOST_WIDE_INT low;
6229 HOST_WIDE_INT high;
6231 if (GET_CODE (operands[1]) == CONST_DOUBLE)
6232 {
6233 low = CONST_DOUBLE_LOW (operands[1]);
6234 high = CONST_DOUBLE_HIGH (operands[1]);
6235 }
6236 else
6237 #if HOST_BITS_PER_WIDE_INT == 32
6238 {
6239 low = INTVAL (operands[1]);
6240 high = (low < 0) ? ~0 : 0;
6241 }
6242 #else
6243 {
6244 low = INTVAL (operands[1]) & 0xffffffff;
6245 high = (HOST_WIDE_INT) INTVAL (operands[1]) >> 32;
6246 }
6247 #endif
6249 if ((high + 0x8000) < 0x10000
6250 && ((low & 0xffff) == 0 || (low & (~ (HOST_WIDE_INT) 0xffff)) == 0))
6251 FAIL;
6253 operands[2] = GEN_INT (high & (~ (HOST_WIDE_INT) 0xffff));
6254 operands[3] = GEN_INT (high & 0xffff);
6255 operands[4] = GEN_INT (low & (~ (HOST_WIDE_INT) 0xffff));
6256 operands[5] = GEN_INT (low & 0xffff);
6257 }")
6259 (define_insn ""
6260 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
6261 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
6262 (const_int 0)))
6263 (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
6264 "TARGET_POWERPC64"
6265 "mr. %0,%1"
6266 [(set_attr "type" "compare")])
6267 \f
6268 ;; TImode is similar, except that we usually want to compute the address into
6269 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
6270 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
6271 (define_expand "movti"
6272 [(parallel [(set (match_operand:TI 0 "general_operand" "")
6273 (match_operand:TI 1 "general_operand" ""))
6274 (clobber (scratch:SI))])]
6275 "TARGET_STRING || TARGET_POWERPC64"
6276 "
6277 {
6278 if (GET_CODE (operands[0]) == MEM)
6279 operands[1] = force_reg (TImode, operands[1]);
6281 if (GET_CODE (operands[0]) == MEM
6282 && GET_CODE (XEXP (operands[0], 0)) != REG
6283 && ! reload_in_progress)
6284 operands[0] = change_address (operands[0], TImode,
6285 copy_addr_to_reg (XEXP (operands[0], 0)));
6287 if (GET_CODE (operands[1]) == MEM
6288 && GET_CODE (XEXP (operands[1], 0)) != REG
6289 && ! reload_in_progress)
6290 operands[1] = change_address (operands[1], TImode,
6291 copy_addr_to_reg (XEXP (operands[1], 0)));
6292 }")
6294 ;; We say that MQ is clobbered in the last alternative because the first
6295 ;; alternative would never get used otherwise since it would need a reload
6296 ;; while the 2nd alternative would not. We put memory cases first so they
6297 ;; are preferred. Otherwise, we'd try to reload the output instead of
6298 ;; giving the SCRATCH mq.
6299 (define_insn ""
6300 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
6301 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
6302 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
6303 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
6304 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
6305 "*
6306 {
6307 switch (which_alternative)
6308 {
6309 default:
6310 abort ();
6312 case 0:
6313 return \"{stsi|stswi} %1,%P0,16\";
6315 case 1:
6316 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
6318 case 2:
6319 /* Normally copy registers with lowest numbered register copied first.
6320 But copy in the other order if the first register of the output
6321 is the second, third, or fourth register in the input. */
6322 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
6323 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
6324 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
6325 else
6326 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
6327 case 3:
6328 /* If the address is not used in the output, we can use lsi. Otherwise,
6329 fall through to generating four loads. */
6330 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
6331 return \"{lsi|lswi} %0,%P1,16\";
6332 /* ... fall through ... */
6333 case 4:
6334 /* If the address register is the same as the register for the lowest-
6335 addressed word, load it last. Similarly for the next two words.
6336 Otherwise load lowest address to highest. */
6337 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
6338 operands[1], 0))
6339 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
6340 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
6341 REGNO (operands[0]) + 2, operands[1], 0))
6342 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
6343 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
6344 REGNO (operands[0]) + 3, operands[1], 0))
6345 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
6346 else
6347 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
6348 }
6349 }"
6350 [(set_attr "type" "store,store,*,load,load")
6351 (set_attr "length" "*,16,16,*,16")])
6353 (define_insn ""
6354 [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r")
6355 (match_operand:TI 1 "reg_or_mem_operand" "r,r,m"))
6356 (clobber (match_scratch:SI 2 "=X,X,X"))]
6357 "TARGET_STRING && !TARGET_POWER && ! TARGET_POWERPC64
6358 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
6359 "*
6360 {
6361 switch (which_alternative)
6362 {
6363 default:
6364 abort ();
6366 case 0:
6367 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
6369 case 1:
6370 /* Normally copy registers with lowest numbered register copied first.
6371 But copy in the other order if the first register of the output
6372 is the second, third, or fourth register in the input. */
6373 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
6374 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
6375 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
6376 else
6377 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
6378 case 2:
6379 /* If the address register is the same as the register for the lowest-
6380 addressed word, load it last. Similarly for the next two words.
6381 Otherwise load lowest address to highest. */
6382 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
6383 operands[1], 0))
6384 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
6385 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
6386 REGNO (operands[0]) + 2, operands[1], 0))
6387 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
6388 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
6389 REGNO (operands[0]) + 3, operands[1], 0))
6390 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
6391 else
6392 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
6393 }
6394 }"
6395 [(set_attr "type" "store,*,load")
6396 (set_attr "length" "16,16,16")])
6398 (define_insn ""
6399 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
6400 (match_operand:TI 1 "input_operand" "r,m,r"))]
6401 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
6402 || gpc_reg_operand (operands[1], TImode))"
6403 "*
6404 {
6405 switch (which_alternative)
6406 {
6407 case 0:
6408 /* We normally copy the low-numbered register first. However, if
6409 the first register operand 0 is the same as the second register of
6410 operand 1, we must copy in the opposite order. */
6411 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
6412 return \"mr %L0,%L1\;mr %0,%1\";
6413 else
6414 return \"mr %0,%1\;mr %L0,%L1\";
6415 case 1:
6416 /* If the low-address word is used in the address, we must load it
6417 last. Otherwise, load it first. Note that we cannot have
6418 auto-increment in that case since the address register is known to be
6419 dead. */
6420 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
6421 operands [1], 0))
6422 return \"ld %L0,%L1\;ld %0,%1\";
6423 else
6424 return \"ld%U1 %0,%1\;ld %L0,%L1\";
6425 case 2:
6426 return \"std%U0 %1,%0\;std %L1,%L0\";
6427 }
6428 }"
6429 [(set_attr "type" "*,load,store")
6430 (set_attr "length" "8,8,8")])
6431 \f
6432 (define_expand "load_multiple"
6433 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
6434 (match_operand:SI 1 "" ""))
6435 (use (match_operand:SI 2 "" ""))])]
6436 "TARGET_STRING"
6437 "
6438 {
6439 int regno;
6440 int count;
6441 rtx from;
6442 int i;
6444 /* Support only loading a constant number of fixed-point registers from
6445 memory and only bother with this if more than two; the machine
6446 doesn't support more than eight. */
6447 if (GET_CODE (operands[2]) != CONST_INT
6448 || INTVAL (operands[2]) <= 2
6449 || INTVAL (operands[2]) > 8
6450 || GET_CODE (operands[1]) != MEM
6451 || GET_CODE (operands[0]) != REG
6452 || REGNO (operands[0]) >= 32)
6453 FAIL;
6455 count = INTVAL (operands[2]);
6456 regno = REGNO (operands[0]);
6458 operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
6459 from = force_reg (SImode, XEXP (operands[1], 0));
6461 for (i = 0; i < count; i++)
6462 XVECEXP (operands[3], 0, i)
6463 = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
6464 change_address (operands[1], SImode,
6465 plus_constant (from, i * 4)));
6466 }")
6468 (define_insn ""
6469 [(match_parallel 0 "load_multiple_operation"
6470 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
6471 (mem:SI (match_operand:SI 2 "register_operand" "b")))])]
6472 "TARGET_STRING"
6473 "*
6474 {
6475 /* We have to handle the case where the pseudo used to contain the address
6476 is assigned to one of the output registers. */
6477 int i, j;
6478 int words = XVECLEN (operands[0], 0);
6479 rtx xop[10];
6481 if (XVECLEN (operands[0], 0) == 1)
6482 return \"{l|lwz} %1,0(%2)\";
6484 for (i = 0; i < words; i++)
6485 if (refers_to_regno_p (REGNO (operands[1]) + i,
6486 REGNO (operands[1]) + i + 1, operands[2], 0))
6487 {
6488 if (i == words-1)
6489 {
6490 xop[0] = operands[1];
6491 xop[1] = operands[2];
6492 xop[2] = GEN_INT (4 * (words-1));
6493 output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop);
6494 return \"\";
6495 }
6496 else if (i == 0)
6497 {
6498 xop[0] = operands[1];
6499 xop[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
6500 xop[2] = GEN_INT (4 * (words-1));
6501 output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop);
6502 return \"\";
6503 }
6504 else
6505 {
6506 for (j = 0; j < words; j++)
6507 if (j != i)
6508 {
6509 xop[0] = gen_rtx (REG, SImode, REGNO (operands[1]) + j);
6510 xop[1] = operands[2];
6511 xop[2] = GEN_INT (j * 4);
6512 output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop);
6513 }
6514 xop[0] = operands[2];
6515 xop[1] = GEN_INT (i * 4);
6516 output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop);
6517 return \"\";
6518 }
6519 }
6521 return \"{lsi|lswi} %1,%2,%N0\";
6522 }"
6523 [(set_attr "type" "load")
6524 (set_attr "length" "32")])
6526 \f
6527 (define_expand "store_multiple"
6528 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
6529 (match_operand:SI 1 "" ""))
6530 (clobber (scratch:SI))
6531 (use (match_operand:SI 2 "" ""))])]
6532 "TARGET_STRING"
6533 "
6534 {
6535 int regno;
6536 int count;
6537 rtx to;
6538 int i;
6540 /* Support only storing a constant number of fixed-point registers to
6541 memory and only bother with this if more than two; the machine
6542 doesn't support more than eight. */
6543 if (GET_CODE (operands[2]) != CONST_INT
6544 || INTVAL (operands[2]) <= 2
6545 || INTVAL (operands[2]) > 8
6546 || GET_CODE (operands[0]) != MEM
6547 || GET_CODE (operands[1]) != REG
6548 || REGNO (operands[1]) >= 32)
6549 FAIL;
6551 count = INTVAL (operands[2]);
6552 regno = REGNO (operands[1]);
6554 operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1));
6555 to = force_reg (SImode, XEXP (operands[0], 0));
6557 XVECEXP (operands[3], 0, 0)
6558 = gen_rtx (SET, VOIDmode, change_address (operands[0], SImode, to),
6559 operands[1]);
6560 XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode,
6561 gen_rtx (SCRATCH, SImode));
6563 for (i = 1; i < count; i++)
6564 XVECEXP (operands[3], 0, i + 1)
6565 = gen_rtx (SET, VOIDmode,
6566 change_address (operands[0], SImode,
6567 plus_constant (to, i * 4)),
6568 gen_rtx (REG, SImode, regno + i));
6569 }")
6571 (define_insn ""
6572 [(match_parallel 0 "store_multiple_operation"
6573 [(set (match_operand:SI 1 "indirect_operand" "=Q")
6574 (match_operand:SI 2 "gpc_reg_operand" "r"))
6575 (clobber (match_scratch:SI 3 "=q"))])]
6576 "TARGET_STRING && TARGET_POWER"
6577 "{stsi|stswi} %2,%P1,%O0"
6578 [(set_attr "type" "store")])
6580 (define_insn ""
6581 [(match_parallel 0 "store_multiple_operation"
6582 [(set (mem:SI (match_operand:SI 1 "register_operand" "b"))
6583 (match_operand:SI 2 "gpc_reg_operand" "r"))
6584 (clobber (match_scratch:SI 3 "X"))])]
6585 "TARGET_STRING && !TARGET_POWER"
6586 "{stsi|stswi} %2,%1,%O0"
6587 [(set_attr "type" "store")])
6589 \f
6590 ;; String/block move insn.
6591 ;; Argument 0 is the destination
6592 ;; Argument 1 is the source
6593 ;; Argument 2 is the length
6594 ;; Argument 3 is the alignment
6596 (define_expand "movstrsi"
6597 [(parallel [(set (match_operand:BLK 0 "" "")
6598 (match_operand:BLK 1 "" ""))
6599 (use (match_operand:SI 2 "" ""))
6600 (use (match_operand:SI 3 "" ""))])]
6601 ""
6602 "
6603 {
6604 if (expand_block_move (operands))
6605 DONE;
6606 else
6607 FAIL;
6608 }")
6610 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
6611 ;; register allocator doesn't have a clue about allocating 8 word registers
6612 (define_expand "movstrsi_8reg"
6613 [(parallel [(set (match_operand 0 "" "")
6614 (match_operand 1 "" ""))
6615 (use (match_operand 2 "" ""))
6616 (use (match_operand 3 "" ""))
6617 (clobber (reg:SI 5))
6618 (clobber (reg:SI 6))
6619 (clobber (reg:SI 7))
6620 (clobber (reg:SI 8))
6621 (clobber (reg:SI 9))
6622 (clobber (reg:SI 10))
6623 (clobber (reg:SI 11))
6624 (clobber (reg:SI 12))
6625 (clobber (match_scratch:SI 4 ""))])]
6626 "TARGET_STRING"
6627 "")
6629 (define_insn ""
6630 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6631 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6632 (use (match_operand:SI 2 "immediate_operand" "i"))
6633 (use (match_operand:SI 3 "immediate_operand" "i"))
6634 (clobber (match_operand:SI 4 "register_operand" "=r"))
6635 (clobber (reg:SI 6))
6636 (clobber (reg:SI 7))
6637 (clobber (reg:SI 8))
6638 (clobber (reg:SI 9))
6639 (clobber (reg:SI 10))
6640 (clobber (reg:SI 11))
6641 (clobber (reg:SI 12))
6642 (clobber (match_scratch:SI 5 "=q"))]
6643 "TARGET_STRING && TARGET_POWER
6644 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0)
6645 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
6646 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
6647 && REGNO (operands[4]) == 5"
6648 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6649 [(set_attr "type" "load")
6650 (set_attr "length" "8")])
6652 (define_insn ""
6653 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6654 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6655 (use (match_operand:SI 2 "immediate_operand" "i"))
6656 (use (match_operand:SI 3 "immediate_operand" "i"))
6657 (clobber (match_operand:SI 4 "register_operand" "=r"))
6658 (clobber (reg:SI 6))
6659 (clobber (reg:SI 7))
6660 (clobber (reg:SI 8))
6661 (clobber (reg:SI 9))
6662 (clobber (reg:SI 10))
6663 (clobber (reg:SI 11))
6664 (clobber (reg:SI 12))
6665 (clobber (match_scratch:SI 5 "X"))]
6666 "TARGET_STRING && !TARGET_POWER
6667 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0)
6668 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
6669 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
6670 && REGNO (operands[4]) == 5"
6671 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6672 [(set_attr "type" "load")
6673 (set_attr "length" "8")])
6675 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
6676 ;; register allocator doesn't have a clue about allocating 6 word registers
6677 (define_expand "movstrsi_6reg"
6678 [(parallel [(set (match_operand 0 "" "")
6679 (match_operand 1 "" ""))
6680 (use (match_operand 2 "" ""))
6681 (use (match_operand 3 "" ""))
6682 (clobber (reg:SI 7))
6683 (clobber (reg:SI 8))
6684 (clobber (reg:SI 9))
6685 (clobber (reg:SI 10))
6686 (clobber (reg:SI 11))
6687 (clobber (reg:SI 12))
6688 (clobber (match_scratch:SI 4 ""))])]
6689 "TARGET_STRING"
6690 "")
6692 (define_insn ""
6693 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6694 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6695 (use (match_operand:SI 2 "immediate_operand" "i"))
6696 (use (match_operand:SI 3 "immediate_operand" "i"))
6697 (clobber (match_operand:SI 4 "register_operand" "=r"))
6698 (clobber (reg:SI 8))
6699 (clobber (reg:SI 9))
6700 (clobber (reg:SI 10))
6701 (clobber (reg:SI 11))
6702 (clobber (reg:SI 12))
6703 (clobber (match_scratch:SI 5 "=q"))]
6704 "TARGET_STRING && TARGET_POWER
6705 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
6706 && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12)
6707 && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
6708 && REGNO (operands[4]) == 7"
6709 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6710 [(set_attr "type" "load")
6711 (set_attr "length" "8")])
6713 (define_insn ""
6714 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6715 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6716 (use (match_operand:SI 2 "immediate_operand" "i"))
6717 (use (match_operand:SI 3 "immediate_operand" "i"))
6718 (clobber (match_operand:SI 4 "register_operand" "=r"))
6719 (clobber (reg:SI 8))
6720 (clobber (reg:SI 9))
6721 (clobber (reg:SI 10))
6722 (clobber (reg:SI 11))
6723 (clobber (reg:SI 12))
6724 (clobber (match_scratch:SI 5 "X"))]
6725 "TARGET_STRING && !TARGET_POWER
6726 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
6727 && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12)
6728 && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
6729 && REGNO (operands[4]) == 7"
6730 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6731 [(set_attr "type" "load")
6732 (set_attr "length" "8")])
6734 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill problems
6735 ;; with TImode
6736 (define_expand "movstrsi_4reg"
6737 [(parallel [(set (match_operand 0 "" "")
6738 (match_operand 1 "" ""))
6739 (use (match_operand 2 "" ""))
6740 (use (match_operand 3 "" ""))
6741 (clobber (reg:SI 9))
6742 (clobber (reg:SI 10))
6743 (clobber (reg:SI 11))
6744 (clobber (reg:SI 12))
6745 (clobber (match_scratch:SI 4 ""))])]
6746 "TARGET_STRING"
6747 "")
6749 (define_insn ""
6750 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6751 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6752 (use (match_operand:SI 2 "immediate_operand" "i"))
6753 (use (match_operand:SI 3 "immediate_operand" "i"))
6754 (clobber (match_operand:SI 4 "register_operand" "=r"))
6755 (clobber (reg:SI 10))
6756 (clobber (reg:SI 11))
6757 (clobber (reg:SI 12))
6758 (clobber (match_scratch:SI 5 "=q"))]
6759 "TARGET_STRING && TARGET_POWER
6760 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
6761 && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12)
6762 && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
6763 && REGNO (operands[4]) == 9"
6764 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6765 [(set_attr "type" "load")
6766 (set_attr "length" "8")])
6768 (define_insn ""
6769 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6770 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6771 (use (match_operand:SI 2 "immediate_operand" "i"))
6772 (use (match_operand:SI 3 "immediate_operand" "i"))
6773 (clobber (match_operand:SI 4 "register_operand" "=r"))
6774 (clobber (reg:SI 10))
6775 (clobber (reg:SI 11))
6776 (clobber (reg:SI 12))
6777 (clobber (match_scratch:SI 5 "X"))]
6778 "TARGET_STRING && !TARGET_POWER
6779 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
6780 && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12)
6781 && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
6782 && REGNO (operands[4]) == 9"
6783 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6784 [(set_attr "type" "load")
6785 (set_attr "length" "8")])
6787 ;; Move up to 8 bytes at a time.
6788 (define_expand "movstrsi_2reg"
6789 [(parallel [(set (match_operand 0 "" "")
6790 (match_operand 1 "" ""))
6791 (use (match_operand 2 "" ""))
6792 (use (match_operand 3 "" ""))
6793 (clobber (match_scratch:DI 4 ""))
6794 (clobber (match_scratch:SI 5 ""))])]
6795 "TARGET_STRING && !TARGET_64BIT"
6796 "")
6798 (define_insn ""
6799 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6800 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6801 (use (match_operand:SI 2 "immediate_operand" "i"))
6802 (use (match_operand:SI 3 "immediate_operand" "i"))
6803 (clobber (match_scratch:DI 4 "=&r"))
6804 (clobber (match_scratch:SI 5 "=q"))]
6805 "TARGET_STRING && TARGET_POWER && !TARGET_64BIT
6806 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
6807 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6808 [(set_attr "type" "load")
6809 (set_attr "length" "8")])
6811 (define_insn ""
6812 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6813 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6814 (use (match_operand:SI 2 "immediate_operand" "i"))
6815 (use (match_operand:SI 3 "immediate_operand" "i"))
6816 (clobber (match_scratch:DI 4 "=&r"))
6817 (clobber (match_scratch:SI 5 "X"))]
6818 "TARGET_STRING && !TARGET_POWER && !TARGET_64BIT
6819 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
6820 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6821 [(set_attr "type" "load")
6822 (set_attr "length" "8")])
6824 ;; Move up to 4 bytes at a time.
6825 (define_expand "movstrsi_1reg"
6826 [(parallel [(set (match_operand 0 "" "")
6827 (match_operand 1 "" ""))
6828 (use (match_operand 2 "" ""))
6829 (use (match_operand 3 "" ""))
6830 (clobber (match_scratch:SI 4 ""))
6831 (clobber (match_scratch:SI 5 ""))])]
6832 "TARGET_STRING"
6833 "")
6835 (define_insn ""
6836 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6837 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6838 (use (match_operand:SI 2 "immediate_operand" "i"))
6839 (use (match_operand:SI 3 "immediate_operand" "i"))
6840 (clobber (match_scratch:SI 4 "=&r"))
6841 (clobber (match_scratch:SI 5 "=q"))]
6842 "TARGET_STRING && TARGET_POWER
6843 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
6844 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6845 [(set_attr "type" "load")
6846 (set_attr "length" "8")])
6848 (define_insn ""
6849 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6850 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6851 (use (match_operand:SI 2 "immediate_operand" "i"))
6852 (use (match_operand:SI 3 "immediate_operand" "i"))
6853 (clobber (match_scratch:SI 4 "=&r"))
6854 (clobber (match_scratch:SI 5 "X"))]
6855 "TARGET_STRING && !TARGET_POWER
6856 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
6857 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6858 [(set_attr "type" "load")
6859 (set_attr "length" "8")])
6861 \f
6862 ;; Define insns that do load or store with update. Some of these we can
6863 ;; get by using pre-decrement or pre-increment, but the hardware can also
6864 ;; do cases where the increment is not the size of the object.
6865 ;;
6866 ;; In all these cases, we use operands 0 and 1 for the register being
6867 ;; incremented because those are the operands that local-alloc will
6868 ;; tie and these are the pair most likely to be tieable (and the ones
6869 ;; that will benefit the most).
6871 (define_insn "*movdi_update1"
6872 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
6873 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
6874 (match_operand:DI 2 "reg_or_short_operand" "r,I"))))
6875 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
6876 (plus:DI (match_dup 1) (match_dup 2)))]
6877 "TARGET_POWERPC64 && TARGET_UPDATE"
6878 "@
6879 ldux %3,%0,%2
6880 ldu %3,%2(%0)"
6881 [(set_attr "type" "load")])
6883 (define_insn "*movdi_update2"
6884 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
6885 (sign_extend:DI
6886 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
6887 (match_operand:DI 2 "gpc_reg_operand" "r")))))
6888 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
6889 (plus:DI (match_dup 1) (match_dup 2)))]
6890 "TARGET_POWERPC64"
6891 "lwaux %3,%0,%2"
6892 [(set_attr "type" "load")])
6894 (define_insn "movdi_update"
6895 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
6896 (match_operand:DI 2 "reg_or_short_operand" "r,I")))
6897 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
6898 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
6899 (plus:DI (match_dup 1) (match_dup 2)))]
6900 "TARGET_POWERPC64 && TARGET_UPDATE"
6901 "@
6902 stdux %3,%0,%2
6903 stdu %3,%2(%0)"
6904 [(set_attr "type" "store")])
6906 (define_insn "*movsi_update1"
6907 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
6908 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6909 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
6910 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6911 (plus:SI (match_dup 1) (match_dup 2)))]
6912 ""
6913 "@
6914 {lux|lwzux} %3,%0,%2
6915 {lu|lwzu} %3,%2(%0)"
6916 [(set_attr "type" "load")])
6918 (define_insn "movsi_update"
6919 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6920 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
6921 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
6922 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6923 (plus:SI (match_dup 1) (match_dup 2)))]
6924 "TARGET_UPDATE"
6925 "@
6926 {stux|stwux} %3,%0,%2
6927 {stu|stwu} %3,%2(%0)"
6928 [(set_attr "type" "store")])
6930 (define_insn "*movhi_update"
6931 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
6932 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6933 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
6934 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6935 (plus:SI (match_dup 1) (match_dup 2)))]
6936 "TARGET_UPDATE"
6937 "@
6938 lhzux %3,%0,%2
6939 lhzu %3,%2(%0)"
6940 [(set_attr "type" "load")])
6942 (define_insn "*movhi_update2"
6943 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
6944 (zero_extend:SI
6945 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6946 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
6947 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6948 (plus:SI (match_dup 1) (match_dup 2)))]
6949 "TARGET_UPDATE"
6950 "@
6951 lhzux %3,%0,%2
6952 lhzu %3,%2(%0)"
6953 [(set_attr "type" "load")])
6955 (define_insn "*movhi_update3"
6956 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
6957 (sign_extend:SI
6958 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6959 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
6960 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6961 (plus:SI (match_dup 1) (match_dup 2)))]
6962 "TARGET_UPDATE"
6963 "@
6964 lhaux %3,%0,%2
6965 lhau %3,%2(%0)"
6966 [(set_attr "type" "load")])
6968 (define_insn "*movhi_update4"
6969 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6970 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
6971 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
6972 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6973 (plus:SI (match_dup 1) (match_dup 2)))]
6974 "TARGET_UPDATE"
6975 "@
6976 sthux %3,%0,%2
6977 sthu %3,%2(%0)"
6978 [(set_attr "type" "store")])
6980 (define_insn "*movqi_update1"
6981 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
6982 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6983 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
6984 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6985 (plus:SI (match_dup 1) (match_dup 2)))]
6986 "TARGET_UPDATE"
6987 "@
6988 lbzux %3,%0,%2
6989 lbzu %3,%2(%0)"
6990 [(set_attr "type" "load")])
6992 (define_insn "*movqi_update2"
6993 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
6994 (zero_extend:SI
6995 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6996 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
6997 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6998 (plus:SI (match_dup 1) (match_dup 2)))]
6999 "TARGET_UPDATE"
7000 "@
7001 lbzux %3,%0,%2
7002 lbzu %3,%2(%0)"
7003 [(set_attr "type" "load")])
7005 (define_insn "*movqi_update3"
7006 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7007 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
7008 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
7009 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7010 (plus:SI (match_dup 1) (match_dup 2)))]
7011 "TARGET_UPDATE"
7012 "@
7013 stbux %3,%0,%2
7014 stbu %3,%2(%0)"
7015 [(set_attr "type" "store")])
7017 (define_insn "*movsf_update1"
7018 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
7019 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7020 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
7021 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7022 (plus:SI (match_dup 1) (match_dup 2)))]
7023 "TARGET_HARD_FLOAT && TARGET_UPDATE"
7024 "@
7025 lfsux %3,%0,%2
7026 lfsu %3,%2(%0)"
7027 [(set_attr "type" "fpload")])
7029 (define_insn "*movsf_update2"
7030 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7031 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
7032 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
7033 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7034 (plus:SI (match_dup 1) (match_dup 2)))]
7035 "TARGET_HARD_FLOAT && TARGET_UPDATE"
7036 "@
7037 stfsux %3,%0,%2
7038 stfsu %3,%2(%0)"
7039 [(set_attr "type" "fpstore")])
7041 (define_insn "*movsf_update3"
7042 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
7043 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7044 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
7045 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7046 (plus:SI (match_dup 1) (match_dup 2)))]
7047 "TARGET_SOFT_FLOAT && TARGET_UPDATE"
7048 "@
7049 {lux|lwzux} %3,%0,%2
7050 {lu|lwzu} %3,%2(%0)"
7051 [(set_attr "type" "load")])
7053 (define_insn "*movsf_update4"
7054 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7055 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
7056 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
7057 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7058 (plus:SI (match_dup 1) (match_dup 2)))]
7059 "TARGET_SOFT_FLOAT && TARGET_UPDATE"
7060 "@
7061 {stux|stwux} %3,%0,%2
7062 {stu|stwu} %3,%2(%0)"
7063 [(set_attr "type" "store")])
7065 (define_insn "*movdf_update1"
7066 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
7067 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7068 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
7069 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7070 (plus:SI (match_dup 1) (match_dup 2)))]
7071 "TARGET_HARD_FLOAT && TARGET_UPDATE"
7072 "@
7073 lfdux %3,%0,%2
7074 lfdu %3,%2(%0)"
7075 [(set_attr "type" "fpload")])
7077 (define_insn "*movdf_update2"
7078 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7079 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
7080 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
7081 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7082 (plus:SI (match_dup 1) (match_dup 2)))]
7083 "TARGET_HARD_FLOAT && TARGET_UPDATE"
7084 "@
7085 stfdux %3,%0,%2
7086 stfdu %3,%2(%0)"
7087 [(set_attr "type" "fpstore")])
7089 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
7091 (define_peephole
7092 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
7093 (match_operand:DF 1 "memory_operand" ""))
7094 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
7095 (match_operand:DF 3 "memory_operand" ""))]
7096 "TARGET_POWER2
7097 && TARGET_HARD_FLOAT
7098 && registers_ok_for_quad_peep (operands[0], operands[2])
7099 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
7100 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
7101 "lfq%U1%X1 %0,%1")
7103 (define_peephole
7104 [(set (match_operand:DF 0 "memory_operand" "")
7105 (match_operand:DF 1 "gpc_reg_operand" "f"))
7106 (set (match_operand:DF 2 "memory_operand" "")
7107 (match_operand:DF 3 "gpc_reg_operand" "f"))]
7108 "TARGET_POWER2
7109 && TARGET_HARD_FLOAT
7110 && registers_ok_for_quad_peep (operands[1], operands[3])
7111 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
7112 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
7113 "stfq%U0%X0 %1,%0")
7114 \f
7115 ;; Next come insns related to the calling sequence.
7116 ;;
7117 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
7118 ;; We move the back-chain and decrement the stack pointer.
7120 (define_expand "allocate_stack"
7121 [(set (match_operand:SI 0 "register_operand" "=r")
7122 (minus:SI (reg:SI 1) (match_operand:SI 1 "reg_or_short_operand" "")))
7123 (set (reg:SI 1)
7124 (minus:SI (reg:SI 1) (match_dup 1)))]
7125 ""
7126 "
7127 { rtx chain = gen_reg_rtx (Pmode);
7128 rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx);
7129 rtx neg_op0;
7131 emit_move_insn (chain, stack_bot);
7133 /* Under Windows NT, we need to add stack probes for large/variable
7134 allocations, so do it via a call to the external function alloca
7135 instead of doing it inline. */
7136 if (DEFAULT_ABI == ABI_NT
7137 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) > 4096))
7138 {
7139 rtx tmp = gen_reg_rtx (SImode);
7140 emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"__allocate_stack\"),
7141 tmp, 0, SImode, 1, operands[1], Pmode);
7142 emit_insn (gen_set_sp (tmp));
7143 emit_move_insn (operands[0], tmp);
7144 DONE;
7145 }
7147 if (GET_CODE (operands[1]) != CONST_INT
7148 || INTVAL (operands[1]) < -32767
7149 || INTVAL (operands[1]) > 32768)
7150 {
7151 neg_op0 = gen_reg_rtx (Pmode);
7152 if (TARGET_32BIT)
7153 emit_insn (gen_negsi2 (neg_op0, operands[1]));
7154 else
7155 emit_insn (gen_negdi2 (neg_op0, operands[1]));
7156 }
7157 else
7158 neg_op0 = GEN_INT (- INTVAL (operands[1]));
7160 if (TARGET_UPDATE)
7161 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
7162 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
7164 else
7165 {
7166 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
7167 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
7168 emit_move_insn (gen_rtx (MEM, (TARGET_32BIT) ? SImode : DImode,
7169 stack_pointer_rtx),
7170 chain);
7171 }
7173 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7174 DONE;
7175 }")
7177 ;; Marker to indicate that the stack pointer was changed under NT in
7178 ;; ways not known to the compiler
7180 (define_insn "set_sp"
7181 [(set (reg:SI 1)
7182 (unspec [(match_operand:SI 0 "register_operand" "r")] 7))]
7183 ""
7184 ""
7185 [(set_attr "length" "0")])
7187 ;; These patterns say how to save and restore the stack pointer. We need not
7188 ;; save the stack pointer at function level since we are careful to
7189 ;; preserve the backchain. At block level, we have to restore the backchain
7190 ;; when we restore the stack pointer.
7191 ;;
7192 ;; For nonlocal gotos, we must save both the stack pointer and its
7193 ;; backchain and restore both. Note that in the nonlocal case, the
7194 ;; save area is a memory location.
7196 (define_expand "save_stack_function"
7197 [(use (const_int 0))]
7198 ""
7199 "")
7201 (define_expand "restore_stack_function"
7202 [(use (const_int 0))]
7203 ""
7204 "")
7206 (define_expand "restore_stack_block"
7207 [(set (match_dup 2) (mem:SI (match_operand:SI 0 "register_operand" "")))
7208 (set (match_dup 0) (match_operand:SI 1 "register_operand" ""))
7209 (set (mem:SI (match_dup 0)) (match_dup 2))]
7210 ""
7211 "
7212 { operands[2] = gen_reg_rtx (SImode); }")
7214 (define_expand "save_stack_nonlocal"
7215 [(match_operand:DI 0 "memory_operand" "")
7216 (match_operand:SI 1 "register_operand" "")]
7217 ""
7218 "
7219 {
7220 rtx temp = gen_reg_rtx (SImode);
7222 /* Copy the backchain to the first word, sp to the second. */
7223 emit_move_insn (temp, gen_rtx (MEM, SImode, operands[1]));
7224 emit_move_insn (operand_subword (operands[0], 0, 0, DImode), temp);
7225 emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]);
7226 DONE;
7227 }")
7229 (define_expand "restore_stack_nonlocal"
7230 [(match_operand:SI 0 "register_operand" "")
7231 (match_operand:DI 1 "memory_operand" "")]
7232 ""
7233 "
7234 {
7235 rtx temp = gen_reg_rtx (SImode);
7237 /* Restore the backchain from the first word, sp from the second. */
7238 emit_move_insn (temp, operand_subword (operands[1], 0, 0, DImode));
7239 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, DImode));
7240 emit_move_insn (gen_rtx (MEM, SImode, operands[0]), temp);
7241 DONE;
7242 }")
7244 ;; If we have -mminimal-toc, we need to reload r30 after a nonlocal goto.
7246 (define_insn "nonlocal_goto_receiver"
7247 [(unspec_volatile [(const_int 0)] 1)]
7248 "TARGET_TOC && TARGET_MINIMAL_TOC"
7249 "*
7250 {
7251 rs6000_output_load_toc_table (asm_out_file, 30);
7252 return \"\";
7253 }"
7254 [(set_attr "type" "load")])
7255 \f
7256 ;; A function pointer under AIX is a pointer to a data area whose first word
7257 ;; contains the actual address of the function, whose second word contains a
7258 ;; pointer to its TOC, and whose third word contains a value to place in the
7259 ;; static chain register (r11). Note that if we load the static chain, our
7260 ;; "trampoline" need not have any executable code.
7261 ;;
7262 ;; operands[0] is a register pointing to the 3 word descriptor (aka, the function address)
7263 ;; operands[1] is the stack size to clean up
7264 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for AIX)
7265 ;; operands[3] is location to store the TOC
7266 ;; operands[4] is the TOC register
7267 ;; operands[5] is the static chain register
7268 ;;
7269 ;; We do not break this into separate insns, so that the scheduler will not try
7270 ;; to move the load of the new TOC before any loads from the TOC.
7272 (define_insn "call_indirect_aix"
7273 [(call (mem:SI (match_operand:SI 0 "register_operand" "b"))
7274 (match_operand 1 "const_int_operand" "n"))
7275 (use (match_operand 2 "const_int_operand" "n"))
7276 (use (match_operand 3 "offsettable_addr_operand" "p"))
7277 (use (match_operand 4 "register_operand" "r"))
7278 (clobber (match_operand 5 "register_operand" "=r"))
7279 (clobber (match_scratch:SI 6 "=&r"))
7280 (clobber (match_scratch:SI 7 "=l"))]
7281 "DEFAULT_ABI == ABI_AIX
7282 && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)"
7283 "{st|stw} %4,%a3\;{l|lwz} %6,0(%0)\;{l|lwz} %4,4(%0)\;mt%7 %6\;{l|lwz} %5,8(%0)\;{brl|blrl}\;{l|lwz} %4,%a3"
7284 [(set_attr "type" "load")
7285 (set_attr "length" "28")])
7287 (define_insn "call_value_indirect_aix"
7288 [(set (match_operand 0 "register_operand" "fg")
7289 (call (mem:SI (match_operand:SI 1 "register_operand" "b"))
7290 (match_operand 2 "const_int_operand" "n")))
7291 (use (match_operand 3 "const_int_operand" "n"))
7292 (use (match_operand 4 "offsettable_addr_operand" "p"))
7293 (use (match_operand 5 "register_operand" "r"))
7294 (clobber (match_operand 6 "register_operand" "=r"))
7295 (clobber (match_scratch:SI 7 "=&r"))
7296 (clobber (match_scratch:SI 8 "=l"))]
7297 "DEFAULT_ABI == ABI_AIX
7298 && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)"
7299 "{st|stw} %5,%a4\;{l|lwz} %7,0(%1)\;{l|lwz} %5,4(%1);\;mt%8 %7\;{l|lwz} %6,8(%1)\;{brl|blrl}\;{l|lwz} %5,%a4"
7300 [(set_attr "type" "load")
7301 (set_attr "length" "28")])
7303 ;; A function pointer undef NT is a pointer to a data area whose first word
7304 ;; contains the actual address of the function, whose second word contains a
7305 ;; pointer to its TOC. The static chain is not stored under NT, which means
7306 ;; that we need a trampoline.
7307 ;;
7308 ;; operands[0] is an SImode pseudo in which we place the address of the function.
7309 ;; operands[1] is the stack size to clean up
7310 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for NT)
7311 ;; operands[3] is location to store the TOC
7312 ;; operands[4] is the TOC register
7313 ;;
7314 ;; We do not break this into separate insns, so that the scheduler will not try
7315 ;; to move the load of the new TOC before any loads from the TOC.
7317 (define_insn "call_indirect_nt"
7318 [(call (mem:SI (match_operand:SI 0 "register_operand" "b"))
7319 (match_operand 1 "const_int_operand" "n"))
7320 (use (match_operand 2 "const_int_operand" "n"))
7321 (use (match_operand 3 "offsettable_addr_operand" "p"))
7322 (use (match_operand 4 "register_operand" "r"))
7323 (clobber (match_scratch:SI 5 "=&r"))
7324 (clobber (match_scratch:SI 6 "=l"))]
7325 "DEFAULT_ABI == ABI_NT
7326 && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)"
7327 "{st|stw} %4,%a3\;{l|lwz} %5,0(%0)\;{l|lwz} %4,4(%0)\;mt%6 %5\;{brl|blrl}\;{l|lwz} %4,%a3"
7328 [(set_attr "type" "load")
7329 (set_attr "length" "24")])
7331 (define_insn "call_value_indirect_nt"
7332 [(set (match_operand 0 "register_operand" "fg")
7333 (call (mem:SI (match_operand:SI 1 "register_operand" "b"))
7334 (match_operand 2 "const_int_operand" "n")))
7335 (use (match_operand 3 "const_int_operand" "n"))
7336 (use (match_operand 4 "offsettable_addr_operand" "p"))
7337 (use (match_operand 5 "register_operand" "r"))
7338 (clobber (match_scratch:SI 6 "=&r"))
7339 (clobber (match_scratch:SI 7 "=l"))]
7340 "DEFAULT_ABI == ABI_NT
7341 && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)"
7342 "{st|stw} %5,%a4\;{l|lwz} %6,0(%1)\;{l|lwz} %5,4(%1)\;mt%7 %6\;{brl|blrl}\;{l|lwz} %5,%a4"
7343 [(set_attr "type" "load")
7344 (set_attr "length" "24")])
7346 ;; A function pointer under System V is just a normal pointer
7347 ;; operands[0] is the function pointer
7348 ;; operands[1] is the stack size to clean up
7349 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument which indicates how to set cr1
7351 (define_insn "call_indirect_sysv"
7352 [(call (mem:SI (match_operand:SI 0 "register_operand" "l,l"))
7353 (match_operand 1 "const_int_operand" "n,n"))
7354 (use (match_operand 2 "const_int_operand" "O,n"))
7355 (clobber (match_scratch:SI 3 "=l,l"))]
7356 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC"
7357 "*
7358 {
7359 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
7360 output_asm_insn (\"crxor 6,6,6\", operands);
7362 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
7363 output_asm_insn (\"creqv 6,6,6\", operands);
7365 return \"{brl|blrl}\";
7366 }"
7367 [(set_attr "type" "jmpreg")
7368 (set_attr "length" "4,8")])
7370 (define_insn "call_value_indirect_sysv"
7371 [(set (match_operand 0 "register_operand" "=fg,fg")
7372 (call (mem:SI (match_operand:SI 1 "register_operand" "l,l"))
7373 (match_operand 2 "const_int_operand" "n,n")))
7374 (use (match_operand 3 "const_int_operand" "O,n"))
7375 (clobber (match_scratch:SI 4 "=l,l"))]
7376 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC"
7377 "*
7378 {
7379 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
7380 output_asm_insn (\"crxor 6,6,6\", operands);
7382 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
7383 output_asm_insn (\"creqv 6,6,6\", operands);
7385 return \"{brl|blrl}\";
7386 }"
7387 [(set_attr "type" "jmpreg")
7388 (set_attr "length" "4,8")])
7390 ;; Now the definitions for the call and call_value insns
7391 (define_expand "call"
7392 [(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" ""))
7393 (match_operand 1 "" ""))
7394 (use (match_operand 2 "" ""))
7395 (clobber (scratch:SI))])]
7396 ""
7397 "
7398 {
7399 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
7400 abort ();
7402 operands[0] = XEXP (operands[0], 0);
7404 /* Convert NT DLL imports into an indirect call. */
7405 if (GET_CODE (operands[0]) == SYMBOL_REF
7406 && (INTVAL (operands[2]) & CALL_NT_DLLIMPORT) != 0)
7407 {
7408 operands[0] = rs6000_dll_import_ref (operands[0]);
7409 operands[2] = GEN_INT ((int)CALL_NORMAL);
7410 }
7412 if (GET_CODE (operands[0]) != SYMBOL_REF
7413 || (INTVAL (operands[2]) & CALL_LONG) != 0)
7414 {
7415 if (INTVAL (operands[2]) & CALL_LONG)
7416 operands[0] = rs6000_longcall_ref (operands[0]);
7418 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS)
7419 emit_call_insn (gen_call_indirect_sysv (force_reg (Pmode, operands[0]),
7420 operands[1], operands[2]));
7421 else
7422 {
7423 rtx toc_reg = gen_rtx (REG, Pmode, 2);
7424 rtx toc_addr = RS6000_SAVE_TOC;
7426 if (DEFAULT_ABI == ABI_AIX)
7427 {
7428 /* AIX function pointers are really pointers to a three word area */
7429 rtx static_chain = gen_rtx (REG, Pmode, STATIC_CHAIN_REGNUM);
7430 emit_call_insn (gen_call_indirect_aix (force_reg (Pmode, operands[0]),
7431 operands[1], operands[2],
7432 toc_addr, toc_reg, static_chain));
7433 }
7434 else if (DEFAULT_ABI == ABI_NT)
7435 {
7436 /* NT function pointers are really pointers to a two word area */
7437 emit_call_insn (gen_call_indirect_nt (force_reg (Pmode, operands[0]),
7438 operands[1], operands[2],
7439 toc_addr, toc_reg));
7440 }
7441 else
7442 abort ();
7443 }
7444 DONE;
7445 }
7446 }")
7448 (define_expand "call_value"
7449 [(parallel [(set (match_operand 0 "" "")
7450 (call (mem:SI (match_operand:SI 1 "address_operand" ""))
7451 (match_operand 2 "" "")))
7452 (use (match_operand 3 "" ""))
7453 (clobber (scratch:SI))])]
7454 ""
7455 "
7456 {
7457 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
7458 abort ();
7460 operands[1] = XEXP (operands[1], 0);
7462 /* Convert NT DLL imports into an indirect call. */
7463 if (GET_CODE (operands[1]) == SYMBOL_REF
7464 && (INTVAL (operands[3]) & CALL_NT_DLLIMPORT) != 0)
7465 {
7466 operands[1] = rs6000_dll_import_ref (operands[1]);
7467 operands[3] = GEN_INT ((int)CALL_NORMAL);
7468 }
7470 if (GET_CODE (operands[1]) != SYMBOL_REF
7471 || (INTVAL (operands[3]) & CALL_LONG) != 0)
7472 {
7473 if (INTVAL (operands[2]) & CALL_LONG)
7474 operands[1] = rs6000_longcall_ref (operands[1]);
7476 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS)
7477 emit_call_insn (gen_call_value_indirect_sysv (operands[0], operands[1],
7478 operands[2], operands[3]));
7479 else
7480 {
7481 rtx toc_reg = gen_rtx (REG, Pmode, 2);
7482 rtx toc_addr = RS6000_SAVE_TOC;
7484 if (DEFAULT_ABI == ABI_AIX)
7485 {
7486 /* AIX function pointers are really pointers to a three word area */
7487 rtx static_chain = gen_rtx (REG, Pmode, STATIC_CHAIN_REGNUM);
7488 emit_call_insn (gen_call_value_indirect_aix (operands[0],
7489 force_reg (Pmode, operands[1]),
7490 operands[2], operands[3],
7491 toc_addr, toc_reg, static_chain));
7492 }
7493 else if (DEFAULT_ABI == ABI_NT)
7494 {
7495 /* NT function pointers are really pointers to a two word area */
7496 emit_call_insn (gen_call_value_indirect_nt (operands[0],
7497 force_reg (Pmode, operands[1]),
7498 operands[2], operands[3],
7499 toc_addr, toc_reg));
7500 }
7501 else
7502 abort ();
7503 }
7504 DONE;
7505 }
7506 }")
7508 ;; Call to function in current module. No TOC pointer reload needed.
7509 ;; Operand2 is non-zero if we are using the V.4 calling sequence and
7510 ;; either the function was not prototyped, or it was prototyped as a
7511 ;; variable argument function. It is > 0 if FP registers were passed
7512 ;; and < 0 if they were not.
7514 (define_insn ""
7515 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
7516 (match_operand 1 "" "g,g"))
7517 (use (match_operand:SI 2 "immediate_operand" "O,n"))
7518 (clobber (match_scratch:SI 3 "=l,l"))]
7519 "(INTVAL (operands[2]) & CALL_LONG) == 0"
7520 "*
7521 {
7522 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
7523 output_asm_insn (\"crxor 6,6,6\", operands);
7525 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
7526 output_asm_insn (\"creqv 6,6,6\", operands);
7528 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
7529 }"
7530 [(set_attr "type" "branch")
7531 (set_attr "length" "4,8")])
7533 ;; Call to function which may be in another module. Restore the TOC
7534 ;; pointer (r2) after the call unless this is System V.
7535 ;; Operand2 is non-zero if we are using the V.4 calling sequence and
7536 ;; either the function was not prototyped, or it was prototyped as a
7537 ;; variable argument function. It is > 0 if FP registers were passed
7538 ;; and < 0 if they were not.
7540 (define_insn ""
7541 [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s"))
7542 (match_operand 1 "" "fg,fg"))
7543 (use (match_operand:SI 2 "immediate_operand" "O,n"))
7544 (clobber (match_scratch:SI 3 "=l,l"))]
7545 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
7546 && (INTVAL (operands[2]) & CALL_LONG) == 0"
7547 "*
7548 {
7549 /* Indirect calls should go through call_indirect */
7550 if (GET_CODE (operands[0]) == REG)
7551 abort ();
7553 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
7554 output_asm_insn (\"crxor 6,6,6\", operands);
7556 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
7557 output_asm_insn (\"creqv 6,6,6\", operands);
7559 return (TARGET_WINDOWS_NT) ? \"bl %z0\;.znop %z0\" : \"bl %z0\;%.\";
7560 }"
7561 [(set_attr "type" "branch")
7562 (set_attr "length" "8,12")])
7564 (define_insn ""
7565 [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s"))
7566 (match_operand 1 "" "fg,fg"))
7567 (use (match_operand:SI 2 "immediate_operand" "O,n"))
7568 (clobber (match_scratch:SI 3 "=l,l"))]
7569 "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
7570 && (INTVAL (operands[2]) & CALL_LONG) == 0"
7571 "*
7572 {
7573 /* Indirect calls should go through call_indirect */
7574 if (GET_CODE (operands[0]) == REG)
7575 abort ();
7577 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
7578 output_asm_insn (\"crxor 6,6,6\", operands);
7580 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
7581 output_asm_insn (\"creqv 6,6,6\", operands);
7583 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@plt\" : \"bl %z0\";
7584 }"
7585 [(set_attr "type" "branch")
7586 (set_attr "length" "4,8")])
7588 (define_insn ""
7589 [(set (match_operand 0 "" "=fg,fg")
7590 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
7591 (match_operand 2 "" "g,g")))
7592 (use (match_operand:SI 3 "immediate_operand" "O,n"))
7593 (clobber (match_scratch:SI 4 "=l,l"))]
7594 "(INTVAL (operands[3]) & CALL_LONG) == 0"
7595 "*
7596 {
7597 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
7598 output_asm_insn (\"crxor 6,6,6\", operands);
7600 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
7601 output_asm_insn (\"creqv 6,6,6\", operands);
7603 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
7604 }"
7605 [(set_attr "type" "branch")
7606 (set_attr "length" "4,8")])
7608 (define_insn ""
7609 [(set (match_operand 0 "" "=fg,fg")
7610 (call (mem:SI (match_operand:SI 1 "call_operand" "s,s"))
7611 (match_operand 2 "" "fg,fg")))
7612 (use (match_operand:SI 3 "immediate_operand" "O,n"))
7613 (clobber (match_scratch:SI 4 "=l,l"))]
7614 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
7615 && (INTVAL (operands[3]) & CALL_LONG) == 0"
7616 "*
7617 {
7618 /* This should be handled by call_value_indirect */
7619 if (GET_CODE (operands[1]) == REG)
7620 abort ();
7622 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
7623 output_asm_insn (\"crxor 6,6,6\", operands);
7625 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
7626 output_asm_insn (\"creqv 6,6,6\", operands);
7628 return (TARGET_WINDOWS_NT) ? \"bl %z1\;.znop %z1\" : \"bl %z1\;%.\";
7629 }"
7630 [(set_attr "type" "branch")
7631 (set_attr "length" "8,12")])
7633 (define_insn ""
7634 [(set (match_operand 0 "" "=fg,fg")
7635 (call (mem:SI (match_operand:SI 1 "call_operand" "s,s"))
7636 (match_operand 2 "" "fg,fg")))
7637 (use (match_operand:SI 3 "immediate_operand" "O,n"))
7638 (clobber (match_scratch:SI 4 "=l,l"))]
7639 "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
7640 && (INTVAL (operands[3]) & CALL_LONG) == 0"
7641 "*
7642 {
7643 /* This should be handled by call_value_indirect */
7644 if (GET_CODE (operands[1]) == REG)
7645 abort ();
7647 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
7648 output_asm_insn (\"crxor 6,6,6\", operands);
7650 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
7651 output_asm_insn (\"creqv 6,6,6\", operands);
7653 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@plt\" : \"bl %z1\";
7654 }"
7655 [(set_attr "type" "branch")
7656 (set_attr "length" "4,8")])
7658 ;; Call subroutine returning any type.
7659 (define_expand "untyped_call"
7660 [(parallel [(call (match_operand 0 "" "")
7661 (const_int 0))
7662 (match_operand 1 "" "")
7663 (match_operand 2 "" "")])]
7664 ""
7665 "
7666 {
7667 int i;
7669 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx, const0_rtx));
7671 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7672 {
7673 rtx set = XVECEXP (operands[2], 0, i);
7674 emit_move_insn (SET_DEST (set), SET_SRC (set));
7675 }
7677 /* The optimizer does not know that the call sets the function value
7678 registers we stored in the result block. We avoid problems by
7679 claiming that all hard registers are used and clobbered at this
7680 point. */
7681 emit_insn (gen_blockage ());
7683 DONE;
7684 }")
7686 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7687 ;; all of memory. This blocks insns from being moved across this point.
7689 (define_insn "blockage"
7690 [(unspec_volatile [(const_int 0)] 0)]
7691 ""
7692 "")
7694 ;; V.4 specific code to initialize the PIC register
7696 (define_insn "init_v4_pic"
7697 [(set (match_operand:SI 0 "register_operand" "=l")
7698 (unspec [(const_int 0)] 7))]
7699 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS"
7700 "bl _GLOBAL_OFFSET_TABLE_@local-4"
7701 [(set_attr "type" "branch")
7702 (set_attr "length" "4")])
7704 \f
7705 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
7706 ;; signed & unsigned, and one type of branch.
7707 ;;
7708 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
7709 ;; insns, and branches. We store the operands of compares until we see
7710 ;; how it is used.
7711 (define_expand "cmpsi"
7712 [(set (cc0)
7713 (compare (match_operand:SI 0 "gpc_reg_operand" "")
7714 (match_operand:SI 1 "reg_or_short_operand" "")))]
7715 ""
7716 "
7717 {
7718 /* Take care of the possibility that operands[1] might be negative but
7719 this might be a logical operation. That insn doesn't exist. */
7720 if (GET_CODE (operands[1]) == CONST_INT
7721 && INTVAL (operands[1]) < 0)
7722 operands[1] = force_reg (SImode, operands[1]);
7724 rs6000_compare_op0 = operands[0];
7725 rs6000_compare_op1 = operands[1];
7726 rs6000_compare_fp_p = 0;
7727 DONE;
7728 }")
7730 (define_expand "cmpdi"
7731 [(set (cc0)
7732 (compare (match_operand:DI 0 "gpc_reg_operand" "")
7733 (match_operand:DI 1 "reg_or_short_operand" "")))]
7734 "TARGET_POWERPC64"
7735 "
7736 {
7737 /* Take care of the possibility that operands[1] might be negative but
7738 this might be a logical operation. That insn doesn't exist. */
7739 if (GET_CODE (operands[1]) == CONST_INT
7740 && INTVAL (operands[1]) < 0)
7741 operands[1] = force_reg (DImode, operands[1]);
7743 rs6000_compare_op0 = operands[0];
7744 rs6000_compare_op1 = operands[1];
7745 rs6000_compare_fp_p = 0;
7746 DONE;
7747 }")
7749 (define_expand "cmpsf"
7750 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
7751 (match_operand:SF 1 "gpc_reg_operand" "")))]
7752 "TARGET_HARD_FLOAT"
7753 "
7754 {
7755 rs6000_compare_op0 = operands[0];
7756 rs6000_compare_op1 = operands[1];
7757 rs6000_compare_fp_p = 1;
7758 DONE;
7759 }")
7761 (define_expand "cmpdf"
7762 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
7763 (match_operand:DF 1 "gpc_reg_operand" "")))]
7764 "TARGET_HARD_FLOAT"
7765 "
7766 {
7767 rs6000_compare_op0 = operands[0];
7768 rs6000_compare_op1 = operands[1];
7769 rs6000_compare_fp_p = 1;
7770 DONE;
7771 }")
7773 (define_expand "beq"
7774 [(set (match_dup 2) (match_dup 1))
7775 (set (pc)
7776 (if_then_else (eq (match_dup 2)
7777 (const_int 0))
7778 (label_ref (match_operand 0 "" ""))
7779 (pc)))]
7780 ""
7781 "
7782 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7783 operands[1] = gen_rtx (COMPARE, mode,
7784 rs6000_compare_op0, rs6000_compare_op1);
7785 operands[2] = gen_reg_rtx (mode);
7786 }")
7788 (define_expand "bne"
7789 [(set (match_dup 2) (match_dup 1))
7790 (set (pc)
7791 (if_then_else (ne (match_dup 2)
7792 (const_int 0))
7793 (label_ref (match_operand 0 "" ""))
7794 (pc)))]
7795 ""
7796 "
7797 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7798 operands[1] = gen_rtx (COMPARE, mode,
7799 rs6000_compare_op0, rs6000_compare_op1);
7800 operands[2] = gen_reg_rtx (mode);
7801 }")
7803 (define_expand "blt"
7804 [(set (match_dup 2) (match_dup 1))
7805 (set (pc)
7806 (if_then_else (lt (match_dup 2)
7807 (const_int 0))
7808 (label_ref (match_operand 0 "" ""))
7809 (pc)))]
7810 ""
7811 "
7812 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7813 operands[1] = gen_rtx (COMPARE, mode,
7814 rs6000_compare_op0, rs6000_compare_op1);
7815 operands[2] = gen_reg_rtx (mode);
7816 }")
7818 (define_expand "bgt"
7819 [(set (match_dup 2) (match_dup 1))
7820 (set (pc)
7821 (if_then_else (gt (match_dup 2)
7822 (const_int 0))
7823 (label_ref (match_operand 0 "" ""))
7824 (pc)))]
7825 ""
7826 "
7827 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7828 operands[1] = gen_rtx (COMPARE, mode,
7829 rs6000_compare_op0, rs6000_compare_op1);
7830 operands[2] = gen_reg_rtx (mode);
7831 }")
7833 (define_expand "ble"
7834 [(set (match_dup 2) (match_dup 1))
7835 (set (pc)
7836 (if_then_else (le (match_dup 2)
7837 (const_int 0))
7838 (label_ref (match_operand 0 "" ""))
7839 (pc)))]
7840 ""
7841 "
7842 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7843 operands[1] = gen_rtx (COMPARE, mode,
7844 rs6000_compare_op0, rs6000_compare_op1);
7845 operands[2] = gen_reg_rtx (mode);
7846 }")
7848 (define_expand "bge"
7849 [(set (match_dup 2) (match_dup 1))
7850 (set (pc)
7851 (if_then_else (ge (match_dup 2)
7852 (const_int 0))
7853 (label_ref (match_operand 0 "" ""))
7854 (pc)))]
7855 ""
7856 "
7857 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7858 operands[1] = gen_rtx (COMPARE, mode,
7859 rs6000_compare_op0, rs6000_compare_op1);
7860 operands[2] = gen_reg_rtx (mode);
7861 }")
7863 (define_expand "bgtu"
7864 [(set (match_dup 2) (match_dup 1))
7865 (set (pc)
7866 (if_then_else (gtu (match_dup 2)
7867 (const_int 0))
7868 (label_ref (match_operand 0 "" ""))
7869 (pc)))]
7870 ""
7871 "
7872 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
7873 rs6000_compare_op0, rs6000_compare_op1);
7874 operands[2] = gen_reg_rtx (CCUNSmode);
7875 }")
7877 (define_expand "bltu"
7878 [(set (match_dup 2) (match_dup 1))
7879 (set (pc)
7880 (if_then_else (ltu (match_dup 2)
7881 (const_int 0))
7882 (label_ref (match_operand 0 "" ""))
7883 (pc)))]
7884 ""
7885 "
7886 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
7887 rs6000_compare_op0, rs6000_compare_op1);
7888 operands[2] = gen_reg_rtx (CCUNSmode);
7889 }")
7891 (define_expand "bgeu"
7892 [(set (match_dup 2) (match_dup 1))
7893 (set (pc)
7894 (if_then_else (geu (match_dup 2)
7895 (const_int 0))
7896 (label_ref (match_operand 0 "" ""))
7897 (pc)))]
7898 ""
7899 "
7900 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
7901 rs6000_compare_op0, rs6000_compare_op1);
7902 operands[2] = gen_reg_rtx (CCUNSmode);
7903 }")
7905 (define_expand "bleu"
7906 [(set (match_dup 2) (match_dup 1))
7907 (set (pc)
7908 (if_then_else (leu (match_dup 2)
7909 (const_int 0))
7910 (label_ref (match_operand 0 "" ""))
7911 (pc)))]
7912 ""
7913 "
7914 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
7915 rs6000_compare_op0, rs6000_compare_op1);
7916 operands[2] = gen_reg_rtx (CCUNSmode);
7917 }")
7919 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
7920 ;; For SEQ, likewise, except that comparisons with zero should be done
7921 ;; with an scc insns. However, due to the order that combine see the
7922 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
7923 ;; the cases we don't want to handle.
7924 (define_expand "seq"
7925 [(set (match_dup 2) (match_dup 1))
7926 (set (match_operand:SI 0 "gpc_reg_operand" "")
7927 (eq:SI (match_dup 2) (const_int 0)))]
7928 ""
7929 "
7930 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7931 operands[1] = gen_rtx (COMPARE, mode,
7932 rs6000_compare_op0, rs6000_compare_op1);
7933 operands[2] = gen_reg_rtx (mode);
7934 }")
7936 (define_expand "sne"
7937 [(set (match_dup 2) (match_dup 1))
7938 (set (match_operand:SI 0 "gpc_reg_operand" "")
7939 (ne:SI (match_dup 2) (const_int 0)))]
7940 ""
7941 "
7942 { if (! rs6000_compare_fp_p)
7943 FAIL;
7945 operands[1] = gen_rtx (COMPARE, CCFPmode,
7946 rs6000_compare_op0, rs6000_compare_op1);
7947 operands[2] = gen_reg_rtx (CCFPmode);
7948 }")
7950 ;; A > 0 is best done using the portable sequence, so fail in that case.
7951 (define_expand "sgt"
7952 [(set (match_dup 2) (match_dup 1))
7953 (set (match_operand:SI 0 "gpc_reg_operand" "")
7954 (gt:SI (match_dup 2) (const_int 0)))]
7955 ""
7956 "
7957 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7959 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
7960 FAIL;
7962 operands[1] = gen_rtx (COMPARE, mode,
7963 rs6000_compare_op0, rs6000_compare_op1);
7964 operands[2] = gen_reg_rtx (mode);
7965 }")
7967 ;; A < 0 is best done in the portable way for A an integer.
7968 (define_expand "slt"
7969 [(set (match_dup 2) (match_dup 1))
7970 (set (match_operand:SI 0 "gpc_reg_operand" "")
7971 (lt:SI (match_dup 2) (const_int 0)))]
7972 ""
7973 "
7974 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7976 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
7977 FAIL;
7979 operands[1] = gen_rtx (COMPARE, mode,
7980 rs6000_compare_op0, rs6000_compare_op1);
7981 operands[2] = gen_reg_rtx (mode);
7982 }")
7984 (define_expand "sge"
7985 [(set (match_dup 2) (match_dup 1))
7986 (set (match_operand:SI 0 "gpc_reg_operand" "")
7987 (ge:SI (match_dup 2) (const_int 0)))]
7988 ""
7989 "
7990 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7991 operands[1] = gen_rtx (COMPARE, mode,
7992 rs6000_compare_op0, rs6000_compare_op1);
7993 operands[2] = gen_reg_rtx (mode);
7994 }")
7996 ;; A <= 0 is best done the portable way for A an integer.
7997 (define_expand "sle"
7998 [(set (match_dup 2) (match_dup 1))
7999 (set (match_operand:SI 0 "gpc_reg_operand" "")
8000 (le:SI (match_dup 2) (const_int 0)))]
8001 ""
8002 "
8003 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8005 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
8006 FAIL;
8008 operands[1] = gen_rtx (COMPARE, mode,
8009 rs6000_compare_op0, rs6000_compare_op1);
8010 operands[2] = gen_reg_rtx (mode);
8011 }")
8013 (define_expand "sgtu"
8014 [(set (match_dup 2) (match_dup 1))
8015 (set (match_operand:SI 0 "gpc_reg_operand" "")
8016 (gtu:SI (match_dup 2) (const_int 0)))]
8017 ""
8018 "
8019 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
8020 rs6000_compare_op0, rs6000_compare_op1);
8021 operands[2] = gen_reg_rtx (CCUNSmode);
8022 }")
8024 (define_expand "sltu"
8025 [(set (match_dup 2) (match_dup 1))
8026 (set (match_operand:SI 0 "gpc_reg_operand" "")
8027 (ltu:SI (match_dup 2) (const_int 0)))]
8028 ""
8029 "
8030 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
8031 rs6000_compare_op0, rs6000_compare_op1);
8032 operands[2] = gen_reg_rtx (CCUNSmode);
8033 }")
8035 (define_expand "sgeu"
8036 [(set (match_dup 2) (match_dup 1))
8037 (set (match_operand:SI 0 "gpc_reg_operand" "")
8038 (geu:SI (match_dup 2) (const_int 0)))]
8039 ""
8040 "
8041 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
8042 rs6000_compare_op0, rs6000_compare_op1);
8043 operands[2] = gen_reg_rtx (CCUNSmode);
8044 }")
8046 (define_expand "sleu"
8047 [(set (match_dup 2) (match_dup 1))
8048 (set (match_operand:SI 0 "gpc_reg_operand" "")
8049 (leu:SI (match_dup 2) (const_int 0)))]
8050 ""
8051 "
8052 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
8053 rs6000_compare_op0, rs6000_compare_op1);
8054 operands[2] = gen_reg_rtx (CCUNSmode);
8055 }")
8056 \f
8057 ;; Here are the actual compare insns.
8058 (define_insn ""
8059 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
8060 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
8061 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
8062 ""
8063 "{cmp%I2|cmpw%I2} %0,%1,%2"
8064 [(set_attr "type" "compare")])
8066 (define_insn ""
8067 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
8068 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
8069 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
8070 "TARGET_POWERPC64"
8071 "cmpd%I2 %0,%1,%2"
8072 [(set_attr "type" "compare")])
8074 ;; If we are comparing a register for equality with a large constant,
8075 ;; we can do this with an XOR followed by a compare. But we need a scratch
8076 ;; register for the result of the XOR.
8078 (define_split
8079 [(set (match_operand:CC 0 "cc_reg_operand" "")
8080 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
8081 (match_operand:SI 2 "non_short_cint_operand" "")))
8082 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
8083 "find_single_use (operands[0], insn, 0)
8084 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
8085 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
8086 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
8087 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
8088 "
8089 {
8090 /* Get the constant we are comparing against, C, and see what it looks like
8091 sign-extended to 16 bits. Then see what constant could be XOR'ed
8092 with C to get the sign-extended value. */
8094 int c = INTVAL (operands[2]);
8095 int sextc = (c << 16) >> 16;
8096 int xorv = c ^ sextc;
8098 operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv);
8099 operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc);
8100 }")
8102 (define_insn ""
8103 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
8104 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
8105 (match_operand:SI 2 "reg_or_u_short_operand" "rI")))]
8106 ""
8107 "{cmpl%I2|cmplw%I2} %0,%1,%W2"
8108 [(set_attr "type" "compare")])
8110 (define_insn ""
8111 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
8112 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
8113 (match_operand:DI 2 "reg_or_u_short_operand" "rI")))]
8114 ""
8115 "cmpld%I2 %0,%1,%W2"
8116 [(set_attr "type" "compare")])
8118 ;; The following two insns don't exist as single insns, but if we provide
8119 ;; them, we can swap an add and compare, which will enable us to overlap more
8120 ;; of the required delay between a compare and branch. We generate code for
8121 ;; them by splitting.
8123 (define_insn ""
8124 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
8125 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
8126 (match_operand:SI 2 "short_cint_operand" "i")))
8127 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8128 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
8129 ""
8130 "#"
8131 [(set_attr "length" "8")])
8133 (define_insn ""
8134 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
8135 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
8136 (match_operand:SI 2 "u_short_cint_operand" "i")))
8137 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8138 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
8139 ""
8140 "#"
8141 [(set_attr "length" "8")])
8143 (define_split
8144 [(set (match_operand:CC 3 "cc_reg_operand" "")
8145 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
8146 (match_operand:SI 2 "short_cint_operand" "")))
8147 (set (match_operand:SI 0 "gpc_reg_operand" "")
8148 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
8149 ""
8150 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
8151 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
8153 (define_split
8154 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
8155 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
8156 (match_operand:SI 2 "u_short_cint_operand" "")))
8157 (set (match_operand:SI 0 "gpc_reg_operand" "")
8158 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
8159 ""
8160 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
8161 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
8163 (define_insn ""
8164 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
8165 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
8166 (match_operand:SF 2 "gpc_reg_operand" "f")))]
8167 "TARGET_HARD_FLOAT"
8168 "fcmpu %0,%1,%2"
8169 [(set_attr "type" "fpcompare")])
8171 (define_insn ""
8172 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
8173 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
8174 (match_operand:DF 2 "gpc_reg_operand" "f")))]
8175 "TARGET_HARD_FLOAT"
8176 "fcmpu %0,%1,%2"
8177 [(set_attr "type" "fpcompare")])
8178 \f
8179 ;; Now we have the scc insns. We can do some combinations because of the
8180 ;; way the machine works.
8181 ;;
8182 ;; Note that this is probably faster if we can put an insn between the
8183 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
8184 ;; cases the insns below which don't use an intermediate CR field will
8185 ;; be used instead.
8186 (define_insn ""
8187 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8188 (match_operator:SI 1 "scc_comparison_operator"
8189 [(match_operand 2 "cc_reg_operand" "y")
8190 (const_int 0)]))]
8191 ""
8192 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
8193 [(set_attr "length" "12")])
8195 (define_insn ""
8196 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8197 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
8198 [(match_operand 2 "cc_reg_operand" "y")
8199 (const_int 0)])
8200 (const_int 0)))
8201 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
8202 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
8203 ""
8204 "%D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1"
8205 [(set_attr "type" "delayed_compare")
8206 (set_attr "length" "12")])
8208 (define_insn ""
8209 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8210 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
8211 [(match_operand 2 "cc_reg_operand" "y")
8212 (const_int 0)])
8213 (match_operand:SI 3 "const_int_operand" "n")))]
8214 ""
8215 "*
8216 {
8217 int is_bit = ccr_bit (operands[1], 1);
8218 int put_bit = 31 - (INTVAL (operands[3]) & 31);
8219 int count;
8221 if (is_bit >= put_bit)
8222 count = is_bit - put_bit;
8223 else
8224 count = 32 - (put_bit - is_bit);
8226 operands[4] = gen_rtx (CONST_INT, VOIDmode, count);
8227 operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit);
8229 return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
8230 }"
8231 [(set_attr "length" "12")])
8233 (define_insn ""
8234 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8235 (compare:CC
8236 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
8237 [(match_operand 2 "cc_reg_operand" "y")
8238 (const_int 0)])
8239 (match_operand:SI 3 "const_int_operand" "n"))
8240 (const_int 0)))
8241 (set (match_operand:SI 4 "gpc_reg_operand" "=r")
8242 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
8243 (match_dup 3)))]
8244 ""
8245 "*
8246 {
8247 int is_bit = ccr_bit (operands[1], 1);
8248 int put_bit = 31 - (INTVAL (operands[3]) & 31);
8249 int count;
8251 if (is_bit >= put_bit)
8252 count = is_bit - put_bit;
8253 else
8254 count = 32 - (put_bit - is_bit);
8256 operands[5] = gen_rtx (CONST_INT, VOIDmode, count);
8257 operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit);
8259 return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
8260 }"
8261 [(set_attr "type" "delayed_compare")
8262 (set_attr "length" "12")])
8264 ;; If we are comparing the result of two comparisons, this can be done
8265 ;; using creqv or crxor.
8267 (define_insn ""
8268 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
8269 (compare:CCEQ (match_operator 1 "scc_comparison_operator"
8270 [(match_operand 2 "cc_reg_operand" "y")
8271 (const_int 0)])
8272 (match_operator 3 "scc_comparison_operator"
8273 [(match_operand 4 "cc_reg_operand" "y")
8274 (const_int 0)])))]
8275 "REGNO (operands[2]) != REGNO (operands[4])"
8276 "*
8277 {
8278 enum rtx_code code1, code2;
8280 code1 = GET_CODE (operands[1]);
8281 code2 = GET_CODE (operands[3]);
8283 if ((code1 == EQ || code1 == LT || code1 == GT
8284 || code1 == LTU || code1 == GTU
8285 || (code1 != NE && GET_MODE (operands[2]) == CCFPmode))
8286 !=
8287 (code2 == EQ || code2 == LT || code2 == GT
8288 || code2 == LTU || code2 == GTU
8289 || (code2 != NE && GET_MODE (operands[4]) == CCFPmode)))
8290 return \"%C1%C3crxor %E0,%j1,%j3\";
8291 else
8292 return \"%C1%C3creqv %E0,%j1,%j3\";
8293 }"
8294 [(set_attr "length" "12")])
8296 ;; There is a 3 cycle delay between consecutive mfcr instructions
8297 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
8299 (define_peephole
8300 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8301 (match_operator:SI 1 "scc_comparison_operator"
8302 [(match_operand 2 "cc_reg_operand" "y")
8303 (const_int 0)]))
8304 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
8305 (match_operator:SI 4 "scc_comparison_operator"
8306 [(match_operand 5 "cc_reg_operand" "y")
8307 (const_int 0)]))]
8308 "REGNO (operands[2]) != REGNO (operands[5])"
8309 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
8310 [(set_attr "length" "20")])
8312 ;; There are some scc insns that can be done directly, without a compare.
8313 ;; These are faster because they don't involve the communications between
8314 ;; the FXU and branch units. In fact, we will be replacing all of the
8315 ;; integer scc insns here or in the portable methods in emit_store_flag.
8316 ;;
8317 ;; Also support (neg (scc ..)) since that construct is used to replace
8318 ;; branches, (plus (scc ..) ..) since that construct is common and
8319 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
8320 ;; cases where it is no more expensive than (neg (scc ..)).
8322 ;; Have reload force a constant into a register for the simple insns that
8323 ;; otherwise won't accept constants. We do this because it is faster than
8324 ;; the cmp/mfcr sequence we would otherwise generate.
8326 (define_insn ""
8327 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
8328 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
8329 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
8330 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
8331 ""
8332 "@
8333 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
8334 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
8335 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
8336 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
8337 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
8338 [(set_attr "length" "12,8,12,12,12")])
8340 (define_insn ""
8341 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
8342 (compare:CC
8343 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
8344 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
8345 (const_int 0)))
8346 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
8347 (eq:SI (match_dup 1) (match_dup 2)))
8348 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
8349 ""
8350 "@
8351 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
8352 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
8353 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
8354 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
8355 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0"
8356 [(set_attr "type" "compare")
8357 (set_attr "length" "12,8,12,12,12")])
8359 ;; We have insns of the form shown by the first define_insn below. If
8360 ;; there is something inside the comparison operation, we must split it.
8361 (define_split
8362 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8363 (plus:SI (match_operator 1 "comparison_operator"
8364 [(match_operand:SI 2 "" "")
8365 (match_operand:SI 3
8366 "reg_or_cint_operand" "")])
8367 (match_operand:SI 4 "gpc_reg_operand" "")))
8368 (clobber (match_operand:SI 5 "register_operand" ""))]
8369 "! gpc_reg_operand (operands[2], SImode)"
8370 [(set (match_dup 5) (match_dup 2))
8371 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
8372 (match_dup 4)))])
8374 (define_insn ""
8375 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
8376 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
8377 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
8378 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
8379 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
8380 ""
8381 "@
8382 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
8383 {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3
8384 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
8385 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
8386 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
8387 [(set_attr "length" "12,8,12,12,12")])
8389 (define_insn ""
8390 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x")
8391 (compare:CC
8392 (plus:SI
8393 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
8394 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
8395 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
8396 (const_int 0)))
8397 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
8398 ""
8399 "@
8400 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
8401 {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3
8402 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
8403 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
8404 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3"
8405 [(set_attr "type" "compare")
8406 (set_attr "length" "12,8,12,12,12")])
8408 (define_insn ""
8409 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x")
8410 (compare:CC
8411 (plus:SI
8412 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
8413 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
8414 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
8415 (const_int 0)))
8416 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
8417 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
8418 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
8419 ""
8420 "@
8421 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
8422 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
8423 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
8424 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
8425 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3"
8426 [(set_attr "type" "compare")
8427 (set_attr "length" "12,8,12,12,12")])
8429 (define_insn ""
8430 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
8431 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
8432 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
8433 ""
8434 "@
8435 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
8436 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
8437 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
8438 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
8439 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
8440 [(set_attr "length" "12,8,12,12,12")])
8442 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
8443 ;; since it nabs/sr is just as fast.
8444 (define_insn ""
8445 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8446 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
8447 (const_int 31)))
8448 (clobber (match_scratch:SI 2 "=&r"))]
8449 "!TARGET_POWER"
8450 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
8451 [(set_attr "length" "8")])
8453 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
8454 (define_insn ""
8455 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8456 (plus:SI (lshiftrt:SI
8457 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
8458 (const_int 31))
8459 (match_operand:SI 2 "gpc_reg_operand" "r")))
8460 (clobber (match_scratch:SI 3 "=&r"))]
8461 ""
8462 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
8463 [(set_attr "length" "8")])
8465 (define_insn ""
8466 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8467 (compare:CC
8468 (plus:SI (lshiftrt:SI
8469 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
8470 (const_int 31))
8471 (match_operand:SI 2 "gpc_reg_operand" "r"))
8472 (const_int 0)))
8473 (clobber (match_scratch:SI 3 "=&r"))]
8474 ""
8475 "{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2"
8476 [(set_attr "type" "compare")
8477 (set_attr "length" "8")])
8479 (define_insn ""
8480 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
8481 (compare:CC
8482 (plus:SI (lshiftrt:SI
8483 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
8484 (const_int 31))
8485 (match_operand:SI 2 "gpc_reg_operand" "r"))
8486 (const_int 0)))
8487 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8488 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
8489 (match_dup 2)))
8490 (clobber (match_scratch:SI 3 "=&r"))]
8491 ""
8492 "{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2"
8493 [(set_attr "type" "compare")
8494 (set_attr "length" "8")])
8496 (define_insn ""
8497 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8498 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8499 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
8500 (clobber (match_scratch:SI 3 "=r,X"))]
8501 "TARGET_POWER"
8502 "@
8503 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
8504 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
8505 [(set_attr "length" "12")])
8507 (define_insn ""
8508 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x")
8509 (compare:CC
8510 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8511 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
8512 (const_int 0)))
8513 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8514 (le:SI (match_dup 1) (match_dup 2)))
8515 (clobber (match_scratch:SI 3 "=r,X"))]
8516 "TARGET_POWER"
8517 "@
8518 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
8519 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31"
8520 [(set_attr "type" "compare,delayed_compare")
8521 (set_attr "length" "12")])
8523 (define_insn ""
8524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8525 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8526 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
8527 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
8528 (clobber (match_scratch:SI 4 "=&r,&r"))]
8529 "TARGET_POWER"
8530 "@
8531 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
8532 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3"
8533 [(set_attr "length" "12")])
8535 (define_insn ""
8536 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
8537 (compare:CC
8538 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8539 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
8540 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8541 (const_int 0)))
8542 (clobber (match_scratch:SI 4 "=&r,&r"))]
8543 "TARGET_POWER"
8544 "@
8545 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
8546 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3"
8547 [(set_attr "type" "compare")
8548 (set_attr "length" "12")])
8550 (define_insn ""
8551 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
8552 (compare:CC
8553 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8554 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
8555 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8556 (const_int 0)))
8557 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8558 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
8559 (clobber (match_scratch:SI 4 "=&r,&r"))]
8560 "TARGET_POWER"
8561 "@
8562 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
8563 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3"
8564 [(set_attr "type" "compare")
8565 (set_attr "length" "12")])
8567 (define_insn ""
8568 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8569 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8570 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
8571 "TARGET_POWER"
8572 "@
8573 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
8574 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
8575 [(set_attr "length" "12")])
8577 (define_insn ""
8578 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8579 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8580 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
8581 ""
8582 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
8583 [(set_attr "length" "12")])
8585 (define_insn ""
8586 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
8587 (compare:CC
8588 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8589 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8590 (const_int 0)))
8591 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8592 (leu:SI (match_dup 1) (match_dup 2)))]
8593 ""
8594 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"
8595 [(set_attr "type" "compare")
8596 (set_attr "length" "12")])
8598 (define_insn ""
8599 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8600 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8601 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8602 (match_operand:SI 3 "gpc_reg_operand" "r")))
8603 (clobber (match_scratch:SI 4 "=&r"))]
8604 ""
8605 "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3"
8606 [(set_attr "length" "8")])
8608 (define_insn ""
8609 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8610 (compare:CC
8611 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8612 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8613 (match_operand:SI 3 "gpc_reg_operand" "r"))
8614 (const_int 0)))
8615 (clobber (match_scratch:SI 4 "=&r"))]
8616 ""
8617 "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3"
8618 [(set_attr "type" "compare")
8619 (set_attr "length" "8")])
8621 (define_insn ""
8622 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
8623 (compare:CC
8624 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8625 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8626 (match_operand:SI 3 "gpc_reg_operand" "r"))
8627 (const_int 0)))
8628 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8629 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
8630 (clobber (match_scratch:SI 4 "=&r"))]
8631 ""
8632 "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3"
8633 [(set_attr "type" "compare")
8634 (set_attr "length" "8")])
8636 (define_insn ""
8637 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8638 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8639 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
8640 ""
8641 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
8642 [(set_attr "length" "12")])
8644 (define_insn ""
8645 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8646 (and:SI (neg:SI
8647 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8648 (match_operand:SI 2 "reg_or_short_operand" "rI")))
8649 (match_operand:SI 3 "gpc_reg_operand" "r")))
8650 (clobber (match_scratch:SI 4 "=&r"))]
8651 ""
8652 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
8653 [(set_attr "length" "12")])
8655 (define_insn ""
8656 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8657 (compare:CC
8658 (and:SI (neg:SI
8659 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8660 (match_operand:SI 2 "reg_or_short_operand" "rI")))
8661 (match_operand:SI 3 "gpc_reg_operand" "r"))
8662 (const_int 0)))
8663 (clobber (match_scratch:SI 4 "=&r"))]
8664 ""
8665 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"
8666 [(set_attr "type" "compare")
8667 (set_attr "length" "12")])
8669 (define_insn ""
8670 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
8671 (compare:CC
8672 (and:SI (neg:SI
8673 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8674 (match_operand:SI 2 "reg_or_short_operand" "rI")))
8675 (match_operand:SI 3 "gpc_reg_operand" "r"))
8676 (const_int 0)))
8677 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8678 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
8679 (clobber (match_scratch:SI 4 "=&r"))]
8680 ""
8681 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"
8682 [(set_attr "type" "compare")
8683 (set_attr "length" "12")])
8685 (define_insn ""
8686 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8687 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8688 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
8689 "TARGET_POWER"
8690 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
8691 [(set_attr "length" "12")])
8693 (define_insn ""
8694 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
8695 (compare:CC
8696 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8697 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8698 (const_int 0)))
8699 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8700 (lt:SI (match_dup 1) (match_dup 2)))]
8701 "TARGET_POWER"
8702 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31"
8703 [(set_attr "type" "delayed_compare")
8704 (set_attr "length" "12")])
8706 (define_insn ""
8707 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8708 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8709 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8710 (match_operand:SI 3 "gpc_reg_operand" "r")))
8711 (clobber (match_scratch:SI 4 "=&r"))]
8712 "TARGET_POWER"
8713 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
8714 [(set_attr "length" "12")])
8716 (define_insn ""
8717 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8718 (compare:CC
8719 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8720 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8721 (match_operand:SI 3 "gpc_reg_operand" "r"))
8722 (const_int 0)))
8723 (clobber (match_scratch:SI 4 "=&r"))]
8724 "TARGET_POWER"
8725 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3"
8726 [(set_attr "type" "compare")
8727 (set_attr "length" "12")])
8729 (define_insn ""
8730 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
8731 (compare:CC
8732 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8733 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8734 (match_operand:SI 3 "gpc_reg_operand" "r"))
8735 (const_int 0)))
8736 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8737 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
8738 (clobber (match_scratch:SI 4 "=&r"))]
8739 "TARGET_POWER"
8740 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3"
8741 [(set_attr "type" "compare")
8742 (set_attr "length" "12")])
8744 (define_insn ""
8745 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8746 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8747 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
8748 "TARGET_POWER"
8749 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
8750 [(set_attr "length" "12")])
8752 (define_insn ""
8753 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8754 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8755 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
8756 ""
8757 "@
8758 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
8759 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
8760 [(set_attr "length" "12")])
8762 (define_insn ""
8763 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
8764 (compare:CC
8765 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8766 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
8767 (const_int 0)))
8768 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8769 (ltu:SI (match_dup 1) (match_dup 2)))]
8770 ""
8771 "@
8772 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
8773 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"
8774 [(set_attr "type" "compare")
8775 (set_attr "length" "12")])
8777 (define_insn ""
8778 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
8779 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
8780 (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
8781 (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))
8782 (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
8783 ""
8784 "@
8785 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
8786 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
8787 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
8788 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
8789 [(set_attr "length" "12")])
8791 (define_insn ""
8792 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
8793 (compare:CC
8794 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8795 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
8796 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8797 (const_int 0)))
8798 (clobber (match_scratch:SI 4 "=&r,&r"))]
8799 ""
8800 "@
8801 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
8802 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3"
8803 [(set_attr "type" "compare")
8804 (set_attr "length" "12")])
8806 (define_insn ""
8807 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
8808 (compare:CC
8809 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8810 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
8811 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8812 (const_int 0)))
8813 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8814 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
8815 (clobber (match_scratch:SI 4 "=&r,&r"))]
8816 ""
8817 "@
8818 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
8819 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
8820 [(set_attr "type" "compare")
8821 (set_attr "length" "12")])
8823 (define_insn ""
8824 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8825 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8826 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
8827 ""
8828 "@
8829 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
8830 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
8831 [(set_attr "length" "8")])
8833 (define_insn ""
8834 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8835 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8836 (match_operand:SI 2 "reg_or_short_operand" "rI")))
8837 (clobber (match_scratch:SI 3 "=r"))]
8838 "TARGET_POWER"
8839 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
8840 [(set_attr "length" "12")])
8842 (define_insn ""
8843 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
8844 (compare:CC
8845 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8846 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8847 (const_int 0)))
8848 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8849 (ge:SI (match_dup 1) (match_dup 2)))
8850 (clobber (match_scratch:SI 3 "=r"))]
8851 "TARGET_POWER"
8852 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3"
8853 [(set_attr "type" "compare")
8854 (set_attr "length" "12")])
8856 (define_insn ""
8857 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8858 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8859 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8860 (match_operand:SI 3 "gpc_reg_operand" "r")))
8861 (clobber (match_scratch:SI 4 "=&r"))]
8862 "TARGET_POWER"
8863 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
8864 [(set_attr "length" "12")])
8866 (define_insn ""
8867 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8868 (compare:CC
8869 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8870 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8871 (match_operand:SI 3 "gpc_reg_operand" "r"))
8872 (const_int 0)))
8873 (clobber (match_scratch:SI 4 "=&r"))]
8874 "TARGET_POWER"
8875 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3"
8876 [(set_attr "type" "compare")
8877 (set_attr "length" "12")])
8879 (define_insn ""
8880 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
8881 (compare:CC
8882 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8883 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8884 (match_operand:SI 3 "gpc_reg_operand" "r"))
8885 (const_int 0)))
8886 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8887 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
8888 (clobber (match_scratch:SI 4 "=&r"))]
8889 "TARGET_POWER"
8890 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3"
8891 [(set_attr "type" "compare")
8892 (set_attr "length" "12")])
8894 (define_insn ""
8895 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8896 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8897 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
8898 "TARGET_POWER"
8899 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
8900 [(set_attr "length" "12")])
8902 ;; This is (and (neg (ge X (const_int 0))) Y).
8903 (define_insn ""
8904 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8905 (and:SI (neg:SI
8906 (lshiftrt:SI
8907 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
8908 (const_int 31)))
8909 (match_operand:SI 2 "gpc_reg_operand" "r")))
8910 (clobber (match_scratch:SI 3 "=&r"))]
8911 ""
8912 "{srai|srawi} %3,%1,31\;andc %0,%2,%3"
8913 [(set_attr "length" "8")])
8915 (define_insn ""
8916 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8917 (compare:CC
8918 (and:SI (neg:SI
8919 (lshiftrt:SI
8920 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
8921 (const_int 31)))
8922 (match_operand:SI 2 "gpc_reg_operand" "r"))
8923 (const_int 0)))
8924 (clobber (match_scratch:SI 3 "=&r"))]
8925 ""
8926 "{srai|srawi} %3,%1,31\;andc. %3,%2,%3"
8927 [(set_attr "type" "compare")
8928 (set_attr "length" "8")])
8930 (define_insn ""
8931 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
8932 (compare:CC
8933 (and:SI (neg:SI
8934 (lshiftrt:SI
8935 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
8936 (const_int 31)))
8937 (match_operand:SI 2 "gpc_reg_operand" "r"))
8938 (const_int 0)))
8939 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8940 (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
8941 (const_int 31)))
8942 (match_dup 2)))
8943 (clobber (match_scratch:SI 3 "=&r"))]
8944 ""
8945 "{srai|srawi} %3,%1,31\;andc. %0,%2,%3"
8946 [(set_attr "type" "compare")
8947 (set_attr "length" "8")])
8949 (define_insn ""
8950 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8951 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8952 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
8953 ""
8954 "@
8955 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
8956 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
8957 [(set_attr "length" "12")])
8959 (define_insn ""
8960 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
8961 (compare:CC
8962 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8963 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
8964 (const_int 0)))
8965 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8966 (geu:SI (match_dup 1) (match_dup 2)))]
8967 ""
8968 "@
8969 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
8970 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"
8971 [(set_attr "type" "compare")
8972 (set_attr "length" "12")])
8974 (define_insn ""
8975 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8976 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8977 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
8978 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
8979 (clobber (match_scratch:SI 4 "=&r,&r"))]
8980 ""
8981 "@
8982 {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3
8983 {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3"
8984 [(set_attr "length" "8")])
8986 (define_insn ""
8987 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
8988 (compare:CC
8989 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8990 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
8991 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8992 (const_int 0)))
8993 (clobber (match_scratch:SI 4 "=&r,&r"))]
8994 ""
8995 "@
8996 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
8997 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3"
8998 [(set_attr "type" "compare")
8999 (set_attr "length" "8")])
9001 (define_insn ""
9002 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
9003 (compare:CC
9004 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9005 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
9006 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9007 (const_int 0)))
9008 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9009 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9010 (clobber (match_scratch:SI 4 "=&r,&r"))]
9011 ""
9012 "@
9013 {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3
9014 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3"
9015 [(set_attr "type" "compare")
9016 (set_attr "length" "8")])
9018 (define_insn ""
9019 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9020 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9021 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
9022 ""
9023 "@
9024 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
9025 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
9026 [(set_attr "length" "12")])
9028 (define_insn ""
9029 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9030 (and:SI (neg:SI
9031 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9032 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
9033 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
9034 (clobber (match_scratch:SI 4 "=&r,&r"))]
9035 ""
9036 "@
9037 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4
9038 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
9039 [(set_attr "length" "12")])
9041 (define_insn ""
9042 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
9043 (compare:CC
9044 (and:SI (neg:SI
9045 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9046 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
9047 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9048 (const_int 0)))
9049 (clobber (match_scratch:SI 4 "=&r,&r"))]
9050 ""
9051 "@
9052 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
9053 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"
9054 [(set_attr "type" "compare")
9055 (set_attr "length" "12")])
9057 (define_insn ""
9058 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
9059 (compare:CC
9060 (and:SI (neg:SI
9061 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9062 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
9063 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9064 (const_int 0)))
9065 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9066 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
9067 (clobber (match_scratch:SI 4 "=&r,&r"))]
9068 ""
9069 "@
9070 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
9071 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"
9072 [(set_attr "type" "compare")
9073 (set_attr "length" "12")])
9075 (define_insn ""
9076 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9077 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9078 (const_int 0)))]
9079 ""
9080 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
9081 [(set_attr "length" "12")])
9083 (define_insn ""
9084 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
9085 (compare:CC
9086 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9087 (const_int 0))
9088 (const_int 0)))
9089 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9090 (gt:SI (match_dup 1) (const_int 0)))]
9091 ""
9092 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31"
9093 [(set_attr "type" "delayed_compare")
9094 (set_attr "length" "12")])
9096 (define_insn ""
9097 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9098 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9099 (match_operand:SI 2 "reg_or_short_operand" "r")))]
9100 "TARGET_POWER"
9101 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
9102 [(set_attr "length" "12")])
9104 (define_insn ""
9105 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
9106 (compare:CC
9107 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9108 (match_operand:SI 2 "reg_or_short_operand" "r"))
9109 (const_int 0)))
9110 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9111 (gt:SI (match_dup 1) (match_dup 2)))]
9112 "TARGET_POWER"
9113 "doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31"
9114 [(set_attr "type" "delayed_compare")
9115 (set_attr "length" "12")])
9117 (define_insn ""
9118 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9119 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9120 (const_int 0))
9121 (match_operand:SI 2 "gpc_reg_operand" "r")))
9122 (clobber (match_scratch:SI 3 "=&r"))]
9123 ""
9124 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2"
9125 [(set_attr "length" "12")])
9127 (define_insn ""
9128 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
9129 (compare:CC
9130 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9131 (const_int 0))
9132 (match_operand:SI 2 "gpc_reg_operand" "r"))
9133 (const_int 0)))
9134 (clobber (match_scratch:SI 3 "=&r"))]
9135 ""
9136 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2"
9137 [(set_attr "type" "compare")
9138 (set_attr "length" "12")])
9140 (define_insn ""
9141 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
9142 (compare:CC
9143 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9144 (const_int 0))
9145 (match_operand:SI 2 "gpc_reg_operand" "r"))
9146 (const_int 0)))
9147 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9148 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
9149 (clobber (match_scratch:SI 3 "=&r"))]
9150 ""
9151 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2"
9152 [(set_attr "type" "compare")
9153 (set_attr "length" "12")])
9155 (define_insn ""
9156 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9157 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9158 (match_operand:SI 2 "reg_or_short_operand" "r"))
9159 (match_operand:SI 3 "gpc_reg_operand" "r")))
9160 (clobber (match_scratch:SI 4 "=&r"))]
9161 "TARGET_POWER"
9162 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
9163 [(set_attr "length" "12")])
9165 (define_insn ""
9166 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
9167 (compare:CC
9168 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9169 (match_operand:SI 2 "reg_or_short_operand" "r"))
9170 (match_operand:SI 3 "gpc_reg_operand" "r"))
9171 (const_int 0)))
9172 (clobber (match_scratch:SI 4 "=&r"))]
9173 "TARGET_POWER"
9174 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3"
9175 [(set_attr "type" "compare")
9176 (set_attr "length" "12")])
9178 (define_insn ""
9179 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
9180 (compare:CC
9181 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9182 (match_operand:SI 2 "reg_or_short_operand" "r"))
9183 (match_operand:SI 3 "gpc_reg_operand" "r"))
9184 (const_int 0)))
9185 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9186 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9187 (clobber (match_scratch:SI 4 "=&r"))]
9188 "TARGET_POWER"
9189 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3"
9190 [(set_attr "type" "compare")
9191 (set_attr "length" "12")])
9193 (define_insn ""
9194 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9195 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9196 (const_int 0))))]
9197 ""
9198 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
9199 [(set_attr "length" "12")])
9201 (define_insn ""
9202 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9203 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9204 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
9205 "TARGET_POWER"
9206 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
9207 [(set_attr "length" "12")])
9209 (define_insn ""
9210 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9211 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9212 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
9213 ""
9214 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
9215 [(set_attr "length" "12")])
9217 (define_insn ""
9218 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
9219 (compare:CC
9220 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9221 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9222 (const_int 0)))
9223 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9224 (gtu:SI (match_dup 1) (match_dup 2)))]
9225 ""
9226 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"
9227 [(set_attr "type" "compare")
9228 (set_attr "length" "12")])
9230 (define_insn ""
9231 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
9232 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
9233 (match_operand:SI 2 "reg_or_short_operand" "I,r,rI"))
9234 (match_operand:SI 3 "reg_or_short_operand" "r,r,I")))
9235 (clobber (match_scratch:SI 4 "=&r,&r,&r"))]
9236 ""
9237 "@
9238 {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3
9239 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
9240 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
9241 [(set_attr "length" "8,12,12")])
9243 (define_insn ""
9244 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
9245 (compare:CC
9246 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9247 (match_operand:SI 2 "reg_or_short_operand" "I,r"))
9248 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9249 (const_int 0)))
9250 (clobber (match_scratch:SI 4 "=&r,&r"))]
9251 ""
9252 "@
9253 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
9254 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
9255 [(set_attr "type" "compare")
9256 (set_attr "length" "8,12")])
9258 (define_insn ""
9259 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
9260 (compare:CC
9261 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9262 (match_operand:SI 2 "reg_or_short_operand" "I,r"))
9263 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9264 (const_int 0)))
9265 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9266 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9267 (clobber (match_scratch:SI 4 "=&r,&r"))]
9268 ""
9269 "@
9270 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
9271 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
9272 [(set_attr "type" "compare")
9273 (set_attr "length" "8,12")])
9275 (define_insn ""
9276 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9277 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9278 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
9279 ""
9280 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
9281 [(set_attr "length" "8")])
9282 \f
9283 ;; Define both directions of branch and return. If we need a reload
9284 ;; register, we'd rather use CR0 since it is much easier to copy a
9285 ;; register CC value to there.
9287 (define_insn ""
9288 [(set (pc)
9289 (if_then_else (match_operator 1 "branch_comparison_operator"
9290 [(match_operand 2
9291 "cc_reg_operand" "x,?y")
9292 (const_int 0)])
9293 (label_ref (match_operand 0 "" ""))
9294 (pc)))]
9295 ""
9296 "*
9297 {
9298 if (get_attr_length (insn) == 8)
9299 return \"%C1bc %t1,%j1,%l0\";
9300 else
9301 return \"%C1bc %T1,%j1,%$+8\;b %l0\";
9303 }"
9304 [(set_attr "type" "branch")])
9306 (define_insn ""
9307 [(set (pc)
9308 (if_then_else (match_operator 0 "branch_comparison_operator"
9309 [(match_operand 1
9310 "cc_reg_operand" "x,?y")
9311 (const_int 0)])
9312 (return)
9313 (pc)))]
9314 "direct_return ()"
9315 "{%C0bcr|%C0bclr} %t0,%j0"
9316 [(set_attr "type" "branch")
9317 (set_attr "length" "8")])
9319 (define_insn ""
9320 [(set (pc)
9321 (if_then_else (match_operator 1 "branch_comparison_operator"
9322 [(match_operand 2
9323 "cc_reg_operand" "x,?y")
9324 (const_int 0)])
9325 (pc)
9326 (label_ref (match_operand 0 "" ""))))]
9327 ""
9328 "*
9329 {
9330 if (get_attr_length (insn) == 8)
9331 return \"%C1bc %T1,%j1,%l0\";
9332 else
9333 return \"%C1bc %t1,%j1,%$+8\;b %l0\";
9334 }"
9335 [(set_attr "type" "branch")])
9337 (define_insn ""
9338 [(set (pc)
9339 (if_then_else (match_operator 0 "branch_comparison_operator"
9340 [(match_operand 1
9341 "cc_reg_operand" "x,?y")
9342 (const_int 0)])
9343 (pc)
9344 (return)))]
9345 "direct_return ()"
9346 "{%C0bcr|%C0bclr} %T0,%j0"
9347 [(set_attr "type" "branch")
9348 (set_attr "length" "8")])
9350 ;; Unconditional branch and return.
9352 (define_insn "jump"
9353 [(set (pc)
9354 (label_ref (match_operand 0 "" "")))]
9355 ""
9356 "b %l0"
9357 [(set_attr "type" "branch")])
9359 (define_insn "return"
9360 [(return)]
9361 "direct_return ()"
9362 "{br|blr}"
9363 [(set_attr "type" "jmpreg")])
9365 (define_insn "indirect_jump"
9366 [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))]
9367 ""
9368 "@
9369 bctr
9370 {br|blr}"
9371 [(set_attr "type" "jmpreg")])
9373 (define_insn ""
9374 [(set (pc) (match_operand:DI 0 "register_operand" "c,l"))]
9375 "TARGET_POWERPC64"
9376 "@
9377 bctr
9378 {br|blr}"
9379 [(set_attr "type" "jmpreg")])
9381 ;; Table jump for switch statements:
9382 (define_expand "tablejump"
9383 [(use (match_operand 0 "" ""))
9384 (use (label_ref (match_operand 1 "" "")))]
9385 ""
9386 "
9387 {
9388 if (TARGET_32BIT)
9389 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
9390 else
9391 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
9392 DONE;
9393 }")
9395 (define_expand "tablejumpsi"
9396 [(set (match_dup 3)
9397 (plus:SI (match_operand:SI 0 "" "")
9398 (match_dup 2)))
9399 (parallel [(set (pc) (match_dup 3))
9400 (use (label_ref (match_operand 1 "" "")))])]
9401 ""
9402 "
9403 { operands[0] = force_reg (SImode, operands[0]);
9404 operands[2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[1]));
9405 operands[3] = gen_reg_rtx (SImode);
9406 }")
9408 (define_expand "tablejumpdi"
9409 [(set (match_dup 3)
9410 (plus:DI (match_operand:DI 0 "" "")
9411 (match_dup 2)))
9412 (parallel [(set (pc) (match_dup 3))
9413 (use (label_ref (match_operand 1 "" "")))])]
9414 ""
9415 "
9416 { operands[0] = force_reg (DImode, operands[0]);
9417 operands[2] = force_reg (DImode, gen_rtx (LABEL_REF, VOIDmode, operands[1]));
9418 operands[3] = gen_reg_rtx (DImode);
9419 }")
9421 (define_insn ""
9422 [(set (pc)
9423 (match_operand:SI 0 "register_operand" "c,l"))
9424 (use (label_ref (match_operand 1 "" "")))]
9425 ""
9426 "@
9427 bctr
9428 {br|blr}"
9429 [(set_attr "type" "jmpreg")])
9431 (define_insn ""
9432 [(set (pc)
9433 (match_operand:DI 0 "register_operand" "c,l"))
9434 (use (label_ref (match_operand 1 "" "")))]
9435 "TARGET_POWERPC64"
9436 "@
9437 bctr
9438 {br|blr}"
9439 [(set_attr "type" "jmpreg")])
9441 (define_insn "nop"
9442 [(const_int 0)]
9443 ""
9444 "{cror 0,0,0|nop}")
9445 \f
9446 ;; Define the subtract-one-and-jump insns, starting with the template
9447 ;; so loop.c knows what to generate.
9449 (define_expand "decrement_and_branch_on_count"
9450 [(parallel [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "")
9451 (const_int 1))
9452 (label_ref (match_operand 1 "" ""))
9453 (pc)))
9454 (set (match_dup 0)
9455 (plus:SI (match_dup 0)
9456 (const_int -1)))
9457 (clobber (match_scratch:CC 2 ""))
9458 (clobber (match_scratch:SI 3 ""))])]
9459 ""
9460 "")
9462 ;; We need to be able to do this for any operand, including MEM, or we
9463 ;; will cause reload to blow up since we don't allow output reloads on
9464 ;; JUMP_INSNs.
9465 ;; In order that the length attribute is calculated correctly, the
9466 ;; label MUST be operand 0.
9468 (define_insn ""
9469 [(set (pc)
9470 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
9471 (const_int 1))
9472 (label_ref (match_operand 0 "" ""))
9473 (pc)))
9474 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
9475 (plus:SI (match_dup 1)
9476 (const_int -1)))
9477 (clobber (match_scratch:CC 3 "=X,&x,&x"))
9478 (clobber (match_scratch:SI 4 "=X,X,r"))]
9479 ""
9480 "*
9481 {
9482 if (which_alternative != 0)
9483 return \"#\";
9484 else if (get_attr_length (insn) == 8)
9485 return \"{bdn|bdnz} %l0\";
9486 else
9487 return \"bdz %$+8\;b %l0\";
9488 }"
9489 [(set_attr "type" "branch")
9490 (set_attr "length" "*,12,16")])
9492 (define_insn ""
9493 [(set (pc)
9494 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
9495 (const_int 1))
9496 (pc)
9497 (label_ref (match_operand 0 "" ""))))
9498 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
9499 (plus:SI (match_dup 1)
9500 (const_int -1)))
9501 (clobber (match_scratch:CC 3 "=X,&x,&x"))
9502 (clobber (match_scratch:SI 4 "=X,X,r"))]
9503 ""
9504 "*
9505 {
9506 if (which_alternative != 0)
9507 return \"#\";
9508 else if (get_attr_length (insn) == 8)
9509 return \"bdz %l0\";
9510 else
9511 return \"{bdn|bdnz} %$+8\;b %l0\";
9512 }"
9513 [(set_attr "type" "branch")
9514 (set_attr "length" "*,12,16")])
9516 ;; Similar, but we can use GE since we have a REG_NONNEG.
9517 (define_insn ""
9518 [(set (pc)
9519 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
9520 (const_int 0))
9521 (label_ref (match_operand 0 "" ""))
9522 (pc)))
9523 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
9524 (plus:SI (match_dup 1)
9525 (const_int -1)))
9526 (clobber (match_scratch:CC 3 "=X,&x,&X"))
9527 (clobber (match_scratch:SI 4 "=X,X,r"))]
9528 "find_reg_note (insn, REG_NONNEG, 0)"
9529 "*
9530 {
9531 if (which_alternative != 0)
9532 return \"#\";
9533 else if (get_attr_length (insn) == 8)
9534 return \"{bdn|bdnz} %l0\";
9535 else
9536 return \"bdz %$+8\;b %l0\";
9537 }"
9538 [(set_attr "type" "branch")
9539 (set_attr "length" "*,12,16")])
9541 (define_insn ""
9542 [(set (pc)
9543 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
9544 (const_int 0))
9545 (pc)
9546 (label_ref (match_operand 0 "" ""))))
9547 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
9548 (plus:SI (match_dup 1)
9549 (const_int -1)))
9550 (clobber (match_scratch:CC 3 "=X,&x,&X"))
9551 (clobber (match_scratch:SI 4 "=X,X,r"))]
9552 "find_reg_note (insn, REG_NONNEG, 0)"
9553 "*
9554 {
9555 if (which_alternative != 0)
9556 return \"#\";
9557 else if (get_attr_length (insn) == 8)
9558 return \"bdz %l0\";
9559 else
9560 return \"{bdn|bdnz} %$+8\;b %l0\";
9561 }"
9562 [(set_attr "type" "branch")
9563 (set_attr "length" "*,12,16")])
9565 (define_insn ""
9566 [(set (pc)
9567 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
9568 (const_int 1))
9569 (label_ref (match_operand 0 "" ""))
9570 (pc)))
9571 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
9572 (plus:SI (match_dup 1)
9573 (const_int -1)))
9574 (clobber (match_scratch:CC 3 "=X,&x,&x"))
9575 (clobber (match_scratch:SI 4 "=X,X,r"))]
9576 ""
9577 "*
9578 {
9579 if (which_alternative != 0)
9580 return \"#\";
9581 else if (get_attr_length (insn) == 8)
9582 return \"bdz %l0\";
9583 else
9584 return \"{bdn|bdnz} %$+8\;b %l0\";
9585 }"
9586 [(set_attr "type" "branch")
9587 (set_attr "length" "*,12,16")])
9589 (define_insn ""
9590 [(set (pc)
9591 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
9592 (const_int 1))
9593 (pc)
9594 (label_ref (match_operand 0 "" ""))))
9595 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
9596 (plus:SI (match_dup 1)
9597 (const_int -1)))
9598 (clobber (match_scratch:CC 3 "=X,&x,&x"))
9599 (clobber (match_scratch:SI 4 "=X,X,r"))]
9600 ""
9601 "*
9602 {
9603 if (which_alternative != 0)
9604 return \"#\";
9605 else if (get_attr_length (insn) == 8)
9606 return \"{bdn|bdnz} %l0\";
9607 else
9608 return \"bdz %$+8\;b %l0\";
9609 }"
9610 [(set_attr "type" "branch")
9611 (set_attr "length" "*,12,16")])
9613 (define_split
9614 [(set (pc)
9615 (if_then_else (match_operator 2 "comparison_operator"
9616 [(match_operand:SI 1 "gpc_reg_operand" "")
9617 (const_int 1)])
9618 (match_operand 5 "" "")
9619 (match_operand 6 "" "")))
9620 (set (match_operand:SI 0 "gpc_reg_operand" "")
9621 (plus:SI (match_dup 1)
9622 (const_int -1)))
9623 (clobber (match_scratch:CC 3 ""))
9624 (clobber (match_scratch:SI 4 ""))]
9625 "reload_completed"
9626 [(parallel [(set (match_dup 3)
9627 (compare:CC (plus:SI (match_dup 1)
9628 (const_int -1))
9629 (const_int 0)))
9630 (set (match_dup 0)
9631 (plus:SI (match_dup 1)
9632 (const_int -1)))])
9633 (set (pc) (if_then_else (match_dup 7)
9634 (match_dup 5)
9635 (match_dup 6)))]
9636 "
9637 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
9638 const0_rtx); }")
9640 (define_split
9641 [(set (pc)
9642 (if_then_else (match_operator 2 "comparison_operator"
9643 [(match_operand:SI 1 "gpc_reg_operand" "")
9644 (const_int 1)])
9645 (match_operand 5 "" "")
9646 (match_operand 6 "" "")))
9647 (set (match_operand:SI 0 "general_operand" "")
9648 (plus:SI (match_dup 1) (const_int -1)))
9649 (clobber (match_scratch:CC 3 ""))
9650 (clobber (match_scratch:SI 4 ""))]
9651 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
9652 [(parallel [(set (match_dup 3)
9653 (compare:CC (plus:SI (match_dup 1)
9654 (const_int -1))
9655 (const_int 0)))
9656 (set (match_dup 4)
9657 (plus:SI (match_dup 1)
9658 (const_int -1)))])
9659 (set (match_dup 0)
9660 (match_dup 4))
9661 (set (pc) (if_then_else (match_dup 7)
9662 (match_dup 5)
9663 (match_dup 6)))]
9664 "
9665 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
9666 const0_rtx); }")