1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
3 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
40 static void restore_unscaled_index_insn_codes
PROTO((rtx
));
41 static void record_unscaled_index_insn_codes
PROTO((rtx
));
43 /* Save the operands last given to a compare for use when we
44 generate a scc or bcc insn. */
46 rtx hppa_compare_op0
, hppa_compare_op1
;
47 enum cmp_type hppa_branch_type
;
49 /* Which cpu we are scheduling for. */
50 enum processor_type pa_cpu
;
52 /* String to hold which cpu we are scheduling for. */
55 /* Set by the FUNCTION_PROFILER macro. */
56 int hp_profile_labelno
;
58 /* Counts for the number of callee-saved general and floating point
59 registers which were saved by the current function's prologue. */
60 static int gr_saved
, fr_saved
;
62 /* Whether or not the current function uses an out-of-line prologue
64 static int out_of_line_prologue_epilogue
;
66 static rtx
find_addr_reg ();
68 /* Keep track of the number of bytes we have output in the CODE subspaces
69 during this compilation so we'll know when to emit inline long-calls. */
71 unsigned int total_code_bytes
;
73 /* Variables to handle plabels that we discover are necessary at assembly
74 output time. They are output after the current function. */
76 struct deferred_plabel
80 } *deferred_plabels
= 0;
81 int n_deferred_plabels
= 0;
83 /* Array indexed by INSN_UIDs holding the INSN_CODE of an insn which
84 uses an unscaled indexed address before delay slot scheduling. */
85 static int *unscaled_index_insn_codes
;
87 /* Upper bound for the array. */
88 static int max_unscaled_index_insn_codes_uid
;
93 /* Default to 7100 scheduling. If the 7100LC scheduling ever
94 gets reasonably tuned, it should be the default since that
95 what most PAs sold now are. */
96 if (pa_cpu_string
== NULL
97 || ! strcmp (pa_cpu_string
, "7100"))
99 pa_cpu_string
= "7100";
100 pa_cpu
= PROCESSOR_7100
;
102 else if (! strcmp (pa_cpu_string
, "700"))
104 pa_cpu_string
= "700";
105 pa_cpu
= PROCESSOR_700
;
107 else if (! strcmp (pa_cpu_string
, "7100LC"))
109 pa_cpu_string
= "7100LC";
110 pa_cpu
= PROCESSOR_7100LC
;
114 warning ("Unknown -mschedule= option (%s).\nValid options are 700, 7100 and 7100LC\n", pa_cpu_string
);
117 if (flag_pic
&& TARGET_PORTABLE_RUNTIME
)
119 warning ("PIC code generation is not supported in the portable runtime model\n");
122 if (flag_pic
&& (TARGET_NO_SPACE_REGS
|| TARGET_FAST_INDIRECT_CALLS
))
124 warning ("PIC code generation is not compatible with fast indirect calls\n");
127 if (flag_pic
&& profile_flag
)
129 warning ("PIC code generation is not compatible with profiling\n");
132 if (TARGET_SPACE
&& (flag_pic
|| profile_flag
))
134 warning ("Out of line entry/exit sequences are not compatible\n");
135 warning ("with PIC or profiling\n");
138 if (! TARGET_GAS
&& write_symbols
!= NO_DEBUG
)
140 warning ("-g is only supported when using GAS on this processor,");
141 warning ("-g option disabled.");
142 write_symbols
= NO_DEBUG
;
147 /* Return non-zero only if OP is a register of mode MODE,
150 reg_or_0_operand (op
, mode
)
152 enum machine_mode mode
;
154 return (op
== CONST0_RTX (mode
) || register_operand (op
, mode
));
157 /* Return non-zero if OP is suitable for use in a call to a named
160 (???) For 2.5 try to eliminate either call_operand_address or
161 function_label_operand, they perform very similar functions. */
163 call_operand_address (op
, mode
)
165 enum machine_mode mode
;
167 return (CONSTANT_P (op
) && ! TARGET_PORTABLE_RUNTIME
);
170 /* Return 1 if X contains a symbolic expression. We know these
171 expressions will have one of a few well defined forms, so
172 we need only check those forms. */
174 symbolic_expression_p (x
)
178 /* Strip off any HIGH. */
179 if (GET_CODE (x
) == HIGH
)
182 return (symbolic_operand (x
, VOIDmode
));
186 symbolic_operand (op
, mode
)
188 enum machine_mode mode
;
190 switch (GET_CODE (op
))
197 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
198 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
199 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
205 /* Return truth value of statement that OP is a symbolic memory
206 operand of mode MODE. */
209 symbolic_memory_operand (op
, mode
)
211 enum machine_mode mode
;
213 if (GET_CODE (op
) == SUBREG
)
214 op
= SUBREG_REG (op
);
215 if (GET_CODE (op
) != MEM
)
218 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
219 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
222 /* Return 1 if the operand is either a register or a memory operand that is
226 reg_or_nonsymb_mem_operand (op
, mode
)
228 enum machine_mode mode
;
230 if (register_operand (op
, mode
))
233 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
239 /* Return 1 if the operand is either a register, zero, or a memory operand
240 that is not symbolic. */
243 reg_or_0_or_nonsymb_mem_operand (op
, mode
)
245 enum machine_mode mode
;
247 if (register_operand (op
, mode
))
250 if (op
== CONST0_RTX (mode
))
253 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
259 /* Accept any constant that can be moved in one instructions into a
262 cint_ok_for_move (intval
)
263 HOST_WIDE_INT intval
;
265 /* OK if ldo, ldil, or zdepi, can be used. */
266 return (VAL_14_BITS_P (intval
) || (intval
& 0x7ff) == 0
267 || zdepi_cint_p (intval
));
270 /* Accept anything that can be moved in one instruction into a general
273 move_operand (op
, mode
)
275 enum machine_mode mode
;
277 if (register_operand (op
, mode
))
280 if (GET_CODE (op
) == CONST_INT
)
281 return cint_ok_for_move (INTVAL (op
));
283 if (GET_CODE (op
) == SUBREG
)
284 op
= SUBREG_REG (op
);
285 if (GET_CODE (op
) != MEM
)
289 if (GET_CODE (op
) == LO_SUM
)
290 return (register_operand (XEXP (op
, 0), Pmode
)
291 && CONSTANT_P (XEXP (op
, 1)));
293 /* Since move_operand is only used for source operands, we can always
294 allow scaled indexing! */
295 if (! TARGET_DISABLE_INDEXING
296 && GET_CODE (op
) == PLUS
297 && ((GET_CODE (XEXP (op
, 0)) == MULT
298 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == REG
299 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
300 && INTVAL (XEXP (XEXP (op
, 0), 1)) == GET_MODE_SIZE (mode
)
301 && GET_CODE (XEXP (op
, 1)) == REG
)
302 || (GET_CODE (XEXP (op
, 1)) == MULT
303 &&GET_CODE (XEXP (XEXP (op
, 1), 0)) == REG
304 && GET_CODE (XEXP (XEXP (op
, 1), 1)) == CONST_INT
305 && INTVAL (XEXP (XEXP (op
, 1), 1)) == GET_MODE_SIZE (mode
)
306 && GET_CODE (XEXP (op
, 0)) == REG
)))
309 return memory_address_p (mode
, op
);
312 /* Accept REG and any CONST_INT that can be moved in one instruction into a
315 reg_or_cint_move_operand (op
, mode
)
317 enum machine_mode mode
;
319 if (register_operand (op
, mode
))
322 if (GET_CODE (op
) == CONST_INT
)
323 return cint_ok_for_move (INTVAL (op
));
329 pic_label_operand (op
, mode
)
331 enum machine_mode mode
;
336 switch (GET_CODE (op
))
342 return (GET_CODE (XEXP (op
, 0)) == LABEL_REF
343 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
350 fp_reg_operand (op
, mode
)
352 enum machine_mode mode
;
354 return reg_renumber
&& FP_REG_P (op
);
359 /* Return truth value of whether OP can be used as an operand in a
360 three operand arithmetic insn that accepts registers of mode MODE
361 or 14-bit signed integers. */
363 arith_operand (op
, mode
)
365 enum machine_mode mode
;
367 return (register_operand (op
, mode
)
368 || (GET_CODE (op
) == CONST_INT
&& INT_14_BITS (op
)));
371 /* Return truth value of whether OP can be used as an operand in a
372 three operand arithmetic insn that accepts registers of mode MODE
373 or 11-bit signed integers. */
375 arith11_operand (op
, mode
)
377 enum machine_mode mode
;
379 return (register_operand (op
, mode
)
380 || (GET_CODE (op
) == CONST_INT
&& INT_11_BITS (op
)));
383 /* A constant integer suitable for use in a PRE_MODIFY memory
386 pre_cint_operand (op
, mode
)
388 enum machine_mode mode
;
390 return (GET_CODE (op
) == CONST_INT
391 && INTVAL (op
) >= -0x2000 && INTVAL (op
) < 0x10);
394 /* A constant integer suitable for use in a POST_MODIFY memory
397 post_cint_operand (op
, mode
)
399 enum machine_mode mode
;
401 return (GET_CODE (op
) == CONST_INT
402 && INTVAL (op
) < 0x2000 && INTVAL (op
) >= -0x10);
406 arith_double_operand (op
, mode
)
408 enum machine_mode mode
;
410 return (register_operand (op
, mode
)
411 || (GET_CODE (op
) == CONST_DOUBLE
412 && GET_MODE (op
) == mode
413 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op
))
414 && (CONST_DOUBLE_HIGH (op
) >= 0
415 == ((CONST_DOUBLE_LOW (op
) & 0x1000) == 0))));
418 /* Return truth value of whether OP is a integer which fits the
419 range constraining immediate operands in three-address insns, or
420 is an integer register. */
423 ireg_or_int5_operand (op
, mode
)
425 enum machine_mode mode
;
427 return ((GET_CODE (op
) == CONST_INT
&& INT_5_BITS (op
))
428 || (GET_CODE (op
) == REG
&& REGNO (op
) > 0 && REGNO (op
) < 32));
431 /* Return truth value of whether OP is a integer which fits the
432 range constraining immediate operands in three-address insns. */
435 int5_operand (op
, mode
)
437 enum machine_mode mode
;
439 return (GET_CODE (op
) == CONST_INT
&& INT_5_BITS (op
));
443 uint5_operand (op
, mode
)
445 enum machine_mode mode
;
447 return (GET_CODE (op
) == CONST_INT
&& INT_U5_BITS (op
));
451 int11_operand (op
, mode
)
453 enum machine_mode mode
;
455 return (GET_CODE (op
) == CONST_INT
&& INT_11_BITS (op
));
459 uint32_operand (op
, mode
)
461 enum machine_mode mode
;
463 #if HOST_BITS_PER_WIDE_INT > 32
464 /* All allowed constants will fit a CONST_INT. */
465 return (GET_CODE (op
) == CONST_INT
466 && (INTVAL (op
) >= 0 && INTVAL (op
) < 0x100000000L
));
468 return (GET_CODE (op
) == CONST_INT
469 || (GET_CODE (op
) == CONST_DOUBLE
470 && CONST_DOUBLE_HIGH (op
) == 0));
475 arith5_operand (op
, mode
)
477 enum machine_mode mode
;
479 return register_operand (op
, mode
) || int5_operand (op
, mode
);
482 /* True iff zdepi can be used to generate this CONST_INT. */
485 unsigned HOST_WIDE_INT x
;
487 unsigned HOST_WIDE_INT lsb_mask
, t
;
489 /* This might not be obvious, but it's at least fast.
490 This function is critical; we don't have the time loops would take. */
492 t
= ((x
>> 4) + lsb_mask
) & ~(lsb_mask
- 1);
493 /* Return true iff t is a power of two. */
494 return ((t
& (t
- 1)) == 0);
497 /* True iff depi or extru can be used to compute (reg & mask).
498 Accept bit pattern like these:
504 unsigned HOST_WIDE_INT mask
;
507 mask
+= mask
& -mask
;
508 return (mask
& (mask
- 1)) == 0;
511 /* True iff depi or extru can be used to compute (reg & OP). */
513 and_operand (op
, mode
)
515 enum machine_mode mode
;
517 return (register_operand (op
, mode
)
518 || (GET_CODE (op
) == CONST_INT
&& and_mask_p (INTVAL (op
))));
521 /* True iff depi can be used to compute (reg | MASK). */
524 unsigned HOST_WIDE_INT mask
;
526 mask
+= mask
& -mask
;
527 return (mask
& (mask
- 1)) == 0;
530 /* True iff depi can be used to compute (reg | OP). */
532 ior_operand (op
, mode
)
534 enum machine_mode mode
;
536 return (GET_CODE (op
) == CONST_INT
&& ior_mask_p (INTVAL (op
)));
540 lhs_lshift_operand (op
, mode
)
542 enum machine_mode mode
;
544 return register_operand (op
, mode
) || lhs_lshift_cint_operand (op
, mode
);
547 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
548 Such values can be the left hand side x in (x << r), using the zvdepi
551 lhs_lshift_cint_operand (op
, mode
)
553 enum machine_mode mode
;
555 unsigned HOST_WIDE_INT x
;
556 if (GET_CODE (op
) != CONST_INT
)
558 x
= INTVAL (op
) >> 4;
559 return (x
& (x
+ 1)) == 0;
563 arith32_operand (op
, mode
)
565 enum machine_mode mode
;
567 return register_operand (op
, mode
) || GET_CODE (op
) == CONST_INT
;
571 pc_or_label_operand (op
, mode
)
573 enum machine_mode mode
;
575 return (GET_CODE (op
) == PC
|| GET_CODE (op
) == LABEL_REF
);
578 /* Legitimize PIC addresses. If the address is already
579 position-independent, we return ORIG. Newly generated
580 position-independent addresses go to REG. If we need more
581 than one register, we lose. */
584 legitimize_pic_address (orig
, mode
, reg
)
586 enum machine_mode mode
;
590 /* Labels need special handling. */
591 if (pic_label_operand (orig
))
593 emit_insn (gen_pic_load_label (reg
, orig
));
594 current_function_uses_pic_offset_table
= 1;
597 if (GET_CODE (orig
) == SYMBOL_REF
)
604 emit_insn (gen_pic2_highpart (reg
, pic_offset_table_rtx
, orig
));
605 pic_ref
= gen_rtx (MEM
, Pmode
,
606 gen_rtx (LO_SUM
, Pmode
, reg
,
607 gen_rtx (UNSPEC
, SImode
, gen_rtvec (1, orig
), 0)));
610 pic_ref
= gen_rtx (MEM
, Pmode
,
611 gen_rtx (PLUS
, Pmode
, pic_offset_table_rtx
, orig
));
612 current_function_uses_pic_offset_table
= 1;
613 RTX_UNCHANGING_P (pic_ref
) = 1;
614 emit_move_insn (reg
, pic_ref
);
617 else if (GET_CODE (orig
) == CONST
)
621 if (GET_CODE (XEXP (orig
, 0)) == PLUS
622 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
628 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
630 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
631 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
632 base
== reg
? 0 : reg
);
635 if (GET_CODE (orig
) == CONST_INT
)
637 if (INT_14_BITS (orig
))
638 return plus_constant_for_output (base
, INTVAL (orig
));
639 orig
= force_reg (Pmode
, orig
);
641 pic_ref
= gen_rtx (PLUS
, Pmode
, base
, orig
);
642 /* Likewise, should we set special REG_NOTEs here? */
647 /* Try machine-dependent ways of modifying an illegitimate address
648 to be legitimate. If we find one, return the new, valid address.
649 This macro is used in only one place: `memory_address' in explow.c.
651 OLDX is the address as it was before break_out_memory_refs was called.
652 In some cases it is useful to look at this to decide what needs to be done.
654 MODE and WIN are passed so that this macro can use
655 GO_IF_LEGITIMATE_ADDRESS.
657 It is always safe for this macro to do nothing. It exists to recognize
658 opportunities to optimize the output.
660 For the PA, transform:
662 memory(X + <large int>)
666 if (<large int> & mask) >= 16
667 Y = (<large int> & ~mask) + mask + 1 Round up.
669 Y = (<large int> & ~mask) Round down.
671 memory (Z + (<large int> - Y));
673 This is for CSE to find several similar references, and only use one Z.
675 X can either be a SYMBOL_REF or REG, but because combine can not
676 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
677 D will not fit in 14 bits.
679 MODE_FLOAT references allow displacements which fit in 5 bits, so use
682 MODE_INT references allow displacements which fit in 14 bits, so use
685 This relies on the fact that most mode MODE_FLOAT references will use FP
686 registers and most mode MODE_INT references will use integer registers.
687 (In the rare case of an FP register used in an integer MODE, we depend
688 on secondary reloads to clean things up.)
691 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
692 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
693 addressing modes to be used).
695 Put X and Z into registers. Then put the entire expression into
699 hppa_legitimize_address (x
, oldx
, mode
)
701 enum machine_mode mode
;
706 return legitimize_pic_address (x
, mode
, gen_reg_rtx (Pmode
));
708 /* Strip off CONST. */
709 if (GET_CODE (x
) == CONST
)
712 /* Special case. Get the SYMBOL_REF into a register and use indexing.
713 That should always be safe. */
714 if (GET_CODE (x
) == PLUS
715 && GET_CODE (XEXP (x
, 0)) == REG
716 && GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
)
718 rtx reg
= force_reg (SImode
, XEXP (x
, 1));
719 return force_reg (SImode
, gen_rtx (PLUS
, SImode
, reg
, XEXP (x
, 0)));
722 /* Note we must reject symbols which represent function addresses
723 since the assembler/linker can't handle arithmetic on plabels. */
724 if (GET_CODE (x
) == PLUS
725 && GET_CODE (XEXP (x
, 1)) == CONST_INT
726 && ((GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
727 && !FUNCTION_NAME_P (XSTR (XEXP (x
, 0), 0)))
728 || GET_CODE (XEXP (x
, 0)) == REG
))
730 rtx int_part
, ptr_reg
;
732 int offset
= INTVAL (XEXP (x
, 1));
733 int mask
= GET_MODE_CLASS (mode
) == MODE_FLOAT
? 0x1f : 0x3fff;
735 /* Choose which way to round the offset. Round up if we
736 are >= halfway to the next boundary. */
737 if ((offset
& mask
) >= ((mask
+ 1) / 2))
738 newoffset
= (offset
& ~ mask
) + mask
+ 1;
740 newoffset
= (offset
& ~ mask
);
742 /* If the newoffset will not fit in 14 bits (ldo), then
743 handling this would take 4 or 5 instructions (2 to load
744 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
745 add the new offset and the SYMBOL_REF.) Combine can
746 not handle 4->2 or 5->2 combinations, so do not create
748 if (! VAL_14_BITS_P (newoffset
)
749 && GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
751 rtx const_part
= gen_rtx (CONST
, VOIDmode
,
752 gen_rtx (PLUS
, Pmode
,
754 GEN_INT (newoffset
)));
757 gen_rtx (HIGH
, Pmode
, const_part
));
760 gen_rtx (LO_SUM
, Pmode
,
761 tmp_reg
, const_part
));
765 if (! VAL_14_BITS_P (newoffset
))
766 int_part
= force_reg (Pmode
, GEN_INT (newoffset
));
768 int_part
= GEN_INT (newoffset
);
770 ptr_reg
= force_reg (Pmode
,
771 gen_rtx (PLUS
, Pmode
,
772 force_reg (Pmode
, XEXP (x
, 0)),
775 return plus_constant (ptr_reg
, offset
- newoffset
);
778 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
780 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
781 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
782 && shadd_constant_p (INTVAL (XEXP (XEXP (x
, 0), 1)))
783 && (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == 'o'
784 || GET_CODE (XEXP (x
, 1)) == SUBREG
)
785 && GET_CODE (XEXP (x
, 1)) != CONST
)
787 int val
= INTVAL (XEXP (XEXP (x
, 0), 1));
791 if (GET_CODE (reg1
) != REG
)
792 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
794 reg2
= XEXP (XEXP (x
, 0), 0);
795 if (GET_CODE (reg2
) != REG
)
796 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
798 return force_reg (Pmode
, gen_rtx (PLUS
, Pmode
,
799 gen_rtx (MULT
, Pmode
,
800 reg2
, GEN_INT (val
)),
804 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
806 Only do so for floating point modes since this is more speculative
807 and we lose if it's an integer store. */
808 if (GET_CODE (x
) == PLUS
809 && GET_CODE (XEXP (x
, 0)) == PLUS
810 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
811 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
812 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
813 && (mode
== SFmode
|| mode
== DFmode
))
816 /* First, try and figure out what to use as a base register. */
817 rtx reg1
, reg2
, base
, idx
, orig_base
;
819 reg1
= XEXP (XEXP (x
, 0), 1);
824 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
825 then emit_move_sequence will turn on REGNO_POINTER_FLAG so we'll
826 know it's a base register below. */
827 if (GET_CODE (reg1
) != REG
)
828 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
830 if (GET_CODE (reg2
) != REG
)
831 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
833 /* Figure out what the base and index are. */
835 if (GET_CODE (reg1
) == REG
836 && REGNO_POINTER_FLAG (REGNO (reg1
)))
839 orig_base
= XEXP (XEXP (x
, 0), 1);
840 idx
= gen_rtx (PLUS
, Pmode
,
841 gen_rtx (MULT
, Pmode
,
842 XEXP (XEXP (XEXP (x
, 0), 0), 0),
843 XEXP (XEXP (XEXP (x
, 0), 0), 1)),
846 else if (GET_CODE (reg2
) == REG
847 && REGNO_POINTER_FLAG (REGNO (reg2
)))
850 orig_base
= XEXP (x
, 1);
857 /* If the index adds a large constant, try to scale the
858 constant so that it can be loaded with only one insn. */
859 if (GET_CODE (XEXP (idx
, 1)) == CONST_INT
860 && VAL_14_BITS_P (INTVAL (XEXP (idx
, 1))
861 / INTVAL (XEXP (XEXP (idx
, 0), 1)))
862 && INTVAL (XEXP (idx
, 1)) % INTVAL (XEXP (XEXP (idx
, 0), 1)) == 0)
864 /* Divide the CONST_INT by the scale factor, then add it to A. */
865 int val
= INTVAL (XEXP (idx
, 1));
867 val
/= INTVAL (XEXP (XEXP (idx
, 0), 1));
868 reg1
= XEXP (XEXP (idx
, 0), 0);
869 if (GET_CODE (reg1
) != REG
)
870 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
872 reg1
= force_reg (Pmode
, gen_rtx (PLUS
, Pmode
, reg1
, GEN_INT (val
)));
874 /* We can now generate a simple scaled indexed address. */
875 return force_reg (Pmode
, gen_rtx (PLUS
, Pmode
,
876 gen_rtx (MULT
, Pmode
, reg1
,
877 XEXP (XEXP (idx
, 0), 1)),
881 /* If B + C is still a valid base register, then add them. */
882 if (GET_CODE (XEXP (idx
, 1)) == CONST_INT
883 && INTVAL (XEXP (idx
, 1)) <= 4096
884 && INTVAL (XEXP (idx
, 1)) >= -4096)
886 int val
= INTVAL (XEXP (XEXP (idx
, 0), 1));
889 reg1
= force_reg (Pmode
, gen_rtx (PLUS
, Pmode
, base
, XEXP (idx
, 1)));
891 reg2
= XEXP (XEXP (idx
, 0), 0);
892 if (GET_CODE (reg2
) != CONST_INT
)
893 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
895 return force_reg (Pmode
, gen_rtx (PLUS
, Pmode
,
896 gen_rtx (MULT
, Pmode
,
897 reg2
, GEN_INT (val
)),
901 /* Get the index into a register, then add the base + index and
902 return a register holding the result. */
904 /* First get A into a register. */
905 reg1
= XEXP (XEXP (idx
, 0), 0);
906 if (GET_CODE (reg1
) != REG
)
907 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
909 /* And get B into a register. */
910 reg2
= XEXP (idx
, 1);
911 if (GET_CODE (reg2
) != REG
)
912 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
914 reg1
= force_reg (Pmode
, gen_rtx (PLUS
, Pmode
,
915 gen_rtx (MULT
, Pmode
, reg1
,
916 XEXP (XEXP (idx
, 0), 1)),
919 /* Add the result to our base register and return. */
920 return force_reg (Pmode
, gen_rtx (PLUS
, Pmode
, base
, reg1
));
924 /* Uh-oh. We might have an address for x[n-100000]. This needs
925 special handling to avoid creating an indexed memory address
926 with x-100000 as the base.
928 If the constant part is small enough, then it's still safe because
929 there is a guard page at the beginning and end of the data segment.
931 Scaled references are common enough that we want to try and rearrange the
932 terms so that we can use indexing for these addresses too. Only
933 do the optimization for floatint point modes. */
935 if (GET_CODE (x
) == PLUS
936 && symbolic_expression_p (XEXP (x
, 1)))
938 /* Ugly. We modify things here so that the address offset specified
939 by the index expression is computed first, then added to x to form
940 the entire address. */
942 rtx regx1
, regx2
, regy1
, regy2
, y
;
944 /* Strip off any CONST. */
946 if (GET_CODE (y
) == CONST
)
949 if (GET_CODE (y
) == PLUS
|| GET_CODE (y
) == MINUS
)
951 /* See if this looks like
952 (plus (mult (reg) (shadd_const))
953 (const (plus (symbol_ref) (const_int))))
955 Where const_int is small. In that case the const
956 expression is a valid pointer for indexing.
958 If const_int is big, but can be divided evenly by shadd_const
959 and added to (reg). This allows more scaled indexed addresses. */
960 if (GET_CODE (XEXP (y
, 0)) == SYMBOL_REF
961 && GET_CODE (XEXP (x
, 0)) == MULT
962 && GET_CODE (XEXP (y
, 1)) == CONST_INT
963 && INTVAL (XEXP (y
, 1)) >= -4096
964 && INTVAL (XEXP (y
, 1)) <= 4095
965 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
966 && shadd_constant_p (INTVAL (XEXP (XEXP (x
, 0), 1))))
968 int val
= INTVAL (XEXP (XEXP (x
, 0), 1));
972 if (GET_CODE (reg1
) != REG
)
973 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
975 reg2
= XEXP (XEXP (x
, 0), 0);
976 if (GET_CODE (reg2
) != REG
)
977 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
979 return force_reg (Pmode
, gen_rtx (PLUS
, Pmode
,
980 gen_rtx (MULT
, Pmode
,
981 reg2
, GEN_INT (val
)),
984 else if ((mode
== DFmode
|| mode
== SFmode
)
985 && GET_CODE (XEXP (y
, 0)) == SYMBOL_REF
986 && GET_CODE (XEXP (x
, 0)) == MULT
987 && GET_CODE (XEXP (y
, 1)) == CONST_INT
988 && INTVAL (XEXP (y
, 1)) % INTVAL (XEXP (XEXP (x
, 0), 1)) == 0
989 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
990 && shadd_constant_p (INTVAL (XEXP (XEXP (x
, 0), 1))))
993 = force_reg (Pmode
, GEN_INT (INTVAL (XEXP (y
, 1))
994 / INTVAL (XEXP (XEXP (x
, 0), 1))));
995 regx2
= XEXP (XEXP (x
, 0), 0);
996 if (GET_CODE (regx2
) != REG
)
997 regx2
= force_reg (Pmode
, force_operand (regx2
, 0));
998 regx2
= force_reg (Pmode
, gen_rtx (GET_CODE (y
), Pmode
,
1000 return force_reg (Pmode
,
1001 gen_rtx (PLUS
, Pmode
,
1002 gen_rtx (MULT
, Pmode
, regx2
,
1003 XEXP (XEXP (x
, 0), 1)),
1004 force_reg (Pmode
, XEXP (y
, 0))));
1006 else if (GET_CODE (XEXP (y
, 1)) == CONST_INT
1007 && INTVAL (XEXP (y
, 1)) >= -4096
1008 && INTVAL (XEXP (y
, 1)) <= 4095)
1010 /* This is safe because of the guard page at the
1011 beginning and end of the data space. Just
1012 return the original address. */
1017 /* Doesn't look like one we can optimize. */
1018 regx1
= force_reg (Pmode
, force_operand (XEXP (x
, 0), 0));
1019 regy1
= force_reg (Pmode
, force_operand (XEXP (y
, 0), 0));
1020 regy2
= force_reg (Pmode
, force_operand (XEXP (y
, 1), 0));
1021 regx1
= force_reg (Pmode
,
1022 gen_rtx (GET_CODE (y
), Pmode
, regx1
, regy2
));
1023 return force_reg (Pmode
, gen_rtx (PLUS
, Pmode
, regx1
, regy1
));
1031 /* For the HPPA, REG and REG+CONST is cost 0
1032 and addresses involving symbolic constants are cost 2.
1034 PIC addresses are very expensive.
1036 It is no coincidence that this has the same structure
1037 as GO_IF_LEGITIMATE_ADDRESS. */
1039 hppa_address_cost (X
)
1042 if (GET_CODE (X
) == PLUS
)
1044 else if (GET_CODE (X
) == LO_SUM
)
1046 else if (GET_CODE (X
) == HIGH
)
1051 /* Emit insns to move operands[1] into operands[0].
1053 Return 1 if we have written out everything that needs to be done to
1054 do the move. Otherwise, return 0 and the caller will emit the move
1058 emit_move_sequence (operands
, mode
, scratch_reg
)
1060 enum machine_mode mode
;
1063 register rtx operand0
= operands
[0];
1064 register rtx operand1
= operands
[1];
1066 if (reload_in_progress
&& GET_CODE (operand0
) == REG
1067 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
1068 operand0
= reg_equiv_mem
[REGNO (operand0
)];
1069 else if (reload_in_progress
&& GET_CODE (operand0
) == SUBREG
1070 && GET_CODE (SUBREG_REG (operand0
)) == REG
1071 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
1073 SUBREG_REG (operand0
) = reg_equiv_mem
[REGNO (SUBREG_REG (operand0
))];
1074 operand0
= alter_subreg (operand0
);
1077 if (reload_in_progress
&& GET_CODE (operand1
) == REG
1078 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
1079 operand1
= reg_equiv_mem
[REGNO (operand1
)];
1080 else if (reload_in_progress
&& GET_CODE (operand1
) == SUBREG
1081 && GET_CODE (SUBREG_REG (operand1
)) == REG
1082 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
1084 SUBREG_REG (operand1
) = reg_equiv_mem
[REGNO (SUBREG_REG (operand1
))];
1085 operand1
= alter_subreg (operand1
);
1088 /* Handle secondary reloads for loads/stores of FP registers from
1089 REG+D addresses where D does not fit in 5 bits, including
1090 (subreg (mem (addr))) cases. */
1091 if (fp_reg_operand (operand0
, mode
)
1092 && ((GET_CODE (operand1
) == MEM
1093 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
1094 || ((GET_CODE (operand1
) == SUBREG
1095 && GET_CODE (XEXP (operand1
, 0)) == MEM
1096 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
1099 if (GET_CODE (operand1
) == SUBREG
)
1100 operand1
= XEXP (operand1
, 0);
1102 scratch_reg
= gen_rtx (REG
, SImode
, REGNO (scratch_reg
));
1104 /* D might not fit in 14 bits either; for such cases load D into
1106 if (!memory_address_p (SImode
, XEXP (operand1
, 0)))
1108 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
1109 emit_move_insn (scratch_reg
, gen_rtx (GET_CODE (XEXP (operand1
, 0)),
1111 XEXP (XEXP (operand1
, 0), 0),
1115 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
1116 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, gen_rtx (MEM
, mode
,
1120 else if (fp_reg_operand (operand1
, mode
)
1121 && ((GET_CODE (operand0
) == MEM
1122 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
1123 || ((GET_CODE (operand0
) == SUBREG
)
1124 && GET_CODE (XEXP (operand0
, 0)) == MEM
1125 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
1128 if (GET_CODE (operand0
) == SUBREG
)
1129 operand0
= XEXP (operand0
, 0);
1131 scratch_reg
= gen_rtx (REG
, SImode
, REGNO (scratch_reg
));
1132 /* D might not fit in 14 bits either; for such cases load D into
1134 if (!memory_address_p (SImode
, XEXP (operand0
, 0)))
1136 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
1137 emit_move_insn (scratch_reg
, gen_rtx (GET_CODE (XEXP (operand0
, 0)),
1139 XEXP (XEXP (operand0
, 0), 0),
1143 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
1144 emit_insn (gen_rtx (SET
, VOIDmode
, gen_rtx (MEM
, mode
, scratch_reg
),
1148 /* Handle secondary reloads for loads of FP registers from constant
1149 expressions by forcing the constant into memory.
1151 use scratch_reg to hold the address of the memory location.
1153 ??? The proper fix is to change PREFERRED_RELOAD_CLASS to return
1154 NO_REGS when presented with a const_int and an register class
1155 containing only FP registers. Doing so unfortunately creates
1156 more problems than it solves. Fix this for 2.5. */
1157 else if (fp_reg_operand (operand0
, mode
)
1158 && CONSTANT_P (operand1
)
1163 /* Force the constant into memory and put the address of the
1164 memory location into scratch_reg. */
1165 xoperands
[0] = scratch_reg
;
1166 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
1167 emit_move_sequence (xoperands
, Pmode
, 0);
1169 /* Now load the destination register. */
1170 emit_insn (gen_rtx (SET
, mode
, operand0
,
1171 gen_rtx (MEM
, mode
, scratch_reg
)));
1174 /* Handle secondary reloads for SAR. These occur when trying to load
1175 the SAR from memory a FP register, or with a constant. */
1176 else if (GET_CODE (operand0
) == REG
1177 && REGNO_REG_CLASS (REGNO (operand0
)) == SHIFT_REGS
1178 && (GET_CODE (operand1
) == MEM
1179 || GET_CODE (operand1
) == CONST_INT
1180 || (GET_CODE (operand1
) == REG
1181 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1
)))))
1184 /* D might not fit in 14 bits either; for such cases load D into
1186 if (GET_CODE (operand1
) == MEM
1187 && !memory_address_p (SImode
, XEXP (operand1
, 0)))
1189 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
1190 emit_move_insn (scratch_reg
, gen_rtx (GET_CODE (XEXP (operand1
, 0)),
1192 XEXP (XEXP (operand1
, 0), 0),
1194 emit_move_insn (scratch_reg
, gen_rtx (MEM
, GET_MODE (operand1
),
1198 emit_move_insn (scratch_reg
, operand1
);
1199 emit_move_insn (operand0
, scratch_reg
);
1202 /* Handle most common case: storing into a register. */
1203 else if (register_operand (operand0
, mode
))
1205 if (register_operand (operand1
, mode
)
1206 || (GET_CODE (operand1
) == CONST_INT
&& INT_14_BITS (operand1
))
1207 || (operand1
== CONST0_RTX (mode
))
1208 || (GET_CODE (operand1
) == HIGH
1209 && !symbolic_operand (XEXP (operand1
, 0), VOIDmode
))
1210 /* Only `general_operands' can come here, so MEM is ok. */
1211 || GET_CODE (operand1
) == MEM
)
1213 /* Run this case quickly. */
1214 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, operand1
));
1218 else if (GET_CODE (operand0
) == MEM
)
1220 if (mode
== DFmode
&& operand1
== CONST0_RTX (mode
)
1221 && !(reload_in_progress
|| reload_completed
))
1223 rtx temp
= gen_reg_rtx (DFmode
);
1225 emit_insn (gen_rtx (SET
, VOIDmode
, temp
, operand1
));
1226 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, temp
));
1229 if (register_operand (operand1
, mode
) || operand1
== CONST0_RTX (mode
))
1231 /* Run this case quickly. */
1232 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, operand1
));
1235 if (! (reload_in_progress
|| reload_completed
))
1237 operands
[0] = validize_mem (operand0
);
1238 operands
[1] = operand1
= force_reg (mode
, operand1
);
1242 /* Simplify the source if we need to. */
1243 if ((GET_CODE (operand1
) != HIGH
&& immediate_operand (operand1
, mode
))
1244 || (GET_CODE (operand1
) == HIGH
1245 && symbolic_operand (XEXP (operand1
, 0), mode
)))
1249 if (GET_CODE (operand1
) == HIGH
)
1252 operand1
= XEXP (operand1
, 0);
1254 if (symbolic_operand (operand1
, mode
))
1256 /* Argh. The assembler and linker can't handle arithmetic
1259 So we force the plabel into memory, load operand0 from
1260 the memory location, then add in the constant part. */
1261 if (GET_CODE (operand1
) == CONST
1262 && GET_CODE (XEXP (operand1
, 0)) == PLUS
1263 && function_label_operand (XEXP (XEXP (operand1
, 0), 0), Pmode
))
1265 rtx temp
, const_part
;
1267 /* Figure out what (if any) scratch register to use. */
1268 if (reload_in_progress
|| reload_completed
)
1269 scratch_reg
= scratch_reg
? scratch_reg
: operand0
;
1271 scratch_reg
= gen_reg_rtx (Pmode
);
1273 /* Save away the constant part of the expression. */
1274 const_part
= XEXP (XEXP (operand1
, 0), 1);
1275 if (GET_CODE (const_part
) != CONST_INT
)
1278 /* Force the function label into memory. */
1279 temp
= force_const_mem (mode
, XEXP (XEXP (operand1
, 0), 0));
1281 /* Get the address of the memory location. PIC-ify it if
1283 temp
= XEXP (temp
, 0);
1285 temp
= legitimize_pic_address (temp
, mode
, scratch_reg
);
1287 /* Put the address of the memory location into our destination
1290 emit_move_sequence (operands
, mode
, scratch_reg
);
1292 /* Now load from the memory location into our destination
1294 operands
[1] = gen_rtx (MEM
, Pmode
, operands
[0]);
1295 emit_move_sequence (operands
, mode
, scratch_reg
);
1297 /* And add back in the constant part. */
1298 expand_inc (operand0
, const_part
);
1307 if (reload_in_progress
|| reload_completed
)
1308 temp
= scratch_reg
? scratch_reg
: operand0
;
1310 temp
= gen_reg_rtx (Pmode
);
1312 /* (const (plus (symbol) (const_int))) must be forced to
1313 memory during/after reload if the const_int will not fit
1315 if (GET_CODE (operand1
) == CONST
1316 && GET_CODE (XEXP (operand1
, 0)) == PLUS
1317 && GET_CODE (XEXP (XEXP (operand1
, 0), 1)) == CONST_INT
1318 && !INT_14_BITS (XEXP (XEXP (operand1
, 0), 1))
1319 && (reload_completed
|| reload_in_progress
)
1322 operands
[1] = force_const_mem (mode
, operand1
);
1323 operands
[1] = legitimize_pic_address (XEXP (operands
[1], 0),
1325 emit_move_sequence (operands
, mode
, temp
);
1329 operands
[1] = legitimize_pic_address (operand1
, mode
, temp
);
1330 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, operands
[1]));
1333 /* On the HPPA, references to data space are supposed to use dp,
1334 register 27, but showing it in the RTL inhibits various cse
1335 and loop optimizations. */
1340 if (reload_in_progress
|| reload_completed
)
1341 temp
= scratch_reg
? scratch_reg
: operand0
;
1343 temp
= gen_reg_rtx (mode
);
1345 /* Loading a SYMBOL_REF into a register makes that register
1346 safe to be used as the base in an indexed address.
1348 Don't mark hard registers though. That loses. */
1349 if (GET_CODE (operand0
) == REG
1350 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
1351 REGNO_POINTER_FLAG (REGNO (operand0
)) = 1;
1352 if (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
)
1353 REGNO_POINTER_FLAG (REGNO (temp
)) = 1;
1355 set
= gen_rtx (SET
, mode
, operand0
, temp
);
1357 set
= gen_rtx (SET
, VOIDmode
,
1359 gen_rtx (LO_SUM
, mode
, temp
, operand1
));
1361 emit_insn (gen_rtx (SET
, VOIDmode
,
1363 gen_rtx (HIGH
, mode
, operand1
)));
1369 else if (GET_CODE (operand1
) != CONST_INT
1370 || ! cint_ok_for_move (INTVAL (operand1
)))
1374 if (reload_in_progress
|| reload_completed
)
1377 temp
= gen_reg_rtx (mode
);
1379 emit_insn (gen_rtx (SET
, VOIDmode
, temp
,
1380 gen_rtx (HIGH
, mode
, operand1
)));
1381 operands
[1] = gen_rtx (LO_SUM
, mode
, temp
, operand1
);
1384 /* Now have insn-emit do whatever it normally does. */
1388 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1389 it will need a link/runtime reloc). */
1397 switch (TREE_CODE (exp
))
1404 reloc
= reloc_needed (TREE_OPERAND (exp
, 0));
1405 reloc
|= reloc_needed (TREE_OPERAND (exp
, 1));
1410 case NON_LVALUE_EXPR
:
1411 reloc
= reloc_needed (TREE_OPERAND (exp
, 0));
1417 for (link
= CONSTRUCTOR_ELTS (exp
); link
; link
= TREE_CHAIN (link
))
1418 if (TREE_VALUE (link
) != 0)
1419 reloc
|= reloc_needed (TREE_VALUE (link
));
1429 /* Does operand (which is a symbolic_operand) live in text space? If
1430 so SYMBOL_REF_FLAG, which is set by ENCODE_SECTION_INFO, will be true. */
1433 read_only_operand (operand
)
1436 if (GET_CODE (operand
) == CONST
)
1437 operand
= XEXP (XEXP (operand
, 0), 0);
1440 if (GET_CODE (operand
) == SYMBOL_REF
)
1441 return SYMBOL_REF_FLAG (operand
) && !CONSTANT_POOL_ADDRESS_P (operand
);
1445 if (GET_CODE (operand
) == SYMBOL_REF
)
1446 return SYMBOL_REF_FLAG (operand
) || CONSTANT_POOL_ADDRESS_P (operand
);
1452 /* Return the best assembler insn template
1453 for moving operands[1] into operands[0] as a fullword. */
1455 singlemove_string (operands
)
1458 HOST_WIDE_INT intval
;
1460 if (GET_CODE (operands
[0]) == MEM
)
1461 return "stw %r1,%0";
1462 if (GET_CODE (operands
[1]) == MEM
)
1464 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1469 if (GET_MODE (operands
[1]) != SFmode
)
1472 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1474 REAL_VALUE_FROM_CONST_DOUBLE (d
, operands
[1]);
1475 REAL_VALUE_TO_TARGET_SINGLE (d
, i
);
1477 operands
[1] = GEN_INT (i
);
1478 /* Fall through to CONST_INT case. */
1480 if (GET_CODE (operands
[1]) == CONST_INT
)
1482 intval
= INTVAL (operands
[1]);
1484 if (VAL_14_BITS_P (intval
))
1486 else if ((intval
& 0x7ff) == 0)
1487 return "ldil L'%1,%0";
1488 else if (zdepi_cint_p (intval
))
1489 return "zdepi %Z1,%0";
1491 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1493 return "copy %1,%0";
1497 /* Compute position (in OP[1]) and width (in OP[2])
1498 useful for copying IMM to a register using the zdepi
1499 instructions. Store the immediate value to insert in OP[0]. */
1501 compute_zdepi_operands (imm
, op
)
1502 unsigned HOST_WIDE_INT imm
;
1507 /* Find the least significant set bit in IMM. */
1508 for (lsb
= 0; lsb
< 32; lsb
++)
1515 /* Choose variants based on *sign* of the 5-bit field. */
1516 if ((imm
& 0x10) == 0)
1517 len
= (lsb
<= 28) ? 4 : 32 - lsb
;
1520 /* Find the width of the bitstring in IMM. */
1521 for (len
= 5; len
< 32; len
++)
1523 if ((imm
& (1 << len
)) == 0)
1527 /* Sign extend IMM as a 5-bit value. */
1528 imm
= (imm
& 0xf) - 0x10;
1536 /* Output assembler code to perform a doubleword move insn
1537 with operands OPERANDS. */
1540 output_move_double (operands
)
1543 enum { REGOP
, OFFSOP
, MEMOP
, CNSTOP
, RNDOP
} optype0
, optype1
;
1545 rtx addreg0
= 0, addreg1
= 0;
1547 /* First classify both operands. */
1549 if (REG_P (operands
[0]))
1551 else if (offsettable_memref_p (operands
[0]))
1553 else if (GET_CODE (operands
[0]) == MEM
)
1558 if (REG_P (operands
[1]))
1560 else if (CONSTANT_P (operands
[1]))
1562 else if (offsettable_memref_p (operands
[1]))
1564 else if (GET_CODE (operands
[1]) == MEM
)
1569 /* Check for the cases that the operand constraints are not
1570 supposed to allow to happen. Abort if we get one,
1571 because generating code for these cases is painful. */
1573 if (optype0
!= REGOP
&& optype1
!= REGOP
)
1576 /* Handle auto decrementing and incrementing loads and stores
1577 specifically, since the structure of the function doesn't work
1578 for them without major modification. Do it better when we learn
1579 this port about the general inc/dec addressing of PA.
1580 (This was written by tege. Chide him if it doesn't work.) */
1582 if (optype0
== MEMOP
)
1584 /* We have to output the address syntax ourselves, since print_operand
1585 doesn't deal with the addresses we want to use. Fix this later. */
1587 rtx addr
= XEXP (operands
[0], 0);
1588 if (GET_CODE (addr
) == POST_INC
|| GET_CODE (addr
) == POST_DEC
)
1590 rtx high_reg
= gen_rtx (SUBREG
, SImode
, operands
[1], 0);
1592 operands
[0] = XEXP (addr
, 0);
1593 if (GET_CODE (operands
[1]) != REG
|| GET_CODE (operands
[0]) != REG
)
1596 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1598 /* No overlap between high target register and address
1599 register. (We do this in a non-obvious way to
1600 save a register file writeback) */
1601 if (GET_CODE (addr
) == POST_INC
)
1602 return "stws,ma %1,8(0,%0)\n\tstw %R1,-4(0,%0)";
1603 return "stws,ma %1,-8(0,%0)\n\tstw %R1,12(0,%0)";
1608 else if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
1610 rtx high_reg
= gen_rtx (SUBREG
, SImode
, operands
[1], 0);
1612 operands
[0] = XEXP (addr
, 0);
1613 if (GET_CODE (operands
[1]) != REG
|| GET_CODE (operands
[0]) != REG
)
1616 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1618 /* No overlap between high target register and address
1619 register. (We do this in a non-obvious way to
1620 save a register file writeback) */
1621 if (GET_CODE (addr
) == PRE_INC
)
1622 return "stws,mb %1,8(0,%0)\n\tstw %R1,4(0,%0)";
1623 return "stws,mb %1,-8(0,%0)\n\tstw %R1,4(0,%0)";
1629 if (optype1
== MEMOP
)
1631 /* We have to output the address syntax ourselves, since print_operand
1632 doesn't deal with the addresses we want to use. Fix this later. */
1634 rtx addr
= XEXP (operands
[1], 0);
1635 if (GET_CODE (addr
) == POST_INC
|| GET_CODE (addr
) == POST_DEC
)
1637 rtx high_reg
= gen_rtx (SUBREG
, SImode
, operands
[0], 0);
1639 operands
[1] = XEXP (addr
, 0);
1640 if (GET_CODE (operands
[0]) != REG
|| GET_CODE (operands
[1]) != REG
)
1643 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1645 /* No overlap between high target register and address
1646 register. (We do this in a non-obvious way to
1647 save a register file writeback) */
1648 if (GET_CODE (addr
) == POST_INC
)
1649 return "ldws,ma 8(0,%1),%0\n\tldw -4(0,%1),%R0";
1650 return "ldws,ma -8(0,%1),%0\n\tldw 12(0,%1),%R0";
1654 /* This is an undefined situation. We should load into the
1655 address register *and* update that register. Probably
1656 we don't need to handle this at all. */
1657 if (GET_CODE (addr
) == POST_INC
)
1658 return "ldw 4(0,%1),%R0\n\tldws,ma 8(0,%1),%0";
1659 return "ldw 4(0,%1),%R0\n\tldws,ma -8(0,%1),%0";
1662 else if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
1664 rtx high_reg
= gen_rtx (SUBREG
, SImode
, operands
[0], 0);
1666 operands
[1] = XEXP (addr
, 0);
1667 if (GET_CODE (operands
[0]) != REG
|| GET_CODE (operands
[1]) != REG
)
1670 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1672 /* No overlap between high target register and address
1673 register. (We do this in a non-obvious way to
1674 save a register file writeback) */
1675 if (GET_CODE (addr
) == PRE_INC
)
1676 return "ldws,mb 8(0,%1),%0\n\tldw 4(0,%1),%R0";
1677 return "ldws,mb -8(0,%1),%0\n\tldw 4(0,%1),%R0";
1681 /* This is an undefined situation. We should load into the
1682 address register *and* update that register. Probably
1683 we don't need to handle this at all. */
1684 if (GET_CODE (addr
) == PRE_INC
)
1685 return "ldw 12(0,%1),%R0\n\tldws,mb 8(0,%1),%0";
1686 return "ldw -4(0,%1),%R0\n\tldws,mb -8(0,%1),%0";
1689 else if (GET_CODE (addr
) == PLUS
1690 && GET_CODE (XEXP (addr
, 0)) == MULT
)
1692 rtx high_reg
= gen_rtx (SUBREG
, SImode
, operands
[0], 0);
1694 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1698 xoperands
[0] = high_reg
;
1699 xoperands
[1] = XEXP (addr
, 1);
1700 xoperands
[2] = XEXP (XEXP (addr
, 0), 0);
1701 xoperands
[3] = XEXP (XEXP (addr
, 0), 1);
1702 output_asm_insn ("sh%O3addl %2,%1,%0", xoperands
);
1703 return "ldw 4(0,%0),%R0\n\tldw 0(0,%0),%0";
1709 xoperands
[0] = high_reg
;
1710 xoperands
[1] = XEXP (addr
, 1);
1711 xoperands
[2] = XEXP (XEXP (addr
, 0), 0);
1712 xoperands
[3] = XEXP (XEXP (addr
, 0), 1);
1713 output_asm_insn ("sh%O3addl %2,%1,%R0", xoperands
);
1714 return "ldw 0(0,%R0),%0\n\tldw 4(0,%R0),%R0";
1720 /* If an operand is an unoffsettable memory ref, find a register
1721 we can increment temporarily to make it refer to the second word. */
1723 if (optype0
== MEMOP
)
1724 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1726 if (optype1
== MEMOP
)
1727 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1729 /* Ok, we can do one word at a time.
1730 Normally we do the low-numbered word first.
1732 In either case, set up in LATEHALF the operands to use
1733 for the high-numbered word and in some cases alter the
1734 operands in OPERANDS to be suitable for the low-numbered word. */
1736 if (optype0
== REGOP
)
1737 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1738 else if (optype0
== OFFSOP
)
1739 latehalf
[0] = adj_offsettable_operand (operands
[0], 4);
1741 latehalf
[0] = operands
[0];
1743 if (optype1
== REGOP
)
1744 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
1745 else if (optype1
== OFFSOP
)
1746 latehalf
[1] = adj_offsettable_operand (operands
[1], 4);
1747 else if (optype1
== CNSTOP
)
1748 split_double (operands
[1], &operands
[1], &latehalf
[1]);
1750 latehalf
[1] = operands
[1];
1752 /* If the first move would clobber the source of the second one,
1753 do them in the other order.
1755 This can happen in two cases:
1757 mem -> register where the first half of the destination register
1758 is the same register used in the memory's address. Reload
1759 can create such insns.
1761 mem in this case will be either register indirect or register
1762 indirect plus a valid offset.
1764 register -> register move where REGNO(dst) == REGNO(src + 1)
1765 someone (Tim/Tege?) claimed this can happen for parameter loads.
1767 Handle mem -> register case first. */
1768 if (optype0
== REGOP
1769 && (optype1
== MEMOP
|| optype1
== OFFSOP
)
1770 && refers_to_regno_p (REGNO (operands
[0]), REGNO (operands
[0]) + 1,
1773 /* Do the late half first. */
1775 output_asm_insn ("ldo 4(%0),%0", &addreg1
);
1776 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1780 output_asm_insn ("ldo -4(%0),%0", &addreg1
);
1781 return singlemove_string (operands
);
1784 /* Now handle register -> register case. */
1785 if (optype0
== REGOP
&& optype1
== REGOP
1786 && REGNO (operands
[0]) == REGNO (operands
[1]) + 1)
1788 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1789 return singlemove_string (operands
);
1792 /* Normal case: do the two words, low-numbered first. */
1794 output_asm_insn (singlemove_string (operands
), operands
);
1796 /* Make any unoffsettable addresses point at high-numbered word. */
1798 output_asm_insn ("ldo 4(%0),%0", &addreg0
);
1800 output_asm_insn ("ldo 4(%0),%0", &addreg1
);
1803 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1805 /* Undo the adds we just did. */
1807 output_asm_insn ("ldo -4(%0),%0", &addreg0
);
1809 output_asm_insn ("ldo -4(%0),%0", &addreg1
);
1815 output_fp_move_double (operands
)
1818 if (FP_REG_P (operands
[0]))
1820 if (FP_REG_P (operands
[1])
1821 || operands
[1] == CONST0_RTX (GET_MODE (operands
[0])))
1822 output_asm_insn ("fcpy,dbl %r1,%0", operands
);
1824 output_asm_insn ("fldd%F1 %1,%0", operands
);
1826 else if (FP_REG_P (operands
[1]))
1828 output_asm_insn ("fstd%F0 %1,%0", operands
);
1830 else if (operands
[1] == CONST0_RTX (GET_MODE (operands
[0])))
1832 if (GET_CODE (operands
[0]) == REG
)
1835 xoperands
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1836 xoperands
[0] = operands
[0];
1837 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands
);
1839 /* This is a pain. You have to be prepared to deal with an
1840 arbitrary address here including pre/post increment/decrement.
1842 so avoid this in the MD. */
1850 /* Return a REG that occurs in ADDR with coefficient 1.
1851 ADDR can be effectively incremented by incrementing REG. */
1854 find_addr_reg (addr
)
1857 while (GET_CODE (addr
) == PLUS
)
1859 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1860 addr
= XEXP (addr
, 0);
1861 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
1862 addr
= XEXP (addr
, 1);
1863 else if (CONSTANT_P (XEXP (addr
, 0)))
1864 addr
= XEXP (addr
, 1);
1865 else if (CONSTANT_P (XEXP (addr
, 1)))
1866 addr
= XEXP (addr
, 0);
1870 if (GET_CODE (addr
) == REG
)
1875 /* Emit code to perform a block move.
1877 OPERANDS[0] is the destination pointer as a REG, clobbered.
1878 OPERANDS[1] is the source pointer as a REG, clobbered.
1879 OPERANDS[2] is a register for temporary storage.
1880 OPERANDS[4] is the size as a CONST_INT
1881 OPERANDS[3] is a register for temporary storage.
1882 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
1883 OPERANDS[6] is another temporary register. */
1886 output_block_move (operands
, size_is_constant
)
1888 int size_is_constant
;
1890 int align
= INTVAL (operands
[5]);
1891 unsigned long n_bytes
= INTVAL (operands
[4]);
1893 /* We can't move more than four bytes at a time because the PA
1894 has no longer integer move insns. (Could use fp mem ops?) */
1898 /* Note that we know each loop below will execute at least twice
1899 (else we would have open-coded the copy). */
1903 /* Pre-adjust the loop counter. */
1904 operands
[4] = GEN_INT (n_bytes
- 8);
1905 output_asm_insn ("ldi %4,%2", operands
);
1908 output_asm_insn ("ldws,ma 4(0,%1),%3", operands
);
1909 output_asm_insn ("ldws,ma 4(0,%1),%6", operands
);
1910 output_asm_insn ("stws,ma %3,4(0,%0)", operands
);
1911 output_asm_insn ("addib,>= -8,%2,.-12", operands
);
1912 output_asm_insn ("stws,ma %6,4(0,%0)", operands
);
1914 /* Handle the residual. There could be up to 7 bytes of
1915 residual to copy! */
1916 if (n_bytes
% 8 != 0)
1918 operands
[4] = GEN_INT (n_bytes
% 4);
1919 if (n_bytes
% 8 >= 4)
1920 output_asm_insn ("ldws,ma 4(0,%1),%3", operands
);
1921 if (n_bytes
% 4 != 0)
1922 output_asm_insn ("ldw 0(0,%1),%6", operands
);
1923 if (n_bytes
% 8 >= 4)
1924 output_asm_insn ("stws,ma %3,4(0,%0)", operands
);
1925 if (n_bytes
% 4 != 0)
1926 output_asm_insn ("stbys,e %6,%4(0,%0)", operands
);
1931 /* Pre-adjust the loop counter. */
1932 operands
[4] = GEN_INT (n_bytes
- 4);
1933 output_asm_insn ("ldi %4,%2", operands
);
1936 output_asm_insn ("ldhs,ma 2(0,%1),%3", operands
);
1937 output_asm_insn ("ldhs,ma 2(0,%1),%6", operands
);
1938 output_asm_insn ("sths,ma %3,2(0,%0)", operands
);
1939 output_asm_insn ("addib,>= -4,%2,.-12", operands
);
1940 output_asm_insn ("sths,ma %6,2(0,%0)", operands
);
1942 /* Handle the residual. */
1943 if (n_bytes
% 4 != 0)
1945 if (n_bytes
% 4 >= 2)
1946 output_asm_insn ("ldhs,ma 2(0,%1),%3", operands
);
1947 if (n_bytes
% 2 != 0)
1948 output_asm_insn ("ldb 0(0,%1),%6", operands
);
1949 if (n_bytes
% 4 >= 2)
1950 output_asm_insn ("sths,ma %3,2(0,%0)", operands
);
1951 if (n_bytes
% 2 != 0)
1952 output_asm_insn ("stb %6,0(0,%0)", operands
);
1957 /* Pre-adjust the loop counter. */
1958 operands
[4] = GEN_INT (n_bytes
- 2);
1959 output_asm_insn ("ldi %4,%2", operands
);
1962 output_asm_insn ("ldbs,ma 1(0,%1),%3", operands
);
1963 output_asm_insn ("ldbs,ma 1(0,%1),%6", operands
);
1964 output_asm_insn ("stbs,ma %3,1(0,%0)", operands
);
1965 output_asm_insn ("addib,>= -2,%2,.-12", operands
);
1966 output_asm_insn ("stbs,ma %6,1(0,%0)", operands
);
1968 /* Handle the residual. */
1969 if (n_bytes
% 2 != 0)
1971 output_asm_insn ("ldb 0(0,%1),%3", operands
);
1972 output_asm_insn ("stb %3,0(0,%0)", operands
);
1981 /* Count the number of insns necessary to handle this block move.
1983 Basic structure is the same as emit_block_move, except that we
1984 count insns rather than emit them. */
1987 compute_movstrsi_length (insn
)
1990 rtx pat
= PATTERN (insn
);
1991 int align
= INTVAL (XEXP (XVECEXP (pat
, 0, 6), 0));
1992 unsigned long n_bytes
= INTVAL (XEXP (XVECEXP (pat
, 0, 5), 0));
1993 unsigned int n_insns
= 0;
1995 /* We can't move more than four bytes at a time because the PA
1996 has no longer integer move insns. (Could use fp mem ops?) */
2000 /* The basic copying loop. */
2004 if (n_bytes
% (2 * align
) != 0)
2006 if ((n_bytes
% (2 * align
)) >= align
)
2009 if ((n_bytes
% align
) != 0)
2013 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2019 output_and (operands
)
2022 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) != 0)
2024 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
2025 int ls0
, ls1
, ms0
, p
, len
;
2027 for (ls0
= 0; ls0
< 32; ls0
++)
2028 if ((mask
& (1 << ls0
)) == 0)
2031 for (ls1
= ls0
; ls1
< 32; ls1
++)
2032 if ((mask
& (1 << ls1
)) != 0)
2035 for (ms0
= ls1
; ms0
< 32; ms0
++)
2036 if ((mask
& (1 << ms0
)) == 0)
2049 operands
[2] = GEN_INT (len
);
2050 return "extru %1,31,%2,%0";
2054 /* We could use this `depi' for the case above as well, but `depi'
2055 requires one more register file access than an `extru'. */
2060 operands
[2] = GEN_INT (p
);
2061 operands
[3] = GEN_INT (len
);
2062 return "depi 0,%2,%3,%0";
2066 return "and %1,%2,%0";
2070 output_ior (operands
)
2073 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
2074 int bs0
, bs1
, p
, len
;
2076 if (INTVAL (operands
[2]) == 0)
2077 return "copy %1,%0";
2079 for (bs0
= 0; bs0
< 32; bs0
++)
2080 if ((mask
& (1 << bs0
)) != 0)
2083 for (bs1
= bs0
; bs1
< 32; bs1
++)
2084 if ((mask
& (1 << bs1
)) == 0)
2087 if (bs1
!= 32 && ((unsigned HOST_WIDE_INT
) 1 << bs1
) <= mask
)
2093 operands
[2] = GEN_INT (p
);
2094 operands
[3] = GEN_INT (len
);
2095 return "depi -1,%2,%3,%0";
2098 /* Output an ascii string. */
2100 output_ascii (file
, p
, size
)
2107 unsigned char partial_output
[16]; /* Max space 4 chars can occupy. */
2109 /* The HP assembler can only take strings of 256 characters at one
2110 time. This is a limitation on input line length, *not* the
2111 length of the string. Sigh. Even worse, it seems that the
2112 restriction is in number of input characters (see \xnn &
2113 \whatever). So we have to do this very carefully. */
2115 fputs ("\t.STRING \"", file
);
2118 for (i
= 0; i
< size
; i
+= 4)
2122 for (io
= 0, co
= 0; io
< MIN (4, size
- i
); io
++)
2124 register unsigned int c
= p
[i
+ io
];
2126 if (c
== '\"' || c
== '\\')
2127 partial_output
[co
++] = '\\';
2128 if (c
>= ' ' && c
< 0177)
2129 partial_output
[co
++] = c
;
2133 partial_output
[co
++] = '\\';
2134 partial_output
[co
++] = 'x';
2135 hexd
= c
/ 16 - 0 + '0';
2137 hexd
-= '9' - 'a' + 1;
2138 partial_output
[co
++] = hexd
;
2139 hexd
= c
% 16 - 0 + '0';
2141 hexd
-= '9' - 'a' + 1;
2142 partial_output
[co
++] = hexd
;
2145 if (chars_output
+ co
> 243)
2147 fputs ("\"\n\t.STRING \"", file
);
2150 fwrite (partial_output
, 1, co
, file
);
2154 fputs ("\"\n", file
);
2157 /* Try to rewrite floating point comparisons & branches to avoid
2158 useless add,tr insns.
2160 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2161 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2162 first attempt to remove useless add,tr insns. It is zero
2163 for the second pass as reorg sometimes leaves bogus REG_DEAD
2166 When CHECK_NOTES is zero we can only eliminate add,tr insns
2167 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2170 remove_useless_addtr_insns (insns
, check_notes
)
2176 static int pass
= 0;
2178 /* This is fairly cheap, so always run it when optimizing. */
2182 int fbranch_count
= 0;
2184 /* Walk all the insns in this function looking for fcmp & fbranch
2185 instructions. Keep track of how many of each we find. */
2186 insns
= get_insns ();
2187 for (insn
= insns
; insn
; insn
= next_insn (insn
))
2191 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2192 if (GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != JUMP_INSN
)
2195 tmp
= PATTERN (insn
);
2197 /* It must be a set. */
2198 if (GET_CODE (tmp
) != SET
)
2201 /* If the destination is CCFP, then we've found an fcmp insn. */
2202 tmp
= SET_DEST (tmp
);
2203 if (GET_CODE (tmp
) == REG
&& REGNO (tmp
) == 0)
2209 tmp
= PATTERN (insn
);
2210 /* If this is an fbranch instruction, bump the fbranch counter. */
2211 if (GET_CODE (tmp
) == SET
2212 && SET_DEST (tmp
) == pc_rtx
2213 && GET_CODE (SET_SRC (tmp
)) == IF_THEN_ELSE
2214 && GET_CODE (XEXP (SET_SRC (tmp
), 0)) == NE
2215 && GET_CODE (XEXP (XEXP (SET_SRC (tmp
), 0), 0)) == REG
2216 && REGNO (XEXP (XEXP (SET_SRC (tmp
), 0), 0)) == 0)
2224 /* Find all floating point compare + branch insns. If possible,
2225 reverse the comparison & the branch to avoid add,tr insns. */
2226 for (insn
= insns
; insn
; insn
= next_insn (insn
))
2230 /* Ignore anything that isn't an INSN. */
2231 if (GET_CODE (insn
) != INSN
)
2234 tmp
= PATTERN (insn
);
2236 /* It must be a set. */
2237 if (GET_CODE (tmp
) != SET
)
2240 /* The destination must be CCFP, which is register zero. */
2241 tmp
= SET_DEST (tmp
);
2242 if (GET_CODE (tmp
) != REG
|| REGNO (tmp
) != 0)
2245 /* INSN should be a set of CCFP.
2247 See if the result of this insn is used in a reversed FP
2248 conditional branch. If so, reverse our condition and
2249 the branch. Doing so avoids useless add,tr insns. */
2250 next
= next_insn (insn
);
2253 /* Jumps, calls and labels stop our search. */
2254 if (GET_CODE (next
) == JUMP_INSN
2255 || GET_CODE (next
) == CALL_INSN
2256 || GET_CODE (next
) == CODE_LABEL
)
2259 /* As does another fcmp insn. */
2260 if (GET_CODE (next
) == INSN
2261 && GET_CODE (PATTERN (next
)) == SET
2262 && GET_CODE (SET_DEST (PATTERN (next
))) == REG
2263 && REGNO (SET_DEST (PATTERN (next
))) == 0)
2266 next
= next_insn (next
);
2269 /* Is NEXT_INSN a branch? */
2271 && GET_CODE (next
) == JUMP_INSN
)
2273 rtx pattern
= PATTERN (next
);
2275 /* If it a reversed fp conditional branch (eg uses add,tr)
2276 and CCFP dies, then reverse our conditional and the branch
2277 to avoid the add,tr. */
2278 if (GET_CODE (pattern
) == SET
2279 && SET_DEST (pattern
) == pc_rtx
2280 && GET_CODE (SET_SRC (pattern
)) == IF_THEN_ELSE
2281 && GET_CODE (XEXP (SET_SRC (pattern
), 0)) == NE
2282 && GET_CODE (XEXP (XEXP (SET_SRC (pattern
), 0), 0)) == REG
2283 && REGNO (XEXP (XEXP (SET_SRC (pattern
), 0), 0)) == 0
2284 && GET_CODE (XEXP (SET_SRC (pattern
), 1)) == PC
2285 && (fcmp_count
== fbranch_count
2287 && find_regno_note (next
, REG_DEAD
, 0))))
2289 /* Reverse the branch. */
2290 tmp
= XEXP (SET_SRC (pattern
), 1);
2291 XEXP (SET_SRC (pattern
), 1) = XEXP (SET_SRC (pattern
), 2);
2292 XEXP (SET_SRC (pattern
), 2) = tmp
;
2293 INSN_CODE (next
) = -1;
2295 /* Reverse our condition. */
2296 tmp
= PATTERN (insn
);
2297 PUT_CODE (XEXP (tmp
, 1),
2298 reverse_condition (GET_CODE (XEXP (tmp
, 1))));
2308 /* You may have trouble believing this, but this is the HP-PA stack
2313 Variable arguments (optional; any number may be allocated)
2315 SP-(4*(N+9)) arg word N
2320 Fixed arguments (must be allocated; may remain unused)
2329 SP-32 External Data Pointer (DP)
2331 SP-24 External/stub RP (RP')
2335 SP-8 Calling Stub RP (RP'')
2340 SP-0 Stack Pointer (points to next available address)
2344 /* This function saves registers as follows. Registers marked with ' are
2345 this function's registers (as opposed to the previous function's).
2346 If a frame_pointer isn't needed, r4 is saved as a general register;
2347 the space for the frame pointer is still allocated, though, to keep
2353 SP (FP') Previous FP
2354 SP + 4 Alignment filler (sigh)
2355 SP + 8 Space for locals reserved here.
2359 SP + n All call saved register used.
2363 SP + o All call saved fp registers used.
2367 SP + p (SP') points to next available address.
2371 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2372 Handle case where DISP > 8k by using the add_high_const pattern.
2374 Note in DISP > 8k case, we will leave the high part of the address
2375 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2377 store_reg (reg
, disp
, base
)
2378 int reg
, disp
, base
;
2380 if (VAL_14_BITS_P (disp
))
2382 emit_move_insn (gen_rtx (MEM
, SImode
,
2383 gen_rtx (PLUS
, SImode
,
2384 gen_rtx (REG
, SImode
, base
),
2386 gen_rtx (REG
, SImode
, reg
));
2390 emit_insn (gen_add_high_const (gen_rtx (REG
, SImode
, 1),
2391 gen_rtx (REG
, SImode
, base
),
2393 emit_move_insn (gen_rtx (MEM
, SImode
,
2394 gen_rtx (LO_SUM
, SImode
,
2395 gen_rtx (REG
, SImode
, 1),
2397 gen_rtx (REG
, SImode
, reg
));
2401 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
2402 Handle case where DISP > 8k by using the add_high_const pattern.
2404 Note in DISP > 8k case, we will leave the high part of the address
2405 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2407 load_reg (reg
, disp
, base
)
2408 int reg
, disp
, base
;
2410 if (VAL_14_BITS_P (disp
))
2412 emit_move_insn (gen_rtx (REG
, SImode
, reg
),
2413 gen_rtx (MEM
, SImode
,
2414 gen_rtx (PLUS
, SImode
,
2415 gen_rtx (REG
, SImode
, base
),
2420 emit_insn (gen_add_high_const (gen_rtx (REG
, SImode
, 1),
2421 gen_rtx (REG
, SImode
, base
),
2423 emit_move_insn (gen_rtx (REG
, SImode
, reg
),
2424 gen_rtx (MEM
, SImode
,
2425 gen_rtx (LO_SUM
, SImode
,
2426 gen_rtx (REG
, SImode
, 1),
2431 /* Emit RTL to set REG to the value specified by BASE+DISP.
2432 Handle case where DISP > 8k by using the add_high_const pattern.
2434 Note in DISP > 8k case, we will leave the high part of the address
2435 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2437 set_reg_plus_d(reg
, base
, disp
)
2438 int reg
, base
, disp
;
2440 if (VAL_14_BITS_P (disp
))
2442 emit_move_insn (gen_rtx (REG
, SImode
, reg
),
2443 gen_rtx (PLUS
, SImode
,
2444 gen_rtx (REG
, SImode
, base
),
2449 emit_insn (gen_add_high_const (gen_rtx (REG
, SImode
, 1),
2450 gen_rtx (REG
, SImode
, base
),
2452 emit_move_insn (gen_rtx (REG
, SImode
, reg
),
2453 gen_rtx (LO_SUM
, SImode
,
2454 gen_rtx (REG
, SImode
, 1),
2459 /* Global variables set by FUNCTION_PROLOGUE. */
2460 /* Size of frame. Need to know this to emit return insns from
2462 static int actual_fsize
;
2463 static int local_fsize
, save_fregs
;
2466 compute_frame_size (size
, fregs_live
)
2470 extern int current_function_outgoing_args_size
;
2473 /* 8 is space for frame pointer + filler. If any frame is allocated
2474 we need to add this in because of STARTING_FRAME_OFFSET. */
2475 fsize
= size
+ (size
|| frame_pointer_needed
? 8 : 0);
2477 /* We must leave enough space for all the callee saved registers
2478 from 3 .. highest used callee save register since we don't
2479 know if we're going to have an inline or out of line prologue
2481 for (i
= 18; i
>= 3; i
--)
2482 if (regs_ever_live
[i
])
2484 fsize
+= 4 * (i
- 2);
2488 /* Round the stack. */
2489 fsize
= (fsize
+ 7) & ~7;
2491 /* We must leave enough space for all the callee saved registers
2492 from 3 .. highest used callee save register since we don't
2493 know if we're going to have an inline or out of line prologue
2495 for (i
= 66; i
>= 48; i
-= 2)
2496 if (regs_ever_live
[i
] || regs_ever_live
[i
+ 1])
2501 fsize
+= 4 * (i
- 46);
2505 fsize
+= current_function_outgoing_args_size
;
2506 if (! leaf_function_p () || fsize
)
2508 return (fsize
+ 63) & ~63;
2511 rtx hp_profile_label_rtx
;
2512 static char hp_profile_label_name
[8];
2514 output_function_prologue (file
, size
)
2518 /* The function's label and associated .PROC must never be
2519 separated and must be output *after* any profiling declarations
2520 to avoid changing spaces/subspaces within a procedure. */
2521 ASM_OUTPUT_LABEL (file
, XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0));
2522 fputs ("\t.PROC\n", file
);
2524 /* hppa_expand_prologue does the dirty work now. We just need
2525 to output the assembler directives which denote the start
2527 fprintf (file
, "\t.CALLINFO FRAME=%d", actual_fsize
);
2528 if (regs_ever_live
[2] || profile_flag
)
2529 fputs (",CALLS,SAVE_RP", file
);
2531 fputs (",NO_CALLS", file
);
2533 if (frame_pointer_needed
)
2534 fputs (",SAVE_SP", file
);
2536 /* Pass on information about the number of callee register saves
2537 performed in the prologue.
2539 The compiler is supposed to pass the highest register number
2540 saved, the assembler then has to adjust that number before
2541 entering it into the unwind descriptor (to account for any
2542 caller saved registers with lower register numbers than the
2543 first callee saved register). */
2545 fprintf (file
, ",ENTRY_GR=%d", gr_saved
+ 2);
2548 fprintf (file
, ",ENTRY_FR=%d", fr_saved
+ 11);
2550 fputs ("\n\t.ENTRY\n", file
);
2552 /* Horrid hack. emit_function_prologue will modify this RTL in
2553 place to get the expected results. */
2555 ASM_GENERATE_INTERNAL_LABEL (hp_profile_label_name
, "LP",
2556 hp_profile_labelno
);
2558 /* If we're using GAS and not using the portable runtime model, then
2559 we don't need to accumulate the total number of code bytes. */
2560 if (TARGET_GAS
&& ! TARGET_PORTABLE_RUNTIME
)
2561 total_code_bytes
= 0;
2562 else if (insn_addresses
)
2564 unsigned int old_total
= total_code_bytes
;
2566 total_code_bytes
+= insn_addresses
[INSN_UID (get_last_insn())];
2567 total_code_bytes
+= FUNCTION_BOUNDARY
/ BITS_PER_UNIT
;
2569 /* Be prepared to handle overflows. */
2570 total_code_bytes
= old_total
> total_code_bytes
? -1 : total_code_bytes
;
2573 total_code_bytes
= -1;
2575 remove_useless_addtr_insns (get_insns (), 0);
2577 /* Restore INSN_CODEs for insn which use unscaled indexed addresses. */
2578 restore_unscaled_index_insn_codes (get_insns ());
2582 hppa_expand_prologue()
2584 extern char call_used_regs
[];
2585 int size
= get_frame_size ();
2586 int merge_sp_adjust_with_store
= 0;
2588 rtx tmpreg
, size_rtx
;
2593 local_fsize
= size
+ (size
|| frame_pointer_needed
? 8 : 0);
2594 actual_fsize
= compute_frame_size (size
, &save_fregs
);
2596 /* Compute a few things we will use often. */
2597 tmpreg
= gen_rtx (REG
, SImode
, 1);
2598 size_rtx
= GEN_INT (actual_fsize
);
2600 /* Handle out of line prologues and epilogues. */
2605 int outline_insn_count
= 0;
2606 int inline_insn_count
= 0;
2608 /* Count the number of insns for the inline and out of line
2609 variants so we can choose one appropriately.
2611 No need to screw with counting actual_fsize operations -- they're
2612 done for both inline and out of line prologues. */
2613 if (regs_ever_live
[2])
2614 inline_insn_count
+= 1;
2616 if (! cint_ok_for_move (local_fsize
))
2617 outline_insn_count
+= 2;
2619 outline_insn_count
+= 1;
2621 /* Put the register save info into %r22. */
2622 for (i
= 18; i
>= 3; i
--)
2623 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2625 /* -1 because the stack adjustment is normally done in
2626 the same insn as a register save. */
2627 inline_insn_count
+= (i
- 2) - 1;
2632 for (i
= 66; i
>= 48; i
-= 2)
2633 if (regs_ever_live
[i
] || regs_ever_live
[i
+ 1])
2635 /* +1 needed as we load %r1 with the start of the freg
2637 inline_insn_count
+= (i
/2 - 23) + 1;
2638 saves
|= ((i
/2 - 12 ) << 16);
2642 if (frame_pointer_needed
)
2643 inline_insn_count
+= 3;
2645 if (! cint_ok_for_move (saves
))
2646 outline_insn_count
+= 2;
2648 outline_insn_count
+= 1;
2650 if (TARGET_PORTABLE_RUNTIME
)
2651 outline_insn_count
+= 2;
2653 outline_insn_count
+= 1;
2655 /* If there's a lot of insns in the prologue, then do it as
2656 an out-of-line sequence. */
2657 if (inline_insn_count
> outline_insn_count
)
2659 /* Put the local_fisze into %r19. */
2660 operands
[0] = gen_rtx (REG
, SImode
, 19);
2661 operands
[1] = GEN_INT (local_fsize
);
2662 emit_move_insn (operands
[0], operands
[1]);
2664 /* Put the stack size into %r21. */
2665 operands
[0] = gen_rtx (REG
, SImode
, 21);
2666 operands
[1] = size_rtx
;
2667 emit_move_insn (operands
[0], operands
[1]);
2669 operands
[0] = gen_rtx (REG
, SImode
, 22);
2670 operands
[1] = GEN_INT (saves
);
2671 emit_move_insn (operands
[0], operands
[1]);
2673 /* Now call the out-of-line prologue. */
2674 emit_insn (gen_outline_prologue_call ());
2675 emit_insn (gen_blockage ());
2677 /* Note that we're using an out-of-line prologue. */
2678 out_of_line_prologue_epilogue
= 1;
2683 out_of_line_prologue_epilogue
= 0;
2685 /* Save RP first. The calling conventions manual states RP will
2686 always be stored into the caller's frame at sp-20. */
2687 if (regs_ever_live
[2] || profile_flag
)
2688 store_reg (2, -20, STACK_POINTER_REGNUM
);
2690 /* Allocate the local frame and set up the frame pointer if needed. */
2692 if (frame_pointer_needed
)
2694 /* Copy the old frame pointer temporarily into %r1. Set up the
2695 new stack pointer, then store away the saved old frame pointer
2696 into the stack at sp+actual_fsize and at the same time update
2697 the stack pointer by actual_fsize bytes. Two versions, first
2698 handles small (<8k) frames. The second handles large (>8k)
2700 emit_move_insn (tmpreg
, frame_pointer_rtx
);
2701 emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
2702 if (VAL_14_BITS_P (actual_fsize
))
2703 emit_insn (gen_post_stwm (stack_pointer_rtx
, tmpreg
, size_rtx
));
2706 /* It is incorrect to store the saved frame pointer at *sp,
2707 then increment sp (writes beyond the current stack boundary).
2709 So instead use stwm to store at *sp and post-increment the
2710 stack pointer as an atomic operation. Then increment sp to
2711 finish allocating the new frame. */
2712 emit_insn (gen_post_stwm (stack_pointer_rtx
, tmpreg
, GEN_INT (64)));
2713 set_reg_plus_d (STACK_POINTER_REGNUM
,
2714 STACK_POINTER_REGNUM
,
2718 /* no frame pointer needed. */
2721 /* In some cases we can perform the first callee register save
2722 and allocating the stack frame at the same time. If so, just
2723 make a note of it and defer allocating the frame until saving
2724 the callee registers. */
2725 if (VAL_14_BITS_P (-actual_fsize
)
2729 merge_sp_adjust_with_store
= 1;
2730 /* Can not optimize. Adjust the stack frame by actual_fsize bytes. */
2731 else if (actual_fsize
!= 0)
2732 set_reg_plus_d (STACK_POINTER_REGNUM
,
2733 STACK_POINTER_REGNUM
,
2736 /* The hppa calling conventions say that that %r19, the pic offset
2737 register, is saved at sp - 32 (in this function's frame) when
2738 generating PIC code. FIXME: What is the correct thing to do
2739 for functions which make no calls and allocate no frame? Do
2740 we need to allocate a frame, or can we just omit the save? For
2741 now we'll just omit the save. */
2742 if (actual_fsize
!= 0 && flag_pic
)
2743 store_reg (PIC_OFFSET_TABLE_REGNUM
, -32, STACK_POINTER_REGNUM
);
2747 Instead of taking one argument, the counter label, as most normal
2748 mcounts do, _mcount appears to behave differently on the HPPA. It
2749 takes the return address of the caller, the address of this routine,
2750 and the address of the label. Also, it isn't magic, so
2751 argument registers have to be preserved. */
2754 int pc_offset
, i
, arg_offset
, basereg
, offsetadj
;
2756 pc_offset
= 4 + (frame_pointer_needed
2757 ? (VAL_14_BITS_P (actual_fsize
) ? 12 : 20)
2758 : (VAL_14_BITS_P (actual_fsize
) ? 4 : 8));
2760 /* When the function has a frame pointer, use it as the base
2761 register for saving/restore registers. Else use the stack
2762 pointer. Adjust the offset according to the frame size if
2763 this function does not have a frame pointer. */
2765 basereg
= frame_pointer_needed
? FRAME_POINTER_REGNUM
2766 : STACK_POINTER_REGNUM
;
2767 offsetadj
= frame_pointer_needed
? 0 : actual_fsize
;
2769 /* Horrid hack. emit_function_prologue will modify this RTL in
2770 place to get the expected results. sprintf here is just to
2771 put something in the name. */
2772 sprintf(hp_profile_label_name
, "LP$%04d", -1);
2773 hp_profile_label_rtx
= gen_rtx (SYMBOL_REF
, SImode
,
2774 hp_profile_label_name
);
2775 if (current_function_returns_struct
)
2776 store_reg (STRUCT_VALUE_REGNUM
, - 12 - offsetadj
, basereg
);
2778 for (i
= 26, arg_offset
= -36 - offsetadj
; i
>= 23; i
--, arg_offset
-= 4)
2779 if (regs_ever_live
[i
])
2781 store_reg (i
, arg_offset
, basereg
);
2782 /* Deal with arg_offset not fitting in 14 bits. */
2783 pc_offset
+= VAL_14_BITS_P (arg_offset
) ? 4 : 8;
2786 emit_move_insn (gen_rtx (REG
, SImode
, 26), gen_rtx (REG
, SImode
, 2));
2787 emit_move_insn (tmpreg
, gen_rtx (HIGH
, SImode
, hp_profile_label_rtx
));
2788 emit_move_insn (gen_rtx (REG
, SImode
, 24),
2789 gen_rtx (LO_SUM
, SImode
, tmpreg
, hp_profile_label_rtx
));
2790 /* %r25 is set from within the output pattern. */
2791 emit_insn (gen_call_profiler (GEN_INT (- pc_offset
- 20)));
2793 /* Restore argument registers. */
2794 for (i
= 26, arg_offset
= -36 - offsetadj
; i
>= 23; i
--, arg_offset
-= 4)
2795 if (regs_ever_live
[i
])
2796 load_reg (i
, arg_offset
, basereg
);
2798 if (current_function_returns_struct
)
2799 load_reg (STRUCT_VALUE_REGNUM
, -12 - offsetadj
, basereg
);
2803 /* Normal register save.
2805 Do not save the frame pointer in the frame_pointer_needed case. It
2806 was done earlier. */
2807 if (frame_pointer_needed
)
2809 for (i
= 18, offset
= local_fsize
; i
>= 4; i
--)
2810 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2812 store_reg (i
, offset
, FRAME_POINTER_REGNUM
);
2816 /* Account for %r3 which is saved in a special place. */
2819 /* No frame pointer needed. */
2822 for (i
= 18, offset
= local_fsize
- actual_fsize
; i
>= 3; i
--)
2823 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2825 /* If merge_sp_adjust_with_store is nonzero, then we can
2826 optimize the first GR save. */
2827 if (merge_sp_adjust_with_store
)
2829 merge_sp_adjust_with_store
= 0;
2830 emit_insn (gen_post_stwm (stack_pointer_rtx
,
2831 gen_rtx (REG
, SImode
, i
),
2832 GEN_INT (-offset
)));
2835 store_reg (i
, offset
, STACK_POINTER_REGNUM
);
2840 /* If we wanted to merge the SP adjustment with a GR save, but we never
2841 did any GR saves, then just emit the adjustment here. */
2842 if (merge_sp_adjust_with_store
)
2843 set_reg_plus_d (STACK_POINTER_REGNUM
,
2844 STACK_POINTER_REGNUM
,
2848 /* Align pointer properly (doubleword boundary). */
2849 offset
= (offset
+ 7) & ~7;
2851 /* Floating point register store. */
2854 /* First get the frame or stack pointer to the start of the FP register
2856 if (frame_pointer_needed
)
2857 set_reg_plus_d (1, FRAME_POINTER_REGNUM
, offset
);
2859 set_reg_plus_d (1, STACK_POINTER_REGNUM
, offset
);
2861 /* Now actually save the FP registers. */
2862 for (i
= 66; i
>= 48; i
-= 2)
2864 if (regs_ever_live
[i
] || regs_ever_live
[i
+ 1])
2866 emit_move_insn (gen_rtx (MEM
, DFmode
,
2867 gen_rtx (POST_INC
, DFmode
, tmpreg
)),
2868 gen_rtx (REG
, DFmode
, i
));
2874 /* When generating PIC code it is necessary to save/restore the
2875 PIC register around each function call. We used to do this
2876 in the call patterns themselves, but that implementation
2877 made incorrect assumptions about using global variables to hold
2878 per-function rtl code generated in the backend.
2880 So instead, we copy the PIC register into a reserved callee saved
2881 register in the prologue. Then after each call we reload the PIC
2882 register from the callee saved register. We also reload the PIC
2883 register from the callee saved register in the epilogue ensure the
2884 PIC register is valid at function exit.
2886 This may (depending on the exact characteristics of the function)
2887 even be more efficient.
2889 Avoid this if the callee saved register wasn't used (these are
2891 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM_SAVED
])
2892 emit_move_insn (gen_rtx (REG
, SImode
, PIC_OFFSET_TABLE_REGNUM_SAVED
),
2893 gen_rtx (REG
, SImode
, PIC_OFFSET_TABLE_REGNUM
));
2898 output_function_epilogue (file
, size
)
2902 rtx insn
= get_last_insn ();
2905 /* hppa_expand_epilogue does the dirty work now. We just need
2906 to output the assembler directives which denote the end
2909 To make debuggers happy, emit a nop if the epilogue was completely
2910 eliminated due to a volatile call as the last insn in the
2911 current function. That way the return address (in %r2) will
2912 always point to a valid instruction in the current function. */
2914 /* Get the last real insn. */
2915 if (GET_CODE (insn
) == NOTE
)
2916 insn
= prev_real_insn (insn
);
2918 /* If it is a sequence, then look inside. */
2919 if (insn
&& GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
)
2920 insn
= XVECEXP (PATTERN (insn
), 0, 0);
2922 /* If insn is a CALL_INSN, then it must be a call to a volatile
2923 function (otherwise there would be epilogue insns). */
2924 if (insn
&& GET_CODE (insn
) == CALL_INSN
)
2925 fputs ("\tnop\n", file
);
2927 fputs ("\t.EXIT\n\t.PROCEND\n", file
);
2929 /* Free up stuff we don't need anymore. */
2930 if (unscaled_index_insn_codes
)
2931 free (unscaled_index_insn_codes
);
2932 max_unscaled_index_insn_codes_uid
= 0;
2936 hppa_expand_epilogue ()
2940 int merge_sp_adjust_with_load
= 0;
2942 /* Handle out of line prologues and epilogues. */
2943 if (TARGET_SPACE
&& out_of_line_prologue_epilogue
)
2948 /* Put the register save info into %r22. */
2949 for (i
= 18; i
>= 3; i
--)
2950 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2956 for (i
= 66; i
>= 48; i
-= 2)
2957 if (regs_ever_live
[i
] || regs_ever_live
[i
+ 1])
2959 saves
|= ((i
/2 - 12 ) << 16);
2963 emit_insn (gen_blockage ());
2965 /* Put the local_fisze into %r19. */
2966 operands
[0] = gen_rtx (REG
, SImode
, 19);
2967 operands
[1] = GEN_INT (local_fsize
);
2968 emit_move_insn (operands
[0], operands
[1]);
2970 /* Put the stack size into %r21. */
2971 operands
[0] = gen_rtx (REG
, SImode
, 21);
2972 operands
[1] = GEN_INT (actual_fsize
);
2973 emit_move_insn (operands
[0], operands
[1]);
2975 operands
[0] = gen_rtx (REG
, SImode
, 22);
2976 operands
[1] = GEN_INT (saves
);
2977 emit_move_insn (operands
[0], operands
[1]);
2979 /* Now call the out-of-line epilogue. */
2980 emit_insn (gen_outline_epilogue_call ());
2984 /* We will use this often. */
2985 tmpreg
= gen_rtx (REG
, SImode
, 1);
2987 /* Try to restore RP early to avoid load/use interlocks when
2988 RP gets used in the return (bv) instruction. This appears to still
2989 be necessary even when we schedule the prologue and epilogue. */
2990 if (frame_pointer_needed
2991 && (regs_ever_live
[2] || profile_flag
))
2992 load_reg (2, -20, FRAME_POINTER_REGNUM
);
2994 /* No frame pointer, and stack is smaller than 8k. */
2995 else if (! frame_pointer_needed
2996 && VAL_14_BITS_P (actual_fsize
+ 20)
2997 && (regs_ever_live
[2] || profile_flag
))
2998 load_reg (2, - (actual_fsize
+ 20), STACK_POINTER_REGNUM
);
3000 /* General register restores. */
3001 if (frame_pointer_needed
)
3003 for (i
= 18, offset
= local_fsize
; i
>= 4; i
--)
3004 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3006 load_reg (i
, offset
, FRAME_POINTER_REGNUM
);
3012 for (i
= 18, offset
= local_fsize
- actual_fsize
; i
>= 3; i
--)
3014 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3016 /* Only for the first load.
3017 merge_sp_adjust_with_load holds the register load
3018 with which we will merge the sp adjustment. */
3019 if (VAL_14_BITS_P (actual_fsize
+ 20)
3021 && ! merge_sp_adjust_with_load
)
3022 merge_sp_adjust_with_load
= i
;
3024 load_reg (i
, offset
, STACK_POINTER_REGNUM
);
3030 /* Align pointer properly (doubleword boundary). */
3031 offset
= (offset
+ 7) & ~7;
3033 /* FP register restores. */
3036 /* Adjust the register to index off of. */
3037 if (frame_pointer_needed
)
3038 set_reg_plus_d (1, FRAME_POINTER_REGNUM
, offset
);
3040 set_reg_plus_d (1, STACK_POINTER_REGNUM
, offset
);
3042 /* Actually do the restores now. */
3043 for (i
= 66; i
>= 48; i
-= 2)
3045 if (regs_ever_live
[i
] || regs_ever_live
[i
+ 1])
3047 emit_move_insn (gen_rtx (REG
, DFmode
, i
),
3048 gen_rtx (MEM
, DFmode
,
3049 gen_rtx (POST_INC
, DFmode
, tmpreg
)));
3054 /* Emit a blockage insn here to keep these insns from being moved to
3055 an earlier spot in the epilogue, or into the main instruction stream.
3057 This is necessary as we must not cut the stack back before all the
3058 restores are finished. */
3059 emit_insn (gen_blockage ());
3060 /* No frame pointer, but we have a stack greater than 8k. We restore
3061 %r2 very late in this case. (All other cases are restored as early
3063 if (! frame_pointer_needed
3064 && ! VAL_14_BITS_P (actual_fsize
+ 20)
3065 && (regs_ever_live
[2] || profile_flag
))
3067 set_reg_plus_d (STACK_POINTER_REGNUM
,
3068 STACK_POINTER_REGNUM
,
3071 /* This used to try and be clever by not depending on the value in
3072 %r30 and instead use the value held in %r1 (so that the 2nd insn
3073 which sets %r30 could be put in the delay slot of the return insn).
3075 That won't work since if the stack is exactly 8k set_reg_plus_d
3076 doesn't set %r1, just %r30. */
3077 load_reg (2, - 20, STACK_POINTER_REGNUM
);
3080 /* Reset stack pointer (and possibly frame pointer). The stack
3081 pointer is initially set to fp + 64 to avoid a race condition. */
3082 else if (frame_pointer_needed
)
3084 set_reg_plus_d (STACK_POINTER_REGNUM
, FRAME_POINTER_REGNUM
, 64);
3085 emit_insn (gen_pre_ldwm (frame_pointer_rtx
,
3089 /* If we were deferring a callee register restore, do it now. */
3090 else if (! frame_pointer_needed
&& merge_sp_adjust_with_load
)
3091 emit_insn (gen_pre_ldwm (gen_rtx (REG
, SImode
,
3092 merge_sp_adjust_with_load
),
3094 GEN_INT (- actual_fsize
)));
3095 else if (actual_fsize
!= 0)
3096 set_reg_plus_d (STACK_POINTER_REGNUM
,
3097 STACK_POINTER_REGNUM
,
3101 /* Fetch the return address for the frame COUNT steps up from
3102 the current frame, after the prologue. FRAMEADDR is the
3103 frame pointer of the COUNT frame.
3105 We want to ignore any export stub remnants here.
3107 The value returned is used in two different ways:
3109 1. To find a function's caller.
3111 2. To change the return address for a function.
3113 This function handles most instances of case 1; however, it will
3114 fail if there are two levels of stubs to execute on the return
3115 path. The only way I believe that can happen is if the return value
3116 needs a parameter relocation, which never happens for C code.
3118 This function handles most instances of case 2; however, it will
3119 fail if we did not originally have stub code on the return path
3120 but will need code on the new return path. This can happen if
3121 the caller & callee are both in the main program, but the new
3122 return location is in a shared library.
3124 To handle this correctly we need to set the return pointer at
3125 frame-20 to point to a return stub frame-24 to point to the
3126 location we wish to return to. */
3129 return_addr_rtx (count
, frameaddr
)
3137 saved_rp
= gen_reg_rtx (Pmode
);
3139 /* First, we start off with the normal return address pointer from
3142 emit_move_insn (saved_rp
, plus_constant (frameaddr
, -5 * UNITS_PER_WORD
));
3144 /* Get pointer to the instruction stream. We have to mask out the
3145 privilege level from the two low order bits of the return address
3146 pointer here so that ins will point to the start of the first
3147 instruction that would have been executed if we returned. */
3148 ins
= copy_to_reg (gen_rtx (AND
, Pmode
,
3149 copy_to_reg (gen_rtx (MEM
, Pmode
, saved_rp
)),
3151 label
= gen_label_rtx ();
3153 /* Check the instruction stream at the normal return address for the
3156 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3157 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3158 0x00011820 | stub+16: mtsp r1,sr0
3159 0xe0400002 | stub+20: be,n 0(sr0,rp)
3161 If it is an export stub, than our return address is really in
3164 emit_cmp_insn (gen_rtx (MEM
, SImode
, ins
),
3165 GEN_INT (0x4bc23fd1),
3166 NE
, NULL_RTX
, SImode
, 1, 0);
3167 emit_jump_insn (gen_bne (label
));
3169 emit_cmp_insn (gen_rtx (MEM
, SImode
, plus_constant (ins
, 4)),
3170 GEN_INT (0x004010a1),
3171 NE
, NULL_RTX
, SImode
, 1, 0);
3172 emit_jump_insn (gen_bne (label
));
3174 emit_cmp_insn (gen_rtx (MEM
, SImode
, plus_constant (ins
, 8)),
3175 GEN_INT (0x00011820),
3176 NE
, NULL_RTX
, SImode
, 1, 0);
3177 emit_jump_insn (gen_bne (label
));
3179 emit_cmp_insn (gen_rtx (MEM
, SImode
, plus_constant (ins
, 12)),
3180 GEN_INT (0xe0400002),
3181 NE
, NULL_RTX
, SImode
, 1, 0);
3183 /* If there is no export stub then just use our initial guess of
3186 emit_jump_insn (gen_bne (label
));
3188 /* Here we know that our return address pointer points to an export
3189 stub. We don't want to return the address of the export stub,
3190 but rather the return address that leads back into user code.
3191 That return address is stored at -24[frameaddr]. */
3193 emit_move_insn (saved_rp
, plus_constant (frameaddr
, -6 * UNITS_PER_WORD
));
3196 return gen_rtx (MEM
, Pmode
, memory_address (Pmode
, saved_rp
));
3199 /* This is only valid once reload has completed because it depends on
3200 knowing exactly how much (if any) frame there is and...
3202 It's only valid if there is no frame marker to de-allocate and...
3204 It's only valid if %r2 hasn't been saved into the caller's frame
3205 (we're not profiling and %r2 isn't live anywhere). */
3207 hppa_can_use_return_insn_p ()
3209 return (reload_completed
3210 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3212 && ! regs_ever_live
[2]
3213 && ! frame_pointer_needed
);
3217 emit_bcond_fp (code
, operand0
)
3221 emit_jump_insn (gen_rtx (SET
, VOIDmode
, pc_rtx
,
3222 gen_rtx (IF_THEN_ELSE
, VOIDmode
,
3223 gen_rtx (code
, VOIDmode
,
3224 gen_rtx (REG
, CCFPmode
, 0),
3226 gen_rtx (LABEL_REF
, VOIDmode
, operand0
),
3232 gen_cmp_fp (code
, operand0
, operand1
)
3234 rtx operand0
, operand1
;
3236 return gen_rtx (SET
, VOIDmode
, gen_rtx (REG
, CCFPmode
, 0),
3237 gen_rtx (code
, CCFPmode
, operand0
, operand1
));
3240 /* Adjust the cost of a scheduling dependency. Return the new cost of
3241 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3244 pa_adjust_cost (insn
, link
, dep_insn
, cost
)
3250 if (! recog_memoized (insn
))
3253 if (REG_NOTE_KIND (link
) == 0)
3255 /* Data dependency; DEP_INSN writes a register that INSN reads some
3258 if (get_attr_type (insn
) == TYPE_FPSTORE
)
3260 rtx pat
= PATTERN (insn
);
3261 rtx dep_pat
= PATTERN (dep_insn
);
3262 if (GET_CODE (pat
) == PARALLEL
)
3264 /* This happens for the fstXs,mb patterns. */
3265 pat
= XVECEXP (pat
, 0, 0);
3267 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
3268 /* If this happens, we have to extend this to schedule
3269 optimally. Return 0 for now. */
3272 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
3274 if (! recog_memoized (dep_insn
))
3276 /* DEP_INSN is writing its result to the register
3277 being stored in the fpstore INSN. */
3278 switch (get_attr_type (dep_insn
))
3281 /* This cost 3 cycles, not 2 as the md says for the
3282 700 and 7100. Note scaling of cost for 7100. */
3283 return cost
+ (pa_cpu
== PROCESSOR_700
) ? 1 : 2;
3290 case TYPE_FPSQRTSGL
:
3291 case TYPE_FPSQRTDBL
:
3292 /* In these important cases, we save one cycle compared to
3293 when flop instruction feed each other. */
3294 return cost
- (pa_cpu
== PROCESSOR_700
) ? 1 : 2;
3302 /* For other data dependencies, the default cost specified in the
3306 else if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
)
3308 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3311 if (get_attr_type (insn
) == TYPE_FPLOAD
)
3313 rtx pat
= PATTERN (insn
);
3314 rtx dep_pat
= PATTERN (dep_insn
);
3315 if (GET_CODE (pat
) == PARALLEL
)
3317 /* This happens for the fldXs,mb patterns. */
3318 pat
= XVECEXP (pat
, 0, 0);
3320 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
3321 /* If this happens, we have to extend this to schedule
3322 optimally. Return 0 for now. */
3325 if (reg_mentioned_p (SET_DEST (pat
), SET_SRC (dep_pat
)))
3327 if (! recog_memoized (dep_insn
))
3329 switch (get_attr_type (dep_insn
))
3336 case TYPE_FPSQRTSGL
:
3337 case TYPE_FPSQRTDBL
:
3338 /* A fpload can't be issued until one cycle before a
3339 preceding arithmetic operation has finished if
3340 the target of the fpload is any of the sources
3341 (or destination) of the arithmetic operation. */
3342 return cost
- (pa_cpu
== PROCESSOR_700
) ? 1 : 2;
3349 else if (get_attr_type (insn
) == TYPE_FPALU
)
3351 rtx pat
= PATTERN (insn
);
3352 rtx dep_pat
= PATTERN (dep_insn
);
3353 if (GET_CODE (pat
) == PARALLEL
)
3355 /* This happens for the fldXs,mb patterns. */
3356 pat
= XVECEXP (pat
, 0, 0);
3358 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
3359 /* If this happens, we have to extend this to schedule
3360 optimally. Return 0 for now. */
3363 if (reg_mentioned_p (SET_DEST (pat
), SET_SRC (dep_pat
)))
3365 if (! recog_memoized (dep_insn
))
3367 switch (get_attr_type (dep_insn
))
3371 case TYPE_FPSQRTSGL
:
3372 case TYPE_FPSQRTDBL
:
3373 /* An ALU flop can't be issued until two cycles before a
3374 preceding divide or sqrt operation has finished if
3375 the target of the ALU flop is any of the sources
3376 (or destination) of the divide or sqrt operation. */
3377 return cost
- (pa_cpu
== PROCESSOR_700
) ? 2 : 4;
3385 /* For other anti dependencies, the cost is 0. */
3388 else if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
3390 /* Output dependency; DEP_INSN writes a register that INSN writes some
3392 if (get_attr_type (insn
) == TYPE_FPLOAD
)
3394 rtx pat
= PATTERN (insn
);
3395 rtx dep_pat
= PATTERN (dep_insn
);
3396 if (GET_CODE (pat
) == PARALLEL
)
3398 /* This happens for the fldXs,mb patterns. */
3399 pat
= XVECEXP (pat
, 0, 0);
3401 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
3402 /* If this happens, we have to extend this to schedule
3403 optimally. Return 0 for now. */
3406 if (reg_mentioned_p (SET_DEST (pat
), SET_DEST (dep_pat
)))
3408 if (! recog_memoized (dep_insn
))
3410 switch (get_attr_type (dep_insn
))
3417 case TYPE_FPSQRTSGL
:
3418 case TYPE_FPSQRTDBL
:
3419 /* A fpload can't be issued until one cycle before a
3420 preceding arithmetic operation has finished if
3421 the target of the fpload is the destination of the
3422 arithmetic operation. */
3423 return cost
- (pa_cpu
== PROCESSOR_700
) ? 1 : 2;
3430 else if (get_attr_type (insn
) == TYPE_FPALU
)
3432 rtx pat
= PATTERN (insn
);
3433 rtx dep_pat
= PATTERN (dep_insn
);
3434 if (GET_CODE (pat
) == PARALLEL
)
3436 /* This happens for the fldXs,mb patterns. */
3437 pat
= XVECEXP (pat
, 0, 0);
3439 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
3440 /* If this happens, we have to extend this to schedule
3441 optimally. Return 0 for now. */
3444 if (reg_mentioned_p (SET_DEST (pat
), SET_DEST (dep_pat
)))
3446 if (! recog_memoized (dep_insn
))
3448 switch (get_attr_type (dep_insn
))
3452 case TYPE_FPSQRTSGL
:
3453 case TYPE_FPSQRTDBL
:
3454 /* An ALU flop can't be issued until two cycles before a
3455 preceding divide or sqrt operation has finished if
3456 the target of the ALU flop is also the target of
3457 of the divide or sqrt operation. */
3458 return cost
- (pa_cpu
== PROCESSOR_700
) ? 2 : 4;
3466 /* For other output dependencies, the cost is 0. */
3473 /* Return any length adjustment needed by INSN which already has its length
3474 computed as LENGTH. Return zero if no adjustment is necessary.
3476 For the PA: function calls, millicode calls, and backwards short
3477 conditional branches with unfilled delay slots need an adjustment by +1
3478 (to account for the NOP which will be inserted into the instruction stream).
3480 Also compute the length of an inline block move here as it is too
3481 complicated to express as a length attribute in pa.md. */
3483 pa_adjust_insn_length (insn
, length
)
3487 rtx pat
= PATTERN (insn
);
3489 /* Call insns which are *not* indirect and have unfilled delay slots. */
3490 if (GET_CODE (insn
) == CALL_INSN
)
3493 if (GET_CODE (XVECEXP (pat
, 0, 0)) == CALL
3494 && GET_CODE (XEXP (XEXP (XVECEXP (pat
, 0, 0), 0), 0)) == SYMBOL_REF
)
3496 else if (GET_CODE (XVECEXP (pat
, 0, 0)) == SET
3497 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat
, 0, 0), 1), 0), 0))
3503 /* Jumps inside switch tables which have unfilled delay slots
3504 also need adjustment. */
3505 else if (GET_CODE (insn
) == JUMP_INSN
3506 && simplejump_p (insn
)
3507 && GET_MODE (PATTERN (insn
)) == DImode
)
3509 /* Millicode insn with an unfilled delay slot. */
3510 else if (GET_CODE (insn
) == INSN
3511 && GET_CODE (pat
) != SEQUENCE
3512 && GET_CODE (pat
) != USE
3513 && GET_CODE (pat
) != CLOBBER
3514 && get_attr_type (insn
) == TYPE_MILLI
)
3516 /* Block move pattern. */
3517 else if (GET_CODE (insn
) == INSN
3518 && GET_CODE (pat
) == PARALLEL
3519 && GET_CODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == MEM
3520 && GET_CODE (XEXP (XVECEXP (pat
, 0, 0), 1)) == MEM
3521 && GET_MODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == BLKmode
3522 && GET_MODE (XEXP (XVECEXP (pat
, 0, 0), 1)) == BLKmode
)
3523 return compute_movstrsi_length (insn
) - 4;
3524 /* Conditional branch with an unfilled delay slot. */
3525 else if (GET_CODE (insn
) == JUMP_INSN
&& ! simplejump_p (insn
))
3527 /* Adjust a short backwards conditional with an unfilled delay slot. */
3528 if (GET_CODE (pat
) == SET
3530 && ! forward_branch_p (insn
))
3532 else if (GET_CODE (pat
) == PARALLEL
3533 && get_attr_type (insn
) == TYPE_PARALLEL_BRANCH
3536 /* Adjust dbra insn with short backwards conditional branch with
3537 unfilled delay slot -- only for case where counter is in a
3538 general register register. */
3539 else if (GET_CODE (pat
) == PARALLEL
3540 && GET_CODE (XVECEXP (pat
, 0, 1)) == SET
3541 && GET_CODE (XEXP (XVECEXP (pat
, 0, 1), 0)) == REG
3542 && ! FP_REG_P (XEXP (XVECEXP (pat
, 0, 1), 0))
3544 && ! forward_branch_p (insn
))
3552 /* Print operand X (an rtx) in assembler syntax to file FILE.
3553 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3554 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3557 print_operand (file
, x
, code
)
3565 /* Output a 'nop' if there's nothing for the delay slot. */
3566 if (dbr_sequence_length () == 0)
3567 fputs ("\n\tnop", file
);
3570 /* Output an nullification completer if there's nothing for the */
3571 /* delay slot or nullification is requested. */
3572 if (dbr_sequence_length () == 0 ||
3574 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0))))
3578 /* Print out the second register name of a register pair.
3579 I.e., R (6) => 7. */
3580 fputs (reg_names
[REGNO (x
)+1], file
);
3583 /* A register or zero. */
3585 || (x
== CONST0_RTX (DFmode
))
3586 || (x
== CONST0_RTX (SFmode
)))
3593 case 'C': /* Plain (C)ondition */
3595 switch (GET_CODE (x
))
3598 fputs ("=", file
); break;
3600 fputs ("<>", file
); break;
3602 fputs (">", file
); break;
3604 fputs (">=", file
); break;
3606 fputs (">>=", file
); break;
3608 fputs (">>", file
); break;
3610 fputs ("<", file
); break;
3612 fputs ("<=", file
); break;
3614 fputs ("<<=", file
); break;
3616 fputs ("<<", file
); break;
3621 case 'N': /* Condition, (N)egated */
3622 switch (GET_CODE (x
))
3625 fputs ("<>", file
); break;
3627 fputs ("=", file
); break;
3629 fputs ("<=", file
); break;
3631 fputs ("<", file
); break;
3633 fputs ("<<", file
); break;
3635 fputs ("<<=", file
); break;
3637 fputs (">=", file
); break;
3639 fputs (">", file
); break;
3641 fputs (">>", file
); break;
3643 fputs (">>=", file
); break;
3648 /* For floating point comparisons. Need special conditions to deal
3649 with NaNs properly. */
3651 switch (GET_CODE (x
))
3654 fputs ("!=", file
); break;
3656 fputs ("=", file
); break;
3658 fputs ("<=", file
); break;
3660 fputs ("<", file
); break;
3662 fputs (">=", file
); break;
3664 fputs (">", file
); break;
3669 case 'S': /* Condition, operands are (S)wapped. */
3670 switch (GET_CODE (x
))
3673 fputs ("=", file
); break;
3675 fputs ("<>", file
); break;
3677 fputs ("<", file
); break;
3679 fputs ("<=", file
); break;
3681 fputs ("<<=", file
); break;
3683 fputs ("<<", file
); break;
3685 fputs (">", file
); break;
3687 fputs (">=", file
); break;
3689 fputs (">>=", file
); break;
3691 fputs (">>", file
); break;
3696 case 'B': /* Condition, (B)oth swapped and negate. */
3697 switch (GET_CODE (x
))
3700 fputs ("<>", file
); break;
3702 fputs ("=", file
); break;
3704 fputs (">=", file
); break;
3706 fputs (">", file
); break;
3708 fputs (">>", file
); break;
3710 fputs (">>=", file
); break;
3712 fputs ("<=", file
); break;
3714 fputs ("<", file
); break;
3716 fputs ("<<", file
); break;
3718 fputs ("<<=", file
); break;
3724 if (GET_CODE (x
) == CONST_INT
)
3726 fprintf (file
, "%d", ~INTVAL (x
));
3731 if (GET_CODE (x
) == CONST_INT
)
3733 fprintf (file
, "%d", 32 - (INTVAL (x
) & 31));
3738 if (GET_CODE (x
) == CONST_INT
&& exact_log2 (INTVAL (x
)) >= 0)
3740 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
3745 if (GET_CODE (x
) == CONST_INT
)
3747 fprintf (file
, "%d", 31 - (INTVAL (x
) & 31));
3752 if (GET_CODE (x
) == CONST_INT
)
3757 switch (GET_CODE (XEXP (x
, 0)))
3761 fputs ("s,mb", file
);
3765 fputs ("s,ma", file
);
3768 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
3769 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == MULT
)
3770 fputs ("x,s", file
);
3771 else if (code
== 'F')
3781 output_global_address (file
, x
, 0);
3784 output_global_address (file
, x
, 1);
3786 case 0: /* Don't do anything special */
3791 compute_zdepi_operands (INTVAL (x
), op
);
3792 fprintf (file
, "%d,%d,%d", op
[0], op
[1], op
[2]);
3798 if (GET_CODE (x
) == REG
)
3800 fputs (reg_names
[REGNO (x
)], file
);
3801 if (FP_REG_P (x
) && GET_MODE_SIZE (GET_MODE (x
)) <= 4 && (REGNO (x
) & 1) == 0)
3804 else if (GET_CODE (x
) == MEM
)
3806 int size
= GET_MODE_SIZE (GET_MODE (x
));
3807 rtx base
= XEXP (XEXP (x
, 0), 0);
3808 switch (GET_CODE (XEXP (x
, 0)))
3812 fprintf (file
, "-%d(0,%s)", size
, reg_names
[REGNO (base
)]);
3816 fprintf (file
, "%d(0,%s)", size
, reg_names
[REGNO (base
)]);
3819 if (GET_CODE (XEXP (x
, 0)) == PLUS
3820 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
)
3821 fprintf (file
, "%s(0,%s)",
3822 reg_names
[REGNO (XEXP (XEXP (XEXP (x
, 0), 0), 0))],
3823 reg_names
[REGNO (XEXP (XEXP (x
, 0), 1))]);
3824 else if (GET_CODE (XEXP (x
, 0)) == PLUS
3825 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == MULT
)
3826 fprintf (file
, "%s(0,%s)",
3827 reg_names
[REGNO (XEXP (XEXP (XEXP (x
, 0), 1), 0))],
3828 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
3830 output_address (XEXP (x
, 0));
3835 output_addr_const (file
, x
);
3838 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
3841 output_global_address (file
, x
, round_constant
)
3847 /* Imagine (high (const (plus ...))). */
3848 if (GET_CODE (x
) == HIGH
)
3851 if (GET_CODE (x
) == SYMBOL_REF
&& read_only_operand (x
))
3852 assemble_name (file
, XSTR (x
, 0));
3853 else if (GET_CODE (x
) == SYMBOL_REF
&& !flag_pic
)
3855 assemble_name (file
, XSTR (x
, 0));
3856 fputs ("-$global$", file
);
3858 else if (GET_CODE (x
) == CONST
)
3861 int offset
= 0; /* assembler wants -$global$ at end */
3864 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)
3866 base
= XEXP (XEXP (x
, 0), 0);
3867 output_addr_const (file
, base
);
3869 else if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == CONST_INT
)
3870 offset
= INTVAL (XEXP (XEXP (x
, 0), 0));
3873 if (GET_CODE (XEXP (XEXP (x
, 0), 1)) == SYMBOL_REF
)
3875 base
= XEXP (XEXP (x
, 0), 1);
3876 output_addr_const (file
, base
);
3878 else if (GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
3879 offset
= INTVAL (XEXP (XEXP (x
, 0),1));
3882 /* How bogus. The compiler is apparently responsible for
3883 rounding the constant if it uses an LR field selector.
3885 The linker and/or assembler seem a better place since
3886 they have to do this kind of thing already.
3888 If we fail to do this, HP's optimizing linker may eliminate
3889 an addil, but not update the ldw/stw/ldo instruction that
3890 uses the result of the addil. */
3892 offset
= ((offset
+ 0x1000) & ~0x1fff);
3894 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
3904 else if (GET_CODE (XEXP (x
, 0)) == MINUS
3905 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
))
3909 if (!read_only_operand (base
) && !flag_pic
)
3910 fputs ("-$global$", file
);
3912 fprintf (file
,"%s%d", sep
, offset
);
3915 output_addr_const (file
, x
);
3919 output_deferred_plabels (file
)
3923 /* If we have deferred plabels, then we need to switch into the data
3924 section and align it to a 4 byte boundary before we output the
3925 deferred plabels. */
3926 if (n_deferred_plabels
)
3929 ASM_OUTPUT_ALIGN (file
, 2);
3932 /* Now output the deferred plabels. */
3933 for (i
= 0; i
< n_deferred_plabels
; i
++)
3935 ASM_OUTPUT_INTERNAL_LABEL (file
, "L", CODE_LABEL_NUMBER (deferred_plabels
[i
].internal_label
));
3936 assemble_integer (gen_rtx (SYMBOL_REF
, VOIDmode
,
3937 deferred_plabels
[i
].name
), 4, 1);
3941 /* HP's millicode routines mean something special to the assembler.
3942 Keep track of which ones we have used. */
3944 enum millicodes
{ remI
, remU
, divI
, divU
, mulI
, mulU
, end1000
};
3945 static char imported
[(int)end1000
];
3946 static char *milli_names
[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
3947 static char import_string
[] = ".IMPORT $$....,MILLICODE";
3948 #define MILLI_START 10
3952 enum millicodes code
;
3954 char str
[sizeof (import_string
)];
3956 if (!imported
[(int)code
])
3958 imported
[(int)code
] = 1;
3959 strcpy (str
, import_string
);
3960 strncpy (str
+ MILLI_START
, milli_names
[(int)code
], 4);
3961 output_asm_insn (str
, 0);
3965 /* The register constraints have put the operands and return value in
3966 the proper registers. */
3969 output_mul_insn (unsignedp
, insn
)
3973 import_milli (mulI
);
3974 return output_millicode_call (insn
, gen_rtx (SYMBOL_REF
, SImode
, "$$mulI"));
3977 /* Emit the rtl for doing a division by a constant. */
3979 /* Do magic division millicodes exist for this value? */
3980 static int magic_milli
[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
3983 /* We'll use an array to keep track of the magic millicodes and
3984 whether or not we've used them already. [n][0] is signed, [n][1] is
3987 static int div_milli
[16][2];
3990 div_operand (op
, mode
)
3992 enum machine_mode mode
;
3994 return (mode
== SImode
3995 && ((GET_CODE (op
) == REG
&& REGNO (op
) == 25)
3996 || (GET_CODE (op
) == CONST_INT
&& INTVAL (op
) > 0
3997 && INTVAL (op
) < 16 && magic_milli
[INTVAL (op
)])));
4001 emit_hpdiv_const (operands
, unsignedp
)
4005 if (GET_CODE (operands
[2]) == CONST_INT
4006 && INTVAL (operands
[2]) > 0
4007 && INTVAL (operands
[2]) < 16
4008 && magic_milli
[INTVAL (operands
[2])])
4010 emit_move_insn ( gen_rtx (REG
, SImode
, 26), operands
[1]);
4013 (PARALLEL
, VOIDmode
,
4014 gen_rtvec (5, gen_rtx (SET
, VOIDmode
, gen_rtx (REG
, SImode
, 29),
4015 gen_rtx (unsignedp
? UDIV
: DIV
, SImode
,
4016 gen_rtx (REG
, SImode
, 26),
4018 gen_rtx (CLOBBER
, VOIDmode
, operands
[3]),
4019 gen_rtx (CLOBBER
, VOIDmode
, gen_rtx (REG
, SImode
, 26)),
4020 gen_rtx (CLOBBER
, VOIDmode
, gen_rtx (REG
, SImode
, 25)),
4021 gen_rtx (CLOBBER
, VOIDmode
, gen_rtx (REG
, SImode
, 31)))));
4022 emit_move_insn (operands
[0], gen_rtx (REG
, SImode
, 29));
4029 output_div_insn (operands
, unsignedp
, insn
)
4036 /* If the divisor is a constant, try to use one of the special
4038 if (GET_CODE (operands
[0]) == CONST_INT
)
4040 static char buf
[100];
4041 divisor
= INTVAL (operands
[0]);
4042 if (!div_milli
[divisor
][unsignedp
])
4044 div_milli
[divisor
][unsignedp
] = 1;
4046 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands
);
4048 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands
);
4052 sprintf (buf
, "$$divU_%d", INTVAL (operands
[0]));
4053 return output_millicode_call (insn
,
4054 gen_rtx (SYMBOL_REF
, SImode
, buf
));
4058 sprintf (buf
, "$$divI_%d", INTVAL (operands
[0]));
4059 return output_millicode_call (insn
,
4060 gen_rtx (SYMBOL_REF
, SImode
, buf
));
4063 /* Divisor isn't a special constant. */
4068 import_milli (divU
);
4069 return output_millicode_call (insn
,
4070 gen_rtx (SYMBOL_REF
, SImode
, "$$divU"));
4074 import_milli (divI
);
4075 return output_millicode_call (insn
,
4076 gen_rtx (SYMBOL_REF
, SImode
, "$$divI"));
4081 /* Output a $$rem millicode to do mod. */
4084 output_mod_insn (unsignedp
, insn
)
4090 import_milli (remU
);
4091 return output_millicode_call (insn
,
4092 gen_rtx (SYMBOL_REF
, SImode
, "$$remU"));
4096 import_milli (remI
);
4097 return output_millicode_call (insn
,
4098 gen_rtx (SYMBOL_REF
, SImode
, "$$remI"));
4103 output_arg_descriptor (call_insn
)
4107 enum machine_mode arg_mode
;
4109 int i
, output_flag
= 0;
4112 for (i
= 0; i
< 4; i
++)
4115 /* Specify explicitly that no argument relocations should take place
4116 if using the portable runtime calling conventions. */
4117 if (TARGET_PORTABLE_RUNTIME
)
4119 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
4124 if (GET_CODE (call_insn
) != CALL_INSN
)
4126 for (link
= CALL_INSN_FUNCTION_USAGE (call_insn
); link
; link
= XEXP (link
, 1))
4128 rtx use
= XEXP (link
, 0);
4130 if (! (GET_CODE (use
) == USE
4131 && GET_CODE (XEXP (use
, 0)) == REG
4132 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use
, 0)))))
4135 arg_mode
= GET_MODE (XEXP (use
, 0));
4136 regno
= REGNO (XEXP (use
, 0));
4137 if (regno
>= 23 && regno
<= 26)
4139 arg_regs
[26 - regno
] = "GR";
4140 if (arg_mode
== DImode
)
4141 arg_regs
[25 - regno
] = "GR";
4143 else if (regno
>= 32 && regno
<= 39)
4145 if (arg_mode
== SFmode
)
4146 arg_regs
[(regno
- 32) / 2] = "FR";
4149 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
4150 arg_regs
[(regno
- 34) / 2] = "FR";
4151 arg_regs
[(regno
- 34) / 2 + 1] = "FU";
4153 arg_regs
[(regno
- 34) / 2] = "FU";
4154 arg_regs
[(regno
- 34) / 2 + 1] = "FR";
4159 fputs ("\t.CALL ", asm_out_file
);
4160 for (i
= 0; i
< 4; i
++)
4165 fputc (',', asm_out_file
);
4166 fprintf (asm_out_file
, "ARGW%d=%s", i
, arg_regs
[i
]);
4169 fputc ('\n', asm_out_file
);
4172 /* Return the class of any secondary reload register that is needed to
4173 move IN into a register in class CLASS using mode MODE.
4175 Profiling has showed this routine and its descendants account for
4176 a significant amount of compile time (~7%). So it has been
4177 optimized to reduce redundant computations and eliminate useless
4180 It might be worthwhile to try and make this a leaf function too. */
4183 secondary_reload_class (class, mode
, in
)
4184 enum reg_class
class;
4185 enum machine_mode mode
;
4188 int regno
, is_symbolic
;
4190 /* Trying to load a constant into a FP register during PIC code
4191 generation will require %r1 as a scratch register. */
4193 && GET_MODE_CLASS (mode
) == MODE_INT
4194 && FP_REG_CLASS_P (class)
4195 && (GET_CODE (in
) == CONST_INT
|| GET_CODE (in
) == CONST_DOUBLE
))
4198 /* Profiling showed the PA port spends about 1.3% of its compilation
4199 time in true_regnum from calls inside secondary_reload_class. */
4201 if (GET_CODE (in
) == REG
)
4204 if (regno
>= FIRST_PSEUDO_REGISTER
)
4205 regno
= true_regnum (in
);
4207 else if (GET_CODE (in
) == SUBREG
)
4208 regno
= true_regnum (in
);
4212 /* If we have something like (mem (mem (...)), we can safely assume the
4213 inner MEM will end up in a general register after reloading, so there's
4214 no need for a secondary reload. */
4215 if (GET_CODE (in
) == MEM
4216 && GET_CODE (XEXP (in
, 0)) == MEM
)
4219 /* Handle out of range displacement for integer mode loads/stores of
4221 if (((regno
>= FIRST_PSEUDO_REGISTER
|| regno
== -1)
4222 && GET_MODE_CLASS (mode
) == MODE_INT
4223 && FP_REG_CLASS_P (class))
4224 || (class == SHIFT_REGS
&& (regno
<= 0 || regno
>= 32)))
4225 return GENERAL_REGS
;
4227 if (GET_CODE (in
) == HIGH
)
4230 /* Profiling has showed GCC spends about 2.6% of its compilation
4231 time in symbolic_operand from calls inside secondary_reload_class.
4233 We use an inline copy and only compute its return value once to avoid
4235 switch (GET_CODE (in
))
4245 is_symbolic
= ((GET_CODE (XEXP (tmp
, 0)) == SYMBOL_REF
4246 || GET_CODE (XEXP (tmp
, 0)) == LABEL_REF
)
4247 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
);
4257 && read_only_operand (in
))
4260 if (class != R1_REGS
&& is_symbolic
)
4267 function_arg_padding (mode
, type
)
4268 enum machine_mode mode
;
4273 if (mode
== BLKmode
)
4275 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
4276 size
= int_size_in_bytes (type
) * BITS_PER_UNIT
;
4278 return upward
; /* Don't know if this is right, but */
4279 /* same as old definition. */
4282 size
= GET_MODE_BITSIZE (mode
);
4283 if (size
< PARM_BOUNDARY
)
4285 else if (size
% PARM_BOUNDARY
)
4292 /* Do what is necessary for `va_start'. The argument is ignored;
4293 We look at the current function to determine if stdargs or varargs
4294 is used and fill in an initial va_list. A pointer to this constructor
4298 hppa_builtin_saveregs (arglist
)
4302 tree fntype
= TREE_TYPE (current_function_decl
);
4303 int argadj
= ((!(TYPE_ARG_TYPES (fntype
) != 0
4304 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
4305 != void_type_node
)))
4306 ? UNITS_PER_WORD
: 0);
4309 offset
= plus_constant (current_function_arg_offset_rtx
, argadj
);
4311 offset
= current_function_arg_offset_rtx
;
4313 /* Store general registers on the stack. */
4314 dest
= gen_rtx (MEM
, BLKmode
,
4315 plus_constant (current_function_internal_arg_pointer
, -16));
4316 move_block_from_reg (23, dest
, 4, 4 * UNITS_PER_WORD
);
4318 /* move_block_from_reg will emit code to store the argument registers
4319 individually as scalar stores.
4321 However, other insns may later load from the same addresses for
4322 a structure load (passing a struct to a varargs routine).
4324 The alias code assumes that such aliasing can never happen, so we
4325 have to keep memory referencing insns from moving up beyond the
4326 last argument register store. So we emit a blockage insn here. */
4327 emit_insn (gen_blockage ());
4329 if (flag_check_memory_usage
)
4330 emit_library_call (chkr_set_right_libfunc
, 1, VOIDmode
, 3,
4332 GEN_INT (4 * UNITS_PER_WORD
), TYPE_MODE (sizetype
),
4333 GEN_INT (MEMORY_USE_RW
),
4334 TYPE_MODE (integer_type_node
));
4336 return copy_to_reg (expand_binop (Pmode
, add_optab
,
4337 current_function_internal_arg_pointer
,
4338 offset
, 0, 0, OPTAB_LIB_WIDEN
));
4341 /* This routine handles all the normal conditional branch sequences we
4342 might need to generate. It handles compare immediate vs compare
4343 register, nullification of delay slots, varying length branches,
4344 negated branches, and all combinations of the above. It returns the
4345 output appropriate to emit the branch corresponding to all given
4349 output_cbranch (operands
, nullify
, length
, negated
, insn
)
4351 int nullify
, length
, negated
;
4354 static char buf
[100];
4357 /* A conditional branch to the following instruction (eg the delay slot) is
4358 asking for a disaster. This can happen when not optimizing.
4360 In such cases it is safe to emit nothing. */
4362 if (next_active_insn (JUMP_LABEL (insn
)) == next_active_insn (insn
))
4365 /* If this is a long branch with its delay slot unfilled, set `nullify'
4366 as it can nullify the delay slot and save a nop. */
4367 if (length
== 8 && dbr_sequence_length () == 0)
4370 /* If this is a short forward conditional branch which did not get
4371 its delay slot filled, the delay slot can still be nullified. */
4372 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
4373 nullify
= forward_branch_p (insn
);
4375 /* A forward branch over a single nullified insn can be done with a
4376 comclr instruction. This avoids a single cycle penalty due to
4377 mis-predicted branch if we fall through (branch not taken). */
4379 && next_real_insn (insn
) != 0
4380 && get_attr_length (next_real_insn (insn
)) == 4
4381 && JUMP_LABEL (insn
) == next_nonnote_insn (next_real_insn (insn
))
4387 /* All short conditional branches except backwards with an unfilled
4391 strcpy (buf
, "com%I2clr,");
4393 strcpy (buf
, "com%I2b,");
4395 strcat (buf
, "%B3");
4397 strcat (buf
, "%S3");
4399 strcat (buf
, " %2,%1,0");
4401 strcat (buf
, ",n %2,%1,%0");
4403 strcat (buf
, " %2,%1,%0");
4406 /* All long conditionals. Note an short backward branch with an
4407 unfilled delay slot is treated just like a long backward branch
4408 with an unfilled delay slot. */
4410 /* Handle weird backwards branch with a filled delay slot
4411 with is nullified. */
4412 if (dbr_sequence_length () != 0
4413 && ! forward_branch_p (insn
)
4416 strcpy (buf
, "com%I2b,");
4418 strcat (buf
, "%S3");
4420 strcat (buf
, "%B3");
4421 strcat (buf
, ",n %2,%1,.+12\n\tbl %0,0");
4423 /* Handle short backwards branch with an unfilled delay slot.
4424 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
4425 taken and untaken branches. */
4426 else if (dbr_sequence_length () == 0
4427 && ! forward_branch_p (insn
)
4429 && VAL_14_BITS_P (insn_addresses
[INSN_UID (JUMP_LABEL (insn
))]
4430 - insn_addresses
[INSN_UID (insn
)] - 8))
4432 strcpy (buf
, "com%I2b,");
4434 strcat (buf
, "%B3 %2,%1,%0%#");
4436 strcat (buf
, "%S3 %2,%1,%0%#");
4440 strcpy (buf
, "com%I2clr,");
4442 strcat (buf
, "%S3");
4444 strcat (buf
, "%B3");
4446 strcat (buf
, " %2,%1,0\n\tbl,n %0,0");
4448 strcat (buf
, " %2,%1,0\n\tbl %0,0");
4453 /* Very long branch. Right now we only handle these when not
4454 optimizing. See "jump" pattern in pa.md for details. */
4458 /* Create a reversed conditional branch which branches around
4459 the following insns. */
4461 strcpy (buf
, "com%I2b,%S3,n %2,%1,.+20");
4463 strcpy (buf
, "com%I2b,%B3,n %2,%1,.+20");
4464 output_asm_insn (buf
, operands
);
4466 /* Output an insn to save %r1. */
4467 output_asm_insn ("stw %%r1,-16(%%r30)", operands
);
4469 /* Now output a very long branch to the original target. */
4470 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands
);
4472 /* Now restore the value of %r1 in the delay slot. We're not
4473 optimizing so we know nothing else can be in the delay slot. */
4474 return "ldw -16(%%r30),%%r1";
4477 /* Very long branch when generating PIC code. Right now we only
4478 handle these when not optimizing. See "jump" pattern in pa.md
4483 /* Create a reversed conditional branch which branches around
4484 the following insns. */
4486 strcpy (buf
, "com%I2b,%S3,n %2,%1,.+28");
4488 strcpy (buf
, "com%I2b,%B3,n %2,%1,.+28");
4489 output_asm_insn (buf
, operands
);
4491 /* Output an insn to save %r1. */
4492 output_asm_insn ("stw %%r1,-16(%%r30)", operands
);
4494 /* Now output a very long PIC branch to the original target. */
4498 xoperands
[0] = operands
[0];
4499 xoperands
[1] = operands
[1];
4500 xoperands
[2] = operands
[2];
4501 xoperands
[3] = operands
[3];
4502 xoperands
[4] = gen_label_rtx ();
4504 output_asm_insn ("bl .+8,%%r1\n\taddil L'%l0-%l4,%%r1", xoperands
);
4505 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
4506 CODE_LABEL_NUMBER (xoperands
[4]));
4507 output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1\n\tbv 0(%%r1)", xoperands
);
4510 /* Now restore the value of %r1 in the delay slot. We're not
4511 optimizing so we know nothing else can be in the delay slot. */
4512 return "ldw -16(%%r30),%%r1";
4520 /* This routine handles all the branch-on-bit conditional branch sequences we
4521 might need to generate. It handles nullification of delay slots,
4522 varying length branches, negated branches and all combinations of the
4523 above. it returns the appropriate output template to emit the branch. */
4526 output_bb (operands
, nullify
, length
, negated
, insn
, which
)
4528 int nullify
, length
, negated
;
4532 static char buf
[100];
4535 /* A conditional branch to the following instruction (eg the delay slot) is
4536 asking for a disaster. I do not think this can happen as this pattern
4537 is only used when optimizing; jump optimization should eliminate the
4538 jump. But be prepared just in case. */
4540 if (next_active_insn (JUMP_LABEL (insn
)) == next_active_insn (insn
))
4543 /* If this is a long branch with its delay slot unfilled, set `nullify'
4544 as it can nullify the delay slot and save a nop. */
4545 if (length
== 8 && dbr_sequence_length () == 0)
4548 /* If this is a short forward conditional branch which did not get
4549 its delay slot filled, the delay slot can still be nullified. */
4550 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
4551 nullify
= forward_branch_p (insn
);
4553 /* A forward branch over a single nullified insn can be done with a
4554 extrs instruction. This avoids a single cycle penalty due to
4555 mis-predicted branch if we fall through (branch not taken). */
4558 && next_real_insn (insn
) != 0
4559 && get_attr_length (next_real_insn (insn
)) == 4
4560 && JUMP_LABEL (insn
) == next_nonnote_insn (next_real_insn (insn
))
4567 /* All short conditional branches except backwards with an unfilled
4571 strcpy (buf
, "extrs,");
4573 strcpy (buf
, "bb,");
4574 if ((which
== 0 && negated
)
4575 || (which
== 1 && ! negated
))
4580 strcat (buf
, " %0,%1,1,0");
4581 else if (nullify
&& negated
)
4582 strcat (buf
, ",n %0,%1,%3");
4583 else if (nullify
&& ! negated
)
4584 strcat (buf
, ",n %0,%1,%2");
4585 else if (! nullify
&& negated
)
4586 strcat (buf
, "%0,%1,%3");
4587 else if (! nullify
&& ! negated
)
4588 strcat (buf
, " %0,%1,%2");
4591 /* All long conditionals. Note an short backward branch with an
4592 unfilled delay slot is treated just like a long backward branch
4593 with an unfilled delay slot. */
4595 /* Handle weird backwards branch with a filled delay slot
4596 with is nullified. */
4597 if (dbr_sequence_length () != 0
4598 && ! forward_branch_p (insn
)
4601 strcpy (buf
, "bb,");
4602 if ((which
== 0 && negated
)
4603 || (which
== 1 && ! negated
))
4608 strcat (buf
, ",n %0,%1,.+12\n\tbl %3,0");
4610 strcat (buf
, ",n %0,%1,.+12\n\tbl %2,0");
4612 /* Handle short backwards branch with an unfilled delay slot.
4613 Using a bb;nop rather than extrs;bl saves 1 cycle for both
4614 taken and untaken branches. */
4615 else if (dbr_sequence_length () == 0
4616 && ! forward_branch_p (insn
)
4618 && VAL_14_BITS_P (insn_addresses
[INSN_UID (JUMP_LABEL (insn
))]
4619 - insn_addresses
[INSN_UID (insn
)] - 8))
4621 strcpy (buf
, "bb,");
4622 if ((which
== 0 && negated
)
4623 || (which
== 1 && ! negated
))
4628 strcat (buf
, " %0,%1,%3%#");
4630 strcat (buf
, " %0,%1,%2%#");
4634 strcpy (buf
, "extrs,");
4635 if ((which
== 0 && negated
)
4636 || (which
== 1 && ! negated
))
4640 if (nullify
&& negated
)
4641 strcat (buf
, " %0,%1,1,0\n\tbl,n %3,0");
4642 else if (nullify
&& ! negated
)
4643 strcat (buf
, " %0,%1,1,0\n\tbl,n %2,0");
4645 strcat (buf
, " %0,%1,1,0\n\tbl %3,0");
4647 strcat (buf
, " %0,%1,1,0\n\tbl %2,0");
4657 /* This routine handles all the branch-on-variable-bit conditional branch
4658 sequences we might need to generate. It handles nullification of delay
4659 slots, varying length branches, negated branches and all combinations
4660 of the above. it returns the appropriate output template to emit the
4664 output_bvb (operands
, nullify
, length
, negated
, insn
, which
)
4666 int nullify
, length
, negated
;
4670 static char buf
[100];
4673 /* A conditional branch to the following instruction (eg the delay slot) is
4674 asking for a disaster. I do not think this can happen as this pattern
4675 is only used when optimizing; jump optimization should eliminate the
4676 jump. But be prepared just in case. */
4678 if (next_active_insn (JUMP_LABEL (insn
)) == next_active_insn (insn
))
4681 /* If this is a long branch with its delay slot unfilled, set `nullify'
4682 as it can nullify the delay slot and save a nop. */
4683 if (length
== 8 && dbr_sequence_length () == 0)
4686 /* If this is a short forward conditional branch which did not get
4687 its delay slot filled, the delay slot can still be nullified. */
4688 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
4689 nullify
= forward_branch_p (insn
);
4691 /* A forward branch over a single nullified insn can be done with a
4692 extrs instruction. This avoids a single cycle penalty due to
4693 mis-predicted branch if we fall through (branch not taken). */
4696 && next_real_insn (insn
) != 0
4697 && get_attr_length (next_real_insn (insn
)) == 4
4698 && JUMP_LABEL (insn
) == next_nonnote_insn (next_real_insn (insn
))
4705 /* All short conditional branches except backwards with an unfilled
4709 strcpy (buf
, "vextrs,");
4711 strcpy (buf
, "bvb,");
4712 if ((which
== 0 && negated
)
4713 || (which
== 1 && ! negated
))
4718 strcat (buf
, " %0,1,0");
4719 else if (nullify
&& negated
)
4720 strcat (buf
, ",n %0,%3");
4721 else if (nullify
&& ! negated
)
4722 strcat (buf
, ",n %0,%2");
4723 else if (! nullify
&& negated
)
4724 strcat (buf
, "%0,%3");
4725 else if (! nullify
&& ! negated
)
4726 strcat (buf
, " %0,%2");
4729 /* All long conditionals. Note an short backward branch with an
4730 unfilled delay slot is treated just like a long backward branch
4731 with an unfilled delay slot. */
4733 /* Handle weird backwards branch with a filled delay slot
4734 with is nullified. */
4735 if (dbr_sequence_length () != 0
4736 && ! forward_branch_p (insn
)
4739 strcpy (buf
, "bvb,");
4740 if ((which
== 0 && negated
)
4741 || (which
== 1 && ! negated
))
4746 strcat (buf
, ",n %0,.+12\n\tbl %3,0");
4748 strcat (buf
, ",n %0,.+12\n\tbl %2,0");
4750 /* Handle short backwards branch with an unfilled delay slot.
4751 Using a bb;nop rather than extrs;bl saves 1 cycle for both
4752 taken and untaken branches. */
4753 else if (dbr_sequence_length () == 0
4754 && ! forward_branch_p (insn
)
4756 && VAL_14_BITS_P (insn_addresses
[INSN_UID (JUMP_LABEL (insn
))]
4757 - insn_addresses
[INSN_UID (insn
)] - 8))
4759 strcpy (buf
, "bvb,");
4760 if ((which
== 0 && negated
)
4761 || (which
== 1 && ! negated
))
4766 strcat (buf
, " %0,%3%#");
4768 strcat (buf
, " %0,%2%#");
4772 strcpy (buf
, "vextrs,");
4773 if ((which
== 0 && negated
)
4774 || (which
== 1 && ! negated
))
4778 if (nullify
&& negated
)
4779 strcat (buf
, " %0,1,0\n\tbl,n %3,0");
4780 else if (nullify
&& ! negated
)
4781 strcat (buf
, " %0,1,0\n\tbl,n %2,0");
4783 strcat (buf
, " %0,1,0\n\tbl %3,0");
4785 strcat (buf
, " %0,1,0\n\tbl %2,0");
4795 /* Return the output template for emitting a dbra type insn.
4797 Note it may perform some output operations on its own before
4798 returning the final output string. */
4800 output_dbra (operands
, insn
, which_alternative
)
4803 int which_alternative
;
4806 /* A conditional branch to the following instruction (eg the delay slot) is
4807 asking for a disaster. Be prepared! */
4809 if (next_active_insn (JUMP_LABEL (insn
)) == next_active_insn (insn
))
4811 if (which_alternative
== 0)
4812 return "ldo %1(%0),%0";
4813 else if (which_alternative
== 1)
4815 output_asm_insn ("fstws %0,-16(0,%%r30)",operands
);
4816 output_asm_insn ("ldw -16(0,%%r30),%4",operands
);
4817 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(0,%%r30)", operands
);
4818 return "fldws -16(0,%%r30),%0";
4822 output_asm_insn ("ldw %0,%4", operands
);
4823 return "ldo %1(%4),%4\n\tstw %4,%0";
4827 if (which_alternative
== 0)
4829 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
4830 int length
= get_attr_length (insn
);
4832 /* If this is a long branch with its delay slot unfilled, set `nullify'
4833 as it can nullify the delay slot and save a nop. */
4834 if (length
== 8 && dbr_sequence_length () == 0)
4837 /* If this is a short forward conditional branch which did not get
4838 its delay slot filled, the delay slot can still be nullified. */
4839 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
4840 nullify
= forward_branch_p (insn
);
4842 /* Handle short versions first. */
4843 if (length
== 4 && nullify
)
4844 return "addib,%C2,n %1,%0,%3";
4845 else if (length
== 4 && ! nullify
)
4846 return "addib,%C2 %1,%0,%3";
4847 else if (length
== 8)
4849 /* Handle weird backwards branch with a fulled delay slot
4850 which is nullified. */
4851 if (dbr_sequence_length () != 0
4852 && ! forward_branch_p (insn
)
4854 return "addib,%N2,n %1,%0,.+12\n\tbl %3,0";
4855 /* Handle short backwards branch with an unfilled delay slot.
4856 Using a addb;nop rather than addi;bl saves 1 cycle for both
4857 taken and untaken branches. */
4858 else if (dbr_sequence_length () == 0
4859 && ! forward_branch_p (insn
)
4861 && VAL_14_BITS_P (insn_addresses
[INSN_UID (JUMP_LABEL (insn
))]
4862 - insn_addresses
[INSN_UID (insn
)] - 8))
4863 return "addib,%C2 %1,%0,%3%#";
4865 /* Handle normal cases. */
4867 return "addi,%N2 %1,%0,%0\n\tbl,n %3,0";
4869 return "addi,%N2 %1,%0,%0\n\tbl %3,0";
4874 /* Deal with gross reload from FP register case. */
4875 else if (which_alternative
== 1)
4877 /* Move loop counter from FP register to MEM then into a GR,
4878 increment the GR, store the GR into MEM, and finally reload
4879 the FP register from MEM from within the branch's delay slot. */
4880 output_asm_insn ("fstws %0,-16(0,%%r30)\n\tldw -16(0,%%r30),%4",operands
);
4881 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(0,%%r30)", operands
);
4882 if (get_attr_length (insn
) == 24)
4883 return "comb,%S2 0,%4,%3\n\tfldws -16(0,%%r30),%0";
4885 return "comclr,%B2 0,%4,0\n\tbl %3,0\n\tfldws -16(0,%%r30),%0";
4887 /* Deal with gross reload from memory case. */
4890 /* Reload loop counter from memory, the store back to memory
4891 happens in the branch's delay slot. */
4892 output_asm_insn ("ldw %0,%4", operands
);
4893 if (get_attr_length (insn
) == 12)
4894 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
4896 return "addi,%N2 %1,%4,%4\n\tbl %3,0\n\tstw %4,%0";
4900 /* Return the output template for emitting a dbra type insn.
4902 Note it may perform some output operations on its own before
4903 returning the final output string. */
4905 output_movb (operands
, insn
, which_alternative
, reverse_comparison
)
4908 int which_alternative
;
4909 int reverse_comparison
;
4912 /* A conditional branch to the following instruction (eg the delay slot) is
4913 asking for a disaster. Be prepared! */
4915 if (next_active_insn (JUMP_LABEL (insn
)) == next_active_insn (insn
))
4917 if (which_alternative
== 0)
4918 return "copy %1,%0";
4919 else if (which_alternative
== 1)
4921 output_asm_insn ("stw %1,-16(0,%%r30)",operands
);
4922 return "fldws -16(0,%%r30),%0";
4924 else if (which_alternative
== 2)
4930 /* Support the second variant. */
4931 if (reverse_comparison
)
4932 PUT_CODE (operands
[2], reverse_condition (GET_CODE (operands
[2])));
4934 if (which_alternative
== 0)
4936 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
4937 int length
= get_attr_length (insn
);
4939 /* If this is a long branch with its delay slot unfilled, set `nullify'
4940 as it can nullify the delay slot and save a nop. */
4941 if (length
== 8 && dbr_sequence_length () == 0)
4944 /* If this is a short forward conditional branch which did not get
4945 its delay slot filled, the delay slot can still be nullified. */
4946 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
4947 nullify
= forward_branch_p (insn
);
4949 /* Handle short versions first. */
4950 if (length
== 4 && nullify
)
4951 return "movb,%C2,n %1,%0,%3";
4952 else if (length
== 4 && ! nullify
)
4953 return "movb,%C2 %1,%0,%3";
4954 else if (length
== 8)
4956 /* Handle weird backwards branch with a filled delay slot
4957 which is nullified. */
4958 if (dbr_sequence_length () != 0
4959 && ! forward_branch_p (insn
)
4961 return "movb,%N2,n %1,%0,.+12\n\tbl %3,0";
4963 /* Handle short backwards branch with an unfilled delay slot.
4964 Using a movb;nop rather than or;bl saves 1 cycle for both
4965 taken and untaken branches. */
4966 else if (dbr_sequence_length () == 0
4967 && ! forward_branch_p (insn
)
4969 && VAL_14_BITS_P (insn_addresses
[INSN_UID (JUMP_LABEL (insn
))]
4970 - insn_addresses
[INSN_UID (insn
)] - 8))
4971 return "movb,%C2 %1,%0,%3%#";
4972 /* Handle normal cases. */
4974 return "or,%N2 %1,%%r0,%0\n\tbl,n %3,0";
4976 return "or,%N2 %1,%%r0,%0\n\tbl %3,0";
4981 /* Deal with gross reload from FP register case. */
4982 else if (which_alternative
== 1)
4984 /* Move loop counter from FP register to MEM then into a GR,
4985 increment the GR, store the GR into MEM, and finally reload
4986 the FP register from MEM from within the branch's delay slot. */
4987 output_asm_insn ("stw %1,-16(0,%%r30)",operands
);
4988 if (get_attr_length (insn
) == 12)
4989 return "comb,%S2 0,%1,%3\n\tfldws -16(0,%%r30),%0";
4991 return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tfldws -16(0,%%r30),%0";
4993 /* Deal with gross reload from memory case. */
4994 else if (which_alternative
== 2)
4996 /* Reload loop counter from memory, the store back to memory
4997 happens in the branch's delay slot. */
4998 if (get_attr_length (insn
) == 8)
4999 return "comb,%S2 0,%1,%3\n\tstw %1,%0";
5001 return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tstw %1,%0";
5003 /* Handle SAR as a destination. */
5006 if (get_attr_length (insn
) == 8)
5007 return "comb,%S2 0,%1,%3\n\tmtsar %r1";
5009 return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tmtsar %r1";
5014 /* INSN is a millicode call. It may have an unconditional jump in its delay
5017 CALL_DEST is the routine we are calling. */
5020 output_millicode_call (insn
, call_dest
)
5028 /* Handle common case -- empty delay slot or no jump in the delay slot,
5029 and we're sure that the branch will reach the beginning of the $CODE$
5031 if ((dbr_sequence_length () == 0
5032 && (get_attr_length (insn
) == 8 || get_attr_length (insn
) == 28))
5033 || (dbr_sequence_length () != 0
5034 && GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
5035 && get_attr_length (insn
) == 4))
5037 xoperands
[0] = call_dest
;
5038 output_asm_insn ("bl %0,%%r31%#", xoperands
);
5042 /* This call may not reach the beginning of the $CODE$ subspace. */
5043 if (get_attr_length (insn
) > 4)
5045 int delay_insn_deleted
= 0;
5049 /* We need to emit an inline long-call branch. */
5050 if (dbr_sequence_length () != 0
5051 && GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
)
5053 /* A non-jump insn in the delay slot. By definition we can
5054 emit this insn before the call. */
5055 final_scan_insn (NEXT_INSN (insn
), asm_out_file
, optimize
, 0, 0);
5057 /* Now delete the delay insn. */
5058 PUT_CODE (NEXT_INSN (insn
), NOTE
);
5059 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
5060 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
5061 delay_insn_deleted
= 1;
5064 /* If we're allowed to use be/ble instructions, then this is the
5065 best sequence to use for a long millicode call. */
5066 if (TARGET_NO_SPACE_REGS
|| TARGET_FAST_INDIRECT_CALLS
5067 || ! (flag_pic
|| TARGET_PORTABLE_RUNTIME
))
5069 xoperands
[0] = call_dest
;
5070 output_asm_insn ("ldil L%%%0,%%r31", xoperands
);
5071 output_asm_insn ("ble R%%%0(%%sr4,%%r31)", xoperands
);
5072 output_asm_insn ("nop", xoperands
);
5074 /* Pure portable runtime doesn't allow be/ble; we also don't have
5075 PIC support int he assembler/linker, so this sequence is needed. */
5076 else if (TARGET_PORTABLE_RUNTIME
)
5078 xoperands
[0] = call_dest
;
5079 /* Get the address of our target into %r29. */
5080 output_asm_insn ("ldil L%%%0,%%r29", xoperands
);
5081 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands
);
5083 /* Get our return address into %r31. */
5084 output_asm_insn ("blr 0,%%r31", xoperands
);
5086 /* Jump to our target address in %r29. */
5087 output_asm_insn ("bv,n 0(%%r29)", xoperands
);
5089 /* Empty delay slot. Note this insn gets fetched twice and
5090 executed once. To be safe we use a nop. */
5091 output_asm_insn ("nop", xoperands
);
5094 /* PIC long millicode call sequence. */
5097 xoperands
[0] = call_dest
;
5098 xoperands
[1] = gen_label_rtx ();
5099 /* Get our address + 8 into %r1. */
5100 output_asm_insn ("bl .+8,%%r1", xoperands
);
5102 /* Add %r1 to the offset of our target from the next insn. */
5103 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands
);
5104 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
5105 CODE_LABEL_NUMBER (xoperands
[1]));
5106 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands
);
5108 /* Get the return address into %r31. */
5109 output_asm_insn ("blr 0,%%r31", xoperands
);
5111 /* Branch to our target which is in %r1. */
5112 output_asm_insn ("bv,n 0(%%r1)", xoperands
);
5114 /* Empty delay slot. Note this insn gets fetched twice and
5115 executed once. To be safe we use a nop. */
5116 output_asm_insn ("nop", xoperands
);
5119 /* If we had a jump in the call's delay slot, output it now. */
5120 if (dbr_sequence_length () != 0
5121 && !delay_insn_deleted
)
5123 xoperands
[0] = XEXP (PATTERN (NEXT_INSN (insn
)), 1);
5124 output_asm_insn ("b,n %0", xoperands
);
5126 /* Now delete the delay insn. */
5127 PUT_CODE (NEXT_INSN (insn
), NOTE
);
5128 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
5129 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
5134 /* This call has an unconditional jump in its delay slot and the
5135 call is known to reach its target or the beginning of the current
5138 /* Use the containing sequence insn's address. */
5139 seq_insn
= NEXT_INSN (PREV_INSN (XVECEXP (final_sequence
, 0, 0)));
5141 distance
= insn_addresses
[INSN_UID (JUMP_LABEL (NEXT_INSN (insn
)))]
5142 - insn_addresses
[INSN_UID (seq_insn
)] - 8;
5144 /* If the branch was too far away, emit a normal call followed
5145 by a nop, followed by the unconditional branch.
5147 If the branch is close, then adjust %r2 from within the
5148 call's delay slot. */
5150 xoperands
[0] = call_dest
;
5151 xoperands
[1] = XEXP (PATTERN (NEXT_INSN (insn
)), 1);
5152 if (! VAL_14_BITS_P (distance
))
5153 output_asm_insn ("bl %0,%%r31\n\tnop\n\tbl,n %1,%%r0", xoperands
);
5156 xoperands
[3] = gen_label_rtx ();
5157 output_asm_insn ("\n\tbl %0,%%r31\n\tldo %1-%3(%%r31),%%r31", xoperands
);
5158 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
5159 CODE_LABEL_NUMBER (xoperands
[3]));
5162 /* Delete the jump. */
5163 PUT_CODE (NEXT_INSN (insn
), NOTE
);
5164 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
5165 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
5169 extern struct obstack permanent_obstack
;
5170 extern struct obstack
*saveable_obstack
;
5171 extern struct obstack
*rtl_obstack
;
5172 extern struct obstack
*current_obstack
;
5174 /* INSN is either a function call. It may have an unconditional jump
5177 CALL_DEST is the routine we are calling. */
5180 output_call (insn
, call_dest
)
5188 /* Handle common case -- empty delay slot or no jump in the delay slot,
5189 and we're sure that the branch will reach the beginning of the $CODE$
5191 if ((dbr_sequence_length () == 0
5192 && get_attr_length (insn
) == 8)
5193 || (dbr_sequence_length () != 0
5194 && GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
5195 && get_attr_length (insn
) == 4))
5197 xoperands
[0] = call_dest
;
5198 output_asm_insn ("bl %0,%%r2%#", xoperands
);
5202 /* This call may not reach the beginning of the $CODE$ subspace. */
5203 if (get_attr_length (insn
) > 8)
5205 int delay_insn_deleted
= 0;
5209 /* We need to emit an inline long-call branch. Furthermore,
5210 because we're changing a named function call into an indirect
5211 function call well after the parameters have been set up, we
5212 need to make sure any FP args appear in both the integer
5213 and FP registers. Also, we need move any delay slot insn
5214 out of the delay slot. And finally, we can't rely on the linker
5215 being able to fix the call to $$dyncall! -- Yuk!. */
5216 if (dbr_sequence_length () != 0
5217 && GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
)
5219 /* A non-jump insn in the delay slot. By definition we can
5220 emit this insn before the call (and in fact before argument
5222 final_scan_insn (NEXT_INSN (insn
), asm_out_file
, optimize
, 0, 0);
5224 /* Now delete the delay insn. */
5225 PUT_CODE (NEXT_INSN (insn
), NOTE
);
5226 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
5227 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
5228 delay_insn_deleted
= 1;
5231 /* Now copy any FP arguments into integer registers. */
5232 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
5234 int arg_mode
, regno
;
5235 rtx use
= XEXP (link
, 0);
5236 if (! (GET_CODE (use
) == USE
5237 && GET_CODE (XEXP (use
, 0)) == REG
5238 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use
, 0)))))
5241 arg_mode
= GET_MODE (XEXP (use
, 0));
5242 regno
= REGNO (XEXP (use
, 0));
5243 /* Is it a floating point register? */
5244 if (regno
>= 32 && regno
<= 39)
5246 /* Copy from the FP register into an integer register
5248 if (arg_mode
== SFmode
)
5250 xoperands
[0] = XEXP (use
, 0);
5251 xoperands
[1] = gen_rtx (REG
, SImode
, 26 - (regno
- 32) / 2);
5252 output_asm_insn ("fstws %0,-16(%%sr0,%%r30)", xoperands
);
5253 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands
);
5257 xoperands
[0] = XEXP (use
, 0);
5258 xoperands
[1] = gen_rtx (REG
, DImode
, 25 - (regno
- 34) / 2);
5259 output_asm_insn ("fstds %0,-16(%%sr0,%%r30)", xoperands
);
5260 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands
);
5261 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands
);
5266 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
5267 we don't have any direct calls in that case. */
5270 char *name
= XSTR (call_dest
, 0);
5272 /* See if we have already put this function on the list
5273 of deferred plabels. This list is generally small,
5274 so a liner search is not too ugly. If it proves too
5275 slow replace it with something faster. */
5276 for (i
= 0; i
< n_deferred_plabels
; i
++)
5277 if (strcmp (name
, deferred_plabels
[i
].name
) == 0)
5280 /* If the deferred plabel list is empty, or this entry was
5281 not found on the list, create a new entry on the list. */
5282 if (deferred_plabels
== NULL
|| i
== n_deferred_plabels
)
5284 struct obstack
*ambient_obstack
= current_obstack
;
5285 struct obstack
*ambient_rtl_obstack
= rtl_obstack
;
5288 /* Any RTL we create here needs to live until the end of
5289 the compilation unit and therefore must live on the
5290 permanent obstack. */
5291 current_obstack
= &permanent_obstack
;
5292 rtl_obstack
= &permanent_obstack
;
5294 if (deferred_plabels
== 0)
5295 deferred_plabels
= (struct deferred_plabel
*)
5296 xmalloc (1 * sizeof (struct deferred_plabel
));
5298 deferred_plabels
= (struct deferred_plabel
*)
5299 xrealloc (deferred_plabels
,
5300 ((n_deferred_plabels
+ 1)
5301 * sizeof (struct deferred_plabel
)));
5303 i
= n_deferred_plabels
++;
5304 deferred_plabels
[i
].internal_label
= gen_label_rtx ();
5305 deferred_plabels
[i
].name
= obstack_alloc (&permanent_obstack
,
5307 strcpy (deferred_plabels
[i
].name
, name
);
5309 /* Switch back to normal obstack allocation. */
5310 current_obstack
= ambient_obstack
;
5311 rtl_obstack
= ambient_rtl_obstack
;
5313 /* Gross. We have just implicitly taken the address of this
5314 function, mark it as such. */
5315 STRIP_NAME_ENCODING (real_name
, name
);
5316 TREE_SYMBOL_REFERENCED (get_identifier (real_name
)) = 1;
5319 /* We have to load the address of the function using a procedure
5320 label (plabel). Inline plabels can lose for PIC and other
5321 cases, so avoid them by creating a 32bit plabel in the data
5325 xoperands
[0] = deferred_plabels
[i
].internal_label
;
5326 xoperands
[1] = gen_label_rtx ();
5328 output_asm_insn ("addil LT%%%0,%%r19", xoperands
);
5329 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands
);
5330 output_asm_insn ("ldw 0(0,%%r22),%%r22", xoperands
);
5332 /* Get our address + 8 into %r1. */
5333 output_asm_insn ("bl .+8,%%r1", xoperands
);
5335 /* Add %r1 to the offset of dyncall from the next insn. */
5336 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands
);
5337 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
5338 CODE_LABEL_NUMBER (xoperands
[1]));
5339 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands
);
5341 /* Get the return address into %r31. */
5342 output_asm_insn ("blr 0,%%r31", xoperands
);
5344 /* Branch to our target which is in %r1. */
5345 output_asm_insn ("bv 0(%%r1)", xoperands
);
5347 /* Copy the return address into %r2 also. */
5348 output_asm_insn ("copy %%r31,%%r2", xoperands
);
5352 xoperands
[0] = deferred_plabels
[i
].internal_label
;
5354 /* Get the address of our target into %r22. */
5355 output_asm_insn ("addil LR%%%0-$global$,%%r27", xoperands
);
5356 output_asm_insn ("ldw RR%%%0-$global$(%%r1),%%r22", xoperands
);
5358 /* Get the high part of the address of $dyncall into %r2, then
5359 add in the low part in the branch instruction. */
5360 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands
);
5361 output_asm_insn ("ble R%%$$dyncall(%%sr4,%%r2)", xoperands
);
5363 /* Copy the return pointer into both %r31 and %r2. */
5364 output_asm_insn ("copy %%r31,%%r2", xoperands
);
5368 /* If we had a jump in the call's delay slot, output it now. */
5369 if (dbr_sequence_length () != 0
5370 && !delay_insn_deleted
)
5372 xoperands
[0] = XEXP (PATTERN (NEXT_INSN (insn
)), 1);
5373 output_asm_insn ("b,n %0", xoperands
);
5375 /* Now delete the delay insn. */
5376 PUT_CODE (NEXT_INSN (insn
), NOTE
);
5377 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
5378 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
5383 /* This call has an unconditional jump in its delay slot and the
5384 call is known to reach its target or the beginning of the current
5387 /* Use the containing sequence insn's address. */
5388 seq_insn
= NEXT_INSN (PREV_INSN (XVECEXP (final_sequence
, 0, 0)));
5390 distance
= insn_addresses
[INSN_UID (JUMP_LABEL (NEXT_INSN (insn
)))]
5391 - insn_addresses
[INSN_UID (seq_insn
)] - 8;
5393 /* If the branch was too far away, emit a normal call followed
5394 by a nop, followed by the unconditional branch.
5396 If the branch is close, then adjust %r2 from within the
5397 call's delay slot. */
5399 xoperands
[0] = call_dest
;
5400 xoperands
[1] = XEXP (PATTERN (NEXT_INSN (insn
)), 1);
5401 if (! VAL_14_BITS_P (distance
))
5402 output_asm_insn ("bl %0,%%r2\n\tnop\n\tbl,n %1,%%r0", xoperands
);
5405 xoperands
[3] = gen_label_rtx ();
5406 output_asm_insn ("\n\tbl %0,%%r2\n\tldo %1-%3(%%r2),%%r2", xoperands
);
5407 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
5408 CODE_LABEL_NUMBER (xoperands
[3]));
5411 /* Delete the jump. */
5412 PUT_CODE (NEXT_INSN (insn
), NOTE
);
5413 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
5414 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
5418 /* In HPUX 8.0's shared library scheme, special relocations are needed
5419 for function labels if they might be passed to a function
5420 in a shared library (because shared libraries don't live in code
5421 space), and special magic is needed to construct their address.
5423 For reasons too disgusting to describe storage for the new name
5424 is allocated either on the saveable_obstack (released at function
5425 exit) or on the permanent_obstack for things that can never change
5426 (libcall names for example). */
5429 hppa_encode_label (sym
, permanent
)
5433 char *str
= XSTR (sym
, 0);
5434 int len
= strlen (str
);
5437 newstr
= obstack_alloc ((permanent
? &permanent_obstack
: saveable_obstack
),
5442 strcpy (newstr
+ 1, str
);
5444 XSTR (sym
,0) = newstr
;
5448 function_label_operand (op
, mode
)
5450 enum machine_mode mode
;
5452 return GET_CODE (op
) == SYMBOL_REF
&& FUNCTION_NAME_P (XSTR (op
, 0));
5455 /* Returns 1 if OP is a function label involved in a simple addition
5456 with a constant. Used to keep certain patterns from matching
5457 during instruction combination. */
5459 is_function_label_plus_const (op
)
5462 /* Strip off any CONST. */
5463 if (GET_CODE (op
) == CONST
)
5466 return (GET_CODE (op
) == PLUS
5467 && function_label_operand (XEXP (op
, 0), Pmode
)
5468 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
5471 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
5472 use in fmpyadd instructions. */
5474 fmpyaddoperands (operands
)
5477 enum machine_mode mode
= GET_MODE (operands
[0]);
5479 /* Must be a floating point mode. */
5480 if (mode
!= SFmode
&& mode
!= DFmode
)
5483 /* All modes must be the same. */
5484 if (! (mode
== GET_MODE (operands
[1])
5485 && mode
== GET_MODE (operands
[2])
5486 && mode
== GET_MODE (operands
[3])
5487 && mode
== GET_MODE (operands
[4])
5488 && mode
== GET_MODE (operands
[5])))
5491 /* All operands must be registers. */
5492 if (! (GET_CODE (operands
[1]) == REG
5493 && GET_CODE (operands
[2]) == REG
5494 && GET_CODE (operands
[3]) == REG
5495 && GET_CODE (operands
[4]) == REG
5496 && GET_CODE (operands
[5]) == REG
))
5499 /* Only 2 real operands to the addition. One of the input operands must
5500 be the same as the output operand. */
5501 if (! rtx_equal_p (operands
[3], operands
[4])
5502 && ! rtx_equal_p (operands
[3], operands
[5]))
5505 /* Inout operand of add can not conflict with any operands from multiply. */
5506 if (rtx_equal_p (operands
[3], operands
[0])
5507 || rtx_equal_p (operands
[3], operands
[1])
5508 || rtx_equal_p (operands
[3], operands
[2]))
5511 /* multiply can not feed into addition operands. */
5512 if (rtx_equal_p (operands
[4], operands
[0])
5513 || rtx_equal_p (operands
[5], operands
[0]))
5516 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
5518 && (REGNO (operands
[0]) < 57
5519 || REGNO (operands
[1]) < 57
5520 || REGNO (operands
[2]) < 57
5521 || REGNO (operands
[3]) < 57
5522 || REGNO (operands
[4]) < 57
5523 || REGNO (operands
[5]) < 57))
5526 /* Passed. Operands are suitable for fmpyadd. */
5530 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
5531 use in fmpysub instructions. */
5533 fmpysuboperands (operands
)
5536 enum machine_mode mode
= GET_MODE (operands
[0]);
5538 /* Must be a floating point mode. */
5539 if (mode
!= SFmode
&& mode
!= DFmode
)
5542 /* All modes must be the same. */
5543 if (! (mode
== GET_MODE (operands
[1])
5544 && mode
== GET_MODE (operands
[2])
5545 && mode
== GET_MODE (operands
[3])
5546 && mode
== GET_MODE (operands
[4])
5547 && mode
== GET_MODE (operands
[5])))
5550 /* All operands must be registers. */
5551 if (! (GET_CODE (operands
[1]) == REG
5552 && GET_CODE (operands
[2]) == REG
5553 && GET_CODE (operands
[3]) == REG
5554 && GET_CODE (operands
[4]) == REG
5555 && GET_CODE (operands
[5]) == REG
))
5558 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
5559 operation, so operands[4] must be the same as operand[3]. */
5560 if (! rtx_equal_p (operands
[3], operands
[4]))
5563 /* multiply can not feed into subtraction. */
5564 if (rtx_equal_p (operands
[5], operands
[0]))
5567 /* Inout operand of sub can not conflict with any operands from multiply. */
5568 if (rtx_equal_p (operands
[3], operands
[0])
5569 || rtx_equal_p (operands
[3], operands
[1])
5570 || rtx_equal_p (operands
[3], operands
[2]))
5573 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
5575 && (REGNO (operands
[0]) < 57
5576 || REGNO (operands
[1]) < 57
5577 || REGNO (operands
[2]) < 57
5578 || REGNO (operands
[3]) < 57
5579 || REGNO (operands
[4]) < 57
5580 || REGNO (operands
[5]) < 57))
5583 /* Passed. Operands are suitable for fmpysub. */
5588 plus_xor_ior_operator (op
, mode
)
5590 enum machine_mode mode
;
5592 return (GET_CODE (op
) == PLUS
|| GET_CODE (op
) == XOR
5593 || GET_CODE (op
) == IOR
);
5596 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
5597 constants for shadd instructions. */
5599 shadd_constant_p (val
)
5602 if (val
== 2 || val
== 4 || val
== 8)
5608 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
5609 the valid constant for shadd instructions. */
5611 shadd_operand (op
, mode
)
5613 enum machine_mode mode
;
5615 return (GET_CODE (op
) == CONST_INT
&& shadd_constant_p (INTVAL (op
)));
5618 /* Return 1 if OP is valid as a base register in a reg + reg address. */
5621 basereg_operand (op
, mode
)
5623 enum machine_mode mode
;
5625 /* cse will create some unscaled indexed addresses, however; it
5626 generally isn't a win on the PA, so avoid creating unscaled
5627 indexed addresses until after cse is finished. */
5628 if (!cse_not_expected
)
5631 /* Once reload has started everything is considered valid. Reload should
5632 only create indexed addresses using the stack/frame pointer, and any
5633 others were checked for validity when created by the combine pass.
5635 Also allow any register when TARGET_NO_SPACE_REGS is in effect since
5636 we don't have to worry about the braindamaged implicit space register
5637 selection using the basereg only (rather than effective address)
5638 screwing us over. */
5639 if (TARGET_NO_SPACE_REGS
|| reload_in_progress
|| reload_completed
)
5640 return (GET_CODE (op
) == REG
);
5642 /* Stack is always OK for indexing. */
5643 if (op
== stack_pointer_rtx
)
5646 /* While it's always safe to index off the frame pointer, it's not
5647 always profitable, particularly when the frame pointer is being
5649 if (! flag_omit_frame_pointer
&& op
== frame_pointer_rtx
)
5652 /* The only other valid OPs are pseudo registers with
5653 REGNO_POINTER_FLAG set. */
5654 if (GET_CODE (op
) != REG
5655 || REGNO (op
) < FIRST_PSEUDO_REGISTER
5656 || ! register_operand (op
, mode
))
5659 return REGNO_POINTER_FLAG (REGNO (op
));
5662 /* Return 1 if this operand is anything other than a hard register. */
5665 non_hard_reg_operand (op
, mode
)
5667 enum machine_mode mode
;
5669 return ! (GET_CODE (op
) == REG
&& REGNO (op
) < FIRST_PSEUDO_REGISTER
);
5672 /* Return 1 if INSN branches forward. Should be using insn_addresses
5673 to avoid walking through all the insns... */
5675 forward_branch_p (insn
)
5678 rtx label
= JUMP_LABEL (insn
);
5685 insn
= NEXT_INSN (insn
);
5688 return (insn
== label
);
5691 /* Return 1 if OP is an equality comparison, else return 0. */
5693 eq_neq_comparison_operator (op
, mode
)
5695 enum machine_mode mode
;
5697 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
5700 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
5702 movb_comparison_operator (op
, mode
)
5704 enum machine_mode mode
;
5706 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
5707 || GET_CODE (op
) == LT
|| GET_CODE (op
) == GE
);
5710 /* Return 1 if INSN is in the delay slot of a call instruction. */
5712 jump_in_call_delay (insn
)
5716 if (GET_CODE (insn
) != JUMP_INSN
)
5719 if (PREV_INSN (insn
)
5720 && PREV_INSN (PREV_INSN (insn
))
5721 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn
)))) == INSN
)
5723 rtx test_insn
= next_active_insn (PREV_INSN (PREV_INSN (insn
)));
5725 return (GET_CODE (PATTERN (test_insn
)) == SEQUENCE
5726 && XVECEXP (PATTERN (test_insn
), 0, 1) == insn
);
5733 /* Output an unconditional move and branch insn. */
5736 output_parallel_movb (operands
, length
)
5740 /* These are the cases in which we win. */
5742 return "mov%I1b,tr %1,%0,%2";
5744 /* None of these cases wins, but they don't lose either. */
5745 if (dbr_sequence_length () == 0)
5747 /* Nothing in the delay slot, fake it by putting the combined
5748 insn (the copy or add) in the delay slot of a bl. */
5749 if (GET_CODE (operands
[1]) == CONST_INT
)
5750 return "bl %2,0\n\tldi %1,%0";
5752 return "bl %2,0\n\tcopy %1,%0";
5756 /* Something in the delay slot, but we've got a long branch. */
5757 if (GET_CODE (operands
[1]) == CONST_INT
)
5758 return "ldi %1,%0\n\tbl %2,0";
5760 return "copy %1,%0\n\tbl %2,0";
5764 /* Output an unconditional add and branch insn. */
5767 output_parallel_addb (operands
, length
)
5771 /* To make life easy we want operand0 to be the shared input/output
5772 operand and operand1 to be the readonly operand. */
5773 if (operands
[0] == operands
[1])
5774 operands
[1] = operands
[2];
5776 /* These are the cases in which we win. */
5778 return "add%I1b,tr %1,%0,%3";
5780 /* None of these cases win, but they don't lose either. */
5781 if (dbr_sequence_length () == 0)
5783 /* Nothing in the delay slot, fake it by putting the combined
5784 insn (the copy or add) in the delay slot of a bl. */
5785 return "bl %3,0\n\tadd%I1 %1,%0,%0";
5789 /* Something in the delay slot, but we've got a long branch. */
5790 return "add%I1 %1,%0,%0\n\tbl %3,0";
5794 /* Return nonzero if INSN (a jump insn) immediately follows a call to
5795 a named function. This is used to discourage creating parallel movb/addb
5796 insns since a jump which immediately follows a call can execute in the
5797 delay slot of the call.
5799 It is also used to avoid filling the delay slot of a jump which
5800 immediately follows a call since the jump can usually be eliminated
5801 completely by modifying RP in the delay slot of the call. */
5803 following_call (insn
)
5806 /* Find the previous real insn, skipping NOTEs. */
5807 insn
= PREV_INSN (insn
);
5808 while (insn
&& GET_CODE (insn
) == NOTE
)
5809 insn
= PREV_INSN (insn
);
5811 /* Check for CALL_INSNs and millicode calls. */
5813 && ((GET_CODE (insn
) == CALL_INSN
5814 && get_attr_type (insn
) != TYPE_DYNCALL
)
5815 || (GET_CODE (insn
) == INSN
5816 && GET_CODE (PATTERN (insn
)) != SEQUENCE
5817 && GET_CODE (PATTERN (insn
)) != USE
5818 && GET_CODE (PATTERN (insn
)) != CLOBBER
5819 && get_attr_type (insn
) == TYPE_MILLI
)))
5825 /* Restore any INSN_CODEs for insns with unscaled indexed addresses since
5826 the INSN_CODE might be clobberd by rerecognition triggered by reorg. */
5829 restore_unscaled_index_insn_codes (insns
)
5834 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
5836 if (INSN_UID (insn
) < max_unscaled_index_insn_codes_uid
5837 && unscaled_index_insn_codes
[INSN_UID (insn
)] != -1)
5838 INSN_CODE (insn
) = unscaled_index_insn_codes
[INSN_UID (insn
)];
5842 /* Severe braindamage:
5844 On the PA, address computations within MEM expressions are not
5845 commutative because of the implicit space register selection
5846 from the base register (instead of the entire effective address).
5848 Because of this mis-feature we have to know which register in a reg+reg
5849 address is the base and which is the index.
5851 Before reload, the base can be identified by REGNO_POINTER_FLAG. We use
5852 this to force base + index addresses to match a different insn than
5853 index + base addresses.
5855 We assume that no pass during or after reload creates new unscaled indexed
5856 addresses, so any unscaled indexed address we find after reload must have
5857 at one time been recognized a base + index or index + base and we accept
5858 any register as a base register.
5860 This scheme assumes that no pass during/after reload will rerecognize an
5861 insn with an unscaled indexed address. This failed due to a reorg call
5862 to rerecognize certain insns.
5864 So, we record if an insn uses an unscaled indexed address and which
5865 register is the base (via recording of the INSN_CODE for such insns).
5867 Just before we output code for the function, we make sure all the insns
5868 using unscaled indexed addresses have the same INSN_CODE as they did
5869 immediately before delay slot scheduling.
5871 This is extremely gross. Long term, I'd like to be able to look at
5872 REG_POINTER_FLAG to handle these kinds of problems. */
5875 record_unscaled_index_insn_codes (insns
)
5880 max_unscaled_index_insn_codes_uid
= get_max_uid ();
5881 unscaled_index_insn_codes
5882 = (int *)xmalloc (max_unscaled_index_insn_codes_uid
* sizeof (int));
5883 memset (unscaled_index_insn_codes
, -1,
5884 max_unscaled_index_insn_codes_uid
* sizeof (int));
5886 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
5888 rtx set
= single_set (insn
);
5891 /* Ignore anything that isn't a normal SET. */
5892 if (set
== NULL_RTX
)
5895 /* No insns can have more than one MEM. */
5896 if (GET_CODE (SET_SRC (set
)) == MEM
)
5897 mem
= SET_SRC (set
);
5899 if (GET_CODE (SET_DEST (set
)) == MEM
)
5900 mem
= SET_DEST (set
);
5902 /* If neither operand is a mem, then there's nothing to do. */
5903 if (mem
== NULL_RTX
)
5906 if (GET_CODE (XEXP (mem
, 0)) != PLUS
)
5909 /* If both are REGs (or SUBREGs), then record the insn code for
5911 if (REG_P (XEXP (XEXP (mem
, 0), 0)) && REG_P (XEXP (XEXP (mem
, 0), 1)))
5912 unscaled_index_insn_codes
[INSN_UID (insn
)] = INSN_CODE (insn
);
5916 /* We use this hook to perform a PA specific optimization which is difficult
5917 to do in earlier passes.
5919 We want the delay slots of branches within jump tables to be filled.
5920 None of the compiler passes at the moment even has the notion that a
5921 PA jump table doesn't contain addresses, but instead contains actual
5924 Because we actually jump into the table, the addresses of each entry
5925 must stay constant in relation to the beginning of the table (which
5926 itself must stay constant relative to the instruction to jump into
5927 it). I don't believe we can guarantee earlier passes of the compiler
5928 will adhere to those rules.
5930 So, late in the compilation process we find all the jump tables, and
5931 expand them into real code -- eg each entry in the jump table vector
5932 will get an appropriate label followed by a jump to the final target.
5934 Reorg and the final jump pass can then optimize these branches and
5935 fill their delay slots. We end up with smaller, more efficient code.
5937 The jump instructions within the table are special; we must be able
5938 to identify them during assembly output (if the jumps don't get filled
5939 we need to emit a nop rather than nullifying the delay slot)). We
5940 identify jumps in switch tables by marking the SET with DImode.
5942 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
5943 insns. This serves two purposes, first it prevents jump.c from
5944 noticing that the last N entries in the table jump to the instruction
5945 immediately after the table and deleting the jumps. Second, those
5946 insns mark where we should emit .begin_brtab and .end_brtab directives
5947 when using GAS (allows for better link time optimizations). */
5954 /* Keep track of which insns have unscaled indexed addresses, and which
5955 register is the base address in such insns. */
5956 record_unscaled_index_insn_codes (insns
);
5958 remove_useless_addtr_insns (insns
, 1);
5960 pa_combine_instructions (get_insns ());
5962 /* This is fairly cheap, so always run it if optimizing. */
5963 if (optimize
> 0 && !TARGET_BIG_SWITCH
)
5965 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
5966 insns
= get_insns ();
5967 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
5969 rtx pattern
, tmp
, location
;
5970 unsigned int length
, i
;
5972 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
5973 if (GET_CODE (insn
) != JUMP_INSN
5974 || (GET_CODE (PATTERN (insn
)) != ADDR_VEC
5975 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
))
5978 /* Emit marker for the beginning of the branch table. */
5979 emit_insn_before (gen_begin_brtab (), insn
);
5981 pattern
= PATTERN (insn
);
5982 location
= PREV_INSN (insn
);
5983 length
= XVECLEN (pattern
, GET_CODE (pattern
) == ADDR_DIFF_VEC
);
5985 for (i
= 0; i
< length
; i
++)
5987 /* Emit a label before each jump to keep jump.c from
5988 removing this code. */
5989 tmp
= gen_label_rtx ();
5990 LABEL_NUSES (tmp
) = 1;
5991 emit_label_after (tmp
, location
);
5992 location
= NEXT_INSN (location
);
5994 if (GET_CODE (pattern
) == ADDR_VEC
)
5996 /* Emit the jump itself. */
5997 tmp
= gen_switch_jump (XEXP (XVECEXP (pattern
, 0, i
), 0));
5998 tmp
= emit_jump_insn_after (tmp
, location
);
5999 JUMP_LABEL (tmp
) = XEXP (XVECEXP (pattern
, 0, i
), 0);
6000 LABEL_NUSES (JUMP_LABEL (tmp
))++;
6001 location
= NEXT_INSN (location
);
6005 /* Emit the jump itself. */
6006 tmp
= gen_switch_jump (XEXP (XVECEXP (pattern
, 1, i
), 0));
6007 tmp
= emit_jump_insn_after (tmp
, location
);
6008 JUMP_LABEL (tmp
) = XEXP (XVECEXP (pattern
, 1, i
), 0);
6009 LABEL_NUSES (JUMP_LABEL (tmp
))++;
6010 location
= NEXT_INSN (location
);
6013 /* Emit a BARRIER after the jump. */
6014 emit_barrier_after (location
);
6015 location
= NEXT_INSN (location
);
6018 /* Emit marker for the end of the branch table. */
6019 emit_insn_before (gen_end_brtab (), location
);
6020 location
= NEXT_INSN (location
);
6021 emit_barrier_after (location
);
6023 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
6029 /* Sill need an end_brtab insn. */
6030 insns
= get_insns ();
6031 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
6033 /* Find an ADDR_VEC insn. */
6034 if (GET_CODE (insn
) != JUMP_INSN
6035 || (GET_CODE (PATTERN (insn
)) != ADDR_VEC
6036 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
))
6039 /* Now generate markers for the beginning and end of the
6041 emit_insn_before (gen_begin_brtab (), insn
);
6042 emit_insn_after (gen_end_brtab (), insn
);
6047 /* The PA has a number of odd instructions which can perform multiple
6048 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
6049 it may be profitable to combine two instructions into one instruction
6050 with two outputs. It's not profitable PA2.0 machines because the
6051 two outputs would take two slots in the reorder buffers.
6053 This routine finds instructions which can be combined and combines
6054 them. We only support some of the potential combinations, and we
6055 only try common ways to find suitable instructions.
6057 * addb can add two registers or a register and a small integer
6058 and jump to a nearby (+-8k) location. Normally the jump to the
6059 nearby location is conditional on the result of the add, but by
6060 using the "true" condition we can make the jump unconditional.
6061 Thus addb can perform two independent operations in one insn.
6063 * movb is similar to addb in that it can perform a reg->reg
6064 or small immediate->reg copy and jump to a nearby (+-8k location).
6066 * fmpyadd and fmpysub can perform a FP multiply and either an
6067 FP add or FP sub if the operands of the multiply and add/sub are
6068 independent (there are other minor restrictions). Note both
6069 the fmpy and fadd/fsub can in theory move to better spots according
6070 to data dependencies, but for now we require the fmpy stay at a
6073 * Many of the memory operations can perform pre & post updates
6074 of index registers. GCC's pre/post increment/decrement addressing
6075 is far too simple to take advantage of all the possibilities. This
6076 pass may not be suitable since those insns may not be independent.
6078 * comclr can compare two ints or an int and a register, nullify
6079 the following instruction and zero some other register. This
6080 is more difficult to use as it's harder to find an insn which
6081 will generate a comclr than finding something like an unconditional
6082 branch. (conditional moves & long branches create comclr insns).
6084 * Most arithmetic operations can conditionally skip the next
6085 instruction. They can be viewed as "perform this operation
6086 and conditionally jump to this nearby location" (where nearby
6087 is an insns away). These are difficult to use due to the
6088 branch length restrictions. */
6090 pa_combine_instructions (insns
)
6095 /* This can get expensive since the basic algorithm is on the
6096 order of O(n^2) (or worse). Only do it for -O2 or higher
6097 levels of optimization. */
6101 /* Walk down the list of insns looking for "anchor" insns which
6102 may be combined with "floating" insns. As the name implies,
6103 "anchor" instructions don't move, while "floating" insns may
6105 new = gen_rtx (PARALLEL
, VOIDmode
, gen_rtvec (2, NULL_RTX
, NULL_RTX
));
6106 new = make_insn_raw (new);
6108 for (anchor
= get_insns (); anchor
; anchor
= NEXT_INSN (anchor
))
6110 enum attr_pa_combine_type anchor_attr
;
6111 enum attr_pa_combine_type floater_attr
;
6113 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
6114 Also ignore any special USE insns. */
6115 if (GET_CODE (anchor
) != INSN
6116 && GET_CODE (anchor
) != JUMP_INSN
6117 && GET_CODE (anchor
) != CALL_INSN
6118 || GET_CODE (PATTERN (anchor
)) == USE
6119 || GET_CODE (PATTERN (anchor
)) == CLOBBER
6120 || GET_CODE (PATTERN (anchor
)) == ADDR_VEC
6121 || GET_CODE (PATTERN (anchor
)) == ADDR_DIFF_VEC
)
6124 anchor_attr
= get_attr_pa_combine_type (anchor
);
6125 /* See if anchor is an insn suitable for combination. */
6126 if (anchor_attr
== PA_COMBINE_TYPE_FMPY
6127 || anchor_attr
== PA_COMBINE_TYPE_FADDSUB
6128 || (anchor_attr
== PA_COMBINE_TYPE_UNCOND_BRANCH
6129 && ! forward_branch_p (anchor
)))
6133 for (floater
= PREV_INSN (anchor
);
6135 floater
= PREV_INSN (floater
))
6137 if (GET_CODE (floater
) == NOTE
6138 || (GET_CODE (floater
) == INSN
6139 && (GET_CODE (PATTERN (floater
)) == USE
6140 || GET_CODE (PATTERN (floater
)) == CLOBBER
)))
6143 /* Anything except a regular INSN will stop our search. */
6144 if (GET_CODE (floater
) != INSN
6145 || GET_CODE (PATTERN (floater
)) == ADDR_VEC
6146 || GET_CODE (PATTERN (floater
)) == ADDR_DIFF_VEC
)
6152 /* See if FLOATER is suitable for combination with the
6154 floater_attr
= get_attr_pa_combine_type (floater
);
6155 if ((anchor_attr
== PA_COMBINE_TYPE_FMPY
6156 && floater_attr
== PA_COMBINE_TYPE_FADDSUB
)
6157 || (anchor_attr
== PA_COMBINE_TYPE_FADDSUB
6158 && floater_attr
== PA_COMBINE_TYPE_FMPY
))
6160 /* If ANCHOR and FLOATER can be combined, then we're
6161 done with this pass. */
6162 if (pa_can_combine_p (new, anchor
, floater
, 0,
6163 SET_DEST (PATTERN (floater
)),
6164 XEXP (SET_SRC (PATTERN (floater
)), 0),
6165 XEXP (SET_SRC (PATTERN (floater
)), 1)))
6169 else if (anchor_attr
== PA_COMBINE_TYPE_UNCOND_BRANCH
6170 && floater_attr
== PA_COMBINE_TYPE_ADDMOVE
)
6172 if (GET_CODE (SET_SRC (PATTERN (floater
))) == PLUS
)
6174 if (pa_can_combine_p (new, anchor
, floater
, 0,
6175 SET_DEST (PATTERN (floater
)),
6176 XEXP (SET_SRC (PATTERN (floater
)), 0),
6177 XEXP (SET_SRC (PATTERN (floater
)), 1)))
6182 if (pa_can_combine_p (new, anchor
, floater
, 0,
6183 SET_DEST (PATTERN (floater
)),
6184 SET_SRC (PATTERN (floater
)),
6185 SET_SRC (PATTERN (floater
))))
6191 /* If we didn't find anything on the backwards scan try forwards. */
6193 && (anchor_attr
== PA_COMBINE_TYPE_FMPY
6194 || anchor_attr
== PA_COMBINE_TYPE_FADDSUB
))
6196 for (floater
= anchor
; floater
; floater
= NEXT_INSN (floater
))
6198 if (GET_CODE (floater
) == NOTE
6199 || (GET_CODE (floater
) == INSN
6200 && (GET_CODE (PATTERN (floater
)) == USE
6201 || GET_CODE (PATTERN (floater
)) == CLOBBER
)))
6205 /* Anything except a regular INSN will stop our search. */
6206 if (GET_CODE (floater
) != INSN
6207 || GET_CODE (PATTERN (floater
)) == ADDR_VEC
6208 || GET_CODE (PATTERN (floater
)) == ADDR_DIFF_VEC
)
6214 /* See if FLOATER is suitable for combination with the
6216 floater_attr
= get_attr_pa_combine_type (floater
);
6217 if ((anchor_attr
== PA_COMBINE_TYPE_FMPY
6218 && floater_attr
== PA_COMBINE_TYPE_FADDSUB
)
6219 || (anchor_attr
== PA_COMBINE_TYPE_FADDSUB
6220 && floater_attr
== PA_COMBINE_TYPE_FMPY
))
6222 /* If ANCHOR and FLOATER can be combined, then we're
6223 done with this pass. */
6224 if (pa_can_combine_p (new, anchor
, floater
, 1,
6225 SET_DEST (PATTERN (floater
)),
6226 XEXP (SET_SRC (PATTERN(floater
)),0),
6227 XEXP(SET_SRC(PATTERN(floater
)),1)))
6233 /* FLOATER will be nonzero if we found a suitable floating
6234 insn for combination with ANCHOR. */
6236 && (anchor_attr
== PA_COMBINE_TYPE_FADDSUB
6237 || anchor_attr
== PA_COMBINE_TYPE_FMPY
))
6239 /* Emit the new instruction and delete the old anchor. */
6240 emit_insn_before (gen_rtx (PARALLEL
, VOIDmode
,
6241 gen_rtvec (2, PATTERN (anchor
),
6242 PATTERN (floater
))),
6244 PUT_CODE (anchor
, NOTE
);
6245 NOTE_LINE_NUMBER (anchor
) = NOTE_INSN_DELETED
;
6246 NOTE_SOURCE_FILE (anchor
) = 0;
6248 /* Emit a special USE insn for FLOATER, then delete
6249 the floating insn. */
6250 emit_insn_before (gen_rtx (USE
, VOIDmode
, floater
), floater
);
6251 delete_insn (floater
);
6256 && anchor_attr
== PA_COMBINE_TYPE_UNCOND_BRANCH
)
6259 /* Emit the new_jump instruction and delete the old anchor. */
6260 temp
= emit_jump_insn_before (gen_rtx (PARALLEL
, VOIDmode
,
6261 gen_rtvec (2, PATTERN (anchor
),
6262 PATTERN (floater
))),
6264 JUMP_LABEL (temp
) = JUMP_LABEL (anchor
);
6265 PUT_CODE (anchor
, NOTE
);
6266 NOTE_LINE_NUMBER (anchor
) = NOTE_INSN_DELETED
;
6267 NOTE_SOURCE_FILE (anchor
) = 0;
6269 /* Emit a special USE insn for FLOATER, then delete
6270 the floating insn. */
6271 emit_insn_before (gen_rtx (USE
, VOIDmode
, floater
), floater
);
6272 delete_insn (floater
);
6280 pa_can_combine_p (new, anchor
, floater
, reversed
, dest
, src1
, src2
)
6281 rtx
new, anchor
, floater
;
6283 rtx dest
, src1
, src2
;
6285 int insn_code_number
;
6288 /* Create a PARALLEL with the patterns of ANCHOR and
6289 FLOATER, try to recognize it, then test constraints
6290 for the resulting pattern.
6292 If the pattern doesn't match or the constraints
6293 aren't met keep searching for a suitable floater
6295 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor
);
6296 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater
);
6297 INSN_CODE (new) = -1;
6298 insn_code_number
= recog_memoized (new);
6299 if (insn_code_number
< 0
6300 || !constrain_operands (insn_code_number
, 1))
6314 /* There's up to three operands to consider. One
6315 output and two inputs.
6317 The output must not be used between FLOATER & ANCHOR
6318 exclusive. The inputs must not be set between
6319 FLOATER and ANCHOR exclusive. */
6321 if (reg_used_between_p (dest
, start
, end
))
6324 if (reg_set_between_p (src1
, start
, end
))
6327 if (reg_set_between_p (src2
, start
, end
))
6330 /* If we get here, then everything is good. */