gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 88, 92-96, 1997 Free Software Foundation, Inc.
   3
   4 This file is part of GNU CC.
   5
   6 GNU CC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2, or (at your option)
   9 any later version.
  10
  11 GNU CC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GNU CC; see the file COPYING.  If not, write to
  18 the Free Software Foundation, 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.  */
  20
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information created by
  53    flow.c aren't completely updated:
  54
  55    - reg_live_length is not updated
  56    - reg_n_refs is not adjusted in the rare case when a register is
  57      no longer required in a computation
  58    - there are extremely rare cases (see distribute_regnotes) when a
  59      REG_DEAD note is lost
  60    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  61      removed because there is no way to know which register it was
  62      linking
  63
  64    To simplify substitution, we combine only when the earlier insn(s)
  65    consist of only a single assignment.  To simplify updating afterward,
  66    we never combine when a subroutine call appears in the middle.
  67
  68    Since we do not represent assignments to CC0 explicitly except when that
  69    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  70    the condition code for the insn that set the condition code.
  71    Fortunately, these two insns must be consecutive.
  72    Therefore, every JUMP_INSN is taken to have an implicit logical link
  73    to the preceding insn.  This is not quite right, since non-jumps can
  74    also use the condition code; but in practice such insns would not
  75    combine anyway.  */
  76
  77 #include "config.h"
  78 #ifdef __STDC__
  79 #include <stdarg.h>
  80 #else
  81 #include <varargs.h>
  82 #endif
  83
  84 /* Must precede rtl.h for FFS.  */
  85 #include <stdio.h>
  86
  87 #include "rtl.h"
  88 #include "flags.h"
  89 #include "regs.h"
  90 #include "hard-reg-set.h"
  91 #include "expr.h"
  92 #include "basic-block.h"
  93 #include "insn-config.h"
  94 #include "insn-flags.h"
  95 #include "insn-codes.h"
  96 #include "insn-attr.h"
  97 #include "recog.h"
  98 #include "real.h"
  99
 100 /* It is not safe to use ordinary gen_lowpart in combine.
 101    Use gen_lowpart_for_combine instead.  See comments there.  */
 102 #define gen_lowpart dont_use_gen_lowpart_you_dummy
 103
 104 /* Number of attempts to combine instructions in this function.  */
 105
 106 static int combine_attempts;
 107
 108 /* Number of attempts that got as far as substitution in this function.  */
 109
 110 static int combine_merges;
 111
 112 /* Number of instructions combined with added SETs in this function.  */
 113
 114 static int combine_extras;
 115
 116 /* Number of instructions combined in this function.  */
 117
 118 static int combine_successes;
 119
 120 /* Totals over entire compilation.  */
 121
 122 static int total_attempts, total_merges, total_extras, total_successes;
 123
 124 /* Define a default value for REVERSIBLE_CC_MODE.
 125    We can never assume that a condition code mode is safe to reverse unless
 126    the md tells us so.  */
 127 #ifndef REVERSIBLE_CC_MODE
 128 #define REVERSIBLE_CC_MODE(MODE) 0
 129 #endif
 130 \f
 131 /* Vector mapping INSN_UIDs to cuids.
 132    The cuids are like uids but increase monotonically always.
 133    Combine always uses cuids so that it can compare them.
 134    But actually renumbering the uids, which we used to do,
 135    proves to be a bad idea because it makes it hard to compare
 136    the dumps produced by earlier passes with those from later passes.  */
 137
 138 static int *uid_cuid;
 139 static int max_uid_cuid;
 140
 141 /* Get the cuid of an insn.  */
 142
 143 #define INSN_CUID(INSN) \
 144 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
 145
 146 /* Maximum register number, which is the size of the tables below.  */
 147
 148 static int combine_max_regno;
 149
 150 /* Record last point of death of (hard or pseudo) register n.  */
 151
 152 static rtx *reg_last_death;
 153
 154 /* Record last point of modification of (hard or pseudo) register n.  */
 155
 156 static rtx *reg_last_set;
 157
 158 /* Record the cuid of the last insn that invalidated memory
 159    (anything that writes memory, and subroutine calls, but not pushes).  */
 160
 161 static int mem_last_set;
 162
 163 /* Record the cuid of the last CALL_INSN
 164    so we can tell whether a potential combination crosses any calls.  */
 165
 166 static int last_call_cuid;
 167
 168 /* When `subst' is called, this is the insn that is being modified
 169    (by combining in a previous insn).  The PATTERN of this insn
 170    is still the old pattern partially modified and it should not be
 171    looked at, but this may be used to examine the successors of the insn
 172    to judge whether a simplification is valid.  */
 173
 174 static rtx subst_insn;
 175
 176 /* This is an insn that belongs before subst_insn, but is not currently
 177    on the insn chain.  */
 178
 179 static rtx subst_prev_insn;
 180
 181 /* This is the lowest CUID that `subst' is currently dealing with.
 182    get_last_value will not return a value if the register was set at or
 183    after this CUID.  If not for this mechanism, we could get confused if
 184    I2 or I1 in try_combine were an insn that used the old value of a register
 185    to obtain a new value.  In that case, we might erroneously get the
 186    new value of the register when we wanted the old one.  */
 187
 188 static int subst_low_cuid;
 189
 190 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 191    must consider all these registers to be always live.  */
 192
 193 static HARD_REG_SET newpat_used_regs;
 194
 195 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 196    insn is the earlier than I2 or I3, combine should rescan starting at
 197    that location.  */
 198
 199 static rtx added_links_insn;
 200
 201 /* Basic block number of the block in which we are performing combines.  */
 202 static int this_basic_block;
 203 \f
 204 /* The next group of arrays allows the recording of the last value assigned
 205    to (hard or pseudo) register n.  We use this information to see if a
 206    operation being processed is redundant given a prior operation performed
 207    on the register.  For example, an `and' with a constant is redundant if
 208    all the zero bits are already known to be turned off.
 209
 210    We use an approach similar to that used by cse, but change it in the
 211    following ways:
 212
 213    (1) We do not want to reinitialize at each label.
 214    (2) It is useful, but not critical, to know the actual value assigned
 215        to a register.  Often just its form is helpful.
 216
 217    Therefore, we maintain the following arrays:
 218
 219    reg_last_set_value           the last value assigned
 220    reg_last_set_label           records the value of label_tick when the
 221                                 register was assigned
 222    reg_last_set_table_tick      records the value of label_tick when a
 223                                 value using the register is assigned
 224    reg_last_set_invalid         set to non-zero when it is not valid
 225                                 to use the value of this register in some
 226                                 register's value
 227
 228    To understand the usage of these tables, it is important to understand
 229    the distinction between the value in reg_last_set_value being valid
 230    and the register being validly contained in some other expression in the
 231    table.
 232
 233    Entry I in reg_last_set_value is valid if it is non-zero, and either
 234    reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
 235
 236    Register I may validly appear in any expression returned for the value
 237    of another register if reg_n_sets[i] is 1.  It may also appear in the
 238    value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
 239    reg_last_set_invalid[j] is zero.
 240
 241    If an expression is found in the table containing a register which may
 242    not validly appear in an expression, the register is replaced by
 243    something that won't match, (clobber (const_int 0)).
 244
 245    reg_last_set_invalid[i] is set non-zero when register I is being assigned
 246    to and reg_last_set_table_tick[i] == label_tick.  */
 247
 248 /* Record last value assigned to (hard or pseudo) register n.  */
 249
 250 static rtx *reg_last_set_value;
 251
 252 /* Record the value of label_tick when the value for register n is placed in
 253    reg_last_set_value[n].  */
 254
 255 static int *reg_last_set_label;
 256
 257 /* Record the value of label_tick when an expression involving register n
 258    is placed in reg_last_set_value.  */
 259
 260 static int *reg_last_set_table_tick;
 261
 262 /* Set non-zero if references to register n in expressions should not be
 263    used.  */
 264
 265 static char *reg_last_set_invalid;
 266
 267 /* Incremented for each label.  */
 268
 269 static int label_tick;
 270
 271 /* Some registers that are set more than once and used in more than one
 272    basic block are nevertheless always set in similar ways.  For example,
 273    a QImode register may be loaded from memory in two places on a machine
 274    where byte loads zero extend.
 275
 276    We record in the following array what we know about the nonzero
 277    bits of a register, specifically which bits are known to be zero.
 278
 279    If an entry is zero, it means that we don't know anything special.  */
 280
 281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
 282
 283 /* Mode used to compute significance in reg_nonzero_bits.  It is the largest
 284    integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 285
 286 static enum machine_mode nonzero_bits_mode;
 287
 288 /* Nonzero if we know that a register has some leading bits that are always
 289    equal to the sign bit.  */
 290
 291 static char *reg_sign_bit_copies;
 292
 293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
 294    It is zero while computing them and after combine has completed.  This
 295    former test prevents propagating values based on previously set values,
 296    which can be incorrect if a variable is modified in a loop.  */
 297
 298 static int nonzero_sign_valid;
 299
 300 /* These arrays are maintained in parallel with reg_last_set_value
 301    and are used to store the mode in which the register was last set,
 302    the bits that were known to be zero when it was last set, and the
 303    number of sign bits copies it was known to have when it was last set.  */
 304
 305 static enum machine_mode *reg_last_set_mode;
 306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
 307 static char *reg_last_set_sign_bit_copies;
 308 \f
 309 /* Record one modification to rtl structure
 310    to be undone by storing old_contents into *where.
 311    is_int is 1 if the contents are an int.  */
 312
 313 struct undo
 314 {
 315   struct undo *next;
 316   int is_int;
 317   union {rtx r; int i;} old_contents;
 318   union {rtx *r; int *i;} where;
 319 };
 320
 321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 322    num_undo says how many are currently recorded.
 323
 324    storage is nonzero if we must undo the allocation of new storage.
 325    The value of storage is what to pass to obfree.
 326
 327    other_insn is nonzero if we have modified some other insn in the process
 328    of working on subst_insn.  It must be verified too.
 329
 330    previous_undos is the value of undobuf.undos when we started processing
 331    this substitution.  This will prevent gen_rtx_combine from re-used a piece
 332    from the previous expression.  Doing so can produce circular rtl
 333    structures.  */
 334
 335 struct undobuf
 336 {
 337   char *storage;
 338   struct undo *undos;
 339   struct undo *frees;
 340   struct undo *previous_undos;
 341   rtx other_insn;
 342 };
 343
 344 static struct undobuf undobuf;
 345
 346 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 347    insn.  The substitution can be undone by undo_all.  If INTO is already
 348    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 349    also call SUBST, we have to compute it before we put anything into
 350    the undo table.  */
 351
 352 #define SUBST(INTO, NEWVAL)  \
 353  do { rtx _new = (NEWVAL);                                      \
 354       struct undo *_buf;                                        \
 355                                                                 \
 356       if (undobuf.frees)                                        \
 357         _buf = undobuf.frees, undobuf.frees = _buf->next;       \
 358       else                                                      \
 359         _buf = (struct undo *) xmalloc (sizeof (struct undo));  \
 360                                                                 \
 361       _buf->is_int = 0;                                         \
 362       _buf->where.r = &INTO;                                    \
 363       _buf->old_contents.r = INTO;                              \
 364       INTO = _new;                                              \
 365       if (_buf->old_contents.r == INTO)                         \
 366         _buf->next = undobuf.frees, undobuf.frees = _buf;       \
 367       else                                                      \
 368         _buf->next = undobuf.undos, undobuf.undos = _buf;       \
 369     } while (0)
 370
 371 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 372    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 373    not safe.  */
 374
 375 #define SUBST_INT(INTO, NEWVAL)  \
 376  do { struct undo *_buf;                                        \
 377                                                                 \
 378       if (undobuf.frees)                                        \
 379         _buf = undobuf.frees, undobuf.frees = _buf->next;       \
 380       else                                                      \
 381         _buf = (struct undo *) xmalloc (sizeof (struct undo));  \
 382                                                                 \
 383       _buf->is_int = 1;                                         \
 384       _buf->where.i = (int *) &INTO;                            \
 385       _buf->old_contents.i = INTO;                              \
 386       INTO = NEWVAL;                                            \
 387       if (_buf->old_contents.i == INTO)                         \
 388         _buf->next = undobuf.frees, undobuf.frees = _buf;       \
 389       else                                                      \
 390         _buf->next = undobuf.undos, undobuf.undos = _buf;       \
 391      } while (0)
 392
 393 /* Number of times the pseudo being substituted for
 394    was found and replaced.  */
 395
 396 static int n_occurrences;
 397
 398 static void init_reg_last_arrays        PROTO((void));
 399 static void setup_incoming_promotions   PROTO((void));
 400 static void set_nonzero_bits_and_sign_copies  PROTO((rtx, rtx));
 401 static int can_combine_p        PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
 402 static int combinable_i3pat     PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
 403 static rtx try_combine          PROTO((rtx, rtx, rtx));
 404 static void undo_all            PROTO((void));
 405 static rtx *find_split_point    PROTO((rtx *, rtx));
 406 static rtx subst                PROTO((rtx, rtx, rtx, int, int));
 407 static rtx simplify_rtx         PROTO((rtx, enum machine_mode, int, int));
 408 static rtx simplify_if_then_else  PROTO((rtx));
 409 static rtx simplify_set         PROTO((rtx));
 410 static rtx simplify_logical     PROTO((rtx, int));
 411 static rtx expand_compound_operation  PROTO((rtx));
 412 static rtx expand_field_assignment  PROTO((rtx));
 413 static rtx make_extraction      PROTO((enum machine_mode, rtx, int, rtx, int,
 414                                        int, int, int));
 415 static rtx extract_left_shift   PROTO((rtx, int));
 416 static rtx make_compound_operation  PROTO((rtx, enum rtx_code));
 417 static int get_pos_from_mask    PROTO((unsigned HOST_WIDE_INT, int *));
 418 static rtx force_to_mode        PROTO((rtx, enum machine_mode,
 419                                        unsigned HOST_WIDE_INT, rtx, int));
 420 static rtx if_then_else_cond    PROTO((rtx, rtx *, rtx *));
 421 static rtx known_cond           PROTO((rtx, enum rtx_code, rtx, rtx));
 422 static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
 423 static rtx make_field_assignment  PROTO((rtx));
 424 static rtx apply_distributive_law  PROTO((rtx));
 425 static rtx simplify_and_const_int  PROTO((rtx, enum machine_mode, rtx,
 426                                           unsigned HOST_WIDE_INT));
 427 static unsigned HOST_WIDE_INT nonzero_bits  PROTO((rtx, enum machine_mode));
 428 static int num_sign_bit_copies  PROTO((rtx, enum machine_mode));
 429 static int merge_outer_ops      PROTO((enum rtx_code *, HOST_WIDE_INT *,
 430                                        enum rtx_code, HOST_WIDE_INT,
 431                                        enum machine_mode, int *));
 432 static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
 433                                        rtx, int));
 434 static int recog_for_combine    PROTO((rtx *, rtx, rtx *, int *));
 435 static rtx gen_lowpart_for_combine  PROTO((enum machine_mode, rtx));
 436 static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
 437                                   ...));
 438 static rtx gen_binary           PROTO((enum rtx_code, enum machine_mode,
 439                                        rtx, rtx));
 440 static rtx gen_unary            PROTO((enum rtx_code, enum machine_mode,
 441                                        enum machine_mode, rtx));
 442 static enum rtx_code simplify_comparison  PROTO((enum rtx_code, rtx *, rtx *));
 443 static int reversible_comparison_p  PROTO((rtx));
 444 static void update_table_tick   PROTO((rtx));
 445 static void record_value_for_reg  PROTO((rtx, rtx, rtx));
 446 static void record_dead_and_set_regs_1  PROTO((rtx, rtx));
 447 static void record_dead_and_set_regs  PROTO((rtx));
 448 static int get_last_value_validate  PROTO((rtx *, rtx, int, int));
 449 static rtx get_last_value       PROTO((rtx));
 450 static int use_crosses_set_p    PROTO((rtx, int));
 451 static void reg_dead_at_p_1     PROTO((rtx, rtx));
 452 static int reg_dead_at_p        PROTO((rtx, rtx));
 453 static void move_deaths         PROTO((rtx, rtx, int, rtx, rtx *));
 454 static int reg_bitfield_target_p  PROTO((rtx, rtx));
 455 static void distribute_notes    PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
 456 static void distribute_links    PROTO((rtx));
 457 static void mark_used_regs_combine PROTO((rtx));
 458 static int insn_cuid            PROTO((rtx));
 459 \f
 460 /* Main entry point for combiner.  F is the first insn of the function.
 461    NREGS is the first unused pseudo-reg number.  */
 462
 463 void
 464 combine_instructions (f, nregs)
 465      rtx f;
 466      int nregs;
 467 {
 468   register rtx insn, next, prev;
 469   register int i;
 470   register rtx links, nextlinks;
 471
 472   combine_attempts = 0;
 473   combine_merges = 0;
 474   combine_extras = 0;
 475   combine_successes = 0;
 476   undobuf.undos = undobuf.previous_undos = 0;
 477
 478   combine_max_regno = nregs;
 479
 480   reg_nonzero_bits
 481     = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
 482   reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
 483
 484   bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
 485   bzero (reg_sign_bit_copies, nregs * sizeof (char));
 486
 487   reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
 488   reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
 489   reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
 490   reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
 491   reg_last_set_label = (int *) alloca (nregs * sizeof (int));
 492   reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
 493   reg_last_set_mode
 494     = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
 495   reg_last_set_nonzero_bits
 496     = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
 497   reg_last_set_sign_bit_copies
 498     = (char *) alloca (nregs * sizeof (char));
 499
 500   init_reg_last_arrays ();
 501
 502   init_recog_no_volatile ();
 503
 504   /* Compute maximum uid value so uid_cuid can be allocated.  */
 505
 506   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 507     if (INSN_UID (insn) > i)
 508       i = INSN_UID (insn);
 509
 510   uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
 511   max_uid_cuid = i;
 512
 513   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
 514
 515   /* Don't use reg_nonzero_bits when computing it.  This can cause problems
 516      when, for example, we have j <<= 1 in a loop.  */
 517
 518   nonzero_sign_valid = 0;
 519
 520   /* Compute the mapping from uids to cuids.
 521      Cuids are numbers assigned to insns, like uids,
 522      except that cuids increase monotonically through the code.
 523
 524      Scan all SETs and see if we can deduce anything about what
 525      bits are known to be zero for some registers and how many copies
 526      of the sign bit are known to exist for those registers.
 527
 528      Also set any known values so that we can use it while searching
 529      for what bits are known to be set.  */
 530
 531   label_tick = 1;
 532
 533   /* We need to initialize it here, because record_dead_and_set_regs may call
 534      get_last_value.  */
 535   subst_prev_insn = NULL_RTX;
 536
 537   setup_incoming_promotions ();
 538
 539   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 540     {
 541       uid_cuid[INSN_UID (insn)] = ++i;
 542       subst_low_cuid = i;
 543       subst_insn = insn;
 544
 545       if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
 546         {
 547           note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
 548           record_dead_and_set_regs (insn);
 549
 550 #ifdef AUTO_INC_DEC
 551           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
 552             if (REG_NOTE_KIND (links) == REG_INC)
 553               set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
 554 #endif
 555         }
 556
 557       if (GET_CODE (insn) == CODE_LABEL)
 558         label_tick++;
 559     }
 560
 561   nonzero_sign_valid = 1;
 562
 563   /* Now scan all the insns in forward order.  */
 564
 565   this_basic_block = -1;
 566   label_tick = 1;
 567   last_call_cuid = 0;
 568   mem_last_set = 0;
 569   init_reg_last_arrays ();
 570   setup_incoming_promotions ();
 571
 572   for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
 573     {
 574       next = 0;
 575
 576       /* If INSN starts a new basic block, update our basic block number.  */
 577       if (this_basic_block + 1 < n_basic_blocks
 578           && basic_block_head[this_basic_block + 1] == insn)
 579         this_basic_block++;
 580
 581       if (GET_CODE (insn) == CODE_LABEL)
 582         label_tick++;
 583
 584       else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
 585         {
 586           /* Try this insn with each insn it links back to.  */
 587
 588           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 589             if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
 590               goto retry;
 591
 592           /* Try each sequence of three linked insns ending with this one.  */
 593
 594           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 595             for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
 596                  nextlinks = XEXP (nextlinks, 1))
 597               if ((next = try_combine (insn, XEXP (links, 0),
 598                                        XEXP (nextlinks, 0))) != 0)
 599                 goto retry;
 600
 601 #ifdef HAVE_cc0
 602           /* Try to combine a jump insn that uses CC0
 603              with a preceding insn that sets CC0, and maybe with its
 604              logical predecessor as well.
 605              This is how we make decrement-and-branch insns.
 606              We need this special code because data flow connections
 607              via CC0 do not get entered in LOG_LINKS.  */
 608
 609           if (GET_CODE (insn) == JUMP_INSN
 610               && (prev = prev_nonnote_insn (insn)) != 0
 611               && GET_CODE (prev) == INSN
 612               && sets_cc0_p (PATTERN (prev)))
 613             {
 614               if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
 615                 goto retry;
 616
 617               for (nextlinks = LOG_LINKS (prev); nextlinks;
 618                    nextlinks = XEXP (nextlinks, 1))
 619                 if ((next = try_combine (insn, prev,
 620                                          XEXP (nextlinks, 0))) != 0)
 621                   goto retry;
 622             }
 623
 624           /* Do the same for an insn that explicitly references CC0.  */
 625           if (GET_CODE (insn) == INSN
 626               && (prev = prev_nonnote_insn (insn)) != 0
 627               && GET_CODE (prev) == INSN
 628               && sets_cc0_p (PATTERN (prev))
 629               && GET_CODE (PATTERN (insn)) == SET
 630               && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
 631             {
 632               if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
 633                 goto retry;
 634
 635               for (nextlinks = LOG_LINKS (prev); nextlinks;
 636                    nextlinks = XEXP (nextlinks, 1))
 637                 if ((next = try_combine (insn, prev,
 638                                          XEXP (nextlinks, 0))) != 0)
 639                   goto retry;
 640             }
 641
 642           /* Finally, see if any of the insns that this insn links to
 643              explicitly references CC0.  If so, try this insn, that insn,
 644              and its predecessor if it sets CC0.  */
 645           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 646             if (GET_CODE (XEXP (links, 0)) == INSN
 647                 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
 648                 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
 649                 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
 650                 && GET_CODE (prev) == INSN
 651                 && sets_cc0_p (PATTERN (prev))
 652                 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
 653               goto retry;
 654 #endif
 655
 656           /* Try combining an insn with two different insns whose results it
 657              uses.  */
 658           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 659             for (nextlinks = XEXP (links, 1); nextlinks;
 660                  nextlinks = XEXP (nextlinks, 1))
 661               if ((next = try_combine (insn, XEXP (links, 0),
 662                                        XEXP (nextlinks, 0))) != 0)
 663                 goto retry;
 664
 665           if (GET_CODE (insn) != NOTE)
 666             record_dead_and_set_regs (insn);
 667
 668         retry:
 669           ;
 670         }
 671     }
 672
 673   total_attempts += combine_attempts;
 674   total_merges += combine_merges;
 675   total_extras += combine_extras;
 676   total_successes += combine_successes;
 677
 678   nonzero_sign_valid = 0;
 679 }
 680
 681 /* Wipe the reg_last_xxx arrays in preparation for another pass.  */
 682
 683 static void
 684 init_reg_last_arrays ()
 685 {
 686   int nregs = combine_max_regno;
 687
 688   bzero ((char *) reg_last_death, nregs * sizeof (rtx));
 689   bzero ((char *) reg_last_set, nregs * sizeof (rtx));
 690   bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
 691   bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
 692   bzero ((char *) reg_last_set_label, nregs * sizeof (int));
 693   bzero (reg_last_set_invalid, nregs * sizeof (char));
 694   bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
 695   bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
 696   bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
 697 }
 698 \f
 699 /* Set up any promoted values for incoming argument registers.  */
 700
 701 static void
 702 setup_incoming_promotions ()
 703 {
 704 #ifdef PROMOTE_FUNCTION_ARGS
 705   int regno;
 706   rtx reg;
 707   enum machine_mode mode;
 708   int unsignedp;
 709   rtx first = get_insns ();
 710
 711   for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
 712     if (FUNCTION_ARG_REGNO_P (regno)
 713         && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
 714       record_value_for_reg (reg, first,
 715                             gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
 716                                      GET_MODE (reg),
 717                                      gen_rtx (CLOBBER, mode, const0_rtx)));
 718 #endif
 719 }
 720 \f
 721 /* Called via note_stores.  If X is a pseudo that is narrower than
 722    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
 723
 724    If we are setting only a portion of X and we can't figure out what
 725    portion, assume all bits will be used since we don't know what will
 726    be happening.
 727
 728    Similarly, set how many bits of X are known to be copies of the sign bit
 729    at all locations in the function.  This is the smallest number implied
 730    by any set of X.  */
 731
 732 static void
 733 set_nonzero_bits_and_sign_copies (x, set)
 734      rtx x;
 735      rtx set;
 736 {
 737   int num;
 738
 739   if (GET_CODE (x) == REG
 740       && REGNO (x) >= FIRST_PSEUDO_REGISTER
 741       /* If this register is undefined at the start of the file, we can't
 742          say what its contents were.  */
 743       && ! REGNO_REG_SET_P (basic_block_live_at_start[0], REGNO (x))
 744       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
 745     {
 746       if (set == 0 || GET_CODE (set) == CLOBBER)
 747         {
 748           reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
 749           reg_sign_bit_copies[REGNO (x)] = 1;
 750           return;
 751         }
 752
 753       /* If this is a complex assignment, see if we can convert it into a
 754          simple assignment.  */
 755       set = expand_field_assignment (set);
 756
 757       /* If this is a simple assignment, or we have a paradoxical SUBREG,
 758          set what we know about X.  */
 759
 760       if (SET_DEST (set) == x
 761           || (GET_CODE (SET_DEST (set)) == SUBREG
 762               && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
 763                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
 764               && SUBREG_REG (SET_DEST (set)) == x))
 765         {
 766           rtx src = SET_SRC (set);
 767
 768 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
 769           /* If X is narrower than a word and SRC is a non-negative
 770              constant that would appear negative in the mode of X,
 771              sign-extend it for use in reg_nonzero_bits because some
 772              machines (maybe most) will actually do the sign-extension
 773              and this is the conservative approach.
 774
 775              ??? For 2.5, try to tighten up the MD files in this regard
 776              instead of this kludge.  */
 777
 778           if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
 779               && GET_CODE (src) == CONST_INT
 780               && INTVAL (src) > 0
 781               && 0 != (INTVAL (src)
 782                        & ((HOST_WIDE_INT) 1
 783                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
 784             src = GEN_INT (INTVAL (src)
 785                            | ((HOST_WIDE_INT) (-1)
 786                               << GET_MODE_BITSIZE (GET_MODE (x))));
 787 #endif
 788
 789           reg_nonzero_bits[REGNO (x)]
 790             |= nonzero_bits (src, nonzero_bits_mode);
 791           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
 792           if (reg_sign_bit_copies[REGNO (x)] == 0
 793               || reg_sign_bit_copies[REGNO (x)] > num)
 794             reg_sign_bit_copies[REGNO (x)] = num;
 795         }
 796       else
 797         {
 798           reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
 799           reg_sign_bit_copies[REGNO (x)] = 1;
 800         }
 801     }
 802 }
 803 \f
 804 /* See if INSN can be combined into I3.  PRED and SUCC are optionally
 805    insns that were previously combined into I3 or that will be combined
 806    into the merger of INSN and I3.
 807
 808    Return 0 if the combination is not allowed for any reason.
 809
 810    If the combination is allowed, *PDEST will be set to the single
 811    destination of INSN and *PSRC to the single source, and this function
 812    will return 1.  */
 813
 814 static int
 815 can_combine_p (insn, i3, pred, succ, pdest, psrc)
 816      rtx insn;
 817      rtx i3;
 818      rtx pred, succ;
 819      rtx *pdest, *psrc;
 820 {
 821   int i;
 822   rtx set = 0, src, dest;
 823   rtx p, link;
 824   int all_adjacent = (succ ? (next_active_insn (insn) == succ
 825                               && next_active_insn (succ) == i3)
 826                       : next_active_insn (insn) == i3);
 827
 828   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
 829      or a PARALLEL consisting of such a SET and CLOBBERs.
 830
 831      If INSN has CLOBBER parallel parts, ignore them for our processing.
 832      By definition, these happen during the execution of the insn.  When it
 833      is merged with another insn, all bets are off.  If they are, in fact,
 834      needed and aren't also supplied in I3, they may be added by
 835      recog_for_combine.  Otherwise, it won't match.
 836
 837      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
 838      note.
 839
 840      Get the source and destination of INSN.  If more than one, can't
 841      combine.  */
 842
 843   if (GET_CODE (PATTERN (insn)) == SET)
 844     set = PATTERN (insn);
 845   else if (GET_CODE (PATTERN (insn)) == PARALLEL
 846            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
 847     {
 848       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
 849         {
 850           rtx elt = XVECEXP (PATTERN (insn), 0, i);
 851
 852           switch (GET_CODE (elt))
 853             {
 854               /* We can ignore CLOBBERs.  */
 855             case CLOBBER:
 856               break;
 857
 858             case SET:
 859               /* Ignore SETs whose result isn't used but not those that
 860                  have side-effects.  */
 861               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
 862                   && ! side_effects_p (elt))
 863                 break;
 864
 865               /* If we have already found a SET, this is a second one and
 866                  so we cannot combine with this insn.  */
 867               if (set)
 868                 return 0;
 869
 870               set = elt;
 871               break;
 872
 873             default:
 874               /* Anything else means we can't combine.  */
 875               return 0;
 876             }
 877         }
 878
 879       if (set == 0
 880           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
 881              so don't do anything with it.  */
 882           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
 883         return 0;
 884     }
 885   else
 886     return 0;
 887
 888   if (set == 0)
 889     return 0;
 890
 891   set = expand_field_assignment (set);
 892   src = SET_SRC (set), dest = SET_DEST (set);
 893
 894   /* Don't eliminate a store in the stack pointer.  */
 895   if (dest == stack_pointer_rtx
 896       /* If we couldn't eliminate a field assignment, we can't combine.  */
 897       || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
 898       /* Don't combine with an insn that sets a register to itself if it has
 899          a REG_EQUAL note.  This may be part of a REG_NO_CONFLICT sequence.  */
 900       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
 901       /* Can't merge a function call.  */
 902       || GET_CODE (src) == CALL
 903       /* Don't eliminate a function call argument.  */
 904       || (GET_CODE (i3) == CALL_INSN
 905           && (find_reg_fusage (i3, USE, dest)
 906               || (GET_CODE (dest) == REG
 907                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
 908                   && global_regs[REGNO (dest)])))
 909       /* Don't substitute into an incremented register.  */
 910       || FIND_REG_INC_NOTE (i3, dest)
 911       || (succ && FIND_REG_INC_NOTE (succ, dest))
 912       /* Don't combine the end of a libcall into anything.  */
 913       || find_reg_note (insn, REG_RETVAL, NULL_RTX)
 914       /* Make sure that DEST is not used after SUCC but before I3.  */
 915       || (succ && ! all_adjacent
 916           && reg_used_between_p (dest, succ, i3))
 917       /* Make sure that the value that is to be substituted for the register
 918          does not use any registers whose values alter in between.  However,
 919          If the insns are adjacent, a use can't cross a set even though we
 920          think it might (this can happen for a sequence of insns each setting
 921          the same destination; reg_last_set of that register might point to
 922          a NOTE).  If INSN has a REG_EQUIV note, the register is always
 923          equivalent to the memory so the substitution is valid even if there
 924          are intervening stores.  Also, don't move a volatile asm or
 925          UNSPEC_VOLATILE across any other insns.  */
 926       || (! all_adjacent
 927           && (((GET_CODE (src) != MEM
 928                 || ! find_reg_note (insn, REG_EQUIV, src))
 929                && use_crosses_set_p (src, INSN_CUID (insn)))
 930               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
 931               || GET_CODE (src) == UNSPEC_VOLATILE))
 932       /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
 933          better register allocation by not doing the combine.  */
 934       || find_reg_note (i3, REG_NO_CONFLICT, dest)
 935       || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
 936       /* Don't combine across a CALL_INSN, because that would possibly
 937          change whether the life span of some REGs crosses calls or not,
 938          and it is a pain to update that information.
 939          Exception: if source is a constant, moving it later can't hurt.
 940          Accept that special case, because it helps -fforce-addr a lot.  */
 941       || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
 942     return 0;
 943
 944   /* DEST must either be a REG or CC0.  */
 945   if (GET_CODE (dest) == REG)
 946     {
 947       /* If register alignment is being enforced for multi-word items in all
 948          cases except for parameters, it is possible to have a register copy
 949          insn referencing a hard register that is not allowed to contain the
 950          mode being copied and which would not be valid as an operand of most
 951          insns.  Eliminate this problem by not combining with such an insn.
 952
 953          Also, on some machines we don't want to extend the life of a hard
 954          register.
 955
 956          This is the same test done in can_combine except that we don't test
 957          if SRC is a CALL operation to permit a hard register with
 958          SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
 959          into account.  */
 960
 961       if (GET_CODE (src) == REG
 962           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
 963                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
 964               /* Don't extend the life of a hard register unless it is
 965                  user variable (if we have few registers) or it can't
 966                  fit into the desired register (meaning something special
 967                  is going on).
 968                  Also avoid substituting a return register into I3, because
 969                  reload can't handle a conflict with constraints of other
 970                  inputs.  */
 971               || (REGNO (src) < FIRST_PSEUDO_REGISTER
 972                   && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
 973                       || (SMALL_REGISTER_CLASSES
 974                           && ((! all_adjacent && ! REG_USERVAR_P (src))
 975                               || (FUNCTION_VALUE_REGNO_P (REGNO (src))
 976                                   && ! REG_USERVAR_P (src))))))))
 977         return 0;
 978     }
 979   else if (GET_CODE (dest) != CC0)
 980     return 0;
 981
 982   /* Don't substitute for a register intended as a clobberable operand.
 983      Similarly, don't substitute an expression containing a register that
 984      will be clobbered in I3.  */
 985   if (GET_CODE (PATTERN (i3)) == PARALLEL)
 986     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
 987       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
 988           && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
 989                                        src)
 990               || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
 991         return 0;
 992
 993   /* If INSN contains anything volatile, or is an `asm' (whether volatile
 994      or not), reject, unless nothing volatile comes between it and I3,
 995      with the exception of SUCC.  */
 996
 997   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
 998     for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
 999       if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1000           && p != succ && volatile_refs_p (PATTERN (p)))
1001         return 0;
1002
1003   /* If there are any volatile insns between INSN and I3, reject, because
1004      they might affect machine state.  */
1005
1006   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1007     if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1008         && p != succ && volatile_insn_p (PATTERN (p)))
1009       return 0;
1010
1011   /* If INSN or I2 contains an autoincrement or autodecrement,
1012      make sure that register is not used between there and I3,
1013      and not already used in I3 either.
1014      Also insist that I3 not be a jump; if it were one
1015      and the incremented register were spilled, we would lose.  */
1016
1017 #ifdef AUTO_INC_DEC
1018   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1019     if (REG_NOTE_KIND (link) == REG_INC
1020         && (GET_CODE (i3) == JUMP_INSN
1021             || reg_used_between_p (XEXP (link, 0), insn, i3)
1022             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1023       return 0;
1024 #endif
1025
1026 #ifdef HAVE_cc0
1027   /* Don't combine an insn that follows a CC0-setting insn.
1028      An insn that uses CC0 must not be separated from the one that sets it.
1029      We do, however, allow I2 to follow a CC0-setting insn if that insn
1030      is passed as I1; in that case it will be deleted also.
1031      We also allow combining in this case if all the insns are adjacent
1032      because that would leave the two CC0 insns adjacent as well.
1033      It would be more logical to test whether CC0 occurs inside I1 or I2,
1034      but that would be much slower, and this ought to be equivalent.  */
1035
1036   p = prev_nonnote_insn (insn);
1037   if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1038       && ! all_adjacent)
1039     return 0;
1040 #endif
1041
1042   /* If we get here, we have passed all the tests and the combination is
1043      to be allowed.  */
1044
1045   *pdest = dest;
1046   *psrc = src;
1047
1048   return 1;
1049 }
1050 \f
1051 /* Check if PAT is an insn - or a part of it - used to set up an
1052    argument for a function in a hard register.  */
1053
1054 static int
1055 sets_function_arg_p (pat)
1056      rtx pat;
1057 {
1058   int i;
1059   rtx inner_dest;
1060
1061   switch (GET_CODE (pat))
1062     {
1063     case INSN:
1064       return sets_function_arg_p (PATTERN (pat));
1065
1066     case PARALLEL:
1067       for (i = XVECLEN (pat, 0); --i >= 0;)
1068         if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1069           return 1;
1070
1071       break;
1072
1073     case SET:
1074       inner_dest = SET_DEST (pat);
1075       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1076              || GET_CODE (inner_dest) == SUBREG
1077              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1078         inner_dest = XEXP (inner_dest, 0);
1079
1080       return (GET_CODE (inner_dest) == REG
1081               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1082               && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1083     }
1084
1085   return 0;
1086 }
1087
1088 /* LOC is the location within I3 that contains its pattern or the component
1089    of a PARALLEL of the pattern.  We validate that it is valid for combining.
1090
1091    One problem is if I3 modifies its output, as opposed to replacing it
1092    entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1093    so would produce an insn that is not equivalent to the original insns.
1094
1095    Consider:
1096
1097          (set (reg:DI 101) (reg:DI 100))
1098          (set (subreg:SI (reg:DI 101) 0) <foo>)
1099
1100    This is NOT equivalent to:
1101
1102          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1103                     (set (reg:DI 101) (reg:DI 100))])
1104
1105    Not only does this modify 100 (in which case it might still be valid
1106    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1107
1108    We can also run into a problem if I2 sets a register that I1
1109    uses and I1 gets directly substituted into I3 (not via I2).  In that
1110    case, we would be getting the wrong value of I2DEST into I3, so we
1111    must reject the combination.  This case occurs when I2 and I1 both
1112    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1113    If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1114    of a SET must prevent combination from occurring.
1115
1116    On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1117    if the destination of a SET is a hard register that isn't a user
1118    variable.
1119
1120    Before doing the above check, we first try to expand a field assignment
1121    into a set of logical operations.
1122
1123    If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1124    we place a register that is both set and used within I3.  If more than one
1125    such register is detected, we fail.
1126
1127    Return 1 if the combination is valid, zero otherwise.  */
1128
1129 static int
1130 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1131      rtx i3;
1132      rtx *loc;
1133      rtx i2dest;
1134      rtx i1dest;
1135      int i1_not_in_src;
1136      rtx *pi3dest_killed;
1137 {
1138   rtx x = *loc;
1139
1140   if (GET_CODE (x) == SET)
1141     {
1142       rtx set = expand_field_assignment (x);
1143       rtx dest = SET_DEST (set);
1144       rtx src = SET_SRC (set);
1145       rtx inner_dest = dest, inner_src = src;
1146
1147       SUBST (*loc, set);
1148
1149       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1150              || GET_CODE (inner_dest) == SUBREG
1151              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1152         inner_dest = XEXP (inner_dest, 0);
1153
1154   /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1155      was added.  */
1156 #if 0
1157       while (GET_CODE (inner_src) == STRICT_LOW_PART
1158              || GET_CODE (inner_src) == SUBREG
1159              || GET_CODE (inner_src) == ZERO_EXTRACT)
1160         inner_src = XEXP (inner_src, 0);
1161
1162       /* If it is better that two different modes keep two different pseudos,
1163          avoid combining them.  This avoids producing the following pattern
1164          on a 386:
1165           (set (subreg:SI (reg/v:QI 21) 0)
1166                (lshiftrt:SI (reg/v:SI 20)
1167                    (const_int 24)))
1168          If that were made, reload could not handle the pair of
1169          reg 20/21, since it would try to get any GENERAL_REGS
1170          but some of them don't handle QImode.  */
1171
1172       if (rtx_equal_p (inner_src, i2dest)
1173           && GET_CODE (inner_dest) == REG
1174           && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1175         return 0;
1176 #endif
1177
1178       /* Check for the case where I3 modifies its output, as
1179          discussed above.  */
1180       if ((inner_dest != dest
1181            && (reg_overlap_mentioned_p (i2dest, inner_dest)
1182                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1183
1184           /* This is the same test done in can_combine_p except that we
1185              allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1186              CALL operation. Moreover, we can't test all_adjacent; we don't
1187              have to, since this instruction will stay in place, thus we are
1188              not considering increasing the lifetime of INNER_DEST.
1189
1190              Also, if this insn sets a function argument, combining it with
1191              something that might need a spill could clobber a previous
1192              function argument; the all_adjacent test in can_combine_p also
1193              checks this; here, we do a more specific test for this case.  */
1194
1195           || (GET_CODE (inner_dest) == REG
1196               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1197               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1198                                         GET_MODE (inner_dest))
1199                  || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1200                      && ! REG_USERVAR_P (inner_dest)
1201                      && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1202                          || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1203                              && i3 != 0
1204                              && sets_function_arg_p (prev_nonnote_insn (i3)))))))
1205           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1206         return 0;
1207
1208       /* If DEST is used in I3, it is being killed in this insn,
1209          so record that for later.
1210          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1211          STACK_POINTER_REGNUM, since these are always considered to be
1212          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
1213       if (pi3dest_killed && GET_CODE (dest) == REG
1214           && reg_referenced_p (dest, PATTERN (i3))
1215           && REGNO (dest) != FRAME_POINTER_REGNUM
1216 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1217           && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1218 #endif
1219 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1220           && (REGNO (dest) != ARG_POINTER_REGNUM
1221               || ! fixed_regs [REGNO (dest)])
1222 #endif
1223           && REGNO (dest) != STACK_POINTER_REGNUM)
1224         {
1225           if (*pi3dest_killed)
1226             return 0;
1227
1228           *pi3dest_killed = dest;
1229         }
1230     }
1231
1232   else if (GET_CODE (x) == PARALLEL)
1233     {
1234       int i;
1235
1236       for (i = 0; i < XVECLEN (x, 0); i++)
1237         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1238                                 i1_not_in_src, pi3dest_killed))
1239           return 0;
1240     }
1241
1242   return 1;
1243 }
1244 \f
1245 /* Try to combine the insns I1 and I2 into I3.
1246    Here I1 and I2 appear earlier than I3.
1247    I1 can be zero; then we combine just I2 into I3.
1248
1249    It we are combining three insns and the resulting insn is not recognized,
1250    try splitting it into two insns.  If that happens, I2 and I3 are retained
1251    and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
1252    are pseudo-deleted.
1253
1254    Return 0 if the combination does not work.  Then nothing is changed.
1255    If we did the combination, return the insn at which combine should
1256    resume scanning.  */
1257
1258 static rtx
1259 try_combine (i3, i2, i1)
1260      register rtx i3, i2, i1;
1261 {
1262   /* New patterns for I3 and I3, respectively.  */
1263   rtx newpat, newi2pat = 0;
1264   /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
1265   int added_sets_1, added_sets_2;
1266   /* Total number of SETs to put into I3.  */
1267   int total_sets;
1268   /* Nonzero is I2's body now appears in I3.  */
1269   int i2_is_used;
1270   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
1271   int insn_code_number, i2_code_number, other_code_number;
1272   /* Contains I3 if the destination of I3 is used in its source, which means
1273      that the old life of I3 is being killed.  If that usage is placed into
1274      I2 and not in I3, a REG_DEAD note must be made.  */
1275   rtx i3dest_killed = 0;
1276   /* SET_DEST and SET_SRC of I2 and I1.  */
1277   rtx i2dest, i2src, i1dest = 0, i1src = 0;
1278   /* PATTERN (I2), or a copy of it in certain cases.  */
1279   rtx i2pat;
1280   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
1281   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1282   int i1_feeds_i3 = 0;
1283   /* Notes that must be added to REG_NOTES in I3 and I2.  */
1284   rtx new_i3_notes, new_i2_notes;
1285   /* Notes that we substituted I3 into I2 instead of the normal case.  */
1286   int i3_subst_into_i2 = 0;
1287   /* Notes that I1, I2 or I3 is a MULT operation.  */
1288   int have_mult = 0;
1289   /* Number of clobbers of SCRATCH we had to add.  */
1290   int i3_scratches = 0, i2_scratches = 0, other_scratches = 0;
1291
1292   int maxreg;
1293   rtx temp;
1294   register rtx link;
1295   int i;
1296
1297   /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1298      This can occur when flow deletes an insn that it has merged into an
1299      auto-increment address.  We also can't do anything if I3 has a
1300      REG_LIBCALL note since we don't want to disrupt the contiguity of a
1301      libcall.  */
1302
1303   if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1304       || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1305       || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1306       || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1307     return 0;
1308
1309   combine_attempts++;
1310
1311   undobuf.undos = undobuf.previous_undos = 0;
1312   undobuf.other_insn = 0;
1313
1314   /* Save the current high-water-mark so we can free storage if we didn't
1315      accept this combination.  */
1316   undobuf.storage = (char *) oballoc (0);
1317
1318   /* Reset the hard register usage information.  */
1319   CLEAR_HARD_REG_SET (newpat_used_regs);
1320
1321   /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
1322      code below, set I1 to be the earlier of the two insns.  */
1323   if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1324     temp = i1, i1 = i2, i2 = temp;
1325
1326   added_links_insn = 0;
1327
1328   /* First check for one important special-case that the code below will
1329      not handle.  Namely, the case where I1 is zero, I2 has multiple sets,
1330      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
1331      we may be able to replace that destination with the destination of I3.
1332      This occurs in the common code where we compute both a quotient and
1333      remainder into a structure, in which case we want to do the computation
1334      directly into the structure to avoid register-register copies.
1335
1336      We make very conservative checks below and only try to handle the
1337      most common cases of this.  For example, we only handle the case
1338      where I2 and I3 are adjacent to avoid making difficult register
1339      usage tests.  */
1340
1341   if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1342       && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1343       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1344       && (! SMALL_REGISTER_CLASSES
1345           || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1346               || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1347               || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
1348       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1349       && GET_CODE (PATTERN (i2)) == PARALLEL
1350       && ! side_effects_p (SET_DEST (PATTERN (i3)))
1351       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1352          below would need to check what is inside (and reg_overlap_mentioned_p
1353          doesn't support those codes anyway).  Don't allow those destinations;
1354          the resulting insn isn't likely to be recognized anyway.  */
1355       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1356       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1357       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1358                                     SET_DEST (PATTERN (i3)))
1359       && next_real_insn (i2) == i3)
1360     {
1361       rtx p2 = PATTERN (i2);
1362
1363       /* Make sure that the destination of I3,
1364          which we are going to substitute into one output of I2,
1365          is not used within another output of I2.  We must avoid making this:
1366          (parallel [(set (mem (reg 69)) ...)
1367                     (set (reg 69) ...)])
1368          which is not well-defined as to order of actions.
1369          (Besides, reload can't handle output reloads for this.)
1370
1371          The problem can also happen if the dest of I3 is a memory ref,
1372          if another dest in I2 is an indirect memory ref.  */
1373       for (i = 0; i < XVECLEN (p2, 0); i++)
1374         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1375              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1376             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1377                                         SET_DEST (XVECEXP (p2, 0, i))))
1378           break;
1379
1380       if (i == XVECLEN (p2, 0))
1381         for (i = 0; i < XVECLEN (p2, 0); i++)
1382           if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1383             {
1384               combine_merges++;
1385
1386               subst_insn = i3;
1387               subst_low_cuid = INSN_CUID (i2);
1388
1389               added_sets_2 = added_sets_1 = 0;
1390               i2dest = SET_SRC (PATTERN (i3));
1391
1392               /* Replace the dest in I2 with our dest and make the resulting
1393                  insn the new pattern for I3.  Then skip to where we
1394                  validate the pattern.  Everything was set up above.  */
1395               SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1396                      SET_DEST (PATTERN (i3)));
1397
1398               newpat = p2;
1399               i3_subst_into_i2 = 1;
1400               goto validate_replacement;
1401             }
1402     }
1403
1404 #ifndef HAVE_cc0
1405   /* If we have no I1 and I2 looks like:
1406         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1407                    (set Y OP)])
1408      make up a dummy I1 that is
1409         (set Y OP)
1410      and change I2 to be
1411         (set (reg:CC X) (compare:CC Y (const_int 0)))
1412
1413      (We can ignore any trailing CLOBBERs.)
1414
1415      This undoes a previous combination and allows us to match a branch-and-
1416      decrement insn.  */
1417
1418   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1419       && XVECLEN (PATTERN (i2), 0) >= 2
1420       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1421       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1422           == MODE_CC)
1423       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1424       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1425       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1426       && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1427       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1428                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1429     {
1430       for (i =  XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1431         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1432           break;
1433
1434       if (i == 1)
1435         {
1436           /* We make I1 with the same INSN_UID as I2.  This gives it
1437              the same INSN_CUID for value tracking.  Our fake I1 will
1438              never appear in the insn stream so giving it the same INSN_UID
1439              as I2 will not cause a problem.  */
1440
1441           subst_prev_insn = i1
1442             = gen_rtx (INSN, VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1443                        XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX, NULL_RTX);
1444
1445           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1446           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1447                  SET_DEST (PATTERN (i1)));
1448         }
1449     }
1450 #endif
1451
1452   /* Verify that I2 and I1 are valid for combining.  */
1453   if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1454       || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1455     {
1456       undo_all ();
1457       return 0;
1458     }
1459
1460   /* Record whether I2DEST is used in I2SRC and similarly for the other
1461      cases.  Knowing this will help in register status updating below.  */
1462   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1463   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1464   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1465
1466   /* See if I1 directly feeds into I3.  It does if I1DEST is not used
1467      in I2SRC.  */
1468   i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1469
1470   /* Ensure that I3's pattern can be the destination of combines.  */
1471   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1472                           i1 && i2dest_in_i1src && i1_feeds_i3,
1473                           &i3dest_killed))
1474     {
1475       undo_all ();
1476       return 0;
1477     }
1478
1479   /* See if any of the insns is a MULT operation.  Unless one is, we will
1480      reject a combination that is, since it must be slower.  Be conservative
1481      here.  */
1482   if (GET_CODE (i2src) == MULT
1483       || (i1 != 0 && GET_CODE (i1src) == MULT)
1484       || (GET_CODE (PATTERN (i3)) == SET
1485           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1486     have_mult = 1;
1487
1488   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1489      We used to do this EXCEPT in one case: I3 has a post-inc in an
1490      output operand.  However, that exception can give rise to insns like
1491         mov r3,(r3)+
1492      which is a famous insn on the PDP-11 where the value of r3 used as the
1493      source was model-dependent.  Avoid this sort of thing.  */
1494
1495 #if 0
1496   if (!(GET_CODE (PATTERN (i3)) == SET
1497         && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1498         && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1499         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1500             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1501     /* It's not the exception.  */
1502 #endif
1503 #ifdef AUTO_INC_DEC
1504     for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1505       if (REG_NOTE_KIND (link) == REG_INC
1506           && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1507               || (i1 != 0
1508                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1509         {
1510           undo_all ();
1511           return 0;
1512         }
1513 #endif
1514
1515   /* See if the SETs in I1 or I2 need to be kept around in the merged
1516      instruction: whenever the value set there is still needed past I3.
1517      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1518
1519      For the SET in I1, we have two cases:  If I1 and I2 independently
1520      feed into I3, the set in I1 needs to be kept around if I1DEST dies
1521      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
1522      in I1 needs to be kept around unless I1DEST dies or is set in either
1523      I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
1524      I1DEST.  If so, we know I1 feeds into I2.  */
1525
1526   added_sets_2 = ! dead_or_set_p (i3, i2dest);
1527
1528   added_sets_1
1529     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1530                : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1531
1532   /* If the set in I2 needs to be kept around, we must make a copy of
1533      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1534      PATTERN (I2), we are only substituting for the original I1DEST, not into
1535      an already-substituted copy.  This also prevents making self-referential
1536      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1537      I2DEST.  */
1538
1539   i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1540            ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1541            : PATTERN (i2));
1542
1543   if (added_sets_2)
1544     i2pat = copy_rtx (i2pat);
1545
1546   combine_merges++;
1547
1548   /* Substitute in the latest insn for the regs set by the earlier ones.  */
1549
1550   maxreg = max_reg_num ();
1551
1552   subst_insn = i3;
1553
1554   /* It is possible that the source of I2 or I1 may be performing an
1555      unneeded operation, such as a ZERO_EXTEND of something that is known
1556      to have the high part zero.  Handle that case by letting subst look at
1557      the innermost one of them.
1558
1559      Another way to do this would be to have a function that tries to
1560      simplify a single insn instead of merging two or more insns.  We don't
1561      do this because of the potential of infinite loops and because
1562      of the potential extra memory required.  However, doing it the way
1563      we are is a bit of a kludge and doesn't catch all cases.
1564
1565      But only do this if -fexpensive-optimizations since it slows things down
1566      and doesn't usually win.  */
1567
1568   if (flag_expensive_optimizations)
1569     {
1570       /* Pass pc_rtx so no substitutions are done, just simplifications.
1571          The cases that we are interested in here do not involve the few
1572          cases were is_replaced is checked.  */
1573       if (i1)
1574         {
1575           subst_low_cuid = INSN_CUID (i1);
1576           i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1577         }
1578       else
1579         {
1580           subst_low_cuid = INSN_CUID (i2);
1581           i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1582         }
1583
1584       undobuf.previous_undos = undobuf.undos;
1585     }
1586
1587 #ifndef HAVE_cc0
1588   /* Many machines that don't use CC0 have insns that can both perform an
1589      arithmetic operation and set the condition code.  These operations will
1590      be represented as a PARALLEL with the first element of the vector
1591      being a COMPARE of an arithmetic operation with the constant zero.
1592      The second element of the vector will set some pseudo to the result
1593      of the same arithmetic operation.  If we simplify the COMPARE, we won't
1594      match such a pattern and so will generate an extra insn.   Here we test
1595      for this case, where both the comparison and the operation result are
1596      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1597      I2SRC.  Later we will make the PARALLEL that contains I2.  */
1598
1599   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1600       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1601       && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1602       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1603     {
1604       rtx *cc_use;
1605       enum machine_mode compare_mode;
1606
1607       newpat = PATTERN (i3);
1608       SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1609
1610       i2_is_used = 1;
1611
1612 #ifdef EXTRA_CC_MODES
1613       /* See if a COMPARE with the operand we substituted in should be done
1614          with the mode that is currently being used.  If not, do the same
1615          processing we do in `subst' for a SET; namely, if the destination
1616          is used only once, try to replace it with a register of the proper
1617          mode and also replace the COMPARE.  */
1618       if (undobuf.other_insn == 0
1619           && (cc_use = find_single_use (SET_DEST (newpat), i3,
1620                                         &undobuf.other_insn))
1621           && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1622                                               i2src, const0_rtx))
1623               != GET_MODE (SET_DEST (newpat))))
1624         {
1625           int regno = REGNO (SET_DEST (newpat));
1626           rtx new_dest = gen_rtx (REG, compare_mode, regno);
1627
1628           if (regno < FIRST_PSEUDO_REGISTER
1629               || (REG_N_SETS (regno) == 1 && ! added_sets_2
1630                   && ! REG_USERVAR_P (SET_DEST (newpat))))
1631             {
1632               if (regno >= FIRST_PSEUDO_REGISTER)
1633                 SUBST (regno_reg_rtx[regno], new_dest);
1634
1635               SUBST (SET_DEST (newpat), new_dest);
1636               SUBST (XEXP (*cc_use, 0), new_dest);
1637               SUBST (SET_SRC (newpat),
1638                      gen_rtx_combine (COMPARE, compare_mode,
1639                                       i2src, const0_rtx));
1640             }
1641           else
1642             undobuf.other_insn = 0;
1643         }
1644 #endif
1645     }
1646   else
1647 #endif
1648     {
1649       n_occurrences = 0;                /* `subst' counts here */
1650
1651       /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1652          need to make a unique copy of I2SRC each time we substitute it
1653          to avoid self-referential rtl.  */
1654
1655       subst_low_cuid = INSN_CUID (i2);
1656       newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1657                       ! i1_feeds_i3 && i1dest_in_i1src);
1658       undobuf.previous_undos = undobuf.undos;
1659
1660       /* Record whether i2's body now appears within i3's body.  */
1661       i2_is_used = n_occurrences;
1662     }
1663
1664   /* If we already got a failure, don't try to do more.  Otherwise,
1665      try to substitute in I1 if we have it.  */
1666
1667   if (i1 && GET_CODE (newpat) != CLOBBER)
1668     {
1669       /* Before we can do this substitution, we must redo the test done
1670          above (see detailed comments there) that ensures  that I1DEST
1671          isn't mentioned in any SETs in NEWPAT that are field assignments.  */
1672
1673       if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1674                               0, NULL_PTR))
1675         {
1676           undo_all ();
1677           return 0;
1678         }
1679
1680       n_occurrences = 0;
1681       subst_low_cuid = INSN_CUID (i1);
1682       newpat = subst (newpat, i1dest, i1src, 0, 0);
1683       undobuf.previous_undos = undobuf.undos;
1684     }
1685
1686   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
1687      to count all the ways that I2SRC and I1SRC can be used.  */
1688   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1689        && i2_is_used + added_sets_2 > 1)
1690       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1691           && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1692               > 1))
1693       /* Fail if we tried to make a new register (we used to abort, but there's
1694          really no reason to).  */
1695       || max_reg_num () != maxreg
1696       /* Fail if we couldn't do something and have a CLOBBER.  */
1697       || GET_CODE (newpat) == CLOBBER
1698       /* Fail if this new pattern is a MULT and we didn't have one before
1699          at the outer level.  */
1700       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1701           && ! have_mult))
1702     {
1703       undo_all ();
1704       return 0;
1705     }
1706
1707   /* If the actions of the earlier insns must be kept
1708      in addition to substituting them into the latest one,
1709      we must make a new PARALLEL for the latest insn
1710      to hold additional the SETs.  */
1711
1712   if (added_sets_1 || added_sets_2)
1713     {
1714       combine_extras++;
1715
1716       if (GET_CODE (newpat) == PARALLEL)
1717         {
1718           rtvec old = XVEC (newpat, 0);
1719           total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1720           newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1721           bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1722                  sizeof (old->elem[0]) * old->num_elem);
1723         }
1724       else
1725         {
1726           rtx old = newpat;
1727           total_sets = 1 + added_sets_1 + added_sets_2;
1728           newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1729           XVECEXP (newpat, 0, 0) = old;
1730         }
1731
1732      if (added_sets_1)
1733        XVECEXP (newpat, 0, --total_sets)
1734          = (GET_CODE (PATTERN (i1)) == PARALLEL
1735             ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1736
1737      if (added_sets_2)
1738         {
1739           /* If there is no I1, use I2's body as is.  We used to also not do
1740              the subst call below if I2 was substituted into I3,
1741              but that could lose a simplification.  */
1742           if (i1 == 0)
1743             XVECEXP (newpat, 0, --total_sets) = i2pat;
1744           else
1745             /* See comment where i2pat is assigned.  */
1746             XVECEXP (newpat, 0, --total_sets)
1747               = subst (i2pat, i1dest, i1src, 0, 0);
1748         }
1749     }
1750
1751   /* We come here when we are replacing a destination in I2 with the
1752      destination of I3.  */
1753  validate_replacement:
1754
1755   /* Note which hard regs this insn has as inputs.  */
1756   mark_used_regs_combine (newpat);
1757
1758   /* Is the result of combination a valid instruction?  */
1759   insn_code_number
1760     = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1761
1762   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1763      the second SET's destination is a register that is unused.  In that case,
1764      we just need the first SET.   This can occur when simplifying a divmod
1765      insn.  We *must* test for this case here because the code below that
1766      splits two independent SETs doesn't handle this case correctly when it
1767      updates the register status.  Also check the case where the first
1768      SET's destination is unused.  That would not cause incorrect code, but
1769      does cause an unneeded insn to remain.  */
1770
1771   if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1772       && XVECLEN (newpat, 0) == 2
1773       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1774       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1775       && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1776       && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1777       && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1778       && asm_noperands (newpat) < 0)
1779     {
1780       newpat = XVECEXP (newpat, 0, 0);
1781       insn_code_number
1782         = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1783     }
1784
1785   else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1786            && XVECLEN (newpat, 0) == 2
1787            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1788            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1789            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1790            && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1791            && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1792            && asm_noperands (newpat) < 0)
1793     {
1794       newpat = XVECEXP (newpat, 0, 1);
1795       insn_code_number
1796         = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1797     }
1798
1799   /* If we were combining three insns and the result is a simple SET
1800      with no ASM_OPERANDS that wasn't recognized, try to split it into two
1801      insns.  There are two ways to do this.  It can be split using a
1802      machine-specific method (like when you have an addition of a large
1803      constant) or by combine in the function find_split_point.  */
1804
1805   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1806       && asm_noperands (newpat) < 0)
1807     {
1808       rtx m_split, *split;
1809       rtx ni2dest = i2dest;
1810
1811       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
1812          use I2DEST as a scratch register will help.  In the latter case,
1813          convert I2DEST to the mode of the source of NEWPAT if we can.  */
1814
1815       m_split = split_insns (newpat, i3);
1816
1817       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1818          inputs of NEWPAT.  */
1819
1820       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1821          possible to try that as a scratch reg.  This would require adding
1822          more code to make it work though.  */
1823
1824       if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1825         {
1826           /* If I2DEST is a hard register or the only use of a pseudo,
1827              we can change its mode.  */
1828           if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1829               && GET_MODE (SET_DEST (newpat)) != VOIDmode
1830               && GET_CODE (i2dest) == REG
1831               && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1832                   || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1833                       && ! REG_USERVAR_P (i2dest))))
1834             ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1835                                REGNO (i2dest));
1836
1837           m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1838                                           gen_rtvec (2, newpat,
1839                                                      gen_rtx (CLOBBER,
1840                                                               VOIDmode,
1841                                                               ni2dest))),
1842                                  i3);
1843         }
1844
1845       if (m_split && GET_CODE (m_split) == SEQUENCE
1846           && XVECLEN (m_split, 0) == 2
1847           && (next_real_insn (i2) == i3
1848               || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1849                                       INSN_CUID (i2))))
1850         {
1851           rtx i2set, i3set;
1852           rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1853           newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1854
1855           i3set = single_set (XVECEXP (m_split, 0, 1));
1856           i2set = single_set (XVECEXP (m_split, 0, 0));
1857
1858           /* In case we changed the mode of I2DEST, replace it in the
1859              pseudo-register table here.  We can't do it above in case this
1860              code doesn't get executed and we do a split the other way.  */
1861
1862           if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1863             SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1864
1865           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes,
1866                                               &i2_scratches);
1867
1868           /* If I2 or I3 has multiple SETs, we won't know how to track
1869              register status, so don't use these insns.  If I2's destination
1870              is used between I2 and I3, we also can't use these insns.  */
1871
1872           if (i2_code_number >= 0 && i2set && i3set
1873               && (next_real_insn (i2) == i3
1874                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
1875             insn_code_number = recog_for_combine (&newi3pat, i3, &new_i3_notes,
1876                                                   &i3_scratches);
1877           if (insn_code_number >= 0)
1878             newpat = newi3pat;
1879
1880           /* It is possible that both insns now set the destination of I3.
1881              If so, we must show an extra use of it.  */
1882
1883           if (insn_code_number >= 0)
1884             {
1885               rtx new_i3_dest = SET_DEST (i3set);
1886               rtx new_i2_dest = SET_DEST (i2set);
1887
1888               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1889                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1890                      || GET_CODE (new_i3_dest) == SUBREG)
1891                 new_i3_dest = XEXP (new_i3_dest, 0);
1892
1893               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
1894                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
1895                      || GET_CODE (new_i2_dest) == SUBREG)
1896                 new_i2_dest = XEXP (new_i2_dest, 0);
1897
1898               if (GET_CODE (new_i3_dest) == REG
1899                   && GET_CODE (new_i2_dest) == REG
1900                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
1901                 REG_N_SETS (REGNO (new_i2_dest))++;
1902             }
1903         }
1904
1905       /* If we can split it and use I2DEST, go ahead and see if that
1906          helps things be recognized.  Verify that none of the registers
1907          are set between I2 and I3.  */
1908       if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1909 #ifdef HAVE_cc0
1910           && GET_CODE (i2dest) == REG
1911 #endif
1912           /* We need I2DEST in the proper mode.  If it is a hard register
1913              or the only use of a pseudo, we can change its mode.  */
1914           && (GET_MODE (*split) == GET_MODE (i2dest)
1915               || GET_MODE (*split) == VOIDmode
1916               || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1917               || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1918                   && ! REG_USERVAR_P (i2dest)))
1919           && (next_real_insn (i2) == i3
1920               || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1921           /* We can't overwrite I2DEST if its value is still used by
1922              NEWPAT.  */
1923           && ! reg_referenced_p (i2dest, newpat))
1924         {
1925           rtx newdest = i2dest;
1926           enum rtx_code split_code = GET_CODE (*split);
1927           enum machine_mode split_mode = GET_MODE (*split);
1928
1929           /* Get NEWDEST as a register in the proper mode.  We have already
1930              validated that we can do this.  */
1931           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
1932             {
1933               newdest = gen_rtx (REG, split_mode, REGNO (i2dest));
1934
1935               if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1936                 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1937             }
1938
1939           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1940              an ASHIFT.  This can occur if it was inside a PLUS and hence
1941              appeared to be a memory address.  This is a kludge.  */
1942           if (split_code == MULT
1943               && GET_CODE (XEXP (*split, 1)) == CONST_INT
1944               && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1945             {
1946               SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
1947                                               XEXP (*split, 0), GEN_INT (i)));
1948               /* Update split_code because we may not have a multiply
1949                  anymore.  */
1950               split_code = GET_CODE (*split);
1951             }
1952
1953 #ifdef INSN_SCHEDULING
1954           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1955              be written as a ZERO_EXTEND.  */
1956           if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
1957             SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
1958                                             XEXP (*split, 0)));
1959 #endif
1960
1961           newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1962           SUBST (*split, newdest);
1963           i2_code_number
1964             = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
1965
1966           /* If the split point was a MULT and we didn't have one before,
1967              don't use one now.  */
1968           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
1969             insn_code_number
1970               = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1971         }
1972     }
1973
1974   /* Check for a case where we loaded from memory in a narrow mode and
1975      then sign extended it, but we need both registers.  In that case,
1976      we have a PARALLEL with both loads from the same memory location.
1977      We can split this into a load from memory followed by a register-register
1978      copy.  This saves at least one insn, more if register allocation can
1979      eliminate the copy.
1980
1981      We cannot do this if the destination of the second assignment is
1982      a register that we have already assumed is zero-extended.  Similarly
1983      for a SUBREG of such a register.  */
1984
1985   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1986            && GET_CODE (newpat) == PARALLEL
1987            && XVECLEN (newpat, 0) == 2
1988            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1989            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1990            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1991            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1992                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1993            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1994                                    INSN_CUID (i2))
1995            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1996            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1997            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
1998                  (GET_CODE (temp) == REG
1999                   && reg_nonzero_bits[REGNO (temp)] != 0
2000                   && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2001                   && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2002                   && (reg_nonzero_bits[REGNO (temp)]
2003                       != GET_MODE_MASK (word_mode))))
2004            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2005                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2006                      (GET_CODE (temp) == REG
2007                       && reg_nonzero_bits[REGNO (temp)] != 0
2008                       && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2009                       && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2010                       && (reg_nonzero_bits[REGNO (temp)]
2011                           != GET_MODE_MASK (word_mode)))))
2012            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2013                                          SET_SRC (XVECEXP (newpat, 0, 1)))
2014            && ! find_reg_note (i3, REG_UNUSED,
2015                                SET_DEST (XVECEXP (newpat, 0, 0))))
2016     {
2017       rtx ni2dest;
2018
2019       newi2pat = XVECEXP (newpat, 0, 0);
2020       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2021       newpat = XVECEXP (newpat, 0, 1);
2022       SUBST (SET_SRC (newpat),
2023              gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2024       i2_code_number
2025         = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2026
2027       if (i2_code_number >= 0)
2028         insn_code_number
2029           = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2030
2031       if (insn_code_number >= 0)
2032         {
2033           rtx insn;
2034           rtx link;
2035
2036           /* If we will be able to accept this, we have made a change to the
2037              destination of I3.  This can invalidate a LOG_LINKS pointing
2038              to I3.  No other part of combine.c makes such a transformation.
2039
2040              The new I3 will have a destination that was previously the
2041              destination of I1 or I2 and which was used in i2 or I3.  Call
2042              distribute_links to make a LOG_LINK from the next use of
2043              that destination.  */
2044
2045           PATTERN (i3) = newpat;
2046           distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
2047
2048           /* I3 now uses what used to be its destination and which is
2049              now I2's destination.  That means we need a LOG_LINK from
2050              I3 to I2.  But we used to have one, so we still will.
2051
2052              However, some later insn might be using I2's dest and have
2053              a LOG_LINK pointing at I3.  We must remove this link.
2054              The simplest way to remove the link is to point it at I1,
2055              which we know will be a NOTE.  */
2056
2057           for (insn = NEXT_INSN (i3);
2058                insn && (this_basic_block == n_basic_blocks - 1
2059                         || insn != basic_block_head[this_basic_block + 1]);
2060                insn = NEXT_INSN (insn))
2061             {
2062               if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2063                   && reg_referenced_p (ni2dest, PATTERN (insn)))
2064                 {
2065                   for (link = LOG_LINKS (insn); link;
2066                        link = XEXP (link, 1))
2067                     if (XEXP (link, 0) == i3)
2068                       XEXP (link, 0) = i1;
2069
2070                   break;
2071                 }
2072             }
2073         }
2074     }
2075
2076   /* Similarly, check for a case where we have a PARALLEL of two independent
2077      SETs but we started with three insns.  In this case, we can do the sets
2078      as two separate insns.  This case occurs when some SET allows two
2079      other insns to combine, but the destination of that SET is still live.  */
2080
2081   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2082            && GET_CODE (newpat) == PARALLEL
2083            && XVECLEN (newpat, 0) == 2
2084            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2085            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2086            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2087            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2088            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2089            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2090            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2091                                    INSN_CUID (i2))
2092            /* Don't pass sets with (USE (MEM ...)) dests to the following.  */
2093            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2094            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2095            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2096                                   XVECEXP (newpat, 0, 0))
2097            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2098                                   XVECEXP (newpat, 0, 1)))
2099     {
2100       /* Normally, it doesn't matter which of the two is done first,
2101          but it does if one references cc0.  In that case, it has to
2102          be first.  */
2103 #ifdef HAVE_cc0
2104       if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2105         {
2106           newi2pat = XVECEXP (newpat, 0, 0);
2107           newpat = XVECEXP (newpat, 0, 1);
2108         }
2109       else
2110 #endif
2111         {
2112           newi2pat = XVECEXP (newpat, 0, 1);
2113           newpat = XVECEXP (newpat, 0, 0);
2114         }
2115
2116       i2_code_number
2117         = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2118
2119       if (i2_code_number >= 0)
2120         insn_code_number
2121           = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2122     }
2123
2124   /* If it still isn't recognized, fail and change things back the way they
2125      were.  */
2126   if ((insn_code_number < 0
2127        /* Is the result a reasonable ASM_OPERANDS?  */
2128        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2129     {
2130       undo_all ();
2131       return 0;
2132     }
2133
2134   /* If we had to change another insn, make sure it is valid also.  */
2135   if (undobuf.other_insn)
2136     {
2137       rtx other_pat = PATTERN (undobuf.other_insn);
2138       rtx new_other_notes;
2139       rtx note, next;
2140
2141       CLEAR_HARD_REG_SET (newpat_used_regs);
2142
2143       other_code_number
2144         = recog_for_combine (&other_pat, undobuf.other_insn,
2145                              &new_other_notes, &other_scratches);
2146
2147       if (other_code_number < 0 && ! check_asm_operands (other_pat))
2148         {
2149           undo_all ();
2150           return 0;
2151         }
2152
2153       PATTERN (undobuf.other_insn) = other_pat;
2154
2155       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2156          are still valid.  Then add any non-duplicate notes added by
2157          recog_for_combine.  */
2158       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2159         {
2160           next = XEXP (note, 1);
2161
2162           if (REG_NOTE_KIND (note) == REG_UNUSED
2163               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2164             {
2165               if (GET_CODE (XEXP (note, 0)) == REG)
2166                 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2167
2168               remove_note (undobuf.other_insn, note);
2169             }
2170         }
2171
2172       for (note = new_other_notes; note; note = XEXP (note, 1))
2173         if (GET_CODE (XEXP (note, 0)) == REG)
2174           REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2175
2176       distribute_notes (new_other_notes, undobuf.other_insn,
2177                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2178     }
2179
2180   /* We now know that we can do this combination.  Merge the insns and
2181      update the status of registers and LOG_LINKS.  */
2182
2183   {
2184     rtx i3notes, i2notes, i1notes = 0;
2185     rtx i3links, i2links, i1links = 0;
2186     rtx midnotes = 0;
2187     register int regno;
2188     /* Compute which registers we expect to eliminate.  */
2189     rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
2190                    ? 0 : i2dest);
2191     rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
2192
2193     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2194        clear them.  */
2195     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2196     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2197     if (i1)
2198       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2199
2200     /* Ensure that we do not have something that should not be shared but
2201        occurs multiple times in the new insns.  Check this by first
2202        resetting all the `used' flags and then copying anything is shared.  */
2203
2204     reset_used_flags (i3notes);
2205     reset_used_flags (i2notes);
2206     reset_used_flags (i1notes);
2207     reset_used_flags (newpat);
2208     reset_used_flags (newi2pat);
2209     if (undobuf.other_insn)
2210       reset_used_flags (PATTERN (undobuf.other_insn));
2211
2212     i3notes = copy_rtx_if_shared (i3notes);
2213     i2notes = copy_rtx_if_shared (i2notes);
2214     i1notes = copy_rtx_if_shared (i1notes);
2215     newpat = copy_rtx_if_shared (newpat);
2216     newi2pat = copy_rtx_if_shared (newi2pat);
2217     if (undobuf.other_insn)
2218       reset_used_flags (PATTERN (undobuf.other_insn));
2219
2220     INSN_CODE (i3) = insn_code_number;
2221     PATTERN (i3) = newpat;
2222     if (undobuf.other_insn)
2223       INSN_CODE (undobuf.other_insn) = other_code_number;
2224
2225     /* We had one special case above where I2 had more than one set and
2226        we replaced a destination of one of those sets with the destination
2227        of I3.  In that case, we have to update LOG_LINKS of insns later
2228        in this basic block.  Note that this (expensive) case is rare.
2229
2230        Also, in this case, we must pretend that all REG_NOTEs for I2
2231        actually came from I3, so that REG_UNUSED notes from I2 will be
2232        properly handled.  */
2233
2234     if (i3_subst_into_i2)
2235       {
2236         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2237           if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2238               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2239               && ! find_reg_note (i2, REG_UNUSED,
2240                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2241             for (temp = NEXT_INSN (i2);
2242                  temp && (this_basic_block == n_basic_blocks - 1
2243                           || basic_block_head[this_basic_block] != temp);
2244                  temp = NEXT_INSN (temp))
2245               if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2246                 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2247                   if (XEXP (link, 0) == i2)
2248                     XEXP (link, 0) = i3;
2249
2250         if (i3notes)
2251           {
2252             rtx link = i3notes;
2253             while (XEXP (link, 1))
2254               link = XEXP (link, 1);
2255             XEXP (link, 1) = i2notes;
2256           }
2257         else
2258           i3notes = i2notes;
2259         i2notes = 0;
2260       }
2261
2262     LOG_LINKS (i3) = 0;
2263     REG_NOTES (i3) = 0;
2264     LOG_LINKS (i2) = 0;
2265     REG_NOTES (i2) = 0;
2266
2267     if (newi2pat)
2268       {
2269         INSN_CODE (i2) = i2_code_number;
2270         PATTERN (i2) = newi2pat;
2271       }
2272     else
2273       {
2274         PUT_CODE (i2, NOTE);
2275         NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2276         NOTE_SOURCE_FILE (i2) = 0;
2277       }
2278
2279     if (i1)
2280       {
2281         LOG_LINKS (i1) = 0;
2282         REG_NOTES (i1) = 0;
2283         PUT_CODE (i1, NOTE);
2284         NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2285         NOTE_SOURCE_FILE (i1) = 0;
2286       }
2287
2288     /* Get death notes for everything that is now used in either I3 or
2289        I2 and used to die in a previous insn.  If we built two new
2290        patterns, move from I1 to I2 then I2 to I3 so that we get the
2291        proper movement on registers that I2 modifies.  */
2292
2293     if (newi2pat)
2294       {
2295         move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2296         move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2297       }
2298     else
2299       move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2300                    i3, &midnotes);
2301
2302     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
2303     if (i3notes)
2304       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2305                         elim_i2, elim_i1);
2306     if (i2notes)
2307       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2308                         elim_i2, elim_i1);
2309     if (i1notes)
2310       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2311                         elim_i2, elim_i1);
2312     if (midnotes)
2313       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2314                         elim_i2, elim_i1);
2315
2316     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
2317        know these are REG_UNUSED and want them to go to the desired insn,
2318        so we always pass it as i3.  We have not counted the notes in
2319        reg_n_deaths yet, so we need to do so now.  */
2320
2321     if (newi2pat && new_i2_notes)
2322       {
2323         for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2324           if (GET_CODE (XEXP (temp, 0)) == REG)
2325             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2326
2327         distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2328       }
2329
2330     if (new_i3_notes)
2331       {
2332         for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2333           if (GET_CODE (XEXP (temp, 0)) == REG)
2334             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2335
2336         distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2337       }
2338
2339     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
2340        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
2341        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
2342        in that case, it might delete I2.  Similarly for I2 and I1.
2343        Show an additional death due to the REG_DEAD note we make here.  If
2344        we discard it in distribute_notes, we will decrement it again.  */
2345
2346     if (i3dest_killed)
2347       {
2348         if (GET_CODE (i3dest_killed) == REG)
2349           REG_N_DEATHS (REGNO (i3dest_killed))++;
2350
2351         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2352           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2353                                      NULL_RTX),
2354                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2355         else
2356           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2357                                      NULL_RTX),
2358                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2359                             NULL_RTX, NULL_RTX);
2360       }
2361
2362     if (i2dest_in_i2src)
2363       {
2364         if (GET_CODE (i2dest) == REG)
2365           REG_N_DEATHS (REGNO (i2dest))++;
2366
2367         if (newi2pat && reg_set_p (i2dest, newi2pat))
2368           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2369                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2370         else
2371           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2372                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2373                             NULL_RTX, NULL_RTX);
2374       }
2375
2376     if (i1dest_in_i1src)
2377       {
2378         if (GET_CODE (i1dest) == REG)
2379           REG_N_DEATHS (REGNO (i1dest))++;
2380
2381         if (newi2pat && reg_set_p (i1dest, newi2pat))
2382           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2383                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2384         else
2385           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2386                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2387                             NULL_RTX, NULL_RTX);
2388       }
2389
2390     distribute_links (i3links);
2391     distribute_links (i2links);
2392     distribute_links (i1links);
2393
2394     if (GET_CODE (i2dest) == REG)
2395       {
2396         rtx link;
2397         rtx i2_insn = 0, i2_val = 0, set;
2398
2399         /* The insn that used to set this register doesn't exist, and
2400            this life of the register may not exist either.  See if one of
2401            I3's links points to an insn that sets I2DEST.  If it does,
2402            that is now the last known value for I2DEST. If we don't update
2403            this and I2 set the register to a value that depended on its old
2404            contents, we will get confused.  If this insn is used, thing
2405            will be set correctly in combine_instructions.  */
2406
2407         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2408           if ((set = single_set (XEXP (link, 0))) != 0
2409               && rtx_equal_p (i2dest, SET_DEST (set)))
2410             i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2411
2412         record_value_for_reg (i2dest, i2_insn, i2_val);
2413
2414         /* If the reg formerly set in I2 died only once and that was in I3,
2415            zero its use count so it won't make `reload' do any work.  */
2416         if (! added_sets_2
2417             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2418             && ! i2dest_in_i2src)
2419           {
2420             regno = REGNO (i2dest);
2421             REG_N_SETS (regno)--;
2422             if (REG_N_SETS (regno) == 0
2423                 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
2424               REG_N_REFS (regno) = 0;
2425           }
2426       }
2427
2428     if (i1 && GET_CODE (i1dest) == REG)
2429       {
2430         rtx link;
2431         rtx i1_insn = 0, i1_val = 0, set;
2432
2433         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2434           if ((set = single_set (XEXP (link, 0))) != 0
2435               && rtx_equal_p (i1dest, SET_DEST (set)))
2436             i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2437
2438         record_value_for_reg (i1dest, i1_insn, i1_val);
2439
2440         regno = REGNO (i1dest);
2441         if (! added_sets_1 && ! i1dest_in_i1src)
2442           {
2443             REG_N_SETS (regno)--;
2444             if (REG_N_SETS (regno) == 0
2445                 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
2446               REG_N_REFS (regno) = 0;
2447           }
2448       }
2449
2450     /* Update reg_nonzero_bits et al for any changes that may have been made
2451        to this insn.  */
2452
2453     note_stores (newpat, set_nonzero_bits_and_sign_copies);
2454     if (newi2pat)
2455       note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2456
2457     /* If we added any (clobber (scratch)), add them to the max for a
2458        block.  This is a very pessimistic calculation, since we might
2459        have had them already and this might not be the worst block, but
2460        it's not worth doing any better.  */
2461     max_scratch += i3_scratches + i2_scratches + other_scratches;
2462
2463     /* If I3 is now an unconditional jump, ensure that it has a
2464        BARRIER following it since it may have initially been a
2465        conditional jump.  It may also be the last nonnote insn.  */
2466
2467     if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2468         && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2469             || GET_CODE (temp) != BARRIER))
2470       emit_barrier_after (i3);
2471   }
2472
2473   combine_successes++;
2474
2475   /* Clear this here, so that subsequent get_last_value calls are not
2476      affected.  */
2477   subst_prev_insn = NULL_RTX;
2478
2479   if (added_links_insn
2480       && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2481       && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2482     return added_links_insn;
2483   else
2484     return newi2pat ? i2 : i3;
2485 }
2486 \f
2487 /* Undo all the modifications recorded in undobuf.  */
2488
2489 static void
2490 undo_all ()
2491 {
2492   struct undo *undo, *next;
2493
2494   for (undo = undobuf.undos; undo; undo = next)
2495     {
2496       next = undo->next;
2497       if (undo->is_int)
2498         *undo->where.i = undo->old_contents.i;
2499       else
2500         *undo->where.r = undo->old_contents.r;
2501
2502       undo->next = undobuf.frees;
2503       undobuf.frees = undo;
2504     }
2505
2506   obfree (undobuf.storage);
2507   undobuf.undos = undobuf.previous_undos = 0;
2508
2509   /* Clear this here, so that subsequent get_last_value calls are not
2510      affected.  */
2511   subst_prev_insn = NULL_RTX;
2512 }
2513 \f
2514 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2515    where we have an arithmetic expression and return that point.  LOC will
2516    be inside INSN.
2517
2518    try_combine will call this function to see if an insn can be split into
2519    two insns.  */
2520
2521 static rtx *
2522 find_split_point (loc, insn)
2523      rtx *loc;
2524      rtx insn;
2525 {
2526   rtx x = *loc;
2527   enum rtx_code code = GET_CODE (x);
2528   rtx *split;
2529   int len = 0, pos, unsignedp;
2530   rtx inner;
2531
2532   /* First special-case some codes.  */
2533   switch (code)
2534     {
2535     case SUBREG:
2536 #ifdef INSN_SCHEDULING
2537       /* If we are making a paradoxical SUBREG invalid, it becomes a split
2538          point.  */
2539       if (GET_CODE (SUBREG_REG (x)) == MEM)
2540         return loc;
2541 #endif
2542       return find_split_point (&SUBREG_REG (x), insn);
2543
2544     case MEM:
2545 #ifdef HAVE_lo_sum
2546       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2547          using LO_SUM and HIGH.  */
2548       if (GET_CODE (XEXP (x, 0)) == CONST
2549           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2550         {
2551           SUBST (XEXP (x, 0),
2552                  gen_rtx_combine (LO_SUM, Pmode,
2553                                   gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2554                                   XEXP (x, 0)));
2555           return &XEXP (XEXP (x, 0), 0);
2556         }
2557 #endif
2558
2559       /* If we have a PLUS whose second operand is a constant and the
2560          address is not valid, perhaps will can split it up using
2561          the machine-specific way to split large constants.  We use
2562          the first pseudo-reg (one of the virtual regs) as a placeholder;
2563          it will not remain in the result.  */
2564       if (GET_CODE (XEXP (x, 0)) == PLUS
2565           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2566           && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2567         {
2568           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2569           rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2570                                  subst_insn);
2571
2572           /* This should have produced two insns, each of which sets our
2573              placeholder.  If the source of the second is a valid address,
2574              we can make put both sources together and make a split point
2575              in the middle.  */
2576
2577           if (seq && XVECLEN (seq, 0) == 2
2578               && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2579               && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2580               && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2581               && ! reg_mentioned_p (reg,
2582                                     SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2583               && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2584               && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2585               && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2586               && memory_address_p (GET_MODE (x),
2587                                    SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2588             {
2589               rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2590               rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2591
2592               /* Replace the placeholder in SRC2 with SRC1.  If we can
2593                  find where in SRC2 it was placed, that can become our
2594                  split point and we can replace this address with SRC2.
2595                  Just try two obvious places.  */
2596
2597               src2 = replace_rtx (src2, reg, src1);
2598               split = 0;
2599               if (XEXP (src2, 0) == src1)
2600                 split = &XEXP (src2, 0);
2601               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2602                        && XEXP (XEXP (src2, 0), 0) == src1)
2603                 split = &XEXP (XEXP (src2, 0), 0);
2604
2605               if (split)
2606                 {
2607                   SUBST (XEXP (x, 0), src2);
2608                   return split;
2609                 }
2610             }
2611
2612           /* If that didn't work, perhaps the first operand is complex and
2613              needs to be computed separately, so make a split point there.
2614              This will occur on machines that just support REG + CONST
2615              and have a constant moved through some previous computation.  */
2616
2617           else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2618                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2619                          && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2620                              == 'o')))
2621             return &XEXP (XEXP (x, 0), 0);
2622         }
2623       break;
2624
2625     case SET:
2626 #ifdef HAVE_cc0
2627       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2628          ZERO_EXTRACT, the most likely reason why this doesn't match is that
2629          we need to put the operand into a register.  So split at that
2630          point.  */
2631
2632       if (SET_DEST (x) == cc0_rtx
2633           && GET_CODE (SET_SRC (x)) != COMPARE
2634           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2635           && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2636           && ! (GET_CODE (SET_SRC (x)) == SUBREG
2637                 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2638         return &SET_SRC (x);
2639 #endif
2640
2641       /* See if we can split SET_SRC as it stands.  */
2642       split = find_split_point (&SET_SRC (x), insn);
2643       if (split && split != &SET_SRC (x))
2644         return split;
2645
2646       /* See if we can split SET_DEST as it stands.  */
2647       split = find_split_point (&SET_DEST (x), insn);
2648       if (split && split != &SET_DEST (x))
2649         return split;
2650
2651       /* See if this is a bitfield assignment with everything constant.  If
2652          so, this is an IOR of an AND, so split it into that.  */
2653       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2654           && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2655               <= HOST_BITS_PER_WIDE_INT)
2656           && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2657           && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2658           && GET_CODE (SET_SRC (x)) == CONST_INT
2659           && ((INTVAL (XEXP (SET_DEST (x), 1))
2660               + INTVAL (XEXP (SET_DEST (x), 2)))
2661               <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2662           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2663         {
2664           int pos = INTVAL (XEXP (SET_DEST (x), 2));
2665           int len = INTVAL (XEXP (SET_DEST (x), 1));
2666           int src = INTVAL (SET_SRC (x));
2667           rtx dest = XEXP (SET_DEST (x), 0);
2668           enum machine_mode mode = GET_MODE (dest);
2669           unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2670
2671           if (BITS_BIG_ENDIAN)
2672             pos = GET_MODE_BITSIZE (mode) - len - pos;
2673
2674           if (src == mask)
2675             SUBST (SET_SRC (x),
2676                    gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2677           else
2678             SUBST (SET_SRC (x),
2679                    gen_binary (IOR, mode,
2680                                gen_binary (AND, mode, dest,
2681                                            GEN_INT (~ (mask << pos)
2682                                                     & GET_MODE_MASK (mode))),
2683                                GEN_INT (src << pos)));
2684
2685           SUBST (SET_DEST (x), dest);
2686
2687           split = find_split_point (&SET_SRC (x), insn);
2688           if (split && split != &SET_SRC (x))
2689             return split;
2690         }
2691
2692       /* Otherwise, see if this is an operation that we can split into two.
2693          If so, try to split that.  */
2694       code = GET_CODE (SET_SRC (x));
2695
2696       switch (code)
2697         {
2698         case AND:
2699           /* If we are AND'ing with a large constant that is only a single
2700              bit and the result is only being used in a context where we
2701              need to know if it is zero or non-zero, replace it with a bit
2702              extraction.  This will avoid the large constant, which might
2703              have taken more than one insn to make.  If the constant were
2704              not a valid argument to the AND but took only one insn to make,
2705              this is no worse, but if it took more than one insn, it will
2706              be better.  */
2707
2708           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2709               && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2710               && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2711               && GET_CODE (SET_DEST (x)) == REG
2712               && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2713               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2714               && XEXP (*split, 0) == SET_DEST (x)
2715               && XEXP (*split, 1) == const0_rtx)
2716             {
2717               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2718                                                 XEXP (SET_SRC (x), 0),
2719                                                 pos, NULL_RTX, 1, 1, 0, 0);
2720               if (extraction != 0)
2721                 {
2722                   SUBST (SET_SRC (x), extraction);
2723                   return find_split_point (loc, insn);
2724                 }
2725             }
2726           break;
2727
2728         case NE:
2729           /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2730              is known to be on, this can be converted into a NEG of a shift. */
2731           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2732               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
2733               && 1 <= (pos = exact_log2
2734                        (nonzero_bits (XEXP (SET_SRC (x), 0),
2735                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
2736             {
2737               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2738
2739               SUBST (SET_SRC (x),
2740                      gen_rtx_combine (NEG, mode,
2741                                       gen_rtx_combine (LSHIFTRT, mode,
2742                                                        XEXP (SET_SRC (x), 0),
2743                                                        GEN_INT (pos))));
2744
2745               split = find_split_point (&SET_SRC (x), insn);
2746               if (split && split != &SET_SRC (x))
2747                 return split;
2748             }
2749           break;
2750
2751         case SIGN_EXTEND:
2752           inner = XEXP (SET_SRC (x), 0);
2753
2754           /* We can't optimize if either mode is a partial integer
2755              mode as we don't know how many bits are significant
2756              in those modes.  */
2757           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
2758               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
2759             break;
2760
2761           pos = 0;
2762           len = GET_MODE_BITSIZE (GET_MODE (inner));
2763           unsignedp = 0;
2764           break;
2765
2766         case SIGN_EXTRACT:
2767         case ZERO_EXTRACT:
2768           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2769               && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2770             {
2771               inner = XEXP (SET_SRC (x), 0);
2772               len = INTVAL (XEXP (SET_SRC (x), 1));
2773               pos = INTVAL (XEXP (SET_SRC (x), 2));
2774
2775               if (BITS_BIG_ENDIAN)
2776                 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2777               unsignedp = (code == ZERO_EXTRACT);
2778             }
2779           break;
2780
2781         default:
2782           break;
2783         }
2784
2785       if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2786         {
2787           enum machine_mode mode = GET_MODE (SET_SRC (x));
2788
2789           /* For unsigned, we have a choice of a shift followed by an
2790              AND or two shifts.  Use two shifts for field sizes where the
2791              constant might be too large.  We assume here that we can
2792              always at least get 8-bit constants in an AND insn, which is
2793              true for every current RISC.  */
2794
2795           if (unsignedp && len <= 8)
2796             {
2797               SUBST (SET_SRC (x),
2798                      gen_rtx_combine
2799                      (AND, mode,
2800                       gen_rtx_combine (LSHIFTRT, mode,
2801                                        gen_lowpart_for_combine (mode, inner),
2802                                        GEN_INT (pos)),
2803                       GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2804
2805               split = find_split_point (&SET_SRC (x), insn);
2806               if (split && split != &SET_SRC (x))
2807                 return split;
2808             }
2809           else
2810             {
2811               SUBST (SET_SRC (x),
2812                      gen_rtx_combine
2813                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2814                       gen_rtx_combine (ASHIFT, mode,
2815                                        gen_lowpart_for_combine (mode, inner),
2816                                        GEN_INT (GET_MODE_BITSIZE (mode)
2817                                                 - len - pos)),
2818                       GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2819
2820               split = find_split_point (&SET_SRC (x), insn);
2821               if (split && split != &SET_SRC (x))
2822                 return split;
2823             }
2824         }
2825
2826       /* See if this is a simple operation with a constant as the second
2827          operand.  It might be that this constant is out of range and hence
2828          could be used as a split point.  */
2829       if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2830            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2831            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2832           && CONSTANT_P (XEXP (SET_SRC (x), 1))
2833           && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2834               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2835                   && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2836                       == 'o'))))
2837         return &XEXP (SET_SRC (x), 1);
2838
2839       /* Finally, see if this is a simple operation with its first operand
2840          not in a register.  The operation might require this operand in a
2841          register, so return it as a split point.  We can always do this
2842          because if the first operand were another operation, we would have
2843          already found it as a split point.  */
2844       if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2845            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2846            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2847            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2848           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2849         return &XEXP (SET_SRC (x), 0);
2850
2851       return 0;
2852
2853     case AND:
2854     case IOR:
2855       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2856          it is better to write this as (not (ior A B)) so we can split it.
2857          Similarly for IOR.  */
2858       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2859         {
2860           SUBST (*loc,
2861                  gen_rtx_combine (NOT, GET_MODE (x),
2862                                   gen_rtx_combine (code == IOR ? AND : IOR,
2863                                                    GET_MODE (x),
2864                                                    XEXP (XEXP (x, 0), 0),
2865                                                    XEXP (XEXP (x, 1), 0))));
2866           return find_split_point (loc, insn);
2867         }
2868
2869       /* Many RISC machines have a large set of logical insns.  If the
2870          second operand is a NOT, put it first so we will try to split the
2871          other operand first.  */
2872       if (GET_CODE (XEXP (x, 1)) == NOT)
2873         {
2874           rtx tem = XEXP (x, 0);
2875           SUBST (XEXP (x, 0), XEXP (x, 1));
2876           SUBST (XEXP (x, 1), tem);
2877         }
2878       break;
2879
2880     default:
2881       break;
2882     }
2883
2884   /* Otherwise, select our actions depending on our rtx class.  */
2885   switch (GET_RTX_CLASS (code))
2886     {
2887     case 'b':                   /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
2888     case '3':
2889       split = find_split_point (&XEXP (x, 2), insn);
2890       if (split)
2891         return split;
2892       /* ... fall through ...  */
2893     case '2':
2894     case 'c':
2895     case '<':
2896       split = find_split_point (&XEXP (x, 1), insn);
2897       if (split)
2898         return split;
2899       /* ... fall through ...  */
2900     case '1':
2901       /* Some machines have (and (shift ...) ...) insns.  If X is not
2902          an AND, but XEXP (X, 0) is, use it as our split point.  */
2903       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2904         return &XEXP (x, 0);
2905
2906       split = find_split_point (&XEXP (x, 0), insn);
2907       if (split)
2908         return split;
2909       return loc;
2910     }
2911
2912   /* Otherwise, we don't have a split point.  */
2913   return 0;
2914 }
2915 \f
2916 /* Throughout X, replace FROM with TO, and return the result.
2917    The result is TO if X is FROM;
2918    otherwise the result is X, but its contents may have been modified.
2919    If they were modified, a record was made in undobuf so that
2920    undo_all will (among other things) return X to its original state.
2921
2922    If the number of changes necessary is too much to record to undo,
2923    the excess changes are not made, so the result is invalid.
2924    The changes already made can still be undone.
2925    undobuf.num_undo is incremented for such changes, so by testing that
2926    the caller can tell whether the result is valid.
2927
2928    `n_occurrences' is incremented each time FROM is replaced.
2929
2930    IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2931
2932    UNIQUE_COPY is non-zero if each substitution must be unique.  We do this
2933    by copying if `n_occurrences' is non-zero.  */
2934
2935 static rtx
2936 subst (x, from, to, in_dest, unique_copy)
2937      register rtx x, from, to;
2938      int in_dest;
2939      int unique_copy;
2940 {
2941   register enum rtx_code code = GET_CODE (x);
2942   enum machine_mode op0_mode = VOIDmode;
2943   register char *fmt;
2944   register int len, i;
2945   rtx new;
2946
2947 /* Two expressions are equal if they are identical copies of a shared
2948    RTX or if they are both registers with the same register number
2949    and mode.  */
2950
2951 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
2952   ((X) == (Y)                                           \
2953    || (GET_CODE (X) == REG && GET_CODE (Y) == REG       \
2954        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2955
2956   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2957     {
2958       n_occurrences++;
2959       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2960     }
2961
2962   /* If X and FROM are the same register but different modes, they will
2963      not have been seen as equal above.  However, flow.c will make a
2964      LOG_LINKS entry for that case.  If we do nothing, we will try to
2965      rerecognize our original insn and, when it succeeds, we will
2966      delete the feeding insn, which is incorrect.
2967
2968      So force this insn not to match in this (rare) case.  */
2969   if (! in_dest && code == REG && GET_CODE (from) == REG
2970       && REGNO (x) == REGNO (from))
2971     return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2972
2973   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2974      of which may contain things that can be combined.  */
2975   if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2976     return x;
2977
2978   /* It is possible to have a subexpression appear twice in the insn.
2979      Suppose that FROM is a register that appears within TO.
2980      Then, after that subexpression has been scanned once by `subst',
2981      the second time it is scanned, TO may be found.  If we were
2982      to scan TO here, we would find FROM within it and create a
2983      self-referent rtl structure which is completely wrong.  */
2984   if (COMBINE_RTX_EQUAL_P (x, to))
2985     return to;
2986
2987   len = GET_RTX_LENGTH (code);
2988   fmt = GET_RTX_FORMAT (code);
2989
2990   /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2991      set up to skip this common case.  All other cases where we want to
2992      suppress replacing something inside a SET_SRC are handled via the
2993      IN_DEST operand.  */
2994   if (code == SET
2995       && (GET_CODE (SET_DEST (x)) == REG
2996         || GET_CODE (SET_DEST (x)) == CC0
2997         || GET_CODE (SET_DEST (x)) == PC))
2998     fmt = "ie";
2999
3000   /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3001      constant.  */
3002   if (fmt[0] == 'e')
3003     op0_mode = GET_MODE (XEXP (x, 0));
3004
3005   for (i = 0; i < len; i++)
3006     {
3007       if (fmt[i] == 'E')
3008         {
3009           register int j;
3010           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3011             {
3012               if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3013                 {
3014                   new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3015                   n_occurrences++;
3016                 }
3017               else
3018                 {
3019                   new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
3020
3021                   /* If this substitution failed, this whole thing fails.  */
3022                   if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3023                     return new;
3024                 }
3025
3026               SUBST (XVECEXP (x, i, j), new);
3027             }
3028         }
3029       else if (fmt[i] == 'e')
3030         {
3031           if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3032             {
3033               /* In general, don't install a subreg involving two modes not
3034                  tieable.  It can worsen register allocation, and can even
3035                  make invalid reload insns, since the reg inside may need to
3036                  be copied from in the outside mode, and that may be invalid
3037                  if it is an fp reg copied in integer mode.
3038
3039                  We allow two exceptions to this: It is valid if it is inside
3040                  another SUBREG and the mode of that SUBREG and the mode of
3041                  the inside of TO is tieable and it is valid if X is a SET
3042                  that copies FROM to CC0.  */
3043               if (GET_CODE (to) == SUBREG
3044                   && ! MODES_TIEABLE_P (GET_MODE (to),
3045                                         GET_MODE (SUBREG_REG (to)))
3046                   && ! (code == SUBREG
3047                         && MODES_TIEABLE_P (GET_MODE (x),
3048                                             GET_MODE (SUBREG_REG (to))))
3049 #ifdef HAVE_cc0
3050                   && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3051 #endif
3052                   )
3053                 return gen_rtx (CLOBBER, VOIDmode, const0_rtx);
3054
3055               new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3056               n_occurrences++;
3057             }
3058           else
3059             /* If we are in a SET_DEST, suppress most cases unless we
3060                have gone inside a MEM, in which case we want to
3061                simplify the address.  We assume here that things that
3062                are actually part of the destination have their inner
3063                parts in the first expression.  This is true for SUBREG,
3064                STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3065                things aside from REG and MEM that should appear in a
3066                SET_DEST.  */
3067             new = subst (XEXP (x, i), from, to,
3068                          (((in_dest
3069                             && (code == SUBREG || code == STRICT_LOW_PART
3070                                 || code == ZERO_EXTRACT))
3071                            || code == SET)
3072                           && i == 0), unique_copy);
3073
3074           /* If we found that we will have to reject this combination,
3075              indicate that by returning the CLOBBER ourselves, rather than
3076              an expression containing it.  This will speed things up as
3077              well as prevent accidents where two CLOBBERs are considered
3078              to be equal, thus producing an incorrect simplification.  */
3079
3080           if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3081             return new;
3082
3083           SUBST (XEXP (x, i), new);
3084         }
3085     }
3086
3087   /* Try to simplify X.  If the simplification changed the code, it is likely
3088      that further simplification will help, so loop, but limit the number
3089      of repetitions that will be performed.  */
3090
3091   for (i = 0; i < 4; i++)
3092     {
3093       /* If X is sufficiently simple, don't bother trying to do anything
3094          with it.  */
3095       if (code != CONST_INT && code != REG && code != CLOBBER)
3096         x = simplify_rtx (x, op0_mode, i == 3, in_dest);
3097
3098       if (GET_CODE (x) == code)
3099         break;
3100
3101       code = GET_CODE (x);
3102
3103       /* We no longer know the original mode of operand 0 since we
3104          have changed the form of X)  */
3105       op0_mode = VOIDmode;
3106     }
3107
3108   return x;
3109 }
3110 \f
3111 /* Simplify X, a piece of RTL.  We just operate on the expression at the
3112    outer level; call `subst' to simplify recursively.  Return the new
3113    expression.
3114
3115    OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3116    will be the iteration even if an expression with a code different from
3117    X is returned; IN_DEST is nonzero if we are inside a SET_DEST.  */
3118
3119 static rtx
3120 simplify_rtx (x, op0_mode, last, in_dest)
3121      rtx x;
3122      enum machine_mode op0_mode;
3123      int last;
3124      int in_dest;
3125 {
3126   enum rtx_code code = GET_CODE (x);
3127   enum machine_mode mode = GET_MODE (x);
3128   rtx temp;
3129   int i;
3130
3131   /* If this is a commutative operation, put a constant last and a complex
3132      expression first.  We don't need to do this for comparisons here.  */
3133   if (GET_RTX_CLASS (code) == 'c'
3134       && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3135           || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3136               && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3137           || (GET_CODE (XEXP (x, 0)) == SUBREG
3138               && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3139               && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3140     {
3141       temp = XEXP (x, 0);
3142       SUBST (XEXP (x, 0), XEXP (x, 1));
3143       SUBST (XEXP (x, 1), temp);
3144     }
3145
3146   /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3147      sign extension of a PLUS with a constant, reverse the order of the sign
3148      extension and the addition. Note that this not the same as the original
3149      code, but overflow is undefined for signed values.  Also note that the
3150      PLUS will have been partially moved "inside" the sign-extension, so that
3151      the first operand of X will really look like:
3152          (ashiftrt (plus (ashift A C4) C5) C4).
3153      We convert this to
3154          (plus (ashiftrt (ashift A C4) C2) C4)
3155      and replace the first operand of X with that expression.  Later parts
3156      of this function may simplify the expression further.
3157
3158      For example, if we start with (mult (sign_extend (plus A C1)) C2),
3159      we swap the SIGN_EXTEND and PLUS.  Later code will apply the
3160      distributive law to produce (plus (mult (sign_extend X) C1) C3).
3161
3162      We do this to simplify address expressions.  */
3163
3164   if ((code == PLUS || code == MINUS || code == MULT)
3165       && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3166       && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3167       && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3168       && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3169       && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3170       && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3171       && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3172       && (temp = simplify_binary_operation (ASHIFTRT, mode,
3173                                             XEXP (XEXP (XEXP (x, 0), 0), 1),
3174                                             XEXP (XEXP (x, 0), 1))) != 0)
3175     {
3176       rtx new
3177         = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3178                                 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3179                                 INTVAL (XEXP (XEXP (x, 0), 1)));
3180
3181       new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3182                                   INTVAL (XEXP (XEXP (x, 0), 1)));
3183
3184       SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3185     }
3186
3187   /* If this is a simple operation applied to an IF_THEN_ELSE, try
3188      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
3189      things.  Check for cases where both arms are testing the same
3190      condition.
3191
3192      Don't do anything if all operands are very simple.  */
3193
3194   if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3195         || GET_RTX_CLASS (code) == '<')
3196        && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3197             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3198                   && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3199                       == 'o')))
3200            || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3201                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3202                      && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3203                          == 'o')))))
3204       || (GET_RTX_CLASS (code) == '1'
3205           && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3206                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3207                      && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3208                          == 'o'))))))
3209     {
3210       rtx cond, true, false;
3211
3212       cond = if_then_else_cond (x, &true, &false);
3213       if (cond != 0
3214           /* If everything is a comparison, what we have is highly unlikely
3215              to be simpler, so don't use it.  */
3216           && ! (GET_RTX_CLASS (code) == '<'
3217                 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3218                     || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3219         {
3220           rtx cop1 = const0_rtx;
3221           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3222
3223           if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3224             return x;
3225
3226           /* Simplify the alternative arms; this may collapse the true and
3227              false arms to store-flag values.  */
3228           true = subst (true, pc_rtx, pc_rtx, 0, 0);
3229           false = subst (false, pc_rtx, pc_rtx, 0, 0);
3230
3231           /* Restarting if we generate a store-flag expression will cause
3232              us to loop.  Just drop through in this case.  */
3233
3234           /* If the result values are STORE_FLAG_VALUE and zero, we can
3235              just make the comparison operation.  */
3236           if (true == const_true_rtx && false == const0_rtx)
3237             x = gen_binary (cond_code, mode, cond, cop1);
3238           else if (true == const0_rtx && false == const_true_rtx)
3239             x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3240
3241           /* Likewise, we can make the negate of a comparison operation
3242              if the result values are - STORE_FLAG_VALUE and zero.  */
3243           else if (GET_CODE (true) == CONST_INT
3244                    && INTVAL (true) == - STORE_FLAG_VALUE
3245                    && false == const0_rtx)
3246             x = gen_unary (NEG, mode, mode,
3247                            gen_binary (cond_code, mode, cond, cop1));
3248           else if (GET_CODE (false) == CONST_INT
3249                    && INTVAL (false) == - STORE_FLAG_VALUE
3250                    && true == const0_rtx)
3251             x = gen_unary (NEG, mode, mode,
3252                            gen_binary (reverse_condition (cond_code),
3253                                        mode, cond, cop1));
3254           else
3255             return gen_rtx (IF_THEN_ELSE, mode,
3256                             gen_binary (cond_code, VOIDmode, cond, cop1),
3257                             true, false);
3258
3259           code = GET_CODE (x);
3260           op0_mode = VOIDmode;
3261         }
3262     }
3263
3264   /* Try to fold this expression in case we have constants that weren't
3265      present before.  */
3266   temp = 0;
3267   switch (GET_RTX_CLASS (code))
3268     {
3269     case '1':
3270       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3271       break;
3272     case '<':
3273       temp = simplify_relational_operation (code, op0_mode,
3274                                             XEXP (x, 0), XEXP (x, 1));
3275 #ifdef FLOAT_STORE_FLAG_VALUE
3276       if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3277         temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3278                 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3279 #endif
3280       break;
3281     case 'c':
3282     case '2':
3283       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3284       break;
3285     case 'b':
3286     case '3':
3287       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3288                                          XEXP (x, 1), XEXP (x, 2));
3289       break;
3290     }
3291
3292   if (temp)
3293     x = temp, code = GET_CODE (temp);
3294
3295   /* First see if we can apply the inverse distributive law.  */
3296   if (code == PLUS || code == MINUS
3297       || code == AND || code == IOR || code == XOR)
3298     {
3299       x = apply_distributive_law (x);
3300       code = GET_CODE (x);
3301     }
3302
3303   /* If CODE is an associative operation not otherwise handled, see if we
3304      can associate some operands.  This can win if they are constants or
3305      if they are logically related (i.e. (a & b) & a.  */
3306   if ((code == PLUS || code == MINUS
3307        || code == MULT || code == AND || code == IOR || code == XOR
3308        || code == DIV || code == UDIV
3309        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3310       && INTEGRAL_MODE_P (mode))
3311     {
3312       if (GET_CODE (XEXP (x, 0)) == code)
3313         {
3314           rtx other = XEXP (XEXP (x, 0), 0);
3315           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3316           rtx inner_op1 = XEXP (x, 1);
3317           rtx inner;
3318
3319           /* Make sure we pass the constant operand if any as the second
3320              one if this is a commutative operation.  */
3321           if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3322             {
3323               rtx tem = inner_op0;
3324               inner_op0 = inner_op1;
3325               inner_op1 = tem;
3326             }
3327           inner = simplify_binary_operation (code == MINUS ? PLUS
3328                                              : code == DIV ? MULT
3329                                              : code == UDIV ? MULT
3330                                              : code,
3331                                              mode, inner_op0, inner_op1);
3332
3333           /* For commutative operations, try the other pair if that one
3334              didn't simplify.  */
3335           if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3336             {
3337               other = XEXP (XEXP (x, 0), 1);
3338               inner = simplify_binary_operation (code, mode,
3339                                                  XEXP (XEXP (x, 0), 0),
3340                                                  XEXP (x, 1));
3341             }
3342
3343           if (inner)
3344             return gen_binary (code, mode, other, inner);
3345         }
3346     }
3347
3348   /* A little bit of algebraic simplification here.  */
3349   switch (code)
3350     {
3351     case MEM:
3352       /* Ensure that our address has any ASHIFTs converted to MULT in case
3353          address-recognizing predicates are called later.  */
3354       temp = make_compound_operation (XEXP (x, 0), MEM);
3355       SUBST (XEXP (x, 0), temp);
3356       break;
3357
3358     case SUBREG:
3359       /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3360          is paradoxical.  If we can't do that safely, then it becomes
3361          something nonsensical so that this combination won't take place.  */
3362
3363       if (GET_CODE (SUBREG_REG (x)) == MEM
3364           && (GET_MODE_SIZE (mode)
3365               <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3366         {
3367           rtx inner = SUBREG_REG (x);
3368           int endian_offset = 0;
3369           /* Don't change the mode of the MEM
3370              if that would change the meaning of the address.  */
3371           if (MEM_VOLATILE_P (SUBREG_REG (x))
3372               || mode_dependent_address_p (XEXP (inner, 0)))
3373             return gen_rtx (CLOBBER, mode, const0_rtx);
3374
3375           if (BYTES_BIG_ENDIAN)
3376             {
3377               if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3378                 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3379               if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3380                 endian_offset -= (UNITS_PER_WORD
3381                                   - GET_MODE_SIZE (GET_MODE (inner)));
3382             }
3383           /* Note if the plus_constant doesn't make a valid address
3384              then this combination won't be accepted.  */
3385           x = gen_rtx (MEM, mode,
3386                        plus_constant (XEXP (inner, 0),
3387                                       (SUBREG_WORD (x) * UNITS_PER_WORD
3388                                        + endian_offset)));
3389           MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3390           RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3391           MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3392           return x;
3393         }
3394
3395       /* If we are in a SET_DEST, these other cases can't apply.  */
3396       if (in_dest)
3397         return x;
3398
3399       /* Changing mode twice with SUBREG => just change it once,
3400          or not at all if changing back to starting mode.  */
3401       if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3402         {
3403           if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3404               && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3405             return SUBREG_REG (SUBREG_REG (x));
3406
3407           SUBST_INT (SUBREG_WORD (x),
3408                      SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3409           SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3410         }
3411
3412       /* SUBREG of a hard register => just change the register number
3413          and/or mode.  If the hard register is not valid in that mode,
3414          suppress this combination.  If the hard register is the stack,
3415          frame, or argument pointer, leave this as a SUBREG.  */
3416
3417       if (GET_CODE (SUBREG_REG (x)) == REG
3418           && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3419           && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3420 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3421           && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3422 #endif
3423 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3424           && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3425 #endif
3426           && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3427         {
3428           if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3429                                   mode))
3430             return gen_rtx (REG, mode,
3431                             REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3432           else
3433             return gen_rtx (CLOBBER, mode, const0_rtx);
3434         }
3435
3436       /* For a constant, try to pick up the part we want.  Handle a full
3437          word and low-order part.  Only do this if we are narrowing
3438          the constant; if it is being widened, we have no idea what
3439          the extra bits will have been set to.  */
3440
3441       if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3442           && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3443           && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3444           && GET_MODE_CLASS (mode) == MODE_INT)
3445         {
3446           temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3447                                   0, op0_mode);
3448           if (temp)
3449             return temp;
3450         }
3451
3452       /* If we want a subreg of a constant, at offset 0,
3453          take the low bits.  On a little-endian machine, that's
3454          always valid.  On a big-endian machine, it's valid
3455          only if the constant's mode fits in one word.   Note that we
3456          cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode.  */
3457       if (CONSTANT_P (SUBREG_REG (x))
3458           && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3459               || ! WORDS_BIG_ENDIAN)
3460               ? SUBREG_WORD (x) == 0
3461               : (SUBREG_WORD (x)
3462                  == ((GET_MODE_SIZE (op0_mode)
3463                       - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3464                      / UNITS_PER_WORD)))
3465           && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3466           && (! WORDS_BIG_ENDIAN
3467               || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3468         return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3469
3470       /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3471          since we are saying that the high bits don't matter.  */
3472       if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3473           && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3474         return SUBREG_REG (x);
3475
3476       /* Note that we cannot do any narrowing for non-constants since
3477          we might have been counting on using the fact that some bits were
3478          zero.  We now do this in the SET.  */
3479
3480       break;
3481
3482     case NOT:
3483       /* (not (plus X -1)) can become (neg X).  */
3484       if (GET_CODE (XEXP (x, 0)) == PLUS
3485           && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3486         return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3487
3488       /* Similarly, (not (neg X)) is (plus X -1).  */
3489       if (GET_CODE (XEXP (x, 0)) == NEG)
3490         return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3491                                 constm1_rtx);
3492
3493       /* (not (xor X C)) for C constant is (xor X D) with D = ~ C.  */
3494       if (GET_CODE (XEXP (x, 0)) == XOR
3495           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3496           && (temp = simplify_unary_operation (NOT, mode,
3497                                                XEXP (XEXP (x, 0), 1),
3498                                                mode)) != 0)
3499         return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3500
3501       /* (not (ashift 1 X)) is (rotate ~1 X).  We used to do this for operands
3502          other than 1, but that is not valid.  We could do a similar
3503          simplification for (not (lshiftrt C X)) where C is just the sign bit,
3504          but this doesn't seem common enough to bother with.  */
3505       if (GET_CODE (XEXP (x, 0)) == ASHIFT
3506           && XEXP (XEXP (x, 0), 0) == const1_rtx)
3507         return gen_rtx (ROTATE, mode, gen_unary (NOT, mode, mode, const1_rtx),
3508                         XEXP (XEXP (x, 0), 1));
3509
3510       if (GET_CODE (XEXP (x, 0)) == SUBREG
3511           && subreg_lowpart_p (XEXP (x, 0))
3512           && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3513               < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3514           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3515           && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3516         {
3517           enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3518
3519           x = gen_rtx (ROTATE, inner_mode,
3520                        gen_unary (NOT, inner_mode, inner_mode, const1_rtx),
3521                        XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3522           return gen_lowpart_for_combine (mode, x);
3523         }
3524
3525       /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3526          reversing the comparison code if valid.  */
3527       if (STORE_FLAG_VALUE == -1
3528           && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3529           && reversible_comparison_p (XEXP (x, 0)))
3530         return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3531                                 mode, XEXP (XEXP (x, 0), 0),
3532                                 XEXP (XEXP (x, 0), 1));
3533
3534       /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3535          is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3536          perform the above simplification.  */
3537
3538       if (STORE_FLAG_VALUE == -1
3539           && XEXP (x, 1) == const1_rtx
3540           && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3541           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3542           && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3543         return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3544
3545       /* Apply De Morgan's laws to reduce number of patterns for machines
3546          with negating logical insns (and-not, nand, etc.).  If result has
3547          only one NOT, put it first, since that is how the patterns are
3548          coded.  */
3549
3550       if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3551         {
3552          rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3553
3554          if (GET_CODE (in1) == NOT)
3555            in1 = XEXP (in1, 0);
3556          else
3557            in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3558
3559          if (GET_CODE (in2) == NOT)
3560            in2 = XEXP (in2, 0);
3561          else if (GET_CODE (in2) == CONST_INT
3562                   && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3563            in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3564          else
3565            in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3566
3567          if (GET_CODE (in2) == NOT)
3568            {
3569              rtx tem = in2;
3570              in2 = in1; in1 = tem;
3571            }
3572
3573          return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3574                                  mode, in1, in2);
3575        }
3576       break;
3577
3578     case NEG:
3579       /* (neg (plus X 1)) can become (not X).  */
3580       if (GET_CODE (XEXP (x, 0)) == PLUS
3581           && XEXP (XEXP (x, 0), 1) == const1_rtx)
3582         return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3583
3584       /* Similarly, (neg (not X)) is (plus X 1).  */
3585       if (GET_CODE (XEXP (x, 0)) == NOT)
3586         return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3587
3588       /* (neg (minus X Y)) can become (minus Y X).  */
3589       if (GET_CODE (XEXP (x, 0)) == MINUS
3590           && (! FLOAT_MODE_P (mode)
3591               /* x-y != -(y-x) with IEEE floating point.  */
3592               || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3593               || flag_fast_math))
3594         return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3595                            XEXP (XEXP (x, 0), 0));
3596
3597       /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1.  */
3598       if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3599           && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3600         return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3601
3602       /* NEG commutes with ASHIFT since it is multiplication.  Only do this
3603          if we can then eliminate the NEG (e.g.,
3604          if the operand is a constant).  */
3605
3606       if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3607         {
3608           temp = simplify_unary_operation (NEG, mode,
3609                                            XEXP (XEXP (x, 0), 0), mode);
3610           if (temp)
3611             {
3612               SUBST (XEXP (XEXP (x, 0), 0), temp);
3613               return XEXP (x, 0);
3614             }
3615         }
3616
3617       temp = expand_compound_operation (XEXP (x, 0));
3618
3619       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3620          replaced by (lshiftrt X C).  This will convert
3621          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
3622
3623       if (GET_CODE (temp) == ASHIFTRT
3624           && GET_CODE (XEXP (temp, 1)) == CONST_INT
3625           && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3626         return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3627                                      INTVAL (XEXP (temp, 1)));
3628
3629       /* If X has only a single bit that might be nonzero, say, bit I, convert
3630          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3631          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
3632          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
3633          or a SUBREG of one since we'd be making the expression more
3634          complex if it was just a register.  */
3635
3636       if (GET_CODE (temp) != REG
3637           && ! (GET_CODE (temp) == SUBREG
3638                 && GET_CODE (SUBREG_REG (temp)) == REG)
3639           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3640         {
3641           rtx temp1 = simplify_shift_const
3642             (NULL_RTX, ASHIFTRT, mode,
3643              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3644                                    GET_MODE_BITSIZE (mode) - 1 - i),
3645              GET_MODE_BITSIZE (mode) - 1 - i);
3646
3647           /* If all we did was surround TEMP with the two shifts, we
3648              haven't improved anything, so don't use it.  Otherwise,
3649              we are better off with TEMP1.  */
3650           if (GET_CODE (temp1) != ASHIFTRT
3651               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3652               || XEXP (XEXP (temp1, 0), 0) != temp)
3653             return temp1;
3654         }
3655       break;
3656
3657     case TRUNCATE:
3658       /* We can't handle truncation to a partial integer mode here
3659          because we don't know the real bitsize of the partial
3660          integer mode.  */
3661       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3662         break;
3663
3664       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3665         SUBST (XEXP (x, 0),
3666                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3667                               GET_MODE_MASK (mode), NULL_RTX, 0));
3668
3669       /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI.  */
3670       if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3671            || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3672           && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3673         return XEXP (XEXP (x, 0), 0);
3674
3675       /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3676          (OP:SI foo:SI) if OP is NEG or ABS.  */
3677       if ((GET_CODE (XEXP (x, 0)) == ABS
3678            || GET_CODE (XEXP (x, 0)) == NEG)
3679           && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3680               || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3681           && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3682         return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3683                           XEXP (XEXP (XEXP (x, 0), 0), 0));
3684
3685       /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3686          (truncate:SI x).  */
3687       if (GET_CODE (XEXP (x, 0)) == SUBREG
3688           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3689           && subreg_lowpart_p (XEXP (x, 0)))
3690         return SUBREG_REG (XEXP (x, 0));
3691
3692       /* If we know that the value is already truncated, we can
3693          replace the TRUNCATE with a SUBREG.  */
3694       if (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) <= HOST_BITS_PER_WIDE_INT
3695           && (nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3696               &~ GET_MODE_MASK (mode)) == 0)
3697         return gen_lowpart_for_combine (mode, XEXP (x, 0));
3698
3699       /* A truncate of a comparison can be replaced with a subreg if
3700          STORE_FLAG_VALUE permits.  This is like the previous test,
3701          but it works even if the comparison is done in a mode larger
3702          than HOST_BITS_PER_WIDE_INT.  */
3703       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3704           && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3705           && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3706         return gen_lowpart_for_combine (mode, XEXP (x, 0));
3707
3708       /* Similarly, a truncate of a register whose value is a
3709          comparison can be replaced with a subreg if STORE_FLAG_VALUE
3710          permits.  */
3711       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3712           && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3713           && (temp = get_last_value (XEXP (x, 0)))
3714           && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3715         return gen_lowpart_for_combine (mode, XEXP (x, 0));
3716
3717       break;
3718
3719     case FLOAT_TRUNCATE:
3720       /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF.  */
3721       if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3722           && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3723         return XEXP (XEXP (x, 0), 0);
3724
3725       /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3726          (OP:SF foo:SF) if OP is NEG or ABS.  */
3727       if ((GET_CODE (XEXP (x, 0)) == ABS
3728            || GET_CODE (XEXP (x, 0)) == NEG)
3729           && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3730           && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3731         return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3732                           XEXP (XEXP (XEXP (x, 0), 0), 0));
3733
3734       /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3735          is (float_truncate:SF x).  */
3736       if (GET_CODE (XEXP (x, 0)) == SUBREG
3737           && subreg_lowpart_p (XEXP (x, 0))
3738           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3739         return SUBREG_REG (XEXP (x, 0));
3740       break;
3741
3742 #ifdef HAVE_cc0
3743     case COMPARE:
3744       /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3745          using cc0, in which case we want to leave it as a COMPARE
3746          so we can distinguish it from a register-register-copy.  */
3747       if (XEXP (x, 1) == const0_rtx)
3748         return XEXP (x, 0);
3749
3750       /* In IEEE floating point, x-0 is not the same as x.  */
3751       if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3752            || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3753            || flag_fast_math)
3754           && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3755         return XEXP (x, 0);
3756       break;
3757 #endif
3758
3759     case CONST:
3760       /* (const (const X)) can become (const X).  Do it this way rather than
3761          returning the inner CONST since CONST can be shared with a
3762          REG_EQUAL note.  */
3763       if (GET_CODE (XEXP (x, 0)) == CONST)
3764         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3765       break;
3766
3767 #ifdef HAVE_lo_sum
3768     case LO_SUM:
3769       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
3770          can add in an offset.  find_split_point will split this address up
3771          again if it doesn't match.  */
3772       if (GET_CODE (XEXP (x, 0)) == HIGH
3773           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3774         return XEXP (x, 1);
3775       break;
3776 #endif
3777
3778     case PLUS:
3779       /* If we have (plus (plus (A const) B)), associate it so that CONST is
3780          outermost.  That's because that's the way indexed addresses are
3781          supposed to appear.  This code used to check many more cases, but
3782          they are now checked elsewhere.  */
3783       if (GET_CODE (XEXP (x, 0)) == PLUS
3784           && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3785         return gen_binary (PLUS, mode,
3786                            gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3787                                        XEXP (x, 1)),
3788                            XEXP (XEXP (x, 0), 1));
3789
3790       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3791          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3792          bit-field and can be replaced by either a sign_extend or a
3793          sign_extract.  The `and' may be a zero_extend.  */
3794       if (GET_CODE (XEXP (x, 0)) == XOR
3795           && GET_CODE (XEXP (x, 1)) == CONST_INT
3796           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3797           && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3798           && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3799           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3800           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3801                && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3802                && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3803                    == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3804               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3805                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3806                       == i + 1))))
3807         return simplify_shift_const
3808           (NULL_RTX, ASHIFTRT, mode,
3809            simplify_shift_const (NULL_RTX, ASHIFT, mode,
3810                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
3811                                  GET_MODE_BITSIZE (mode) - (i + 1)),
3812            GET_MODE_BITSIZE (mode) - (i + 1));
3813
3814       /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3815          C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3816          is 1.  This produces better code than the alternative immediately
3817          below.  */
3818       if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3819           && reversible_comparison_p (XEXP (x, 0))
3820           && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3821               || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
3822         return
3823           gen_unary (NEG, mode, mode,
3824                      gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3825                                  mode, XEXP (XEXP (x, 0), 0),
3826                                  XEXP (XEXP (x, 0), 1)));
3827
3828       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3829          can become (ashiftrt (ashift (xor x 1) C) C) where C is
3830          the bitsize of the mode - 1.  This allows simplification of
3831          "a = (b & 8) == 0;"  */
3832       if (XEXP (x, 1) == constm1_rtx
3833           && GET_CODE (XEXP (x, 0)) != REG
3834           && ! (GET_CODE (XEXP (x,0)) == SUBREG
3835                 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3836           && nonzero_bits (XEXP (x, 0), mode) == 1)
3837         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3838            simplify_shift_const (NULL_RTX, ASHIFT, mode,
3839                                  gen_rtx_combine (XOR, mode,
3840                                                   XEXP (x, 0), const1_rtx),
3841                                  GET_MODE_BITSIZE (mode) - 1),
3842            GET_MODE_BITSIZE (mode) - 1);
3843
3844       /* If we are adding two things that have no bits in common, convert
3845          the addition into an IOR.  This will often be further simplified,
3846          for example in cases like ((a & 1) + (a & 2)), which can
3847          become a & 3.  */
3848
3849       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3850           && (nonzero_bits (XEXP (x, 0), mode)
3851               & nonzero_bits (XEXP (x, 1), mode)) == 0)
3852         return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3853       break;
3854
3855     case MINUS:
3856       /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
3857          by reversing the comparison code if valid.  */
3858       if (STORE_FLAG_VALUE == 1
3859           && XEXP (x, 0) == const1_rtx
3860           && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3861           && reversible_comparison_p (XEXP (x, 1)))
3862         return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3863                            mode, XEXP (XEXP (x, 1), 0),
3864                                 XEXP (XEXP (x, 1), 1));
3865
3866       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3867          (and <foo> (const_int pow2-1))  */
3868       if (GET_CODE (XEXP (x, 1)) == AND
3869           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3870           && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3871           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3872         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3873                                        - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3874
3875       /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3876          integers.  */
3877       if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
3878         return gen_binary (MINUS, mode,
3879                            gen_binary (MINUS, mode, XEXP (x, 0),
3880                                        XEXP (XEXP (x, 1), 0)),
3881                            XEXP (XEXP (x, 1), 1));
3882       break;
3883
3884     case MULT:
3885       /* If we have (mult (plus A B) C), apply the distributive law and then
3886          the inverse distributive law to see if things simplify.  This
3887          occurs mostly in addresses, often when unrolling loops.  */
3888
3889       if (GET_CODE (XEXP (x, 0)) == PLUS)
3890         {
3891           x = apply_distributive_law
3892             (gen_binary (PLUS, mode,
3893                          gen_binary (MULT, mode,
3894                                      XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3895                          gen_binary (MULT, mode,
3896                                      XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3897
3898           if (GET_CODE (x) != MULT)
3899             return x;
3900         }
3901       break;
3902
3903     case UDIV:
3904       /* If this is a divide by a power of two, treat it as a shift if
3905          its first operand is a shift.  */
3906       if (GET_CODE (XEXP (x, 1)) == CONST_INT
3907           && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3908           && (GET_CODE (XEXP (x, 0)) == ASHIFT
3909               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3910               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3911               || GET_CODE (XEXP (x, 0)) == ROTATE
3912               || GET_CODE (XEXP (x, 0)) == ROTATERT))
3913         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3914       break;
3915
3916     case EQ:  case NE:
3917     case GT:  case GTU:  case GE:  case GEU:
3918     case LT:  case LTU:  case LE:  case LEU:
3919       /* If the first operand is a condition code, we can't do anything
3920          with it.  */
3921       if (GET_CODE (XEXP (x, 0)) == COMPARE
3922           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3923 #ifdef HAVE_cc0
3924               && XEXP (x, 0) != cc0_rtx
3925 #endif
3926                ))
3927         {
3928           rtx op0 = XEXP (x, 0);
3929           rtx op1 = XEXP (x, 1);
3930           enum rtx_code new_code;
3931
3932           if (GET_CODE (op0) == COMPARE)
3933             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3934
3935           /* Simplify our comparison, if possible.  */
3936           new_code = simplify_comparison (code, &op0, &op1);
3937
3938           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3939              if only the low-order bit is possibly nonzero in X (such as when
3940              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
3941              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
3942              known to be either 0 or -1, NE becomes a NEG and EQ becomes
3943              (plus X 1).
3944
3945              Remove any ZERO_EXTRACT we made when thinking this was a
3946              comparison.  It may now be simpler to use, e.g., an AND.  If a
3947              ZERO_EXTRACT is indeed appropriate, it will be placed back by
3948              the call to make_compound_operation in the SET case.  */
3949
3950           if (STORE_FLAG_VALUE == 1
3951               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3952               && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
3953             return gen_lowpart_for_combine (mode,
3954                                             expand_compound_operation (op0));
3955
3956           else if (STORE_FLAG_VALUE == 1
3957                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3958                    && op1 == const0_rtx
3959                    && (num_sign_bit_copies (op0, mode)
3960                        == GET_MODE_BITSIZE (mode)))
3961             {
3962               op0 = expand_compound_operation (op0);
3963               return gen_unary (NEG, mode, mode,
3964                                 gen_lowpart_for_combine (mode, op0));
3965             }
3966
3967           else if (STORE_FLAG_VALUE == 1
3968                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3969                    && op1 == const0_rtx
3970                    && nonzero_bits (op0, mode) == 1)
3971             {
3972               op0 = expand_compound_operation (op0);
3973               return gen_binary (XOR, mode,
3974                                  gen_lowpart_for_combine (mode, op0),
3975                                  const1_rtx);
3976             }
3977
3978           else if (STORE_FLAG_VALUE == 1
3979                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3980                    && op1 == const0_rtx
3981                    && (num_sign_bit_copies (op0, mode)
3982                        == GET_MODE_BITSIZE (mode)))
3983             {
3984               op0 = expand_compound_operation (op0);
3985               return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
3986             }
3987
3988           /* If STORE_FLAG_VALUE is -1, we have cases similar to
3989              those above.  */
3990           if (STORE_FLAG_VALUE == -1
3991               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3992               && op1 == const0_rtx
3993               && (num_sign_bit_copies (op0, mode)
3994                   == GET_MODE_BITSIZE (mode)))
3995             return gen_lowpart_for_combine (mode,
3996                                             expand_compound_operation (op0));
3997
3998           else if (STORE_FLAG_VALUE == -1
3999                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4000                    && op1 == const0_rtx
4001                    && nonzero_bits (op0, mode) == 1)
4002             {
4003               op0 = expand_compound_operation (op0);
4004               return gen_unary (NEG, mode, mode,
4005                                 gen_lowpart_for_combine (mode, op0));
4006             }
4007
4008           else if (STORE_FLAG_VALUE == -1
4009                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4010                    && op1 == const0_rtx
4011                    && (num_sign_bit_copies (op0, mode)
4012                        == GET_MODE_BITSIZE (mode)))
4013             {
4014               op0 = expand_compound_operation (op0);
4015               return gen_unary (NOT, mode, mode,
4016                                 gen_lowpart_for_combine (mode, op0));
4017             }
4018
4019           /* If X is 0/1, (eq X 0) is X-1.  */
4020           else if (STORE_FLAG_VALUE == -1
4021                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4022                    && op1 == const0_rtx
4023                    && nonzero_bits (op0, mode) == 1)
4024             {
4025               op0 = expand_compound_operation (op0);
4026               return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4027             }
4028
4029           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4030              one bit that might be nonzero, we can convert (ne x 0) to
4031              (ashift x c) where C puts the bit in the sign bit.  Remove any
4032              AND with STORE_FLAG_VALUE when we are done, since we are only
4033              going to test the sign bit.  */
4034           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4035               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4036               && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4037                   == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4038               && op1 == const0_rtx
4039               && mode == GET_MODE (op0)
4040               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4041             {
4042               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4043                                         expand_compound_operation (op0),
4044                                         GET_MODE_BITSIZE (mode) - 1 - i);
4045               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4046                 return XEXP (x, 0);
4047               else
4048                 return x;
4049             }
4050
4051           /* If the code changed, return a whole new comparison.  */
4052           if (new_code != code)
4053             return gen_rtx_combine (new_code, mode, op0, op1);
4054
4055           /* Otherwise, keep this operation, but maybe change its operands.
4056              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
4057           SUBST (XEXP (x, 0), op0);
4058           SUBST (XEXP (x, 1), op1);
4059         }
4060       break;
4061
4062     case IF_THEN_ELSE:
4063       return simplify_if_then_else (x);
4064
4065     case ZERO_EXTRACT:
4066     case SIGN_EXTRACT:
4067     case ZERO_EXTEND:
4068     case SIGN_EXTEND:
4069       /* If we are processing SET_DEST, we are done.  */
4070       if (in_dest)
4071         return x;
4072
4073       return expand_compound_operation (x);
4074
4075     case SET:
4076       return simplify_set (x);
4077
4078     case AND:
4079     case IOR:
4080     case XOR:
4081       return simplify_logical (x, last);
4082
4083     case ABS:
4084       /* (abs (neg <foo>)) -> (abs <foo>) */
4085       if (GET_CODE (XEXP (x, 0)) == NEG)
4086         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4087
4088       /* If operand is something known to be positive, ignore the ABS.  */
4089       if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4090           || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4091                <= HOST_BITS_PER_WIDE_INT)
4092               && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4093                    & ((HOST_WIDE_INT) 1
4094                       << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4095                   == 0)))
4096         return XEXP (x, 0);
4097
4098
4099       /* If operand is known to be only -1 or 0, convert ABS to NEG.  */
4100       if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4101         return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4102
4103       break;
4104
4105     case FFS:
4106       /* (ffs (*_extend <X>)) = (ffs <X>) */
4107       if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4108           || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4109         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4110       break;
4111
4112     case FLOAT:
4113       /* (float (sign_extend <X>)) = (float <X>).  */
4114       if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4115         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4116       break;
4117
4118     case ASHIFT:
4119     case LSHIFTRT:
4120     case ASHIFTRT:
4121     case ROTATE:
4122     case ROTATERT:
4123       /* If this is a shift by a constant amount, simplify it.  */
4124       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4125         return simplify_shift_const (x, code, mode, XEXP (x, 0),
4126                                      INTVAL (XEXP (x, 1)));
4127
4128 #ifdef SHIFT_COUNT_TRUNCATED
4129       else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4130         SUBST (XEXP (x, 1),
4131                force_to_mode (XEXP (x, 1), GET_MODE (x),
4132                               ((HOST_WIDE_INT) 1
4133                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4134                               - 1,
4135                               NULL_RTX, 0));
4136 #endif
4137
4138       break;
4139
4140     default:
4141       break;
4142     }
4143
4144   return x;
4145 }
4146 \f
4147 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
4148
4149 static rtx
4150 simplify_if_then_else (x)
4151      rtx x;
4152 {
4153   enum machine_mode mode = GET_MODE (x);
4154   rtx cond = XEXP (x, 0);
4155   rtx true = XEXP (x, 1);
4156   rtx false = XEXP (x, 2);
4157   enum rtx_code true_code = GET_CODE (cond);
4158   int comparison_p = GET_RTX_CLASS (true_code) == '<';
4159   rtx temp;
4160   int i;
4161
4162   /* Simplify storing of the truth value.  */
4163   if (comparison_p && true == const_true_rtx && false == const0_rtx)
4164     return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4165
4166   /* Also when the truth value has to be reversed.  */
4167   if (comparison_p && reversible_comparison_p (cond)
4168       && true == const0_rtx && false == const_true_rtx)
4169     return gen_binary (reverse_condition (true_code),
4170                        mode, XEXP (cond, 0), XEXP (cond, 1));
4171
4172   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4173      in it is being compared against certain values.  Get the true and false
4174      comparisons and see if that says anything about the value of each arm.  */
4175
4176   if (comparison_p && reversible_comparison_p (cond)
4177       && GET_CODE (XEXP (cond, 0)) == REG)
4178     {
4179       HOST_WIDE_INT nzb;
4180       rtx from = XEXP (cond, 0);
4181       enum rtx_code false_code = reverse_condition (true_code);
4182       rtx true_val = XEXP (cond, 1);
4183       rtx false_val = true_val;
4184       int swapped = 0;
4185
4186       /* If FALSE_CODE is EQ, swap the codes and arms.  */
4187
4188       if (false_code == EQ)
4189         {
4190           swapped = 1, true_code = EQ, false_code = NE;
4191           temp = true, true = false, false = temp;
4192         }
4193
4194       /* If we are comparing against zero and the expression being tested has
4195          only a single bit that might be nonzero, that is its value when it is
4196          not equal to zero.  Similarly if it is known to be -1 or 0.  */
4197
4198       if (true_code == EQ && true_val == const0_rtx
4199           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4200         false_code = EQ, false_val = GEN_INT (nzb);
4201       else if (true_code == EQ && true_val == const0_rtx
4202                && (num_sign_bit_copies (from, GET_MODE (from))
4203                    == GET_MODE_BITSIZE (GET_MODE (from))))
4204         false_code = EQ, false_val = constm1_rtx;
4205
4206       /* Now simplify an arm if we know the value of the register in the
4207          branch and it is used in the arm.  Be careful due to the potential
4208          of locally-shared RTL.  */
4209
4210       if (reg_mentioned_p (from, true))
4211         true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4212                       pc_rtx, pc_rtx, 0, 0);
4213       if (reg_mentioned_p (from, false))
4214         false = subst (known_cond (copy_rtx (false), false_code,
4215                                    from, false_val),
4216                        pc_rtx, pc_rtx, 0, 0);
4217
4218       SUBST (XEXP (x, 1), swapped ? false : true);
4219       SUBST (XEXP (x, 2), swapped ? true : false);
4220
4221       true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4222     }
4223
4224   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4225      reversed, do so to avoid needing two sets of patterns for
4226      subtract-and-branch insns.  Similarly if we have a constant in the true
4227      arm, the false arm is the same as the first operand of the comparison, or
4228      the false arm is more complicated than the true arm.  */
4229
4230   if (comparison_p && reversible_comparison_p (cond)
4231       && (true == pc_rtx
4232           || (CONSTANT_P (true)
4233               && GET_CODE (false) != CONST_INT && false != pc_rtx)
4234           || true == const0_rtx
4235           || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4236               && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4237           || (GET_CODE (true) == SUBREG
4238               && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4239               && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4240           || reg_mentioned_p (true, false)
4241           || rtx_equal_p (false, XEXP (cond, 0))))
4242     {
4243       true_code = reverse_condition (true_code);
4244       SUBST (XEXP (x, 0),
4245              gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4246                          XEXP (cond, 1)));
4247
4248       SUBST (XEXP (x, 1), false);
4249       SUBST (XEXP (x, 2), true);
4250
4251       temp = true, true = false, false = temp, cond = XEXP (x, 0);
4252
4253       /* It is possible that the conditional has been simplified out.  */
4254       true_code = GET_CODE (cond);
4255       comparison_p = GET_RTX_CLASS (true_code) == '<';
4256     }
4257
4258   /* If the two arms are identical, we don't need the comparison.  */
4259
4260   if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4261     return true;
4262
4263   /* Convert a == b ? b : a to "a".  */
4264   if (true_code == EQ && ! side_effects_p (cond)
4265       && rtx_equal_p (XEXP (cond, 0), false)
4266       && rtx_equal_p (XEXP (cond, 1), true))
4267     return false;
4268   else if (true_code == NE && ! side_effects_p (cond)
4269            && rtx_equal_p (XEXP (cond, 0), true)
4270            && rtx_equal_p (XEXP (cond, 1), false))
4271     return true;
4272
4273   /* Look for cases where we have (abs x) or (neg (abs X)).  */
4274
4275   if (GET_MODE_CLASS (mode) == MODE_INT
4276       && GET_CODE (false) == NEG
4277       && rtx_equal_p (true, XEXP (false, 0))
4278       && comparison_p
4279       && rtx_equal_p (true, XEXP (cond, 0))
4280       && ! side_effects_p (true))
4281     switch (true_code)
4282       {
4283       case GT:
4284       case GE:
4285         return gen_unary (ABS, mode, mode, true);
4286       case LT:
4287       case LE:
4288         return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4289     default:
4290       break;
4291       }
4292
4293   /* Look for MIN or MAX.  */
4294
4295   if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4296       && comparison_p
4297       && rtx_equal_p (XEXP (cond, 0), true)
4298       && rtx_equal_p (XEXP (cond, 1), false)
4299       && ! side_effects_p (cond))
4300     switch (true_code)
4301       {
4302       case GE:
4303       case GT:
4304         return gen_binary (SMAX, mode, true, false);
4305       case LE:
4306       case LT:
4307         return gen_binary (SMIN, mode, true, false);
4308       case GEU:
4309       case GTU:
4310         return gen_binary (UMAX, mode, true, false);
4311       case LEU:
4312       case LTU:
4313         return gen_binary (UMIN, mode, true, false);
4314       default:
4315         break;
4316       }
4317
4318   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4319      second operand is zero, this can be done as (OP Z (mult COND C2)) where
4320      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4321      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4322      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4323      neither 1 or -1, but it isn't worth checking for.  */
4324
4325   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4326       && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4327     {
4328       rtx t = make_compound_operation (true, SET);
4329       rtx f = make_compound_operation (false, SET);
4330       rtx cond_op0 = XEXP (cond, 0);
4331       rtx cond_op1 = XEXP (cond, 1);
4332       enum rtx_code op, extend_op = NIL;
4333       enum machine_mode m = mode;
4334       rtx z = 0, c1;
4335
4336       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4337            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4338            || GET_CODE (t) == ASHIFT
4339            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4340           && rtx_equal_p (XEXP (t, 0), f))
4341         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4342
4343       /* If an identity-zero op is commutative, check whether there
4344          would be a match if we swapped the operands.  */
4345       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4346                 || GET_CODE (t) == XOR)
4347                && rtx_equal_p (XEXP (t, 1), f))
4348         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4349       else if (GET_CODE (t) == SIGN_EXTEND
4350                && (GET_CODE (XEXP (t, 0)) == PLUS
4351                    || GET_CODE (XEXP (t, 0)) == MINUS
4352                    || GET_CODE (XEXP (t, 0)) == IOR
4353                    || GET_CODE (XEXP (t, 0)) == XOR
4354                    || GET_CODE (XEXP (t, 0)) == ASHIFT
4355                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4356                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4357                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4358                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4359                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4360                && (num_sign_bit_copies (f, GET_MODE (f))
4361                    > (GET_MODE_BITSIZE (mode)
4362                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4363         {
4364           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4365           extend_op = SIGN_EXTEND;
4366           m = GET_MODE (XEXP (t, 0));
4367         }
4368       else if (GET_CODE (t) == SIGN_EXTEND
4369                && (GET_CODE (XEXP (t, 0)) == PLUS
4370                    || GET_CODE (XEXP (t, 0)) == IOR
4371                    || GET_CODE (XEXP (t, 0)) == XOR)
4372                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4373                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4374                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4375                && (num_sign_bit_copies (f, GET_MODE (f))
4376                    > (GET_MODE_BITSIZE (mode)
4377                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4378         {
4379           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4380           extend_op = SIGN_EXTEND;
4381           m = GET_MODE (XEXP (t, 0));
4382         }
4383       else if (GET_CODE (t) == ZERO_EXTEND
4384                && (GET_CODE (XEXP (t, 0)) == PLUS
4385                    || GET_CODE (XEXP (t, 0)) == MINUS
4386                    || GET_CODE (XEXP (t, 0)) == IOR
4387                    || GET_CODE (XEXP (t, 0)) == XOR
4388                    || GET_CODE (XEXP (t, 0)) == ASHIFT
4389                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4390                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4391                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4392                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4393                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4394                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4395                && ((nonzero_bits (f, GET_MODE (f))
4396                     & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4397                    == 0))
4398         {
4399           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4400           extend_op = ZERO_EXTEND;
4401           m = GET_MODE (XEXP (t, 0));
4402         }
4403       else if (GET_CODE (t) == ZERO_EXTEND
4404                && (GET_CODE (XEXP (t, 0)) == PLUS
4405                    || GET_CODE (XEXP (t, 0)) == IOR
4406                    || GET_CODE (XEXP (t, 0)) == XOR)
4407                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4408                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4409                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4410                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4411                && ((nonzero_bits (f, GET_MODE (f))
4412                     & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4413                    == 0))
4414         {
4415           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4416           extend_op = ZERO_EXTEND;
4417           m = GET_MODE (XEXP (t, 0));
4418         }
4419
4420       if (z)
4421         {
4422           temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4423                         pc_rtx, pc_rtx, 0, 0);
4424           temp = gen_binary (MULT, m, temp,
4425                              gen_binary (MULT, m, c1, const_true_rtx));
4426           temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4427           temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4428
4429           if (extend_op != NIL)
4430             temp = gen_unary (extend_op, mode, m, temp);
4431
4432           return temp;
4433         }
4434     }
4435
4436   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4437      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4438      negation of a single bit, we can convert this operation to a shift.  We
4439      can actually do this more generally, but it doesn't seem worth it.  */
4440
4441   if (true_code == NE && XEXP (cond, 1) == const0_rtx
4442       && false == const0_rtx && GET_CODE (true) == CONST_INT
4443       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4444            && (i = exact_log2 (INTVAL (true))) >= 0)
4445           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4446                == GET_MODE_BITSIZE (mode))
4447               && (i = exact_log2 (- INTVAL (true))) >= 0)))
4448     return
4449       simplify_shift_const (NULL_RTX, ASHIFT, mode,
4450                             gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4451
4452   return x;
4453 }
4454 \f
4455 /* Simplify X, a SET expression.  Return the new expression.  */
4456
4457 static rtx
4458 simplify_set (x)
4459      rtx x;
4460 {
4461   rtx src = SET_SRC (x);
4462   rtx dest = SET_DEST (x);
4463   enum machine_mode mode
4464     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4465   rtx other_insn;
4466   rtx *cc_use;
4467
4468   /* (set (pc) (return)) gets written as (return).  */
4469   if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4470     return src;
4471
4472   /* Now that we know for sure which bits of SRC we are using, see if we can
4473      simplify the expression for the object knowing that we only need the
4474      low-order bits.  */
4475
4476   if (GET_MODE_CLASS (mode) == MODE_INT)
4477     src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4478
4479   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4480      the comparison result and try to simplify it unless we already have used
4481      undobuf.other_insn.  */
4482   if ((GET_CODE (src) == COMPARE
4483 #ifdef HAVE_cc0
4484        || dest == cc0_rtx
4485 #endif
4486        )
4487       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4488       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4489       && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4490       && rtx_equal_p (XEXP (*cc_use, 0), dest))
4491     {
4492       enum rtx_code old_code = GET_CODE (*cc_use);
4493       enum rtx_code new_code;
4494       rtx op0, op1;
4495       int other_changed = 0;
4496       enum machine_mode compare_mode = GET_MODE (dest);
4497
4498       if (GET_CODE (src) == COMPARE)
4499         op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4500       else
4501         op0 = src, op1 = const0_rtx;
4502
4503       /* Simplify our comparison, if possible.  */
4504       new_code = simplify_comparison (old_code, &op0, &op1);
4505
4506 #ifdef EXTRA_CC_MODES
4507       /* If this machine has CC modes other than CCmode, check to see if we
4508          need to use a different CC mode here.  */
4509       compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4510 #endif /* EXTRA_CC_MODES */
4511
4512 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4513       /* If the mode changed, we have to change SET_DEST, the mode in the
4514          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
4515          a hard register, just build new versions with the proper mode.  If it
4516          is a pseudo, we lose unless it is only time we set the pseudo, in
4517          which case we can safely change its mode.  */
4518       if (compare_mode != GET_MODE (dest))
4519         {
4520           int regno = REGNO (dest);
4521           rtx new_dest = gen_rtx (REG, compare_mode, regno);
4522
4523           if (regno < FIRST_PSEUDO_REGISTER
4524               || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4525             {
4526               if (regno >= FIRST_PSEUDO_REGISTER)
4527                 SUBST (regno_reg_rtx[regno], new_dest);
4528
4529               SUBST (SET_DEST (x), new_dest);
4530               SUBST (XEXP (*cc_use, 0), new_dest);
4531               other_changed = 1;
4532
4533               dest = new_dest;
4534             }
4535         }
4536 #endif
4537
4538       /* If the code changed, we have to build a new comparison in
4539          undobuf.other_insn.  */
4540       if (new_code != old_code)
4541         {
4542           unsigned HOST_WIDE_INT mask;
4543
4544           SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4545                                            dest, const0_rtx));
4546
4547           /* If the only change we made was to change an EQ into an NE or
4548              vice versa, OP0 has only one bit that might be nonzero, and OP1
4549              is zero, check if changing the user of the condition code will
4550              produce a valid insn.  If it won't, we can keep the original code
4551              in that insn by surrounding our operation with an XOR.  */
4552
4553           if (((old_code == NE && new_code == EQ)
4554                || (old_code == EQ && new_code == NE))
4555               && ! other_changed && op1 == const0_rtx
4556               && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4557               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4558             {
4559               rtx pat = PATTERN (other_insn), note = 0;
4560               int scratches;
4561
4562               if ((recog_for_combine (&pat, other_insn, &note, &scratches) < 0
4563                    && ! check_asm_operands (pat)))
4564                 {
4565                   PUT_CODE (*cc_use, old_code);
4566                   other_insn = 0;
4567
4568                   op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4569                 }
4570             }
4571
4572           other_changed = 1;
4573         }
4574
4575       if (other_changed)
4576         undobuf.other_insn = other_insn;
4577
4578 #ifdef HAVE_cc0
4579       /* If we are now comparing against zero, change our source if
4580          needed.  If we do not use cc0, we always have a COMPARE.  */
4581       if (op1 == const0_rtx && dest == cc0_rtx)
4582         {
4583           SUBST (SET_SRC (x), op0);
4584           src = op0;
4585         }
4586       else
4587 #endif
4588
4589       /* Otherwise, if we didn't previously have a COMPARE in the
4590          correct mode, we need one.  */
4591       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4592         {
4593           SUBST (SET_SRC (x),
4594                  gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4595           src = SET_SRC (x);
4596         }
4597       else
4598         {
4599           /* Otherwise, update the COMPARE if needed.  */
4600           SUBST (XEXP (src, 0), op0);
4601           SUBST (XEXP (src, 1), op1);
4602         }
4603     }
4604   else
4605     {
4606       /* Get SET_SRC in a form where we have placed back any
4607          compound expressions.  Then do the checks below.  */
4608       src = make_compound_operation (src, SET);
4609       SUBST (SET_SRC (x), src);
4610     }
4611
4612   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4613      and X being a REG or (subreg (reg)), we may be able to convert this to
4614      (set (subreg:m2 x) (op)).
4615
4616      We can always do this if M1 is narrower than M2 because that means that
4617      we only care about the low bits of the result.
4618
4619      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4620      perform a narrower operation that requested since the high-order bits will
4621      be undefined.  On machine where it is defined, this transformation is safe
4622      as long as M1 and M2 have the same number of words.  */
4623
4624   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4625       && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4626       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4627            / UNITS_PER_WORD)
4628           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4629                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4630 #ifndef WORD_REGISTER_OPERATIONS
4631       && (GET_MODE_SIZE (GET_MODE (src))
4632           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4633 #endif
4634 #ifdef CLASS_CANNOT_CHANGE_SIZE
4635       && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4636             && (TEST_HARD_REG_BIT
4637                 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4638                  REGNO (dest)))
4639             && (GET_MODE_SIZE (GET_MODE (src))
4640                 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4641 #endif
4642       && (GET_CODE (dest) == REG
4643           || (GET_CODE (dest) == SUBREG
4644               && GET_CODE (SUBREG_REG (dest)) == REG)))
4645     {
4646       SUBST (SET_DEST (x),
4647              gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4648                                       dest));
4649       SUBST (SET_SRC (x), SUBREG_REG (src));
4650
4651       src = SET_SRC (x), dest = SET_DEST (x);
4652     }
4653
4654 #ifdef LOAD_EXTEND_OP
4655   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4656      would require a paradoxical subreg.  Replace the subreg with a
4657      zero_extend to avoid the reload that would otherwise be required.  */
4658
4659   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4660       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4661       && SUBREG_WORD (src) == 0
4662       && (GET_MODE_SIZE (GET_MODE (src))
4663           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4664       && GET_CODE (SUBREG_REG (src)) == MEM)
4665     {
4666       SUBST (SET_SRC (x),
4667              gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4668                               GET_MODE (src), XEXP (src, 0)));
4669
4670       src = SET_SRC (x);
4671     }
4672 #endif
4673
4674   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4675      are comparing an item known to be 0 or -1 against 0, use a logical
4676      operation instead. Check for one of the arms being an IOR of the other
4677      arm with some value.  We compute three terms to be IOR'ed together.  In
4678      practice, at most two will be nonzero.  Then we do the IOR's.  */
4679
4680   if (GET_CODE (dest) != PC
4681       && GET_CODE (src) == IF_THEN_ELSE
4682       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
4683       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4684       && XEXP (XEXP (src, 0), 1) == const0_rtx
4685       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
4686 #ifdef HAVE_conditional_move
4687       && ! can_conditionally_move_p (GET_MODE (src))
4688 #endif
4689       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4690                                GET_MODE (XEXP (XEXP (src, 0), 0)))
4691           == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4692       && ! side_effects_p (src))
4693     {
4694       rtx true = (GET_CODE (XEXP (src, 0)) == NE
4695                       ? XEXP (src, 1) : XEXP (src, 2));
4696       rtx false = (GET_CODE (XEXP (src, 0)) == NE
4697                    ? XEXP (src, 2) : XEXP (src, 1));
4698       rtx term1 = const0_rtx, term2, term3;
4699
4700       if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4701         term1 = false, true = XEXP (true, 1), false = const0_rtx;
4702       else if (GET_CODE (true) == IOR
4703                && rtx_equal_p (XEXP (true, 1), false))
4704         term1 = false, true = XEXP (true, 0), false = const0_rtx;
4705       else if (GET_CODE (false) == IOR
4706                && rtx_equal_p (XEXP (false, 0), true))
4707         term1 = true, false = XEXP (false, 1), true = const0_rtx;
4708       else if (GET_CODE (false) == IOR
4709                && rtx_equal_p (XEXP (false, 1), true))
4710         term1 = true, false = XEXP (false, 0), true = const0_rtx;
4711
4712       term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4713       term3 = gen_binary (AND, GET_MODE (src),
4714                           gen_unary (NOT, GET_MODE (src), GET_MODE (src),
4715                                      XEXP (XEXP (src, 0), 0)),
4716                           false);
4717
4718       SUBST (SET_SRC (x),
4719              gen_binary (IOR, GET_MODE (src),
4720                          gen_binary (IOR, GET_MODE (src), term1, term2),
4721                          term3));
4722
4723       src = SET_SRC (x);
4724     }
4725
4726   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4727      whole thing fail.  */
4728   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4729     return src;
4730   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4731     return dest;
4732   else
4733     /* Convert this into a field assignment operation, if possible.  */
4734     return make_field_assignment (x);
4735 }
4736 \f
4737 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4738    result.  LAST is nonzero if this is the last retry.  */
4739
4740 static rtx
4741 simplify_logical (x, last)
4742      rtx x;
4743      int last;
4744 {
4745   enum machine_mode mode = GET_MODE (x);
4746   rtx op0 = XEXP (x, 0);
4747   rtx op1 = XEXP (x, 1);
4748
4749   switch (GET_CODE (x))
4750     {
4751     case AND:
4752       /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4753          insn (and may simplify more).  */
4754       if (GET_CODE (op0) == XOR
4755           && rtx_equal_p (XEXP (op0, 0), op1)
4756           && ! side_effects_p (op1))
4757         x = gen_binary (AND, mode,
4758                         gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
4759
4760       if (GET_CODE (op0) == XOR
4761           && rtx_equal_p (XEXP (op0, 1), op1)
4762           && ! side_effects_p (op1))
4763         x = gen_binary (AND, mode,
4764                         gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
4765
4766       /* Similarly for (~ (A ^ B)) & A.  */
4767       if (GET_CODE (op0) == NOT
4768           && GET_CODE (XEXP (op0, 0)) == XOR
4769           && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4770           && ! side_effects_p (op1))
4771         x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4772
4773       if (GET_CODE (op0) == NOT
4774           && GET_CODE (XEXP (op0, 0)) == XOR
4775           && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4776           && ! side_effects_p (op1))
4777         x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4778
4779       if (GET_CODE (op1) == CONST_INT)
4780         {
4781           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
4782
4783           /* If we have (ior (and (X C1) C2)) and the next restart would be
4784              the last, simplify this by making C1 as small as possible
4785              and then exit.  */
4786           if (last
4787               && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4788               && GET_CODE (XEXP (op0, 1)) == CONST_INT
4789               && GET_CODE (op1) == CONST_INT)
4790             return gen_binary (IOR, mode,
4791                                gen_binary (AND, mode, XEXP (op0, 0),
4792                                            GEN_INT (INTVAL (XEXP (op0, 1))
4793                                                     & ~ INTVAL (op1))), op1);
4794
4795           if (GET_CODE (x) != AND)
4796             return x;
4797
4798           if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
4799               || GET_RTX_CLASS (GET_CODE (x)) == '2')
4800             op0 = XEXP (x, 0), op1 = XEXP (x, 1);
4801         }
4802
4803       /* Convert (A | B) & A to A.  */
4804       if (GET_CODE (op0) == IOR
4805           && (rtx_equal_p (XEXP (op0, 0), op1)
4806               || rtx_equal_p (XEXP (op0, 1), op1))
4807           && ! side_effects_p (XEXP (op0, 0))
4808           && ! side_effects_p (XEXP (op0, 1)))
4809         return op1;
4810
4811       /* In the following group of tests (and those in case IOR below),
4812          we start with some combination of logical operations and apply
4813          the distributive law followed by the inverse distributive law.
4814          Most of the time, this results in no change.  However, if some of
4815          the operands are the same or inverses of each other, simplifications
4816          will result.
4817
4818          For example, (and (ior A B) (not B)) can occur as the result of
4819          expanding a bit field assignment.  When we apply the distributive
4820          law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4821          which then simplifies to (and (A (not B))).
4822
4823          If we have (and (ior A B) C), apply the distributive law and then
4824          the inverse distributive law to see if things simplify.  */
4825
4826       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
4827         {
4828           x = apply_distributive_law
4829             (gen_binary (GET_CODE (op0), mode,
4830                          gen_binary (AND, mode, XEXP (op0, 0), op1),
4831                          gen_binary (AND, mode, XEXP (op0, 1), op1)));
4832           if (GET_CODE (x) != AND)
4833             return x;
4834         }
4835
4836       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
4837         return apply_distributive_law
4838           (gen_binary (GET_CODE (op1), mode,
4839                        gen_binary (AND, mode, XEXP (op1, 0), op0),
4840                        gen_binary (AND, mode, XEXP (op1, 1), op0)));
4841
4842       /* Similarly, taking advantage of the fact that
4843          (and (not A) (xor B C)) == (xor (ior A B) (ior A C))  */
4844
4845       if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
4846         return apply_distributive_law
4847           (gen_binary (XOR, mode,
4848                        gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
4849                        gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
4850
4851       else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
4852         return apply_distributive_law
4853           (gen_binary (XOR, mode,
4854                        gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
4855                        gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
4856       break;
4857
4858     case IOR:
4859       /* (ior A C) is C if all bits of A that might be nonzero are on in C.  */
4860       if (GET_CODE (op1) == CONST_INT
4861           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4862           && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
4863         return op1;
4864
4865       /* Convert (A & B) | A to A.  */
4866       if (GET_CODE (op0) == AND
4867           && (rtx_equal_p (XEXP (op0, 0), op1)
4868               || rtx_equal_p (XEXP (op0, 1), op1))
4869           && ! side_effects_p (XEXP (op0, 0))
4870           && ! side_effects_p (XEXP (op0, 1)))
4871         return op1;
4872
4873       /* If we have (ior (and A B) C), apply the distributive law and then
4874          the inverse distributive law to see if things simplify.  */
4875
4876       if (GET_CODE (op0) == AND)
4877         {
4878           x = apply_distributive_law
4879             (gen_binary (AND, mode,
4880                          gen_binary (IOR, mode, XEXP (op0, 0), op1),
4881                          gen_binary (IOR, mode, XEXP (op0, 1), op1)));
4882
4883           if (GET_CODE (x) != IOR)
4884             return x;
4885         }
4886
4887       if (GET_CODE (op1) == AND)
4888         {
4889           x = apply_distributive_law
4890             (gen_binary (AND, mode,
4891                          gen_binary (IOR, mode, XEXP (op1, 0), op0),
4892                          gen_binary (IOR, mode, XEXP (op1, 1), op0)));
4893
4894           if (GET_CODE (x) != IOR)
4895             return x;
4896         }
4897
4898       /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4899          mode size to (rotate A CX).  */
4900
4901       if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
4902            || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
4903           && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
4904           && GET_CODE (XEXP (op0, 1)) == CONST_INT
4905           && GET_CODE (XEXP (op1, 1)) == CONST_INT
4906           && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
4907               == GET_MODE_BITSIZE (mode)))
4908         return gen_rtx (ROTATE, mode, XEXP (op0, 0),
4909                         (GET_CODE (op0) == ASHIFT
4910                          ? XEXP (op0, 1) : XEXP (op1, 1)));
4911
4912       /* If OP0 is (ashiftrt (plus ...) C), it might actually be
4913          a (sign_extend (plus ...)).  If so, OP1 is a CONST_INT, and the PLUS
4914          does not affect any of the bits in OP1, it can really be done
4915          as a PLUS and we can associate.  We do this by seeing if OP1
4916          can be safely shifted left C bits.  */
4917       if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
4918           && GET_CODE (XEXP (op0, 0)) == PLUS
4919           && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
4920           && GET_CODE (XEXP (op0, 1)) == CONST_INT
4921           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
4922         {
4923           int count = INTVAL (XEXP (op0, 1));
4924           HOST_WIDE_INT mask = INTVAL (op1) << count;
4925
4926           if (mask >> count == INTVAL (op1)
4927               && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
4928             {
4929               SUBST (XEXP (XEXP (op0, 0), 1),
4930                      GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
4931               return op0;
4932             }
4933         }
4934       break;
4935
4936     case XOR:
4937       /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4938          Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4939          (NOT y).  */
4940       {
4941         int num_negated = 0;
4942
4943         if (GET_CODE (op0) == NOT)
4944           num_negated++, op0 = XEXP (op0, 0);
4945         if (GET_CODE (op1) == NOT)
4946           num_negated++, op1 = XEXP (op1, 0);
4947
4948         if (num_negated == 2)
4949           {
4950             SUBST (XEXP (x, 0), op0);
4951             SUBST (XEXP (x, 1), op1);
4952           }
4953         else if (num_negated == 1)
4954           return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
4955       }
4956
4957       /* Convert (xor (and A B) B) to (and (not A) B).  The latter may
4958          correspond to a machine insn or result in further simplifications
4959          if B is a constant.  */
4960
4961       if (GET_CODE (op0) == AND
4962           && rtx_equal_p (XEXP (op0, 1), op1)
4963           && ! side_effects_p (op1))
4964         return gen_binary (AND, mode,
4965                            gen_unary (NOT, mode, mode, XEXP (op0, 0)),
4966                            op1);
4967
4968       else if (GET_CODE (op0) == AND
4969                && rtx_equal_p (XEXP (op0, 0), op1)
4970                && ! side_effects_p (op1))
4971         return gen_binary (AND, mode,
4972                            gen_unary (NOT, mode, mode, XEXP (op0, 1)),
4973                            op1);
4974
4975       /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4976          comparison if STORE_FLAG_VALUE is 1.  */
4977       if (STORE_FLAG_VALUE == 1
4978           && op1 == const1_rtx
4979           && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4980           && reversible_comparison_p (op0))
4981         return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4982                                 mode, XEXP (op0, 0), XEXP (op0, 1));
4983
4984       /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
4985          is (lt foo (const_int 0)), so we can perform the above
4986          simplification if STORE_FLAG_VALUE is 1.  */
4987
4988       if (STORE_FLAG_VALUE == 1
4989           && op1 == const1_rtx
4990           && GET_CODE (op0) == LSHIFTRT
4991           && GET_CODE (XEXP (op0, 1)) == CONST_INT
4992           && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
4993         return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
4994
4995       /* (xor (comparison foo bar) (const_int sign-bit))
4996          when STORE_FLAG_VALUE is the sign bit.  */
4997       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4998           && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4999               == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5000           && op1 == const_true_rtx
5001           && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5002           && reversible_comparison_p (op0))
5003         return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5004                                 mode, XEXP (op0, 0), XEXP (op0, 1));
5005       break;
5006
5007     default:
5008       abort ();
5009     }
5010
5011   return x;
5012 }
5013 \f
5014 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5015    operations" because they can be replaced with two more basic operations.
5016    ZERO_EXTEND is also considered "compound" because it can be replaced with
5017    an AND operation, which is simpler, though only one operation.
5018
5019    The function expand_compound_operation is called with an rtx expression
5020    and will convert it to the appropriate shifts and AND operations,
5021    simplifying at each stage.
5022
5023    The function make_compound_operation is called to convert an expression
5024    consisting of shifts and ANDs into the equivalent compound expression.
5025    It is the inverse of this function, loosely speaking.  */
5026
5027 static rtx
5028 expand_compound_operation (x)
5029      rtx x;
5030 {
5031   int pos = 0, len;
5032   int unsignedp = 0;
5033   int modewidth;
5034   rtx tem;
5035
5036   switch (GET_CODE (x))
5037     {
5038     case ZERO_EXTEND:
5039       unsignedp = 1;
5040     case SIGN_EXTEND:
5041       /* We can't necessarily use a const_int for a multiword mode;
5042          it depends on implicitly extending the value.
5043          Since we don't know the right way to extend it,
5044          we can't tell whether the implicit way is right.
5045
5046          Even for a mode that is no wider than a const_int,
5047          we can't win, because we need to sign extend one of its bits through
5048          the rest of it, and we don't know which bit.  */
5049       if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5050         return x;
5051
5052       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5053          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
5054          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5055          reloaded. If not for that, MEM's would very rarely be safe.
5056
5057          Reject MODEs bigger than a word, because we might not be able
5058          to reference a two-register group starting with an arbitrary register
5059          (and currently gen_lowpart might crash for a SUBREG).  */
5060
5061       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5062         return x;
5063
5064       len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5065       /* If the inner object has VOIDmode (the only way this can happen
5066          is if it is a ASM_OPERANDS), we can't do anything since we don't
5067          know how much masking to do.  */
5068       if (len == 0)
5069         return x;
5070
5071       break;
5072
5073     case ZERO_EXTRACT:
5074       unsignedp = 1;
5075     case SIGN_EXTRACT:
5076       /* If the operand is a CLOBBER, just return it.  */
5077       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5078         return XEXP (x, 0);
5079
5080       if (GET_CODE (XEXP (x, 1)) != CONST_INT
5081           || GET_CODE (XEXP (x, 2)) != CONST_INT
5082           || GET_MODE (XEXP (x, 0)) == VOIDmode)
5083         return x;
5084
5085       len = INTVAL (XEXP (x, 1));
5086       pos = INTVAL (XEXP (x, 2));
5087
5088       /* If this goes outside the object being extracted, replace the object
5089          with a (use (mem ...)) construct that only combine understands
5090          and is used only for this purpose.  */
5091       if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5092         SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
5093
5094       if (BITS_BIG_ENDIAN)
5095         pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5096
5097       break;
5098
5099     default:
5100       return x;
5101     }
5102
5103   /* We can optimize some special cases of ZERO_EXTEND.  */
5104   if (GET_CODE (x) == ZERO_EXTEND)
5105     {
5106       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5107          know that the last value didn't have any inappropriate bits
5108          set.  */
5109       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5110           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5111           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5112           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5113               & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5114         return XEXP (XEXP (x, 0), 0);
5115
5116       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5117       if (GET_CODE (XEXP (x, 0)) == SUBREG
5118           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5119           && subreg_lowpart_p (XEXP (x, 0))
5120           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5121           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5122               & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0)
5123         return SUBREG_REG (XEXP (x, 0));
5124
5125       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5126          is a comparison and STORE_FLAG_VALUE permits.  This is like
5127          the first case, but it works even when GET_MODE (x) is larger
5128          than HOST_WIDE_INT.  */
5129       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5130           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5131           && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5132           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5133               <= HOST_BITS_PER_WIDE_INT)
5134           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5135               & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5136         return XEXP (XEXP (x, 0), 0);
5137
5138       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5139       if (GET_CODE (XEXP (x, 0)) == SUBREG
5140           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5141           && subreg_lowpart_p (XEXP (x, 0))
5142           && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5143           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5144               <= HOST_BITS_PER_WIDE_INT)
5145           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5146               & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5147         return SUBREG_REG (XEXP (x, 0));
5148
5149       /* If sign extension is cheaper than zero extension, then use it
5150          if we know that no extraneous bits are set, and that the high
5151          bit is not set.  */
5152       if (flag_expensive_optimizations
5153           && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5154                && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5155                     & ~ (((unsigned HOST_WIDE_INT)
5156                           GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5157                          >> 1))
5158                    == 0))
5159               || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5160                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5161                       <= HOST_BITS_PER_WIDE_INT)
5162                   && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5163                        & ~ (((unsigned HOST_WIDE_INT)
5164                              GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5165                             >> 1))
5166                       == 0))))
5167         {
5168           rtx temp = gen_rtx (SIGN_EXTEND, GET_MODE (x), XEXP (x, 0));
5169
5170           if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5171             return expand_compound_operation (temp);
5172         }
5173     }
5174
5175   /* If we reach here, we want to return a pair of shifts.  The inner
5176      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
5177      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
5178      logical depending on the value of UNSIGNEDP.
5179
5180      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5181      converted into an AND of a shift.
5182
5183      We must check for the case where the left shift would have a negative
5184      count.  This can happen in a case like (x >> 31) & 255 on machines
5185      that can't shift by a constant.  On those machines, we would first
5186      combine the shift with the AND to produce a variable-position
5187      extraction.  Then the constant of 31 would be substituted in to produce
5188      a such a position.  */
5189
5190   modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5191   if (modewidth >= pos - len)
5192     tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5193                                 GET_MODE (x),
5194                                 simplify_shift_const (NULL_RTX, ASHIFT,
5195                                                       GET_MODE (x),
5196                                                       XEXP (x, 0),
5197                                                       modewidth - pos - len),
5198                                 modewidth - len);
5199
5200   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5201     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5202                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
5203                                                         GET_MODE (x),
5204                                                         XEXP (x, 0), pos),
5205                                   ((HOST_WIDE_INT) 1 << len) - 1);
5206   else
5207     /* Any other cases we can't handle.  */
5208     return x;
5209
5210
5211   /* If we couldn't do this for some reason, return the original
5212      expression.  */
5213   if (GET_CODE (tem) == CLOBBER)
5214     return x;
5215
5216   return tem;
5217 }
5218 \f
5219 /* X is a SET which contains an assignment of one object into
5220    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5221    or certain SUBREGS). If possible, convert it into a series of
5222    logical operations.
5223
5224    We half-heartedly support variable positions, but do not at all
5225    support variable lengths.  */
5226
5227 static rtx
5228 expand_field_assignment (x)
5229      rtx x;
5230 {
5231   rtx inner;
5232   rtx pos;                      /* Always counts from low bit.  */
5233   int len;
5234   rtx mask;
5235   enum machine_mode compute_mode;
5236
5237   /* Loop until we find something we can't simplify.  */
5238   while (1)
5239     {
5240       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5241           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5242         {
5243           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5244           len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5245           pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5246         }
5247       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5248                && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5249         {
5250           inner = XEXP (SET_DEST (x), 0);
5251           len = INTVAL (XEXP (SET_DEST (x), 1));
5252           pos = XEXP (SET_DEST (x), 2);
5253
5254           /* If the position is constant and spans the width of INNER,
5255              surround INNER  with a USE to indicate this.  */
5256           if (GET_CODE (pos) == CONST_INT
5257               && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5258             inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
5259
5260           if (BITS_BIG_ENDIAN)
5261             {
5262               if (GET_CODE (pos) == CONST_INT)
5263                 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5264                                - INTVAL (pos));
5265               else if (GET_CODE (pos) == MINUS
5266                        && GET_CODE (XEXP (pos, 1)) == CONST_INT
5267                        && (INTVAL (XEXP (pos, 1))
5268                            == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5269                 /* If position is ADJUST - X, new position is X.  */
5270                 pos = XEXP (pos, 0);
5271               else
5272                 pos = gen_binary (MINUS, GET_MODE (pos),
5273                                   GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5274                                            - len),
5275                                   pos);
5276             }
5277         }
5278
5279       /* A SUBREG between two modes that occupy the same numbers of words
5280          can be done by moving the SUBREG to the source.  */
5281       else if (GET_CODE (SET_DEST (x)) == SUBREG
5282                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5283                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5284                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5285                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5286         {
5287           x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
5288                        gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5289                                                 SET_SRC (x)));
5290           continue;
5291         }
5292       else
5293         break;
5294
5295       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5296         inner = SUBREG_REG (inner);
5297
5298       compute_mode = GET_MODE (inner);
5299
5300       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
5301       if (len < HOST_BITS_PER_WIDE_INT)
5302         mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5303       else
5304         break;
5305
5306       /* Now compute the equivalent expression.  Make a copy of INNER
5307          for the SET_DEST in case it is a MEM into which we will substitute;
5308          we don't want shared RTL in that case.  */
5309       x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
5310                    gen_binary (IOR, compute_mode,
5311                                gen_binary (AND, compute_mode,
5312                                            gen_unary (NOT, compute_mode,
5313                                                       compute_mode,
5314                                                       gen_binary (ASHIFT,
5315                                                                   compute_mode,
5316                                                                   mask, pos)),
5317                                            inner),
5318                                gen_binary (ASHIFT, compute_mode,
5319                                            gen_binary (AND, compute_mode,
5320                                                        gen_lowpart_for_combine
5321                                                        (compute_mode,
5322                                                         SET_SRC (x)),
5323                                                        mask),
5324                                            pos)));
5325     }
5326
5327   return x;
5328 }
5329 \f
5330 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
5331    it is an RTX that represents a variable starting position; otherwise,
5332    POS is the (constant) starting bit position (counted from the LSB).
5333
5334    INNER may be a USE.  This will occur when we started with a bitfield
5335    that went outside the boundary of the object in memory, which is
5336    allowed on most machines.  To isolate this case, we produce a USE
5337    whose mode is wide enough and surround the MEM with it.  The only
5338    code that understands the USE is this routine.  If it is not removed,
5339    it will cause the resulting insn not to match.
5340
5341    UNSIGNEDP is non-zero for an unsigned reference and zero for a
5342    signed reference.
5343
5344    IN_DEST is non-zero if this is a reference in the destination of a
5345    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If non-zero,
5346    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5347    be used.
5348
5349    IN_COMPARE is non-zero if we are in a COMPARE.  This means that a
5350    ZERO_EXTRACT should be built even for bits starting at bit 0.
5351
5352    MODE is the desired mode of the result (if IN_DEST == 0).
5353
5354    The result is an RTX for the extraction or NULL_RTX if the target
5355    can't handle it.  */
5356
5357 static rtx
5358 make_extraction (mode, inner, pos, pos_rtx, len,
5359                  unsignedp, in_dest, in_compare)
5360      enum machine_mode mode;
5361      rtx inner;
5362      int pos;
5363      rtx pos_rtx;
5364      int len;
5365      int unsignedp;
5366      int in_dest, in_compare;
5367 {
5368   /* This mode describes the size of the storage area
5369      to fetch the overall value from.  Within that, we
5370      ignore the POS lowest bits, etc.  */
5371   enum machine_mode is_mode = GET_MODE (inner);
5372   enum machine_mode inner_mode;
5373   enum machine_mode wanted_inner_mode = byte_mode;
5374   enum machine_mode wanted_inner_reg_mode = word_mode;
5375   enum machine_mode pos_mode = word_mode;
5376   enum machine_mode extraction_mode = word_mode;
5377   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5378   int spans_byte = 0;
5379   rtx new = 0;
5380   rtx orig_pos_rtx = pos_rtx;
5381   int orig_pos;
5382
5383   /* Get some information about INNER and get the innermost object.  */
5384   if (GET_CODE (inner) == USE)
5385     /* (use:SI (mem:QI foo)) stands for (mem:SI foo).  */
5386     /* We don't need to adjust the position because we set up the USE
5387        to pretend that it was a full-word object.  */
5388     spans_byte = 1, inner = XEXP (inner, 0);
5389   else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5390     {
5391       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5392          consider just the QI as the memory to extract from.
5393          The subreg adds or removes high bits; its mode is
5394          irrelevant to the meaning of this extraction,
5395          since POS and LEN count from the lsb.  */
5396       if (GET_CODE (SUBREG_REG (inner)) == MEM)
5397         is_mode = GET_MODE (SUBREG_REG (inner));
5398       inner = SUBREG_REG (inner);
5399     }
5400
5401   inner_mode = GET_MODE (inner);
5402
5403   if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5404     pos = INTVAL (pos_rtx), pos_rtx = 0;
5405
5406   /* See if this can be done without an extraction.  We never can if the
5407      width of the field is not the same as that of some integer mode. For
5408      registers, we can only avoid the extraction if the position is at the
5409      low-order bit and this is either not in the destination or we have the
5410      appropriate STRICT_LOW_PART operation available.
5411
5412      For MEM, we can avoid an extract if the field starts on an appropriate
5413      boundary and we can change the mode of the memory reference.  However,
5414      we cannot directly access the MEM if we have a USE and the underlying
5415      MEM is not TMODE.  This combination means that MEM was being used in a
5416      context where bits outside its mode were being referenced; that is only
5417      valid in bit-field insns.  */
5418
5419   if (tmode != BLKmode
5420       && ! (spans_byte && inner_mode != tmode)
5421       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5422            && GET_CODE (inner) != MEM
5423            && (! in_dest
5424                || (GET_CODE (inner) == REG
5425                    && (movstrict_optab->handlers[(int) tmode].insn_code
5426                        != CODE_FOR_nothing))))
5427           || (GET_CODE (inner) == MEM && pos_rtx == 0
5428               && (pos
5429                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5430                      : BITS_PER_UNIT)) == 0
5431               /* We can't do this if we are widening INNER_MODE (it
5432                  may not be aligned, for one thing).  */
5433               && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5434               && (inner_mode == tmode
5435                   || (! mode_dependent_address_p (XEXP (inner, 0))
5436                       && ! MEM_VOLATILE_P (inner))))))
5437     {
5438       /* If INNER is a MEM, make a new MEM that encompasses just the desired
5439          field.  If the original and current mode are the same, we need not
5440          adjust the offset.  Otherwise, we do if bytes big endian.
5441
5442          If INNER is not a MEM, get a piece consisting of just the field
5443          of interest (in this case POS % BITS_PER_WORD must be 0).  */
5444
5445       if (GET_CODE (inner) == MEM)
5446         {
5447           int offset;
5448           /* POS counts from lsb, but make OFFSET count in memory order.  */
5449           if (BYTES_BIG_ENDIAN)
5450             offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5451           else
5452             offset = pos / BITS_PER_UNIT;
5453
5454           new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
5455           RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5456           MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
5457           MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
5458         }
5459       else if (GET_CODE (inner) == REG)
5460         {
5461           /* We can't call gen_lowpart_for_combine here since we always want
5462              a SUBREG and it would sometimes return a new hard register.  */
5463           if (tmode != inner_mode)
5464             new = gen_rtx (SUBREG, tmode, inner,
5465                            (WORDS_BIG_ENDIAN
5466                             && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5467                             ? (((GET_MODE_SIZE (inner_mode)
5468                                  - GET_MODE_SIZE (tmode))
5469                                 / UNITS_PER_WORD)
5470                                - pos / BITS_PER_WORD)
5471                             : pos / BITS_PER_WORD));
5472           else
5473             new = inner;
5474         }
5475       else
5476         new = force_to_mode (inner, tmode,
5477                              len >= HOST_BITS_PER_WIDE_INT
5478                              ? GET_MODE_MASK (tmode)
5479                              : ((HOST_WIDE_INT) 1 << len) - 1,
5480                              NULL_RTX, 0);
5481
5482       /* If this extraction is going into the destination of a SET,
5483          make a STRICT_LOW_PART unless we made a MEM.  */
5484
5485       if (in_dest)
5486         return (GET_CODE (new) == MEM ? new
5487                 : (GET_CODE (new) != SUBREG
5488                    ? gen_rtx (CLOBBER, tmode, const0_rtx)
5489                    : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5490
5491       /* Otherwise, sign- or zero-extend unless we already are in the
5492          proper mode.  */
5493
5494       return (mode == tmode ? new
5495               : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5496                                  mode, new));
5497     }
5498
5499   /* Unless this is a COMPARE or we have a funny memory reference,
5500      don't do anything with zero-extending field extracts starting at
5501      the low-order bit since they are simple AND operations.  */
5502   if (pos_rtx == 0 && pos == 0 && ! in_dest
5503       && ! in_compare && ! spans_byte && unsignedp)
5504     return 0;
5505
5506   /* Unless we are allowed to span bytes, reject this if we would be
5507      spanning bytes or if the position is not a constant and the length
5508      is not 1.  In all other cases, we would only be going outside
5509      out object in cases when an original shift would have been
5510      undefined.  */
5511   if (! spans_byte
5512       && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5513           || (pos_rtx != 0 && len != 1)))
5514     return 0;
5515
5516   /* Get the mode to use should INNER not be a MEM, the mode for the position,
5517      and the mode for the result.  */
5518 #ifdef HAVE_insv
5519   if (in_dest)
5520     {
5521       wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
5522       pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
5523       extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
5524     }
5525 #endif
5526
5527 #ifdef HAVE_extzv
5528   if (! in_dest && unsignedp)
5529     {
5530       wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
5531       pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
5532       extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
5533     }
5534 #endif
5535
5536 #ifdef HAVE_extv
5537   if (! in_dest && ! unsignedp)
5538     {
5539       wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
5540       pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
5541       extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
5542     }
5543 #endif
5544
5545   /* Never narrow an object, since that might not be safe.  */
5546
5547   if (mode != VOIDmode
5548       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5549     extraction_mode = mode;
5550
5551   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5552       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5553     pos_mode = GET_MODE (pos_rtx);
5554
5555   /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5556      if we have to change the mode of memory and cannot, the desired mode is
5557      EXTRACTION_MODE.  */
5558   if (GET_CODE (inner) != MEM)
5559     wanted_inner_mode = wanted_inner_reg_mode;
5560   else if (inner_mode != wanted_inner_mode
5561            && (mode_dependent_address_p (XEXP (inner, 0))
5562                || MEM_VOLATILE_P (inner)))
5563     wanted_inner_mode = extraction_mode;
5564
5565   orig_pos = pos;
5566
5567   if (BITS_BIG_ENDIAN)
5568     {
5569       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5570          BITS_BIG_ENDIAN style.  If position is constant, compute new
5571          position.  Otherwise, build subtraction.
5572          Note that POS is relative to the mode of the original argument.
5573          If it's a MEM we need to recompute POS relative to that.
5574          However, if we're extracting from (or inserting into) a register,
5575          we want to recompute POS relative to wanted_inner_mode.  */
5576       int width = (GET_CODE (inner) == MEM
5577                    ? GET_MODE_BITSIZE (is_mode)
5578                    : GET_MODE_BITSIZE (wanted_inner_mode));
5579
5580       if (pos_rtx == 0)
5581         pos = width - len - pos;
5582       else
5583         pos_rtx
5584           = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5585                              GEN_INT (width - len), pos_rtx);
5586       /* POS may be less than 0 now, but we check for that below.
5587          Note that it can only be less than 0 if GET_CODE (inner) != MEM.  */
5588     }
5589
5590   /* If INNER has a wider mode, make it smaller.  If this is a constant
5591      extract, try to adjust the byte to point to the byte containing
5592      the value.  */
5593   if (wanted_inner_mode != VOIDmode
5594       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
5595       && ((GET_CODE (inner) == MEM
5596            && (inner_mode == wanted_inner_mode
5597                || (! mode_dependent_address_p (XEXP (inner, 0))
5598                    && ! MEM_VOLATILE_P (inner))))))
5599     {
5600       int offset = 0;
5601
5602       /* The computations below will be correct if the machine is big
5603          endian in both bits and bytes or little endian in bits and bytes.
5604          If it is mixed, we must adjust.  */
5605
5606       /* If bytes are big endian and we had a paradoxical SUBREG, we must
5607          adjust OFFSET to compensate.  */
5608       if (BYTES_BIG_ENDIAN
5609           && ! spans_byte
5610           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5611         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5612
5613       /* If this is a constant position, we can move to the desired byte.  */
5614       if (pos_rtx == 0)
5615         {
5616           offset += pos / BITS_PER_UNIT;
5617           pos %= GET_MODE_BITSIZE (wanted_inner_mode);
5618         }
5619
5620       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5621           && ! spans_byte
5622           && is_mode != wanted_inner_mode)
5623         offset = (GET_MODE_SIZE (is_mode)
5624                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
5625
5626       if (offset != 0 || inner_mode != wanted_inner_mode)
5627         {
5628           rtx newmem = gen_rtx (MEM, wanted_inner_mode,
5629                                 plus_constant (XEXP (inner, 0), offset));
5630           RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5631           MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5632           MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5633           inner = newmem;
5634         }
5635     }
5636
5637   /* If INNER is not memory, we can always get it into the proper mode.  If we
5638      are changing its mode, POS must be a constant and smaller than the size
5639      of the new mode.  */
5640   else if (GET_CODE (inner) != MEM)
5641     {
5642       if (GET_MODE (inner) != wanted_inner_mode
5643           && (pos_rtx != 0
5644               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5645         return 0;
5646
5647       inner = force_to_mode (inner, wanted_inner_mode,
5648                              pos_rtx
5649                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5650                              ? GET_MODE_MASK (wanted_inner_mode)
5651                              : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5652                              NULL_RTX, 0);
5653     }
5654
5655   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
5656      have to zero extend.  Otherwise, we can just use a SUBREG.  */
5657   if (pos_rtx != 0
5658       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5659     pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5660   else if (pos_rtx != 0
5661            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5662     pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5663
5664   /* Make POS_RTX unless we already have it and it is correct.  If we don't
5665      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5666      be a CONST_INT.  */
5667   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5668     pos_rtx = orig_pos_rtx;
5669
5670   else if (pos_rtx == 0)
5671     pos_rtx = GEN_INT (pos);
5672
5673   /* Make the required operation.  See if we can use existing rtx.  */
5674   new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5675                          extraction_mode, inner, GEN_INT (len), pos_rtx);
5676   if (! in_dest)
5677     new = gen_lowpart_for_combine (mode, new);
5678
5679   return new;
5680 }
5681 \f
5682 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5683    with any other operations in X.  Return X without that shift if so.  */
5684
5685 static rtx
5686 extract_left_shift (x, count)
5687      rtx x;
5688      int count;
5689 {
5690   enum rtx_code code = GET_CODE (x);
5691   enum machine_mode mode = GET_MODE (x);
5692   rtx tem;
5693
5694   switch (code)
5695     {
5696     case ASHIFT:
5697       /* This is the shift itself.  If it is wide enough, we will return
5698          either the value being shifted if the shift count is equal to
5699          COUNT or a shift for the difference.  */
5700       if (GET_CODE (XEXP (x, 1)) == CONST_INT
5701           && INTVAL (XEXP (x, 1)) >= count)
5702         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5703                                      INTVAL (XEXP (x, 1)) - count);
5704       break;
5705
5706     case NEG:  case NOT:
5707       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5708         return gen_unary (code, mode, mode, tem);
5709
5710       break;
5711
5712     case PLUS:  case IOR:  case XOR:  case AND:
5713       /* If we can safely shift this constant and we find the inner shift,
5714          make a new operation.  */
5715       if (GET_CODE (XEXP (x,1)) == CONST_INT
5716           && (INTVAL (XEXP (x, 1)) & (((HOST_WIDE_INT) 1 << count)) - 1) == 0
5717           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5718         return gen_binary (code, mode, tem,
5719                            GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5720
5721       break;
5722
5723     default:
5724       break;
5725     }
5726
5727   return 0;
5728 }
5729 \f
5730 /* Look at the expression rooted at X.  Look for expressions
5731    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5732    Form these expressions.
5733
5734    Return the new rtx, usually just X.
5735
5736    Also, for machines like the Vax that don't have logical shift insns,
5737    try to convert logical to arithmetic shift operations in cases where
5738    they are equivalent.  This undoes the canonicalizations to logical
5739    shifts done elsewhere.
5740
5741    We try, as much as possible, to re-use rtl expressions to save memory.
5742
5743    IN_CODE says what kind of expression we are processing.  Normally, it is
5744    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
5745    being kludges), it is MEM.  When processing the arguments of a comparison
5746    or a COMPARE against zero, it is COMPARE.  */
5747
5748 static rtx
5749 make_compound_operation (x, in_code)
5750      rtx x;
5751      enum rtx_code in_code;
5752 {
5753   enum rtx_code code = GET_CODE (x);
5754   enum machine_mode mode = GET_MODE (x);
5755   int mode_width = GET_MODE_BITSIZE (mode);
5756   rtx rhs, lhs;
5757   enum rtx_code next_code;
5758   int i;
5759   rtx new = 0;
5760   rtx tem;
5761   char *fmt;
5762
5763   /* Select the code to be used in recursive calls.  Once we are inside an
5764      address, we stay there.  If we have a comparison, set to COMPARE,
5765      but once inside, go back to our default of SET.  */
5766
5767   next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
5768                : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5769                   && XEXP (x, 1) == const0_rtx) ? COMPARE
5770                : in_code == COMPARE ? SET : in_code);
5771
5772   /* Process depending on the code of this operation.  If NEW is set
5773      non-zero, it will be returned.  */
5774
5775   switch (code)
5776     {
5777     case ASHIFT:
5778       /* Convert shifts by constants into multiplications if inside
5779          an address.  */
5780       if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5781           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5782           && INTVAL (XEXP (x, 1)) >= 0)
5783         {
5784           new = make_compound_operation (XEXP (x, 0), next_code);
5785           new = gen_rtx_combine (MULT, mode, new,
5786                                  GEN_INT ((HOST_WIDE_INT) 1
5787                                           << INTVAL (XEXP (x, 1))));
5788         }
5789       break;
5790
5791     case AND:
5792       /* If the second operand is not a constant, we can't do anything
5793          with it.  */
5794       if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5795         break;
5796
5797       /* If the constant is a power of two minus one and the first operand
5798          is a logical right shift, make an extraction.  */
5799       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5800           && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5801         {
5802           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5803           new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5804                                  0, in_code == COMPARE);
5805         }
5806
5807       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
5808       else if (GET_CODE (XEXP (x, 0)) == SUBREG
5809                && subreg_lowpart_p (XEXP (x, 0))
5810                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5811                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5812         {
5813           new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5814                                          next_code);
5815           new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
5816                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5817                                  0, in_code == COMPARE);
5818         }
5819       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
5820       else if ((GET_CODE (XEXP (x, 0)) == XOR
5821                 || GET_CODE (XEXP (x, 0)) == IOR)
5822                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5823                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5824                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5825         {
5826           /* Apply the distributive law, and then try to make extractions.  */
5827           new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
5828                                  gen_rtx (AND, mode, XEXP (XEXP (x, 0), 0),
5829                                           XEXP (x, 1)),
5830                                  gen_rtx (AND, mode, XEXP (XEXP (x, 0), 1),
5831                                           XEXP (x, 1)));
5832           new = make_compound_operation (new, in_code);
5833         }
5834
5835       /* If we are have (and (rotate X C) M) and C is larger than the number
5836          of bits in M, this is an extraction.  */
5837
5838       else if (GET_CODE (XEXP (x, 0)) == ROTATE
5839                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5840                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5841                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
5842         {
5843           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5844           new = make_extraction (mode, new,
5845                                  (GET_MODE_BITSIZE (mode)
5846                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
5847                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
5848         }
5849
5850       /* On machines without logical shifts, if the operand of the AND is
5851          a logical shift and our mask turns off all the propagated sign
5852          bits, we can replace the logical shift with an arithmetic shift.  */
5853       else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5854                && (lshr_optab->handlers[(int) mode].insn_code
5855                    == CODE_FOR_nothing)
5856                && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5857                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5858                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5859                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5860                && mode_width <= HOST_BITS_PER_WIDE_INT)
5861         {
5862           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
5863
5864           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5865           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5866             SUBST (XEXP (x, 0),
5867                    gen_rtx_combine (ASHIFTRT, mode,
5868                                     make_compound_operation (XEXP (XEXP (x, 0), 0),
5869                                                              next_code),
5870                                     XEXP (XEXP (x, 0), 1)));
5871         }
5872
5873       /* If the constant is one less than a power of two, this might be
5874          representable by an extraction even if no shift is present.
5875          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5876          we are in a COMPARE.  */
5877       else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5878         new = make_extraction (mode,
5879                                make_compound_operation (XEXP (x, 0),
5880                                                         next_code),
5881                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
5882
5883       /* If we are in a comparison and this is an AND with a power of two,
5884          convert this into the appropriate bit extract.  */
5885       else if (in_code == COMPARE
5886                && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5887         new = make_extraction (mode,
5888                                make_compound_operation (XEXP (x, 0),
5889                                                         next_code),
5890                                i, NULL_RTX, 1, 1, 0, 1);
5891
5892       break;
5893
5894     case LSHIFTRT:
5895       /* If the sign bit is known to be zero, replace this with an
5896          arithmetic shift.  */
5897       if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5898           && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5899           && mode_width <= HOST_BITS_PER_WIDE_INT
5900           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
5901         {
5902           new = gen_rtx_combine (ASHIFTRT, mode,
5903                                  make_compound_operation (XEXP (x, 0),
5904                                                           next_code),
5905                                  XEXP (x, 1));
5906           break;
5907         }
5908
5909       /* ... fall through ...  */
5910
5911     case ASHIFTRT:
5912       lhs = XEXP (x, 0);
5913       rhs = XEXP (x, 1);
5914
5915       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5916          this is a SIGN_EXTRACT.  */
5917       if (GET_CODE (rhs) == CONST_INT
5918           && GET_CODE (lhs) == ASHIFT
5919           && GET_CODE (XEXP (lhs, 1)) == CONST_INT
5920           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
5921         {
5922           new = make_compound_operation (XEXP (lhs, 0), next_code);
5923           new = make_extraction (mode, new,
5924                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
5925                                  NULL_RTX, mode_width - INTVAL (rhs),
5926                                  code == LSHIFTRT, 0, in_code == COMPARE);
5927         }
5928
5929       /* See if we have operations between an ASHIFTRT and an ASHIFT.
5930          If so, try to merge the shifts into a SIGN_EXTEND.  We could
5931          also do this for some cases of SIGN_EXTRACT, but it doesn't
5932          seem worth the effort; the case checked for occurs on Alpha.  */
5933
5934       if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
5935           && ! (GET_CODE (lhs) == SUBREG
5936                 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
5937           && GET_CODE (rhs) == CONST_INT
5938           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
5939           && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
5940         new = make_extraction (mode, make_compound_operation (new, next_code),
5941                                0, NULL_RTX, mode_width - INTVAL (rhs),
5942                                code == LSHIFTRT, 0, in_code == COMPARE);
5943
5944       break;
5945
5946     case SUBREG:
5947       /* Call ourselves recursively on the inner expression.  If we are
5948          narrowing the object and it has a different RTL code from
5949          what it originally did, do this SUBREG as a force_to_mode.  */
5950
5951       tem = make_compound_operation (SUBREG_REG (x), in_code);
5952       if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
5953           && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
5954           && subreg_lowpart_p (x))
5955         {
5956           rtx newer = force_to_mode (tem, mode,
5957                                      GET_MODE_MASK (mode), NULL_RTX, 0);
5958
5959           /* If we have something other than a SUBREG, we might have
5960              done an expansion, so rerun outselves.  */
5961           if (GET_CODE (newer) != SUBREG)
5962             newer = make_compound_operation (newer, in_code);
5963
5964           return newer;
5965         }
5966       break;
5967
5968     default:
5969       break;
5970     }
5971
5972   if (new)
5973     {
5974       x = gen_lowpart_for_combine (mode, new);
5975       code = GET_CODE (x);
5976     }
5977
5978   /* Now recursively process each operand of this operation.  */
5979   fmt = GET_RTX_FORMAT (code);
5980   for (i = 0; i < GET_RTX_LENGTH (code); i++)
5981     if (fmt[i] == 'e')
5982       {
5983         new = make_compound_operation (XEXP (x, i), next_code);
5984         SUBST (XEXP (x, i), new);
5985       }
5986
5987   return x;
5988 }
5989 \f
5990 /* Given M see if it is a value that would select a field of bits
5991     within an item, but not the entire word.  Return -1 if not.
5992     Otherwise, return the starting position of the field, where 0 is the
5993     low-order bit.
5994
5995    *PLEN is set to the length of the field.  */
5996
5997 static int
5998 get_pos_from_mask (m, plen)
5999      unsigned HOST_WIDE_INT m;
6000      int *plen;
6001 {
6002   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
6003   int pos = exact_log2 (m & - m);
6004
6005   if (pos < 0)
6006     return -1;
6007
6008   /* Now shift off the low-order zero bits and see if we have a power of
6009      two minus 1.  */
6010   *plen = exact_log2 ((m >> pos) + 1);
6011
6012   if (*plen <= 0)
6013     return -1;
6014
6015   return pos;
6016 }
6017 \f
6018 /* See if X can be simplified knowing that we will only refer to it in
6019    MODE and will only refer to those bits that are nonzero in MASK.
6020    If other bits are being computed or if masking operations are done
6021    that select a superset of the bits in MASK, they can sometimes be
6022    ignored.
6023
6024    Return a possibly simplified expression, but always convert X to
6025    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
6026
6027    Also, if REG is non-zero and X is a register equal in value to REG,
6028    replace X with REG.
6029
6030    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6031    are all off in X.  This is used when X will be complemented, by either
6032    NOT, NEG, or XOR.  */
6033
6034 static rtx
6035 force_to_mode (x, mode, mask, reg, just_select)
6036      rtx x;
6037      enum machine_mode mode;
6038      unsigned HOST_WIDE_INT mask;
6039      rtx reg;
6040      int just_select;
6041 {
6042   enum rtx_code code = GET_CODE (x);
6043   int next_select = just_select || code == XOR || code == NOT || code == NEG;
6044   enum machine_mode op_mode;
6045   unsigned HOST_WIDE_INT fuller_mask, nonzero;
6046   rtx op0, op1, temp;
6047
6048   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
6049      code below will do the wrong thing since the mode of such an
6050      expression is VOIDmode.  */
6051   if (code == CALL || code == ASM_OPERANDS)
6052     return x;
6053
6054   /* We want to perform the operation is its present mode unless we know
6055      that the operation is valid in MODE, in which case we do the operation
6056      in MODE.  */
6057   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6058               && code_to_optab[(int) code] != 0
6059               && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6060                   != CODE_FOR_nothing))
6061              ? mode : GET_MODE (x));
6062
6063   /* It is not valid to do a right-shift in a narrower mode
6064      than the one it came in with.  */
6065   if ((code == LSHIFTRT || code == ASHIFTRT)
6066       && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6067     op_mode = GET_MODE (x);
6068
6069   /* Truncate MASK to fit OP_MODE.  */
6070   if (op_mode)
6071     mask &= GET_MODE_MASK (op_mode);
6072
6073   /* When we have an arithmetic operation, or a shift whose count we
6074      do not know, we need to assume that all bit the up to the highest-order
6075      bit in MASK will be needed.  This is how we form such a mask.  */
6076   if (op_mode)
6077     fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6078                    ? GET_MODE_MASK (op_mode)
6079                    : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
6080   else
6081     fuller_mask = ~ (HOST_WIDE_INT) 0;
6082
6083   /* Determine what bits of X are guaranteed to be (non)zero.  */
6084   nonzero = nonzero_bits (x, mode);
6085
6086   /* If none of the bits in X are needed, return a zero.  */
6087   if (! just_select && (nonzero & mask) == 0)
6088     return const0_rtx;
6089
6090   /* If X is a CONST_INT, return a new one.  Do this here since the
6091      test below will fail.  */
6092   if (GET_CODE (x) == CONST_INT)
6093     {
6094       HOST_WIDE_INT cval = INTVAL (x) & mask;
6095       int width = GET_MODE_BITSIZE (mode);
6096
6097       /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6098          number, sign extend it.  */
6099       if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6100           && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6101         cval |= (HOST_WIDE_INT) -1 << width;
6102
6103       return GEN_INT (cval);
6104     }
6105
6106   /* If X is narrower than MODE and we want all the bits in X's mode, just
6107      get X in the proper mode.  */
6108   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6109       && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
6110     return gen_lowpart_for_combine (mode, x);
6111
6112   /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6113      MASK are already known to be zero in X, we need not do anything.  */
6114   if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6115     return x;
6116
6117   switch (code)
6118     {
6119     case CLOBBER:
6120       /* If X is a (clobber (const_int)), return it since we know we are
6121          generating something that won't match.  */
6122       return x;
6123
6124     case USE:
6125       /* X is a (use (mem ..)) that was made from a bit-field extraction that
6126          spanned the boundary of the MEM.  If we are now masking so it is
6127          within that boundary, we don't need the USE any more.  */
6128       if (! BITS_BIG_ENDIAN
6129           && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6130         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6131       break;
6132
6133     case SIGN_EXTEND:
6134     case ZERO_EXTEND:
6135     case ZERO_EXTRACT:
6136     case SIGN_EXTRACT:
6137       x = expand_compound_operation (x);
6138       if (GET_CODE (x) != code)
6139         return force_to_mode (x, mode, mask, reg, next_select);
6140       break;
6141
6142     case REG:
6143       if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6144                        || rtx_equal_p (reg, get_last_value (x))))
6145         x = reg;
6146       break;
6147
6148     case SUBREG:
6149       if (subreg_lowpart_p (x)
6150           /* We can ignore the effect of this SUBREG if it narrows the mode or
6151              if the constant masks to zero all the bits the mode doesn't
6152              have.  */
6153           && ((GET_MODE_SIZE (GET_MODE (x))
6154                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6155               || (0 == (mask
6156                         & GET_MODE_MASK (GET_MODE (x))
6157                         & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6158         return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6159       break;
6160
6161     case AND:
6162       /* If this is an AND with a constant, convert it into an AND
6163          whose constant is the AND of that constant with MASK.  If it
6164          remains an AND of MASK, delete it since it is redundant.  */
6165
6166       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6167         {
6168           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6169                                       mask & INTVAL (XEXP (x, 1)));
6170
6171           /* If X is still an AND, see if it is an AND with a mask that
6172              is just some low-order bits.  If so, and it is MASK, we don't
6173              need it.  */
6174
6175           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6176               && INTVAL (XEXP (x, 1)) == mask)
6177             x = XEXP (x, 0);
6178
6179           /* If it remains an AND, try making another AND with the bits
6180              in the mode mask that aren't in MASK turned on.  If the
6181              constant in the AND is wide enough, this might make a
6182              cheaper constant.  */
6183
6184           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6185               && GET_MODE_MASK (GET_MODE (x)) != mask
6186               && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6187             {
6188               HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6189                                     | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6190               int width = GET_MODE_BITSIZE (GET_MODE (x));
6191               rtx y;
6192
6193               /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6194                  number, sign extend it.  */
6195               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6196                   && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6197                 cval |= (HOST_WIDE_INT) -1 << width;
6198
6199               y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6200               if (rtx_cost (y, SET) < rtx_cost (x, SET))
6201                 x = y;
6202             }
6203
6204           break;
6205         }
6206
6207       goto binop;
6208
6209     case PLUS:
6210       /* In (and (plus FOO C1) M), if M is a mask that just turns off
6211          low-order bits (as in an alignment operation) and FOO is already
6212          aligned to that boundary, mask C1 to that boundary as well.
6213          This may eliminate that PLUS and, later, the AND.  */
6214
6215       {
6216         int width = GET_MODE_BITSIZE (mode);
6217         unsigned HOST_WIDE_INT smask = mask;
6218
6219         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6220            number, sign extend it.  */
6221
6222         if (width < HOST_BITS_PER_WIDE_INT
6223             && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6224           smask |= (HOST_WIDE_INT) -1 << width;
6225
6226         if (GET_CODE (XEXP (x, 1)) == CONST_INT
6227             && exact_log2 (- smask) >= 0
6228             && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
6229             && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
6230           return force_to_mode (plus_constant (XEXP (x, 0),
6231                                                INTVAL (XEXP (x, 1)) & mask),
6232                                 mode, mask, reg, next_select);
6233       }
6234
6235       /* ... fall through ...  */
6236
6237     case MINUS:
6238     case MULT:
6239       /* For PLUS, MINUS and MULT, we need any bits less significant than the
6240          most significant bit in MASK since carries from those bits will
6241          affect the bits we are interested in.  */
6242       mask = fuller_mask;
6243       goto binop;
6244
6245     case IOR:
6246     case XOR:
6247       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6248          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6249          operation which may be a bitfield extraction.  Ensure that the
6250          constant we form is not wider than the mode of X.  */
6251
6252       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6253           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6254           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6255           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6256           && GET_CODE (XEXP (x, 1)) == CONST_INT
6257           && ((INTVAL (XEXP (XEXP (x, 0), 1))
6258                + floor_log2 (INTVAL (XEXP (x, 1))))
6259               < GET_MODE_BITSIZE (GET_MODE (x)))
6260           && (INTVAL (XEXP (x, 1))
6261               & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6262         {
6263           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6264                               << INTVAL (XEXP (XEXP (x, 0), 1)));
6265           temp = gen_binary (GET_CODE (x), GET_MODE (x),
6266                              XEXP (XEXP (x, 0), 0), temp);
6267           x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6268                           XEXP (XEXP (x, 0), 1));
6269           return force_to_mode (x, mode, mask, reg, next_select);
6270         }
6271
6272     binop:
6273       /* For most binary operations, just propagate into the operation and
6274          change the mode if we have an operation of that mode.   */
6275
6276       op0 = gen_lowpart_for_combine (op_mode,
6277                                      force_to_mode (XEXP (x, 0), mode, mask,
6278                                                     reg, next_select));
6279       op1 = gen_lowpart_for_combine (op_mode,
6280                                      force_to_mode (XEXP (x, 1), mode, mask,
6281                                                     reg, next_select));
6282
6283       /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6284          MASK since OP1 might have been sign-extended but we never want
6285          to turn on extra bits, since combine might have previously relied
6286          on them being off.  */
6287       if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6288           && (INTVAL (op1) & mask) != 0)
6289         op1 = GEN_INT (INTVAL (op1) & mask);
6290
6291       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6292         x = gen_binary (code, op_mode, op0, op1);
6293       break;
6294
6295     case ASHIFT:
6296       /* For left shifts, do the same, but just for the first operand.
6297          However, we cannot do anything with shifts where we cannot
6298          guarantee that the counts are smaller than the size of the mode
6299          because such a count will have a different meaning in a
6300          wider mode.  */
6301
6302       if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6303              && INTVAL (XEXP (x, 1)) >= 0
6304              && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6305           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6306                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6307                     < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6308         break;
6309
6310       /* If the shift count is a constant and we can do arithmetic in
6311          the mode of the shift, refine which bits we need.  Otherwise, use the
6312          conservative form of the mask.  */
6313       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6314           && INTVAL (XEXP (x, 1)) >= 0
6315           && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6316           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6317         mask >>= INTVAL (XEXP (x, 1));
6318       else
6319         mask = fuller_mask;
6320
6321       op0 = gen_lowpart_for_combine (op_mode,
6322                                      force_to_mode (XEXP (x, 0), op_mode,
6323                                                     mask, reg, next_select));
6324
6325       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6326         x =  gen_binary (code, op_mode, op0, XEXP (x, 1));
6327       break;
6328
6329     case LSHIFTRT:
6330       /* Here we can only do something if the shift count is a constant,
6331          this shift constant is valid for the host, and we can do arithmetic
6332          in OP_MODE.  */
6333
6334       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6335           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6336           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6337         {
6338           rtx inner = XEXP (x, 0);
6339
6340           /* Select the mask of the bits we need for the shift operand.  */
6341           mask <<= INTVAL (XEXP (x, 1));
6342
6343           /* We can only change the mode of the shift if we can do arithmetic
6344              in the mode of the shift and MASK is no wider than the width of
6345              OP_MODE.  */
6346           if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6347               || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
6348             op_mode = GET_MODE (x);
6349
6350           inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6351
6352           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6353             x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6354         }
6355
6356       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6357          shift and AND produces only copies of the sign bit (C2 is one less
6358          than a power of two), we can do this with just a shift.  */
6359
6360       if (GET_CODE (x) == LSHIFTRT
6361           && GET_CODE (XEXP (x, 1)) == CONST_INT
6362           && ((INTVAL (XEXP (x, 1))
6363                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6364               >= GET_MODE_BITSIZE (GET_MODE (x)))
6365           && exact_log2 (mask + 1) >= 0
6366           && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6367               >= exact_log2 (mask + 1)))
6368         x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6369                         GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6370                                  - exact_log2 (mask + 1)));
6371       break;
6372
6373     case ASHIFTRT:
6374       /* If we are just looking for the sign bit, we don't need this shift at
6375          all, even if it has a variable count.  */
6376       if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6377           && (mask == ((HOST_WIDE_INT) 1
6378                        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6379         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6380
6381       /* If this is a shift by a constant, get a mask that contains those bits
6382          that are not copies of the sign bit.  We then have two cases:  If
6383          MASK only includes those bits, this can be a logical shift, which may
6384          allow simplifications.  If MASK is a single-bit field not within
6385          those bits, we are requesting a copy of the sign bit and hence can
6386          shift the sign bit to the appropriate location.  */
6387
6388       if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6389           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6390         {
6391           int i = -1;
6392
6393           /* If the considered data is wider then HOST_WIDE_INT, we can't
6394              represent a mask for all its bits in a single scalar.
6395              But we only care about the lower bits, so calculate these.  */
6396
6397           if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6398             {
6399               nonzero = ~ (HOST_WIDE_INT) 0;
6400
6401               /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6402                  is the number of bits a full-width mask would have set.
6403                  We need only shift if these are fewer than nonzero can
6404                  hold.  If not, we must keep all bits set in nonzero.  */
6405
6406               if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6407                   < HOST_BITS_PER_WIDE_INT)
6408                 nonzero >>= INTVAL (XEXP (x, 1))
6409                             + HOST_BITS_PER_WIDE_INT
6410                             - GET_MODE_BITSIZE (GET_MODE (x)) ;
6411             }
6412           else
6413             {
6414               nonzero = GET_MODE_MASK (GET_MODE (x));
6415               nonzero >>= INTVAL (XEXP (x, 1));
6416             }
6417
6418           if ((mask & ~ nonzero) == 0
6419               || (i = exact_log2 (mask)) >= 0)
6420             {
6421               x = simplify_shift_const
6422                 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6423                  i < 0 ? INTVAL (XEXP (x, 1))
6424                  : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6425
6426               if (GET_CODE (x) != ASHIFTRT)
6427                 return force_to_mode (x, mode, mask, reg, next_select);
6428             }
6429         }
6430
6431       /* If MASK is 1, convert this to a LSHIFTRT.  This can be done
6432          even if the shift count isn't a constant.  */
6433       if (mask == 1)
6434         x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6435
6436       /* If this is a sign-extension operation that just affects bits
6437          we don't care about, remove it.  Be sure the call above returned
6438          something that is still a shift.  */
6439
6440       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6441           && GET_CODE (XEXP (x, 1)) == CONST_INT
6442           && INTVAL (XEXP (x, 1)) >= 0
6443           && (INTVAL (XEXP (x, 1))
6444               <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
6445           && GET_CODE (XEXP (x, 0)) == ASHIFT
6446           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6447           && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
6448         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6449                               reg, next_select);
6450
6451       break;
6452
6453     case ROTATE:
6454     case ROTATERT:
6455       /* If the shift count is constant and we can do computations
6456          in the mode of X, compute where the bits we care about are.
6457          Otherwise, we can't do anything.  Don't change the mode of
6458          the shift or propagate MODE into the shift, though.  */
6459       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6460           && INTVAL (XEXP (x, 1)) >= 0)
6461         {
6462           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6463                                             GET_MODE (x), GEN_INT (mask),
6464                                             XEXP (x, 1));
6465           if (temp && GET_CODE(temp) == CONST_INT)
6466             SUBST (XEXP (x, 0),
6467                    force_to_mode (XEXP (x, 0), GET_MODE (x),
6468                                   INTVAL (temp), reg, next_select));
6469         }
6470       break;
6471
6472     case NEG:
6473       /* If we just want the low-order bit, the NEG isn't needed since it
6474          won't change the low-order bit.    */
6475       if (mask == 1)
6476         return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6477
6478       /* We need any bits less significant than the most significant bit in
6479          MASK since carries from those bits will affect the bits we are
6480          interested in.  */
6481       mask = fuller_mask;
6482       goto unop;
6483
6484     case NOT:
6485       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6486          same as the XOR case above.  Ensure that the constant we form is not
6487          wider than the mode of X.  */
6488
6489       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6490           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6491           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6492           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6493               < GET_MODE_BITSIZE (GET_MODE (x)))
6494           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6495         {
6496           temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6497           temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6498           x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6499
6500           return force_to_mode (x, mode, mask, reg, next_select);
6501         }
6502
6503       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6504          use the full mask inside the NOT.  */
6505       mask = fuller_mask;
6506
6507     unop:
6508       op0 = gen_lowpart_for_combine (op_mode,
6509                                      force_to_mode (XEXP (x, 0), mode, mask,
6510                                                     reg, next_select));
6511       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6512         x = gen_unary (code, op_mode, op_mode, op0);
6513       break;
6514
6515     case NE:
6516       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6517          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
6518          which is equal to STORE_FLAG_VALUE.  */
6519       if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6520           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
6521           && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
6522         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6523
6524       break;
6525
6526     case IF_THEN_ELSE:
6527       /* We have no way of knowing if the IF_THEN_ELSE can itself be
6528          written in a narrower mode.  We play it safe and do not do so.  */
6529
6530       SUBST (XEXP (x, 1),
6531              gen_lowpart_for_combine (GET_MODE (x),
6532                                       force_to_mode (XEXP (x, 1), mode,
6533                                                      mask, reg, next_select)));
6534       SUBST (XEXP (x, 2),
6535              gen_lowpart_for_combine (GET_MODE (x),
6536                                       force_to_mode (XEXP (x, 2), mode,
6537                                                      mask, reg,next_select)));
6538       break;
6539
6540     default:
6541       break;
6542     }
6543
6544   /* Ensure we return a value of the proper mode.  */
6545   return gen_lowpart_for_combine (mode, x);
6546 }
6547 \f
6548 /* Return nonzero if X is an expression that has one of two values depending on
6549    whether some other value is zero or nonzero.  In that case, we return the
6550    value that is being tested, *PTRUE is set to the value if the rtx being
6551    returned has a nonzero value, and *PFALSE is set to the other alternative.
6552
6553    If we return zero, we set *PTRUE and *PFALSE to X.  */
6554
6555 static rtx
6556 if_then_else_cond (x, ptrue, pfalse)
6557      rtx x;
6558      rtx *ptrue, *pfalse;
6559 {
6560   enum machine_mode mode = GET_MODE (x);
6561   enum rtx_code code = GET_CODE (x);
6562   int size = GET_MODE_BITSIZE (mode);
6563   rtx cond0, cond1, true0, true1, false0, false1;
6564   unsigned HOST_WIDE_INT nz;
6565
6566   /* If this is a unary operation whose operand has one of two values, apply
6567      our opcode to compute those values.  */
6568   if (GET_RTX_CLASS (code) == '1'
6569       && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6570     {
6571       *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6572       *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
6573       return cond0;
6574     }
6575
6576   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6577      make can't possibly match and would suppress other optimizations.  */
6578   else if (code == COMPARE)
6579     ;
6580
6581   /* If this is a binary operation, see if either side has only one of two
6582      values.  If either one does or if both do and they are conditional on
6583      the same value, compute the new true and false values.  */
6584   else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6585            || GET_RTX_CLASS (code) == '<')
6586     {
6587       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6588       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6589
6590       if ((cond0 != 0 || cond1 != 0)
6591           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6592         {
6593           /* If if_then_else_cond returned zero, then true/false are the
6594              same rtl.  We must copy one of them to prevent invalid rtl
6595              sharing.  */
6596           if (cond0 == 0)
6597             true0 = copy_rtx (true0);
6598           else if (cond1 == 0)
6599             true1 = copy_rtx (true1);
6600
6601           *ptrue = gen_binary (code, mode, true0, true1);
6602           *pfalse = gen_binary (code, mode, false0, false1);
6603           return cond0 ? cond0 : cond1;
6604         }
6605
6606       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6607          operands is zero when the other is non-zero, and vice-versa,
6608          and STORE_FLAG_VALUE is 1 or -1.  */
6609
6610       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6611           && (code == PLUS || code == IOR || code == XOR || code == MINUS
6612            || code == UMAX)
6613           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6614         {
6615           rtx op0 = XEXP (XEXP (x, 0), 1);
6616           rtx op1 = XEXP (XEXP (x, 1), 1);
6617
6618           cond0 = XEXP (XEXP (x, 0), 0);
6619           cond1 = XEXP (XEXP (x, 1), 0);
6620
6621           if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6622               && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6623               && reversible_comparison_p (cond1)
6624               && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6625                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6626                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6627                   || ((swap_condition (GET_CODE (cond0))
6628                        == reverse_condition (GET_CODE (cond1)))
6629                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6630                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6631               && ! side_effects_p (x))
6632             {
6633               *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6634               *pfalse = gen_binary (MULT, mode,
6635                                     (code == MINUS
6636                                      ? gen_unary (NEG, mode, mode, op1) : op1),
6637                                     const_true_rtx);
6638               return cond0;
6639             }
6640         }
6641
6642       /* Similarly for MULT, AND and UMIN, execpt that for these the result
6643          is always zero.  */
6644       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6645           && (code == MULT || code == AND || code == UMIN)
6646           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6647         {
6648           cond0 = XEXP (XEXP (x, 0), 0);
6649           cond1 = XEXP (XEXP (x, 1), 0);
6650
6651           if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6652               && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6653               && reversible_comparison_p (cond1)
6654               && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6655                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6656                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6657                   || ((swap_condition (GET_CODE (cond0))
6658                        == reverse_condition (GET_CODE (cond1)))
6659                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6660                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6661               && ! side_effects_p (x))
6662             {
6663               *ptrue = *pfalse = const0_rtx;
6664               return cond0;
6665             }
6666         }
6667     }
6668
6669   else if (code == IF_THEN_ELSE)
6670     {
6671       /* If we have IF_THEN_ELSE already, extract the condition and
6672          canonicalize it if it is NE or EQ.  */
6673       cond0 = XEXP (x, 0);
6674       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6675       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6676         return XEXP (cond0, 0);
6677       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6678         {
6679           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6680           return XEXP (cond0, 0);
6681         }
6682       else
6683         return cond0;
6684     }
6685
6686   /* If X is a normal SUBREG with both inner and outer modes integral,
6687      we can narrow both the true and false values of the inner expression,
6688      if there is a condition.  */
6689   else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6690            && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6691            && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6692            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6693                                                &true0, &false0)))
6694     {
6695       *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6696       *pfalse
6697         = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6698
6699       return cond0;
6700     }
6701
6702   /* If X is a constant, this isn't special and will cause confusions
6703      if we treat it as such.  Likewise if it is equivalent to a constant.  */
6704   else if (CONSTANT_P (x)
6705            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6706     ;
6707
6708   /* If X is known to be either 0 or -1, those are the true and
6709      false values when testing X.  */
6710   else if (num_sign_bit_copies (x, mode) == size)
6711     {
6712       *ptrue = constm1_rtx, *pfalse = const0_rtx;
6713       return x;
6714     }
6715
6716   /* Likewise for 0 or a single bit.  */
6717   else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6718     {
6719       *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6720       return x;
6721     }
6722
6723   /* Otherwise fail; show no condition with true and false values the same.  */
6724   *ptrue = *pfalse = x;
6725   return 0;
6726 }
6727 \f
6728 /* Return the value of expression X given the fact that condition COND
6729    is known to be true when applied to REG as its first operand and VAL
6730    as its second.  X is known to not be shared and so can be modified in
6731    place.
6732
6733    We only handle the simplest cases, and specifically those cases that
6734    arise with IF_THEN_ELSE expressions.  */
6735
6736 static rtx
6737 known_cond (x, cond, reg, val)
6738      rtx x;
6739      enum rtx_code cond;
6740      rtx reg, val;
6741 {
6742   enum rtx_code code = GET_CODE (x);
6743   rtx temp;
6744   char *fmt;
6745   int i, j;
6746
6747   if (side_effects_p (x))
6748     return x;
6749
6750   if (cond == EQ && rtx_equal_p (x, reg))
6751     return val;
6752
6753   /* If X is (abs REG) and we know something about REG's relationship
6754      with zero, we may be able to simplify this.  */
6755
6756   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6757     switch (cond)
6758       {
6759       case GE:  case GT:  case EQ:
6760         return XEXP (x, 0);
6761       case LT:  case LE:
6762         return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6763                           XEXP (x, 0));
6764       default:
6765         break;
6766       }
6767
6768   /* The only other cases we handle are MIN, MAX, and comparisons if the
6769      operands are the same as REG and VAL.  */
6770
6771   else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6772     {
6773       if (rtx_equal_p (XEXP (x, 0), val))
6774         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6775
6776       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6777         {
6778           if (GET_RTX_CLASS (code) == '<')
6779             return (comparison_dominates_p (cond, code) ? const_true_rtx
6780                     : (comparison_dominates_p (cond,
6781                                                reverse_condition (code))
6782                        ? const0_rtx : x));
6783
6784           else if (code == SMAX || code == SMIN
6785                    || code == UMIN || code == UMAX)
6786             {
6787               int unsignedp = (code == UMIN || code == UMAX);
6788
6789               if (code == SMAX || code == UMAX)
6790                 cond = reverse_condition (cond);
6791
6792               switch (cond)
6793                 {
6794                 case GE:   case GT:
6795                   return unsignedp ? x : XEXP (x, 1);
6796                 case LE:   case LT:
6797                   return unsignedp ? x : XEXP (x, 0);
6798                 case GEU:  case GTU:
6799                   return unsignedp ? XEXP (x, 1) : x;
6800                 case LEU:  case LTU:
6801                   return unsignedp ? XEXP (x, 0) : x;
6802                 default:
6803                   break;
6804                 }
6805             }
6806         }
6807     }
6808
6809   fmt = GET_RTX_FORMAT (code);
6810   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6811     {
6812       if (fmt[i] == 'e')
6813         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
6814       else if (fmt[i] == 'E')
6815         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6816           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
6817                                                 cond, reg, val));
6818     }
6819
6820   return x;
6821 }
6822 \f
6823 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
6824    assignment as a field assignment.  */
6825
6826 static int
6827 rtx_equal_for_field_assignment_p (x, y)
6828      rtx x;
6829      rtx y;
6830 {
6831   rtx last_x, last_y;
6832
6833   if (x == y || rtx_equal_p (x, y))
6834     return 1;
6835
6836   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
6837     return 0;
6838
6839   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
6840      Note that all SUBREGs of MEM are paradoxical; otherwise they
6841      would have been rewritten.  */
6842   if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
6843       && GET_CODE (SUBREG_REG (y)) == MEM
6844       && rtx_equal_p (SUBREG_REG (y),
6845                       gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
6846     return 1;
6847
6848   if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
6849       && GET_CODE (SUBREG_REG (x)) == MEM
6850       && rtx_equal_p (SUBREG_REG (x),
6851                       gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
6852     return 1;
6853
6854   last_x = get_last_value (x);
6855   last_y = get_last_value (y);
6856
6857   return ((last_x != 0
6858            && GET_CODE (last_x) != CLOBBER
6859            && rtx_equal_for_field_assignment_p (last_x, y))
6860           || (last_y != 0
6861               && GET_CODE (last_y) != CLOBBER
6862               && rtx_equal_for_field_assignment_p (x, last_y))
6863           || (last_x != 0 && last_y != 0
6864               && GET_CODE (last_x) != CLOBBER
6865               && GET_CODE (last_y) != CLOBBER
6866               && rtx_equal_for_field_assignment_p (last_x, last_y)));
6867 }
6868 \f
6869 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
6870    Return that assignment if so.
6871
6872    We only handle the most common cases.  */
6873
6874 static rtx
6875 make_field_assignment (x)
6876      rtx x;
6877 {
6878   rtx dest = SET_DEST (x);
6879   rtx src = SET_SRC (x);
6880   rtx assign;
6881   rtx rhs, lhs;
6882   HOST_WIDE_INT c1;
6883   int pos, len;
6884   rtx other;
6885   enum machine_mode mode;
6886
6887   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
6888      a clear of a one-bit field.  We will have changed it to
6889      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
6890      for a SUBREG.  */
6891
6892   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
6893       && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
6894       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
6895       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6896     {
6897       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6898                                 1, 1, 1, 0);
6899       if (assign != 0)
6900         return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6901       return x;
6902     }
6903
6904   else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
6905            && subreg_lowpart_p (XEXP (src, 0))
6906            && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
6907                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
6908            && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
6909            && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
6910            && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6911     {
6912       assign = make_extraction (VOIDmode, dest, 0,
6913                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
6914                                 1, 1, 1, 0);
6915       if (assign != 0)
6916         return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6917       return x;
6918     }
6919
6920   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
6921      one-bit field.  */
6922   else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
6923            && XEXP (XEXP (src, 0), 0) == const1_rtx
6924            && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6925     {
6926       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6927                                 1, 1, 1, 0);
6928       if (assign != 0)
6929         return gen_rtx (SET, VOIDmode, assign, const1_rtx);
6930       return x;
6931     }
6932
6933   /* The other case we handle is assignments into a constant-position
6934      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
6935      a mask that has all one bits except for a group of zero bits and
6936      OTHER is known to have zeros where C1 has ones, this is such an
6937      assignment.  Compute the position and length from C1.  Shift OTHER
6938      to the appropriate position, force it to the required mode, and
6939      make the extraction.  Check for the AND in both operands.  */
6940
6941   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
6942     return x;
6943
6944   rhs = expand_compound_operation (XEXP (src, 0));
6945   lhs = expand_compound_operation (XEXP (src, 1));
6946
6947   if (GET_CODE (rhs) == AND
6948       && GET_CODE (XEXP (rhs, 1)) == CONST_INT
6949       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
6950     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
6951   else if (GET_CODE (lhs) == AND
6952            && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6953            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
6954     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
6955   else
6956     return x;
6957
6958   pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
6959   if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
6960       || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
6961           && (c1 & nonzero_bits (other, GET_MODE (other))) != 0))
6962     return x;
6963
6964   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
6965   if (assign == 0)
6966     return x;
6967
6968   /* The mode to use for the source is the mode of the assignment, or of
6969      what is inside a possible STRICT_LOW_PART.  */
6970   mode = (GET_CODE (assign) == STRICT_LOW_PART
6971           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
6972
6973   /* Shift OTHER right POS places and make it the source, restricting it
6974      to the proper length and mode.  */
6975
6976   src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
6977                                              GET_MODE (src), other, pos),
6978                        mode,
6979                        GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
6980                        ? GET_MODE_MASK (mode)
6981                        : ((HOST_WIDE_INT) 1 << len) - 1,
6982                        dest, 0);
6983
6984   return gen_rtx_combine (SET, VOIDmode, assign, src);
6985 }
6986 \f
6987 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
6988    if so.  */
6989
6990 static rtx
6991 apply_distributive_law (x)
6992      rtx x;
6993 {
6994   enum rtx_code code = GET_CODE (x);
6995   rtx lhs, rhs, other;
6996   rtx tem;
6997   enum rtx_code inner_code;
6998
6999   /* Distributivity is not true for floating point.
7000      It can change the value.  So don't do it.
7001      -- rms and moshier@world.std.com.  */
7002   if (FLOAT_MODE_P (GET_MODE (x)))
7003     return x;
7004
7005   /* The outer operation can only be one of the following:  */
7006   if (code != IOR && code != AND && code != XOR
7007       && code != PLUS && code != MINUS)
7008     return x;
7009
7010   lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7011
7012   /* If either operand is a primitive we can't do anything, so get out
7013      fast.  */
7014   if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7015       || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7016     return x;
7017
7018   lhs = expand_compound_operation (lhs);
7019   rhs = expand_compound_operation (rhs);
7020   inner_code = GET_CODE (lhs);
7021   if (inner_code != GET_CODE (rhs))
7022     return x;
7023
7024   /* See if the inner and outer operations distribute.  */
7025   switch (inner_code)
7026     {
7027     case LSHIFTRT:
7028     case ASHIFTRT:
7029     case AND:
7030     case IOR:
7031       /* These all distribute except over PLUS.  */
7032       if (code == PLUS || code == MINUS)
7033         return x;
7034       break;
7035
7036     case MULT:
7037       if (code != PLUS && code != MINUS)
7038         return x;
7039       break;
7040
7041     case ASHIFT:
7042       /* This is also a multiply, so it distributes over everything.  */
7043       break;
7044
7045     case SUBREG:
7046       /* Non-paradoxical SUBREGs distributes over all operations, provided
7047          the inner modes and word numbers are the same, this is an extraction
7048          of a low-order part, we don't convert an fp operation to int or
7049          vice versa, and we would not be converting a single-word
7050          operation into a multi-word operation.  The latter test is not
7051          required, but it prevents generating unneeded multi-word operations.
7052          Some of the previous tests are redundant given the latter test, but
7053          are retained because they are required for correctness.
7054
7055          We produce the result slightly differently in this case.  */
7056
7057       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7058           || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7059           || ! subreg_lowpart_p (lhs)
7060           || (GET_MODE_CLASS (GET_MODE (lhs))
7061               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7062           || (GET_MODE_SIZE (GET_MODE (lhs))
7063               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7064           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7065         return x;
7066
7067       tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7068                         SUBREG_REG (lhs), SUBREG_REG (rhs));
7069       return gen_lowpart_for_combine (GET_MODE (x), tem);
7070
7071     default:
7072       return x;
7073     }
7074
7075   /* Set LHS and RHS to the inner operands (A and B in the example
7076      above) and set OTHER to the common operand (C in the example).
7077      These is only one way to do this unless the inner operation is
7078      commutative.  */
7079   if (GET_RTX_CLASS (inner_code) == 'c'
7080       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7081     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7082   else if (GET_RTX_CLASS (inner_code) == 'c'
7083            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7084     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7085   else if (GET_RTX_CLASS (inner_code) == 'c'
7086            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7087     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7088   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7089     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7090   else
7091     return x;
7092
7093   /* Form the new inner operation, seeing if it simplifies first.  */
7094   tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7095
7096   /* There is one exception to the general way of distributing:
7097      (a ^ b) | (a ^ c) -> (~a) & (b ^ c)  */
7098   if (code == XOR && inner_code == IOR)
7099     {
7100       inner_code = AND;
7101       other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7102     }
7103
7104   /* We may be able to continuing distributing the result, so call
7105      ourselves recursively on the inner operation before forming the
7106      outer operation, which we return.  */
7107   return gen_binary (inner_code, GET_MODE (x),
7108                      apply_distributive_law (tem), other);
7109 }
7110 \f
7111 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7112    in MODE.
7113
7114    Return an equivalent form, if different from X.  Otherwise, return X.  If
7115    X is zero, we are to always construct the equivalent form.  */
7116
7117 static rtx
7118 simplify_and_const_int (x, mode, varop, constop)
7119      rtx x;
7120      enum machine_mode mode;
7121      rtx varop;
7122      unsigned HOST_WIDE_INT constop;
7123 {
7124   unsigned HOST_WIDE_INT nonzero;
7125   int width = GET_MODE_BITSIZE (mode);
7126   int i;
7127
7128   /* Simplify VAROP knowing that we will be only looking at some of the
7129      bits in it.  */
7130   varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7131
7132   /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7133      CONST_INT, we are done.  */
7134   if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7135     return varop;
7136
7137   /* See what bits may be nonzero in VAROP.  Unlike the general case of
7138      a call to nonzero_bits, here we don't care about bits outside
7139      MODE.  */
7140
7141   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7142
7143   /* If this would be an entire word for the target, but is not for
7144      the host, then sign-extend on the host so that the number will look
7145      the same way on the host that it would on the target.
7146
7147      For example, when building a 64 bit alpha hosted 32 bit sparc
7148      targeted compiler, then we want the 32 bit unsigned value -1 to be
7149      represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7150      The later confuses the sparc backend.  */
7151
7152   if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7153       && (nonzero & ((HOST_WIDE_INT) 1 << (width - 1))))
7154     nonzero |= ((HOST_WIDE_INT) (-1) << width);
7155
7156   /* Turn off all bits in the constant that are known to already be zero.
7157      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7158      which is tested below.  */
7159
7160   constop &= nonzero;
7161
7162   /* If we don't have any bits left, return zero.  */
7163   if (constop == 0)
7164     return const0_rtx;
7165
7166   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7167      a power of two, we can replace this with a ASHIFT.  */
7168   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7169       && (i = exact_log2 (constop)) >= 0)
7170     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7171
7172   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7173      or XOR, then try to apply the distributive law.  This may eliminate
7174      operations if either branch can be simplified because of the AND.
7175      It may also make some cases more complex, but those cases probably
7176      won't match a pattern either with or without this.  */
7177
7178   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7179     return
7180       gen_lowpart_for_combine
7181         (mode,
7182          apply_distributive_law
7183          (gen_binary (GET_CODE (varop), GET_MODE (varop),
7184                       simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7185                                               XEXP (varop, 0), constop),
7186                       simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7187                                               XEXP (varop, 1), constop))));
7188
7189   /* Get VAROP in MODE.  Try to get a SUBREG if not.  Don't make a new SUBREG
7190      if we already had one (just check for the simplest cases).  */
7191   if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7192       && GET_MODE (XEXP (x, 0)) == mode
7193       && SUBREG_REG (XEXP (x, 0)) == varop)
7194     varop = XEXP (x, 0);
7195   else
7196     varop = gen_lowpart_for_combine (mode, varop);
7197
7198   /* If we can't make the SUBREG, try to return what we were given.  */
7199   if (GET_CODE (varop) == CLOBBER)
7200     return x ? x : varop;
7201
7202   /* If we are only masking insignificant bits, return VAROP.  */
7203   if (constop == nonzero)
7204     x = varop;
7205
7206   /* Otherwise, return an AND.  See how much, if any, of X we can use.  */
7207   else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7208     x = gen_binary (AND, mode, varop, GEN_INT (constop));
7209
7210   else
7211     {
7212       if (GET_CODE (XEXP (x, 1)) != CONST_INT
7213           || INTVAL (XEXP (x, 1)) != constop)
7214         SUBST (XEXP (x, 1), GEN_INT (constop));
7215
7216       SUBST (XEXP (x, 0), varop);
7217     }
7218
7219   return x;
7220 }
7221 \f
7222 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7223    We don't let nonzero_bits recur into num_sign_bit_copies, because that
7224    is less useful.  We can't allow both, because that results in exponential
7225    run time recursion.  There is a nullstone testcase that triggered
7226    this.  This macro avoids accidental uses of num_sign_bit_copies.  */
7227 #define num_sign_bit_copies()
7228
7229 /* Given an expression, X, compute which bits in X can be non-zero.
7230    We don't care about bits outside of those defined in MODE.
7231
7232    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7233    a shift, AND, or zero_extract, we can do better.  */
7234
7235 static unsigned HOST_WIDE_INT
7236 nonzero_bits (x, mode)
7237      rtx x;
7238      enum machine_mode mode;
7239 {
7240   unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7241   unsigned HOST_WIDE_INT inner_nz;
7242   enum rtx_code code;
7243   int mode_width = GET_MODE_BITSIZE (mode);
7244   rtx tem;
7245
7246   /* For floating-point values, assume all bits are needed.  */
7247   if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7248     return nonzero;
7249
7250   /* If X is wider than MODE, use its mode instead.  */
7251   if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7252     {
7253       mode = GET_MODE (x);
7254       nonzero = GET_MODE_MASK (mode);
7255       mode_width = GET_MODE_BITSIZE (mode);
7256     }
7257
7258   if (mode_width > HOST_BITS_PER_WIDE_INT)
7259     /* Our only callers in this case look for single bit values.  So
7260        just return the mode mask.  Those tests will then be false.  */
7261     return nonzero;
7262
7263 #ifndef WORD_REGISTER_OPERATIONS
7264   /* If MODE is wider than X, but both are a single word for both the host
7265      and target machines, we can compute this from which bits of the
7266      object might be nonzero in its own mode, taking into account the fact
7267      that on many CISC machines, accessing an object in a wider mode
7268      causes the high-order bits to become undefined.  So they are
7269      not known to be zero.  */
7270
7271   if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7272       && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7273       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7274       && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7275     {
7276       nonzero &= nonzero_bits (x, GET_MODE (x));
7277       nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7278       return nonzero;
7279     }
7280 #endif
7281
7282   code = GET_CODE (x);
7283   switch (code)
7284     {
7285     case REG:
7286 #ifdef POINTERS_EXTEND_UNSIGNED
7287       /* If pointers extend unsigned and this is a pointer in Pmode, say that
7288          all the bits above ptr_mode are known to be zero.  */
7289       if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7290           && REGNO_POINTER_FLAG (REGNO (x)))
7291         nonzero &= GET_MODE_MASK (ptr_mode);
7292 #endif
7293
7294 #ifdef STACK_BOUNDARY
7295       /* If this is the stack pointer, we may know something about its
7296          alignment.  If PUSH_ROUNDING is defined, it is possible for the
7297          stack to be momentarily aligned only to that amount, so we pick
7298          the least alignment.  */
7299
7300       /* We can't check for arg_pointer_rtx here, because it is not
7301          guaranteed to have as much alignment as the stack pointer.
7302          In particular, in the Irix6 n64 ABI, the stack has 128 bit
7303          alignment but the argument pointer has only 64 bit alignment.  */
7304
7305       if (x == stack_pointer_rtx || x == frame_pointer_rtx
7306           || x == hard_frame_pointer_rtx
7307           || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7308               && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7309         {
7310           int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7311
7312 #ifdef PUSH_ROUNDING
7313           if (REGNO (x) == STACK_POINTER_REGNUM)
7314             sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7315 #endif
7316
7317           /* We must return here, otherwise we may get a worse result from
7318              one of the choices below.  There is nothing useful below as
7319              far as the stack pointer is concerned.  */
7320           return nonzero &= ~ (sp_alignment - 1);
7321         }
7322 #endif
7323
7324       /* If X is a register whose nonzero bits value is current, use it.
7325          Otherwise, if X is a register whose value we can find, use that
7326          value.  Otherwise, use the previously-computed global nonzero bits
7327          for this register.  */
7328
7329       if (reg_last_set_value[REGNO (x)] != 0
7330           && reg_last_set_mode[REGNO (x)] == mode
7331           && (REG_N_SETS (REGNO (x)) == 1
7332               || reg_last_set_label[REGNO (x)] == label_tick)
7333           && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7334         return reg_last_set_nonzero_bits[REGNO (x)];
7335
7336       tem = get_last_value (x);
7337
7338       if (tem)
7339         {
7340 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7341           /* If X is narrower than MODE and TEM is a non-negative
7342              constant that would appear negative in the mode of X,
7343              sign-extend it for use in reg_nonzero_bits because some
7344              machines (maybe most) will actually do the sign-extension
7345              and this is the conservative approach.
7346
7347              ??? For 2.5, try to tighten up the MD files in this regard
7348              instead of this kludge.  */
7349
7350           if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7351               && GET_CODE (tem) == CONST_INT
7352               && INTVAL (tem) > 0
7353               && 0 != (INTVAL (tem)
7354                        & ((HOST_WIDE_INT) 1
7355                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7356             tem = GEN_INT (INTVAL (tem)
7357                            | ((HOST_WIDE_INT) (-1)
7358                               << GET_MODE_BITSIZE (GET_MODE (x))));
7359 #endif
7360           return nonzero_bits (tem, mode);
7361         }
7362       else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7363         return reg_nonzero_bits[REGNO (x)] & nonzero;
7364       else
7365         return nonzero;
7366
7367     case CONST_INT:
7368 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7369       /* If X is negative in MODE, sign-extend the value.  */
7370       if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7371           && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7372         return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7373 #endif
7374
7375       return INTVAL (x);
7376
7377     case MEM:
7378 #ifdef LOAD_EXTEND_OP
7379       /* In many, if not most, RISC machines, reading a byte from memory
7380          zeros the rest of the register.  Noticing that fact saves a lot
7381          of extra zero-extends.  */
7382       if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7383         nonzero &= GET_MODE_MASK (GET_MODE (x));
7384 #endif
7385       break;
7386
7387     case EQ:  case NE:
7388     case GT:  case GTU:
7389     case LT:  case LTU:
7390     case GE:  case GEU:
7391     case LE:  case LEU:
7392
7393       /* If this produces an integer result, we know which bits are set.
7394          Code here used to clear bits outside the mode of X, but that is
7395          now done above.  */
7396
7397       if (GET_MODE_CLASS (mode) == MODE_INT
7398           && mode_width <= HOST_BITS_PER_WIDE_INT)
7399         nonzero = STORE_FLAG_VALUE;
7400       break;
7401
7402     case NEG:
7403 #if 0
7404       /* Disabled to avoid exponential mutual recursion between nonzero_bits
7405          and num_sign_bit_copies.  */
7406       if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7407           == GET_MODE_BITSIZE (GET_MODE (x)))
7408         nonzero = 1;
7409 #endif
7410
7411       if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
7412         nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
7413       break;
7414
7415     case ABS:
7416 #if 0
7417       /* Disabled to avoid exponential mutual recursion between nonzero_bits
7418          and num_sign_bit_copies.  */
7419       if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7420           == GET_MODE_BITSIZE (GET_MODE (x)))
7421         nonzero = 1;
7422 #endif
7423       break;
7424
7425     case TRUNCATE:
7426       nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
7427       break;
7428
7429     case ZERO_EXTEND:
7430       nonzero &= nonzero_bits (XEXP (x, 0), mode);
7431       if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7432         nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7433       break;
7434
7435     case SIGN_EXTEND:
7436       /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7437          Otherwise, show all the bits in the outer mode but not the inner
7438          may be non-zero.  */
7439       inner_nz = nonzero_bits (XEXP (x, 0), mode);
7440       if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7441         {
7442           inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7443           if (inner_nz
7444               & (((HOST_WIDE_INT) 1
7445                   << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
7446             inner_nz |= (GET_MODE_MASK (mode)
7447                           & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7448         }
7449
7450       nonzero &= inner_nz;
7451       break;
7452
7453     case AND:
7454       nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7455                   & nonzero_bits (XEXP (x, 1), mode));
7456       break;
7457
7458     case XOR:   case IOR:
7459     case UMIN:  case UMAX:  case SMIN:  case SMAX:
7460       nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7461                   | nonzero_bits (XEXP (x, 1), mode));
7462       break;
7463
7464     case PLUS:  case MINUS:
7465     case MULT:
7466     case DIV:   case UDIV:
7467     case MOD:   case UMOD:
7468       /* We can apply the rules of arithmetic to compute the number of
7469          high- and low-order zero bits of these operations.  We start by
7470          computing the width (position of the highest-order non-zero bit)
7471          and the number of low-order zero bits for each value.  */
7472       {
7473         unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7474         unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7475         int width0 = floor_log2 (nz0) + 1;
7476         int width1 = floor_log2 (nz1) + 1;
7477         int low0 = floor_log2 (nz0 & -nz0);
7478         int low1 = floor_log2 (nz1 & -nz1);
7479         HOST_WIDE_INT op0_maybe_minusp
7480           = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7481         HOST_WIDE_INT op1_maybe_minusp
7482           = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7483         int result_width = mode_width;
7484         int result_low = 0;
7485
7486         switch (code)
7487           {
7488           case PLUS:
7489             result_width = MAX (width0, width1) + 1;
7490             result_low = MIN (low0, low1);
7491             break;
7492           case MINUS:
7493             result_low = MIN (low0, low1);
7494             break;
7495           case MULT:
7496             result_width = width0 + width1;
7497             result_low = low0 + low1;
7498             break;
7499           case DIV:
7500             if (! op0_maybe_minusp && ! op1_maybe_minusp)
7501               result_width = width0;
7502             break;
7503           case UDIV:
7504             result_width = width0;
7505             break;
7506           case MOD:
7507             if (! op0_maybe_minusp && ! op1_maybe_minusp)
7508               result_width = MIN (width0, width1);
7509             result_low = MIN (low0, low1);
7510             break;
7511           case UMOD:
7512             result_width = MIN (width0, width1);
7513             result_low = MIN (low0, low1);
7514             break;
7515           default:
7516             abort ();
7517           }
7518
7519         if (result_width < mode_width)
7520           nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
7521
7522         if (result_low > 0)
7523           nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
7524       }
7525       break;
7526
7527     case ZERO_EXTRACT:
7528       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7529           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7530         nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
7531       break;
7532
7533     case SUBREG:
7534       /* If this is a SUBREG formed for a promoted variable that has
7535          been zero-extended, we know that at least the high-order bits
7536          are zero, though others might be too.  */
7537
7538       if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
7539         nonzero = (GET_MODE_MASK (GET_MODE (x))
7540                    & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
7541
7542       /* If the inner mode is a single word for both the host and target
7543          machines, we can compute this from which bits of the inner
7544          object might be nonzero.  */
7545       if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
7546           && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7547               <= HOST_BITS_PER_WIDE_INT))
7548         {
7549           nonzero &= nonzero_bits (SUBREG_REG (x), mode);
7550
7551 #ifndef WORD_REGISTER_OPERATIONS
7552           /* On many CISC machines, accessing an object in a wider mode
7553              causes the high-order bits to become undefined.  So they are
7554              not known to be zero.  */
7555           if (GET_MODE_SIZE (GET_MODE (x))
7556               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7557             nonzero |= (GET_MODE_MASK (GET_MODE (x))
7558                         & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7559 #endif
7560         }
7561       break;
7562
7563     case ASHIFTRT:
7564     case LSHIFTRT:
7565     case ASHIFT:
7566     case ROTATE:
7567       /* The nonzero bits are in two classes: any bits within MODE
7568          that aren't in GET_MODE (x) are always significant.  The rest of the
7569          nonzero bits are those that are significant in the operand of
7570          the shift when shifted the appropriate number of bits.  This
7571          shows that high-order bits are cleared by the right shift and
7572          low-order bits by left shifts.  */
7573       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7574           && INTVAL (XEXP (x, 1)) >= 0
7575           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7576         {
7577           enum machine_mode inner_mode = GET_MODE (x);
7578           int width = GET_MODE_BITSIZE (inner_mode);
7579           int count = INTVAL (XEXP (x, 1));
7580           unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
7581           unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7582           unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
7583           unsigned HOST_WIDE_INT outer = 0;
7584
7585           if (mode_width > width)
7586             outer = (op_nonzero & nonzero & ~ mode_mask);
7587
7588           if (code == LSHIFTRT)
7589             inner >>= count;
7590           else if (code == ASHIFTRT)
7591             {
7592               inner >>= count;
7593
7594               /* If the sign bit may have been nonzero before the shift, we
7595                  need to mark all the places it could have been copied to
7596                  by the shift as possibly nonzero.  */
7597               if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7598                 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
7599             }
7600           else if (code == ASHIFT)
7601             inner <<= count;
7602           else
7603             inner = ((inner << (count % width)
7604                       | (inner >> (width - (count % width)))) & mode_mask);
7605
7606           nonzero &= (outer | inner);
7607         }
7608       break;
7609
7610     case FFS:
7611       /* This is at most the number of bits in the mode.  */
7612       nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
7613       break;
7614
7615     case IF_THEN_ELSE:
7616       nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7617                   | nonzero_bits (XEXP (x, 2), mode));
7618       break;
7619
7620     default:
7621       break;
7622     }
7623
7624   return nonzero;
7625 }
7626
7627 /* See the macro definition above.  */
7628 #undef num_sign_bit_copies
7629 \f
7630 /* Return the number of bits at the high-order end of X that are known to
7631    be equal to the sign bit.  X will be used in mode MODE; if MODE is
7632    VOIDmode, X will be used in its own mode.  The returned value  will always
7633    be between 1 and the number of bits in MODE.  */
7634
7635 static int
7636 num_sign_bit_copies (x, mode)
7637      rtx x;
7638      enum machine_mode mode;
7639 {
7640   enum rtx_code code = GET_CODE (x);
7641   int bitwidth;
7642   int num0, num1, result;
7643   unsigned HOST_WIDE_INT nonzero;
7644   rtx tem;
7645
7646   /* If we weren't given a mode, use the mode of X.  If the mode is still
7647      VOIDmode, we don't know anything.  Likewise if one of the modes is
7648      floating-point.  */
7649
7650   if (mode == VOIDmode)
7651     mode = GET_MODE (x);
7652
7653   if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
7654     return 1;
7655
7656   bitwidth = GET_MODE_BITSIZE (mode);
7657
7658   /* For a smaller object, just ignore the high bits.  */
7659   if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7660     return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7661                     - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7662
7663   if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7664     {
7665 #ifndef WORD_REGISTER_OPERATIONS
7666   /* If this machine does not do all register operations on the entire
7667      register and MODE is wider than the mode of X, we can say nothing
7668      at all about the high-order bits.  */
7669       return 1;
7670 #else
7671       /* Likewise on machines that do, if the mode of the object is smaller
7672          than a word and loads of that size don't sign extend, we can say
7673          nothing about the high order bits.  */
7674       if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
7675 #ifdef LOAD_EXTEND_OP
7676           && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
7677 #endif
7678           )
7679         return 1;
7680 #endif
7681     }
7682
7683   switch (code)
7684     {
7685     case REG:
7686
7687 #ifdef POINTERS_EXTEND_UNSIGNED
7688       /* If pointers extend signed and this is a pointer in Pmode, say that
7689          all the bits above ptr_mode are known to be sign bit copies.  */
7690       if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7691           && REGNO_POINTER_FLAG (REGNO (x)))
7692         return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7693 #endif
7694
7695       if (reg_last_set_value[REGNO (x)] != 0
7696           && reg_last_set_mode[REGNO (x)] == mode
7697           && (REG_N_SETS (REGNO (x)) == 1
7698               || reg_last_set_label[REGNO (x)] == label_tick)
7699           && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7700         return reg_last_set_sign_bit_copies[REGNO (x)];
7701
7702       tem =  get_last_value (x);
7703       if (tem != 0)
7704         return num_sign_bit_copies (tem, mode);
7705
7706       if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
7707         return reg_sign_bit_copies[REGNO (x)];
7708       break;
7709
7710     case MEM:
7711 #ifdef LOAD_EXTEND_OP
7712       /* Some RISC machines sign-extend all loads of smaller than a word.  */
7713       if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
7714         return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
7715 #endif
7716       break;
7717
7718     case CONST_INT:
7719       /* If the constant is negative, take its 1's complement and remask.
7720          Then see how many zero bits we have.  */
7721       nonzero = INTVAL (x) & GET_MODE_MASK (mode);
7722       if (bitwidth <= HOST_BITS_PER_WIDE_INT
7723           && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7724         nonzero = (~ nonzero) & GET_MODE_MASK (mode);
7725
7726       return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
7727
7728     case SUBREG:
7729       /* If this is a SUBREG for a promoted object that is sign-extended
7730          and we are looking at it in a wider mode, we know that at least the
7731          high-order bits are known to be sign bit copies.  */
7732
7733       if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
7734         return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7735                     num_sign_bit_copies (SUBREG_REG (x), mode));
7736
7737       /* For a smaller object, just ignore the high bits.  */
7738       if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7739         {
7740           num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7741           return MAX (1, (num0
7742                           - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7743                              - bitwidth)));
7744         }
7745
7746 #ifdef WORD_REGISTER_OPERATIONS
7747 #ifdef LOAD_EXTEND_OP
7748       /* For paradoxical SUBREGs on machines where all register operations
7749          affect the entire register, just look inside.  Note that we are
7750          passing MODE to the recursive call, so the number of sign bit copies
7751          will remain relative to that mode, not the inner mode.  */
7752
7753       /* This works only if loads sign extend.  Otherwise, if we get a
7754          reload for the inner part, it may be loaded from the stack, and
7755          then we lose all sign bit copies that existed before the store
7756          to the stack.  */
7757
7758       if ((GET_MODE_SIZE (GET_MODE (x))
7759            > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7760           && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
7761         return num_sign_bit_copies (SUBREG_REG (x), mode);
7762 #endif
7763 #endif
7764       break;
7765
7766     case SIGN_EXTRACT:
7767       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7768         return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7769       break;
7770
7771     case SIGN_EXTEND:
7772       return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7773               + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7774
7775     case TRUNCATE:
7776       /* For a smaller object, just ignore the high bits.  */
7777       num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7778       return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7779                               - bitwidth)));
7780
7781     case NOT:
7782       return num_sign_bit_copies (XEXP (x, 0), mode);
7783
7784     case ROTATE:       case ROTATERT:
7785       /* If we are rotating left by a number of bits less than the number
7786          of sign bit copies, we can just subtract that amount from the
7787          number.  */
7788       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7789           && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
7790         {
7791           num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7792           return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
7793                                  : bitwidth - INTVAL (XEXP (x, 1))));
7794         }
7795       break;
7796
7797     case NEG:
7798       /* In general, this subtracts one sign bit copy.  But if the value
7799          is known to be positive, the number of sign bit copies is the
7800          same as that of the input.  Finally, if the input has just one bit
7801          that might be nonzero, all the bits are copies of the sign bit.  */
7802       nonzero = nonzero_bits (XEXP (x, 0), mode);
7803       if (nonzero == 1)
7804         return bitwidth;
7805
7806       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7807       if (num0 > 1
7808           && bitwidth <= HOST_BITS_PER_WIDE_INT
7809           && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
7810         num0--;
7811
7812       return num0;
7813
7814     case IOR:   case AND:   case XOR:
7815     case SMIN:  case SMAX:  case UMIN:  case UMAX:
7816       /* Logical operations will preserve the number of sign-bit copies.
7817          MIN and MAX operations always return one of the operands.  */
7818       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7819       num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7820       return MIN (num0, num1);
7821
7822     case PLUS:  case MINUS:
7823       /* For addition and subtraction, we can have a 1-bit carry.  However,
7824          if we are subtracting 1 from a positive number, there will not
7825          be such a carry.  Furthermore, if the positive number is known to
7826          be 0 or 1, we know the result is either -1 or 0.  */
7827
7828       if (code == PLUS && XEXP (x, 1) == constm1_rtx
7829           && bitwidth <= HOST_BITS_PER_WIDE_INT)
7830         {
7831           nonzero = nonzero_bits (XEXP (x, 0), mode);
7832           if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
7833             return (nonzero == 1 || nonzero == 0 ? bitwidth
7834                     : bitwidth - floor_log2 (nonzero) - 1);
7835         }
7836
7837       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7838       num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7839       return MAX (1, MIN (num0, num1) - 1);
7840
7841     case MULT:
7842       /* The number of bits of the product is the sum of the number of
7843          bits of both terms.  However, unless one of the terms if known
7844          to be positive, we must allow for an additional bit since negating
7845          a negative number can remove one sign bit copy.  */
7846
7847       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7848       num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7849
7850       result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
7851       if (result > 0
7852           && bitwidth <= HOST_BITS_PER_WIDE_INT
7853           && ((nonzero_bits (XEXP (x, 0), mode)
7854                & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7855           && ((nonzero_bits (XEXP (x, 1), mode)
7856               & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
7857         result--;
7858
7859       return MAX (1, result);
7860
7861     case UDIV:
7862       /* The result must be <= the first operand.  */
7863       return num_sign_bit_copies (XEXP (x, 0), mode);
7864
7865     case UMOD:
7866       /* The result must be <= the scond operand.  */
7867       return num_sign_bit_copies (XEXP (x, 1), mode);
7868
7869     case DIV:
7870       /* Similar to unsigned division, except that we have to worry about
7871          the case where the divisor is negative, in which case we have
7872          to add 1.  */
7873       result = num_sign_bit_copies (XEXP (x, 0), mode);
7874       if (result > 1
7875           && bitwidth <= HOST_BITS_PER_WIDE_INT
7876           && (nonzero_bits (XEXP (x, 1), mode)
7877               & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7878         result --;
7879
7880       return result;
7881
7882     case MOD:
7883       result = num_sign_bit_copies (XEXP (x, 1), mode);
7884       if (result > 1
7885           && bitwidth <= HOST_BITS_PER_WIDE_INT
7886           && (nonzero_bits (XEXP (x, 1), mode)
7887               & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7888         result --;
7889
7890       return result;
7891
7892     case ASHIFTRT:
7893       /* Shifts by a constant add to the number of bits equal to the
7894          sign bit.  */
7895       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7896       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7897           && INTVAL (XEXP (x, 1)) > 0)
7898         num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
7899
7900       return num0;
7901
7902     case ASHIFT:
7903       /* Left shifts destroy copies.  */
7904       if (GET_CODE (XEXP (x, 1)) != CONST_INT
7905           || INTVAL (XEXP (x, 1)) < 0
7906           || INTVAL (XEXP (x, 1)) >= bitwidth)
7907         return 1;
7908
7909       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7910       return MAX (1, num0 - INTVAL (XEXP (x, 1)));
7911
7912     case IF_THEN_ELSE:
7913       num0 = num_sign_bit_copies (XEXP (x, 1), mode);
7914       num1 = num_sign_bit_copies (XEXP (x, 2), mode);
7915       return MIN (num0, num1);
7916
7917     case EQ:  case NE:  case GE:  case GT:  case LE:  case LT:
7918     case GEU: case GTU: case LEU: case LTU:
7919       if (STORE_FLAG_VALUE == -1)
7920         return bitwidth;
7921       break;
7922
7923     default:
7924       break;
7925     }
7926
7927   /* If we haven't been able to figure it out by one of the above rules,
7928      see if some of the high-order bits are known to be zero.  If so,
7929      count those bits and return one less than that amount.  If we can't
7930      safely compute the mask for this mode, always return BITWIDTH.  */
7931
7932   if (bitwidth > HOST_BITS_PER_WIDE_INT)
7933     return 1;
7934
7935   nonzero = nonzero_bits (x, mode);
7936   return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
7937           ? 1 : bitwidth - floor_log2 (nonzero) - 1);
7938 }
7939 \f
7940 /* Return the number of "extended" bits there are in X, when interpreted
7941    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
7942    unsigned quantities, this is the number of high-order zero bits.
7943    For signed quantities, this is the number of copies of the sign bit
7944    minus 1.  In both case, this function returns the number of "spare"
7945    bits.  For example, if two quantities for which this function returns
7946    at least 1 are added, the addition is known not to overflow.
7947
7948    This function will always return 0 unless called during combine, which
7949    implies that it must be called from a define_split.  */
7950
7951 int
7952 extended_count (x, mode, unsignedp)
7953      rtx x;
7954      enum machine_mode mode;
7955      int unsignedp;
7956 {
7957   if (nonzero_sign_valid == 0)
7958     return 0;
7959
7960   return (unsignedp
7961           ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7962              && (GET_MODE_BITSIZE (mode) - 1
7963                  - floor_log2 (nonzero_bits (x, mode))))
7964           : num_sign_bit_copies (x, mode) - 1);
7965 }
7966 \f
7967 /* This function is called from `simplify_shift_const' to merge two
7968    outer operations.  Specifically, we have already found that we need
7969    to perform operation *POP0 with constant *PCONST0 at the outermost
7970    position.  We would now like to also perform OP1 with constant CONST1
7971    (with *POP0 being done last).
7972
7973    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
7974    the resulting operation.  *PCOMP_P is set to 1 if we would need to
7975    complement the innermost operand, otherwise it is unchanged.
7976
7977    MODE is the mode in which the operation will be done.  No bits outside
7978    the width of this mode matter.  It is assumed that the width of this mode
7979    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
7980
7981    If *POP0 or OP1 are NIL, it means no operation is required.  Only NEG, PLUS,
7982    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
7983    result is simply *PCONST0.
7984
7985    If the resulting operation cannot be expressed as one operation, we
7986    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
7987
7988 static int
7989 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
7990      enum rtx_code *pop0;
7991      HOST_WIDE_INT *pconst0;
7992      enum rtx_code op1;
7993      HOST_WIDE_INT const1;
7994      enum machine_mode mode;
7995      int *pcomp_p;
7996 {
7997   enum rtx_code op0 = *pop0;
7998   HOST_WIDE_INT const0 = *pconst0;
7999   int width = GET_MODE_BITSIZE (mode);
8000
8001   const0 &= GET_MODE_MASK (mode);
8002   const1 &= GET_MODE_MASK (mode);
8003
8004   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
8005   if (op0 == AND)
8006     const1 &= const0;
8007
8008   /* If OP0 or OP1 is NIL, this is easy.  Similarly if they are the same or
8009      if OP0 is SET.  */
8010
8011   if (op1 == NIL || op0 == SET)
8012     return 1;
8013
8014   else if (op0 == NIL)
8015     op0 = op1, const0 = const1;
8016
8017   else if (op0 == op1)
8018     {
8019       switch (op0)
8020         {
8021         case AND:
8022           const0 &= const1;
8023           break;
8024         case IOR:
8025           const0 |= const1;
8026           break;
8027         case XOR:
8028           const0 ^= const1;
8029           break;
8030         case PLUS:
8031           const0 += const1;
8032           break;
8033         case NEG:
8034           op0 = NIL;
8035           break;
8036         default:
8037           break;
8038         }
8039     }
8040
8041   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
8042   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8043     return 0;
8044
8045   /* If the two constants aren't the same, we can't do anything.  The
8046      remaining six cases can all be done.  */
8047   else if (const0 != const1)
8048     return 0;
8049
8050   else
8051     switch (op0)
8052       {
8053       case IOR:
8054         if (op1 == AND)
8055           /* (a & b) | b == b */
8056           op0 = SET;
8057         else /* op1 == XOR */
8058           /* (a ^ b) | b == a | b */
8059           ;
8060         break;
8061
8062       case XOR:
8063         if (op1 == AND)
8064           /* (a & b) ^ b == (~a) & b */
8065           op0 = AND, *pcomp_p = 1;
8066         else /* op1 == IOR */
8067           /* (a | b) ^ b == a & ~b */
8068           op0 = AND, *pconst0 = ~ const0;
8069         break;
8070
8071       case AND:
8072         if (op1 == IOR)
8073           /* (a | b) & b == b */
8074         op0 = SET;
8075         else /* op1 == XOR */
8076           /* (a ^ b) & b) == (~a) & b */
8077           *pcomp_p = 1;
8078         break;
8079       default:
8080         break;
8081       }
8082
8083   /* Check for NO-OP cases.  */
8084   const0 &= GET_MODE_MASK (mode);
8085   if (const0 == 0
8086       && (op0 == IOR || op0 == XOR || op0 == PLUS))
8087     op0 = NIL;
8088   else if (const0 == 0 && op0 == AND)
8089     op0 = SET;
8090   else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
8091     op0 = NIL;
8092
8093   /* If this would be an entire word for the target, but is not for
8094      the host, then sign-extend on the host so that the number will look
8095      the same way on the host that it would on the target.
8096
8097      For example, when building a 64 bit alpha hosted 32 bit sparc
8098      targeted compiler, then we want the 32 bit unsigned value -1 to be
8099      represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8100      The later confuses the sparc backend.  */
8101
8102   if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8103       && (const0 & ((HOST_WIDE_INT) 1 << (width - 1))))
8104     const0 |= ((HOST_WIDE_INT) (-1) << width);
8105
8106   *pop0 = op0;
8107   *pconst0 = const0;
8108
8109   return 1;
8110 }
8111 \f
8112 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
8113    The result of the shift is RESULT_MODE.  X, if non-zero, is an expression
8114    that we started with.
8115
8116    The shift is normally computed in the widest mode we find in VAROP, as
8117    long as it isn't a different number of words than RESULT_MODE.  Exceptions
8118    are ASHIFTRT and ROTATE, which are always done in their original mode,  */
8119
8120 static rtx
8121 simplify_shift_const (x, code, result_mode, varop, count)
8122      rtx x;
8123      enum rtx_code code;
8124      enum machine_mode result_mode;
8125      rtx varop;
8126      int count;
8127 {
8128   enum rtx_code orig_code = code;
8129   int orig_count = count;
8130   enum machine_mode mode = result_mode;
8131   enum machine_mode shift_mode, tmode;
8132   int mode_words
8133     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8134   /* We form (outer_op (code varop count) (outer_const)).  */
8135   enum rtx_code outer_op = NIL;
8136   HOST_WIDE_INT outer_const = 0;
8137   rtx const_rtx;
8138   int complement_p = 0;
8139   rtx new;
8140
8141   /* If we were given an invalid count, don't do anything except exactly
8142      what was requested.  */
8143
8144   if (count < 0 || count > GET_MODE_BITSIZE (mode))
8145     {
8146       if (x)
8147         return x;
8148
8149       return gen_rtx (code, mode, varop, GEN_INT (count));
8150     }
8151
8152   /* Unless one of the branches of the `if' in this loop does a `continue',
8153      we will `break' the loop after the `if'.  */
8154
8155   while (count != 0)
8156     {
8157       /* If we have an operand of (clobber (const_int 0)), just return that
8158          value.  */
8159       if (GET_CODE (varop) == CLOBBER)
8160         return varop;
8161
8162       /* If we discovered we had to complement VAROP, leave.  Making a NOT
8163          here would cause an infinite loop.  */
8164       if (complement_p)
8165         break;
8166
8167       /* Convert ROTATERT to ROTATE.  */
8168       if (code == ROTATERT)
8169         code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8170
8171       /* We need to determine what mode we will do the shift in.  If the
8172          shift is a right shift or a ROTATE, we must always do it in the mode
8173          it was originally done in.  Otherwise, we can do it in MODE, the
8174          widest mode encountered.  */
8175       shift_mode
8176         = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8177            ? result_mode : mode);
8178
8179       /* Handle cases where the count is greater than the size of the mode
8180          minus 1.  For ASHIFT, use the size minus one as the count (this can
8181          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
8182          take the count modulo the size.  For other shifts, the result is
8183          zero.
8184
8185          Since these shifts are being produced by the compiler by combining
8186          multiple operations, each of which are defined, we know what the
8187          result is supposed to be.  */
8188
8189       if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8190         {
8191           if (code == ASHIFTRT)
8192             count = GET_MODE_BITSIZE (shift_mode) - 1;
8193           else if (code == ROTATE || code == ROTATERT)
8194             count %= GET_MODE_BITSIZE (shift_mode);
8195           else
8196             {
8197               /* We can't simply return zero because there may be an
8198                  outer op.  */
8199               varop = const0_rtx;
8200               count = 0;
8201               break;
8202             }
8203         }
8204
8205       /* Negative counts are invalid and should not have been made (a
8206          programmer-specified negative count should have been handled
8207          above).  */
8208       else if (count < 0)
8209         abort ();
8210
8211       /* An arithmetic right shift of a quantity known to be -1 or 0
8212          is a no-op.  */
8213       if (code == ASHIFTRT
8214           && (num_sign_bit_copies (varop, shift_mode)
8215               == GET_MODE_BITSIZE (shift_mode)))
8216         {
8217           count = 0;
8218           break;
8219         }
8220
8221       /* If we are doing an arithmetic right shift and discarding all but
8222          the sign bit copies, this is equivalent to doing a shift by the
8223          bitsize minus one.  Convert it into that shift because it will often
8224          allow other simplifications.  */
8225
8226       if (code == ASHIFTRT
8227           && (count + num_sign_bit_copies (varop, shift_mode)
8228               >= GET_MODE_BITSIZE (shift_mode)))
8229         count = GET_MODE_BITSIZE (shift_mode) - 1;
8230
8231       /* We simplify the tests below and elsewhere by converting
8232          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8233          `make_compound_operation' will convert it to a ASHIFTRT for
8234          those machines (such as Vax) that don't have a LSHIFTRT.  */
8235       if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8236           && code == ASHIFTRT
8237           && ((nonzero_bits (varop, shift_mode)
8238                & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8239               == 0))
8240         code = LSHIFTRT;
8241
8242       switch (GET_CODE (varop))
8243         {
8244         case SIGN_EXTEND:
8245         case ZERO_EXTEND:
8246         case SIGN_EXTRACT:
8247         case ZERO_EXTRACT:
8248           new = expand_compound_operation (varop);
8249           if (new != varop)
8250             {
8251               varop = new;
8252               continue;
8253             }
8254           break;
8255
8256         case MEM:
8257           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8258              minus the width of a smaller mode, we can do this with a
8259              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
8260           if ((code == ASHIFTRT || code == LSHIFTRT)
8261               && ! mode_dependent_address_p (XEXP (varop, 0))
8262               && ! MEM_VOLATILE_P (varop)
8263               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8264                                          MODE_INT, 1)) != BLKmode)
8265             {
8266               if (BYTES_BIG_ENDIAN)
8267                 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
8268               else
8269                 new = gen_rtx (MEM, tmode,
8270                                plus_constant (XEXP (varop, 0),
8271                                               count / BITS_PER_UNIT));
8272               RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8273               MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
8274               MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
8275               varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8276                                        : ZERO_EXTEND, mode, new);
8277               count = 0;
8278               continue;
8279             }
8280           break;
8281
8282         case USE:
8283           /* Similar to the case above, except that we can only do this if
8284              the resulting mode is the same as that of the underlying
8285              MEM and adjust the address depending on the *bits* endianness
8286              because of the way that bit-field extract insns are defined.  */
8287           if ((code == ASHIFTRT || code == LSHIFTRT)
8288               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8289                                          MODE_INT, 1)) != BLKmode
8290               && tmode == GET_MODE (XEXP (varop, 0)))
8291             {
8292               if (BITS_BIG_ENDIAN)
8293                 new = XEXP (varop, 0);
8294               else
8295                 {
8296                   new = copy_rtx (XEXP (varop, 0));
8297                   SUBST (XEXP (new, 0),
8298                          plus_constant (XEXP (new, 0),
8299                                         count / BITS_PER_UNIT));
8300                 }
8301
8302               varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8303                                        : ZERO_EXTEND, mode, new);
8304               count = 0;
8305               continue;
8306             }
8307           break;
8308
8309         case SUBREG:
8310           /* If VAROP is a SUBREG, strip it as long as the inner operand has
8311              the same number of words as what we've seen so far.  Then store
8312              the widest mode in MODE.  */
8313           if (subreg_lowpart_p (varop)
8314               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8315                   > GET_MODE_SIZE (GET_MODE (varop)))
8316               && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8317                     + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8318                   == mode_words))
8319             {
8320               varop = SUBREG_REG (varop);
8321               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8322                 mode = GET_MODE (varop);
8323               continue;
8324             }
8325           break;
8326
8327         case MULT:
8328           /* Some machines use MULT instead of ASHIFT because MULT
8329              is cheaper.  But it is still better on those machines to
8330              merge two shifts into one.  */
8331           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8332               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8333             {
8334               varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8335                                   GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
8336               continue;
8337             }
8338           break;
8339
8340         case UDIV:
8341           /* Similar, for when divides are cheaper.  */
8342           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8343               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8344             {
8345               varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8346                                   GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8347               continue;
8348             }
8349           break;
8350
8351         case ASHIFTRT:
8352           /* If we are extracting just the sign bit of an arithmetic right
8353              shift, that shift is not needed.  */
8354           if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8355             {
8356               varop = XEXP (varop, 0);
8357               continue;
8358             }
8359
8360           /* ... fall through ...  */
8361
8362         case LSHIFTRT:
8363         case ASHIFT:
8364         case ROTATE:
8365           /* Here we have two nested shifts.  The result is usually the
8366              AND of a new shift with a mask.  We compute the result below.  */
8367           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8368               && INTVAL (XEXP (varop, 1)) >= 0
8369               && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8370               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8371               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8372             {
8373               enum rtx_code first_code = GET_CODE (varop);
8374               int first_count = INTVAL (XEXP (varop, 1));
8375               unsigned HOST_WIDE_INT mask;
8376               rtx mask_rtx;
8377
8378               /* We have one common special case.  We can't do any merging if
8379                  the inner code is an ASHIFTRT of a smaller mode.  However, if
8380                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8381                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8382                  we can convert it to
8383                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8384                  This simplifies certain SIGN_EXTEND operations.  */
8385               if (code == ASHIFT && first_code == ASHIFTRT
8386                   && (GET_MODE_BITSIZE (result_mode)
8387                       - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8388                 {
8389                   /* C3 has the low-order C1 bits zero.  */
8390
8391                   mask = (GET_MODE_MASK (mode)
8392                           & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
8393
8394                   varop = simplify_and_const_int (NULL_RTX, result_mode,
8395                                                   XEXP (varop, 0), mask);
8396                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8397                                                 varop, count);
8398                   count = first_count;
8399                   code = ASHIFTRT;
8400                   continue;
8401                 }
8402
8403               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8404                  than C1 high-order bits equal to the sign bit, we can convert
8405                  this to either an ASHIFT or a ASHIFTRT depending on the
8406                  two counts.
8407
8408                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
8409
8410               if (code == ASHIFTRT && first_code == ASHIFT
8411                   && GET_MODE (varop) == shift_mode
8412                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8413                       > first_count))
8414                 {
8415                   count -= first_count;
8416                   if (count < 0)
8417                     count = - count, code = ASHIFT;
8418                   varop = XEXP (varop, 0);
8419                   continue;
8420                 }
8421
8422               /* There are some cases we can't do.  If CODE is ASHIFTRT,
8423                  we can only do this if FIRST_CODE is also ASHIFTRT.
8424
8425                  We can't do the case when CODE is ROTATE and FIRST_CODE is
8426                  ASHIFTRT.
8427
8428                  If the mode of this shift is not the mode of the outer shift,
8429                  we can't do this if either shift is a right shift or ROTATE.
8430
8431                  Finally, we can't do any of these if the mode is too wide
8432                  unless the codes are the same.
8433
8434                  Handle the case where the shift codes are the same
8435                  first.  */
8436
8437               if (code == first_code)
8438                 {
8439                   if (GET_MODE (varop) != result_mode
8440                       && (code == ASHIFTRT || code == LSHIFTRT
8441                           || code == ROTATE))
8442                     break;
8443
8444                   count += first_count;
8445                   varop = XEXP (varop, 0);
8446                   continue;
8447                 }
8448
8449               if (code == ASHIFTRT
8450                   || (code == ROTATE && first_code == ASHIFTRT)
8451                   || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8452                   || (GET_MODE (varop) != result_mode
8453                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
8454                           || first_code == ROTATE
8455                           || code == ROTATE)))
8456                 break;
8457
8458               /* To compute the mask to apply after the shift, shift the
8459                  nonzero bits of the inner shift the same way the
8460                  outer shift will.  */
8461
8462               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8463
8464               mask_rtx
8465                 = simplify_binary_operation (code, result_mode, mask_rtx,
8466                                              GEN_INT (count));
8467
8468               /* Give up if we can't compute an outer operation to use.  */
8469               if (mask_rtx == 0
8470                   || GET_CODE (mask_rtx) != CONST_INT
8471                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
8472                                         INTVAL (mask_rtx),
8473                                         result_mode, &complement_p))
8474                 break;
8475
8476               /* If the shifts are in the same direction, we add the
8477                  counts.  Otherwise, we subtract them.  */
8478               if ((code == ASHIFTRT || code == LSHIFTRT)
8479                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8480                 count += first_count;
8481               else
8482                 count -= first_count;
8483
8484               /* If COUNT is positive, the new shift is usually CODE,
8485                  except for the two exceptions below, in which case it is
8486                  FIRST_CODE.  If the count is negative, FIRST_CODE should
8487                  always be used  */
8488               if (count > 0
8489                   && ((first_code == ROTATE && code == ASHIFT)
8490                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
8491                 code = first_code;
8492               else if (count < 0)
8493                 code = first_code, count = - count;
8494
8495               varop = XEXP (varop, 0);
8496               continue;
8497             }
8498
8499           /* If we have (A << B << C) for any shift, we can convert this to
8500              (A << C << B).  This wins if A is a constant.  Only try this if
8501              B is not a constant.  */
8502
8503           else if (GET_CODE (varop) == code
8504                    && GET_CODE (XEXP (varop, 1)) != CONST_INT
8505                    && 0 != (new
8506                             = simplify_binary_operation (code, mode,
8507                                                          XEXP (varop, 0),
8508                                                          GEN_INT (count))))
8509             {
8510               varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8511               count = 0;
8512               continue;
8513             }
8514           break;
8515
8516         case NOT:
8517           /* Make this fit the case below.  */
8518           varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
8519                                    GEN_INT (GET_MODE_MASK (mode)));
8520           continue;
8521
8522         case IOR:
8523         case AND:
8524         case XOR:
8525           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8526              with C the size of VAROP - 1 and the shift is logical if
8527              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8528              we have an (le X 0) operation.   If we have an arithmetic shift
8529              and STORE_FLAG_VALUE is 1 or we have a logical shift with
8530              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
8531
8532           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8533               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8534               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8535               && (code == LSHIFTRT || code == ASHIFTRT)
8536               && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8537               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8538             {
8539               count = 0;
8540               varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8541                                        const0_rtx);
8542
8543               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8544                 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8545
8546               continue;
8547             }
8548
8549           /* If we have (shift (logical)), move the logical to the outside
8550              to allow it to possibly combine with another logical and the
8551              shift to combine with another shift.  This also canonicalizes to
8552              what a ZERO_EXTRACT looks like.  Also, some machines have
8553              (and (shift)) insns.  */
8554
8555           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8556               && (new = simplify_binary_operation (code, result_mode,
8557                                                    XEXP (varop, 1),
8558                                                    GEN_INT (count))) != 0
8559               && GET_CODE(new) == CONST_INT
8560               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8561                                   INTVAL (new), result_mode, &complement_p))
8562             {
8563               varop = XEXP (varop, 0);
8564               continue;
8565             }
8566
8567           /* If we can't do that, try to simplify the shift in each arm of the
8568              logical expression, make a new logical expression, and apply
8569              the inverse distributive law.  */
8570           {
8571             rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8572                                             XEXP (varop, 0), count);
8573             rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8574                                             XEXP (varop, 1), count);
8575
8576             varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8577             varop = apply_distributive_law (varop);
8578
8579             count = 0;
8580           }
8581           break;
8582
8583         case EQ:
8584           /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8585              says that the sign bit can be tested, FOO has mode MODE, C is
8586              GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8587              that may be nonzero.  */
8588           if (code == LSHIFTRT
8589               && XEXP (varop, 1) == const0_rtx
8590               && GET_MODE (XEXP (varop, 0)) == result_mode
8591               && count == GET_MODE_BITSIZE (result_mode) - 1
8592               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8593               && ((STORE_FLAG_VALUE
8594                    & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
8595               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8596               && merge_outer_ops (&outer_op, &outer_const, XOR,
8597                                   (HOST_WIDE_INT) 1, result_mode,
8598                                   &complement_p))
8599             {
8600               varop = XEXP (varop, 0);
8601               count = 0;
8602               continue;
8603             }
8604           break;
8605
8606         case NEG:
8607           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8608              than the number of bits in the mode is equivalent to A.  */
8609           if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8610               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8611             {
8612               varop = XEXP (varop, 0);
8613               count = 0;
8614               continue;
8615             }
8616
8617           /* NEG commutes with ASHIFT since it is multiplication.  Move the
8618              NEG outside to allow shifts to combine.  */
8619           if (code == ASHIFT
8620               && merge_outer_ops (&outer_op, &outer_const, NEG,
8621                                   (HOST_WIDE_INT) 0, result_mode,
8622                                   &complement_p))
8623             {
8624               varop = XEXP (varop, 0);
8625               continue;
8626             }
8627           break;
8628
8629         case PLUS:
8630           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8631              is one less than the number of bits in the mode is
8632              equivalent to (xor A 1).  */
8633           if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8634               && XEXP (varop, 1) == constm1_rtx
8635               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8636               && merge_outer_ops (&outer_op, &outer_const, XOR,
8637                                   (HOST_WIDE_INT) 1, result_mode,
8638                                   &complement_p))
8639             {
8640               count = 0;
8641               varop = XEXP (varop, 0);
8642               continue;
8643             }
8644
8645           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8646              that might be nonzero in BAR are those being shifted out and those
8647              bits are known zero in FOO, we can replace the PLUS with FOO.
8648              Similarly in the other operand order.  This code occurs when
8649              we are computing the size of a variable-size array.  */
8650
8651           if ((code == ASHIFTRT || code == LSHIFTRT)
8652               && count < HOST_BITS_PER_WIDE_INT
8653               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8654               && (nonzero_bits (XEXP (varop, 1), result_mode)
8655                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8656             {
8657               varop = XEXP (varop, 0);
8658               continue;
8659             }
8660           else if ((code == ASHIFTRT || code == LSHIFTRT)
8661                    && count < HOST_BITS_PER_WIDE_INT
8662                    && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8663                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8664                             >> count)
8665                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8666                             & nonzero_bits (XEXP (varop, 1),
8667                                                  result_mode)))
8668             {
8669               varop = XEXP (varop, 1);
8670               continue;
8671             }
8672
8673           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
8674           if (code == ASHIFT
8675               && GET_CODE (XEXP (varop, 1)) == CONST_INT
8676               && (new = simplify_binary_operation (ASHIFT, result_mode,
8677                                                    XEXP (varop, 1),
8678                                                    GEN_INT (count))) != 0
8679               && GET_CODE(new) == CONST_INT
8680               && merge_outer_ops (&outer_op, &outer_const, PLUS,
8681                                   INTVAL (new), result_mode, &complement_p))
8682             {
8683               varop = XEXP (varop, 0);
8684               continue;
8685             }
8686           break;
8687
8688         case MINUS:
8689           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8690              with C the size of VAROP - 1 and the shift is logical if
8691              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8692              we have a (gt X 0) operation.  If the shift is arithmetic with
8693              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8694              we have a (neg (gt X 0)) operation.  */
8695
8696           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8697               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
8698               && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8699               && (code == LSHIFTRT || code == ASHIFTRT)
8700               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8701               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8702               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8703             {
8704               count = 0;
8705               varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8706                                        const0_rtx);
8707
8708               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8709                 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8710
8711               continue;
8712             }
8713           break;
8714
8715         default:
8716           break;
8717         }
8718
8719       break;
8720     }
8721
8722   /* We need to determine what mode to do the shift in.  If the shift is
8723      a right shift or ROTATE, we must always do it in the mode it was
8724      originally done in.  Otherwise, we can do it in MODE, the widest mode
8725      encountered.  The code we care about is that of the shift that will
8726      actually be done, not the shift that was originally requested.  */
8727   shift_mode
8728     = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8729        ? result_mode : mode);
8730
8731   /* We have now finished analyzing the shift.  The result should be
8732      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
8733      OUTER_OP is non-NIL, it is an operation that needs to be applied
8734      to the result of the shift.  OUTER_CONST is the relevant constant,
8735      but we must turn off all bits turned off in the shift.
8736
8737      If we were passed a value for X, see if we can use any pieces of
8738      it.  If not, make new rtx.  */
8739
8740   if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
8741       && GET_CODE (XEXP (x, 1)) == CONST_INT
8742       && INTVAL (XEXP (x, 1)) == count)
8743     const_rtx = XEXP (x, 1);
8744   else
8745     const_rtx = GEN_INT (count);
8746
8747   if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8748       && GET_MODE (XEXP (x, 0)) == shift_mode
8749       && SUBREG_REG (XEXP (x, 0)) == varop)
8750     varop = XEXP (x, 0);
8751   else if (GET_MODE (varop) != shift_mode)
8752     varop = gen_lowpart_for_combine (shift_mode, varop);
8753
8754   /* If we can't make the SUBREG, try to return what we were given.  */
8755   if (GET_CODE (varop) == CLOBBER)
8756     return x ? x : varop;
8757
8758   new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
8759   if (new != 0)
8760     x = new;
8761   else
8762     {
8763       if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
8764         x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
8765
8766       SUBST (XEXP (x, 0), varop);
8767       SUBST (XEXP (x, 1), const_rtx);
8768     }
8769
8770   /* If we have an outer operation and we just made a shift, it is
8771      possible that we could have simplified the shift were it not
8772      for the outer operation.  So try to do the simplification
8773      recursively.  */
8774
8775   if (outer_op != NIL && GET_CODE (x) == code
8776       && GET_CODE (XEXP (x, 1)) == CONST_INT)
8777     x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
8778                               INTVAL (XEXP (x, 1)));
8779
8780   /* If we were doing a LSHIFTRT in a wider mode than it was originally,
8781      turn off all the bits that the shift would have turned off.  */
8782   if (orig_code == LSHIFTRT && result_mode != shift_mode)
8783     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
8784                                 GET_MODE_MASK (result_mode) >> orig_count);
8785
8786   /* Do the remainder of the processing in RESULT_MODE.  */
8787   x = gen_lowpart_for_combine (result_mode, x);
8788
8789   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
8790      operation.  */
8791   if (complement_p)
8792     x = gen_unary (NOT, result_mode, result_mode, x);
8793
8794   if (outer_op != NIL)
8795     {
8796       if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
8797         {
8798           int width = GET_MODE_BITSIZE (result_mode);
8799
8800           outer_const &= GET_MODE_MASK (result_mode);
8801
8802           /* If this would be an entire word for the target, but is not for
8803              the host, then sign-extend on the host so that the number will
8804              look the same way on the host that it would on the target.
8805
8806              For example, when building a 64 bit alpha hosted 32 bit sparc
8807              targeted compiler, then we want the 32 bit unsigned value -1 to be
8808              represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8809              The later confuses the sparc backend.  */
8810
8811           if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8812               && (outer_const & ((HOST_WIDE_INT) 1 << (width - 1))))
8813             outer_const |= ((HOST_WIDE_INT) (-1) << width);
8814         }
8815
8816       if (outer_op == AND)
8817         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
8818       else if (outer_op == SET)
8819         /* This means that we have determined that the result is
8820            equivalent to a constant.  This should be rare.  */
8821         x = GEN_INT (outer_const);
8822       else if (GET_RTX_CLASS (outer_op) == '1')
8823         x = gen_unary (outer_op, result_mode, result_mode, x);
8824       else
8825         x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
8826     }
8827
8828   return x;
8829 }
8830 \f
8831 /* Like recog, but we receive the address of a pointer to a new pattern.
8832    We try to match the rtx that the pointer points to.
8833    If that fails, we may try to modify or replace the pattern,
8834    storing the replacement into the same pointer object.
8835
8836    Modifications include deletion or addition of CLOBBERs.
8837
8838    PNOTES is a pointer to a location where any REG_UNUSED notes added for
8839    the CLOBBERs are placed.
8840
8841    PADDED_SCRATCHES is set to the number of (clobber (scratch)) patterns
8842    we had to add.
8843
8844    The value is the final insn code from the pattern ultimately matched,
8845    or -1.  */
8846
8847 static int
8848 recog_for_combine (pnewpat, insn, pnotes, padded_scratches)
8849      rtx *pnewpat;
8850      rtx insn;
8851      rtx *pnotes;
8852      int *padded_scratches;
8853 {
8854   register rtx pat = *pnewpat;
8855   int insn_code_number;
8856   int num_clobbers_to_add = 0;
8857   int i;
8858   rtx notes = 0;
8859
8860   *padded_scratches = 0;
8861
8862   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
8863      we use to indicate that something didn't match.  If we find such a
8864      thing, force rejection.  */
8865   if (GET_CODE (pat) == PARALLEL)
8866     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
8867       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
8868           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
8869         return -1;
8870
8871   /* Is the result of combination a valid instruction?  */
8872   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8873
8874   /* If it isn't, there is the possibility that we previously had an insn
8875      that clobbered some register as a side effect, but the combined
8876      insn doesn't need to do that.  So try once more without the clobbers
8877      unless this represents an ASM insn.  */
8878
8879   if (insn_code_number < 0 && ! check_asm_operands (pat)
8880       && GET_CODE (pat) == PARALLEL)
8881     {
8882       int pos;
8883
8884       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
8885         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
8886           {
8887             if (i != pos)
8888               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
8889             pos++;
8890           }
8891
8892       SUBST_INT (XVECLEN (pat, 0), pos);
8893
8894       if (pos == 1)
8895         pat = XVECEXP (pat, 0, 0);
8896
8897       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8898     }
8899
8900   /* If we had any clobbers to add, make a new pattern than contains
8901      them.  Then check to make sure that all of them are dead.  */
8902   if (num_clobbers_to_add)
8903     {
8904       rtx newpat = gen_rtx (PARALLEL, VOIDmode,
8905                             gen_rtvec (GET_CODE (pat) == PARALLEL
8906                                        ? XVECLEN (pat, 0) + num_clobbers_to_add
8907                                        : num_clobbers_to_add + 1));
8908
8909       if (GET_CODE (pat) == PARALLEL)
8910         for (i = 0; i < XVECLEN (pat, 0); i++)
8911           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
8912       else
8913         XVECEXP (newpat, 0, 0) = pat;
8914
8915       add_clobbers (newpat, insn_code_number);
8916
8917       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
8918            i < XVECLEN (newpat, 0); i++)
8919         {
8920           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
8921               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
8922             return -1;
8923           else if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == SCRATCH)
8924             (*padded_scratches)++;
8925           notes = gen_rtx (EXPR_LIST, REG_UNUSED,
8926                            XEXP (XVECEXP (newpat, 0, i), 0), notes);
8927         }
8928       pat = newpat;
8929     }
8930
8931   *pnewpat = pat;
8932   *pnotes = notes;
8933
8934   return insn_code_number;
8935 }
8936 \f
8937 /* Like gen_lowpart but for use by combine.  In combine it is not possible
8938    to create any new pseudoregs.  However, it is safe to create
8939    invalid memory addresses, because combine will try to recognize
8940    them and all they will do is make the combine attempt fail.
8941
8942    If for some reason this cannot do its job, an rtx
8943    (clobber (const_int 0)) is returned.
8944    An insn containing that will not be recognized.  */
8945
8946 #undef gen_lowpart
8947
8948 static rtx
8949 gen_lowpart_for_combine (mode, x)
8950      enum machine_mode mode;
8951      register rtx x;
8952 {
8953   rtx result;
8954
8955   if (GET_MODE (x) == mode)
8956     return x;
8957
8958   /* We can only support MODE being wider than a word if X is a
8959      constant integer or has a mode the same size.  */
8960
8961   if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8962       && ! ((GET_MODE (x) == VOIDmode
8963              && (GET_CODE (x) == CONST_INT
8964                  || GET_CODE (x) == CONST_DOUBLE))
8965             || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
8966     return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8967
8968   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
8969      won't know what to do.  So we will strip off the SUBREG here and
8970      process normally.  */
8971   if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
8972     {
8973       x = SUBREG_REG (x);
8974       if (GET_MODE (x) == mode)
8975         return x;
8976     }
8977
8978   result = gen_lowpart_common (mode, x);
8979   if (result != 0
8980       && GET_CODE (result) == SUBREG
8981       && GET_CODE (SUBREG_REG (result)) == REG
8982       && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
8983       && (GET_MODE_SIZE (GET_MODE (result))
8984           != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
8985     REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
8986
8987   if (result)
8988     return result;
8989
8990   if (GET_CODE (x) == MEM)
8991     {
8992       register int offset = 0;
8993       rtx new;
8994
8995       /* Refuse to work on a volatile memory ref or one with a mode-dependent
8996          address.  */
8997       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
8998         return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8999
9000       /* If we want to refer to something bigger than the original memref,
9001          generate a perverse subreg instead.  That will force a reload
9002          of the original memref X.  */
9003       if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9004         return gen_rtx (SUBREG, mode, x, 0);
9005
9006       if (WORDS_BIG_ENDIAN)
9007         offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9008                   - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9009       if (BYTES_BIG_ENDIAN)
9010         {
9011           /* Adjust the address so that the address-after-the-data is
9012              unchanged.  */
9013           offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9014                      - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9015         }
9016       new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
9017       RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
9018       MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
9019       MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
9020       return new;
9021     }
9022
9023   /* If X is a comparison operator, rewrite it in a new mode.  This
9024      probably won't match, but may allow further simplifications.  */
9025   else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9026     return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9027
9028   /* If we couldn't simplify X any other way, just enclose it in a
9029      SUBREG.  Normally, this SUBREG won't match, but some patterns may
9030      include an explicit SUBREG or we may simplify it further in combine.  */
9031   else
9032     {
9033       int word = 0;
9034
9035       if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9036         word = ((GET_MODE_SIZE (GET_MODE (x))
9037                  - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9038                 / UNITS_PER_WORD);
9039       return gen_rtx (SUBREG, mode, x, word);
9040     }
9041 }
9042 \f
9043 /* Make an rtx expression.  This is a subset of gen_rtx and only supports
9044    expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9045
9046    If the identical expression was previously in the insn (in the undobuf),
9047    it will be returned.  Only if it is not found will a new expression
9048    be made.  */
9049
9050 /*VARARGS2*/
9051 static rtx
9052 gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
9053 {
9054 #ifndef __STDC__
9055   enum rtx_code code;
9056   enum machine_mode mode;
9057 #endif
9058   va_list p;
9059   int n_args;
9060   rtx args[3];
9061   int i, j;
9062   char *fmt;
9063   rtx rt;
9064   struct undo *undo;
9065
9066   VA_START (p, mode);
9067
9068 #ifndef __STDC__
9069   code = va_arg (p, enum rtx_code);
9070   mode = va_arg (p, enum machine_mode);
9071 #endif
9072
9073   n_args = GET_RTX_LENGTH (code);
9074   fmt = GET_RTX_FORMAT (code);
9075
9076   if (n_args == 0 || n_args > 3)
9077     abort ();
9078
9079   /* Get each arg and verify that it is supposed to be an expression.  */
9080   for (j = 0; j < n_args; j++)
9081     {
9082       if (*fmt++ != 'e')
9083         abort ();
9084
9085       args[j] = va_arg (p, rtx);
9086     }
9087
9088   /* See if this is in undobuf.  Be sure we don't use objects that came
9089      from another insn; this could produce circular rtl structures.  */
9090
9091   for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9092     if (!undo->is_int
9093         && GET_CODE (undo->old_contents.r) == code
9094         && GET_MODE (undo->old_contents.r) == mode)
9095       {
9096         for (j = 0; j < n_args; j++)
9097           if (XEXP (undo->old_contents.r, j) != args[j])
9098             break;
9099
9100         if (j == n_args)
9101           return undo->old_contents.r;
9102       }
9103
9104   /* Otherwise make a new rtx.  We know we have 1, 2, or 3 args.
9105      Use rtx_alloc instead of gen_rtx because it's faster on RISC.  */
9106   rt = rtx_alloc (code);
9107   PUT_MODE (rt, mode);
9108   XEXP (rt, 0) = args[0];
9109   if (n_args > 1)
9110     {
9111       XEXP (rt, 1) = args[1];
9112       if (n_args > 2)
9113         XEXP (rt, 2) = args[2];
9114     }
9115   return rt;
9116 }
9117
9118 /* These routines make binary and unary operations by first seeing if they
9119    fold; if not, a new expression is allocated.  */
9120
9121 static rtx
9122 gen_binary (code, mode, op0, op1)
9123      enum rtx_code code;
9124      enum machine_mode mode;
9125      rtx op0, op1;
9126 {
9127   rtx result;
9128   rtx tem;
9129
9130   if (GET_RTX_CLASS (code) == 'c'
9131       && (GET_CODE (op0) == CONST_INT
9132           || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9133     tem = op0, op0 = op1, op1 = tem;
9134
9135   if (GET_RTX_CLASS (code) == '<')
9136     {
9137       enum machine_mode op_mode = GET_MODE (op0);
9138
9139       /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9140          just (REL_OP X Y).  */
9141       if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9142         {
9143           op1 = XEXP (op0, 1);
9144           op0 = XEXP (op0, 0);
9145           op_mode = GET_MODE (op0);
9146         }
9147
9148       if (op_mode == VOIDmode)
9149         op_mode = GET_MODE (op1);
9150       result = simplify_relational_operation (code, op_mode, op0, op1);
9151     }
9152   else
9153     result = simplify_binary_operation (code, mode, op0, op1);
9154
9155   if (result)
9156     return result;
9157
9158   /* Put complex operands first and constants second.  */
9159   if (GET_RTX_CLASS (code) == 'c'
9160       && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9161           || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9162               && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9163           || (GET_CODE (op0) == SUBREG
9164               && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9165               && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9166     return gen_rtx_combine (code, mode, op1, op0);
9167
9168   return gen_rtx_combine (code, mode, op0, op1);
9169 }
9170
9171 static rtx
9172 gen_unary (code, mode, op0_mode, op0)
9173      enum rtx_code code;
9174      enum machine_mode mode, op0_mode;
9175      rtx op0;
9176 {
9177   rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9178
9179   if (result)
9180     return result;
9181
9182   return gen_rtx_combine (code, mode, op0);
9183 }
9184 \f
9185 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9186    comparison code that will be tested.
9187
9188    The result is a possibly different comparison code to use.  *POP0 and
9189    *POP1 may be updated.
9190
9191    It is possible that we might detect that a comparison is either always
9192    true or always false.  However, we do not perform general constant
9193    folding in combine, so this knowledge isn't useful.  Such tautologies
9194    should have been detected earlier.  Hence we ignore all such cases.  */
9195
9196 static enum rtx_code
9197 simplify_comparison (code, pop0, pop1)
9198      enum rtx_code code;
9199      rtx *pop0;
9200      rtx *pop1;
9201 {
9202   rtx op0 = *pop0;
9203   rtx op1 = *pop1;
9204   rtx tem, tem1;
9205   int i;
9206   enum machine_mode mode, tmode;
9207
9208   /* Try a few ways of applying the same transformation to both operands.  */
9209   while (1)
9210     {
9211 #ifndef WORD_REGISTER_OPERATIONS
9212       /* The test below this one won't handle SIGN_EXTENDs on these machines,
9213          so check specially.  */
9214       if (code != GTU && code != GEU && code != LTU && code != LEU
9215           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9216           && GET_CODE (XEXP (op0, 0)) == ASHIFT
9217           && GET_CODE (XEXP (op1, 0)) == ASHIFT
9218           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9219           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9220           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9221               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9222           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9223           && GET_CODE (XEXP (op1, 1)) == CONST_INT
9224           && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9225           && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9226           && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9227           && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9228           && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9229           && (INTVAL (XEXP (op0, 1))
9230               == (GET_MODE_BITSIZE (GET_MODE (op0))
9231                   - (GET_MODE_BITSIZE
9232                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9233         {
9234           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9235           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9236         }
9237 #endif
9238
9239       /* If both operands are the same constant shift, see if we can ignore the
9240          shift.  We can if the shift is a rotate or if the bits shifted out of
9241          this shift are known to be zero for both inputs and if the type of
9242          comparison is compatible with the shift.  */
9243       if (GET_CODE (op0) == GET_CODE (op1)
9244           && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9245           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9246               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9247                   && (code != GT && code != LT && code != GE && code != LE))
9248               || (GET_CODE (op0) == ASHIFTRT
9249                   && (code != GTU && code != LTU
9250                       && code != GEU && code != GEU)))
9251           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9252           && INTVAL (XEXP (op0, 1)) >= 0
9253           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9254           && XEXP (op0, 1) == XEXP (op1, 1))
9255         {
9256           enum machine_mode mode = GET_MODE (op0);
9257           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9258           int shift_count = INTVAL (XEXP (op0, 1));
9259
9260           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9261             mask &= (mask >> shift_count) << shift_count;
9262           else if (GET_CODE (op0) == ASHIFT)
9263             mask = (mask & (mask << shift_count)) >> shift_count;
9264
9265           if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9266               && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9267             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9268           else
9269             break;
9270         }
9271
9272       /* If both operands are AND's of a paradoxical SUBREG by constant, the
9273          SUBREGs are of the same mode, and, in both cases, the AND would
9274          be redundant if the comparison was done in the narrower mode,
9275          do the comparison in the narrower mode (e.g., we are AND'ing with 1
9276          and the operand's possibly nonzero bits are 0xffffff01; in that case
9277          if we only care about QImode, we don't need the AND).  This case
9278          occurs if the output mode of an scc insn is not SImode and
9279          STORE_FLAG_VALUE == 1 (e.g., the 386).
9280
9281          Similarly, check for a case where the AND's are ZERO_EXTEND
9282          operations from some narrower mode even though a SUBREG is not
9283          present.  */
9284
9285       else if  (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9286                 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9287                 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9288         {
9289           rtx inner_op0 = XEXP (op0, 0);
9290           rtx inner_op1 = XEXP (op1, 0);
9291           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9292           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9293           int changed = 0;
9294
9295           if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9296               && (GET_MODE_SIZE (GET_MODE (inner_op0))
9297                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9298               && (GET_MODE (SUBREG_REG (inner_op0))
9299                   == GET_MODE (SUBREG_REG (inner_op1)))
9300               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9301                   <= HOST_BITS_PER_WIDE_INT)
9302               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9303                                              GET_MODE (SUBREG_REG (op0)))))
9304               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9305                                              GET_MODE (SUBREG_REG (inner_op1))))))
9306             {
9307               op0 = SUBREG_REG (inner_op0);
9308               op1 = SUBREG_REG (inner_op1);
9309
9310               /* The resulting comparison is always unsigned since we masked
9311                  off the original sign bit.  */
9312               code = unsigned_condition (code);
9313
9314               changed = 1;
9315             }
9316
9317           else if (c0 == c1)
9318             for (tmode = GET_CLASS_NARROWEST_MODE
9319                  (GET_MODE_CLASS (GET_MODE (op0)));
9320                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9321               if (c0 == GET_MODE_MASK (tmode))
9322                 {
9323                   op0 = gen_lowpart_for_combine (tmode, inner_op0);
9324                   op1 = gen_lowpart_for_combine (tmode, inner_op1);
9325                   code = unsigned_condition (code);
9326                   changed = 1;
9327                   break;
9328                 }
9329
9330           if (! changed)
9331             break;
9332         }
9333
9334       /* If both operands are NOT, we can strip off the outer operation
9335          and adjust the comparison code for swapped operands; similarly for
9336          NEG, except that this must be an equality comparison.  */
9337       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9338                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9339                    && (code == EQ || code == NE)))
9340         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9341
9342       else
9343         break;
9344     }
9345
9346   /* If the first operand is a constant, swap the operands and adjust the
9347      comparison code appropriately, but don't do this if the second operand
9348      is already a constant integer.  */
9349   if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9350     {
9351       tem = op0, op0 = op1, op1 = tem;
9352       code = swap_condition (code);
9353     }
9354
9355   /* We now enter a loop during which we will try to simplify the comparison.
9356      For the most part, we only are concerned with comparisons with zero,
9357      but some things may really be comparisons with zero but not start
9358      out looking that way.  */
9359
9360   while (GET_CODE (op1) == CONST_INT)
9361     {
9362       enum machine_mode mode = GET_MODE (op0);
9363       int mode_width = GET_MODE_BITSIZE (mode);
9364       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9365       int equality_comparison_p;
9366       int sign_bit_comparison_p;
9367       int unsigned_comparison_p;
9368       HOST_WIDE_INT const_op;
9369
9370       /* We only want to handle integral modes.  This catches VOIDmode,
9371          CCmode, and the floating-point modes.  An exception is that we
9372          can handle VOIDmode if OP0 is a COMPARE or a comparison
9373          operation.  */
9374
9375       if (GET_MODE_CLASS (mode) != MODE_INT
9376           && ! (mode == VOIDmode
9377                 && (GET_CODE (op0) == COMPARE
9378                     || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9379         break;
9380
9381       /* Get the constant we are comparing against and turn off all bits
9382          not on in our mode.  */
9383       const_op = INTVAL (op1);
9384       if (mode_width <= HOST_BITS_PER_WIDE_INT)
9385         const_op &= mask;
9386
9387       /* If we are comparing against a constant power of two and the value
9388          being compared can only have that single bit nonzero (e.g., it was
9389          `and'ed with that bit), we can replace this with a comparison
9390          with zero.  */
9391       if (const_op
9392           && (code == EQ || code == NE || code == GE || code == GEU
9393               || code == LT || code == LTU)
9394           && mode_width <= HOST_BITS_PER_WIDE_INT
9395           && exact_log2 (const_op) >= 0
9396           && nonzero_bits (op0, mode) == const_op)
9397         {
9398           code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9399           op1 = const0_rtx, const_op = 0;
9400         }
9401
9402       /* Similarly, if we are comparing a value known to be either -1 or
9403          0 with -1, change it to the opposite comparison against zero.  */
9404
9405       if (const_op == -1
9406           && (code == EQ || code == NE || code == GT || code == LE
9407               || code == GEU || code == LTU)
9408           && num_sign_bit_copies (op0, mode) == mode_width)
9409         {
9410           code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9411           op1 = const0_rtx, const_op = 0;
9412         }
9413
9414       /* Do some canonicalizations based on the comparison code.  We prefer
9415          comparisons against zero and then prefer equality comparisons.
9416          If we can reduce the size of a constant, we will do that too.  */
9417
9418       switch (code)
9419         {
9420         case LT:
9421           /* < C is equivalent to <= (C - 1) */
9422           if (const_op > 0)
9423             {
9424               const_op -= 1;
9425               op1 = GEN_INT (const_op);
9426               code = LE;
9427               /* ... fall through to LE case below.  */
9428             }
9429           else
9430             break;
9431
9432         case LE:
9433           /* <= C is equivalent to < (C + 1); we do this for C < 0  */
9434           if (const_op < 0)
9435             {
9436               const_op += 1;
9437               op1 = GEN_INT (const_op);
9438               code = LT;
9439             }
9440
9441           /* If we are doing a <= 0 comparison on a value known to have
9442              a zero sign bit, we can replace this with == 0.  */
9443           else if (const_op == 0
9444                    && mode_width <= HOST_BITS_PER_WIDE_INT
9445                    && (nonzero_bits (op0, mode)
9446                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9447             code = EQ;
9448           break;
9449
9450         case GE:
9451           /* >= C is equivalent to > (C - 1).  */
9452           if (const_op > 0)
9453             {
9454               const_op -= 1;
9455               op1 = GEN_INT (const_op);
9456               code = GT;
9457               /* ... fall through to GT below.  */
9458             }
9459           else
9460             break;
9461
9462         case GT:
9463           /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9464           if (const_op < 0)
9465             {
9466               const_op += 1;
9467               op1 = GEN_INT (const_op);
9468               code = GE;
9469             }
9470
9471           /* If we are doing a > 0 comparison on a value known to have
9472              a zero sign bit, we can replace this with != 0.  */
9473           else if (const_op == 0
9474                    && mode_width <= HOST_BITS_PER_WIDE_INT
9475                    && (nonzero_bits (op0, mode)
9476                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9477             code = NE;
9478           break;
9479
9480         case LTU:
9481           /* < C is equivalent to <= (C - 1).  */
9482           if (const_op > 0)
9483             {
9484               const_op -= 1;
9485               op1 = GEN_INT (const_op);
9486               code = LEU;
9487               /* ... fall through ...  */
9488             }
9489
9490           /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
9491           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9492                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9493             {
9494               const_op = 0, op1 = const0_rtx;
9495               code = GE;
9496               break;
9497             }
9498           else
9499             break;
9500
9501         case LEU:
9502           /* unsigned <= 0 is equivalent to == 0 */
9503           if (const_op == 0)
9504             code = EQ;
9505
9506           /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
9507           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9508                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9509             {
9510               const_op = 0, op1 = const0_rtx;
9511               code = GE;
9512             }
9513           break;
9514
9515         case GEU:
9516           /* >= C is equivalent to < (C - 1).  */
9517           if (const_op > 1)
9518             {
9519               const_op -= 1;
9520               op1 = GEN_INT (const_op);
9521               code = GTU;
9522               /* ... fall through ...  */
9523             }
9524
9525           /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
9526           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9527                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9528             {
9529               const_op = 0, op1 = const0_rtx;
9530               code = LT;
9531               break;
9532             }
9533           else
9534             break;
9535
9536         case GTU:
9537           /* unsigned > 0 is equivalent to != 0 */
9538           if (const_op == 0)
9539             code = NE;
9540
9541           /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
9542           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9543                     && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9544             {
9545               const_op = 0, op1 = const0_rtx;
9546               code = LT;
9547             }
9548           break;
9549
9550         default:
9551           break;
9552         }
9553
9554       /* Compute some predicates to simplify code below.  */
9555
9556       equality_comparison_p = (code == EQ || code == NE);
9557       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9558       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9559                                || code == LEU);
9560
9561       /* If this is a sign bit comparison and we can do arithmetic in
9562          MODE, say that we will only be needing the sign bit of OP0.  */
9563       if (sign_bit_comparison_p
9564           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9565         op0 = force_to_mode (op0, mode,
9566                              ((HOST_WIDE_INT) 1
9567                               << (GET_MODE_BITSIZE (mode) - 1)),
9568                              NULL_RTX, 0);
9569
9570       /* Now try cases based on the opcode of OP0.  If none of the cases
9571          does a "continue", we exit this loop immediately after the
9572          switch.  */
9573
9574       switch (GET_CODE (op0))
9575         {
9576         case ZERO_EXTRACT:
9577           /* If we are extracting a single bit from a variable position in
9578              a constant that has only a single bit set and are comparing it
9579              with zero, we can convert this into an equality comparison
9580              between the position and the location of the single bit.  */
9581
9582           if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9583               && XEXP (op0, 1) == const1_rtx
9584               && equality_comparison_p && const_op == 0
9585               && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9586             {
9587               if (BITS_BIG_ENDIAN)
9588 #ifdef HAVE_extzv
9589                 i = (GET_MODE_BITSIZE
9590                      (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
9591 #else
9592                 i = BITS_PER_WORD - 1 - i;
9593 #endif
9594
9595               op0 = XEXP (op0, 2);
9596               op1 = GEN_INT (i);
9597               const_op = i;
9598
9599               /* Result is nonzero iff shift count is equal to I.  */
9600               code = reverse_condition (code);
9601               continue;
9602             }
9603
9604           /* ... fall through ...  */
9605
9606         case SIGN_EXTRACT:
9607           tem = expand_compound_operation (op0);
9608           if (tem != op0)
9609             {
9610               op0 = tem;
9611               continue;
9612             }
9613           break;
9614
9615         case NOT:
9616           /* If testing for equality, we can take the NOT of the constant.  */
9617           if (equality_comparison_p
9618               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9619             {
9620               op0 = XEXP (op0, 0);
9621               op1 = tem;
9622               continue;
9623             }
9624
9625           /* If just looking at the sign bit, reverse the sense of the
9626              comparison.  */
9627           if (sign_bit_comparison_p)
9628             {
9629               op0 = XEXP (op0, 0);
9630               code = (code == GE ? LT : GE);
9631               continue;
9632             }
9633           break;
9634
9635         case NEG:
9636           /* If testing for equality, we can take the NEG of the constant.  */
9637           if (equality_comparison_p
9638               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9639             {
9640               op0 = XEXP (op0, 0);
9641               op1 = tem;
9642               continue;
9643             }
9644
9645           /* The remaining cases only apply to comparisons with zero.  */
9646           if (const_op != 0)
9647             break;
9648
9649           /* When X is ABS or is known positive,
9650              (neg X) is < 0 if and only if X != 0.  */
9651
9652           if (sign_bit_comparison_p
9653               && (GET_CODE (XEXP (op0, 0)) == ABS
9654                   || (mode_width <= HOST_BITS_PER_WIDE_INT
9655                       && (nonzero_bits (XEXP (op0, 0), mode)
9656                           & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9657             {
9658               op0 = XEXP (op0, 0);
9659               code = (code == LT ? NE : EQ);
9660               continue;
9661             }
9662
9663           /* If we have NEG of something whose two high-order bits are the
9664              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
9665           if (num_sign_bit_copies (op0, mode) >= 2)
9666             {
9667               op0 = XEXP (op0, 0);
9668               code = swap_condition (code);
9669               continue;
9670             }
9671           break;
9672
9673         case ROTATE:
9674           /* If we are testing equality and our count is a constant, we
9675              can perform the inverse operation on our RHS.  */
9676           if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9677               && (tem = simplify_binary_operation (ROTATERT, mode,
9678                                                    op1, XEXP (op0, 1))) != 0)
9679             {
9680               op0 = XEXP (op0, 0);
9681               op1 = tem;
9682               continue;
9683             }
9684
9685           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9686              a particular bit.  Convert it to an AND of a constant of that
9687              bit.  This will be converted into a ZERO_EXTRACT.  */
9688           if (const_op == 0 && sign_bit_comparison_p
9689               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9690               && mode_width <= HOST_BITS_PER_WIDE_INT)
9691             {
9692               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9693                                             ((HOST_WIDE_INT) 1
9694                                              << (mode_width - 1
9695                                                  - INTVAL (XEXP (op0, 1)))));
9696               code = (code == LT ? NE : EQ);
9697               continue;
9698             }
9699
9700           /* ... fall through ...  */
9701
9702         case ABS:
9703           /* ABS is ignorable inside an equality comparison with zero.  */
9704           if (const_op == 0 && equality_comparison_p)
9705             {
9706               op0 = XEXP (op0, 0);
9707               continue;
9708             }
9709           break;
9710
9711
9712         case SIGN_EXTEND:
9713           /* Can simplify (compare (zero/sign_extend FOO) CONST)
9714              to (compare FOO CONST) if CONST fits in FOO's mode and we
9715              are either testing inequality or have an unsigned comparison
9716              with ZERO_EXTEND or a signed comparison with SIGN_EXTEND.  */
9717           if (! unsigned_comparison_p
9718               && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9719                   <= HOST_BITS_PER_WIDE_INT)
9720               && ((unsigned HOST_WIDE_INT) const_op
9721                   < (((HOST_WIDE_INT) 1
9722                       << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
9723             {
9724               op0 = XEXP (op0, 0);
9725               continue;
9726             }
9727           break;
9728
9729         case SUBREG:
9730           /* Check for the case where we are comparing A - C1 with C2,
9731              both constants are smaller than 1/2 the maximum positive
9732              value in MODE, and the comparison is equality or unsigned.
9733              In that case, if A is either zero-extended to MODE or has
9734              sufficient sign bits so that the high-order bit in MODE
9735              is a copy of the sign in the inner mode, we can prove that it is
9736              safe to do the operation in the wider mode.  This simplifies
9737              many range checks.  */
9738
9739           if (mode_width <= HOST_BITS_PER_WIDE_INT
9740               && subreg_lowpart_p (op0)
9741               && GET_CODE (SUBREG_REG (op0)) == PLUS
9742               && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
9743               && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
9744               && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
9745                   < GET_MODE_MASK (mode) / 2)
9746               && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
9747               && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
9748                                       GET_MODE (SUBREG_REG (op0)))
9749                         & ~ GET_MODE_MASK (mode))
9750                   || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
9751                                            GET_MODE (SUBREG_REG (op0)))
9752                       > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9753                          - GET_MODE_BITSIZE (mode)))))
9754             {
9755               op0 = SUBREG_REG (op0);
9756               continue;
9757             }
9758
9759           /* If the inner mode is narrower and we are extracting the low part,
9760              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
9761           if (subreg_lowpart_p (op0)
9762               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9763             /* Fall through */ ;
9764           else
9765             break;
9766
9767           /* ... fall through ...  */
9768
9769         case ZERO_EXTEND:
9770           if ((unsigned_comparison_p || equality_comparison_p)
9771               && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9772                   <= HOST_BITS_PER_WIDE_INT)
9773               && ((unsigned HOST_WIDE_INT) const_op
9774                   < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
9775             {
9776               op0 = XEXP (op0, 0);
9777               continue;
9778             }
9779           break;
9780
9781         case PLUS:
9782           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
9783              this for equality comparisons due to pathological cases involving
9784              overflows.  */
9785           if (equality_comparison_p
9786               && 0 != (tem = simplify_binary_operation (MINUS, mode,
9787                                                         op1, XEXP (op0, 1))))
9788             {
9789               op0 = XEXP (op0, 0);
9790               op1 = tem;
9791               continue;
9792             }
9793
9794           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
9795           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
9796               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
9797             {
9798               op0 = XEXP (XEXP (op0, 0), 0);
9799               code = (code == LT ? EQ : NE);
9800               continue;
9801             }
9802           break;
9803
9804         case MINUS:
9805           /* (eq (minus A B) C) -> (eq A (plus B C)) or
9806              (eq B (minus A C)), whichever simplifies.  We can only do
9807              this for equality comparisons due to pathological cases involving
9808              overflows.  */
9809           if (equality_comparison_p
9810               && 0 != (tem = simplify_binary_operation (PLUS, mode,
9811                                                         XEXP (op0, 1), op1)))
9812             {
9813               op0 = XEXP (op0, 0);
9814               op1 = tem;
9815               continue;
9816             }
9817
9818           if (equality_comparison_p
9819               && 0 != (tem = simplify_binary_operation (MINUS, mode,
9820                                                         XEXP (op0, 0), op1)))
9821             {
9822               op0 = XEXP (op0, 1);
9823               op1 = tem;
9824               continue;
9825             }
9826
9827           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
9828              of bits in X minus 1, is one iff X > 0.  */
9829           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
9830               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9831               && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
9832               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9833             {
9834               op0 = XEXP (op0, 1);
9835               code = (code == GE ? LE : GT);
9836               continue;
9837             }
9838           break;
9839
9840         case XOR:
9841           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
9842              if C is zero or B is a constant.  */
9843           if (equality_comparison_p
9844               && 0 != (tem = simplify_binary_operation (XOR, mode,
9845                                                         XEXP (op0, 1), op1)))
9846             {
9847               op0 = XEXP (op0, 0);
9848               op1 = tem;
9849               continue;
9850             }
9851           break;
9852
9853         case EQ:  case NE:
9854         case LT:  case LTU:  case LE:  case LEU:
9855         case GT:  case GTU:  case GE:  case GEU:
9856           /* We can't do anything if OP0 is a condition code value, rather
9857              than an actual data value.  */
9858           if (const_op != 0
9859 #ifdef HAVE_cc0
9860               || XEXP (op0, 0) == cc0_rtx
9861 #endif
9862               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
9863             break;
9864
9865           /* Get the two operands being compared.  */
9866           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
9867             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
9868           else
9869             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
9870
9871           /* Check for the cases where we simply want the result of the
9872              earlier test or the opposite of that result.  */
9873           if (code == NE
9874               || (code == EQ && reversible_comparison_p (op0))
9875               || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9876                   && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9877                   && (STORE_FLAG_VALUE
9878                       & (((HOST_WIDE_INT) 1
9879                           << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
9880                   && (code == LT
9881                       || (code == GE && reversible_comparison_p (op0)))))
9882             {
9883               code = (code == LT || code == NE
9884                       ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
9885               op0 = tem, op1 = tem1;
9886               continue;
9887             }
9888           break;
9889
9890         case IOR:
9891           /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
9892              iff X <= 0.  */
9893           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
9894               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
9895               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9896             {
9897               op0 = XEXP (op0, 1);
9898               code = (code == GE ? GT : LE);
9899               continue;
9900             }
9901           break;
9902
9903         case AND:
9904           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
9905              will be converted to a ZERO_EXTRACT later.  */
9906           if (const_op == 0 && equality_comparison_p
9907               && GET_CODE (XEXP (op0, 0)) == ASHIFT
9908               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
9909             {
9910               op0 = simplify_and_const_int
9911                 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
9912                                              XEXP (op0, 1),
9913                                              XEXP (XEXP (op0, 0), 1)),
9914                  (HOST_WIDE_INT) 1);
9915               continue;
9916             }
9917
9918           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
9919              zero and X is a comparison and C1 and C2 describe only bits set
9920              in STORE_FLAG_VALUE, we can compare with X.  */
9921           if (const_op == 0 && equality_comparison_p
9922               && mode_width <= HOST_BITS_PER_WIDE_INT
9923               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9924               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
9925               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9926               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
9927               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
9928             {
9929               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9930                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
9931               if ((~ STORE_FLAG_VALUE & mask) == 0
9932                   && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
9933                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
9934                           && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
9935                 {
9936                   op0 = XEXP (XEXP (op0, 0), 0);
9937                   continue;
9938                 }
9939             }
9940
9941           /* If we are doing an equality comparison of an AND of a bit equal
9942              to the sign bit, replace this with a LT or GE comparison of
9943              the underlying value.  */
9944           if (equality_comparison_p
9945               && const_op == 0
9946               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9947               && mode_width <= HOST_BITS_PER_WIDE_INT
9948               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9949                   == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9950             {
9951               op0 = XEXP (op0, 0);
9952               code = (code == EQ ? GE : LT);
9953               continue;
9954             }
9955
9956           /* If this AND operation is really a ZERO_EXTEND from a narrower
9957              mode, the constant fits within that mode, and this is either an
9958              equality or unsigned comparison, try to do this comparison in
9959              the narrower mode.  */
9960           if ((equality_comparison_p || unsigned_comparison_p)
9961               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9962               && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
9963                                    & GET_MODE_MASK (mode))
9964                                   + 1)) >= 0
9965               && const_op >> i == 0
9966               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
9967             {
9968               op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
9969               continue;
9970             }
9971           break;
9972
9973         case ASHIFT:
9974           /* If we have (compare (ashift FOO N) (const_int C)) and
9975              the high order N bits of FOO (N+1 if an inequality comparison)
9976              are known to be zero, we can do this by comparing FOO with C
9977              shifted right N bits so long as the low-order N bits of C are
9978              zero.  */
9979           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9980               && INTVAL (XEXP (op0, 1)) >= 0
9981               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
9982                   < HOST_BITS_PER_WIDE_INT)
9983               && ((const_op
9984                    & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
9985               && mode_width <= HOST_BITS_PER_WIDE_INT
9986               && (nonzero_bits (XEXP (op0, 0), mode)
9987                   & ~ (mask >> (INTVAL (XEXP (op0, 1))
9988                                 + ! equality_comparison_p))) == 0)
9989             {
9990               const_op >>= INTVAL (XEXP (op0, 1));
9991               op1 = GEN_INT (const_op);
9992               op0 = XEXP (op0, 0);
9993               continue;
9994             }
9995
9996           /* If we are doing a sign bit comparison, it means we are testing
9997              a particular bit.  Convert it to the appropriate AND.  */
9998           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9999               && mode_width <= HOST_BITS_PER_WIDE_INT)
10000             {
10001               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10002                                             ((HOST_WIDE_INT) 1
10003                                              << (mode_width - 1
10004                                                  - INTVAL (XEXP (op0, 1)))));
10005               code = (code == LT ? NE : EQ);
10006               continue;
10007             }
10008
10009           /* If this an equality comparison with zero and we are shifting
10010              the low bit to the sign bit, we can convert this to an AND of the
10011              low-order bit.  */
10012           if (const_op == 0 && equality_comparison_p
10013               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10014               && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10015             {
10016               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10017                                             (HOST_WIDE_INT) 1);
10018               continue;
10019             }
10020           break;
10021
10022         case ASHIFTRT:
10023           /* If this is an equality comparison with zero, we can do this
10024              as a logical shift, which might be much simpler.  */
10025           if (equality_comparison_p && const_op == 0
10026               && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10027             {
10028               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10029                                           XEXP (op0, 0),
10030                                           INTVAL (XEXP (op0, 1)));
10031               continue;
10032             }
10033
10034           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10035              do the comparison in a narrower mode.  */
10036           if (! unsigned_comparison_p
10037               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10038               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10039               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10040               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10041                                          MODE_INT, 1)) != BLKmode
10042               && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10043                   || ((unsigned HOST_WIDE_INT) - const_op
10044                       <= GET_MODE_MASK (tmode))))
10045             {
10046               op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10047               continue;
10048             }
10049
10050           /* ... fall through ...  */
10051         case LSHIFTRT:
10052           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10053              the low order N bits of FOO are known to be zero, we can do this
10054              by comparing FOO with C shifted left N bits so long as no
10055              overflow occurs.  */
10056           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10057               && INTVAL (XEXP (op0, 1)) >= 0
10058               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10059               && mode_width <= HOST_BITS_PER_WIDE_INT
10060               && (nonzero_bits (XEXP (op0, 0), mode)
10061                   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10062               && (const_op == 0
10063                   || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10064                       < mode_width)))
10065             {
10066               const_op <<= INTVAL (XEXP (op0, 1));
10067               op1 = GEN_INT (const_op);
10068               op0 = XEXP (op0, 0);
10069               continue;
10070             }
10071
10072           /* If we are using this shift to extract just the sign bit, we
10073              can replace this with an LT or GE comparison.  */
10074           if (const_op == 0
10075               && (equality_comparison_p || sign_bit_comparison_p)
10076               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10077               && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10078             {
10079               op0 = XEXP (op0, 0);
10080               code = (code == NE || code == GT ? LT : GE);
10081               continue;
10082             }
10083           break;
10084
10085         default:
10086           break;
10087         }
10088
10089       break;
10090     }
10091
10092   /* Now make any compound operations involved in this comparison.  Then,
10093      check for an outmost SUBREG on OP0 that isn't doing anything or is
10094      paradoxical.  The latter case can only occur when it is known that the
10095      "extra" bits will be zero.  Therefore, it is safe to remove the SUBREG.
10096      We can never remove a SUBREG for a non-equality comparison because the
10097      sign bit is in a different place in the underlying object.  */
10098
10099   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10100   op1 = make_compound_operation (op1, SET);
10101
10102   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10103       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10104       && (code == NE || code == EQ)
10105       && ((GET_MODE_SIZE (GET_MODE (op0))
10106            > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10107     {
10108       op0 = SUBREG_REG (op0);
10109       op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10110     }
10111
10112   else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10113            && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10114            && (code == NE || code == EQ)
10115            && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10116                <= HOST_BITS_PER_WIDE_INT)
10117            && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10118                & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10119            && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10120                                               op1),
10121                (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10122                 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10123     op0 = SUBREG_REG (op0), op1 = tem;
10124
10125   /* We now do the opposite procedure: Some machines don't have compare
10126      insns in all modes.  If OP0's mode is an integer mode smaller than a
10127      word and we can't do a compare in that mode, see if there is a larger
10128      mode for which we can do the compare.  There are a number of cases in
10129      which we can use the wider mode.  */
10130
10131   mode = GET_MODE (op0);
10132   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10133       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10134       && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10135     for (tmode = GET_MODE_WIDER_MODE (mode);
10136          (tmode != VOIDmode
10137           && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10138          tmode = GET_MODE_WIDER_MODE (tmode))
10139       if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10140         {
10141           /* If the only nonzero bits in OP0 and OP1 are those in the
10142              narrower mode and this is an equality or unsigned comparison,
10143              we can use the wider mode.  Similarly for sign-extended
10144              values, in which case it is true for all comparisons.  */
10145           if (((code == EQ || code == NE
10146                 || code == GEU || code == GTU || code == LEU || code == LTU)
10147                && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10148                && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
10149               || ((num_sign_bit_copies (op0, tmode)
10150                    > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10151                   && (num_sign_bit_copies (op1, tmode)
10152                       > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10153             {
10154               op0 = gen_lowpart_for_combine (tmode, op0);
10155               op1 = gen_lowpart_for_combine (tmode, op1);
10156               break;
10157             }
10158
10159           /* If this is a test for negative, we can make an explicit
10160              test of the sign bit.  */
10161
10162           if (op1 == const0_rtx && (code == LT || code == GE)
10163               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10164             {
10165               op0 = gen_binary (AND, tmode,
10166                                 gen_lowpart_for_combine (tmode, op0),
10167                                 GEN_INT ((HOST_WIDE_INT) 1
10168                                          << (GET_MODE_BITSIZE (mode) - 1)));
10169               code = (code == LT) ? NE : EQ;
10170               break;
10171             }
10172         }
10173
10174 #ifdef CANONICALIZE_COMPARISON
10175   /* If this machine only supports a subset of valid comparisons, see if we
10176      can convert an unsupported one into a supported one.  */
10177   CANONICALIZE_COMPARISON (code, op0, op1);
10178 #endif
10179
10180   *pop0 = op0;
10181   *pop1 = op1;
10182
10183   return code;
10184 }
10185 \f
10186 /* Return 1 if we know that X, a comparison operation, is not operating
10187    on a floating-point value or is EQ or NE, meaning that we can safely
10188    reverse it.  */
10189
10190 static int
10191 reversible_comparison_p (x)
10192      rtx x;
10193 {
10194   if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
10195       || flag_fast_math
10196       || GET_CODE (x) == NE || GET_CODE (x) == EQ)
10197     return 1;
10198
10199   switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10200     {
10201     case MODE_INT:
10202     case MODE_PARTIAL_INT:
10203     case MODE_COMPLEX_INT:
10204       return 1;
10205
10206     case MODE_CC:
10207       /* If the mode of the condition codes tells us that this is safe,
10208          we need look no further.  */
10209       if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10210         return 1;
10211
10212       /* Otherwise try and find where the condition codes were last set and
10213          use that.  */
10214       x = get_last_value (XEXP (x, 0));
10215       return (x && GET_CODE (x) == COMPARE
10216               && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10217
10218     default:
10219       return 0;
10220     }
10221 }
10222 \f
10223 /* Utility function for following routine.  Called when X is part of a value
10224    being stored into reg_last_set_value.  Sets reg_last_set_table_tick
10225    for each register mentioned.  Similar to mention_regs in cse.c  */
10226
10227 static void
10228 update_table_tick (x)
10229      rtx x;
10230 {
10231   register enum rtx_code code = GET_CODE (x);
10232   register char *fmt = GET_RTX_FORMAT (code);
10233   register int i;
10234
10235   if (code == REG)
10236     {
10237       int regno = REGNO (x);
10238       int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10239                               ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10240
10241       for (i = regno; i < endregno; i++)
10242         reg_last_set_table_tick[i] = label_tick;
10243
10244       return;
10245     }
10246
10247   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10248     /* Note that we can't have an "E" in values stored; see
10249        get_last_value_validate.  */
10250     if (fmt[i] == 'e')
10251       update_table_tick (XEXP (x, i));
10252 }
10253
10254 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
10255    are saying that the register is clobbered and we no longer know its
10256    value.  If INSN is zero, don't update reg_last_set; this is only permitted
10257    with VALUE also zero and is used to invalidate the register.  */
10258
10259 static void
10260 record_value_for_reg (reg, insn, value)
10261      rtx reg;
10262      rtx insn;
10263      rtx value;
10264 {
10265   int regno = REGNO (reg);
10266   int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10267                           ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10268   int i;
10269
10270   /* If VALUE contains REG and we have a previous value for REG, substitute
10271      the previous value.  */
10272   if (value && insn && reg_overlap_mentioned_p (reg, value))
10273     {
10274       rtx tem;
10275
10276       /* Set things up so get_last_value is allowed to see anything set up to
10277          our insn.  */
10278       subst_low_cuid = INSN_CUID (insn);
10279       tem = get_last_value (reg);
10280
10281       if (tem)
10282         value = replace_rtx (copy_rtx (value), reg, tem);
10283     }
10284
10285   /* For each register modified, show we don't know its value, that
10286      we don't know about its bitwise content, that its value has been
10287      updated, and that we don't know the location of the death of the
10288      register.  */
10289   for (i = regno; i < endregno; i ++)
10290     {
10291       if (insn)
10292         reg_last_set[i] = insn;
10293       reg_last_set_value[i] = 0;
10294       reg_last_set_mode[i] = 0;
10295       reg_last_set_nonzero_bits[i] = 0;
10296       reg_last_set_sign_bit_copies[i] = 0;
10297       reg_last_death[i] = 0;
10298     }
10299
10300   /* Mark registers that are being referenced in this value.  */
10301   if (value)
10302     update_table_tick (value);
10303
10304   /* Now update the status of each register being set.
10305      If someone is using this register in this block, set this register
10306      to invalid since we will get confused between the two lives in this
10307      basic block.  This makes using this register always invalid.  In cse, we
10308      scan the table to invalidate all entries using this register, but this
10309      is too much work for us.  */
10310
10311   for (i = regno; i < endregno; i++)
10312     {
10313       reg_last_set_label[i] = label_tick;
10314       if (value && reg_last_set_table_tick[i] == label_tick)
10315         reg_last_set_invalid[i] = 1;
10316       else
10317         reg_last_set_invalid[i] = 0;
10318     }
10319
10320   /* The value being assigned might refer to X (like in "x++;").  In that
10321      case, we must replace it with (clobber (const_int 0)) to prevent
10322      infinite loops.  */
10323   if (value && ! get_last_value_validate (&value, insn,
10324                                           reg_last_set_label[regno], 0))
10325     {
10326       value = copy_rtx (value);
10327       if (! get_last_value_validate (&value, insn,
10328                                      reg_last_set_label[regno], 1))
10329         value = 0;
10330     }
10331
10332   /* For the main register being modified, update the value, the mode, the
10333      nonzero bits, and the number of sign bit copies.  */
10334
10335   reg_last_set_value[regno] = value;
10336
10337   if (value)
10338     {
10339       subst_low_cuid = INSN_CUID (insn);
10340       reg_last_set_mode[regno] = GET_MODE (reg);
10341       reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10342       reg_last_set_sign_bit_copies[regno]
10343         = num_sign_bit_copies (value, GET_MODE (reg));
10344     }
10345 }
10346
10347 /* Used for communication between the following two routines.  */
10348 static rtx record_dead_insn;
10349
10350 /* Called via note_stores from record_dead_and_set_regs to handle one
10351    SET or CLOBBER in an insn.  */
10352
10353 static void
10354 record_dead_and_set_regs_1 (dest, setter)
10355      rtx dest, setter;
10356 {
10357   if (GET_CODE (dest) == SUBREG)
10358     dest = SUBREG_REG (dest);
10359
10360   if (GET_CODE (dest) == REG)
10361     {
10362       /* If we are setting the whole register, we know its value.  Otherwise
10363          show that we don't know the value.  We can handle SUBREG in
10364          some cases.  */
10365       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10366         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10367       else if (GET_CODE (setter) == SET
10368                && GET_CODE (SET_DEST (setter)) == SUBREG
10369                && SUBREG_REG (SET_DEST (setter)) == dest
10370                && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10371                && subreg_lowpart_p (SET_DEST (setter)))
10372         record_value_for_reg (dest, record_dead_insn,
10373                               gen_lowpart_for_combine (GET_MODE (dest),
10374                                                        SET_SRC (setter)));
10375       else
10376         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10377     }
10378   else if (GET_CODE (dest) == MEM
10379            /* Ignore pushes, they clobber nothing.  */
10380            && ! push_operand (dest, GET_MODE (dest)))
10381     mem_last_set = INSN_CUID (record_dead_insn);
10382 }
10383
10384 /* Update the records of when each REG was most recently set or killed
10385    for the things done by INSN.  This is the last thing done in processing
10386    INSN in the combiner loop.
10387
10388    We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10389    reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10390    and also the similar information mem_last_set (which insn most recently
10391    modified memory) and last_call_cuid (which insn was the most recent
10392    subroutine call).  */
10393
10394 static void
10395 record_dead_and_set_regs (insn)
10396      rtx insn;
10397 {
10398   register rtx link;
10399   int i;
10400
10401   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10402     {
10403       if (REG_NOTE_KIND (link) == REG_DEAD
10404           && GET_CODE (XEXP (link, 0)) == REG)
10405         {
10406           int regno = REGNO (XEXP (link, 0));
10407           int endregno
10408             = regno + (regno < FIRST_PSEUDO_REGISTER
10409                        ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10410                        : 1);
10411
10412           for (i = regno; i < endregno; i++)
10413             reg_last_death[i] = insn;
10414         }
10415       else if (REG_NOTE_KIND (link) == REG_INC)
10416         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10417     }
10418
10419   if (GET_CODE (insn) == CALL_INSN)
10420     {
10421       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10422         if (call_used_regs[i])
10423           {
10424             reg_last_set_value[i] = 0;
10425             reg_last_set_mode[i] = 0;
10426             reg_last_set_nonzero_bits[i] = 0;
10427             reg_last_set_sign_bit_copies[i] = 0;
10428             reg_last_death[i] = 0;
10429           }
10430
10431       last_call_cuid = mem_last_set = INSN_CUID (insn);
10432     }
10433
10434   record_dead_insn = insn;
10435   note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10436 }
10437 \f
10438 /* Utility routine for the following function.  Verify that all the registers
10439    mentioned in *LOC are valid when *LOC was part of a value set when
10440    label_tick == TICK.  Return 0 if some are not.
10441
10442    If REPLACE is non-zero, replace the invalid reference with
10443    (clobber (const_int 0)) and return 1.  This replacement is useful because
10444    we often can get useful information about the form of a value (e.g., if
10445    it was produced by a shift that always produces -1 or 0) even though
10446    we don't know exactly what registers it was produced from.  */
10447
10448 static int
10449 get_last_value_validate (loc, insn, tick, replace)
10450      rtx *loc;
10451      rtx insn;
10452      int tick;
10453      int replace;
10454 {
10455   rtx x = *loc;
10456   char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10457   int len = GET_RTX_LENGTH (GET_CODE (x));
10458   int i;
10459
10460   if (GET_CODE (x) == REG)
10461     {
10462       int regno = REGNO (x);
10463       int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10464                               ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10465       int j;
10466
10467       for (j = regno; j < endregno; j++)
10468         if (reg_last_set_invalid[j]
10469             /* If this is a pseudo-register that was only set once, it is
10470                always valid.  */
10471             || (! (regno >= FIRST_PSEUDO_REGISTER && REG_N_SETS (regno) == 1)
10472                 && reg_last_set_label[j] > tick))
10473           {
10474             if (replace)
10475               *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
10476             return replace;
10477           }
10478
10479       return 1;
10480     }
10481   /* If this is a memory reference, make sure that there were
10482      no stores after it that might have clobbered the value.  We don't
10483      have alias info, so we assume any store invalidates it.  */
10484   else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
10485            && INSN_CUID (insn) <= mem_last_set)
10486     {
10487       if (replace)
10488         *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
10489       return replace;
10490     }
10491
10492   for (i = 0; i < len; i++)
10493     if ((fmt[i] == 'e'
10494          && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
10495         /* Don't bother with these.  They shouldn't occur anyway.  */
10496         || fmt[i] == 'E')
10497       return 0;
10498
10499   /* If we haven't found a reason for it to be invalid, it is valid.  */
10500   return 1;
10501 }
10502
10503 /* Get the last value assigned to X, if known.  Some registers
10504    in the value may be replaced with (clobber (const_int 0)) if their value
10505    is known longer known reliably.  */
10506
10507 static rtx
10508 get_last_value (x)
10509      rtx x;
10510 {
10511   int regno;
10512   rtx value;
10513
10514   /* If this is a non-paradoxical SUBREG, get the value of its operand and
10515      then convert it to the desired mode.  If this is a paradoxical SUBREG,
10516      we cannot predict what values the "extra" bits might have.  */
10517   if (GET_CODE (x) == SUBREG
10518       && subreg_lowpart_p (x)
10519       && (GET_MODE_SIZE (GET_MODE (x))
10520           <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10521       && (value = get_last_value (SUBREG_REG (x))) != 0)
10522     return gen_lowpart_for_combine (GET_MODE (x), value);
10523
10524   if (GET_CODE (x) != REG)
10525     return 0;
10526
10527   regno = REGNO (x);
10528   value = reg_last_set_value[regno];
10529
10530   /* If we don't have a value or if it isn't for this basic block,
10531      return 0.  */
10532
10533   if (value == 0
10534       || (REG_N_SETS (regno) != 1
10535           && reg_last_set_label[regno] != label_tick))
10536     return 0;
10537
10538   /* If the value was set in a later insn than the ones we are processing,
10539      we can't use it even if the register was only set once, but make a quick
10540      check to see if the previous insn set it to something.  This is commonly
10541      the case when the same pseudo is used by repeated insns.
10542
10543      This does not work if there exists an instruction which is temporarily
10544      not on the insn chain.  */
10545
10546   if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
10547     {
10548       rtx insn, set;
10549
10550       /* We can not do anything useful in this case, because there is
10551          an instruction which is not on the insn chain.  */
10552       if (subst_prev_insn)
10553         return 0;
10554
10555       /* Skip over USE insns.  They are not useful here, and they may have
10556          been made by combine, in which case they do not have a INSN_CUID
10557          value.  We can't use prev_real_insn, because that would incorrectly
10558          take us backwards across labels.  Skip over BARRIERs also, since
10559          they could have been made by combine.  If we see one, we must be
10560          optimizing dead code, so it doesn't matter what we do.  */
10561       for (insn = prev_nonnote_insn (subst_insn);
10562            insn && ((GET_CODE (insn) == INSN
10563                      && GET_CODE (PATTERN (insn)) == USE)
10564                     || GET_CODE (insn) == BARRIER
10565                     || INSN_CUID (insn) >= subst_low_cuid);
10566            insn = prev_nonnote_insn (insn))
10567         ;
10568
10569       if (insn
10570           && (set = single_set (insn)) != 0
10571           && rtx_equal_p (SET_DEST (set), x))
10572         {
10573           value = SET_SRC (set);
10574
10575           /* Make sure that VALUE doesn't reference X.  Replace any
10576              explicit references with a CLOBBER.  If there are any remaining
10577              references (rare), don't use the value.  */
10578
10579           if (reg_mentioned_p (x, value))
10580             value = replace_rtx (copy_rtx (value), x,
10581                                  gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
10582
10583           if (reg_overlap_mentioned_p (x, value))
10584             return 0;
10585         }
10586       else
10587         return 0;
10588     }
10589
10590   /* If the value has all its registers valid, return it.  */
10591   if (get_last_value_validate (&value, reg_last_set[regno],
10592                                reg_last_set_label[regno], 0))
10593     return value;
10594
10595   /* Otherwise, make a copy and replace any invalid register with
10596      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
10597
10598   value = copy_rtx (value);
10599   if (get_last_value_validate (&value, reg_last_set[regno],
10600                                reg_last_set_label[regno], 1))
10601     return value;
10602
10603   return 0;
10604 }
10605 \f
10606 /* Return nonzero if expression X refers to a REG or to memory
10607    that is set in an instruction more recent than FROM_CUID.  */
10608
10609 static int
10610 use_crosses_set_p (x, from_cuid)
10611      register rtx x;
10612      int from_cuid;
10613 {
10614   register char *fmt;
10615   register int i;
10616   register enum rtx_code code = GET_CODE (x);
10617
10618   if (code == REG)
10619     {
10620       register int regno = REGNO (x);
10621       int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10622                             ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10623
10624 #ifdef PUSH_ROUNDING
10625       /* Don't allow uses of the stack pointer to be moved,
10626          because we don't know whether the move crosses a push insn.  */
10627       if (regno == STACK_POINTER_REGNUM)
10628         return 1;
10629 #endif
10630       for (;regno < endreg; regno++)
10631         if (reg_last_set[regno]
10632             && INSN_CUID (reg_last_set[regno]) > from_cuid)
10633           return 1;
10634       return 0;
10635     }
10636
10637   if (code == MEM && mem_last_set > from_cuid)
10638     return 1;
10639
10640   fmt = GET_RTX_FORMAT (code);
10641
10642   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10643     {
10644       if (fmt[i] == 'E')
10645         {
10646           register int j;
10647           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10648             if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
10649               return 1;
10650         }
10651       else if (fmt[i] == 'e'
10652                && use_crosses_set_p (XEXP (x, i), from_cuid))
10653         return 1;
10654     }
10655   return 0;
10656 }
10657 \f
10658 /* Define three variables used for communication between the following
10659    routines.  */
10660
10661 static int reg_dead_regno, reg_dead_endregno;
10662 static int reg_dead_flag;
10663
10664 /* Function called via note_stores from reg_dead_at_p.
10665
10666    If DEST is within [reg_dead_regno, reg_dead_endregno), set
10667    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
10668
10669 static void
10670 reg_dead_at_p_1 (dest, x)
10671      rtx dest;
10672      rtx x;
10673 {
10674   int regno, endregno;
10675
10676   if (GET_CODE (dest) != REG)
10677     return;
10678
10679   regno = REGNO (dest);
10680   endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10681                       ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
10682
10683   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
10684     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
10685 }
10686
10687 /* Return non-zero if REG is known to be dead at INSN.
10688
10689    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
10690    referencing REG, it is dead.  If we hit a SET referencing REG, it is
10691    live.  Otherwise, see if it is live or dead at the start of the basic
10692    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
10693    must be assumed to be always live.  */
10694
10695 static int
10696 reg_dead_at_p (reg, insn)
10697      rtx reg;
10698      rtx insn;
10699 {
10700   int block, i;
10701
10702   /* Set variables for reg_dead_at_p_1.  */
10703   reg_dead_regno = REGNO (reg);
10704   reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
10705                                         ? HARD_REGNO_NREGS (reg_dead_regno,
10706                                                             GET_MODE (reg))
10707                                         : 1);
10708
10709   reg_dead_flag = 0;
10710
10711   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  */
10712   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
10713     {
10714       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10715         if (TEST_HARD_REG_BIT (newpat_used_regs, i))
10716           return 0;
10717     }
10718
10719   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
10720      beginning of function.  */
10721   for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
10722        insn = prev_nonnote_insn (insn))
10723     {
10724       note_stores (PATTERN (insn), reg_dead_at_p_1);
10725       if (reg_dead_flag)
10726         return reg_dead_flag == 1 ? 1 : 0;
10727
10728       if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
10729         return 1;
10730     }
10731
10732   /* Get the basic block number that we were in.  */
10733   if (insn == 0)
10734     block = 0;
10735   else
10736     {
10737       for (block = 0; block < n_basic_blocks; block++)
10738         if (insn == basic_block_head[block])
10739           break;
10740
10741       if (block == n_basic_blocks)
10742         return 0;
10743     }
10744
10745   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10746     if (REGNO_REG_SET_P (basic_block_live_at_start[block], i))
10747       return 0;
10748
10749   return 1;
10750 }
10751 \f
10752 /* Note hard registers in X that are used.  This code is similar to
10753    that in flow.c, but much simpler since we don't care about pseudos.  */
10754
10755 static void
10756 mark_used_regs_combine (x)
10757      rtx x;
10758 {
10759   register RTX_CODE code = GET_CODE (x);
10760   register int regno;
10761   int i;
10762
10763   switch (code)
10764     {
10765     case LABEL_REF:
10766     case SYMBOL_REF:
10767     case CONST_INT:
10768     case CONST:
10769     case CONST_DOUBLE:
10770     case PC:
10771     case ADDR_VEC:
10772     case ADDR_DIFF_VEC:
10773     case ASM_INPUT:
10774 #ifdef HAVE_cc0
10775     /* CC0 must die in the insn after it is set, so we don't need to take
10776        special note of it here.  */
10777     case CC0:
10778 #endif
10779       return;
10780
10781     case CLOBBER:
10782       /* If we are clobbering a MEM, mark any hard registers inside the
10783          address as used.  */
10784       if (GET_CODE (XEXP (x, 0)) == MEM)
10785         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
10786       return;
10787
10788     case REG:
10789       regno = REGNO (x);
10790       /* A hard reg in a wide mode may really be multiple registers.
10791          If so, mark all of them just like the first.  */
10792       if (regno < FIRST_PSEUDO_REGISTER)
10793         {
10794           /* None of this applies to the stack, frame or arg pointers */
10795           if (regno == STACK_POINTER_REGNUM
10796 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
10797               || regno == HARD_FRAME_POINTER_REGNUM
10798 #endif
10799 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
10800               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
10801 #endif
10802               || regno == FRAME_POINTER_REGNUM)
10803             return;
10804
10805           i = HARD_REGNO_NREGS (regno, GET_MODE (x));
10806           while (i-- > 0)
10807             SET_HARD_REG_BIT (newpat_used_regs, regno + i);
10808         }
10809       return;
10810
10811     case SET:
10812       {
10813         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
10814            the address.  */
10815         register rtx testreg = SET_DEST (x);
10816
10817         while (GET_CODE (testreg) == SUBREG
10818                || GET_CODE (testreg) == ZERO_EXTRACT
10819                || GET_CODE (testreg) == SIGN_EXTRACT
10820                || GET_CODE (testreg) == STRICT_LOW_PART)
10821           testreg = XEXP (testreg, 0);
10822
10823         if (GET_CODE (testreg) == MEM)
10824           mark_used_regs_combine (XEXP (testreg, 0));
10825
10826         mark_used_regs_combine (SET_SRC (x));
10827       }
10828       return;
10829
10830     default:
10831       break;
10832     }
10833
10834   /* Recursively scan the operands of this expression.  */
10835
10836   {
10837     register char *fmt = GET_RTX_FORMAT (code);
10838
10839     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10840       {
10841         if (fmt[i] == 'e')
10842           mark_used_regs_combine (XEXP (x, i));
10843         else if (fmt[i] == 'E')
10844           {
10845             register int j;
10846
10847             for (j = 0; j < XVECLEN (x, i); j++)
10848               mark_used_regs_combine (XVECEXP (x, i, j));
10849           }
10850       }
10851   }
10852 }
10853
10854 \f
10855 /* Remove register number REGNO from the dead registers list of INSN.
10856
10857    Return the note used to record the death, if there was one.  */
10858
10859 rtx
10860 remove_death (regno, insn)
10861      int regno;
10862      rtx insn;
10863 {
10864   register rtx note = find_regno_note (insn, REG_DEAD, regno);
10865
10866   if (note)
10867     {
10868       REG_N_DEATHS (regno)--;
10869       remove_note (insn, note);
10870     }
10871
10872   return note;
10873 }
10874
10875 /* For each register (hardware or pseudo) used within expression X, if its
10876    death is in an instruction with cuid between FROM_CUID (inclusive) and
10877    TO_INSN (exclusive), put a REG_DEAD note for that register in the
10878    list headed by PNOTES.
10879
10880    That said, don't move registers killed by maybe_kill_insn.
10881
10882    This is done when X is being merged by combination into TO_INSN.  These
10883    notes will then be distributed as needed.  */
10884
10885 static void
10886 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
10887      rtx x;
10888      rtx maybe_kill_insn;
10889      int from_cuid;
10890      rtx to_insn;
10891      rtx *pnotes;
10892 {
10893   register char *fmt;
10894   register int len, i;
10895   register enum rtx_code code = GET_CODE (x);
10896
10897   if (code == REG)
10898     {
10899       register int regno = REGNO (x);
10900       register rtx where_dead = reg_last_death[regno];
10901       register rtx before_dead, after_dead;
10902
10903       /* Don't move the register if it gets killed in between from and to */
10904       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
10905           && !reg_referenced_p (x, maybe_kill_insn))
10906         return;
10907
10908       /* WHERE_DEAD could be a USE insn made by combine, so first we
10909          make sure that we have insns with valid INSN_CUID values.  */
10910       before_dead = where_dead;
10911       while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
10912         before_dead = PREV_INSN (before_dead);
10913       after_dead = where_dead;
10914       while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
10915         after_dead = NEXT_INSN (after_dead);
10916
10917       if (before_dead && after_dead
10918           && INSN_CUID (before_dead) >= from_cuid
10919           && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
10920               || (where_dead != after_dead
10921                   && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
10922         {
10923           rtx note = remove_death (regno, where_dead);
10924
10925           /* It is possible for the call above to return 0.  This can occur
10926              when reg_last_death points to I2 or I1 that we combined with.
10927              In that case make a new note.
10928
10929              We must also check for the case where X is a hard register
10930              and NOTE is a death note for a range of hard registers
10931              including X.  In that case, we must put REG_DEAD notes for
10932              the remaining registers in place of NOTE.  */
10933
10934           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
10935               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
10936                   > GET_MODE_SIZE (GET_MODE (x))))
10937             {
10938               int deadregno = REGNO (XEXP (note, 0));
10939               int deadend
10940                 = (deadregno + HARD_REGNO_NREGS (deadregno,
10941                                                  GET_MODE (XEXP (note, 0))));
10942               int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10943               int i;
10944
10945               for (i = deadregno; i < deadend; i++)
10946                 if (i < regno || i >= ourend)
10947                   REG_NOTES (where_dead)
10948                     = gen_rtx (EXPR_LIST, REG_DEAD,
10949                                gen_rtx (REG, reg_raw_mode[i], i),
10950                                REG_NOTES (where_dead));
10951             }
10952           /* If we didn't find any note, or if we found a REG_DEAD note that
10953              covers only part of the given reg, and we have a multi-reg hard
10954              register, then to be safe we must check for REG_DEAD notes
10955              for each register other than the first.  They could have
10956              their own REG_DEAD notes lying around.  */
10957           else if ((note == 0
10958                     || (note != 0
10959                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
10960                             < GET_MODE_SIZE (GET_MODE (x)))))
10961                    && regno < FIRST_PSEUDO_REGISTER
10962                    && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
10963             {
10964               int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10965               int i, offset;
10966               rtx oldnotes = 0;
10967
10968               if (note)
10969                 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
10970               else
10971                 offset = 1;
10972
10973               for (i = regno + offset; i < ourend; i++)
10974                 move_deaths (gen_rtx (REG, reg_raw_mode[i], i),
10975                              maybe_kill_insn, from_cuid, to_insn, &oldnotes);
10976             }
10977
10978           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
10979             {
10980               XEXP (note, 1) = *pnotes;
10981               *pnotes = note;
10982             }
10983           else
10984             *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
10985
10986           REG_N_DEATHS (regno)++;
10987         }
10988
10989       return;
10990     }
10991
10992   else if (GET_CODE (x) == SET)
10993     {
10994       rtx dest = SET_DEST (x);
10995
10996       move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
10997
10998       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
10999          that accesses one word of a multi-word item, some
11000          piece of everything register in the expression is used by
11001          this insn, so remove any old death.  */
11002
11003       if (GET_CODE (dest) == ZERO_EXTRACT
11004           || GET_CODE (dest) == STRICT_LOW_PART
11005           || (GET_CODE (dest) == SUBREG
11006               && (((GET_MODE_SIZE (GET_MODE (dest))
11007                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11008                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11009                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11010         {
11011           move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11012           return;
11013         }
11014
11015       /* If this is some other SUBREG, we know it replaces the entire
11016          value, so use that as the destination.  */
11017       if (GET_CODE (dest) == SUBREG)
11018         dest = SUBREG_REG (dest);
11019
11020       /* If this is a MEM, adjust deaths of anything used in the address.
11021          For a REG (the only other possibility), the entire value is
11022          being replaced so the old value is not used in this insn.  */
11023
11024       if (GET_CODE (dest) == MEM)
11025         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11026                      to_insn, pnotes);
11027       return;
11028     }
11029
11030   else if (GET_CODE (x) == CLOBBER)
11031     return;
11032
11033   len = GET_RTX_LENGTH (code);
11034   fmt = GET_RTX_FORMAT (code);
11035
11036   for (i = 0; i < len; i++)
11037     {
11038       if (fmt[i] == 'E')
11039         {
11040           register int j;
11041           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11042             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11043                          to_insn, pnotes);
11044         }
11045       else if (fmt[i] == 'e')
11046         move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11047     }
11048 }
11049 \f
11050 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11051    pattern of an insn.  X must be a REG.  */
11052
11053 static int
11054 reg_bitfield_target_p (x, body)
11055      rtx x;
11056      rtx body;
11057 {
11058   int i;
11059
11060   if (GET_CODE (body) == SET)
11061     {
11062       rtx dest = SET_DEST (body);
11063       rtx target;
11064       int regno, tregno, endregno, endtregno;
11065
11066       if (GET_CODE (dest) == ZERO_EXTRACT)
11067         target = XEXP (dest, 0);
11068       else if (GET_CODE (dest) == STRICT_LOW_PART)
11069         target = SUBREG_REG (XEXP (dest, 0));
11070       else
11071         return 0;
11072
11073       if (GET_CODE (target) == SUBREG)
11074         target = SUBREG_REG (target);
11075
11076       if (GET_CODE (target) != REG)
11077         return 0;
11078
11079       tregno = REGNO (target), regno = REGNO (x);
11080       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11081         return target == x;
11082
11083       endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11084       endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11085
11086       return endregno > tregno && regno < endtregno;
11087     }
11088
11089   else if (GET_CODE (body) == PARALLEL)
11090     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11091       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11092         return 1;
11093
11094   return 0;
11095 }
11096 \f
11097 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11098    as appropriate.  I3 and I2 are the insns resulting from the combination
11099    insns including FROM (I2 may be zero).
11100
11101    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11102    not need REG_DEAD notes because they are being substituted for.  This
11103    saves searching in the most common cases.
11104
11105    Each note in the list is either ignored or placed on some insns, depending
11106    on the type of note.  */
11107
11108 static void
11109 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11110      rtx notes;
11111      rtx from_insn;
11112      rtx i3, i2;
11113      rtx elim_i2, elim_i1;
11114 {
11115   rtx note, next_note;
11116   rtx tem;
11117
11118   for (note = notes; note; note = next_note)
11119     {
11120       rtx place = 0, place2 = 0;
11121
11122       /* If this NOTE references a pseudo register, ensure it references
11123          the latest copy of that register.  */
11124       if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11125           && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11126         XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11127
11128       next_note = XEXP (note, 1);
11129       switch (REG_NOTE_KIND (note))
11130         {
11131         case REG_BR_PROB:
11132         case REG_EXEC_COUNT:
11133           /* Doesn't matter much where we put this, as long as it's somewhere.
11134              It is preferable to keep these notes on branches, which is most
11135              likely to be i3.  */
11136           place = i3;
11137           break;
11138
11139         case REG_UNUSED:
11140           /* Any clobbers for i3 may still exist, and so we must process
11141              REG_UNUSED notes from that insn.
11142
11143              Any clobbers from i2 or i1 can only exist if they were added by
11144              recog_for_combine.  In that case, recog_for_combine created the
11145              necessary REG_UNUSED notes.  Trying to keep any original
11146              REG_UNUSED notes from these insns can cause incorrect output
11147              if it is for the same register as the original i3 dest.
11148              In that case, we will notice that the register is set in i3,
11149              and then add a REG_UNUSED note for the destination of i3, which
11150              is wrong.  However, it is possible to have REG_UNUSED notes from
11151              i2 or i1 for register which were both used and clobbered, so
11152              we keep notes from i2 or i1 if they will turn into REG_DEAD
11153              notes.  */
11154
11155           /* If this register is set or clobbered in I3, put the note there
11156              unless there is one already.  */
11157           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11158             {
11159               if (from_insn != i3)
11160                 break;
11161
11162               if (! (GET_CODE (XEXP (note, 0)) == REG
11163                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11164                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11165                 place = i3;
11166             }
11167           /* Otherwise, if this register is used by I3, then this register
11168              now dies here, so we must put a REG_DEAD note here unless there
11169              is one already.  */
11170           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11171                    && ! (GET_CODE (XEXP (note, 0)) == REG
11172                          ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
11173                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11174             {
11175               PUT_REG_NOTE_KIND (note, REG_DEAD);
11176               place = i3;
11177             }
11178           break;
11179
11180         case REG_EQUAL:
11181         case REG_EQUIV:
11182         case REG_NONNEG:
11183           /* These notes say something about results of an insn.  We can
11184              only support them if they used to be on I3 in which case they
11185              remain on I3.  Otherwise they are ignored.
11186
11187              If the note refers to an expression that is not a constant, we
11188              must also ignore the note since we cannot tell whether the
11189              equivalence is still true.  It might be possible to do
11190              slightly better than this (we only have a problem if I2DEST
11191              or I1DEST is present in the expression), but it doesn't
11192              seem worth the trouble.  */
11193
11194           if (from_insn == i3
11195               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11196             place = i3;
11197           break;
11198
11199         case REG_INC:
11200         case REG_NO_CONFLICT:
11201         case REG_LABEL:
11202           /* These notes say something about how a register is used.  They must
11203              be present on any use of the register in I2 or I3.  */
11204           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11205             place = i3;
11206
11207           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11208             {
11209               if (place)
11210                 place2 = i2;
11211               else
11212                 place = i2;
11213             }
11214           break;
11215
11216         case REG_WAS_0:
11217           /* It is too much trouble to try to see if this note is still
11218              correct in all situations.  It is better to simply delete it.  */
11219           break;
11220
11221         case REG_RETVAL:
11222           /* If the insn previously containing this note still exists,
11223              put it back where it was.  Otherwise move it to the previous
11224              insn.  Adjust the corresponding REG_LIBCALL note.  */
11225           if (GET_CODE (from_insn) != NOTE)
11226             place = from_insn;
11227           else
11228             {
11229               tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11230               place = prev_real_insn (from_insn);
11231               if (tem && place)
11232                 XEXP (tem, 0) = place;
11233             }
11234           break;
11235
11236         case REG_LIBCALL:
11237           /* This is handled similarly to REG_RETVAL.  */
11238           if (GET_CODE (from_insn) != NOTE)
11239             place = from_insn;
11240           else
11241             {
11242               tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11243               place = next_real_insn (from_insn);
11244               if (tem && place)
11245                 XEXP (tem, 0) = place;
11246             }
11247           break;
11248
11249         case REG_DEAD:
11250           /* If the register is used as an input in I3, it dies there.
11251              Similarly for I2, if it is non-zero and adjacent to I3.
11252
11253              If the register is not used as an input in either I3 or I2
11254              and it is not one of the registers we were supposed to eliminate,
11255              there are two possibilities.  We might have a non-adjacent I2
11256              or we might have somehow eliminated an additional register
11257              from a computation.  For example, we might have had A & B where
11258              we discover that B will always be zero.  In this case we will
11259              eliminate the reference to A.
11260
11261              In both cases, we must search to see if we can find a previous
11262              use of A and put the death note there.  */
11263
11264           if (from_insn
11265               && GET_CODE (from_insn) == CALL_INSN
11266               && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11267             place = from_insn;
11268           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11269             place = i3;
11270           else if (i2 != 0 && next_nonnote_insn (i2) == i3
11271                    && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11272             place = i2;
11273
11274           if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
11275             break;
11276
11277           /* If the register is used in both I2 and I3 and it dies in I3,
11278              we might have added another reference to it.  If reg_n_refs
11279              was 2, bump it to 3.  This has to be correct since the
11280              register must have been set somewhere.  The reason this is
11281              done is because local-alloc.c treats 2 references as a
11282              special case.  */
11283
11284           if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
11285               && REG_N_REFS (REGNO (XEXP (note, 0)))== 2
11286               && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11287             REG_N_REFS (REGNO (XEXP (note, 0))) = 3;
11288
11289           if (place == 0)
11290             {
11291               for (tem = prev_nonnote_insn (i3);
11292                    place == 0 && tem
11293                    && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
11294                    tem = prev_nonnote_insn (tem))
11295                 {
11296                   /* If the register is being set at TEM, see if that is all
11297                      TEM is doing.  If so, delete TEM.  Otherwise, make this
11298                      into a REG_UNUSED note instead.  */
11299                   if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11300                     {
11301                       rtx set = single_set (tem);
11302
11303                       /* Verify that it was the set, and not a clobber that
11304                          modified the register.  */
11305
11306                       if (set != 0 && ! side_effects_p (SET_SRC (set))
11307                           && (rtx_equal_p (XEXP (note, 0), SET_DEST (set))
11308                               || (GET_CODE (SET_DEST (set)) == SUBREG
11309                                   && rtx_equal_p (XEXP (note, 0),
11310                                                   XEXP (SET_DEST (set), 0)))))
11311                         {
11312                           /* Move the notes and links of TEM elsewhere.
11313                              This might delete other dead insns recursively.
11314                              First set the pattern to something that won't use
11315                              any register.  */
11316
11317                           PATTERN (tem) = pc_rtx;
11318
11319                           distribute_notes (REG_NOTES (tem), tem, tem,
11320                                             NULL_RTX, NULL_RTX, NULL_RTX);
11321                           distribute_links (LOG_LINKS (tem));
11322
11323                           PUT_CODE (tem, NOTE);
11324                           NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11325                           NOTE_SOURCE_FILE (tem) = 0;
11326                         }
11327                       else
11328                         {
11329                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
11330
11331                           /*  If there isn't already a REG_UNUSED note, put one
11332                               here.  */
11333                           if (! find_regno_note (tem, REG_UNUSED,
11334                                                  REGNO (XEXP (note, 0))))
11335                             place = tem;
11336                           break;
11337                       }
11338                   }
11339                 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11340                          || (GET_CODE (tem) == CALL_INSN
11341                              && find_reg_fusage (tem, USE, XEXP (note, 0))))
11342                   {
11343                     place = tem;
11344
11345                     /* If we are doing a 3->2 combination, and we have a
11346                        register which formerly died in i3 and was not used
11347                        by i2, which now no longer dies in i3 and is used in
11348                        i2 but does not die in i2, and place is between i2
11349                        and i3, then we may need to move a link from place to
11350                        i2.  */
11351                     if (i2 && INSN_UID (place) <= max_uid_cuid
11352                         && INSN_CUID (place) > INSN_CUID (i2)
11353                         && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
11354                         && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11355                       {
11356                         rtx links = LOG_LINKS (place);
11357                         LOG_LINKS (place) = 0;
11358                         distribute_links (links);
11359                       }
11360                     break;
11361                   }
11362                 }
11363
11364               /* If we haven't found an insn for the death note and it
11365                  is still a REG_DEAD note, but we have hit a CODE_LABEL,
11366                  insert a USE insn for the register at that label and
11367                  put the death node there.  This prevents problems with
11368                  call-state tracking in caller-save.c.  */
11369               if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
11370                 {
11371                   place
11372                     = emit_insn_after (gen_rtx (USE, VOIDmode, XEXP (note, 0)),
11373                                        tem);
11374
11375                   /* If this insn was emitted between blocks, then update
11376                      basic_block_head of the current block to include it.  */
11377                   if (basic_block_end[this_basic_block - 1] == tem)
11378                     basic_block_head[this_basic_block] = place;
11379                 }
11380             }
11381
11382           /* If the register is set or already dead at PLACE, we needn't do
11383              anything with this note if it is still a REG_DEAD note.
11384
11385              Note that we cannot use just `dead_or_set_p' here since we can
11386              convert an assignment to a register into a bit-field assignment.
11387              Therefore, we must also omit the note if the register is the
11388              target of a bitfield assignment.  */
11389
11390           if (place && REG_NOTE_KIND (note) == REG_DEAD)
11391             {
11392               int regno = REGNO (XEXP (note, 0));
11393
11394               if (dead_or_set_p (place, XEXP (note, 0))
11395                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11396                 {
11397                   /* Unless the register previously died in PLACE, clear
11398                      reg_last_death.  [I no longer understand why this is
11399                      being done.] */
11400                   if (reg_last_death[regno] != place)
11401                     reg_last_death[regno] = 0;
11402                   place = 0;
11403                 }
11404               else
11405                 reg_last_death[regno] = place;
11406
11407               /* If this is a death note for a hard reg that is occupying
11408                  multiple registers, ensure that we are still using all
11409                  parts of the object.  If we find a piece of the object
11410                  that is unused, we must add a USE for that piece before
11411                  PLACE and put the appropriate REG_DEAD note on it.
11412
11413                  An alternative would be to put a REG_UNUSED for the pieces
11414                  on the insn that set the register, but that can't be done if
11415                  it is not in the same block.  It is simpler, though less
11416                  efficient, to add the USE insns.  */
11417
11418               if (place && regno < FIRST_PSEUDO_REGISTER
11419                   && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11420                 {
11421                   int endregno
11422                     = regno + HARD_REGNO_NREGS (regno,
11423                                                 GET_MODE (XEXP (note, 0)));
11424                   int all_used = 1;
11425                   int i;
11426
11427                   for (i = regno; i < endregno; i++)
11428                     if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11429                         && ! find_regno_fusage (place, USE, i))
11430                       {
11431                         rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11432                         rtx p;
11433
11434                         /* See if we already placed a USE note for this
11435                            register in front of PLACE.  */
11436                         for (p = place;
11437                              GET_CODE (PREV_INSN (p)) == INSN
11438                              && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11439                              p = PREV_INSN (p))
11440                           if (rtx_equal_p (piece,
11441                                            XEXP (PATTERN (PREV_INSN (p)), 0)))
11442                             {
11443                               p = 0;
11444                               break;
11445                             }
11446
11447                         if (p)
11448                           {
11449                             rtx use_insn
11450                               = emit_insn_before (gen_rtx (USE, VOIDmode,
11451                                                            piece),
11452                                                   p);
11453                             REG_NOTES (use_insn)
11454                               = gen_rtx (EXPR_LIST, REG_DEAD, piece,
11455                                          REG_NOTES (use_insn));
11456                           }
11457
11458                         all_used = 0;
11459                       }
11460
11461                   /* Check for the case where the register dying partially
11462                      overlaps the register set by this insn.  */
11463                   if (all_used)
11464                     for (i = regno; i < endregno; i++)
11465                       if (dead_or_set_regno_p (place, i))
11466                           {
11467                             all_used = 0;
11468                             break;
11469                           }
11470
11471                   if (! all_used)
11472                     {
11473                       /* Put only REG_DEAD notes for pieces that are
11474                          still used and that are not already dead or set.  */
11475
11476                       for (i = regno; i < endregno; i++)
11477                         {
11478                           rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11479
11480                           if ((reg_referenced_p (piece, PATTERN (place))
11481                                || (GET_CODE (place) == CALL_INSN
11482                                    && find_reg_fusage (place, USE, piece)))
11483                               && ! dead_or_set_p (place, piece)
11484                               && ! reg_bitfield_target_p (piece,
11485                                                           PATTERN (place)))
11486                             REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
11487                                                          piece,
11488                                                          REG_NOTES (place));
11489                         }
11490
11491                       place = 0;
11492                     }
11493                 }
11494             }
11495           break;
11496
11497         default:
11498           /* Any other notes should not be present at this point in the
11499              compilation.  */
11500           abort ();
11501         }
11502
11503       if (place)
11504         {
11505           XEXP (note, 1) = REG_NOTES (place);
11506           REG_NOTES (place) = note;
11507         }
11508       else if ((REG_NOTE_KIND (note) == REG_DEAD
11509                 || REG_NOTE_KIND (note) == REG_UNUSED)
11510                && GET_CODE (XEXP (note, 0)) == REG)
11511         REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
11512
11513       if (place2)
11514         {
11515           if ((REG_NOTE_KIND (note) == REG_DEAD
11516                || REG_NOTE_KIND (note) == REG_UNUSED)
11517               && GET_CODE (XEXP (note, 0)) == REG)
11518             REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
11519
11520           REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
11521                                         XEXP (note, 0), REG_NOTES (place2));
11522         }
11523     }
11524 }
11525 \f
11526 /* Similarly to above, distribute the LOG_LINKS that used to be present on
11527    I3, I2, and I1 to new locations.  This is also called in one case to
11528    add a link pointing at I3 when I3's destination is changed.  */
11529
11530 static void
11531 distribute_links (links)
11532      rtx links;
11533 {
11534   rtx link, next_link;
11535
11536   for (link = links; link; link = next_link)
11537     {
11538       rtx place = 0;
11539       rtx insn;
11540       rtx set, reg;
11541
11542       next_link = XEXP (link, 1);
11543
11544       /* If the insn that this link points to is a NOTE or isn't a single
11545          set, ignore it.  In the latter case, it isn't clear what we
11546          can do other than ignore the link, since we can't tell which
11547          register it was for.  Such links wouldn't be used by combine
11548          anyway.
11549
11550          It is not possible for the destination of the target of the link to
11551          have been changed by combine.  The only potential of this is if we
11552          replace I3, I2, and I1 by I3 and I2.  But in that case the
11553          destination of I2 also remains unchanged.  */
11554
11555       if (GET_CODE (XEXP (link, 0)) == NOTE
11556           || (set = single_set (XEXP (link, 0))) == 0)
11557         continue;
11558
11559       reg = SET_DEST (set);
11560       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
11561              || GET_CODE (reg) == SIGN_EXTRACT
11562              || GET_CODE (reg) == STRICT_LOW_PART)
11563         reg = XEXP (reg, 0);
11564
11565       /* A LOG_LINK is defined as being placed on the first insn that uses
11566          a register and points to the insn that sets the register.  Start
11567          searching at the next insn after the target of the link and stop
11568          when we reach a set of the register or the end of the basic block.
11569
11570          Note that this correctly handles the link that used to point from
11571          I3 to I2.  Also note that not much searching is typically done here
11572          since most links don't point very far away.  */
11573
11574       for (insn = NEXT_INSN (XEXP (link, 0));
11575            (insn && (this_basic_block == n_basic_blocks - 1
11576                      || basic_block_head[this_basic_block + 1] != insn));
11577            insn = NEXT_INSN (insn))
11578         if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
11579             && reg_overlap_mentioned_p (reg, PATTERN (insn)))
11580           {
11581             if (reg_referenced_p (reg, PATTERN (insn)))
11582               place = insn;
11583             break;
11584           }
11585         else if (GET_CODE (insn) == CALL_INSN
11586               && find_reg_fusage (insn, USE, reg))
11587           {
11588             place = insn;
11589             break;
11590           }
11591
11592       /* If we found a place to put the link, place it there unless there
11593          is already a link to the same insn as LINK at that point.  */
11594
11595       if (place)
11596         {
11597           rtx link2;
11598
11599           for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
11600             if (XEXP (link2, 0) == XEXP (link, 0))
11601               break;
11602
11603           if (link2 == 0)
11604             {
11605               XEXP (link, 1) = LOG_LINKS (place);
11606               LOG_LINKS (place) = link;
11607
11608               /* Set added_links_insn to the earliest insn we added a
11609                  link to.  */
11610               if (added_links_insn == 0
11611                   || INSN_CUID (added_links_insn) > INSN_CUID (place))
11612                 added_links_insn = place;
11613             }
11614         }
11615     }
11616 }
11617 \f
11618 /* Compute INSN_CUID for INSN, which is an insn made by combine.  */
11619
11620 static int
11621 insn_cuid (insn)
11622      rtx insn;
11623 {
11624   while (insn != 0 && INSN_UID (insn) > max_uid_cuid
11625          && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
11626     insn = NEXT_INSN (insn);
11627
11628   if (INSN_UID (insn) > max_uid_cuid)
11629     abort ();
11630
11631   return INSN_CUID (insn);
11632 }
11633 \f
11634 void
11635 dump_combine_stats (file)
11636      FILE *file;
11637 {
11638   fprintf
11639     (file,
11640      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11641      combine_attempts, combine_merges, combine_extras, combine_successes);
11642 }
11643
11644 void
11645 dump_combine_total_stats (file)
11646      FILE *file;
11647 {
11648   fprintf
11649     (file,
11650      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
11651      total_attempts, total_merges, total_extras, total_successes);
11652 }