gcc/testsuite/gcc.target/riscv/shift-and-1.c

   1 /* { dg-do compile } */
   2 /* { dg-options "-march=rv32gc -mabi=ilp32 -O" } */
   3
   4 /* Test for <optab>si3_mask.  */
   5 int
   6 sub1 (int i, int j)
   7 {
   8   return i << (j & 0x1f);
   9 }
  10 /* { dg-final { scan-assembler-not "andi" } } */