1 /* Subroutines used for code generation for RISC-V.
2 Copyright (C) 2011-2018 Free Software Foundation, Inc.
3 Contributed by Andrew Waterman (andrew@sifive.com).
4 Based on MIPS target for GNU compiler.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 #define IN_TARGET_CODE 1
26 #include "coretypes.h"
30 #include "insn-config.h"
31 #include "insn-attr.h"
36 #include "stringpool.h"
39 #include "stor-layout.h"
48 #include "target-def.h"
49 #include "basic-block.h"
54 #include "diagnostic.h"
58 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
59 #define UNSPEC_ADDRESS_P(X) \
60 (GET_CODE (X) == UNSPEC \
61 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
62 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
64 /* Extract the symbol or label from UNSPEC wrapper X. */
65 #define UNSPEC_ADDRESS(X) \
68 /* Extract the symbol type from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS_TYPE(X) \
70 ((enum riscv_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
72 /* True if bit BIT is set in VALUE. */
73 #define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0)
75 /* Classifies an address.
78 A natural register + offset address. The register satisfies
79 riscv_valid_base_register_p and the offset is a const_arith_operand.
82 A LO_SUM rtx. The first operand is a valid base register and
83 the second operand is a symbolic address.
86 A signed 16-bit constant address.
89 A constant symbolic address. */
90 enum riscv_address_type
{
97 /* Information about a function's frame layout. */
98 struct GTY(()) riscv_frame_info
{
99 /* The size of the frame in bytes. */
100 HOST_WIDE_INT total_size
;
102 /* Bit X is set if the function saves or restores GPR X. */
105 /* Likewise FPR X. */
108 /* How much the GPR save/restore routines adjust sp (or 0 if unused). */
109 unsigned save_libcall_adjustment
;
111 /* Offsets of fixed-point and floating-point save areas from frame bottom */
112 HOST_WIDE_INT gp_sp_offset
;
113 HOST_WIDE_INT fp_sp_offset
;
115 /* Offset of virtual frame pointer from stack pointer/frame bottom */
116 HOST_WIDE_INT frame_pointer_offset
;
118 /* Offset of hard frame pointer from stack pointer/frame bottom */
119 HOST_WIDE_INT hard_frame_pointer_offset
;
121 /* The offset of arg_pointer_rtx from the bottom of the frame. */
122 HOST_WIDE_INT arg_pointer_offset
;
125 enum riscv_privilege_levels
{
126 UNKNOWN_MODE
, USER_MODE
, SUPERVISOR_MODE
, MACHINE_MODE
129 struct GTY(()) machine_function
{
130 /* The number of extra stack bytes taken up by register varargs.
131 This area is allocated by the callee at the very top of the frame. */
134 /* True if current function is a naked function. */
137 /* True if current function is an interrupt function. */
138 bool interrupt_handler_p
;
139 /* For an interrupt handler, indicates the privilege level. */
140 enum riscv_privilege_levels interrupt_mode
;
142 /* True if attributes on current function have been checked. */
143 bool attributes_checked_p
;
145 /* The current frame information, calculated by riscv_compute_frame_info. */
146 struct riscv_frame_info frame
;
149 /* Information about a single argument. */
150 struct riscv_arg_info
{
151 /* True if the argument is at least partially passed on the stack. */
154 /* The number of integer registers allocated to this argument. */
155 unsigned int num_gprs
;
157 /* The offset of the first register used, provided num_gprs is nonzero.
158 If passed entirely on the stack, the value is MAX_ARGS_IN_REGISTERS. */
159 unsigned int gpr_offset
;
161 /* The number of floating-point registers allocated to this argument. */
162 unsigned int num_fprs
;
164 /* The offset of the first register used, provided num_fprs is nonzero. */
165 unsigned int fpr_offset
;
168 /* Information about an address described by riscv_address_type.
174 REG is the base register and OFFSET is the constant offset.
177 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
178 is the type of symbol it references.
181 SYMBOL_TYPE is the type of symbol that the address references. */
182 struct riscv_address_info
{
183 enum riscv_address_type type
;
186 enum riscv_symbol_type symbol_type
;
189 /* One stage in a constant building sequence. These sequences have
193 A = A CODE[1] VALUE[1]
194 A = A CODE[2] VALUE[2]
197 where A is an accumulator, each CODE[i] is a binary rtl operation
198 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
199 struct riscv_integer_op
{
201 unsigned HOST_WIDE_INT value
;
204 /* The largest number of operations needed to load an integer constant.
205 The worst case is LUI, ADDI, SLLI, ADDI, SLLI, ADDI, SLLI, ADDI. */
206 #define RISCV_MAX_INTEGER_OPS 8
208 /* Costs of various operations on the different architectures. */
210 struct riscv_tune_info
212 unsigned short fp_add
[2];
213 unsigned short fp_mul
[2];
214 unsigned short fp_div
[2];
215 unsigned short int_mul
[2];
216 unsigned short int_div
[2];
217 unsigned short issue_rate
;
218 unsigned short branch_cost
;
219 unsigned short memory_cost
;
220 bool slow_unaligned_access
;
223 /* Information about one CPU we know about. */
224 struct riscv_cpu_info
{
225 /* This CPU's canonical name. */
228 /* Tuning parameters for this CPU. */
229 const struct riscv_tune_info
*tune_info
;
232 /* Global variables for machine-dependent things. */
234 /* Whether unaligned accesses execute very slowly. */
235 bool riscv_slow_unaligned_access_p
;
237 /* Stack alignment to assume/maintain. */
238 unsigned riscv_stack_boundary
;
240 /* Which tuning parameters to use. */
241 static const struct riscv_tune_info
*tune_info
;
243 /* Index R is the smallest register class that contains register R. */
244 const enum reg_class riscv_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
245 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
246 GR_REGS
, GR_REGS
, SIBCALL_REGS
, SIBCALL_REGS
,
247 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
248 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
249 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
250 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
251 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
252 SIBCALL_REGS
, SIBCALL_REGS
, SIBCALL_REGS
, SIBCALL_REGS
,
253 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
254 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
255 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
256 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
257 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
258 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
259 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
260 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
261 FRAME_REGS
, FRAME_REGS
,
264 /* Costs to use when optimizing for rocket. */
265 static const struct riscv_tune_info rocket_tune_info
= {
266 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
267 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
268 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
269 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
270 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
274 true, /* slow_unaligned_access */
277 /* Costs to use when optimizing for size. */
278 static const struct riscv_tune_info optimize_size_tune_info
= {
279 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_add */
280 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_mul */
281 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_div */
282 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_mul */
283 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_div */
287 false, /* slow_unaligned_access */
290 static tree
riscv_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
291 static tree
riscv_handle_type_attribute (tree
*, tree
, tree
, int, bool *);
293 /* Defining target-specific uses of __attribute__. */
294 static const struct attribute_spec riscv_attribute_table
[] =
296 /* Syntax: { name, min_len, max_len, decl_required, type_required,
297 function_type_required, affects_type_identity, handler,
300 /* The attribute telling no prologue/epilogue. */
301 { "naked", 0, 0, true, false, false, false,
302 riscv_handle_fndecl_attribute
, NULL
},
303 /* This attribute generates prologue/epilogue for interrupt handlers. */
304 { "interrupt", 0, 1, false, true, true, false,
305 riscv_handle_type_attribute
, NULL
},
307 /* The last attribute spec is set to be NULL. */
308 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
311 /* A table describing all the processors GCC knows about. */
312 static const struct riscv_cpu_info riscv_cpu_info_table
[] = {
313 { "rocket", &rocket_tune_info
},
314 { "size", &optimize_size_tune_info
},
317 /* Return the riscv_cpu_info entry for the given name string. */
319 static const struct riscv_cpu_info
*
320 riscv_parse_cpu (const char *cpu_string
)
322 for (unsigned i
= 0; i
< ARRAY_SIZE (riscv_cpu_info_table
); i
++)
323 if (strcmp (riscv_cpu_info_table
[i
].name
, cpu_string
) == 0)
324 return riscv_cpu_info_table
+ i
;
326 error ("unknown cpu %qs for -mtune", cpu_string
);
327 return riscv_cpu_info_table
;
330 /* Helper function for riscv_build_integer; arguments are as for
331 riscv_build_integer. */
334 riscv_build_integer_1 (struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
],
335 HOST_WIDE_INT value
, machine_mode mode
)
337 HOST_WIDE_INT low_part
= CONST_LOW_PART (value
);
338 int cost
= RISCV_MAX_INTEGER_OPS
+ 1, alt_cost
;
339 struct riscv_integer_op alt_codes
[RISCV_MAX_INTEGER_OPS
];
341 if (SMALL_OPERAND (value
) || LUI_OPERAND (value
))
343 /* Simply ADDI or LUI. */
344 codes
[0].code
= UNKNOWN
;
345 codes
[0].value
= value
;
349 /* End with ADDI. When constructing HImode constants, do not generate any
350 intermediate value that is not itself a valid HImode constant. The
351 XORI case below will handle those remaining HImode constants. */
354 || value
- low_part
<= ((1 << (GET_MODE_BITSIZE (HImode
) - 1)) - 1)))
356 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, value
- low_part
, mode
);
359 alt_codes
[alt_cost
-1].code
= PLUS
;
360 alt_codes
[alt_cost
-1].value
= low_part
;
361 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
367 if (cost
> 2 && (low_part
< 0 || mode
== HImode
))
369 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, value
^ low_part
, mode
);
372 alt_codes
[alt_cost
-1].code
= XOR
;
373 alt_codes
[alt_cost
-1].value
= low_part
;
374 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
379 /* Eliminate trailing zeros and end with SLLI. */
380 if (cost
> 2 && (value
& 1) == 0)
382 int shift
= ctz_hwi (value
);
383 unsigned HOST_WIDE_INT x
= value
;
384 x
= sext_hwi (x
>> shift
, HOST_BITS_PER_WIDE_INT
- shift
);
386 /* Don't eliminate the lower 12 bits if LUI might apply. */
387 if (shift
> IMM_BITS
&& !SMALL_OPERAND (x
) && LUI_OPERAND (x
<< IMM_BITS
))
388 shift
-= IMM_BITS
, x
<<= IMM_BITS
;
390 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, x
, mode
);
393 alt_codes
[alt_cost
-1].code
= ASHIFT
;
394 alt_codes
[alt_cost
-1].value
= shift
;
395 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
400 gcc_assert (cost
<= RISCV_MAX_INTEGER_OPS
);
404 /* Fill CODES with a sequence of rtl operations to load VALUE.
405 Return the number of operations needed. */
408 riscv_build_integer (struct riscv_integer_op
*codes
, HOST_WIDE_INT value
,
411 int cost
= riscv_build_integer_1 (codes
, value
, mode
);
413 /* Eliminate leading zeros and end with SRLI. */
414 if (value
> 0 && cost
> 2)
416 struct riscv_integer_op alt_codes
[RISCV_MAX_INTEGER_OPS
];
417 int alt_cost
, shift
= clz_hwi (value
);
418 HOST_WIDE_INT shifted_val
;
420 /* Try filling trailing bits with 1s. */
421 shifted_val
= (value
<< shift
) | ((((HOST_WIDE_INT
) 1) << shift
) - 1);
422 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, shifted_val
, mode
);
425 alt_codes
[alt_cost
-1].code
= LSHIFTRT
;
426 alt_codes
[alt_cost
-1].value
= shift
;
427 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
431 /* Try filling trailing bits with 0s. */
432 shifted_val
= value
<< shift
;
433 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, shifted_val
, mode
);
436 alt_codes
[alt_cost
-1].code
= LSHIFTRT
;
437 alt_codes
[alt_cost
-1].value
= shift
;
438 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
446 /* Return the cost of constructing VAL in the event that a scratch
447 register is available. */
450 riscv_split_integer_cost (HOST_WIDE_INT val
)
453 unsigned HOST_WIDE_INT loval
= sext_hwi (val
, 32);
454 unsigned HOST_WIDE_INT hival
= sext_hwi ((val
- loval
) >> 32, 32);
455 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
457 cost
= 2 + riscv_build_integer (codes
, loval
, VOIDmode
);
459 cost
+= riscv_build_integer (codes
, hival
, VOIDmode
);
464 /* Return the cost of constructing the integer constant VAL. */
467 riscv_integer_cost (HOST_WIDE_INT val
)
469 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
470 return MIN (riscv_build_integer (codes
, val
, VOIDmode
),
471 riscv_split_integer_cost (val
));
474 /* Try to split a 64b integer into 32b parts, then reassemble. */
477 riscv_split_integer (HOST_WIDE_INT val
, machine_mode mode
)
479 unsigned HOST_WIDE_INT loval
= sext_hwi (val
, 32);
480 unsigned HOST_WIDE_INT hival
= sext_hwi ((val
- loval
) >> 32, 32);
481 rtx hi
= gen_reg_rtx (mode
), lo
= gen_reg_rtx (mode
);
483 riscv_move_integer (hi
, hi
, hival
);
484 riscv_move_integer (lo
, lo
, loval
);
486 hi
= gen_rtx_fmt_ee (ASHIFT
, mode
, hi
, GEN_INT (32));
487 hi
= force_reg (mode
, hi
);
489 return gen_rtx_fmt_ee (PLUS
, mode
, hi
, lo
);
492 /* Return true if X is a thread-local symbol. */
495 riscv_tls_symbol_p (const_rtx x
)
497 return SYMBOL_REF_P (x
) && SYMBOL_REF_TLS_MODEL (x
) != 0;
500 /* Return true if symbol X binds locally. */
503 riscv_symbol_binds_local_p (const_rtx x
)
505 if (SYMBOL_REF_P (x
))
506 return (SYMBOL_REF_DECL (x
)
507 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
508 : SYMBOL_REF_LOCAL_P (x
));
513 /* Return the method that should be used to access SYMBOL_REF or
516 static enum riscv_symbol_type
517 riscv_classify_symbol (const_rtx x
)
519 if (riscv_tls_symbol_p (x
))
522 if (GET_CODE (x
) == SYMBOL_REF
&& flag_pic
&& !riscv_symbol_binds_local_p (x
))
523 return SYMBOL_GOT_DISP
;
525 return riscv_cmodel
== CM_MEDLOW
? SYMBOL_ABSOLUTE
: SYMBOL_PCREL
;
528 /* Classify the base of symbolic expression X. */
530 enum riscv_symbol_type
531 riscv_classify_symbolic_expression (rtx x
)
535 split_const (x
, &x
, &offset
);
536 if (UNSPEC_ADDRESS_P (x
))
537 return UNSPEC_ADDRESS_TYPE (x
);
539 return riscv_classify_symbol (x
);
542 /* Return true if X is a symbolic constant. If it is, store the type of
543 the symbol in *SYMBOL_TYPE. */
546 riscv_symbolic_constant_p (rtx x
, enum riscv_symbol_type
*symbol_type
)
550 split_const (x
, &x
, &offset
);
551 if (UNSPEC_ADDRESS_P (x
))
553 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
554 x
= UNSPEC_ADDRESS (x
);
556 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
557 *symbol_type
= riscv_classify_symbol (x
);
561 if (offset
== const0_rtx
)
564 /* Nonzero offsets are only valid for references that don't use the GOT. */
565 switch (*symbol_type
)
567 case SYMBOL_ABSOLUTE
:
570 /* GAS rejects offsets outside the range [-2^31, 2^31-1]. */
571 return sext_hwi (INTVAL (offset
), 32) == INTVAL (offset
);
578 /* Returns the number of instructions necessary to reference a symbol. */
580 static int riscv_symbol_insns (enum riscv_symbol_type type
)
584 case SYMBOL_TLS
: return 0; /* Depends on the TLS model. */
585 case SYMBOL_ABSOLUTE
: return 2; /* LUI + the reference. */
586 case SYMBOL_PCREL
: return 2; /* AUIPC + the reference. */
587 case SYMBOL_TLS_LE
: return 3; /* LUI + ADD TP + the reference. */
588 case SYMBOL_GOT_DISP
: return 3; /* AUIPC + LD GOT + the reference. */
589 default: gcc_unreachable ();
593 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
596 riscv_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
598 return riscv_const_insns (x
) > 0;
601 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
604 riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
606 enum riscv_symbol_type type
;
609 /* There is no assembler syntax for expressing an address-sized
611 if (GET_CODE (x
) == HIGH
)
614 split_const (x
, &base
, &offset
);
615 if (riscv_symbolic_constant_p (base
, &type
))
617 /* As an optimization, don't spill symbolic constants that are as
618 cheap to rematerialize as to access in the constant pool. */
619 if (SMALL_OPERAND (INTVAL (offset
)) && riscv_symbol_insns (type
) > 0)
622 /* As an optimization, avoid needlessly generate dynamic relocations. */
627 /* TLS symbols must be computed by riscv_legitimize_move. */
628 if (tls_referenced_p (x
))
634 /* Return true if register REGNO is a valid base register for mode MODE.
635 STRICT_P is true if REG_OK_STRICT is in effect. */
638 riscv_regno_mode_ok_for_base_p (int regno
,
639 machine_mode mode ATTRIBUTE_UNUSED
,
642 if (!HARD_REGISTER_NUM_P (regno
))
646 regno
= reg_renumber
[regno
];
649 /* These fake registers will be eliminated to either the stack or
650 hard frame pointer, both of which are usually valid base registers.
651 Reload deals with the cases where the eliminated form isn't valid. */
652 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
655 return GP_REG_P (regno
);
658 /* Return true if X is a valid base register for mode MODE.
659 STRICT_P is true if REG_OK_STRICT is in effect. */
662 riscv_valid_base_register_p (rtx x
, machine_mode mode
, bool strict_p
)
664 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
668 && riscv_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
671 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
672 can address a value of mode MODE. */
675 riscv_valid_offset_p (rtx x
, machine_mode mode
)
677 /* Check that X is a signed 12-bit number. */
678 if (!const_arith_operand (x
, Pmode
))
681 /* We may need to split multiword moves, so make sure that every word
683 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
684 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
690 /* Should a symbol of type SYMBOL_TYPE should be split in two? */
693 riscv_split_symbol_type (enum riscv_symbol_type symbol_type
)
695 if (symbol_type
== SYMBOL_TLS_LE
)
698 if (!TARGET_EXPLICIT_RELOCS
)
701 return symbol_type
== SYMBOL_ABSOLUTE
|| symbol_type
== SYMBOL_PCREL
;
704 /* Return true if a LO_SUM can address a value of mode MODE when the
705 LO_SUM symbol has type SYM_TYPE. */
708 riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type
, machine_mode mode
)
710 /* Check that symbols of type SYMBOL_TYPE can be used to access values
712 if (riscv_symbol_insns (sym_type
) == 0)
715 /* Check that there is a known low-part relocation. */
716 if (!riscv_split_symbol_type (sym_type
))
719 /* We may need to split multiword moves, so make sure that each word
720 can be accessed without inducing a carry. */
721 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
722 && (!TARGET_STRICT_ALIGN
723 || GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
)))
729 /* Return true if X is a valid address for machine mode MODE. If it is,
730 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
734 riscv_classify_address (struct riscv_address_info
*info
, rtx x
,
735 machine_mode mode
, bool strict_p
)
737 switch (GET_CODE (x
))
741 info
->type
= ADDRESS_REG
;
743 info
->offset
= const0_rtx
;
744 return riscv_valid_base_register_p (info
->reg
, mode
, strict_p
);
747 info
->type
= ADDRESS_REG
;
748 info
->reg
= XEXP (x
, 0);
749 info
->offset
= XEXP (x
, 1);
750 return (riscv_valid_base_register_p (info
->reg
, mode
, strict_p
)
751 && riscv_valid_offset_p (info
->offset
, mode
));
754 info
->type
= ADDRESS_LO_SUM
;
755 info
->reg
= XEXP (x
, 0);
756 info
->offset
= XEXP (x
, 1);
757 /* We have to trust the creator of the LO_SUM to do something vaguely
758 sane. Target-independent code that creates a LO_SUM should also
759 create and verify the matching HIGH. Target-independent code that
760 adds an offset to a LO_SUM must prove that the offset will not
761 induce a carry. Failure to do either of these things would be
762 a bug, and we are not required to check for it here. The RISC-V
763 backend itself should only create LO_SUMs for valid symbolic
764 constants, with the high part being either a HIGH or a copy
767 = riscv_classify_symbolic_expression (info
->offset
);
768 return (riscv_valid_base_register_p (info
->reg
, mode
, strict_p
)
769 && riscv_valid_lo_sum_p (info
->symbol_type
, mode
));
772 /* Small-integer addresses don't occur very often, but they
773 are legitimate if x0 is a valid base register. */
774 info
->type
= ADDRESS_CONST_INT
;
775 return SMALL_OPERAND (INTVAL (x
));
782 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
785 riscv_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
787 struct riscv_address_info addr
;
789 return riscv_classify_address (&addr
, x
, mode
, strict_p
);
792 /* Return the number of instructions needed to load or store a value
793 of mode MODE at address X. Return 0 if X isn't valid for MODE.
794 Assume that multiword moves may need to be split into word moves
795 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
799 riscv_address_insns (rtx x
, machine_mode mode
, bool might_split_p
)
801 struct riscv_address_info addr
;
804 if (!riscv_classify_address (&addr
, x
, mode
, false))
807 /* BLKmode is used for single unaligned loads and stores and should
808 not count as a multiword mode. */
809 if (mode
!= BLKmode
&& might_split_p
)
810 n
+= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
812 if (addr
.type
== ADDRESS_LO_SUM
)
813 n
+= riscv_symbol_insns (addr
.symbol_type
) - 1;
818 /* Return the number of instructions needed to load constant X.
819 Return 0 if X isn't a valid constant. */
822 riscv_const_insns (rtx x
)
824 enum riscv_symbol_type symbol_type
;
827 switch (GET_CODE (x
))
830 if (!riscv_symbolic_constant_p (XEXP (x
, 0), &symbol_type
)
831 || !riscv_split_symbol_type (symbol_type
))
834 /* This is simply an LUI. */
839 int cost
= riscv_integer_cost (INTVAL (x
));
840 /* Force complicated constants to memory. */
841 return cost
< 4 ? cost
: 0;
846 /* We can use x0 to load floating-point zero. */
847 return x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
850 /* See if we can refer to X directly. */
851 if (riscv_symbolic_constant_p (x
, &symbol_type
))
852 return riscv_symbol_insns (symbol_type
);
854 /* Otherwise try splitting the constant into a base and offset. */
855 split_const (x
, &x
, &offset
);
858 int n
= riscv_const_insns (x
);
860 return n
+ riscv_integer_cost (INTVAL (offset
));
866 return riscv_symbol_insns (riscv_classify_symbol (x
));
873 /* X is a doubleword constant that can be handled by splitting it into
874 two words and loading each word separately. Return the number of
875 instructions required to do this. */
878 riscv_split_const_insns (rtx x
)
880 unsigned int low
, high
;
882 low
= riscv_const_insns (riscv_subword (x
, false));
883 high
= riscv_const_insns (riscv_subword (x
, true));
884 gcc_assert (low
> 0 && high
> 0);
888 /* Return the number of instructions needed to implement INSN,
889 given that it loads from or stores to MEM. */
892 riscv_load_store_insns (rtx mem
, rtx_insn
*insn
)
898 gcc_assert (MEM_P (mem
));
899 mode
= GET_MODE (mem
);
901 /* Try to prove that INSN does not need to be split. */
902 might_split_p
= true;
903 if (GET_MODE_BITSIZE (mode
) <= 32)
904 might_split_p
= false;
905 else if (GET_MODE_BITSIZE (mode
) == 64)
907 set
= single_set (insn
);
908 if (set
&& !riscv_split_64bit_move_p (SET_DEST (set
), SET_SRC (set
)))
909 might_split_p
= false;
912 return riscv_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
915 /* Emit a move from SRC to DEST. Assume that the move expanders can
916 handle all moves if !can_create_pseudo_p (). The distinction is
917 important because, unlike emit_move_insn, the move expanders know
918 how to force Pmode objects into the constant pool even when the
919 constant pool address is not itself legitimate. */
922 riscv_emit_move (rtx dest
, rtx src
)
924 return (can_create_pseudo_p ()
925 ? emit_move_insn (dest
, src
)
926 : emit_move_insn_1 (dest
, src
));
929 /* Emit an instruction of the form (set TARGET SRC). */
932 riscv_emit_set (rtx target
, rtx src
)
934 emit_insn (gen_rtx_SET (target
, src
));
938 /* Emit an instruction of the form (set DEST (CODE X Y)). */
941 riscv_emit_binary (enum rtx_code code
, rtx dest
, rtx x
, rtx y
)
943 return riscv_emit_set (dest
, gen_rtx_fmt_ee (code
, GET_MODE (dest
), x
, y
));
946 /* Compute (CODE X Y) and store the result in a new register
947 of mode MODE. Return that new register. */
950 riscv_force_binary (machine_mode mode
, enum rtx_code code
, rtx x
, rtx y
)
952 return riscv_emit_binary (code
, gen_reg_rtx (mode
), x
, y
);
955 /* Copy VALUE to a register and return that register. If new pseudos
956 are allowed, copy it into a new register, otherwise use DEST. */
959 riscv_force_temporary (rtx dest
, rtx value
)
961 if (can_create_pseudo_p ())
962 return force_reg (Pmode
, value
);
965 riscv_emit_move (dest
, value
);
970 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
971 then add CONST_INT OFFSET to the result. */
974 riscv_unspec_address_offset (rtx base
, rtx offset
,
975 enum riscv_symbol_type symbol_type
)
977 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
978 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
979 if (offset
!= const0_rtx
)
980 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
981 return gen_rtx_CONST (Pmode
, base
);
984 /* Return an UNSPEC address with underlying address ADDRESS and symbol
988 riscv_unspec_address (rtx address
, enum riscv_symbol_type symbol_type
)
992 split_const (address
, &base
, &offset
);
993 return riscv_unspec_address_offset (base
, offset
, symbol_type
);
996 /* If OP is an UNSPEC address, return the address to which it refers,
997 otherwise return OP itself. */
1000 riscv_strip_unspec_address (rtx op
)
1004 split_const (op
, &base
, &offset
);
1005 if (UNSPEC_ADDRESS_P (base
))
1006 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
1010 /* If riscv_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1011 high part to BASE and return the result. Just return BASE otherwise.
1012 TEMP is as for riscv_force_temporary.
1014 The returned expression can be used as the first operand to a LO_SUM. */
1017 riscv_unspec_offset_high (rtx temp
, rtx addr
, enum riscv_symbol_type symbol_type
)
1019 addr
= gen_rtx_HIGH (Pmode
, riscv_unspec_address (addr
, symbol_type
));
1020 return riscv_force_temporary (temp
, addr
);
1023 /* Load an entry from the GOT for a TLS GD access. */
1025 static rtx
riscv_got_load_tls_gd (rtx dest
, rtx sym
)
1027 if (Pmode
== DImode
)
1028 return gen_got_load_tls_gddi (dest
, sym
);
1030 return gen_got_load_tls_gdsi (dest
, sym
);
1033 /* Load an entry from the GOT for a TLS IE access. */
1035 static rtx
riscv_got_load_tls_ie (rtx dest
, rtx sym
)
1037 if (Pmode
== DImode
)
1038 return gen_got_load_tls_iedi (dest
, sym
);
1040 return gen_got_load_tls_iesi (dest
, sym
);
1043 /* Add in the thread pointer for a TLS LE access. */
1045 static rtx
riscv_tls_add_tp_le (rtx dest
, rtx base
, rtx sym
)
1047 rtx tp
= gen_rtx_REG (Pmode
, THREAD_POINTER_REGNUM
);
1048 if (Pmode
== DImode
)
1049 return gen_tls_add_tp_ledi (dest
, base
, tp
, sym
);
1051 return gen_tls_add_tp_lesi (dest
, base
, tp
, sym
);
1054 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
1055 it appears in a MEM of that mode. Return true if ADDR is a legitimate
1056 constant in that context and can be split into high and low parts.
1057 If so, and if LOW_OUT is nonnull, emit the high part and store the
1058 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
1060 TEMP is as for riscv_force_temporary and is used to load the high
1061 part into a register.
1063 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
1064 a legitimize SET_SRC for an .md pattern, otherwise the low part
1065 is guaranteed to be a legitimate address for mode MODE. */
1068 riscv_split_symbol (rtx temp
, rtx addr
, machine_mode mode
, rtx
*low_out
)
1070 enum riscv_symbol_type symbol_type
;
1072 if ((GET_CODE (addr
) == HIGH
&& mode
== MAX_MACHINE_MODE
)
1073 || !riscv_symbolic_constant_p (addr
, &symbol_type
)
1074 || riscv_symbol_insns (symbol_type
) == 0
1075 || !riscv_split_symbol_type (symbol_type
))
1079 switch (symbol_type
)
1081 case SYMBOL_ABSOLUTE
:
1083 rtx high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
1084 high
= riscv_force_temporary (temp
, high
);
1085 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
1091 static unsigned seqno
;
1095 ssize_t bytes
= snprintf (buf
, sizeof (buf
), ".LA%u", seqno
);
1096 gcc_assert ((size_t) bytes
< sizeof (buf
));
1098 label
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
1099 SYMBOL_REF_FLAGS (label
) |= SYMBOL_FLAG_LOCAL
;
1102 temp
= gen_reg_rtx (Pmode
);
1104 if (Pmode
== DImode
)
1105 emit_insn (gen_auipcdi (temp
, copy_rtx (addr
), GEN_INT (seqno
)));
1107 emit_insn (gen_auipcsi (temp
, copy_rtx (addr
), GEN_INT (seqno
)));
1109 *low_out
= gen_rtx_LO_SUM (Pmode
, temp
, label
);
1122 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1123 riscv_force_temporary; it is only needed when OFFSET is not a
1127 riscv_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
1129 if (!SMALL_OPERAND (offset
))
1133 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
1134 The addition inside the macro CONST_HIGH_PART may cause an
1135 overflow, so we need to force a sign-extension check. */
1136 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
1137 offset
= CONST_LOW_PART (offset
);
1138 high
= riscv_force_temporary (temp
, high
);
1139 reg
= riscv_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
1141 return plus_constant (Pmode
, reg
, offset
);
1144 /* The __tls_get_attr symbol. */
1145 static GTY(()) rtx riscv_tls_symbol
;
1147 /* Return an instruction sequence that calls __tls_get_addr. SYM is
1148 the TLS symbol we are referencing and TYPE is the symbol type to use
1149 (either global dynamic or local dynamic). RESULT is an RTX for the
1150 return value location. */
1153 riscv_call_tls_get_addr (rtx sym
, rtx result
)
1155 rtx a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
), func
;
1158 if (!riscv_tls_symbol
)
1159 riscv_tls_symbol
= init_one_libfunc ("__tls_get_addr");
1160 func
= gen_rtx_MEM (FUNCTION_MODE
, riscv_tls_symbol
);
1164 emit_insn (riscv_got_load_tls_gd (a0
, sym
));
1165 insn
= emit_call_insn (gen_call_value (result
, func
, const0_rtx
, NULL
));
1166 RTL_CONST_CALL_P (insn
) = 1;
1167 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
1168 insn
= get_insns ();
1175 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
1176 its address. The return value will be both a valid address and a valid
1177 SET_SRC (either a REG or a LO_SUM). */
1180 riscv_legitimize_tls_address (rtx loc
)
1183 enum tls_model model
= SYMBOL_REF_TLS_MODEL (loc
);
1185 /* Since we support TLS copy relocs, non-PIC TLS accesses may all use LE. */
1187 model
= TLS_MODEL_LOCAL_EXEC
;
1191 case TLS_MODEL_LOCAL_DYNAMIC
:
1192 /* Rely on section anchors for the optimization that LDM TLS
1193 provides. The anchor's address is loaded with GD TLS. */
1194 case TLS_MODEL_GLOBAL_DYNAMIC
:
1195 tmp
= gen_rtx_REG (Pmode
, GP_RETURN
);
1196 dest
= gen_reg_rtx (Pmode
);
1197 emit_libcall_block (riscv_call_tls_get_addr (loc
, tmp
), dest
, tmp
, loc
);
1200 case TLS_MODEL_INITIAL_EXEC
:
1201 /* la.tls.ie; tp-relative add */
1202 tp
= gen_rtx_REG (Pmode
, THREAD_POINTER_REGNUM
);
1203 tmp
= gen_reg_rtx (Pmode
);
1204 emit_insn (riscv_got_load_tls_ie (tmp
, loc
));
1205 dest
= gen_reg_rtx (Pmode
);
1206 emit_insn (gen_add3_insn (dest
, tmp
, tp
));
1209 case TLS_MODEL_LOCAL_EXEC
:
1210 tmp
= riscv_unspec_offset_high (NULL
, loc
, SYMBOL_TLS_LE
);
1211 dest
= gen_reg_rtx (Pmode
);
1212 emit_insn (riscv_tls_add_tp_le (dest
, tmp
, loc
));
1213 dest
= gen_rtx_LO_SUM (Pmode
, dest
,
1214 riscv_unspec_address (loc
, SYMBOL_TLS_LE
));
1223 /* If X is not a valid address for mode MODE, force it into a register. */
1226 riscv_force_address (rtx x
, machine_mode mode
)
1228 if (!riscv_legitimate_address_p (mode
, x
, false))
1229 x
= force_reg (Pmode
, x
);
1233 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
1234 be legitimized in a way that the generic machinery might not expect,
1235 return a new address, otherwise return NULL. MODE is the mode of
1236 the memory being accessed. */
1239 riscv_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1244 if (riscv_tls_symbol_p (x
))
1245 return riscv_legitimize_tls_address (x
);
1247 /* See if the address can split into a high part and a LO_SUM. */
1248 if (riscv_split_symbol (NULL
, x
, mode
, &addr
))
1249 return riscv_force_address (addr
, mode
);
1251 /* Handle BASE + OFFSET using riscv_add_offset. */
1252 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1))
1253 && INTVAL (XEXP (x
, 1)) != 0)
1255 rtx base
= XEXP (x
, 0);
1256 HOST_WIDE_INT offset
= INTVAL (XEXP (x
, 1));
1258 if (!riscv_valid_base_register_p (base
, mode
, false))
1259 base
= copy_to_mode_reg (Pmode
, base
);
1260 addr
= riscv_add_offset (NULL
, base
, offset
);
1261 return riscv_force_address (addr
, mode
);
1267 /* Load VALUE into DEST. TEMP is as for riscv_force_temporary. */
1270 riscv_move_integer (rtx temp
, rtx dest
, HOST_WIDE_INT value
)
1272 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
1277 mode
= GET_MODE (dest
);
1278 num_ops
= riscv_build_integer (codes
, value
, mode
);
1280 if (can_create_pseudo_p () && num_ops
> 2 /* not a simple constant */
1281 && num_ops
>= riscv_split_integer_cost (value
))
1282 x
= riscv_split_integer (value
, mode
);
1285 /* Apply each binary operation to X. */
1286 x
= GEN_INT (codes
[0].value
);
1288 for (i
= 1; i
< num_ops
; i
++)
1290 if (!can_create_pseudo_p ())
1291 x
= riscv_emit_set (temp
, x
);
1293 x
= force_reg (mode
, x
);
1295 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
1299 riscv_emit_set (dest
, x
);
1302 /* Subroutine of riscv_legitimize_move. Move constant SRC into register
1303 DEST given that SRC satisfies immediate_operand but doesn't satisfy
1307 riscv_legitimize_const_move (machine_mode mode
, rtx dest
, rtx src
)
1311 /* Split moves of big integers into smaller pieces. */
1312 if (splittable_const_int_operand (src
, mode
))
1314 riscv_move_integer (dest
, dest
, INTVAL (src
));
1318 /* Split moves of symbolic constants into high/low pairs. */
1319 if (riscv_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
1321 riscv_emit_set (dest
, src
);
1325 /* Generate the appropriate access sequences for TLS symbols. */
1326 if (riscv_tls_symbol_p (src
))
1328 riscv_emit_move (dest
, riscv_legitimize_tls_address (src
));
1332 /* If we have (const (plus symbol offset)), and that expression cannot
1333 be forced into memory, load the symbol first and add in the offset. Also
1334 prefer to do this even if the constant _can_ be forced into memory, as it
1335 usually produces better code. */
1336 split_const (src
, &base
, &offset
);
1337 if (offset
!= const0_rtx
1338 && (targetm
.cannot_force_const_mem (mode
, src
) || can_create_pseudo_p ()))
1340 base
= riscv_force_temporary (dest
, base
);
1341 riscv_emit_move (dest
, riscv_add_offset (NULL
, base
, INTVAL (offset
)));
1345 src
= force_const_mem (mode
, src
);
1347 /* When using explicit relocs, constant pool references are sometimes
1348 not legitimate addresses. */
1349 riscv_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
1350 riscv_emit_move (dest
, src
);
1353 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
1354 sequence that is valid. */
1357 riscv_legitimize_move (machine_mode mode
, rtx dest
, rtx src
)
1359 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
1361 riscv_emit_move (dest
, force_reg (mode
, src
));
1365 /* We need to deal with constants that would be legitimate
1366 immediate_operands but aren't legitimate move_operands. */
1367 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
1369 riscv_legitimize_const_move (mode
, dest
, src
);
1370 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
1374 /* RISC-V GCC may generate non-legitimate address due to we provide some
1375 pattern for optimize access PIC local symbol and it's make GCC generate
1376 unrecognizable instruction during optmizing. */
1378 if (MEM_P (dest
) && !riscv_legitimate_address_p (mode
, XEXP (dest
, 0),
1381 XEXP (dest
, 0) = riscv_force_address (XEXP (dest
, 0), mode
);
1384 if (MEM_P (src
) && !riscv_legitimate_address_p (mode
, XEXP (src
, 0),
1387 XEXP (src
, 0) = riscv_force_address (XEXP (src
, 0), mode
);
1393 /* Return true if there is an instruction that implements CODE and accepts
1394 X as an immediate operand. */
1397 riscv_immediate_operand_p (int code
, HOST_WIDE_INT x
)
1404 /* All shift counts are truncated to a valid constant. */
1413 /* These instructions take 12-bit signed immediates. */
1414 return SMALL_OPERAND (x
);
1417 /* We add 1 to the immediate and use SLT. */
1418 return SMALL_OPERAND (x
+ 1);
1421 /* Likewise SLTU, but reject the always-true case. */
1422 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
1426 /* We can emulate an immediate of 1 by using GT/GTU against x0. */
1430 /* By default assume that x0 can be used for 0. */
1435 /* Return the cost of binary operation X, given that the instruction
1436 sequence for a word-sized or smaller operation takes SIGNLE_INSNS
1437 instructions and that the sequence of a double-word operation takes
1438 DOUBLE_INSNS instructions. */
1441 riscv_binary_cost (rtx x
, int single_insns
, int double_insns
)
1443 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
1444 return COSTS_N_INSNS (double_insns
);
1445 return COSTS_N_INSNS (single_insns
);
1448 /* Return the cost of sign- or zero-extending OP. */
1451 riscv_extend_cost (rtx op
, bool unsigned_p
)
1456 if (unsigned_p
&& GET_MODE (op
) == QImode
)
1457 /* We can use ANDI. */
1458 return COSTS_N_INSNS (1);
1460 if (!unsigned_p
&& GET_MODE (op
) == SImode
)
1461 /* We can use SEXT.W. */
1462 return COSTS_N_INSNS (1);
1464 /* We need to use a shift left and a shift right. */
1465 return COSTS_N_INSNS (2);
1468 /* Implement TARGET_RTX_COSTS. */
1470 #define SINGLE_SHIFT_COST 1
1473 riscv_rtx_costs (rtx x
, machine_mode mode
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
1474 int *total
, bool speed
)
1476 bool float_mode_p
= FLOAT_MODE_P (mode
);
1479 switch (GET_CODE (x
))
1482 if (riscv_immediate_operand_p (outer_code
, INTVAL (x
)))
1493 if ((cost
= riscv_const_insns (x
)) > 0)
1495 /* If the constant is likely to be stored in a GPR, SETs of
1496 single-insn constants are as cheap as register sets; we
1497 never want to CSE them. */
1498 if (cost
== 1 && outer_code
== SET
)
1500 /* When we load a constant more than once, it usually is better
1501 to duplicate the last operation in the sequence than to CSE
1502 the constant itself. */
1503 else if (outer_code
== SET
|| GET_MODE (x
) == VOIDmode
)
1504 *total
= COSTS_N_INSNS (1);
1506 else /* The instruction will be fetched from the constant pool. */
1507 *total
= COSTS_N_INSNS (riscv_symbol_insns (SYMBOL_ABSOLUTE
));
1511 /* If the address is legitimate, return the number of
1512 instructions it needs. */
1513 if ((cost
= riscv_address_insns (XEXP (x
, 0), mode
, true)) > 0)
1515 *total
= COSTS_N_INSNS (cost
+ tune_info
->memory_cost
);
1518 /* Otherwise use the default handling. */
1522 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
1528 /* Double-word operations use two single-word operations. */
1529 *total
= riscv_binary_cost (x
, 1, 2);
1533 /* This is an SImode shift. */
1534 if (outer_code
== SET
&& (INTVAL (XEXP (x
, 2)) > 0)
1535 && (INTVAL (XEXP (x
, 1)) + INTVAL (XEXP (x
, 2)) == 32))
1537 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
1545 *total
= riscv_binary_cost (x
, SINGLE_SHIFT_COST
,
1546 CONSTANT_P (XEXP (x
, 1)) ? 4 : 9);
1550 *total
= COSTS_N_INSNS (float_mode_p
? 1 : 3);
1554 *total
= set_src_cost (XEXP (x
, 0), mode
, speed
);
1558 /* This is an SImode shift. */
1559 if (outer_code
== SET
&& GET_MODE (x
) == DImode
1560 && GET_MODE (XEXP (x
, 0)) == SImode
)
1562 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
1575 /* Branch comparisons have VOIDmode, so use the first operand's
1577 mode
= GET_MODE (XEXP (x
, 0));
1579 *total
= tune_info
->fp_add
[mode
== DFmode
];
1581 *total
= riscv_binary_cost (x
, 1, 3);
1586 /* (FEQ(A, A) & FEQ(B, B)) compared against 0. */
1587 mode
= GET_MODE (XEXP (x
, 0));
1588 *total
= tune_info
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (2);
1593 /* (FEQ(A, A) & FEQ(B, B)) compared against FEQ(A, B). */
1594 mode
= GET_MODE (XEXP (x
, 0));
1595 *total
= tune_info
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (3);
1602 /* FLT or FLE, but guarded by an FFLAGS read and write. */
1603 mode
= GET_MODE (XEXP (x
, 0));
1604 *total
= tune_info
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (4);
1610 *total
= tune_info
->fp_add
[mode
== DFmode
];
1612 *total
= riscv_binary_cost (x
, 1, 4);
1617 rtx op
= XEXP (x
, 0);
1618 if (GET_CODE (op
) == FMA
&& !HONOR_SIGNED_ZEROS (mode
))
1620 *total
= (tune_info
->fp_mul
[mode
== DFmode
]
1621 + set_src_cost (XEXP (op
, 0), mode
, speed
)
1622 + set_src_cost (XEXP (op
, 1), mode
, speed
)
1623 + set_src_cost (XEXP (op
, 2), mode
, speed
));
1629 *total
= tune_info
->fp_add
[mode
== DFmode
];
1631 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
1636 *total
= tune_info
->fp_mul
[mode
== DFmode
];
1637 else if (!TARGET_MUL
)
1638 /* Estimate the cost of a library call. */
1639 *total
= COSTS_N_INSNS (speed
? 32 : 6);
1640 else if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
1641 *total
= 3 * tune_info
->int_mul
[0] + COSTS_N_INSNS (2);
1643 *total
= COSTS_N_INSNS (1);
1645 *total
= tune_info
->int_mul
[mode
== DImode
];
1653 *total
= tune_info
->fp_div
[mode
== DFmode
];
1661 /* Estimate the cost of a library call. */
1662 *total
= COSTS_N_INSNS (speed
? 32 : 6);
1664 *total
= tune_info
->int_div
[mode
== DImode
];
1666 *total
= COSTS_N_INSNS (1);
1670 /* This is an SImode shift. */
1671 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
)
1673 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
1678 *total
= riscv_extend_cost (XEXP (x
, 0), GET_CODE (x
) == ZERO_EXTEND
);
1682 case UNSIGNED_FLOAT
:
1685 case FLOAT_TRUNCATE
:
1686 *total
= tune_info
->fp_add
[mode
== DFmode
];
1690 *total
= (tune_info
->fp_mul
[mode
== DFmode
]
1691 + set_src_cost (XEXP (x
, 0), mode
, speed
)
1692 + set_src_cost (XEXP (x
, 1), mode
, speed
)
1693 + set_src_cost (XEXP (x
, 2), mode
, speed
));
1697 if (XINT (x
, 1) == UNSPEC_AUIPC
)
1699 /* Make AUIPC cheap to avoid spilling its result to the stack. */
1710 /* Implement TARGET_ADDRESS_COST. */
1713 riscv_address_cost (rtx addr
, machine_mode mode
,
1714 addr_space_t as ATTRIBUTE_UNUSED
,
1715 bool speed ATTRIBUTE_UNUSED
)
1717 return riscv_address_insns (addr
, mode
, false);
1720 /* Return one word of double-word value OP. HIGH_P is true to select the
1721 high part or false to select the low part. */
1724 riscv_subword (rtx op
, bool high_p
)
1726 unsigned int byte
= high_p
? UNITS_PER_WORD
: 0;
1727 machine_mode mode
= GET_MODE (op
);
1729 if (mode
== VOIDmode
)
1730 mode
= TARGET_64BIT
? TImode
: DImode
;
1733 return adjust_address (op
, word_mode
, byte
);
1736 gcc_assert (!FP_REG_RTX_P (op
));
1738 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
1741 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
1744 riscv_split_64bit_move_p (rtx dest
, rtx src
)
1749 /* Allow FPR <-> FPR and FPR <-> MEM moves, and permit the special case
1750 of zeroing an FPR with FCVT.D.W. */
1751 if (TARGET_DOUBLE_FLOAT
1752 && ((FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
1753 || (FP_REG_RTX_P (dest
) && MEM_P (src
))
1754 || (FP_REG_RTX_P (src
) && MEM_P (dest
))
1755 || (FP_REG_RTX_P (dest
) && src
== CONST0_RTX (GET_MODE (src
)))))
1761 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
1762 this function handles 64-bit moves for which riscv_split_64bit_move_p
1763 holds. For 64-bit targets, this function handles 128-bit moves. */
1766 riscv_split_doubleword_move (rtx dest
, rtx src
)
1770 /* The operation can be split into two normal moves. Decide in
1771 which order to do them. */
1772 low_dest
= riscv_subword (dest
, false);
1773 if (REG_P (low_dest
) && reg_overlap_mentioned_p (low_dest
, src
))
1775 riscv_emit_move (riscv_subword (dest
, true), riscv_subword (src
, true));
1776 riscv_emit_move (low_dest
, riscv_subword (src
, false));
1780 riscv_emit_move (low_dest
, riscv_subword (src
, false));
1781 riscv_emit_move (riscv_subword (dest
, true), riscv_subword (src
, true));
1785 /* Return the appropriate instructions to move SRC into DEST. Assume
1786 that SRC is operand 1 and DEST is operand 0. */
1789 riscv_output_move (rtx dest
, rtx src
)
1791 enum rtx_code dest_code
, src_code
;
1795 dest_code
= GET_CODE (dest
);
1796 src_code
= GET_CODE (src
);
1797 mode
= GET_MODE (dest
);
1798 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
1800 if (dbl_p
&& riscv_split_64bit_move_p (dest
, src
))
1803 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
1805 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
1806 return dbl_p
? "fmv.x.d\t%0,%1" : "fmv.x.s\t%0,%1";
1808 if (src_code
== MEM
)
1809 switch (GET_MODE_SIZE (mode
))
1811 case 1: return "lbu\t%0,%1";
1812 case 2: return "lhu\t%0,%1";
1813 case 4: return "lw\t%0,%1";
1814 case 8: return "ld\t%0,%1";
1817 if (src_code
== CONST_INT
)
1820 if (src_code
== HIGH
)
1821 return "lui\t%0,%h1";
1823 if (symbolic_operand (src
, VOIDmode
))
1824 switch (riscv_classify_symbolic_expression (src
))
1826 case SYMBOL_GOT_DISP
: return "la\t%0,%1";
1827 case SYMBOL_ABSOLUTE
: return "lla\t%0,%1";
1828 case SYMBOL_PCREL
: return "lla\t%0,%1";
1829 default: gcc_unreachable ();
1832 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
1833 || (src
== CONST0_RTX (mode
)))
1835 if (dest_code
== REG
)
1837 if (GP_REG_P (REGNO (dest
)))
1838 return "mv\t%0,%z1";
1840 if (FP_REG_P (REGNO (dest
)))
1843 return "fmv.s.x\t%0,%z1";
1845 return "fmv.d.x\t%0,%z1";
1846 /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */
1847 gcc_assert (src
== CONST0_RTX (mode
));
1848 return "fcvt.d.w\t%0,x0";
1851 if (dest_code
== MEM
)
1852 switch (GET_MODE_SIZE (mode
))
1854 case 1: return "sb\t%z1,%0";
1855 case 2: return "sh\t%z1,%0";
1856 case 4: return "sw\t%z1,%0";
1857 case 8: return "sd\t%z1,%0";
1860 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
1862 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
1863 return dbl_p
? "fmv.d\t%0,%1" : "fmv.s\t%0,%1";
1865 if (dest_code
== MEM
)
1866 return dbl_p
? "fsd\t%1,%0" : "fsw\t%1,%0";
1868 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
1870 if (src_code
== MEM
)
1871 return dbl_p
? "fld\t%0,%1" : "flw\t%0,%1";
1877 riscv_output_return ()
1879 if (cfun
->machine
->naked_p
)
1886 /* Return true if CMP1 is a suitable second operand for integer ordering
1887 test CODE. See also the *sCC patterns in riscv.md. */
1890 riscv_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
1896 return reg_or_0_operand (cmp1
, VOIDmode
);
1900 return cmp1
== const1_rtx
;
1904 return arith_operand (cmp1
, VOIDmode
);
1907 return sle_operand (cmp1
, VOIDmode
);
1910 return sleu_operand (cmp1
, VOIDmode
);
1917 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
1918 integer ordering test *CODE, or if an equivalent combination can
1919 be formed by adjusting *CODE and *CMP1. When returning true, update
1920 *CODE and *CMP1 with the chosen code and operand, otherwise leave
1924 riscv_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
1927 HOST_WIDE_INT plus_one
;
1929 if (riscv_int_order_operand_ok_p (*code
, *cmp1
))
1932 if (CONST_INT_P (*cmp1
))
1936 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
1937 if (INTVAL (*cmp1
) < plus_one
)
1940 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
1946 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
1950 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
1961 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
1962 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
1963 is nonnull, it's OK to set TARGET to the inverse of the result and
1964 flip *INVERT_PTR instead. */
1967 riscv_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
1968 rtx target
, rtx cmp0
, rtx cmp1
)
1972 /* First see if there is a RISCV instruction that can do this operation.
1973 If not, try doing the same for the inverse operation. If that also
1974 fails, force CMP1 into a register and try again. */
1975 mode
= GET_MODE (cmp0
);
1976 if (riscv_canonicalize_int_order_test (&code
, &cmp1
, mode
))
1977 riscv_emit_binary (code
, target
, cmp0
, cmp1
);
1980 enum rtx_code inv_code
= reverse_condition (code
);
1981 if (!riscv_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
1983 cmp1
= force_reg (mode
, cmp1
);
1984 riscv_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
1986 else if (invert_ptr
== 0)
1988 rtx inv_target
= riscv_force_binary (GET_MODE (target
),
1989 inv_code
, cmp0
, cmp1
);
1990 riscv_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
1994 *invert_ptr
= !*invert_ptr
;
1995 riscv_emit_binary (inv_code
, target
, cmp0
, cmp1
);
2000 /* Return a register that is zero iff CMP0 and CMP1 are equal.
2001 The register will have the same mode as CMP0. */
2004 riscv_zero_if_equal (rtx cmp0
, rtx cmp1
)
2006 if (cmp1
== const0_rtx
)
2009 return expand_binop (GET_MODE (cmp0
), sub_optab
,
2010 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
2013 /* Sign- or zero-extend OP0 and OP1 for integer comparisons. */
2016 riscv_extend_comparands (rtx_code code
, rtx
*op0
, rtx
*op1
)
2018 /* Comparisons consider all XLEN bits, so extend sub-XLEN values. */
2019 if (GET_MODE_SIZE (word_mode
) > GET_MODE_SIZE (GET_MODE (*op0
)))
2021 /* It is more profitable to zero-extend QImode values. But not if the
2022 first operand has already been sign-extended, and the second one is
2023 is a constant or has already been sign-extended also. */
2024 if (unsigned_condition (code
) == code
2025 && (GET_MODE (*op0
) == QImode
2026 && ! (GET_CODE (*op0
) == SUBREG
2027 && SUBREG_PROMOTED_VAR_P (*op0
)
2028 && SUBREG_PROMOTED_SIGNED_P (*op0
)
2029 && (CONST_INT_P (*op1
)
2030 || (GET_CODE (*op1
) == SUBREG
2031 && SUBREG_PROMOTED_VAR_P (*op1
)
2032 && SUBREG_PROMOTED_SIGNED_P (*op1
))))))
2034 *op0
= gen_rtx_ZERO_EXTEND (word_mode
, *op0
);
2035 if (CONST_INT_P (*op1
))
2036 *op1
= GEN_INT ((uint8_t) INTVAL (*op1
));
2038 *op1
= gen_rtx_ZERO_EXTEND (word_mode
, *op1
);
2042 *op0
= gen_rtx_SIGN_EXTEND (word_mode
, *op0
);
2043 if (*op1
!= const0_rtx
)
2044 *op1
= gen_rtx_SIGN_EXTEND (word_mode
, *op1
);
2049 /* Convert a comparison into something that can be used in a branch. On
2050 entry, *OP0 and *OP1 are the values being compared and *CODE is the code
2051 used to compare them. Update them to describe the final comparison. */
2054 riscv_emit_int_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
2056 if (splittable_const_int_operand (*op1
, VOIDmode
))
2058 HOST_WIDE_INT rhs
= INTVAL (*op1
);
2060 if (*code
== EQ
|| *code
== NE
)
2062 /* Convert e.g. OP0 == 2048 into OP0 - 2048 == 0. */
2063 if (SMALL_OPERAND (-rhs
))
2065 *op0
= riscv_force_binary (GET_MODE (*op0
), PLUS
, *op0
,
2072 static const enum rtx_code mag_comparisons
[][2] = {
2073 {LEU
, LTU
}, {GTU
, GEU
}, {LE
, LT
}, {GT
, GE
}
2076 /* Convert e.g. (OP0 <= 0xFFF) into (OP0 < 0x1000). */
2077 for (size_t i
= 0; i
< ARRAY_SIZE (mag_comparisons
); i
++)
2079 HOST_WIDE_INT new_rhs
;
2080 bool increment
= *code
== mag_comparisons
[i
][0];
2081 bool decrement
= *code
== mag_comparisons
[i
][1];
2082 if (!increment
&& !decrement
)
2085 new_rhs
= rhs
+ (increment
? 1 : -1);
2086 if (riscv_integer_cost (new_rhs
) < riscv_integer_cost (rhs
)
2087 && (rhs
< 0) == (new_rhs
< 0))
2089 *op1
= GEN_INT (new_rhs
);
2090 *code
= mag_comparisons
[i
][increment
];
2097 riscv_extend_comparands (*code
, op0
, op1
);
2099 *op0
= force_reg (word_mode
, *op0
);
2100 if (*op1
!= const0_rtx
)
2101 *op1
= force_reg (word_mode
, *op1
);
2104 /* Like riscv_emit_int_compare, but for floating-point comparisons. */
2107 riscv_emit_float_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
2109 rtx tmp0
, tmp1
, cmp_op0
= *op0
, cmp_op1
= *op1
;
2110 enum rtx_code fp_code
= *code
;
2120 /* a == a && b == b */
2121 tmp0
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op0
);
2122 tmp1
= riscv_force_binary (word_mode
, EQ
, cmp_op1
, cmp_op1
);
2123 *op0
= riscv_force_binary (word_mode
, AND
, tmp0
, tmp1
);
2129 /* ordered(a, b) > (a == b) */
2130 *code
= fp_code
== LTGT
? GTU
: EQ
;
2131 tmp0
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op0
);
2132 tmp1
= riscv_force_binary (word_mode
, EQ
, cmp_op1
, cmp_op1
);
2133 *op0
= riscv_force_binary (word_mode
, AND
, tmp0
, tmp1
);
2134 *op1
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op1
);
2137 #define UNORDERED_COMPARISON(CODE, CMP) \
2140 *op0 = gen_reg_rtx (word_mode); \
2141 if (GET_MODE (cmp_op0) == SFmode && TARGET_64BIT) \
2142 emit_insn (gen_f##CMP##_quietsfdi4 (*op0, cmp_op0, cmp_op1)); \
2143 else if (GET_MODE (cmp_op0) == SFmode) \
2144 emit_insn (gen_f##CMP##_quietsfsi4 (*op0, cmp_op0, cmp_op1)); \
2145 else if (GET_MODE (cmp_op0) == DFmode && TARGET_64BIT) \
2146 emit_insn (gen_f##CMP##_quietdfdi4 (*op0, cmp_op0, cmp_op1)); \
2147 else if (GET_MODE (cmp_op0) == DFmode) \
2148 emit_insn (gen_f##CMP##_quietdfsi4 (*op0, cmp_op0, cmp_op1)); \
2150 gcc_unreachable (); \
2151 *op1 = const0_rtx; \
2155 std::swap (cmp_op0
, cmp_op1
);
2158 UNORDERED_COMPARISON(UNGT
, le
)
2161 std::swap (cmp_op0
, cmp_op1
);
2164 UNORDERED_COMPARISON(UNGE
, lt
)
2165 #undef UNORDERED_COMPARISON
2177 /* We have instructions for these cases. */
2178 *op0
= riscv_force_binary (word_mode
, fp_code
, cmp_op0
, cmp_op1
);
2187 /* CODE-compare OP0 and OP1. Store the result in TARGET. */
2190 riscv_expand_int_scc (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
2192 riscv_extend_comparands (code
, &op0
, &op1
);
2193 op0
= force_reg (word_mode
, op0
);
2195 if (code
== EQ
|| code
== NE
)
2197 rtx zie
= riscv_zero_if_equal (op0
, op1
);
2198 riscv_emit_binary (code
, target
, zie
, const0_rtx
);
2201 riscv_emit_int_order_test (code
, 0, target
, op0
, op1
);
2204 /* Like riscv_expand_int_scc, but for floating-point comparisons. */
2207 riscv_expand_float_scc (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
2209 riscv_emit_float_compare (&code
, &op0
, &op1
);
2211 rtx cmp
= riscv_force_binary (word_mode
, code
, op0
, op1
);
2212 riscv_emit_set (target
, lowpart_subreg (SImode
, cmp
, word_mode
));
2215 /* Jump to LABEL if (CODE OP0 OP1) holds. */
2218 riscv_expand_conditional_branch (rtx label
, rtx_code code
, rtx op0
, rtx op1
)
2220 if (FLOAT_MODE_P (GET_MODE (op1
)))
2221 riscv_emit_float_compare (&code
, &op0
, &op1
);
2223 riscv_emit_int_compare (&code
, &op0
, &op1
);
2225 rtx condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
2226 emit_jump_insn (gen_condjump (condition
, label
));
2229 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
2230 least PARM_BOUNDARY bits of alignment, but will be given anything up
2231 to PREFERRED_STACK_BOUNDARY bits if the type requires it. */
2234 riscv_function_arg_boundary (machine_mode mode
, const_tree type
)
2236 unsigned int alignment
;
2238 /* Use natural alignment if the type is not aggregate data. */
2239 if (type
&& !AGGREGATE_TYPE_P (type
))
2240 alignment
= TYPE_ALIGN (TYPE_MAIN_VARIANT (type
));
2242 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
2244 return MIN (PREFERRED_STACK_BOUNDARY
, MAX (PARM_BOUNDARY
, alignment
));
2247 /* If MODE represents an argument that can be passed or returned in
2248 floating-point registers, return the number of registers, else 0. */
2251 riscv_pass_mode_in_fpr_p (machine_mode mode
)
2253 if (GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FP_ARG
)
2255 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2258 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
2267 HOST_WIDE_INT offset
;
2268 } riscv_aggregate_field
;
2270 /* Identify subfields of aggregates that are candidates for passing in
2271 floating-point registers. */
2274 riscv_flatten_aggregate_field (const_tree type
,
2275 riscv_aggregate_field fields
[2],
2276 int n
, HOST_WIDE_INT offset
)
2278 switch (TREE_CODE (type
))
2281 /* Can't handle incomplete types nor sizes that are not fixed. */
2282 if (!COMPLETE_TYPE_P (type
)
2283 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
2284 || !tree_fits_uhwi_p (TYPE_SIZE (type
)))
2287 for (tree f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
2288 if (TREE_CODE (f
) == FIELD_DECL
)
2290 if (!TYPE_P (TREE_TYPE (f
)))
2293 HOST_WIDE_INT pos
= offset
+ int_byte_position (f
);
2294 n
= riscv_flatten_aggregate_field (TREE_TYPE (f
), fields
, n
, pos
);
2302 HOST_WIDE_INT n_elts
;
2303 riscv_aggregate_field subfields
[2];
2304 tree index
= TYPE_DOMAIN (type
);
2305 tree elt_size
= TYPE_SIZE_UNIT (TREE_TYPE (type
));
2306 int n_subfields
= riscv_flatten_aggregate_field (TREE_TYPE (type
),
2307 subfields
, 0, offset
);
2309 /* Can't handle incomplete types nor sizes that are not fixed. */
2310 if (n_subfields
<= 0
2311 || !COMPLETE_TYPE_P (type
)
2312 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
2314 || !TYPE_MAX_VALUE (index
)
2315 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
2316 || !TYPE_MIN_VALUE (index
)
2317 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
2318 || !tree_fits_uhwi_p (elt_size
))
2321 n_elts
= 1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
2322 - tree_to_uhwi (TYPE_MIN_VALUE (index
));
2323 gcc_assert (n_elts
>= 0);
2325 for (HOST_WIDE_INT i
= 0; i
< n_elts
; i
++)
2326 for (int j
= 0; j
< n_subfields
; j
++)
2331 fields
[n
] = subfields
[j
];
2332 fields
[n
++].offset
+= i
* tree_to_uhwi (elt_size
);
2340 /* Complex type need consume 2 field, so n must be 0. */
2344 HOST_WIDE_INT elt_size
= GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (type
)));
2346 if (elt_size
<= UNITS_PER_FP_ARG
)
2348 fields
[0].type
= TREE_TYPE (type
);
2349 fields
[0].offset
= offset
;
2350 fields
[1].type
= TREE_TYPE (type
);
2351 fields
[1].offset
= offset
+ elt_size
;
2361 && ((SCALAR_FLOAT_TYPE_P (type
)
2362 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FP_ARG
)
2363 || (INTEGRAL_TYPE_P (type
)
2364 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_WORD
)))
2366 fields
[n
].type
= type
;
2367 fields
[n
].offset
= offset
;
2375 /* Identify candidate aggregates for passing in floating-point registers.
2376 Candidates have at most two fields after flattening. */
2379 riscv_flatten_aggregate_argument (const_tree type
,
2380 riscv_aggregate_field fields
[2])
2382 if (!type
|| TREE_CODE (type
) != RECORD_TYPE
)
2385 return riscv_flatten_aggregate_field (type
, fields
, 0, 0);
2388 /* See whether TYPE is a record whose fields should be returned in one or
2389 two floating-point registers. If so, populate FIELDS accordingly. */
2392 riscv_pass_aggregate_in_fpr_pair_p (const_tree type
,
2393 riscv_aggregate_field fields
[2])
2395 int n
= riscv_flatten_aggregate_argument (type
, fields
);
2397 for (int i
= 0; i
< n
; i
++)
2398 if (!SCALAR_FLOAT_TYPE_P (fields
[i
].type
))
2401 return n
> 0 ? n
: 0;
2404 /* See whether TYPE is a record whose fields should be returned in one or
2405 floating-point register and one integer register. If so, populate
2406 FIELDS accordingly. */
2409 riscv_pass_aggregate_in_fpr_and_gpr_p (const_tree type
,
2410 riscv_aggregate_field fields
[2])
2412 unsigned num_int
= 0, num_float
= 0;
2413 int n
= riscv_flatten_aggregate_argument (type
, fields
);
2415 for (int i
= 0; i
< n
; i
++)
2417 num_float
+= SCALAR_FLOAT_TYPE_P (fields
[i
].type
);
2418 num_int
+= INTEGRAL_TYPE_P (fields
[i
].type
);
2421 return num_int
== 1 && num_float
== 1;
2424 /* Return the representation of an argument passed or returned in an FPR
2425 when the value has mode VALUE_MODE and the type has TYPE_MODE. The
2426 two modes may be different for structures like:
2428 struct __attribute__((packed)) foo { float f; }
2430 where the SFmode value "f" is passed in REGNO but the struct itself
2431 has mode BLKmode. */
2434 riscv_pass_fpr_single (machine_mode type_mode
, unsigned regno
,
2435 machine_mode value_mode
)
2437 rtx x
= gen_rtx_REG (value_mode
, regno
);
2439 if (type_mode
!= value_mode
)
2441 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
2442 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
2447 /* Pass or return a composite value in the FPR pair REGNO and REGNO + 1.
2448 MODE is the mode of the composite. MODE1 and OFFSET1 are the mode and
2449 byte offset for the first value, likewise MODE2 and OFFSET2 for the
2453 riscv_pass_fpr_pair (machine_mode mode
, unsigned regno1
,
2454 machine_mode mode1
, HOST_WIDE_INT offset1
,
2455 unsigned regno2
, machine_mode mode2
,
2456 HOST_WIDE_INT offset2
)
2458 return gen_rtx_PARALLEL
2461 gen_rtx_EXPR_LIST (VOIDmode
,
2462 gen_rtx_REG (mode1
, regno1
),
2464 gen_rtx_EXPR_LIST (VOIDmode
,
2465 gen_rtx_REG (mode2
, regno2
),
2466 GEN_INT (offset2
))));
2469 /* Fill INFO with information about a single argument, and return an
2470 RTL pattern to pass or return the argument. CUM is the cumulative
2471 state for earlier arguments. MODE is the mode of this argument and
2472 TYPE is its type (if known). NAMED is true if this is a named
2473 (fixed) argument rather than a variable one. RETURN_P is true if
2474 returning the argument, or false if passing the argument. */
2477 riscv_get_arg_info (struct riscv_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
2478 machine_mode mode
, const_tree type
, bool named
,
2481 unsigned num_bytes
, num_words
;
2482 unsigned fpr_base
= return_p
? FP_RETURN
: FP_ARG_FIRST
;
2483 unsigned gpr_base
= return_p
? GP_RETURN
: GP_ARG_FIRST
;
2484 unsigned alignment
= riscv_function_arg_boundary (mode
, type
);
2486 memset (info
, 0, sizeof (*info
));
2487 info
->gpr_offset
= cum
->num_gprs
;
2488 info
->fpr_offset
= cum
->num_fprs
;
2492 riscv_aggregate_field fields
[2];
2493 unsigned fregno
= fpr_base
+ info
->fpr_offset
;
2494 unsigned gregno
= gpr_base
+ info
->gpr_offset
;
2496 /* Pass one- or two-element floating-point aggregates in FPRs. */
2497 if ((info
->num_fprs
= riscv_pass_aggregate_in_fpr_pair_p (type
, fields
))
2498 && info
->fpr_offset
+ info
->num_fprs
<= MAX_ARGS_IN_REGISTERS
)
2499 switch (info
->num_fprs
)
2502 return riscv_pass_fpr_single (mode
, fregno
,
2503 TYPE_MODE (fields
[0].type
));
2506 return riscv_pass_fpr_pair (mode
, fregno
,
2507 TYPE_MODE (fields
[0].type
),
2510 TYPE_MODE (fields
[1].type
),
2517 /* Pass real and complex floating-point numbers in FPRs. */
2518 if ((info
->num_fprs
= riscv_pass_mode_in_fpr_p (mode
))
2519 && info
->fpr_offset
+ info
->num_fprs
<= MAX_ARGS_IN_REGISTERS
)
2520 switch (GET_MODE_CLASS (mode
))
2523 return gen_rtx_REG (mode
, fregno
);
2525 case MODE_COMPLEX_FLOAT
:
2526 return riscv_pass_fpr_pair (mode
, fregno
, GET_MODE_INNER (mode
), 0,
2527 fregno
+ 1, GET_MODE_INNER (mode
),
2528 GET_MODE_UNIT_SIZE (mode
));
2534 /* Pass structs with one float and one integer in an FPR and a GPR. */
2535 if (riscv_pass_aggregate_in_fpr_and_gpr_p (type
, fields
)
2536 && info
->gpr_offset
< MAX_ARGS_IN_REGISTERS
2537 && info
->fpr_offset
< MAX_ARGS_IN_REGISTERS
)
2542 if (!SCALAR_FLOAT_TYPE_P (fields
[0].type
))
2543 std::swap (fregno
, gregno
);
2545 return riscv_pass_fpr_pair (mode
, fregno
, TYPE_MODE (fields
[0].type
),
2547 gregno
, TYPE_MODE (fields
[1].type
),
2552 /* Work out the size of the argument. */
2553 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
2554 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2556 /* Doubleword-aligned varargs start on an even register boundary. */
2557 if (!named
&& num_bytes
!= 0 && alignment
> BITS_PER_WORD
)
2558 info
->gpr_offset
+= info
->gpr_offset
& 1;
2560 /* Partition the argument between registers and stack. */
2562 info
->num_gprs
= MIN (num_words
, MAX_ARGS_IN_REGISTERS
- info
->gpr_offset
);
2563 info
->stack_p
= (num_words
- info
->num_gprs
) != 0;
2565 if (info
->num_gprs
|| return_p
)
2566 return gen_rtx_REG (mode
, gpr_base
+ info
->gpr_offset
);
2571 /* Implement TARGET_FUNCTION_ARG. */
2574 riscv_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
2575 const_tree type
, bool named
)
2577 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2578 struct riscv_arg_info info
;
2580 if (mode
== VOIDmode
)
2583 return riscv_get_arg_info (&info
, cum
, mode
, type
, named
, false);
2586 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
2589 riscv_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
2590 const_tree type
, bool named
)
2592 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2593 struct riscv_arg_info info
;
2595 riscv_get_arg_info (&info
, cum
, mode
, type
, named
, false);
2597 /* Advance the register count. This has the effect of setting
2598 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
2599 argument required us to skip the final GPR and pass the whole
2600 argument on the stack. */
2601 cum
->num_fprs
= info
.fpr_offset
+ info
.num_fprs
;
2602 cum
->num_gprs
= info
.gpr_offset
+ info
.num_gprs
;
2605 /* Implement TARGET_ARG_PARTIAL_BYTES. */
2608 riscv_arg_partial_bytes (cumulative_args_t cum
,
2609 machine_mode mode
, tree type
, bool named
)
2611 struct riscv_arg_info arg
;
2613 riscv_get_arg_info (&arg
, get_cumulative_args (cum
), mode
, type
, named
, false);
2614 return arg
.stack_p
? arg
.num_gprs
* UNITS_PER_WORD
: 0;
2617 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
2618 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
2619 VALTYPE is null and MODE is the mode of the return value. */
2622 riscv_function_value (const_tree type
, const_tree func
, machine_mode mode
)
2624 struct riscv_arg_info info
;
2625 CUMULATIVE_ARGS args
;
2629 int unsigned_p
= TYPE_UNSIGNED (type
);
2631 mode
= TYPE_MODE (type
);
2633 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
2634 return values, promote the mode here too. */
2635 mode
= promote_function_mode (type
, mode
, &unsigned_p
, func
, 1);
2638 memset (&args
, 0, sizeof args
);
2639 return riscv_get_arg_info (&info
, &args
, mode
, type
, true, true);
2642 /* Implement TARGET_PASS_BY_REFERENCE. */
2645 riscv_pass_by_reference (cumulative_args_t cum_v
, machine_mode mode
,
2646 const_tree type
, bool named
)
2648 HOST_WIDE_INT size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
2649 struct riscv_arg_info info
;
2650 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2652 /* ??? std_gimplify_va_arg_expr passes NULL for cum. Fortunately, we
2653 never pass variadic arguments in floating-point registers, so we can
2654 avoid the call to riscv_get_arg_info in this case. */
2657 /* Don't pass by reference if we can use a floating-point register. */
2658 riscv_get_arg_info (&info
, cum
, mode
, type
, named
, false);
2663 /* Pass by reference if the data do not fit in two integer registers. */
2664 return !IN_RANGE (size
, 0, 2 * UNITS_PER_WORD
);
2667 /* Implement TARGET_RETURN_IN_MEMORY. */
2670 riscv_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
2672 CUMULATIVE_ARGS args
;
2673 cumulative_args_t cum
= pack_cumulative_args (&args
);
2675 /* The rules for returning in memory are the same as for passing the
2676 first named argument by reference. */
2677 memset (&args
, 0, sizeof args
);
2678 return riscv_pass_by_reference (cum
, TYPE_MODE (type
), type
, true);
2681 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
2684 riscv_setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
2685 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
2688 CUMULATIVE_ARGS local_cum
;
2691 /* The caller has advanced CUM up to, but not beyond, the last named
2692 argument. Advance a local copy of CUM past the last "real" named
2693 argument, to find out how many registers are left over. */
2694 local_cum
= *get_cumulative_args (cum
);
2695 riscv_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
, 1);
2697 /* Found out how many registers we need to save. */
2698 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
2700 if (!no_rtl
&& gp_saved
> 0)
2702 rtx ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
2703 REG_PARM_STACK_SPACE (cfun
->decl
)
2704 - gp_saved
* UNITS_PER_WORD
);
2705 rtx mem
= gen_frame_mem (BLKmode
, ptr
);
2706 set_mem_alias_set (mem
, get_varargs_alias_set ());
2708 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
2711 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
2712 cfun
->machine
->varargs_size
= gp_saved
* UNITS_PER_WORD
;
2715 /* Handle an attribute requiring a FUNCTION_DECL;
2716 arguments as in struct attribute_spec.handler. */
2718 riscv_handle_fndecl_attribute (tree
*node
, tree name
,
2719 tree args ATTRIBUTE_UNUSED
,
2720 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2722 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2724 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
2726 *no_add_attrs
= true;
2732 /* Verify type based attributes. NODE is the what the attribute is being
2733 applied to. NAME is the attribute name. ARGS are the attribute args.
2734 FLAGS gives info about the context. NO_ADD_ATTRS should be set to true if
2735 the attribute should be ignored. */
2738 riscv_handle_type_attribute (tree
*node ATTRIBUTE_UNUSED
, tree name
, tree args
,
2739 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2741 /* Check for an argument. */
2742 if (is_attribute_p ("interrupt", name
))
2746 tree cst
= TREE_VALUE (args
);
2749 if (TREE_CODE (cst
) != STRING_CST
)
2751 warning (OPT_Wattributes
,
2752 "%qE attribute requires a string argument",
2754 *no_add_attrs
= true;
2758 string
= TREE_STRING_POINTER (cst
);
2759 if (strcmp (string
, "user") && strcmp (string
, "supervisor")
2760 && strcmp (string
, "machine"))
2762 warning (OPT_Wattributes
,
2763 "argument to %qE attribute is not \"user\", \"supervisor\", or \"machine\"",
2765 *no_add_attrs
= true;
2773 /* Return true if function TYPE is an interrupt function. */
2775 riscv_interrupt_type_p (tree type
)
2777 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
2780 /* Return true if FUNC is a naked function. */
2782 riscv_naked_function_p (tree func
)
2784 tree func_decl
= func
;
2785 if (func
== NULL_TREE
)
2786 func_decl
= current_function_decl
;
2787 return NULL_TREE
!= lookup_attribute ("naked", DECL_ATTRIBUTES (func_decl
));
2790 /* Implement TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS. */
2792 riscv_allocate_stack_slots_for_args ()
2794 /* Naked functions should not allocate stack slots for arguments. */
2795 return !riscv_naked_function_p (current_function_decl
);
2798 /* Implement TARGET_WARN_FUNC_RETURN. */
2800 riscv_warn_func_return (tree decl
)
2802 /* Naked functions are implemented entirely in assembly, including the
2803 return sequence, so suppress warnings about this. */
2804 return !riscv_naked_function_p (decl
);
2807 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
2810 riscv_va_start (tree valist
, rtx nextarg
)
2812 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
2813 std_expand_builtin_va_start (valist
, nextarg
);
2816 /* Make ADDR suitable for use as a call or sibcall target. */
2819 riscv_legitimize_call_address (rtx addr
)
2821 if (!call_insn_operand (addr
, VOIDmode
))
2823 rtx reg
= RISCV_PROLOGUE_TEMP (Pmode
);
2824 riscv_emit_move (reg
, addr
);
2830 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
2831 Assume that the areas do not overlap. */
2834 riscv_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
2836 HOST_WIDE_INT offset
, delta
;
2837 unsigned HOST_WIDE_INT bits
;
2839 enum machine_mode mode
;
2842 bits
= MAX (BITS_PER_UNIT
,
2843 MIN (BITS_PER_WORD
, MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
))));
2845 mode
= mode_for_size (bits
, MODE_INT
, 0).require ();
2846 delta
= bits
/ BITS_PER_UNIT
;
2848 /* Allocate a buffer for the temporary registers. */
2849 regs
= XALLOCAVEC (rtx
, length
/ delta
);
2851 /* Load as many BITS-sized chunks as possible. Use a normal load if
2852 the source has enough alignment, otherwise use left/right pairs. */
2853 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
2855 regs
[i
] = gen_reg_rtx (mode
);
2856 riscv_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
2859 /* Copy the chunks to the destination. */
2860 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
2861 riscv_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
2863 /* Mop up any left-over bytes. */
2864 if (offset
< length
)
2866 src
= adjust_address (src
, BLKmode
, offset
);
2867 dest
= adjust_address (dest
, BLKmode
, offset
);
2868 move_by_pieces (dest
, src
, length
- offset
,
2869 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
2873 /* Helper function for doing a loop-based block operation on memory
2874 reference MEM. Each iteration of the loop will operate on LENGTH
2877 Create a new base register for use within the loop and point it to
2878 the start of MEM. Create a new memory reference that uses this
2879 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
2882 riscv_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
2883 rtx
*loop_reg
, rtx
*loop_mem
)
2885 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
2887 /* Although the new mem does not refer to a known location,
2888 it does keep up to LENGTH bytes of alignment. */
2889 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
2890 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
2893 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
2894 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
2895 the memory regions do not overlap. */
2898 riscv_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
2899 HOST_WIDE_INT bytes_per_iter
)
2901 rtx label
, src_reg
, dest_reg
, final_src
, test
;
2902 HOST_WIDE_INT leftover
;
2904 leftover
= length
% bytes_per_iter
;
2907 /* Create registers and memory references for use within the loop. */
2908 riscv_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
2909 riscv_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
2911 /* Calculate the value that SRC_REG should have after the last iteration
2913 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
2916 /* Emit the start of the loop. */
2917 label
= gen_label_rtx ();
2920 /* Emit the loop body. */
2921 riscv_block_move_straight (dest
, src
, bytes_per_iter
);
2923 /* Move on to the next block. */
2924 riscv_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
2925 riscv_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
2927 /* Emit the loop condition. */
2928 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
2929 if (Pmode
== DImode
)
2930 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
2932 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
2934 /* Mop up any left-over bytes. */
2936 riscv_block_move_straight (dest
, src
, leftover
);
2938 emit_insn(gen_nop ());
2941 /* Expand a movmemsi instruction, which copies LENGTH bytes from
2942 memory reference SRC to memory reference DEST. */
2945 riscv_expand_block_move (rtx dest
, rtx src
, rtx length
)
2947 if (CONST_INT_P (length
))
2949 HOST_WIDE_INT factor
, align
;
2951 align
= MIN (MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), BITS_PER_WORD
);
2952 factor
= BITS_PER_WORD
/ align
;
2954 if (optimize_function_for_size_p (cfun
)
2955 && INTVAL (length
) * factor
* UNITS_PER_WORD
> MOVE_RATIO (false))
2958 if (INTVAL (length
) <= RISCV_MAX_MOVE_BYTES_STRAIGHT
/ factor
)
2960 riscv_block_move_straight (dest
, src
, INTVAL (length
));
2963 else if (optimize
&& align
>= BITS_PER_WORD
)
2965 unsigned min_iter_words
2966 = RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER
/ UNITS_PER_WORD
;
2967 unsigned iter_words
= min_iter_words
;
2968 HOST_WIDE_INT bytes
= INTVAL (length
), words
= bytes
/ UNITS_PER_WORD
;
2970 /* Lengthen the loop body if it shortens the tail. */
2971 for (unsigned i
= min_iter_words
; i
< min_iter_words
* 2 - 1; i
++)
2973 unsigned cur_cost
= iter_words
+ words
% iter_words
;
2974 unsigned new_cost
= i
+ words
% i
;
2975 if (new_cost
<= cur_cost
)
2979 riscv_block_move_loop (dest
, src
, bytes
, iter_words
* UNITS_PER_WORD
);
2986 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
2987 in context CONTEXT. HI_RELOC indicates a high-part reloc. */
2990 riscv_print_operand_reloc (FILE *file
, rtx op
, bool hi_reloc
)
2994 switch (riscv_classify_symbolic_expression (op
))
2996 case SYMBOL_ABSOLUTE
:
2997 reloc
= hi_reloc
? "%hi" : "%lo";
3001 reloc
= hi_reloc
? "%pcrel_hi" : "%pcrel_lo";
3005 reloc
= hi_reloc
? "%tprel_hi" : "%tprel_lo";
3012 fprintf (file
, "%s(", reloc
);
3013 output_addr_const (file
, riscv_strip_unspec_address (op
));
3017 /* Return true if the .AQ suffix should be added to an AMO to implement the
3018 acquire portion of memory model MODEL. */
3021 riscv_memmodel_needs_amo_acquire (enum memmodel model
)
3025 case MEMMODEL_ACQ_REL
:
3026 case MEMMODEL_SEQ_CST
:
3027 case MEMMODEL_SYNC_SEQ_CST
:
3028 case MEMMODEL_ACQUIRE
:
3029 case MEMMODEL_CONSUME
:
3030 case MEMMODEL_SYNC_ACQUIRE
:
3033 case MEMMODEL_RELEASE
:
3034 case MEMMODEL_SYNC_RELEASE
:
3035 case MEMMODEL_RELAXED
:
3043 /* Return true if a FENCE should be emitted to before a memory access to
3044 implement the release portion of memory model MODEL. */
3047 riscv_memmodel_needs_release_fence (enum memmodel model
)
3051 case MEMMODEL_ACQ_REL
:
3052 case MEMMODEL_SEQ_CST
:
3053 case MEMMODEL_SYNC_SEQ_CST
:
3054 case MEMMODEL_RELEASE
:
3055 case MEMMODEL_SYNC_RELEASE
:
3058 case MEMMODEL_ACQUIRE
:
3059 case MEMMODEL_CONSUME
:
3060 case MEMMODEL_SYNC_ACQUIRE
:
3061 case MEMMODEL_RELAXED
:
3069 /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are:
3071 'h' Print the high-part relocation associated with OP, after stripping
3073 'R' Print the low-part relocation associated with OP.
3074 'C' Print the integer branch condition for comparison OP.
3075 'A' Print the atomic operation suffix for memory model OP.
3076 'F' Print a FENCE if the memory model requires a release.
3077 'z' Print x0 if OP is zero, otherwise print OP normally.
3078 'i' Print i if the operand is not a register. */
3081 riscv_print_operand (FILE *file
, rtx op
, int letter
)
3083 machine_mode mode
= GET_MODE (op
);
3084 enum rtx_code code
= GET_CODE (op
);
3091 riscv_print_operand_reloc (file
, op
, true);
3095 riscv_print_operand_reloc (file
, op
, false);
3099 /* The RTL names match the instruction names. */
3100 fputs (GET_RTX_NAME (code
), file
);
3104 if (riscv_memmodel_needs_amo_acquire ((enum memmodel
) INTVAL (op
)))
3105 fputs (".aq", file
);
3109 if (riscv_memmodel_needs_release_fence ((enum memmodel
) INTVAL (op
)))
3110 fputs ("fence iorw,ow; ", file
);
3122 if (letter
&& letter
!= 'z')
3123 output_operand_lossage ("invalid use of '%%%c'", letter
);
3124 fprintf (file
, "%s", reg_names
[REGNO (op
)]);
3128 if (letter
&& letter
!= 'z')
3129 output_operand_lossage ("invalid use of '%%%c'", letter
);
3131 output_address (mode
, XEXP (op
, 0));
3135 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
3136 fputs (reg_names
[GP_REG_FIRST
], file
);
3137 else if (letter
&& letter
!= 'z')
3138 output_operand_lossage ("invalid use of '%%%c'", letter
);
3140 output_addr_const (file
, riscv_strip_unspec_address (op
));
3146 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
3149 riscv_print_operand_address (FILE *file
, machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
3151 struct riscv_address_info addr
;
3153 if (riscv_classify_address (&addr
, x
, word_mode
, true))
3157 riscv_print_operand (file
, addr
.offset
, 0);
3158 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
3161 case ADDRESS_LO_SUM
:
3162 riscv_print_operand_reloc (file
, addr
.offset
, false);
3163 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
3166 case ADDRESS_CONST_INT
:
3167 output_addr_const (file
, x
);
3168 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
3171 case ADDRESS_SYMBOLIC
:
3172 output_addr_const (file
, riscv_strip_unspec_address (x
));
3179 riscv_size_ok_for_small_data_p (int size
)
3181 return g_switch_value
&& IN_RANGE (size
, 1, g_switch_value
);
3184 /* Return true if EXP should be placed in the small data section. */
3187 riscv_in_small_data_p (const_tree x
)
3189 if (TREE_CODE (x
) == STRING_CST
|| TREE_CODE (x
) == FUNCTION_DECL
)
3192 if (TREE_CODE (x
) == VAR_DECL
&& DECL_SECTION_NAME (x
))
3194 const char *sec
= DECL_SECTION_NAME (x
);
3195 return strcmp (sec
, ".sdata") == 0 || strcmp (sec
, ".sbss") == 0;
3198 return riscv_size_ok_for_small_data_p (int_size_in_bytes (TREE_TYPE (x
)));
3201 /* Switch to the appropriate section for output of DECL. */
3204 riscv_select_section (tree decl
, int reloc
,
3205 unsigned HOST_WIDE_INT align
)
3207 switch (categorize_decl_for_section (decl
, reloc
))
3209 case SECCAT_SRODATA
:
3210 return get_named_section (decl
, ".srodata", reloc
);
3213 return default_elf_select_section (decl
, reloc
, align
);
3217 /* Return a section for X, handling small data. */
3220 riscv_elf_select_rtx_section (machine_mode mode
, rtx x
,
3221 unsigned HOST_WIDE_INT align
)
3223 section
*s
= default_elf_select_rtx_section (mode
, x
, align
);
3225 if (riscv_size_ok_for_small_data_p (GET_MODE_SIZE (mode
)))
3227 if (strncmp (s
->named
.name
, ".rodata.cst", strlen (".rodata.cst")) == 0)
3229 /* Rename .rodata.cst* to .srodata.cst*. */
3230 char *name
= (char *) alloca (strlen (s
->named
.name
) + 2);
3231 sprintf (name
, ".s%s", s
->named
.name
+ 1);
3232 return get_section (name
, s
->named
.common
.flags
, NULL
);
3235 if (s
== data_section
)
3236 return sdata_section
;
3242 /* Make the last instruction frame-related and note that it performs
3243 the operation described by FRAME_PATTERN. */
3246 riscv_set_frame_expr (rtx frame_pattern
)
3250 insn
= get_last_insn ();
3251 RTX_FRAME_RELATED_P (insn
) = 1;
3252 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
3257 /* Return a frame-related rtx that stores REG at MEM.
3258 REG must be a single register. */
3261 riscv_frame_set (rtx mem
, rtx reg
)
3263 rtx set
= gen_rtx_SET (mem
, reg
);
3264 RTX_FRAME_RELATED_P (set
) = 1;
3268 /* Return true if the current function must save register REGNO. */
3271 riscv_save_reg_p (unsigned int regno
)
3273 bool call_saved
= !global_regs
[regno
] && !call_used_regs
[regno
];
3274 bool might_clobber
= crtl
->saves_all_registers
3275 || df_regs_ever_live_p (regno
);
3277 if (call_saved
&& might_clobber
)
3280 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
3283 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
3286 /* If this is an interrupt handler, then must save extra registers. */
3287 if (cfun
->machine
->interrupt_handler_p
)
3289 /* zero register is always zero. */
3290 if (regno
== GP_REG_FIRST
)
3293 /* The function will return the stack pointer to its original value. */
3294 if (regno
== STACK_POINTER_REGNUM
)
3297 /* By convention, we assume that gp and tp are safe. */
3298 if (regno
== GP_REGNUM
|| regno
== THREAD_POINTER_REGNUM
)
3301 /* We must save every register used in this function. If this is not a
3302 leaf function, then we must save all temporary registers. */
3303 if (df_regs_ever_live_p (regno
)
3304 || (!crtl
->is_leaf
&& call_used_regs
[regno
]))
3311 /* Determine whether to call GPR save/restore routines. */
3313 riscv_use_save_libcall (const struct riscv_frame_info
*frame
)
3315 if (!TARGET_SAVE_RESTORE
|| crtl
->calls_eh_return
|| frame_pointer_needed
3316 || cfun
->machine
->interrupt_handler_p
)
3319 return frame
->save_libcall_adjustment
!= 0;
3322 /* Determine which GPR save/restore routine to call. */
3325 riscv_save_libcall_count (unsigned mask
)
3327 for (unsigned n
= GP_REG_LAST
; n
> GP_REG_FIRST
; n
--)
3328 if (BITSET_P (mask
, n
))
3329 return CALLEE_SAVED_REG_NUMBER (n
) + 1;
3333 /* Populate the current function's riscv_frame_info structure.
3335 RISC-V stack frames grown downward. High addresses are at the top.
3337 +-------------------------------+
3339 | incoming stack arguments |
3341 +-------------------------------+ <-- incoming stack pointer
3343 | callee-allocated save area |
3344 | for arguments that are |
3345 | split between registers and |
3348 +-------------------------------+ <-- arg_pointer_rtx
3350 | callee-allocated save area |
3351 | for register varargs |
3353 +-------------------------------+ <-- hard_frame_pointer_rtx;
3354 | | stack_pointer_rtx + gp_sp_offset
3355 | GPR save area | + UNITS_PER_WORD
3357 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
3358 | | + UNITS_PER_HWVALUE
3361 +-------------------------------+ <-- frame_pointer_rtx (virtual)
3365 P +-------------------------------+
3367 | outgoing stack arguments |
3369 +-------------------------------+ <-- stack_pointer_rtx
3371 Dynamic stack allocations such as alloca insert data at point P.
3372 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
3373 hard_frame_pointer_rtx unchanged. */
3375 static HOST_WIDE_INT
riscv_first_stack_step (struct riscv_frame_info
*frame
);
3378 riscv_compute_frame_info (void)
3380 struct riscv_frame_info
*frame
;
3381 HOST_WIDE_INT offset
;
3382 bool interrupt_save_t1
= false;
3383 unsigned int regno
, i
, num_x_saved
= 0, num_f_saved
= 0;
3385 frame
= &cfun
->machine
->frame
;
3387 /* In an interrupt function, if we have a large frame, then we need to
3388 save/restore t1. We check for this before clearing the frame struct. */
3389 if (cfun
->machine
->interrupt_handler_p
)
3391 HOST_WIDE_INT step1
= riscv_first_stack_step (frame
);
3392 if (! SMALL_OPERAND (frame
->total_size
- step1
))
3393 interrupt_save_t1
= true;
3396 memset (frame
, 0, sizeof (*frame
));
3398 if (!cfun
->machine
->naked_p
)
3400 /* Find out which GPRs we need to save. */
3401 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3402 if (riscv_save_reg_p (regno
)
3403 || (interrupt_save_t1
&& (regno
== T1_REGNUM
)))
3404 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
), num_x_saved
++;
3406 /* If this function calls eh_return, we must also save and restore the
3407 EH data registers. */
3408 if (crtl
->calls_eh_return
)
3409 for (i
= 0; (regno
= EH_RETURN_DATA_REGNO (i
)) != INVALID_REGNUM
; i
++)
3410 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
), num_x_saved
++;
3412 /* Find out which FPRs we need to save. This loop must iterate over
3413 the same space as its companion in riscv_for_each_saved_reg. */
3414 if (TARGET_HARD_FLOAT
)
3415 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
3416 if (riscv_save_reg_p (regno
))
3417 frame
->fmask
|= 1 << (regno
- FP_REG_FIRST
), num_f_saved
++;
3420 /* At the bottom of the frame are any outgoing stack arguments. */
3421 offset
= RISCV_STACK_ALIGN (crtl
->outgoing_args_size
);
3422 /* Next are local stack variables. */
3423 offset
+= RISCV_STACK_ALIGN (get_frame_size ());
3424 /* The virtual frame pointer points above the local variables. */
3425 frame
->frame_pointer_offset
= offset
;
3426 /* Next are the callee-saved FPRs. */
3428 offset
+= RISCV_STACK_ALIGN (num_f_saved
* UNITS_PER_FP_REG
);
3429 frame
->fp_sp_offset
= offset
- UNITS_PER_FP_REG
;
3430 /* Next are the callee-saved GPRs. */
3433 unsigned x_save_size
= RISCV_STACK_ALIGN (num_x_saved
* UNITS_PER_WORD
);
3434 unsigned num_save_restore
= 1 + riscv_save_libcall_count (frame
->mask
);
3436 /* Only use save/restore routines if they don't alter the stack size. */
3437 if (RISCV_STACK_ALIGN (num_save_restore
* UNITS_PER_WORD
) == x_save_size
)
3439 /* Libcall saves/restores 3 registers at once, so we need to
3440 allocate 12 bytes for callee-saved register. */
3442 x_save_size
= 3 * UNITS_PER_WORD
;
3444 frame
->save_libcall_adjustment
= x_save_size
;
3447 offset
+= x_save_size
;
3449 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
3450 /* The hard frame pointer points above the callee-saved GPRs. */
3451 frame
->hard_frame_pointer_offset
= offset
;
3452 /* Above the hard frame pointer is the callee-allocated varags save area. */
3453 offset
+= RISCV_STACK_ALIGN (cfun
->machine
->varargs_size
);
3454 /* Next is the callee-allocated area for pretend stack arguments. */
3455 offset
+= RISCV_STACK_ALIGN (crtl
->args
.pretend_args_size
);
3456 /* Arg pointer must be below pretend args, but must be above alignment
3458 frame
->arg_pointer_offset
= offset
- crtl
->args
.pretend_args_size
;
3459 frame
->total_size
= offset
;
3460 /* Next points the incoming stack pointer and any incoming arguments. */
3462 /* Only use save/restore routines when the GPRs are atop the frame. */
3463 if (frame
->hard_frame_pointer_offset
!= frame
->total_size
)
3464 frame
->save_libcall_adjustment
= 0;
3467 /* Make sure that we're not trying to eliminate to the wrong hard frame
3471 riscv_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
3473 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
3476 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
3477 or argument pointer. TO is either the stack pointer or hard frame
3481 riscv_initial_elimination_offset (int from
, int to
)
3483 HOST_WIDE_INT src
, dest
;
3485 riscv_compute_frame_info ();
3487 if (to
== HARD_FRAME_POINTER_REGNUM
)
3488 dest
= cfun
->machine
->frame
.hard_frame_pointer_offset
;
3489 else if (to
== STACK_POINTER_REGNUM
)
3490 dest
= 0; /* The stack pointer is the base of all offsets, hence 0. */
3494 if (from
== FRAME_POINTER_REGNUM
)
3495 src
= cfun
->machine
->frame
.frame_pointer_offset
;
3496 else if (from
== ARG_POINTER_REGNUM
)
3497 src
= cfun
->machine
->frame
.arg_pointer_offset
;
3504 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
3508 riscv_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
3513 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
3516 /* Emit code to change the current function's return address to
3517 ADDRESS. SCRATCH is available as a scratch register, if needed.
3518 ADDRESS and SCRATCH are both word-mode GPRs. */
3521 riscv_set_return_address (rtx address
, rtx scratch
)
3525 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
3526 slot_address
= riscv_add_offset (scratch
, stack_pointer_rtx
,
3527 cfun
->machine
->frame
.gp_sp_offset
);
3528 riscv_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
3531 /* A function to save or store a register. The first argument is the
3532 register and the second is the stack slot. */
3533 typedef void (*riscv_save_restore_fn
) (rtx
, rtx
);
3535 /* Use FN to save or restore register REGNO. MODE is the register's
3536 mode and OFFSET is the offset of its save slot from the current
3540 riscv_save_restore_reg (machine_mode mode
, int regno
,
3541 HOST_WIDE_INT offset
, riscv_save_restore_fn fn
)
3545 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
, offset
));
3546 fn (gen_rtx_REG (mode
, regno
), mem
);
3549 /* Call FN for each register that is saved by the current function.
3550 SP_OFFSET is the offset of the current stack pointer from the start
3554 riscv_for_each_saved_reg (HOST_WIDE_INT sp_offset
, riscv_save_restore_fn fn
,
3555 bool epilogue
, bool maybe_eh_return
)
3557 HOST_WIDE_INT offset
;
3559 /* Save the link register and s-registers. */
3560 offset
= cfun
->machine
->frame
.gp_sp_offset
- sp_offset
;
3561 for (unsigned int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3562 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
3564 bool handle_reg
= TRUE
;
3566 /* If this is a normal return in a function that calls the eh_return
3567 builtin, then do not restore the eh return data registers as that
3568 would clobber the return value. But we do still need to save them
3569 in the prologue, and restore them for an exception return, so we
3570 need special handling here. */
3571 if (epilogue
&& !maybe_eh_return
&& crtl
->calls_eh_return
)
3573 unsigned int i
, regnum
;
3575 for (i
= 0; (regnum
= EH_RETURN_DATA_REGNO (i
)) != INVALID_REGNUM
;
3577 if (regno
== regnum
)
3585 riscv_save_restore_reg (word_mode
, regno
, offset
, fn
);
3586 offset
-= UNITS_PER_WORD
;
3589 /* This loop must iterate over the same space as its companion in
3590 riscv_compute_frame_info. */
3591 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
3592 for (unsigned int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
3593 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
3595 machine_mode mode
= TARGET_DOUBLE_FLOAT
? DFmode
: SFmode
;
3597 riscv_save_restore_reg (mode
, regno
, offset
, fn
);
3598 offset
-= GET_MODE_SIZE (mode
);
3602 /* Save register REG to MEM. Make the instruction frame-related. */
3605 riscv_save_reg (rtx reg
, rtx mem
)
3607 riscv_emit_move (mem
, reg
);
3608 riscv_set_frame_expr (riscv_frame_set (mem
, reg
));
3611 /* Restore register REG from MEM. */
3614 riscv_restore_reg (rtx reg
, rtx mem
)
3616 rtx insn
= riscv_emit_move (reg
, mem
);
3617 rtx dwarf
= NULL_RTX
;
3618 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
3619 REG_NOTES (insn
) = dwarf
;
3621 RTX_FRAME_RELATED_P (insn
) = 1;
3624 /* Return the code to invoke the GPR save routine. */
3627 riscv_output_gpr_save (unsigned mask
)
3630 unsigned n
= riscv_save_libcall_count (mask
);
3632 ssize_t bytes
= snprintf (s
, sizeof (s
), "call\tt0,__riscv_save_%u", n
);
3633 gcc_assert ((size_t) bytes
< sizeof (s
));
3638 /* For stack frames that can't be allocated with a single ADDI instruction,
3639 compute the best value to initially allocate. It must at a minimum
3640 allocate enough space to spill the callee-saved registers. If TARGET_RVC,
3641 try to pick a value that will allow compression of the register saves
3642 without adding extra instructions. */
3644 static HOST_WIDE_INT
3645 riscv_first_stack_step (struct riscv_frame_info
*frame
)
3647 if (SMALL_OPERAND (frame
->total_size
))
3648 return frame
->total_size
;
3650 HOST_WIDE_INT min_first_step
=
3651 RISCV_STACK_ALIGN (frame
->total_size
- frame
->fp_sp_offset
);
3652 HOST_WIDE_INT max_first_step
= IMM_REACH
/ 2 - PREFERRED_STACK_BOUNDARY
/ 8;
3653 HOST_WIDE_INT min_second_step
= frame
->total_size
- max_first_step
;
3654 gcc_assert (min_first_step
<= max_first_step
);
3656 /* As an optimization, use the least-significant bits of the total frame
3657 size, so that the second adjustment step is just LUI + ADD. */
3658 if (!SMALL_OPERAND (min_second_step
)
3659 && frame
->total_size
% IMM_REACH
< IMM_REACH
/ 2
3660 && frame
->total_size
% IMM_REACH
>= min_first_step
)
3661 return frame
->total_size
% IMM_REACH
;
3665 /* If we need two subtracts, and one is small enough to allow compressed
3666 loads and stores, then put that one first. */
3667 if (IN_RANGE (min_second_step
, 0,
3668 (TARGET_64BIT
? SDSP_REACH
: SWSP_REACH
)))
3669 return MAX (min_second_step
, min_first_step
);
3671 /* If we need LUI + ADDI + ADD for the second adjustment step, then start
3672 with the minimum first step, so that we can get compressed loads and
3674 else if (!SMALL_OPERAND (min_second_step
))
3675 return min_first_step
;
3678 return max_first_step
;
3682 riscv_adjust_libcall_cfi_prologue ()
3684 rtx dwarf
= NULL_RTX
;
3685 rtx adjust_sp_rtx
, reg
, mem
, insn
;
3686 int saved_size
= cfun
->machine
->frame
.save_libcall_adjustment
;
3689 for (int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3690 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
3692 /* The save order is ra, s0, s1, s2 to s11. */
3693 if (regno
== RETURN_ADDR_REGNUM
)
3694 offset
= saved_size
- UNITS_PER_WORD
;
3695 else if (regno
== S0_REGNUM
)
3696 offset
= saved_size
- UNITS_PER_WORD
* 2;
3697 else if (regno
== S1_REGNUM
)
3698 offset
= saved_size
- UNITS_PER_WORD
* 3;
3700 offset
= saved_size
- ((regno
- S2_REGNUM
+ 4) * UNITS_PER_WORD
);
3702 reg
= gen_rtx_REG (SImode
, regno
);
3703 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
3707 insn
= gen_rtx_SET (mem
, reg
);
3708 dwarf
= alloc_reg_note (REG_CFA_OFFSET
, insn
, dwarf
);
3711 /* Debug info for adjust sp. */
3712 adjust_sp_rtx
= gen_add3_insn (stack_pointer_rtx
,
3713 stack_pointer_rtx
, GEN_INT (-saved_size
));
3714 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, adjust_sp_rtx
,
3720 riscv_emit_stack_tie (void)
3722 if (Pmode
== SImode
)
3723 emit_insn (gen_stack_tiesi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
3725 emit_insn (gen_stack_tiedi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
3728 /* Expand the "prologue" pattern. */
3731 riscv_expand_prologue (void)
3733 struct riscv_frame_info
*frame
= &cfun
->machine
->frame
;
3734 HOST_WIDE_INT size
= frame
->total_size
;
3735 unsigned mask
= frame
->mask
;
3738 if (flag_stack_usage_info
)
3739 current_function_static_stack_size
= size
;
3741 if (cfun
->machine
->naked_p
)
3744 /* When optimizing for size, call a subroutine to save the registers. */
3745 if (riscv_use_save_libcall (frame
))
3747 rtx dwarf
= NULL_RTX
;
3748 dwarf
= riscv_adjust_libcall_cfi_prologue ();
3750 frame
->mask
= 0; /* Temporarily fib that we need not save GPRs. */
3751 size
-= frame
->save_libcall_adjustment
;
3752 insn
= emit_insn (gen_gpr_save (GEN_INT (mask
)));
3754 RTX_FRAME_RELATED_P (insn
) = 1;
3755 REG_NOTES (insn
) = dwarf
;
3758 /* Save the registers. */
3759 if ((frame
->mask
| frame
->fmask
) != 0)
3761 HOST_WIDE_INT step1
= MIN (size
, riscv_first_stack_step (frame
));
3763 insn
= gen_add3_insn (stack_pointer_rtx
,
3766 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
3768 riscv_for_each_saved_reg (size
, riscv_save_reg
, false, false);
3771 frame
->mask
= mask
; /* Undo the above fib. */
3773 /* Set up the frame pointer, if we're using one. */
3774 if (frame_pointer_needed
)
3776 insn
= gen_add3_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
,
3777 GEN_INT (frame
->hard_frame_pointer_offset
- size
));
3778 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
3780 riscv_emit_stack_tie ();
3783 /* Allocate the rest of the frame. */
3786 if (SMALL_OPERAND (-size
))
3788 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
3790 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
3794 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), GEN_INT (-size
));
3795 emit_insn (gen_add3_insn (stack_pointer_rtx
,
3797 RISCV_PROLOGUE_TEMP (Pmode
)));
3799 /* Describe the effect of the previous instructions. */
3800 insn
= plus_constant (Pmode
, stack_pointer_rtx
, -size
);
3801 insn
= gen_rtx_SET (stack_pointer_rtx
, insn
);
3802 riscv_set_frame_expr (insn
);
3808 riscv_adjust_libcall_cfi_epilogue ()
3810 rtx dwarf
= NULL_RTX
;
3811 rtx adjust_sp_rtx
, reg
;
3812 int saved_size
= cfun
->machine
->frame
.save_libcall_adjustment
;
3814 /* Debug info for adjust sp. */
3815 adjust_sp_rtx
= gen_add3_insn (stack_pointer_rtx
,
3816 stack_pointer_rtx
, GEN_INT (saved_size
));
3817 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, adjust_sp_rtx
,
3820 for (int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3821 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
3823 reg
= gen_rtx_REG (SImode
, regno
);
3824 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
3830 /* Expand an "epilogue", "sibcall_epilogue", or "eh_return_internal" pattern;
3831 style says which. */
3834 riscv_expand_epilogue (int style
)
3836 /* Split the frame into two. STEP1 is the amount of stack we should
3837 deallocate before restoring the registers. STEP2 is the amount we
3838 should deallocate afterwards.
3840 Start off by assuming that no registers need to be restored. */
3841 struct riscv_frame_info
*frame
= &cfun
->machine
->frame
;
3842 unsigned mask
= frame
->mask
;
3843 HOST_WIDE_INT step1
= frame
->total_size
;
3844 HOST_WIDE_INT step2
= 0;
3845 bool use_restore_libcall
= ((style
== NORMAL_RETURN
)
3846 && riscv_use_save_libcall (frame
));
3847 rtx ra
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
3850 /* We need to add memory barrier to prevent read from deallocated stack. */
3851 bool need_barrier_p
= (get_frame_size ()
3852 + cfun
->machine
->frame
.arg_pointer_offset
) != 0;
3854 if (cfun
->machine
->naked_p
)
3856 gcc_assert (style
== NORMAL_RETURN
);
3858 emit_jump_insn (gen_return ());
3863 if ((style
== NORMAL_RETURN
) && riscv_can_use_return_insn ())
3865 emit_jump_insn (gen_return ());
3869 /* Move past any dynamic stack allocations. */
3870 if (cfun
->calls_alloca
)
3872 /* Emit a barrier to prevent loads from a deallocated stack. */
3873 riscv_emit_stack_tie ();
3874 need_barrier_p
= false;
3876 rtx adjust
= GEN_INT (-frame
->hard_frame_pointer_offset
);
3877 if (!SMALL_OPERAND (INTVAL (adjust
)))
3879 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), adjust
);
3880 adjust
= RISCV_PROLOGUE_TEMP (Pmode
);
3884 gen_add3_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
,
3887 rtx dwarf
= NULL_RTX
;
3888 rtx cfa_adjust_value
= gen_rtx_PLUS (
3889 Pmode
, hard_frame_pointer_rtx
,
3890 GEN_INT (-frame
->hard_frame_pointer_offset
));
3891 rtx cfa_adjust_rtx
= gen_rtx_SET (stack_pointer_rtx
, cfa_adjust_value
);
3892 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, cfa_adjust_rtx
, dwarf
);
3893 RTX_FRAME_RELATED_P (insn
) = 1;
3895 REG_NOTES (insn
) = dwarf
;
3898 /* If we need to restore registers, deallocate as much stack as
3899 possible in the second step without going out of range. */
3900 if ((frame
->mask
| frame
->fmask
) != 0)
3902 step2
= riscv_first_stack_step (frame
);
3906 /* Set TARGET to BASE + STEP1. */
3909 /* Emit a barrier to prevent loads from a deallocated stack. */
3910 riscv_emit_stack_tie ();
3911 need_barrier_p
= false;
3913 /* Get an rtx for STEP1 that we can add to BASE. */
3914 rtx adjust
= GEN_INT (step1
);
3915 if (!SMALL_OPERAND (step1
))
3917 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), adjust
);
3918 adjust
= RISCV_PROLOGUE_TEMP (Pmode
);
3922 gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
, adjust
));
3924 rtx dwarf
= NULL_RTX
;
3925 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
3928 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
3929 RTX_FRAME_RELATED_P (insn
) = 1;
3931 REG_NOTES (insn
) = dwarf
;
3934 if (use_restore_libcall
)
3935 frame
->mask
= 0; /* Temporarily fib that we need not save GPRs. */
3937 /* Restore the registers. */
3938 riscv_for_each_saved_reg (frame
->total_size
- step2
, riscv_restore_reg
,
3939 true, style
== EXCEPTION_RETURN
);
3941 if (use_restore_libcall
)
3943 frame
->mask
= mask
; /* Undo the above fib. */
3944 gcc_assert (step2
>= frame
->save_libcall_adjustment
);
3945 step2
-= frame
->save_libcall_adjustment
;
3949 riscv_emit_stack_tie ();
3951 /* Deallocate the final bit of the frame. */
3954 insn
= emit_insn (gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
3957 rtx dwarf
= NULL_RTX
;
3958 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
3960 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
3961 RTX_FRAME_RELATED_P (insn
) = 1;
3963 REG_NOTES (insn
) = dwarf
;
3966 if (use_restore_libcall
)
3968 rtx dwarf
= riscv_adjust_libcall_cfi_epilogue ();
3969 insn
= emit_insn (gen_gpr_restore (GEN_INT (riscv_save_libcall_count (mask
))));
3970 RTX_FRAME_RELATED_P (insn
) = 1;
3971 REG_NOTES (insn
) = dwarf
;
3973 emit_jump_insn (gen_gpr_restore_return (ra
));
3977 /* Add in the __builtin_eh_return stack adjustment. */
3978 if ((style
== EXCEPTION_RETURN
) && crtl
->calls_eh_return
)
3979 emit_insn (gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
3980 EH_RETURN_STACKADJ_RTX
));
3982 /* Return from interrupt. */
3983 if (cfun
->machine
->interrupt_handler_p
)
3985 enum riscv_privilege_levels mode
= cfun
->machine
->interrupt_mode
;
3987 gcc_assert (mode
!= UNKNOWN_MODE
);
3989 if (mode
== MACHINE_MODE
)
3990 emit_jump_insn (gen_riscv_mret ());
3991 else if (mode
== SUPERVISOR_MODE
)
3992 emit_jump_insn (gen_riscv_sret ());
3994 emit_jump_insn (gen_riscv_uret ());
3996 else if (style
!= SIBCALL_RETURN
)
3997 emit_jump_insn (gen_simple_return_internal (ra
));
4000 /* Implement EPILOGUE_USES. */
4003 riscv_epilogue_uses (unsigned int regno
)
4005 if (regno
== RETURN_ADDR_REGNUM
)
4008 if (epilogue_completed
&& cfun
->machine
->interrupt_handler_p
)
4010 /* An interrupt function restores temp regs, so we must indicate that
4011 they are live at function end. */
4012 if (df_regs_ever_live_p (regno
)
4013 || (!crtl
->is_leaf
&& call_used_regs
[regno
]))
4020 /* Return nonzero if this function is known to have a null epilogue.
4021 This allows the optimizer to omit jumps to jumps if no stack
4025 riscv_can_use_return_insn (void)
4027 return (reload_completed
&& cfun
->machine
->frame
.total_size
== 0
4028 && ! cfun
->machine
->interrupt_handler_p
);
4031 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
4033 When floating-point registers are wider than integer ones, moves between
4034 them must go through memory. */
4037 riscv_secondary_memory_needed (machine_mode mode
, reg_class_t class1
,
4040 return (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
4041 && (class1
== FP_REGS
) != (class2
== FP_REGS
));
4044 /* Implement TARGET_REGISTER_MOVE_COST. */
4047 riscv_register_move_cost (machine_mode mode
,
4048 reg_class_t from
, reg_class_t to
)
4050 return riscv_secondary_memory_needed (mode
, from
, to
) ? 8 : 2;
4053 /* Implement TARGET_HARD_REGNO_NREGS. */
4056 riscv_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
4058 if (FP_REG_P (regno
))
4059 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_REG
- 1) / UNITS_PER_FP_REG
;
4061 /* All other registers are word-sized. */
4062 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4065 /* Implement TARGET_HARD_REGNO_MODE_OK. */
4068 riscv_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
4070 unsigned int nregs
= riscv_hard_regno_nregs (regno
, mode
);
4072 if (GP_REG_P (regno
))
4074 if (!GP_REG_P (regno
+ nregs
- 1))
4077 else if (FP_REG_P (regno
))
4079 if (!FP_REG_P (regno
+ nregs
- 1))
4082 if (GET_MODE_CLASS (mode
) != MODE_FLOAT
4083 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
4086 /* Only use callee-saved registers if a potential callee is guaranteed
4087 to spill the requisite width. */
4088 if (GET_MODE_UNIT_SIZE (mode
) > UNITS_PER_FP_REG
4089 || (!call_used_regs
[regno
]
4090 && GET_MODE_UNIT_SIZE (mode
) > UNITS_PER_FP_ARG
))
4096 /* Require same callee-savedness for all registers. */
4097 for (unsigned i
= 1; i
< nregs
; i
++)
4098 if (call_used_regs
[regno
] != call_used_regs
[regno
+ i
])
4104 /* Implement TARGET_MODES_TIEABLE_P.
4106 Don't allow floating-point modes to be tied, since type punning of
4107 single-precision and double-precision is implementation defined. */
4110 riscv_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
4112 return (mode1
== mode2
4113 || !(GET_MODE_CLASS (mode1
) == MODE_FLOAT
4114 && GET_MODE_CLASS (mode2
) == MODE_FLOAT
));
4117 /* Implement CLASS_MAX_NREGS. */
4119 static unsigned char
4120 riscv_class_max_nregs (reg_class_t rclass
, machine_mode mode
)
4122 if (reg_class_subset_p (FP_REGS
, rclass
))
4123 return riscv_hard_regno_nregs (FP_REG_FIRST
, mode
);
4125 if (reg_class_subset_p (GR_REGS
, rclass
))
4126 return riscv_hard_regno_nregs (GP_REG_FIRST
, mode
);
4131 /* Implement TARGET_MEMORY_MOVE_COST. */
4134 riscv_memory_move_cost (machine_mode mode
, reg_class_t rclass
, bool in
)
4136 return (tune_info
->memory_cost
4137 + memory_move_secondary_cost (mode
, rclass
, in
));
4140 /* Return the number of instructions that can be issued per cycle. */
4143 riscv_issue_rate (void)
4145 return tune_info
->issue_rate
;
4148 /* Implement TARGET_ASM_FILE_START. */
4151 riscv_file_start (void)
4153 default_file_start ();
4155 /* Instruct GAS to generate position-[in]dependent code. */
4156 fprintf (asm_out_file
, "\t.option %spic\n", (flag_pic
? "" : "no"));
4158 /* If the user specifies "-mno-relax" on the command line then disable linker
4159 relaxation in the assembler. */
4161 fprintf (asm_out_file
, "\t.option norelax\n");
4164 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
4165 in order to avoid duplicating too much logic from elsewhere. */
4168 riscv_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
4169 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
4172 rtx this_rtx
, temp1
, temp2
, fnaddr
;
4175 /* Pretend to be a post-reload pass while generating rtl. */
4176 reload_completed
= 1;
4178 /* Mark the end of the (empty) prologue. */
4179 emit_note (NOTE_INSN_PROLOGUE_END
);
4181 /* Determine if we can use a sibcall to call FUNCTION directly. */
4182 fnaddr
= gen_rtx_MEM (FUNCTION_MODE
, XEXP (DECL_RTL (function
), 0));
4184 /* We need two temporary registers in some cases. */
4185 temp1
= gen_rtx_REG (Pmode
, RISCV_PROLOGUE_TEMP_REGNUM
);
4186 temp2
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
4188 /* Find out which register contains the "this" pointer. */
4189 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
4190 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
4192 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
4194 /* Add DELTA to THIS_RTX. */
4197 rtx offset
= GEN_INT (delta
);
4198 if (!SMALL_OPERAND (delta
))
4200 riscv_emit_move (temp1
, offset
);
4203 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
4206 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
4207 if (vcall_offset
!= 0)
4211 /* Set TEMP1 to *THIS_RTX. */
4212 riscv_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
4214 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
4215 addr
= riscv_add_offset (temp2
, temp1
, vcall_offset
);
4217 /* Load the offset and add it to THIS_RTX. */
4218 riscv_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
4219 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
4222 /* Jump to the target function. */
4223 insn
= emit_call_insn (gen_sibcall (fnaddr
, const0_rtx
, NULL
, const0_rtx
));
4224 SIBLING_CALL_P (insn
) = 1;
4226 /* Run just enough of rest_of_compilation. This sequence was
4227 "borrowed" from alpha.c. */
4228 insn
= get_insns ();
4229 split_all_insns_noflow ();
4230 shorten_branches (insn
);
4231 final_start_function (insn
, file
, 1);
4232 final (insn
, file
, 1);
4233 final_end_function ();
4235 /* Clean up the vars set above. Note that final_end_function resets
4236 the global pointer for us. */
4237 reload_completed
= 0;
4240 /* Allocate a chunk of memory for per-function machine-dependent data. */
4242 static struct machine_function
*
4243 riscv_init_machine_status (void)
4245 return ggc_cleared_alloc
<machine_function
> ();
4248 /* Implement TARGET_OPTION_OVERRIDE. */
4251 riscv_option_override (void)
4253 const struct riscv_cpu_info
*cpu
;
4255 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4256 SUBTARGET_OVERRIDE_OPTIONS
;
4259 flag_pcc_struct_return
= 0;
4264 /* The presence of the M extension implies that division instructions
4265 are present, so include them unless explicitly disabled. */
4266 if (TARGET_MUL
&& (target_flags_explicit
& MASK_DIV
) == 0)
4267 target_flags
|= MASK_DIV
;
4268 else if (!TARGET_MUL
&& TARGET_DIV
)
4269 error ("-mdiv requires -march to subsume the %<M%> extension");
4271 /* Likewise floating-point division and square root. */
4272 if (TARGET_HARD_FLOAT
&& (target_flags_explicit
& MASK_FDIV
) == 0)
4273 target_flags
|= MASK_FDIV
;
4275 /* Handle -mtune. */
4276 cpu
= riscv_parse_cpu (riscv_tune_string
? riscv_tune_string
:
4277 RISCV_TUNE_STRING_DEFAULT
);
4278 tune_info
= optimize_size
? &optimize_size_tune_info
: cpu
->tune_info
;
4280 /* Use -mtune's setting for slow_unaligned_access, even when optimizing
4281 for size. For architectures that trap and emulate unaligned accesses,
4282 the performance cost is too great, even for -Os. Similarly, if
4283 -m[no-]strict-align is left unspecified, heed -mtune's advice. */
4284 riscv_slow_unaligned_access_p
= (cpu
->tune_info
->slow_unaligned_access
4285 || TARGET_STRICT_ALIGN
);
4286 if ((target_flags_explicit
& MASK_STRICT_ALIGN
) == 0
4287 && cpu
->tune_info
->slow_unaligned_access
)
4288 target_flags
|= MASK_STRICT_ALIGN
;
4290 /* If the user hasn't specified a branch cost, use the processor's
4292 if (riscv_branch_cost
== 0)
4293 riscv_branch_cost
= tune_info
->branch_cost
;
4295 /* Function to allocate machine-dependent function status. */
4296 init_machine_status
= &riscv_init_machine_status
;
4299 riscv_cmodel
= CM_PIC
;
4301 /* We get better code with explicit relocs for CM_MEDLOW, but
4302 worse code for the others (for now). Pick the best default. */
4303 if ((target_flags_explicit
& MASK_EXPLICIT_RELOCS
) == 0)
4304 if (riscv_cmodel
== CM_MEDLOW
)
4305 target_flags
|= MASK_EXPLICIT_RELOCS
;
4307 /* Require that the ISA supports the requested floating-point ABI. */
4308 if (UNITS_PER_FP_ARG
> (TARGET_HARD_FLOAT
? UNITS_PER_FP_REG
: 0))
4309 error ("requested ABI requires -march to subsume the %qc extension",
4310 UNITS_PER_FP_ARG
> 8 ? 'Q' : (UNITS_PER_FP_ARG
> 4 ? 'D' : 'F'));
4312 if (TARGET_RVE
&& riscv_abi
!= ABI_ILP32E
)
4313 error ("rv32e requires ilp32e ABI");
4315 /* We do not yet support ILP32 on RV64. */
4316 if (BITS_PER_WORD
!= POINTER_SIZE
)
4317 error ("ABI requires -march=rv%d", POINTER_SIZE
);
4319 /* Validate -mpreferred-stack-boundary= value. */
4320 riscv_stack_boundary
= ABI_STACK_BOUNDARY
;
4321 if (riscv_preferred_stack_boundary_arg
)
4323 int min
= ctz_hwi (STACK_BOUNDARY
/ 8);
4326 if (!IN_RANGE (riscv_preferred_stack_boundary_arg
, min
, max
))
4327 error ("-mpreferred-stack-boundary=%d must be between %d and %d",
4328 riscv_preferred_stack_boundary_arg
, min
, max
);
4330 riscv_stack_boundary
= 8 << riscv_preferred_stack_boundary_arg
;
4334 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
4337 riscv_conditional_register_usage (void)
4339 /* We have only x0~x15 on RV32E. */
4342 for (int r
= 16; r
<= 31; r
++)
4346 if (riscv_abi
== ABI_ILP32E
)
4348 for (int r
= 16; r
<= 31; r
++)
4349 call_used_regs
[r
] = 1;
4352 if (!TARGET_HARD_FLOAT
)
4354 for (int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
4355 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
4358 /* In the soft-float ABI, there are no callee-saved FP registers. */
4359 if (UNITS_PER_FP_ARG
== 0)
4361 for (int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
4362 call_used_regs
[regno
] = 1;
4366 /* Return a register priority for hard reg REGNO. */
4369 riscv_register_priority (int regno
)
4371 /* Favor x8-x15/f8-f15 to improve the odds of RVC instruction selection. */
4372 if (TARGET_RVC
&& (IN_RANGE (regno
, GP_REG_FIRST
+ 8, GP_REG_FIRST
+ 15)
4373 || IN_RANGE (regno
, FP_REG_FIRST
+ 8, FP_REG_FIRST
+ 15)))
4379 /* Implement TARGET_TRAMPOLINE_INIT. */
4382 riscv_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
4384 rtx addr
, end_addr
, mem
;
4385 uint32_t trampoline
[4];
4387 HOST_WIDE_INT static_chain_offset
, target_function_offset
;
4389 /* Work out the offsets of the pointers from the start of the
4391 gcc_assert (ARRAY_SIZE (trampoline
) * 4 == TRAMPOLINE_CODE_SIZE
);
4393 /* Get pointers to the beginning and end of the code block. */
4394 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
4395 end_addr
= riscv_force_binary (Pmode
, PLUS
, addr
,
4396 GEN_INT (TRAMPOLINE_CODE_SIZE
));
4399 if (Pmode
== SImode
)
4401 chain_value
= force_reg (Pmode
, chain_value
);
4403 rtx target_function
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
4404 /* lui t2, hi(chain)
4406 addi t2, t2, lo(chain)
4409 unsigned HOST_WIDE_INT lui_hi_chain_code
, lui_hi_func_code
;
4410 unsigned HOST_WIDE_INT lo_chain_code
, lo_func_code
;
4412 rtx uimm_mask
= force_reg (SImode
, gen_int_mode (-IMM_REACH
, SImode
));
4415 rtx imm12_mask
= gen_reg_rtx (SImode
);
4416 emit_insn (gen_one_cmplsi2 (imm12_mask
, uimm_mask
));
4418 rtx fixup_value
= force_reg (SImode
, gen_int_mode (IMM_REACH
/2, SImode
));
4420 /* Gen lui t2, hi(chain). */
4421 rtx hi_chain
= riscv_force_binary (SImode
, PLUS
, chain_value
,
4423 hi_chain
= riscv_force_binary (SImode
, AND
, hi_chain
,
4425 lui_hi_chain_code
= OPCODE_LUI
| (STATIC_CHAIN_REGNUM
<< SHIFT_RD
);
4426 rtx lui_hi_chain
= riscv_force_binary (SImode
, IOR
, hi_chain
,
4427 gen_int_mode (lui_hi_chain_code
, SImode
));
4429 mem
= adjust_address (m_tramp
, SImode
, 0);
4430 riscv_emit_move (mem
, lui_hi_chain
);
4432 /* Gen lui t1, hi(func). */
4433 rtx hi_func
= riscv_force_binary (SImode
, PLUS
, target_function
,
4435 hi_func
= riscv_force_binary (SImode
, AND
, hi_func
,
4437 lui_hi_func_code
= OPCODE_LUI
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RD
);
4438 rtx lui_hi_func
= riscv_force_binary (SImode
, IOR
, hi_func
,
4439 gen_int_mode (lui_hi_func_code
, SImode
));
4441 mem
= adjust_address (m_tramp
, SImode
, 1 * GET_MODE_SIZE (SImode
));
4442 riscv_emit_move (mem
, lui_hi_func
);
4444 /* Gen addi t2, t2, lo(chain). */
4445 rtx lo_chain
= riscv_force_binary (SImode
, AND
, chain_value
,
4447 lo_chain
= riscv_force_binary (SImode
, ASHIFT
, lo_chain
, GEN_INT (20));
4449 lo_chain_code
= OPCODE_ADDI
4450 | (STATIC_CHAIN_REGNUM
<< SHIFT_RD
)
4451 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
);
4453 rtx addi_lo_chain
= riscv_force_binary (SImode
, IOR
, lo_chain
,
4454 force_reg (SImode
, GEN_INT (lo_chain_code
)));
4456 mem
= adjust_address (m_tramp
, SImode
, 2 * GET_MODE_SIZE (SImode
));
4457 riscv_emit_move (mem
, addi_lo_chain
);
4459 /* Gen jr r1, lo(func). */
4460 rtx lo_func
= riscv_force_binary (SImode
, AND
, target_function
,
4462 lo_func
= riscv_force_binary (SImode
, ASHIFT
, lo_func
, GEN_INT (20));
4464 lo_func_code
= OPCODE_JALR
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RS1
);
4466 rtx jr_lo_func
= riscv_force_binary (SImode
, IOR
, lo_func
,
4467 force_reg (SImode
, GEN_INT (lo_func_code
)));
4469 mem
= adjust_address (m_tramp
, SImode
, 3 * GET_MODE_SIZE (SImode
));
4470 riscv_emit_move (mem
, jr_lo_func
);
4474 static_chain_offset
= TRAMPOLINE_CODE_SIZE
;
4475 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
4478 l[wd] t1, target_function_offset(t2)
4479 l[wd] t2, static_chain_offset(t2)
4482 trampoline
[0] = OPCODE_AUIPC
| (STATIC_CHAIN_REGNUM
<< SHIFT_RD
);
4483 trampoline
[1] = (Pmode
== DImode
? OPCODE_LD
: OPCODE_LW
)
4484 | (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RD
)
4485 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
)
4486 | (target_function_offset
<< SHIFT_IMM
);
4487 trampoline
[2] = (Pmode
== DImode
? OPCODE_LD
: OPCODE_LW
)
4488 | (STATIC_CHAIN_REGNUM
<< SHIFT_RD
)
4489 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
)
4490 | (static_chain_offset
<< SHIFT_IMM
);
4491 trampoline
[3] = OPCODE_JALR
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RS1
);
4493 /* Copy the trampoline code. */
4494 for (i
= 0; i
< ARRAY_SIZE (trampoline
); i
++)
4496 mem
= adjust_address (m_tramp
, SImode
, i
* GET_MODE_SIZE (SImode
));
4497 riscv_emit_move (mem
, gen_int_mode (trampoline
[i
], SImode
));
4500 /* Set up the static chain pointer field. */
4501 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
4502 riscv_emit_move (mem
, chain_value
);
4504 /* Set up the target function field. */
4505 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
4506 riscv_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
4509 /* Flush the code part of the trampoline. */
4510 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
4511 emit_insn (gen_clear_cache (addr
, end_addr
));
4514 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
4517 riscv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
4518 tree exp ATTRIBUTE_UNUSED
)
4520 /* Don't use sibcalls when use save-restore routine. */
4521 if (TARGET_SAVE_RESTORE
)
4524 /* Don't use sibcall for naked functions. */
4525 if (cfun
->machine
->naked_p
)
4528 /* Don't use sibcall for interrupt functions. */
4529 if (cfun
->machine
->interrupt_handler_p
)
4535 /* Get the intterupt type, return UNKNOWN_MODE if it's not
4536 interrupt function. */
4537 static enum riscv_privilege_levels
4538 riscv_get_interrupt_type (tree decl
)
4540 gcc_assert (decl
!= NULL_TREE
);
4542 if ((TREE_CODE(decl
) != FUNCTION_DECL
)
4543 || (!riscv_interrupt_type_p (TREE_TYPE (decl
))))
4544 return UNKNOWN_MODE
;
4547 = TREE_VALUE (lookup_attribute ("interrupt",
4548 TYPE_ATTRIBUTES (TREE_TYPE (decl
))));
4550 if (attr_args
&& TREE_CODE (TREE_VALUE (attr_args
)) != VOID_TYPE
)
4552 const char *string
= TREE_STRING_POINTER (TREE_VALUE (attr_args
));
4554 if (!strcmp (string
, "user"))
4556 else if (!strcmp (string
, "supervisor"))
4557 return SUPERVISOR_MODE
;
4558 else /* Must be "machine". */
4559 return MACHINE_MODE
;
4562 /* Interrupt attributes are machine mode by default. */
4563 return MACHINE_MODE
;
4566 /* Implement `TARGET_SET_CURRENT_FUNCTION'. */
4567 /* Sanity cheching for above function attributes. */
4569 riscv_set_current_function (tree decl
)
4571 if (decl
== NULL_TREE
4572 || current_function_decl
== NULL_TREE
4573 || current_function_decl
== error_mark_node
4575 || cfun
->machine
->attributes_checked_p
)
4578 cfun
->machine
->naked_p
= riscv_naked_function_p (decl
);
4579 cfun
->machine
->interrupt_handler_p
4580 = riscv_interrupt_type_p (TREE_TYPE (decl
));
4582 if (cfun
->machine
->naked_p
&& cfun
->machine
->interrupt_handler_p
)
4583 error ("function attributes %qs and %qs are mutually exclusive",
4584 "interrupt", "naked");
4586 if (cfun
->machine
->interrupt_handler_p
)
4588 tree ret
= TREE_TYPE (TREE_TYPE (decl
));
4589 tree args
= TYPE_ARG_TYPES (TREE_TYPE (decl
));
4591 if (TREE_CODE (ret
) != VOID_TYPE
)
4592 error ("%qs function cannot return a value", "interrupt");
4594 if (args
&& TREE_CODE (TREE_VALUE (args
)) != VOID_TYPE
)
4595 error ("%qs function cannot have arguments", "interrupt");
4597 cfun
->machine
->interrupt_mode
= riscv_get_interrupt_type (decl
);
4599 gcc_assert (cfun
->machine
->interrupt_mode
!= UNKNOWN_MODE
);
4602 /* Don't print the above diagnostics more than once. */
4603 cfun
->machine
->attributes_checked_p
= 1;
4606 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
4608 riscv_merge_decl_attributes (tree olddecl
, tree newdecl
)
4610 tree combined_attrs
;
4612 enum riscv_privilege_levels old_interrupt_type
4613 = riscv_get_interrupt_type (olddecl
);
4614 enum riscv_privilege_levels new_interrupt_type
4615 = riscv_get_interrupt_type (newdecl
);
4617 /* Check old and new has same interrupt type. */
4618 if ((old_interrupt_type
!= UNKNOWN_MODE
)
4619 && (new_interrupt_type
!= UNKNOWN_MODE
)
4620 && (old_interrupt_type
!= new_interrupt_type
))
4621 error ("%qs function cannot have different intterupt type.", "interrupt");
4623 /* Create combined attributes. */
4624 combined_attrs
= merge_attributes (DECL_ATTRIBUTES (olddecl
),
4625 DECL_ATTRIBUTES (newdecl
));
4627 return combined_attrs
;
4630 /* Implement TARGET_CANNOT_COPY_INSN_P. */
4633 riscv_cannot_copy_insn_p (rtx_insn
*insn
)
4635 return recog_memoized (insn
) >= 0 && get_attr_cannot_copy (insn
);
4638 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. */
4641 riscv_slow_unaligned_access (machine_mode
, unsigned int)
4643 return riscv_slow_unaligned_access_p
;
4646 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
4649 riscv_can_change_mode_class (machine_mode
, machine_mode
, reg_class_t rclass
)
4651 return !reg_classes_intersect_p (FP_REGS
, rclass
);
4655 /* Implement TARGET_CONSTANT_ALIGNMENT. */
4657 static HOST_WIDE_INT
4658 riscv_constant_alignment (const_tree exp
, HOST_WIDE_INT align
)
4660 if (TREE_CODE (exp
) == STRING_CST
|| TREE_CODE (exp
) == CONSTRUCTOR
)
4661 return MAX (align
, BITS_PER_WORD
);
4665 /* Initialize the GCC target structure. */
4666 #undef TARGET_ASM_ALIGNED_HI_OP
4667 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
4668 #undef TARGET_ASM_ALIGNED_SI_OP
4669 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
4670 #undef TARGET_ASM_ALIGNED_DI_OP
4671 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
4673 #undef TARGET_OPTION_OVERRIDE
4674 #define TARGET_OPTION_OVERRIDE riscv_option_override
4676 #undef TARGET_LEGITIMIZE_ADDRESS
4677 #define TARGET_LEGITIMIZE_ADDRESS riscv_legitimize_address
4679 #undef TARGET_SCHED_ISSUE_RATE
4680 #define TARGET_SCHED_ISSUE_RATE riscv_issue_rate
4682 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
4683 #define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall
4685 #undef TARGET_SET_CURRENT_FUNCTION
4686 #define TARGET_SET_CURRENT_FUNCTION riscv_set_current_function
4688 #undef TARGET_REGISTER_MOVE_COST
4689 #define TARGET_REGISTER_MOVE_COST riscv_register_move_cost
4690 #undef TARGET_MEMORY_MOVE_COST
4691 #define TARGET_MEMORY_MOVE_COST riscv_memory_move_cost
4692 #undef TARGET_RTX_COSTS
4693 #define TARGET_RTX_COSTS riscv_rtx_costs
4694 #undef TARGET_ADDRESS_COST
4695 #define TARGET_ADDRESS_COST riscv_address_cost
4697 #undef TARGET_ASM_FILE_START
4698 #define TARGET_ASM_FILE_START riscv_file_start
4699 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
4700 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
4702 #undef TARGET_EXPAND_BUILTIN_VA_START
4703 #define TARGET_EXPAND_BUILTIN_VA_START riscv_va_start
4705 #undef TARGET_PROMOTE_FUNCTION_MODE
4706 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
4708 #undef TARGET_RETURN_IN_MEMORY
4709 #define TARGET_RETURN_IN_MEMORY riscv_return_in_memory
4711 #undef TARGET_ASM_OUTPUT_MI_THUNK
4712 #define TARGET_ASM_OUTPUT_MI_THUNK riscv_output_mi_thunk
4713 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
4714 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
4716 #undef TARGET_PRINT_OPERAND
4717 #define TARGET_PRINT_OPERAND riscv_print_operand
4718 #undef TARGET_PRINT_OPERAND_ADDRESS
4719 #define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address
4721 #undef TARGET_SETUP_INCOMING_VARARGS
4722 #define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs
4723 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
4724 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS riscv_allocate_stack_slots_for_args
4725 #undef TARGET_STRICT_ARGUMENT_NAMING
4726 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
4727 #undef TARGET_MUST_PASS_IN_STACK
4728 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
4729 #undef TARGET_PASS_BY_REFERENCE
4730 #define TARGET_PASS_BY_REFERENCE riscv_pass_by_reference
4731 #undef TARGET_ARG_PARTIAL_BYTES
4732 #define TARGET_ARG_PARTIAL_BYTES riscv_arg_partial_bytes
4733 #undef TARGET_FUNCTION_ARG
4734 #define TARGET_FUNCTION_ARG riscv_function_arg
4735 #undef TARGET_FUNCTION_ARG_ADVANCE
4736 #define TARGET_FUNCTION_ARG_ADVANCE riscv_function_arg_advance
4737 #undef TARGET_FUNCTION_ARG_BOUNDARY
4738 #define TARGET_FUNCTION_ARG_BOUNDARY riscv_function_arg_boundary
4740 /* The generic ELF target does not always have TLS support. */
4742 #undef TARGET_HAVE_TLS
4743 #define TARGET_HAVE_TLS true
4746 #undef TARGET_CANNOT_FORCE_CONST_MEM
4747 #define TARGET_CANNOT_FORCE_CONST_MEM riscv_cannot_force_const_mem
4749 #undef TARGET_LEGITIMATE_CONSTANT_P
4750 #define TARGET_LEGITIMATE_CONSTANT_P riscv_legitimate_constant_p
4752 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
4753 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
4755 #undef TARGET_LEGITIMATE_ADDRESS_P
4756 #define TARGET_LEGITIMATE_ADDRESS_P riscv_legitimate_address_p
4758 #undef TARGET_CAN_ELIMINATE
4759 #define TARGET_CAN_ELIMINATE riscv_can_eliminate
4761 #undef TARGET_CONDITIONAL_REGISTER_USAGE
4762 #define TARGET_CONDITIONAL_REGISTER_USAGE riscv_conditional_register_usage
4764 #undef TARGET_CLASS_MAX_NREGS
4765 #define TARGET_CLASS_MAX_NREGS riscv_class_max_nregs
4767 #undef TARGET_TRAMPOLINE_INIT
4768 #define TARGET_TRAMPOLINE_INIT riscv_trampoline_init
4770 #undef TARGET_IN_SMALL_DATA_P
4771 #define TARGET_IN_SMALL_DATA_P riscv_in_small_data_p
4773 #undef TARGET_HAVE_SRODATA_SECTION
4774 #define TARGET_HAVE_SRODATA_SECTION true
4776 #undef TARGET_ASM_SELECT_SECTION
4777 #define TARGET_ASM_SELECT_SECTION riscv_select_section
4779 #undef TARGET_ASM_SELECT_RTX_SECTION
4780 #define TARGET_ASM_SELECT_RTX_SECTION riscv_elf_select_rtx_section
4782 #undef TARGET_MIN_ANCHOR_OFFSET
4783 #define TARGET_MIN_ANCHOR_OFFSET (-IMM_REACH/2)
4785 #undef TARGET_MAX_ANCHOR_OFFSET
4786 #define TARGET_MAX_ANCHOR_OFFSET (IMM_REACH/2-1)
4788 #undef TARGET_REGISTER_PRIORITY
4789 #define TARGET_REGISTER_PRIORITY riscv_register_priority
4791 #undef TARGET_CANNOT_COPY_INSN_P
4792 #define TARGET_CANNOT_COPY_INSN_P riscv_cannot_copy_insn_p
4794 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
4795 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV riscv_atomic_assign_expand_fenv
4797 #undef TARGET_INIT_BUILTINS
4798 #define TARGET_INIT_BUILTINS riscv_init_builtins
4800 #undef TARGET_BUILTIN_DECL
4801 #define TARGET_BUILTIN_DECL riscv_builtin_decl
4803 #undef TARGET_EXPAND_BUILTIN
4804 #define TARGET_EXPAND_BUILTIN riscv_expand_builtin
4806 #undef TARGET_HARD_REGNO_NREGS
4807 #define TARGET_HARD_REGNO_NREGS riscv_hard_regno_nregs
4808 #undef TARGET_HARD_REGNO_MODE_OK
4809 #define TARGET_HARD_REGNO_MODE_OK riscv_hard_regno_mode_ok
4811 #undef TARGET_MODES_TIEABLE_P
4812 #define TARGET_MODES_TIEABLE_P riscv_modes_tieable_p
4814 #undef TARGET_SLOW_UNALIGNED_ACCESS
4815 #define TARGET_SLOW_UNALIGNED_ACCESS riscv_slow_unaligned_access
4817 #undef TARGET_SECONDARY_MEMORY_NEEDED
4818 #define TARGET_SECONDARY_MEMORY_NEEDED riscv_secondary_memory_needed
4820 #undef TARGET_CAN_CHANGE_MODE_CLASS
4821 #define TARGET_CAN_CHANGE_MODE_CLASS riscv_can_change_mode_class
4823 #undef TARGET_CONSTANT_ALIGNMENT
4824 #define TARGET_CONSTANT_ALIGNMENT riscv_constant_alignment
4826 #undef TARGET_MERGE_DECL_ATTRIBUTES
4827 #define TARGET_MERGE_DECL_ATTRIBUTES riscv_merge_decl_attributes
4829 #undef TARGET_ATTRIBUTE_TABLE
4830 #define TARGET_ATTRIBUTE_TABLE riscv_attribute_table
4832 #undef TARGET_WARN_FUNC_RETURN
4833 #define TARGET_WARN_FUNC_RETURN riscv_warn_func_return
4835 /* The low bit is ignored by jump instructions so is safe to use. */
4836 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
4837 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
4839 struct gcc_target targetm
= TARGET_INITIALIZER
;
4841 #include "gt-riscv.h"