1 ;; Copyright (C) 2007-2018 Free Software Foundation, Inc.
3 ;; This file is part of GCC.
5 ;; GCC is free software; you can redistribute it and/or modify
6 ;; it under the terms of the GNU General Public License as published by
7 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; GCC is distributed in the hope that it will be useful,
11 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ;; GNU General Public License for more details.
15 ;; You should have received a copy of the GNU General Public License
16 ;; along with GCC; see the file COPYING3. If not see
17 ;; <http://www.gnu.org/licenses/>.
19 ; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
21 (define_c_enum "unspec" [
48 UNSPEC_PRECR_SRA_R_PH_W
73 (define_insn "mips_absq_s_qb"
74 [(set (match_operand:V4QI 0 "register_operand" "=d")
75 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")]
77 (set (reg:CCDSP CCDSP_OU_REGNUM)
78 (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S_QB))]
81 [(set_attr "type" "dspalusat")
82 (set_attr "mode" "SI")])
84 (define_insn "mips_addu_ph"
85 [(set (match_operand:V2HI 0 "register_operand" "=d")
86 (plus:V2HI (match_operand:V2HI 1 "reg_or_0_operand" "dYG")
87 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")))
88 (set (reg:CCDSP CCDSP_OU_REGNUM)
89 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_PH))]
92 [(set_attr "type" "dspalu")
93 (set_attr "mode" "SI")])
95 (define_insn "mips_addu_s_ph"
96 [(set (match_operand:V2HI 0 "register_operand" "=d")
97 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
98 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
100 (set (reg:CCDSP CCDSP_OU_REGNUM)
101 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_S_PH))]
103 "addu_s.ph\t%0,%z1,%z2"
104 [(set_attr "type" "dspalusat")
105 (set_attr "mode" "SI")])
107 (define_insn "mips_adduh_qb"
108 [(set (match_operand:V4QI 0 "register_operand" "=d")
109 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
110 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
113 "adduh.qb\t%0,%z1,%z2"
114 [(set_attr "type" "dspalu")
115 (set_attr "mode" "SI")])
117 (define_insn "mips_adduh_r_qb"
118 [(set (match_operand:V4QI 0 "register_operand" "=d")
119 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
120 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
123 "adduh_r.qb\t%0,%z1,%z2"
124 [(set_attr "type" "dspalusat")
125 (set_attr "mode" "SI")])
127 (define_insn "mips_append"
128 [(set (match_operand:SI 0 "register_operand" "=d")
129 (unspec:SI [(match_operand:SI 1 "register_operand" "0")
130 (match_operand:SI 2 "reg_or_0_operand" "dJ")
131 (match_operand:SI 3 "const_int_operand" "n")]
135 if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
136 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
137 return "append\t%0,%z2,%3";
139 [(set_attr "type" "dspalu")
140 (set_attr "mode" "SI")])
142 (define_insn "mips_balign"
143 [(set (match_operand:SI 0 "register_operand" "=d")
144 (unspec:SI [(match_operand:SI 1 "register_operand" "0")
145 (match_operand:SI 2 "reg_or_0_operand" "dJ")
146 (match_operand:SI 3 "const_int_operand" "n")]
150 if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 3)
151 operands[2] = GEN_INT (INTVAL (operands[2]) & 3);
152 return "balign\t%0,%z2,%3";
154 [(set_attr "type" "dspalu")
155 (set_attr "mode" "SI")])
157 (define_insn "mips_cmpgdu_eq_qb"
158 [(set (match_operand:SI 0 "register_operand" "=d")
159 (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
160 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
161 UNSPEC_CMPGDU_EQ_QB))
162 (set (reg:CCDSP CCDSP_CC_REGNUM)
163 (unspec:CCDSP [(match_dup 1) (match_dup 2)
164 (reg:CCDSP CCDSP_CC_REGNUM)]
165 UNSPEC_CMPGDU_EQ_QB))]
167 "cmpgdu.eq.qb\t%0,%z1,%z2"
168 [(set_attr "type" "dspalu")
169 (set_attr "mode" "SI")])
171 (define_insn "mips_cmpgdu_lt_qb"
172 [(set (match_operand:SI 0 "register_operand" "=d")
173 (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
174 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
175 UNSPEC_CMPGDU_LT_QB))
176 (set (reg:CCDSP CCDSP_CC_REGNUM)
177 (unspec:CCDSP [(match_dup 1) (match_dup 2)
178 (reg:CCDSP CCDSP_CC_REGNUM)]
179 UNSPEC_CMPGDU_LT_QB))]
181 "cmpgdu.lt.qb\t%0,%z1,%z2"
182 [(set_attr "type" "dspalu")
183 (set_attr "mode" "SI")])
185 (define_insn "mips_cmpgdu_le_qb"
186 [(set (match_operand:SI 0 "register_operand" "=d")
187 (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
188 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
189 UNSPEC_CMPGDU_LE_QB))
190 (set (reg:CCDSP CCDSP_CC_REGNUM)
191 (unspec:CCDSP [(match_dup 1) (match_dup 2)
192 (reg:CCDSP CCDSP_CC_REGNUM)]
193 UNSPEC_CMPGDU_LE_QB))]
195 "cmpgdu.le.qb\t%0,%z1,%z2"
196 [(set_attr "type" "dspalu")
197 (set_attr "mode" "SI")])
199 (define_insn "mips_dpa_w_ph"
200 [(set (match_operand:DI 0 "register_operand" "=a")
201 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
202 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
203 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
205 "ISA_HAS_DSPR2 && !TARGET_64BIT"
206 "dpa.w.ph\t%q0,%z2,%z3"
207 [(set_attr "type" "dspmac")
208 (set_attr "accum_in" "1")
209 (set_attr "mode" "SI")])
211 (define_insn "mips_dps_w_ph"
212 [(set (match_operand:DI 0 "register_operand" "=a")
213 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
214 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
215 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
217 "ISA_HAS_DSPR2 && !TARGET_64BIT"
218 "dps.w.ph\t%q0,%z2,%z3"
219 [(set_attr "type" "dspmac")
220 (set_attr "accum_in" "1")
221 (set_attr "mode" "SI")])
223 (define_insn "mulv2hi3"
224 [(set (match_operand:V2HI 0 "register_operand" "=d")
225 (mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
226 (match_operand:V2HI 2 "register_operand" "d")))
227 (set (reg:CCDSP CCDSP_OU_REGNUM)
228 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_PH))
229 (clobber (match_scratch:DI 3 "=x"))]
232 [(set_attr "type" "imul3")
233 (set_attr "mode" "SI")])
235 (define_insn "mips_mul_s_ph"
236 [(set (match_operand:V2HI 0 "register_operand" "=d")
237 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
238 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
240 (set (reg:CCDSP CCDSP_OU_REGNUM)
241 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_S_PH))
242 (clobber (match_scratch:DI 3 "=x"))]
244 "mul_s.ph\t%0,%z1,%z2"
245 [(set_attr "type" "imul3")
246 (set_attr "mode" "SI")])
248 (define_insn "mips_mulq_rs_w"
249 [(set (match_operand:SI 0 "register_operand" "=d")
250 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
251 (match_operand:SI 2 "reg_or_0_operand" "dJ")]
253 (set (reg:CCDSP CCDSP_OU_REGNUM)
254 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_W))
255 (clobber (match_scratch:DI 3 "=x"))]
257 "mulq_rs.w\t%0,%z1,%z2"
258 [(set_attr "type" "imul3")
259 (set_attr "mode" "SI")])
261 (define_insn "mips_mulq_s_ph"
262 [(set (match_operand:V2HI 0 "register_operand" "=d")
263 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
264 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
266 (set (reg:CCDSP CCDSP_OU_REGNUM)
267 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_PH))
268 (clobber (match_scratch:DI 3 "=x"))]
270 "mulq_s.ph\t%0,%z1,%z2"
271 [(set_attr "type" "imul3")
272 (set_attr "mode" "SI")])
274 (define_insn "mips_mulq_s_w"
275 [(set (match_operand:SI 0 "register_operand" "=d")
276 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
277 (match_operand:SI 2 "reg_or_0_operand" "dJ")]
279 (set (reg:CCDSP CCDSP_OU_REGNUM)
280 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_W))
281 (clobber (match_scratch:DI 3 "=x"))]
283 "mulq_s.w\t%0,%z1,%z2"
284 [(set_attr "type" "imul3")
285 (set_attr "mode" "SI")])
287 (define_insn "mips_mulsa_w_ph"
288 [(set (match_operand:DI 0 "register_operand" "=a")
289 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
290 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
291 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
293 "ISA_HAS_DSPR2 && !TARGET_64BIT"
294 "mulsa.w.ph\t%q0,%z2,%z3"
295 [(set_attr "type" "dspmac")
296 (set_attr "accum_in" "1")
297 (set_attr "mode" "SI")])
299 (define_insn "mips_precr_qb_ph"
300 [(set (match_operand:V4QI 0 "register_operand" "=d")
301 (unspec:V4QI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
302 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
303 UNSPEC_PRECR_QB_PH))]
305 "precr.qb.ph\t%0,%z1,%z2"
306 [(set_attr "type" "dspalu")
307 (set_attr "mode" "SI")])
309 (define_insn "mips_precr_sra_ph_w"
310 [(set (match_operand:V2HI 0 "register_operand" "=d")
311 (unspec:V2HI [(match_operand:SI 1 "register_operand" "0")
312 (match_operand:SI 2 "reg_or_0_operand" "dJ")
313 (match_operand:SI 3 "const_int_operand" "n")]
314 UNSPEC_PRECR_SRA_PH_W))]
317 if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
318 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
319 return "precr_sra.ph.w\t%0,%z2,%3";
321 [(set_attr "type" "dspalu")
322 (set_attr "mode" "SI")])
324 (define_insn "mips_precr_sra_r_ph_w"
325 [(set (match_operand:V2HI 0 "register_operand" "=d")
326 (unspec:V2HI [(match_operand:SI 1 "register_operand" "0")
327 (match_operand:SI 2 "reg_or_0_operand" "dJ")
328 (match_operand:SI 3 "const_int_operand" "n")]
329 UNSPEC_PRECR_SRA_R_PH_W))]
332 if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
333 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
334 return "precr_sra_r.ph.w\t%0,%z2,%3";
336 [(set_attr "type" "dspalu")
337 (set_attr "mode" "SI")])
339 (define_insn "mips_prepend"
340 [(set (match_operand:SI 0 "register_operand" "=d")
341 (unspec:SI [(match_operand:SI 1 "register_operand" "0")
342 (match_operand:SI 2 "reg_or_0_operand" "dJ")
343 (match_operand:SI 3 "const_int_operand" "n")]
347 if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
348 operands[3] = GEN_INT (INTVAL (operands[3]) & 31);
349 return "prepend\t%0,%z2,%3";
351 [(set_attr "type" "dspalu")
352 (set_attr "mode" "SI")])
354 (define_insn "mips_shra_qb"
355 [(set (match_operand:V4QI 0 "register_operand" "=d,d")
356 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
357 (match_operand:SI 2 "arith_operand" "I,d")]
361 if (which_alternative == 0)
363 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 7)
364 operands[2] = GEN_INT (INTVAL (operands[2]) & 7);
365 return "shra.qb\t%0,%z1,%2";
367 return "shrav.qb\t%0,%z1,%2";
369 [(set_attr "type" "dspalu")
370 (set_attr "mode" "SI")])
373 (define_insn "mips_shra_r_qb"
374 [(set (match_operand:V4QI 0 "register_operand" "=d,d")
375 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
376 (match_operand:SI 2 "arith_operand" "I,d")]
380 if (which_alternative == 0)
382 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 7)
383 operands[2] = GEN_INT (INTVAL (operands[2]) & 7);
384 return "shra_r.qb\t%0,%z1,%2";
386 return "shrav_r.qb\t%0,%z1,%2";
388 [(set_attr "type" "dspalu")
389 (set_attr "mode" "SI")])
391 (define_insn "mips_shrl_ph"
392 [(set (match_operand:V2HI 0 "register_operand" "=d,d")
393 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG,dYG")
394 (match_operand:SI 2 "arith_operand" "I,d")]
398 if (which_alternative == 0)
400 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 15)
401 operands[2] = GEN_INT (INTVAL (operands[2]) & 15);
402 return "shrl.ph\t%0,%z1,%2";
404 return "shrlv.ph\t%0,%z1,%2";
406 [(set_attr "type" "dspalu")
407 (set_attr "mode" "SI")])
409 (define_insn "mips_subu_ph"
410 [(set (match_operand:V2HI 0 "register_operand" "=d")
411 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
412 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
414 (set (reg:CCDSP CCDSP_OU_REGNUM)
415 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_PH))]
417 "subu.ph\t%0,%z1,%z2"
418 [(set_attr "type" "dspalu")
419 (set_attr "mode" "SI")])
421 (define_insn "mips_subu_s_ph"
422 [(set (match_operand:V2HI 0 "register_operand" "=d")
423 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
424 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
426 (set (reg:CCDSP CCDSP_OU_REGNUM)
427 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_S_PH))]
429 "subu_s.ph\t%0,%z1,%z2"
430 [(set_attr "type" "dspalusat")
431 (set_attr "mode" "SI")])
433 (define_insn "mips_subuh_qb"
434 [(set (match_operand:V4QI 0 "register_operand" "=d")
435 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
436 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
439 "subuh.qb\t%0,%z1,%z2"
440 [(set_attr "type" "dspalu")
441 (set_attr "mode" "SI")])
443 (define_insn "mips_subuh_r_qb"
444 [(set (match_operand:V4QI 0 "register_operand" "=d")
445 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
446 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
449 "subuh_r.qb\t%0,%z1,%z2"
450 [(set_attr "type" "dspalu")
451 (set_attr "mode" "SI")])
453 (define_insn "mips_addqh_ph"
454 [(set (match_operand:V2HI 0 "register_operand" "=d")
455 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
456 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
459 "addqh.ph\t%0,%z1,%z2"
460 [(set_attr "type" "dspalu")
461 (set_attr "mode" "SI")])
463 (define_insn "mips_addqh_r_ph"
464 [(set (match_operand:V2HI 0 "register_operand" "=d")
465 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
466 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
469 "addqh_r.ph\t%0,%z1,%z2"
470 [(set_attr "type" "dspalu")
471 (set_attr "mode" "SI")])
473 (define_insn "mips_addqh_w"
474 [(set (match_operand:SI 0 "register_operand" "=d")
475 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
476 (match_operand:SI 2 "reg_or_0_operand" "dJ")]
479 "addqh.w\t%0,%z1,%z2"
480 [(set_attr "type" "dspalu")
481 (set_attr "mode" "SI")])
483 (define_insn "mips_addqh_r_w"
484 [(set (match_operand:SI 0 "register_operand" "=d")
485 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
486 (match_operand:SI 2 "reg_or_0_operand" "dJ")]
489 "addqh_r.w\t%0,%z1,%z2"
490 [(set_attr "type" "dspalu")
491 (set_attr "mode" "SI")])
493 (define_insn "mips_subqh_ph"
494 [(set (match_operand:V2HI 0 "register_operand" "=d")
495 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
496 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
499 "subqh.ph\t%0,%z1,%z2"
500 [(set_attr "type" "dspalu")
501 (set_attr "mode" "SI")])
503 (define_insn "mips_subqh_r_ph"
504 [(set (match_operand:V2HI 0 "register_operand" "=d")
505 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
506 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
509 "subqh_r.ph\t%0,%z1,%z2"
510 [(set_attr "type" "dspalu")
511 (set_attr "mode" "SI")])
513 (define_insn "mips_subqh_w"
514 [(set (match_operand:SI 0 "register_operand" "=d")
515 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
516 (match_operand:SI 2 "reg_or_0_operand" "dJ")]
519 "subqh.w\t%0,%z1,%z2"
520 [(set_attr "type" "dspalu")
521 (set_attr "mode" "SI")])
523 (define_insn "mips_subqh_r_w"
524 [(set (match_operand:SI 0 "register_operand" "=d")
525 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
526 (match_operand:SI 2 "reg_or_0_operand" "dJ")]
529 "subqh_r.w\t%0,%z1,%z2"
530 [(set_attr "type" "dspalu")
531 (set_attr "mode" "SI")])
533 (define_insn "mips_dpax_w_ph"
534 [(set (match_operand:DI 0 "register_operand" "=a")
535 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
536 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
537 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
539 "ISA_HAS_DSPR2 && !TARGET_64BIT"
540 "dpax.w.ph\t%q0,%z2,%z3"
541 [(set_attr "type" "dspmac")
542 (set_attr "accum_in" "1")
543 (set_attr "mode" "SI")])
545 (define_insn "mips_dpsx_w_ph"
546 [(set (match_operand:DI 0 "register_operand" "=a")
547 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
548 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
549 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
551 "ISA_HAS_DSPR2 && !TARGET_64BIT"
552 "dpsx.w.ph\t%q0,%z2,%z3"
553 [(set_attr "type" "dspmac")
554 (set_attr "accum_in" "1")
555 (set_attr "mode" "SI")])
557 (define_insn "mips_dpaqx_s_w_ph"
558 [(set (match_operand:DI 0 "register_operand" "=a")
559 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
560 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
561 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
562 UNSPEC_DPAQX_S_W_PH))
563 (set (reg:CCDSP CCDSP_OU_REGNUM)
564 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
565 UNSPEC_DPAQX_S_W_PH))]
566 "ISA_HAS_DSPR2 && !TARGET_64BIT"
567 "dpaqx_s.w.ph\t%q0,%z2,%z3"
568 [(set_attr "type" "dspmac")
569 (set_attr "accum_in" "1")
570 (set_attr "mode" "SI")])
572 (define_insn "mips_dpaqx_sa_w_ph"
573 [(set (match_operand:DI 0 "register_operand" "=a")
574 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
575 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
576 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
577 UNSPEC_DPAQX_SA_W_PH))
578 (set (reg:CCDSP CCDSP_OU_REGNUM)
579 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
580 UNSPEC_DPAQX_SA_W_PH))]
581 "ISA_HAS_DSPR2 && !TARGET_64BIT"
582 "dpaqx_sa.w.ph\t%q0,%z2,%z3"
583 [(set_attr "type" "dspmacsat")
584 (set_attr "accum_in" "1")
585 (set_attr "mode" "SI")])
587 (define_insn "mips_dpsqx_s_w_ph"
588 [(set (match_operand:DI 0 "register_operand" "=a")
589 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
590 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
591 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
592 UNSPEC_DPSQX_S_W_PH))
593 (set (reg:CCDSP CCDSP_OU_REGNUM)
594 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
595 UNSPEC_DPSQX_S_W_PH))]
596 "ISA_HAS_DSPR2 && !TARGET_64BIT"
597 "dpsqx_s.w.ph\t%q0,%z2,%z3"
598 [(set_attr "type" "dspmac")
599 (set_attr "accum_in" "1")
600 (set_attr "mode" "SI")])
602 (define_insn "mips_dpsqx_sa_w_ph"
603 [(set (match_operand:DI 0 "register_operand" "=a")
604 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
605 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
606 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
607 UNSPEC_DPSQX_SA_W_PH))
608 (set (reg:CCDSP CCDSP_OU_REGNUM)
609 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
610 UNSPEC_DPSQX_SA_W_PH))]
611 "ISA_HAS_DSPR2 && !TARGET_64BIT"
612 "dpsqx_sa.w.ph\t%q0,%z2,%z3"
613 [(set_attr "type" "dspmacsat")
614 (set_attr "accum_in" "1")
615 (set_attr "mode" "SI")])