1 ; Options for the rs6000 port of the compiler
3 ; Copyright (C) 2005-2016 Free Software Foundation, Inc.
4 ; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
6 ; This file is part of GCC.
8 ; GCC is free software; you can redistribute it and/or modify it under
9 ; the terms of the GNU General Public License as published by the Free
10 ; Software Foundation; either version 3, or (at your option) any later
13 ; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ; License for more details.
18 ; You should have received a copy of the GNU General Public License
19 ; along with GCC; see the file COPYING3. If not see
20 ; <http://www.gnu.org/licenses/>.
23 config/rs6000/rs6000-opts.h
25 ;; ISA flag bits (on/off)
27 HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT
30 HOST_WIDE_INT x_rs6000_isa_flags
32 ;; Miscellaneous flag bits that were set explicitly by the user
34 HOST_WIDE_INT rs6000_isa_flags_explicit
37 HOST_WIDE_INT x_rs6000_isa_flags_explicit
41 enum processor_type rs6000_cpu = PROCESSOR_PPC603
43 ;; Always emit branch hint bits.
45 unsigned char rs6000_always_hint
47 ;; Schedule instructions for group formation.
49 unsigned char rs6000_sched_groups
51 ;; Align branch targets.
53 unsigned char rs6000_align_branch_targets
55 ;; Support for -msched-costly-dep option.
57 enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly
59 ;; Support for -minsert-sched-nops option.
61 enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none
63 ;; Non-zero to allow overriding loop alignment.
65 unsigned char can_override_loop_align
67 ;; Which small data model to use (for System V targets only)
69 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA
71 ;; Bit size of immediate TLS offsets and string from which it is decoded.
73 int rs6000_tls_size = 32
75 ;; ABI enumeration available for subtarget to use.
77 enum rs6000_abi rs6000_current_abi = ABI_NONE
79 ;; Type of traceback to use.
81 enum rs6000_traceback_type rs6000_traceback = traceback_default
83 ;; Control alignment for fields within structures.
85 unsigned char rs6000_alignment_flags
87 ;; Code model for 64-bit linux.
89 enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL
91 ;; What type of reciprocal estimation instructions to generate
93 unsigned int rs6000_recip_control
95 ;; Mask of what builtin functions are allowed
97 HOST_WIDE_INT rs6000_builtin_mask
101 unsigned int rs6000_debug
103 ;; This option existed in the past, but now is always on.
105 Target RejectNegative Undocumented Ignore
108 Target Report Mask(POWERPC64) Var(rs6000_isa_flags)
109 Use PowerPC-64 instruction set.
112 Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags)
113 Use PowerPC General Purpose group optional instructions.
116 Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags)
117 Use PowerPC Graphics group optional instructions.
120 Target Report Mask(MFCRF) Var(rs6000_isa_flags)
121 Use PowerPC V2.01 single field mfcr instruction.
124 Target Report Mask(POPCNTB) Var(rs6000_isa_flags)
125 Use PowerPC V2.02 popcntb instruction.
128 Target Report Mask(FPRND) Var(rs6000_isa_flags)
129 Use PowerPC V2.02 floating point rounding instructions.
132 Target Report Mask(CMPB) Var(rs6000_isa_flags)
133 Use PowerPC V2.05 compare bytes instruction.
136 Target Report Mask(MFPGPR) Var(rs6000_isa_flags)
137 Use extended PowerPC V2.05 move floating point to/from GPR instructions.
140 Target Report Mask(ALTIVEC) Var(rs6000_isa_flags)
141 Use AltiVec instructions.
144 Target Report RejectNegative Var(rs6000_altivec_element_order, 1) Save
145 Generate Altivec instructions using little-endian element order.
148 Target Report RejectNegative Var(rs6000_altivec_element_order, 2)
149 Generate Altivec instructions using big-endian element order.
152 Target Report Mask(DFP) Var(rs6000_isa_flags)
153 Use decimal floating point instructions.
156 Target Report Mask(MULHW) Var(rs6000_isa_flags)
157 Use 4xx half-word multiply instructions.
160 Target Report Mask(DLMZB) Var(rs6000_isa_flags)
161 Use 4xx string-search dlmzb instruction.
164 Target Report Mask(MULTIPLE) Var(rs6000_isa_flags)
165 Generate load/store multiple instructions.
168 Target Report Mask(STRING) Var(rs6000_isa_flags)
169 Generate string instructions for block moves.
172 Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags)
173 Do not use hardware floating point.
176 Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags)
177 Use hardware floating point.
180 Target Report Mask(POPCNTD) Var(rs6000_isa_flags)
181 Use PowerPC V2.06 popcntd instruction.
184 Target Report Var(TARGET_FRIZ) Init(-1) Save
185 Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions.
188 Target RejectNegative Joined Var(rs6000_veclibabi_name)
189 Vector library ABI to use.
192 Target Report Mask(VSX) Var(rs6000_isa_flags)
193 Use vector/scalar (VSX) instructions.
196 Target Undocumented Report Var(TARGET_VSX_SCALAR_FLOAT) Init(1)
197 ; If -mpower8-vector, use VSX arithmetic instructions for SFmode (on by default)
200 Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(1)
201 ; If -mvsx, use VSX arithmetic instructions for DFmode (on by default)
204 Target Undocumented Report Alias(mupper-regs-df)
207 Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save
208 ; If -mvsx, set alignment to 128 bits instead of 32/64
211 Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save
212 ; Allow the movmisalign in DF/DI vectors
214 mefficient-unaligned-vsx
215 Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags)
216 ; Consider unaligned VSX vector and fp accesses to be efficient
219 Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE) Save
220 ; Allow permutation of DF/DI vectors
223 Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Save
224 ; Explicitly set rs6000_sched_groups
227 Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Save
228 ; Explicitly set rs6000_always_hint
230 malign-branch-targets
231 Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save
232 ; Explicitly set rs6000_align_branch_targets
235 Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1) Save
236 ; Explicitly control whether we vectorize the builtins or not.
239 Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags)
240 Do not generate load/store with update instructions.
243 Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags)
244 Generate load/store with update instructions.
247 Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0)
248 Do not load the PIC register in function prologues.
250 mavoid-indexed-addresses
251 Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save
252 Avoid generation of indexed load/store instructions when possible.
255 Target Report Var(tls_markers) Init(1) Save
256 Mark __tls_get_addr calls with argument info.
259 Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save
262 Target Report Var(TARGET_SCHED_PROLOG) Save
263 Schedule the start and end of the procedure.
266 Target Report RejectNegative Var(aix_struct_return) Save
267 Return all structures in memory (AIX default).
270 Target Report RejectNegative Var(aix_struct_return,0) Save
271 Return small structures in registers (SVR4 default).
274 Target Report Var(TARGET_XL_COMPAT) Save
275 Conform more closely to IBM XLC semantics.
279 Generate software reciprocal divide and square root for better throughput.
282 Target Report RejectNegative Joined Var(rs6000_recip_name)
283 Generate software reciprocal divide and square root for better throughput.
286 Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags)
287 Assume that the reciprocal estimate instructions provide more accuracy.
290 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save
291 Do not place floating point constants in TOC.
294 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save
295 Place floating point constants in TOC.
298 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save
299 Do not place symbol+offset constants in TOC.
302 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save
303 Place symbol+offset constants in TOC.
305 ; Output only one TOC entry per module. Normally linking fails if
306 ; there are more than 16K unique variables/constants in an executable. With
307 ; this option, linking fails only if there are more than 16K modules, or
308 ; if there are more than 16K unique variables/constant in a single module.
310 ; This is at the cost of having 2 extra loads and one extra store per
311 ; function, and one less allocable register.
313 Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags)
314 Use only one TOC entry per procedure.
318 Put everything in the regular TOC.
321 Target Report Var(TARGET_ALTIVEC_VRSAVE) Save
322 Generate VRSAVE instructions when generating AltiVec code.
325 Target RejectNegative Alias(mvrsave) NegativeAlias
326 Deprecated option. Use -mno-vrsave instead.
329 Target RejectNegative Alias(mvrsave)
330 Deprecated option. Use -mvrsave instead.
332 mblock-move-inline-limit=
333 Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save
334 Specify how many bytes should be moved inline before calling out to memcpy/memmove.
336 mblock-compare-inline-limit=
337 Target Report Var(rs6000_block_compare_inline_limit) Init(5) RejectNegative Joined UInteger Save
338 Specify the maximum number pairs of load instructions that should be generated inline for the compare. If the number needed exceeds the limit, a call to memcmp will be generated instead.
341 Target Report Mask(ISEL) Var(rs6000_isa_flags)
342 Generate isel instructions.
345 Target RejectNegative Alias(misel) NegativeAlias
346 Deprecated option. Use -mno-isel instead.
349 Target RejectNegative Alias(misel)
350 Deprecated option. Use -misel instead.
353 Target Var(rs6000_spe) Save
354 Generate SPE SIMD instructions on E500.
357 Target Var(rs6000_paired_float) Save
358 Generate PPC750CL paired-single instructions.
361 Target RejectNegative Alias(mspe) NegativeAlias
362 Deprecated option. Use -mno-spe instead.
365 Target RejectNegative Alias(mspe)
366 Deprecated option. Use -mspe instead.
369 Target RejectNegative Joined
370 -mdebug= Enable debug output.
373 Target RejectNegative Var(rs6000_altivec_abi) Save
374 Use the AltiVec ABI extensions.
377 Target RejectNegative Var(rs6000_altivec_abi, 0)
378 Do not use the AltiVec ABI extensions.
381 Target RejectNegative Var(rs6000_spe_abi) Save
382 Use the SPE ABI extensions.
385 Target RejectNegative Var(rs6000_spe_abi, 0)
386 Do not use the SPE ABI extensions.
389 Target RejectNegative Var(rs6000_elf_abi, 1) Save
393 Target RejectNegative Var(rs6000_elf_abi, 2)
396 ; These are here for testing during development only, do not document
397 ; in the manual please.
399 ; If we want Darwin's struct-by-value-in-regs ABI.
401 Target RejectNegative Undocumented Warn(using darwin64 ABI) Var(rs6000_darwin64_abi) Save
404 Target RejectNegative Undocumented Warn(using old darwin ABI) Var(rs6000_darwin64_abi, 0)
407 Target RejectNegative Undocumented Warn(using IEEE extended precision long double) Var(rs6000_ieeequad) Save
410 Target RejectNegative Undocumented Warn(using IBM extended precision long double) Var(rs6000_ieeequad, 0)
413 Target RejectNegative Joined Var(rs6000_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
414 -mcpu= Use features of and schedule code for given CPU.
417 Target RejectNegative Joined Var(rs6000_tune_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
418 -mtune= Schedule code for given CPU.
421 Target RejectNegative Joined Enum(rs6000_traceback_type) Var(rs6000_traceback)
422 -mtraceback= Select full, part, or no traceback table.
425 Name(rs6000_traceback_type) Type(enum rs6000_traceback_type)
428 Enum(rs6000_traceback_type) String(full) Value(traceback_full)
431 Enum(rs6000_traceback_type) String(part) Value(traceback_part)
434 Enum(rs6000_traceback_type) String(no) Value(traceback_none)
437 Target Report Var(rs6000_default_long_calls) Save
438 Avoid all range limits on call instructions.
441 Target Report Var(rs6000_gen_cell_microcode) Init(-1) Save
442 Generate Cell microcode.
445 Target Var(rs6000_warn_cell_microcode) Init(0) Warning Save
446 Warn when a Cell microcoded instruction is emitted.
449 Target Var(rs6000_warn_altivec_long) Init(1) Save
450 Warn about deprecated 'vector long ...' AltiVec type usage.
453 Target RejectNegative Joined Enum(rs6000_float_gprs) Var(rs6000_float_gprs) Save
454 -mfloat-gprs= Select GPR floating point method.
457 Name(rs6000_float_gprs) Type(unsigned char)
458 Valid arguments to -mfloat-gprs=:
461 Enum(rs6000_float_gprs) String(yes) Value(1)
464 Enum(rs6000_float_gprs) String(single) Value(1)
467 Enum(rs6000_float_gprs) String(double) Value(2)
470 Enum(rs6000_float_gprs) String(no) Value(0)
473 Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save
474 -mlong-double-<n> Specify size of long double (64 or 128 bits).
477 Target Report Mask(LRA) Var(rs6000_isa_flags)
478 Enable Local Register Allocation.
481 Target RejectNegative Joined Var(rs6000_sched_costly_dep_str)
482 Determine which dependences between insns are considered costly.
485 Target RejectNegative Joined Var(rs6000_sched_insert_nops_str)
486 Specify which post scheduling nop insertion scheme to apply.
489 Target RejectNegative Joined Enum(rs6000_alignment_flags) Var(rs6000_alignment_flags)
490 Specify alignment of structure fields default/natural.
493 Name(rs6000_alignment_flags) Type(unsigned char)
494 Valid arguments to -malign-:
497 Enum(rs6000_alignment_flags) String(power) Value(MASK_ALIGN_POWER)
500 Enum(rs6000_alignment_flags) String(natural) Value(MASK_ALIGN_NATURAL)
502 mprioritize-restricted-insns=
503 Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save
504 Specify scheduling priority for dispatch slot restricted insns.
507 Target RejectNegative Var(rs6000_single_float) Save
508 Single-precision floating point unit.
511 Target RejectNegative Var(rs6000_double_float) Save
512 Double-precision floating point unit.
515 Target RejectNegative Var(rs6000_simple_fpu) Save
516 Floating point unit does not support divide & sqrt.
519 Target RejectNegative Joined Enum(fpu_type_t) Var(rs6000_fpu_type) Init(FPU_NONE)
520 -mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu).
523 Name(fpu_type_t) Type(enum fpu_type_t)
526 Enum(fpu_type_t) String(none) Value(FPU_NONE)
529 Enum(fpu_type_t) String(sp_lite) Value(FPU_SF_LITE)
532 Enum(fpu_type_t) String(dp_lite) Value(FPU_DF_LITE)
535 Enum(fpu_type_t) String(sp_full) Value(FPU_SF_FULL)
538 Enum(fpu_type_t) String(dp_full) Value(FPU_DF_FULL)
541 Target Var(rs6000_xilinx_fpu) Save
544 mpointers-to-nested-functions
545 Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save
546 Use r11 to hold the static link in calls to functions via pointers.
549 Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags)
550 Save the TOC in the prologue for indirect calls rather than inline.
553 Target Undocumented Mask(VSX_TIMODE) Var(rs6000_isa_flags)
554 Allow 128-bit integers in VSX registers.
557 Target Report Mask(P8_FUSION) Var(rs6000_isa_flags)
558 Fuse certain integer operations together for better performance on power8.
561 Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags)
562 Allow sign extension in fusion operations.
565 Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags)
566 Use vector and scalar instructions added in ISA 2.07.
569 Target Report Mask(CRYPTO) Var(rs6000_isa_flags)
570 Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions.
573 Target Report Mask(DIRECT_MOVE) Var(rs6000_isa_flags)
574 Use ISA 2.07 direct move between GPR & VSX register instructions.
577 Target Report Mask(HTM) Var(rs6000_isa_flags)
578 Use ISA 2.07 transactional memory (HTM) instructions.
581 Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags)
582 Generate the quad word memory instructions (lq/stq).
585 Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags)
586 Generate the quad word memory atomic instructions (lqarx/stqcx).
589 Target Report Var(rs6000_compat_align_parm) Init(0) Save
590 Generate aggregate parameter passing code with at most 64-bit alignment.
593 Target Report Mask(UPPER_REGS_DF) Var(rs6000_isa_flags)
594 Allow double variables in upper registers with -mcpu=power7 or -mvsx.
597 Target Report Mask(UPPER_REGS_SF) Var(rs6000_isa_flags)
598 Allow float variables in upper registers with -mcpu=power8 or -mpower8-vector.
601 Target Report Var(TARGET_UPPER_REGS) Init(-1) Save
602 Allow float/double variables in upper registers if cpu allows it.
605 Target Report Mask(UPPER_REGS_DI) Var(rs6000_isa_flags)
606 Allow 64-bit integer variables in upper registers with -mcpu=power7 or -mvsx.
609 Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save
610 Analyze and remove doubleword swaps from VSX computations.
613 Target Undocumented Report Mask(P9_FUSION) Var(rs6000_isa_flags)
614 Fuse certain operations together for better performance on power9.
617 Target Undocumented Report Mask(P9_MISC) Var(rs6000_isa_flags)
618 Use certain scalar instructions added in ISA 3.0.
621 Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
622 Use vector instructions added in ISA 3.0.
625 Target Undocumented Mask(P9_DFORM_SCALAR) Var(rs6000_isa_flags)
626 Use scalar register+offset memory instructions added in ISA 3.0.
629 Target Undocumented Mask(P9_DFORM_VECTOR) Var(rs6000_isa_flags)
630 Use vector register+offset memory instructions added in ISA 3.0.
633 Target Undocumented Report Var(TARGET_P9_DFORM_BOTH) Init(-1) Save
634 Use register+offset memory instructions added in ISA 3.0.
637 Target Undocumented Mask(P9_MINMAX) Var(rs6000_isa_flags)
638 Use the new min/max instructions defined in ISA 3.0.
641 Target Undocumented Mask(TOC_FUSION) Var(rs6000_isa_flags)
642 Fuse medium/large code model toc references with the memory instruction.
645 Target Undocumented Report Mask(MODULO) Var(rs6000_isa_flags)
646 Generate the integer modulo instructions.
648 ; We want to enable the internal support for the IEEE 128-bit floating point
649 ; type without necessarily enabling the __float128 keyword. This is to allow
650 ; Boost and other libraries that know about __float128 to work until the
651 ; official library support is finished.
653 Target Undocumented Mask(FLOAT128_TYPE) Var(rs6000_isa_flags)
654 Allow the IEEE 128-bit types without requiring the __float128 keyword.
657 Target Report Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags)
658 Enable IEEE 128-bit floating point via the __float128 keyword.
661 Target Report Mask(FLOAT128_HW) Var(rs6000_isa_flags)
662 Enable using IEEE 128-bit floating point instructions.
665 Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags)
666 Enable default conversions between __float128 & long double.
669 Target Report Mask(VSX_SMALL_INTEGER) Var(rs6000_isa_flags)
670 Enable small integers to be in VSX registers.