1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010, 2011, 2012
3 Free Software Foundation, Inc.
4 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
23 /* This file contains code for 3 passes: constraint pass,
24 inheritance/split pass, and pass for undoing failed inheritance and
27 The major goal of constraint pass is to transform RTL to satisfy
28 insn and address constraints by:
29 o choosing insn alternatives;
30 o generating *reload insns* (or reloads in brief) and *reload
31 pseudos* which will get necessary hard registers later;
32 o substituting pseudos with equivalent values and removing the
33 instructions that initialized those pseudos.
35 The constraint pass has biggest and most complicated code in LRA.
36 There are a lot of important details like:
37 o reuse of input reload pseudos to simplify reload pseudo
39 o some heuristics to choose insn alternative to improve the
43 The pass is mimicking former reload pass in alternative choosing
44 because the reload pass is oriented to current machine description
45 model. It might be changed if the machine description model is
48 There is special code for preventing all LRA and this pass cycling
51 On the first iteration of the pass we process every instruction and
52 choose an alternative for each one. On subsequent iterations we try
53 to avoid reprocessing instructions if we can be sure that the old
54 choice is still valid.
56 The inheritance/spilt pass is to transform code to achieve
57 ineheritance and live range splitting. It is done on backward
60 The inheritance optimization goal is to reuse values in hard
61 registers. There is analogous optimization in old reload pass. The
62 inheritance is achieved by following transformation:
64 reload_p1 <- p reload_p1 <- p
65 ... new_p <- reload_p1
67 reload_p2 <- p reload_p2 <- new_p
69 where p is spilled and not changed between the insns. Reload_p1 is
70 also called *original pseudo* and new_p is called *inheritance
73 The subsequent assignment pass will try to assign the same (or
74 another if it is not possible) hard register to new_p as to
75 reload_p1 or reload_p2.
77 If the assignment pass fails to assign a hard register to new_p,
78 this file will undo the inheritance and restore the original code.
79 This is because implementing the above sequence with a spilled
80 new_p would make the code much worse. The inheritance is done in
81 EBB scope. The above is just a simplified example to get an idea
82 of the inheritance as the inheritance is also done for non-reload
85 Splitting (transformation) is also done in EBB scope on the same
86 pass as the inheritance:
88 r <- ... or ... <- r r <- ... or ... <- r
89 ... s <- r (new insn -- save)
91 ... r <- s (new insn -- restore)
94 The *split pseudo* s is assigned to the hard register of the
95 original pseudo or hard register r.
98 o In EBBs with high register pressure for global pseudos (living
99 in at least 2 BBs) and assigned to hard registers when there
100 are more one reloads needing the hard registers;
101 o for pseudos needing save/restore code around calls.
103 If the split pseudo still has the same hard register as the
104 original pseudo after the subsequent assignment pass or the
105 original pseudo was split, the opposite transformation is done on
106 the same pass for undoing inheritance. */
112 #include "coretypes.h"
114 #include "hard-reg-set.h"
118 #include "insn-config.h"
119 #include "insn-codes.h"
122 #include "addresses.h"
124 #include "function.h"
126 #include "basic-block.h"
131 #include "rtl-error.h"
134 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
135 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
137 static int bb_reload_num
;
139 /* The current insn being processed and corresponding its data (basic
140 block, the insn data, the insn static data, and the mode of each
142 static rtx curr_insn
;
143 static basic_block curr_bb
;
144 static lra_insn_recog_data_t curr_id
;
145 static struct lra_static_insn_data
*curr_static_id
;
146 static enum machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Start numbers for new registers and insns at the current constraints
152 static int new_regno_start
;
153 static int new_insn_uid_start
;
155 /* If LOC is nonnull, strip any outer subreg from it. */
157 strip_subreg (rtx
*loc
)
159 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
162 /* Return hard regno of REGNO or if it is was not assigned to a hard
163 register, use a hard register from its allocno class. */
165 get_try_hard_regno (int regno
)
168 enum reg_class rclass
;
170 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
171 hard_regno
= lra_get_regno_hard_regno (regno
);
174 rclass
= lra_get_allocno_class (regno
);
175 if (rclass
== NO_REGS
)
177 return ira_class_hard_regs
[rclass
][0];
180 /* Return final hard regno (plus offset) which will be after
181 elimination. We do this for matching constraints because the final
182 hard regno could have a different class. */
184 get_final_hard_regno (int hard_regno
, int offset
)
188 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
189 return hard_regno
+ offset
;
192 /* Return hard regno of X after removing subreg and making
193 elimination. If X is not a register or subreg of register, return
194 -1. For pseudo use its assignment. */
196 get_hard_regno (rtx x
)
199 int offset
, hard_regno
;
202 if (GET_CODE (x
) == SUBREG
)
203 reg
= SUBREG_REG (x
);
206 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
207 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
211 if (GET_CODE (x
) == SUBREG
)
212 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
213 SUBREG_BYTE (x
), GET_MODE (x
));
214 return get_final_hard_regno (hard_regno
, offset
);
217 /* If REGNO is a hard register or has been allocated a hard register,
218 return the class of that register. If REGNO is a reload pseudo
219 created by the current constraints pass, return its allocno class.
220 Return NO_REGS otherwise. */
221 static enum reg_class
222 get_reg_class (int regno
)
226 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
227 hard_regno
= lra_get_regno_hard_regno (regno
);
230 hard_regno
= get_final_hard_regno (hard_regno
, 0);
231 return REGNO_REG_CLASS (hard_regno
);
233 if (regno
>= new_regno_start
)
234 return lra_get_allocno_class (regno
);
238 /* Return true if REG satisfies (or will satisfy) reg class constraint
239 CL. Use elimination first if REG is a hard register. If REG is a
240 reload pseudo created by this constraints pass, assume that it will
241 be allocated a hard register from its allocno class, but allow that
242 class to be narrowed to CL if it is currently a superset of CL.
244 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
245 REGNO (reg), or NO_REGS if no change in its class was needed. */
247 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
249 enum reg_class rclass
, common_class
;
250 enum machine_mode reg_mode
;
251 int class_size
, hard_regno
, nregs
, i
, j
;
252 int regno
= REGNO (reg
);
254 if (new_class
!= NULL
)
255 *new_class
= NO_REGS
;
256 if (regno
< FIRST_PSEUDO_REGISTER
)
259 rtx
*final_loc
= &final_reg
;
261 lra_eliminate_reg_if_possible (final_loc
);
262 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
264 reg_mode
= GET_MODE (reg
);
265 rclass
= get_reg_class (regno
);
266 if (regno
< new_regno_start
267 /* Do not allow the constraints for reload instructions to
268 influence the classes of new pseudos. These reloads are
269 typically moves that have many alternatives, and restricting
270 reload pseudos for one alternative may lead to situations
271 where other reload pseudos are no longer allocatable. */
272 || INSN_UID (curr_insn
) >= new_insn_uid_start
)
273 /* When we don't know what class will be used finally for reload
274 pseudos, we use ALL_REGS. */
275 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
276 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
277 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
278 lra_no_alloc_regs
)));
281 common_class
= ira_reg_class_subset
[rclass
][cl
];
282 if (new_class
!= NULL
)
283 *new_class
= common_class
;
284 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
287 /* Check that there are enough allocatable regs. */
288 class_size
= ira_class_hard_regs_num
[common_class
];
289 for (i
= 0; i
< class_size
; i
++)
291 hard_regno
= ira_class_hard_regs
[common_class
][i
];
292 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
295 for (j
= 0; j
< nregs
; j
++)
296 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
))
305 /* Return true if REGNO satisfies a memory constraint. */
309 return get_reg_class (regno
) == NO_REGS
;
312 /* If we have decided to substitute X with another value, return that
313 value, otherwise return X. */
315 get_equiv_substitution (rtx x
)
320 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
321 || ! ira_reg_equiv
[regno
].defined_p
322 || ! ira_reg_equiv
[regno
].profitable_p
323 || lra_get_regno_hard_regno (regno
) >= 0)
325 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
327 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
329 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
334 /* Set up curr_operand_mode. */
336 init_curr_operand_mode (void)
338 int nop
= curr_static_id
->n_operands
;
339 for (int i
= 0; i
< nop
; i
++)
341 enum machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
342 if (mode
== VOIDmode
)
344 /* The .md mode for address operands is the mode of the
345 addressed value rather than the mode of the address itself. */
346 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
349 mode
= curr_static_id
->operand
[i
].mode
;
351 curr_operand_mode
[i
] = mode
;
357 /* The page contains code to reuse input reloads. */
359 /* Structure describes input reload of the current insns. */
362 /* Reloaded value. */
364 /* Reload pseudo used. */
368 /* The number of elements in the following array. */
369 static int curr_insn_input_reloads_num
;
370 /* Array containing info about input reloads. It is used to find the
371 same input reload and reuse the reload pseudo in this case. */
372 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
374 /* Initiate data concerning reuse of input reloads for the current
377 init_curr_insn_input_reloads (void)
379 curr_insn_input_reloads_num
= 0;
382 /* Change class of pseudo REGNO to NEW_CLASS. Print info about it
383 using TITLE. Output a new line if NL_P. */
385 change_class (int regno
, enum reg_class new_class
,
386 const char *title
, bool nl_p
)
388 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
);
389 if (lra_dump_file
!= NULL
)
390 fprintf (lra_dump_file
, "%s to class %s for r%d",
391 title
, reg_class_names
[new_class
], regno
);
392 setup_reg_classes (regno
, new_class
, NO_REGS
, new_class
);
393 if (lra_dump_file
!= NULL
&& nl_p
)
394 fprintf (lra_dump_file
, "\n");
397 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
398 created input reload pseudo (only if TYPE is not OP_OUT). The
399 result pseudo is returned through RESULT_REG. Return TRUE if we
400 created a new pseudo, FALSE if we reused the already created input
401 reload pseudo. Use TITLE to describe new registers for debug
404 get_reload_reg (enum op_type type
, enum machine_mode mode
, rtx original
,
405 enum reg_class rclass
, const char *title
, rtx
*result_reg
)
408 enum reg_class new_class
;
413 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
416 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
417 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
418 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
420 lra_assert (! side_effects_p (original
));
421 *result_reg
= curr_insn_input_reloads
[i
].reg
;
422 regno
= REGNO (*result_reg
);
423 if (lra_dump_file
!= NULL
)
425 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
426 print_value_slim (lra_dump_file
, original
, 1);
428 if (rclass
!= new_class
)
429 change_class (regno
, new_class
, ", change", false);
430 if (lra_dump_file
!= NULL
)
431 fprintf (lra_dump_file
, "\n");
434 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
435 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
436 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
437 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
443 /* The page contains code to extract memory address parts. */
445 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
447 ok_for_index_p_nonstrict (rtx reg
)
449 unsigned regno
= REGNO (reg
);
451 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
454 /* A version of regno_ok_for_base_p for use here, when all pseudos
455 should count as OK. Arguments as for regno_ok_for_base_p. */
457 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
458 enum rtx_code outer_code
, enum rtx_code index_code
)
460 unsigned regno
= REGNO (reg
);
462 if (regno
>= FIRST_PSEUDO_REGISTER
)
464 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
469 /* The page contains major code to choose the current insn alternative
470 and generate reloads for it. */
472 /* Return the offset from REGNO of the least significant register
475 This function is used to tell whether two registers satisfy
476 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
478 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
479 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
481 lra_constraint_offset (int regno
, enum machine_mode mode
)
483 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
484 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
485 && SCALAR_INT_MODE_P (mode
))
486 return hard_regno_nregs
[regno
][mode
] - 1;
490 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
491 if they are the same hard reg, and has special hacks for
492 auto-increment and auto-decrement. This is specifically intended for
493 process_alt_operands to use in determining whether two operands
494 match. X is the operand whose number is the lower of the two.
496 It is supposed that X is the output operand and Y is the input
497 operand. Y_HARD_REGNO is the final hard regno of register Y or
498 register in subreg Y as we know it now. Otherwise, it is a
501 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
504 RTX_CODE code
= GET_CODE (x
);
509 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
510 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
514 i
= get_hard_regno (x
);
518 if ((j
= y_hard_regno
) < 0)
521 i
+= lra_constraint_offset (i
, GET_MODE (x
));
522 j
+= lra_constraint_offset (j
, GET_MODE (y
));
527 /* If two operands must match, because they are really a single
528 operand of an assembler insn, then two post-increments are invalid
529 because the assembler insn would increment only once. On the
530 other hand, a post-increment matches ordinary indexing if the
531 post-increment is the output operand. */
532 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
533 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
535 /* Two pre-increments are invalid because the assembler insn would
536 increment only once. On the other hand, a pre-increment matches
537 ordinary indexing if the pre-increment is the input operand. */
538 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
539 || GET_CODE (y
) == PRE_MODIFY
)
540 return operands_match_p (x
, XEXP (y
, 0), -1);
544 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
545 && x
== SUBREG_REG (y
))
547 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
548 && SUBREG_REG (x
) == y
)
551 /* Now we have disposed of all the cases in which different rtx
553 if (code
!= GET_CODE (y
))
556 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
557 if (GET_MODE (x
) != GET_MODE (y
))
566 return XEXP (x
, 0) == XEXP (y
, 0);
568 return XSTR (x
, 0) == XSTR (y
, 0);
574 /* Compare the elements. If any pair of corresponding elements fail
575 to match, return false for the whole things. */
577 fmt
= GET_RTX_FORMAT (code
);
578 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
584 if (XWINT (x
, i
) != XWINT (y
, i
))
589 if (XINT (x
, i
) != XINT (y
, i
))
594 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
603 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
605 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
607 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
613 /* It is believed that rtx's at this level will never
614 contain anything but integers and other rtx's, except for
615 within LABEL_REFs and SYMBOL_REFs. */
623 /* True if X is a constant that can be forced into the constant pool.
624 MODE is the mode of the operand, or VOIDmode if not known. */
625 #define CONST_POOL_OK_P(MODE, X) \
626 ((MODE) != VOIDmode \
628 && GET_CODE (X) != HIGH \
629 && !targetm.cannot_force_const_mem (MODE, X))
631 /* True if C is a non-empty register class that has too few registers
632 to be safely used as a reload target class. */
633 #define SMALL_REGISTER_CLASS_P(C) \
634 (reg_class_size [(C)] == 1 \
635 || (reg_class_size [(C)] >= 1 && targetm.class_likely_spilled_p (C)))
637 /* If REG is a reload pseudo, try to make its class satisfying CL. */
639 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
641 enum reg_class rclass
;
643 /* Do not make more accurate class from reloads generated. They are
644 mostly moves with a lot of constraints. Making more accurate
645 class may results in very narrow class and impossibility of find
646 registers for several reloads of one insn. */
647 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
649 if (GET_CODE (reg
) == SUBREG
)
650 reg
= SUBREG_REG (reg
);
651 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
653 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
654 change_class (REGNO (reg
), rclass
, " Change", true);
657 /* Generate reloads for matching OUT and INS (array of input operand
658 numbers with end marker -1) with reg class GOAL_CLASS. Add input
659 and output reloads correspondingly to the lists *BEFORE and
662 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
663 rtx
*before
, rtx
*after
)
666 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
667 enum machine_mode inmode
, outmode
;
668 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
669 rtx out_rtx
= *curr_id
->operand_loc
[out
];
671 outmode
= curr_operand_mode
[out
];
672 inmode
= curr_operand_mode
[ins
[0]];
673 push_to_sequence (*before
);
674 if (inmode
!= outmode
)
676 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
679 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
681 if (SCALAR_INT_MODE_P (inmode
))
682 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
684 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
689 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
691 if (SCALAR_INT_MODE_P (outmode
))
692 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
694 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
695 /* NEW_IN_REG is non-paradoxical subreg. We don't want
696 NEW_OUT_REG living above. We add clobber clause for
697 this. This is just a temporary clobber. We can remove
698 it at the end of LRA work. */
699 clobber
= emit_clobber (new_out_reg
);
700 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
705 /* Pseudos have values -- see comments for lra_reg_info.
706 Different pseudos with the same value do not conflict even if
707 they live in the same place. When we create a pseudo we
708 assign value of original pseudo (if any) from which we
709 created the new pseudo. If we create the pseudo from the
710 input pseudo, the new pseudo will no conflict with the input
711 pseudo which is wrong when the input pseudo lives after the
712 insn and as the new pseudo value is changed by the insn
713 output. Therefore we create the new pseudo from the output.
715 We cannot reuse the current output register because we might
716 have a situation like "a <- a op b", where the constraints
717 force the second input operand ("b") to match the output
718 operand ("a"). "b" must then be copied into a new register
719 so that it doesn't clobber the current value of "a". */
721 new_in_reg
= new_out_reg
722 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
725 /* In and out operand can be got from transformations before
726 processing insn constraints. One example of such transformations
727 is subreg reloading (see function simplify_operand_subreg). The
728 new pseudos created by the transformations might have inaccurate
729 class (ALL_REGS) and we should make their classes more
731 narrow_reload_pseudo_class (in_rtx
, goal_class
);
732 narrow_reload_pseudo_class (out_rtx
, goal_class
);
733 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
734 *before
= get_insns ();
736 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
739 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
740 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
741 *curr_id
->operand_loc
[in
] = new_in_reg
;
743 lra_update_dups (curr_id
, ins
);
744 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
747 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
749 *after
= get_insns ();
752 *curr_id
->operand_loc
[out
] = new_out_reg
;
753 lra_update_dup (curr_id
, out
);
756 /* Return register class which is union of all reg classes in insn
757 constraint alternative string starting with P. */
758 static enum reg_class
759 reg_class_from_constraints (const char *p
)
762 enum reg_class op_class
= NO_REGS
;
765 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
772 op_class
= (reg_class_subunion
773 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
779 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
783 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
785 #ifdef EXTRA_CONSTRAINT_STR
786 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
788 = (reg_class_subunion
789 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
796 = reg_class_subunion
[op_class
][REG_CLASS_FROM_CONSTRAINT (c
, p
)];
799 while ((p
+= len
), c
);
803 /* If OP is a register, return the class of the register as per
804 get_reg_class, otherwise return NO_REGS. */
805 static inline enum reg_class
806 get_op_class (rtx op
)
808 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
811 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
812 otherwise. If modes of MEM_PSEUDO and VAL are different, use
813 SUBREG for VAL to make them equal. */
815 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
817 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
818 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
819 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
822 ? gen_move_insn (mem_pseudo
, val
)
823 : gen_move_insn (val
, mem_pseudo
));
826 /* Process a special case insn (register move), return true if we
827 don't need to process it anymore. Return that RTL was changed
828 through CHANGE_P and macro SECONDARY_MEMORY_NEEDED says to use
829 secondary memory through SEC_MEM_P. */
831 check_and_process_move (bool *change_p
, bool *sec_mem_p
)
834 rtx set
, dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, before
, scratch_reg
;
835 enum reg_class dclass
, sclass
, secondary_class
;
836 enum machine_mode sreg_mode
;
837 secondary_reload_info sri
;
839 *sec_mem_p
= *change_p
= false;
840 if ((set
= single_set (curr_insn
)) == NULL
)
842 dreg
= dest
= SET_DEST (set
);
843 sreg
= src
= SET_SRC (set
);
844 /* Quick check on the right move insn which does not need
846 if ((dclass
= get_op_class (dest
)) != NO_REGS
847 && (sclass
= get_op_class (src
)) != NO_REGS
848 /* The backend guarantees that register moves of cost 2 never
850 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2)
852 if (GET_CODE (dest
) == SUBREG
)
853 dreg
= SUBREG_REG (dest
);
854 if (GET_CODE (src
) == SUBREG
)
855 sreg
= SUBREG_REG (src
);
856 if (! REG_P (dreg
) || ! REG_P (sreg
))
858 sclass
= dclass
= NO_REGS
;
859 dreg
= get_equiv_substitution (dreg
);
861 dclass
= get_reg_class (REGNO (dreg
));
862 if (dclass
== ALL_REGS
)
863 /* ALL_REGS is used for new pseudos created by transformations
864 like reload of SUBREG_REG (see function
865 simplify_operand_subreg). We don't know their class yet. We
866 should figure out the class from processing the insn
867 constraints not in this fast path function. Even if ALL_REGS
868 were a right class for the pseudo, secondary_... hooks usually
869 are not define for ALL_REGS. */
871 sreg_mode
= GET_MODE (sreg
);
873 sreg
= get_equiv_substitution (sreg
);
875 sclass
= get_reg_class (REGNO (sreg
));
876 if (sclass
== ALL_REGS
)
877 /* See comments above. */
879 #ifdef SECONDARY_MEMORY_NEEDED
880 if (dclass
!= NO_REGS
&& sclass
!= NO_REGS
881 && SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
)))
888 sri
.icode
= CODE_FOR_nothing
;
890 secondary_class
= NO_REGS
;
891 /* Set up hard register for a reload pseudo for hook
892 secondary_reload because some targets just ignore unassigned
893 pseudos in the hook. */
894 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
896 dregno
= REGNO (dreg
);
897 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
901 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
903 sregno
= REGNO (sreg
);
904 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
908 if (sclass
!= NO_REGS
)
910 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
911 (reg_class_t
) sclass
,
912 GET_MODE (src
), &sri
);
913 if (sclass
== NO_REGS
914 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
915 && dclass
!= NO_REGS
))
917 enum reg_class old_sclass
= secondary_class
;
918 secondary_reload_info old_sri
= sri
;
921 sri
.icode
= CODE_FOR_nothing
;
924 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
925 (reg_class_t
) dclass
,
927 /* Check the target hook consistency. */
929 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
930 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
931 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
934 reg_renumber
[sregno
] = -1;
936 reg_renumber
[dregno
] = -1;
937 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
941 if (secondary_class
!= NO_REGS
)
942 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
946 if (old_sreg
!= sreg
)
947 sreg
= copy_rtx (sreg
);
948 if (sri
.icode
== CODE_FOR_nothing
)
949 lra_emit_move (new_reg
, sreg
);
952 enum reg_class scratch_class
;
954 scratch_class
= (reg_class_from_constraints
955 (insn_data
[sri
.icode
].operand
[2].constraint
));
956 scratch_reg
= (lra_create_new_reg_with_unique_value
957 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
958 scratch_class
, "scratch"));
959 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
962 before
= get_insns ();
964 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Inserting the move");
965 if (new_reg
!= NULL_RTX
)
967 if (GET_CODE (src
) == SUBREG
)
968 SUBREG_REG (src
) = new_reg
;
970 SET_SRC (set
) = new_reg
;
974 if (lra_dump_file
!= NULL
)
976 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
977 debug_rtl_slim (lra_dump_file
, curr_insn
, curr_insn
, -1, 0);
979 lra_set_insn_deleted (curr_insn
);
985 /* The following data describe the result of process_alt_operands.
986 The data are used in curr_insn_transform to generate reloads. */
988 /* The chosen reg classes which should be used for the corresponding
990 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
991 /* True if the operand should be the same as another operand and that
992 other operand does not need a reload. */
993 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
994 /* True if the operand does not need a reload. */
995 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
996 /* True if the operand can be offsetable memory. */
997 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
998 /* The number of an operand to which given operand can be matched to. */
999 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1000 /* The number of elements in the following array. */
1001 static int goal_alt_dont_inherit_ops_num
;
1002 /* Numbers of operands whose reload pseudos should not be inherited. */
1003 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1004 /* True if the insn commutative operands should be swapped. */
1005 static bool goal_alt_swapped
;
1006 /* The chosen insn alternative. */
1007 static int goal_alt_number
;
1009 /* The following five variables are used to choose the best insn
1010 alternative. They reflect final characteristics of the best
1013 /* Number of necessary reloads and overall cost reflecting the
1014 previous value and other unpleasantness of the best alternative. */
1015 static int best_losers
, best_overall
;
1016 /* Number of small register classes used for operands of the best
1018 static int best_small_class_operands_num
;
1019 /* Overall number hard registers used for reloads. For example, on
1020 some targets we need 2 general registers to reload DFmode and only
1021 one floating point register. */
1022 static int best_reload_nregs
;
1023 /* Overall number reflecting distances of previous reloading the same
1024 value. The distances are counted from the current BB start. It is
1025 used to improve inheritance chances. */
1026 static int best_reload_sum
;
1028 /* True if the current insn should have no correspondingly input or
1030 static bool no_input_reloads_p
, no_output_reloads_p
;
1032 /* True if we swapped the commutative operands in the current
1034 static int curr_swapped
;
1036 /* Arrange for address element *LOC to be a register of class CL.
1037 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1038 automodified value; handle that case by adding the required output
1039 reloads to list AFTER. Return true if the RTL was changed. */
1041 process_addr_reg (rtx
*loc
, rtx
*before
, rtx
*after
, enum reg_class cl
)
1044 enum reg_class rclass
, new_class
;
1047 enum machine_mode mode
;
1048 bool before_p
= false;
1050 loc
= strip_subreg (loc
);
1052 mode
= GET_MODE (reg
);
1055 /* Always reload memory in an address even if the target supports
1057 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1062 regno
= REGNO (reg
);
1063 rclass
= get_reg_class (regno
);
1064 if ((*loc
= get_equiv_substitution (reg
)) != reg
)
1066 if (lra_dump_file
!= NULL
)
1068 fprintf (lra_dump_file
,
1069 "Changing pseudo %d in address of insn %u on equiv ",
1070 REGNO (reg
), INSN_UID (curr_insn
));
1071 print_value_slim (lra_dump_file
, *loc
, 1);
1072 fprintf (lra_dump_file
, "\n");
1074 *loc
= copy_rtx (*loc
);
1076 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1079 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1080 mode
, reg
, cl
, "address", &new_reg
))
1083 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1085 change_class (regno
, new_class
, " Change", true);
1093 push_to_sequence (*before
);
1094 lra_emit_move (new_reg
, reg
);
1095 *before
= get_insns ();
1102 lra_emit_move (reg
, new_reg
);
1104 *after
= get_insns ();
1110 /* Make reloads for subreg in operand NOP with internal subreg mode
1111 REG_MODE, add new reloads for further processing. Return true if
1112 any reload was generated. */
1114 simplify_operand_subreg (int nop
, enum machine_mode reg_mode
)
1118 enum machine_mode mode
;
1120 rtx operand
= *curr_id
->operand_loc
[nop
];
1122 before
= after
= NULL_RTX
;
1124 if (GET_CODE (operand
) != SUBREG
)
1127 mode
= GET_MODE (operand
);
1128 reg
= SUBREG_REG (operand
);
1129 /* If we change address for paradoxical subreg of memory, the
1130 address might violate the necessary alignment or the access might
1131 be slow. So take this into consideration. */
1133 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1134 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1135 || (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
))
1137 alter_subreg (curr_id
->operand_loc
[nop
], false);
1140 /* Put constant into memory when we have mixed modes. It generates
1141 a better code in most cases as it does not need a secondary
1142 reload memory. It also prevents LRA looping when LRA is using
1143 secondary reload memory again and again. */
1144 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1145 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1147 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1148 alter_subreg (curr_id
->operand_loc
[nop
], false);
1151 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1152 if there may be a problem accessing OPERAND in the outer
1155 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1156 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1157 /* Don't reload paradoxical subregs because we could be looping
1158 having repeatedly final regno out of hard regs range. */
1159 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1160 >= hard_regno_nregs
[hard_regno
][mode
])
1161 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1162 SUBREG_BYTE (operand
), mode
) < 0)
1163 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1165 enum op_type type
= curr_static_id
->operand
[nop
].type
;
1166 /* The class will be defined later in curr_insn_transform. */
1167 enum reg_class rclass
1168 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1170 new_reg
= lra_create_new_reg_with_unique_value (reg_mode
, reg
, rclass
,
1172 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (new_reg
));
1174 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
))
1176 push_to_sequence (before
);
1177 lra_emit_move (new_reg
, reg
);
1178 before
= get_insns ();
1184 lra_emit_move (reg
, new_reg
);
1186 after
= get_insns ();
1189 SUBREG_REG (operand
) = new_reg
;
1190 lra_process_new_insns (curr_insn
, before
, after
,
1191 "Inserting subreg reload");
1197 /* Return TRUE if X refers for a hard register from SET. */
1199 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1201 int i
, j
, x_hard_regno
;
1202 enum machine_mode mode
;
1208 code
= GET_CODE (x
);
1209 mode
= GET_MODE (x
);
1213 code
= GET_CODE (x
);
1214 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1215 mode
= GET_MODE (x
);
1220 x_hard_regno
= get_hard_regno (x
);
1221 return (x_hard_regno
>= 0
1222 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1226 struct address_info ad
;
1228 decompose_mem_address (&ad
, x
);
1229 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1231 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1234 fmt
= GET_RTX_FORMAT (code
);
1235 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1239 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1242 else if (fmt
[i
] == 'E')
1244 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1245 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1252 /* Return true if OP is a spilled pseudo. */
1254 spilled_pseudo_p (rtx op
)
1257 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1260 /* Return true if X is a general constant. */
1262 general_constant_p (rtx x
)
1264 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1267 /* Cost factor for each additional reload and maximal cost bound for
1268 insn reloads. One might ask about such strange numbers. Their
1269 values occurred historically from former reload pass. */
1270 #define LOSER_COST_FACTOR 6
1271 #define MAX_OVERALL_COST_BOUND 600
1273 /* Major function to choose the current insn alternative and what
1274 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1275 negative we should consider only this alternative. Return false if
1276 we can not choose the alternative or find how to reload the
1279 process_alt_operands (int only_alternative
)
1282 int nop
, small_class_operands_num
, overall
, nalt
;
1283 int n_alternatives
= curr_static_id
->n_alternatives
;
1284 int n_operands
= curr_static_id
->n_operands
;
1285 /* LOSERS counts the operands that don't fit this alternative and
1286 would require loading. */
1288 /* REJECT is a count of how undesirable this alternative says it is
1289 if any reloading is required. If the alternative matches exactly
1290 then REJECT is ignored, but otherwise it gets this much counted
1291 against it in addition to the reloading needed. */
1293 /* The number of elements in the following array. */
1294 int early_clobbered_regs_num
;
1295 /* Numbers of operands which are early clobber registers. */
1296 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1297 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1298 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1299 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1300 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1301 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1302 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1303 /* The number of elements in the following array. */
1304 int curr_alt_dont_inherit_ops_num
;
1305 /* Numbers of operands whose reload pseudos should not be inherited. */
1306 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1308 /* The register when the operand is a subreg of register, otherwise the
1310 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1311 /* The register if the operand is a register or subreg of register,
1313 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1314 int hard_regno
[MAX_RECOG_OPERANDS
];
1315 enum machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1316 int reload_nregs
, reload_sum
;
1320 /* Calculate some data common for all alternatives to speed up the
1322 for (nop
= 0; nop
< n_operands
; nop
++)
1324 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1325 /* The real hard regno of the operand after the allocation. */
1326 hard_regno
[nop
] = get_hard_regno (op
);
1328 operand_reg
[nop
] = op
;
1329 biggest_mode
[nop
] = GET_MODE (operand_reg
[nop
]);
1330 if (GET_CODE (operand_reg
[nop
]) == SUBREG
)
1332 operand_reg
[nop
] = SUBREG_REG (operand_reg
[nop
]);
1333 if (GET_MODE_SIZE (biggest_mode
[nop
])
1334 < GET_MODE_SIZE (GET_MODE (operand_reg
[nop
])))
1335 biggest_mode
[nop
] = GET_MODE (operand_reg
[nop
]);
1337 if (REG_P (operand_reg
[nop
]))
1338 no_subreg_reg_operand
[nop
] = operand_reg
[nop
];
1340 operand_reg
[nop
] = NULL_RTX
;
1343 /* The constraints are made of several alternatives. Each operand's
1344 constraint looks like foo,bar,... with commas separating the
1345 alternatives. The first alternatives for all operands go
1346 together, the second alternatives go together, etc.
1348 First loop over alternatives. */
1349 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1351 /* Loop over operands for one constraint alternative. */
1352 #ifdef HAVE_ATTR_enabled
1353 if (curr_id
->alternative_enabled_p
!= NULL
1354 && ! curr_id
->alternative_enabled_p
[nalt
])
1358 if (only_alternative
>= 0 && nalt
!= only_alternative
)
1361 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1362 for (nop
= 0; nop
< n_operands
; nop
++)
1363 reject
+= (curr_static_id
1364 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1365 early_clobbered_regs_num
= 0;
1367 for (nop
= 0; nop
< n_operands
; nop
++)
1371 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1372 bool win
, did_match
, offmemok
, early_clobber_p
;
1373 /* false => this operand can be reloaded somehow for this
1376 /* true => this operand can be reloaded if the alternative
1379 /* True if a constant forced into memory would be OK for
1382 enum reg_class this_alternative
, this_costly_alternative
;
1383 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1384 bool this_alternative_match_win
, this_alternative_win
;
1385 bool this_alternative_offmemok
;
1386 enum machine_mode mode
;
1388 opalt_num
= nalt
* n_operands
+ nop
;
1389 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1391 /* Fast track for no constraints at all. */
1392 curr_alt
[nop
] = NO_REGS
;
1393 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1394 curr_alt_win
[nop
] = true;
1395 curr_alt_match_win
[nop
] = false;
1396 curr_alt_offmemok
[nop
] = false;
1397 curr_alt_matches
[nop
] = -1;
1401 op
= no_subreg_reg_operand
[nop
];
1402 mode
= curr_operand_mode
[nop
];
1404 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1407 early_clobber_p
= false;
1408 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1410 this_costly_alternative
= this_alternative
= NO_REGS
;
1411 /* We update set of possible hard regs besides its class
1412 because reg class might be inaccurate. For example,
1413 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1414 is translated in HI_REGS because classes are merged by
1415 pairs and there is no accurate intermediate class. */
1416 CLEAR_HARD_REG_SET (this_alternative_set
);
1417 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1418 this_alternative_win
= false;
1419 this_alternative_match_win
= false;
1420 this_alternative_offmemok
= false;
1421 this_alternative_matches
= -1;
1423 /* An empty constraint should be excluded by the fast
1425 lra_assert (*p
!= 0 && *p
!= ',');
1427 /* Scan this alternative's specs for this operand; set WIN
1428 if the operand fits any letter in this alternative.
1429 Otherwise, clear BADOP if this operand could fit some
1430 letter after reloads, or set WINREG if this operand could
1431 fit after reloads provided the constraint allows some
1436 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1445 case '=': case '+': case '?': case '*': case '!':
1446 case ' ': case '\t':
1450 /* We only support one commutative marker, the first
1451 one. We already set commutative above. */
1455 early_clobber_p
= true;
1459 /* Ignore rest of this alternative. */
1463 case '0': case '1': case '2': case '3': case '4':
1464 case '5': case '6': case '7': case '8': case '9':
1469 m
= strtoul (p
, &end
, 10);
1472 lra_assert (nop
> m
);
1474 this_alternative_matches
= m
;
1475 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1476 /* We are supposed to match a previous operand.
1477 If we do, we win if that one did. If we do
1478 not, count both of the operands as losers.
1479 (This is too conservative, since most of the
1480 time only a single reload insn will be needed
1481 to make the two operands win. As a result,
1482 this alternative may be rejected when it is
1483 actually desirable.) */
1485 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1486 *curr_id
->operand_loc
[m
], m_hregno
))
1488 /* We should reject matching of an early
1489 clobber operand if the matching operand is
1490 not dying in the insn. */
1491 if (! curr_static_id
->operand
[m
].early_clobber
1492 || operand_reg
[nop
] == NULL_RTX
1493 || (find_regno_note (curr_insn
, REG_DEAD
,
1494 REGNO (operand_reg
[nop
]))
1500 /* If we are matching a non-offsettable
1501 address where an offsettable address was
1502 expected, then we must reject this
1503 combination, because we can't reload
1505 if (curr_alt_offmemok
[m
]
1506 && MEM_P (*curr_id
->operand_loc
[m
])
1507 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1513 /* Operands don't match. Both operands must
1514 allow a reload register, otherwise we
1515 cannot make them match. */
1516 if (curr_alt
[m
] == NO_REGS
)
1518 /* Retroactively mark the operand we had to
1519 match as a loser, if it wasn't already and
1520 it wasn't matched to a register constraint
1521 (e.g it might be matched by memory). */
1523 && (operand_reg
[m
] == NULL_RTX
1524 || hard_regno
[m
] < 0))
1528 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1529 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1532 /* We prefer no matching alternatives because
1533 it gives more freedom in RA. */
1534 if (operand_reg
[nop
] == NULL_RTX
1535 || (find_regno_note (curr_insn
, REG_DEAD
,
1536 REGNO (operand_reg
[nop
]))
1540 /* If we have to reload this operand and some
1541 previous operand also had to match the same
1542 thing as this operand, we don't know how to do
1544 if (!match_p
|| !curr_alt_win
[m
])
1546 for (i
= 0; i
< nop
; i
++)
1547 if (curr_alt_matches
[i
] == m
)
1555 /* This can be fixed with reloads if the operand
1556 we are supposed to match can be fixed with
1559 this_alternative
= curr_alt
[m
];
1560 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1565 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1567 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1568 IOR_HARD_REG_SET (this_alternative_set
,
1569 reg_class_contents
[cl
]);
1572 this_costly_alternative
1573 = reg_class_subunion
[this_costly_alternative
][cl
];
1574 IOR_HARD_REG_SET (this_costly_alternative_set
,
1575 reg_class_contents
[cl
]);
1581 case TARGET_MEM_CONSTRAINT
:
1582 if (MEM_P (op
) || spilled_pseudo_p (op
))
1584 if (CONST_POOL_OK_P (mode
, op
))
1591 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1592 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1598 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1599 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1603 /* Memory op whose address is not offsettable. */
1606 && ! offsettable_nonstrict_memref_p (op
))
1610 /* Memory operand whose address is offsettable. */
1613 && offsettable_nonstrict_memref_p (op
))
1614 || spilled_pseudo_p (op
))
1616 if (CONST_POOL_OK_P (mode
, op
) || MEM_P (op
))
1624 if (GET_CODE (op
) == CONST_DOUBLE
1625 || (GET_CODE (op
) == CONST_VECTOR
1626 && (GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)))
1632 if (GET_CODE (op
) == CONST_DOUBLE
1633 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1638 if (CONST_INT_P (op
)
1639 || (GET_CODE (op
) == CONST_DOUBLE
&& mode
== VOIDmode
))
1642 if (general_constant_p (op
))
1647 if (CONST_INT_P (op
)
1648 || (GET_CODE (op
) == CONST_DOUBLE
&& mode
== VOIDmode
))
1660 if (CONST_INT_P (op
)
1661 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
1666 /* This constraint should be excluded by the fast
1673 || general_constant_p (op
)
1674 || spilled_pseudo_p (op
))
1676 /* Drop through into 'r' case. */
1680 = reg_class_subunion
[this_alternative
][GENERAL_REGS
];
1681 IOR_HARD_REG_SET (this_alternative_set
,
1682 reg_class_contents
[GENERAL_REGS
]);
1685 this_costly_alternative
1686 = (reg_class_subunion
1687 [this_costly_alternative
][GENERAL_REGS
]);
1688 IOR_HARD_REG_SET (this_costly_alternative_set
,
1689 reg_class_contents
[GENERAL_REGS
]);
1694 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
1696 #ifdef EXTRA_CONSTRAINT_STR
1697 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
1699 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1701 else if (spilled_pseudo_p (op
))
1704 /* If we didn't already win, we can reload
1705 constants via force_const_mem, and other
1706 MEMs by reloading the address like for
1708 if (CONST_POOL_OK_P (mode
, op
) || MEM_P (op
))
1714 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1716 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1719 /* If we didn't already win, we can reload
1720 the address into a base register. */
1721 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1724 = reg_class_subunion
[this_alternative
][cl
];
1725 IOR_HARD_REG_SET (this_alternative_set
,
1726 reg_class_contents
[cl
]);
1729 this_costly_alternative
1730 = (reg_class_subunion
1731 [this_costly_alternative
][cl
]);
1732 IOR_HARD_REG_SET (this_costly_alternative_set
,
1733 reg_class_contents
[cl
]);
1739 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1745 cl
= REG_CLASS_FROM_CONSTRAINT (c
, p
);
1746 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1747 IOR_HARD_REG_SET (this_alternative_set
,
1748 reg_class_contents
[cl
]);
1751 this_costly_alternative
1752 = reg_class_subunion
[this_costly_alternative
][cl
];
1753 IOR_HARD_REG_SET (this_costly_alternative_set
,
1754 reg_class_contents
[cl
]);
1757 if (mode
== BLKmode
)
1762 if (hard_regno
[nop
] >= 0
1763 && in_hard_reg_set_p (this_alternative_set
,
1764 mode
, hard_regno
[nop
]))
1766 else if (hard_regno
[nop
] < 0
1767 && in_class_p (op
, this_alternative
, NULL
))
1772 if (c
!= ' ' && c
!= '\t')
1773 costly_p
= c
== '*';
1775 while ((p
+= len
), c
);
1777 /* Record which operands fit this alternative. */
1780 this_alternative_win
= true;
1781 if (operand_reg
[nop
] != NULL_RTX
)
1783 if (hard_regno
[nop
] >= 0)
1785 if (in_hard_reg_set_p (this_costly_alternative_set
,
1786 mode
, hard_regno
[nop
]))
1791 /* Prefer won reg to spilled pseudo under other equal
1794 if (in_class_p (operand_reg
[nop
],
1795 this_costly_alternative
, NULL
))
1798 /* We simulate the behaviour of old reload here.
1799 Although scratches need hard registers and it
1800 might result in spilling other pseudos, no reload
1801 insns are generated for the scratches. So it
1802 might cost something but probably less than old
1803 reload pass believes. */
1804 if (lra_former_scratch_p (REGNO (operand_reg
[nop
])))
1805 reject
+= LOSER_COST_FACTOR
;
1809 this_alternative_match_win
= true;
1812 int const_to_mem
= 0;
1816 = (this_alternative
== NO_REGS
1817 || (hard_reg_set_subset_p
1818 (reg_class_contents
[this_alternative
],
1819 lra_no_alloc_regs
)));
1820 /* If this operand accepts a register, and if the
1821 register class has at least one allocatable register,
1822 then this operand can be reloaded. */
1823 if (winreg
&& !no_regs_p
)
1829 this_alternative_offmemok
= offmemok
;
1830 if (this_costly_alternative
!= NO_REGS
)
1832 /* If the operand is dying, has a matching constraint,
1833 and satisfies constraints of the matched operand
1834 which failed to satisfy the own constraints, we do
1835 not need to generate a reload insn for this
1837 if (!(this_alternative_matches
>= 0
1838 && !curr_alt_win
[this_alternative_matches
]
1840 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
1841 && (hard_regno
[nop
] >= 0
1842 ? in_hard_reg_set_p (this_alternative_set
,
1843 mode
, hard_regno
[nop
])
1844 : in_class_p (op
, this_alternative
, NULL
))))
1846 if (operand_reg
[nop
] != NULL_RTX
1847 /* Output operands and matched input operands are
1848 not inherited. The following conditions do not
1849 exactly describe the previous statement but they
1850 are pretty close. */
1851 && curr_static_id
->operand
[nop
].type
!= OP_OUT
1852 && (this_alternative_matches
< 0
1853 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
1855 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
1859 if (last_reload
> bb_reload_num
)
1860 reload_sum
+= last_reload
- bb_reload_num
;
1862 /* If this is a constant that is reloaded into the
1863 desired class by copying it to memory first, count
1864 that as another reload. This is consistent with
1865 other code and is required to avoid choosing another
1866 alternative when the constant is moved into memory.
1867 Note that the test here is precisely the same as in
1868 the code below that calls force_const_mem. */
1869 if (CONST_POOL_OK_P (mode
, op
)
1870 && ((targetm
.preferred_reload_class
1871 (op
, this_alternative
) == NO_REGS
)
1872 || no_input_reloads_p
))
1879 /* Alternative loses if it requires a type of reload not
1880 permitted for this insn. We can always reload
1881 objects with a REG_UNUSED note. */
1882 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
1883 && no_output_reloads_p
1884 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
1885 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
1886 && no_input_reloads_p
&& ! const_to_mem
))
1889 /* If we can't reload this value at all, reject this
1890 alternative. Note that we could also lose due to
1891 LIMIT_RELOAD_CLASS, but we don't check that here. */
1892 if (! CONSTANT_P (op
) && ! no_regs_p
)
1894 if (targetm
.preferred_reload_class
1895 (op
, this_alternative
) == NO_REGS
)
1896 reject
= MAX_OVERALL_COST_BOUND
;
1898 if (curr_static_id
->operand
[nop
].type
== OP_OUT
1899 && (targetm
.preferred_output_reload_class
1900 (op
, this_alternative
) == NO_REGS
))
1901 reject
= MAX_OVERALL_COST_BOUND
;
1904 if (! ((const_to_mem
&& constmemok
)
1905 || (MEM_P (op
) && offmemok
)))
1907 /* We prefer to reload pseudos over reloading other
1908 things, since such reloads may be able to be
1909 eliminated later. So bump REJECT in other cases.
1910 Don't do this in the case where we are forcing a
1911 constant into memory and it will then win since
1912 we don't want to have a different alternative
1914 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
1919 += ira_reg_class_max_nregs
[this_alternative
][mode
];
1922 /* Input reloads can be inherited more often than output
1923 reloads can be removed, so penalize output
1925 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
1929 if (early_clobber_p
)
1931 /* ??? We check early clobbers after processing all operands
1932 (see loop below) and there we update the costs more.
1933 Should we update the cost (may be approximately) here
1934 because of early clobber register reloads or it is a rare
1935 or non-important thing to be worth to do it. */
1936 overall
= losers
* LOSER_COST_FACTOR
+ reject
;
1937 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
1940 curr_alt
[nop
] = this_alternative
;
1941 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
1942 curr_alt_win
[nop
] = this_alternative_win
;
1943 curr_alt_match_win
[nop
] = this_alternative_match_win
;
1944 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
1945 curr_alt_matches
[nop
] = this_alternative_matches
;
1947 if (this_alternative_matches
>= 0
1948 && !did_match
&& !this_alternative_win
)
1949 curr_alt_win
[this_alternative_matches
] = false;
1951 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
1952 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
1955 curr_alt_dont_inherit_ops_num
= 0;
1956 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
1958 int i
, j
, clobbered_hard_regno
;
1959 HARD_REG_SET temp_set
;
1961 i
= early_clobbered_nops
[nop
];
1962 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
1963 || hard_regno
[i
] < 0)
1965 clobbered_hard_regno
= hard_regno
[i
];
1966 CLEAR_HARD_REG_SET (temp_set
);
1967 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
1968 for (j
= 0; j
< n_operands
; j
++)
1970 /* We don't want process insides of match_operator and
1971 match_parallel because otherwise we would process
1972 their operands once again generating a wrong
1974 || curr_static_id
->operand
[j
].is_operator
)
1976 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
1977 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
1979 else if (uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
1981 if (j
>= n_operands
)
1983 /* We need to reload early clobbered register. */
1984 for (j
= 0; j
< n_operands
; j
++)
1985 if (curr_alt_matches
[j
] == i
)
1987 curr_alt_match_win
[j
] = false;
1989 overall
+= LOSER_COST_FACTOR
;
1991 if (! curr_alt_match_win
[i
])
1992 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
1995 /* Remember pseudos used for match reloads are never
1997 lra_assert (curr_alt_matches
[i
] >= 0);
1998 curr_alt_win
[curr_alt_matches
[i
]] = false;
2000 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2002 overall
+= LOSER_COST_FACTOR
;
2004 small_class_operands_num
= 0;
2005 for (nop
= 0; nop
< n_operands
; nop
++)
2006 small_class_operands_num
2007 += SMALL_REGISTER_CLASS_P (curr_alt
[nop
]) ? 1 : 0;
2009 /* If this alternative can be made to work by reloading, and it
2010 needs less reloading than the others checked so far, record
2011 it as the chosen goal for reloading. */
2012 if ((best_losers
!= 0 && losers
== 0)
2013 || (((best_losers
== 0 && losers
== 0)
2014 || (best_losers
!= 0 && losers
!= 0))
2015 && (best_overall
> overall
2016 || (best_overall
== overall
2017 /* If the cost of the reloads is the same,
2018 prefer alternative which requires minimal
2019 number of small register classes for the
2020 operands. This improves chances of reloads
2021 for insn requiring small register
2023 && (small_class_operands_num
2024 < best_small_class_operands_num
2025 || (small_class_operands_num
2026 == best_small_class_operands_num
2027 && (reload_nregs
< best_reload_nregs
2028 || (reload_nregs
== best_reload_nregs
2029 && best_reload_sum
< reload_sum
))))))))
2031 for (nop
= 0; nop
< n_operands
; nop
++)
2033 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2034 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2035 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2036 goal_alt
[nop
] = curr_alt
[nop
];
2037 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2039 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2040 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2041 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2042 goal_alt_swapped
= curr_swapped
;
2043 best_overall
= overall
;
2044 best_losers
= losers
;
2045 best_small_class_operands_num
= small_class_operands_num
;
2046 best_reload_nregs
= reload_nregs
;
2047 best_reload_sum
= reload_sum
;
2048 goal_alt_number
= nalt
;
2051 /* Everything is satisfied. Do not process alternatives
2060 /* Return 1 if ADDR is a valid memory address for mode MODE in address
2061 space AS, and check that each pseudo has the proper kind of hard
2064 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2065 rtx addr
, addr_space_t as
)
2067 #ifdef GO_IF_LEGITIMATE_ADDRESS
2068 lra_assert (ADDR_SPACE_GENERIC_P (as
));
2069 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
2075 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
2079 /* Return whether address AD is valid. */
2082 valid_address_p (struct address_info
*ad
)
2084 /* Some ports do not check displacements for eliminable registers,
2085 so we replace them temporarily with the elimination target. */
2086 rtx saved_base_reg
= NULL_RTX
;
2087 rtx saved_index_reg
= NULL_RTX
;
2088 rtx
*base_term
= strip_subreg (ad
->base_term
);
2089 rtx
*index_term
= strip_subreg (ad
->index_term
);
2090 if (base_term
!= NULL
)
2092 saved_base_reg
= *base_term
;
2093 lra_eliminate_reg_if_possible (base_term
);
2094 if (ad
->base_term2
!= NULL
)
2095 *ad
->base_term2
= *ad
->base_term
;
2097 if (index_term
!= NULL
)
2099 saved_index_reg
= *index_term
;
2100 lra_eliminate_reg_if_possible (index_term
);
2102 bool ok_p
= valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
2103 if (saved_base_reg
!= NULL_RTX
)
2105 *base_term
= saved_base_reg
;
2106 if (ad
->base_term2
!= NULL
)
2107 *ad
->base_term2
= *ad
->base_term
;
2109 if (saved_index_reg
!= NULL_RTX
)
2110 *index_term
= saved_index_reg
;
2114 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2116 base_plus_disp_to_reg (struct address_info
*ad
)
2121 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2122 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2123 get_index_code (ad
));
2124 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2126 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2130 /* Return true if we can add a displacement to address AD, even if that
2131 makes the address invalid. The fix-up code requires any new address
2132 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2134 can_add_disp_p (struct address_info
*ad
)
2136 return (!ad
->autoinc_p
2137 && ad
->segment
== NULL
2138 && ad
->base
== ad
->base_term
2139 && ad
->disp
== ad
->disp_term
);
2142 /* Make equiv substitution in address AD. Return true if a substitution
2145 equiv_address_substitution (struct address_info
*ad
)
2147 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2148 HOST_WIDE_INT disp
, scale
;
2151 base_term
= strip_subreg (ad
->base_term
);
2152 if (base_term
== NULL
)
2153 base_reg
= new_base_reg
= NULL_RTX
;
2156 base_reg
= *base_term
;
2157 new_base_reg
= get_equiv_substitution (base_reg
);
2159 index_term
= strip_subreg (ad
->index_term
);
2160 if (index_term
== NULL
)
2161 index_reg
= new_index_reg
= NULL_RTX
;
2164 index_reg
= *index_term
;
2165 new_index_reg
= get_equiv_substitution (index_reg
);
2167 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2171 if (lra_dump_file
!= NULL
)
2173 fprintf (lra_dump_file
, "Changing address in insn %d ",
2174 INSN_UID (curr_insn
));
2175 print_value_slim (lra_dump_file
, *ad
->outer
, 1);
2177 if (base_reg
!= new_base_reg
)
2179 if (REG_P (new_base_reg
))
2181 *base_term
= new_base_reg
;
2184 else if (GET_CODE (new_base_reg
) == PLUS
2185 && REG_P (XEXP (new_base_reg
, 0))
2186 && CONST_INT_P (XEXP (new_base_reg
, 1))
2187 && can_add_disp_p (ad
))
2189 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2190 *base_term
= XEXP (new_base_reg
, 0);
2193 if (ad
->base_term2
!= NULL
)
2194 *ad
->base_term2
= *ad
->base_term
;
2196 if (index_reg
!= new_index_reg
)
2198 if (REG_P (new_index_reg
))
2200 *index_term
= new_index_reg
;
2203 else if (GET_CODE (new_index_reg
) == PLUS
2204 && REG_P (XEXP (new_index_reg
, 0))
2205 && CONST_INT_P (XEXP (new_index_reg
, 1))
2206 && can_add_disp_p (ad
)
2207 && (scale
= get_index_scale (ad
)))
2209 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2210 *index_term
= XEXP (new_index_reg
, 0);
2216 if (ad
->disp
!= NULL
)
2217 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2220 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2221 update_address (ad
);
2225 if (lra_dump_file
!= NULL
)
2228 fprintf (lra_dump_file
, " -- no change\n");
2231 fprintf (lra_dump_file
, " on equiv ");
2232 print_value_slim (lra_dump_file
, *ad
->outer
, 1);
2233 fprintf (lra_dump_file
, "\n");
2239 /* Major function to make reloads for an address in operand NOP.
2240 The supported cases are:
2242 1) an address that existed before LRA started, at which point it must
2243 have been valid. These addresses are subject to elimination and
2244 may have become invalid due to the elimination offset being out
2247 2) an address created by forcing a constant to memory (force_const_to_mem).
2248 The initial form of these addresses might not be valid, and it is this
2249 function's job to make them valid.
2251 3) a frame address formed from a register and a (possibly zero)
2252 constant offset. As above, these addresses might not be valid
2253 and this function must make them so.
2255 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2256 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2257 address. Return true for any RTL change. */
2259 process_address (int nop
, rtx
*before
, rtx
*after
)
2261 struct address_info ad
;
2263 rtx op
= *curr_id
->operand_loc
[nop
];
2264 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2267 if (constraint
[0] == 'p'
2268 || EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
))
2269 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2270 else if (MEM_P (op
))
2271 decompose_mem_address (&ad
, op
);
2272 else if (GET_CODE (op
) == SUBREG
2273 && MEM_P (SUBREG_REG (op
)))
2274 decompose_mem_address (&ad
, SUBREG_REG (op
));
2277 change_p
= equiv_address_substitution (&ad
);
2278 if (ad
.base_term
!= NULL
2279 && (process_addr_reg
2280 (ad
.base_term
, before
,
2282 && !(REG_P (*ad
.base_term
)
2283 && find_regno_note (curr_insn
, REG_DEAD
,
2284 REGNO (*ad
.base_term
)) != NULL_RTX
)
2286 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2287 get_index_code (&ad
)))))
2290 if (ad
.base_term2
!= NULL
)
2291 *ad
.base_term2
= *ad
.base_term
;
2293 if (ad
.index_term
!= NULL
2294 && process_addr_reg (ad
.index_term
, before
, NULL
, INDEX_REG_CLASS
))
2297 /* There are three cases where the shape of *AD.INNER may now be invalid:
2299 1) the original address was valid, but either elimination or
2300 equiv_address_substitution applied a displacement that made
2303 2) the address is an invalid symbolic address created by
2306 3) the address is a frame address with an invalid offset.
2308 All these cases involve a displacement and a non-autoinc address,
2309 so there is no point revalidating other types. */
2310 if (ad
.disp
== NULL
|| ad
.autoinc_p
|| valid_address_p (&ad
))
2313 /* Any index existed before LRA started, so we can assume that the
2314 presence and shape of the index is valid. */
2315 push_to_sequence (*before
);
2316 gcc_assert (ad
.segment
== NULL
);
2317 gcc_assert (ad
.disp
== ad
.disp_term
);
2318 if (ad
.base
== NULL
)
2320 if (ad
.index
== NULL
)
2323 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2325 rtx disp
= *ad
.disp
;
2327 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2331 rtx last
= get_last_insn ();
2333 /* disp => lo_sum (new_base, disp), case (2) above. */
2334 insn
= emit_insn (gen_rtx_SET
2336 gen_rtx_HIGH (Pmode
, copy_rtx (disp
))));
2337 code
= recog_memoized (insn
);
2340 *ad
.disp
= gen_rtx_LO_SUM (Pmode
, new_reg
, disp
);
2341 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2348 delete_insns_since (last
);
2353 /* disp => new_base, case (2) above. */
2354 lra_emit_move (new_reg
, disp
);
2360 /* index * scale + disp => new base + index * scale,
2362 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2363 GET_CODE (*ad
.index
));
2365 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2366 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2367 lra_emit_move (new_reg
, *ad
.disp
);
2368 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2369 new_reg
, *ad
.index
);
2372 else if (ad
.index
== NULL
)
2374 /* base + disp => new base, cases (1) and (3) above. */
2375 /* Another option would be to reload the displacement into an
2376 index register. However, postreload has code to optimize
2377 address reloads that have the same base and different
2378 displacements, so reloading into an index register would
2379 not necessarily be a win. */
2380 new_reg
= base_plus_disp_to_reg (&ad
);
2381 *ad
.inner
= new_reg
;
2385 /* base + scale * index + disp => new base + scale * index,
2387 new_reg
= base_plus_disp_to_reg (&ad
);
2388 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2389 new_reg
, *ad
.index
);
2391 *before
= get_insns ();
2396 /* Emit insns to reload VALUE into a new register. VALUE is an
2397 auto-increment or auto-decrement RTX whose operand is a register or
2398 memory location; so reloading involves incrementing that location.
2399 IN is either identical to VALUE, or some cheaper place to reload
2400 value being incremented/decremented from.
2402 INC_AMOUNT is the number to increment or decrement by (always
2403 positive and ignored for POST_MODIFY/PRE_MODIFY).
2405 Return pseudo containing the result. */
2407 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
2409 /* REG or MEM to be copied and incremented. */
2410 rtx incloc
= XEXP (value
, 0);
2411 /* Nonzero if increment after copying. */
2412 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
2413 || GET_CODE (value
) == POST_MODIFY
);
2418 rtx real_in
= in
== value
? incloc
: in
;
2422 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
2424 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
2425 || GET_CODE (XEXP (value
, 1)) == MINUS
);
2426 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
2427 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
2428 inc
= XEXP (XEXP (value
, 1), 1);
2432 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
2433 inc_amount
= -inc_amount
;
2435 inc
= GEN_INT (inc_amount
);
2438 if (! post
&& REG_P (incloc
))
2441 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
2444 if (real_in
!= result
)
2446 /* First copy the location to the result register. */
2447 lra_assert (REG_P (result
));
2448 emit_insn (gen_move_insn (result
, real_in
));
2451 /* We suppose that there are insns to add/sub with the constant
2452 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
2453 old reload worked with this assumption. If the assumption
2454 becomes wrong, we should use approach in function
2455 base_plus_disp_to_reg. */
2458 /* See if we can directly increment INCLOC. */
2459 last
= get_last_insn ();
2460 add_insn
= emit_insn (plus_p
2461 ? gen_add2_insn (incloc
, inc
)
2462 : gen_sub2_insn (incloc
, inc
));
2464 code
= recog_memoized (add_insn
);
2467 if (! post
&& result
!= incloc
)
2468 emit_insn (gen_move_insn (result
, incloc
));
2471 delete_insns_since (last
);
2474 /* If couldn't do the increment directly, must increment in RESULT.
2475 The way we do this depends on whether this is pre- or
2476 post-increment. For pre-increment, copy INCLOC to the reload
2477 register, increment it there, then save back. */
2480 if (real_in
!= result
)
2481 emit_insn (gen_move_insn (result
, real_in
));
2483 emit_insn (gen_add2_insn (result
, inc
));
2485 emit_insn (gen_sub2_insn (result
, inc
));
2486 if (result
!= incloc
)
2487 emit_insn (gen_move_insn (incloc
, result
));
2493 Because this might be a jump insn or a compare, and because
2494 RESULT may not be available after the insn in an input
2495 reload, we must do the incrementing before the insn being
2498 We have already copied IN to RESULT. Increment the copy in
2499 RESULT, save that back, then decrement RESULT so it has
2500 the original value. */
2502 emit_insn (gen_add2_insn (result
, inc
));
2504 emit_insn (gen_sub2_insn (result
, inc
));
2505 emit_insn (gen_move_insn (incloc
, result
));
2506 /* Restore non-modified value for the result. We prefer this
2507 way because it does not require an additional hard
2511 if (CONST_INT_P (inc
))
2512 emit_insn (gen_add2_insn (result
, GEN_INT (-INTVAL (inc
))));
2514 emit_insn (gen_sub2_insn (result
, inc
));
2517 emit_insn (gen_add2_insn (result
, inc
));
2522 /* Swap operands NOP and NOP + 1. */
2524 swap_operands (int nop
)
2526 enum machine_mode mode
= curr_operand_mode
[nop
];
2527 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
2528 curr_operand_mode
[nop
+ 1] = mode
;
2529 rtx x
= *curr_id
->operand_loc
[nop
];
2530 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
2531 *curr_id
->operand_loc
[nop
+ 1] = x
;
2532 /* Swap the duplicates too. */
2533 lra_update_dup (curr_id
, nop
);
2534 lra_update_dup (curr_id
, nop
+ 1);
2537 /* Main entry point of the constraint code: search the body of the
2538 current insn to choose the best alternative. It is mimicking insn
2539 alternative cost calculation model of former reload pass. That is
2540 because machine descriptions were written to use this model. This
2541 model can be changed in future. Make commutative operand exchange
2544 Return true if some RTL changes happened during function call. */
2546 curr_insn_transform (void)
2552 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
2555 /* Flag that the insn has been changed through a transformation. */
2558 #ifdef SECONDARY_MEMORY_NEEDED
2561 int max_regno_before
;
2562 int reused_alternative_num
;
2564 no_input_reloads_p
= no_output_reloads_p
= false;
2565 goal_alt_number
= -1;
2567 if (check_and_process_move (&change_p
, &sec_mem_p
))
2570 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
2571 reloads; neither are insns that SET cc0. Insns that use CC0 are
2572 not allowed to have any input reloads. */
2573 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
2574 no_output_reloads_p
= true;
2577 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
2578 no_input_reloads_p
= true;
2579 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
2580 no_output_reloads_p
= true;
2583 n_operands
= curr_static_id
->n_operands
;
2584 n_alternatives
= curr_static_id
->n_alternatives
;
2586 /* Just return "no reloads" if insn has no operands with
2588 if (n_operands
== 0 || n_alternatives
== 0)
2591 max_regno_before
= max_reg_num ();
2593 for (i
= 0; i
< n_operands
; i
++)
2595 goal_alt_matched
[i
][0] = -1;
2596 goal_alt_matches
[i
] = -1;
2599 commutative
= curr_static_id
->commutative
;
2601 /* Now see what we need for pseudos that didn't get hard regs or got
2602 the wrong kind of hard reg. For this, we must consider all the
2603 operands together against the register constraints. */
2605 best_losers
= best_overall
= MAX_RECOG_OPERANDS
* 2 + MAX_OVERALL_COST_BOUND
;
2606 best_small_class_operands_num
= best_reload_sum
= 0;
2608 curr_swapped
= false;
2609 goal_alt_swapped
= false;
2611 /* Make equivalence substitution and memory subreg elimination
2612 before address processing because an address legitimacy can
2613 depend on memory mode. */
2614 for (i
= 0; i
< n_operands
; i
++)
2616 rtx op
= *curr_id
->operand_loc
[i
];
2617 rtx subst
, old
= op
;
2618 bool op_change_p
= false;
2620 if (GET_CODE (old
) == SUBREG
)
2621 old
= SUBREG_REG (old
);
2622 subst
= get_equiv_substitution (old
);
2625 subst
= copy_rtx (subst
);
2626 lra_assert (REG_P (old
));
2627 if (GET_CODE (op
) == SUBREG
)
2628 SUBREG_REG (op
) = subst
;
2630 *curr_id
->operand_loc
[i
] = subst
;
2631 if (lra_dump_file
!= NULL
)
2633 fprintf (lra_dump_file
,
2634 "Changing pseudo %d in operand %i of insn %u on equiv ",
2635 REGNO (old
), i
, INSN_UID (curr_insn
));
2636 print_value_slim (lra_dump_file
, subst
, 1);
2637 fprintf (lra_dump_file
, "\n");
2639 op_change_p
= change_p
= true;
2641 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
2644 lra_update_dup (curr_id
, i
);
2648 /* Reload address registers and displacements. We do it before
2649 finding an alternative because of memory constraints. */
2650 before
= after
= NULL_RTX
;
2651 for (i
= 0; i
< n_operands
; i
++)
2652 if (! curr_static_id
->operand
[i
].is_operator
2653 && process_address (i
, &before
, &after
))
2656 lra_update_dup (curr_id
, i
);
2660 /* If we've changed the instruction then any alternative that
2661 we chose previously may no longer be valid. */
2662 lra_set_used_insn_alternative (curr_insn
, -1);
2666 reused_alternative_num
= curr_id
->used_insn_alternative
;
2667 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
2668 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
2669 reused_alternative_num
, INSN_UID (curr_insn
));
2671 if (process_alt_operands (reused_alternative_num
))
2674 /* If insn is commutative (it's safe to exchange a certain pair of
2675 operands) then we need to try each alternative twice, the second
2676 time matching those two operands as if we had exchanged them. To
2677 do this, really exchange them in operands.
2679 If we have just tried the alternatives the second time, return
2680 operands to normal and drop through. */
2682 if (reused_alternative_num
< 0 && commutative
>= 0)
2684 curr_swapped
= !curr_swapped
;
2687 swap_operands (commutative
);
2691 swap_operands (commutative
);
2694 /* The operands don't meet the constraints. goal_alt describes the
2695 alternative that we could reach by reloading the fewest operands.
2696 Reload so as to fit it. */
2698 if (! alt_p
&& ! sec_mem_p
)
2700 /* No alternative works with reloads?? */
2701 if (INSN_CODE (curr_insn
) >= 0)
2702 fatal_insn ("unable to generate reloads for:", curr_insn
);
2703 error_for_asm (curr_insn
,
2704 "inconsistent operand constraints in an %<asm%>");
2705 /* Avoid further trouble with this insn. */
2706 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
2707 lra_invalidate_insn_data (curr_insn
);
2711 /* If the best alternative is with operands 1 and 2 swapped, swap
2712 them. Update the operand numbers of any reloads already
2715 if (goal_alt_swapped
)
2717 if (lra_dump_file
!= NULL
)
2718 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
2719 INSN_UID (curr_insn
));
2721 /* Swap the duplicates too. */
2722 swap_operands (commutative
);
2726 #ifdef SECONDARY_MEMORY_NEEDED
2727 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
2728 too conservatively. So we use the secondary memory only if there
2729 is no any alternative without reloads. */
2730 use_sec_mem_p
= false;
2732 use_sec_mem_p
= true;
2735 for (i
= 0; i
< n_operands
; i
++)
2736 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
2738 use_sec_mem_p
= i
< n_operands
;
2743 rtx new_reg
, set
, src
, dest
;
2744 enum machine_mode sec_mode
;
2746 lra_assert (sec_mem_p
);
2747 set
= single_set (curr_insn
);
2748 lra_assert (set
!= NULL_RTX
&& ! side_effects_p (set
));
2749 dest
= SET_DEST (set
);
2750 src
= SET_SRC (set
);
2751 #ifdef SECONDARY_MEMORY_NEEDED_MODE
2752 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
));
2754 sec_mode
= GET_MODE (src
);
2756 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
2757 NO_REGS
, "secondary");
2758 /* If the mode is changed, it should be wider. */
2759 lra_assert (GET_MODE_SIZE (GET_MODE (new_reg
))
2760 >= GET_MODE_SIZE (GET_MODE (src
)));
2761 after
= emit_spill_move (false, new_reg
, dest
);
2762 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
2763 "Inserting the sec. move");
2764 before
= emit_spill_move (true, new_reg
, src
);
2765 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Changing on");
2766 lra_set_insn_deleted (curr_insn
);
2771 lra_assert (goal_alt_number
>= 0);
2772 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
2774 if (lra_dump_file
!= NULL
)
2778 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
2779 goal_alt_number
, INSN_UID (curr_insn
));
2780 for (i
= 0; i
< n_operands
; i
++)
2782 p
= (curr_static_id
->operand_alternative
2783 [goal_alt_number
* n_operands
+ i
].constraint
);
2786 fprintf (lra_dump_file
, " (%d) ", i
);
2787 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
2788 fputc (*p
, lra_dump_file
);
2790 fprintf (lra_dump_file
, "\n");
2793 /* Right now, for any pair of operands I and J that are required to
2794 match, with J < I, goal_alt_matches[I] is J. Add I to
2795 goal_alt_matched[J]. */
2797 for (i
= 0; i
< n_operands
; i
++)
2798 if ((j
= goal_alt_matches
[i
]) >= 0)
2800 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
2802 /* We allow matching one output operand and several input
2805 || (curr_static_id
->operand
[j
].type
== OP_OUT
2806 && curr_static_id
->operand
[i
].type
== OP_IN
2807 && (curr_static_id
->operand
2808 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
2809 goal_alt_matched
[j
][k
] = i
;
2810 goal_alt_matched
[j
][k
+ 1] = -1;
2813 for (i
= 0; i
< n_operands
; i
++)
2814 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
2816 /* Any constants that aren't allowed and can't be reloaded into
2817 registers are here changed into memory references. */
2818 for (i
= 0; i
< n_operands
; i
++)
2819 if (goal_alt_win
[i
])
2822 enum reg_class new_class
;
2823 rtx reg
= *curr_id
->operand_loc
[i
];
2825 if (GET_CODE (reg
) == SUBREG
)
2826 reg
= SUBREG_REG (reg
);
2828 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
2830 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
2832 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
2835 change_class (regno
, new_class
, " Change", true);
2841 const char *constraint
;
2843 rtx op
= *curr_id
->operand_loc
[i
];
2844 rtx subreg
= NULL_RTX
;
2845 enum machine_mode mode
= curr_operand_mode
[i
];
2847 if (GET_CODE (op
) == SUBREG
)
2850 op
= SUBREG_REG (op
);
2851 mode
= GET_MODE (op
);
2854 if (CONST_POOL_OK_P (mode
, op
)
2855 && ((targetm
.preferred_reload_class
2856 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
2857 || no_input_reloads_p
))
2859 rtx tem
= force_const_mem (mode
, op
);
2862 if (subreg
!= NULL_RTX
)
2863 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
2865 *curr_id
->operand_loc
[i
] = tem
;
2866 lra_update_dup (curr_id
, i
);
2867 process_address (i
, &before
, &after
);
2869 /* If the alternative accepts constant pool refs directly
2870 there will be no reload needed at all. */
2871 if (subreg
!= NULL_RTX
)
2873 /* Skip alternatives before the one requested. */
2874 constraint
= (curr_static_id
->operand_alternative
2875 [goal_alt_number
* n_operands
+ i
].constraint
);
2877 (c
= *constraint
) && c
!= ',' && c
!= '#';
2878 constraint
+= CONSTRAINT_LEN (c
, constraint
))
2880 if (c
== TARGET_MEM_CONSTRAINT
|| c
== 'o')
2882 #ifdef EXTRA_CONSTRAINT_STR
2883 if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
)
2884 && EXTRA_CONSTRAINT_STR (tem
, c
, constraint
))
2888 if (c
== '\0' || c
== ',' || c
== '#')
2891 goal_alt_win
[i
] = true;
2895 for (i
= 0; i
< n_operands
; i
++)
2898 rtx op
= *curr_id
->operand_loc
[i
];
2900 if (goal_alt_win
[i
])
2902 if (goal_alt
[i
] == NO_REGS
2904 /* When we assign NO_REGS it means that we will not
2905 assign a hard register to the scratch pseudo by
2906 assigment pass and the scratch pseudo will be
2907 spilled. Spilled scratch pseudos are transformed
2908 back to scratches at the LRA end. */
2909 && lra_former_scratch_operand_p (curr_insn
, i
))
2910 change_class (REGNO (op
), NO_REGS
, " Change", true);
2914 /* Operands that match previous ones have already been handled. */
2915 if (goal_alt_matches
[i
] >= 0)
2918 /* We should not have an operand with a non-offsettable address
2919 appearing where an offsettable address will do. It also may
2920 be a case when the address should be special in other words
2921 not a general one (e.g. it needs no index reg). */
2922 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
2924 enum reg_class rclass
;
2925 rtx
*loc
= &XEXP (op
, 0);
2926 enum rtx_code code
= GET_CODE (*loc
);
2928 push_to_sequence (before
);
2929 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
2931 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
2932 new_reg
= emit_inc (rclass
, *loc
, *loc
,
2933 /* This value does not matter for MODIFY. */
2934 GET_MODE_SIZE (GET_MODE (op
)));
2935 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
,
2936 "offsetable address", &new_reg
))
2937 lra_emit_move (new_reg
, *loc
);
2938 before
= get_insns ();
2941 lra_update_dup (curr_id
, i
);
2943 else if (goal_alt_matched
[i
][0] == -1)
2945 enum machine_mode mode
;
2947 int hard_regno
, byte
;
2948 enum op_type type
= curr_static_id
->operand
[i
].type
;
2950 loc
= curr_id
->operand_loc
[i
];
2951 mode
= curr_operand_mode
[i
];
2952 if (GET_CODE (*loc
) == SUBREG
)
2954 reg
= SUBREG_REG (*loc
);
2955 byte
= SUBREG_BYTE (*loc
);
2957 /* Strict_low_part requires reload the register not
2958 the sub-register. */
2959 && (curr_static_id
->operand
[i
].strict_low
2960 || (GET_MODE_SIZE (mode
)
2961 <= GET_MODE_SIZE (GET_MODE (reg
))
2963 = get_try_hard_regno (REGNO (reg
))) >= 0
2964 && (simplify_subreg_regno
2966 GET_MODE (reg
), byte
, mode
) < 0)
2967 && (goal_alt
[i
] == NO_REGS
2968 || (simplify_subreg_regno
2969 (ira_class_hard_regs
[goal_alt
[i
]][0],
2970 GET_MODE (reg
), byte
, mode
) >= 0)))))
2972 loc
= &SUBREG_REG (*loc
);
2973 mode
= GET_MODE (*loc
);
2977 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
], "", &new_reg
)
2980 push_to_sequence (before
);
2981 lra_emit_move (new_reg
, old
);
2982 before
= get_insns ();
2987 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
2990 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
2992 after
= get_insns ();
2996 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
2997 if (goal_alt_dont_inherit_ops
[j
] == i
)
2999 lra_set_regno_unique_value (REGNO (new_reg
));
3002 lra_update_dup (curr_id
, i
);
3004 else if (curr_static_id
->operand
[i
].type
== OP_IN
3005 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3012 match_reload (goal_alt_matched
[i
][0], arr
,
3013 goal_alt
[i
], &before
, &after
);
3015 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3016 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3018 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3020 /* We must generate code in any case when function
3021 process_alt_operands decides that it is possible. */
3024 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3025 || max_regno_before
!= max_reg_num ())
3029 lra_update_operator_dups (curr_id
);
3030 /* Something changes -- process the insn. */
3031 lra_update_insn_regno_info (curr_insn
);
3033 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3037 /* Return true if X is in LIST. */
3039 in_list_p (rtx x
, rtx list
)
3041 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3042 if (XEXP (list
, 0) == x
)
3047 /* Return true if X contains an allocatable hard register (if
3048 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3050 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3056 code
= GET_CODE (x
);
3059 int regno
= REGNO (x
);
3060 HARD_REG_SET alloc_regs
;
3064 if (regno
>= FIRST_PSEUDO_REGISTER
)
3065 regno
= lra_get_regno_hard_regno (regno
);
3068 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3069 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3073 if (regno
< FIRST_PSEUDO_REGISTER
)
3077 return lra_get_regno_hard_regno (regno
) < 0;
3080 fmt
= GET_RTX_FORMAT (code
);
3081 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3085 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3088 else if (fmt
[i
] == 'E')
3090 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3091 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3098 /* Process all regs in location *LOC and change them on equivalent
3099 substitution. Return true if any change was done. */
3101 loc_equivalence_change_p (rtx
*loc
)
3103 rtx subst
, reg
, x
= *loc
;
3104 bool result
= false;
3105 enum rtx_code code
= GET_CODE (x
);
3111 reg
= SUBREG_REG (x
);
3112 if ((subst
= get_equiv_substitution (reg
)) != reg
3113 && GET_MODE (subst
) == VOIDmode
)
3115 /* We cannot reload debug location. Simplify subreg here
3116 while we know the inner mode. */
3117 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3118 GET_MODE (reg
), SUBREG_BYTE (x
));
3122 if (code
== REG
&& (subst
= get_equiv_substitution (x
)) != x
)
3128 /* Scan all the operand sub-expressions. */
3129 fmt
= GET_RTX_FORMAT (code
);
3130 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3133 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3134 else if (fmt
[i
] == 'E')
3135 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3137 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3142 /* Maximum allowed number of constraint pass iterations after the last
3143 spill pass. It is for preventing LRA cycling in a bug case. */
3144 #define MAX_CONSTRAINT_ITERATION_NUMBER 15
3146 /* Maximum number of generated reload insns per an insn. It is for
3147 preventing this pass cycling in a bug case. */
3148 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3150 /* The current iteration number of this LRA pass. */
3151 int lra_constraint_iter
;
3153 /* The current iteration number of this LRA pass after the last spill
3155 int lra_constraint_iter_after_spill
;
3157 /* True if we substituted equiv which needs checking register
3158 allocation correctness because the equivalent value contains
3159 allocatable hard registers or when we restore multi-register
3161 bool lra_risky_transformations_p
;
3163 /* Return true if REGNO is referenced in more than one block. */
3165 multi_block_pseudo_p (int regno
)
3167 basic_block bb
= NULL
;
3171 if (regno
< FIRST_PSEUDO_REGISTER
)
3174 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
3176 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
3177 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
3182 /* Return true if X contains a pseudo dying in INSN. */
3184 dead_pseudo_p (rtx x
, rtx insn
)
3191 return (insn
!= NULL_RTX
3192 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
3193 code
= GET_CODE (x
);
3194 fmt
= GET_RTX_FORMAT (code
);
3195 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3199 if (dead_pseudo_p (XEXP (x
, i
), insn
))
3202 else if (fmt
[i
] == 'E')
3204 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3205 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
3212 /* Return true if INSN contains a dying pseudo in INSN right hand
3215 insn_rhs_dead_pseudo_p (rtx insn
)
3217 rtx set
= single_set (insn
);
3219 gcc_assert (set
!= NULL
);
3220 return dead_pseudo_p (SET_SRC (set
), insn
);
3223 /* Return true if any init insn of REGNO contains a dying pseudo in
3224 insn right hand side. */
3226 init_insn_rhs_dead_pseudo_p (int regno
)
3228 rtx insns
= ira_reg_equiv
[regno
].init_insns
;
3233 return insn_rhs_dead_pseudo_p (insns
);
3234 for (; insns
!= NULL_RTX
; insns
= XEXP (insns
, 1))
3235 if (insn_rhs_dead_pseudo_p (XEXP (insns
, 0)))
3240 /* Entry function of LRA constraint pass. Return true if the
3241 constraint pass did change the code. */
3243 lra_constraints (bool first_p
)
3246 int i
, hard_regno
, new_insns_num
;
3247 unsigned int min_len
, new_min_len
, uid
;
3248 rtx set
, x
, reg
, dest_reg
;
3249 basic_block last_bb
;
3250 bitmap_head equiv_insn_bitmap
;
3253 lra_constraint_iter
++;
3254 if (lra_dump_file
!= NULL
)
3255 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
3256 lra_constraint_iter
);
3257 lra_constraint_iter_after_spill
++;
3258 if (lra_constraint_iter_after_spill
> MAX_CONSTRAINT_ITERATION_NUMBER
)
3260 ("Maximum number of LRA constraint passes is achieved (%d)\n",
3261 MAX_CONSTRAINT_ITERATION_NUMBER
);
3263 lra_risky_transformations_p
= false;
3264 new_insn_uid_start
= get_max_uid ();
3265 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
3266 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
3267 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3268 if (lra_reg_info
[i
].nrefs
!= 0)
3270 ira_reg_equiv
[i
].profitable_p
= true;
3271 reg
= regno_reg_rtx
[i
];
3272 if ((hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3274 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
3276 for (j
= 0; j
< nregs
; j
++)
3277 df_set_regs_ever_live (hard_regno
+ j
, true);
3279 else if ((x
= get_equiv_substitution (reg
)) != reg
)
3281 bool pseudo_p
= contains_reg_p (x
, false, false);
3284 /* We don't use DF for compilation speed sake. So it is
3285 problematic to update live info when we use an
3286 equivalence containing pseudos in more than one BB. */
3287 if ((pseudo_p
&& multi_block_pseudo_p (i
))
3288 /* If it is not a reverse equivalence, we check that a
3289 pseudo in rhs of the init insn is not dying in the
3290 insn. Otherwise, the live info at the beginning of
3291 the corresponding BB might be wrong after we
3292 removed the insn. When the equiv can be a
3293 constant, the right hand side of the init insn can
3295 || (! ((insn
= ira_reg_equiv
[i
].init_insns
) != NULL_RTX
3297 && (set
= single_set (insn
)) != NULL_RTX
3298 && REG_P (SET_DEST (set
))
3299 && (int) REGNO (SET_DEST (set
)) == i
)
3300 && init_insn_rhs_dead_pseudo_p (i
)))
3301 ira_reg_equiv
[i
].defined_p
= false;
3302 else if (! first_p
&& pseudo_p
)
3303 /* After RTL transformation, we can not guarantee that
3304 pseudo in the substitution was not reloaded which
3305 might make equivalence invalid. For example, in
3312 the memory address register was reloaded before the
3314 ira_reg_equiv
[i
].defined_p
= false;
3315 if (contains_reg_p (x
, false, true))
3316 ira_reg_equiv
[i
].profitable_p
= false;
3317 if (get_equiv_substitution (reg
) != reg
)
3318 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
3321 /* We should add all insns containing pseudos which should be
3322 substituted by their equivalences. */
3323 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
3324 lra_push_insn_by_uid (uid
);
3325 lra_eliminate (false);
3326 min_len
= lra_insn_stack_length ();
3330 while ((new_min_len
= lra_insn_stack_length ()) != 0)
3332 curr_insn
= lra_pop_insn ();
3334 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
3335 if (curr_bb
!= last_bb
)
3338 bb_reload_num
= lra_curr_reload_num
;
3340 if (min_len
> new_min_len
)
3342 min_len
= new_min_len
;
3345 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
3347 ("Max. number of generated reload insns per insn is achieved (%d)\n",
3348 MAX_RELOAD_INSNS_NUMBER
);
3350 if (DEBUG_INSN_P (curr_insn
))
3352 /* We need to check equivalence in debug insn and change
3353 pseudo to the equivalent value if necessary. */
3354 curr_id
= lra_get_insn_recog_data (curr_insn
);
3355 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
3356 && loc_equivalence_change_p (curr_id
->operand_loc
[0]))
3358 lra_update_insn_regno_info (curr_insn
);
3362 else if (INSN_P (curr_insn
))
3364 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
3366 dest_reg
= SET_DEST (set
);
3367 /* The equivalence pseudo could be set up as SUBREG in a
3368 case when it is a call restore insn in a mode
3369 different from the pseudo mode. */
3370 if (GET_CODE (dest_reg
) == SUBREG
)
3371 dest_reg
= SUBREG_REG (dest_reg
);
3372 if ((REG_P (dest_reg
)
3373 && (x
= get_equiv_substitution (dest_reg
)) != dest_reg
3374 /* Remove insns which set up a pseudo whose value
3375 can not be changed. Such insns might be not in
3376 init_insns because we don't update equiv data
3377 during insn transformations.
3379 As an example, let suppose that a pseudo got
3380 hard register and on the 1st pass was not
3381 changed to equivalent constant. We generate an
3382 additional insn setting up the pseudo because of
3383 secondary memory movement. Then the pseudo is
3384 spilled and we use the equiv constant. In this
3385 case we should remove the additional insn and
3386 this insn is not init_insns list. */
3387 && (! MEM_P (x
) || MEM_READONLY_P (x
)
3388 || in_list_p (curr_insn
,
3390 [REGNO (dest_reg
)].init_insns
)))
3391 || (((x
= get_equiv_substitution (SET_SRC (set
)))
3393 && in_list_p (curr_insn
,
3395 [REGNO (SET_SRC (set
))].init_insns
)))
3397 /* This is equiv init insn of pseudo which did not get a
3398 hard register -- remove the insn. */
3399 if (lra_dump_file
!= NULL
)
3401 fprintf (lra_dump_file
,
3402 " Removing equiv init insn %i (freq=%d)\n",
3403 INSN_UID (curr_insn
),
3404 BLOCK_FOR_INSN (curr_insn
)->frequency
);
3405 debug_rtl_slim (lra_dump_file
,
3406 curr_insn
, curr_insn
, -1, 0);
3408 if (contains_reg_p (x
, true, false))
3409 lra_risky_transformations_p
= true;
3410 lra_set_insn_deleted (curr_insn
);
3414 curr_id
= lra_get_insn_recog_data (curr_insn
);
3415 curr_static_id
= curr_id
->insn_static_data
;
3416 init_curr_insn_input_reloads ();
3417 init_curr_operand_mode ();
3418 if (curr_insn_transform ())
3420 /* Check non-transformed insns too for equiv change as USE
3421 or CLOBBER don't need reloads but can contain pseudos
3422 being changed on their equivalences. */
3423 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
3424 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
3426 lra_update_insn_regno_info (curr_insn
);
3431 bitmap_clear (&equiv_insn_bitmap
);
3432 /* If we used a new hard regno, changed_p should be true because the
3433 hard reg is assigned to a new pseudo. */
3434 #ifdef ENABLE_CHECKING
3437 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3438 if (lra_reg_info
[i
].nrefs
!= 0
3439 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3441 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
3443 for (j
= 0; j
< nregs
; j
++)
3444 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
3451 /* Initiate the LRA constraint pass. It is done once per
3454 lra_constraints_init (void)
3458 /* Finalize the LRA constraint pass. It is done once per
3461 lra_constraints_finish (void)
3467 /* This page contains code to do inheritance/split
3470 /* Number of reloads passed so far in current EBB. */
3471 static int reloads_num
;
3473 /* Number of calls passed so far in current EBB. */
3474 static int calls_num
;
3476 /* Current reload pseudo check for validity of elements in
3478 static int curr_usage_insns_check
;
3480 /* Info about last usage of registers in EBB to do inheritance/split
3481 transformation. Inheritance transformation is done from a spilled
3482 pseudo and split transformations from a hard register or a pseudo
3483 assigned to a hard register. */
3486 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
3487 value INSNS is valid. The insns is chain of optional debug insns
3488 and a finishing non-debug insn using the corresponding reg. */
3490 /* Value of global reloads_num at the last insn in INSNS. */
3492 /* Value of global reloads_nums at the last insn in INSNS. */
3494 /* It can be true only for splitting. And it means that the restore
3495 insn should be put after insn given by the following member. */
3497 /* Next insns in the current EBB which use the original reg and the
3498 original reg value is not changed between the current insn and
3499 the next insns. In order words, e.g. for inheritance, if we need
3500 to use the original reg value again in the next insns we can try
3501 to use the value in a hard register from a reload insn of the
3506 /* Map: regno -> corresponding pseudo usage insns. */
3507 static struct usage_insns
*usage_insns
;
3510 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
3512 usage_insns
[regno
].check
= curr_usage_insns_check
;
3513 usage_insns
[regno
].insns
= insn
;
3514 usage_insns
[regno
].reloads_num
= reloads_num
;
3515 usage_insns
[regno
].calls_num
= calls_num
;
3516 usage_insns
[regno
].after_p
= after_p
;
3519 /* The function is used to form list REGNO usages which consists of
3520 optional debug insns finished by a non-debug insn using REGNO.
3521 RELOADS_NUM is current number of reload insns processed so far. */
3523 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
3525 rtx next_usage_insns
;
3527 if (usage_insns
[regno
].check
== curr_usage_insns_check
3528 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
3529 && DEBUG_INSN_P (insn
))
3531 /* Check that we did not add the debug insn yet. */
3532 if (next_usage_insns
!= insn
3533 && (GET_CODE (next_usage_insns
) != INSN_LIST
3534 || XEXP (next_usage_insns
, 0) != insn
))
3535 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
3538 else if (NONDEBUG_INSN_P (insn
))
3539 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
3541 usage_insns
[regno
].check
= 0;
3544 /* Replace all references to register OLD_REGNO in *LOC with pseudo
3545 register NEW_REG. Return true if any change was made. */
3547 substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
3550 bool result
= false;
3558 code
= GET_CODE (x
);
3559 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
3561 enum machine_mode mode
= GET_MODE (*loc
);
3562 enum machine_mode inner_mode
= GET_MODE (new_reg
);
3564 if (mode
!= inner_mode
)
3566 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
3567 || ! SCALAR_INT_MODE_P (inner_mode
))
3568 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
3570 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
3576 /* Scan all the operand sub-expressions. */
3577 fmt
= GET_RTX_FORMAT (code
);
3578 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3582 if (substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
3585 else if (fmt
[i
] == 'E')
3587 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3588 if (substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
3595 /* Return first non-debug insn in list USAGE_INSNS. */
3597 skip_usage_debug_insns (rtx usage_insns
)
3601 /* Skip debug insns. */
3602 for (insn
= usage_insns
;
3603 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
3604 insn
= XEXP (insn
, 1))
3609 /* Return true if we need secondary memory moves for insn in
3610 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
3613 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
3614 rtx usage_insns ATTRIBUTE_UNUSED
)
3616 #ifndef SECONDARY_MEMORY_NEEDED
3619 rtx insn
, set
, dest
;
3622 if (inher_cl
== ALL_REGS
3623 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
3625 lra_assert (INSN_P (insn
));
3626 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
3628 dest
= SET_DEST (set
);
3631 lra_assert (inher_cl
!= NO_REGS
);
3632 cl
= get_reg_class (REGNO (dest
));
3633 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
3634 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
3638 /* Registers involved in inheritance/split in the current EBB
3639 (inheritance/split pseudos and original registers). */
3640 static bitmap_head check_only_regs
;
3642 /* Do inheritance transformations for insn INSN, which defines (if
3643 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
3644 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
3645 form as the "insns" field of usage_insns. Return true if we
3646 succeed in such transformation.
3648 The transformations look like:
3651 ... p <- i (new insn)
3653 <- ... p ... <- ... i ...
3655 ... i <- p (new insn)
3656 <- ... p ... <- ... i ...
3658 <- ... p ... <- ... i ...
3659 where p is a spilled original pseudo and i is a new inheritance pseudo.
3662 The inheritance pseudo has the smallest class of two classes CL and
3663 class of ORIGINAL REGNO. */
3665 inherit_reload_reg (bool def_p
, int original_regno
,
3666 enum reg_class cl
, rtx insn
, rtx next_usage_insns
)
3668 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
3669 rtx original_reg
= regno_reg_rtx
[original_regno
];
3670 rtx new_reg
, new_insns
, usage_insn
;
3672 lra_assert (! usage_insns
[original_regno
].after_p
);
3673 if (lra_dump_file
!= NULL
)
3674 fprintf (lra_dump_file
,
3675 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
3676 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
3678 if (lra_dump_file
!= NULL
)
3680 fprintf (lra_dump_file
,
3681 " Rejecting inheritance for %d "
3682 "because of disjoint classes %s and %s\n",
3683 original_regno
, reg_class_names
[cl
],
3684 reg_class_names
[rclass
]);
3685 fprintf (lra_dump_file
,
3686 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
3690 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
3691 /* We don't use a subset of two classes because it can be
3692 NO_REGS. This transformation is still profitable in most
3693 cases even if the classes are not intersected as register
3694 move is probably cheaper than a memory load. */
3695 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
3697 if (lra_dump_file
!= NULL
)
3698 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
3699 reg_class_names
[cl
], reg_class_names
[rclass
]);
3703 if (check_secondary_memory_needed_p (cl
, next_usage_insns
))
3705 /* Reject inheritance resulting in secondary memory moves.
3706 Otherwise, there is a danger in LRA cycling. Also such
3707 transformation will be unprofitable. */
3708 if (lra_dump_file
!= NULL
)
3710 rtx insn
= skip_usage_debug_insns (next_usage_insns
);
3711 rtx set
= single_set (insn
);
3713 lra_assert (set
!= NULL_RTX
);
3715 rtx dest
= SET_DEST (set
);
3717 lra_assert (REG_P (dest
));
3718 fprintf (lra_dump_file
,
3719 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
3720 "as secondary mem is needed\n",
3721 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
3722 original_regno
, reg_class_names
[cl
]);
3723 fprintf (lra_dump_file
,
3724 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
3728 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
3729 rclass
, "inheritance");
3732 emit_move_insn (original_reg
, new_reg
);
3734 emit_move_insn (new_reg
, original_reg
);
3735 new_insns
= get_insns ();
3737 if (NEXT_INSN (new_insns
) != NULL_RTX
)
3739 if (lra_dump_file
!= NULL
)
3741 fprintf (lra_dump_file
,
3742 " Rejecting inheritance %d->%d "
3743 "as it results in 2 or more insns:\n",
3744 original_regno
, REGNO (new_reg
));
3745 debug_rtl_slim (lra_dump_file
, new_insns
, NULL_RTX
, -1, 0);
3746 fprintf (lra_dump_file
,
3747 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
3751 substitute_pseudo (&insn
, original_regno
, new_reg
);
3752 lra_update_insn_regno_info (insn
);
3754 /* We now have a new usage insn for original regno. */
3755 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
3756 if (lra_dump_file
!= NULL
)
3757 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
3758 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
3759 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
3760 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
3761 bitmap_set_bit (&check_only_regs
, original_regno
);
3762 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
3764 lra_process_new_insns (insn
, NULL_RTX
, new_insns
,
3765 "Add original<-inheritance");
3767 lra_process_new_insns (insn
, new_insns
, NULL_RTX
,
3768 "Add inheritance<-original");
3769 while (next_usage_insns
!= NULL_RTX
)
3771 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
3773 usage_insn
= next_usage_insns
;
3774 lra_assert (NONDEBUG_INSN_P (usage_insn
));
3775 next_usage_insns
= NULL
;
3779 usage_insn
= XEXP (next_usage_insns
, 0);
3780 lra_assert (DEBUG_INSN_P (usage_insn
));
3781 next_usage_insns
= XEXP (next_usage_insns
, 1);
3783 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
3784 lra_update_insn_regno_info (usage_insn
);
3785 if (lra_dump_file
!= NULL
)
3787 fprintf (lra_dump_file
,
3788 " Inheritance reuse change %d->%d (bb%d):\n",
3789 original_regno
, REGNO (new_reg
),
3790 BLOCK_FOR_INSN (usage_insn
)->index
);
3791 debug_rtl_slim (lra_dump_file
, usage_insn
, usage_insn
,
3795 if (lra_dump_file
!= NULL
)
3796 fprintf (lra_dump_file
,
3797 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
3801 /* Return true if we need a caller save/restore for pseudo REGNO which
3802 was assigned to a hard register. */
3804 need_for_call_save_p (int regno
)
3806 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
3807 return (usage_insns
[regno
].calls_num
< calls_num
3808 && (overlaps_hard_reg_set_p
3810 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])));
3813 /* Global registers occuring in the current EBB. */
3814 static bitmap_head ebb_global_regs
;
3816 /* Return true if we need a split for hard register REGNO or pseudo
3817 REGNO which was assigned to a hard register.
3818 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
3819 used for reloads since the EBB end. It is an approximation of the
3820 used hard registers in the split range. The exact value would
3821 require expensive calculations. If we were aggressive with
3822 splitting because of the approximation, the split pseudo will save
3823 the same hard register assignment and will be removed in the undo
3824 pass. We still need the approximation because too aggressive
3825 splitting would result in too inaccurate cost calculation in the
3826 assignment pass because of too many generated moves which will be
3827 probably removed in the undo pass. */
3829 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
3831 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
3833 lra_assert (hard_regno
>= 0);
3834 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
3835 /* Don't split eliminable hard registers, otherwise we can
3836 split hard registers like hard frame pointer, which
3837 lives on BB start/end according to DF-infrastructure,
3838 when there is a pseudo assigned to the register and
3839 living in the same BB. */
3840 && (regno
>= FIRST_PSEUDO_REGISTER
3841 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
3842 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
3843 /* We need at least 2 reloads to make pseudo splitting
3844 profitable. We should provide hard regno splitting in
3845 any case to solve 1st insn scheduling problem when
3846 moving hard register definition up might result in
3847 impossibility to find hard register for reload pseudo of
3848 small register class. */
3849 && (usage_insns
[regno
].reloads_num
3850 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 2) < reloads_num
)
3851 && (regno
< FIRST_PSEUDO_REGISTER
3852 /* For short living pseudos, spilling + inheritance can
3853 be considered a substitution for splitting.
3854 Therefore we do not splitting for local pseudos. It
3855 decreases also aggressiveness of splitting. The
3856 minimal number of references is chosen taking into
3857 account that for 2 references splitting has no sense
3858 as we can just spill the pseudo. */
3859 || (regno
>= FIRST_PSEUDO_REGISTER
3860 && lra_reg_info
[regno
].nrefs
> 3
3861 && bitmap_bit_p (&ebb_global_regs
, regno
))))
3862 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
3865 /* Return class for the split pseudo created from original pseudo with
3866 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
3867 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
3868 results in no secondary memory movements. */
3869 static enum reg_class
3870 choose_split_class (enum reg_class allocno_class
,
3871 int hard_regno ATTRIBUTE_UNUSED
,
3872 enum machine_mode mode ATTRIBUTE_UNUSED
)
3874 #ifndef SECONDARY_MEMORY_NEEDED
3875 return allocno_class
;
3878 enum reg_class cl
, best_cl
= NO_REGS
;
3879 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
3880 = REGNO_REG_CLASS (hard_regno
);
3882 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
3883 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
3884 return allocno_class
;
3886 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
3888 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
3889 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
3890 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
3891 && (best_cl
== NO_REGS
3892 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
3898 /* Do split transformations for insn INSN, which defines or uses
3899 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
3900 the EBB next uses ORIGINAL_REGNO; it has the same form as the
3901 "insns" field of usage_insns.
3903 The transformations look like:
3906 ... s <- p (new insn -- save)
3908 ... p <- s (new insn -- restore)
3909 <- ... p ... <- ... p ...
3911 <- ... p ... <- ... p ...
3912 ... s <- p (new insn -- save)
3914 ... p <- s (new insn -- restore)
3915 <- ... p ... <- ... p ...
3917 where p is an original pseudo got a hard register or a hard
3918 register and s is a new split pseudo. The save is put before INSN
3919 if BEFORE_P is true. Return true if we succeed in such
3922 split_reg (bool before_p
, int original_regno
, rtx insn
, rtx next_usage_insns
)
3924 enum reg_class rclass
;
3927 rtx new_reg
, save
, restore
, usage_insn
;
3931 if (original_regno
< FIRST_PSEUDO_REGISTER
)
3933 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
3934 hard_regno
= original_regno
;
3935 call_save_p
= false;
3939 hard_regno
= reg_renumber
[original_regno
];
3940 rclass
= lra_get_allocno_class (original_regno
);
3941 original_reg
= regno_reg_rtx
[original_regno
];
3942 call_save_p
= need_for_call_save_p (original_regno
);
3944 original_reg
= regno_reg_rtx
[original_regno
];
3945 lra_assert (hard_regno
>= 0);
3946 if (lra_dump_file
!= NULL
)
3947 fprintf (lra_dump_file
,
3948 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
3951 enum machine_mode sec_mode
;
3953 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3954 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (original_reg
));
3956 sec_mode
= GET_MODE (original_reg
);
3958 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3963 rclass
= choose_split_class (rclass
, hard_regno
,
3964 GET_MODE (original_reg
));
3965 if (rclass
== NO_REGS
)
3967 if (lra_dump_file
!= NULL
)
3969 fprintf (lra_dump_file
,
3970 " Rejecting split of %d(%s): "
3971 "no good reg class for %d(%s)\n",
3973 reg_class_names
[lra_get_allocno_class (original_regno
)],
3975 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
3978 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
3982 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
3984 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
3986 save
= emit_spill_move (true, new_reg
, original_reg
);
3987 if (NEXT_INSN (save
) != NULL_RTX
)
3989 lra_assert (! call_save_p
);
3990 if (lra_dump_file
!= NULL
)
3994 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
3995 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
3996 debug_rtl_slim (lra_dump_file
, save
, NULL_RTX
, -1, 0);
3997 fprintf (lra_dump_file
,
3998 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4002 restore
= emit_spill_move (false, new_reg
, original_reg
);
4003 if (NEXT_INSN (restore
) != NULL_RTX
)
4005 lra_assert (! call_save_p
);
4006 if (lra_dump_file
!= NULL
)
4008 fprintf (lra_dump_file
,
4009 " Rejecting split %d->%d "
4010 "resulting in > 2 %s restore insns:\n",
4011 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4012 debug_rtl_slim (lra_dump_file
, restore
, NULL_RTX
, -1, 0);
4013 fprintf (lra_dump_file
,
4014 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4018 after_p
= usage_insns
[original_regno
].after_p
;
4019 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4020 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4021 bitmap_set_bit (&check_only_regs
, original_regno
);
4022 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4025 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4027 usage_insn
= next_usage_insns
;
4030 usage_insn
= XEXP (next_usage_insns
, 0);
4031 lra_assert (DEBUG_INSN_P (usage_insn
));
4032 next_usage_insns
= XEXP (next_usage_insns
, 1);
4033 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4034 lra_update_insn_regno_info (usage_insn
);
4035 if (lra_dump_file
!= NULL
)
4037 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4038 original_regno
, REGNO (new_reg
));
4039 debug_rtl_slim (lra_dump_file
, usage_insn
, usage_insn
,
4043 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4044 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4045 lra_process_new_insns (usage_insn
, after_p
? NULL_RTX
: restore
,
4046 after_p
? restore
: NULL_RTX
,
4048 ? "Add reg<-save" : "Add reg<-split");
4049 lra_process_new_insns (insn
, before_p
? save
: NULL_RTX
,
4050 before_p
? NULL_RTX
: save
,
4052 ? "Add save<-reg" : "Add split<-reg");
4053 if (lra_dump_file
!= NULL
)
4054 fprintf (lra_dump_file
,
4055 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4059 /* Recognize that we need a split transformation for insn INSN, which
4060 defines or uses REGNO in its insn biggest MODE (we use it only if
4061 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4062 hard registers which might be used for reloads since the EBB end.
4063 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4064 uid before starting INSN processing. Return true if we succeed in
4065 such transformation. */
4067 split_if_necessary (int regno
, enum machine_mode mode
,
4068 HARD_REG_SET potential_reload_hard_regs
,
4069 bool before_p
, rtx insn
, int max_uid
)
4073 rtx next_usage_insns
;
4075 if (regno
< FIRST_PSEUDO_REGISTER
)
4076 nregs
= hard_regno_nregs
[regno
][mode
];
4077 for (i
= 0; i
< nregs
; i
++)
4078 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4079 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4080 /* To avoid processing the register twice or more. */
4081 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4082 && INSN_UID (next_usage_insns
) < max_uid
)
4083 || (GET_CODE (next_usage_insns
) == INSN_LIST
4084 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4085 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4086 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4091 /* Check only registers living at the current program point in the
4093 static bitmap_head live_regs
;
4095 /* Update live info in EBB given by its HEAD and TAIL insns after
4096 inheritance/split transformation. The function removes dead moves
4099 update_ebb_live_info (rtx head
, rtx tail
)
4106 basic_block last_bb
, prev_bb
, curr_bb
;
4108 struct lra_insn_reg
*reg
;
4112 last_bb
= BLOCK_FOR_INSN (tail
);
4114 for (curr_insn
= tail
;
4115 curr_insn
!= PREV_INSN (head
);
4116 curr_insn
= prev_insn
)
4118 prev_insn
= PREV_INSN (curr_insn
);
4119 /* We need to process empty blocks too. They contain
4120 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
4121 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
4123 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4124 if (curr_bb
!= prev_bb
)
4126 if (prev_bb
!= NULL
)
4128 /* Update df_get_live_in (prev_bb): */
4129 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4130 if (bitmap_bit_p (&live_regs
, j
))
4131 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
4133 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
4135 if (curr_bb
!= last_bb
)
4137 /* Update df_get_live_out (curr_bb): */
4138 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4140 live_p
= bitmap_bit_p (&live_regs
, j
);
4142 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
4143 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
4149 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
4151 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
4155 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
4157 if (! NONDEBUG_INSN_P (curr_insn
))
4159 curr_id
= lra_get_insn_recog_data (curr_insn
);
4161 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
4162 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
4163 && bitmap_bit_p (&check_only_regs
, regno
)
4164 && ! bitmap_bit_p (&live_regs
, regno
))
4166 /* See which defined values die here. */
4167 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4168 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4169 bitmap_clear_bit (&live_regs
, reg
->regno
);
4170 /* Mark each used value as live. */
4171 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4172 if (reg
->type
== OP_IN
4173 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4174 bitmap_set_bit (&live_regs
, reg
->regno
);
4175 /* It is quite important to remove dead move insns because it
4176 means removing dead store. We don't need to process them for
4180 if (lra_dump_file
!= NULL
)
4182 fprintf (lra_dump_file
, " Removing dead insn:\n ");
4183 debug_rtl_slim (lra_dump_file
, curr_insn
, curr_insn
, -1, 0);
4185 lra_set_insn_deleted (curr_insn
);
4190 /* The structure describes info to do an inheritance for the current
4191 insn. We need to collect such info first before doing the
4192 transformations because the transformations change the insn
4193 internal representation. */
4196 /* Original regno. */
4198 /* Subsequent insns which can inherit original reg value. */
4202 /* Array containing all info for doing inheritance from the current
4204 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
4206 /* Number elements in the previous array. */
4207 static int to_inherit_num
;
4209 /* Add inheritance info REGNO and INSNS. Their meaning is described in
4210 structure to_inherit. */
4212 add_to_inherit (int regno
, rtx insns
)
4216 for (i
= 0; i
< to_inherit_num
; i
++)
4217 if (to_inherit
[i
].regno
== regno
)
4219 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
4220 to_inherit
[to_inherit_num
].regno
= regno
;
4221 to_inherit
[to_inherit_num
++].insns
= insns
;
4224 /* Return the last non-debug insn in basic block BB, or the block begin
4227 get_last_insertion_point (basic_block bb
)
4231 FOR_BB_INSNS_REVERSE (bb
, insn
)
4232 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
4237 /* Set up RES by registers living on edges FROM except the edge (FROM,
4238 TO) or by registers set up in a jump insn in BB FROM. */
4240 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
4243 struct lra_insn_reg
*reg
;
4247 lra_assert (to
!= NULL
);
4249 FOR_EACH_EDGE (e
, ei
, from
->succs
)
4251 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
4252 last
= get_last_insertion_point (from
);
4253 if (! JUMP_P (last
))
4255 curr_id
= lra_get_insn_recog_data (last
);
4256 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4257 if (reg
->type
!= OP_IN
)
4258 bitmap_set_bit (res
, reg
->regno
);
4261 /* Used as a temporary results of some bitmap calculations. */
4262 static bitmap_head temp_bitmap
;
4264 /* Do inheritance/split transformations in EBB starting with HEAD and
4265 finishing on TAIL. We process EBB insns in the reverse order.
4266 Return true if we did any inheritance/split transformation in the
4269 We should avoid excessive splitting which results in worse code
4270 because of inaccurate cost calculations for spilling new split
4271 pseudos in such case. To achieve this we do splitting only if
4272 register pressure is high in given basic block and there are reload
4273 pseudos requiring hard registers. We could do more register
4274 pressure calculations at any given program point to avoid necessary
4275 splitting even more but it is to expensive and the current approach
4276 works well enough. */
4278 inherit_in_ebb (rtx head
, rtx tail
)
4280 int i
, src_regno
, dst_regno
, nregs
;
4281 bool change_p
, succ_p
;
4282 rtx prev_insn
, next_usage_insns
, set
, last_insn
;
4284 struct lra_insn_reg
*reg
;
4285 basic_block last_processed_bb
, curr_bb
= NULL
;
4286 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
4290 bool head_p
, after_p
;
4293 curr_usage_insns_check
++;
4294 reloads_num
= calls_num
= 0;
4295 bitmap_clear (&check_only_regs
);
4296 last_processed_bb
= NULL
;
4297 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
4298 CLEAR_HARD_REG_SET (live_hard_regs
);
4299 /* We don't process new insns generated in the loop. */
4300 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
4302 prev_insn
= PREV_INSN (curr_insn
);
4303 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
4304 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4305 if (last_processed_bb
!= curr_bb
)
4307 /* We are at the end of BB. Add qualified living
4308 pseudos for potential splitting. */
4309 to_process
= df_get_live_out (curr_bb
);
4310 if (last_processed_bb
!= NULL
)
4312 /* We are somewhere in the middle of EBB. */
4313 get_live_on_other_edges (curr_bb
, last_processed_bb
,
4315 to_process
= &temp_bitmap
;
4317 last_processed_bb
= curr_bb
;
4318 last_insn
= get_last_insertion_point (curr_bb
);
4319 after_p
= (! JUMP_P (last_insn
)
4320 && (! CALL_P (last_insn
)
4321 || (find_reg_note (last_insn
,
4322 REG_NORETURN
, NULL_RTX
) == NULL_RTX
4323 && ! SIBLING_CALL_P (last_insn
))));
4324 REG_SET_TO_HARD_REG_SET (live_hard_regs
, df_get_live_out (curr_bb
));
4325 IOR_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
4326 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
4327 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
4328 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
4330 if ((int) j
>= lra_constraint_new_regno_start
)
4332 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
4334 if (j
< FIRST_PSEUDO_REGISTER
)
4335 SET_HARD_REG_BIT (live_hard_regs
, j
);
4337 add_to_hard_reg_set (&live_hard_regs
,
4338 PSEUDO_REGNO_MODE (j
),
4340 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
4344 src_regno
= dst_regno
= -1;
4345 if (NONDEBUG_INSN_P (curr_insn
)
4346 && (set
= single_set (curr_insn
)) != NULL_RTX
4347 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
4349 src_regno
= REGNO (SET_SRC (set
));
4350 dst_regno
= REGNO (SET_DEST (set
));
4352 if (src_regno
< lra_constraint_new_regno_start
4353 && src_regno
>= FIRST_PSEUDO_REGISTER
4354 && reg_renumber
[src_regno
] < 0
4355 && dst_regno
>= lra_constraint_new_regno_start
4356 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
4358 /* 'reload_pseudo <- original_pseudo'. */
4361 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
4362 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
4363 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
4364 curr_insn
, next_usage_insns
);
4368 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
4369 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
4370 IOR_HARD_REG_SET (potential_reload_hard_regs
,
4371 reg_class_contents
[cl
]);
4373 else if (src_regno
>= lra_constraint_new_regno_start
4374 && dst_regno
< lra_constraint_new_regno_start
4375 && dst_regno
>= FIRST_PSEUDO_REGISTER
4376 && reg_renumber
[dst_regno
] < 0
4377 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
4378 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
4379 && (next_usage_insns
4380 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
4383 /* 'original_pseudo <- reload_pseudo'. */
4384 if (! JUMP_P (curr_insn
)
4385 && inherit_reload_reg (true, dst_regno
, cl
,
4386 curr_insn
, next_usage_insns
))
4389 usage_insns
[dst_regno
].check
= 0;
4390 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
4391 IOR_HARD_REG_SET (potential_reload_hard_regs
,
4392 reg_class_contents
[cl
]);
4394 else if (INSN_P (curr_insn
))
4396 int max_uid
= get_max_uid ();
4398 curr_id
= lra_get_insn_recog_data (curr_insn
);
4400 /* Process insn definitions. */
4401 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4402 if (reg
->type
!= OP_IN
4403 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
4405 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
4406 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
4407 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
4408 && (next_usage_insns
4409 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
4411 struct lra_insn_reg
*r
;
4413 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
4414 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
4416 /* Don't do inheritance if the pseudo is also
4417 used in the insn. */
4419 /* We can not do inheritance right now
4420 because the current insn reg info (chain
4421 regs) can change after that. */
4422 add_to_inherit (dst_regno
, next_usage_insns
);
4424 /* We can not process one reg twice here because of
4425 usage_insns invalidation. */
4426 if ((dst_regno
< FIRST_PSEUDO_REGISTER
4427 || reg_renumber
[dst_regno
] >= 0)
4428 && ! reg
->subreg_p
&& reg
->type
== OP_OUT
)
4432 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
4433 potential_reload_hard_regs
,
4434 false, curr_insn
, max_uid
))
4436 CLEAR_HARD_REG_SET (s
);
4437 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
4438 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
4440 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
4441 reg_renumber
[dst_regno
]);
4442 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
4444 /* We should invalidate potential inheritance or
4445 splitting for the current insn usages to the next
4446 usage insns (see code below) as the output pseudo
4448 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
4449 && reg_renumber
[dst_regno
] < 0)
4450 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
4451 && (dst_regno
< FIRST_PSEUDO_REGISTER
4452 || reg_renumber
[dst_regno
] >= 0)))
4455 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
4456 usage_insns
[dst_regno
].check
= 0;
4459 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
4460 for (i
= 0; i
< nregs
; i
++)
4461 usage_insns
[dst_regno
+ i
].check
= 0;
4465 if (! JUMP_P (curr_insn
))
4466 for (i
= 0; i
< to_inherit_num
; i
++)
4467 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
4468 ALL_REGS
, curr_insn
,
4469 to_inherit
[i
].insns
))
4471 if (CALL_P (curr_insn
))
4473 rtx cheap
, pat
, dest
, restore
;
4474 int regno
, hard_regno
;
4477 if ((cheap
= find_reg_note (curr_insn
,
4478 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
4479 && ((cheap
= XEXP (cheap
, 0)), true)
4480 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
4481 && (hard_regno
= reg_renumber
[regno
]) >= 0
4482 /* If there are pending saves/restores, the
4483 optimization is not worth. */
4484 && usage_insns
[regno
].calls_num
== calls_num
- 1
4485 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
4487 /* Restore the pseudo from the call result as
4488 REG_RETURNED note says that the pseudo value is
4489 in the call result and the pseudo is an argument
4491 pat
= PATTERN (curr_insn
);
4492 if (GET_CODE (pat
) == PARALLEL
)
4493 pat
= XVECEXP (pat
, 0, 0);
4494 dest
= SET_DEST (pat
);
4496 emit_move_insn (cheap
, copy_rtx (dest
));
4497 restore
= get_insns ();
4499 lra_process_new_insns (curr_insn
, NULL
, restore
,
4500 "Inserting call parameter restore");
4501 /* We don't need to save/restore of the pseudo from
4503 usage_insns
[regno
].calls_num
= calls_num
;
4504 bitmap_set_bit (&check_only_regs
, regno
);
4508 /* Process insn usages. */
4509 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4510 if ((reg
->type
!= OP_OUT
4511 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
4512 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
4514 if (src_regno
>= FIRST_PSEUDO_REGISTER
4515 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
4517 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
4518 && (next_usage_insns
4519 = usage_insns
[src_regno
].insns
) != NULL_RTX
4520 && NONDEBUG_INSN_P (curr_insn
))
4521 add_to_inherit (src_regno
, next_usage_insns
);
4524 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
4526 else if (src_regno
< FIRST_PSEUDO_REGISTER
4527 || reg_renumber
[src_regno
] >= 0)
4530 rtx use_insn
= curr_insn
;
4532 before_p
= (JUMP_P (curr_insn
)
4533 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
4534 if (NONDEBUG_INSN_P (curr_insn
)
4535 && split_if_necessary (src_regno
, reg
->biggest_mode
,
4536 potential_reload_hard_regs
,
4537 before_p
, curr_insn
, max_uid
))
4540 lra_risky_transformations_p
= true;
4543 usage_insns
[src_regno
].check
= 0;
4545 use_insn
= PREV_INSN (curr_insn
);
4547 if (NONDEBUG_INSN_P (curr_insn
))
4549 if (src_regno
< FIRST_PSEUDO_REGISTER
)
4550 add_to_hard_reg_set (&live_hard_regs
,
4551 reg
->biggest_mode
, src_regno
);
4553 add_to_hard_reg_set (&live_hard_regs
,
4554 PSEUDO_REGNO_MODE (src_regno
),
4555 reg_renumber
[src_regno
]);
4557 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
4560 for (i
= 0; i
< to_inherit_num
; i
++)
4562 src_regno
= to_inherit
[i
].regno
;
4563 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
4564 curr_insn
, to_inherit
[i
].insns
))
4567 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
4570 /* We reached the start of the current basic block. */
4571 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
4572 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
4574 /* We reached the beginning of the current block -- do
4575 rest of spliting in the current BB. */
4576 to_process
= df_get_live_in (curr_bb
);
4577 if (BLOCK_FOR_INSN (head
) != curr_bb
)
4579 /* We are somewhere in the middle of EBB. */
4580 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
4581 curr_bb
, &temp_bitmap
);
4582 to_process
= &temp_bitmap
;
4585 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
4587 if ((int) j
>= lra_constraint_new_regno_start
)
4589 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
4590 && usage_insns
[j
].check
== curr_usage_insns_check
4591 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
4593 if (need_for_split_p (potential_reload_hard_regs
, j
))
4595 if (lra_dump_file
!= NULL
&& head_p
)
4597 fprintf (lra_dump_file
,
4598 " ----------------------------------\n");
4601 if (split_reg (false, j
, bb_note (curr_bb
),
4605 usage_insns
[j
].check
= 0;
4613 /* This value affects EBB forming. If probability of edge from EBB to
4614 a BB is not greater than the following value, we don't add the BB
4616 #define EBB_PROBABILITY_CUTOFF (REG_BR_PROB_BASE / 2)
4618 /* Current number of inheritance/split iteration. */
4619 int lra_inheritance_iter
;
4621 /* Entry function for inheritance/split pass. */
4623 lra_inheritance (void)
4626 basic_block bb
, start_bb
;
4629 timevar_push (TV_LRA_INHERITANCE
);
4630 lra_inheritance_iter
++;
4631 if (lra_dump_file
!= NULL
)
4632 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
4633 lra_inheritance_iter
);
4634 curr_usage_insns_check
= 0;
4635 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
4636 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
4637 usage_insns
[i
].check
= 0;
4638 bitmap_initialize (&check_only_regs
, ®_obstack
);
4639 bitmap_initialize (&live_regs
, ®_obstack
);
4640 bitmap_initialize (&temp_bitmap
, ®_obstack
);
4641 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
4645 if (lra_dump_file
!= NULL
)
4646 fprintf (lra_dump_file
, "EBB");
4647 /* Form a EBB starting with BB. */
4648 bitmap_clear (&ebb_global_regs
);
4649 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
4652 if (lra_dump_file
!= NULL
)
4653 fprintf (lra_dump_file
, " %d", bb
->index
);
4654 if (bb
->next_bb
== EXIT_BLOCK_PTR
|| LABEL_P (BB_HEAD (bb
->next_bb
)))
4656 e
= find_fallthru_edge (bb
->succs
);
4659 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
4663 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
4664 if (lra_dump_file
!= NULL
)
4665 fprintf (lra_dump_file
, "\n");
4666 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
4667 /* Remember that the EBB head and tail can change in
4669 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
4671 bitmap_clear (&ebb_global_regs
);
4672 bitmap_clear (&temp_bitmap
);
4673 bitmap_clear (&live_regs
);
4674 bitmap_clear (&check_only_regs
);
4677 timevar_pop (TV_LRA_INHERITANCE
);
4682 /* This page contains code to undo failed inheritance/split
4685 /* Current number of iteration undoing inheritance/split. */
4686 int lra_undo_inheritance_iter
;
4688 /* Fix BB live info LIVE after removing pseudos created on pass doing
4689 inheritance/split which are REMOVED_PSEUDOS. */
4691 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
4696 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
4697 if (bitmap_clear_bit (live
, regno
))
4698 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
4701 /* Return regno of the (subreg of) REG. Otherwise, return a negative
4706 if (GET_CODE (reg
) == SUBREG
)
4707 reg
= SUBREG_REG (reg
);
4713 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
4714 return true if we did any change. The undo transformations for
4715 inheritance looks like
4719 p <- i, i <- p, and i <- i3
4720 where p is original pseudo from which inheritance pseudo i was
4721 created, i and i3 are removed inheritance pseudos, i2 is another
4722 not removed inheritance pseudo. All split pseudos or other
4723 occurrences of removed inheritance pseudos are changed on the
4724 corresponding original pseudos.
4726 The function also schedules insns changed and created during
4727 inheritance/split pass for processing by the subsequent constraint
4730 remove_inheritance_pseudos (bitmap remove_pseudos
)
4733 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
4734 rtx set
, prev_set
, prev_insn
;
4735 bool change_p
, done_p
;
4737 change_p
= ! bitmap_empty_p (remove_pseudos
);
4738 /* We can not finish the function right away if CHANGE_P is true
4739 because we need to marks insns affected by previous
4740 inheritance/split pass for processing by the subsequent
4744 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
4745 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
4746 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
4748 if (! INSN_P (curr_insn
))
4751 sregno
= dregno
= -1;
4752 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
4753 && (set
= single_set (curr_insn
)) != NULL_RTX
)
4755 dregno
= get_regno (SET_DEST (set
));
4756 sregno
= get_regno (SET_SRC (set
));
4759 if (sregno
>= 0 && dregno
>= 0)
4761 if ((bitmap_bit_p (remove_pseudos
, sregno
)
4762 && (lra_reg_info
[sregno
].restore_regno
== dregno
4763 || (bitmap_bit_p (remove_pseudos
, dregno
)
4764 && (lra_reg_info
[sregno
].restore_regno
4765 == lra_reg_info
[dregno
].restore_regno
))))
4766 || (bitmap_bit_p (remove_pseudos
, dregno
)
4767 && lra_reg_info
[dregno
].restore_regno
== sregno
))
4768 /* One of the following cases:
4769 original <- removed inheritance pseudo
4770 removed inherit pseudo <- another removed inherit pseudo
4771 removed inherit pseudo <- original pseudo
4773 removed_split_pseudo <- original_reg
4774 original_reg <- removed_split_pseudo */
4776 if (lra_dump_file
!= NULL
)
4778 fprintf (lra_dump_file
, " Removing %s:\n",
4779 bitmap_bit_p (&lra_split_regs
, sregno
)
4780 || bitmap_bit_p (&lra_split_regs
, dregno
)
4781 ? "split" : "inheritance");
4782 debug_rtl_slim (lra_dump_file
,
4783 curr_insn
, curr_insn
, -1, 0);
4785 lra_set_insn_deleted (curr_insn
);
4788 else if (bitmap_bit_p (remove_pseudos
, sregno
)
4789 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
4791 /* Search the following pattern:
4792 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
4793 original_pseudo <- inherit_or_split_pseudo1
4794 where the 2nd insn is the current insn and
4795 inherit_or_split_pseudo2 is not removed. If it is found,
4796 change the current insn onto:
4797 original_pseudo <- inherit_or_split_pseudo2. */
4798 for (prev_insn
= PREV_INSN (curr_insn
);
4799 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
4800 prev_insn
= PREV_INSN (prev_insn
))
4802 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
4803 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
4804 /* There should be no subregs in insn we are
4805 searching because only the original reg might
4806 be in subreg when we changed the mode of
4807 load/store for splitting. */
4808 && REG_P (SET_DEST (prev_set
))
4809 && REG_P (SET_SRC (prev_set
))
4810 && (int) REGNO (SET_DEST (prev_set
)) == sregno
4811 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
4812 >= FIRST_PSEUDO_REGISTER
)
4813 /* As we consider chain of inheritance or
4814 splitting described in above comment we should
4815 check that sregno and prev_sregno were
4816 inheritance/split pseudos created from the
4817 same original regno. */
4818 && (lra_reg_info
[sregno
].restore_regno
4819 == lra_reg_info
[prev_sregno
].restore_regno
)
4820 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
4822 lra_assert (GET_MODE (SET_SRC (prev_set
))
4823 == GET_MODE (regno_reg_rtx
[sregno
]));
4824 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
4825 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
4827 SET_SRC (set
) = SET_SRC (prev_set
);
4828 lra_push_insn_and_update_insn_regno_info (curr_insn
);
4829 lra_set_used_insn_alternative_by_uid
4830 (INSN_UID (curr_insn
), -1);
4832 if (lra_dump_file
!= NULL
)
4834 fprintf (lra_dump_file
, " Change reload insn:\n");
4835 debug_rtl_slim (lra_dump_file
,
4836 curr_insn
, curr_insn
, -1, 0);
4843 struct lra_insn_reg
*reg
;
4844 bool restored_regs_p
= false;
4845 bool kept_regs_p
= false;
4847 curr_id
= lra_get_insn_recog_data (curr_insn
);
4848 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4851 restore_regno
= lra_reg_info
[regno
].restore_regno
;
4852 if (restore_regno
>= 0)
4854 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
4856 substitute_pseudo (&curr_insn
, regno
,
4857 regno_reg_rtx
[restore_regno
]);
4858 restored_regs_p
= true;
4864 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
4866 /* The instruction has changed since the previous
4867 constraints pass. */
4868 lra_push_insn_and_update_insn_regno_info (curr_insn
);
4869 lra_set_used_insn_alternative_by_uid
4870 (INSN_UID (curr_insn
), -1);
4872 else if (restored_regs_p
)
4873 /* The instruction has been restored to the form that
4874 it had during the previous constraints pass. */
4875 lra_update_insn_regno_info (curr_insn
);
4876 if (restored_regs_p
&& lra_dump_file
!= NULL
)
4878 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
4879 debug_rtl_slim (lra_dump_file
, curr_insn
, curr_insn
, -1, 0);
4887 /* Entry function for undoing inheritance/split transformation. Return true
4888 if we did any RTL change in this pass. */
4890 lra_undo_inheritance (void)
4893 int restore_regno
, hard_regno
;
4894 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
4895 bitmap_head remove_pseudos
;
4899 lra_undo_inheritance_iter
++;
4900 if (lra_dump_file
!= NULL
)
4901 fprintf (lra_dump_file
,
4902 "\n********** Undoing inheritance #%d: **********\n\n",
4903 lra_undo_inheritance_iter
);
4904 bitmap_initialize (&remove_pseudos
, ®_obstack
);
4905 n_inherit
= n_all_inherit
= 0;
4906 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
4907 if (lra_reg_info
[regno
].restore_regno
>= 0)
4910 if (reg_renumber
[regno
] < 0)
4911 bitmap_set_bit (&remove_pseudos
, regno
);
4915 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
4916 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
4917 n_inherit
, n_all_inherit
,
4918 (double) n_inherit
/ n_all_inherit
* 100);
4919 n_split
= n_all_split
= 0;
4920 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
4921 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
4924 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
4925 ? reg_renumber
[restore_regno
] : restore_regno
);
4926 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
4927 bitmap_set_bit (&remove_pseudos
, regno
);
4931 if (lra_dump_file
!= NULL
)
4932 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
4933 regno
, restore_regno
);
4936 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
4937 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
4938 n_split
, n_all_split
,
4939 (double) n_split
/ n_all_split
* 100);
4940 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
4941 bitmap_clear (&remove_pseudos
);
4942 /* Clear restore_regnos. */
4943 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
4944 lra_reg_info
[regno
].restore_regno
= -1;
4945 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
4946 lra_reg_info
[regno
].restore_regno
= -1;