| blob | af0d781d148bf882c35772da32c95fcfc26365e1 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 ;; MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
26 ;; UNSPEC usage
27 ;;
29 (define_constants
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
34 (UNSPEC_MOVSI_GOT 8)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
36 (UNSPEC_FCTIWZ 10)
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
39 (UNSPEC_TLSGD 17)
40 (UNSPEC_TLSLD 18)
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
43 (UNSPEC_TLSDTPREL 21)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
47 (UNSPEC_TLSTPREL 25)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
51 (UNSPEC_TLSTLS 29)
52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
53 ])
55 ;;
56 ;; UNSPEC_VOLATILE usage
57 ;;
59 (define_constants
60 [(UNSPECV_BLOCK 0)
61 (UNSPECV_EH_RR 9) ; eh_reg_restore
62 ])
63 \f
64 ;; Define an insn type attribute. This is used in function unit delay
65 ;; computations.
66 (define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
67 (const_string "integer"))
69 ;; Length (in bytes).
70 ; '(pc)' in the following doesn't include the instruction itself; it is
71 ; calculated as if the instruction had zero size.
72 (define_attr "length" ""
73 (if_then_else (eq_attr "type" "branch")
74 (if_then_else (and (ge (minus (match_dup 0) (pc))
75 (const_int -32768))
76 (lt (minus (match_dup 0) (pc))
77 (const_int 32764)))
78 (const_int 4)
79 (const_int 8))
80 (const_int 4)))
82 ;; Processor type -- this attribute must exactly match the processor_type
83 ;; enumeration in rs6000.h.
85 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4"
86 (const (symbol_ref "rs6000_cpu_attr")))
88 (automata_option "ndfa")
90 (include "rios1.md")
91 (include "rios2.md")
92 (include "rs64.md")
93 (include "mpc.md")
94 (include "40x.md")
95 (include "440.md")
96 (include "603.md")
97 (include "6xx.md")
98 (include "7xx.md")
99 (include "7450.md")
100 (include "8540.md")
101 (include "power4.md")
103 \f
104 ;; Start with fixed-point load and store insns. Here we put only the more
105 ;; complex forms. Basic data transfer is done later.
107 (define_expand "zero_extendqidi2"
108 [(set (match_operand:DI 0 "gpc_reg_operand" "")
109 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
110 "TARGET_POWERPC64"
111 "")
113 (define_insn ""
114 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
115 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
116 "TARGET_POWERPC64"
117 "@
118 lbz%U1%X1 %0,%1
119 rldicl %0,%1,0,56"
120 [(set_attr "type" "load,*")])
122 (define_insn ""
123 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
124 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
125 (const_int 0)))
126 (clobber (match_scratch:DI 2 "=r,r"))]
127 "TARGET_64BIT"
128 "@
129 rldicl. %2,%1,0,56
130 #"
131 [(set_attr "type" "compare")
132 (set_attr "length" "4,8")])
134 (define_split
135 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
136 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
137 (const_int 0)))
138 (clobber (match_scratch:DI 2 ""))]
139 "TARGET_POWERPC64 && reload_completed"
140 [(set (match_dup 2)
141 (zero_extend:DI (match_dup 1)))
142 (set (match_dup 0)
143 (compare:CC (match_dup 2)
144 (const_int 0)))]
145 "")
147 (define_insn ""
148 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
149 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
150 (const_int 0)))
151 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
152 (zero_extend:DI (match_dup 1)))]
153 "TARGET_64BIT"
154 "@
155 rldicl. %0,%1,0,56
156 #"
157 [(set_attr "type" "compare")
158 (set_attr "length" "4,8")])
160 (define_split
161 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
162 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
163 (const_int 0)))
164 (set (match_operand:DI 0 "gpc_reg_operand" "")
165 (zero_extend:DI (match_dup 1)))]
166 "TARGET_POWERPC64 && reload_completed"
167 [(set (match_dup 0)
168 (zero_extend:DI (match_dup 1)))
169 (set (match_dup 2)
170 (compare:CC (match_dup 0)
171 (const_int 0)))]
172 "")
174 (define_insn "extendqidi2"
175 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
176 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
177 "TARGET_POWERPC64"
178 "extsb %0,%1")
180 (define_insn ""
181 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
182 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
183 (const_int 0)))
184 (clobber (match_scratch:DI 2 "=r,r"))]
185 "TARGET_64BIT"
186 "@
187 extsb. %2,%1
188 #"
189 [(set_attr "type" "compare")
190 (set_attr "length" "4,8")])
192 (define_split
193 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
194 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
195 (const_int 0)))
196 (clobber (match_scratch:DI 2 ""))]
197 "TARGET_POWERPC64 && reload_completed"
198 [(set (match_dup 2)
199 (sign_extend:DI (match_dup 1)))
200 (set (match_dup 0)
201 (compare:CC (match_dup 2)
202 (const_int 0)))]
203 "")
205 (define_insn ""
206 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
207 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
208 (const_int 0)))
209 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
210 (sign_extend:DI (match_dup 1)))]
211 "TARGET_64BIT"
212 "@
213 extsb. %0,%1
214 #"
215 [(set_attr "type" "compare")
216 (set_attr "length" "4,8")])
218 (define_split
219 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
220 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
221 (const_int 0)))
222 (set (match_operand:DI 0 "gpc_reg_operand" "")
223 (sign_extend:DI (match_dup 1)))]
224 "TARGET_POWERPC64 && reload_completed"
225 [(set (match_dup 0)
226 (sign_extend:DI (match_dup 1)))
227 (set (match_dup 2)
228 (compare:CC (match_dup 0)
229 (const_int 0)))]
230 "")
232 (define_expand "zero_extendhidi2"
233 [(set (match_operand:DI 0 "gpc_reg_operand" "")
234 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
235 "TARGET_POWERPC64"
236 "")
238 (define_insn ""
239 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
240 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
241 "TARGET_POWERPC64"
242 "@
243 lhz%U1%X1 %0,%1
244 rldicl %0,%1,0,48"
245 [(set_attr "type" "load,*")])
247 (define_insn ""
248 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
249 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
250 (const_int 0)))
251 (clobber (match_scratch:DI 2 "=r,r"))]
252 "TARGET_64BIT"
253 "@
254 rldicl. %2,%1,0,48
255 #"
256 [(set_attr "type" "compare")
257 (set_attr "length" "4,8")])
259 (define_split
260 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
261 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
262 (const_int 0)))
263 (clobber (match_scratch:DI 2 ""))]
264 "TARGET_POWERPC64 && reload_completed"
265 [(set (match_dup 2)
266 (zero_extend:DI (match_dup 1)))
267 (set (match_dup 0)
268 (compare:CC (match_dup 2)
269 (const_int 0)))]
270 "")
272 (define_insn ""
273 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
274 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
275 (const_int 0)))
276 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
277 (zero_extend:DI (match_dup 1)))]
278 "TARGET_64BIT"
279 "@
280 rldicl. %0,%1,0,48
281 #"
282 [(set_attr "type" "compare")
283 (set_attr "length" "4,8")])
285 (define_split
286 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
287 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
288 (const_int 0)))
289 (set (match_operand:DI 0 "gpc_reg_operand" "")
290 (zero_extend:DI (match_dup 1)))]
291 "TARGET_POWERPC64 && reload_completed"
292 [(set (match_dup 0)
293 (zero_extend:DI (match_dup 1)))
294 (set (match_dup 2)
295 (compare:CC (match_dup 0)
296 (const_int 0)))]
297 "")
299 (define_expand "extendhidi2"
300 [(set (match_operand:DI 0 "gpc_reg_operand" "")
301 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
302 "TARGET_POWERPC64"
303 "")
305 (define_insn ""
306 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
307 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
308 "TARGET_POWERPC64"
309 "@
310 lha%U1%X1 %0,%1
311 extsh %0,%1"
312 [(set_attr "type" "load_ext,*")])
314 (define_insn ""
315 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
316 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
317 (const_int 0)))
318 (clobber (match_scratch:DI 2 "=r,r"))]
319 "TARGET_64BIT"
320 "@
321 extsh. %2,%1
322 #"
323 [(set_attr "type" "compare")
324 (set_attr "length" "4,8")])
326 (define_split
327 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
328 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
329 (const_int 0)))
330 (clobber (match_scratch:DI 2 ""))]
331 "TARGET_POWERPC64 && reload_completed"
332 [(set (match_dup 2)
333 (sign_extend:DI (match_dup 1)))
334 (set (match_dup 0)
335 (compare:CC (match_dup 2)
336 (const_int 0)))]
337 "")
339 (define_insn ""
340 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
341 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
342 (const_int 0)))
343 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
344 (sign_extend:DI (match_dup 1)))]
345 "TARGET_64BIT"
346 "@
347 extsh. %0,%1
348 #"
349 [(set_attr "type" "compare")
350 (set_attr "length" "4,8")])
352 (define_split
353 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
354 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
355 (const_int 0)))
356 (set (match_operand:DI 0 "gpc_reg_operand" "")
357 (sign_extend:DI (match_dup 1)))]
358 "TARGET_POWERPC64 && reload_completed"
359 [(set (match_dup 0)
360 (sign_extend:DI (match_dup 1)))
361 (set (match_dup 2)
362 (compare:CC (match_dup 0)
363 (const_int 0)))]
364 "")
366 (define_expand "zero_extendsidi2"
367 [(set (match_operand:DI 0 "gpc_reg_operand" "")
368 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
369 "TARGET_POWERPC64"
370 "")
372 (define_insn ""
373 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
374 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
375 "TARGET_POWERPC64"
376 "@
377 lwz%U1%X1 %0,%1
378 rldicl %0,%1,0,32"
379 [(set_attr "type" "load,*")])
381 (define_insn ""
382 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
383 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
384 (const_int 0)))
385 (clobber (match_scratch:DI 2 "=r,r"))]
386 "TARGET_64BIT"
387 "@
388 rldicl. %2,%1,0,32
389 #"
390 [(set_attr "type" "compare")
391 (set_attr "length" "4,8")])
393 (define_split
394 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
395 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
396 (const_int 0)))
397 (clobber (match_scratch:DI 2 ""))]
398 "TARGET_POWERPC64 && reload_completed"
399 [(set (match_dup 2)
400 (zero_extend:DI (match_dup 1)))
401 (set (match_dup 0)
402 (compare:CC (match_dup 2)
403 (const_int 0)))]
404 "")
406 (define_insn ""
407 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
408 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
409 (const_int 0)))
410 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
411 (zero_extend:DI (match_dup 1)))]
412 "TARGET_64BIT"
413 "@
414 rldicl. %0,%1,0,32
415 #"
416 [(set_attr "type" "compare")
417 (set_attr "length" "4,8")])
419 (define_split
420 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
421 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
422 (const_int 0)))
423 (set (match_operand:DI 0 "gpc_reg_operand" "")
424 (zero_extend:DI (match_dup 1)))]
425 "TARGET_POWERPC64 && reload_completed"
426 [(set (match_dup 0)
427 (zero_extend:DI (match_dup 1)))
428 (set (match_dup 2)
429 (compare:CC (match_dup 0)
430 (const_int 0)))]
431 "")
433 (define_expand "extendsidi2"
434 [(set (match_operand:DI 0 "gpc_reg_operand" "")
435 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
436 "TARGET_POWERPC64"
437 "")
439 (define_insn ""
440 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
441 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
442 "TARGET_POWERPC64"
443 "@
444 lwa%U1%X1 %0,%1
445 extsw %0,%1"
446 [(set_attr "type" "load_ext,*")])
448 (define_insn ""
449 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
450 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
451 (const_int 0)))
452 (clobber (match_scratch:DI 2 "=r,r"))]
453 "TARGET_64BIT"
454 "@
455 extsw. %2,%1
456 #"
457 [(set_attr "type" "compare")
458 (set_attr "length" "4,8")])
460 (define_split
461 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
462 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
463 (const_int 0)))
464 (clobber (match_scratch:DI 2 ""))]
465 "TARGET_POWERPC64 && reload_completed"
466 [(set (match_dup 2)
467 (sign_extend:DI (match_dup 1)))
468 (set (match_dup 0)
469 (compare:CC (match_dup 2)
470 (const_int 0)))]
471 "")
473 (define_insn ""
474 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
475 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
476 (const_int 0)))
477 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
478 (sign_extend:DI (match_dup 1)))]
479 "TARGET_64BIT"
480 "@
481 extsw. %0,%1
482 #"
483 [(set_attr "type" "compare")
484 (set_attr "length" "4,8")])
486 (define_split
487 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
488 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
489 (const_int 0)))
490 (set (match_operand:DI 0 "gpc_reg_operand" "")
491 (sign_extend:DI (match_dup 1)))]
492 "TARGET_POWERPC64 && reload_completed"
493 [(set (match_dup 0)
494 (sign_extend:DI (match_dup 1)))
495 (set (match_dup 2)
496 (compare:CC (match_dup 0)
497 (const_int 0)))]
498 "")
500 (define_expand "zero_extendqisi2"
501 [(set (match_operand:SI 0 "gpc_reg_operand" "")
502 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
503 ""
504 "")
506 (define_insn ""
507 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
508 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
509 ""
510 "@
511 lbz%U1%X1 %0,%1
512 {rlinm|rlwinm} %0,%1,0,0xff"
513 [(set_attr "type" "load,*")])
515 (define_insn ""
516 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
517 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
518 (const_int 0)))
519 (clobber (match_scratch:SI 2 "=r,r"))]
520 ""
521 "@
522 {andil.|andi.} %2,%1,0xff
523 #"
524 [(set_attr "type" "compare")
525 (set_attr "length" "4,8")])
527 (define_split
528 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
529 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
530 (const_int 0)))
531 (clobber (match_scratch:SI 2 ""))]
532 "reload_completed"
533 [(set (match_dup 2)
534 (zero_extend:SI (match_dup 1)))
535 (set (match_dup 0)
536 (compare:CC (match_dup 2)
537 (const_int 0)))]
538 "")
540 (define_insn ""
541 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
542 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
543 (const_int 0)))
544 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
545 (zero_extend:SI (match_dup 1)))]
546 ""
547 "@
548 {andil.|andi.} %0,%1,0xff
549 #"
550 [(set_attr "type" "compare")
551 (set_attr "length" "4,8")])
553 (define_split
554 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
555 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
556 (const_int 0)))
557 (set (match_operand:SI 0 "gpc_reg_operand" "")
558 (zero_extend:SI (match_dup 1)))]
559 "reload_completed"
560 [(set (match_dup 0)
561 (zero_extend:SI (match_dup 1)))
562 (set (match_dup 2)
563 (compare:CC (match_dup 0)
564 (const_int 0)))]
565 "")
567 (define_expand "extendqisi2"
568 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
569 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
570 ""
571 "
572 {
573 if (TARGET_POWERPC)
574 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
575 else if (TARGET_POWER)
576 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
577 else
578 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
579 DONE;
580 }")
582 (define_insn "extendqisi2_ppc"
583 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
584 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
585 "TARGET_POWERPC"
586 "extsb %0,%1")
588 (define_insn ""
589 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
590 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
591 (const_int 0)))
592 (clobber (match_scratch:SI 2 "=r,r"))]
593 "TARGET_POWERPC"
594 "@
595 extsb. %2,%1
596 #"
597 [(set_attr "type" "compare")
598 (set_attr "length" "4,8")])
600 (define_split
601 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
602 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
603 (const_int 0)))
604 (clobber (match_scratch:SI 2 ""))]
605 "TARGET_POWERPC && reload_completed"
606 [(set (match_dup 2)
607 (sign_extend:SI (match_dup 1)))
608 (set (match_dup 0)
609 (compare:CC (match_dup 2)
610 (const_int 0)))]
611 "")
613 (define_insn ""
614 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
615 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
616 (const_int 0)))
617 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
618 (sign_extend:SI (match_dup 1)))]
619 "TARGET_POWERPC"
620 "@
621 extsb. %0,%1
622 #"
623 [(set_attr "type" "compare")
624 (set_attr "length" "4,8")])
626 (define_split
627 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
628 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
629 (const_int 0)))
630 (set (match_operand:SI 0 "gpc_reg_operand" "")
631 (sign_extend:SI (match_dup 1)))]
632 "TARGET_POWERPC && reload_completed"
633 [(set (match_dup 0)
634 (sign_extend:SI (match_dup 1)))
635 (set (match_dup 2)
636 (compare:CC (match_dup 0)
637 (const_int 0)))]
638 "")
640 (define_expand "extendqisi2_power"
641 [(parallel [(set (match_dup 2)
642 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
643 (const_int 24)))
644 (clobber (scratch:SI))])
645 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
646 (ashiftrt:SI (match_dup 2)
647 (const_int 24)))
648 (clobber (scratch:SI))])]
649 "TARGET_POWER"
650 "
651 { operands[1] = gen_lowpart (SImode, operands[1]);
652 operands[2] = gen_reg_rtx (SImode); }")
654 (define_expand "extendqisi2_no_power"
655 [(set (match_dup 2)
656 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
657 (const_int 24)))
658 (set (match_operand:SI 0 "gpc_reg_operand" "")
659 (ashiftrt:SI (match_dup 2)
660 (const_int 24)))]
661 "! TARGET_POWER && ! TARGET_POWERPC"
662 "
663 { operands[1] = gen_lowpart (SImode, operands[1]);
664 operands[2] = gen_reg_rtx (SImode); }")
666 (define_expand "zero_extendqihi2"
667 [(set (match_operand:HI 0 "gpc_reg_operand" "")
668 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
669 ""
670 "")
672 (define_insn ""
673 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
674 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
675 ""
676 "@
677 lbz%U1%X1 %0,%1
678 {rlinm|rlwinm} %0,%1,0,0xff"
679 [(set_attr "type" "load,*")])
681 (define_insn ""
682 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
683 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
684 (const_int 0)))
685 (clobber (match_scratch:HI 2 "=r,r"))]
686 ""
687 "@
688 {andil.|andi.} %2,%1,0xff
689 #"
690 [(set_attr "type" "compare")
691 (set_attr "length" "4,8")])
693 (define_split
694 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
695 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
696 (const_int 0)))
697 (clobber (match_scratch:HI 2 ""))]
698 "reload_completed"
699 [(set (match_dup 2)
700 (zero_extend:HI (match_dup 1)))
701 (set (match_dup 0)
702 (compare:CC (match_dup 2)
703 (const_int 0)))]
704 "")
706 (define_insn ""
707 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
708 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
709 (const_int 0)))
710 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
711 (zero_extend:HI (match_dup 1)))]
712 ""
713 "@
714 {andil.|andi.} %0,%1,0xff
715 #"
716 [(set_attr "type" "compare")
717 (set_attr "length" "4,8")])
719 (define_split
720 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
721 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
722 (const_int 0)))
723 (set (match_operand:HI 0 "gpc_reg_operand" "")
724 (zero_extend:HI (match_dup 1)))]
725 "reload_completed"
726 [(set (match_dup 0)
727 (zero_extend:HI (match_dup 1)))
728 (set (match_dup 2)
729 (compare:CC (match_dup 0)
730 (const_int 0)))]
731 "")
733 (define_expand "extendqihi2"
734 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
735 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
736 ""
737 "
738 {
739 if (TARGET_POWERPC)
740 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
741 else if (TARGET_POWER)
742 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
743 else
744 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
745 DONE;
746 }")
748 (define_insn "extendqihi2_ppc"
749 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
750 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
751 "TARGET_POWERPC"
752 "extsb %0,%1")
754 (define_insn ""
755 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
756 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
757 (const_int 0)))
758 (clobber (match_scratch:HI 2 "=r,r"))]
759 "TARGET_POWERPC"
760 "@
761 extsb. %2,%1
762 #"
763 [(set_attr "type" "compare")
764 (set_attr "length" "4,8")])
766 (define_split
767 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
768 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
769 (const_int 0)))
770 (clobber (match_scratch:HI 2 ""))]
771 "TARGET_POWERPC && reload_completed"
772 [(set (match_dup 2)
773 (sign_extend:HI (match_dup 1)))
774 (set (match_dup 0)
775 (compare:CC (match_dup 2)
776 (const_int 0)))]
777 "")
779 (define_insn ""
780 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
781 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
782 (const_int 0)))
783 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
784 (sign_extend:HI (match_dup 1)))]
785 "TARGET_POWERPC"
786 "@
787 extsb. %0,%1
788 #"
789 [(set_attr "type" "compare")
790 (set_attr "length" "4,8")])
792 (define_split
793 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
794 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
795 (const_int 0)))
796 (set (match_operand:HI 0 "gpc_reg_operand" "")
797 (sign_extend:HI (match_dup 1)))]
798 "TARGET_POWERPC && reload_completed"
799 [(set (match_dup 0)
800 (sign_extend:HI (match_dup 1)))
801 (set (match_dup 2)
802 (compare:CC (match_dup 0)
803 (const_int 0)))]
804 "")
806 (define_expand "extendqihi2_power"
807 [(parallel [(set (match_dup 2)
808 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
809 (const_int 24)))
810 (clobber (scratch:SI))])
811 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
812 (ashiftrt:SI (match_dup 2)
813 (const_int 24)))
814 (clobber (scratch:SI))])]
815 "TARGET_POWER"
816 "
817 { operands[0] = gen_lowpart (SImode, operands[0]);
818 operands[1] = gen_lowpart (SImode, operands[1]);
819 operands[2] = gen_reg_rtx (SImode); }")
821 (define_expand "extendqihi2_no_power"
822 [(set (match_dup 2)
823 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
824 (const_int 24)))
825 (set (match_operand:HI 0 "gpc_reg_operand" "")
826 (ashiftrt:SI (match_dup 2)
827 (const_int 24)))]
828 "! TARGET_POWER && ! TARGET_POWERPC"
829 "
830 { operands[0] = gen_lowpart (SImode, operands[0]);
831 operands[1] = gen_lowpart (SImode, operands[1]);
832 operands[2] = gen_reg_rtx (SImode); }")
834 (define_expand "zero_extendhisi2"
835 [(set (match_operand:SI 0 "gpc_reg_operand" "")
836 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
837 ""
838 "")
840 (define_insn ""
841 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
842 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
843 ""
844 "@
845 lhz%U1%X1 %0,%1
846 {rlinm|rlwinm} %0,%1,0,0xffff"
847 [(set_attr "type" "load,*")])
849 (define_insn ""
850 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
851 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
852 (const_int 0)))
853 (clobber (match_scratch:SI 2 "=r,r"))]
854 ""
855 "@
856 {andil.|andi.} %2,%1,0xffff
857 #"
858 [(set_attr "type" "compare")
859 (set_attr "length" "4,8")])
861 (define_split
862 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
863 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
864 (const_int 0)))
865 (clobber (match_scratch:SI 2 ""))]
866 "reload_completed"
867 [(set (match_dup 2)
868 (zero_extend:SI (match_dup 1)))
869 (set (match_dup 0)
870 (compare:CC (match_dup 2)
871 (const_int 0)))]
872 "")
874 (define_insn ""
875 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
876 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
877 (const_int 0)))
878 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
879 (zero_extend:SI (match_dup 1)))]
880 ""
881 "@
882 {andil.|andi.} %0,%1,0xffff
883 #"
884 [(set_attr "type" "compare")
885 (set_attr "length" "4,8")])
887 (define_split
888 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
889 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
890 (const_int 0)))
891 (set (match_operand:SI 0 "gpc_reg_operand" "")
892 (zero_extend:SI (match_dup 1)))]
893 "reload_completed"
894 [(set (match_dup 0)
895 (zero_extend:SI (match_dup 1)))
896 (set (match_dup 2)
897 (compare:CC (match_dup 0)
898 (const_int 0)))]
899 "")
901 (define_expand "extendhisi2"
902 [(set (match_operand:SI 0 "gpc_reg_operand" "")
903 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
904 ""
905 "")
907 (define_insn ""
908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
909 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
910 ""
911 "@
912 lha%U1%X1 %0,%1
913 {exts|extsh} %0,%1"
914 [(set_attr "type" "load_ext,*")])
916 (define_insn ""
917 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
918 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
919 (const_int 0)))
920 (clobber (match_scratch:SI 2 "=r,r"))]
921 ""
922 "@
923 {exts.|extsh.} %2,%1
924 #"
925 [(set_attr "type" "compare")
926 (set_attr "length" "4,8")])
928 (define_split
929 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
930 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
931 (const_int 0)))
932 (clobber (match_scratch:SI 2 ""))]
933 "reload_completed"
934 [(set (match_dup 2)
935 (sign_extend:SI (match_dup 1)))
936 (set (match_dup 0)
937 (compare:CC (match_dup 2)
938 (const_int 0)))]
939 "")
941 (define_insn ""
942 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
943 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
944 (const_int 0)))
945 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
946 (sign_extend:SI (match_dup 1)))]
947 ""
948 "@
949 {exts.|extsh.} %0,%1
950 #"
951 [(set_attr "type" "compare")
952 (set_attr "length" "4,8")])
953 \f
954 (define_split
955 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
956 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
957 (const_int 0)))
958 (set (match_operand:SI 0 "gpc_reg_operand" "")
959 (sign_extend:SI (match_dup 1)))]
960 "reload_completed"
961 [(set (match_dup 0)
962 (sign_extend:SI (match_dup 1)))
963 (set (match_dup 2)
964 (compare:CC (match_dup 0)
965 (const_int 0)))]
966 "")
968 ;; Fixed-point arithmetic insns.
970 ;; Discourage ai/addic because of carry but provide it in an alternative
971 ;; allowing register zero as source.
972 (define_expand "addsi3"
973 [(set (match_operand:SI 0 "gpc_reg_operand" "")
974 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
975 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
976 ""
977 "
978 {
979 if (GET_CODE (operands[2]) == CONST_INT
980 && ! add_operand (operands[2], SImode))
981 {
982 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
983 ? operands[0] : gen_reg_rtx (SImode));
985 HOST_WIDE_INT val = INTVAL (operands[2]);
986 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
987 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
989 /* The ordering here is important for the prolog expander.
990 When space is allocated from the stack, adding 'low' first may
991 produce a temporary deallocation (which would be bad). */
992 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
993 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
994 DONE;
995 }
996 }")
998 (define_insn "*addsi3_internal1"
999 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
1000 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
1001 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
1002 ""
1003 "@
1004 {cax|add} %0,%1,%2
1005 {cal %0,%2(%1)|addi %0,%1,%2}
1006 {ai|addic} %0,%1,%2
1007 {cau|addis} %0,%1,%v2"
1008 [(set_attr "length" "4,4,4,4")])
1010 (define_insn "addsi3_high"
1011 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1012 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1013 (high:SI (match_operand 2 "" ""))))]
1014 "TARGET_MACHO && !TARGET_64BIT"
1015 "{cau|addis} %0,%1,ha16(%2)"
1016 [(set_attr "length" "4")])
1018 (define_insn "*addsi3_internal2"
1019 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1020 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1021 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1022 (const_int 0)))
1023 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1024 "TARGET_32BIT"
1025 "@
1026 {cax.|add.} %3,%1,%2
1027 {ai.|addic.} %3,%1,%2
1028 #
1029 #"
1030 [(set_attr "type" "fast_compare,compare,compare,compare")
1031 (set_attr "length" "4,4,8,8")])
1033 (define_split
1034 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1035 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1036 (match_operand:SI 2 "reg_or_short_operand" ""))
1037 (const_int 0)))
1038 (clobber (match_scratch:SI 3 ""))]
1039 "TARGET_32BIT && reload_completed"
1040 [(set (match_dup 3)
1041 (plus:SI (match_dup 1)
1042 (match_dup 2)))
1043 (set (match_dup 0)
1044 (compare:CC (match_dup 3)
1045 (const_int 0)))]
1046 "")
1048 (define_insn "*addsi3_internal3"
1049 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1050 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1051 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1052 (const_int 0)))
1053 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1054 (plus:SI (match_dup 1)
1055 (match_dup 2)))]
1056 "TARGET_32BIT"
1057 "@
1058 {cax.|add.} %0,%1,%2
1059 {ai.|addic.} %0,%1,%2
1060 #
1061 #"
1062 [(set_attr "type" "fast_compare,compare,compare,compare")
1063 (set_attr "length" "4,4,8,8")])
1065 (define_split
1066 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1067 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1068 (match_operand:SI 2 "reg_or_short_operand" ""))
1069 (const_int 0)))
1070 (set (match_operand:SI 0 "gpc_reg_operand" "")
1071 (plus:SI (match_dup 1) (match_dup 2)))]
1072 "TARGET_32BIT && reload_completed"
1073 [(set (match_dup 0)
1074 (plus:SI (match_dup 1)
1075 (match_dup 2)))
1076 (set (match_dup 3)
1077 (compare:CC (match_dup 0)
1078 (const_int 0)))]
1079 "")
1081 ;; Split an add that we can't do in one insn into two insns, each of which
1082 ;; does one 16-bit part. This is used by combine. Note that the low-order
1083 ;; add should be last in case the result gets used in an address.
1085 (define_split
1086 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1087 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1088 (match_operand:SI 2 "non_add_cint_operand" "")))]
1089 ""
1090 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1091 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1092 "
1093 {
1094 HOST_WIDE_INT val = INTVAL (operands[2]);
1095 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1096 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1098 operands[3] = GEN_INT (rest);
1099 operands[4] = GEN_INT (low);
1100 }")
1102 (define_insn "one_cmplsi2"
1103 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1104 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1105 ""
1106 "nor %0,%1,%1")
1108 (define_insn ""
1109 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1110 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1111 (const_int 0)))
1112 (clobber (match_scratch:SI 2 "=r,r"))]
1113 "TARGET_32BIT"
1114 "@
1115 nor. %2,%1,%1
1116 #"
1117 [(set_attr "type" "compare")
1118 (set_attr "length" "4,8")])
1120 (define_split
1121 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1122 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1123 (const_int 0)))
1124 (clobber (match_scratch:SI 2 ""))]
1125 "TARGET_32BIT && reload_completed"
1126 [(set (match_dup 2)
1127 (not:SI (match_dup 1)))
1128 (set (match_dup 0)
1129 (compare:CC (match_dup 2)
1130 (const_int 0)))]
1131 "")
1133 (define_insn ""
1134 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1135 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1136 (const_int 0)))
1137 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1138 (not:SI (match_dup 1)))]
1139 "TARGET_32BIT"
1140 "@
1141 nor. %0,%1,%1
1142 #"
1143 [(set_attr "type" "compare")
1144 (set_attr "length" "4,8")])
1146 (define_split
1147 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1148 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1149 (const_int 0)))
1150 (set (match_operand:SI 0 "gpc_reg_operand" "")
1151 (not:SI (match_dup 1)))]
1152 "TARGET_32BIT && reload_completed"
1153 [(set (match_dup 0)
1154 (not:SI (match_dup 1)))
1155 (set (match_dup 2)
1156 (compare:CC (match_dup 0)
1157 (const_int 0)))]
1158 "")
1160 (define_insn ""
1161 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1162 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1163 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1164 "! TARGET_POWERPC"
1165 "{sf%I1|subf%I1c} %0,%2,%1")
1167 (define_insn ""
1168 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1169 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1170 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1171 "TARGET_POWERPC"
1172 "@
1173 subf %0,%2,%1
1174 subfic %0,%2,%1")
1176 (define_insn ""
1177 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1178 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1179 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1180 (const_int 0)))
1181 (clobber (match_scratch:SI 3 "=r,r"))]
1182 "! TARGET_POWERPC"
1183 "@
1184 {sf.|subfc.} %3,%2,%1
1185 #"
1186 [(set_attr "type" "compare")
1187 (set_attr "length" "4,8")])
1189 (define_insn ""
1190 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1191 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1192 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1193 (const_int 0)))
1194 (clobber (match_scratch:SI 3 "=r,r"))]
1195 "TARGET_POWERPC && TARGET_32BIT"
1196 "@
1197 subf. %3,%2,%1
1198 #"
1199 [(set_attr "type" "fast_compare")
1200 (set_attr "length" "4,8")])
1202 (define_split
1203 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1204 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1205 (match_operand:SI 2 "gpc_reg_operand" ""))
1206 (const_int 0)))
1207 (clobber (match_scratch:SI 3 ""))]
1208 "TARGET_32BIT && reload_completed"
1209 [(set (match_dup 3)
1210 (minus:SI (match_dup 1)
1211 (match_dup 2)))
1212 (set (match_dup 0)
1213 (compare:CC (match_dup 3)
1214 (const_int 0)))]
1215 "")
1217 (define_insn ""
1218 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1219 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1220 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1221 (const_int 0)))
1222 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1223 (minus:SI (match_dup 1) (match_dup 2)))]
1224 "! TARGET_POWERPC"
1225 "@
1226 {sf.|subfc.} %0,%2,%1
1227 #"
1228 [(set_attr "type" "compare")
1229 (set_attr "length" "4,8")])
1231 (define_insn ""
1232 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1233 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1234 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1235 (const_int 0)))
1236 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1237 (minus:SI (match_dup 1)
1238 (match_dup 2)))]
1239 "TARGET_POWERPC && TARGET_32BIT"
1240 "@
1241 subf. %0,%2,%1
1242 #"
1243 [(set_attr "type" "fast_compare")
1244 (set_attr "length" "4,8")])
1246 (define_split
1247 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1248 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1249 (match_operand:SI 2 "gpc_reg_operand" ""))
1250 (const_int 0)))
1251 (set (match_operand:SI 0 "gpc_reg_operand" "")
1252 (minus:SI (match_dup 1)
1253 (match_dup 2)))]
1254 "TARGET_32BIT && reload_completed"
1255 [(set (match_dup 0)
1256 (minus:SI (match_dup 1)
1257 (match_dup 2)))
1258 (set (match_dup 3)
1259 (compare:CC (match_dup 0)
1260 (const_int 0)))]
1261 "")
1263 (define_expand "subsi3"
1264 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1265 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1266 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1267 ""
1268 "
1269 {
1270 if (GET_CODE (operands[2]) == CONST_INT)
1271 {
1272 emit_insn (gen_addsi3 (operands[0], operands[1],
1273 negate_rtx (SImode, operands[2])));
1274 DONE;
1275 }
1276 }")
1278 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1279 ;; instruction and some auxiliary computations. Then we just have a single
1280 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1281 ;; combine.
1283 (define_expand "sminsi3"
1284 [(set (match_dup 3)
1285 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1286 (match_operand:SI 2 "reg_or_short_operand" ""))
1287 (const_int 0)
1288 (minus:SI (match_dup 2) (match_dup 1))))
1289 (set (match_operand:SI 0 "gpc_reg_operand" "")
1290 (minus:SI (match_dup 2) (match_dup 3)))]
1291 "TARGET_POWER || TARGET_ISEL"
1292 "
1293 {
1294 if (TARGET_ISEL)
1295 {
1296 operands[2] = force_reg (SImode, operands[2]);
1297 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1298 DONE;
1299 }
1301 operands[3] = gen_reg_rtx (SImode);
1302 }")
1304 (define_split
1305 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1306 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1307 (match_operand:SI 2 "reg_or_short_operand" "")))
1308 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1309 "TARGET_POWER"
1310 [(set (match_dup 3)
1311 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1312 (const_int 0)
1313 (minus:SI (match_dup 2) (match_dup 1))))
1314 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1315 "")
1317 (define_expand "smaxsi3"
1318 [(set (match_dup 3)
1319 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1320 (match_operand:SI 2 "reg_or_short_operand" ""))
1321 (const_int 0)
1322 (minus:SI (match_dup 2) (match_dup 1))))
1323 (set (match_operand:SI 0 "gpc_reg_operand" "")
1324 (plus:SI (match_dup 3) (match_dup 1)))]
1325 "TARGET_POWER || TARGET_ISEL"
1326 "
1327 {
1328 if (TARGET_ISEL)
1329 {
1330 operands[2] = force_reg (SImode, operands[2]);
1331 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1332 DONE;
1333 }
1334 operands[3] = gen_reg_rtx (SImode);
1335 }")
1337 (define_split
1338 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1339 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1340 (match_operand:SI 2 "reg_or_short_operand" "")))
1341 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1342 "TARGET_POWER"
1343 [(set (match_dup 3)
1344 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1345 (const_int 0)
1346 (minus:SI (match_dup 2) (match_dup 1))))
1347 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1348 "")
1350 (define_expand "uminsi3"
1351 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1352 (match_dup 5)))
1353 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1354 (match_dup 5)))
1355 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1356 (const_int 0)
1357 (minus:SI (match_dup 4) (match_dup 3))))
1358 (set (match_operand:SI 0 "gpc_reg_operand" "")
1359 (minus:SI (match_dup 2) (match_dup 3)))]
1360 "TARGET_POWER || TARGET_ISEL"
1361 "
1362 {
1363 if (TARGET_ISEL)
1364 {
1365 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1366 DONE;
1367 }
1368 operands[3] = gen_reg_rtx (SImode);
1369 operands[4] = gen_reg_rtx (SImode);
1370 operands[5] = GEN_INT (-2147483647 - 1);
1371 }")
1373 (define_expand "umaxsi3"
1374 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1375 (match_dup 5)))
1376 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1377 (match_dup 5)))
1378 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1379 (const_int 0)
1380 (minus:SI (match_dup 4) (match_dup 3))))
1381 (set (match_operand:SI 0 "gpc_reg_operand" "")
1382 (plus:SI (match_dup 3) (match_dup 1)))]
1383 "TARGET_POWER || TARGET_ISEL"
1384 "
1385 {
1386 if (TARGET_ISEL)
1387 {
1388 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1389 DONE;
1390 }
1391 operands[3] = gen_reg_rtx (SImode);
1392 operands[4] = gen_reg_rtx (SImode);
1393 operands[5] = GEN_INT (-2147483647 - 1);
1394 }")
1396 (define_insn ""
1397 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1398 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1399 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1400 (const_int 0)
1401 (minus:SI (match_dup 2) (match_dup 1))))]
1402 "TARGET_POWER"
1403 "doz%I2 %0,%1,%2")
1405 (define_insn ""
1406 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1407 (compare:CC
1408 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1409 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1410 (const_int 0)
1411 (minus:SI (match_dup 2) (match_dup 1)))
1412 (const_int 0)))
1413 (clobber (match_scratch:SI 3 "=r,r"))]
1414 "TARGET_POWER"
1415 "@
1416 doz%I2. %3,%1,%2
1417 #"
1418 [(set_attr "type" "delayed_compare")
1419 (set_attr "length" "4,8")])
1421 (define_split
1422 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1423 (compare:CC
1424 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1425 (match_operand:SI 2 "reg_or_short_operand" ""))
1426 (const_int 0)
1427 (minus:SI (match_dup 2) (match_dup 1)))
1428 (const_int 0)))
1429 (clobber (match_scratch:SI 3 ""))]
1430 "TARGET_POWER && reload_completed"
1431 [(set (match_dup 3)
1432 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1433 (const_int 0)
1434 (minus:SI (match_dup 2) (match_dup 1))))
1435 (set (match_dup 0)
1436 (compare:CC (match_dup 3)
1437 (const_int 0)))]
1438 "")
1440 (define_insn ""
1441 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1442 (compare:CC
1443 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1444 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1445 (const_int 0)
1446 (minus:SI (match_dup 2) (match_dup 1)))
1447 (const_int 0)))
1448 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1449 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1450 (const_int 0)
1451 (minus:SI (match_dup 2) (match_dup 1))))]
1452 "TARGET_POWER"
1453 "@
1454 doz%I2. %0,%1,%2
1455 #"
1456 [(set_attr "type" "delayed_compare")
1457 (set_attr "length" "4,8")])
1459 (define_split
1460 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1461 (compare:CC
1462 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1463 (match_operand:SI 2 "reg_or_short_operand" ""))
1464 (const_int 0)
1465 (minus:SI (match_dup 2) (match_dup 1)))
1466 (const_int 0)))
1467 (set (match_operand:SI 0 "gpc_reg_operand" "")
1468 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1469 (const_int 0)
1470 (minus:SI (match_dup 2) (match_dup 1))))]
1471 "TARGET_POWER && reload_completed"
1472 [(set (match_dup 0)
1473 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1474 (const_int 0)
1475 (minus:SI (match_dup 2) (match_dup 1))))
1476 (set (match_dup 3)
1477 (compare:CC (match_dup 0)
1478 (const_int 0)))]
1479 "")
1481 ;; We don't need abs with condition code because such comparisons should
1482 ;; never be done.
1483 (define_expand "abssi2"
1484 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1485 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1486 ""
1487 "
1488 {
1489 if (TARGET_ISEL)
1490 {
1491 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1492 DONE;
1493 }
1494 else if (! TARGET_POWER)
1495 {
1496 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1497 DONE;
1498 }
1499 }")
1501 (define_insn "*abssi2_power"
1502 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1503 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1504 "TARGET_POWER"
1505 "abs %0,%1")
1507 (define_insn_and_split "abssi2_isel"
1508 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1509 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1510 (clobber (match_scratch:SI 2 "=&b"))
1511 (clobber (match_scratch:CC 3 "=y"))]
1512 "TARGET_ISEL"
1513 "#"
1514 "&& reload_completed"
1515 [(set (match_dup 2) (neg:SI (match_dup 1)))
1516 (set (match_dup 3)
1517 (compare:CC (match_dup 1)
1518 (const_int 0)))
1519 (set (match_dup 0)
1520 (if_then_else:SI (ge (match_dup 3)
1521 (const_int 0))
1522 (match_dup 1)
1523 (match_dup 2)))]
1524 "")
1526 (define_insn_and_split "abssi2_nopower"
1527 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1528 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1529 (clobber (match_scratch:SI 2 "=&r,&r"))]
1530 "! TARGET_POWER && ! TARGET_ISEL"
1531 "#"
1532 "&& reload_completed"
1533 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1534 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1535 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1536 "")
1538 (define_insn "*nabs_power"
1539 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1540 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1541 "TARGET_POWER"
1542 "nabs %0,%1")
1544 (define_insn_and_split "*nabs_nopower"
1545 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1546 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1547 (clobber (match_scratch:SI 2 "=&r,&r"))]
1548 "! TARGET_POWER"
1549 "#"
1550 "&& reload_completed"
1551 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1552 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1553 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1554 "")
1556 (define_insn "negsi2"
1557 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1558 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1559 ""
1560 "neg %0,%1")
1562 (define_insn ""
1563 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1564 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1565 (const_int 0)))
1566 (clobber (match_scratch:SI 2 "=r,r"))]
1567 "TARGET_32BIT"
1568 "@
1569 neg. %2,%1
1570 #"
1571 [(set_attr "type" "fast_compare")
1572 (set_attr "length" "4,8")])
1574 (define_split
1575 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1576 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1577 (const_int 0)))
1578 (clobber (match_scratch:SI 2 ""))]
1579 "TARGET_32BIT && reload_completed"
1580 [(set (match_dup 2)
1581 (neg:SI (match_dup 1)))
1582 (set (match_dup 0)
1583 (compare:CC (match_dup 2)
1584 (const_int 0)))]
1585 "")
1587 (define_insn ""
1588 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1589 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1590 (const_int 0)))
1591 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1592 (neg:SI (match_dup 1)))]
1593 "TARGET_32BIT"
1594 "@
1595 neg. %0,%1
1596 #"
1597 [(set_attr "type" "fast_compare")
1598 (set_attr "length" "4,8")])
1600 (define_split
1601 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1602 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1603 (const_int 0)))
1604 (set (match_operand:SI 0 "gpc_reg_operand" "")
1605 (neg:SI (match_dup 1)))]
1606 "TARGET_32BIT && reload_completed"
1607 [(set (match_dup 0)
1608 (neg:SI (match_dup 1)))
1609 (set (match_dup 2)
1610 (compare:CC (match_dup 0)
1611 (const_int 0)))]
1612 "")
1614 (define_insn "clzsi2"
1615 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1616 (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1617 ""
1618 "{cntlz|cntlzw} %0,%1")
1620 (define_expand "ctzsi2"
1621 [(set (match_dup 2)
1622 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1623 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1624 (match_dup 2)))
1625 (clobber (scratch:CC))])
1626 (set (match_dup 4) (clz:SI (match_dup 3)))
1627 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1628 (minus:SI (const_int 31) (match_dup 4)))]
1629 ""
1630 {
1631 operands[2] = gen_reg_rtx (SImode);
1632 operands[3] = gen_reg_rtx (SImode);
1633 operands[4] = gen_reg_rtx (SImode);
1634 })
1636 (define_expand "ffssi2"
1637 [(set (match_dup 2)
1638 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1639 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1640 (match_dup 2)))
1641 (clobber (scratch:CC))])
1642 (set (match_dup 4) (clz:SI (match_dup 3)))
1643 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1644 (minus:SI (const_int 32) (match_dup 4)))]
1645 ""
1646 {
1647 operands[2] = gen_reg_rtx (SImode);
1648 operands[3] = gen_reg_rtx (SImode);
1649 operands[4] = gen_reg_rtx (SImode);
1650 })
1652 (define_expand "mulsi3"
1653 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1654 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1655 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1656 ""
1657 "
1658 {
1659 if (TARGET_POWER)
1660 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1661 else
1662 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1663 DONE;
1664 }")
1666 (define_insn "mulsi3_mq"
1667 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1668 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1669 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1670 (clobber (match_scratch:SI 3 "=q,q"))]
1671 "TARGET_POWER"
1672 "@
1673 {muls|mullw} %0,%1,%2
1674 {muli|mulli} %0,%1,%2"
1675 [(set (attr "type")
1676 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1677 (const_string "imul3")
1678 (match_operand:SI 2 "short_cint_operand" "")
1679 (const_string "imul2")]
1680 (const_string "imul")))])
1682 (define_insn "mulsi3_no_mq"
1683 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1684 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1685 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1686 "! TARGET_POWER"
1687 "@
1688 {muls|mullw} %0,%1,%2
1689 {muli|mulli} %0,%1,%2"
1690 [(set (attr "type")
1691 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1692 (const_string "imul3")
1693 (match_operand:SI 2 "short_cint_operand" "")
1694 (const_string "imul2")]
1695 (const_string "imul")))])
1697 (define_insn "*mulsi3_mq_internal1"
1698 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1699 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1700 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1701 (const_int 0)))
1702 (clobber (match_scratch:SI 3 "=r,r"))
1703 (clobber (match_scratch:SI 4 "=q,q"))]
1704 "TARGET_POWER"
1705 "@
1706 {muls.|mullw.} %3,%1,%2
1707 #"
1708 [(set_attr "type" "imul_compare")
1709 (set_attr "length" "4,8")])
1711 (define_split
1712 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1713 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1714 (match_operand:SI 2 "gpc_reg_operand" ""))
1715 (const_int 0)))
1716 (clobber (match_scratch:SI 3 ""))
1717 (clobber (match_scratch:SI 4 ""))]
1718 "TARGET_POWER && reload_completed"
1719 [(parallel [(set (match_dup 3)
1720 (mult:SI (match_dup 1) (match_dup 2)))
1721 (clobber (match_dup 4))])
1722 (set (match_dup 0)
1723 (compare:CC (match_dup 3)
1724 (const_int 0)))]
1725 "")
1727 (define_insn "*mulsi3_no_mq_internal1"
1728 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1729 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1730 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1731 (const_int 0)))
1732 (clobber (match_scratch:SI 3 "=r,r"))]
1733 "! TARGET_POWER"
1734 "@
1735 {muls.|mullw.} %3,%1,%2
1736 #"
1737 [(set_attr "type" "imul_compare")
1738 (set_attr "length" "4,8")])
1740 (define_split
1741 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1742 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1743 (match_operand:SI 2 "gpc_reg_operand" ""))
1744 (const_int 0)))
1745 (clobber (match_scratch:SI 3 ""))]
1746 "! TARGET_POWER && reload_completed"
1747 [(set (match_dup 3)
1748 (mult:SI (match_dup 1) (match_dup 2)))
1749 (set (match_dup 0)
1750 (compare:CC (match_dup 3)
1751 (const_int 0)))]
1752 "")
1754 (define_insn "*mulsi3_mq_internal2"
1755 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1756 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1757 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1758 (const_int 0)))
1759 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1760 (mult:SI (match_dup 1) (match_dup 2)))
1761 (clobber (match_scratch:SI 4 "=q,q"))]
1762 "TARGET_POWER"
1763 "@
1764 {muls.|mullw.} %0,%1,%2
1765 #"
1766 [(set_attr "type" "imul_compare")
1767 (set_attr "length" "4,8")])
1769 (define_split
1770 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1771 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1772 (match_operand:SI 2 "gpc_reg_operand" ""))
1773 (const_int 0)))
1774 (set (match_operand:SI 0 "gpc_reg_operand" "")
1775 (mult:SI (match_dup 1) (match_dup 2)))
1776 (clobber (match_scratch:SI 4 ""))]
1777 "TARGET_POWER && reload_completed"
1778 [(parallel [(set (match_dup 0)
1779 (mult:SI (match_dup 1) (match_dup 2)))
1780 (clobber (match_dup 4))])
1781 (set (match_dup 3)
1782 (compare:CC (match_dup 0)
1783 (const_int 0)))]
1784 "")
1786 (define_insn "*mulsi3_no_mq_internal2"
1787 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1788 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1789 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1790 (const_int 0)))
1791 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1792 (mult:SI (match_dup 1) (match_dup 2)))]
1793 "! TARGET_POWER"
1794 "@
1795 {muls.|mullw.} %0,%1,%2
1796 #"
1797 [(set_attr "type" "imul_compare")
1798 (set_attr "length" "4,8")])
1800 (define_split
1801 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1802 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1803 (match_operand:SI 2 "gpc_reg_operand" ""))
1804 (const_int 0)))
1805 (set (match_operand:SI 0 "gpc_reg_operand" "")
1806 (mult:SI (match_dup 1) (match_dup 2)))]
1807 "! TARGET_POWER && reload_completed"
1808 [(set (match_dup 0)
1809 (mult:SI (match_dup 1) (match_dup 2)))
1810 (set (match_dup 3)
1811 (compare:CC (match_dup 0)
1812 (const_int 0)))]
1813 "")
1815 ;; Operand 1 is divided by operand 2; quotient goes to operand
1816 ;; 0 and remainder to operand 3.
1817 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1819 (define_expand "divmodsi4"
1820 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1821 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1822 (match_operand:SI 2 "gpc_reg_operand" "")))
1823 (set (match_operand:SI 3 "register_operand" "")
1824 (mod:SI (match_dup 1) (match_dup 2)))])]
1825 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1826 "
1827 {
1828 if (! TARGET_POWER && ! TARGET_POWERPC)
1829 {
1830 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1831 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1832 emit_insn (gen_divss_call ());
1833 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1834 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1835 DONE;
1836 }
1837 }")
1839 (define_insn "*divmodsi4_internal"
1840 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1841 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1842 (match_operand:SI 2 "gpc_reg_operand" "r")))
1843 (set (match_operand:SI 3 "register_operand" "=q")
1844 (mod:SI (match_dup 1) (match_dup 2)))]
1845 "TARGET_POWER"
1846 "divs %0,%1,%2"
1847 [(set_attr "type" "idiv")])
1849 (define_expand "udivsi3"
1850 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1851 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1852 (match_operand:SI 2 "gpc_reg_operand" "")))]
1853 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1854 "
1855 {
1856 if (! TARGET_POWER && ! TARGET_POWERPC)
1857 {
1858 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1859 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1860 emit_insn (gen_quous_call ());
1861 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1862 DONE;
1863 }
1864 else if (TARGET_POWER)
1865 {
1866 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1867 DONE;
1868 }
1869 }")
1871 (define_insn "udivsi3_mq"
1872 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1873 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1874 (match_operand:SI 2 "gpc_reg_operand" "r")))
1875 (clobber (match_scratch:SI 3 "=q"))]
1876 "TARGET_POWERPC && TARGET_POWER"
1877 "divwu %0,%1,%2"
1878 [(set_attr "type" "idiv")])
1880 (define_insn "*udivsi3_no_mq"
1881 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1882 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1883 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1884 "TARGET_POWERPC && ! TARGET_POWER"
1885 "divwu %0,%1,%2"
1886 [(set_attr "type" "idiv")])
1888 ;; For powers of two we can do srai/aze for divide and then adjust for
1889 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1890 ;; used; for PowerPC, force operands into register and do a normal divide;
1891 ;; for AIX common-mode, use quoss call on register operands.
1892 (define_expand "divsi3"
1893 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1894 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1895 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1896 ""
1897 "
1898 {
1899 if (GET_CODE (operands[2]) == CONST_INT
1900 && INTVAL (operands[2]) > 0
1901 && exact_log2 (INTVAL (operands[2])) >= 0)
1902 ;
1903 else if (TARGET_POWERPC)
1904 {
1905 operands[2] = force_reg (SImode, operands[2]);
1906 if (TARGET_POWER)
1907 {
1908 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1909 DONE;
1910 }
1911 }
1912 else if (TARGET_POWER)
1913 FAIL;
1914 else
1915 {
1916 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1917 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1918 emit_insn (gen_quoss_call ());
1919 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1920 DONE;
1921 }
1922 }")
1924 (define_insn "divsi3_mq"
1925 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1926 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1927 (match_operand:SI 2 "gpc_reg_operand" "r")))
1928 (clobber (match_scratch:SI 3 "=q"))]
1929 "TARGET_POWERPC && TARGET_POWER"
1930 "divw %0,%1,%2"
1931 [(set_attr "type" "idiv")])
1933 (define_insn "*divsi3_no_mq"
1934 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1935 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1936 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1937 "TARGET_POWERPC && ! TARGET_POWER"
1938 "divw %0,%1,%2"
1939 [(set_attr "type" "idiv")])
1941 (define_expand "modsi3"
1942 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1943 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1944 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1945 ""
1946 "
1947 {
1948 int i;
1949 rtx temp1;
1950 rtx temp2;
1952 if (GET_CODE (operands[2]) != CONST_INT
1953 || INTVAL (operands[2]) <= 0
1954 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
1955 FAIL;
1957 temp1 = gen_reg_rtx (SImode);
1958 temp2 = gen_reg_rtx (SImode);
1960 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
1961 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1962 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1963 DONE;
1964 }")
1966 (define_insn ""
1967 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1968 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1969 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
1970 ""
1971 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
1972 [(set_attr "length" "8")])
1974 (define_insn ""
1975 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1976 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1977 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
1978 (const_int 0)))
1979 (clobber (match_scratch:SI 3 "=r,r"))]
1980 ""
1981 "@
1982 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
1983 #"
1984 [(set_attr "type" "compare")
1985 (set_attr "length" "8,12")])
1987 (define_split
1988 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1989 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1990 (match_operand:SI 2 "exact_log2_cint_operand" ""))
1991 (const_int 0)))
1992 (clobber (match_scratch:SI 3 ""))]
1993 "reload_completed"
1994 [(set (match_dup 3)
1995 (div:SI (match_dup 1) (match_dup 2)))
1996 (set (match_dup 0)
1997 (compare:CC (match_dup 3)
1998 (const_int 0)))]
1999 "")
2001 (define_insn ""
2002 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2003 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2004 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2005 (const_int 0)))
2006 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2007 (div:SI (match_dup 1) (match_dup 2)))]
2008 ""
2009 "@
2010 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2011 #"
2012 [(set_attr "type" "compare")
2013 (set_attr "length" "8,12")])
2015 (define_split
2016 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2017 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2018 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2019 (const_int 0)))
2020 (set (match_operand:SI 0 "gpc_reg_operand" "")
2021 (div:SI (match_dup 1) (match_dup 2)))]
2022 "reload_completed"
2023 [(set (match_dup 0)
2024 (div:SI (match_dup 1) (match_dup 2)))
2025 (set (match_dup 3)
2026 (compare:CC (match_dup 0)
2027 (const_int 0)))]
2028 "")
2030 (define_insn ""
2031 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2032 (udiv:SI
2033 (plus:DI (ashift:DI
2034 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2035 (const_int 32))
2036 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2037 (match_operand:SI 3 "gpc_reg_operand" "r")))
2038 (set (match_operand:SI 2 "register_operand" "=*q")
2039 (umod:SI
2040 (plus:DI (ashift:DI
2041 (zero_extend:DI (match_dup 1)) (const_int 32))
2042 (zero_extend:DI (match_dup 4)))
2043 (match_dup 3)))]
2044 "TARGET_POWER"
2045 "div %0,%1,%3"
2046 [(set_attr "type" "idiv")])
2048 ;; To do unsigned divide we handle the cases of the divisor looking like a
2049 ;; negative number. If it is a constant that is less than 2**31, we don't
2050 ;; have to worry about the branches. So make a few subroutines here.
2051 ;;
2052 ;; First comes the normal case.
2053 (define_expand "udivmodsi4_normal"
2054 [(set (match_dup 4) (const_int 0))
2055 (parallel [(set (match_operand:SI 0 "" "")
2056 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2057 (const_int 32))
2058 (zero_extend:DI (match_operand:SI 1 "" "")))
2059 (match_operand:SI 2 "" "")))
2060 (set (match_operand:SI 3 "" "")
2061 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2062 (const_int 32))
2063 (zero_extend:DI (match_dup 1)))
2064 (match_dup 2)))])]
2065 "TARGET_POWER"
2066 "
2067 { operands[4] = gen_reg_rtx (SImode); }")
2069 ;; This handles the branches.
2070 (define_expand "udivmodsi4_tests"
2071 [(set (match_operand:SI 0 "" "") (const_int 0))
2072 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2073 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2074 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2075 (label_ref (match_operand:SI 4 "" "")) (pc)))
2076 (set (match_dup 0) (const_int 1))
2077 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2078 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2079 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2080 (label_ref (match_dup 4)) (pc)))]
2081 "TARGET_POWER"
2082 "
2083 { operands[5] = gen_reg_rtx (CCUNSmode);
2084 operands[6] = gen_reg_rtx (CCmode);
2085 }")
2087 (define_expand "udivmodsi4"
2088 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2089 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2090 (match_operand:SI 2 "reg_or_cint_operand" "")))
2091 (set (match_operand:SI 3 "gpc_reg_operand" "")
2092 (umod:SI (match_dup 1) (match_dup 2)))])]
2093 ""
2094 "
2095 {
2096 rtx label = 0;
2098 if (! TARGET_POWER)
2099 {
2100 if (! TARGET_POWERPC)
2101 {
2102 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2103 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2104 emit_insn (gen_divus_call ());
2105 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2106 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2107 DONE;
2108 }
2109 else
2110 FAIL;
2111 }
2113 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2114 {
2115 operands[2] = force_reg (SImode, operands[2]);
2116 label = gen_label_rtx ();
2117 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2118 operands[3], label));
2119 }
2120 else
2121 operands[2] = force_reg (SImode, operands[2]);
2123 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2124 operands[3]));
2125 if (label)
2126 emit_label (label);
2128 DONE;
2129 }")
2131 ;; AIX architecture-independent common-mode multiply (DImode),
2132 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2133 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2134 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2135 ;; assumed unused if generating common-mode, so ignore.
2136 (define_insn "mulh_call"
2137 [(set (reg:SI 3)
2138 (truncate:SI
2139 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2140 (sign_extend:DI (reg:SI 4)))
2141 (const_int 32))))
2142 (clobber (match_scratch:SI 0 "=l"))]
2143 "! TARGET_POWER && ! TARGET_POWERPC"
2144 "bla __mulh"
2145 [(set_attr "type" "imul")])
2147 (define_insn "mull_call"
2148 [(set (reg:DI 3)
2149 (mult:DI (sign_extend:DI (reg:SI 3))
2150 (sign_extend:DI (reg:SI 4))))
2151 (clobber (match_scratch:SI 0 "=l"))
2152 (clobber (reg:SI 0))]
2153 "! TARGET_POWER && ! TARGET_POWERPC"
2154 "bla __mull"
2155 [(set_attr "type" "imul")])
2157 (define_insn "divss_call"
2158 [(set (reg:SI 3)
2159 (div:SI (reg:SI 3) (reg:SI 4)))
2160 (set (reg:SI 4)
2161 (mod:SI (reg:SI 3) (reg:SI 4)))
2162 (clobber (match_scratch:SI 0 "=l"))
2163 (clobber (reg:SI 0))]
2164 "! TARGET_POWER && ! TARGET_POWERPC"
2165 "bla __divss"
2166 [(set_attr "type" "idiv")])
2168 (define_insn "divus_call"
2169 [(set (reg:SI 3)
2170 (udiv:SI (reg:SI 3) (reg:SI 4)))
2171 (set (reg:SI 4)
2172 (umod:SI (reg:SI 3) (reg:SI 4)))
2173 (clobber (match_scratch:SI 0 "=l"))
2174 (clobber (reg:SI 0))
2175 (clobber (match_scratch:CC 1 "=x"))
2176 (clobber (reg:CC 69))]
2177 "! TARGET_POWER && ! TARGET_POWERPC"
2178 "bla __divus"
2179 [(set_attr "type" "idiv")])
2181 (define_insn "quoss_call"
2182 [(set (reg:SI 3)
2183 (div:SI (reg:SI 3) (reg:SI 4)))
2184 (clobber (match_scratch:SI 0 "=l"))]
2185 "! TARGET_POWER && ! TARGET_POWERPC"
2186 "bla __quoss"
2187 [(set_attr "type" "idiv")])
2189 (define_insn "quous_call"
2190 [(set (reg:SI 3)
2191 (udiv:SI (reg:SI 3) (reg:SI 4)))
2192 (clobber (match_scratch:SI 0 "=l"))
2193 (clobber (reg:SI 0))
2194 (clobber (match_scratch:CC 1 "=x"))
2195 (clobber (reg:CC 69))]
2196 "! TARGET_POWER && ! TARGET_POWERPC"
2197 "bla __quous"
2198 [(set_attr "type" "idiv")])
2199 \f
2200 ;; Logical instructions
2201 ;; The logical instructions are mostly combined by using match_operator,
2202 ;; but the plain AND insns are somewhat different because there is no
2203 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2204 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2206 (define_insn "andsi3"
2207 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2208 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2209 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2210 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2211 ""
2212 "@
2213 and %0,%1,%2
2214 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2215 {andil.|andi.} %0,%1,%b2
2216 {andiu.|andis.} %0,%1,%u2")
2218 ;; Note to set cr's other than cr0 we do the and immediate and then
2219 ;; the test again -- this avoids a mfcr which on the higher end
2220 ;; machines causes an execution serialization
2222 (define_insn "*andsi3_internal2"
2223 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2224 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2225 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2226 (const_int 0)))
2227 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2228 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2229 "TARGET_32BIT"
2230 "@
2231 and. %3,%1,%2
2232 {andil.|andi.} %3,%1,%b2
2233 {andiu.|andis.} %3,%1,%u2
2234 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2235 #
2236 #
2237 #
2238 #"
2239 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2240 (set_attr "length" "4,4,4,4,8,8,8,8")])
2242 (define_insn "*andsi3_internal3"
2243 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2244 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2245 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2246 (const_int 0)))
2247 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2248 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2249 "TARGET_64BIT"
2250 "@
2251 #
2252 {andil.|andi.} %3,%1,%b2
2253 {andiu.|andis.} %3,%1,%u2
2254 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2255 #
2256 #
2257 #
2258 #"
2259 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2260 (set_attr "length" "8,4,4,4,8,8,8,8")])
2262 (define_split
2263 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2264 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2265 (match_operand:SI 2 "and_operand" ""))
2266 (const_int 0)))
2267 (clobber (match_scratch:SI 3 ""))
2268 (clobber (match_scratch:CC 4 ""))]
2269 "reload_completed"
2270 [(parallel [(set (match_dup 3)
2271 (and:SI (match_dup 1)
2272 (match_dup 2)))
2273 (clobber (match_dup 4))])
2274 (set (match_dup 0)
2275 (compare:CC (match_dup 3)
2276 (const_int 0)))]
2277 "")
2279 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2280 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2282 (define_split
2283 [(set (match_operand:CC 0 "cc_reg_operand" "")
2284 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2285 (match_operand:SI 2 "gpc_reg_operand" ""))
2286 (const_int 0)))
2287 (clobber (match_scratch:SI 3 ""))
2288 (clobber (match_scratch:CC 4 ""))]
2289 "TARGET_POWERPC64 && reload_completed"
2290 [(parallel [(set (match_dup 3)
2291 (and:SI (match_dup 1)
2292 (match_dup 2)))
2293 (clobber (match_dup 4))])
2294 (set (match_dup 0)
2295 (compare:CC (match_dup 3)
2296 (const_int 0)))]
2297 "")
2299 (define_insn "*andsi3_internal4"
2300 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2301 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2302 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2303 (const_int 0)))
2304 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2305 (and:SI (match_dup 1)
2306 (match_dup 2)))
2307 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2308 "TARGET_32BIT"
2309 "@
2310 and. %0,%1,%2
2311 {andil.|andi.} %0,%1,%b2
2312 {andiu.|andis.} %0,%1,%u2
2313 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2314 #
2315 #
2316 #
2317 #"
2318 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2319 (set_attr "length" "4,4,4,4,8,8,8,8")])
2321 (define_insn "*andsi3_internal5"
2322 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2323 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2324 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2325 (const_int 0)))
2326 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2327 (and:SI (match_dup 1)
2328 (match_dup 2)))
2329 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2330 "TARGET_64BIT"
2331 "@
2332 #
2333 {andil.|andi.} %0,%1,%b2
2334 {andiu.|andis.} %0,%1,%u2
2335 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2336 #
2337 #
2338 #
2339 #"
2340 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2341 (set_attr "length" "8,4,4,4,8,8,8,8")])
2343 (define_split
2344 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2345 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2346 (match_operand:SI 2 "and_operand" ""))
2347 (const_int 0)))
2348 (set (match_operand:SI 0 "gpc_reg_operand" "")
2349 (and:SI (match_dup 1)
2350 (match_dup 2)))
2351 (clobber (match_scratch:CC 4 ""))]
2352 "reload_completed"
2353 [(parallel [(set (match_dup 0)
2354 (and:SI (match_dup 1)
2355 (match_dup 2)))
2356 (clobber (match_dup 4))])
2357 (set (match_dup 3)
2358 (compare:CC (match_dup 0)
2359 (const_int 0)))]
2360 "")
2362 (define_split
2363 [(set (match_operand:CC 3 "cc_reg_operand" "")
2364 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2365 (match_operand:SI 2 "gpc_reg_operand" ""))
2366 (const_int 0)))
2367 (set (match_operand:SI 0 "gpc_reg_operand" "")
2368 (and:SI (match_dup 1)
2369 (match_dup 2)))
2370 (clobber (match_scratch:CC 4 ""))]
2371 "TARGET_POWERPC64 && reload_completed"
2372 [(parallel [(set (match_dup 0)
2373 (and:SI (match_dup 1)
2374 (match_dup 2)))
2375 (clobber (match_dup 4))])
2376 (set (match_dup 3)
2377 (compare:CC (match_dup 0)
2378 (const_int 0)))]
2379 "")
2381 ;; Handle the PowerPC64 rlwinm corner case
2383 (define_insn_and_split "*andsi3_internal6"
2384 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2385 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2386 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2387 "TARGET_POWERPC64"
2388 "#"
2389 "TARGET_POWERPC64"
2390 [(set (match_dup 0)
2391 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2392 (match_dup 4)))
2393 (set (match_dup 0)
2394 (rotate:SI (match_dup 0) (match_dup 5)))]
2395 "
2396 {
2397 int mb = extract_MB (operands[2]);
2398 int me = extract_ME (operands[2]);
2399 operands[3] = GEN_INT (me + 1);
2400 operands[5] = GEN_INT (32 - (me + 1));
2401 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2402 }"
2403 [(set_attr "length" "8")])
2405 (define_insn_and_split "*andsi3_internal7"
2406 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2407 (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r")
2408 (match_operand:SI 1 "mask_operand_wrap" "i,i"))
2409 (const_int 0)))
2410 (clobber (match_scratch:SI 3 "=r,r"))]
2411 "TARGET_POWERPC64"
2412 "#"
2413 "TARGET_POWERPC64"
2414 [(parallel [(set (match_dup 2)
2415 (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4))
2416 (match_dup 5))
2417 (const_int 0)))
2418 (clobber (match_dup 3))])]
2419 "
2420 {
2421 int mb = extract_MB (operands[1]);
2422 int me = extract_ME (operands[1]);
2423 operands[4] = GEN_INT (me + 1);
2424 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2425 }"
2426 [(set_attr "type" "delayed_compare,compare")
2427 (set_attr "length" "4,8")])
2429 (define_insn_and_split "*andsi3_internal8"
2430 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2431 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2432 (match_operand:SI 2 "mask_operand_wrap" "i,i"))
2433 (const_int 0)))
2434 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2435 (and:SI (match_dup 1)
2436 (match_dup 2)))]
2437 "TARGET_POWERPC64"
2438 "#"
2439 "TARGET_POWERPC64"
2440 [(parallel [(set (match_dup 3)
2441 (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4))
2442 (match_dup 5))
2443 (const_int 0)))
2444 (set (match_dup 0)
2445 (and:SI (rotate:SI (match_dup 1) (match_dup 4))
2446 (match_dup 5)))])
2447 (set (match_dup 0)
2448 (rotate:SI (match_dup 0) (match_dup 6)))]
2449 "
2450 {
2451 int mb = extract_MB (operands[2]);
2452 int me = extract_ME (operands[2]);
2453 operands[4] = GEN_INT (me + 1);
2454 operands[6] = GEN_INT (32 - (me + 1));
2455 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2456 }"
2457 [(set_attr "type" "delayed_compare,compare")
2458 (set_attr "length" "8,12")])
2460 (define_expand "iorsi3"
2461 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2462 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2463 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2464 ""
2465 "
2466 {
2467 if (GET_CODE (operands[2]) == CONST_INT
2468 && ! logical_operand (operands[2], SImode))
2469 {
2470 HOST_WIDE_INT value = INTVAL (operands[2]);
2471 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2472 ? operands[0] : gen_reg_rtx (SImode));
2474 emit_insn (gen_iorsi3 (tmp, operands[1],
2475 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2476 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2477 DONE;
2478 }
2479 }")
2481 (define_expand "xorsi3"
2482 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2483 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2484 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2485 ""
2486 "
2487 {
2488 if (GET_CODE (operands[2]) == CONST_INT
2489 && ! logical_operand (operands[2], SImode))
2490 {
2491 HOST_WIDE_INT value = INTVAL (operands[2]);
2492 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2493 ? operands[0] : gen_reg_rtx (SImode));
2495 emit_insn (gen_xorsi3 (tmp, operands[1],
2496 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2497 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2498 DONE;
2499 }
2500 }")
2502 (define_insn "*boolsi3_internal1"
2503 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2504 (match_operator:SI 3 "boolean_or_operator"
2505 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2506 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2507 ""
2508 "@
2509 %q3 %0,%1,%2
2510 {%q3il|%q3i} %0,%1,%b2
2511 {%q3iu|%q3is} %0,%1,%u2")
2513 (define_insn "*boolsi3_internal2"
2514 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2515 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2516 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2517 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2518 (const_int 0)))
2519 (clobber (match_scratch:SI 3 "=r,r"))]
2520 "TARGET_32BIT"
2521 "@
2522 %q4. %3,%1,%2
2523 #"
2524 [(set_attr "type" "compare")
2525 (set_attr "length" "4,8")])
2527 (define_split
2528 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2529 (compare:CC (match_operator:SI 4 "boolean_operator"
2530 [(match_operand:SI 1 "gpc_reg_operand" "")
2531 (match_operand:SI 2 "gpc_reg_operand" "")])
2532 (const_int 0)))
2533 (clobber (match_scratch:SI 3 ""))]
2534 "TARGET_32BIT && reload_completed"
2535 [(set (match_dup 3) (match_dup 4))
2536 (set (match_dup 0)
2537 (compare:CC (match_dup 3)
2538 (const_int 0)))]
2539 "")
2541 (define_insn "*boolsi3_internal3"
2542 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2543 (compare:CC (match_operator:SI 4 "boolean_operator"
2544 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2545 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2546 (const_int 0)))
2547 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2548 (match_dup 4))]
2549 "TARGET_32BIT"
2550 "@
2551 %q4. %0,%1,%2
2552 #"
2553 [(set_attr "type" "compare")
2554 (set_attr "length" "4,8")])
2556 (define_split
2557 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2558 (compare:CC (match_operator:SI 4 "boolean_operator"
2559 [(match_operand:SI 1 "gpc_reg_operand" "")
2560 (match_operand:SI 2 "gpc_reg_operand" "")])
2561 (const_int 0)))
2562 (set (match_operand:SI 0 "gpc_reg_operand" "")
2563 (match_dup 4))]
2564 "TARGET_32BIT && reload_completed"
2565 [(set (match_dup 0) (match_dup 4))
2566 (set (match_dup 3)
2567 (compare:CC (match_dup 0)
2568 (const_int 0)))]
2569 "")
2571 ;; Split a logical operation that we can't do in one insn into two insns,
2572 ;; each of which does one 16-bit part. This is used by combine.
2574 (define_split
2575 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2576 (match_operator:SI 3 "boolean_or_operator"
2577 [(match_operand:SI 1 "gpc_reg_operand" "")
2578 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2579 ""
2580 [(set (match_dup 0) (match_dup 4))
2581 (set (match_dup 0) (match_dup 5))]
2582 "
2583 {
2584 rtx i;
2585 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2586 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2587 operands[1], i);
2588 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2589 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2590 operands[0], i);
2591 }")
2593 (define_insn "*boolcsi3_internal1"
2594 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2595 (match_operator:SI 3 "boolean_operator"
2596 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2597 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2598 ""
2599 "%q3 %0,%2,%1")
2601 (define_insn "*boolcsi3_internal2"
2602 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2603 (compare:CC (match_operator:SI 4 "boolean_operator"
2604 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2605 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2606 (const_int 0)))
2607 (clobber (match_scratch:SI 3 "=r,r"))]
2608 "TARGET_32BIT"
2609 "@
2610 %q4. %3,%2,%1
2611 #"
2612 [(set_attr "type" "compare")
2613 (set_attr "length" "4,8")])
2615 (define_split
2616 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2617 (compare:CC (match_operator:SI 4 "boolean_operator"
2618 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2619 (match_operand:SI 2 "gpc_reg_operand" "")])
2620 (const_int 0)))
2621 (clobber (match_scratch:SI 3 ""))]
2622 "TARGET_32BIT && reload_completed"
2623 [(set (match_dup 3) (match_dup 4))
2624 (set (match_dup 0)
2625 (compare:CC (match_dup 3)
2626 (const_int 0)))]
2627 "")
2629 (define_insn "*boolcsi3_internal3"
2630 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2631 (compare:CC (match_operator:SI 4 "boolean_operator"
2632 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2633 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2634 (const_int 0)))
2635 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2636 (match_dup 4))]
2637 "TARGET_32BIT"
2638 "@
2639 %q4. %0,%2,%1
2640 #"
2641 [(set_attr "type" "compare")
2642 (set_attr "length" "4,8")])
2644 (define_split
2645 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2646 (compare:CC (match_operator:SI 4 "boolean_operator"
2647 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2648 (match_operand:SI 2 "gpc_reg_operand" "")])
2649 (const_int 0)))
2650 (set (match_operand:SI 0 "gpc_reg_operand" "")
2651 (match_dup 4))]
2652 "TARGET_32BIT && reload_completed"
2653 [(set (match_dup 0) (match_dup 4))
2654 (set (match_dup 3)
2655 (compare:CC (match_dup 0)
2656 (const_int 0)))]
2657 "")
2659 (define_insn "*boolccsi3_internal1"
2660 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2661 (match_operator:SI 3 "boolean_operator"
2662 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2663 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2664 ""
2665 "%q3 %0,%1,%2")
2667 (define_insn "*boolccsi3_internal2"
2668 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2669 (compare:CC (match_operator:SI 4 "boolean_operator"
2670 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2671 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2672 (const_int 0)))
2673 (clobber (match_scratch:SI 3 "=r,r"))]
2674 "TARGET_32BIT"
2675 "@
2676 %q4. %3,%1,%2
2677 #"
2678 [(set_attr "type" "compare")
2679 (set_attr "length" "4,8")])
2681 (define_split
2682 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2683 (compare:CC (match_operator:SI 4 "boolean_operator"
2684 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2685 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2686 (const_int 0)))
2687 (clobber (match_scratch:SI 3 ""))]
2688 "TARGET_32BIT && reload_completed"
2689 [(set (match_dup 3) (match_dup 4))
2690 (set (match_dup 0)
2691 (compare:CC (match_dup 3)
2692 (const_int 0)))]
2693 "")
2695 (define_insn "*boolccsi3_internal3"
2696 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2697 (compare:CC (match_operator:SI 4 "boolean_operator"
2698 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2699 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2700 (const_int 0)))
2701 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2702 (match_dup 4))]
2703 "TARGET_32BIT"
2704 "@
2705 %q4. %0,%1,%2
2706 #"
2707 [(set_attr "type" "compare")
2708 (set_attr "length" "4,8")])
2710 (define_split
2711 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2712 (compare:CC (match_operator:SI 4 "boolean_operator"
2713 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2714 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2715 (const_int 0)))
2716 (set (match_operand:SI 0 "gpc_reg_operand" "")
2717 (match_dup 4))]
2718 "TARGET_32BIT && reload_completed"
2719 [(set (match_dup 0) (match_dup 4))
2720 (set (match_dup 3)
2721 (compare:CC (match_dup 0)
2722 (const_int 0)))]
2723 "")
2725 ;; maskir insn. We need four forms because things might be in arbitrary
2726 ;; orders. Don't define forms that only set CR fields because these
2727 ;; would modify an input register.
2729 (define_insn "*maskir_internal1"
2730 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2731 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2732 (match_operand:SI 1 "gpc_reg_operand" "0"))
2733 (and:SI (match_dup 2)
2734 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2735 "TARGET_POWER"
2736 "maskir %0,%3,%2")
2738 (define_insn "*maskir_internal2"
2739 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2740 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2741 (match_operand:SI 1 "gpc_reg_operand" "0"))
2742 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2743 (match_dup 2))))]
2744 "TARGET_POWER"
2745 "maskir %0,%3,%2")
2747 (define_insn "*maskir_internal3"
2748 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2749 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2750 (match_operand:SI 3 "gpc_reg_operand" "r"))
2751 (and:SI (not:SI (match_dup 2))
2752 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2753 "TARGET_POWER"
2754 "maskir %0,%3,%2")
2756 (define_insn "*maskir_internal4"
2757 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2758 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2759 (match_operand:SI 2 "gpc_reg_operand" "r"))
2760 (and:SI (not:SI (match_dup 2))
2761 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2762 "TARGET_POWER"
2763 "maskir %0,%3,%2")
2765 (define_insn "*maskir_internal5"
2766 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2767 (compare:CC
2768 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2769 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2770 (and:SI (match_dup 2)
2771 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2772 (const_int 0)))
2773 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2774 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2775 (and:SI (match_dup 2) (match_dup 3))))]
2776 "TARGET_POWER"
2777 "@
2778 maskir. %0,%3,%2
2779 #"
2780 [(set_attr "type" "compare")
2781 (set_attr "length" "4,8")])
2783 (define_split
2784 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2785 (compare:CC
2786 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2787 (match_operand:SI 1 "gpc_reg_operand" ""))
2788 (and:SI (match_dup 2)
2789 (match_operand:SI 3 "gpc_reg_operand" "")))
2790 (const_int 0)))
2791 (set (match_operand:SI 0 "gpc_reg_operand" "")
2792 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2793 (and:SI (match_dup 2) (match_dup 3))))]
2794 "TARGET_POWER && reload_completed"
2795 [(set (match_dup 0)
2796 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2797 (and:SI (match_dup 2) (match_dup 3))))
2798 (set (match_dup 4)
2799 (compare:CC (match_dup 0)
2800 (const_int 0)))]
2801 "")
2803 (define_insn "*maskir_internal6"
2804 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2805 (compare:CC
2806 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2807 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2808 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2809 (match_dup 2)))
2810 (const_int 0)))
2811 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2812 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2813 (and:SI (match_dup 3) (match_dup 2))))]
2814 "TARGET_POWER"
2815 "@
2816 maskir. %0,%3,%2
2817 #"
2818 [(set_attr "type" "compare")
2819 (set_attr "length" "4,8")])
2821 (define_split
2822 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2823 (compare:CC
2824 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2825 (match_operand:SI 1 "gpc_reg_operand" ""))
2826 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2827 (match_dup 2)))
2828 (const_int 0)))
2829 (set (match_operand:SI 0 "gpc_reg_operand" "")
2830 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2831 (and:SI (match_dup 3) (match_dup 2))))]
2832 "TARGET_POWER && reload_completed"
2833 [(set (match_dup 0)
2834 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2835 (and:SI (match_dup 3) (match_dup 2))))
2836 (set (match_dup 4)
2837 (compare:CC (match_dup 0)
2838 (const_int 0)))]
2839 "")
2841 (define_insn "*maskir_internal7"
2842 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2843 (compare:CC
2844 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2845 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2846 (and:SI (not:SI (match_dup 2))
2847 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2848 (const_int 0)))
2849 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2850 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2851 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2852 "TARGET_POWER"
2853 "@
2854 maskir. %0,%3,%2
2855 #"
2856 [(set_attr "type" "compare")
2857 (set_attr "length" "4,8")])
2859 (define_split
2860 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2861 (compare:CC
2862 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2863 (match_operand:SI 3 "gpc_reg_operand" ""))
2864 (and:SI (not:SI (match_dup 2))
2865 (match_operand:SI 1 "gpc_reg_operand" "")))
2866 (const_int 0)))
2867 (set (match_operand:SI 0 "gpc_reg_operand" "")
2868 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2869 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2870 "TARGET_POWER && reload_completed"
2871 [(set (match_dup 0)
2872 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2873 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2874 (set (match_dup 4)
2875 (compare:CC (match_dup 0)
2876 (const_int 0)))]
2877 "")
2879 (define_insn "*maskir_internal8"
2880 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2881 (compare:CC
2882 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2883 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2884 (and:SI (not:SI (match_dup 2))
2885 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2886 (const_int 0)))
2887 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2888 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2889 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2890 "TARGET_POWER"
2891 "@
2892 maskir. %0,%3,%2
2893 #"
2894 [(set_attr "type" "compare")
2895 (set_attr "length" "4,8")])
2897 (define_split
2898 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2899 (compare:CC
2900 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2901 (match_operand:SI 2 "gpc_reg_operand" ""))
2902 (and:SI (not:SI (match_dup 2))
2903 (match_operand:SI 1 "gpc_reg_operand" "")))
2904 (const_int 0)))
2905 (set (match_operand:SI 0 "gpc_reg_operand" "")
2906 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2907 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2908 "TARGET_POWER && reload_completed"
2909 [(set (match_dup 0)
2910 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2911 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2912 (set (match_dup 4)
2913 (compare:CC (match_dup 0)
2914 (const_int 0)))]
2915 "")
2916 \f
2917 ;; Rotate and shift insns, in all their variants. These support shifts,
2918 ;; field inserts and extracts, and various combinations thereof.
2919 (define_expand "insv"
2920 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2921 (match_operand:SI 1 "const_int_operand" "")
2922 (match_operand:SI 2 "const_int_operand" ""))
2923 (match_operand 3 "gpc_reg_operand" ""))]
2924 ""
2925 "
2926 {
2927 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2928 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2929 compiler if the address of the structure is taken later. */
2930 if (GET_CODE (operands[0]) == SUBREG
2931 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2932 FAIL;
2934 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2935 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2936 else
2937 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2938 DONE;
2939 }")
2941 (define_insn "insvsi"
2942 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2943 (match_operand:SI 1 "const_int_operand" "i")
2944 (match_operand:SI 2 "const_int_operand" "i"))
2945 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2946 ""
2947 "*
2948 {
2949 int start = INTVAL (operands[2]) & 31;
2950 int size = INTVAL (operands[1]) & 31;
2952 operands[4] = GEN_INT (32 - start - size);
2953 operands[1] = GEN_INT (start + size - 1);
2954 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2955 }"
2956 [(set_attr "type" "insert_word")])
2958 (define_insn "*insvsi_internal1"
2959 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2960 (match_operand:SI 1 "const_int_operand" "i")
2961 (match_operand:SI 2 "const_int_operand" "i"))
2962 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2963 (match_operand:SI 4 "const_int_operand" "i")))]
2964 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2965 "*
2966 {
2967 int shift = INTVAL (operands[4]) & 31;
2968 int start = INTVAL (operands[2]) & 31;
2969 int size = INTVAL (operands[1]) & 31;
2971 operands[4] = GEN_INT (shift - start - size);
2972 operands[1] = GEN_INT (start + size - 1);
2973 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2974 }"
2975 [(set_attr "type" "insert_word")])
2977 (define_insn "*insvsi_internal2"
2978 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2979 (match_operand:SI 1 "const_int_operand" "i")
2980 (match_operand:SI 2 "const_int_operand" "i"))
2981 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2982 (match_operand:SI 4 "const_int_operand" "i")))]
2983 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2984 "*
2985 {
2986 int shift = INTVAL (operands[4]) & 31;
2987 int start = INTVAL (operands[2]) & 31;
2988 int size = INTVAL (operands[1]) & 31;
2990 operands[4] = GEN_INT (32 - shift - start - size);
2991 operands[1] = GEN_INT (start + size - 1);
2992 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2993 }"
2994 [(set_attr "type" "insert_word")])
2996 (define_insn "*insvsi_internal3"
2997 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2998 (match_operand:SI 1 "const_int_operand" "i")
2999 (match_operand:SI 2 "const_int_operand" "i"))
3000 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3001 (match_operand:SI 4 "const_int_operand" "i")))]
3002 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3003 "*
3004 {
3005 int shift = INTVAL (operands[4]) & 31;
3006 int start = INTVAL (operands[2]) & 31;
3007 int size = INTVAL (operands[1]) & 31;
3009 operands[4] = GEN_INT (32 - shift - start - size);
3010 operands[1] = GEN_INT (start + size - 1);
3011 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3012 }"
3013 [(set_attr "type" "insert_word")])
3015 (define_insn "*insvsi_internal4"
3016 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3017 (match_operand:SI 1 "const_int_operand" "i")
3018 (match_operand:SI 2 "const_int_operand" "i"))
3019 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3020 (match_operand:SI 4 "const_int_operand" "i")
3021 (match_operand:SI 5 "const_int_operand" "i")))]
3022 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3023 "*
3024 {
3025 int extract_start = INTVAL (operands[5]) & 31;
3026 int extract_size = INTVAL (operands[4]) & 31;
3027 int insert_start = INTVAL (operands[2]) & 31;
3028 int insert_size = INTVAL (operands[1]) & 31;
3030 /* Align extract field with insert field */
3031 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3032 operands[1] = GEN_INT (insert_start + insert_size - 1);
3033 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3034 }"
3035 [(set_attr "type" "insert_word")])
3037 (define_insn "insvdi"
3038 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3039 (match_operand:SI 1 "const_int_operand" "i")
3040 (match_operand:SI 2 "const_int_operand" "i"))
3041 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3042 "TARGET_POWERPC64"
3043 "*
3044 {
3045 int start = INTVAL (operands[2]) & 63;
3046 int size = INTVAL (operands[1]) & 63;
3048 operands[1] = GEN_INT (64 - start - size);
3049 return \"rldimi %0,%3,%H1,%H2\";
3050 }")
3052 (define_expand "extzv"
3053 [(set (match_operand 0 "gpc_reg_operand" "")
3054 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3055 (match_operand:SI 2 "const_int_operand" "")
3056 (match_operand:SI 3 "const_int_operand" "")))]
3057 ""
3058 "
3059 {
3060 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3061 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3062 compiler if the address of the structure is taken later. */
3063 if (GET_CODE (operands[0]) == SUBREG
3064 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3065 FAIL;
3067 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3068 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3069 else
3070 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3071 DONE;
3072 }")
3074 (define_insn "extzvsi"
3075 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3076 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3077 (match_operand:SI 2 "const_int_operand" "i")
3078 (match_operand:SI 3 "const_int_operand" "i")))]
3079 ""
3080 "*
3081 {
3082 int start = INTVAL (operands[3]) & 31;
3083 int size = INTVAL (operands[2]) & 31;
3085 if (start + size >= 32)
3086 operands[3] = const0_rtx;
3087 else
3088 operands[3] = GEN_INT (start + size);
3089 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3090 }")
3092 (define_insn "*extzvsi_internal1"
3093 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3094 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3095 (match_operand:SI 2 "const_int_operand" "i,i")
3096 (match_operand:SI 3 "const_int_operand" "i,i"))
3097 (const_int 0)))
3098 (clobber (match_scratch:SI 4 "=r,r"))]
3099 ""
3100 "*
3101 {
3102 int start = INTVAL (operands[3]) & 31;
3103 int size = INTVAL (operands[2]) & 31;
3105 /* Force split for non-cc0 compare. */
3106 if (which_alternative == 1)
3107 return \"#\";
3109 /* If the bit-field being tested fits in the upper or lower half of a
3110 word, it is possible to use andiu. or andil. to test it. This is
3111 useful because the condition register set-use delay is smaller for
3112 andi[ul]. than for rlinm. This doesn't work when the starting bit
3113 position is 0 because the LT and GT bits may be set wrong. */
3115 if ((start > 0 && start + size <= 16) || start >= 16)
3116 {
3117 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3118 - (1 << (16 - (start & 15) - size))));
3119 if (start < 16)
3120 return \"{andiu.|andis.} %4,%1,%3\";
3121 else
3122 return \"{andil.|andi.} %4,%1,%3\";
3123 }
3125 if (start + size >= 32)
3126 operands[3] = const0_rtx;
3127 else
3128 operands[3] = GEN_INT (start + size);
3129 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3130 }"
3131 [(set_attr "type" "compare")
3132 (set_attr "length" "4,8")])
3134 (define_split
3135 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3136 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3137 (match_operand:SI 2 "const_int_operand" "")
3138 (match_operand:SI 3 "const_int_operand" ""))
3139 (const_int 0)))
3140 (clobber (match_scratch:SI 4 ""))]
3141 "reload_completed"
3142 [(set (match_dup 4)
3143 (zero_extract:SI (match_dup 1) (match_dup 2)
3144 (match_dup 3)))
3145 (set (match_dup 0)
3146 (compare:CC (match_dup 4)
3147 (const_int 0)))]
3148 "")
3150 (define_insn "*extzvsi_internal2"
3151 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3152 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3153 (match_operand:SI 2 "const_int_operand" "i,i")
3154 (match_operand:SI 3 "const_int_operand" "i,i"))
3155 (const_int 0)))
3156 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3157 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3158 ""
3159 "*
3160 {
3161 int start = INTVAL (operands[3]) & 31;
3162 int size = INTVAL (operands[2]) & 31;
3164 /* Force split for non-cc0 compare. */
3165 if (which_alternative == 1)
3166 return \"#\";
3168 /* Since we are using the output value, we can't ignore any need for
3169 a shift. The bit-field must end at the LSB. */
3170 if (start >= 16 && start + size == 32)
3171 {
3172 operands[3] = GEN_INT ((1 << size) - 1);
3173 return \"{andil.|andi.} %0,%1,%3\";
3174 }
3176 if (start + size >= 32)
3177 operands[3] = const0_rtx;
3178 else
3179 operands[3] = GEN_INT (start + size);
3180 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3181 }"
3182 [(set_attr "type" "compare")
3183 (set_attr "length" "4,8")])
3185 (define_split
3186 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3187 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3188 (match_operand:SI 2 "const_int_operand" "")
3189 (match_operand:SI 3 "const_int_operand" ""))
3190 (const_int 0)))
3191 (set (match_operand:SI 0 "gpc_reg_operand" "")
3192 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3193 "reload_completed"
3194 [(set (match_dup 0)
3195 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3196 (set (match_dup 4)
3197 (compare:CC (match_dup 0)
3198 (const_int 0)))]
3199 "")
3201 (define_insn "extzvdi"
3202 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3203 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3204 (match_operand:SI 2 "const_int_operand" "i")
3205 (match_operand:SI 3 "const_int_operand" "i")))]
3206 "TARGET_POWERPC64"
3207 "*
3208 {
3209 int start = INTVAL (operands[3]) & 63;
3210 int size = INTVAL (operands[2]) & 63;
3212 if (start + size >= 64)
3213 operands[3] = const0_rtx;
3214 else
3215 operands[3] = GEN_INT (start + size);
3216 operands[2] = GEN_INT (64 - size);
3217 return \"rldicl %0,%1,%3,%2\";
3218 }")
3220 (define_insn "*extzvdi_internal1"
3221 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3222 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3223 (match_operand:SI 2 "const_int_operand" "i")
3224 (match_operand:SI 3 "const_int_operand" "i"))
3225 (const_int 0)))
3226 (clobber (match_scratch:DI 4 "=r"))]
3227 "TARGET_64BIT"
3228 "*
3229 {
3230 int start = INTVAL (operands[3]) & 63;
3231 int size = INTVAL (operands[2]) & 63;
3233 if (start + size >= 64)
3234 operands[3] = const0_rtx;
3235 else
3236 operands[3] = GEN_INT (start + size);
3237 operands[2] = GEN_INT (64 - size);
3238 return \"rldicl. %4,%1,%3,%2\";
3239 }")
3241 (define_insn "*extzvdi_internal2"
3242 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3243 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3244 (match_operand:SI 2 "const_int_operand" "i")
3245 (match_operand:SI 3 "const_int_operand" "i"))
3246 (const_int 0)))
3247 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3248 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3249 "TARGET_64BIT"
3250 "*
3251 {
3252 int start = INTVAL (operands[3]) & 63;
3253 int size = INTVAL (operands[2]) & 63;
3255 if (start + size >= 64)
3256 operands[3] = const0_rtx;
3257 else
3258 operands[3] = GEN_INT (start + size);
3259 operands[2] = GEN_INT (64 - size);
3260 return \"rldicl. %0,%1,%3,%2\";
3261 }")
3263 (define_insn "rotlsi3"
3264 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3265 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3266 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3267 ""
3268 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3270 (define_insn "*rotlsi3_internal2"
3271 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3272 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3273 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3274 (const_int 0)))
3275 (clobber (match_scratch:SI 3 "=r,r"))]
3276 ""
3277 "@
3278 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3279 #"
3280 [(set_attr "type" "delayed_compare")
3281 (set_attr "length" "4,8")])
3283 (define_split
3284 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3285 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3286 (match_operand:SI 2 "reg_or_cint_operand" ""))
3287 (const_int 0)))
3288 (clobber (match_scratch:SI 3 ""))]
3289 "reload_completed"
3290 [(set (match_dup 3)
3291 (rotate:SI (match_dup 1) (match_dup 2)))
3292 (set (match_dup 0)
3293 (compare:CC (match_dup 3)
3294 (const_int 0)))]
3295 "")
3297 (define_insn "*rotlsi3_internal3"
3298 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3299 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3300 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3301 (const_int 0)))
3302 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3303 (rotate:SI (match_dup 1) (match_dup 2)))]
3304 ""
3305 "@
3306 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3307 #"
3308 [(set_attr "type" "delayed_compare")
3309 (set_attr "length" "4,8")])
3311 (define_split
3312 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3313 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3314 (match_operand:SI 2 "reg_or_cint_operand" ""))
3315 (const_int 0)))
3316 (set (match_operand:SI 0 "gpc_reg_operand" "")
3317 (rotate:SI (match_dup 1) (match_dup 2)))]
3318 "reload_completed"
3319 [(set (match_dup 0)
3320 (rotate:SI (match_dup 1) (match_dup 2)))
3321 (set (match_dup 3)
3322 (compare:CC (match_dup 0)
3323 (const_int 0)))]
3324 "")
3326 (define_insn "*rotlsi3_internal4"
3327 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3328 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3329 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3330 (match_operand:SI 3 "mask_operand" "n")))]
3331 ""
3332 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3334 (define_insn "*rotlsi3_internal5"
3335 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3336 (compare:CC (and:SI
3337 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3338 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3339 (match_operand:SI 3 "mask_operand" "n,n"))
3340 (const_int 0)))
3341 (clobber (match_scratch:SI 4 "=r,r"))]
3342 ""
3343 "@
3344 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3345 #"
3346 [(set_attr "type" "delayed_compare")
3347 (set_attr "length" "4,8")])
3349 (define_split
3350 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3351 (compare:CC (and:SI
3352 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3353 (match_operand:SI 2 "reg_or_cint_operand" ""))
3354 (match_operand:SI 3 "mask_operand" ""))
3355 (const_int 0)))
3356 (clobber (match_scratch:SI 4 ""))]
3357 "reload_completed"
3358 [(set (match_dup 4)
3359 (and:SI (rotate:SI (match_dup 1)
3360 (match_dup 2))
3361 (match_dup 3)))
3362 (set (match_dup 0)
3363 (compare:CC (match_dup 4)
3364 (const_int 0)))]
3365 "")
3367 (define_insn "*rotlsi3_internal6"
3368 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3369 (compare:CC (and:SI
3370 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3371 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3372 (match_operand:SI 3 "mask_operand" "n,n"))
3373 (const_int 0)))
3374 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3375 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3376 ""
3377 "@
3378 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3379 #"
3380 [(set_attr "type" "delayed_compare")
3381 (set_attr "length" "4,8")])
3383 (define_split
3384 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3385 (compare:CC (and:SI
3386 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3387 (match_operand:SI 2 "reg_or_cint_operand" ""))
3388 (match_operand:SI 3 "mask_operand" ""))
3389 (const_int 0)))
3390 (set (match_operand:SI 0 "gpc_reg_operand" "")
3391 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3392 "reload_completed"
3393 [(set (match_dup 0)
3394 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3395 (set (match_dup 4)
3396 (compare:CC (match_dup 0)
3397 (const_int 0)))]
3398 "")
3400 (define_insn "*rotlsi3_internal7"
3401 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3402 (zero_extend:SI
3403 (subreg:QI
3404 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3405 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3406 ""
3407 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3409 (define_insn "*rotlsi3_internal8"
3410 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3411 (compare:CC (zero_extend:SI
3412 (subreg:QI
3413 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3414 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3415 (const_int 0)))
3416 (clobber (match_scratch:SI 3 "=r,r"))]
3417 ""
3418 "@
3419 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3420 #"
3421 [(set_attr "type" "delayed_compare")
3422 (set_attr "length" "4,8")])
3424 (define_split
3425 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3426 (compare:CC (zero_extend:SI
3427 (subreg:QI
3428 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3429 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3430 (const_int 0)))
3431 (clobber (match_scratch:SI 3 ""))]
3432 "reload_completed"
3433 [(set (match_dup 3)
3434 (zero_extend:SI (subreg:QI
3435 (rotate:SI (match_dup 1)
3436 (match_dup 2)) 0)))
3437 (set (match_dup 0)
3438 (compare:CC (match_dup 3)
3439 (const_int 0)))]
3440 "")
3442 (define_insn "*rotlsi3_internal9"
3443 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3444 (compare:CC (zero_extend:SI
3445 (subreg:QI
3446 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3447 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3448 (const_int 0)))
3449 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3450 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3451 ""
3452 "@
3453 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3454 #"
3455 [(set_attr "type" "delayed_compare")
3456 (set_attr "length" "4,8")])
3458 (define_split
3459 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3460 (compare:CC (zero_extend:SI
3461 (subreg:QI
3462 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3463 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3464 (const_int 0)))
3465 (set (match_operand:SI 0 "gpc_reg_operand" "")
3466 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3467 "reload_completed"
3468 [(set (match_dup 0)
3469 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3470 (set (match_dup 3)
3471 (compare:CC (match_dup 0)
3472 (const_int 0)))]
3473 "")
3475 (define_insn "*rotlsi3_internal10"
3476 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3477 (zero_extend:SI
3478 (subreg:HI
3479 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3480 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3481 ""
3482 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3484 (define_insn "*rotlsi3_internal11"
3485 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3486 (compare:CC (zero_extend:SI
3487 (subreg:HI
3488 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3489 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3490 (const_int 0)))
3491 (clobber (match_scratch:SI 3 "=r,r"))]
3492 ""
3493 "@
3494 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3495 #"
3496 [(set_attr "type" "delayed_compare")
3497 (set_attr "length" "4,8")])
3499 (define_split
3500 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3501 (compare:CC (zero_extend:SI
3502 (subreg:HI
3503 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3504 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3505 (const_int 0)))
3506 (clobber (match_scratch:SI 3 ""))]
3507 "reload_completed"
3508 [(set (match_dup 3)
3509 (zero_extend:SI (subreg:HI
3510 (rotate:SI (match_dup 1)
3511 (match_dup 2)) 0)))
3512 (set (match_dup 0)
3513 (compare:CC (match_dup 3)
3514 (const_int 0)))]
3515 "")
3517 (define_insn "*rotlsi3_internal12"
3518 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3519 (compare:CC (zero_extend:SI
3520 (subreg:HI
3521 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3522 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3523 (const_int 0)))
3524 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3525 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3526 ""
3527 "@
3528 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3529 #"
3530 [(set_attr "type" "delayed_compare")
3531 (set_attr "length" "4,8")])
3533 (define_split
3534 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3535 (compare:CC (zero_extend:SI
3536 (subreg:HI
3537 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3538 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3539 (const_int 0)))
3540 (set (match_operand:SI 0 "gpc_reg_operand" "")
3541 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3542 "reload_completed"
3543 [(set (match_dup 0)
3544 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3545 (set (match_dup 3)
3546 (compare:CC (match_dup 0)
3547 (const_int 0)))]
3548 "")
3550 ;; Note that we use "sle." instead of "sl." so that we can set
3551 ;; SHIFT_COUNT_TRUNCATED.
3553 (define_expand "ashlsi3"
3554 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3555 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3556 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3557 ""
3558 "
3559 {
3560 if (TARGET_POWER)
3561 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3562 else
3563 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3564 DONE;
3565 }")
3567 (define_insn "ashlsi3_power"
3568 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3569 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3570 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3571 (clobber (match_scratch:SI 3 "=q,X"))]
3572 "TARGET_POWER"
3573 "@
3574 sle %0,%1,%2
3575 {sli|slwi} %0,%1,%h2")
3577 (define_insn "ashlsi3_no_power"
3578 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3579 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3580 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3581 "! TARGET_POWER"
3582 "{sl|slw}%I2 %0,%1,%h2")
3584 (define_insn ""
3585 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3586 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3587 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3588 (const_int 0)))
3589 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3590 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3591 "TARGET_POWER"
3592 "@
3593 sle. %3,%1,%2
3594 {sli.|slwi.} %3,%1,%h2
3595 #
3596 #"
3597 [(set_attr "type" "delayed_compare")
3598 (set_attr "length" "4,4,8,8")])
3600 (define_split
3601 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3602 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3603 (match_operand:SI 2 "reg_or_cint_operand" ""))
3604 (const_int 0)))
3605 (clobber (match_scratch:SI 3 ""))
3606 (clobber (match_scratch:SI 4 ""))]
3607 "TARGET_POWER && reload_completed"
3608 [(parallel [(set (match_dup 3)
3609 (ashift:SI (match_dup 1) (match_dup 2)))
3610 (clobber (match_dup 4))])
3611 (set (match_dup 0)
3612 (compare:CC (match_dup 3)
3613 (const_int 0)))]
3614 "")
3616 (define_insn ""
3617 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3618 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3619 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3620 (const_int 0)))
3621 (clobber (match_scratch:SI 3 "=r,r"))]
3622 "! TARGET_POWER && TARGET_32BIT"
3623 "@
3624 {sl|slw}%I2. %3,%1,%h2
3625 #"
3626 [(set_attr "type" "delayed_compare")
3627 (set_attr "length" "4,8")])
3629 (define_split
3630 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3631 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3632 (match_operand:SI 2 "reg_or_cint_operand" ""))
3633 (const_int 0)))
3634 (clobber (match_scratch:SI 3 ""))]
3635 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3636 [(set (match_dup 3)
3637 (ashift:SI (match_dup 1) (match_dup 2)))
3638 (set (match_dup 0)
3639 (compare:CC (match_dup 3)
3640 (const_int 0)))]
3641 "")
3643 (define_insn ""
3644 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3645 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3646 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3647 (const_int 0)))
3648 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3649 (ashift:SI (match_dup 1) (match_dup 2)))
3650 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3651 "TARGET_POWER"
3652 "@
3653 sle. %0,%1,%2
3654 {sli.|slwi.} %0,%1,%h2
3655 #
3656 #"
3657 [(set_attr "type" "delayed_compare")
3658 (set_attr "length" "4,4,8,8")])
3660 (define_split
3661 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3662 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3663 (match_operand:SI 2 "reg_or_cint_operand" ""))
3664 (const_int 0)))
3665 (set (match_operand:SI 0 "gpc_reg_operand" "")
3666 (ashift:SI (match_dup 1) (match_dup 2)))
3667 (clobber (match_scratch:SI 4 ""))]
3668 "TARGET_POWER && reload_completed"
3669 [(parallel [(set (match_dup 0)
3670 (ashift:SI (match_dup 1) (match_dup 2)))
3671 (clobber (match_dup 4))])
3672 (set (match_dup 3)
3673 (compare:CC (match_dup 0)
3674 (const_int 0)))]
3675 "")
3677 (define_insn ""
3678 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3679 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3680 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3681 (const_int 0)))
3682 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3683 (ashift:SI (match_dup 1) (match_dup 2)))]
3684 "! TARGET_POWER && TARGET_32BIT"
3685 "@
3686 {sl|slw}%I2. %0,%1,%h2
3687 #"
3688 [(set_attr "type" "delayed_compare")
3689 (set_attr "length" "4,8")])
3691 (define_split
3692 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3693 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3694 (match_operand:SI 2 "reg_or_cint_operand" ""))
3695 (const_int 0)))
3696 (set (match_operand:SI 0 "gpc_reg_operand" "")
3697 (ashift:SI (match_dup 1) (match_dup 2)))]
3698 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3699 [(set (match_dup 0)
3700 (ashift:SI (match_dup 1) (match_dup 2)))
3701 (set (match_dup 3)
3702 (compare:CC (match_dup 0)
3703 (const_int 0)))]
3704 "")
3706 (define_insn ""
3707 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3708 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3709 (match_operand:SI 2 "const_int_operand" "i"))
3710 (match_operand:SI 3 "mask_operand" "n")))]
3711 "includes_lshift_p (operands[2], operands[3])"
3712 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3714 (define_insn ""
3715 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3716 (compare:CC
3717 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3718 (match_operand:SI 2 "const_int_operand" "i,i"))
3719 (match_operand:SI 3 "mask_operand" "n,n"))
3720 (const_int 0)))
3721 (clobber (match_scratch:SI 4 "=r,r"))]
3722 "includes_lshift_p (operands[2], operands[3])"
3723 "@
3724 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3725 #"
3726 [(set_attr "type" "delayed_compare")
3727 (set_attr "length" "4,8")])
3729 (define_split
3730 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3731 (compare:CC
3732 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3733 (match_operand:SI 2 "const_int_operand" ""))
3734 (match_operand:SI 3 "mask_operand" ""))
3735 (const_int 0)))
3736 (clobber (match_scratch:SI 4 ""))]
3737 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3738 [(set (match_dup 4)
3739 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3740 (match_dup 3)))
3741 (set (match_dup 0)
3742 (compare:CC (match_dup 4)
3743 (const_int 0)))]
3744 "")
3746 (define_insn ""
3747 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3748 (compare:CC
3749 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3750 (match_operand:SI 2 "const_int_operand" "i,i"))
3751 (match_operand:SI 3 "mask_operand" "n,n"))
3752 (const_int 0)))
3753 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3754 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3755 "includes_lshift_p (operands[2], operands[3])"
3756 "@
3757 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3758 #"
3759 [(set_attr "type" "delayed_compare")
3760 (set_attr "length" "4,8")])
3762 (define_split
3763 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3764 (compare:CC
3765 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3766 (match_operand:SI 2 "const_int_operand" ""))
3767 (match_operand:SI 3 "mask_operand" ""))
3768 (const_int 0)))
3769 (set (match_operand:SI 0 "gpc_reg_operand" "")
3770 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3771 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3772 [(set (match_dup 0)
3773 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3774 (set (match_dup 4)
3775 (compare:CC (match_dup 0)
3776 (const_int 0)))]
3777 "")
3779 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3780 ;; "sli x,x,0".
3781 (define_expand "lshrsi3"
3782 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3783 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3784 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3785 ""
3786 "
3787 {
3788 if (TARGET_POWER)
3789 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3790 else
3791 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3792 DONE;
3793 }")
3795 (define_insn "lshrsi3_power"
3796 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3797 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3798 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3799 (clobber (match_scratch:SI 3 "=q,X,X"))]
3800 "TARGET_POWER"
3801 "@
3802 sre %0,%1,%2
3803 mr %0,%1
3804 {s%A2i|s%A2wi} %0,%1,%h2")
3806 (define_insn "lshrsi3_no_power"
3807 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3808 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3809 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3810 "! TARGET_POWER"
3811 "@
3812 mr %0,%1
3813 {sr|srw}%I2 %0,%1,%h2")
3815 (define_insn ""
3816 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3817 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3818 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3819 (const_int 0)))
3820 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3821 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3822 "TARGET_POWER"
3823 "@
3824 sre. %3,%1,%2
3825 mr. %1,%1
3826 {s%A2i.|s%A2wi.} %3,%1,%h2
3827 #
3828 #
3829 #"
3830 [(set_attr "type" "delayed_compare")
3831 (set_attr "length" "4,4,4,8,8,8")])
3833 (define_split
3834 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3835 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3836 (match_operand:SI 2 "reg_or_cint_operand" ""))
3837 (const_int 0)))
3838 (clobber (match_scratch:SI 3 ""))
3839 (clobber (match_scratch:SI 4 ""))]
3840 "TARGET_POWER && reload_completed"
3841 [(parallel [(set (match_dup 3)
3842 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3843 (clobber (match_dup 4))])
3844 (set (match_dup 0)
3845 (compare:CC (match_dup 3)
3846 (const_int 0)))]
3847 "")
3849 (define_insn ""
3850 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3851 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3852 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3853 (const_int 0)))
3854 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3855 "! TARGET_POWER && TARGET_32BIT"
3856 "@
3857 mr. %1,%1
3858 {sr|srw}%I2. %3,%1,%h2
3859 #
3860 #"
3861 [(set_attr "type" "delayed_compare")
3862 (set_attr "length" "4,4,8,8")])
3864 (define_split
3865 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3866 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3867 (match_operand:SI 2 "reg_or_cint_operand" ""))
3868 (const_int 0)))
3869 (clobber (match_scratch:SI 3 ""))]
3870 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3871 [(set (match_dup 3)
3872 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3873 (set (match_dup 0)
3874 (compare:CC (match_dup 3)
3875 (const_int 0)))]
3876 "")
3878 (define_insn ""
3879 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3880 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3881 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3882 (const_int 0)))
3883 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
3884 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3885 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3886 "TARGET_POWER"
3887 "@
3888 sre. %0,%1,%2
3889 mr. %0,%1
3890 {s%A2i.|s%A2wi.} %0,%1,%h2
3891 #
3892 #
3893 #"
3894 [(set_attr "type" "delayed_compare")
3895 (set_attr "length" "4,4,4,8,8,8")])
3897 (define_split
3898 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3899 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3900 (match_operand:SI 2 "reg_or_cint_operand" ""))
3901 (const_int 0)))
3902 (set (match_operand:SI 0 "gpc_reg_operand" "")
3903 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3904 (clobber (match_scratch:SI 4 ""))]
3905 "TARGET_POWER && reload_completed"
3906 [(parallel [(set (match_dup 0)
3907 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3908 (clobber (match_dup 4))])
3909 (set (match_dup 3)
3910 (compare:CC (match_dup 0)
3911 (const_int 0)))]
3912 "")
3914 (define_insn ""
3915 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3916 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3917 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3918 (const_int 0)))
3919 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3920 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3921 "! TARGET_POWER && TARGET_32BIT"
3922 "@
3923 mr. %0,%1
3924 {sr|srw}%I2. %0,%1,%h2
3925 #
3926 #"
3927 [(set_attr "type" "delayed_compare")
3928 (set_attr "length" "4,4,8,8")])
3930 (define_split
3931 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3932 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3933 (match_operand:SI 2 "reg_or_cint_operand" ""))
3934 (const_int 0)))
3935 (set (match_operand:SI 0 "gpc_reg_operand" "")
3936 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3937 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3938 [(set (match_dup 0)
3939 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3940 (set (match_dup 3)
3941 (compare:CC (match_dup 0)
3942 (const_int 0)))]
3943 "")
3945 (define_insn ""
3946 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3947 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3948 (match_operand:SI 2 "const_int_operand" "i"))
3949 (match_operand:SI 3 "mask_operand" "n")))]
3950 "includes_rshift_p (operands[2], operands[3])"
3951 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
3953 (define_insn ""
3954 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3955 (compare:CC
3956 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3957 (match_operand:SI 2 "const_int_operand" "i,i"))
3958 (match_operand:SI 3 "mask_operand" "n,n"))
3959 (const_int 0)))
3960 (clobber (match_scratch:SI 4 "=r,r"))]
3961 "includes_rshift_p (operands[2], operands[3])"
3962 "@
3963 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
3964 #"
3965 [(set_attr "type" "delayed_compare")
3966 (set_attr "length" "4,8")])
3968 (define_split
3969 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3970 (compare:CC
3971 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3972 (match_operand:SI 2 "const_int_operand" ""))
3973 (match_operand:SI 3 "mask_operand" ""))
3974 (const_int 0)))
3975 (clobber (match_scratch:SI 4 ""))]
3976 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
3977 [(set (match_dup 4)
3978 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
3979 (match_dup 3)))
3980 (set (match_dup 0)
3981 (compare:CC (match_dup 4)
3982 (const_int 0)))]
3983 "")
3985 (define_insn ""
3986 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3987 (compare:CC
3988 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3989 (match_operand:SI 2 "const_int_operand" "i,i"))
3990 (match_operand:SI 3 "mask_operand" "n,n"))
3991 (const_int 0)))
3992 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3993 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3994 "includes_rshift_p (operands[2], operands[3])"
3995 "@
3996 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
3997 #"
3998 [(set_attr "type" "delayed_compare")
3999 (set_attr "length" "4,8")])
4001 (define_split
4002 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4003 (compare:CC
4004 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4005 (match_operand:SI 2 "const_int_operand" ""))
4006 (match_operand:SI 3 "mask_operand" ""))
4007 (const_int 0)))
4008 (set (match_operand:SI 0 "gpc_reg_operand" "")
4009 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4010 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4011 [(set (match_dup 0)
4012 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4013 (set (match_dup 4)
4014 (compare:CC (match_dup 0)
4015 (const_int 0)))]
4016 "")
4018 (define_insn ""
4019 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4020 (zero_extend:SI
4021 (subreg:QI
4022 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4023 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4024 "includes_rshift_p (operands[2], GEN_INT (255))"
4025 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4027 (define_insn ""
4028 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4029 (compare:CC
4030 (zero_extend:SI
4031 (subreg:QI
4032 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4033 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4034 (const_int 0)))
4035 (clobber (match_scratch:SI 3 "=r,r"))]
4036 "includes_rshift_p (operands[2], GEN_INT (255))"
4037 "@
4038 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4039 #"
4040 [(set_attr "type" "delayed_compare")
4041 (set_attr "length" "4,8")])
4043 (define_split
4044 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4045 (compare:CC
4046 (zero_extend:SI
4047 (subreg:QI
4048 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4049 (match_operand:SI 2 "const_int_operand" "")) 0))
4050 (const_int 0)))
4051 (clobber (match_scratch:SI 3 ""))]
4052 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4053 [(set (match_dup 3)
4054 (zero_extend:SI (subreg:QI
4055 (lshiftrt:SI (match_dup 1)
4056 (match_dup 2)) 0)))
4057 (set (match_dup 0)
4058 (compare:CC (match_dup 3)
4059 (const_int 0)))]
4060 "")
4062 (define_insn ""
4063 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4064 (compare:CC
4065 (zero_extend:SI
4066 (subreg:QI
4067 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4068 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4069 (const_int 0)))
4070 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4071 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4072 "includes_rshift_p (operands[2], GEN_INT (255))"
4073 "@
4074 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4075 #"
4076 [(set_attr "type" "delayed_compare")
4077 (set_attr "length" "4,8")])
4079 (define_split
4080 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4081 (compare:CC
4082 (zero_extend:SI
4083 (subreg:QI
4084 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4085 (match_operand:SI 2 "const_int_operand" "")) 0))
4086 (const_int 0)))
4087 (set (match_operand:SI 0 "gpc_reg_operand" "")
4088 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4089 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4090 [(set (match_dup 0)
4091 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4092 (set (match_dup 3)
4093 (compare:CC (match_dup 0)
4094 (const_int 0)))]
4095 "")
4097 (define_insn ""
4098 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4099 (zero_extend:SI
4100 (subreg:HI
4101 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4102 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4103 "includes_rshift_p (operands[2], GEN_INT (65535))"
4104 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4106 (define_insn ""
4107 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4108 (compare:CC
4109 (zero_extend:SI
4110 (subreg:HI
4111 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4112 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4113 (const_int 0)))
4114 (clobber (match_scratch:SI 3 "=r,r"))]
4115 "includes_rshift_p (operands[2], GEN_INT (65535))"
4116 "@
4117 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4118 #"
4119 [(set_attr "type" "delayed_compare")
4120 (set_attr "length" "4,8")])
4122 (define_split
4123 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4124 (compare:CC
4125 (zero_extend:SI
4126 (subreg:HI
4127 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4128 (match_operand:SI 2 "const_int_operand" "")) 0))
4129 (const_int 0)))
4130 (clobber (match_scratch:SI 3 ""))]
4131 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4132 [(set (match_dup 3)
4133 (zero_extend:SI (subreg:HI
4134 (lshiftrt:SI (match_dup 1)
4135 (match_dup 2)) 0)))
4136 (set (match_dup 0)
4137 (compare:CC (match_dup 3)
4138 (const_int 0)))]
4139 "")
4141 (define_insn ""
4142 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4143 (compare:CC
4144 (zero_extend:SI
4145 (subreg:HI
4146 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4147 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4148 (const_int 0)))
4149 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4150 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4151 "includes_rshift_p (operands[2], GEN_INT (65535))"
4152 "@
4153 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4154 #"
4155 [(set_attr "type" "delayed_compare")
4156 (set_attr "length" "4,8")])
4158 (define_split
4159 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4160 (compare:CC
4161 (zero_extend:SI
4162 (subreg:HI
4163 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4164 (match_operand:SI 2 "const_int_operand" "")) 0))
4165 (const_int 0)))
4166 (set (match_operand:SI 0 "gpc_reg_operand" "")
4167 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4168 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4169 [(set (match_dup 0)
4170 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4171 (set (match_dup 3)
4172 (compare:CC (match_dup 0)
4173 (const_int 0)))]
4174 "")
4176 (define_insn ""
4177 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4178 (const_int 1)
4179 (match_operand:SI 1 "gpc_reg_operand" "r"))
4180 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4181 (const_int 31)))]
4182 "TARGET_POWER"
4183 "rrib %0,%1,%2")
4185 (define_insn ""
4186 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4187 (const_int 1)
4188 (match_operand:SI 1 "gpc_reg_operand" "r"))
4189 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4190 (const_int 31)))]
4191 "TARGET_POWER"
4192 "rrib %0,%1,%2")
4194 (define_insn ""
4195 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4196 (const_int 1)
4197 (match_operand:SI 1 "gpc_reg_operand" "r"))
4198 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4199 (const_int 1)
4200 (const_int 0)))]
4201 "TARGET_POWER"
4202 "rrib %0,%1,%2")
4204 (define_expand "ashrsi3"
4205 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4206 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4207 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4208 ""
4209 "
4210 {
4211 if (TARGET_POWER)
4212 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4213 else
4214 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4215 DONE;
4216 }")
4218 (define_insn "ashrsi3_power"
4219 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4220 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4221 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4222 (clobber (match_scratch:SI 3 "=q,X"))]
4223 "TARGET_POWER"
4224 "@
4225 srea %0,%1,%2
4226 {srai|srawi} %0,%1,%h2")
4228 (define_insn "ashrsi3_no_power"
4229 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4230 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4231 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4232 "! TARGET_POWER"
4233 "{sra|sraw}%I2 %0,%1,%h2")
4235 (define_insn ""
4236 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4237 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4238 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4239 (const_int 0)))
4240 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4241 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4242 "TARGET_POWER"
4243 "@
4244 srea. %3,%1,%2
4245 {srai.|srawi.} %3,%1,%h2
4246 #
4247 #"
4248 [(set_attr "type" "delayed_compare")
4249 (set_attr "length" "4,4,8,8")])
4251 (define_split
4252 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4253 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4254 (match_operand:SI 2 "reg_or_cint_operand" ""))
4255 (const_int 0)))
4256 (clobber (match_scratch:SI 3 ""))
4257 (clobber (match_scratch:SI 4 ""))]
4258 "TARGET_POWER && reload_completed"
4259 [(parallel [(set (match_dup 3)
4260 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4261 (clobber (match_dup 4))])
4262 (set (match_dup 0)
4263 (compare:CC (match_dup 3)
4264 (const_int 0)))]
4265 "")
4267 (define_insn ""
4268 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4269 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4270 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4271 (const_int 0)))
4272 (clobber (match_scratch:SI 3 "=r,r"))]
4273 "! TARGET_POWER"
4274 "@
4275 {sra|sraw}%I2. %3,%1,%h2
4276 #"
4277 [(set_attr "type" "delayed_compare")
4278 (set_attr "length" "4,8")])
4280 (define_split
4281 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4282 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4283 (match_operand:SI 2 "reg_or_cint_operand" ""))
4284 (const_int 0)))
4285 (clobber (match_scratch:SI 3 ""))]
4286 "! TARGET_POWER && reload_completed"
4287 [(set (match_dup 3)
4288 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4289 (set (match_dup 0)
4290 (compare:CC (match_dup 3)
4291 (const_int 0)))]
4292 "")
4294 (define_insn ""
4295 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4296 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4297 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4298 (const_int 0)))
4299 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4300 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4301 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4302 "TARGET_POWER"
4303 "@
4304 srea. %0,%1,%2
4305 {srai.|srawi.} %0,%1,%h2
4306 #
4307 #"
4308 [(set_attr "type" "delayed_compare")
4309 (set_attr "length" "4,4,8,8")])
4311 (define_split
4312 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4313 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4314 (match_operand:SI 2 "reg_or_cint_operand" ""))
4315 (const_int 0)))
4316 (set (match_operand:SI 0 "gpc_reg_operand" "")
4317 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4318 (clobber (match_scratch:SI 4 ""))]
4319 "TARGET_POWER && reload_completed"
4320 [(parallel [(set (match_dup 0)
4321 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4322 (clobber (match_dup 4))])
4323 (set (match_dup 3)
4324 (compare:CC (match_dup 0)
4325 (const_int 0)))]
4326 "")
4328 (define_insn ""
4329 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4330 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4331 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4332 (const_int 0)))
4333 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4334 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4335 "! TARGET_POWER"
4336 "@
4337 {sra|sraw}%I2. %0,%1,%h2
4338 #"
4339 [(set_attr "type" "delayed_compare")
4340 (set_attr "length" "4,8")])
4341 \f
4342 (define_split
4343 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4344 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4345 (match_operand:SI 2 "reg_or_cint_operand" ""))
4346 (const_int 0)))
4347 (set (match_operand:SI 0 "gpc_reg_operand" "")
4348 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4349 "! TARGET_POWER && reload_completed"
4350 [(set (match_dup 0)
4351 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4352 (set (match_dup 3)
4353 (compare:CC (match_dup 0)
4354 (const_int 0)))]
4355 "")
4357 ;; Floating-point insns, excluding normal data motion.
4358 ;;
4359 ;; PowerPC has a full set of single-precision floating point instructions.
4360 ;;
4361 ;; For the POWER architecture, we pretend that we have both SFmode and
4362 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4363 ;; The only conversions we will do will be when storing to memory. In that
4364 ;; case, we will use the "frsp" instruction before storing.
4365 ;;
4366 ;; Note that when we store into a single-precision memory location, we need to
4367 ;; use the frsp insn first. If the register being stored isn't dead, we
4368 ;; need a scratch register for the frsp. But this is difficult when the store
4369 ;; is done by reload. It is not incorrect to do the frsp on the register in
4370 ;; this case, we just lose precision that we would have otherwise gotten but
4371 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4373 (define_insn "extendsfdf2"
4374 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4375 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4376 "TARGET_HARD_FLOAT && TARGET_FPRS"
4377 "*
4378 {
4379 if (REGNO (operands[0]) == REGNO (operands[1]))
4380 return \"\";
4381 else
4382 return \"fmr %0,%1\";
4383 }"
4384 [(set_attr "type" "fp")])
4386 (define_insn "truncdfsf2"
4387 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4388 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4389 "TARGET_HARD_FLOAT && TARGET_FPRS"
4390 "frsp %0,%1"
4391 [(set_attr "type" "fp")])
4393 (define_insn "aux_truncdfsf2"
4394 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4395 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4396 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4397 "frsp %0,%1"
4398 [(set_attr "type" "fp")])
4400 (define_expand "negsf2"
4401 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4402 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4403 "TARGET_HARD_FLOAT"
4404 "")
4406 (define_insn "*negsf2"
4407 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4408 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4409 "TARGET_HARD_FLOAT && TARGET_FPRS"
4410 "fneg %0,%1"
4411 [(set_attr "type" "fp")])
4413 (define_expand "abssf2"
4414 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4415 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4416 "TARGET_HARD_FLOAT"
4417 "")
4419 (define_insn "*abssf2"
4420 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4421 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4422 "TARGET_HARD_FLOAT && TARGET_FPRS"
4423 "fabs %0,%1"
4424 [(set_attr "type" "fp")])
4426 (define_insn ""
4427 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4428 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4429 "TARGET_HARD_FLOAT && TARGET_FPRS"
4430 "fnabs %0,%1"
4431 [(set_attr "type" "fp")])
4433 (define_expand "addsf3"
4434 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4435 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4436 (match_operand:SF 2 "gpc_reg_operand" "")))]
4437 "TARGET_HARD_FLOAT"
4438 "")
4440 (define_insn ""
4441 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4442 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4443 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4444 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4445 "fadds %0,%1,%2"
4446 [(set_attr "type" "fp")])
4448 (define_insn ""
4449 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4450 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4451 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4452 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4453 "{fa|fadd} %0,%1,%2"
4454 [(set_attr "type" "fp")])
4456 (define_expand "subsf3"
4457 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4458 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4459 (match_operand:SF 2 "gpc_reg_operand" "")))]
4460 "TARGET_HARD_FLOAT"
4461 "")
4463 (define_insn ""
4464 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4465 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4466 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4467 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4468 "fsubs %0,%1,%2"
4469 [(set_attr "type" "fp")])
4471 (define_insn ""
4472 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4473 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4474 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4475 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4476 "{fs|fsub} %0,%1,%2"
4477 [(set_attr "type" "fp")])
4479 (define_expand "mulsf3"
4480 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4481 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4482 (match_operand:SF 2 "gpc_reg_operand" "")))]
4483 "TARGET_HARD_FLOAT"
4484 "")
4486 (define_insn ""
4487 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4488 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4489 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4490 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4491 "fmuls %0,%1,%2"
4492 [(set_attr "type" "fp")])
4494 (define_insn ""
4495 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4496 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4497 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4498 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4499 "{fm|fmul} %0,%1,%2"
4500 [(set_attr "type" "dmul")])
4502 (define_expand "divsf3"
4503 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4504 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4505 (match_operand:SF 2 "gpc_reg_operand" "")))]
4506 "TARGET_HARD_FLOAT"
4507 "")
4509 (define_insn ""
4510 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4511 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4512 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4513 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4514 "fdivs %0,%1,%2"
4515 [(set_attr "type" "sdiv")])
4517 (define_insn ""
4518 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4519 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4520 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4521 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4522 "{fd|fdiv} %0,%1,%2"
4523 [(set_attr "type" "ddiv")])
4525 (define_insn ""
4526 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4527 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4528 (match_operand:SF 2 "gpc_reg_operand" "f"))
4529 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4530 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4531 "fmadds %0,%1,%2,%3"
4532 [(set_attr "type" "fp")])
4534 (define_insn ""
4535 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4536 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4537 (match_operand:SF 2 "gpc_reg_operand" "f"))
4538 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4539 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4540 "{fma|fmadd} %0,%1,%2,%3"
4541 [(set_attr "type" "dmul")])
4543 (define_insn ""
4544 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4545 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4546 (match_operand:SF 2 "gpc_reg_operand" "f"))
4547 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4548 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4549 "fmsubs %0,%1,%2,%3"
4550 [(set_attr "type" "fp")])
4552 (define_insn ""
4553 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4554 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4555 (match_operand:SF 2 "gpc_reg_operand" "f"))
4556 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4557 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4558 "{fms|fmsub} %0,%1,%2,%3"
4559 [(set_attr "type" "dmul")])
4561 (define_insn ""
4562 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4563 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4564 (match_operand:SF 2 "gpc_reg_operand" "f"))
4565 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4566 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4567 && HONOR_SIGNED_ZEROS (SFmode)"
4568 "fnmadds %0,%1,%2,%3"
4569 [(set_attr "type" "fp")])
4571 (define_insn ""
4572 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4573 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4574 (match_operand:SF 2 "gpc_reg_operand" "f"))
4575 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4576 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4577 && ! HONOR_SIGNED_ZEROS (SFmode)"
4578 "fnmadds %0,%1,%2,%3"
4579 [(set_attr "type" "fp")])
4581 (define_insn ""
4582 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4583 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4584 (match_operand:SF 2 "gpc_reg_operand" "f"))
4585 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4586 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4587 "{fnma|fnmadd} %0,%1,%2,%3"
4588 [(set_attr "type" "dmul")])
4590 (define_insn ""
4591 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4592 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4593 (match_operand:SF 2 "gpc_reg_operand" "f"))
4594 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4595 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4596 && ! HONOR_SIGNED_ZEROS (SFmode)"
4597 "{fnma|fnmadd} %0,%1,%2,%3"
4598 [(set_attr "type" "dmul")])
4600 (define_insn ""
4601 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4602 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4603 (match_operand:SF 2 "gpc_reg_operand" "f"))
4604 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4605 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4606 && HONOR_SIGNED_ZEROS (SFmode)"
4607 "fnmsubs %0,%1,%2,%3"
4608 [(set_attr "type" "fp")])
4610 (define_insn ""
4611 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4612 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4613 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4614 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4615 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4616 && ! HONOR_SIGNED_ZEROS (SFmode)"
4617 "fnmsubs %0,%1,%2,%3"
4618 [(set_attr "type" "fp")])
4620 (define_insn ""
4621 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4622 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4623 (match_operand:SF 2 "gpc_reg_operand" "f"))
4624 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4625 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4626 "{fnms|fnmsub} %0,%1,%2,%3"
4627 [(set_attr "type" "dmul")])
4629 (define_insn ""
4630 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4631 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4632 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4633 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4634 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4635 && ! HONOR_SIGNED_ZEROS (SFmode)"
4636 "{fnms|fnmsub} %0,%1,%2,%3"
4637 [(set_attr "type" "fp")])
4639 (define_expand "sqrtsf2"
4640 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4641 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4642 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4643 "")
4645 (define_insn ""
4646 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4647 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4648 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4649 "fsqrts %0,%1"
4650 [(set_attr "type" "ssqrt")])
4652 (define_insn ""
4653 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4654 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4655 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4656 "fsqrt %0,%1"
4657 [(set_attr "type" "dsqrt")])
4659 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4660 ;; fsel instruction and some auxiliary computations. Then we just have a
4661 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4662 ;; combine.
4663 (define_expand "maxsf3"
4664 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4665 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4666 (match_operand:SF 2 "gpc_reg_operand" ""))
4667 (match_dup 1)
4668 (match_dup 2)))]
4669 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4670 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4672 (define_expand "minsf3"
4673 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4674 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4675 (match_operand:SF 2 "gpc_reg_operand" ""))
4676 (match_dup 2)
4677 (match_dup 1)))]
4678 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4679 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4681 (define_split
4682 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4683 (match_operator:SF 3 "min_max_operator"
4684 [(match_operand:SF 1 "gpc_reg_operand" "")
4685 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4686 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4687 [(const_int 0)]
4688 "
4689 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4690 operands[1], operands[2]);
4691 DONE;
4692 }")
4694 (define_expand "movsicc"
4695 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4696 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4697 (match_operand:SI 2 "gpc_reg_operand" "")
4698 (match_operand:SI 3 "gpc_reg_operand" "")))]
4699 "TARGET_ISEL"
4700 "
4701 {
4702 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4703 DONE;
4704 else
4705 FAIL;
4706 }")
4708 ;; We use the BASE_REGS for the isel input operands because, if rA is
4709 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4710 ;; because we may switch the operands and rB may end up being rA.
4711 ;;
4712 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4713 ;; leave out the mode in operand 4 and use one pattern, but reload can
4714 ;; change the mode underneath our feet and then gets confused trying
4715 ;; to reload the value.
4716 (define_insn "isel_signed"
4717 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4718 (if_then_else:SI
4719 (match_operator 1 "comparison_operator"
4720 [(match_operand:CC 4 "cc_reg_operand" "y")
4721 (const_int 0)])
4722 (match_operand:SI 2 "gpc_reg_operand" "b")
4723 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4724 "TARGET_ISEL"
4725 "*
4726 { return output_isel (operands); }"
4727 [(set_attr "length" "4")])
4729 (define_insn "isel_unsigned"
4730 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4731 (if_then_else:SI
4732 (match_operator 1 "comparison_operator"
4733 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4734 (const_int 0)])
4735 (match_operand:SI 2 "gpc_reg_operand" "b")
4736 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4737 "TARGET_ISEL"
4738 "*
4739 { return output_isel (operands); }"
4740 [(set_attr "length" "4")])
4742 (define_expand "movsfcc"
4743 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4744 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4745 (match_operand:SF 2 "gpc_reg_operand" "")
4746 (match_operand:SF 3 "gpc_reg_operand" "")))]
4747 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4748 "
4749 {
4750 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4751 DONE;
4752 else
4753 FAIL;
4754 }")
4756 (define_insn "*fselsfsf4"
4757 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4758 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4759 (match_operand:SF 4 "zero_fp_constant" "F"))
4760 (match_operand:SF 2 "gpc_reg_operand" "f")
4761 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4762 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4763 "fsel %0,%1,%2,%3"
4764 [(set_attr "type" "fp")])
4766 (define_insn "*fseldfsf4"
4767 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4768 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4769 (match_operand:DF 4 "zero_fp_constant" "F"))
4770 (match_operand:SF 2 "gpc_reg_operand" "f")
4771 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4772 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4773 "fsel %0,%1,%2,%3"
4774 [(set_attr "type" "fp")])
4776 (define_insn "negdf2"
4777 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4778 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4779 "TARGET_HARD_FLOAT && TARGET_FPRS"
4780 "fneg %0,%1"
4781 [(set_attr "type" "fp")])
4783 (define_insn "absdf2"
4784 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4785 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4786 "TARGET_HARD_FLOAT && TARGET_FPRS"
4787 "fabs %0,%1"
4788 [(set_attr "type" "fp")])
4790 (define_insn ""
4791 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4792 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4793 "TARGET_HARD_FLOAT && TARGET_FPRS"
4794 "fnabs %0,%1"
4795 [(set_attr "type" "fp")])
4797 (define_insn "adddf3"
4798 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4799 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4800 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4801 "TARGET_HARD_FLOAT && TARGET_FPRS"
4802 "{fa|fadd} %0,%1,%2"
4803 [(set_attr "type" "fp")])
4805 (define_insn "subdf3"
4806 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4807 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4808 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4809 "TARGET_HARD_FLOAT && TARGET_FPRS"
4810 "{fs|fsub} %0,%1,%2"
4811 [(set_attr "type" "fp")])
4813 (define_insn "muldf3"
4814 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4815 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4816 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4817 "TARGET_HARD_FLOAT && TARGET_FPRS"
4818 "{fm|fmul} %0,%1,%2"
4819 [(set_attr "type" "dmul")])
4821 (define_insn "divdf3"
4822 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4823 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4824 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4825 "TARGET_HARD_FLOAT && TARGET_FPRS"
4826 "{fd|fdiv} %0,%1,%2"
4827 [(set_attr "type" "ddiv")])
4829 (define_insn ""
4830 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4831 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4832 (match_operand:DF 2 "gpc_reg_operand" "f"))
4833 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4834 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4835 "{fma|fmadd} %0,%1,%2,%3"
4836 [(set_attr "type" "dmul")])
4838 (define_insn ""
4839 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4840 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4841 (match_operand:DF 2 "gpc_reg_operand" "f"))
4842 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4843 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4844 "{fms|fmsub} %0,%1,%2,%3"
4845 [(set_attr "type" "dmul")])
4847 (define_insn ""
4848 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4849 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4850 (match_operand:DF 2 "gpc_reg_operand" "f"))
4851 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4852 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4853 && HONOR_SIGNED_ZEROS (DFmode)"
4854 "{fnma|fnmadd} %0,%1,%2,%3"
4855 [(set_attr "type" "dmul")])
4857 (define_insn ""
4858 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4859 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
4860 (match_operand:DF 2 "gpc_reg_operand" "f"))
4861 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4862 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4863 && ! HONOR_SIGNED_ZEROS (DFmode)"
4864 "{fnma|fnmadd} %0,%1,%2,%3"
4865 [(set_attr "type" "dmul")])
4867 (define_insn ""
4868 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4869 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4870 (match_operand:DF 2 "gpc_reg_operand" "f"))
4871 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4872 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4873 && HONOR_SIGNED_ZEROS (DFmode)"
4874 "{fnms|fnmsub} %0,%1,%2,%3"
4875 [(set_attr "type" "dmul")])
4877 (define_insn ""
4878 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4879 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
4880 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4881 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
4882 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4883 && ! HONOR_SIGNED_ZEROS (DFmode)"
4884 "{fnms|fnmsub} %0,%1,%2,%3"
4885 [(set_attr "type" "dmul")])
4887 (define_insn "sqrtdf2"
4888 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4889 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4890 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4891 "fsqrt %0,%1"
4892 [(set_attr "type" "dsqrt")])
4894 ;; The conditional move instructions allow us to perform max and min
4895 ;; operations even when
4897 (define_expand "maxdf3"
4898 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4899 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4900 (match_operand:DF 2 "gpc_reg_operand" ""))
4901 (match_dup 1)
4902 (match_dup 2)))]
4903 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4904 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4906 (define_expand "mindf3"
4907 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4908 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4909 (match_operand:DF 2 "gpc_reg_operand" ""))
4910 (match_dup 2)
4911 (match_dup 1)))]
4912 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4913 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4915 (define_split
4916 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4917 (match_operator:DF 3 "min_max_operator"
4918 [(match_operand:DF 1 "gpc_reg_operand" "")
4919 (match_operand:DF 2 "gpc_reg_operand" "")]))]
4920 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4921 [(const_int 0)]
4922 "
4923 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4924 operands[1], operands[2]);
4925 DONE;
4926 }")
4928 (define_expand "movdfcc"
4929 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4930 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4931 (match_operand:DF 2 "gpc_reg_operand" "")
4932 (match_operand:DF 3 "gpc_reg_operand" "")))]
4933 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4934 "
4935 {
4936 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4937 DONE;
4938 else
4939 FAIL;
4940 }")
4942 (define_insn "*fseldfdf4"
4943 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4944 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4945 (match_operand:DF 4 "zero_fp_constant" "F"))
4946 (match_operand:DF 2 "gpc_reg_operand" "f")
4947 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4948 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4949 "fsel %0,%1,%2,%3"
4950 [(set_attr "type" "fp")])
4952 (define_insn "*fselsfdf4"
4953 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4954 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4955 (match_operand:SF 4 "zero_fp_constant" "F"))
4956 (match_operand:DF 2 "gpc_reg_operand" "f")
4957 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4958 "TARGET_PPC_GFXOPT"
4959 "fsel %0,%1,%2,%3"
4960 [(set_attr "type" "fp")])
4961 \f
4962 ;; Conversions to and from floating-point.
4964 (define_expand "fixuns_truncsfsi2"
4965 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4966 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
4967 "TARGET_HARD_FLOAT && !TARGET_FPRS"
4968 "")
4970 (define_expand "fix_truncsfsi2"
4971 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4972 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
4973 "TARGET_HARD_FLOAT && !TARGET_FPRS"
4974 "")
4976 ; For each of these conversions, there is a define_expand, a define_insn
4977 ; with a '#' template, and a define_split (with C code). The idea is
4978 ; to allow constant folding with the template of the define_insn,
4979 ; then to have the insns split later (between sched1 and final).
4981 (define_expand "floatsidf2"
4982 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
4983 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
4984 (use (match_dup 2))
4985 (use (match_dup 3))
4986 (clobber (match_dup 4))
4987 (clobber (match_dup 5))
4988 (clobber (match_dup 6))])]
4989 "TARGET_HARD_FLOAT && TARGET_FPRS"
4990 "
4991 {
4992 if (TARGET_POWERPC64)
4993 {
4994 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
4995 rtx t1 = gen_reg_rtx (DImode);
4996 rtx t2 = gen_reg_rtx (DImode);
4997 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
4998 DONE;
4999 }
5001 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5002 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5003 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5004 operands[5] = gen_reg_rtx (DFmode);
5005 operands[6] = gen_reg_rtx (SImode);
5006 }")
5008 (define_insn "*floatsidf2_internal"
5009 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5010 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5011 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5012 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5013 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5014 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5015 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5016 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5017 "#"
5018 [(set_attr "length" "24")])
5020 (define_split
5021 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5022 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5023 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5024 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5025 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5026 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5027 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5028 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5029 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5030 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5031 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5032 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5033 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5034 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5035 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5036 "
5037 {
5038 rtx lowword, highword;
5039 if (GET_CODE (operands[4]) != MEM)
5040 abort();
5041 highword = XEXP (operands[4], 0);
5042 lowword = plus_constant (highword, 4);
5043 if (! WORDS_BIG_ENDIAN)
5044 {
5045 rtx tmp;
5046 tmp = highword; highword = lowword; lowword = tmp;
5047 }
5049 emit_insn (gen_xorsi3 (operands[6], operands[1],
5050 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5051 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
5052 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5053 emit_move_insn (operands[5], operands[4]);
5054 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5055 DONE;
5056 }")
5058 (define_expand "floatunssisf2"
5059 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5060 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5061 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5062 "")
5064 (define_expand "floatunssidf2"
5065 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5066 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5067 (use (match_dup 2))
5068 (use (match_dup 3))
5069 (clobber (match_dup 4))
5070 (clobber (match_dup 5))])]
5071 "TARGET_HARD_FLOAT && TARGET_FPRS"
5072 "
5073 {
5074 if (TARGET_POWERPC64)
5075 {
5076 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5077 rtx t1 = gen_reg_rtx (DImode);
5078 rtx t2 = gen_reg_rtx (DImode);
5079 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5080 t1, t2));
5081 DONE;
5082 }
5084 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5085 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5086 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5087 operands[5] = gen_reg_rtx (DFmode);
5088 }")
5090 (define_insn "*floatunssidf2_internal"
5091 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5092 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5093 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5094 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5095 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5096 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5097 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5098 "#"
5099 [(set_attr "length" "20")])
5101 (define_split
5102 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5103 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5104 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5105 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5106 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5107 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5108 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5109 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5110 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5111 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5112 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5113 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5114 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5115 "
5116 {
5117 rtx lowword, highword;
5118 if (GET_CODE (operands[4]) != MEM)
5119 abort();
5120 highword = XEXP (operands[4], 0);
5121 lowword = plus_constant (highword, 4);
5122 if (! WORDS_BIG_ENDIAN)
5123 {
5124 rtx tmp;
5125 tmp = highword; highword = lowword; lowword = tmp;
5126 }
5128 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5129 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5130 emit_move_insn (operands[5], operands[4]);
5131 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5132 DONE;
5133 }")
5135 (define_expand "fix_truncdfsi2"
5136 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5137 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5138 (clobber (match_dup 2))
5139 (clobber (match_dup 3))])]
5140 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5141 "
5142 {
5143 operands[2] = gen_reg_rtx (DImode);
5144 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5145 }")
5147 (define_insn "*fix_truncdfsi2_internal"
5148 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5149 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5150 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5151 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5152 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5153 "#"
5154 [(set_attr "length" "16")])
5156 (define_split
5157 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5158 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5159 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5160 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5161 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5162 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5163 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5164 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5165 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5166 "
5167 {
5168 rtx lowword;
5169 if (GET_CODE (operands[3]) != MEM)
5170 abort();
5171 lowword = XEXP (operands[3], 0);
5172 if (WORDS_BIG_ENDIAN)
5173 lowword = plus_constant (lowword, 4);
5175 emit_insn (gen_fctiwz (operands[2], operands[1]));
5176 emit_move_insn (operands[3], operands[2]);
5177 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5178 DONE;
5179 }")
5181 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5182 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5183 ; because the first makes it clear that operand 0 is not live
5184 ; before the instruction.
5185 (define_insn "fctiwz"
5186 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5187 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5188 UNSPEC_FCTIWZ))]
5189 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5190 "{fcirz|fctiwz} %0,%1"
5191 [(set_attr "type" "fp")])
5193 (define_expand "floatsisf2"
5194 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5195 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5196 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5197 "")
5199 (define_insn "floatdidf2"
5200 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5201 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5202 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5203 "fcfid %0,%1"
5204 [(set_attr "type" "fp")])
5206 (define_insn_and_split "floatsidf_ppc64"
5207 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5208 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5209 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5210 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5211 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5212 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5213 "#"
5214 "&& 1"
5215 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5216 (set (match_dup 2) (match_dup 3))
5217 (set (match_dup 4) (match_dup 2))
5218 (set (match_dup 0) (float:DF (match_dup 4)))]
5219 "")
5221 (define_insn_and_split "floatunssidf_ppc64"
5222 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5223 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5224 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5225 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5226 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5227 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5228 "#"
5229 "&& 1"
5230 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5231 (set (match_dup 2) (match_dup 3))
5232 (set (match_dup 4) (match_dup 2))
5233 (set (match_dup 0) (float:DF (match_dup 4)))]
5234 "")
5236 (define_insn "fix_truncdfdi2"
5237 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5238 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5239 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5240 "fctidz %0,%1"
5241 [(set_attr "type" "fp")])
5243 (define_expand "floatdisf2"
5244 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5245 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5246 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS"
5247 "
5248 {
5249 if (!flag_unsafe_math_optimizations)
5250 {
5251 rtx label = gen_label_rtx ();
5252 emit_insn (gen_floatdisf2_internal2 (operands[1], label));
5253 emit_label (label);
5254 }
5255 emit_insn (gen_floatdisf2_internal1 (operands[0], operands[1]));
5256 DONE;
5257 }")
5259 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5260 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5261 ;; from double rounding.
5262 (define_insn_and_split "floatdisf2_internal1"
5263 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5264 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5265 (clobber (match_scratch:DF 2 "=f"))]
5266 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5267 "#"
5268 "&& reload_completed"
5269 [(set (match_dup 2)
5270 (float:DF (match_dup 1)))
5271 (set (match_dup 0)
5272 (float_truncate:SF (match_dup 2)))]
5273 "")
5275 ;; Twiddles bits to avoid double rounding.
5276 ;; Bits that might be truncated when converting to DFmode are replaced
5277 ;; by a bit that won't be lost at that stage, but is below the SFmode
5278 ;; rounding position.
5279 (define_expand "floatdisf2_internal2"
5280 [(parallel [(set (match_dup 4)
5281 (compare:CC (and:DI (match_operand:DI 0 "" "")
5282 (const_int 2047))
5283 (const_int 0)))
5284 (set (match_dup 2) (and:DI (match_dup 0) (const_int 2047)))
5285 (clobber (match_scratch:CC 7 ""))])
5286 (set (match_dup 3) (ashiftrt:DI (match_dup 0) (const_int 53)))
5287 (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1)))
5288 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
5289 (label_ref (match_operand:DI 1 "" ""))
5290 (pc)))
5291 (set (match_dup 5) (compare:CCUNS (match_dup 3) (const_int 2)))
5292 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
5293 (label_ref (match_dup 1))
5294 (pc)))
5295 (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 2)))
5296 (set (match_dup 0) (ior:DI (match_dup 0) (const_int 2048)))]
5297 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS"
5298 "
5299 {
5300 operands[2] = gen_reg_rtx (DImode);
5301 operands[3] = gen_reg_rtx (DImode);
5302 operands[4] = gen_reg_rtx (CCmode);
5303 operands[5] = gen_reg_rtx (CCUNSmode);
5304 }")
5305 \f
5306 ;; Define the DImode operations that can be done in a small number
5307 ;; of instructions. The & constraints are to prevent the register
5308 ;; allocator from allocating registers that overlap with the inputs
5309 ;; (for example, having an input in 7,8 and an output in 6,7). We
5310 ;; also allow for the output being the same as one of the inputs.
5312 (define_insn "*adddi3_noppc64"
5313 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5314 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5315 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5316 "! TARGET_POWERPC64"
5317 "*
5318 {
5319 if (WORDS_BIG_ENDIAN)
5320 return (GET_CODE (operands[2])) != CONST_INT
5321 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5322 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5323 else
5324 return (GET_CODE (operands[2])) != CONST_INT
5325 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5326 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5327 }"
5328 [(set_attr "length" "8")])
5330 (define_insn "*subdi3_noppc64"
5331 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5332 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5333 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5334 "! TARGET_POWERPC64"
5335 "*
5336 {
5337 if (WORDS_BIG_ENDIAN)
5338 return (GET_CODE (operands[1]) != CONST_INT)
5339 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5340 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5341 else
5342 return (GET_CODE (operands[1]) != CONST_INT)
5343 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5344 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5345 }"
5346 [(set_attr "length" "8")])
5348 (define_insn "*negdi2_noppc64"
5349 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5350 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5351 "! TARGET_POWERPC64"
5352 "*
5353 {
5354 return (WORDS_BIG_ENDIAN)
5355 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5356 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5357 }"
5358 [(set_attr "length" "8")])
5360 (define_expand "mulsidi3"
5361 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5362 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5363 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5364 "! TARGET_POWERPC64"
5365 "
5366 {
5367 if (! TARGET_POWER && ! TARGET_POWERPC)
5368 {
5369 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5370 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5371 emit_insn (gen_mull_call ());
5372 if (WORDS_BIG_ENDIAN)
5373 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5374 else
5375 {
5376 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5377 gen_rtx_REG (SImode, 3));
5378 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5379 gen_rtx_REG (SImode, 4));
5380 }
5381 DONE;
5382 }
5383 else if (TARGET_POWER)
5384 {
5385 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5386 DONE;
5387 }
5388 }")
5390 (define_insn "mulsidi3_mq"
5391 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5392 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5393 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5394 (clobber (match_scratch:SI 3 "=q"))]
5395 "TARGET_POWER"
5396 "mul %0,%1,%2\;mfmq %L0"
5397 [(set_attr "type" "imul")
5398 (set_attr "length" "8")])
5400 (define_insn "*mulsidi3_no_mq"
5401 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5402 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5403 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5404 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5405 "*
5406 {
5407 return (WORDS_BIG_ENDIAN)
5408 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5409 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5410 }"
5411 [(set_attr "type" "imul")
5412 (set_attr "length" "8")])
5414 (define_split
5415 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5416 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5417 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5418 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5419 [(set (match_dup 3)
5420 (truncate:SI
5421 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5422 (sign_extend:DI (match_dup 2)))
5423 (const_int 32))))
5424 (set (match_dup 4)
5425 (mult:SI (match_dup 1)
5426 (match_dup 2)))]
5427 "
5428 {
5429 int endian = (WORDS_BIG_ENDIAN == 0);
5430 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5431 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5432 }")
5434 (define_expand "umulsidi3"
5435 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5436 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5437 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5438 "TARGET_POWERPC && ! TARGET_POWERPC64"
5439 "
5440 {
5441 if (TARGET_POWER)
5442 {
5443 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5444 DONE;
5445 }
5446 }")
5448 (define_insn "umulsidi3_mq"
5449 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5450 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5451 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5452 (clobber (match_scratch:SI 3 "=q"))]
5453 "TARGET_POWERPC && TARGET_POWER"
5454 "*
5455 {
5456 return (WORDS_BIG_ENDIAN)
5457 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5458 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5459 }"
5460 [(set_attr "type" "imul")
5461 (set_attr "length" "8")])
5463 (define_insn "*umulsidi3_no_mq"
5464 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5465 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5466 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5467 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5468 "*
5469 {
5470 return (WORDS_BIG_ENDIAN)
5471 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5472 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5473 }"
5474 [(set_attr "type" "imul")
5475 (set_attr "length" "8")])
5477 (define_split
5478 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5479 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5480 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5481 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5482 [(set (match_dup 3)
5483 (truncate:SI
5484 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5485 (zero_extend:DI (match_dup 2)))
5486 (const_int 32))))
5487 (set (match_dup 4)
5488 (mult:SI (match_dup 1)
5489 (match_dup 2)))]
5490 "
5491 {
5492 int endian = (WORDS_BIG_ENDIAN == 0);
5493 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5494 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5495 }")
5497 (define_expand "smulsi3_highpart"
5498 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5499 (truncate:SI
5500 (lshiftrt:DI (mult:DI (sign_extend:DI
5501 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5502 (sign_extend:DI
5503 (match_operand:SI 2 "gpc_reg_operand" "r")))
5504 (const_int 32))))]
5505 ""
5506 "
5507 {
5508 if (! TARGET_POWER && ! TARGET_POWERPC)
5509 {
5510 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5511 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5512 emit_insn (gen_mulh_call ());
5513 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5514 DONE;
5515 }
5516 else if (TARGET_POWER)
5517 {
5518 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5519 DONE;
5520 }
5521 }")
5523 (define_insn "smulsi3_highpart_mq"
5524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5525 (truncate:SI
5526 (lshiftrt:DI (mult:DI (sign_extend:DI
5527 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5528 (sign_extend:DI
5529 (match_operand:SI 2 "gpc_reg_operand" "r")))
5530 (const_int 32))))
5531 (clobber (match_scratch:SI 3 "=q"))]
5532 "TARGET_POWER"
5533 "mul %0,%1,%2"
5534 [(set_attr "type" "imul")])
5536 (define_insn "*smulsi3_highpart_no_mq"
5537 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5538 (truncate:SI
5539 (lshiftrt:DI (mult:DI (sign_extend:DI
5540 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5541 (sign_extend:DI
5542 (match_operand:SI 2 "gpc_reg_operand" "r")))
5543 (const_int 32))))]
5544 "TARGET_POWERPC && ! TARGET_POWER"
5545 "mulhw %0,%1,%2"
5546 [(set_attr "type" "imul")])
5548 (define_expand "umulsi3_highpart"
5549 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5550 (truncate:SI
5551 (lshiftrt:DI (mult:DI (zero_extend:DI
5552 (match_operand:SI 1 "gpc_reg_operand" ""))
5553 (zero_extend:DI
5554 (match_operand:SI 2 "gpc_reg_operand" "")))
5555 (const_int 32))))]
5556 "TARGET_POWERPC"
5557 "
5558 {
5559 if (TARGET_POWER)
5560 {
5561 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5562 DONE;
5563 }
5564 }")
5566 (define_insn "umulsi3_highpart_mq"
5567 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5568 (truncate:SI
5569 (lshiftrt:DI (mult:DI (zero_extend:DI
5570 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5571 (zero_extend:DI
5572 (match_operand:SI 2 "gpc_reg_operand" "r")))
5573 (const_int 32))))
5574 (clobber (match_scratch:SI 3 "=q"))]
5575 "TARGET_POWERPC && TARGET_POWER"
5576 "mulhwu %0,%1,%2"
5577 [(set_attr "type" "imul")])
5579 (define_insn "*umulsi3_highpart_no_mq"
5580 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5581 (truncate:SI
5582 (lshiftrt:DI (mult:DI (zero_extend:DI
5583 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5584 (zero_extend:DI
5585 (match_operand:SI 2 "gpc_reg_operand" "r")))
5586 (const_int 32))))]
5587 "TARGET_POWERPC && ! TARGET_POWER"
5588 "mulhwu %0,%1,%2"
5589 [(set_attr "type" "imul")])
5591 ;; If operands 0 and 2 are in the same register, we have a problem. But
5592 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5593 ;; why we have the strange constraints below.
5594 (define_insn "ashldi3_power"
5595 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5596 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5597 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5598 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5599 "TARGET_POWER"
5600 "@
5601 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5602 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5603 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5604 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5605 [(set_attr "length" "8")])
5607 (define_insn "lshrdi3_power"
5608 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5609 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5610 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5611 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5612 "TARGET_POWER"
5613 "@
5614 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5615 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5616 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5617 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5618 [(set_attr "length" "8")])
5620 ;; Shift by a variable amount is too complex to be worth open-coding. We
5621 ;; just handle shifts by constants.
5622 (define_insn "ashrdi3_power"
5623 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5624 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5625 (match_operand:SI 2 "const_int_operand" "M,i")))
5626 (clobber (match_scratch:SI 3 "=X,q"))]
5627 "TARGET_POWER"
5628 "@
5629 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5630 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5631 [(set_attr "length" "8")])
5633 (define_insn "ashrdi3_no_power"
5634 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5635 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5636 (match_operand:SI 2 "const_int_operand" "M,i")))]
5637 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER"
5638 "@
5639 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5640 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5641 [(set_attr "length" "8,12")])
5643 (define_insn "*ashrdisi3_noppc64"
5644 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5645 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5646 (const_int 32)) 4))]
5647 "TARGET_32BIT && !TARGET_POWERPC64"
5648 "*
5649 {
5650 if (REGNO (operands[0]) == REGNO (operands[1]))
5651 return \"\";
5652 else
5653 return \"mr %0,%1\";
5654 }"
5655 [(set_attr "length" "4")])
5657 \f
5658 ;; PowerPC64 DImode operations.
5660 (define_expand "adddi3"
5661 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5662 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5663 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
5664 ""
5665 "
5666 {
5667 if (! TARGET_POWERPC64)
5668 {
5669 if (non_short_cint_operand (operands[2], DImode))
5670 FAIL;
5671 }
5672 else
5673 if (GET_CODE (operands[2]) == CONST_INT
5674 && ! add_operand (operands[2], DImode))
5675 {
5676 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
5677 ? operands[0] : gen_reg_rtx (DImode));
5679 HOST_WIDE_INT val = INTVAL (operands[2]);
5680 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5681 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5683 if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
5684 FAIL;
5686 /* The ordering here is important for the prolog expander.
5687 When space is allocated from the stack, adding 'low' first may
5688 produce a temporary deallocation (which would be bad). */
5689 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
5690 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
5691 DONE;
5692 }
5693 }")
5695 ;; Discourage ai/addic because of carry but provide it in an alternative
5696 ;; allowing register zero as source.
5698 (define_insn "*adddi3_internal1"
5699 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
5700 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
5701 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
5702 "TARGET_POWERPC64"
5703 "@
5704 add %0,%1,%2
5705 addi %0,%1,%2
5706 addic %0,%1,%2
5707 addis %0,%1,%v2")
5709 (define_insn "*adddi3_internal2"
5710 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5711 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5712 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5713 (const_int 0)))
5714 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
5715 "TARGET_64BIT"
5716 "@
5717 add. %3,%1,%2
5718 addic. %3,%1,%2
5719 #
5720 #"
5721 [(set_attr "type" "fast_compare,compare,compare,compare")
5722 (set_attr "length" "4,4,8,8")])
5724 (define_split
5725 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5726 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5727 (match_operand:DI 2 "reg_or_short_operand" ""))
5728 (const_int 0)))
5729 (clobber (match_scratch:DI 3 ""))]
5730 "TARGET_POWERPC64 && reload_completed"
5731 [(set (match_dup 3)
5732 (plus:DI (match_dup 1) (match_dup 2)))
5733 (set (match_dup 0)
5734 (compare:CC (match_dup 3)
5735 (const_int 0)))]
5736 "")
5738 (define_insn "*adddi3_internal3"
5739 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5740 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5741 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5742 (const_int 0)))
5743 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5744 (plus:DI (match_dup 1) (match_dup 2)))]
5745 "TARGET_64BIT"
5746 "@
5747 add. %0,%1,%2
5748 addic. %0,%1,%2
5749 #
5750 #"
5751 [(set_attr "type" "fast_compare,compare,compare,compare")
5752 (set_attr "length" "4,4,8,8")])
5754 (define_split
5755 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5756 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5757 (match_operand:DI 2 "reg_or_short_operand" ""))
5758 (const_int 0)))
5759 (set (match_operand:DI 0 "gpc_reg_operand" "")
5760 (plus:DI (match_dup 1) (match_dup 2)))]
5761 "TARGET_POWERPC64 && reload_completed"
5762 [(set (match_dup 0)
5763 (plus:DI (match_dup 1) (match_dup 2)))
5764 (set (match_dup 3)
5765 (compare:CC (match_dup 0)
5766 (const_int 0)))]
5767 "")
5769 ;; Split an add that we can't do in one insn into two insns, each of which
5770 ;; does one 16-bit part. This is used by combine. Note that the low-order
5771 ;; add should be last in case the result gets used in an address.
5773 (define_split
5774 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5775 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5776 (match_operand:DI 2 "non_add_cint_operand" "")))]
5777 "TARGET_POWERPC64"
5778 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
5779 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5780 "
5781 {
5782 HOST_WIDE_INT val = INTVAL (operands[2]);
5783 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5784 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5786 operands[4] = GEN_INT (low);
5787 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
5788 operands[3] = GEN_INT (rest);
5789 else if (! no_new_pseudos)
5790 {
5791 operands[3] = gen_reg_rtx (DImode);
5792 emit_move_insn (operands[3], operands[2]);
5793 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
5794 DONE;
5795 }
5796 else
5797 FAIL;
5798 }")
5800 (define_insn "one_cmpldi2"
5801 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5802 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5803 "TARGET_POWERPC64"
5804 "nor %0,%1,%1")
5806 (define_insn ""
5807 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5808 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5809 (const_int 0)))
5810 (clobber (match_scratch:DI 2 "=r,r"))]
5811 "TARGET_64BIT"
5812 "@
5813 nor. %2,%1,%1
5814 #"
5815 [(set_attr "type" "compare")
5816 (set_attr "length" "4,8")])
5818 (define_split
5819 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5820 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5821 (const_int 0)))
5822 (clobber (match_scratch:DI 2 ""))]
5823 "TARGET_POWERPC64 && reload_completed"
5824 [(set (match_dup 2)
5825 (not:DI (match_dup 1)))
5826 (set (match_dup 0)
5827 (compare:CC (match_dup 2)
5828 (const_int 0)))]
5829 "")
5831 (define_insn ""
5832 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5833 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5834 (const_int 0)))
5835 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5836 (not:DI (match_dup 1)))]
5837 "TARGET_64BIT"
5838 "@
5839 nor. %0,%1,%1
5840 #"
5841 [(set_attr "type" "compare")
5842 (set_attr "length" "4,8")])
5844 (define_split
5845 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5846 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5847 (const_int 0)))
5848 (set (match_operand:DI 0 "gpc_reg_operand" "")
5849 (not:DI (match_dup 1)))]
5850 "TARGET_POWERPC64 && reload_completed"
5851 [(set (match_dup 0)
5852 (not:DI (match_dup 1)))
5853 (set (match_dup 2)
5854 (compare:CC (match_dup 0)
5855 (const_int 0)))]
5856 "")
5858 (define_insn ""
5859 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5860 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
5861 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
5862 "TARGET_POWERPC64"
5863 "@
5864 subf %0,%2,%1
5865 subfic %0,%2,%1")
5867 (define_insn ""
5868 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5869 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5870 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5871 (const_int 0)))
5872 (clobber (match_scratch:DI 3 "=r,r"))]
5873 "TARGET_64BIT"
5874 "@
5875 subf. %3,%2,%1
5876 #"
5877 [(set_attr "type" "fast_compare")
5878 (set_attr "length" "4,8")])
5880 (define_split
5881 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5882 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5883 (match_operand:DI 2 "gpc_reg_operand" ""))
5884 (const_int 0)))
5885 (clobber (match_scratch:DI 3 ""))]
5886 "TARGET_POWERPC64 && reload_completed"
5887 [(set (match_dup 3)
5888 (minus:DI (match_dup 1) (match_dup 2)))
5889 (set (match_dup 0)
5890 (compare:CC (match_dup 3)
5891 (const_int 0)))]
5892 "")
5894 (define_insn ""
5895 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5896 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5897 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5898 (const_int 0)))
5899 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5900 (minus:DI (match_dup 1) (match_dup 2)))]
5901 "TARGET_64BIT"
5902 "@
5903 subf. %0,%2,%1
5904 #"
5905 [(set_attr "type" "fast_compare")
5906 (set_attr "length" "4,8")])
5908 (define_split
5909 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5910 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5911 (match_operand:DI 2 "gpc_reg_operand" ""))
5912 (const_int 0)))
5913 (set (match_operand:DI 0 "gpc_reg_operand" "")
5914 (minus:DI (match_dup 1) (match_dup 2)))]
5915 "TARGET_POWERPC64 && reload_completed"
5916 [(set (match_dup 0)
5917 (minus:DI (match_dup 1) (match_dup 2)))
5918 (set (match_dup 3)
5919 (compare:CC (match_dup 0)
5920 (const_int 0)))]
5921 "")
5923 (define_expand "subdi3"
5924 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5925 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
5926 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
5927 ""
5928 "
5929 {
5930 if (GET_CODE (operands[2]) == CONST_INT)
5931 {
5932 emit_insn (gen_adddi3 (operands[0], operands[1],
5933 negate_rtx (DImode, operands[2])));
5934 DONE;
5935 }
5936 }")
5938 (define_insn_and_split "absdi2"
5939 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5940 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5941 (clobber (match_scratch:DI 2 "=&r,&r"))]
5942 "TARGET_POWERPC64"
5943 "#"
5944 "&& reload_completed"
5945 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5946 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5947 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
5948 "")
5950 (define_insn_and_split "*nabsdi2"
5951 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5952 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5953 (clobber (match_scratch:DI 2 "=&r,&r"))]
5954 "TARGET_POWERPC64"
5955 "#"
5956 "&& reload_completed"
5957 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5958 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5959 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
5960 "")
5962 (define_expand "negdi2"
5963 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5964 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
5965 ""
5966 "")
5968 (define_insn ""
5969 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5970 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5971 "TARGET_POWERPC64"
5972 "neg %0,%1")
5974 (define_insn ""
5975 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5976 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5977 (const_int 0)))
5978 (clobber (match_scratch:DI 2 "=r,r"))]
5979 "TARGET_64BIT"
5980 "@
5981 neg. %2,%1
5982 #"
5983 [(set_attr "type" "fast_compare")
5984 (set_attr "length" "4,8")])
5986 (define_split
5987 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5988 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5989 (const_int 0)))
5990 (clobber (match_scratch:DI 2 ""))]
5991 "TARGET_POWERPC64 && reload_completed"
5992 [(set (match_dup 2)
5993 (neg:DI (match_dup 1)))
5994 (set (match_dup 0)
5995 (compare:CC (match_dup 2)
5996 (const_int 0)))]
5997 "")
5999 (define_insn ""
6000 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
6001 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6002 (const_int 0)))
6003 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6004 (neg:DI (match_dup 1)))]
6005 "TARGET_64BIT"
6006 "@
6007 neg. %0,%1
6008 #"
6009 [(set_attr "type" "fast_compare")
6010 (set_attr "length" "4,8")])
6012 (define_split
6013 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
6014 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6015 (const_int 0)))
6016 (set (match_operand:DI 0 "gpc_reg_operand" "")
6017 (neg:DI (match_dup 1)))]
6018 "TARGET_POWERPC64 && reload_completed"
6019 [(set (match_dup 0)
6020 (neg:DI (match_dup 1)))
6021 (set (match_dup 2)
6022 (compare:CC (match_dup 0)
6023 (const_int 0)))]
6024 "")
6026 (define_insn "clzdi2"
6027 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6028 (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6029 "TARGET_POWERPC64"
6030 "cntlzd %0,%1")
6032 (define_expand "ctzdi2"
6033 [(set (match_dup 2)
6034 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6035 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6036 (match_dup 2)))
6037 (clobber (scratch:CC))])
6038 (set (match_dup 4) (clz:DI (match_dup 3)))
6039 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6040 (minus:DI (const_int 63) (match_dup 4)))]
6041 "TARGET_POWERPC64"
6042 {
6043 operands[2] = gen_reg_rtx (DImode);
6044 operands[3] = gen_reg_rtx (DImode);
6045 operands[4] = gen_reg_rtx (DImode);
6046 })
6048 (define_expand "ffsdi2"
6049 [(set (match_dup 2)
6050 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6051 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6052 (match_dup 2)))
6053 (clobber (scratch:CC))])
6054 (set (match_dup 4) (clz:DI (match_dup 3)))
6055 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6056 (minus:DI (const_int 64) (match_dup 4)))]
6057 "TARGET_POWERPC64"
6058 {
6059 operands[2] = gen_reg_rtx (DImode);
6060 operands[3] = gen_reg_rtx (DImode);
6061 operands[4] = gen_reg_rtx (DImode);
6062 })
6064 (define_insn "muldi3"
6065 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6066 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6067 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6068 "TARGET_POWERPC64"
6069 "mulld %0,%1,%2"
6070 [(set_attr "type" "lmul")])
6072 (define_insn "*muldi3_internal1"
6073 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6074 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6075 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6076 (const_int 0)))
6077 (clobber (match_scratch:DI 3 "=r,r"))]
6078 "TARGET_POWERPC64"
6079 "@
6080 mulld. %3,%1,%2
6081 #"
6082 [(set_attr "type" "lmul_compare")
6083 (set_attr "length" "4,8")])
6085 (define_split
6086 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6087 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6088 (match_operand:DI 2 "gpc_reg_operand" ""))
6089 (const_int 0)))
6090 (clobber (match_scratch:DI 3 ""))]
6091 "TARGET_POWERPC64 && reload_completed"
6092 [(set (match_dup 3)
6093 (mult:DI (match_dup 1) (match_dup 2)))
6094 (set (match_dup 0)
6095 (compare:CC (match_dup 3)
6096 (const_int 0)))]
6097 "")
6099 (define_insn "*muldi3_internal2"
6100 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6101 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6102 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6103 (const_int 0)))
6104 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6105 (mult:DI (match_dup 1) (match_dup 2)))]
6106 "TARGET_POWERPC64"
6107 "@
6108 mulld. %0,%1,%2
6109 #"
6110 [(set_attr "type" "lmul_compare")
6111 (set_attr "length" "4,8")])
6113 (define_split
6114 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6115 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6116 (match_operand:DI 2 "gpc_reg_operand" ""))
6117 (const_int 0)))
6118 (set (match_operand:DI 0 "gpc_reg_operand" "")
6119 (mult:DI (match_dup 1) (match_dup 2)))]
6120 "TARGET_POWERPC64 && reload_completed"
6121 [(set (match_dup 0)
6122 (mult:DI (match_dup 1) (match_dup 2)))
6123 (set (match_dup 3)
6124 (compare:CC (match_dup 0)
6125 (const_int 0)))]
6126 "")
6128 (define_insn "smuldi3_highpart"
6129 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6130 (truncate:DI
6131 (lshiftrt:TI (mult:TI (sign_extend:TI
6132 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6133 (sign_extend:TI
6134 (match_operand:DI 2 "gpc_reg_operand" "r")))
6135 (const_int 64))))]
6136 "TARGET_POWERPC64"
6137 "mulhd %0,%1,%2"
6138 [(set_attr "type" "lmul")])
6140 (define_insn "umuldi3_highpart"
6141 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6142 (truncate:DI
6143 (lshiftrt:TI (mult:TI (zero_extend:TI
6144 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6145 (zero_extend:TI
6146 (match_operand:DI 2 "gpc_reg_operand" "r")))
6147 (const_int 64))))]
6148 "TARGET_POWERPC64"
6149 "mulhdu %0,%1,%2"
6150 [(set_attr "type" "lmul")])
6152 (define_expand "divdi3"
6153 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6154 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6155 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6156 "TARGET_POWERPC64"
6157 "
6158 {
6159 if (GET_CODE (operands[2]) == CONST_INT
6160 && INTVAL (operands[2]) > 0
6161 && exact_log2 (INTVAL (operands[2])) >= 0)
6162 ;
6163 else
6164 operands[2] = force_reg (DImode, operands[2]);
6165 }")
6167 (define_expand "moddi3"
6168 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6169 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6170 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6171 "TARGET_POWERPC64"
6172 "
6173 {
6174 int i;
6175 rtx temp1;
6176 rtx temp2;
6178 if (GET_CODE (operands[2]) != CONST_INT
6179 || INTVAL (operands[2]) <= 0
6180 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
6181 FAIL;
6183 temp1 = gen_reg_rtx (DImode);
6184 temp2 = gen_reg_rtx (DImode);
6186 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6187 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6188 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6189 DONE;
6190 }")
6192 (define_insn ""
6193 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6194 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6195 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6196 "TARGET_POWERPC64"
6197 "sradi %0,%1,%p2\;addze %0,%0"
6198 [(set_attr "length" "8")])
6200 (define_insn ""
6201 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6202 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6203 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6204 (const_int 0)))
6205 (clobber (match_scratch:DI 3 "=r,r"))]
6206 "TARGET_64BIT"
6207 "@
6208 sradi %3,%1,%p2\;addze. %3,%3
6209 #"
6210 [(set_attr "type" "compare")
6211 (set_attr "length" "8,12")])
6213 (define_split
6214 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6215 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6216 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6217 (const_int 0)))
6218 (clobber (match_scratch:DI 3 ""))]
6219 "TARGET_POWERPC64 && reload_completed"
6220 [(set (match_dup 3)
6221 (div:DI (match_dup 1) (match_dup 2)))
6222 (set (match_dup 0)
6223 (compare:CC (match_dup 3)
6224 (const_int 0)))]
6225 "")
6227 (define_insn ""
6228 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6229 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6230 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6231 (const_int 0)))
6232 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6233 (div:DI (match_dup 1) (match_dup 2)))]
6234 "TARGET_64BIT"
6235 "@
6236 sradi %0,%1,%p2\;addze. %0,%0
6237 #"
6238 [(set_attr "type" "compare")
6239 (set_attr "length" "8,12")])
6241 (define_split
6242 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6243 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6244 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6245 (const_int 0)))
6246 (set (match_operand:DI 0 "gpc_reg_operand" "")
6247 (div:DI (match_dup 1) (match_dup 2)))]
6248 "TARGET_POWERPC64 && reload_completed"
6249 [(set (match_dup 0)
6250 (div:DI (match_dup 1) (match_dup 2)))
6251 (set (match_dup 3)
6252 (compare:CC (match_dup 0)
6253 (const_int 0)))]
6254 "")
6256 (define_insn ""
6257 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6258 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6259 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6260 "TARGET_POWERPC64"
6261 "divd %0,%1,%2"
6262 [(set_attr "type" "ldiv")])
6264 (define_insn "udivdi3"
6265 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6266 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6267 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6268 "TARGET_POWERPC64"
6269 "divdu %0,%1,%2"
6270 [(set_attr "type" "ldiv")])
6272 (define_insn "rotldi3"
6273 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6274 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6275 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6276 "TARGET_POWERPC64"
6277 "rld%I2cl %0,%1,%H2,0")
6279 (define_insn "*rotldi3_internal2"
6280 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6281 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6282 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6283 (const_int 0)))
6284 (clobber (match_scratch:DI 3 "=r,r"))]
6285 "TARGET_64BIT"
6286 "@
6287 rld%I2cl. %3,%1,%H2,0
6288 #"
6289 [(set_attr "type" "delayed_compare")
6290 (set_attr "length" "4,8")])
6292 (define_split
6293 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6294 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6295 (match_operand:DI 2 "reg_or_cint_operand" ""))
6296 (const_int 0)))
6297 (clobber (match_scratch:DI 3 ""))]
6298 "TARGET_POWERPC64 && reload_completed"
6299 [(set (match_dup 3)
6300 (rotate:DI (match_dup 1) (match_dup 2)))
6301 (set (match_dup 0)
6302 (compare:CC (match_dup 3)
6303 (const_int 0)))]
6304 "")
6306 (define_insn "*rotldi3_internal3"
6307 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6308 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6309 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6310 (const_int 0)))
6311 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6312 (rotate:DI (match_dup 1) (match_dup 2)))]
6313 "TARGET_64BIT"
6314 "@
6315 rld%I2cl. %0,%1,%H2,0
6316 #"
6317 [(set_attr "type" "delayed_compare")
6318 (set_attr "length" "4,8")])
6320 (define_split
6321 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6322 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6323 (match_operand:DI 2 "reg_or_cint_operand" ""))
6324 (const_int 0)))
6325 (set (match_operand:DI 0 "gpc_reg_operand" "")
6326 (rotate:DI (match_dup 1) (match_dup 2)))]
6327 "TARGET_POWERPC64 && reload_completed"
6328 [(set (match_dup 0)
6329 (rotate:DI (match_dup 1) (match_dup 2)))
6330 (set (match_dup 3)
6331 (compare:CC (match_dup 0)
6332 (const_int 0)))]
6333 "")
6335 (define_insn "*rotldi3_internal4"
6336 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6337 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6338 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6339 (match_operand:DI 3 "mask64_operand" "n")))]
6340 "TARGET_POWERPC64"
6341 "rld%I2c%B3 %0,%1,%H2,%S3")
6343 (define_insn "*rotldi3_internal5"
6344 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6345 (compare:CC (and:DI
6346 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6347 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6348 (match_operand:DI 3 "mask64_operand" "n,n"))
6349 (const_int 0)))
6350 (clobber (match_scratch:DI 4 "=r,r"))]
6351 "TARGET_64BIT"
6352 "@
6353 rld%I2c%B3. %4,%1,%H2,%S3
6354 #"
6355 [(set_attr "type" "delayed_compare")
6356 (set_attr "length" "4,8")])
6358 (define_split
6359 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6360 (compare:CC (and:DI
6361 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6362 (match_operand:DI 2 "reg_or_cint_operand" ""))
6363 (match_operand:DI 3 "mask64_operand" ""))
6364 (const_int 0)))
6365 (clobber (match_scratch:DI 4 ""))]
6366 "TARGET_POWERPC64 && reload_completed"
6367 [(set (match_dup 4)
6368 (and:DI (rotate:DI (match_dup 1)
6369 (match_dup 2))
6370 (match_dup 3)))
6371 (set (match_dup 0)
6372 (compare:CC (match_dup 4)
6373 (const_int 0)))]
6374 "")
6376 (define_insn "*rotldi3_internal6"
6377 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6378 (compare:CC (and:DI
6379 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6380 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6381 (match_operand:DI 3 "mask64_operand" "n,n"))
6382 (const_int 0)))
6383 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6384 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6385 "TARGET_64BIT"
6386 "@
6387 rld%I2c%B3. %0,%1,%H2,%S3
6388 #"
6389 [(set_attr "type" "delayed_compare")
6390 (set_attr "length" "4,8")])
6392 (define_split
6393 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6394 (compare:CC (and:DI
6395 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6396 (match_operand:DI 2 "reg_or_cint_operand" ""))
6397 (match_operand:DI 3 "mask64_operand" ""))
6398 (const_int 0)))
6399 (set (match_operand:DI 0 "gpc_reg_operand" "")
6400 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6401 "TARGET_POWERPC64 && reload_completed"
6402 [(set (match_dup 0)
6403 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6404 (set (match_dup 4)
6405 (compare:CC (match_dup 0)
6406 (const_int 0)))]
6407 "")
6409 (define_insn "*rotldi3_internal7"
6410 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6411 (zero_extend:DI
6412 (subreg:QI
6413 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6414 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6415 "TARGET_POWERPC64"
6416 "rld%I2cl %0,%1,%H2,56")
6418 (define_insn "*rotldi3_internal8"
6419 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6420 (compare:CC (zero_extend:DI
6421 (subreg:QI
6422 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6423 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6424 (const_int 0)))
6425 (clobber (match_scratch:DI 3 "=r,r"))]
6426 "TARGET_64BIT"
6427 "@
6428 rld%I2cl. %3,%1,%H2,56
6429 #"
6430 [(set_attr "type" "delayed_compare")
6431 (set_attr "length" "4,8")])
6433 (define_split
6434 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6435 (compare:CC (zero_extend:DI
6436 (subreg:QI
6437 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6438 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6439 (const_int 0)))
6440 (clobber (match_scratch:DI 3 ""))]
6441 "TARGET_POWERPC64 && reload_completed"
6442 [(set (match_dup 3)
6443 (zero_extend:DI (subreg:QI
6444 (rotate:DI (match_dup 1)
6445 (match_dup 2)) 0)))
6446 (set (match_dup 0)
6447 (compare:CC (match_dup 3)
6448 (const_int 0)))]
6449 "")
6451 (define_insn "*rotldi3_internal9"
6452 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6453 (compare:CC (zero_extend:DI
6454 (subreg:QI
6455 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6456 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6457 (const_int 0)))
6458 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6459 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6460 "TARGET_64BIT"
6461 "@
6462 rld%I2cl. %0,%1,%H2,56
6463 #"
6464 [(set_attr "type" "delayed_compare")
6465 (set_attr "length" "4,8")])
6467 (define_split
6468 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6469 (compare:CC (zero_extend:DI
6470 (subreg:QI
6471 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6472 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6473 (const_int 0)))
6474 (set (match_operand:DI 0 "gpc_reg_operand" "")
6475 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6476 "TARGET_POWERPC64 && reload_completed"
6477 [(set (match_dup 0)
6478 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6479 (set (match_dup 3)
6480 (compare:CC (match_dup 0)
6481 (const_int 0)))]
6482 "")
6484 (define_insn "*rotldi3_internal10"
6485 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6486 (zero_extend:DI
6487 (subreg:HI
6488 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6489 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6490 "TARGET_POWERPC64"
6491 "rld%I2cl %0,%1,%H2,48")
6493 (define_insn "*rotldi3_internal11"
6494 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6495 (compare:CC (zero_extend:DI
6496 (subreg:HI
6497 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6498 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6499 (const_int 0)))
6500 (clobber (match_scratch:DI 3 "=r,r"))]
6501 "TARGET_64BIT"
6502 "@
6503 rld%I2cl. %3,%1,%H2,48
6504 #"
6505 [(set_attr "type" "delayed_compare")
6506 (set_attr "length" "4,8")])
6508 (define_split
6509 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6510 (compare:CC (zero_extend:DI
6511 (subreg:HI
6512 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6513 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6514 (const_int 0)))
6515 (clobber (match_scratch:DI 3 ""))]
6516 "TARGET_POWERPC64 && reload_completed"
6517 [(set (match_dup 3)
6518 (zero_extend:DI (subreg:HI
6519 (rotate:DI (match_dup 1)
6520 (match_dup 2)) 0)))
6521 (set (match_dup 0)
6522 (compare:CC (match_dup 3)
6523 (const_int 0)))]
6524 "")
6526 (define_insn "*rotldi3_internal12"
6527 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6528 (compare:CC (zero_extend:DI
6529 (subreg:HI
6530 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6531 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6532 (const_int 0)))
6533 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6534 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6535 "TARGET_64BIT"
6536 "@
6537 rld%I2cl. %0,%1,%H2,48
6538 #"
6539 [(set_attr "type" "delayed_compare")
6540 (set_attr "length" "4,8")])
6542 (define_split
6543 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6544 (compare:CC (zero_extend:DI
6545 (subreg:HI
6546 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6547 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6548 (const_int 0)))
6549 (set (match_operand:DI 0 "gpc_reg_operand" "")
6550 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6551 "TARGET_POWERPC64 && reload_completed"
6552 [(set (match_dup 0)
6553 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6554 (set (match_dup 3)
6555 (compare:CC (match_dup 0)
6556 (const_int 0)))]
6557 "")
6559 (define_insn "*rotldi3_internal13"
6560 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6561 (zero_extend:DI
6562 (subreg:SI
6563 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6564 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6565 "TARGET_POWERPC64"
6566 "rld%I2cl %0,%1,%H2,32")
6568 (define_insn "*rotldi3_internal14"
6569 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6570 (compare:CC (zero_extend:DI
6571 (subreg:SI
6572 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6573 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6574 (const_int 0)))
6575 (clobber (match_scratch:DI 3 "=r,r"))]
6576 "TARGET_64BIT"
6577 "@
6578 rld%I2cl. %3,%1,%H2,32
6579 #"
6580 [(set_attr "type" "delayed_compare")
6581 (set_attr "length" "4,8")])
6583 (define_split
6584 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6585 (compare:CC (zero_extend:DI
6586 (subreg:SI
6587 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6588 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6589 (const_int 0)))
6590 (clobber (match_scratch:DI 3 ""))]
6591 "TARGET_POWERPC64 && reload_completed"
6592 [(set (match_dup 3)
6593 (zero_extend:DI (subreg:SI
6594 (rotate:DI (match_dup 1)
6595 (match_dup 2)) 0)))
6596 (set (match_dup 0)
6597 (compare:CC (match_dup 3)
6598 (const_int 0)))]
6599 "")
6601 (define_insn "*rotldi3_internal15"
6602 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6603 (compare:CC (zero_extend:DI
6604 (subreg:SI
6605 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6606 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6607 (const_int 0)))
6608 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6609 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6610 "TARGET_64BIT"
6611 "@
6612 rld%I2cl. %0,%1,%H2,32
6613 #"
6614 [(set_attr "type" "delayed_compare")
6615 (set_attr "length" "4,8")])
6617 (define_split
6618 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6619 (compare:CC (zero_extend:DI
6620 (subreg:SI
6621 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6622 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6623 (const_int 0)))
6624 (set (match_operand:DI 0 "gpc_reg_operand" "")
6625 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6626 "TARGET_POWERPC64 && reload_completed"
6627 [(set (match_dup 0)
6628 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6629 (set (match_dup 3)
6630 (compare:CC (match_dup 0)
6631 (const_int 0)))]
6632 "")
6634 (define_expand "ashldi3"
6635 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6636 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6637 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6638 "TARGET_POWERPC64 || TARGET_POWER"
6639 "
6640 {
6641 if (TARGET_POWERPC64)
6642 ;
6643 else if (TARGET_POWER)
6644 {
6645 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6646 DONE;
6647 }
6648 else
6649 FAIL;
6650 }")
6652 (define_insn "*ashldi3_internal1"
6653 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6654 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6655 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6656 "TARGET_POWERPC64"
6657 "sld%I2 %0,%1,%H2"
6658 [(set_attr "length" "8")])
6660 (define_insn "*ashldi3_internal2"
6661 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6662 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6663 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6664 (const_int 0)))
6665 (clobber (match_scratch:DI 3 "=r,r"))]
6666 "TARGET_64BIT"
6667 "@
6668 sld%I2. %3,%1,%H2
6669 #"
6670 [(set_attr "type" "delayed_compare")
6671 (set_attr "length" "4,8")])
6673 (define_split
6674 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6675 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6676 (match_operand:SI 2 "reg_or_cint_operand" ""))
6677 (const_int 0)))
6678 (clobber (match_scratch:DI 3 ""))]
6679 "TARGET_POWERPC64 && reload_completed"
6680 [(set (match_dup 3)
6681 (ashift:DI (match_dup 1) (match_dup 2)))
6682 (set (match_dup 0)
6683 (compare:CC (match_dup 3)
6684 (const_int 0)))]
6685 "")
6687 (define_insn "*ashldi3_internal3"
6688 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6689 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6690 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6691 (const_int 0)))
6692 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6693 (ashift:DI (match_dup 1) (match_dup 2)))]
6694 "TARGET_64BIT"
6695 "@
6696 sld%I2. %0,%1,%H2
6697 #"
6698 [(set_attr "type" "delayed_compare")
6699 (set_attr "length" "4,8")])
6701 (define_split
6702 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6703 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6704 (match_operand:SI 2 "reg_or_cint_operand" ""))
6705 (const_int 0)))
6706 (set (match_operand:DI 0 "gpc_reg_operand" "")
6707 (ashift:DI (match_dup 1) (match_dup 2)))]
6708 "TARGET_POWERPC64 && reload_completed"
6709 [(set (match_dup 0)
6710 (ashift:DI (match_dup 1) (match_dup 2)))
6711 (set (match_dup 3)
6712 (compare:CC (match_dup 0)
6713 (const_int 0)))]
6714 "")
6716 (define_insn "*ashldi3_internal4"
6717 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6718 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6719 (match_operand:SI 2 "const_int_operand" "i"))
6720 (match_operand:DI 3 "const_int_operand" "n")))]
6721 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6722 "rldic %0,%1,%H2,%W3")
6724 (define_insn "ashldi3_internal5"
6725 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6726 (compare:CC
6727 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6728 (match_operand:SI 2 "const_int_operand" "i,i"))
6729 (match_operand:DI 3 "const_int_operand" "n,n"))
6730 (const_int 0)))
6731 (clobber (match_scratch:DI 4 "=r,r"))]
6732 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6733 "@
6734 rldic. %4,%1,%H2,%W3
6735 #"
6736 [(set_attr "type" "delayed_compare")
6737 (set_attr "length" "4,8")])
6739 (define_split
6740 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6741 (compare:CC
6742 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6743 (match_operand:SI 2 "const_int_operand" ""))
6744 (match_operand:DI 3 "const_int_operand" ""))
6745 (const_int 0)))
6746 (clobber (match_scratch:DI 4 ""))]
6747 "TARGET_POWERPC64 && reload_completed
6748 && includes_rldic_lshift_p (operands[2], operands[3])"
6749 [(set (match_dup 4)
6750 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6751 (match_dup 3)))
6752 (set (match_dup 0)
6753 (compare:CC (match_dup 4)
6754 (const_int 0)))]
6755 "")
6757 (define_insn "*ashldi3_internal6"
6758 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6759 (compare:CC
6760 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6761 (match_operand:SI 2 "const_int_operand" "i,i"))
6762 (match_operand:DI 3 "const_int_operand" "n,n"))
6763 (const_int 0)))
6764 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6765 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6766 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6767 "@
6768 rldic. %0,%1,%H2,%W3
6769 #"
6770 [(set_attr "type" "delayed_compare")
6771 (set_attr "length" "4,8")])
6773 (define_split
6774 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6775 (compare:CC
6776 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6777 (match_operand:SI 2 "const_int_operand" ""))
6778 (match_operand:DI 3 "const_int_operand" ""))
6779 (const_int 0)))
6780 (set (match_operand:DI 0 "gpc_reg_operand" "")
6781 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6782 "TARGET_POWERPC64 && reload_completed
6783 && includes_rldic_lshift_p (operands[2], operands[3])"
6784 [(set (match_dup 0)
6785 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6786 (match_dup 3)))
6787 (set (match_dup 4)
6788 (compare:CC (match_dup 0)
6789 (const_int 0)))]
6790 "")
6792 (define_insn "*ashldi3_internal7"
6793 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6794 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6795 (match_operand:SI 2 "const_int_operand" "i"))
6796 (match_operand:DI 3 "mask64_operand" "n")))]
6797 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6798 "rldicr %0,%1,%H2,%S3")
6800 (define_insn "ashldi3_internal8"
6801 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6802 (compare:CC
6803 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6804 (match_operand:SI 2 "const_int_operand" "i,i"))
6805 (match_operand:DI 3 "mask64_operand" "n,n"))
6806 (const_int 0)))
6807 (clobber (match_scratch:DI 4 "=r,r"))]
6808 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6809 "@
6810 rldicr. %4,%1,%H2,%S3
6811 #"
6812 [(set_attr "type" "delayed_compare")
6813 (set_attr "length" "4,8")])
6815 (define_split
6816 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6817 (compare:CC
6818 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6819 (match_operand:SI 2 "const_int_operand" ""))
6820 (match_operand:DI 3 "mask64_operand" ""))
6821 (const_int 0)))
6822 (clobber (match_scratch:DI 4 ""))]
6823 "TARGET_POWERPC64 && reload_completed
6824 && includes_rldicr_lshift_p (operands[2], operands[3])"
6825 [(set (match_dup 4)
6826 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6827 (match_dup 3)))
6828 (set (match_dup 0)
6829 (compare:CC (match_dup 4)
6830 (const_int 0)))]
6831 "")
6833 (define_insn "*ashldi3_internal9"
6834 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6835 (compare:CC
6836 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6837 (match_operand:SI 2 "const_int_operand" "i,i"))
6838 (match_operand:DI 3 "mask64_operand" "n,n"))
6839 (const_int 0)))
6840 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6841 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6842 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6843 "@
6844 rldicr. %0,%1,%H2,%S3
6845 #"
6846 [(set_attr "type" "delayed_compare")
6847 (set_attr "length" "4,8")])
6849 (define_split
6850 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6851 (compare:CC
6852 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6853 (match_operand:SI 2 "const_int_operand" ""))
6854 (match_operand:DI 3 "mask64_operand" ""))
6855 (const_int 0)))
6856 (set (match_operand:DI 0 "gpc_reg_operand" "")
6857 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6858 "TARGET_POWERPC64 && reload_completed
6859 && includes_rldicr_lshift_p (operands[2], operands[3])"
6860 [(set (match_dup 0)
6861 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6862 (match_dup 3)))
6863 (set (match_dup 4)
6864 (compare:CC (match_dup 0)
6865 (const_int 0)))]
6866 "")
6868 (define_expand "lshrdi3"
6869 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6870 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6871 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6872 "TARGET_POWERPC64 || TARGET_POWER"
6873 "
6874 {
6875 if (TARGET_POWERPC64)
6876 ;
6877 else if (TARGET_POWER)
6878 {
6879 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6880 DONE;
6881 }
6882 else
6883 FAIL;
6884 }")
6886 (define_insn "*lshrdi3_internal1"
6887 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6888 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6889 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6890 "TARGET_POWERPC64"
6891 "srd%I2 %0,%1,%H2")
6893 (define_insn "*lshrdi3_internal2"
6894 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6895 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6896 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6897 (const_int 0)))
6898 (clobber (match_scratch:DI 3 "=r,r"))]
6899 "TARGET_64BIT "
6900 "@
6901 srd%I2. %3,%1,%H2
6902 #"
6903 [(set_attr "type" "delayed_compare")
6904 (set_attr "length" "4,8")])
6906 (define_split
6907 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6908 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6909 (match_operand:SI 2 "reg_or_cint_operand" ""))
6910 (const_int 0)))
6911 (clobber (match_scratch:DI 3 ""))]
6912 "TARGET_POWERPC64 && reload_completed"
6913 [(set (match_dup 3)
6914 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6915 (set (match_dup 0)
6916 (compare:CC (match_dup 3)
6917 (const_int 0)))]
6918 "")
6920 (define_insn "*lshrdi3_internal3"
6921 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6922 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6923 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6924 (const_int 0)))
6925 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6926 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6927 "TARGET_64BIT"
6928 "@
6929 srd%I2. %0,%1,%H2
6930 #"
6931 [(set_attr "type" "delayed_compare")
6932 (set_attr "length" "4,8")])
6934 (define_split
6935 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6936 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6937 (match_operand:SI 2 "reg_or_cint_operand" ""))
6938 (const_int 0)))
6939 (set (match_operand:DI 0 "gpc_reg_operand" "")
6940 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6941 "TARGET_POWERPC64 && reload_completed"
6942 [(set (match_dup 0)
6943 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6944 (set (match_dup 3)
6945 (compare:CC (match_dup 0)
6946 (const_int 0)))]
6947 "")
6949 (define_expand "ashrdi3"
6950 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6951 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6952 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6953 ""
6954 "
6955 {
6956 if (TARGET_POWERPC64)
6957 ;
6958 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6959 {
6960 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6961 DONE;
6962 }
6963 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT)
6964 {
6965 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6966 DONE;
6967 }
6968 else
6969 FAIL;
6970 }")
6972 (define_insn "*ashrdi3_internal1"
6973 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6974 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6975 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6976 "TARGET_POWERPC64"
6977 "srad%I2 %0,%1,%H2")
6979 (define_insn "*ashrdi3_internal2"
6980 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6981 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6982 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6983 (const_int 0)))
6984 (clobber (match_scratch:DI 3 "=r,r"))]
6985 "TARGET_64BIT"
6986 "@
6987 srad%I2. %3,%1,%H2
6988 #"
6989 [(set_attr "type" "delayed_compare")
6990 (set_attr "length" "4,8")])
6992 (define_split
6993 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6994 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6995 (match_operand:SI 2 "reg_or_cint_operand" ""))
6996 (const_int 0)))
6997 (clobber (match_scratch:DI 3 ""))]
6998 "TARGET_POWERPC64 && reload_completed"
6999 [(set (match_dup 3)
7000 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7001 (set (match_dup 0)
7002 (compare:CC (match_dup 3)
7003 (const_int 0)))]
7004 "")
7006 (define_insn "*ashrdi3_internal3"
7007 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7008 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7009 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7010 (const_int 0)))
7011 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7012 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7013 "TARGET_64BIT"
7014 "@
7015 srad%I2. %0,%1,%H2
7016 #"
7017 [(set_attr "type" "delayed_compare")
7018 (set_attr "length" "4,8")])
7020 (define_split
7021 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7022 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7023 (match_operand:SI 2 "reg_or_cint_operand" ""))
7024 (const_int 0)))
7025 (set (match_operand:DI 0 "gpc_reg_operand" "")
7026 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7027 "TARGET_POWERPC64 && reload_completed"
7028 [(set (match_dup 0)
7029 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7030 (set (match_dup 3)
7031 (compare:CC (match_dup 0)
7032 (const_int 0)))]
7033 "")
7035 (define_insn "anddi3"
7036 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
7037 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
7038 (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t")))
7039 (clobber (match_scratch:CC 3 "=X,X,x,x,X"))]
7040 "TARGET_POWERPC64"
7041 "@
7042 and %0,%1,%2
7043 rldic%B2 %0,%1,0,%S2
7044 andi. %0,%1,%b2
7045 andis. %0,%1,%u2
7046 #"
7047 [(set_attr "length" "4,4,4,4,8")])
7049 (define_split
7050 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7051 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7052 (match_operand:DI 2 "mask64_2_operand" "")))
7053 (clobber (match_scratch:CC 3 ""))]
7054 "TARGET_POWERPC64
7055 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7056 && !mask64_operand (operands[2], DImode)"
7057 [(set (match_dup 0)
7058 (and:DI (rotate:DI (match_dup 1)
7059 (match_dup 4))
7060 (match_dup 5)))
7061 (set (match_dup 0)
7062 (and:DI (rotate:DI (match_dup 0)
7063 (match_dup 6))
7064 (match_dup 7)))]
7065 "
7066 {
7067 build_mask64_2_operands (operands[2], &operands[4]);
7068 }")
7070 (define_insn "*anddi3_internal2"
7071 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7072 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7073 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7074 (const_int 0)))
7075 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
7076 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7077 "TARGET_64BIT"
7078 "@
7079 and. %3,%1,%2
7080 rldic%B2. %3,%1,0,%S2
7081 andi. %3,%1,%b2
7082 andis. %3,%1,%u2
7083 #
7084 #
7085 #
7086 #
7087 #
7088 #"
7089 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7090 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7092 (define_split
7093 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7094 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7095 (match_operand:DI 2 "and64_operand" ""))
7096 (const_int 0)))
7097 (clobber (match_scratch:DI 3 ""))
7098 (clobber (match_scratch:CC 4 ""))]
7099 "TARGET_POWERPC64 && reload_completed"
7100 [(parallel [(set (match_dup 3)
7101 (and:DI (match_dup 1)
7102 (match_dup 2)))
7103 (clobber (match_dup 4))])
7104 (set (match_dup 0)
7105 (compare:CC (match_dup 3)
7106 (const_int 0)))]
7107 "")
7109 (define_split
7110 [(set (match_operand:CC 0 "cc_reg_operand" "")
7111 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7112 (match_operand:DI 2 "mask64_2_operand" ""))
7113 (const_int 0)))
7114 (clobber (match_scratch:DI 3 ""))
7115 (clobber (match_scratch:CC 4 ""))]
7116 "TARGET_POWERPC64 && reload_completed
7117 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7118 && !mask64_operand (operands[2], DImode)"
7119 [(set (match_dup 3)
7120 (and:DI (rotate:DI (match_dup 1)
7121 (match_dup 5))
7122 (match_dup 6)))
7123 (parallel [(set (match_dup 0)
7124 (compare:CC (and:DI (rotate:DI (match_dup 3)
7125 (match_dup 7))
7126 (match_dup 8))
7127 (const_int 0)))
7128 (clobber (match_dup 3))])]
7129 "
7130 {
7131 build_mask64_2_operands (operands[2], &operands[5]);
7132 }")
7134 (define_insn "*anddi3_internal3"
7135 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7136 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7137 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7138 (const_int 0)))
7139 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
7140 (and:DI (match_dup 1) (match_dup 2)))
7141 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7142 "TARGET_64BIT"
7143 "@
7144 and. %0,%1,%2
7145 rldic%B2. %0,%1,0,%S2
7146 andi. %0,%1,%b2
7147 andis. %0,%1,%u2
7148 #
7149 #
7150 #
7151 #
7152 #
7153 #"
7154 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7155 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7157 (define_split
7158 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7159 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7160 (match_operand:DI 2 "and64_operand" ""))
7161 (const_int 0)))
7162 (set (match_operand:DI 0 "gpc_reg_operand" "")
7163 (and:DI (match_dup 1) (match_dup 2)))
7164 (clobber (match_scratch:CC 4 ""))]
7165 "TARGET_POWERPC64 && reload_completed"
7166 [(parallel [(set (match_dup 0)
7167 (and:DI (match_dup 1) (match_dup 2)))
7168 (clobber (match_dup 4))])
7169 (set (match_dup 3)
7170 (compare:CC (match_dup 0)
7171 (const_int 0)))]
7172 "")
7174 (define_split
7175 [(set (match_operand:CC 3 "cc_reg_operand" "")
7176 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7177 (match_operand:DI 2 "mask64_2_operand" ""))
7178 (const_int 0)))
7179 (set (match_operand:DI 0 "gpc_reg_operand" "")
7180 (and:DI (match_dup 1) (match_dup 2)))
7181 (clobber (match_scratch:CC 4 ""))]
7182 "TARGET_POWERPC64 && reload_completed
7183 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7184 && !mask64_operand (operands[2], DImode)"
7185 [(set (match_dup 0)
7186 (and:DI (rotate:DI (match_dup 1)
7187 (match_dup 5))
7188 (match_dup 6)))
7189 (parallel [(set (match_dup 3)
7190 (compare:CC (and:DI (rotate:DI (match_dup 0)
7191 (match_dup 7))
7192 (match_dup 8))
7193 (const_int 0)))
7194 (set (match_dup 0)
7195 (and:DI (rotate:DI (match_dup 0)
7196 (match_dup 7))
7197 (match_dup 8)))])]
7198 "
7199 {
7200 build_mask64_2_operands (operands[2], &operands[5]);
7201 }")
7203 (define_expand "iordi3"
7204 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7205 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7206 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7207 "TARGET_POWERPC64"
7208 "
7209 {
7210 if (non_logical_cint_operand (operands[2], DImode))
7211 {
7212 HOST_WIDE_INT value;
7213 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7214 ? operands[0] : gen_reg_rtx (DImode));
7216 if (GET_CODE (operands[2]) == CONST_INT)
7217 {
7218 value = INTVAL (operands[2]);
7219 emit_insn (gen_iordi3 (tmp, operands[1],
7220 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7221 }
7222 else
7223 {
7224 value = CONST_DOUBLE_LOW (operands[2]);
7225 emit_insn (gen_iordi3 (tmp, operands[1],
7226 immed_double_const (value
7227 & (~ (HOST_WIDE_INT) 0xffff),
7228 0, DImode)));
7229 }
7231 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7232 DONE;
7233 }
7234 }")
7236 (define_expand "xordi3"
7237 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7238 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7239 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7240 "TARGET_POWERPC64"
7241 "
7242 {
7243 if (non_logical_cint_operand (operands[2], DImode))
7244 {
7245 HOST_WIDE_INT value;
7246 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7247 ? operands[0] : gen_reg_rtx (DImode));
7249 if (GET_CODE (operands[2]) == CONST_INT)
7250 {
7251 value = INTVAL (operands[2]);
7252 emit_insn (gen_xordi3 (tmp, operands[1],
7253 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7254 }
7255 else
7256 {
7257 value = CONST_DOUBLE_LOW (operands[2]);
7258 emit_insn (gen_xordi3 (tmp, operands[1],
7259 immed_double_const (value
7260 & (~ (HOST_WIDE_INT) 0xffff),
7261 0, DImode)));
7262 }
7264 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7265 DONE;
7266 }
7267 }")
7269 (define_insn "*booldi3_internal1"
7270 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7271 (match_operator:DI 3 "boolean_or_operator"
7272 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7273 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7274 "TARGET_POWERPC64"
7275 "@
7276 %q3 %0,%1,%2
7277 %q3i %0,%1,%b2
7278 %q3is %0,%1,%u2")
7280 (define_insn "*booldi3_internal2"
7281 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7282 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7283 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7284 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7285 (const_int 0)))
7286 (clobber (match_scratch:DI 3 "=r,r"))]
7287 "TARGET_64BIT"
7288 "@
7289 %q4. %3,%1,%2
7290 #"
7291 [(set_attr "type" "compare")
7292 (set_attr "length" "4,8")])
7294 (define_split
7295 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7296 (compare:CC (match_operator:DI 4 "boolean_operator"
7297 [(match_operand:DI 1 "gpc_reg_operand" "")
7298 (match_operand:DI 2 "gpc_reg_operand" "")])
7299 (const_int 0)))
7300 (clobber (match_scratch:DI 3 ""))]
7301 "TARGET_POWERPC64 && reload_completed"
7302 [(set (match_dup 3) (match_dup 4))
7303 (set (match_dup 0)
7304 (compare:CC (match_dup 3)
7305 (const_int 0)))]
7306 "")
7308 (define_insn "*booldi3_internal3"
7309 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7310 (compare:CC (match_operator:DI 4 "boolean_operator"
7311 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7312 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7313 (const_int 0)))
7314 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7315 (match_dup 4))]
7316 "TARGET_64BIT"
7317 "@
7318 %q4. %0,%1,%2
7319 #"
7320 [(set_attr "type" "compare")
7321 (set_attr "length" "4,8")])
7323 (define_split
7324 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7325 (compare:CC (match_operator:DI 4 "boolean_operator"
7326 [(match_operand:DI 1 "gpc_reg_operand" "")
7327 (match_operand:DI 2 "gpc_reg_operand" "")])
7328 (const_int 0)))
7329 (set (match_operand:DI 0 "gpc_reg_operand" "")
7330 (match_dup 4))]
7331 "TARGET_POWERPC64 && reload_completed"
7332 [(set (match_dup 0) (match_dup 4))
7333 (set (match_dup 3)
7334 (compare:CC (match_dup 0)
7335 (const_int 0)))]
7336 "")
7338 ;; Split a logical operation that we can't do in one insn into two insns,
7339 ;; each of which does one 16-bit part. This is used by combine.
7341 (define_split
7342 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7343 (match_operator:DI 3 "boolean_or_operator"
7344 [(match_operand:DI 1 "gpc_reg_operand" "")
7345 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7346 "TARGET_POWERPC64"
7347 [(set (match_dup 0) (match_dup 4))
7348 (set (match_dup 0) (match_dup 5))]
7349 "
7350 {
7351 rtx i3,i4;
7353 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7354 {
7355 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7356 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7357 0, DImode);
7358 i4 = GEN_INT (value & 0xffff);
7359 }
7360 else
7361 {
7362 i3 = GEN_INT (INTVAL (operands[2])
7363 & (~ (HOST_WIDE_INT) 0xffff));
7364 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7365 }
7366 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7367 operands[1], i3);
7368 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7369 operands[0], i4);
7370 }")
7372 (define_insn "*boolcdi3_internal1"
7373 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7374 (match_operator:DI 3 "boolean_operator"
7375 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7376 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7377 "TARGET_POWERPC64"
7378 "%q3 %0,%2,%1")
7380 (define_insn "*boolcdi3_internal2"
7381 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7382 (compare:CC (match_operator:DI 4 "boolean_operator"
7383 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7384 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7385 (const_int 0)))
7386 (clobber (match_scratch:DI 3 "=r,r"))]
7387 "TARGET_64BIT"
7388 "@
7389 %q4. %3,%2,%1
7390 #"
7391 [(set_attr "type" "compare")
7392 (set_attr "length" "4,8")])
7394 (define_split
7395 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7396 (compare:CC (match_operator:DI 4 "boolean_operator"
7397 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7398 (match_operand:DI 2 "gpc_reg_operand" "")])
7399 (const_int 0)))
7400 (clobber (match_scratch:DI 3 ""))]
7401 "TARGET_POWERPC64 && reload_completed"
7402 [(set (match_dup 3) (match_dup 4))
7403 (set (match_dup 0)
7404 (compare:CC (match_dup 3)
7405 (const_int 0)))]
7406 "")
7408 (define_insn "*boolcdi3_internal3"
7409 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7410 (compare:CC (match_operator:DI 4 "boolean_operator"
7411 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7412 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7413 (const_int 0)))
7414 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7415 (match_dup 4))]
7416 "TARGET_64BIT"
7417 "@
7418 %q4. %0,%2,%1
7419 #"
7420 [(set_attr "type" "compare")
7421 (set_attr "length" "4,8")])
7423 (define_split
7424 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7425 (compare:CC (match_operator:DI 4 "boolean_operator"
7426 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7427 (match_operand:DI 2 "gpc_reg_operand" "")])
7428 (const_int 0)))
7429 (set (match_operand:DI 0 "gpc_reg_operand" "")
7430 (match_dup 4))]
7431 "TARGET_POWERPC64 && reload_completed"
7432 [(set (match_dup 0) (match_dup 4))
7433 (set (match_dup 3)
7434 (compare:CC (match_dup 0)
7435 (const_int 0)))]
7436 "")
7438 (define_insn "*boolccdi3_internal1"
7439 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7440 (match_operator:DI 3 "boolean_operator"
7441 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7442 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7443 "TARGET_POWERPC64"
7444 "%q3 %0,%1,%2")
7446 (define_insn "*boolccdi3_internal2"
7447 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7448 (compare:CC (match_operator:DI 4 "boolean_operator"
7449 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7450 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7451 (const_int 0)))
7452 (clobber (match_scratch:DI 3 "=r,r"))]
7453 "TARGET_64BIT"
7454 "@
7455 %q4. %3,%1,%2
7456 #"
7457 [(set_attr "type" "compare")
7458 (set_attr "length" "4,8")])
7460 (define_split
7461 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7462 (compare:CC (match_operator:DI 4 "boolean_operator"
7463 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7464 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7465 (const_int 0)))
7466 (clobber (match_scratch:DI 3 ""))]
7467 "TARGET_POWERPC64 && reload_completed"
7468 [(set (match_dup 3) (match_dup 4))
7469 (set (match_dup 0)
7470 (compare:CC (match_dup 3)
7471 (const_int 0)))]
7472 "")
7474 (define_insn "*boolccdi3_internal3"
7475 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7476 (compare:CC (match_operator:DI 4 "boolean_operator"
7477 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7478 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7479 (const_int 0)))
7480 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7481 (match_dup 4))]
7482 "TARGET_64BIT"
7483 "@
7484 %q4. %0,%1,%2
7485 #"
7486 [(set_attr "type" "compare")
7487 (set_attr "length" "4,8")])
7489 (define_split
7490 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7491 (compare:CC (match_operator:DI 4 "boolean_operator"
7492 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7493 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7494 (const_int 0)))
7495 (set (match_operand:DI 0 "gpc_reg_operand" "")
7496 (match_dup 4))]
7497 "TARGET_POWERPC64 && reload_completed"
7498 [(set (match_dup 0) (match_dup 4))
7499 (set (match_dup 3)
7500 (compare:CC (match_dup 0)
7501 (const_int 0)))]
7502 "")
7503 \f
7504 ;; Now define ways of moving data around.
7506 ;; Elf specific ways of loading addresses for non-PIC code.
7507 ;; The output of this could be r0, but we make a very strong
7508 ;; preference for a base register because it will usually
7509 ;; be needed there.
7510 (define_insn "elf_high"
7511 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7512 (high:SI (match_operand 1 "" "")))]
7513 "TARGET_ELF && ! TARGET_64BIT"
7514 "{liu|lis} %0,%1@ha")
7516 (define_insn "elf_low"
7517 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7518 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7519 (match_operand 2 "" "")))]
7520 "TARGET_ELF && ! TARGET_64BIT"
7521 "@
7522 {cal|la} %0,%2@l(%1)
7523 {ai|addic} %0,%1,%K2")
7525 ;; Mach-O PIC trickery.
7526 (define_insn "macho_high"
7527 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7528 (high:SI (match_operand 1 "" "")))]
7529 "TARGET_MACHO && ! TARGET_64BIT"
7530 "{liu|lis} %0,ha16(%1)")
7532 (define_insn "macho_low"
7533 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7534 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7535 (match_operand 2 "" "")))]
7536 "TARGET_MACHO && ! TARGET_64BIT"
7537 "@
7538 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
7539 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
7541 ;; Set up a register with a value from the GOT table
7543 (define_expand "movsi_got"
7544 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7545 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7546 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7547 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7548 "
7549 {
7550 if (GET_CODE (operands[1]) == CONST)
7551 {
7552 rtx offset = const0_rtx;
7553 HOST_WIDE_INT value;
7555 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7556 value = INTVAL (offset);
7557 if (value != 0)
7558 {
7559 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7560 emit_insn (gen_movsi_got (tmp, operands[1]));
7561 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7562 DONE;
7563 }
7564 }
7566 operands[2] = rs6000_got_register (operands[1]);
7567 }")
7569 (define_insn "*movsi_got_internal"
7570 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7571 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7572 (match_operand:SI 2 "gpc_reg_operand" "b")]
7573 UNSPEC_MOVSI_GOT))]
7574 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7575 "{l|lwz} %0,%a1@got(%2)"
7576 [(set_attr "type" "load")])
7578 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7579 ;; didn't get allocated to a hard register.
7580 (define_split
7581 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7582 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7583 (match_operand:SI 2 "memory_operand" "")]
7584 UNSPEC_MOVSI_GOT))]
7585 "DEFAULT_ABI == ABI_V4
7586 && flag_pic == 1
7587 && (reload_in_progress || reload_completed)"
7588 [(set (match_dup 0) (match_dup 2))
7589 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7590 UNSPEC_MOVSI_GOT))]
7591 "")
7593 ;; For SI, we special-case integers that can't be loaded in one insn. We
7594 ;; do the load 16-bits at a time. We could do this by loading from memory,
7595 ;; and this is even supposed to be faster, but it is simpler not to get
7596 ;; integers in the TOC.
7597 (define_expand "movsi"
7598 [(set (match_operand:SI 0 "general_operand" "")
7599 (match_operand:SI 1 "any_operand" ""))]
7600 ""
7601 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
7603 (define_insn "movsi_low"
7604 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7605 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7606 (match_operand 2 "" ""))))]
7607 "TARGET_MACHO && ! TARGET_64BIT"
7608 "{l|lwz} %0,lo16(%2)(%1)"
7609 [(set_attr "type" "load")
7610 (set_attr "length" "4")])
7612 (define_insn "movsi_low_st"
7613 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7614 (match_operand 2 "" "")))
7615 (match_operand:SI 0 "gpc_reg_operand" "r"))]
7616 "TARGET_MACHO && ! TARGET_64BIT"
7617 "{st|stw} %0,lo16(%2)(%1)"
7618 [(set_attr "type" "store")
7619 (set_attr "length" "4")])
7621 (define_insn "movdf_low"
7622 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
7623 (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7624 (match_operand 2 "" ""))))]
7625 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7626 "*
7627 {
7628 switch (which_alternative)
7629 {
7630 case 0:
7631 return \"lfd %0,lo16(%2)(%1)\";
7632 case 1:
7633 {
7634 rtx operands2[4];
7635 operands2[0] = operands[0];
7636 operands2[1] = operands[1];
7637 operands2[2] = operands[2];
7638 if (TARGET_POWERPC64 && TARGET_32BIT)
7639 /* Note, old assemblers didn't support relocation here. */
7640 return \"ld %0,lo16(%2)(%1)\";
7641 else
7642 {
7643 operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM);
7644 output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands);
7645 #if TARGET_MACHO
7646 if (MACHO_DYNAMIC_NO_PIC_P)
7647 output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands);
7648 else
7649 /* We cannot rely on ha16(low half)==ha16(high half), alas,
7650 although in practice it almost always is. */
7651 output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2);
7652 #endif
7653 return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\");
7654 }
7655 }
7656 default:
7657 abort();
7658 }
7659 }"
7660 [(set_attr "type" "load")
7661 (set_attr "length" "4,12")])
7663 (define_insn "movdf_low_st"
7664 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7665 (match_operand 2 "" "")))
7666 (match_operand:DF 0 "gpc_reg_operand" "f"))]
7667 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7668 "stfd %0,lo16(%2)(%1)"
7669 [(set_attr "type" "store")
7670 (set_attr "length" "4")])
7672 (define_insn "movsf_low"
7673 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
7674 (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7675 (match_operand 2 "" ""))))]
7676 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7677 "@
7678 lfs %0,lo16(%2)(%1)
7679 {l|lwz} %0,lo16(%2)(%1)"
7680 [(set_attr "type" "load")
7681 (set_attr "length" "4")])
7683 (define_insn "movsf_low_st"
7684 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7685 (match_operand 2 "" "")))
7686 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
7687 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7688 "@
7689 stfs %0,lo16(%2)(%1)
7690 {st|stw} %0,lo16(%2)(%1)"
7691 [(set_attr "type" "store")
7692 (set_attr "length" "4")])
7694 (define_insn "*movsi_internal1"
7695 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7696 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7697 "gpc_reg_operand (operands[0], SImode)
7698 || gpc_reg_operand (operands[1], SImode)"
7699 "@
7700 mr %0,%1
7701 {cal|la} %0,%a1
7702 {l%U1%X1|lwz%U1%X1} %0,%1
7703 {st%U0%X0|stw%U0%X0} %1,%0
7704 {lil|li} %0,%1
7705 {liu|lis} %0,%v1
7706 #
7707 {cal|la} %0,%a1
7708 mf%1 %0
7709 mt%0 %1
7710 mt%0 %1
7711 mt%0 %1
7712 {cror 0,0,0|nop}"
7713 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7714 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7716 ;; Split a load of a large constant into the appropriate two-insn
7717 ;; sequence.
7719 (define_split
7720 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7721 (match_operand:SI 1 "const_int_operand" ""))]
7722 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7723 && (INTVAL (operands[1]) & 0xffff) != 0"
7724 [(set (match_dup 0)
7725 (match_dup 2))
7726 (set (match_dup 0)
7727 (ior:SI (match_dup 0)
7728 (match_dup 3)))]
7729 "
7730 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7732 if (tem == operands[0])
7733 DONE;
7734 else
7735 FAIL;
7736 }")
7738 (define_insn "*movsi_internal2"
7739 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7740 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r")
7741 (const_int 0)))
7742 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7743 "TARGET_32BIT"
7744 "@
7745 {cmpi|cmpwi} %2,%0,0
7746 mr. %0,%1
7747 #"
7748 [(set_attr "type" "cmp,compare,cmp")
7749 (set_attr "length" "4,4,8")])
7751 (define_split
7752 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7753 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7754 (const_int 0)))
7755 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7756 "TARGET_32BIT && reload_completed"
7757 [(set (match_dup 0) (match_dup 1))
7758 (set (match_dup 2)
7759 (compare:CC (match_dup 0)
7760 (const_int 0)))]
7761 "")
7762 \f
7763 (define_expand "movhi"
7764 [(set (match_operand:HI 0 "general_operand" "")
7765 (match_operand:HI 1 "any_operand" ""))]
7766 ""
7767 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
7769 (define_insn "*movhi_internal"
7770 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7771 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7772 "gpc_reg_operand (operands[0], HImode)
7773 || gpc_reg_operand (operands[1], HImode)"
7774 "@
7775 mr %0,%1
7776 lhz%U1%X1 %0,%1
7777 sth%U0%X0 %1,%0
7778 {lil|li} %0,%w1
7779 mf%1 %0
7780 mt%0 %1
7781 mt%0 %1
7782 {cror 0,0,0|nop}"
7783 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7785 (define_expand "movqi"
7786 [(set (match_operand:QI 0 "general_operand" "")
7787 (match_operand:QI 1 "any_operand" ""))]
7788 ""
7789 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
7791 (define_insn "*movqi_internal"
7792 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7793 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7794 "gpc_reg_operand (operands[0], QImode)
7795 || gpc_reg_operand (operands[1], QImode)"
7796 "@
7797 mr %0,%1
7798 lbz%U1%X1 %0,%1
7799 stb%U0%X0 %1,%0
7800 {lil|li} %0,%1
7801 mf%1 %0
7802 mt%0 %1
7803 mt%0 %1
7804 {cror 0,0,0|nop}"
7805 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7806 \f
7807 ;; Here is how to move condition codes around. When we store CC data in
7808 ;; an integer register or memory, we store just the high-order 4 bits.
7809 ;; This lets us not shift in the most common case of CR0.
7810 (define_expand "movcc"
7811 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7812 (match_operand:CC 1 "nonimmediate_operand" ""))]
7813 ""
7814 "")
7816 (define_insn "*movcc_internal1"
7817 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7818 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7819 "register_operand (operands[0], CCmode)
7820 || register_operand (operands[1], CCmode)"
7821 "@
7822 mcrf %0,%1
7823 mtcrf 128,%1
7824 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7825 mfcr %0%Q1
7826 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7827 mr %0,%1
7828 mf%1 %0
7829 mt%0 %1
7830 mt%0 %1
7831 {l%U1%X1|lwz%U1%X1} %0,%1
7832 {st%U0%U1|stw%U0%U1} %1,%0"
7833 [(set (attr "type")
7834 (cond [(eq_attr "alternative" "0")
7835 (const_string "cr_logical")
7836 (eq_attr "alternative" "1,2")
7837 (const_string "mtcr")
7838 (eq_attr "alternative" "5,7")
7839 (const_string "integer")
7840 (eq_attr "alternative" "6")
7841 (const_string "mfjmpr")
7842 (eq_attr "alternative" "8")
7843 (const_string "mtjmpr")
7844 (eq_attr "alternative" "9")
7845 (const_string "load")
7846 (eq_attr "alternative" "10")
7847 (const_string "store")
7848 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7849 (const_string "mfcrf")
7850 ]
7851 (const_string "mfcr")))
7852 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7853 \f
7854 ;; For floating-point, we normally deal with the floating-point registers
7855 ;; unless -msoft-float is used. The sole exception is that parameter passing
7856 ;; can produce floating-point values in fixed-point registers. Unless the
7857 ;; value is a simple constant or already in memory, we deal with this by
7858 ;; allocating memory and copying the value explicitly via that memory location.
7859 (define_expand "movsf"
7860 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7861 (match_operand:SF 1 "any_operand" ""))]
7862 ""
7863 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7865 (define_split
7866 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7867 (match_operand:SF 1 "const_double_operand" ""))]
7868 "reload_completed
7869 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7870 || (GET_CODE (operands[0]) == SUBREG
7871 && GET_CODE (SUBREG_REG (operands[0])) == REG
7872 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7873 [(set (match_dup 2) (match_dup 3))]
7874 "
7875 {
7876 long l;
7877 REAL_VALUE_TYPE rv;
7879 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7880 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7882 if (! TARGET_POWERPC64)
7883 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7884 else
7885 operands[2] = gen_lowpart (SImode, operands[0]);
7887 operands[3] = gen_int_mode (l, SImode);
7888 }")
7890 (define_insn "*movsf_hardfloat"
7891 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
7892 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
7893 "(gpc_reg_operand (operands[0], SFmode)
7894 || gpc_reg_operand (operands[1], SFmode))
7895 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7896 "@
7897 mr %0,%1
7898 {l%U1%X1|lwz%U1%X1} %0,%1
7899 {st%U0%X0|stw%U0%X0} %1,%0
7900 fmr %0,%1
7901 lfs%U1%X1 %0,%1
7902 stfs%U0%X0 %1,%0
7903 mt%0 %1
7904 mt%0 %1
7905 mf%1 %0
7906 {cror 0,0,0|nop}
7907 #
7908 #"
7909 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
7910 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
7912 (define_insn "*movsf_softfloat"
7913 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7914 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7915 "(gpc_reg_operand (operands[0], SFmode)
7916 || gpc_reg_operand (operands[1], SFmode))
7917 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7918 "@
7919 mr %0,%1
7920 mt%0 %1
7921 mt%0 %1
7922 mf%1 %0
7923 {l%U1%X1|lwz%U1%X1} %0,%1
7924 {st%U0%X0|stw%U0%X0} %1,%0
7925 {lil|li} %0,%1
7926 {liu|lis} %0,%v1
7927 {cal|la} %0,%a1
7928 #
7929 #
7930 {cror 0,0,0|nop}"
7931 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
7932 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
7934 \f
7935 (define_expand "movdf"
7936 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7937 (match_operand:DF 1 "any_operand" ""))]
7938 ""
7939 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7941 (define_split
7942 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7943 (match_operand:DF 1 "const_int_operand" ""))]
7944 "! TARGET_POWERPC64 && reload_completed
7945 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7946 || (GET_CODE (operands[0]) == SUBREG
7947 && GET_CODE (SUBREG_REG (operands[0])) == REG
7948 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7949 [(set (match_dup 2) (match_dup 4))
7950 (set (match_dup 3) (match_dup 1))]
7951 "
7952 {
7953 int endian = (WORDS_BIG_ENDIAN == 0);
7954 HOST_WIDE_INT value = INTVAL (operands[1]);
7956 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7957 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7958 #if HOST_BITS_PER_WIDE_INT == 32
7959 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7960 #else
7961 operands[4] = GEN_INT (value >> 32);
7962 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7963 #endif
7964 }")
7966 (define_split
7967 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7968 (match_operand:DF 1 "const_double_operand" ""))]
7969 "! TARGET_POWERPC64 && reload_completed
7970 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7971 || (GET_CODE (operands[0]) == SUBREG
7972 && GET_CODE (SUBREG_REG (operands[0])) == REG
7973 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7974 [(set (match_dup 2) (match_dup 4))
7975 (set (match_dup 3) (match_dup 5))]
7976 "
7977 {
7978 int endian = (WORDS_BIG_ENDIAN == 0);
7979 long l[2];
7980 REAL_VALUE_TYPE rv;
7982 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7983 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7985 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7986 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7987 operands[4] = gen_int_mode (l[endian], SImode);
7988 operands[5] = gen_int_mode (l[1 - endian], SImode);
7989 }")
7991 (define_split
7992 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7993 (match_operand:DF 1 "easy_fp_constant" ""))]
7994 "TARGET_POWERPC64 && reload_completed
7995 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7996 || (GET_CODE (operands[0]) == SUBREG
7997 && GET_CODE (SUBREG_REG (operands[0])) == REG
7998 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7999 [(set (match_dup 2) (match_dup 3))]
8000 "
8001 {
8002 int endian = (WORDS_BIG_ENDIAN == 0);
8003 long l[2];
8004 REAL_VALUE_TYPE rv;
8005 #if HOST_BITS_PER_WIDE_INT >= 64
8006 HOST_WIDE_INT val;
8007 #endif
8009 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8010 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8012 operands[2] = gen_lowpart (DImode, operands[0]);
8013 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8014 #if HOST_BITS_PER_WIDE_INT >= 64
8015 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8016 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8018 operands[3] = gen_int_mode (val, DImode);
8019 #else
8020 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8021 #endif
8022 }")
8024 ;; Don't have reload use general registers to load a constant. First,
8025 ;; it might not work if the output operand is the equivalent of
8026 ;; a non-offsettable memref, but also it is less efficient than loading
8027 ;; the constant into an FP register, since it will probably be used there.
8028 ;; The "??" is a kludge until we can figure out a more reasonable way
8029 ;; of handling these non-offsettable values.
8030 (define_insn "*movdf_hardfloat32"
8031 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8032 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8033 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8034 && (gpc_reg_operand (operands[0], DFmode)
8035 || gpc_reg_operand (operands[1], DFmode))"
8036 "*
8037 {
8038 switch (which_alternative)
8039 {
8040 default:
8041 abort ();
8042 case 0:
8043 /* We normally copy the low-numbered register first. However, if
8044 the first register operand 0 is the same as the second register
8045 of operand 1, we must copy in the opposite order. */
8046 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8047 return \"mr %L0,%L1\;mr %0,%1\";
8048 else
8049 return \"mr %0,%1\;mr %L0,%L1\";
8050 case 1:
8051 if (offsettable_memref_p (operands[1])
8052 || (GET_CODE (operands[1]) == MEM
8053 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8054 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8055 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
8056 {
8057 /* If the low-address word is used in the address, we must load
8058 it last. Otherwise, load it first. Note that we cannot have
8059 auto-increment in that case since the address register is
8060 known to be dead. */
8061 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8062 operands[1], 0))
8063 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8064 else
8065 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8066 }
8067 else
8068 {
8069 rtx addreg;
8071 addreg = find_addr_reg (XEXP (operands[1], 0));
8072 if (refers_to_regno_p (REGNO (operands[0]),
8073 REGNO (operands[0]) + 1,
8074 operands[1], 0))
8075 {
8076 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8077 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8078 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8079 return \"{lx|lwzx} %0,%1\";
8080 }
8081 else
8082 {
8083 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
8084 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8085 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8086 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8087 return \"\";
8088 }
8089 }
8090 case 2:
8091 if (offsettable_memref_p (operands[0])
8092 || (GET_CODE (operands[0]) == MEM
8093 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8094 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8095 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
8096 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8097 else
8098 {
8099 rtx addreg;
8101 addreg = find_addr_reg (XEXP (operands[0], 0));
8102 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
8103 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8104 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
8105 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8106 return \"\";
8107 }
8108 case 3:
8109 return \"fmr %0,%1\";
8110 case 4:
8111 return \"lfd%U1%X1 %0,%1\";
8112 case 5:
8113 return \"stfd%U0%X0 %1,%0\";
8114 case 6:
8115 case 7:
8116 case 8:
8117 return \"#\";
8118 }
8119 }"
8120 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*")
8121 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8123 (define_insn "*movdf_softfloat32"
8124 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8125 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8126 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8127 && (gpc_reg_operand (operands[0], DFmode)
8128 || gpc_reg_operand (operands[1], DFmode))"
8129 "*
8130 {
8131 switch (which_alternative)
8132 {
8133 default:
8134 abort ();
8135 case 0:
8136 /* We normally copy the low-numbered register first. However, if
8137 the first register operand 0 is the same as the second register of
8138 operand 1, we must copy in the opposite order. */
8139 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8140 return \"mr %L0,%L1\;mr %0,%1\";
8141 else
8142 return \"mr %0,%1\;mr %L0,%L1\";
8143 case 1:
8144 /* If the low-address word is used in the address, we must load
8145 it last. Otherwise, load it first. Note that we cannot have
8146 auto-increment in that case since the address register is
8147 known to be dead. */
8148 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8149 operands[1], 0))
8150 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8151 else
8152 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8153 case 2:
8154 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8155 case 3:
8156 case 4:
8157 case 5:
8158 return \"#\";
8159 }
8160 }"
8161 [(set_attr "type" "*,load,store,*,*,*")
8162 (set_attr "length" "8,8,8,8,12,16")])
8164 ; ld/std require word-aligned displacements -> 'Y' constraint.
8165 ; List Y->r and r->Y before r->r for reload.
8166 (define_insn "*movdf_hardfloat64"
8167 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
8168 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8169 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8170 && (gpc_reg_operand (operands[0], DFmode)
8171 || gpc_reg_operand (operands[1], DFmode))"
8172 "@
8173 std%U0%X0 %1,%0
8174 ld%U1%X1 %0,%1
8175 mr %0,%1
8176 fmr %0,%1
8177 lfd%U1%X1 %0,%1
8178 stfd%U0%X0 %1,%0
8179 mt%0 %1
8180 mf%1 %0
8181 {cror 0,0,0|nop}
8182 #
8183 #
8184 #"
8185 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
8186 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8188 (define_insn "*movdf_softfloat64"
8189 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8190 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8191 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8192 && (gpc_reg_operand (operands[0], DFmode)
8193 || gpc_reg_operand (operands[1], DFmode))"
8194 "@
8195 ld%U1%X1 %0,%1
8196 std%U0%X0 %1,%0
8197 mr %0,%1
8198 mt%0 %1
8199 mf%1 %0
8200 #
8201 #
8202 #
8203 {cror 0,0,0|nop}"
8204 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
8205 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8206 \f
8207 (define_expand "movtf"
8208 [(set (match_operand:TF 0 "general_operand" "")
8209 (match_operand:TF 1 "any_operand" ""))]
8210 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8211 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8212 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8214 ; It's important to list the o->f and f->o moves before f->f because
8215 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8216 ; which doesn't make progress.
8217 (define_insn_and_split "*movtf_internal"
8218 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,rm,r")
8219 (match_operand:TF 1 "input_operand" "f,o,f,r,mGHF"))]
8220 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8221 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8222 && (gpc_reg_operand (operands[0], TFmode)
8223 || gpc_reg_operand (operands[1], TFmode))"
8224 "#"
8225 "&& reload_completed"
8226 [(pc)]
8227 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8228 [(set_attr "length" "8,8,8,20,20")])
8230 (define_expand "extenddftf2"
8231 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8232 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8233 (use (match_dup 2))])]
8234 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8235 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8236 {
8237 operands[2] = CONST0_RTX (DFmode);
8238 })
8240 (define_insn_and_split "*extenddftf2_internal"
8241 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8242 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8243 (use (match_operand:DF 2 "input_operand" "rf,m,f,n"))]
8244 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8245 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8246 "#"
8247 "&& reload_completed"
8248 [(pc)]
8249 {
8250 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8251 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8252 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8253 operands[1]);
8254 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8255 operands[2]);
8256 DONE;
8257 })
8259 (define_expand "extendsftf2"
8260 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8261 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8262 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8263 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8264 {
8265 rtx tmp = gen_reg_rtx (DFmode);
8266 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8267 emit_insn (gen_extenddftf2 (operands[0], tmp));
8268 DONE;
8269 })
8271 (define_insn "trunctfdf2"
8272 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8273 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8274 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8275 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8276 "fadd %0,%1,%L1"
8277 [(set_attr "type" "fp")
8278 (set_attr "length" "4")])
8280 (define_insn_and_split "trunctfsf2"
8281 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8282 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8283 (clobber (match_scratch:DF 2 "=f"))]
8284 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8285 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8286 "#"
8287 "&& reload_completed"
8288 [(set (match_dup 2)
8289 (float_truncate:DF (match_dup 1)))
8290 (set (match_dup 0)
8291 (float_truncate:SF (match_dup 2)))]
8292 "")
8294 (define_expand "floatsitf2"
8295 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8296 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
8297 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8298 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8299 {
8300 rtx tmp = gen_reg_rtx (DFmode);
8301 expand_float (tmp, operands[1], false);
8302 emit_insn (gen_extenddftf2 (operands[0], tmp));
8303 DONE;
8304 })
8306 ; fadd, but rounding towards zero.
8307 ; This is probably not the optimal code sequence.
8308 (define_insn "fix_trunc_helper"
8309 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8310 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8311 UNSPEC_FIX_TRUNC_TF))
8312 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8313 "TARGET_HARD_FLOAT && TARGET_FPRS"
8314 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8315 [(set_attr "type" "fp")
8316 (set_attr "length" "20")])
8318 (define_expand "fix_trunctfsi2"
8319 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8320 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8321 (clobber (match_dup 2))
8322 (clobber (match_dup 3))
8323 (clobber (match_dup 4))
8324 (clobber (match_dup 5))])]
8325 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8326 && (TARGET_POWER2 || TARGET_POWERPC)
8327 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8328 {
8329 operands[2] = gen_reg_rtx (DFmode);
8330 operands[3] = gen_reg_rtx (DFmode);
8331 operands[4] = gen_reg_rtx (DImode);
8332 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8333 })
8335 (define_insn_and_split "*fix_trunctfsi2_internal"
8336 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8337 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8338 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8339 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8340 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8341 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8342 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8343 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8344 "#"
8345 "&& reload_completed"
8346 [(pc)]
8347 {
8348 rtx lowword;
8349 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8351 if (GET_CODE (operands[5]) != MEM)
8352 abort();
8353 lowword = XEXP (operands[5], 0);
8354 if (WORDS_BIG_ENDIAN)
8355 lowword = plus_constant (lowword, 4);
8357 emit_insn (gen_fctiwz (operands[4], operands[2]));
8358 emit_move_insn (operands[5], operands[4]);
8359 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
8360 DONE;
8361 })
8363 (define_insn "negtf2"
8364 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8365 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8366 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8367 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8368 "*
8369 {
8370 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8371 return \"fneg %L0,%L1\;fneg %0,%1\";
8372 else
8373 return \"fneg %0,%1\;fneg %L0,%L1\";
8374 }"
8375 [(set_attr "type" "fp")
8376 (set_attr "length" "8")])
8378 (define_insn "abstf2"
8379 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8380 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8381 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8382 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8383 "*
8384 {
8385 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8386 return \"fabs %L0,%L1\;fabs %0,%1\";
8387 else
8388 return \"fabs %0,%1\;fabs %L0,%L1\";
8389 }"
8390 [(set_attr "type" "fp")
8391 (set_attr "length" "8")])
8393 (define_insn ""
8394 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8395 (neg:TF (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f"))))]
8396 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8397 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8398 "*
8399 {
8400 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8401 return \"fnabs %L0,%L1\;fnabs %0,%1\";
8402 else
8403 return \"fnabs %0,%1\;fnabs %L0,%L1\";
8404 }"
8405 [(set_attr "type" "fp")
8406 (set_attr "length" "8")])
8407 \f
8408 ;; Next come the multi-word integer load and store and the load and store
8409 ;; multiple insns.
8410 (define_expand "movdi"
8411 [(set (match_operand:DI 0 "general_operand" "")
8412 (match_operand:DI 1 "any_operand" ""))]
8413 ""
8414 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
8416 (define_insn "*movdi_internal32"
8417 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
8418 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
8419 "! TARGET_POWERPC64
8420 && (gpc_reg_operand (operands[0], DImode)
8421 || gpc_reg_operand (operands[1], DImode))"
8422 "*
8423 {
8424 switch (which_alternative)
8425 {
8426 default:
8427 abort ();
8428 case 0:
8429 case 1:
8430 case 2:
8431 return \"#\";
8432 case 3:
8433 return \"fmr %0,%1\";
8434 case 4:
8435 return \"lfd%U1%X1 %0,%1\";
8436 case 5:
8437 return \"stfd%U0%X0 %1,%0\";
8438 case 6:
8439 case 7:
8440 case 8:
8441 case 9:
8442 case 10:
8443 return \"#\";
8444 }
8445 }"
8446 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")])
8448 (define_split
8449 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8450 (match_operand:DI 1 "const_int_operand" ""))]
8451 "! TARGET_POWERPC64 && reload_completed"
8452 [(set (match_dup 2) (match_dup 4))
8453 (set (match_dup 3) (match_dup 1))]
8454 "
8455 {
8456 HOST_WIDE_INT value = INTVAL (operands[1]);
8457 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8458 DImode);
8459 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8460 DImode);
8461 #if HOST_BITS_PER_WIDE_INT == 32
8462 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8463 #else
8464 operands[4] = GEN_INT (value >> 32);
8465 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8466 #endif
8467 }")
8469 (define_split
8470 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8471 (match_operand:DI 1 "input_operand" ""))]
8472 "reload_completed && !TARGET_POWERPC64
8473 && gpr_or_gpr_p (operands[0], operands[1])"
8474 [(pc)]
8475 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8477 (define_split
8478 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8479 (match_operand:TI 1 "const_double_operand" ""))]
8480 "TARGET_POWERPC64"
8481 [(set (match_dup 2) (match_dup 4))
8482 (set (match_dup 3) (match_dup 5))]
8483 "
8484 {
8485 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8486 TImode);
8487 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8488 TImode);
8489 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8490 {
8491 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8492 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8493 }
8494 else if (GET_CODE (operands[1]) == CONST_INT)
8495 {
8496 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8497 operands[5] = operands[1];
8498 }
8499 else
8500 FAIL;
8501 }")
8503 (define_insn "*movdi_internal64"
8504 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,?f,f,m,r,*h,*h")
8505 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8506 "TARGET_POWERPC64
8507 && (gpc_reg_operand (operands[0], DImode)
8508 || gpc_reg_operand (operands[1], DImode))"
8509 "@
8510 mr %0,%1
8511 ld%U1%X1 %0,%1
8512 std%U0%X0 %1,%0
8513 li %0,%1
8514 lis %0,%v1
8515 #
8516 {cal|la} %0,%a1
8517 fmr %0,%1
8518 lfd%U1%X1 %0,%1
8519 stfd%U0%X0 %1,%0
8520 mf%1 %0
8521 mt%0 %1
8522 {cror 0,0,0|nop}"
8523 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8524 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8526 ;; immediate value valid for a single instruction hiding in a const_double
8527 (define_insn ""
8528 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8529 (match_operand:DI 1 "const_double_operand" "F"))]
8530 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8531 && GET_CODE (operands[1]) == CONST_DOUBLE
8532 && num_insns_constant (operands[1], DImode) == 1"
8533 "*
8534 {
8535 return ((unsigned HOST_WIDE_INT)
8536 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8537 ? \"li %0,%1\" : \"lis %0,%v1\";
8538 }")
8540 ;; Generate all one-bits and clear left or right.
8541 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8542 (define_split
8543 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8544 (match_operand:DI 1 "mask64_operand" ""))]
8545 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8546 [(set (match_dup 0) (const_int -1))
8547 (set (match_dup 0)
8548 (and:DI (rotate:DI (match_dup 0)
8549 (const_int 0))
8550 (match_dup 1)))]
8551 "")
8553 ;; Split a load of a large constant into the appropriate five-instruction
8554 ;; sequence. Handle anything in a constant number of insns.
8555 ;; When non-easy constants can go in the TOC, this should use
8556 ;; easy_fp_constant predicate.
8557 (define_split
8558 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8559 (match_operand:DI 1 "const_int_operand" ""))]
8560 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8561 [(set (match_dup 0) (match_dup 2))
8562 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8563 "
8564 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8566 if (tem == operands[0])
8567 DONE;
8568 else
8569 FAIL;
8570 }")
8572 (define_split
8573 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8574 (match_operand:DI 1 "const_double_operand" ""))]
8575 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8576 [(set (match_dup 0) (match_dup 2))
8577 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8578 "
8579 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8581 if (tem == operands[0])
8582 DONE;
8583 else
8584 FAIL;
8585 }")
8587 (define_insn "*movdi_internal2"
8588 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8589 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r")
8590 (const_int 0)))
8591 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8592 "TARGET_64BIT"
8593 "@
8594 cmpdi %2,%0,0
8595 mr. %0,%1
8596 #"
8597 [(set_attr "type" "cmp,compare,cmp")
8598 (set_attr "length" "4,4,8")])
8600 (define_split
8601 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8602 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8603 (const_int 0)))
8604 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8605 "TARGET_POWERPC64 && reload_completed"
8606 [(set (match_dup 0) (match_dup 1))
8607 (set (match_dup 2)
8608 (compare:CC (match_dup 0)
8609 (const_int 0)))]
8610 "")
8611 \f
8612 ;; TImode is similar, except that we usually want to compute the address into
8613 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8614 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8615 (define_expand "movti"
8616 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8617 (match_operand:TI 1 "general_operand" ""))
8618 (clobber (scratch:SI))])]
8619 ""
8620 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
8622 ;; We say that MQ is clobbered in the last alternative because the first
8623 ;; alternative would never get used otherwise since it would need a reload
8624 ;; while the 2nd alternative would not. We put memory cases first so they
8625 ;; are preferred. Otherwise, we'd try to reload the output instead of
8626 ;; giving the SCRATCH mq.
8628 (define_insn "*movti_power"
8629 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8630 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
8631 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
8632 "TARGET_POWER && ! TARGET_POWERPC64
8633 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8634 "*
8635 {
8636 switch (which_alternative)
8637 {
8638 default:
8639 abort ();
8641 case 0:
8642 if (TARGET_STRING)
8643 return \"{stsi|stswi} %1,%P0,16\";
8644 case 1:
8645 case 2:
8646 return \"#\";
8647 case 3:
8648 /* If the address is not used in the output, we can use lsi. Otherwise,
8649 fall through to generating four loads. */
8650 if (TARGET_STRING
8651 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8652 return \"{lsi|lswi} %0,%P1,16\";
8653 /* ... fall through ... */
8654 case 4:
8655 return \"#\";
8656 }
8657 }"
8658 [(set_attr "type" "store,store,*,load,load")])
8660 (define_insn "*movti_string"
8661 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8662 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))]
8663 "! TARGET_POWER && ! TARGET_POWERPC64
8664 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8665 "*
8666 {
8667 switch (which_alternative)
8668 {
8669 default:
8670 abort ();
8671 case 0:
8672 if (TARGET_STRING)
8673 return \"{stsi|stswi} %1,%P0,16\";
8674 case 1:
8675 case 2:
8676 return \"#\";
8677 case 3:
8678 /* If the address is not used in the output, we can use lsi. Otherwise,
8679 fall through to generating four loads. */
8680 if (TARGET_STRING
8681 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8682 return \"{lsi|lswi} %0,%P1,16\";
8683 /* ... fall through ... */
8684 case 4:
8685 return \"#\";
8686 }
8687 }"
8688 [(set_attr "type" "store,store,*,load,load")])
8690 (define_insn "*movti_ppc64"
8691 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,m,r")
8692 (match_operand:TI 1 "input_operand" "r,r,o"))]
8693 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8694 || gpc_reg_operand (operands[1], TImode))"
8695 "@
8696 #
8697 #
8698 #"
8699 [(set_attr "type" "*,load,store")])
8701 (define_split
8702 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8703 (match_operand:TI 1 "input_operand" ""))]
8704 "reload_completed
8705 && gpr_or_gpr_p (operands[0], operands[1])"
8706 [(pc)]
8707 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8708 \f
8709 (define_expand "load_multiple"
8710 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8711 (match_operand:SI 1 "" ""))
8712 (use (match_operand:SI 2 "" ""))])]
8713 "TARGET_STRING && !TARGET_POWERPC64"
8714 "
8715 {
8716 int regno;
8717 int count;
8718 rtx op1;
8719 int i;
8721 /* Support only loading a constant number of fixed-point registers from
8722 memory and only bother with this if more than two; the machine
8723 doesn't support more than eight. */
8724 if (GET_CODE (operands[2]) != CONST_INT
8725 || INTVAL (operands[2]) <= 2
8726 || INTVAL (operands[2]) > 8
8727 || GET_CODE (operands[1]) != MEM
8728 || GET_CODE (operands[0]) != REG
8729 || REGNO (operands[0]) >= 32)
8730 FAIL;
8732 count = INTVAL (operands[2]);
8733 regno = REGNO (operands[0]);
8735 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8736 op1 = replace_equiv_address (operands[1],
8737 force_reg (SImode, XEXP (operands[1], 0)));
8739 for (i = 0; i < count; i++)
8740 XVECEXP (operands[3], 0, i)
8741 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8742 adjust_address_nv (op1, SImode, i * 4));
8743 }")
8745 (define_insn "*ldmsi8"
8746 [(match_parallel 0 "load_multiple_operation"
8747 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8748 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8749 (set (match_operand:SI 3 "gpc_reg_operand" "")
8750 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8751 (set (match_operand:SI 4 "gpc_reg_operand" "")
8752 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8753 (set (match_operand:SI 5 "gpc_reg_operand" "")
8754 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8755 (set (match_operand:SI 6 "gpc_reg_operand" "")
8756 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8757 (set (match_operand:SI 7 "gpc_reg_operand" "")
8758 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8759 (set (match_operand:SI 8 "gpc_reg_operand" "")
8760 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8761 (set (match_operand:SI 9 "gpc_reg_operand" "")
8762 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8763 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8764 "*
8765 { return rs6000_output_load_multiple (operands); }"
8766 [(set_attr "type" "load")
8767 (set_attr "length" "32")])
8769 (define_insn "*ldmsi7"
8770 [(match_parallel 0 "load_multiple_operation"
8771 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8772 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8773 (set (match_operand:SI 3 "gpc_reg_operand" "")
8774 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8775 (set (match_operand:SI 4 "gpc_reg_operand" "")
8776 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8777 (set (match_operand:SI 5 "gpc_reg_operand" "")
8778 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8779 (set (match_operand:SI 6 "gpc_reg_operand" "")
8780 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8781 (set (match_operand:SI 7 "gpc_reg_operand" "")
8782 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8783 (set (match_operand:SI 8 "gpc_reg_operand" "")
8784 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8785 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8786 "*
8787 { return rs6000_output_load_multiple (operands); }"
8788 [(set_attr "type" "load")
8789 (set_attr "length" "32")])
8791 (define_insn "*ldmsi6"
8792 [(match_parallel 0 "load_multiple_operation"
8793 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8794 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8795 (set (match_operand:SI 3 "gpc_reg_operand" "")
8796 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8797 (set (match_operand:SI 4 "gpc_reg_operand" "")
8798 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8799 (set (match_operand:SI 5 "gpc_reg_operand" "")
8800 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8801 (set (match_operand:SI 6 "gpc_reg_operand" "")
8802 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8803 (set (match_operand:SI 7 "gpc_reg_operand" "")
8804 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8805 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8806 "*
8807 { return rs6000_output_load_multiple (operands); }"
8808 [(set_attr "type" "load")
8809 (set_attr "length" "32")])
8811 (define_insn "*ldmsi5"
8812 [(match_parallel 0 "load_multiple_operation"
8813 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8814 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8815 (set (match_operand:SI 3 "gpc_reg_operand" "")
8816 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8817 (set (match_operand:SI 4 "gpc_reg_operand" "")
8818 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8819 (set (match_operand:SI 5 "gpc_reg_operand" "")
8820 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8821 (set (match_operand:SI 6 "gpc_reg_operand" "")
8822 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8823 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8824 "*
8825 { return rs6000_output_load_multiple (operands); }"
8826 [(set_attr "type" "load")
8827 (set_attr "length" "32")])
8829 (define_insn "*ldmsi4"
8830 [(match_parallel 0 "load_multiple_operation"
8831 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8832 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8833 (set (match_operand:SI 3 "gpc_reg_operand" "")
8834 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8835 (set (match_operand:SI 4 "gpc_reg_operand" "")
8836 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8837 (set (match_operand:SI 5 "gpc_reg_operand" "")
8838 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8839 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8840 "*
8841 { return rs6000_output_load_multiple (operands); }"
8842 [(set_attr "type" "load")
8843 (set_attr "length" "32")])
8845 (define_insn "*ldmsi3"
8846 [(match_parallel 0 "load_multiple_operation"
8847 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8848 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8849 (set (match_operand:SI 3 "gpc_reg_operand" "")
8850 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8851 (set (match_operand:SI 4 "gpc_reg_operand" "")
8852 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8853 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8854 "*
8855 { return rs6000_output_load_multiple (operands); }"
8856 [(set_attr "type" "load")
8857 (set_attr "length" "32")])
8859 (define_expand "store_multiple"
8860 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8861 (match_operand:SI 1 "" ""))
8862 (clobber (scratch:SI))
8863 (use (match_operand:SI 2 "" ""))])]
8864 "TARGET_STRING && !TARGET_POWERPC64"
8865 "
8866 {
8867 int regno;
8868 int count;
8869 rtx to;
8870 rtx op0;
8871 int i;
8873 /* Support only storing a constant number of fixed-point registers to
8874 memory and only bother with this if more than two; the machine
8875 doesn't support more than eight. */
8876 if (GET_CODE (operands[2]) != CONST_INT
8877 || INTVAL (operands[2]) <= 2
8878 || INTVAL (operands[2]) > 8
8879 || GET_CODE (operands[0]) != MEM
8880 || GET_CODE (operands[1]) != REG
8881 || REGNO (operands[1]) >= 32)
8882 FAIL;
8884 count = INTVAL (operands[2]);
8885 regno = REGNO (operands[1]);
8887 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8888 to = force_reg (SImode, XEXP (operands[0], 0));
8889 op0 = replace_equiv_address (operands[0], to);
8891 XVECEXP (operands[3], 0, 0)
8892 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8893 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8894 gen_rtx_SCRATCH (SImode));
8896 for (i = 1; i < count; i++)
8897 XVECEXP (operands[3], 0, i + 1)
8898 = gen_rtx_SET (VOIDmode,
8899 adjust_address_nv (op0, SImode, i * 4),
8900 gen_rtx_REG (SImode, regno + i));
8901 }")
8903 (define_insn "*store_multiple_power"
8904 [(match_parallel 0 "store_multiple_operation"
8905 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8906 (match_operand:SI 2 "gpc_reg_operand" "r"))
8907 (clobber (match_scratch:SI 3 "=q"))])]
8908 "TARGET_STRING && TARGET_POWER"
8909 "{stsi|stswi} %2,%P1,%O0"
8910 [(set_attr "type" "store")])
8912 (define_insn "*stmsi8"
8913 [(match_parallel 0 "store_multiple_operation"
8914 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8915 (match_operand:SI 2 "gpc_reg_operand" "r"))
8916 (clobber (match_scratch:SI 3 "X"))
8917 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8918 (match_operand:SI 4 "gpc_reg_operand" "r"))
8919 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8920 (match_operand:SI 5 "gpc_reg_operand" "r"))
8921 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8922 (match_operand:SI 6 "gpc_reg_operand" "r"))
8923 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8924 (match_operand:SI 7 "gpc_reg_operand" "r"))
8925 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8926 (match_operand:SI 8 "gpc_reg_operand" "r"))
8927 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8928 (match_operand:SI 9 "gpc_reg_operand" "r"))
8929 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8930 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8931 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8932 "{stsi|stswi} %2,%1,%O0"
8933 [(set_attr "type" "store")])
8935 (define_insn "*stmsi7"
8936 [(match_parallel 0 "store_multiple_operation"
8937 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8938 (match_operand:SI 2 "gpc_reg_operand" "r"))
8939 (clobber (match_scratch:SI 3 "X"))
8940 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8941 (match_operand:SI 4 "gpc_reg_operand" "r"))
8942 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8943 (match_operand:SI 5 "gpc_reg_operand" "r"))
8944 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8945 (match_operand:SI 6 "gpc_reg_operand" "r"))
8946 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8947 (match_operand:SI 7 "gpc_reg_operand" "r"))
8948 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8949 (match_operand:SI 8 "gpc_reg_operand" "r"))
8950 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8951 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8952 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8953 "{stsi|stswi} %2,%1,%O0"
8954 [(set_attr "type" "store")])
8956 (define_insn "*stmsi6"
8957 [(match_parallel 0 "store_multiple_operation"
8958 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8959 (match_operand:SI 2 "gpc_reg_operand" "r"))
8960 (clobber (match_scratch:SI 3 "X"))
8961 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8962 (match_operand:SI 4 "gpc_reg_operand" "r"))
8963 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8964 (match_operand:SI 5 "gpc_reg_operand" "r"))
8965 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8966 (match_operand:SI 6 "gpc_reg_operand" "r"))
8967 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8968 (match_operand:SI 7 "gpc_reg_operand" "r"))
8969 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8970 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8971 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8972 "{stsi|stswi} %2,%1,%O0"
8973 [(set_attr "type" "store")])
8975 (define_insn "*stmsi5"
8976 [(match_parallel 0 "store_multiple_operation"
8977 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8978 (match_operand:SI 2 "gpc_reg_operand" "r"))
8979 (clobber (match_scratch:SI 3 "X"))
8980 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8981 (match_operand:SI 4 "gpc_reg_operand" "r"))
8982 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8983 (match_operand:SI 5 "gpc_reg_operand" "r"))
8984 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8985 (match_operand:SI 6 "gpc_reg_operand" "r"))
8986 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8987 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8988 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
8989 "{stsi|stswi} %2,%1,%O0"
8990 [(set_attr "type" "store")])
8992 (define_insn "*stmsi4"
8993 [(match_parallel 0 "store_multiple_operation"
8994 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8995 (match_operand:SI 2 "gpc_reg_operand" "r"))
8996 (clobber (match_scratch:SI 3 "X"))
8997 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8998 (match_operand:SI 4 "gpc_reg_operand" "r"))
8999 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9000 (match_operand:SI 5 "gpc_reg_operand" "r"))
9001 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9002 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9003 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9004 "{stsi|stswi} %2,%1,%O0"
9005 [(set_attr "type" "store")])
9007 (define_insn "*stmsi3"
9008 [(match_parallel 0 "store_multiple_operation"
9009 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9010 (match_operand:SI 2 "gpc_reg_operand" "r"))
9011 (clobber (match_scratch:SI 3 "X"))
9012 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9013 (match_operand:SI 4 "gpc_reg_operand" "r"))
9014 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9015 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9016 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9017 "{stsi|stswi} %2,%1,%O0"
9018 [(set_attr "type" "store")])
9019 \f
9020 ;; String/block move insn.
9021 ;; Argument 0 is the destination
9022 ;; Argument 1 is the source
9023 ;; Argument 2 is the length
9024 ;; Argument 3 is the alignment
9026 (define_expand "movstrsi"
9027 [(parallel [(set (match_operand:BLK 0 "" "")
9028 (match_operand:BLK 1 "" ""))
9029 (use (match_operand:SI 2 "" ""))
9030 (use (match_operand:SI 3 "" ""))])]
9031 ""
9032 "
9033 {
9034 if (expand_block_move (operands))
9035 DONE;
9036 else
9037 FAIL;
9038 }")
9040 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9041 ;; register allocator doesn't have a clue about allocating 8 word registers.
9042 ;; rD/rS = r5 is preferred, efficient form.
9043 (define_expand "movstrsi_8reg"
9044 [(parallel [(set (match_operand 0 "" "")
9045 (match_operand 1 "" ""))
9046 (use (match_operand 2 "" ""))
9047 (use (match_operand 3 "" ""))
9048 (clobber (reg:SI 5))
9049 (clobber (reg:SI 6))
9050 (clobber (reg:SI 7))
9051 (clobber (reg:SI 8))
9052 (clobber (reg:SI 9))
9053 (clobber (reg:SI 10))
9054 (clobber (reg:SI 11))
9055 (clobber (reg:SI 12))
9056 (clobber (match_scratch:SI 4 ""))])]
9057 "TARGET_STRING"
9058 "")
9060 (define_insn ""
9061 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9062 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9063 (use (match_operand:SI 2 "immediate_operand" "i"))
9064 (use (match_operand:SI 3 "immediate_operand" "i"))
9065 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9066 (clobber (reg:SI 6))
9067 (clobber (reg:SI 7))
9068 (clobber (reg:SI 8))
9069 (clobber (reg:SI 9))
9070 (clobber (reg:SI 10))
9071 (clobber (reg:SI 11))
9072 (clobber (reg:SI 12))
9073 (clobber (match_scratch:SI 5 "=q"))]
9074 "TARGET_STRING && TARGET_POWER
9075 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9076 || INTVAL (operands[2]) == 0)
9077 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9078 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9079 && REGNO (operands[4]) == 5"
9080 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9081 [(set_attr "type" "load")
9082 (set_attr "length" "8")])
9084 (define_insn ""
9085 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9086 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9087 (use (match_operand:SI 2 "immediate_operand" "i"))
9088 (use (match_operand:SI 3 "immediate_operand" "i"))
9089 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9090 (clobber (reg:SI 6))
9091 (clobber (reg:SI 7))
9092 (clobber (reg:SI 8))
9093 (clobber (reg:SI 9))
9094 (clobber (reg:SI 10))
9095 (clobber (reg:SI 11))
9096 (clobber (reg:SI 12))
9097 (clobber (match_scratch:SI 5 "X"))]
9098 "TARGET_STRING && ! TARGET_POWER
9099 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9100 || INTVAL (operands[2]) == 0)
9101 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9102 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9103 && REGNO (operands[4]) == 5"
9104 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9105 [(set_attr "type" "load")
9106 (set_attr "length" "8")])
9108 (define_insn ""
9109 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9110 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9111 (use (match_operand:SI 2 "immediate_operand" "i"))
9112 (use (match_operand:SI 3 "immediate_operand" "i"))
9113 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9114 (clobber (reg:SI 6))
9115 (clobber (reg:SI 7))
9116 (clobber (reg:SI 8))
9117 (clobber (reg:SI 9))
9118 (clobber (reg:SI 10))
9119 (clobber (reg:SI 11))
9120 (clobber (reg:SI 12))
9121 (clobber (match_scratch:SI 5 "X"))]
9122 "TARGET_STRING && TARGET_POWERPC64
9123 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9124 || INTVAL (operands[2]) == 0)
9125 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9126 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9127 && REGNO (operands[4]) == 5"
9128 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9129 [(set_attr "type" "load")
9130 (set_attr "length" "8")])
9132 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9133 ;; register allocator doesn't have a clue about allocating 6 word registers.
9134 ;; rD/rS = r5 is preferred, efficient form.
9135 (define_expand "movstrsi_6reg"
9136 [(parallel [(set (match_operand 0 "" "")
9137 (match_operand 1 "" ""))
9138 (use (match_operand 2 "" ""))
9139 (use (match_operand 3 "" ""))
9140 (clobber (reg:SI 5))
9141 (clobber (reg:SI 6))
9142 (clobber (reg:SI 7))
9143 (clobber (reg:SI 8))
9144 (clobber (reg:SI 9))
9145 (clobber (reg:SI 10))
9146 (clobber (match_scratch:SI 4 ""))])]
9147 "TARGET_STRING"
9148 "")
9150 (define_insn ""
9151 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9152 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9153 (use (match_operand:SI 2 "immediate_operand" "i"))
9154 (use (match_operand:SI 3 "immediate_operand" "i"))
9155 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9156 (clobber (reg:SI 6))
9157 (clobber (reg:SI 7))
9158 (clobber (reg:SI 8))
9159 (clobber (reg:SI 9))
9160 (clobber (reg:SI 10))
9161 (clobber (match_scratch:SI 5 "=q"))]
9162 "TARGET_STRING && TARGET_POWER
9163 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9164 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9165 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9166 && REGNO (operands[4]) == 5"
9167 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9168 [(set_attr "type" "load")
9169 (set_attr "length" "8")])
9171 (define_insn ""
9172 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9173 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9174 (use (match_operand:SI 2 "immediate_operand" "i"))
9175 (use (match_operand:SI 3 "immediate_operand" "i"))
9176 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9177 (clobber (reg:SI 6))
9178 (clobber (reg:SI 7))
9179 (clobber (reg:SI 8))
9180 (clobber (reg:SI 9))
9181 (clobber (reg:SI 10))
9182 (clobber (match_scratch:SI 5 "X"))]
9183 "TARGET_STRING && ! TARGET_POWER
9184 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9185 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9186 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9187 && REGNO (operands[4]) == 5"
9188 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9189 [(set_attr "type" "load")
9190 (set_attr "length" "8")])
9192 (define_insn ""
9193 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9194 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9195 (use (match_operand:SI 2 "immediate_operand" "i"))
9196 (use (match_operand:SI 3 "immediate_operand" "i"))
9197 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9198 (clobber (reg:SI 6))
9199 (clobber (reg:SI 7))
9200 (clobber (reg:SI 8))
9201 (clobber (reg:SI 9))
9202 (clobber (reg:SI 10))
9203 (clobber (match_scratch:SI 5 "X"))]
9204 "TARGET_STRING && TARGET_POWERPC64
9205 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9206 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9207 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9208 && REGNO (operands[4]) == 5"
9209 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9210 [(set_attr "type" "load")
9211 (set_attr "length" "8")])
9213 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9214 ;; problems with TImode.
9215 ;; rD/rS = r5 is preferred, efficient form.
9216 (define_expand "movstrsi_4reg"
9217 [(parallel [(set (match_operand 0 "" "")
9218 (match_operand 1 "" ""))
9219 (use (match_operand 2 "" ""))
9220 (use (match_operand 3 "" ""))
9221 (clobber (reg:SI 5))
9222 (clobber (reg:SI 6))
9223 (clobber (reg:SI 7))
9224 (clobber (reg:SI 8))
9225 (clobber (match_scratch:SI 4 ""))])]
9226 "TARGET_STRING"
9227 "")
9229 (define_insn ""
9230 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9231 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9232 (use (match_operand:SI 2 "immediate_operand" "i"))
9233 (use (match_operand:SI 3 "immediate_operand" "i"))
9234 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9235 (clobber (reg:SI 6))
9236 (clobber (reg:SI 7))
9237 (clobber (reg:SI 8))
9238 (clobber (match_scratch:SI 5 "=q"))]
9239 "TARGET_STRING && TARGET_POWER
9240 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9241 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9242 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9243 && REGNO (operands[4]) == 5"
9244 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9245 [(set_attr "type" "load")
9246 (set_attr "length" "8")])
9248 (define_insn ""
9249 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9250 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9251 (use (match_operand:SI 2 "immediate_operand" "i"))
9252 (use (match_operand:SI 3 "immediate_operand" "i"))
9253 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9254 (clobber (reg:SI 6))
9255 (clobber (reg:SI 7))
9256 (clobber (reg:SI 8))
9257 (clobber (match_scratch:SI 5 "X"))]
9258 "TARGET_STRING && ! TARGET_POWER
9259 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9260 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9261 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9262 && REGNO (operands[4]) == 5"
9263 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9264 [(set_attr "type" "load")
9265 (set_attr "length" "8")])
9267 (define_insn ""
9268 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9269 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9270 (use (match_operand:SI 2 "immediate_operand" "i"))
9271 (use (match_operand:SI 3 "immediate_operand" "i"))
9272 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9273 (clobber (reg:SI 6))
9274 (clobber (reg:SI 7))
9275 (clobber (reg:SI 8))
9276 (clobber (match_scratch:SI 5 "X"))]
9277 "TARGET_STRING && TARGET_POWERPC64
9278 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9279 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9280 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9281 && REGNO (operands[4]) == 5"
9282 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9283 [(set_attr "type" "load")
9284 (set_attr "length" "8")])
9286 ;; Move up to 8 bytes at a time.
9287 (define_expand "movstrsi_2reg"
9288 [(parallel [(set (match_operand 0 "" "")
9289 (match_operand 1 "" ""))
9290 (use (match_operand 2 "" ""))
9291 (use (match_operand 3 "" ""))
9292 (clobber (match_scratch:DI 4 ""))
9293 (clobber (match_scratch:SI 5 ""))])]
9294 "TARGET_STRING && ! TARGET_POWERPC64"
9295 "")
9297 (define_insn ""
9298 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9299 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9300 (use (match_operand:SI 2 "immediate_operand" "i"))
9301 (use (match_operand:SI 3 "immediate_operand" "i"))
9302 (clobber (match_scratch:DI 4 "=&r"))
9303 (clobber (match_scratch:SI 5 "=q"))]
9304 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9305 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9306 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9307 [(set_attr "type" "load")
9308 (set_attr "length" "8")])
9310 (define_insn ""
9311 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9312 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9313 (use (match_operand:SI 2 "immediate_operand" "i"))
9314 (use (match_operand:SI 3 "immediate_operand" "i"))
9315 (clobber (match_scratch:DI 4 "=&r"))
9316 (clobber (match_scratch:SI 5 "X"))]
9317 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9318 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9319 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9320 [(set_attr "type" "load")
9321 (set_attr "length" "8")])
9323 ;; Move up to 4 bytes at a time.
9324 (define_expand "movstrsi_1reg"
9325 [(parallel [(set (match_operand 0 "" "")
9326 (match_operand 1 "" ""))
9327 (use (match_operand 2 "" ""))
9328 (use (match_operand 3 "" ""))
9329 (clobber (match_scratch:SI 4 ""))
9330 (clobber (match_scratch:SI 5 ""))])]
9331 "TARGET_STRING"
9332 "")
9334 (define_insn ""
9335 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9336 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9337 (use (match_operand:SI 2 "immediate_operand" "i"))
9338 (use (match_operand:SI 3 "immediate_operand" "i"))
9339 (clobber (match_scratch:SI 4 "=&r"))
9340 (clobber (match_scratch:SI 5 "=q"))]
9341 "TARGET_STRING && TARGET_POWER
9342 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9343 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9344 [(set_attr "type" "load")
9345 (set_attr "length" "8")])
9347 (define_insn ""
9348 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9349 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9350 (use (match_operand:SI 2 "immediate_operand" "i"))
9351 (use (match_operand:SI 3 "immediate_operand" "i"))
9352 (clobber (match_scratch:SI 4 "=&r"))
9353 (clobber (match_scratch:SI 5 "X"))]
9354 "TARGET_STRING && ! TARGET_POWER
9355 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9356 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9357 [(set_attr "type" "load")
9358 (set_attr "length" "8")])
9360 (define_insn ""
9361 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9362 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9363 (use (match_operand:SI 2 "immediate_operand" "i"))
9364 (use (match_operand:SI 3 "immediate_operand" "i"))
9365 (clobber (match_scratch:SI 4 "=&r"))
9366 (clobber (match_scratch:SI 5 "X"))]
9367 "TARGET_STRING && TARGET_POWERPC64
9368 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9369 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9370 [(set_attr "type" "load")
9371 (set_attr "length" "8")])
9373 \f
9374 ;; Define insns that do load or store with update. Some of these we can
9375 ;; get by using pre-decrement or pre-increment, but the hardware can also
9376 ;; do cases where the increment is not the size of the object.
9377 ;;
9378 ;; In all these cases, we use operands 0 and 1 for the register being
9379 ;; incremented because those are the operands that local-alloc will
9380 ;; tie and these are the pair most likely to be tieable (and the ones
9381 ;; that will benefit the most).
9383 (define_insn "*movdi_update1"
9384 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9385 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9386 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9387 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9388 (plus:DI (match_dup 1) (match_dup 2)))]
9389 "TARGET_POWERPC64 && TARGET_UPDATE"
9390 "@
9391 ldux %3,%0,%2
9392 ldu %3,%2(%0)"
9393 [(set_attr "type" "load_ux,load_u")])
9395 (define_insn "movdi_update"
9396 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9397 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))
9398 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9399 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9400 (plus:DI (match_dup 1) (match_dup 2)))]
9401 "TARGET_POWERPC64 && TARGET_UPDATE"
9402 "@
9403 stdux %3,%0,%2
9404 stdu %3,%2(%0)"
9405 [(set_attr "type" "store_ux,store_u")])
9407 (define_insn "*movsi_update1"
9408 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9409 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9410 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9411 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9412 (plus:SI (match_dup 1) (match_dup 2)))]
9413 "TARGET_UPDATE"
9414 "@
9415 {lux|lwzux} %3,%0,%2
9416 {lu|lwzu} %3,%2(%0)"
9417 [(set_attr "type" "load_ux,load_u")])
9419 (define_insn "*movsi_update2"
9420 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9421 (sign_extend:DI
9422 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9423 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9424 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9425 (plus:DI (match_dup 1) (match_dup 2)))]
9426 "TARGET_POWERPC64"
9427 "lwaux %3,%0,%2"
9428 [(set_attr "type" "load_ext_ux")])
9430 (define_insn "movsi_update"
9431 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9432 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9433 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9434 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9435 (plus:SI (match_dup 1) (match_dup 2)))]
9436 "TARGET_UPDATE"
9437 "@
9438 {stux|stwux} %3,%0,%2
9439 {stu|stwu} %3,%2(%0)"
9440 [(set_attr "type" "store_ux,store_u")])
9442 (define_insn "*movhi_update1"
9443 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9444 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9445 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9446 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9447 (plus:SI (match_dup 1) (match_dup 2)))]
9448 "TARGET_UPDATE"
9449 "@
9450 lhzux %3,%0,%2
9451 lhzu %3,%2(%0)"
9452 [(set_attr "type" "load_ux,load_u")])
9454 (define_insn "*movhi_update2"
9455 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9456 (zero_extend:SI
9457 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9458 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9459 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9460 (plus:SI (match_dup 1) (match_dup 2)))]
9461 "TARGET_UPDATE"
9462 "@
9463 lhzux %3,%0,%2
9464 lhzu %3,%2(%0)"
9465 [(set_attr "type" "load_ux,load_u")])
9467 (define_insn "*movhi_update3"
9468 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9469 (sign_extend:SI
9470 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9471 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9472 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9473 (plus:SI (match_dup 1) (match_dup 2)))]
9474 "TARGET_UPDATE"
9475 "@
9476 lhaux %3,%0,%2
9477 lhau %3,%2(%0)"
9478 [(set_attr "type" "load_ext_ux,load_ext_u")])
9480 (define_insn "*movhi_update4"
9481 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9482 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9483 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9484 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9485 (plus:SI (match_dup 1) (match_dup 2)))]
9486 "TARGET_UPDATE"
9487 "@
9488 sthux %3,%0,%2
9489 sthu %3,%2(%0)"
9490 [(set_attr "type" "store_ux,store_u")])
9492 (define_insn "*movqi_update1"
9493 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9494 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9495 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9496 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9497 (plus:SI (match_dup 1) (match_dup 2)))]
9498 "TARGET_UPDATE"
9499 "@
9500 lbzux %3,%0,%2
9501 lbzu %3,%2(%0)"
9502 [(set_attr "type" "load_ux,load_u")])
9504 (define_insn "*movqi_update2"
9505 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9506 (zero_extend:SI
9507 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9508 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9509 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9510 (plus:SI (match_dup 1) (match_dup 2)))]
9511 "TARGET_UPDATE"
9512 "@
9513 lbzux %3,%0,%2
9514 lbzu %3,%2(%0)"
9515 [(set_attr "type" "load_ux,load_u")])
9517 (define_insn "*movqi_update3"
9518 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9519 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9520 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9521 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9522 (plus:SI (match_dup 1) (match_dup 2)))]
9523 "TARGET_UPDATE"
9524 "@
9525 stbux %3,%0,%2
9526 stbu %3,%2(%0)"
9527 [(set_attr "type" "store_ux,store_u")])
9529 (define_insn "*movsf_update1"
9530 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9531 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9532 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9533 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9534 (plus:SI (match_dup 1) (match_dup 2)))]
9535 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9536 "@
9537 lfsux %3,%0,%2
9538 lfsu %3,%2(%0)"
9539 [(set_attr "type" "fpload_ux,fpload_u")])
9541 (define_insn "*movsf_update2"
9542 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9543 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9544 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9545 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9546 (plus:SI (match_dup 1) (match_dup 2)))]
9547 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9548 "@
9549 stfsux %3,%0,%2
9550 stfsu %3,%2(%0)"
9551 [(set_attr "type" "fpstore_ux,fpstore_u")])
9553 (define_insn "*movsf_update3"
9554 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9555 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9556 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9557 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9558 (plus:SI (match_dup 1) (match_dup 2)))]
9559 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9560 "@
9561 {lux|lwzux} %3,%0,%2
9562 {lu|lwzu} %3,%2(%0)"
9563 [(set_attr "type" "load_ux,load_u")])
9565 (define_insn "*movsf_update4"
9566 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9567 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9568 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9569 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9570 (plus:SI (match_dup 1) (match_dup 2)))]
9571 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9572 "@
9573 {stux|stwux} %3,%0,%2
9574 {stu|stwu} %3,%2(%0)"
9575 [(set_attr "type" "store_ux,store_u")])
9577 (define_insn "*movdf_update1"
9578 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9579 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9580 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9581 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9582 (plus:SI (match_dup 1) (match_dup 2)))]
9583 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9584 "@
9585 lfdux %3,%0,%2
9586 lfdu %3,%2(%0)"
9587 [(set_attr "type" "fpload_ux,fpload_u")])
9589 (define_insn "*movdf_update2"
9590 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9591 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9592 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9593 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9594 (plus:SI (match_dup 1) (match_dup 2)))]
9595 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9596 "@
9597 stfdux %3,%0,%2
9598 stfdu %3,%2(%0)"
9599 [(set_attr "type" "fpstore_ux,fpstore_u")])
9601 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9603 (define_peephole
9604 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
9605 (match_operand:DF 1 "memory_operand" ""))
9606 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
9607 (match_operand:DF 3 "memory_operand" ""))]
9608 "TARGET_POWER2
9609 && TARGET_HARD_FLOAT && TARGET_FPRS
9610 && registers_ok_for_quad_peep (operands[0], operands[2])
9611 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
9612 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
9613 "lfq%U1%X1 %0,%1")
9615 (define_peephole
9616 [(set (match_operand:DF 0 "memory_operand" "")
9617 (match_operand:DF 1 "gpc_reg_operand" "f"))
9618 (set (match_operand:DF 2 "memory_operand" "")
9619 (match_operand:DF 3 "gpc_reg_operand" "f"))]
9620 "TARGET_POWER2
9621 && TARGET_HARD_FLOAT && TARGET_FPRS
9622 && registers_ok_for_quad_peep (operands[1], operands[3])
9623 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
9624 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
9625 "stfq%U0%X0 %1,%0")
9626 \f
9627 ;; TLS support.
9629 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9630 (define_insn "tls_gd_32"
9631 [(set (match_operand:SI 0 "register_operand" "=b")
9632 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9633 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9634 UNSPEC_TLSGD))]
9635 "HAVE_AS_TLS && !TARGET_64BIT"
9636 "addi %0,%1,%2@got@tlsgd")
9638 (define_insn "tls_gd_64"
9639 [(set (match_operand:DI 0 "register_operand" "=b")
9640 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9641 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9642 UNSPEC_TLSGD))]
9643 "HAVE_AS_TLS && TARGET_64BIT"
9644 "addi %0,%1,%2@got@tlsgd")
9646 (define_insn "tls_ld_32"
9647 [(set (match_operand:SI 0 "register_operand" "=b")
9648 (unspec:SI [(match_operand:SI 1 "register_operand" "b")]
9649 UNSPEC_TLSLD))]
9650 "HAVE_AS_TLS && !TARGET_64BIT"
9651 "addi %0,%1,%&@got@tlsld")
9653 (define_insn "tls_ld_64"
9654 [(set (match_operand:DI 0 "register_operand" "=b")
9655 (unspec:DI [(match_operand:DI 1 "register_operand" "b")]
9656 UNSPEC_TLSLD))]
9657 "HAVE_AS_TLS && TARGET_64BIT"
9658 "addi %0,%1,%&@got@tlsld")
9660 (define_insn "tls_dtprel_32"
9661 [(set (match_operand:SI 0 "register_operand" "=r")
9662 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9663 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9664 UNSPEC_TLSDTPREL))]
9665 "HAVE_AS_TLS && !TARGET_64BIT"
9666 "addi %0,%1,%2@dtprel")
9668 (define_insn "tls_dtprel_64"
9669 [(set (match_operand:DI 0 "register_operand" "=r")
9670 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9671 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9672 UNSPEC_TLSDTPREL))]
9673 "HAVE_AS_TLS && TARGET_64BIT"
9674 "addi %0,%1,%2@dtprel")
9676 (define_insn "tls_dtprel_ha_32"
9677 [(set (match_operand:SI 0 "register_operand" "=r")
9678 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9679 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9680 UNSPEC_TLSDTPRELHA))]
9681 "HAVE_AS_TLS && !TARGET_64BIT"
9682 "addis %0,%1,%2@dtprel@ha")
9684 (define_insn "tls_dtprel_ha_64"
9685 [(set (match_operand:DI 0 "register_operand" "=r")
9686 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9687 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9688 UNSPEC_TLSDTPRELHA))]
9689 "HAVE_AS_TLS && TARGET_64BIT"
9690 "addis %0,%1,%2@dtprel@ha")
9692 (define_insn "tls_dtprel_lo_32"
9693 [(set (match_operand:SI 0 "register_operand" "=r")
9694 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9695 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9696 UNSPEC_TLSDTPRELLO))]
9697 "HAVE_AS_TLS && !TARGET_64BIT"
9698 "addi %0,%1,%2@dtprel@l")
9700 (define_insn "tls_dtprel_lo_64"
9701 [(set (match_operand:DI 0 "register_operand" "=r")
9702 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9703 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9704 UNSPEC_TLSDTPRELLO))]
9705 "HAVE_AS_TLS && TARGET_64BIT"
9706 "addi %0,%1,%2@dtprel@l")
9708 (define_insn "tls_got_dtprel_32"
9709 [(set (match_operand:SI 0 "register_operand" "=r")
9710 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9711 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9712 UNSPEC_TLSGOTDTPREL))]
9713 "HAVE_AS_TLS && !TARGET_64BIT"
9714 "lwz %0,%2@got@dtprel(%1)")
9716 (define_insn "tls_got_dtprel_64"
9717 [(set (match_operand:DI 0 "register_operand" "=r")
9718 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9719 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9720 UNSPEC_TLSGOTDTPREL))]
9721 "HAVE_AS_TLS && TARGET_64BIT"
9722 "ld %0,%2@got@dtprel(%1)")
9724 (define_insn "tls_tprel_32"
9725 [(set (match_operand:SI 0 "register_operand" "=r")
9726 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9727 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9728 UNSPEC_TLSTPREL))]
9729 "HAVE_AS_TLS && !TARGET_64BIT"
9730 "addi %0,%1,%2@tprel")
9732 (define_insn "tls_tprel_64"
9733 [(set (match_operand:DI 0 "register_operand" "=r")
9734 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9735 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9736 UNSPEC_TLSTPREL))]
9737 "HAVE_AS_TLS && TARGET_64BIT"
9738 "addi %0,%1,%2@tprel")
9740 (define_insn "tls_tprel_ha_32"
9741 [(set (match_operand:SI 0 "register_operand" "=r")
9742 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9743 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9744 UNSPEC_TLSTPRELHA))]
9745 "HAVE_AS_TLS && !TARGET_64BIT"
9746 "addis %0,%1,%2@tprel@ha")
9748 (define_insn "tls_tprel_ha_64"
9749 [(set (match_operand:DI 0 "register_operand" "=r")
9750 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9751 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9752 UNSPEC_TLSTPRELHA))]
9753 "HAVE_AS_TLS && TARGET_64BIT"
9754 "addis %0,%1,%2@tprel@ha")
9756 (define_insn "tls_tprel_lo_32"
9757 [(set (match_operand:SI 0 "register_operand" "=r")
9758 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9759 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9760 UNSPEC_TLSTPRELLO))]
9761 "HAVE_AS_TLS && !TARGET_64BIT"
9762 "addi %0,%1,%2@tprel@l")
9764 (define_insn "tls_tprel_lo_64"
9765 [(set (match_operand:DI 0 "register_operand" "=r")
9766 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9767 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9768 UNSPEC_TLSTPRELLO))]
9769 "HAVE_AS_TLS && TARGET_64BIT"
9770 "addi %0,%1,%2@tprel@l")
9772 ;; "b" output constraint here and on tls_tls input to support linker tls
9773 ;; optimization. The linker may edit the instructions emitted by a
9774 ;; tls_got_tprel/tls_tls pair to addis,addi.
9775 (define_insn "tls_got_tprel_32"
9776 [(set (match_operand:SI 0 "register_operand" "=b")
9777 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9778 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9779 UNSPEC_TLSGOTTPREL))]
9780 "HAVE_AS_TLS && !TARGET_64BIT"
9781 "lwz %0,%2@got@tprel(%1)")
9783 (define_insn "tls_got_tprel_64"
9784 [(set (match_operand:DI 0 "register_operand" "=b")
9785 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9786 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9787 UNSPEC_TLSGOTTPREL))]
9788 "HAVE_AS_TLS && TARGET_64BIT"
9789 "ld %0,%2@got@tprel(%1)")
9791 (define_insn "tls_tls_32"
9792 [(set (match_operand:SI 0 "register_operand" "=r")
9793 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9794 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9795 UNSPEC_TLSTLS))]
9796 "HAVE_AS_TLS && !TARGET_64BIT"
9797 "add %0,%1,%2@tls")
9799 (define_insn "tls_tls_64"
9800 [(set (match_operand:DI 0 "register_operand" "=r")
9801 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9802 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9803 UNSPEC_TLSTLS))]
9804 "HAVE_AS_TLS && TARGET_64BIT"
9805 "add %0,%1,%2@tls")
9806 \f
9807 ;; Next come insns related to the calling sequence.
9808 ;;
9809 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9810 ;; We move the back-chain and decrement the stack pointer.
9812 (define_expand "allocate_stack"
9813 [(set (match_operand 0 "gpc_reg_operand" "=r")
9814 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9815 (set (reg 1)
9816 (minus (reg 1) (match_dup 1)))]
9817 ""
9818 "
9819 { rtx chain = gen_reg_rtx (Pmode);
9820 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9821 rtx neg_op0;
9823 emit_move_insn (chain, stack_bot);
9825 /* Check stack bounds if necessary. */
9826 if (current_function_limit_stack)
9827 {
9828 rtx available;
9829 available = expand_binop (Pmode, sub_optab,
9830 stack_pointer_rtx, stack_limit_rtx,
9831 NULL_RTX, 1, OPTAB_WIDEN);
9832 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9833 }
9835 if (GET_CODE (operands[1]) != CONST_INT
9836 || INTVAL (operands[1]) < -32767
9837 || INTVAL (operands[1]) > 32768)
9838 {
9839 neg_op0 = gen_reg_rtx (Pmode);
9840 if (TARGET_32BIT)
9841 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9842 else
9843 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9844 }
9845 else
9846 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9848 if (TARGET_UPDATE)
9849 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
9850 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9852 else
9853 {
9854 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9855 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9856 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9857 }
9859 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9860 DONE;
9861 }")
9863 ;; These patterns say how to save and restore the stack pointer. We need not
9864 ;; save the stack pointer at function level since we are careful to
9865 ;; preserve the backchain. At block level, we have to restore the backchain
9866 ;; when we restore the stack pointer.
9867 ;;
9868 ;; For nonlocal gotos, we must save both the stack pointer and its
9869 ;; backchain and restore both. Note that in the nonlocal case, the
9870 ;; save area is a memory location.
9872 (define_expand "save_stack_function"
9873 [(match_operand 0 "any_operand" "")
9874 (match_operand 1 "any_operand" "")]
9875 ""
9876 "DONE;")
9878 (define_expand "restore_stack_function"
9879 [(match_operand 0 "any_operand" "")
9880 (match_operand 1 "any_operand" "")]
9881 ""
9882 "DONE;")
9884 (define_expand "restore_stack_block"
9885 [(use (match_operand 0 "register_operand" ""))
9886 (set (match_dup 2) (match_dup 3))
9887 (set (match_dup 0) (match_operand 1 "register_operand" ""))
9888 (set (match_dup 3) (match_dup 2))]
9889 ""
9890 "
9891 {
9892 operands[2] = gen_reg_rtx (Pmode);
9893 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
9894 }")
9896 (define_expand "save_stack_nonlocal"
9897 [(match_operand 0 "memory_operand" "")
9898 (match_operand 1 "register_operand" "")]
9899 ""
9900 "
9901 {
9902 rtx temp = gen_reg_rtx (Pmode);
9903 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9905 /* Copy the backchain to the first word, sp to the second. */
9906 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
9907 emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp);
9908 emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word),
9909 operands[1]);
9910 DONE;
9911 }")
9913 (define_expand "restore_stack_nonlocal"
9914 [(match_operand 0 "register_operand" "")
9915 (match_operand 1 "memory_operand" "")]
9916 ""
9917 "
9918 {
9919 rtx temp = gen_reg_rtx (Pmode);
9920 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9922 /* Restore the backchain from the first word, sp from the second. */
9923 emit_move_insn (temp,
9924 adjust_address_nv (operands[1], Pmode, 0));
9925 emit_move_insn (operands[0],
9926 adjust_address_nv (operands[1], Pmode, units_per_word));
9927 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
9928 DONE;
9929 }")
9930 \f
9931 ;; TOC register handling.
9933 ;; Code to initialize the TOC register...
9935 (define_insn "load_toc_aix_si"
9936 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9937 (unspec:SI [(const_int 0)] UNSPEC_TOC))
9938 (use (reg:SI 2))])]
9939 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
9940 "*
9941 {
9942 char buf[30];
9943 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9944 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9945 operands[2] = gen_rtx_REG (Pmode, 2);
9946 return \"{l|lwz} %0,%1(%2)\";
9947 }"
9948 [(set_attr "type" "load")])
9950 (define_insn "load_toc_aix_di"
9951 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9952 (unspec:DI [(const_int 0)] UNSPEC_TOC))
9953 (use (reg:DI 2))])]
9954 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9955 "*
9956 {
9957 char buf[30];
9958 #ifdef TARGET_RELOCATABLE
9959 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9960 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
9961 #else
9962 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9963 #endif
9964 if (TARGET_ELF)
9965 strcat (buf, \"@toc\");
9966 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9967 operands[2] = gen_rtx_REG (Pmode, 2);
9968 return \"ld %0,%1(%2)\";
9969 }"
9970 [(set_attr "type" "load")])
9972 (define_insn "load_toc_v4_pic_si"
9973 [(set (match_operand:SI 0 "register_operand" "=l")
9974 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
9975 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9976 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9977 [(set_attr "type" "branch")
9978 (set_attr "length" "4")])
9980 (define_insn "load_toc_v4_PIC_1"
9981 [(set (match_operand:SI 0 "register_operand" "=l")
9982 (match_operand:SI 1 "immediate_operand" "s"))
9983 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
9984 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9985 "bcl 20,31,%1\\n%1:"
9986 [(set_attr "type" "branch")
9987 (set_attr "length" "4")])
9989 (define_insn "load_toc_v4_PIC_1b"
9990 [(set (match_operand:SI 0 "register_operand" "=l")
9991 (match_operand:SI 1 "immediate_operand" "s"))
9992 (use (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")]
9993 UNSPEC_TOCPTR))]
9994 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9995 "bcl 20,31,%1+4\\n%1:\\n\\t.long %2-%1"
9996 [(set_attr "type" "branch")
9997 (set_attr "length" "8")])
9999 (define_insn "load_toc_v4_PIC_2"
10000 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10001 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10002 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10003 (match_operand:SI 3 "immediate_operand" "s")))))]
10004 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10005 "{l|lwz} %0,%2-%3(%1)"
10006 [(set_attr "type" "load")])
10008 (define_insn "load_macho_picbase"
10009 [(set (match_operand:SI 0 "register_operand" "=l")
10010 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
10011 UNSPEC_LD_MPIC))]
10012 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
10013 "bcl 20,31,%1\\n%1:"
10014 [(set_attr "type" "branch")
10015 (set_attr "length" "4")])
10017 (define_insn "macho_correct_pic"
10018 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10019 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10020 (unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
10021 (match_operand:SI 3 "immediate_operand" "s")]
10022 UNSPEC_MPIC_CORRECT)))]
10023 "DEFAULT_ABI == ABI_DARWIN"
10024 "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
10025 [(set_attr "length" "8")])
10027 ;; If the TOC is shared over a translation unit, as happens with all
10028 ;; the kinds of PIC that we support, we need to restore the TOC
10029 ;; pointer only when jumping over units of translation.
10030 ;; On Darwin, we need to reload the picbase.
10032 (define_expand "builtin_setjmp_receiver"
10033 [(use (label_ref (match_operand 0 "" "")))]
10034 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10035 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10036 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10037 "
10038 {
10039 #if TARGET_MACHO
10040 if (DEFAULT_ABI == ABI_DARWIN)
10041 {
10042 const char *picbase = machopic_function_base_name ();
10043 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10044 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10045 rtx tmplabrtx;
10046 char tmplab[20];
10048 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10049 CODE_LABEL_NUMBER (operands[0]));
10050 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10052 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10053 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10054 }
10055 else
10056 #endif
10057 rs6000_emit_load_toc_table (FALSE);
10058 DONE;
10059 }")
10060 \f
10061 ;; A function pointer under AIX is a pointer to a data area whose first word
10062 ;; contains the actual address of the function, whose second word contains a
10063 ;; pointer to its TOC, and whose third word contains a value to place in the
10064 ;; static chain register (r11). Note that if we load the static chain, our
10065 ;; "trampoline" need not have any executable code.
10067 (define_expand "call_indirect_aix32"
10068 [(set (match_dup 2)
10069 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10070 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10071 (reg:SI 2))
10072 (set (reg:SI 2)
10073 (mem:SI (plus:SI (match_dup 0)
10074 (const_int 4))))
10075 (set (reg:SI 11)
10076 (mem:SI (plus:SI (match_dup 0)
10077 (const_int 8))))
10078 (parallel [(call (mem:SI (match_dup 2))
10079 (match_operand 1 "" ""))
10080 (use (reg:SI 2))
10081 (use (reg:SI 11))
10082 (set (reg:SI 2)
10083 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10084 (clobber (scratch:SI))])]
10085 "TARGET_32BIT"
10086 "
10087 { operands[2] = gen_reg_rtx (SImode); }")
10089 (define_expand "call_indirect_aix64"
10090 [(set (match_dup 2)
10091 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10092 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10093 (reg:DI 2))
10094 (set (reg:DI 2)
10095 (mem:DI (plus:DI (match_dup 0)
10096 (const_int 8))))
10097 (set (reg:DI 11)
10098 (mem:DI (plus:DI (match_dup 0)
10099 (const_int 16))))
10100 (parallel [(call (mem:SI (match_dup 2))
10101 (match_operand 1 "" ""))
10102 (use (reg:DI 2))
10103 (use (reg:DI 11))
10104 (set (reg:DI 2)
10105 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10106 (clobber (scratch:SI))])]
10107 "TARGET_64BIT"
10108 "
10109 { operands[2] = gen_reg_rtx (DImode); }")
10111 (define_expand "call_value_indirect_aix32"
10112 [(set (match_dup 3)
10113 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10114 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10115 (reg:SI 2))
10116 (set (reg:SI 2)
10117 (mem:SI (plus:SI (match_dup 1)
10118 (const_int 4))))
10119 (set (reg:SI 11)
10120 (mem:SI (plus:SI (match_dup 1)
10121 (const_int 8))))
10122 (parallel [(set (match_operand 0 "" "")
10123 (call (mem:SI (match_dup 3))
10124 (match_operand 2 "" "")))
10125 (use (reg:SI 2))
10126 (use (reg:SI 11))
10127 (set (reg:SI 2)
10128 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10129 (clobber (scratch:SI))])]
10130 "TARGET_32BIT"
10131 "
10132 { operands[3] = gen_reg_rtx (SImode); }")
10134 (define_expand "call_value_indirect_aix64"
10135 [(set (match_dup 3)
10136 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10137 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10138 (reg:DI 2))
10139 (set (reg:DI 2)
10140 (mem:DI (plus:DI (match_dup 1)
10141 (const_int 8))))
10142 (set (reg:DI 11)
10143 (mem:DI (plus:DI (match_dup 1)
10144 (const_int 16))))
10145 (parallel [(set (match_operand 0 "" "")
10146 (call (mem:SI (match_dup 3))
10147 (match_operand 2 "" "")))
10148 (use (reg:DI 2))
10149 (use (reg:DI 11))
10150 (set (reg:DI 2)
10151 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10152 (clobber (scratch:SI))])]
10153 "TARGET_64BIT"
10154 "
10155 { operands[3] = gen_reg_rtx (DImode); }")
10157 ;; Now the definitions for the call and call_value insns
10158 (define_expand "call"
10159 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10160 (match_operand 1 "" ""))
10161 (use (match_operand 2 "" ""))
10162 (clobber (scratch:SI))])]
10163 ""
10164 "
10165 {
10166 #if TARGET_MACHO
10167 if (MACHOPIC_INDIRECT)
10168 operands[0] = machopic_indirect_call_target (operands[0]);
10169 #endif
10171 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10172 abort ();
10174 operands[0] = XEXP (operands[0], 0);
10176 if (GET_CODE (operands[0]) != SYMBOL_REF
10177 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10178 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10179 {
10180 if (INTVAL (operands[2]) & CALL_LONG)
10181 operands[0] = rs6000_longcall_ref (operands[0]);
10183 if (DEFAULT_ABI == ABI_V4
10184 || DEFAULT_ABI == ABI_DARWIN)
10185 operands[0] = force_reg (Pmode, operands[0]);
10187 else if (DEFAULT_ABI == ABI_AIX)
10188 {
10189 /* AIX function pointers are really pointers to a three word
10190 area. */
10191 emit_call_insn (TARGET_32BIT
10192 ? gen_call_indirect_aix32 (force_reg (SImode,
10193 operands[0]),
10194 operands[1])
10195 : gen_call_indirect_aix64 (force_reg (DImode,
10196 operands[0]),
10197 operands[1]));
10198 DONE;
10199 }
10200 else
10201 abort ();
10202 }
10203 }")
10205 (define_expand "call_value"
10206 [(parallel [(set (match_operand 0 "" "")
10207 (call (mem:SI (match_operand 1 "address_operand" ""))
10208 (match_operand 2 "" "")))
10209 (use (match_operand 3 "" ""))
10210 (clobber (scratch:SI))])]
10211 ""
10212 "
10213 {
10214 #if TARGET_MACHO
10215 if (MACHOPIC_INDIRECT)
10216 operands[1] = machopic_indirect_call_target (operands[1]);
10217 #endif
10219 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10220 abort ();
10222 operands[1] = XEXP (operands[1], 0);
10224 if (GET_CODE (operands[1]) != SYMBOL_REF
10225 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10226 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10227 {
10228 if (INTVAL (operands[3]) & CALL_LONG)
10229 operands[1] = rs6000_longcall_ref (operands[1]);
10231 if (DEFAULT_ABI == ABI_V4
10232 || DEFAULT_ABI == ABI_DARWIN)
10233 operands[1] = force_reg (Pmode, operands[1]);
10235 else if (DEFAULT_ABI == ABI_AIX)
10236 {
10237 /* AIX function pointers are really pointers to a three word
10238 area. */
10239 emit_call_insn (TARGET_32BIT
10240 ? gen_call_value_indirect_aix32 (operands[0],
10241 force_reg (SImode,
10242 operands[1]),
10243 operands[2])
10244 : gen_call_value_indirect_aix64 (operands[0],
10245 force_reg (DImode,
10246 operands[1]),
10247 operands[2]));
10248 DONE;
10249 }
10250 else
10251 abort ();
10252 }
10253 }")
10255 ;; Call to function in current module. No TOC pointer reload needed.
10256 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10257 ;; either the function was not prototyped, or it was prototyped as a
10258 ;; variable argument function. It is > 0 if FP registers were passed
10259 ;; and < 0 if they were not.
10261 (define_insn "*call_local32"
10262 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10263 (match_operand 1 "" "g,g"))
10264 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10265 (clobber (match_scratch:SI 3 "=l,l"))]
10266 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10267 "*
10268 {
10269 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10270 output_asm_insn (\"crxor 6,6,6\", operands);
10272 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10273 output_asm_insn (\"creqv 6,6,6\", operands);
10275 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10276 }"
10277 [(set_attr "type" "branch")
10278 (set_attr "length" "4,8")])
10280 (define_insn "*call_local64"
10281 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10282 (match_operand 1 "" "g,g"))
10283 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10284 (clobber (match_scratch:SI 3 "=l,l"))]
10285 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10286 "*
10287 {
10288 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10289 output_asm_insn (\"crxor 6,6,6\", operands);
10291 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10292 output_asm_insn (\"creqv 6,6,6\", operands);
10294 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10295 }"
10296 [(set_attr "type" "branch")
10297 (set_attr "length" "4,8")])
10299 (define_insn "*call_value_local32"
10300 [(set (match_operand 0 "" "")
10301 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10302 (match_operand 2 "" "g,g")))
10303 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10304 (clobber (match_scratch:SI 4 "=l,l"))]
10305 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10306 "*
10307 {
10308 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10309 output_asm_insn (\"crxor 6,6,6\", operands);
10311 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10312 output_asm_insn (\"creqv 6,6,6\", operands);
10314 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10315 }"
10316 [(set_attr "type" "branch")
10317 (set_attr "length" "4,8")])
10320 (define_insn "*call_value_local64"
10321 [(set (match_operand 0 "" "")
10322 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10323 (match_operand 2 "" "g,g")))
10324 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10325 (clobber (match_scratch:SI 4 "=l,l"))]
10326 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10327 "*
10328 {
10329 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10330 output_asm_insn (\"crxor 6,6,6\", operands);
10332 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10333 output_asm_insn (\"creqv 6,6,6\", operands);
10335 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10336 }"
10337 [(set_attr "type" "branch")
10338 (set_attr "length" "4,8")])
10340 ;; Call to function which may be in another module. Restore the TOC
10341 ;; pointer (r2) after the call unless this is System V.
10342 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10343 ;; either the function was not prototyped, or it was prototyped as a
10344 ;; variable argument function. It is > 0 if FP registers were passed
10345 ;; and < 0 if they were not.
10347 (define_insn "*call_indirect_nonlocal_aix32"
10348 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
10349 (match_operand 1 "" "g"))
10350 (use (reg:SI 2))
10351 (use (reg:SI 11))
10352 (set (reg:SI 2)
10353 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10354 (clobber (match_scratch:SI 2 "=l"))]
10355 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10356 "b%T0l\;{l|lwz} 2,20(1)"
10357 [(set_attr "type" "jmpreg")
10358 (set_attr "length" "8")])
10360 (define_insn "*call_nonlocal_aix32"
10361 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10362 (match_operand 1 "" "g"))
10363 (use (match_operand:SI 2 "immediate_operand" "O"))
10364 (clobber (match_scratch:SI 3 "=l"))]
10365 "TARGET_32BIT
10366 && DEFAULT_ABI == ABI_AIX
10367 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10368 "bl %z0\;%."
10369 [(set_attr "type" "branch")
10370 (set_attr "length" "8")])
10372 (define_insn "*call_indirect_nonlocal_aix64"
10373 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
10374 (match_operand 1 "" "g"))
10375 (use (reg:DI 2))
10376 (use (reg:DI 11))
10377 (set (reg:DI 2)
10378 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10379 (clobber (match_scratch:SI 2 "=l"))]
10380 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10381 "b%T0l\;ld 2,40(1)"
10382 [(set_attr "type" "jmpreg")
10383 (set_attr "length" "8")])
10385 (define_insn "*call_nonlocal_aix64"
10386 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10387 (match_operand 1 "" "g"))
10388 (use (match_operand:SI 2 "immediate_operand" "O"))
10389 (clobber (match_scratch:SI 3 "=l"))]
10390 "TARGET_64BIT
10391 && DEFAULT_ABI == ABI_AIX
10392 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10393 "bl %z0\;%."
10394 [(set_attr "type" "branch")
10395 (set_attr "length" "8")])
10397 (define_insn "*call_value_indirect_nonlocal_aix32"
10398 [(set (match_operand 0 "" "")
10399 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
10400 (match_operand 2 "" "g")))
10401 (use (reg:SI 2))
10402 (use (reg:SI 11))
10403 (set (reg:SI 2)
10404 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10405 (clobber (match_scratch:SI 3 "=l"))]
10406 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10407 "b%T1l\;{l|lwz} 2,20(1)"
10408 [(set_attr "type" "jmpreg")
10409 (set_attr "length" "8")])
10411 (define_insn "*call_value_nonlocal_aix32"
10412 [(set (match_operand 0 "" "")
10413 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10414 (match_operand 2 "" "g")))
10415 (use (match_operand:SI 3 "immediate_operand" "O"))
10416 (clobber (match_scratch:SI 4 "=l"))]
10417 "TARGET_32BIT
10418 && DEFAULT_ABI == ABI_AIX
10419 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10420 "bl %z1\;%."
10421 [(set_attr "type" "branch")
10422 (set_attr "length" "8")])
10424 (define_insn "*call_value_indirect_nonlocal_aix64"
10425 [(set (match_operand 0 "" "")
10426 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
10427 (match_operand 2 "" "g")))
10428 (use (reg:DI 2))
10429 (use (reg:DI 11))
10430 (set (reg:DI 2)
10431 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10432 (clobber (match_scratch:SI 3 "=l"))]
10433 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10434 "b%T1l\;ld 2,40(1)"
10435 [(set_attr "type" "jmpreg")
10436 (set_attr "length" "8")])
10438 (define_insn "*call_value_nonlocal_aix64"
10439 [(set (match_operand 0 "" "")
10440 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10441 (match_operand 2 "" "g")))
10442 (use (match_operand:SI 3 "immediate_operand" "O"))
10443 (clobber (match_scratch:SI 4 "=l"))]
10444 "TARGET_64BIT
10445 && DEFAULT_ABI == ABI_AIX
10446 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10447 "bl %z1\;%."
10448 [(set_attr "type" "branch")
10449 (set_attr "length" "8")])
10451 ;; A function pointer under System V is just a normal pointer
10452 ;; operands[0] is the function pointer
10453 ;; operands[1] is the stack size to clean up
10454 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10455 ;; which indicates how to set cr1
10457 (define_insn "*call_indirect_nonlocal_sysv"
10458 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl"))
10459 (match_operand 1 "" "g,g"))
10460 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10461 (clobber (match_scratch:SI 3 "=l,l"))]
10462 "DEFAULT_ABI == ABI_V4
10463 || DEFAULT_ABI == ABI_DARWIN"
10464 {
10465 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10466 output_asm_insn ("crxor 6,6,6", operands);
10468 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10469 output_asm_insn ("creqv 6,6,6", operands);
10471 return "b%T0l";
10472 }
10473 [(set_attr "type" "jmpreg,jmpreg")
10474 (set_attr "length" "4,8")])
10476 (define_insn "*call_nonlocal_sysv"
10477 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10478 (match_operand 1 "" "g,g"))
10479 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10480 (clobber (match_scratch:SI 3 "=l,l"))]
10481 "(DEFAULT_ABI == ABI_DARWIN
10482 || (DEFAULT_ABI == ABI_V4
10483 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10484 {
10485 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10486 output_asm_insn ("crxor 6,6,6", operands);
10488 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10489 output_asm_insn ("creqv 6,6,6", operands);
10491 #if TARGET_MACHO
10492 return output_call(insn, operands, 0, 2);
10493 #else
10494 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0";
10495 #endif
10496 }
10497 [(set_attr "type" "branch,branch")
10498 (set_attr "length" "4,8")])
10500 (define_insn "*call_value_indirect_nonlocal_sysv"
10501 [(set (match_operand 0 "" "")
10502 (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl"))
10503 (match_operand 2 "" "g,g")))
10504 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10505 (clobber (match_scratch:SI 4 "=l,l"))]
10506 "DEFAULT_ABI == ABI_V4
10507 || DEFAULT_ABI == ABI_DARWIN"
10508 {
10509 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10510 output_asm_insn ("crxor 6,6,6", operands);
10512 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10513 output_asm_insn ("creqv 6,6,6", operands);
10515 return "b%T1l";
10516 }
10517 [(set_attr "type" "jmpreg,jmpreg")
10518 (set_attr "length" "4,8")])
10520 (define_insn "*call_value_nonlocal_sysv"
10521 [(set (match_operand 0 "" "")
10522 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10523 (match_operand 2 "" "g,g")))
10524 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10525 (clobber (match_scratch:SI 4 "=l,l"))]
10526 "(DEFAULT_ABI == ABI_DARWIN
10527 || (DEFAULT_ABI == ABI_V4
10528 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10529 {
10530 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10531 output_asm_insn ("crxor 6,6,6", operands);
10533 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10534 output_asm_insn ("creqv 6,6,6", operands);
10536 #if TARGET_MACHO
10537 return output_call(insn, operands, 1, 3);
10538 #else
10539 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1";
10540 #endif
10541 }
10542 [(set_attr "type" "branch,branch")
10543 (set_attr "length" "4,8")])
10545 ;; Call subroutine returning any type.
10546 (define_expand "untyped_call"
10547 [(parallel [(call (match_operand 0 "" "")
10548 (const_int 0))
10549 (match_operand 1 "" "")
10550 (match_operand 2 "" "")])]
10551 ""
10552 "
10553 {
10554 int i;
10556 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10558 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10559 {
10560 rtx set = XVECEXP (operands[2], 0, i);
10561 emit_move_insn (SET_DEST (set), SET_SRC (set));
10562 }
10564 /* The optimizer does not know that the call sets the function value
10565 registers we stored in the result block. We avoid problems by
10566 claiming that all hard registers are used and clobbered at this
10567 point. */
10568 emit_insn (gen_blockage ());
10570 DONE;
10571 }")
10573 ;; sibling call patterns
10574 (define_expand "sibcall"
10575 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10576 (match_operand 1 "" ""))
10577 (use (match_operand 2 "" ""))
10578 (use (match_operand 3 "" ""))
10579 (return)])]
10580 ""
10581 "
10582 {
10583 #if TARGET_MACHO
10584 if (MACHOPIC_INDIRECT)
10585 operands[0] = machopic_indirect_call_target (operands[0]);
10586 #endif
10588 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10589 abort ();
10591 operands[0] = XEXP (operands[0], 0);
10592 operands[3] = gen_reg_rtx (SImode);
10594 }")
10596 ;; this and similar patterns must be marked as using LR, otherwise
10597 ;; dataflow will try to delete the store into it. This is true
10598 ;; even when the actual reg to jump to is in CTR, when LR was
10599 ;; saved and restored around the PIC-setting BCL.
10600 (define_insn "*sibcall_local32"
10601 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10602 (match_operand 1 "" "g,g"))
10603 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10604 (use (match_operand:SI 3 "register_operand" "l,l"))
10605 (return)]
10606 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10607 "*
10608 {
10609 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10610 output_asm_insn (\"crxor 6,6,6\", operands);
10612 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10613 output_asm_insn (\"creqv 6,6,6\", operands);
10615 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10616 }"
10617 [(set_attr "type" "branch")
10618 (set_attr "length" "4,8")])
10620 (define_insn "*sibcall_local64"
10621 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10622 (match_operand 1 "" "g,g"))
10623 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10624 (use (match_operand:SI 3 "register_operand" "l,l"))
10625 (return)]
10626 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10627 "*
10628 {
10629 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10630 output_asm_insn (\"crxor 6,6,6\", operands);
10632 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10633 output_asm_insn (\"creqv 6,6,6\", operands);
10635 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10636 }"
10637 [(set_attr "type" "branch")
10638 (set_attr "length" "4,8")])
10640 (define_insn "*sibcall_value_local32"
10641 [(set (match_operand 0 "" "")
10642 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10643 (match_operand 2 "" "g,g")))
10644 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10645 (use (match_operand:SI 4 "register_operand" "l,l"))
10646 (return)]
10647 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10648 "*
10649 {
10650 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10651 output_asm_insn (\"crxor 6,6,6\", operands);
10653 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10654 output_asm_insn (\"creqv 6,6,6\", operands);
10656 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10657 }"
10658 [(set_attr "type" "branch")
10659 (set_attr "length" "4,8")])
10662 (define_insn "*sibcall_value_local64"
10663 [(set (match_operand 0 "" "")
10664 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10665 (match_operand 2 "" "g,g")))
10666 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10667 (use (match_operand:SI 4 "register_operand" "l,l"))
10668 (return)]
10669 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10670 "*
10671 {
10672 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10673 output_asm_insn (\"crxor 6,6,6\", operands);
10675 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10676 output_asm_insn (\"creqv 6,6,6\", operands);
10678 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10679 }"
10680 [(set_attr "type" "branch")
10681 (set_attr "length" "4,8")])
10683 (define_insn "*sibcall_nonlocal_aix32"
10684 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10685 (match_operand 1 "" "g"))
10686 (use (match_operand:SI 2 "immediate_operand" "O"))
10687 (use (match_operand:SI 3 "register_operand" "l"))
10688 (return)]
10689 "TARGET_32BIT
10690 && DEFAULT_ABI == ABI_AIX
10691 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10692 "b %z0"
10693 [(set_attr "type" "branch")
10694 (set_attr "length" "4")])
10696 (define_insn "*sibcall_nonlocal_aix64"
10697 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10698 (match_operand 1 "" "g"))
10699 (use (match_operand:SI 2 "immediate_operand" "O"))
10700 (use (match_operand:SI 3 "register_operand" "l"))
10701 (return)]
10702 "TARGET_64BIT
10703 && DEFAULT_ABI == ABI_AIX
10704 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10705 "b %z0"
10706 [(set_attr "type" "branch")
10707 (set_attr "length" "4")])
10709 (define_insn "*sibcall_value_nonlocal_aix32"
10710 [(set (match_operand 0 "" "")
10711 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10712 (match_operand 2 "" "g")))
10713 (use (match_operand:SI 3 "immediate_operand" "O"))
10714 (use (match_operand:SI 4 "register_operand" "l"))
10715 (return)]
10716 "TARGET_32BIT
10717 && DEFAULT_ABI == ABI_AIX
10718 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10719 "b %z1"
10720 [(set_attr "type" "branch")
10721 (set_attr "length" "4")])
10723 (define_insn "*sibcall_value_nonlocal_aix64"
10724 [(set (match_operand 0 "" "")
10725 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10726 (match_operand 2 "" "g")))
10727 (use (match_operand:SI 3 "immediate_operand" "O"))
10728 (use (match_operand:SI 4 "register_operand" "l"))
10729 (return)]
10730 "TARGET_64BIT
10731 && DEFAULT_ABI == ABI_AIX
10732 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10733 "b %z1"
10734 [(set_attr "type" "branch")
10735 (set_attr "length" "4")])
10737 (define_insn "*sibcall_nonlocal_sysv"
10738 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10739 (match_operand 1 "" ""))
10740 (use (match_operand 2 "immediate_operand" "O,n"))
10741 (use (match_operand:SI 3 "register_operand" "l,l"))
10742 (return)]
10743 "(DEFAULT_ABI == ABI_DARWIN
10744 || DEFAULT_ABI == ABI_V4)
10745 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10746 "*
10747 {
10748 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10749 output_asm_insn (\"crxor 6,6,6\", operands);
10751 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10752 output_asm_insn (\"creqv 6,6,6\", operands);
10754 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\";
10755 }"
10756 [(set_attr "type" "branch,branch")
10757 (set_attr "length" "4,8")])
10759 (define_expand "sibcall_value"
10760 [(parallel [(set (match_operand 0 "register_operand" "")
10761 (call (mem:SI (match_operand 1 "address_operand" ""))
10762 (match_operand 2 "" "")))
10763 (use (match_operand 3 "" ""))
10764 (use (match_operand 4 "" ""))
10765 (return)])]
10766 ""
10767 "
10768 {
10769 #if TARGET_MACHO
10770 if (MACHOPIC_INDIRECT)
10771 operands[1] = machopic_indirect_call_target (operands[1]);
10772 #endif
10774 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10775 abort ();
10777 operands[1] = XEXP (operands[1], 0);
10778 operands[4] = gen_reg_rtx (SImode);
10780 }")
10782 (define_insn "*sibcall_value_nonlocal_sysv"
10783 [(set (match_operand 0 "" "")
10784 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10785 (match_operand 2 "" "")))
10786 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10787 (use (match_operand:SI 4 "register_operand" "l,l"))
10788 (return)]
10789 "(DEFAULT_ABI == ABI_DARWIN
10790 || DEFAULT_ABI == ABI_V4)
10791 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10792 "*
10793 {
10794 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10795 output_asm_insn (\"crxor 6,6,6\", operands);
10797 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10798 output_asm_insn (\"creqv 6,6,6\", operands);
10800 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\";
10801 }"
10802 [(set_attr "type" "branch,branch")
10803 (set_attr "length" "4,8")])
10805 (define_expand "sibcall_epilogue"
10806 [(use (const_int 0))]
10807 "TARGET_SCHED_PROLOG"
10808 "
10809 {
10810 rs6000_emit_epilogue (TRUE);
10811 DONE;
10812 }")
10814 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10815 ;; all of memory. This blocks insns from being moved across this point.
10817 (define_insn "blockage"
10818 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10819 ""
10820 "")
10821 \f
10822 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10823 ;; signed & unsigned, and one type of branch.
10824 ;;
10825 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10826 ;; insns, and branches. We store the operands of compares until we see
10827 ;; how it is used.
10828 (define_expand "cmpsi"
10829 [(set (cc0)
10830 (compare (match_operand:SI 0 "gpc_reg_operand" "")
10831 (match_operand:SI 1 "reg_or_short_operand" "")))]
10832 ""
10833 "
10834 {
10835 /* Take care of the possibility that operands[1] might be negative but
10836 this might be a logical operation. That insn doesn't exist. */
10837 if (GET_CODE (operands[1]) == CONST_INT
10838 && INTVAL (operands[1]) < 0)
10839 operands[1] = force_reg (SImode, operands[1]);
10841 rs6000_compare_op0 = operands[0];
10842 rs6000_compare_op1 = operands[1];
10843 rs6000_compare_fp_p = 0;
10844 DONE;
10845 }")
10847 (define_expand "cmpdi"
10848 [(set (cc0)
10849 (compare (match_operand:DI 0 "gpc_reg_operand" "")
10850 (match_operand:DI 1 "reg_or_short_operand" "")))]
10851 "TARGET_POWERPC64"
10852 "
10853 {
10854 /* Take care of the possibility that operands[1] might be negative but
10855 this might be a logical operation. That insn doesn't exist. */
10856 if (GET_CODE (operands[1]) == CONST_INT
10857 && INTVAL (operands[1]) < 0)
10858 operands[1] = force_reg (DImode, operands[1]);
10860 rs6000_compare_op0 = operands[0];
10861 rs6000_compare_op1 = operands[1];
10862 rs6000_compare_fp_p = 0;
10863 DONE;
10864 }")
10866 (define_expand "cmpsf"
10867 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
10868 (match_operand:SF 1 "gpc_reg_operand" "")))]
10869 "TARGET_HARD_FLOAT"
10870 "
10871 {
10872 rs6000_compare_op0 = operands[0];
10873 rs6000_compare_op1 = operands[1];
10874 rs6000_compare_fp_p = 1;
10875 DONE;
10876 }")
10878 (define_expand "cmpdf"
10879 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
10880 (match_operand:DF 1 "gpc_reg_operand" "")))]
10881 "TARGET_HARD_FLOAT && TARGET_FPRS"
10882 "
10883 {
10884 rs6000_compare_op0 = operands[0];
10885 rs6000_compare_op1 = operands[1];
10886 rs6000_compare_fp_p = 1;
10887 DONE;
10888 }")
10890 (define_expand "cmptf"
10891 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
10892 (match_operand:TF 1 "gpc_reg_operand" "")))]
10893 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10894 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10895 "
10896 {
10897 rs6000_compare_op0 = operands[0];
10898 rs6000_compare_op1 = operands[1];
10899 rs6000_compare_fp_p = 1;
10900 DONE;
10901 }")
10903 (define_expand "beq"
10904 [(use (match_operand 0 "" ""))]
10905 ""
10906 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
10908 (define_expand "bne"
10909 [(use (match_operand 0 "" ""))]
10910 ""
10911 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
10913 (define_expand "bge"
10914 [(use (match_operand 0 "" ""))]
10915 ""
10916 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
10918 (define_expand "bgt"
10919 [(use (match_operand 0 "" ""))]
10920 ""
10921 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
10923 (define_expand "ble"
10924 [(use (match_operand 0 "" ""))]
10925 ""
10926 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
10928 (define_expand "blt"
10929 [(use (match_operand 0 "" ""))]
10930 ""
10931 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
10933 (define_expand "bgeu"
10934 [(use (match_operand 0 "" ""))]
10935 ""
10936 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
10938 (define_expand "bgtu"
10939 [(use (match_operand 0 "" ""))]
10940 ""
10941 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
10943 (define_expand "bleu"
10944 [(use (match_operand 0 "" ""))]
10945 ""
10946 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
10948 (define_expand "bltu"
10949 [(use (match_operand 0 "" ""))]
10950 ""
10951 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
10953 (define_expand "bunordered"
10954 [(use (match_operand 0 "" ""))]
10955 ""
10956 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
10958 (define_expand "bordered"
10959 [(use (match_operand 0 "" ""))]
10960 ""
10961 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
10963 (define_expand "buneq"
10964 [(use (match_operand 0 "" ""))]
10965 ""
10966 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
10968 (define_expand "bunge"
10969 [(use (match_operand 0 "" ""))]
10970 ""
10971 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
10973 (define_expand "bungt"
10974 [(use (match_operand 0 "" ""))]
10975 ""
10976 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
10978 (define_expand "bunle"
10979 [(use (match_operand 0 "" ""))]
10980 ""
10981 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
10983 (define_expand "bunlt"
10984 [(use (match_operand 0 "" ""))]
10985 ""
10986 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
10988 (define_expand "bltgt"
10989 [(use (match_operand 0 "" ""))]
10990 ""
10991 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
10993 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
10994 ;; For SEQ, likewise, except that comparisons with zero should be done
10995 ;; with an scc insns. However, due to the order that combine see the
10996 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
10997 ;; the cases we don't want to handle.
10998 (define_expand "seq"
10999 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11000 ""
11001 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11003 (define_expand "sne"
11004 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11005 ""
11006 "
11007 {
11008 if (! rs6000_compare_fp_p)
11009 FAIL;
11011 rs6000_emit_sCOND (NE, operands[0]);
11012 DONE;
11013 }")
11015 ;; A >= 0 is best done the portable way for A an integer.
11016 (define_expand "sge"
11017 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11018 ""
11019 "
11020 {
11021 if (! rs6000_compare_fp_p
11022 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11023 FAIL;
11025 rs6000_emit_sCOND (GE, operands[0]);
11026 DONE;
11027 }")
11029 ;; A > 0 is best done using the portable sequence, so fail in that case.
11030 (define_expand "sgt"
11031 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11032 ""
11033 "
11034 {
11035 if (! rs6000_compare_fp_p
11036 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11037 FAIL;
11039 rs6000_emit_sCOND (GT, operands[0]);
11040 DONE;
11041 }")
11043 ;; A <= 0 is best done the portable way for A an integer.
11044 (define_expand "sle"
11045 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11046 ""
11047 "
11048 {
11049 if (! rs6000_compare_fp_p
11050 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11051 FAIL;
11053 rs6000_emit_sCOND (LE, operands[0]);
11054 DONE;
11055 }")
11057 ;; A < 0 is best done in the portable way for A an integer.
11058 (define_expand "slt"
11059 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11060 ""
11061 "
11062 {
11063 if (! rs6000_compare_fp_p
11064 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11065 FAIL;
11067 rs6000_emit_sCOND (LT, operands[0]);
11068 DONE;
11069 }")
11071 (define_expand "sgeu"
11072 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11073 ""
11074 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11076 (define_expand "sgtu"
11077 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11078 ""
11079 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11081 (define_expand "sleu"
11082 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11083 ""
11084 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11086 (define_expand "sltu"
11087 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11088 ""
11089 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11091 (define_expand "sunordered"
11092 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11093 ""
11094 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11096 (define_expand "sordered"
11097 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11098 ""
11099 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11101 (define_expand "suneq"
11102 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11103 ""
11104 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11106 (define_expand "sunge"
11107 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11108 ""
11109 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11111 (define_expand "sungt"
11112 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11113 ""
11114 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11116 (define_expand "sunle"
11117 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11118 ""
11119 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11121 (define_expand "sunlt"
11122 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11123 ""
11124 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11126 (define_expand "sltgt"
11127 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11128 ""
11129 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11131 \f
11132 ;; Here are the actual compare insns.
11133 (define_insn "*cmpsi_internal1"
11134 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11135 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11136 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11137 ""
11138 "{cmp%I2|cmpw%I2} %0,%1,%2"
11139 [(set_attr "type" "cmp")])
11141 (define_insn "*cmpdi_internal1"
11142 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11143 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
11144 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11145 "TARGET_POWERPC64"
11146 "cmpd%I2 %0,%1,%2"
11147 [(set_attr "type" "cmp")])
11149 ;; If we are comparing a register for equality with a large constant,
11150 ;; we can do this with an XOR followed by a compare. But we need a scratch
11151 ;; register for the result of the XOR.
11153 (define_split
11154 [(set (match_operand:CC 0 "cc_reg_operand" "")
11155 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11156 (match_operand:SI 2 "non_short_cint_operand" "")))
11157 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
11158 "find_single_use (operands[0], insn, 0)
11159 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
11160 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
11161 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
11162 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
11163 "
11164 {
11165 /* Get the constant we are comparing against, C, and see what it looks like
11166 sign-extended to 16 bits. Then see what constant could be XOR'ed
11167 with C to get the sign-extended value. */
11169 HOST_WIDE_INT c = INTVAL (operands[2]);
11170 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11171 HOST_WIDE_INT xorv = c ^ sextc;
11173 operands[4] = GEN_INT (xorv);
11174 operands[5] = GEN_INT (sextc);
11175 }")
11177 (define_insn "*cmpsi_internal2"
11178 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11179 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11180 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11181 ""
11182 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11183 [(set_attr "type" "cmp")])
11185 (define_insn "*cmpdi_internal2"
11186 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11187 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11188 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11189 ""
11190 "cmpld%I2 %0,%1,%b2"
11191 [(set_attr "type" "cmp")])
11193 ;; The following two insns don't exist as single insns, but if we provide
11194 ;; them, we can swap an add and compare, which will enable us to overlap more
11195 ;; of the required delay between a compare and branch. We generate code for
11196 ;; them by splitting.
11198 (define_insn ""
11199 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11200 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11201 (match_operand:SI 2 "short_cint_operand" "i")))
11202 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11203 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11204 ""
11205 "#"
11206 [(set_attr "length" "8")])
11208 (define_insn ""
11209 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11210 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11211 (match_operand:SI 2 "u_short_cint_operand" "i")))
11212 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11213 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11214 ""
11215 "#"
11216 [(set_attr "length" "8")])
11218 (define_split
11219 [(set (match_operand:CC 3 "cc_reg_operand" "")
11220 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11221 (match_operand:SI 2 "short_cint_operand" "")))
11222 (set (match_operand:SI 0 "gpc_reg_operand" "")
11223 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11224 ""
11225 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11226 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11228 (define_split
11229 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11230 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11231 (match_operand:SI 2 "u_short_cint_operand" "")))
11232 (set (match_operand:SI 0 "gpc_reg_operand" "")
11233 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11234 ""
11235 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11236 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11238 (define_insn "*cmpsf_internal1"
11239 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11240 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11241 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11242 "TARGET_HARD_FLOAT && TARGET_FPRS"
11243 "fcmpu %0,%1,%2"
11244 [(set_attr "type" "fpcompare")])
11246 (define_insn "*cmpdf_internal1"
11247 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11248 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11249 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11250 "TARGET_HARD_FLOAT && TARGET_FPRS"
11251 "fcmpu %0,%1,%2"
11252 [(set_attr "type" "fpcompare")])
11254 ;; Only need to compare second words if first words equal
11255 (define_insn "*cmptf_internal1"
11256 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11257 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11258 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11259 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
11260 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11261 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11262 [(set_attr "type" "fpcompare")
11263 (set_attr "length" "12")])
11264 \f
11265 ;; Now we have the scc insns. We can do some combinations because of the
11266 ;; way the machine works.
11267 ;;
11268 ;; Note that this is probably faster if we can put an insn between the
11269 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11270 ;; cases the insns below which don't use an intermediate CR field will
11271 ;; be used instead.
11272 (define_insn ""
11273 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11274 (match_operator:SI 1 "scc_comparison_operator"
11275 [(match_operand 2 "cc_reg_operand" "y")
11276 (const_int 0)]))]
11277 ""
11278 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11279 [(set (attr "type")
11280 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11281 (const_string "mfcrf")
11282 ]
11283 (const_string "mfcr")))
11284 (set_attr "length" "12")])
11286 ;; Same as above, but get the OV/ORDERED bit.
11287 (define_insn "move_from_CR_ov_bit"
11288 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11289 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11290 "TARGET_ISEL"
11291 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11292 [(set_attr "type" "mfcr")
11293 (set_attr "length" "12")])
11295 (define_insn ""
11296 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11297 (match_operator:DI 1 "scc_comparison_operator"
11298 [(match_operand 2 "cc_reg_operand" "y")
11299 (const_int 0)]))]
11300 "TARGET_POWERPC64"
11301 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11302 [(set (attr "type")
11303 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11304 (const_string "mfcrf")
11305 ]
11306 (const_string "mfcr")))
11307 (set_attr "length" "12")])
11309 (define_insn ""
11310 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11311 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11312 [(match_operand 2 "cc_reg_operand" "y,y")
11313 (const_int 0)])
11314 (const_int 0)))
11315 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11316 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11317 "TARGET_32BIT"
11318 "@
11319 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11320 #"
11321 [(set_attr "type" "delayed_compare")
11322 (set_attr "length" "12,16")])
11324 (define_split
11325 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11326 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11327 [(match_operand 2 "cc_reg_operand" "")
11328 (const_int 0)])
11329 (const_int 0)))
11330 (set (match_operand:SI 3 "gpc_reg_operand" "")
11331 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11332 "TARGET_32BIT && reload_completed"
11333 [(set (match_dup 3)
11334 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11335 (set (match_dup 0)
11336 (compare:CC (match_dup 3)
11337 (const_int 0)))]
11338 "")
11340 (define_insn ""
11341 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11342 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11343 [(match_operand 2 "cc_reg_operand" "y")
11344 (const_int 0)])
11345 (match_operand:SI 3 "const_int_operand" "n")))]
11346 ""
11347 "*
11348 {
11349 int is_bit = ccr_bit (operands[1], 1);
11350 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11351 int count;
11353 if (is_bit >= put_bit)
11354 count = is_bit - put_bit;
11355 else
11356 count = 32 - (put_bit - is_bit);
11358 operands[4] = GEN_INT (count);
11359 operands[5] = GEN_INT (put_bit);
11361 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11362 }"
11363 [(set (attr "type")
11364 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11365 (const_string "mfcrf")
11366 ]
11367 (const_string "mfcr")))
11368 (set_attr "length" "12")])
11370 (define_insn ""
11371 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11372 (compare:CC
11373 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11374 [(match_operand 2 "cc_reg_operand" "y,y")
11375 (const_int 0)])
11376 (match_operand:SI 3 "const_int_operand" "n,n"))
11377 (const_int 0)))
11378 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11379 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11380 (match_dup 3)))]
11381 ""
11382 "*
11383 {
11384 int is_bit = ccr_bit (operands[1], 1);
11385 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11386 int count;
11388 /* Force split for non-cc0 compare. */
11389 if (which_alternative == 1)
11390 return \"#\";
11392 if (is_bit >= put_bit)
11393 count = is_bit - put_bit;
11394 else
11395 count = 32 - (put_bit - is_bit);
11397 operands[5] = GEN_INT (count);
11398 operands[6] = GEN_INT (put_bit);
11400 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11401 }"
11402 [(set_attr "type" "delayed_compare")
11403 (set_attr "length" "12,16")])
11405 (define_split
11406 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11407 (compare:CC
11408 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11409 [(match_operand 2 "cc_reg_operand" "")
11410 (const_int 0)])
11411 (match_operand:SI 3 "const_int_operand" ""))
11412 (const_int 0)))
11413 (set (match_operand:SI 4 "gpc_reg_operand" "")
11414 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11415 (match_dup 3)))]
11416 "reload_completed"
11417 [(set (match_dup 4)
11418 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11419 (match_dup 3)))
11420 (set (match_dup 0)
11421 (compare:CC (match_dup 4)
11422 (const_int 0)))]
11423 "")
11425 ;; There is a 3 cycle delay between consecutive mfcr instructions
11426 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11428 (define_peephole
11429 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11430 (match_operator:SI 1 "scc_comparison_operator"
11431 [(match_operand 2 "cc_reg_operand" "y")
11432 (const_int 0)]))
11433 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11434 (match_operator:SI 4 "scc_comparison_operator"
11435 [(match_operand 5 "cc_reg_operand" "y")
11436 (const_int 0)]))]
11437 "REGNO (operands[2]) != REGNO (operands[5])"
11438 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11439 [(set_attr "type" "mfcr")
11440 (set_attr "length" "20")])
11442 (define_peephole
11443 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11444 (match_operator:DI 1 "scc_comparison_operator"
11445 [(match_operand 2 "cc_reg_operand" "y")
11446 (const_int 0)]))
11447 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11448 (match_operator:DI 4 "scc_comparison_operator"
11449 [(match_operand 5 "cc_reg_operand" "y")
11450 (const_int 0)]))]
11451 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11452 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11453 [(set_attr "type" "mfcr")
11454 (set_attr "length" "20")])
11456 ;; There are some scc insns that can be done directly, without a compare.
11457 ;; These are faster because they don't involve the communications between
11458 ;; the FXU and branch units. In fact, we will be replacing all of the
11459 ;; integer scc insns here or in the portable methods in emit_store_flag.
11460 ;;
11461 ;; Also support (neg (scc ..)) since that construct is used to replace
11462 ;; branches, (plus (scc ..) ..) since that construct is common and
11463 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11464 ;; cases where it is no more expensive than (neg (scc ..)).
11466 ;; Have reload force a constant into a register for the simple insns that
11467 ;; otherwise won't accept constants. We do this because it is faster than
11468 ;; the cmp/mfcr sequence we would otherwise generate.
11470 (define_insn ""
11471 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11472 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11473 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11474 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11475 "TARGET_32BIT"
11476 "@
11477 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11478 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11479 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11480 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11481 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11482 [(set_attr "length" "12,8,12,12,12")])
11484 (define_insn ""
11485 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
11486 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
11487 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11488 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
11489 "TARGET_64BIT"
11490 "@
11491 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
11492 subfic %3,%1,0\;adde %0,%3,%1
11493 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
11494 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
11495 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
11496 [(set_attr "length" "12,8,12,12,12")])
11498 (define_insn ""
11499 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11500 (compare:CC
11501 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11502 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11503 (const_int 0)))
11504 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11505 (eq:SI (match_dup 1) (match_dup 2)))
11506 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11507 "TARGET_32BIT"
11508 "@
11509 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11510 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
11511 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11512 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11513 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11514 #
11515 #
11516 #
11517 #
11518 #"
11519 [(set_attr "type" "compare")
11520 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11522 (define_split
11523 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11524 (compare:CC
11525 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11526 (match_operand:SI 2 "reg_or_cint_operand" ""))
11527 (const_int 0)))
11528 (set (match_operand:SI 0 "gpc_reg_operand" "")
11529 (eq:SI (match_dup 1) (match_dup 2)))
11530 (clobber (match_scratch:SI 3 ""))]
11531 "TARGET_32BIT && reload_completed"
11532 [(parallel [(set (match_dup 0)
11533 (eq:SI (match_dup 1) (match_dup 2)))
11534 (clobber (match_dup 3))])
11535 (set (match_dup 4)
11536 (compare:CC (match_dup 0)
11537 (const_int 0)))]
11538 "")
11540 (define_insn ""
11541 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11542 (compare:CC
11543 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11544 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
11545 (const_int 0)))
11546 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11547 (eq:DI (match_dup 1) (match_dup 2)))
11548 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11549 "TARGET_64BIT"
11550 "@
11551 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11552 subfic %3,%1,0\;adde. %0,%3,%1
11553 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
11554 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
11555 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11556 #
11557 #
11558 #
11559 #
11560 #"
11561 [(set_attr "type" "compare")
11562 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11564 (define_split
11565 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11566 (compare:CC
11567 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
11568 (match_operand:DI 2 "reg_or_cint_operand" ""))
11569 (const_int 0)))
11570 (set (match_operand:DI 0 "gpc_reg_operand" "")
11571 (eq:DI (match_dup 1) (match_dup 2)))
11572 (clobber (match_scratch:DI 3 ""))]
11573 "TARGET_64BIT && reload_completed"
11574 [(parallel [(set (match_dup 0)
11575 (eq:DI (match_dup 1) (match_dup 2)))
11576 (clobber (match_dup 3))])
11577 (set (match_dup 4)
11578 (compare:CC (match_dup 0)
11579 (const_int 0)))]
11580 "")
11582 ;; We have insns of the form shown by the first define_insn below. If
11583 ;; there is something inside the comparison operation, we must split it.
11584 (define_split
11585 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11586 (plus:SI (match_operator 1 "comparison_operator"
11587 [(match_operand:SI 2 "" "")
11588 (match_operand:SI 3
11589 "reg_or_cint_operand" "")])
11590 (match_operand:SI 4 "gpc_reg_operand" "")))
11591 (clobber (match_operand:SI 5 "register_operand" ""))]
11592 "! gpc_reg_operand (operands[2], SImode)"
11593 [(set (match_dup 5) (match_dup 2))
11594 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11595 (match_dup 4)))])
11597 (define_insn ""
11598 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11599 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11600 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
11601 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11602 "TARGET_32BIT"
11603 "@
11604 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11605 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11606 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11607 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11608 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11609 [(set_attr "length" "12,8,12,12,12")])
11611 (define_insn ""
11612 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11613 (compare:CC
11614 (plus:SI
11615 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11616 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11617 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11618 (const_int 0)))
11619 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11620 "TARGET_32BIT"
11621 "@
11622 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11623 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11624 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11625 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11626 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11627 #
11628 #
11629 #
11630 #
11631 #"
11632 [(set_attr "type" "compare")
11633 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11635 (define_split
11636 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11637 (compare:CC
11638 (plus:SI
11639 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11640 (match_operand:SI 2 "reg_or_cint_operand" ""))
11641 (match_operand:SI 3 "gpc_reg_operand" ""))
11642 (const_int 0)))
11643 (clobber (match_scratch:SI 4 ""))]
11644 "TARGET_32BIT && reload_completed"
11645 [(set (match_dup 4)
11646 (plus:SI (eq:SI (match_dup 1)
11647 (match_dup 2))
11648 (match_dup 3)))
11649 (set (match_dup 0)
11650 (compare:CC (match_dup 4)
11651 (const_int 0)))]
11652 "")
11654 (define_insn ""
11655 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11656 (compare:CC
11657 (plus:SI
11658 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11659 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11660 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11661 (const_int 0)))
11662 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11663 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11664 "TARGET_32BIT"
11665 "@
11666 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11667 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11668 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11669 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11670 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11671 #
11672 #
11673 #
11674 #
11675 #"
11676 [(set_attr "type" "compare")
11677 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11679 (define_split
11680 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11681 (compare:CC
11682 (plus:SI
11683 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11684 (match_operand:SI 2 "reg_or_cint_operand" ""))
11685 (match_operand:SI 3 "gpc_reg_operand" ""))
11686 (const_int 0)))
11687 (set (match_operand:SI 0 "gpc_reg_operand" "")
11688 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11689 "TARGET_32BIT && reload_completed"
11690 [(set (match_dup 0)
11691 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11692 (set (match_dup 4)
11693 (compare:CC (match_dup 0)
11694 (const_int 0)))]
11695 "")
11697 (define_insn ""
11698 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11699 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11700 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
11701 "TARGET_32BIT"
11702 "@
11703 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11704 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11705 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11706 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11707 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11708 [(set_attr "length" "12,8,12,12,12")])
11710 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11711 ;; since it nabs/sr is just as fast.
11712 (define_insn "*ne0"
11713 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11714 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11715 (const_int 31)))
11716 (clobber (match_scratch:SI 2 "=&r"))]
11717 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11718 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11719 [(set_attr "length" "8")])
11721 (define_insn ""
11722 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11723 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11724 (const_int 63)))
11725 (clobber (match_scratch:DI 2 "=&r"))]
11726 "TARGET_64BIT"
11727 "addic %2,%1,-1\;subfe %0,%2,%1"
11728 [(set_attr "length" "8")])
11730 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11731 (define_insn ""
11732 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11733 (plus:SI (lshiftrt:SI
11734 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11735 (const_int 31))
11736 (match_operand:SI 2 "gpc_reg_operand" "r")))
11737 (clobber (match_scratch:SI 3 "=&r"))]
11738 "TARGET_32BIT"
11739 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11740 [(set_attr "length" "8")])
11742 (define_insn ""
11743 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11744 (plus:DI (lshiftrt:DI
11745 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11746 (const_int 63))
11747 (match_operand:DI 2 "gpc_reg_operand" "r")))
11748 (clobber (match_scratch:DI 3 "=&r"))]
11749 "TARGET_64BIT"
11750 "addic %3,%1,-1\;addze %0,%2"
11751 [(set_attr "length" "8")])
11753 (define_insn ""
11754 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11755 (compare:CC
11756 (plus:SI (lshiftrt:SI
11757 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11758 (const_int 31))
11759 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11760 (const_int 0)))
11761 (clobber (match_scratch:SI 3 "=&r,&r"))
11762 (clobber (match_scratch:SI 4 "=X,&r"))]
11763 "TARGET_32BIT"
11764 "@
11765 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11766 #"
11767 [(set_attr "type" "compare")
11768 (set_attr "length" "8,12")])
11770 (define_split
11771 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11772 (compare:CC
11773 (plus:SI (lshiftrt:SI
11774 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11775 (const_int 31))
11776 (match_operand:SI 2 "gpc_reg_operand" ""))
11777 (const_int 0)))
11778 (clobber (match_scratch:SI 3 ""))
11779 (clobber (match_scratch:SI 4 ""))]
11780 "TARGET_32BIT && reload_completed"
11781 [(parallel [(set (match_dup 3)
11782 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11783 (const_int 31))
11784 (match_dup 2)))
11785 (clobber (match_dup 4))])
11786 (set (match_dup 0)
11787 (compare:CC (match_dup 3)
11788 (const_int 0)))]
11789 "")
11791 (define_insn ""
11792 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11793 (compare:CC
11794 (plus:DI (lshiftrt:DI
11795 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11796 (const_int 63))
11797 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11798 (const_int 0)))
11799 (clobber (match_scratch:DI 3 "=&r,&r"))]
11800 "TARGET_64BIT"
11801 "@
11802 addic %3,%1,-1\;addze. %3,%2
11803 #"
11804 [(set_attr "type" "compare")
11805 (set_attr "length" "8,12")])
11807 (define_split
11808 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11809 (compare:CC
11810 (plus:DI (lshiftrt:DI
11811 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11812 (const_int 63))
11813 (match_operand:DI 2 "gpc_reg_operand" ""))
11814 (const_int 0)))
11815 (clobber (match_scratch:DI 3 ""))]
11816 "TARGET_64BIT && reload_completed"
11817 [(set (match_dup 3)
11818 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11819 (const_int 63))
11820 (match_dup 2)))
11821 (set (match_dup 0)
11822 (compare:CC (match_dup 3)
11823 (const_int 0)))]
11824 "")
11826 (define_insn ""
11827 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11828 (compare:CC
11829 (plus:SI (lshiftrt:SI
11830 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11831 (const_int 31))
11832 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11833 (const_int 0)))
11834 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11835 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11836 (match_dup 2)))
11837 (clobber (match_scratch:SI 3 "=&r,&r"))]
11838 "TARGET_32BIT"
11839 "@
11840 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11841 #"
11842 [(set_attr "type" "compare")
11843 (set_attr "length" "8,12")])
11845 (define_split
11846 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11847 (compare:CC
11848 (plus:SI (lshiftrt:SI
11849 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11850 (const_int 31))
11851 (match_operand:SI 2 "gpc_reg_operand" ""))
11852 (const_int 0)))
11853 (set (match_operand:SI 0 "gpc_reg_operand" "")
11854 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11855 (match_dup 2)))
11856 (clobber (match_scratch:SI 3 ""))]
11857 "TARGET_32BIT && reload_completed"
11858 [(parallel [(set (match_dup 0)
11859 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11860 (match_dup 2)))
11861 (clobber (match_dup 3))])
11862 (set (match_dup 4)
11863 (compare:CC (match_dup 0)
11864 (const_int 0)))]
11865 "")
11867 (define_insn ""
11868 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11869 (compare:CC
11870 (plus:DI (lshiftrt:DI
11871 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11872 (const_int 63))
11873 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11874 (const_int 0)))
11875 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11876 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11877 (match_dup 2)))
11878 (clobber (match_scratch:DI 3 "=&r,&r"))]
11879 "TARGET_64BIT"
11880 "@
11881 addic %3,%1,-1\;addze. %0,%2
11882 #"
11883 [(set_attr "type" "compare")
11884 (set_attr "length" "8,12")])
11886 (define_split
11887 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11888 (compare:CC
11889 (plus:DI (lshiftrt:DI
11890 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11891 (const_int 63))
11892 (match_operand:DI 2 "gpc_reg_operand" ""))
11893 (const_int 0)))
11894 (set (match_operand:DI 0 "gpc_reg_operand" "")
11895 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11896 (match_dup 2)))
11897 (clobber (match_scratch:DI 3 ""))]
11898 "TARGET_64BIT && reload_completed"
11899 [(parallel [(set (match_dup 0)
11900 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11901 (match_dup 2)))
11902 (clobber (match_dup 3))])
11903 (set (match_dup 4)
11904 (compare:CC (match_dup 0)
11905 (const_int 0)))]
11906 "")
11908 (define_insn ""
11909 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11910 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11911 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11912 (clobber (match_scratch:SI 3 "=r,X"))]
11913 "TARGET_POWER"
11914 "@
11915 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
11916 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
11917 [(set_attr "length" "12")])
11919 (define_insn ""
11920 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11921 (compare:CC
11922 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11923 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11924 (const_int 0)))
11925 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11926 (le:SI (match_dup 1) (match_dup 2)))
11927 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
11928 "TARGET_POWER"
11929 "@
11930 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11931 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11932 #
11933 #"
11934 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11935 (set_attr "length" "12,12,16,16")])
11937 (define_split
11938 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11939 (compare:CC
11940 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11941 (match_operand:SI 2 "reg_or_short_operand" ""))
11942 (const_int 0)))
11943 (set (match_operand:SI 0 "gpc_reg_operand" "")
11944 (le:SI (match_dup 1) (match_dup 2)))
11945 (clobber (match_scratch:SI 3 ""))]
11946 "TARGET_POWER && reload_completed"
11947 [(parallel [(set (match_dup 0)
11948 (le:SI (match_dup 1) (match_dup 2)))
11949 (clobber (match_dup 3))])
11950 (set (match_dup 4)
11951 (compare:CC (match_dup 0)
11952 (const_int 0)))]
11953 "")
11955 (define_insn ""
11956 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11957 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11958 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
11959 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
11960 "TARGET_POWER"
11961 "@
11962 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11963 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
11964 [(set_attr "length" "12")])
11966 (define_insn ""
11967 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11968 (compare:CC
11969 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11970 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11971 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11972 (const_int 0)))
11973 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11974 "TARGET_POWER"
11975 "@
11976 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11977 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
11978 #
11979 #"
11980 [(set_attr "type" "compare")
11981 (set_attr "length" "12,12,16,16")])
11983 (define_split
11984 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11985 (compare:CC
11986 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11987 (match_operand:SI 2 "reg_or_short_operand" ""))
11988 (match_operand:SI 3 "gpc_reg_operand" ""))
11989 (const_int 0)))
11990 (clobber (match_scratch:SI 4 ""))]
11991 "TARGET_POWER && reload_completed"
11992 [(set (match_dup 4)
11993 (plus:SI (le:SI (match_dup 1) (match_dup 2))
11994 (match_dup 3)))
11995 (set (match_dup 0)
11996 (compare:CC (match_dup 4)
11997 (const_int 0)))]
11998 "")
12000 (define_insn ""
12001 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12002 (compare:CC
12003 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12004 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12005 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12006 (const_int 0)))
12007 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12008 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12009 "TARGET_POWER"
12010 "@
12011 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12012 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12013 #
12014 #"
12015 [(set_attr "type" "compare")
12016 (set_attr "length" "12,12,16,16")])
12018 (define_split
12019 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12020 (compare:CC
12021 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12022 (match_operand:SI 2 "reg_or_short_operand" ""))
12023 (match_operand:SI 3 "gpc_reg_operand" ""))
12024 (const_int 0)))
12025 (set (match_operand:SI 0 "gpc_reg_operand" "")
12026 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12027 "TARGET_POWER && reload_completed"
12028 [(set (match_dup 0)
12029 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12030 (set (match_dup 4)
12031 (compare:CC (match_dup 0)
12032 (const_int 0)))]
12033 "")
12035 (define_insn ""
12036 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12037 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12038 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12039 "TARGET_POWER"
12040 "@
12041 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12042 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12043 [(set_attr "length" "12")])
12045 (define_insn ""
12046 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12047 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12048 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12049 "TARGET_32BIT"
12050 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12051 [(set_attr "length" "12")])
12053 (define_insn ""
12054 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12055 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12056 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
12057 "TARGET_64BIT"
12058 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12059 [(set_attr "length" "12")])
12061 (define_insn ""
12062 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12063 (compare:CC
12064 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12065 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
12066 (const_int 0)))
12067 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12068 (leu:DI (match_dup 1) (match_dup 2)))]
12069 "TARGET_64BIT"
12070 "@
12071 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12072 #"
12073 [(set_attr "type" "compare")
12074 (set_attr "length" "12,16")])
12076 (define_split
12077 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12078 (compare:CC
12079 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12080 (match_operand:DI 2 "reg_or_short_operand" ""))
12081 (const_int 0)))
12082 (set (match_operand:DI 0 "gpc_reg_operand" "")
12083 (leu:DI (match_dup 1) (match_dup 2)))]
12084 "TARGET_64BIT && reload_completed"
12085 [(set (match_dup 0)
12086 (leu:DI (match_dup 1) (match_dup 2)))
12087 (set (match_dup 3)
12088 (compare:CC (match_dup 0)
12089 (const_int 0)))]
12090 "")
12092 (define_insn ""
12093 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12094 (compare:CC
12095 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12096 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12097 (const_int 0)))
12098 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12099 (leu:SI (match_dup 1) (match_dup 2)))]
12100 "TARGET_32BIT"
12101 "@
12102 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12103 #"
12104 [(set_attr "type" "compare")
12105 (set_attr "length" "12,16")])
12107 (define_split
12108 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12109 (compare:CC
12110 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12111 (match_operand:SI 2 "reg_or_short_operand" ""))
12112 (const_int 0)))
12113 (set (match_operand:SI 0 "gpc_reg_operand" "")
12114 (leu:SI (match_dup 1) (match_dup 2)))]
12115 "TARGET_32BIT && reload_completed"
12116 [(set (match_dup 0)
12117 (leu:SI (match_dup 1) (match_dup 2)))
12118 (set (match_dup 3)
12119 (compare:CC (match_dup 0)
12120 (const_int 0)))]
12121 "")
12123 (define_insn ""
12124 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12125 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12126 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12127 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12128 "TARGET_32BIT"
12129 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12130 [(set_attr "length" "8")])
12132 (define_insn ""
12133 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12134 (compare:CC
12135 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12136 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12137 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12138 (const_int 0)))
12139 (clobber (match_scratch:SI 4 "=&r,&r"))]
12140 "TARGET_32BIT"
12141 "@
12142 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12143 #"
12144 [(set_attr "type" "compare")
12145 (set_attr "length" "8,12")])
12147 (define_split
12148 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12149 (compare:CC
12150 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12151 (match_operand:SI 2 "reg_or_short_operand" ""))
12152 (match_operand:SI 3 "gpc_reg_operand" ""))
12153 (const_int 0)))
12154 (clobber (match_scratch:SI 4 ""))]
12155 "TARGET_32BIT && reload_completed"
12156 [(set (match_dup 4)
12157 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12158 (match_dup 3)))
12159 (set (match_dup 0)
12160 (compare:CC (match_dup 4)
12161 (const_int 0)))]
12162 "")
12164 (define_insn ""
12165 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12166 (compare:CC
12167 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12168 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12169 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12170 (const_int 0)))
12171 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12172 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12173 "TARGET_32BIT"
12174 "@
12175 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12176 #"
12177 [(set_attr "type" "compare")
12178 (set_attr "length" "8,12")])
12180 (define_split
12181 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12182 (compare:CC
12183 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12184 (match_operand:SI 2 "reg_or_short_operand" ""))
12185 (match_operand:SI 3 "gpc_reg_operand" ""))
12186 (const_int 0)))
12187 (set (match_operand:SI 0 "gpc_reg_operand" "")
12188 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12189 "TARGET_32BIT && reload_completed"
12190 [(set (match_dup 0)
12191 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12192 (set (match_dup 4)
12193 (compare:CC (match_dup 0)
12194 (const_int 0)))]
12195 "")
12197 (define_insn ""
12198 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12199 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12200 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12201 "TARGET_32BIT"
12202 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12203 [(set_attr "length" "12")])
12205 (define_insn ""
12206 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12207 (and:SI (neg:SI
12208 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12209 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12210 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12211 "TARGET_32BIT"
12212 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12213 [(set_attr "length" "12")])
12215 (define_insn ""
12216 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12217 (compare:CC
12218 (and:SI (neg:SI
12219 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12220 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12221 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12222 (const_int 0)))
12223 (clobber (match_scratch:SI 4 "=&r,&r"))]
12224 "TARGET_32BIT"
12225 "@
12226 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12227 #"
12228 [(set_attr "type" "compare")
12229 (set_attr "length" "12,16")])
12231 (define_split
12232 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12233 (compare:CC
12234 (and:SI (neg:SI
12235 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12236 (match_operand:SI 2 "reg_or_short_operand" "")))
12237 (match_operand:SI 3 "gpc_reg_operand" ""))
12238 (const_int 0)))
12239 (clobber (match_scratch:SI 4 ""))]
12240 "TARGET_32BIT && reload_completed"
12241 [(set (match_dup 4)
12242 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12243 (match_dup 3)))
12244 (set (match_dup 0)
12245 (compare:CC (match_dup 4)
12246 (const_int 0)))]
12247 "")
12249 (define_insn ""
12250 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12251 (compare:CC
12252 (and:SI (neg:SI
12253 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12254 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12255 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12256 (const_int 0)))
12257 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12258 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12259 "TARGET_32BIT"
12260 "@
12261 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12262 #"
12263 [(set_attr "type" "compare")
12264 (set_attr "length" "12,16")])
12266 (define_split
12267 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12268 (compare:CC
12269 (and:SI (neg:SI
12270 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12271 (match_operand:SI 2 "reg_or_short_operand" "")))
12272 (match_operand:SI 3 "gpc_reg_operand" ""))
12273 (const_int 0)))
12274 (set (match_operand:SI 0 "gpc_reg_operand" "")
12275 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12276 "TARGET_32BIT && reload_completed"
12277 [(set (match_dup 0)
12278 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12279 (match_dup 3)))
12280 (set (match_dup 4)
12281 (compare:CC (match_dup 0)
12282 (const_int 0)))]
12283 "")
12285 (define_insn ""
12286 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12287 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12288 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12289 "TARGET_POWER"
12290 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12291 [(set_attr "length" "12")])
12293 (define_insn ""
12294 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12295 (compare:CC
12296 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12297 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12298 (const_int 0)))
12299 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12300 (lt:SI (match_dup 1) (match_dup 2)))]
12301 "TARGET_POWER"
12302 "@
12303 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12304 #"
12305 [(set_attr "type" "delayed_compare")
12306 (set_attr "length" "12,16")])
12308 (define_split
12309 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12310 (compare:CC
12311 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12312 (match_operand:SI 2 "reg_or_short_operand" ""))
12313 (const_int 0)))
12314 (set (match_operand:SI 0 "gpc_reg_operand" "")
12315 (lt:SI (match_dup 1) (match_dup 2)))]
12316 "TARGET_POWER && reload_completed"
12317 [(set (match_dup 0)
12318 (lt:SI (match_dup 1) (match_dup 2)))
12319 (set (match_dup 3)
12320 (compare:CC (match_dup 0)
12321 (const_int 0)))]
12322 "")
12324 (define_insn ""
12325 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12326 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12327 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12328 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12329 "TARGET_POWER"
12330 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12331 [(set_attr "length" "12")])
12333 (define_insn ""
12334 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12335 (compare:CC
12336 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12337 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12338 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12339 (const_int 0)))
12340 (clobber (match_scratch:SI 4 "=&r,&r"))]
12341 "TARGET_POWER"
12342 "@
12343 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12344 #"
12345 [(set_attr "type" "compare")
12346 (set_attr "length" "12,16")])
12348 (define_split
12349 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12350 (compare:CC
12351 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12352 (match_operand:SI 2 "reg_or_short_operand" ""))
12353 (match_operand:SI 3 "gpc_reg_operand" ""))
12354 (const_int 0)))
12355 (clobber (match_scratch:SI 4 ""))]
12356 "TARGET_POWER && reload_completed"
12357 [(set (match_dup 4)
12358 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12359 (match_dup 3)))
12360 (set (match_dup 0)
12361 (compare:CC (match_dup 4)
12362 (const_int 0)))]
12363 "")
12365 (define_insn ""
12366 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12367 (compare:CC
12368 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12369 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12370 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12371 (const_int 0)))
12372 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12373 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12374 "TARGET_POWER"
12375 "@
12376 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12377 #"
12378 [(set_attr "type" "compare")
12379 (set_attr "length" "12,16")])
12381 (define_split
12382 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12383 (compare:CC
12384 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12385 (match_operand:SI 2 "reg_or_short_operand" ""))
12386 (match_operand:SI 3 "gpc_reg_operand" ""))
12387 (const_int 0)))
12388 (set (match_operand:SI 0 "gpc_reg_operand" "")
12389 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12390 "TARGET_POWER && reload_completed"
12391 [(set (match_dup 0)
12392 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12393 (set (match_dup 4)
12394 (compare:CC (match_dup 0)
12395 (const_int 0)))]
12396 "")
12398 (define_insn ""
12399 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12400 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12401 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12402 "TARGET_POWER"
12403 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12404 [(set_attr "length" "12")])
12406 (define_insn ""
12407 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12408 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12409 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12410 "TARGET_32BIT"
12411 "@
12412 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
12413 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
12414 [(set_attr "length" "12")])
12416 (define_insn ""
12417 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12418 (compare:CC
12419 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12420 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12421 (const_int 0)))
12422 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12423 (ltu:SI (match_dup 1) (match_dup 2)))]
12424 "TARGET_32BIT"
12425 "@
12426 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12427 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12428 #
12429 #"
12430 [(set_attr "type" "compare")
12431 (set_attr "length" "12,12,16,16")])
12433 (define_split
12434 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12435 (compare:CC
12436 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12437 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12438 (const_int 0)))
12439 (set (match_operand:SI 0 "gpc_reg_operand" "")
12440 (ltu:SI (match_dup 1) (match_dup 2)))]
12441 "TARGET_32BIT && reload_completed"
12442 [(set (match_dup 0)
12443 (ltu:SI (match_dup 1) (match_dup 2)))
12444 (set (match_dup 3)
12445 (compare:CC (match_dup 0)
12446 (const_int 0)))]
12447 "")
12449 (define_insn ""
12450 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12451 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12452 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12453 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
12454 "TARGET_32BIT"
12455 "@
12456 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3
12457 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
12458 [(set_attr "length" "12")])
12460 (define_insn ""
12461 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12462 (compare:CC
12463 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12464 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12465 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12466 (const_int 0)))
12467 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12468 "TARGET_32BIT"
12469 "@
12470 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12471 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12472 #
12473 #"
12474 [(set_attr "type" "compare")
12475 (set_attr "length" "12,12,16,16")])
12477 (define_split
12478 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12479 (compare:CC
12480 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12481 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12482 (match_operand:SI 3 "gpc_reg_operand" ""))
12483 (const_int 0)))
12484 (clobber (match_scratch:SI 4 ""))]
12485 "TARGET_32BIT && reload_completed"
12486 [(set (match_dup 4)
12487 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
12488 (match_dup 3)))
12489 (set (match_dup 0)
12490 (compare:CC (match_dup 4)
12491 (const_int 0)))]
12492 "")
12494 (define_insn ""
12495 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12496 (compare:CC
12497 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12498 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12499 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12500 (const_int 0)))
12501 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12502 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12503 "TARGET_32BIT"
12504 "@
12505 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12506 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12507 #
12508 #"
12509 [(set_attr "type" "compare")
12510 (set_attr "length" "12,12,16,16")])
12512 (define_split
12513 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12514 (compare:CC
12515 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12516 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12517 (match_operand:SI 3 "gpc_reg_operand" ""))
12518 (const_int 0)))
12519 (set (match_operand:SI 0 "gpc_reg_operand" "")
12520 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12521 "TARGET_32BIT && reload_completed"
12522 [(set (match_dup 0)
12523 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12524 (set (match_dup 4)
12525 (compare:CC (match_dup 0)
12526 (const_int 0)))]
12527 "")
12529 (define_insn ""
12530 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12531 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12532 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12533 "TARGET_32BIT"
12534 "@
12535 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12536 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12537 [(set_attr "length" "8")])
12539 (define_insn ""
12540 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12541 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12542 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12543 (clobber (match_scratch:SI 3 "=r"))]
12544 "TARGET_POWER"
12545 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12546 [(set_attr "length" "12")])
12548 (define_insn ""
12549 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12550 (compare:CC
12551 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12552 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12553 (const_int 0)))
12554 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12555 (ge:SI (match_dup 1) (match_dup 2)))
12556 (clobber (match_scratch:SI 3 "=r,r"))]
12557 "TARGET_POWER"
12558 "@
12559 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12560 #"
12561 [(set_attr "type" "compare")
12562 (set_attr "length" "12,16")])
12564 (define_split
12565 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12566 (compare:CC
12567 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12568 (match_operand:SI 2 "reg_or_short_operand" ""))
12569 (const_int 0)))
12570 (set (match_operand:SI 0 "gpc_reg_operand" "")
12571 (ge:SI (match_dup 1) (match_dup 2)))
12572 (clobber (match_scratch:SI 3 ""))]
12573 "TARGET_POWER && reload_completed"
12574 [(parallel [(set (match_dup 0)
12575 (ge:SI (match_dup 1) (match_dup 2)))
12576 (clobber (match_dup 3))])
12577 (set (match_dup 4)
12578 (compare:CC (match_dup 0)
12579 (const_int 0)))]
12580 "")
12582 (define_insn ""
12583 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12584 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12585 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12586 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12587 "TARGET_POWER"
12588 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12589 [(set_attr "length" "12")])
12591 (define_insn ""
12592 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12593 (compare:CC
12594 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12595 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12596 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12597 (const_int 0)))
12598 (clobber (match_scratch:SI 4 "=&r,&r"))]
12599 "TARGET_POWER"
12600 "@
12601 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12602 #"
12603 [(set_attr "type" "compare")
12604 (set_attr "length" "12,16")])
12606 (define_split
12607 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12608 (compare:CC
12609 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12610 (match_operand:SI 2 "reg_or_short_operand" ""))
12611 (match_operand:SI 3 "gpc_reg_operand" ""))
12612 (const_int 0)))
12613 (clobber (match_scratch:SI 4 ""))]
12614 "TARGET_POWER && reload_completed"
12615 [(set (match_dup 4)
12616 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12617 (match_dup 3)))
12618 (set (match_dup 0)
12619 (compare:CC (match_dup 4)
12620 (const_int 0)))]
12621 "")
12623 (define_insn ""
12624 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12625 (compare:CC
12626 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12627 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12628 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12629 (const_int 0)))
12630 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12631 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12632 "TARGET_POWER"
12633 "@
12634 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12635 #"
12636 [(set_attr "type" "compare")
12637 (set_attr "length" "12,16")])
12639 (define_split
12640 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12641 (compare:CC
12642 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12643 (match_operand:SI 2 "reg_or_short_operand" ""))
12644 (match_operand:SI 3 "gpc_reg_operand" ""))
12645 (const_int 0)))
12646 (set (match_operand:SI 0 "gpc_reg_operand" "")
12647 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12648 "TARGET_POWER && reload_completed"
12649 [(set (match_dup 0)
12650 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12651 (set (match_dup 4)
12652 (compare:CC (match_dup 0)
12653 (const_int 0)))]
12654 "")
12656 (define_insn ""
12657 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12658 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12659 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12660 "TARGET_POWER"
12661 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12662 [(set_attr "length" "12")])
12664 (define_insn ""
12665 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12666 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12667 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12668 "TARGET_32BIT"
12669 "@
12670 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12671 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12672 [(set_attr "length" "12")])
12674 (define_insn ""
12675 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12676 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12677 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12678 "TARGET_64BIT"
12679 "@
12680 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12681 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12682 [(set_attr "length" "12")])
12684 (define_insn ""
12685 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12686 (compare:CC
12687 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12688 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12689 (const_int 0)))
12690 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12691 (geu:SI (match_dup 1) (match_dup 2)))]
12692 "TARGET_32BIT"
12693 "@
12694 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12695 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12696 #
12697 #"
12698 [(set_attr "type" "compare")
12699 (set_attr "length" "12,12,16,16")])
12701 (define_split
12702 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12703 (compare:CC
12704 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12705 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12706 (const_int 0)))
12707 (set (match_operand:SI 0 "gpc_reg_operand" "")
12708 (geu:SI (match_dup 1) (match_dup 2)))]
12709 "TARGET_32BIT && reload_completed"
12710 [(set (match_dup 0)
12711 (geu:SI (match_dup 1) (match_dup 2)))
12712 (set (match_dup 3)
12713 (compare:CC (match_dup 0)
12714 (const_int 0)))]
12715 "")
12717 (define_insn ""
12718 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12719 (compare:CC
12720 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12721 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12722 (const_int 0)))
12723 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12724 (geu:DI (match_dup 1) (match_dup 2)))]
12725 "TARGET_64BIT"
12726 "@
12727 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12728 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12729 #
12730 #"
12731 [(set_attr "type" "compare")
12732 (set_attr "length" "12,12,16,16")])
12734 (define_split
12735 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12736 (compare:CC
12737 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12738 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12739 (const_int 0)))
12740 (set (match_operand:DI 0 "gpc_reg_operand" "")
12741 (geu:DI (match_dup 1) (match_dup 2)))]
12742 "TARGET_64BIT && reload_completed"
12743 [(set (match_dup 0)
12744 (geu:DI (match_dup 1) (match_dup 2)))
12745 (set (match_dup 3)
12746 (compare:CC (match_dup 0)
12747 (const_int 0)))]
12748 "")
12750 (define_insn ""
12751 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12752 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12753 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12754 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12755 "TARGET_32BIT"
12756 "@
12757 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12758 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12759 [(set_attr "length" "8")])
12761 (define_insn ""
12762 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12763 (compare:CC
12764 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12765 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12766 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12767 (const_int 0)))
12768 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12769 "TARGET_32BIT"
12770 "@
12771 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12772 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12773 #
12774 #"
12775 [(set_attr "type" "compare")
12776 (set_attr "length" "8,8,12,12")])
12778 (define_split
12779 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12780 (compare:CC
12781 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12782 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12783 (match_operand:SI 3 "gpc_reg_operand" ""))
12784 (const_int 0)))
12785 (clobber (match_scratch:SI 4 ""))]
12786 "TARGET_32BIT && reload_completed"
12787 [(set (match_dup 4)
12788 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12789 (match_dup 3)))
12790 (set (match_dup 0)
12791 (compare:CC (match_dup 4)
12792 (const_int 0)))]
12793 "")
12795 (define_insn ""
12796 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12797 (compare:CC
12798 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12799 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12800 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12801 (const_int 0)))
12802 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12803 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12804 "TARGET_32BIT"
12805 "@
12806 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12807 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12808 #
12809 #"
12810 [(set_attr "type" "compare")
12811 (set_attr "length" "8,8,12,12")])
12813 (define_split
12814 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12815 (compare:CC
12816 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12817 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12818 (match_operand:SI 3 "gpc_reg_operand" ""))
12819 (const_int 0)))
12820 (set (match_operand:SI 0 "gpc_reg_operand" "")
12821 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12822 "TARGET_32BIT && reload_completed"
12823 [(set (match_dup 0)
12824 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12825 (set (match_dup 4)
12826 (compare:CC (match_dup 0)
12827 (const_int 0)))]
12828 "")
12830 (define_insn ""
12831 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12832 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12833 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
12834 "TARGET_32BIT"
12835 "@
12836 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12837 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12838 [(set_attr "length" "12")])
12840 (define_insn ""
12841 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12842 (and:SI (neg:SI
12843 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12844 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
12845 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12846 "TARGET_32BIT"
12847 "@
12848 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12849 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12850 [(set_attr "length" "12")])
12852 (define_insn ""
12853 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12854 (compare:CC
12855 (and:SI (neg:SI
12856 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12857 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12858 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12859 (const_int 0)))
12860 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12861 "TARGET_32BIT"
12862 "@
12863 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12864 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12865 #
12866 #"
12867 [(set_attr "type" "compare")
12868 (set_attr "length" "12,12,16,16")])
12870 (define_split
12871 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12872 (compare:CC
12873 (and:SI (neg:SI
12874 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12875 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12876 (match_operand:SI 3 "gpc_reg_operand" ""))
12877 (const_int 0)))
12878 (clobber (match_scratch:SI 4 ""))]
12879 "TARGET_32BIT && reload_completed"
12880 [(set (match_dup 4)
12881 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12882 (match_dup 3)))
12883 (set (match_dup 0)
12884 (compare:CC (match_dup 4)
12885 (const_int 0)))]
12886 "")
12888 (define_insn ""
12889 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12890 (compare:CC
12891 (and:SI (neg:SI
12892 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12893 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12894 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12895 (const_int 0)))
12896 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12897 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12898 "TARGET_32BIT"
12899 "@
12900 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12901 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12902 #
12903 #"
12904 [(set_attr "type" "compare")
12905 (set_attr "length" "12,12,16,16")])
12907 (define_split
12908 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12909 (compare:CC
12910 (and:SI (neg:SI
12911 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12912 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12913 (match_operand:SI 3 "gpc_reg_operand" ""))
12914 (const_int 0)))
12915 (set (match_operand:SI 0 "gpc_reg_operand" "")
12916 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12917 "TARGET_32BIT && reload_completed"
12918 [(set (match_dup 0)
12919 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12920 (set (match_dup 4)
12921 (compare:CC (match_dup 0)
12922 (const_int 0)))]
12923 "")
12925 (define_insn ""
12926 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12927 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12928 (const_int 0)))]
12929 "TARGET_32BIT"
12930 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
12931 [(set_attr "length" "12")])
12933 (define_insn ""
12934 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12935 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12936 (const_int 0)))]
12937 "TARGET_64BIT"
12938 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
12939 [(set_attr "length" "12")])
12941 (define_insn ""
12942 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12943 (compare:CC
12944 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12945 (const_int 0))
12946 (const_int 0)))
12947 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12948 (gt:SI (match_dup 1) (const_int 0)))]
12949 "TARGET_32BIT"
12950 "@
12951 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
12952 #"
12953 [(set_attr "type" "delayed_compare")
12954 (set_attr "length" "12,16")])
12956 (define_split
12957 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12958 (compare:CC
12959 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12960 (const_int 0))
12961 (const_int 0)))
12962 (set (match_operand:SI 0 "gpc_reg_operand" "")
12963 (gt:SI (match_dup 1) (const_int 0)))]
12964 "TARGET_32BIT && reload_completed"
12965 [(set (match_dup 0)
12966 (gt:SI (match_dup 1) (const_int 0)))
12967 (set (match_dup 2)
12968 (compare:CC (match_dup 0)
12969 (const_int 0)))]
12970 "")
12972 (define_insn ""
12973 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12974 (compare:CC
12975 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12976 (const_int 0))
12977 (const_int 0)))
12978 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12979 (gt:DI (match_dup 1) (const_int 0)))]
12980 "TARGET_64BIT"
12981 "@
12982 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
12983 #"
12984 [(set_attr "type" "delayed_compare")
12985 (set_attr "length" "12,16")])
12987 (define_split
12988 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12989 (compare:CC
12990 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12991 (const_int 0))
12992 (const_int 0)))
12993 (set (match_operand:DI 0 "gpc_reg_operand" "")
12994 (gt:DI (match_dup 1) (const_int 0)))]
12995 "TARGET_64BIT && reload_completed"
12996 [(set (match_dup 0)
12997 (gt:DI (match_dup 1) (const_int 0)))
12998 (set (match_dup 2)
12999 (compare:CC (match_dup 0)
13000 (const_int 0)))]
13001 "")
13003 (define_insn ""
13004 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13005 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13006 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13007 "TARGET_POWER"
13008 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13009 [(set_attr "length" "12")])
13011 (define_insn ""
13012 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13013 (compare:CC
13014 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13015 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13016 (const_int 0)))
13017 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13018 (gt:SI (match_dup 1) (match_dup 2)))]
13019 "TARGET_POWER"
13020 "@
13021 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13022 #"
13023 [(set_attr "type" "delayed_compare")
13024 (set_attr "length" "12,16")])
13026 (define_split
13027 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13028 (compare:CC
13029 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13030 (match_operand:SI 2 "reg_or_short_operand" ""))
13031 (const_int 0)))
13032 (set (match_operand:SI 0 "gpc_reg_operand" "")
13033 (gt:SI (match_dup 1) (match_dup 2)))]
13034 "TARGET_POWER && reload_completed"
13035 [(set (match_dup 0)
13036 (gt:SI (match_dup 1) (match_dup 2)))
13037 (set (match_dup 3)
13038 (compare:CC (match_dup 0)
13039 (const_int 0)))]
13040 "")
13042 (define_insn ""
13043 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13044 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13045 (const_int 0))
13046 (match_operand:SI 2 "gpc_reg_operand" "r")))]
13047 "TARGET_32BIT"
13048 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13049 [(set_attr "length" "12")])
13051 (define_insn ""
13052 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13053 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13054 (const_int 0))
13055 (match_operand:DI 2 "gpc_reg_operand" "r")))]
13056 "TARGET_64BIT"
13057 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
13058 [(set_attr "length" "12")])
13060 (define_insn ""
13061 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13062 (compare:CC
13063 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13064 (const_int 0))
13065 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13066 (const_int 0)))
13067 (clobber (match_scratch:SI 3 "=&r,&r"))]
13068 "TARGET_32BIT"
13069 "@
13070 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13071 #"
13072 [(set_attr "type" "compare")
13073 (set_attr "length" "12,16")])
13075 (define_split
13076 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13077 (compare:CC
13078 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13079 (const_int 0))
13080 (match_operand:SI 2 "gpc_reg_operand" ""))
13081 (const_int 0)))
13082 (clobber (match_scratch:SI 3 ""))]
13083 "TARGET_32BIT && reload_completed"
13084 [(set (match_dup 3)
13085 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13086 (match_dup 2)))
13087 (set (match_dup 0)
13088 (compare:CC (match_dup 3)
13089 (const_int 0)))]
13090 "")
13092 (define_insn ""
13093 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13094 (compare:CC
13095 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13096 (const_int 0))
13097 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13098 (const_int 0)))
13099 (clobber (match_scratch:DI 3 "=&r,&r"))]
13100 "TARGET_64BIT"
13101 "@
13102 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13103 #"
13104 [(set_attr "type" "compare")
13105 (set_attr "length" "12,16")])
13107 (define_split
13108 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13109 (compare:CC
13110 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13111 (const_int 0))
13112 (match_operand:DI 2 "gpc_reg_operand" ""))
13113 (const_int 0)))
13114 (clobber (match_scratch:DI 3 ""))]
13115 "TARGET_64BIT && reload_completed"
13116 [(set (match_dup 3)
13117 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13118 (match_dup 2)))
13119 (set (match_dup 0)
13120 (compare:CC (match_dup 3)
13121 (const_int 0)))]
13122 "")
13124 (define_insn ""
13125 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13126 (compare:CC
13127 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13128 (const_int 0))
13129 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13130 (const_int 0)))
13131 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13132 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13133 "TARGET_32BIT"
13134 "@
13135 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13136 #"
13137 [(set_attr "type" "compare")
13138 (set_attr "length" "12,16")])
13140 (define_split
13141 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13142 (compare:CC
13143 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13144 (const_int 0))
13145 (match_operand:SI 2 "gpc_reg_operand" ""))
13146 (const_int 0)))
13147 (set (match_operand:SI 0 "gpc_reg_operand" "")
13148 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13149 "TARGET_32BIT && reload_completed"
13150 [(set (match_dup 0)
13151 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13152 (set (match_dup 3)
13153 (compare:CC (match_dup 0)
13154 (const_int 0)))]
13155 "")
13157 (define_insn ""
13158 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13159 (compare:CC
13160 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13161 (const_int 0))
13162 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13163 (const_int 0)))
13164 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13165 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13166 "TARGET_64BIT"
13167 "@
13168 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13169 #"
13170 [(set_attr "type" "compare")
13171 (set_attr "length" "12,16")])
13173 (define_split
13174 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13175 (compare:CC
13176 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13177 (const_int 0))
13178 (match_operand:DI 2 "gpc_reg_operand" ""))
13179 (const_int 0)))
13180 (set (match_operand:DI 0 "gpc_reg_operand" "")
13181 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13182 "TARGET_64BIT && reload_completed"
13183 [(set (match_dup 0)
13184 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13185 (set (match_dup 3)
13186 (compare:CC (match_dup 0)
13187 (const_int 0)))]
13188 "")
13190 (define_insn ""
13191 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13192 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13193 (match_operand:SI 2 "reg_or_short_operand" "r"))
13194 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13195 "TARGET_POWER"
13196 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13197 [(set_attr "length" "12")])
13199 (define_insn ""
13200 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13201 (compare:CC
13202 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13203 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13204 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13205 (const_int 0)))
13206 (clobber (match_scratch:SI 4 "=&r,&r"))]
13207 "TARGET_POWER"
13208 "@
13209 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13210 #"
13211 [(set_attr "type" "compare")
13212 (set_attr "length" "12,16")])
13214 (define_split
13215 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13216 (compare:CC
13217 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13218 (match_operand:SI 2 "reg_or_short_operand" ""))
13219 (match_operand:SI 3 "gpc_reg_operand" ""))
13220 (const_int 0)))
13221 (clobber (match_scratch:SI 4 ""))]
13222 "TARGET_POWER && reload_completed"
13223 [(set (match_dup 4)
13224 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13225 (set (match_dup 0)
13226 (compare:CC (match_dup 4)
13227 (const_int 0)))]
13228 "")
13230 (define_insn ""
13231 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13232 (compare:CC
13233 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13234 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13235 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13236 (const_int 0)))
13237 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13238 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13239 "TARGET_POWER"
13240 "@
13241 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13242 #"
13243 [(set_attr "type" "compare")
13244 (set_attr "length" "12,16")])
13246 (define_split
13247 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13248 (compare:CC
13249 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13250 (match_operand:SI 2 "reg_or_short_operand" ""))
13251 (match_operand:SI 3 "gpc_reg_operand" ""))
13252 (const_int 0)))
13253 (set (match_operand:SI 0 "gpc_reg_operand" "")
13254 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13255 "TARGET_POWER && reload_completed"
13256 [(set (match_dup 0)
13257 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13258 (set (match_dup 4)
13259 (compare:CC (match_dup 0)
13260 (const_int 0)))]
13261 "")
13263 (define_insn ""
13264 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13265 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13266 (const_int 0))))]
13267 "TARGET_32BIT"
13268 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
13269 [(set_attr "length" "12")])
13271 (define_insn ""
13272 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13273 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13274 (const_int 0))))]
13275 "TARGET_64BIT"
13276 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
13277 [(set_attr "length" "12")])
13279 (define_insn ""
13280 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13281 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13282 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13283 "TARGET_POWER"
13284 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13285 [(set_attr "length" "12")])
13287 (define_insn ""
13288 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13289 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13290 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13291 "TARGET_32BIT"
13292 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
13293 [(set_attr "length" "12")])
13295 (define_insn ""
13296 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13297 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13298 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13299 "TARGET_64BIT"
13300 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
13301 [(set_attr "length" "12")])
13303 (define_insn ""
13304 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13305 (compare:CC
13306 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13307 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13308 (const_int 0)))
13309 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13310 (gtu:SI (match_dup 1) (match_dup 2)))]
13311 "TARGET_32BIT"
13312 "@
13313 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13314 #"
13315 [(set_attr "type" "compare")
13316 (set_attr "length" "12,16")])
13318 (define_split
13319 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13320 (compare:CC
13321 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13322 (match_operand:SI 2 "reg_or_short_operand" ""))
13323 (const_int 0)))
13324 (set (match_operand:SI 0 "gpc_reg_operand" "")
13325 (gtu:SI (match_dup 1) (match_dup 2)))]
13326 "TARGET_32BIT && reload_completed"
13327 [(set (match_dup 0)
13328 (gtu:SI (match_dup 1) (match_dup 2)))
13329 (set (match_dup 3)
13330 (compare:CC (match_dup 0)
13331 (const_int 0)))]
13332 "")
13334 (define_insn ""
13335 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13336 (compare:CC
13337 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13338 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
13339 (const_int 0)))
13340 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13341 (gtu:DI (match_dup 1) (match_dup 2)))]
13342 "TARGET_64BIT"
13343 "@
13344 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13345 #"
13346 [(set_attr "type" "compare")
13347 (set_attr "length" "12,16")])
13349 (define_split
13350 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13351 (compare:CC
13352 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13353 (match_operand:DI 2 "reg_or_short_operand" ""))
13354 (const_int 0)))
13355 (set (match_operand:DI 0 "gpc_reg_operand" "")
13356 (gtu:DI (match_dup 1) (match_dup 2)))]
13357 "TARGET_64BIT && reload_completed"
13358 [(set (match_dup 0)
13359 (gtu:DI (match_dup 1) (match_dup 2)))
13360 (set (match_dup 3)
13361 (compare:CC (match_dup 0)
13362 (const_int 0)))]
13363 "")
13365 (define_insn ""
13366 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13367 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13368 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
13369 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))]
13370 "TARGET_32BIT"
13371 "@
13372 {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3
13373 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
13374 [(set_attr "length" "8,12")])
13376 (define_insn ""
13377 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13378 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13379 (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
13380 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))]
13381 "TARGET_64BIT"
13382 "@
13383 addic %0,%1,%k2\;addze %0,%3
13384 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3"
13385 [(set_attr "length" "8,12")])
13387 (define_insn ""
13388 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13389 (compare:CC
13390 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13391 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13392 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13393 (const_int 0)))
13394 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13395 "TARGET_32BIT"
13396 "@
13397 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
13398 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
13399 #
13400 #"
13401 [(set_attr "type" "compare")
13402 (set_attr "length" "8,12,12,16")])
13404 (define_split
13405 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13406 (compare:CC
13407 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13408 (match_operand:SI 2 "reg_or_short_operand" ""))
13409 (match_operand:SI 3 "gpc_reg_operand" ""))
13410 (const_int 0)))
13411 (clobber (match_scratch:SI 4 ""))]
13412 "TARGET_32BIT && reload_completed"
13413 [(set (match_dup 4)
13414 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
13415 (match_dup 3)))
13416 (set (match_dup 0)
13417 (compare:CC (match_dup 4)
13418 (const_int 0)))]
13419 "")
13421 (define_insn ""
13422 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13423 (compare:CC
13424 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13425 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13426 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13427 (const_int 0)))
13428 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
13429 "TARGET_64BIT"
13430 "@
13431 addic %4,%1,%k2\;addze. %4,%3
13432 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3
13433 #
13434 #"
13435 [(set_attr "type" "compare")
13436 (set_attr "length" "8,12,12,16")])
13438 (define_split
13439 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13440 (compare:CC
13441 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13442 (match_operand:DI 2 "reg_or_short_operand" ""))
13443 (match_operand:DI 3 "gpc_reg_operand" ""))
13444 (const_int 0)))
13445 (clobber (match_scratch:DI 4 ""))]
13446 "TARGET_64BIT && reload_completed"
13447 [(set (match_dup 4)
13448 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13449 (match_dup 3)))
13450 (set (match_dup 0)
13451 (compare:CC (match_dup 4)
13452 (const_int 0)))]
13453 "")
13455 (define_insn ""
13456 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13457 (compare:CC
13458 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13459 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13460 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13461 (const_int 0)))
13462 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13463 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13464 "TARGET_32BIT"
13465 "@
13466 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13467 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
13468 #
13469 #"
13470 [(set_attr "type" "compare")
13471 (set_attr "length" "8,12,12,16")])
13473 (define_split
13474 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13475 (compare:CC
13476 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13477 (match_operand:SI 2 "reg_or_short_operand" ""))
13478 (match_operand:SI 3 "gpc_reg_operand" ""))
13479 (const_int 0)))
13480 (set (match_operand:SI 0 "gpc_reg_operand" "")
13481 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13482 "TARGET_32BIT && reload_completed"
13483 [(set (match_dup 0)
13484 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13485 (set (match_dup 4)
13486 (compare:CC (match_dup 0)
13487 (const_int 0)))]
13488 "")
13490 (define_insn ""
13491 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13492 (compare:CC
13493 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13494 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13495 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13496 (const_int 0)))
13497 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13498 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13499 "TARGET_64BIT"
13500 "@
13501 addic %0,%1,%k2\;addze. %0,%3
13502 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3
13503 #
13504 #"
13505 [(set_attr "type" "compare")
13506 (set_attr "length" "8,12,12,16")])
13508 (define_split
13509 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13510 (compare:CC
13511 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13512 (match_operand:DI 2 "reg_or_short_operand" ""))
13513 (match_operand:DI 3 "gpc_reg_operand" ""))
13514 (const_int 0)))
13515 (set (match_operand:DI 0 "gpc_reg_operand" "")
13516 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13517 "TARGET_64BIT && reload_completed"
13518 [(set (match_dup 0)
13519 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
13520 (set (match_dup 4)
13521 (compare:CC (match_dup 0)
13522 (const_int 0)))]
13523 "")
13525 (define_insn ""
13526 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13527 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13528 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13529 "TARGET_32BIT"
13530 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13531 [(set_attr "length" "8")])
13533 (define_insn ""
13534 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13535 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13536 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13537 "TARGET_64BIT"
13538 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13539 [(set_attr "length" "8")])
13540 \f
13541 ;; Define both directions of branch and return. If we need a reload
13542 ;; register, we'd rather use CR0 since it is much easier to copy a
13543 ;; register CC value to there.
13545 (define_insn ""
13546 [(set (pc)
13547 (if_then_else (match_operator 1 "branch_comparison_operator"
13548 [(match_operand 2
13549 "cc_reg_operand" "y")
13550 (const_int 0)])
13551 (label_ref (match_operand 0 "" ""))
13552 (pc)))]
13553 ""
13554 "*
13555 {
13556 return output_cbranch (operands[1], \"%l0\", 0, insn);
13557 }"
13558 [(set_attr "type" "branch")])
13560 (define_insn ""
13561 [(set (pc)
13562 (if_then_else (match_operator 0 "branch_comparison_operator"
13563 [(match_operand 1
13564 "cc_reg_operand" "y")
13565 (const_int 0)])
13566 (return)
13567 (pc)))]
13568 "direct_return ()"
13569 "*
13570 {
13571 return output_cbranch (operands[0], NULL, 0, insn);
13572 }"
13573 [(set_attr "type" "branch")
13574 (set_attr "length" "4")])
13576 (define_insn ""
13577 [(set (pc)
13578 (if_then_else (match_operator 1 "branch_comparison_operator"
13579 [(match_operand 2
13580 "cc_reg_operand" "y")
13581 (const_int 0)])
13582 (pc)
13583 (label_ref (match_operand 0 "" ""))))]
13584 ""
13585 "*
13586 {
13587 return output_cbranch (operands[1], \"%l0\", 1, insn);
13588 }"
13589 [(set_attr "type" "branch")])
13591 (define_insn ""
13592 [(set (pc)
13593 (if_then_else (match_operator 0 "branch_comparison_operator"
13594 [(match_operand 1
13595 "cc_reg_operand" "y")
13596 (const_int 0)])
13597 (pc)
13598 (return)))]
13599 "direct_return ()"
13600 "*
13601 {
13602 return output_cbranch (operands[0], NULL, 1, insn);
13603 }"
13604 [(set_attr "type" "branch")
13605 (set_attr "length" "4")])
13607 ;; Logic on condition register values.
13609 ; This pattern matches things like
13610 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13611 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13612 ; (const_int 1)))
13613 ; which are generated by the branch logic.
13614 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13616 (define_insn ""
13617 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13618 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13619 [(match_operator:SI 2
13620 "branch_positive_comparison_operator"
13621 [(match_operand 3
13622 "cc_reg_operand" "y,y")
13623 (const_int 0)])
13624 (match_operator:SI 4
13625 "branch_positive_comparison_operator"
13626 [(match_operand 5
13627 "cc_reg_operand" "0,y")
13628 (const_int 0)])])
13629 (const_int 1)))]
13630 ""
13631 "cr%q1 %E0,%j2,%j4"
13632 [(set_attr "type" "cr_logical,delayed_cr")])
13634 ; Why is the constant -1 here, but 1 in the previous pattern?
13635 ; Because ~1 has all but the low bit set.
13636 (define_insn ""
13637 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13638 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13639 [(not:SI (match_operator:SI 2
13640 "branch_positive_comparison_operator"
13641 [(match_operand 3
13642 "cc_reg_operand" "y,y")
13643 (const_int 0)]))
13644 (match_operator:SI 4
13645 "branch_positive_comparison_operator"
13646 [(match_operand 5
13647 "cc_reg_operand" "0,y")
13648 (const_int 0)])])
13649 (const_int -1)))]
13650 ""
13651 "cr%q1 %E0,%j2,%j4"
13652 [(set_attr "type" "cr_logical,delayed_cr")])
13654 (define_insn ""
13655 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13656 (compare:CCEQ (match_operator:SI 1
13657 "branch_positive_comparison_operator"
13658 [(match_operand 2
13659 "cc_reg_operand" "0,y")
13660 (const_int 0)])
13661 (const_int 0)))]
13662 "!TARGET_SPE"
13663 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13664 [(set_attr "type" "cr_logical,delayed_cr")])
13666 ;; If we are comparing the result of two comparisons, this can be done
13667 ;; using creqv or crxor.
13669 (define_insn_and_split ""
13670 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13671 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13672 [(match_operand 2 "cc_reg_operand" "y")
13673 (const_int 0)])
13674 (match_operator 3 "branch_comparison_operator"
13675 [(match_operand 4 "cc_reg_operand" "y")
13676 (const_int 0)])))]
13677 ""
13678 "#"
13679 ""
13680 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13681 (match_dup 5)))]
13682 "
13683 {
13684 int positive_1, positive_2;
13686 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode);
13687 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode);
13689 if (! positive_1)
13690 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13691 GET_CODE (operands[1])),
13692 SImode,
13693 operands[2], const0_rtx);
13694 else if (GET_MODE (operands[1]) != SImode)
13695 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13696 operands[2], const0_rtx);
13698 if (! positive_2)
13699 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13700 GET_CODE (operands[3])),
13701 SImode,
13702 operands[4], const0_rtx);
13703 else if (GET_MODE (operands[3]) != SImode)
13704 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13705 operands[4], const0_rtx);
13707 if (positive_1 == positive_2)
13708 {
13709 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13710 operands[5] = constm1_rtx;
13711 }
13712 else
13713 {
13714 operands[5] = const1_rtx;
13715 }
13716 }")
13718 ;; Unconditional branch and return.
13720 (define_insn "jump"
13721 [(set (pc)
13722 (label_ref (match_operand 0 "" "")))]
13723 ""
13724 "b %l0"
13725 [(set_attr "type" "branch")])
13727 (define_insn "return"
13728 [(return)]
13729 "direct_return ()"
13730 "{br|blr}"
13731 [(set_attr "type" "jmpreg")])
13733 (define_expand "indirect_jump"
13734 [(set (pc) (match_operand 0 "register_operand" ""))]
13735 ""
13736 "
13737 {
13738 if (TARGET_32BIT)
13739 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
13740 else
13741 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
13742 DONE;
13743 }")
13745 (define_insn "indirect_jumpsi"
13746 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
13747 "TARGET_32BIT"
13748 "@
13749 bctr
13750 {br|blr}"
13751 [(set_attr "type" "jmpreg")])
13753 (define_insn "indirect_jumpdi"
13754 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
13755 "TARGET_64BIT"
13756 "@
13757 bctr
13758 blr"
13759 [(set_attr "type" "jmpreg")])
13761 ;; Table jump for switch statements:
13762 (define_expand "tablejump"
13763 [(use (match_operand 0 "" ""))
13764 (use (label_ref (match_operand 1 "" "")))]
13765 ""
13766 "
13767 {
13768 if (TARGET_32BIT)
13769 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13770 else
13771 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13772 DONE;
13773 }")
13775 (define_expand "tablejumpsi"
13776 [(set (match_dup 3)
13777 (plus:SI (match_operand:SI 0 "" "")
13778 (match_dup 2)))
13779 (parallel [(set (pc) (match_dup 3))
13780 (use (label_ref (match_operand 1 "" "")))])]
13781 "TARGET_32BIT"
13782 "
13783 { operands[0] = force_reg (SImode, operands[0]);
13784 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13785 operands[3] = gen_reg_rtx (SImode);
13786 }")
13788 (define_expand "tablejumpdi"
13789 [(set (match_dup 4)
13790 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13791 (set (match_dup 3)
13792 (plus:DI (match_dup 4)
13793 (match_dup 2)))
13794 (parallel [(set (pc) (match_dup 3))
13795 (use (label_ref (match_operand 1 "" "")))])]
13796 "TARGET_64BIT"
13797 "
13798 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13799 operands[3] = gen_reg_rtx (DImode);
13800 operands[4] = gen_reg_rtx (DImode);
13801 }")
13803 (define_insn ""
13804 [(set (pc)
13805 (match_operand:SI 0 "register_operand" "c,*l"))
13806 (use (label_ref (match_operand 1 "" "")))]
13807 "TARGET_32BIT"
13808 "@
13809 bctr
13810 {br|blr}"
13811 [(set_attr "type" "jmpreg")])
13813 (define_insn ""
13814 [(set (pc)
13815 (match_operand:DI 0 "register_operand" "c,*l"))
13816 (use (label_ref (match_operand 1 "" "")))]
13817 "TARGET_64BIT"
13818 "@
13819 bctr
13820 blr"
13821 [(set_attr "type" "jmpreg")])
13823 (define_insn "nop"
13824 [(const_int 0)]
13825 ""
13826 "{cror 0,0,0|nop}")
13827 \f
13828 ;; Define the subtract-one-and-jump insns, starting with the template
13829 ;; so loop.c knows what to generate.
13831 (define_expand "doloop_end"
13832 [(use (match_operand 0 "" "")) ; loop pseudo
13833 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13834 (use (match_operand 2 "" "")) ; max iterations
13835 (use (match_operand 3 "" "")) ; loop level
13836 (use (match_operand 4 "" ""))] ; label
13837 ""
13838 "
13839 {
13840 /* Only use this on innermost loops. */
13841 if (INTVAL (operands[3]) > 1)
13842 FAIL;
13843 if (TARGET_64BIT)
13844 {
13845 if (GET_MODE (operands[0]) != DImode)
13846 FAIL;
13847 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13848 }
13849 else
13850 {
13851 if (GET_MODE (operands[0]) != SImode)
13852 FAIL;
13853 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13854 }
13855 DONE;
13856 }")
13858 (define_expand "ctrsi"
13859 [(parallel [(set (pc)
13860 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
13861 (const_int 1))
13862 (label_ref (match_operand 1 "" ""))
13863 (pc)))
13864 (set (match_dup 0)
13865 (plus:SI (match_dup 0)
13866 (const_int -1)))
13867 (clobber (match_scratch:CC 2 ""))
13868 (clobber (match_scratch:SI 3 ""))])]
13869 "TARGET_32BIT"
13870 "")
13872 (define_expand "ctrdi"
13873 [(parallel [(set (pc)
13874 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
13875 (const_int 1))
13876 (label_ref (match_operand 1 "" ""))
13877 (pc)))
13878 (set (match_dup 0)
13879 (plus:DI (match_dup 0)
13880 (const_int -1)))
13881 (clobber (match_scratch:CC 2 ""))
13882 (clobber (match_scratch:DI 3 ""))])]
13883 "TARGET_64BIT"
13884 "")
13886 ;; We need to be able to do this for any operand, including MEM, or we
13887 ;; will cause reload to blow up since we don't allow output reloads on
13888 ;; JUMP_INSNs.
13889 ;; For the length attribute to be calculated correctly, the
13890 ;; label MUST be operand 0.
13892 (define_insn "*ctrsi_internal1"
13893 [(set (pc)
13894 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
13895 (const_int 1))
13896 (label_ref (match_operand 0 "" ""))
13897 (pc)))
13898 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
13899 (plus:SI (match_dup 1)
13900 (const_int -1)))
13901 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13902 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
13903 "TARGET_32BIT"
13904 "*
13905 {
13906 if (which_alternative != 0)
13907 return \"#\";
13908 else if (get_attr_length (insn) == 4)
13909 return \"{bdn|bdnz} %l0\";
13910 else
13911 return \"bdz $+8\;b %l0\";
13912 }"
13913 [(set_attr "type" "branch")
13914 (set_attr "length" "*,12,16,16")])
13916 (define_insn "*ctrsi_internal2"
13917 [(set (pc)
13918 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
13919 (const_int 1))
13920 (pc)
13921 (label_ref (match_operand 0 "" ""))))
13922 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
13923 (plus:SI (match_dup 1)
13924 (const_int -1)))
13925 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13926 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
13927 "TARGET_32BIT"
13928 "*
13929 {
13930 if (which_alternative != 0)
13931 return \"#\";
13932 else if (get_attr_length (insn) == 4)
13933 return \"bdz %l0\";
13934 else
13935 return \"{bdn|bdnz} $+8\;b %l0\";
13936 }"
13937 [(set_attr "type" "branch")
13938 (set_attr "length" "*,12,16,16")])
13940 (define_insn "*ctrdi_internal1"
13941 [(set (pc)
13942 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
13943 (const_int 1))
13944 (label_ref (match_operand 0 "" ""))
13945 (pc)))
13946 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
13947 (plus:DI (match_dup 1)
13948 (const_int -1)))
13949 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13950 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
13951 "TARGET_64BIT"
13952 "*
13953 {
13954 if (which_alternative != 0)
13955 return \"#\";
13956 else if (get_attr_length (insn) == 4)
13957 return \"{bdn|bdnz} %l0\";
13958 else
13959 return \"bdz $+8\;b %l0\";
13960 }"
13961 [(set_attr "type" "branch")
13962 (set_attr "length" "*,12,16,16")])
13964 (define_insn "*ctrdi_internal2"
13965 [(set (pc)
13966 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
13967 (const_int 1))
13968 (pc)
13969 (label_ref (match_operand 0 "" ""))))
13970 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
13971 (plus:DI (match_dup 1)
13972 (const_int -1)))
13973 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13974 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
13975 "TARGET_64BIT"
13976 "*
13977 {
13978 if (which_alternative != 0)
13979 return \"#\";
13980 else if (get_attr_length (insn) == 4)
13981 return \"bdz %l0\";
13982 else
13983 return \"{bdn|bdnz} $+8\;b %l0\";
13984 }"
13985 [(set_attr "type" "branch")
13986 (set_attr "length" "*,12,16,16")])
13988 ;; Similar, but we can use GE since we have a REG_NONNEG.
13990 (define_insn "*ctrsi_internal3"
13991 [(set (pc)
13992 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
13993 (const_int 0))
13994 (label_ref (match_operand 0 "" ""))
13995 (pc)))
13996 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
13997 (plus:SI (match_dup 1)
13998 (const_int -1)))
13999 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14000 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14001 "TARGET_32BIT && find_reg_note (insn, REG_NONNEG, 0)"
14002 "*
14003 {
14004 if (which_alternative != 0)
14005 return \"#\";
14006 else if (get_attr_length (insn) == 4)
14007 return \"{bdn|bdnz} %l0\";
14008 else
14009 return \"bdz $+8\;b %l0\";
14010 }"
14011 [(set_attr "type" "branch")
14012 (set_attr "length" "*,12,16,16")])
14014 (define_insn "*ctrsi_internal4"
14015 [(set (pc)
14016 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14017 (const_int 0))
14018 (pc)
14019 (label_ref (match_operand 0 "" ""))))
14020 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
14021 (plus:SI (match_dup 1)
14022 (const_int -1)))
14023 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14024 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14025 "TARGET_32BIT && find_reg_note (insn, REG_NONNEG, 0)"
14026 "*
14027 {
14028 if (which_alternative != 0)
14029 return \"#\";
14030 else if (get_attr_length (insn) == 4)
14031 return \"bdz %l0\";
14032 else
14033 return \"{bdn|bdnz} $+8\;b %l0\";
14034 }"
14035 [(set_attr "type" "branch")
14036 (set_attr "length" "*,12,16,16")])
14038 (define_insn "*ctrdi_internal3"
14039 [(set (pc)
14040 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14041 (const_int 0))
14042 (label_ref (match_operand 0 "" ""))
14043 (pc)))
14044 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14045 (plus:DI (match_dup 1)
14046 (const_int -1)))
14047 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14048 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14049 "TARGET_64BIT && find_reg_note (insn, REG_NONNEG, 0)"
14050 "*
14051 {
14052 if (which_alternative != 0)
14053 return \"#\";
14054 else if (get_attr_length (insn) == 4)
14055 return \"{bdn|bdnz} %l0\";
14056 else
14057 return \"bdz $+8\;b %l0\";
14058 }"
14059 [(set_attr "type" "branch")
14060 (set_attr "length" "*,12,16,16")])
14062 (define_insn "*ctrdi_internal4"
14063 [(set (pc)
14064 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14065 (const_int 0))
14066 (pc)
14067 (label_ref (match_operand 0 "" ""))))
14068 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14069 (plus:DI (match_dup 1)
14070 (const_int -1)))
14071 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14072 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14073 "TARGET_64BIT && find_reg_note (insn, REG_NONNEG, 0)"
14074 "*
14075 {
14076 if (which_alternative != 0)
14077 return \"#\";
14078 else if (get_attr_length (insn) == 4)
14079 return \"bdz %l0\";
14080 else
14081 return \"{bdn|bdnz} $+8\;b %l0\";
14082 }"
14083 [(set_attr "type" "branch")
14084 (set_attr "length" "*,12,16,16")])
14086 ;; Similar but use EQ
14088 (define_insn "*ctrsi_internal5"
14089 [(set (pc)
14090 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14091 (const_int 1))
14092 (label_ref (match_operand 0 "" ""))
14093 (pc)))
14094 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
14095 (plus:SI (match_dup 1)
14096 (const_int -1)))
14097 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14098 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14099 "TARGET_32BIT"
14100 "*
14101 {
14102 if (which_alternative != 0)
14103 return \"#\";
14104 else if (get_attr_length (insn) == 4)
14105 return \"bdz %l0\";
14106 else
14107 return \"{bdn|bdnz} $+8\;b %l0\";
14108 }"
14109 [(set_attr "type" "branch")
14110 (set_attr "length" "*,12,16,16")])
14112 (define_insn "*ctrsi_internal6"
14113 [(set (pc)
14114 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14115 (const_int 1))
14116 (pc)
14117 (label_ref (match_operand 0 "" ""))))
14118 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
14119 (plus:SI (match_dup 1)
14120 (const_int -1)))
14121 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14122 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14123 "TARGET_32BIT"
14124 "*
14125 {
14126 if (which_alternative != 0)
14127 return \"#\";
14128 else if (get_attr_length (insn) == 4)
14129 return \"{bdn|bdnz} %l0\";
14130 else
14131 return \"bdz $+8\;b %l0\";
14132 }"
14133 [(set_attr "type" "branch")
14134 (set_attr "length" "*,12,16,16")])
14136 (define_insn "*ctrdi_internal5"
14137 [(set (pc)
14138 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14139 (const_int 1))
14140 (label_ref (match_operand 0 "" ""))
14141 (pc)))
14142 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14143 (plus:DI (match_dup 1)
14144 (const_int -1)))
14145 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14146 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14147 "TARGET_64BIT"
14148 "*
14149 {
14150 if (which_alternative != 0)
14151 return \"#\";
14152 else if (get_attr_length (insn) == 4)
14153 return \"bdz %l0\";
14154 else
14155 return \"{bdn|bdnz} $+8\;b %l0\";
14156 }"
14157 [(set_attr "type" "branch")
14158 (set_attr "length" "*,12,16,16")])
14160 (define_insn "*ctrdi_internal6"
14161 [(set (pc)
14162 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14163 (const_int 1))
14164 (pc)
14165 (label_ref (match_operand 0 "" ""))))
14166 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14167 (plus:DI (match_dup 1)
14168 (const_int -1)))
14169 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14170 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14171 "TARGET_64BIT"
14172 "*
14173 {
14174 if (which_alternative != 0)
14175 return \"#\";
14176 else if (get_attr_length (insn) == 4)
14177 return \"{bdn|bdnz} %l0\";
14178 else
14179 return \"bdz $+8\;b %l0\";
14180 }"
14181 [(set_attr "type" "branch")
14182 (set_attr "length" "*,12,16,16")])
14184 ;; Now the splitters if we could not allocate the CTR register
14186 (define_split
14187 [(set (pc)
14188 (if_then_else (match_operator 2 "comparison_operator"
14189 [(match_operand:SI 1 "gpc_reg_operand" "")
14190 (const_int 1)])
14191 (match_operand 5 "" "")
14192 (match_operand 6 "" "")))
14193 (set (match_operand:SI 0 "gpc_reg_operand" "")
14194 (plus:SI (match_dup 1)
14195 (const_int -1)))
14196 (clobber (match_scratch:CC 3 ""))
14197 (clobber (match_scratch:SI 4 ""))]
14198 "TARGET_32BIT && reload_completed"
14199 [(parallel [(set (match_dup 3)
14200 (compare:CC (plus:SI (match_dup 1)
14201 (const_int -1))
14202 (const_int 0)))
14203 (set (match_dup 0)
14204 (plus:SI (match_dup 1)
14205 (const_int -1)))])
14206 (set (pc) (if_then_else (match_dup 7)
14207 (match_dup 5)
14208 (match_dup 6)))]
14209 "
14210 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14211 operands[3], const0_rtx); }")
14213 (define_split
14214 [(set (pc)
14215 (if_then_else (match_operator 2 "comparison_operator"
14216 [(match_operand:SI 1 "gpc_reg_operand" "")
14217 (const_int 1)])
14218 (match_operand 5 "" "")
14219 (match_operand 6 "" "")))
14220 (set (match_operand:SI 0 "nonimmediate_operand" "")
14221 (plus:SI (match_dup 1) (const_int -1)))
14222 (clobber (match_scratch:CC 3 ""))
14223 (clobber (match_scratch:SI 4 ""))]
14224 "TARGET_32BIT && reload_completed
14225 && ! gpc_reg_operand (operands[0], SImode)"
14226 [(parallel [(set (match_dup 3)
14227 (compare:CC (plus:SI (match_dup 1)
14228 (const_int -1))
14229 (const_int 0)))
14230 (set (match_dup 4)
14231 (plus:SI (match_dup 1)
14232 (const_int -1)))])
14233 (set (match_dup 0)
14234 (match_dup 4))
14235 (set (pc) (if_then_else (match_dup 7)
14236 (match_dup 5)
14237 (match_dup 6)))]
14238 "
14239 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14240 operands[3], const0_rtx); }")
14241 (define_split
14242 [(set (pc)
14243 (if_then_else (match_operator 2 "comparison_operator"
14244 [(match_operand:DI 1 "gpc_reg_operand" "")
14245 (const_int 1)])
14246 (match_operand 5 "" "")
14247 (match_operand 6 "" "")))
14248 (set (match_operand:DI 0 "gpc_reg_operand" "")
14249 (plus:DI (match_dup 1)
14250 (const_int -1)))
14251 (clobber (match_scratch:CC 3 ""))
14252 (clobber (match_scratch:DI 4 ""))]
14253 "TARGET_64BIT && reload_completed"
14254 [(parallel [(set (match_dup 3)
14255 (compare:CC (plus:DI (match_dup 1)
14256 (const_int -1))
14257 (const_int 0)))
14258 (set (match_dup 0)
14259 (plus:DI (match_dup 1)
14260 (const_int -1)))])
14261 (set (pc) (if_then_else (match_dup 7)
14262 (match_dup 5)
14263 (match_dup 6)))]
14264 "
14265 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14266 operands[3], const0_rtx); }")
14268 (define_split
14269 [(set (pc)
14270 (if_then_else (match_operator 2 "comparison_operator"
14271 [(match_operand:DI 1 "gpc_reg_operand" "")
14272 (const_int 1)])
14273 (match_operand 5 "" "")
14274 (match_operand 6 "" "")))
14275 (set (match_operand:DI 0 "nonimmediate_operand" "")
14276 (plus:DI (match_dup 1) (const_int -1)))
14277 (clobber (match_scratch:CC 3 ""))
14278 (clobber (match_scratch:DI 4 ""))]
14279 "TARGET_64BIT && reload_completed
14280 && ! gpc_reg_operand (operands[0], DImode)"
14281 [(parallel [(set (match_dup 3)
14282 (compare:CC (plus:DI (match_dup 1)
14283 (const_int -1))
14284 (const_int 0)))
14285 (set (match_dup 4)
14286 (plus:DI (match_dup 1)
14287 (const_int -1)))])
14288 (set (match_dup 0)
14289 (match_dup 4))
14290 (set (pc) (if_then_else (match_dup 7)
14291 (match_dup 5)
14292 (match_dup 6)))]
14293 "
14294 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14295 operands[3], const0_rtx); }")
14296 \f
14297 (define_insn "trap"
14298 [(trap_if (const_int 1) (const_int 0))]
14299 ""
14300 "{t 31,0,0|trap}")
14302 (define_expand "conditional_trap"
14303 [(trap_if (match_operator 0 "trap_comparison_operator"
14304 [(match_dup 2) (match_dup 3)])
14305 (match_operand 1 "const_int_operand" ""))]
14306 ""
14307 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14308 operands[2] = rs6000_compare_op0;
14309 operands[3] = rs6000_compare_op1;")
14311 (define_insn ""
14312 [(trap_if (match_operator 0 "trap_comparison_operator"
14313 [(match_operand:SI 1 "register_operand" "r")
14314 (match_operand:SI 2 "reg_or_short_operand" "rI")])
14315 (const_int 0))]
14316 ""
14317 "{t|tw}%V0%I2 %1,%2")
14319 (define_insn ""
14320 [(trap_if (match_operator 0 "trap_comparison_operator"
14321 [(match_operand:DI 1 "register_operand" "r")
14322 (match_operand:DI 2 "reg_or_short_operand" "rI")])
14323 (const_int 0))]
14324 "TARGET_POWERPC64"
14325 "td%V0%I2 %1,%2")
14326 \f
14327 ;; Insns related to generating the function prologue and epilogue.
14329 (define_expand "prologue"
14330 [(use (const_int 0))]
14331 "TARGET_SCHED_PROLOG"
14332 "
14333 {
14334 rs6000_emit_prologue ();
14335 DONE;
14336 }")
14338 (define_insn "*movesi_from_cr_one"
14339 [(match_parallel 0 "mfcr_operation"
14340 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14341 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14342 (match_operand 3 "immediate_operand" "n")]
14343 UNSPEC_MOVESI_FROM_CR))])]
14344 "TARGET_MFCRF"
14345 "*
14346 {
14347 int mask = 0;
14348 int i;
14349 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14350 {
14351 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14352 operands[4] = GEN_INT (mask);
14353 output_asm_insn (\"mfcr %1,%4\", operands);
14354 }
14355 return \"\";
14356 }"
14357 [(set_attr "type" "mfcrf")])
14359 (define_insn "movesi_from_cr"
14360 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14361 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14362 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14363 UNSPEC_MOVESI_FROM_CR))]
14364 ""
14365 "mfcr %0"
14366 [(set_attr "type" "mfcr")])
14368 (define_insn "*stmw"
14369 [(match_parallel 0 "stmw_operation"
14370 [(set (match_operand:SI 1 "memory_operand" "=m")
14371 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14372 "TARGET_MULTIPLE"
14373 "{stm|stmw} %2,%1")
14375 (define_insn "*save_fpregs_si"
14376 [(match_parallel 0 "any_operand"
14377 [(clobber (match_operand:SI 1 "register_operand" "=l"))
14378 (use (match_operand:SI 2 "call_operand" "s"))
14379 (set (match_operand:DF 3 "memory_operand" "=m")
14380 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14381 "TARGET_32BIT"
14382 "bl %z2"
14383 [(set_attr "type" "branch")
14384 (set_attr "length" "4")])
14386 (define_insn "*save_fpregs_di"
14387 [(match_parallel 0 "any_operand"
14388 [(clobber (match_operand:DI 1 "register_operand" "=l"))
14389 (use (match_operand:DI 2 "call_operand" "s"))
14390 (set (match_operand:DF 3 "memory_operand" "=m")
14391 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14392 "TARGET_64BIT"
14393 "bl %z2"
14394 [(set_attr "type" "branch")
14395 (set_attr "length" "4")])
14397 ; These are to explain that changes to the stack pointer should
14398 ; not be moved over stores to stack memory.
14399 (define_insn "stack_tie"
14400 [(set (match_operand:BLK 0 "memory_operand" "+m")
14401 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14402 ""
14403 ""
14404 [(set_attr "length" "0")])
14407 (define_expand "epilogue"
14408 [(use (const_int 0))]
14409 "TARGET_SCHED_PROLOG"
14410 "
14411 {
14412 rs6000_emit_epilogue (FALSE);
14413 DONE;
14414 }")
14416 ; On some processors, doing the mtcrf one CC register at a time is
14417 ; faster (like on the 604e). On others, doing them all at once is
14418 ; faster; for instance, on the 601 and 750.
14420 (define_expand "movsi_to_cr_one"
14421 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14422 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14423 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14424 ""
14425 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14427 (define_insn "*movsi_to_cr"
14428 [(match_parallel 0 "mtcrf_operation"
14429 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14430 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14431 (match_operand 3 "immediate_operand" "n")]
14432 UNSPEC_MOVESI_TO_CR))])]
14433 ""
14434 "*
14435 {
14436 int mask = 0;
14437 int i;
14438 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14439 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14440 operands[4] = GEN_INT (mask);
14441 return \"mtcrf %4,%2\";
14442 }"
14443 [(set_attr "type" "mtcr")])
14445 (define_insn "*mtcrfsi"
14446 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14447 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14448 (match_operand 2 "immediate_operand" "n")]
14449 UNSPEC_MOVESI_TO_CR))]
14450 "GET_CODE (operands[0]) == REG
14451 && CR_REGNO_P (REGNO (operands[0]))
14452 && GET_CODE (operands[2]) == CONST_INT
14453 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14454 "mtcrf %R0,%1"
14455 [(set_attr "type" "mtcr")])
14457 ; The load-multiple instructions have similar properties.
14458 ; Note that "load_multiple" is a name known to the machine-independent
14459 ; code that actually corresponds to the powerpc load-string.
14461 (define_insn "*lmw"
14462 [(match_parallel 0 "lmw_operation"
14463 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14464 (match_operand:SI 2 "memory_operand" "m"))])]
14465 "TARGET_MULTIPLE"
14466 "{lm|lmw} %1,%2")
14468 (define_insn "*return_internal_si"
14469 [(return)
14470 (use (match_operand:SI 0 "register_operand" "lc"))]
14471 "TARGET_32BIT"
14472 "b%T0"
14473 [(set_attr "type" "jmpreg")])
14475 (define_insn "*return_internal_di"
14476 [(return)
14477 (use (match_operand:DI 0 "register_operand" "lc"))]
14478 "TARGET_64BIT"
14479 "b%T0"
14480 [(set_attr "type" "jmpreg")])
14482 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14483 ; stuff was in GCC. Oh, and "any_operand" is a bit flexible...
14485 (define_insn "*return_and_restore_fpregs_si"
14486 [(match_parallel 0 "any_operand"
14487 [(return)
14488 (use (match_operand:SI 1 "register_operand" "l"))
14489 (use (match_operand:SI 2 "call_operand" "s"))
14490 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14491 (match_operand:DF 4 "memory_operand" "m"))])]
14492 "TARGET_32BIT"
14493 "b %z2")
14495 (define_insn "*return_and_restore_fpregs_di"
14496 [(match_parallel 0 "any_operand"
14497 [(return)
14498 (use (match_operand:DI 1 "register_operand" "l"))
14499 (use (match_operand:DI 2 "call_operand" "s"))
14500 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14501 (match_operand:DF 4 "memory_operand" "m"))])]
14502 "TARGET_64BIT"
14503 "b %z2")
14505 ; This is used in compiling the unwind routines.
14506 (define_expand "eh_return"
14507 [(use (match_operand 0 "general_operand" ""))]
14508 ""
14509 "
14510 {
14511 if (TARGET_32BIT)
14512 emit_insn (gen_eh_set_lr_si (operands[0]));
14513 else
14514 emit_insn (gen_eh_set_lr_di (operands[0]));
14515 DONE;
14516 }")
14518 ; We can't expand this before we know where the link register is stored.
14519 (define_insn "eh_set_lr_si"
14520 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
14521 UNSPECV_EH_RR)
14522 (clobber (match_scratch:SI 1 "=&b"))]
14523 "TARGET_32BIT"
14524 "#")
14526 (define_insn "eh_set_lr_di"
14527 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
14528 UNSPECV_EH_RR)
14529 (clobber (match_scratch:DI 1 "=&b"))]
14530 "TARGET_64BIT"
14531 "#")
14533 (define_split
14534 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14535 (clobber (match_scratch 1 ""))]
14536 "reload_completed"
14537 [(const_int 0)]
14538 "
14539 {
14540 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14541 DONE;
14542 }")
14544 (define_insn "prefetch"
14545 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
14546 (match_operand:SI 1 "const_int_operand" "n")
14547 (match_operand:SI 2 "const_int_operand" "n"))]
14548 "TARGET_POWERPC"
14549 "*
14550 {
14551 if (GET_CODE (operands[0]) == REG)
14552 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14553 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14554 }"
14555 [(set_attr "type" "load")])
14557 (include "altivec.md")
14558 (include "spe.md")