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2002-06-10 Eric Christopher <echristo@redhat.com>
[official-gcc.git] / gcc / config / i386 / i386.h
blob12e9bc24f287c8dd290de8afc7043fe4317235f5
1 /* Definitions of target machine for GNU compiler for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
4
5 This file is part of GNU CC.
6
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
24
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
27
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
30
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
36
37 /* Define the specific costs for a given cpu */
38
39 struct processor_costs {
40 const int add; /* cost of an add instruction */
41 const int lea; /* cost of a lea instruction */
42 const int shift_var; /* variable shift costs */
43 const int shift_const; /* constant shift costs */
44 const int mult_init; /* cost of starting a multiply */
45 const int mult_bit; /* cost of multiply per each bit set */
46 const int divide; /* cost of a divide/mod */
47 int movsx; /* The cost of movsx operation. */
48 int movzx; /* The cost of movzx operation. */
49 const int large_insn; /* insns larger than this cost more */
50 const int move_ratio; /* The threshold of number of scalar
51 memory-to-memory move insns. */
52 const int movzbl_load; /* cost of loading using movzbl */
53 const int int_load[3]; /* cost of loading integer registers
54 in QImode, HImode and SImode relative
55 to reg-reg move (2). */
56 const int int_store[3]; /* cost of storing integer register
57 in QImode, HImode and SImode */
58 const int fp_move; /* cost of reg,reg fld/fst */
59 const int fp_load[3]; /* cost of loading FP register
60 in SFmode, DFmode and XFmode */
61 const int fp_store[3]; /* cost of storing FP register
62 in SFmode, DFmode and XFmode */
63 const int mmx_move; /* cost of moving MMX register. */
64 const int mmx_load[2]; /* cost of loading MMX register
65 in SImode and DImode */
66 const int mmx_store[2]; /* cost of storing MMX register
67 in SImode and DImode */
68 const int sse_move; /* cost of moving SSE register. */
69 const int sse_load[3]; /* cost of loading SSE register
70 in SImode, DImode and TImode*/
71 const int sse_store[3]; /* cost of storing SSE register
72 in SImode, DImode and TImode*/
73 const int mmxsse_to_integer; /* cost of moving mmxsse register to
74 integer and vice versa. */
75 const int prefetch_block; /* bytes moved to cache for prefetch. */
76 const int simultaneous_prefetches; /* number of parallel prefetch
77 operations. */
78 };
79
80 extern const struct processor_costs *ix86_cost;
81
82 /* Run-time compilation parameters selecting different hardware subsets. */
83
84 extern int target_flags;
85
86 /* Macros used in the machine description to test the flags. */
87
88 /* configure can arrange to make this 2, to force a 486. */
89
90 #ifndef TARGET_CPU_DEFAULT
91 #define TARGET_CPU_DEFAULT 0
92 #endif
93
94 /* Masks for the -m switches */
95 #define MASK_80387 0x00000001 /* Hardware floating point */
96 #define MASK_RTD 0x00000002 /* Use ret that pops args */
97 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
98 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
99 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
100 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
101 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
102 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
103 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
104 #define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */
105 #define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */
106 #define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */
107 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */
108 #define MASK_ACCUMULATE_OUTGOING_ARGS_SET 0x00002000
109 #define MASK_MMX 0x00004000 /* Support MMX regs/builtins */
110 #define MASK_MMX_SET 0x00008000
111 #define MASK_SSE 0x00010000 /* Support SSE regs/builtins */
112 #define MASK_SSE_SET 0x00020000
113 #define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */
114 #define MASK_SSE2_SET 0x00080000
115 #define MASK_3DNOW 0x00100000 /* Support 3Dnow builtins */
116 #define MASK_3DNOW_SET 0x00200000
117 #define MASK_3DNOW_A 0x00400000 /* Support Athlon 3Dnow builtins */
118 #define MASK_3DNOW_A_SET 0x00800000
119 #define MASK_128BIT_LONG_DOUBLE 0x01000000 /* long double size is 128bit */
120 #define MASK_64BIT 0x02000000 /* Produce 64bit code */
121 /* ... overlap with subtarget options starts by 0x04000000. */
122 #define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */
123
124 /* Use the floating point instructions */
125 #define TARGET_80387 (target_flags & MASK_80387)
126
127 /* Compile using ret insn that pops args.
128 This will not work unless you use prototypes at least
129 for all functions that can take varying numbers of args. */
130 #define TARGET_RTD (target_flags & MASK_RTD)
131
132 /* Align doubles to a two word boundary. This breaks compatibility with
133 the published ABI's for structures containing doubles, but produces
134 faster code on the pentium. */
135 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
136
137 /* Use push instructions to save outgoing args. */
138 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
139
140 /* Accumulate stack adjustments to prologue/epilogue. */
141 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
142 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
143
144 /* Put uninitialized locals into bss, not data.
145 Meaningful only on svr3. */
146 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
147
148 /* Use IEEE floating point comparisons. These handle correctly the cases
149 where the result of a comparison is unordered. Normally SIGFPE is
150 generated in such cases, in which case this isn't needed. */
151 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
152
153 /* Functions that return a floating point value may return that value
154 in the 387 FPU or in 386 integer registers. If set, this flag causes
155 the 387 to be used, which is compatible with most calling conventions. */
156 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
157
158 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
159 This mode wastes cache, but avoid misaligned data accesses and simplifies
160 address calculations. */
161 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
162
163 /* Disable generation of FP sin, cos and sqrt operations for 387.
164 This is because FreeBSD lacks these in the math-emulator-code */
165 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
166
167 /* Don't create frame pointers for leaf functions */
168 #define TARGET_OMIT_LEAF_FRAME_POINTER \
169 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
170
171 /* Debug GO_IF_LEGITIMATE_ADDRESS */
172 #define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0)
173
174 /* Debug FUNCTION_ARG macros */
175 #define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0)
176
177 /* 64bit Sledgehammer mode */
178 #ifdef TARGET_BI_ARCH
179 #define TARGET_64BIT (target_flags & MASK_64BIT)
180 #else
181 #if TARGET_64BIT_DEFAULT
182 #define TARGET_64BIT 1
183 #else
184 #define TARGET_64BIT 0
185 #endif
186 #endif
187
188 #define TARGET_386 (ix86_cpu == PROCESSOR_I386)
189 #define TARGET_486 (ix86_cpu == PROCESSOR_I486)
190 #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
191 #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
192 #define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
193 #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
194 #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4)
195
196 #define CPUMASK (1 << ix86_cpu)
197 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
198 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
199 extern const int x86_branch_hints, x86_unroll_strlen;
200 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
201 extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
202 extern const int x86_use_cltd, x86_read_modify_write;
203 extern const int x86_read_modify, x86_split_long_moves;
204 extern const int x86_promote_QImode, x86_single_stringop;
205 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
206 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
207 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
208 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
209 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
210 extern const int x86_epilogue_using_move, x86_decompose_lea;
211 extern const int x86_arch_always_fancy_math_387;
212 extern int x86_prefetch_sse;
213
214 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
215 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
216 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
217 #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
218 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
219 /* For sane SSE instruction set generation we need fcomi instruction. It is
220 safe to enable all CMOVE instructions. */
221 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
222 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
223 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK)
224 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
225 #define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT)
226 #define TARGET_MOVX (x86_movx & CPUMASK)
227 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK)
228 #define TARGET_USE_LOOP (x86_use_loop & CPUMASK)
229 #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK)
230 #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK)
231 #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK)
232 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
233 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
234 #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
235 #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
236 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
237 #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
238 #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
239 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
240 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
241 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK)
242 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK)
243 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK)
244 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK)
245 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK)
246 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK)
247 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK)
248 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK)
249 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK)
250 #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK)
251 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
252
253 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
254
255 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
256 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
257
258 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
259
260 #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
261 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
262 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
263 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
264 && (ix86_fpmath & FPMATH_387))
265 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
266 #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
267 #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
268
269 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
270
271 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
272 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
273
274 /* WARNING: Do not mark empty strings for translation, as calling
275 gettext on an empty string does NOT return an empty
276 string. */
277
278
279 #define TARGET_SWITCHES \
280 { { "80387", MASK_80387, N_("Use hardware fp") }, \
281 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
282 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
283 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
284 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
285 { "386", 0, "" /*Deprecated.*/}, \
286 { "486", 0, "" /*Deprecated.*/}, \
287 { "pentium", 0, "" /*Deprecated.*/}, \
288 { "pentiumpro", 0, "" /*Deprecated.*/}, \
289 { "intel-syntax", 0, "" /*Deprecated.*/}, \
290 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \
291 { "rtd", MASK_RTD, \
292 N_("Alternate calling convention") }, \
293 { "no-rtd", -MASK_RTD, \
294 N_("Use normal calling convention") }, \
295 { "align-double", MASK_ALIGN_DOUBLE, \
296 N_("Align some doubles on dword boundary") }, \
297 { "no-align-double", -MASK_ALIGN_DOUBLE, \
298 N_("Align doubles on word boundary") }, \
299 { "svr3-shlib", MASK_SVR3_SHLIB, \
300 N_("Uninitialized locals in .bss") }, \
301 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
302 N_("Uninitialized locals in .data") }, \
303 { "ieee-fp", MASK_IEEE_FP, \
304 N_("Use IEEE math for fp comparisons") }, \
305 { "no-ieee-fp", -MASK_IEEE_FP, \
306 N_("Do not use IEEE math for fp comparisons") }, \
307 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
308 N_("Return values of functions in FPU registers") }, \
309 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
310 N_("Do not return values of functions in FPU registers")}, \
311 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
312 N_("Do not generate sin, cos, sqrt for FPU") }, \
313 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
314 N_("Generate sin, cos, sqrt for FPU")}, \
315 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
316 N_("Omit the frame pointer in leaf functions") }, \
317 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
318 { "stack-arg-probe", MASK_STACK_PROBE, \
319 N_("Enable stack probing") }, \
320 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
321 { "windows", 0, 0 /* undocumented */ }, \
322 { "dll", 0, 0 /* undocumented */ }, \
323 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
324 N_("Align destination of the string operations") }, \
325 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
326 N_("Do not align destination of the string operations") }, \
327 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
328 N_("Inline all known string operations") }, \
329 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
330 N_("Do not inline all known string operations") }, \
331 { "push-args", -MASK_NO_PUSH_ARGS, \
332 N_("Use push instructions to save outgoing arguments") }, \
333 { "no-push-args", MASK_NO_PUSH_ARGS, \
334 N_("Do not use push instructions to save outgoing arguments") }, \
335 { "accumulate-outgoing-args", (MASK_ACCUMULATE_OUTGOING_ARGS \
336 | MASK_ACCUMULATE_OUTGOING_ARGS_SET), \
337 N_("Use push instructions to save outgoing arguments") }, \
338 { "no-accumulate-outgoing-args",MASK_ACCUMULATE_OUTGOING_ARGS_SET, \
339 N_("Do not use push instructions to save outgoing arguments") }, \
340 { "mmx", MASK_MMX | MASK_MMX_SET, \
341 N_("Support MMX built-in functions") }, \
342 { "no-mmx", -MASK_MMX, \
343 N_("Do not support MMX built-in functions") }, \
344 { "no-mmx", MASK_MMX_SET, "" }, \
345 { "3dnow", MASK_3DNOW | MASK_3DNOW_SET, \
346 N_("Support 3DNow! built-in functions") }, \
347 { "no-3dnow", -MASK_3DNOW, "" }, \
348 { "no-3dnow", MASK_3DNOW_SET, \
349 N_("Do not support 3DNow! built-in functions") }, \
350 { "sse", MASK_SSE | MASK_SSE_SET, \
351 N_("Support MMX and SSE built-in functions and code generation") }, \
352 { "no-sse", -MASK_SSE, "" }, \
353 { "no-sse", MASK_SSE_SET, \
354 N_("Do not support MMX and SSE built-in functions and code generation") },\
355 { "sse2", MASK_SSE2 | MASK_SSE2_SET, \
356 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
357 { "no-sse2", -MASK_SSE2, "" }, \
358 { "no-sse2", MASK_SSE2_SET, \
359 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
360 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
361 N_("sizeof(long double) is 16") }, \
362 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
363 N_("sizeof(long double) is 12") }, \
364 { "64", MASK_64BIT, \
365 N_("Generate 64bit x86-64 code") }, \
366 { "32", -MASK_64BIT, \
367 N_("Generate 32bit i386 code") }, \
368 { "red-zone", -MASK_NO_RED_ZONE, \
369 N_("Use red-zone in the x86-64 code") }, \
370 { "no-red-zone", MASK_NO_RED_ZONE, \
371 N_("Do not use red-zone in the x86-64 code") }, \
372 SUBTARGET_SWITCHES \
373 { "", TARGET_DEFAULT | TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_DEFAULT, 0 }}
374
375 #ifndef TARGET_64BIT_DEFAULT
376 #define TARGET_64BIT_DEFAULT 0
377 #endif
378
379 #define TARGET_DEFAULT MASK_OMIT_LEAF_FRAME_POINTER
380
381
382 /* This macro is similar to `TARGET_SWITCHES' but defines names of
383 command options that have values. Its definition is an
384 initializer with a subgrouping for each command option.
385
386 Each subgrouping contains a string constant, that defines the
387 fixed part of the option name, and the address of a variable. The
388 variable, type `char *', is set to the variable part of the given
389 option if the fixed part matches. The actual option name is made
390 by appending `-m' to the specified name. */
391 #define TARGET_OPTIONS \
392 { { "cpu=", &ix86_cpu_string, \
393 N_("Schedule code for given CPU")}, \
394 { "fpmath=", &ix86_fpmath_string, \
395 N_("Generate floating point mathematics using given instruction set")},\
396 { "arch=", &ix86_arch_string, \
397 N_("Generate code for given CPU")}, \
398 { "regparm=", &ix86_regparm_string, \
399 N_("Number of registers used to pass integer arguments") }, \
400 { "align-loops=", &ix86_align_loops_string, \
401 N_("Loop code aligned to this power of 2") }, \
402 { "align-jumps=", &ix86_align_jumps_string, \
403 N_("Jump targets are aligned to this power of 2") }, \
404 { "align-functions=", &ix86_align_funcs_string, \
405 N_("Function starts are aligned to this power of 2") }, \
406 { "preferred-stack-boundary=", \
407 &ix86_preferred_stack_boundary_string, \
408 N_("Attempt to keep stack aligned to this power of 2") }, \
409 { "branch-cost=", &ix86_branch_cost_string, \
410 N_("Branches are this expensive (1-5, arbitrary units)") }, \
411 { "cmodel=", &ix86_cmodel_string, \
412 N_("Use given x86-64 code model") }, \
413 { "debug-arg", &ix86_debug_arg_string, \
414 "" /* Undocumented. */ }, \
415 { "debug-addr", &ix86_debug_addr_string, \
416 "" /* Undocumented. */ }, \
417 { "asm=", &ix86_asm_string, \
418 N_("Use given assembler dialect") }, \
419 { "tls-dialect=", &ix86_tls_dialect_string, \
420 N_("Use given thread-local storage dialect") }, \
421 SUBTARGET_OPTIONS \
422 }
423
424 /* Sometimes certain combinations of command options do not make
425 sense on a particular target machine. You can define a macro
426 `OVERRIDE_OPTIONS' to take account of this. This macro, if
427 defined, is executed once just after all the command options have
428 been parsed.
429
430 Don't use this macro to turn on various extra optimizations for
431 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
432
433 #define OVERRIDE_OPTIONS override_options ()
434
435 /* These are meant to be redefined in the host dependent files */
436 #define SUBTARGET_SWITCHES
437 #define SUBTARGET_OPTIONS
438
439 /* Define this to change the optimizations performed by default. */
440 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
441 optimization_options ((LEVEL), (SIZE))
442
443 /* Specs for the compiler proper */
444
445 #ifndef CC1_CPU_SPEC
446 #define CC1_CPU_SPEC "\
447 %{!mcpu*: \
448 %{m386:-mcpu=i386 \
449 %n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \
450 %{m486:-mcpu=i486 \
451 %n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \
452 %{mpentium:-mcpu=pentium \
453 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \
454 %{mpentiumpro:-mcpu=pentiumpro \
455 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \
456 %{mintel-syntax:-masm=intel \
457 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
458 %{mno-intel-syntax:-masm=att \
459 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
460 #endif
461 \f
462 /* Target CPU builtins. */
463 #define TARGET_CPU_CPP_BUILTINS() \
464 do \
465 { \
466 size_t arch_len = strlen (ix86_arch_string); \
467 size_t cpu_len = strlen (ix86_cpu_string); \
468 int last_arch_char = ix86_arch_string[arch_len - 1]; \
469 int last_cpu_char = ix86_cpu_string[cpu_len - 1]; \
470 \
471 if (TARGET_64BIT) \
472 { \
473 builtin_assert ("cpu=x86_64"); \
474 builtin_assert ("machine=x86_64"); \
475 builtin_define ("__x86_64"); \
476 builtin_define ("__x86_64__"); \
477 } \
478 else \
479 { \
480 builtin_assert ("cpu=i386"); \
481 builtin_assert ("machine=i386"); \
482 builtin_define_std ("i386"); \
483 } \
484 \
485 /* Built-ins based on -mcpu= (or -march= if no \
486 CPU given). */ \
487 if (TARGET_386) \
488 builtin_define ("__tune_i386__"); \
489 else if (TARGET_486) \
490 builtin_define ("__tune_i486__"); \
491 else if (TARGET_PENTIUM) \
492 { \
493 builtin_define ("__tune_i586__"); \
494 builtin_define ("__tune_pentium__"); \
495 if (last_cpu_char == 'x') \
496 builtin_define ("__tune_pentium_mmx__"); \
497 } \
498 else if (TARGET_PENTIUMPRO) \
499 { \
500 builtin_define ("__tune_i686__"); \
501 builtin_define ("__tune_pentiumpro__"); \
502 } \
503 else if (TARGET_K6) \
504 { \
505 builtin_define ("__tune_k6__"); \
506 if (last_cpu_char == '2') \
507 builtin_define ("__tune_k6_2__"); \
508 else if (last_cpu_char == '3') \
509 builtin_define ("__tune_k6_3__"); \
510 } \
511 else if (TARGET_ATHLON) \
512 { \
513 builtin_define ("__tune_athlon__"); \
514 /* Only plain "athlon" lacks SSE. */ \
515 if (last_cpu_char != 'n') \
516 builtin_define ("__tune_athlon_sse__"); \
517 } \
518 else if (TARGET_PENTIUM4) \
519 builtin_define ("__tune_pentium4__"); \
520 \
521 if (TARGET_MMX) \
522 builtin_define ("__MMX__"); \
523 if (TARGET_3DNOW) \
524 builtin_define ("__3dNOW__"); \
525 if (TARGET_3DNOW_A) \
526 builtin_define ("__3dNOW_A__"); \
527 if (TARGET_SSE) \
528 builtin_define ("__SSE__"); \
529 if (TARGET_SSE2) \
530 builtin_define ("__SSE2__"); \
531 \
532 /* Built-ins based on -march=. */ \
533 if (ix86_arch == PROCESSOR_I486) \
534 { \
535 builtin_define ("__i486"); \
536 builtin_define ("__i486__"); \
537 } \
538 else if (ix86_arch == PROCESSOR_PENTIUM) \
539 { \
540 builtin_define ("__i586"); \
541 builtin_define ("__i586__"); \
542 builtin_define ("__pentium"); \
543 builtin_define ("__pentium__"); \
544 if (last_arch_char == 'x') \
545 builtin_define ("__pentium_mmx__"); \
546 } \
547 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
548 { \
549 builtin_define ("__i686"); \
550 builtin_define ("__i686__"); \
551 builtin_define ("__pentiumpro"); \
552 builtin_define ("__pentiumpro__"); \
553 } \
554 else if (ix86_arch == PROCESSOR_K6) \
555 { \
556 \
557 builtin_define ("__k6"); \
558 builtin_define ("__k6__"); \
559 if (last_arch_char == '2') \
560 builtin_define ("__k6_2__"); \
561 else if (last_arch_char == '3') \
562 builtin_define ("__k6_3__"); \
563 } \
564 else if (ix86_arch == PROCESSOR_ATHLON) \
565 { \
566 builtin_define ("__athlon"); \
567 builtin_define ("__athlon__"); \
568 /* Only plain "athlon" lacks SSE. */ \
569 if (last_arch_char != 'n') \
570 builtin_define ("__athlon_sse__"); \
571 } \
572 else if (ix86_arch == PROCESSOR_PENTIUM4) \
573 { \
574 builtin_define ("__pentium4"); \
575 builtin_define ("__pentium4__"); \
576 } \
577 } \
578 while (0)
579
580 #define TARGET_CPU_DEFAULT_i386 0
581 #define TARGET_CPU_DEFAULT_i486 1
582 #define TARGET_CPU_DEFAULT_pentium 2
583 #define TARGET_CPU_DEFAULT_pentium_mmx 3
584 #define TARGET_CPU_DEFAULT_pentiumpro 4
585 #define TARGET_CPU_DEFAULT_pentium2 5
586 #define TARGET_CPU_DEFAULT_pentium3 6
587 #define TARGET_CPU_DEFAULT_pentium4 7
588 #define TARGET_CPU_DEFAULT_k6 8
589 #define TARGET_CPU_DEFAULT_k6_2 9
590 #define TARGET_CPU_DEFAULT_k6_3 10
591 #define TARGET_CPU_DEFAULT_athlon 11
592 #define TARGET_CPU_DEFAULT_athlon_sse 12
593
594 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
595 "pentiumpro", "pentium2", "pentium3", \
596 "pentium4", "k6", "k6-2", "k6-3",\
597 "athlon", "athlon-4"}
598
599 #ifndef CC1_SPEC
600 #define CC1_SPEC "%(cc1_cpu) "
601 #endif
602
603 /* This macro defines names of additional specifications to put in the
604 specs that can be used in various specifications like CC1_SPEC. Its
605 definition is an initializer with a subgrouping for each command option.
606
607 Each subgrouping contains a string constant, that defines the
608 specification name, and a string constant that used by the GNU CC driver
609 program.
610
611 Do not define this macro if it does not need to do anything. */
612
613 #ifndef SUBTARGET_EXTRA_SPECS
614 #define SUBTARGET_EXTRA_SPECS
615 #endif
616
617 #define EXTRA_SPECS \
618 { "cc1_cpu", CC1_CPU_SPEC }, \
619 SUBTARGET_EXTRA_SPECS
620 \f
621 /* target machine storage layout */
622
623 /* Define for XFmode or TFmode extended real floating point support.
624 The XFmode is specified by i386 ABI, while TFmode may be faster
625 due to alignment and simplifications in the address calculations.
626 */
627 #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
628 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
629 #ifdef __x86_64__
630 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
631 #else
632 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
633 #endif
634 /* Tell real.c that this is the 80-bit Intel extended float format
635 packaged in a 128-bit or 96bit entity. */
636 #define INTEL_EXTENDED_IEEE_FORMAT 1
637
638
639 #define SHORT_TYPE_SIZE 16
640 #define INT_TYPE_SIZE 32
641 #define FLOAT_TYPE_SIZE 32
642 #define LONG_TYPE_SIZE BITS_PER_WORD
643 #define MAX_WCHAR_TYPE_SIZE 32
644 #define DOUBLE_TYPE_SIZE 64
645 #define LONG_LONG_TYPE_SIZE 64
646
647 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
648 #define MAX_BITS_PER_WORD 64
649 #define MAX_LONG_TYPE_SIZE 64
650 #else
651 #define MAX_BITS_PER_WORD 32
652 #define MAX_LONG_TYPE_SIZE 32
653 #endif
654
655 /* Define this if most significant byte of a word is the lowest numbered. */
656 /* That is true on the 80386. */
657
658 #define BITS_BIG_ENDIAN 0
659
660 /* Define this if most significant byte of a word is the lowest numbered. */
661 /* That is not true on the 80386. */
662 #define BYTES_BIG_ENDIAN 0
663
664 /* Define this if most significant word of a multiword number is the lowest
665 numbered. */
666 /* Not true for 80386 */
667 #define WORDS_BIG_ENDIAN 0
668
669 /* Width of a word, in units (bytes). */
670 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
671 #define MIN_UNITS_PER_WORD 4
672
673 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
674 #define PARM_BOUNDARY BITS_PER_WORD
675
676 /* Boundary (in *bits*) on which stack pointer should be aligned. */
677 #define STACK_BOUNDARY BITS_PER_WORD
678
679 /* Boundary (in *bits*) on which the stack pointer preferrs to be
680 aligned; the compiler cannot rely on having this alignment. */
681 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
682
683 /* As of July 2001, many runtimes to not align the stack properly when
684 entering main. This causes expand_main_function to forcably align
685 the stack, which results in aligned frames for functions called from
686 main, though it does nothing for the alignment of main itself. */
687 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
688 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
689
690 /* Allocation boundary for the code of a function. */
691 #define FUNCTION_BOUNDARY 16
692
693 /* Alignment of field after `int : 0' in a structure. */
694
695 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
696
697 /* Minimum size in bits of the largest boundary to which any
698 and all fundamental data types supported by the hardware
699 might need to be aligned. No data type wants to be aligned
700 rounder than this.
701
702 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary
703 and Pentium Pro XFmode values at 128 bit boundaries. */
704
705 #define BIGGEST_ALIGNMENT 128
706
707 /* Decide whether a variable of mode MODE must be 128 bit aligned. */
708 #define ALIGN_MODE_128(MODE) \
709 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \
710 || (MODE) == V4SFmode || (MODE) == V4SImode)
711
712 /* The published ABIs say that doubles should be aligned on word
713 boundaries, so lower the aligment for structure fields unless
714 -malign-double is set. */
715 /* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be
716 constant. Use the smaller value in that context. */
717 #ifndef IN_TARGET_LIBS
718 #define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32))
719 #else
720 #define BIGGEST_FIELD_ALIGNMENT 32
721 #endif
722
723 /* If defined, a C expression to compute the alignment given to a
724 constant that is being placed in memory. EXP is the constant
725 and ALIGN is the alignment that the object would ordinarily have.
726 The value of this macro is used instead of that alignment to align
727 the object.
728
729 If this macro is not defined, then ALIGN is used.
730
731 The typical use of this macro is to increase alignment for string
732 constants to be word aligned so that `strcpy' calls that copy
733 constants can be done inline. */
734
735 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
736
737 /* If defined, a C expression to compute the alignment for a static
738 variable. TYPE is the data type, and ALIGN is the alignment that
739 the object would ordinarily have. The value of this macro is used
740 instead of that alignment to align the object.
741
742 If this macro is not defined, then ALIGN is used.
743
744 One use of this macro is to increase alignment of medium-size
745 data to make it all fit in fewer cache lines. Another is to
746 cause character arrays to be word-aligned so that `strcpy' calls
747 that copy constants to character arrays can be done inline. */
748
749 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
750
751 /* If defined, a C expression to compute the alignment for a local
752 variable. TYPE is the data type, and ALIGN is the alignment that
753 the object would ordinarily have. The value of this macro is used
754 instead of that alignment to align the object.
755
756 If this macro is not defined, then ALIGN is used.
757
758 One use of this macro is to increase alignment of medium-size
759 data to make it all fit in fewer cache lines. */
760
761 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
762
763 /* If defined, a C expression that gives the alignment boundary, in
764 bits, of an argument with the specified mode and type. If it is
765 not defined, `PARM_BOUNDARY' is used for all arguments. */
766
767 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
768 ix86_function_arg_boundary ((MODE), (TYPE))
769
770 /* Set this non-zero if move instructions will actually fail to work
771 when given unaligned data. */
772 #define STRICT_ALIGNMENT 0
773
774 /* If bit field type is int, don't let it cross an int,
775 and give entire struct the alignment of an int. */
776 /* Required on the 386 since it doesn't have bitfield insns. */
777 #define PCC_BITFIELD_TYPE_MATTERS 1
778 \f
779 /* Standard register usage. */
780
781 /* This processor has special stack-like registers. See reg-stack.c
782 for details. */
783
784 #define STACK_REGS
785 #define IS_STACK_MODE(MODE) \
786 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \
787 || (MODE) == TFmode)
788
789 /* Number of actual hardware registers.
790 The hardware registers are assigned numbers for the compiler
791 from 0 to just below FIRST_PSEUDO_REGISTER.
792 All registers that the compiler knows about must be given numbers,
793 even those that are not normally considered general registers.
794
795 In the 80386 we give the 8 general purpose registers the numbers 0-7.
796 We number the floating point registers 8-15.
797 Note that registers 0-7 can be accessed as a short or int,
798 while only 0-3 may be used with byte `mov' instructions.
799
800 Reg 16 does not correspond to any hardware register, but instead
801 appears in the RTL as an argument pointer prior to reload, and is
802 eliminated during reloading in favor of either the stack or frame
803 pointer. */
804
805 #define FIRST_PSEUDO_REGISTER 53
806
807 /* Number of hardware registers that go into the DWARF-2 unwind info.
808 If not defined, equals FIRST_PSEUDO_REGISTER. */
809
810 #define DWARF_FRAME_REGISTERS 17
811
812 /* 1 for registers that have pervasive standard uses
813 and are not available for the register allocator.
814 On the 80386, the stack pointer is such, as is the arg pointer.
815
816 The value is an mask - bit 1 is set for fixed registers
817 for 32bit target, while 2 is set for fixed registers for 64bit.
818 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
819 */
820 #define FIXED_REGISTERS \
821 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
822 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
823 /*arg,flags,fpsr,dir,frame*/ \
824 3, 3, 3, 3, 3, \
825 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
826 0, 0, 0, 0, 0, 0, 0, 0, \
827 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
828 0, 0, 0, 0, 0, 0, 0, 0, \
829 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
830 1, 1, 1, 1, 1, 1, 1, 1, \
831 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
832 1, 1, 1, 1, 1, 1, 1, 1}
833
834
835 /* 1 for registers not available across function calls.
836 These must include the FIXED_REGISTERS and also any
837 registers that can be used without being saved.
838 The latter must include the registers where values are returned
839 and the register where structure-value addresses are passed.
840 Aside from that, you can include as many other registers as you like.
841
842 The value is an mask - bit 1 is set for call used
843 for 32bit target, while 2 is set for call used for 64bit.
844 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
845 */
846 #define CALL_USED_REGISTERS \
847 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
848 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
849 /*arg,flags,fpsr,dir,frame*/ \
850 3, 3, 3, 3, 3, \
851 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
852 3, 3, 3, 3, 3, 3, 3, 3, \
853 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
854 3, 3, 3, 3, 3, 3, 3, 3, \
855 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
856 3, 3, 3, 3, 1, 1, 1, 1, \
857 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
858 3, 3, 3, 3, 3, 3, 3, 3} \
859
860 /* Order in which to allocate registers. Each register must be
861 listed once, even those in FIXED_REGISTERS. List frame pointer
862 late and fixed registers last. Note that, in general, we prefer
863 registers listed in CALL_USED_REGISTERS, keeping the others
864 available for storage of persistent values.
865
866 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
867 so this is just empty initializer for array. */
868
869 #define REG_ALLOC_ORDER \
870 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
871 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
872 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
873 48, 49, 50, 51, 52 }
874
875 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
876 to be rearranged based on a particular function. When using sse math,
877 we want to allocase SSE before x87 registers and vice vera. */
878
879 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
880
881
882 /* Macro to conditionally modify fixed_regs/call_used_regs. */
883 #define CONDITIONAL_REGISTER_USAGE \
884 do { \
885 int i; \
886 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
887 { \
888 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
889 call_used_regs[i] = (call_used_regs[i] \
890 & (TARGET_64BIT ? 2 : 1)) != 0; \
891 } \
892 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
893 { \
894 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
895 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
896 } \
897 if (! TARGET_MMX) \
898 { \
899 int i; \
900 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
901 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
902 fixed_regs[i] = call_used_regs[i] = 1; \
903 } \
904 if (! TARGET_SSE) \
905 { \
906 int i; \
907 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
908 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
909 fixed_regs[i] = call_used_regs[i] = 1; \
910 } \
911 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
912 { \
913 int i; \
914 HARD_REG_SET x; \
915 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
916 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
917 if (TEST_HARD_REG_BIT (x, i)) \
918 fixed_regs[i] = call_used_regs[i] = 1; \
919 } \
920 } while (0)
921
922 /* Return number of consecutive hard regs needed starting at reg REGNO
923 to hold something of mode MODE.
924 This is ordinarily the length in words of a value of mode MODE
925 but can be less for certain modes in special long registers.
926
927 Actually there are no two word move instructions for consecutive
928 registers. And only registers 0-3 may have mov byte instructions
929 applied to them.
930 */
931
932 #define HARD_REGNO_NREGS(REGNO, MODE) \
933 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
934 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
935 : ((MODE) == TFmode \
936 ? (TARGET_64BIT ? 2 : 3) \
937 : (MODE) == TCmode \
938 ? (TARGET_64BIT ? 4 : 6) \
939 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
940
941 #define VALID_SSE2_REG_MODE(MODE) \
942 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
943 || (MODE) == V2DImode)
944
945 #define VALID_SSE_REG_MODE(MODE) \
946 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
947 || (MODE) == SFmode \
948 /* Always accept SSE2 modes so that xmmintrin.h compiles. */ \
949 || VALID_SSE2_REG_MODE (MODE) \
950 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
951
952 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
953 ((MODE) == V2SFmode || (MODE) == SFmode)
954
955 #define VALID_MMX_REG_MODE(MODE) \
956 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
957 || (MODE) == V2SImode || (MODE) == SImode)
958
959 #define VECTOR_MODE_SUPPORTED_P(MODE) \
960 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
961 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \
962 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
963
964 #define VALID_FP_MODE_P(MODE) \
965 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
966 || (!TARGET_64BIT && (MODE) == XFmode) \
967 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \
968 || (!TARGET_64BIT && (MODE) == XCmode))
969
970 #define VALID_INT_MODE_P(MODE) \
971 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
972 || (MODE) == DImode \
973 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
974 || (MODE) == CDImode \
975 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode)))
976
977 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
978
979 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
980 ix86_hard_regno_mode_ok ((REGNO), (MODE))
981
982 /* Value is 1 if it is a good idea to tie two pseudo registers
983 when one has mode MODE1 and one has mode MODE2.
984 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
985 for any hard reg, then this must be 0 for correct output. */
986
987 #define MODES_TIEABLE_P(MODE1, MODE2) \
988 ((MODE1) == (MODE2) \
989 || (((MODE1) == HImode || (MODE1) == SImode \
990 || ((MODE1) == QImode \
991 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
992 || ((MODE1) == DImode && TARGET_64BIT)) \
993 && ((MODE2) == HImode || (MODE2) == SImode \
994 || ((MODE1) == QImode \
995 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
996 || ((MODE2) == DImode && TARGET_64BIT))))
997
998
999 /* Specify the modes required to caller save a given hard regno.
1000 We do this on i386 to prevent flags from being saved at all.
1001
1002 Kill any attempts to combine saving of modes. */
1003
1004 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1005 (CC_REGNO_P (REGNO) ? VOIDmode \
1006 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1007 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
1008 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1009 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1010 : (MODE))
1011 /* Specify the registers used for certain standard purposes.
1012 The values of these macros are register numbers. */
1013
1014 /* on the 386 the pc register is %eip, and is not usable as a general
1015 register. The ordinary mov instructions won't work */
1016 /* #define PC_REGNUM */
1017
1018 /* Register to use for pushing function arguments. */
1019 #define STACK_POINTER_REGNUM 7
1020
1021 /* Base register for access to local variables of the function. */
1022 #define HARD_FRAME_POINTER_REGNUM 6
1023
1024 /* Base register for access to local variables of the function. */
1025 #define FRAME_POINTER_REGNUM 20
1026
1027 /* First floating point reg */
1028 #define FIRST_FLOAT_REG 8
1029
1030 /* First & last stack-like regs */
1031 #define FIRST_STACK_REG FIRST_FLOAT_REG
1032 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1033
1034 #define FLAGS_REG 17
1035 #define FPSR_REG 18
1036 #define DIRFLAG_REG 19
1037
1038 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1039 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1040
1041 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1042 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1043
1044 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1045 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1046
1047 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1048 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1049
1050 /* Value should be nonzero if functions must have frame pointers.
1051 Zero means the frame pointer need not be set up (and parms
1052 may be accessed via the stack pointer) in functions that seem suitable.
1053 This is computed in `reload', in reload1.c. */
1054 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1055
1056 /* Override this in other tm.h files to cope with various OS losage
1057 requiring a frame pointer. */
1058 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1059 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1060 #endif
1061
1062 /* Make sure we can access arbitrary call frames. */
1063 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1064
1065 /* Base register for access to arguments of the function. */
1066 #define ARG_POINTER_REGNUM 16
1067
1068 /* Register in which static-chain is passed to a function.
1069 We do use ECX as static chain register for 32 bit ABI. On the
1070 64bit ABI, ECX is an argument register, so we use R10 instead. */
1071 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1072
1073 /* Register to hold the addressing base for position independent
1074 code access to data items. We don't use PIC pointer for 64bit
1075 mode. Define the regnum to dummy value to prevent gcc from
1076 pessimizing code dealing with EBX.
1077
1078 To avoid clobbering a call-saved register unnecessarily, we renumber
1079 the pic register when possible. The change is visible after the
1080 prologue has been emitted. */
1081
1082 #define REAL_PIC_OFFSET_TABLE_REGNUM 3
1083
1084 #define PIC_OFFSET_TABLE_REGNUM \
1085 (TARGET_64BIT || !flag_pic ? INVALID_REGNUM \
1086 : reload_completed ? REGNO (pic_offset_table_rtx) \
1087 : REAL_PIC_OFFSET_TABLE_REGNUM)
1088
1089 /* Register in which address to store a structure value
1090 arrives in the function. On the 386, the prologue
1091 copies this from the stack to register %eax. */
1092 #define STRUCT_VALUE_INCOMING 0
1093
1094 /* Place in which caller passes the structure value address.
1095 0 means push the value on the stack like an argument. */
1096 #define STRUCT_VALUE 0
1097
1098 /* A C expression which can inhibit the returning of certain function
1099 values in registers, based on the type of value. A nonzero value
1100 says to return the function value in memory, just as large
1101 structures are always returned. Here TYPE will be a C expression
1102 of type `tree', representing the data type of the value.
1103
1104 Note that values of mode `BLKmode' must be explicitly handled by
1105 this macro. Also, the option `-fpcc-struct-return' takes effect
1106 regardless of this macro. On most systems, it is possible to
1107 leave the macro undefined; this causes a default definition to be
1108 used, whose value is the constant 1 for `BLKmode' values, and 0
1109 otherwise.
1110
1111 Do not use this macro to indicate that structures and unions
1112 should always be returned in memory. You should instead use
1113 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1114
1115 #define RETURN_IN_MEMORY(TYPE) \
1116 ix86_return_in_memory (TYPE)
1117
1118 \f
1119 /* Define the classes of registers for register constraints in the
1120 machine description. Also define ranges of constants.
1121
1122 One of the classes must always be named ALL_REGS and include all hard regs.
1123 If there is more than one class, another class must be named NO_REGS
1124 and contain no registers.
1125
1126 The name GENERAL_REGS must be the name of a class (or an alias for
1127 another name such as ALL_REGS). This is the class of registers
1128 that is allowed by "g" or "r" in a register constraint.
1129 Also, registers outside this class are allocated only when
1130 instructions express preferences for them.
1131
1132 The classes must be numbered in nondecreasing order; that is,
1133 a larger-numbered class must never be contained completely
1134 in a smaller-numbered class.
1135
1136 For any two classes, it is very desirable that there be another
1137 class that represents their union.
1138
1139 It might seem that class BREG is unnecessary, since no useful 386
1140 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1141 and the "b" register constraint is useful in asms for syscalls.
1142
1143 The flags and fpsr registers are in no class. */
1144
1145 enum reg_class
1146 {
1147 NO_REGS,
1148 AREG, DREG, CREG, BREG, SIREG, DIREG,
1149 AD_REGS, /* %eax/%edx for DImode */
1150 Q_REGS, /* %eax %ebx %ecx %edx */
1151 NON_Q_REGS, /* %esi %edi %ebp %esp */
1152 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1153 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1154 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1155 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1156 FLOAT_REGS,
1157 SSE_REGS,
1158 MMX_REGS,
1159 FP_TOP_SSE_REGS,
1160 FP_SECOND_SSE_REGS,
1161 FLOAT_SSE_REGS,
1162 FLOAT_INT_REGS,
1163 INT_SSE_REGS,
1164 FLOAT_INT_SSE_REGS,
1165 ALL_REGS, LIM_REG_CLASSES
1166 };
1167
1168 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1169
1170 #define INTEGER_CLASS_P(CLASS) \
1171 reg_class_subset_p ((CLASS), GENERAL_REGS)
1172 #define FLOAT_CLASS_P(CLASS) \
1173 reg_class_subset_p ((CLASS), FLOAT_REGS)
1174 #define SSE_CLASS_P(CLASS) \
1175 reg_class_subset_p ((CLASS), SSE_REGS)
1176 #define MMX_CLASS_P(CLASS) \
1177 reg_class_subset_p ((CLASS), MMX_REGS)
1178 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1179 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1180 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1181 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1182 #define MAYBE_SSE_CLASS_P(CLASS) \
1183 reg_classes_intersect_p (SSE_REGS, (CLASS))
1184 #define MAYBE_MMX_CLASS_P(CLASS) \
1185 reg_classes_intersect_p (MMX_REGS, (CLASS))
1186
1187 #define Q_CLASS_P(CLASS) \
1188 reg_class_subset_p ((CLASS), Q_REGS)
1189
1190 /* Give names of register classes as strings for dump file. */
1191
1192 #define REG_CLASS_NAMES \
1193 { "NO_REGS", \
1194 "AREG", "DREG", "CREG", "BREG", \
1195 "SIREG", "DIREG", \
1196 "AD_REGS", \
1197 "Q_REGS", "NON_Q_REGS", \
1198 "INDEX_REGS", \
1199 "LEGACY_REGS", \
1200 "GENERAL_REGS", \
1201 "FP_TOP_REG", "FP_SECOND_REG", \
1202 "FLOAT_REGS", \
1203 "SSE_REGS", \
1204 "MMX_REGS", \
1205 "FP_TOP_SSE_REGS", \
1206 "FP_SECOND_SSE_REGS", \
1207 "FLOAT_SSE_REGS", \
1208 "FLOAT_INT_REGS", \
1209 "INT_SSE_REGS", \
1210 "FLOAT_INT_SSE_REGS", \
1211 "ALL_REGS" }
1212
1213 /* Define which registers fit in which classes.
1214 This is an initializer for a vector of HARD_REG_SET
1215 of length N_REG_CLASSES. */
1216
1217 #define REG_CLASS_CONTENTS \
1218 { { 0x00, 0x0 }, \
1219 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1220 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1221 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1222 { 0x03, 0x0 }, /* AD_REGS */ \
1223 { 0x0f, 0x0 }, /* Q_REGS */ \
1224 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1225 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1226 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1227 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1228 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1229 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1230 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1231 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1232 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1233 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1234 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1235 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1236 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1237 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1238 { 0xffffffff,0x1fffff } \
1239 }
1240
1241 /* The same information, inverted:
1242 Return the class number of the smallest class containing
1243 reg number REGNO. This could be a conditional expression
1244 or could index an array. */
1245
1246 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1247
1248 /* When defined, the compiler allows registers explicitly used in the
1249 rtl to be used as spill registers but prevents the compiler from
1250 extending the lifetime of these registers. */
1251
1252 #define SMALL_REGISTER_CLASSES 1
1253
1254 #define QI_REG_P(X) \
1255 (REG_P (X) && REGNO (X) < 4)
1256
1257 #define GENERAL_REGNO_P(N) \
1258 ((N) < 8 || REX_INT_REGNO_P (N))
1259
1260 #define GENERAL_REG_P(X) \
1261 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1262
1263 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1264
1265 #define NON_QI_REG_P(X) \
1266 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1267
1268 #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1269 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1270
1271 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1272 #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1273 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1274 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1275
1276 #define SSE_REGNO_P(N) \
1277 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1278 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1279
1280 #define SSE_REGNO(N) \
1281 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1282 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1283
1284 #define SSE_FLOAT_MODE_P(MODE) \
1285 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1286
1287 #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1288 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1289
1290 #define STACK_REG_P(XOP) \
1291 (REG_P (XOP) && \
1292 REGNO (XOP) >= FIRST_STACK_REG && \
1293 REGNO (XOP) <= LAST_STACK_REG)
1294
1295 #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1296
1297 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1298
1299 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1300 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1301
1302 /* Indicate whether hard register numbered REG_NO should be converted
1303 to SSA form. */
1304 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1305 ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM)
1306
1307 /* The class value for index registers, and the one for base regs. */
1308
1309 #define INDEX_REG_CLASS INDEX_REGS
1310 #define BASE_REG_CLASS GENERAL_REGS
1311
1312 /* Get reg_class from a letter such as appears in the machine description. */
1313
1314 #define REG_CLASS_FROM_LETTER(C) \
1315 ((C) == 'r' ? GENERAL_REGS : \
1316 (C) == 'R' ? LEGACY_REGS : \
1317 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1318 (C) == 'Q' ? Q_REGS : \
1319 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1320 ? FLOAT_REGS \
1321 : NO_REGS) : \
1322 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1323 ? FP_TOP_REG \
1324 : NO_REGS) : \
1325 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1326 ? FP_SECOND_REG \
1327 : NO_REGS) : \
1328 (C) == 'a' ? AREG : \
1329 (C) == 'b' ? BREG : \
1330 (C) == 'c' ? CREG : \
1331 (C) == 'd' ? DREG : \
1332 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1333 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1334 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1335 (C) == 'A' ? AD_REGS : \
1336 (C) == 'D' ? DIREG : \
1337 (C) == 'S' ? SIREG : NO_REGS)
1338
1339 /* The letters I, J, K, L and M in a register constraint string
1340 can be used to stand for particular ranges of immediate operands.
1341 This macro defines what the ranges are.
1342 C is the letter, and VALUE is a constant value.
1343 Return 1 if VALUE is in the range specified by C.
1344
1345 I is for non-DImode shifts.
1346 J is for DImode shifts.
1347 K is for signed imm8 operands.
1348 L is for andsi as zero-extending move.
1349 M is for shifts that can be executed by the "lea" opcode.
1350 N is for immedaite operands for out/in instructions (0-255)
1351 */
1352
1353 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1354 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1355 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1356 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1357 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1358 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1359 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1360 : 0)
1361
1362 /* Similar, but for floating constants, and defining letters G and H.
1363 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1364 TARGET_387 isn't set, because the stack register converter may need to
1365 load 0.0 into the function value register. */
1366
1367 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1368 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1369 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0))
1370
1371 /* A C expression that defines the optional machine-dependent
1372 constraint letters that can be used to segregate specific types of
1373 operands, usually memory references, for the target machine. Any
1374 letter that is not elsewhere defined and not matched by
1375 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1376 be defined.
1377
1378 If it is required for a particular target machine, it should
1379 return 1 if VALUE corresponds to the operand type represented by
1380 the constraint letter C. If C is not defined as an extra
1381 constraint, the value returned should be 0 regardless of VALUE. */
1382
1383 #define EXTRA_CONSTRAINT(VALUE, C) \
1384 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \
1385 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \
1386 : 0)
1387
1388 /* Place additional restrictions on the register class to use when it
1389 is necessary to be able to hold a value of mode MODE in a reload
1390 register for which class CLASS would ordinarily be used. */
1391
1392 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1393 ((MODE) == QImode && !TARGET_64BIT \
1394 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1395 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1396 ? Q_REGS : (CLASS))
1397
1398 /* Given an rtx X being reloaded into a reg required to be
1399 in class CLASS, return the class of reg to actually use.
1400 In general this is just CLASS; but on some machines
1401 in some cases it is preferable to use a more restrictive class.
1402 On the 80386 series, we prevent floating constants from being
1403 reloaded into floating registers (since no move-insn can do that)
1404 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1405
1406 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1407 QImode must go into class Q_REGS.
1408 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1409 movdf to do mem-to-mem moves through integer regs. */
1410
1411 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1412 ix86_preferred_reload_class ((X), (CLASS))
1413
1414 /* If we are copying between general and FP registers, we need a memory
1415 location. The same is true for SSE and MMX registers. */
1416 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1417 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1418
1419 /* QImode spills from non-QI registers need a scratch. This does not
1420 happen often -- the only example so far requires an uninitialized
1421 pseudo. */
1422
1423 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1424 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1425 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1426 ? Q_REGS : NO_REGS)
1427
1428 /* Return the maximum number of consecutive registers
1429 needed to represent mode MODE in a register of class CLASS. */
1430 /* On the 80386, this is the size of MODE in words,
1431 except in the FP regs, where a single reg is always enough.
1432 The TFmodes are really just 80bit values, so we use only 3 registers
1433 to hold them, instead of 4, as the size would suggest.
1434 */
1435 #define CLASS_MAX_NREGS(CLASS, MODE) \
1436 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1437 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1438 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \
1439 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1440
1441 /* A C expression whose value is nonzero if pseudos that have been
1442 assigned to registers of class CLASS would likely be spilled
1443 because registers of CLASS are needed for spill registers.
1444
1445 The default value of this macro returns 1 if CLASS has exactly one
1446 register and zero otherwise. On most machines, this default
1447 should be used. Only define this macro to some other expression
1448 if pseudo allocated by `local-alloc.c' end up in memory because
1449 their hard registers were needed for spill registers. If this
1450 macro returns nonzero for those classes, those pseudos will only
1451 be allocated by `global.c', which knows how to reallocate the
1452 pseudo to another register. If there would not be another
1453 register available for reallocation, you should not change the
1454 definition of this macro since the only effect of such a
1455 definition would be to slow down register allocation. */
1456
1457 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1458 (((CLASS) == AREG) \
1459 || ((CLASS) == DREG) \
1460 || ((CLASS) == CREG) \
1461 || ((CLASS) == BREG) \
1462 || ((CLASS) == AD_REGS) \
1463 || ((CLASS) == SIREG) \
1464 || ((CLASS) == DIREG))
1465
1466 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1467 to automatically clobber for all asms.
1468
1469 We do this in the new i386 backend to maintain source compatibility
1470 with the old cc0-based compiler. */
1471
1472 #define MD_ASM_CLOBBERS(CLOBBERS) \
1473 do { \
1474 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \
1475 (CLOBBERS)); \
1476 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \
1477 (CLOBBERS)); \
1478 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \
1479 (CLOBBERS)); \
1480 } while (0)
1481 \f
1482 /* Stack layout; function entry, exit and calling. */
1483
1484 /* Define this if pushing a word on the stack
1485 makes the stack pointer a smaller address. */
1486 #define STACK_GROWS_DOWNWARD
1487
1488 /* Define this if the nominal address of the stack frame
1489 is at the high-address end of the local variables;
1490 that is, each additional local variable allocated
1491 goes at a more negative offset in the frame. */
1492 #define FRAME_GROWS_DOWNWARD
1493
1494 /* Offset within stack frame to start allocating local variables at.
1495 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1496 first local allocated. Otherwise, it is the offset to the BEGINNING
1497 of the first local allocated. */
1498 #define STARTING_FRAME_OFFSET 0
1499
1500 /* If we generate an insn to push BYTES bytes,
1501 this says how many the stack pointer really advances by.
1502 On 386 pushw decrements by exactly 2 no matter what the position was.
1503 On the 386 there is no pushb; we use pushw instead, and this
1504 has the effect of rounding up to 2.
1505
1506 For 64bit ABI we round up to 8 bytes.
1507 */
1508
1509 #define PUSH_ROUNDING(BYTES) \
1510 (TARGET_64BIT \
1511 ? (((BYTES) + 7) & (-8)) \
1512 : (((BYTES) + 1) & (-2)))
1513
1514 /* If defined, the maximum amount of space required for outgoing arguments will
1515 be computed and placed into the variable
1516 `current_function_outgoing_args_size'. No space will be pushed onto the
1517 stack for each call; instead, the function prologue should increase the stack
1518 frame size by this amount. */
1519
1520 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1521
1522 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1523 instructions to pass outgoing arguments. */
1524
1525 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1526
1527 /* Offset of first parameter from the argument pointer register value. */
1528 #define FIRST_PARM_OFFSET(FNDECL) 0
1529
1530 /* Define this macro if functions should assume that stack space has been
1531 allocated for arguments even when their values are passed in registers.
1532
1533 The value of this macro is the size, in bytes, of the area reserved for
1534 arguments passed in registers for the function represented by FNDECL.
1535
1536 This space can be allocated by the caller, or be a part of the
1537 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1538 which. */
1539 #define REG_PARM_STACK_SPACE(FNDECL) 0
1540
1541 /* Define as a C expression that evaluates to nonzero if we do not know how
1542 to pass TYPE solely in registers. The file expr.h defines a
1543 definition that is usually appropriate, refer to expr.h for additional
1544 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1545 computed in the stack and then loaded into a register. */
1546 #define MUST_PASS_IN_STACK(MODE, TYPE) \
1547 ((TYPE) != 0 \
1548 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1549 || TREE_ADDRESSABLE (TYPE) \
1550 || ((MODE) == TImode) \
1551 || ((MODE) == BLKmode \
1552 && ! ((TYPE) != 0 \
1553 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
1554 && 0 == (int_size_in_bytes (TYPE) \
1555 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
1556 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
1557 == (BYTES_BIG_ENDIAN ? upward : downward)))))
1558
1559 /* Value is the number of bytes of arguments automatically
1560 popped when returning from a subroutine call.
1561 FUNDECL is the declaration node of the function (as a tree),
1562 FUNTYPE is the data type of the function (as a tree),
1563 or for a library call it is an identifier node for the subroutine name.
1564 SIZE is the number of bytes of arguments passed on the stack.
1565
1566 On the 80386, the RTD insn may be used to pop them if the number
1567 of args is fixed, but if the number is variable then the caller
1568 must pop them all. RTD can't be used for library calls now
1569 because the library is compiled with the Unix compiler.
1570 Use of RTD is a selectable option, since it is incompatible with
1571 standard Unix calling sequences. If the option is not selected,
1572 the caller must always pop the args.
1573
1574 The attribute stdcall is equivalent to RTD on a per module basis. */
1575
1576 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1577 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1578
1579 /* Define how to find the value returned by a function.
1580 VALTYPE is the data type of the value (as a tree).
1581 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1582 otherwise, FUNC is 0. */
1583 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1584 ix86_function_value (VALTYPE)
1585
1586 #define FUNCTION_VALUE_REGNO_P(N) \
1587 ix86_function_value_regno_p (N)
1588
1589 /* Define how to find the value returned by a library function
1590 assuming the value has mode MODE. */
1591
1592 #define LIBCALL_VALUE(MODE) \
1593 ix86_libcall_value (MODE)
1594
1595 /* Define the size of the result block used for communication between
1596 untyped_call and untyped_return. The block contains a DImode value
1597 followed by the block used by fnsave and frstor. */
1598
1599 #define APPLY_RESULT_SIZE (8+108)
1600
1601 /* 1 if N is a possible register number for function argument passing. */
1602 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1603
1604 /* Define a data type for recording info about an argument list
1605 during the scan of that argument list. This data type should
1606 hold all necessary information about the function itself
1607 and about the args processed so far, enough to enable macros
1608 such as FUNCTION_ARG to determine where the next arg should go. */
1609
1610 typedef struct ix86_args {
1611 int words; /* # words passed so far */
1612 int nregs; /* # registers available for passing */
1613 int regno; /* next available register number */
1614 int sse_words; /* # sse words passed so far */
1615 int sse_nregs; /* # sse registers available for passing */
1616 int sse_regno; /* next available sse register number */
1617 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1618 } CUMULATIVE_ARGS;
1619
1620 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1621 for a call to a function whose data type is FNTYPE.
1622 For a library call, FNTYPE is 0. */
1623
1624 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1625 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME))
1626
1627 /* Update the data in CUM to advance over an argument
1628 of mode MODE and data type TYPE.
1629 (TYPE is null for libcalls where that information may not be available.) */
1630
1631 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1632 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1633
1634 /* Define where to put the arguments to a function.
1635 Value is zero to push the argument on the stack,
1636 or a hard register in which to store the argument.
1637
1638 MODE is the argument's machine mode.
1639 TYPE is the data type of the argument (as a tree).
1640 This is null for libcalls where that information may
1641 not be available.
1642 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1643 the preceding args and about the function being called.
1644 NAMED is nonzero if this argument is a named parameter
1645 (otherwise it is an extra parameter matching an ellipsis). */
1646
1647 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1648 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1649
1650 /* For an arg passed partly in registers and partly in memory,
1651 this is the number of registers used.
1652 For args passed entirely in registers or entirely in memory, zero. */
1653
1654 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1655
1656 /* If PIC, we cannot make sibling calls to global functions
1657 because the PLT requires %ebx live.
1658 If we are returning floats on the register stack, we cannot make
1659 sibling calls to functions that return floats. (The stack adjust
1660 instruction will wind up after the sibcall jump, and not be executed.) */
1661 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1662 ((DECL) \
1663 && (! flag_pic || ! TREE_PUBLIC (DECL)) \
1664 && (! TARGET_FLOAT_RETURNS_IN_80387 \
1665 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \
1666 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))
1667
1668 /* Perform any needed actions needed for a function that is receiving a
1669 variable number of arguments.
1670
1671 CUM is as above.
1672
1673 MODE and TYPE are the mode and type of the current parameter.
1674
1675 PRETEND_SIZE is a variable that should be set to the amount of stack
1676 that must be pushed by the prolog to pretend that our caller pushed
1677 it.
1678
1679 Normally, this macro will push all remaining incoming registers on the
1680 stack and set PRETEND_SIZE to the length of the registers pushed. */
1681
1682 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1683 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \
1684 (NO_RTL))
1685
1686 /* Define the `__builtin_va_list' type for the ABI. */
1687 #define BUILD_VA_LIST_TYPE(VALIST) \
1688 ((VALIST) = ix86_build_va_list ())
1689
1690 /* Implement `va_start' for varargs and stdarg. */
1691 #define EXPAND_BUILTIN_VA_START(STDARG, VALIST, NEXTARG) \
1692 ix86_va_start ((STDARG), (VALIST), (NEXTARG))
1693
1694 /* Implement `va_arg'. */
1695 #define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \
1696 ix86_va_arg ((VALIST), (TYPE))
1697
1698 /* This macro is invoked at the end of compilation. It is used here to
1699 output code for -fpic that will load the return address into %ebx. */
1700
1701 #undef ASM_FILE_END
1702 #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE)
1703
1704 /* Output assembler code to FILE to increment profiler label # LABELNO
1705 for profiling a function entry. */
1706
1707 #define FUNCTION_PROFILER(FILE, LABELNO) \
1708 do { \
1709 if (flag_pic) \
1710 { \
1711 fprintf ((FILE), "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \
1712 LPREFIX, (LABELNO)); \
1713 fprintf ((FILE), "\tcall\t*_mcount@GOT(%%ebx)\n"); \
1714 } \
1715 else \
1716 { \
1717 fprintf ((FILE), "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
1718 fprintf ((FILE), "\tcall\t_mcount\n"); \
1719 } \
1720 } while (0)
1721
1722 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1723 the stack pointer does not matter. The value is tested only in
1724 functions that have frame pointers.
1725 No definition is equivalent to always zero. */
1726 /* Note on the 386 it might be more efficient not to define this since
1727 we have to restore it ourselves from the frame pointer, in order to
1728 use pop */
1729
1730 #define EXIT_IGNORE_STACK 1
1731
1732 /* Output assembler code for a block containing the constant parts
1733 of a trampoline, leaving space for the variable parts. */
1734
1735 /* On the 386, the trampoline contains two instructions:
1736 mov #STATIC,ecx
1737 jmp FUNCTION
1738 The trampoline is generated entirely at runtime. The operand of JMP
1739 is the address of FUNCTION relative to the instruction following the
1740 JMP (which is 5 bytes long). */
1741
1742 /* Length in units of the trampoline for entering a nested function. */
1743
1744 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1745
1746 /* Emit RTL insns to initialize the variable parts of a trampoline.
1747 FNADDR is an RTX for the address of the function's pure code.
1748 CXT is an RTX for the static chain value for the function. */
1749
1750 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1751 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1752 \f
1753 /* Definitions for register eliminations.
1754
1755 This is an array of structures. Each structure initializes one pair
1756 of eliminable registers. The "from" register number is given first,
1757 followed by "to". Eliminations of the same "from" register are listed
1758 in order of preference.
1759
1760 There are two registers that can always be eliminated on the i386.
1761 The frame pointer and the arg pointer can be replaced by either the
1762 hard frame pointer or to the stack pointer, depending upon the
1763 circumstances. The hard frame pointer is not used before reload and
1764 so it is not eligible for elimination. */
1765
1766 #define ELIMINABLE_REGS \
1767 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1768 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1769 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1770 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1771
1772 /* Given FROM and TO register numbers, say whether this elimination is
1773 allowed. Frame pointer elimination is automatically handled.
1774
1775 All other eliminations are valid. */
1776
1777 #define CAN_ELIMINATE(FROM, TO) \
1778 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1779
1780 /* Define the offset between two registers, one to be eliminated, and the other
1781 its replacement, at the start of a routine. */
1782
1783 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1784 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1785 \f
1786 /* Addressing modes, and classification of registers for them. */
1787
1788 /* #define HAVE_POST_INCREMENT 0 */
1789 /* #define HAVE_POST_DECREMENT 0 */
1790
1791 /* #define HAVE_PRE_DECREMENT 0 */
1792 /* #define HAVE_PRE_INCREMENT 0 */
1793
1794 /* Macros to check register numbers against specific register classes. */
1795
1796 /* These assume that REGNO is a hard or pseudo reg number.
1797 They give nonzero only if REGNO is a hard reg of the suitable class
1798 or a pseudo reg currently allocated to a suitable hard reg.
1799 Since they use reg_renumber, they are safe only once reg_renumber
1800 has been allocated, which happens in local-alloc.c. */
1801
1802 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1803 ((REGNO) < STACK_POINTER_REGNUM \
1804 || (REGNO >= FIRST_REX_INT_REG \
1805 && (REGNO) <= LAST_REX_INT_REG) \
1806 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1807 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1808 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1809
1810 #define REGNO_OK_FOR_BASE_P(REGNO) \
1811 ((REGNO) <= STACK_POINTER_REGNUM \
1812 || (REGNO) == ARG_POINTER_REGNUM \
1813 || (REGNO) == FRAME_POINTER_REGNUM \
1814 || (REGNO >= FIRST_REX_INT_REG \
1815 && (REGNO) <= LAST_REX_INT_REG) \
1816 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1817 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1818 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1819
1820 #define REGNO_OK_FOR_SIREG_P(REGNO) \
1821 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1822 #define REGNO_OK_FOR_DIREG_P(REGNO) \
1823 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1824
1825 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1826 and check its validity for a certain class.
1827 We have two alternate definitions for each of them.
1828 The usual definition accepts all pseudo regs; the other rejects
1829 them unless they have been allocated suitable hard regs.
1830 The symbol REG_OK_STRICT causes the latter definition to be used.
1831
1832 Most source files want to accept pseudo regs in the hope that
1833 they will get allocated to the class that the insn wants them to be in.
1834 Source files for reload pass need to be strict.
1835 After reload, it makes no difference, since pseudo regs have
1836 been eliminated by then. */
1837
1838
1839 /* Non strict versions, pseudos are ok */
1840 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1841 (REGNO (X) < STACK_POINTER_REGNUM \
1842 || (REGNO (X) >= FIRST_REX_INT_REG \
1843 && REGNO (X) <= LAST_REX_INT_REG) \
1844 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1845
1846 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1847 (REGNO (X) <= STACK_POINTER_REGNUM \
1848 || REGNO (X) == ARG_POINTER_REGNUM \
1849 || REGNO (X) == FRAME_POINTER_REGNUM \
1850 || (REGNO (X) >= FIRST_REX_INT_REG \
1851 && REGNO (X) <= LAST_REX_INT_REG) \
1852 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1853
1854 /* Strict versions, hard registers only */
1855 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1856 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1857
1858 #ifndef REG_OK_STRICT
1859 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1860 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1861
1862 #else
1863 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1864 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1865 #endif
1866
1867 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1868 that is a valid memory address for an instruction.
1869 The MODE argument is the machine mode for the MEM expression
1870 that wants to use this address.
1871
1872 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1873 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1874
1875 See legitimize_pic_address in i386.c for details as to what
1876 constitutes a legitimate address when -fpic is used. */
1877
1878 #define MAX_REGS_PER_ADDRESS 2
1879
1880 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1881
1882 /* Nonzero if the constant value X is a legitimate general operand.
1883 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1884
1885 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1886
1887 #ifdef REG_OK_STRICT
1888 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1889 do { \
1890 if (legitimate_address_p ((MODE), (X), 1)) \
1891 goto ADDR; \
1892 } while (0)
1893
1894 #else
1895 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1896 do { \
1897 if (legitimate_address_p ((MODE), (X), 0)) \
1898 goto ADDR; \
1899 } while (0)
1900
1901 #endif
1902
1903 /* If defined, a C expression to determine the base term of address X.
1904 This macro is used in only one place: `find_base_term' in alias.c.
1905
1906 It is always safe for this macro to not be defined. It exists so
1907 that alias analysis can understand machine-dependent addresses.
1908
1909 The typical use of this macro is to handle addresses containing
1910 a label_ref or symbol_ref within an UNSPEC. */
1911
1912 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1913
1914 /* Try machine-dependent ways of modifying an illegitimate address
1915 to be legitimate. If we find one, return the new, valid address.
1916 This macro is used in only one place: `memory_address' in explow.c.
1917
1918 OLDX is the address as it was before break_out_memory_refs was called.
1919 In some cases it is useful to look at this to decide what needs to be done.
1920
1921 MODE and WIN are passed so that this macro can use
1922 GO_IF_LEGITIMATE_ADDRESS.
1923
1924 It is always safe for this macro to do nothing. It exists to recognize
1925 opportunities to optimize the output.
1926
1927 For the 80386, we handle X+REG by loading X into a register R and
1928 using R+REG. R will go in a general reg and indexing will be used.
1929 However, if REG is a broken-out memory address or multiplication,
1930 nothing needs to be done because REG can certainly go in a general reg.
1931
1932 When -fpic is used, special handling is needed for symbolic references.
1933 See comments by legitimize_pic_address in i386.c for details. */
1934
1935 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1936 do { \
1937 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1938 if (memory_address_p ((MODE), (X))) \
1939 goto WIN; \
1940 } while (0)
1941
1942 #define REWRITE_ADDRESS(X) rewrite_address (X)
1943
1944 /* Nonzero if the constant value X is a legitimate general operand
1945 when generating PIC code. It is given that flag_pic is on and
1946 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1947
1948 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1949
1950 #define SYMBOLIC_CONST(X) \
1951 (GET_CODE (X) == SYMBOL_REF \
1952 || GET_CODE (X) == LABEL_REF \
1953 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1954
1955 /* Go to LABEL if ADDR (a legitimate address expression)
1956 has an effect that depends on the machine mode it is used for.
1957 On the 80386, only postdecrement and postincrement address depend thus
1958 (the amount of decrement or increment being the length of the operand). */
1959 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1960 do { \
1961 if (GET_CODE (ADDR) == POST_INC \
1962 || GET_CODE (ADDR) == POST_DEC) \
1963 goto LABEL; \
1964 } while (0)
1965 \f
1966 /* Codes for all the SSE/MMX builtins. */
1967 enum ix86_builtins
1968 {
1969 IX86_BUILTIN_ADDPS,
1970 IX86_BUILTIN_ADDSS,
1971 IX86_BUILTIN_DIVPS,
1972 IX86_BUILTIN_DIVSS,
1973 IX86_BUILTIN_MULPS,
1974 IX86_BUILTIN_MULSS,
1975 IX86_BUILTIN_SUBPS,
1976 IX86_BUILTIN_SUBSS,
1977
1978 IX86_BUILTIN_CMPEQPS,
1979 IX86_BUILTIN_CMPLTPS,
1980 IX86_BUILTIN_CMPLEPS,
1981 IX86_BUILTIN_CMPGTPS,
1982 IX86_BUILTIN_CMPGEPS,
1983 IX86_BUILTIN_CMPNEQPS,
1984 IX86_BUILTIN_CMPNLTPS,
1985 IX86_BUILTIN_CMPNLEPS,
1986 IX86_BUILTIN_CMPNGTPS,
1987 IX86_BUILTIN_CMPNGEPS,
1988 IX86_BUILTIN_CMPORDPS,
1989 IX86_BUILTIN_CMPUNORDPS,
1990 IX86_BUILTIN_CMPNEPS,
1991 IX86_BUILTIN_CMPEQSS,
1992 IX86_BUILTIN_CMPLTSS,
1993 IX86_BUILTIN_CMPLESS,
1994 IX86_BUILTIN_CMPGTSS,
1995 IX86_BUILTIN_CMPGESS,
1996 IX86_BUILTIN_CMPNEQSS,
1997 IX86_BUILTIN_CMPNLTSS,
1998 IX86_BUILTIN_CMPNLESS,
1999 IX86_BUILTIN_CMPNGTSS,
2000 IX86_BUILTIN_CMPNGESS,
2001 IX86_BUILTIN_CMPORDSS,
2002 IX86_BUILTIN_CMPUNORDSS,
2003 IX86_BUILTIN_CMPNESS,
2004
2005 IX86_BUILTIN_COMIEQSS,
2006 IX86_BUILTIN_COMILTSS,
2007 IX86_BUILTIN_COMILESS,
2008 IX86_BUILTIN_COMIGTSS,
2009 IX86_BUILTIN_COMIGESS,
2010 IX86_BUILTIN_COMINEQSS,
2011 IX86_BUILTIN_UCOMIEQSS,
2012 IX86_BUILTIN_UCOMILTSS,
2013 IX86_BUILTIN_UCOMILESS,
2014 IX86_BUILTIN_UCOMIGTSS,
2015 IX86_BUILTIN_UCOMIGESS,
2016 IX86_BUILTIN_UCOMINEQSS,
2017
2018 IX86_BUILTIN_CVTPI2PS,
2019 IX86_BUILTIN_CVTPS2PI,
2020 IX86_BUILTIN_CVTSI2SS,
2021 IX86_BUILTIN_CVTSS2SI,
2022 IX86_BUILTIN_CVTTPS2PI,
2023 IX86_BUILTIN_CVTTSS2SI,
2024
2025 IX86_BUILTIN_MAXPS,
2026 IX86_BUILTIN_MAXSS,
2027 IX86_BUILTIN_MINPS,
2028 IX86_BUILTIN_MINSS,
2029
2030 IX86_BUILTIN_LOADAPS,
2031 IX86_BUILTIN_LOADUPS,
2032 IX86_BUILTIN_STOREAPS,
2033 IX86_BUILTIN_STOREUPS,
2034 IX86_BUILTIN_LOADSS,
2035 IX86_BUILTIN_STORESS,
2036 IX86_BUILTIN_MOVSS,
2037
2038 IX86_BUILTIN_MOVHLPS,
2039 IX86_BUILTIN_MOVLHPS,
2040 IX86_BUILTIN_LOADHPS,
2041 IX86_BUILTIN_LOADLPS,
2042 IX86_BUILTIN_STOREHPS,
2043 IX86_BUILTIN_STORELPS,
2044
2045 IX86_BUILTIN_MASKMOVQ,
2046 IX86_BUILTIN_MOVMSKPS,
2047 IX86_BUILTIN_PMOVMSKB,
2048
2049 IX86_BUILTIN_MOVNTPS,
2050 IX86_BUILTIN_MOVNTQ,
2051
2052 IX86_BUILTIN_PACKSSWB,
2053 IX86_BUILTIN_PACKSSDW,
2054 IX86_BUILTIN_PACKUSWB,
2055
2056 IX86_BUILTIN_PADDB,
2057 IX86_BUILTIN_PADDW,
2058 IX86_BUILTIN_PADDD,
2059 IX86_BUILTIN_PADDSB,
2060 IX86_BUILTIN_PADDSW,
2061 IX86_BUILTIN_PADDUSB,
2062 IX86_BUILTIN_PADDUSW,
2063 IX86_BUILTIN_PSUBB,
2064 IX86_BUILTIN_PSUBW,
2065 IX86_BUILTIN_PSUBD,
2066 IX86_BUILTIN_PSUBSB,
2067 IX86_BUILTIN_PSUBSW,
2068 IX86_BUILTIN_PSUBUSB,
2069 IX86_BUILTIN_PSUBUSW,
2070
2071 IX86_BUILTIN_PAND,
2072 IX86_BUILTIN_PANDN,
2073 IX86_BUILTIN_POR,
2074 IX86_BUILTIN_PXOR,
2075
2076 IX86_BUILTIN_PAVGB,
2077 IX86_BUILTIN_PAVGW,
2078
2079 IX86_BUILTIN_PCMPEQB,
2080 IX86_BUILTIN_PCMPEQW,
2081 IX86_BUILTIN_PCMPEQD,
2082 IX86_BUILTIN_PCMPGTB,
2083 IX86_BUILTIN_PCMPGTW,
2084 IX86_BUILTIN_PCMPGTD,
2085
2086 IX86_BUILTIN_PEXTRW,
2087 IX86_BUILTIN_PINSRW,
2088
2089 IX86_BUILTIN_PMADDWD,
2090
2091 IX86_BUILTIN_PMAXSW,
2092 IX86_BUILTIN_PMAXUB,
2093 IX86_BUILTIN_PMINSW,
2094 IX86_BUILTIN_PMINUB,
2095
2096 IX86_BUILTIN_PMULHUW,
2097 IX86_BUILTIN_PMULHW,
2098 IX86_BUILTIN_PMULLW,
2099
2100 IX86_BUILTIN_PSADBW,
2101 IX86_BUILTIN_PSHUFW,
2102
2103 IX86_BUILTIN_PSLLW,
2104 IX86_BUILTIN_PSLLD,
2105 IX86_BUILTIN_PSLLQ,
2106 IX86_BUILTIN_PSRAW,
2107 IX86_BUILTIN_PSRAD,
2108 IX86_BUILTIN_PSRLW,
2109 IX86_BUILTIN_PSRLD,
2110 IX86_BUILTIN_PSRLQ,
2111 IX86_BUILTIN_PSLLWI,
2112 IX86_BUILTIN_PSLLDI,
2113 IX86_BUILTIN_PSLLQI,
2114 IX86_BUILTIN_PSRAWI,
2115 IX86_BUILTIN_PSRADI,
2116 IX86_BUILTIN_PSRLWI,
2117 IX86_BUILTIN_PSRLDI,
2118 IX86_BUILTIN_PSRLQI,
2119
2120 IX86_BUILTIN_PUNPCKHBW,
2121 IX86_BUILTIN_PUNPCKHWD,
2122 IX86_BUILTIN_PUNPCKHDQ,
2123 IX86_BUILTIN_PUNPCKLBW,
2124 IX86_BUILTIN_PUNPCKLWD,
2125 IX86_BUILTIN_PUNPCKLDQ,
2126
2127 IX86_BUILTIN_SHUFPS,
2128
2129 IX86_BUILTIN_RCPPS,
2130 IX86_BUILTIN_RCPSS,
2131 IX86_BUILTIN_RSQRTPS,
2132 IX86_BUILTIN_RSQRTSS,
2133 IX86_BUILTIN_SQRTPS,
2134 IX86_BUILTIN_SQRTSS,
2135
2136 IX86_BUILTIN_UNPCKHPS,
2137 IX86_BUILTIN_UNPCKLPS,
2138
2139 IX86_BUILTIN_ANDPS,
2140 IX86_BUILTIN_ANDNPS,
2141 IX86_BUILTIN_ORPS,
2142 IX86_BUILTIN_XORPS,
2143
2144 IX86_BUILTIN_EMMS,
2145 IX86_BUILTIN_LDMXCSR,
2146 IX86_BUILTIN_STMXCSR,
2147 IX86_BUILTIN_SFENCE,
2148
2149 /* 3DNow! Original */
2150 IX86_BUILTIN_FEMMS,
2151 IX86_BUILTIN_PAVGUSB,
2152 IX86_BUILTIN_PF2ID,
2153 IX86_BUILTIN_PFACC,
2154 IX86_BUILTIN_PFADD,
2155 IX86_BUILTIN_PFCMPEQ,
2156 IX86_BUILTIN_PFCMPGE,
2157 IX86_BUILTIN_PFCMPGT,
2158 IX86_BUILTIN_PFMAX,
2159 IX86_BUILTIN_PFMIN,
2160 IX86_BUILTIN_PFMUL,
2161 IX86_BUILTIN_PFRCP,
2162 IX86_BUILTIN_PFRCPIT1,
2163 IX86_BUILTIN_PFRCPIT2,
2164 IX86_BUILTIN_PFRSQIT1,
2165 IX86_BUILTIN_PFRSQRT,
2166 IX86_BUILTIN_PFSUB,
2167 IX86_BUILTIN_PFSUBR,
2168 IX86_BUILTIN_PI2FD,
2169 IX86_BUILTIN_PMULHRW,
2170
2171 /* 3DNow! Athlon Extensions */
2172 IX86_BUILTIN_PF2IW,
2173 IX86_BUILTIN_PFNACC,
2174 IX86_BUILTIN_PFPNACC,
2175 IX86_BUILTIN_PI2FW,
2176 IX86_BUILTIN_PSWAPDSI,
2177 IX86_BUILTIN_PSWAPDSF,
2178
2179 IX86_BUILTIN_SSE_ZERO,
2180 IX86_BUILTIN_MMX_ZERO,
2181
2182 /* SSE2 */
2183 IX86_BUILTIN_ADDPD,
2184 IX86_BUILTIN_ADDSD,
2185 IX86_BUILTIN_DIVPD,
2186 IX86_BUILTIN_DIVSD,
2187 IX86_BUILTIN_MULPD,
2188 IX86_BUILTIN_MULSD,
2189 IX86_BUILTIN_SUBPD,
2190 IX86_BUILTIN_SUBSD,
2191
2192 IX86_BUILTIN_CMPEQPD,
2193 IX86_BUILTIN_CMPLTPD,
2194 IX86_BUILTIN_CMPLEPD,
2195 IX86_BUILTIN_CMPGTPD,
2196 IX86_BUILTIN_CMPGEPD,
2197 IX86_BUILTIN_CMPNEQPD,
2198 IX86_BUILTIN_CMPNLTPD,
2199 IX86_BUILTIN_CMPNLEPD,
2200 IX86_BUILTIN_CMPNGTPD,
2201 IX86_BUILTIN_CMPNGEPD,
2202 IX86_BUILTIN_CMPORDPD,
2203 IX86_BUILTIN_CMPUNORDPD,
2204 IX86_BUILTIN_CMPNEPD,
2205 IX86_BUILTIN_CMPEQSD,
2206 IX86_BUILTIN_CMPLTSD,
2207 IX86_BUILTIN_CMPLESD,
2208 IX86_BUILTIN_CMPGTSD,
2209 IX86_BUILTIN_CMPGESD,
2210 IX86_BUILTIN_CMPNEQSD,
2211 IX86_BUILTIN_CMPNLTSD,
2212 IX86_BUILTIN_CMPNLESD,
2213 IX86_BUILTIN_CMPNGTSD,
2214 IX86_BUILTIN_CMPNGESD,
2215 IX86_BUILTIN_CMPORDSD,
2216 IX86_BUILTIN_CMPUNORDSD,
2217 IX86_BUILTIN_CMPNESD,
2218
2219 IX86_BUILTIN_COMIEQSD,
2220 IX86_BUILTIN_COMILTSD,
2221 IX86_BUILTIN_COMILESD,
2222 IX86_BUILTIN_COMIGTSD,
2223 IX86_BUILTIN_COMIGESD,
2224 IX86_BUILTIN_COMINEQSD,
2225 IX86_BUILTIN_UCOMIEQSD,
2226 IX86_BUILTIN_UCOMILTSD,
2227 IX86_BUILTIN_UCOMILESD,
2228 IX86_BUILTIN_UCOMIGTSD,
2229 IX86_BUILTIN_UCOMIGESD,
2230 IX86_BUILTIN_UCOMINEQSD,
2231
2232 IX86_BUILTIN_MAXPD,
2233 IX86_BUILTIN_MAXSD,
2234 IX86_BUILTIN_MINPD,
2235 IX86_BUILTIN_MINSD,
2236
2237 IX86_BUILTIN_ANDPD,
2238 IX86_BUILTIN_ANDNPD,
2239 IX86_BUILTIN_ORPD,
2240 IX86_BUILTIN_XORPD,
2241
2242 IX86_BUILTIN_SQRTPD,
2243 IX86_BUILTIN_SQRTSD,
2244
2245 IX86_BUILTIN_UNPCKHPD,
2246 IX86_BUILTIN_UNPCKLPD,
2247
2248 IX86_BUILTIN_SHUFPD,
2249
2250 IX86_BUILTIN_LOADAPD,
2251 IX86_BUILTIN_LOADUPD,
2252 IX86_BUILTIN_STOREAPD,
2253 IX86_BUILTIN_STOREUPD,
2254 IX86_BUILTIN_LOADSD,
2255 IX86_BUILTIN_STORESD,
2256 IX86_BUILTIN_MOVSD,
2257
2258 IX86_BUILTIN_LOADHPD,
2259 IX86_BUILTIN_LOADLPD,
2260 IX86_BUILTIN_STOREHPD,
2261 IX86_BUILTIN_STORELPD,
2262
2263 IX86_BUILTIN_CVTDQ2PD,
2264 IX86_BUILTIN_CVTDQ2PS,
2265
2266 IX86_BUILTIN_CVTPD2DQ,
2267 IX86_BUILTIN_CVTPD2PI,
2268 IX86_BUILTIN_CVTPD2PS,
2269 IX86_BUILTIN_CVTTPD2DQ,
2270 IX86_BUILTIN_CVTTPD2PI,
2271
2272 IX86_BUILTIN_CVTPI2PD,
2273 IX86_BUILTIN_CVTSI2SD,
2274
2275 IX86_BUILTIN_CVTSD2SI,
2276 IX86_BUILTIN_CVTSD2SS,
2277 IX86_BUILTIN_CVTSS2SD,
2278 IX86_BUILTIN_CVTTSD2SI,
2279
2280 IX86_BUILTIN_CVTPS2DQ,
2281 IX86_BUILTIN_CVTPS2PD,
2282 IX86_BUILTIN_CVTTPS2DQ,
2283
2284 IX86_BUILTIN_MOVNTI,
2285 IX86_BUILTIN_MOVNTPD,
2286 IX86_BUILTIN_MOVNTDQ,
2287
2288 IX86_BUILTIN_SETPD1,
2289 IX86_BUILTIN_SETPD,
2290 IX86_BUILTIN_CLRPD,
2291 IX86_BUILTIN_SETRPD,
2292 IX86_BUILTIN_LOADPD1,
2293 IX86_BUILTIN_LOADRPD,
2294 IX86_BUILTIN_STOREPD1,
2295 IX86_BUILTIN_STORERPD,
2296
2297 /* SSE2 MMX */
2298 IX86_BUILTIN_MASKMOVDQU,
2299 IX86_BUILTIN_MOVMSKPD,
2300 IX86_BUILTIN_PMOVMSKB128,
2301 IX86_BUILTIN_MOVQ2DQ,
2302
2303 IX86_BUILTIN_PACKSSWB128,
2304 IX86_BUILTIN_PACKSSDW128,
2305 IX86_BUILTIN_PACKUSWB128,
2306
2307 IX86_BUILTIN_PADDB128,
2308 IX86_BUILTIN_PADDW128,
2309 IX86_BUILTIN_PADDD128,
2310 IX86_BUILTIN_PADDQ128,
2311 IX86_BUILTIN_PADDSB128,
2312 IX86_BUILTIN_PADDSW128,
2313 IX86_BUILTIN_PADDUSB128,
2314 IX86_BUILTIN_PADDUSW128,
2315 IX86_BUILTIN_PSUBB128,
2316 IX86_BUILTIN_PSUBW128,
2317 IX86_BUILTIN_PSUBD128,
2318 IX86_BUILTIN_PSUBQ128,
2319 IX86_BUILTIN_PSUBSB128,
2320 IX86_BUILTIN_PSUBSW128,
2321 IX86_BUILTIN_PSUBUSB128,
2322 IX86_BUILTIN_PSUBUSW128,
2323
2324 IX86_BUILTIN_PAND128,
2325 IX86_BUILTIN_PANDN128,
2326 IX86_BUILTIN_POR128,
2327 IX86_BUILTIN_PXOR128,
2328
2329 IX86_BUILTIN_PAVGB128,
2330 IX86_BUILTIN_PAVGW128,
2331
2332 IX86_BUILTIN_PCMPEQB128,
2333 IX86_BUILTIN_PCMPEQW128,
2334 IX86_BUILTIN_PCMPEQD128,
2335 IX86_BUILTIN_PCMPGTB128,
2336 IX86_BUILTIN_PCMPGTW128,
2337 IX86_BUILTIN_PCMPGTD128,
2338
2339 IX86_BUILTIN_PEXTRW128,
2340 IX86_BUILTIN_PINSRW128,
2341
2342 IX86_BUILTIN_PMADDWD128,
2343
2344 IX86_BUILTIN_PMAXSW128,
2345 IX86_BUILTIN_PMAXUB128,
2346 IX86_BUILTIN_PMINSW128,
2347 IX86_BUILTIN_PMINUB128,
2348
2349 IX86_BUILTIN_PMULUDQ,
2350 IX86_BUILTIN_PMULUDQ128,
2351 IX86_BUILTIN_PMULHUW128,
2352 IX86_BUILTIN_PMULHW128,
2353 IX86_BUILTIN_PMULLW128,
2354
2355 IX86_BUILTIN_PSADBW128,
2356 IX86_BUILTIN_PSHUFHW,
2357 IX86_BUILTIN_PSHUFLW,
2358 IX86_BUILTIN_PSHUFD,
2359
2360 IX86_BUILTIN_PSLLW128,
2361 IX86_BUILTIN_PSLLD128,
2362 IX86_BUILTIN_PSLLQ128,
2363 IX86_BUILTIN_PSRAW128,
2364 IX86_BUILTIN_PSRAD128,
2365 IX86_BUILTIN_PSRLW128,
2366 IX86_BUILTIN_PSRLD128,
2367 IX86_BUILTIN_PSRLQ128,
2368 IX86_BUILTIN_PSLLWI128,
2369 IX86_BUILTIN_PSLLDI128,
2370 IX86_BUILTIN_PSLLQI128,
2371 IX86_BUILTIN_PSRAWI128,
2372 IX86_BUILTIN_PSRADI128,
2373 IX86_BUILTIN_PSRLWI128,
2374 IX86_BUILTIN_PSRLDI128,
2375 IX86_BUILTIN_PSRLQI128,
2376
2377 IX86_BUILTIN_PUNPCKHBW128,
2378 IX86_BUILTIN_PUNPCKHWD128,
2379 IX86_BUILTIN_PUNPCKHDQ128,
2380 IX86_BUILTIN_PUNPCKLBW128,
2381 IX86_BUILTIN_PUNPCKLWD128,
2382 IX86_BUILTIN_PUNPCKLDQ128,
2383
2384 IX86_BUILTIN_CLFLUSH,
2385 IX86_BUILTIN_MFENCE,
2386 IX86_BUILTIN_LFENCE,
2387
2388 IX86_BUILTIN_MAX
2389 };
2390 \f
2391 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
2392 #define TARGET_STRIP_NAME_ENCODING ix86_strip_name_encoding
2393
2394 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2395 do { \
2396 const char *xname = (NAME); \
2397 if (xname[0] == '%') \
2398 xname += 2; \
2399 if (xname[0] == '*') \
2400 xname += 1; \
2401 else \
2402 fputs (user_label_prefix, FILE); \
2403 fputs (xname, FILE); \
2404 } while (0)
2405 \f
2406 /* Max number of args passed in registers. If this is more than 3, we will
2407 have problems with ebx (register #4), since it is a caller save register and
2408 is also used as the pic register in ELF. So for now, don't allow more than
2409 3 registers to be passed in registers. */
2410
2411 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2412
2413 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0)
2414
2415 \f
2416 /* Specify the machine mode that this machine uses
2417 for the index in the tablejump instruction. */
2418 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
2419
2420 /* Define as C expression which evaluates to nonzero if the tablejump
2421 instruction expects the table to contain offsets from the address of the
2422 table.
2423 Do not define this if the table should contain absolute addresses. */
2424 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2425
2426 /* Define this as 1 if `char' should by default be signed; else as 0. */
2427 #define DEFAULT_SIGNED_CHAR 1
2428
2429 /* Number of bytes moved into a data cache for a single prefetch operation. */
2430 #define PREFETCH_BLOCK ix86_cost->prefetch_block
2431
2432 /* Number of prefetch operations that can be done in parallel. */
2433 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
2434
2435 /* Max number of bytes we can move from memory to memory
2436 in one reasonably fast instruction. */
2437 #define MOVE_MAX 16
2438
2439 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2440 move efficiently, as opposed to MOVE_MAX which is the maximum
2441 number of bytes we can move with a single instruction. */
2442 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2443
2444 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2445 move-instruction pairs, we will do a movstr or libcall instead.
2446 Increasing the value will always make code faster, but eventually
2447 incurs high cost in increased code size.
2448
2449 If you don't define this, a reasonable default is used. */
2450
2451 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2452
2453 /* Define if shifts truncate the shift count
2454 which implies one can omit a sign-extension or zero-extension
2455 of a shift count. */
2456 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2457
2458 /* #define SHIFT_COUNT_TRUNCATED */
2459
2460 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2461 is done just by pretending it is already truncated. */
2462 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2463
2464 /* We assume that the store-condition-codes instructions store 0 for false
2465 and some other value for true. This is the value stored for true. */
2466
2467 #define STORE_FLAG_VALUE 1
2468
2469 /* When a prototype says `char' or `short', really pass an `int'.
2470 (The 386 can't easily push less than an int.) */
2471
2472 #define PROMOTE_PROTOTYPES 1
2473
2474 /* A macro to update M and UNSIGNEDP when an object whose type is
2475 TYPE and which has the specified mode and signedness is to be
2476 stored in a register. This macro is only called when TYPE is a
2477 scalar type.
2478
2479 On i386 it is sometimes useful to promote HImode and QImode
2480 quantities to SImode. The choice depends on target type. */
2481
2482 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2483 do { \
2484 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2485 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2486 (MODE) = SImode; \
2487 } while (0)
2488
2489 /* Specify the machine mode that pointers have.
2490 After generation of rtl, the compiler makes no further distinction
2491 between pointers and any other objects of this machine mode. */
2492 #define Pmode (TARGET_64BIT ? DImode : SImode)
2493
2494 /* A function address in a call instruction
2495 is a byte address (for indexing purposes)
2496 so give the MEM rtx a byte's mode. */
2497 #define FUNCTION_MODE QImode
2498 \f
2499 /* A part of a C `switch' statement that describes the relative costs
2500 of constant RTL expressions. It must contain `case' labels for
2501 expression codes `const_int', `const', `symbol_ref', `label_ref'
2502 and `const_double'. Each case must ultimately reach a `return'
2503 statement to return the relative cost of the use of that kind of
2504 constant value in an expression. The cost may depend on the
2505 precise value of the constant, which is available for examination
2506 in X, and the rtx code of the expression in which it is contained,
2507 found in OUTER_CODE.
2508
2509 CODE is the expression code--redundant, since it can be obtained
2510 with `GET_CODE (X)'. */
2511
2512 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
2513 case CONST_INT: \
2514 case CONST: \
2515 case LABEL_REF: \
2516 case SYMBOL_REF: \
2517 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \
2518 return 3; \
2519 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \
2520 return 2; \
2521 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \
2522 \
2523 case CONST_DOUBLE: \
2524 if (GET_MODE (RTX) == VOIDmode) \
2525 return 0; \
2526 switch (standard_80387_constant_p (RTX)) \
2527 { \
2528 case 1: /* 0.0 */ \
2529 return 1; \
2530 case 2: /* 1.0 */ \
2531 return 2; \
2532 default: \
2533 /* Start with (MEM (SYMBOL_REF)), since that's where \
2534 it'll probably end up. Add a penalty for size. */ \
2535 return (COSTS_N_INSNS (1) + (flag_pic != 0) \
2536 + (GET_MODE (RTX) == SFmode ? 0 \
2537 : GET_MODE (RTX) == DFmode ? 1 : 2)); \
2538 }
2539
2540 /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */
2541 #define TOPLEVEL_COSTS_N_INSNS(N) \
2542 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0)
2543
2544 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2545 This can be used, for example, to indicate how costly a multiply
2546 instruction is. In writing this macro, you can use the construct
2547 `COSTS_N_INSNS (N)' to specify a cost equal to N fast
2548 instructions. OUTER_CODE is the code of the expression in which X
2549 is contained.
2550
2551 This macro is optional; do not define it if the default cost
2552 assumptions are adequate for the target machine. */
2553
2554 #define RTX_COSTS(X, CODE, OUTER_CODE) \
2555 case ZERO_EXTEND: \
2556 /* The zero extensions is often completely free on x86_64, so make \
2557 it as cheap as possible. */ \
2558 if (TARGET_64BIT && GET_MODE (X) == DImode \
2559 && GET_MODE (XEXP (X, 0)) == SImode) \
2560 { \
2561 total = 1; goto egress_rtx_costs; \
2562 } \
2563 else \
2564 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \
2565 ix86_cost->add : ix86_cost->movzx); \
2566 break; \
2567 case SIGN_EXTEND: \
2568 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \
2569 break; \
2570 case ASHIFT: \
2571 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2572 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \
2573 { \
2574 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2575 if (value == 1) \
2576 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2577 if ((value == 2 || value == 3) \
2578 && !TARGET_DECOMPOSE_LEA \
2579 && ix86_cost->lea <= ix86_cost->shift_const) \
2580 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \
2581 } \
2582 /* fall through */ \
2583 \
2584 case ROTATE: \
2585 case ASHIFTRT: \
2586 case LSHIFTRT: \
2587 case ROTATERT: \
2588 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \
2589 { \
2590 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2591 { \
2592 if (INTVAL (XEXP (X, 1)) > 32) \
2593 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \
2594 else \
2595 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \
2596 } \
2597 else \
2598 { \
2599 if (GET_CODE (XEXP (X, 1)) == AND) \
2600 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \
2601 else \
2602 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \
2603 } \
2604 } \
2605 else \
2606 { \
2607 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2608 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \
2609 else \
2610 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \
2611 } \
2612 break; \
2613 \
2614 case MULT: \
2615 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2616 { \
2617 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2618 int nbits = 0; \
2619 \
2620 while (value != 0) \
2621 { \
2622 nbits++; \
2623 value >>= 1; \
2624 } \
2625 \
2626 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2627 + nbits * ix86_cost->mult_bit); \
2628 } \
2629 else /* This is arbitrary */ \
2630 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2631 + 7 * ix86_cost->mult_bit); \
2632 \
2633 case DIV: \
2634 case UDIV: \
2635 case MOD: \
2636 case UMOD: \
2637 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
2638 \
2639 case PLUS: \
2640 if (!TARGET_DECOMPOSE_LEA \
2641 && INTEGRAL_MODE_P (GET_MODE (X)) \
2642 && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \
2643 { \
2644 if (GET_CODE (XEXP (X, 0)) == PLUS \
2645 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \
2646 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \
2647 && CONSTANT_P (XEXP (X, 1))) \
2648 { \
2649 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\
2650 if (val == 2 || val == 4 || val == 8) \
2651 { \
2652 return (COSTS_N_INSNS (ix86_cost->lea) \
2653 + rtx_cost (XEXP (XEXP (X, 0), 1), \
2654 (OUTER_CODE)) \
2655 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), \
2656 (OUTER_CODE)) \
2657 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2658 } \
2659 } \
2660 else if (GET_CODE (XEXP (X, 0)) == MULT \
2661 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
2662 { \
2663 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
2664 if (val == 2 || val == 4 || val == 8) \
2665 { \
2666 return (COSTS_N_INSNS (ix86_cost->lea) \
2667 + rtx_cost (XEXP (XEXP (X, 0), 0), \
2668 (OUTER_CODE)) \
2669 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2670 } \
2671 } \
2672 else if (GET_CODE (XEXP (X, 0)) == PLUS) \
2673 { \
2674 return (COSTS_N_INSNS (ix86_cost->lea) \
2675 + rtx_cost (XEXP (XEXP (X, 0), 0), (OUTER_CODE)) \
2676 + rtx_cost (XEXP (XEXP (X, 0), 1), (OUTER_CODE)) \
2677 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2678 } \
2679 } \
2680 \
2681 /* fall through */ \
2682 case AND: \
2683 case IOR: \
2684 case XOR: \
2685 case MINUS: \
2686 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2687 return (COSTS_N_INSNS (ix86_cost->add) * 2 \
2688 + (rtx_cost (XEXP (X, 0), (OUTER_CODE)) \
2689 << (GET_MODE (XEXP (X, 0)) != DImode)) \
2690 + (rtx_cost (XEXP (X, 1), (OUTER_CODE)) \
2691 << (GET_MODE (XEXP (X, 1)) != DImode))); \
2692 \
2693 /* fall through */ \
2694 case NEG: \
2695 case NOT: \
2696 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2697 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \
2698 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2699 \
2700 case FLOAT_EXTEND: \
2701 TOPLEVEL_COSTS_N_INSNS (0); \
2702 \
2703 egress_rtx_costs: \
2704 break;
2705
2706
2707 /* An expression giving the cost of an addressing mode that contains
2708 ADDRESS. If not defined, the cost is computed from the ADDRESS
2709 expression and the `CONST_COSTS' values.
2710
2711 For most CISC machines, the default cost is a good approximation
2712 of the true cost of the addressing mode. However, on RISC
2713 machines, all instructions normally have the same length and
2714 execution time. Hence all addresses will have equal costs.
2715
2716 In cases where more than one form of an address is known, the form
2717 with the lowest cost will be used. If multiple forms have the
2718 same, lowest, cost, the one that is the most complex will be used.
2719
2720 For example, suppose an address that is equal to the sum of a
2721 register and a constant is used twice in the same basic block.
2722 When this macro is not defined, the address will be computed in a
2723 register and memory references will be indirect through that
2724 register. On machines where the cost of the addressing mode
2725 containing the sum is no higher than that of a simple indirect
2726 reference, this will produce an additional instruction and
2727 possibly require an additional register. Proper specification of
2728 this macro eliminates this overhead for such machines.
2729
2730 Similar use of this macro is made in strength reduction of loops.
2731
2732 ADDRESS need not be valid as an address. In such a case, the cost
2733 is not relevant and can be any value; invalid addresses need not be
2734 assigned a different cost.
2735
2736 On machines where an address involving more than one register is as
2737 cheap as an address computation involving only one register,
2738 defining `ADDRESS_COST' to reflect this can cause two registers to
2739 be live over a region of code where only one would have been if
2740 `ADDRESS_COST' were not defined in that manner. This effect should
2741 be considered in the definition of this macro. Equivalent costs
2742 should probably only be given to addresses with different numbers
2743 of registers on machines with lots of registers.
2744
2745 This macro will normally either not be defined or be defined as a
2746 constant.
2747
2748 For i386, it is better to use a complex address than let gcc copy
2749 the address into a reg and make a new pseudo. But not if the address
2750 requires to two regs - that would mean more pseudos with longer
2751 lifetimes. */
2752
2753 #define ADDRESS_COST(RTX) \
2754 ix86_address_cost (RTX)
2755
2756 /* A C expression for the cost of moving data from a register in class FROM to
2757 one in class TO. The classes are expressed using the enumeration values
2758 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2759 interpreted relative to that.
2760
2761 It is not required that the cost always equal 2 when FROM is the same as TO;
2762 on some machines it is expensive to move between registers if they are not
2763 general registers. */
2764
2765 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2766 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
2767
2768 /* A C expression for the cost of moving data of mode M between a
2769 register and memory. A value of 2 is the default; this cost is
2770 relative to those in `REGISTER_MOVE_COST'.
2771
2772 If moving between registers and memory is more expensive than
2773 between two registers, you should define this macro to express the
2774 relative cost. */
2775
2776 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
2777 ix86_memory_move_cost ((MODE), (CLASS), (IN))
2778
2779 /* A C expression for the cost of a branch instruction. A value of 1
2780 is the default; other values are interpreted relative to that. */
2781
2782 #define BRANCH_COST ix86_branch_cost
2783
2784 /* Define this macro as a C expression which is nonzero if accessing
2785 less than a word of memory (i.e. a `char' or a `short') is no
2786 faster than accessing a word of memory, i.e., if such access
2787 require more than one instruction or if there is no difference in
2788 cost between byte and (aligned) word loads.
2789
2790 When this macro is not defined, the compiler will access a field by
2791 finding the smallest containing object; when it is defined, a
2792 fullword load will be used if alignment permits. Unless bytes
2793 accesses are faster than word accesses, using word accesses is
2794 preferable since it may eliminate subsequent memory access if
2795 subsequent accesses occur to other fields in the same word of the
2796 structure, but to different bytes. */
2797
2798 #define SLOW_BYTE_ACCESS 0
2799
2800 /* Nonzero if access to memory by shorts is slow and undesirable. */
2801 #define SLOW_SHORT_ACCESS 0
2802
2803 /* Define this macro to be the value 1 if unaligned accesses have a
2804 cost many times greater than aligned accesses, for example if they
2805 are emulated in a trap handler.
2806
2807 When this macro is non-zero, the compiler will act as if
2808 `STRICT_ALIGNMENT' were non-zero when generating code for block
2809 moves. This can cause significantly more instructions to be
2810 produced. Therefore, do not set this macro non-zero if unaligned
2811 accesses only add a cycle or two to the time for a memory access.
2812
2813 If the value of this macro is always zero, it need not be defined. */
2814
2815 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2816
2817 /* Define this macro to inhibit strength reduction of memory
2818 addresses. (On some machines, such strength reduction seems to do
2819 harm rather than good.) */
2820
2821 /* #define DONT_REDUCE_ADDR */
2822
2823 /* Define this macro if it is as good or better to call a constant
2824 function address than to call an address kept in a register.
2825
2826 Desirable on the 386 because a CALL with a constant address is
2827 faster than one with a register address. */
2828
2829 #define NO_FUNCTION_CSE
2830
2831 /* Define this macro if it is as good or better for a function to call
2832 itself with an explicit address than to call an address kept in a
2833 register. */
2834
2835 #define NO_RECURSIVE_FUNCTION_CSE
2836 \f
2837 /* Add any extra modes needed to represent the condition code.
2838
2839 For the i386, we need separate modes when floating-point
2840 equality comparisons are being done.
2841
2842 Add CCNO to indicate comparisons against zero that requires
2843 Overflow flag to be unset. Sign bit test is used instead and
2844 thus can be used to form "a&b>0" type of tests.
2845
2846 Add CCGC to indicate comparisons agains zero that allows
2847 unspecified garbage in the Carry flag. This mode is used
2848 by inc/dec instructions.
2849
2850 Add CCGOC to indicate comparisons agains zero that allows
2851 unspecified garbage in the Carry and Overflow flag. This
2852 mode is used to simulate comparisons of (a-b) and (a+b)
2853 against zero using sub/cmp/add operations.
2854
2855 Add CCZ to indicate that only the Zero flag is valid. */
2856
2857 #define EXTRA_CC_MODES \
2858 CC (CCGCmode, "CCGC") \
2859 CC (CCGOCmode, "CCGOC") \
2860 CC (CCNOmode, "CCNO") \
2861 CC (CCZmode, "CCZ") \
2862 CC (CCFPmode, "CCFP") \
2863 CC (CCFPUmode, "CCFPU")
2864
2865 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2866 return the mode to be used for the comparison.
2867
2868 For floating-point equality comparisons, CCFPEQmode should be used.
2869 VOIDmode should be used in all other cases.
2870
2871 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2872 possible, to allow for more combinations. */
2873
2874 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2875
2876 /* Return non-zero if MODE implies a floating point inequality can be
2877 reversed. */
2878
2879 #define REVERSIBLE_CC_MODE(MODE) 1
2880
2881 /* A C expression whose value is reversed condition code of the CODE for
2882 comparison done in CC_MODE mode. */
2883 #define REVERSE_CONDITION(CODE, MODE) \
2884 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
2885 : reverse_condition_maybe_unordered (CODE))
2886
2887 \f
2888 /* Control the assembler format that we output, to the extent
2889 this does not vary between assemblers. */
2890
2891 /* How to refer to registers in assembler output.
2892 This sequence is indexed by compiler's hard-register-number (see above). */
2893
2894 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2895 For non floating point regs, the following are the HImode names.
2896
2897 For float regs, the stack top is sometimes referred to as "%st(0)"
2898 instead of just "%st". PRINT_REG handles this with the "y" code. */
2899
2900 #undef HI_REGISTER_NAMES
2901 #define HI_REGISTER_NAMES \
2902 {"ax","dx","cx","bx","si","di","bp","sp", \
2903 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2904 "flags","fpsr", "dirflag", "frame", \
2905 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2906 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2907 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2908 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2909
2910 #define REGISTER_NAMES HI_REGISTER_NAMES
2911
2912 /* Table of additional register names to use in user input. */
2913
2914 #define ADDITIONAL_REGISTER_NAMES \
2915 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2916 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2917 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2918 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2919 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2920 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2921 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2922 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2923
2924 /* Note we are omitting these since currently I don't know how
2925 to get gcc to use these, since they want the same but different
2926 number as al, and ax.
2927 */
2928
2929 #define QI_REGISTER_NAMES \
2930 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2931
2932 /* These parallel the array above, and can be used to access bits 8:15
2933 of regs 0 through 3. */
2934
2935 #define QI_HIGH_REGISTER_NAMES \
2936 {"ah", "dh", "ch", "bh", }
2937
2938 /* How to renumber registers for dbx and gdb. */
2939
2940 #define DBX_REGISTER_NUMBER(N) \
2941 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2942
2943 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2944 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2945 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2946
2947 /* Before the prologue, RA is at 0(%esp). */
2948 #define INCOMING_RETURN_ADDR_RTX \
2949 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2950
2951 /* After the prologue, RA is at -4(AP) in the current frame. */
2952 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2953 ((COUNT) == 0 \
2954 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2955 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2956
2957 /* PC is dbx register 8; let's use that column for RA. */
2958 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2959
2960 /* Before the prologue, the top of the frame is at 4(%esp). */
2961 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2962
2963 /* Describe how we implement __builtin_eh_return. */
2964 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2965 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2966
2967
2968 /* Select a format to encode pointers in exception handling data. CODE
2969 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2970 true if the symbol may be affected by dynamic relocations.
2971
2972 ??? All x86 object file formats are capable of representing this.
2973 After all, the relocation needed is the same as for the call insn.
2974 Whether or not a particular assembler allows us to enter such, I
2975 guess we'll have to see. */
2976 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2977 (flag_pic \
2978 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
2979 : DW_EH_PE_absptr)
2980
2981 /* This is how to output the definition of a user-level label named NAME,
2982 such as the label on a static function or variable NAME. */
2983
2984 #define ASM_OUTPUT_LABEL(FILE, NAME) \
2985 (assemble_name ((FILE), (NAME)), fputs (":\n", (FILE)))
2986
2987 /* Store in OUTPUT a string (made with alloca) containing
2988 an assembler-name for a local static variable named NAME.
2989 LABELNO is an integer which is different for each call. */
2990
2991 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2992 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2993 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2994
2995 /* This is how to output an insn to push a register on the stack.
2996 It need not be very fast code. */
2997
2998 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2999 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)])
3000
3001 /* This is how to output an insn to pop a register from the stack.
3002 It need not be very fast code. */
3003
3004 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
3005 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)])
3006
3007 /* This is how to output an element of a case-vector that is absolute. */
3008
3009 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
3010 ix86_output_addr_vec_elt ((FILE), (VALUE))
3011
3012 /* This is how to output an element of a case-vector that is relative. */
3013
3014 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
3015 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
3016
3017 /* Under some conditions we need jump tables in the text section, because
3018 the assembler cannot handle label differences between sections. */
3019
3020 #define JUMP_TABLES_IN_TEXT_SECTION \
3021 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
3022
3023 /* A C statement that outputs an address constant appropriate to
3024 for DWARF debugging. */
3025
3026 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \
3027 i386_dwarf_output_addr_const ((FILE), (X))
3028
3029 /* Either simplify a location expression, or return the original. */
3030
3031 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
3032 i386_simplify_dwarf_addr (X)
3033
3034 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
3035 and switch back. For x86 we do this only to save a few bytes that
3036 would otherwise be unused in the text section. */
3037 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3038 asm (SECTION_OP "\n\t" \
3039 "call " USER_LABEL_PREFIX #FUNC "\n" \
3040 TEXT_SECTION_ASM_OP);
3041 \f
3042 /* Print operand X (an rtx) in assembler syntax to file FILE.
3043 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3044 Effect of various CODE letters is described in i386.c near
3045 print_operand function. */
3046
3047 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
3048 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
3049
3050 /* Print the name of a register based on its machine mode and number.
3051 If CODE is 'w', pretend the mode is HImode.
3052 If CODE is 'b', pretend the mode is QImode.
3053 If CODE is 'k', pretend the mode is SImode.
3054 If CODE is 'q', pretend the mode is DImode.
3055 If CODE is 'h', pretend the reg is the `high' byte register.
3056 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
3057
3058 #define PRINT_REG(X, CODE, FILE) \
3059 print_reg ((X), (CODE), (FILE))
3060
3061 #define PRINT_OPERAND(FILE, X, CODE) \
3062 print_operand ((FILE), (X), (CODE))
3063
3064 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
3065 print_operand_address ((FILE), (ADDR))
3066
3067 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
3068 do { \
3069 if (! output_addr_const_extra (FILE, (X))) \
3070 goto FAIL; \
3071 } while (0);
3072
3073 /* Print the name of a register for based on its machine mode and number.
3074 This macro is used to print debugging output.
3075 This macro is different from PRINT_REG in that it may be used in
3076 programs that are not linked with aux-output.o. */
3077
3078 #define DEBUG_PRINT_REG(X, CODE, FILE) \
3079 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
3080 static const char * const qi_name[] = QI_REGISTER_NAMES; \
3081 fprintf ((FILE), "%d ", REGNO (X)); \
3082 if (REGNO (X) == FLAGS_REG) \
3083 { fputs ("flags", (FILE)); break; } \
3084 if (REGNO (X) == DIRFLAG_REG) \
3085 { fputs ("dirflag", (FILE)); break; } \
3086 if (REGNO (X) == FPSR_REG) \
3087 { fputs ("fpsr", (FILE)); break; } \
3088 if (REGNO (X) == ARG_POINTER_REGNUM) \
3089 { fputs ("argp", (FILE)); break; } \
3090 if (REGNO (X) == FRAME_POINTER_REGNUM) \
3091 { fputs ("frame", (FILE)); break; } \
3092 if (STACK_TOP_P (X)) \
3093 { fputs ("st(0)", (FILE)); break; } \
3094 if (FP_REG_P (X)) \
3095 { fputs (hi_name[REGNO(X)], (FILE)); break; } \
3096 if (REX_INT_REG_P (X)) \
3097 { \
3098 switch (GET_MODE_SIZE (GET_MODE (X))) \
3099 { \
3100 default: \
3101 case 8: \
3102 fprintf ((FILE), "r%i", REGNO (X) \
3103 - FIRST_REX_INT_REG + 8); \
3104 break; \
3105 case 4: \
3106 fprintf ((FILE), "r%id", REGNO (X) \
3107 - FIRST_REX_INT_REG + 8); \
3108 break; \
3109 case 2: \
3110 fprintf ((FILE), "r%iw", REGNO (X) \
3111 - FIRST_REX_INT_REG + 8); \
3112 break; \
3113 case 1: \
3114 fprintf ((FILE), "r%ib", REGNO (X) \
3115 - FIRST_REX_INT_REG + 8); \
3116 break; \
3117 } \
3118 break; \
3119 } \
3120 switch (GET_MODE_SIZE (GET_MODE (X))) \
3121 { \
3122 case 8: \
3123 fputs ("r", (FILE)); \
3124 fputs (hi_name[REGNO (X)], (FILE)); \
3125 break; \
3126 default: \
3127 fputs ("e", (FILE)); \
3128 case 2: \
3129 fputs (hi_name[REGNO (X)], (FILE)); \
3130 break; \
3131 case 1: \
3132 fputs (qi_name[REGNO (X)], (FILE)); \
3133 break; \
3134 } \
3135 } while (0)
3136
3137 /* a letter which is not needed by the normal asm syntax, which
3138 we can use for operand syntax in the extended asm */
3139
3140 #define ASM_OPERAND_LETTER '#'
3141 #define RET return ""
3142 #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
3143 \f
3144 /* Define the codes that are matched by predicates in i386.c. */
3145
3146 #define PREDICATE_CODES \
3147 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
3148 SYMBOL_REF, LABEL_REF, CONST}}, \
3149 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3150 SYMBOL_REF, LABEL_REF, CONST}}, \
3151 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
3152 SYMBOL_REF, LABEL_REF, CONST}}, \
3153 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3154 SYMBOL_REF, LABEL_REF, CONST}}, \
3155 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3156 SYMBOL_REF, LABEL_REF, CONST}}, \
3157 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3158 SYMBOL_REF, LABEL_REF, CONST}}, \
3159 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3160 SYMBOL_REF, LABEL_REF}}, \
3161 {"shiftdi_operand", {SUBREG, REG, MEM}}, \
3162 {"const_int_1_operand", {CONST_INT}}, \
3163 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3164 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3165 LABEL_REF, SUBREG, REG, MEM}}, \
3166 {"pic_symbolic_operand", {CONST}}, \
3167 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
3168 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
3169 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
3170 {"const1_operand", {CONST_INT}}, \
3171 {"const248_operand", {CONST_INT}}, \
3172 {"incdec_operand", {CONST_INT}}, \
3173 {"mmx_reg_operand", {REG}}, \
3174 {"reg_no_sp_operand", {SUBREG, REG}}, \
3175 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3176 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
3177 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
3178 {"q_regs_operand", {SUBREG, REG}}, \
3179 {"non_q_regs_operand", {SUBREG, REG}}, \
3180 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
3181 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
3182 GE, UNGE, LTGT, UNEQ}}, \
3183 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
3184 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
3185 }}, \
3186 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
3187 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
3188 UNGE, UNGT, LTGT, UNEQ }}, \
3189 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
3190 {"ext_register_operand", {SUBREG, REG}}, \
3191 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
3192 {"mult_operator", {MULT}}, \
3193 {"div_operator", {DIV}}, \
3194 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
3195 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
3196 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
3197 LSHIFTRT, ROTATERT}}, \
3198 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
3199 {"memory_displacement_operand", {MEM}}, \
3200 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3201 LABEL_REF, SUBREG, REG, MEM, AND}}, \
3202 {"long_memory_operand", {MEM}}, \
3203 {"tls_symbolic_operand", {SYMBOL_REF}}, \
3204 {"global_dynamic_symbolic_operand", {SYMBOL_REF}}, \
3205 {"local_dynamic_symbolic_operand", {SYMBOL_REF}}, \
3206 {"initial_exec_symbolic_operand", {SYMBOL_REF}}, \
3207 {"local_exec_symbolic_operand", {SYMBOL_REF}},
3208
3209 /* A list of predicates that do special things with modes, and so
3210 should not elicit warnings for VOIDmode match_operand. */
3211
3212 #define SPECIAL_MODE_PREDICATES \
3213 "ext_register_operand",
3214 \f
3215 /* Which processor to schedule for. The cpu attribute defines a list that
3216 mirrors this list, so changes to i386.md must be made at the same time. */
3217
3218 enum processor_type
3219 {
3220 PROCESSOR_I386, /* 80386 */
3221 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
3222 PROCESSOR_PENTIUM,
3223 PROCESSOR_PENTIUMPRO,
3224 PROCESSOR_K6,
3225 PROCESSOR_ATHLON,
3226 PROCESSOR_PENTIUM4,
3227 PROCESSOR_max
3228 };
3229
3230 extern enum processor_type ix86_cpu;
3231 extern const char *ix86_cpu_string;
3232
3233 extern enum processor_type ix86_arch;
3234 extern const char *ix86_arch_string;
3235
3236 enum fpmath_unit
3237 {
3238 FPMATH_387 = 1,
3239 FPMATH_SSE = 2
3240 };
3241
3242 extern enum fpmath_unit ix86_fpmath;
3243 extern const char *ix86_fpmath_string;
3244
3245 enum tls_dialect
3246 {
3247 TLS_DIALECT_GNU,
3248 TLS_DIALECT_SUN
3249 };
3250
3251 extern enum tls_dialect ix86_tls_dialect;
3252 extern const char *ix86_tls_dialect_string;
3253
3254 enum cmodel {
3255 CM_32, /* The traditional 32-bit ABI. */
3256 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
3257 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
3258 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
3259 CM_LARGE, /* No assumptions. */
3260 CM_SMALL_PIC /* Assumes code+data+got/plt fits in a 31 bit region. */
3261 };
3262
3263 extern enum cmodel ix86_cmodel;
3264 extern const char *ix86_cmodel_string;
3265
3266 /* Size of the RED_ZONE area. */
3267 #define RED_ZONE_SIZE 128
3268 /* Reserved area of the red zone for temporaries. */
3269 #define RED_ZONE_RESERVE 8
3270
3271 enum asm_dialect {
3272 ASM_ATT,
3273 ASM_INTEL
3274 };
3275
3276 extern const char *ix86_asm_string;
3277 extern enum asm_dialect ix86_asm_dialect;
3278
3279 extern int ix86_regparm;
3280 extern const char *ix86_regparm_string;
3281
3282 extern int ix86_preferred_stack_boundary;
3283 extern const char *ix86_preferred_stack_boundary_string;
3284
3285 extern int ix86_branch_cost;
3286 extern const char *ix86_branch_cost_string;
3287
3288 extern const char *ix86_debug_arg_string;
3289 extern const char *ix86_debug_addr_string;
3290
3291 /* Obsoleted by -f options. Remove before 3.2 ships. */
3292 extern const char *ix86_align_loops_string;
3293 extern const char *ix86_align_jumps_string;
3294 extern const char *ix86_align_funcs_string;
3295
3296 /* Smallest class containing REGNO. */
3297 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
3298
3299 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
3300 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
3301 \f
3302 /* To properly truncate FP values into integers, we need to set i387 control
3303 word. We can't emit proper mode switching code before reload, as spills
3304 generated by reload may truncate values incorrectly, but we still can avoid
3305 redundant computation of new control word by the mode switching pass.
3306 The fldcw instructions are still emitted redundantly, but this is probably
3307 not going to be noticeable problem, as most CPUs do have fast path for
3308 the sequence.
3309
3310 The machinery is to emit simple truncation instructions and split them
3311 before reload to instructions having USEs of two memory locations that
3312 are filled by this code to old and new control word.
3313
3314 Post-reload pass may be later used to eliminate the redundant fildcw if
3315 needed. */
3316
3317 enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY};
3318
3319 /* Define this macro if the port needs extra instructions inserted
3320 for mode switching in an optimizing compilation. */
3321
3322 #define OPTIMIZE_MODE_SWITCHING(ENTITY) 1
3323
3324 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
3325 initializer for an array of integers. Each initializer element N
3326 refers to an entity that needs mode switching, and specifies the
3327 number of different modes that might need to be set for this
3328 entity. The position of the initializer in the initializer -
3329 starting counting at zero - determines the integer that is used to
3330 refer to the mode-switched entity in question. */
3331
3332 #define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY }
3333
3334 /* ENTITY is an integer specifying a mode-switched entity. If
3335 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
3336 return an integer value not larger than the corresponding element
3337 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
3338 must be switched into prior to the execution of INSN. */
3339
3340 #define MODE_NEEDED(ENTITY, I) \
3341 (GET_CODE (I) == CALL_INSN \
3342 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
3343 || GET_CODE (PATTERN (I)) == ASM_INPUT))\
3344 ? FP_CW_UNINITIALIZED \
3345 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \
3346 ? FP_CW_ANY \
3347 : FP_CW_STORED)
3348
3349 /* This macro specifies the order in which modes for ENTITY are
3350 processed. 0 is the highest priority. */
3351
3352 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
3353
3354 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
3355 is the set of hard registers live at the point where the insn(s)
3356 are to be inserted. */
3357
3358 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3359 ((MODE) == FP_CW_STORED \
3360 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
3361 assign_386_stack_local (HImode, 2)), 0\
3362 : 0)
3363 \f
3364 /* Avoid renaming of stack registers, as doing so in combination with
3365 scheduling just increases amount of live registers at time and in
3366 the turn amount of fxch instructions needed.
3367
3368 ??? Maybe Pentium chips benefits from renaming, someone can try... */
3369
3370 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
3371 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
3372
3373 \f
3374 /*
3375 Local variables:
3376 version-control: t
3377 End:
3378 */
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