1 @c Copyright (C) 1988-2014 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
7 @chapter Machine Descriptions
8 @cindex machine descriptions
10 A machine description has two parts: a file of instruction patterns
11 (@file{.md} file) and a C header file of macro definitions.
13 The @file{.md} file for a target machine contains a pattern for each
14 instruction that the target machine supports (or at least each instruction
15 that is worth telling the compiler about). It may also contain comments.
16 A semicolon causes the rest of the line to be a comment, unless the semicolon
17 is inside a quoted string.
19 See the next chapter for information on the C header file.
22 * Overview:: How the machine description is used.
23 * Patterns:: How to write instruction patterns.
24 * Example:: An explained example of a @code{define_insn} pattern.
25 * RTL Template:: The RTL template defines what insns match a pattern.
26 * Output Template:: The output template says how to make assembler code
28 * Output Statement:: For more generality, write C code to output
30 * Predicates:: Controlling what kinds of operands can be used
32 * Constraints:: Fine-tuning operand selection.
33 * Standard Names:: Names mark patterns to use for code generation.
34 * Pattern Ordering:: When the order of patterns makes a difference.
35 * Dependent Patterns:: Having one pattern may make you need another.
36 * Jump Patterns:: Special considerations for patterns for jump insns.
37 * Looping Patterns:: How to define patterns for special looping insns.
38 * Insn Canonicalizations::Canonicalization of Instructions
39 * Expander Definitions::Generating a sequence of several RTL insns
40 for a standard operation.
41 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
42 * Including Patterns:: Including Patterns in Machine Descriptions.
43 * Peephole Definitions::Defining machine-specific peephole optimizations.
44 * Insn Attributes:: Specifying the value of attributes for generated insns.
45 * Conditional Execution::Generating @code{define_insn} patterns for
47 * Define Subst:: Generating @code{define_insn} and @code{define_expand}
48 patterns from other patterns.
49 * Constant Definitions::Defining symbolic constants that can be used in the
51 * Iterators:: Using iterators to generate patterns from a template.
55 @section Overview of How the Machine Description is Used
57 There are three main conversions that happen in the compiler:
62 The front end reads the source code and builds a parse tree.
65 The parse tree is used to generate an RTL insn list based on named
69 The insn list is matched against the RTL templates to produce assembler
74 For the generate pass, only the names of the insns matter, from either a
75 named @code{define_insn} or a @code{define_expand}. The compiler will
76 choose the pattern with the right name and apply the operands according
77 to the documentation later in this chapter, without regard for the RTL
78 template or operand constraints. Note that the names the compiler looks
79 for are hard-coded in the compiler---it will ignore unnamed patterns and
80 patterns with names it doesn't know about, but if you don't provide a
81 named pattern it needs, it will abort.
83 If a @code{define_insn} is used, the template given is inserted into the
84 insn list. If a @code{define_expand} is used, one of three things
85 happens, based on the condition logic. The condition logic may manually
86 create new insns for the insn list, say via @code{emit_insn()}, and
87 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
88 compiler to use an alternate way of performing that task. If it invokes
89 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
90 is inserted, as if the @code{define_expand} were a @code{define_insn}.
92 Once the insn list is generated, various optimization passes convert,
93 replace, and rearrange the insns in the insn list. This is where the
94 @code{define_split} and @code{define_peephole} patterns get used, for
97 Finally, the insn list's RTL is matched up with the RTL templates in the
98 @code{define_insn} patterns, and those patterns are used to emit the
99 final assembly code. For this purpose, each named @code{define_insn}
100 acts like it's unnamed, since the names are ignored.
103 @section Everything about Instruction Patterns
105 @cindex instruction patterns
108 Each instruction pattern contains an incomplete RTL expression, with pieces
109 to be filled in later, operand constraints that restrict how the pieces can
110 be filled in, and an output pattern or C code to generate the assembler
111 output, all wrapped up in a @code{define_insn} expression.
113 A @code{define_insn} is an RTL expression containing four or five operands:
117 An optional name. The presence of a name indicate that this instruction
118 pattern can perform a certain standard job for the RTL-generation
119 pass of the compiler. This pass knows certain names and will use
120 the instruction patterns with those names, if the names are defined
121 in the machine description.
123 The absence of a name is indicated by writing an empty string
124 where the name should go. Nameless instruction patterns are never
125 used for generating RTL code, but they may permit several simpler insns
126 to be combined later on.
128 Names that are not thus known and used in RTL-generation have no
129 effect; they are equivalent to no name at all.
131 For the purpose of debugging the compiler, you may also specify a
132 name beginning with the @samp{*} character. Such a name is used only
133 for identifying the instruction in RTL dumps; it is entirely equivalent
134 to having a nameless pattern for all other purposes.
137 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
138 RTL expressions which show what the instruction should look like. It is
139 incomplete because it may contain @code{match_operand},
140 @code{match_operator}, and @code{match_dup} expressions that stand for
141 operands of the instruction.
143 If the vector has only one element, that element is the template for the
144 instruction pattern. If the vector has multiple elements, then the
145 instruction pattern is a @code{parallel} expression containing the
149 @cindex pattern conditions
150 @cindex conditions, in patterns
151 A condition. This is a string which contains a C expression that is
152 the final test to decide whether an insn body matches this pattern.
154 @cindex named patterns and conditions
155 For a named pattern, the condition (if present) may not depend on
156 the data in the insn being matched, but only the target-machine-type
157 flags. The compiler needs to test these conditions during
158 initialization in order to learn exactly which named instructions are
159 available in a particular run.
162 For nameless patterns, the condition is applied only when matching an
163 individual insn, and only after the insn has matched the pattern's
164 recognition template. The insn's operands may be found in the vector
165 @code{operands}. For an insn where the condition has once matched, it
166 can't be used to control register allocation, for example by excluding
167 certain hard registers or hard register combinations.
170 The @dfn{output template}: a string that says how to output matching
171 insns as assembler code. @samp{%} in this string specifies where
172 to substitute the value of an operand. @xref{Output Template}.
174 When simple substitution isn't general enough, you can specify a piece
175 of C code to compute the output. @xref{Output Statement}.
178 Optionally, a vector containing the values of attributes for insns matching
179 this pattern. @xref{Insn Attributes}.
183 @section Example of @code{define_insn}
184 @cindex @code{define_insn} example
186 Here is an actual example of an instruction pattern, for the 68000/68020.
191 (match_operand:SI 0 "general_operand" "rm"))]
195 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
197 return \"cmpl #0,%0\";
202 This can also be written using braced strings:
207 (match_operand:SI 0 "general_operand" "rm"))]
210 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
216 This is an instruction that sets the condition codes based on the value of
217 a general operand. It has no condition, so any insn whose RTL description
218 has the form shown may be handled according to this pattern. The name
219 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
220 pass that, when it is necessary to test such a value, an insn to do so
221 can be constructed using this pattern.
223 The output control string is a piece of C code which chooses which
224 output template to return based on the kind of operand and the specific
225 type of CPU for which code is being generated.
227 @samp{"rm"} is an operand constraint. Its meaning is explained below.
230 @section RTL Template
231 @cindex RTL insn template
232 @cindex generating insns
233 @cindex insns, generating
234 @cindex recognizing insns
235 @cindex insns, recognizing
237 The RTL template is used to define which insns match the particular pattern
238 and how to find their operands. For named patterns, the RTL template also
239 says how to construct an insn from specified operands.
241 Construction involves substituting specified operands into a copy of the
242 template. Matching involves determining the values that serve as the
243 operands in the insn being matched. Both of these activities are
244 controlled by special expression types that direct matching and
245 substitution of the operands.
248 @findex match_operand
249 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
250 This expression is a placeholder for operand number @var{n} of
251 the insn. When constructing an insn, operand number @var{n}
252 will be substituted at this point. When matching an insn, whatever
253 appears at this position in the insn will be taken as operand
254 number @var{n}; but it must satisfy @var{predicate} or this instruction
255 pattern will not match at all.
257 Operand numbers must be chosen consecutively counting from zero in
258 each instruction pattern. There may be only one @code{match_operand}
259 expression in the pattern for each operand number. Usually operands
260 are numbered in the order of appearance in @code{match_operand}
261 expressions. In the case of a @code{define_expand}, any operand numbers
262 used only in @code{match_dup} expressions have higher values than all
263 other operand numbers.
265 @var{predicate} is a string that is the name of a function that
266 accepts two arguments, an expression and a machine mode.
267 @xref{Predicates}. During matching, the function will be called with
268 the putative operand as the expression and @var{m} as the mode
269 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
270 which normally causes @var{predicate} to accept any mode). If it
271 returns zero, this instruction pattern fails to match.
272 @var{predicate} may be an empty string; then it means no test is to be
273 done on the operand, so anything which occurs in this position is
276 Most of the time, @var{predicate} will reject modes other than @var{m}---but
277 not always. For example, the predicate @code{address_operand} uses
278 @var{m} as the mode of memory ref that the address should be valid for.
279 Many predicates accept @code{const_int} nodes even though their mode is
282 @var{constraint} controls reloading and the choice of the best register
283 class to use for a value, as explained later (@pxref{Constraints}).
284 If the constraint would be an empty string, it can be omitted.
286 People are often unclear on the difference between the constraint and the
287 predicate. The predicate helps decide whether a given insn matches the
288 pattern. The constraint plays no role in this decision; instead, it
289 controls various decisions in the case of an insn which does match.
291 @findex match_scratch
292 @item (match_scratch:@var{m} @var{n} @var{constraint})
293 This expression is also a placeholder for operand number @var{n}
294 and indicates that operand must be a @code{scratch} or @code{reg}
297 When matching patterns, this is equivalent to
300 (match_operand:@var{m} @var{n} "scratch_operand" @var{constraint})
303 but, when generating RTL, it produces a (@code{scratch}:@var{m})
306 If the last few expressions in a @code{parallel} are @code{clobber}
307 expressions whose operands are either a hard register or
308 @code{match_scratch}, the combiner can add or delete them when
309 necessary. @xref{Side Effects}.
312 @item (match_dup @var{n})
313 This expression is also a placeholder for operand number @var{n}.
314 It is used when the operand needs to appear more than once in the
317 In construction, @code{match_dup} acts just like @code{match_operand}:
318 the operand is substituted into the insn being constructed. But in
319 matching, @code{match_dup} behaves differently. It assumes that operand
320 number @var{n} has already been determined by a @code{match_operand}
321 appearing earlier in the recognition template, and it matches only an
322 identical-looking expression.
324 Note that @code{match_dup} should not be used to tell the compiler that
325 a particular register is being used for two operands (example:
326 @code{add} that adds one register to another; the second register is
327 both an input operand and the output operand). Use a matching
328 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
329 operand is used in two places in the template, such as an instruction
330 that computes both a quotient and a remainder, where the opcode takes
331 two input operands but the RTL template has to refer to each of those
332 twice; once for the quotient pattern and once for the remainder pattern.
334 @findex match_operator
335 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
336 This pattern is a kind of placeholder for a variable RTL expression
339 When constructing an insn, it stands for an RTL expression whose
340 expression code is taken from that of operand @var{n}, and whose
341 operands are constructed from the patterns @var{operands}.
343 When matching an expression, it matches an expression if the function
344 @var{predicate} returns nonzero on that expression @emph{and} the
345 patterns @var{operands} match the operands of the expression.
347 Suppose that the function @code{commutative_operator} is defined as
348 follows, to match any expression whose operator is one of the
349 commutative arithmetic operators of RTL and whose mode is @var{mode}:
353 commutative_integer_operator (x, mode)
357 enum rtx_code code = GET_CODE (x);
358 if (GET_MODE (x) != mode)
360 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
361 || code == EQ || code == NE);
365 Then the following pattern will match any RTL expression consisting
366 of a commutative operator applied to two general operands:
369 (match_operator:SI 3 "commutative_operator"
370 [(match_operand:SI 1 "general_operand" "g")
371 (match_operand:SI 2 "general_operand" "g")])
374 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
375 because the expressions to be matched all contain two operands.
377 When this pattern does match, the two operands of the commutative
378 operator are recorded as operands 1 and 2 of the insn. (This is done
379 by the two instances of @code{match_operand}.) Operand 3 of the insn
380 will be the entire commutative expression: use @code{GET_CODE
381 (operands[3])} to see which commutative operator was used.
383 The machine mode @var{m} of @code{match_operator} works like that of
384 @code{match_operand}: it is passed as the second argument to the
385 predicate function, and that function is solely responsible for
386 deciding whether the expression to be matched ``has'' that mode.
388 When constructing an insn, argument 3 of the gen-function will specify
389 the operation (i.e.@: the expression code) for the expression to be
390 made. It should be an RTL expression, whose expression code is copied
391 into a new expression whose operands are arguments 1 and 2 of the
392 gen-function. The subexpressions of argument 3 are not used;
393 only its expression code matters.
395 When @code{match_operator} is used in a pattern for matching an insn,
396 it usually best if the operand number of the @code{match_operator}
397 is higher than that of the actual operands of the insn. This improves
398 register allocation because the register allocator often looks at
399 operands 1 and 2 of insns to see if it can do register tying.
401 There is no way to specify constraints in @code{match_operator}. The
402 operand of the insn which corresponds to the @code{match_operator}
403 never has any constraints because it is never reloaded as a whole.
404 However, if parts of its @var{operands} are matched by
405 @code{match_operand} patterns, those parts may have constraints of
409 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
410 Like @code{match_dup}, except that it applies to operators instead of
411 operands. When constructing an insn, operand number @var{n} will be
412 substituted at this point. But in matching, @code{match_op_dup} behaves
413 differently. It assumes that operand number @var{n} has already been
414 determined by a @code{match_operator} appearing earlier in the
415 recognition template, and it matches only an identical-looking
418 @findex match_parallel
419 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
420 This pattern is a placeholder for an insn that consists of a
421 @code{parallel} expression with a variable number of elements. This
422 expression should only appear at the top level of an insn pattern.
424 When constructing an insn, operand number @var{n} will be substituted at
425 this point. When matching an insn, it matches if the body of the insn
426 is a @code{parallel} expression with at least as many elements as the
427 vector of @var{subpat} expressions in the @code{match_parallel}, if each
428 @var{subpat} matches the corresponding element of the @code{parallel},
429 @emph{and} the function @var{predicate} returns nonzero on the
430 @code{parallel} that is the body of the insn. It is the responsibility
431 of the predicate to validate elements of the @code{parallel} beyond
432 those listed in the @code{match_parallel}.
434 A typical use of @code{match_parallel} is to match load and store
435 multiple expressions, which can contain a variable number of elements
436 in a @code{parallel}. For example,
440 [(match_parallel 0 "load_multiple_operation"
441 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
442 (match_operand:SI 2 "memory_operand" "m"))
444 (clobber (reg:SI 179))])]
449 This example comes from @file{a29k.md}. The function
450 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
451 that subsequent elements in the @code{parallel} are the same as the
452 @code{set} in the pattern, except that they are referencing subsequent
453 registers and memory locations.
455 An insn that matches this pattern might look like:
459 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
461 (clobber (reg:SI 179))
463 (mem:SI (plus:SI (reg:SI 100)
466 (mem:SI (plus:SI (reg:SI 100)
470 @findex match_par_dup
471 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
472 Like @code{match_op_dup}, but for @code{match_parallel} instead of
473 @code{match_operator}.
477 @node Output Template
478 @section Output Templates and Operand Substitution
479 @cindex output templates
480 @cindex operand substitution
482 @cindex @samp{%} in template
484 The @dfn{output template} is a string which specifies how to output the
485 assembler code for an instruction pattern. Most of the template is a
486 fixed string which is output literally. The character @samp{%} is used
487 to specify where to substitute an operand; it can also be used to
488 identify places where different variants of the assembler require
491 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
492 operand @var{n} at that point in the string.
494 @samp{%} followed by a letter and a digit says to output an operand in an
495 alternate fashion. Four letters have standard, built-in meanings described
496 below. The machine description macro @code{PRINT_OPERAND} can define
497 additional letters with nonstandard meanings.
499 @samp{%c@var{digit}} can be used to substitute an operand that is a
500 constant value without the syntax that normally indicates an immediate
503 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
504 the constant is negated before printing.
506 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
507 memory reference, with the actual operand treated as the address. This may
508 be useful when outputting a ``load address'' instruction, because often the
509 assembler syntax for such an instruction requires you to write the operand
510 as if it were a memory reference.
512 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
515 @samp{%=} outputs a number which is unique to each instruction in the
516 entire compilation. This is useful for making local labels to be
517 referred to more than once in a single template that generates multiple
518 assembler instructions.
520 @samp{%} followed by a punctuation character specifies a substitution that
521 does not use an operand. Only one case is standard: @samp{%%} outputs a
522 @samp{%} into the assembler code. Other nonstandard cases can be
523 defined in the @code{PRINT_OPERAND} macro. You must also define
524 which punctuation characters are valid with the
525 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
529 The template may generate multiple assembler instructions. Write the text
530 for the instructions, with @samp{\;} between them.
532 @cindex matching operands
533 When the RTL contains two operands which are required by constraint to match
534 each other, the output template must refer only to the lower-numbered operand.
535 Matching operands are not always identical, and the rest of the compiler
536 arranges to put the proper RTL expression for printing into the lower-numbered
539 One use of nonstandard letters or punctuation following @samp{%} is to
540 distinguish between different assembler languages for the same machine; for
541 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
542 requires periods in most opcode names, while MIT syntax does not. For
543 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
544 syntax. The same file of patterns is used for both kinds of output syntax,
545 but the character sequence @samp{%.} is used in each place where Motorola
546 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
547 defines the sequence to output a period; the macro for MIT syntax defines
550 @cindex @code{#} in template
551 As a special case, a template consisting of the single character @code{#}
552 instructs the compiler to first split the insn, and then output the
553 resulting instructions separately. This helps eliminate redundancy in the
554 output templates. If you have a @code{define_insn} that needs to emit
555 multiple assembler instructions, and there is a matching @code{define_split}
556 already defined, then you can simply use @code{#} as the output template
557 instead of writing an output template that emits the multiple assembler
560 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
561 of the form @samp{@{option0|option1|option2@}} in the templates. These
562 describe multiple variants of assembler language syntax.
563 @xref{Instruction Output}.
565 @node Output Statement
566 @section C Statements for Assembler Output
567 @cindex output statements
568 @cindex C statements for assembler output
569 @cindex generating assembler output
571 Often a single fixed template string cannot produce correct and efficient
572 assembler code for all the cases that are recognized by a single
573 instruction pattern. For example, the opcodes may depend on the kinds of
574 operands; or some unfortunate combinations of operands may require extra
575 machine instructions.
577 If the output control string starts with a @samp{@@}, then it is actually
578 a series of templates, each on a separate line. (Blank lines and
579 leading spaces and tabs are ignored.) The templates correspond to the
580 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
581 if a target machine has a two-address add instruction @samp{addr} to add
582 into a register and another @samp{addm} to add a register to memory, you
583 might write this pattern:
586 (define_insn "addsi3"
587 [(set (match_operand:SI 0 "general_operand" "=r,m")
588 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
589 (match_operand:SI 2 "general_operand" "g,r")))]
596 @cindex @code{*} in template
597 @cindex asterisk in template
598 If the output control string starts with a @samp{*}, then it is not an
599 output template but rather a piece of C program that should compute a
600 template. It should execute a @code{return} statement to return the
601 template-string you want. Most such templates use C string literals, which
602 require doublequote characters to delimit them. To include these
603 doublequote characters in the string, prefix each one with @samp{\}.
605 If the output control string is written as a brace block instead of a
606 double-quoted string, it is automatically assumed to be C code. In that
607 case, it is not necessary to put in a leading asterisk, or to escape the
608 doublequotes surrounding C string literals.
610 The operands may be found in the array @code{operands}, whose C data type
613 It is very common to select different ways of generating assembler code
614 based on whether an immediate operand is within a certain range. Be
615 careful when doing this, because the result of @code{INTVAL} is an
616 integer on the host machine. If the host machine has more bits in an
617 @code{int} than the target machine has in the mode in which the constant
618 will be used, then some of the bits you get from @code{INTVAL} will be
619 superfluous. For proper results, you must carefully disregard the
620 values of those bits.
622 @findex output_asm_insn
623 It is possible to output an assembler instruction and then go on to output
624 or compute more of them, using the subroutine @code{output_asm_insn}. This
625 receives two arguments: a template-string and a vector of operands. The
626 vector may be @code{operands}, or it may be another array of @code{rtx}
627 that you declare locally and initialize yourself.
629 @findex which_alternative
630 When an insn pattern has multiple alternatives in its constraints, often
631 the appearance of the assembler code is determined mostly by which alternative
632 was matched. When this is so, the C code can test the variable
633 @code{which_alternative}, which is the ordinal number of the alternative
634 that was actually satisfied (0 for the first, 1 for the second alternative,
637 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
638 for registers and @samp{clrmem} for memory locations. Here is how
639 a pattern could use @code{which_alternative} to choose between them:
643 [(set (match_operand:SI 0 "general_operand" "=r,m")
647 return (which_alternative == 0
648 ? "clrreg %0" : "clrmem %0");
652 The example above, where the assembler code to generate was
653 @emph{solely} determined by the alternative, could also have been specified
654 as follows, having the output control string start with a @samp{@@}:
659 [(set (match_operand:SI 0 "general_operand" "=r,m")
668 If you just need a little bit of C code in one (or a few) alternatives,
669 you can use @samp{*} inside of a @samp{@@} multi-alternative template:
674 [(set (match_operand:SI 0 "general_operand" "=r,<,m")
679 * return stack_mem_p (operands[0]) ? \"push 0\" : \"clrmem %0\";
687 @cindex operand predicates
688 @cindex operator predicates
690 A predicate determines whether a @code{match_operand} or
691 @code{match_operator} expression matches, and therefore whether the
692 surrounding instruction pattern will be used for that combination of
693 operands. GCC has a number of machine-independent predicates, and you
694 can define machine-specific predicates as needed. By convention,
695 predicates used with @code{match_operand} have names that end in
696 @samp{_operand}, and those used with @code{match_operator} have names
697 that end in @samp{_operator}.
699 All predicates are Boolean functions (in the mathematical sense) of
700 two arguments: the RTL expression that is being considered at that
701 position in the instruction pattern, and the machine mode that the
702 @code{match_operand} or @code{match_operator} specifies. In this
703 section, the first argument is called @var{op} and the second argument
704 @var{mode}. Predicates can be called from C as ordinary two-argument
705 functions; this can be useful in output templates or other
706 machine-specific code.
708 Operand predicates can allow operands that are not actually acceptable
709 to the hardware, as long as the constraints give reload the ability to
710 fix them up (@pxref{Constraints}). However, GCC will usually generate
711 better code if the predicates specify the requirements of the machine
712 instructions as closely as possible. Reload cannot fix up operands
713 that must be constants (``immediate operands''); you must use a
714 predicate that allows only constants, or else enforce the requirement
715 in the extra condition.
717 @cindex predicates and machine modes
718 @cindex normal predicates
719 @cindex special predicates
720 Most predicates handle their @var{mode} argument in a uniform manner.
721 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
722 any mode. If @var{mode} is anything else, then @var{op} must have the
723 same mode, unless @var{op} is a @code{CONST_INT} or integer
724 @code{CONST_DOUBLE}. These RTL expressions always have
725 @code{VOIDmode}, so it would be counterproductive to check that their
726 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
727 integer @code{CONST_DOUBLE} check that the value stored in the
728 constant will fit in the requested mode.
730 Predicates with this behavior are called @dfn{normal}.
731 @command{genrecog} can optimize the instruction recognizer based on
732 knowledge of how normal predicates treat modes. It can also diagnose
733 certain kinds of common errors in the use of normal predicates; for
734 instance, it is almost always an error to use a normal predicate
735 without specifying a mode.
737 Predicates that do something different with their @var{mode} argument
738 are called @dfn{special}. The generic predicates
739 @code{address_operand} and @code{pmode_register_operand} are special
740 predicates. @command{genrecog} does not do any optimizations or
741 diagnosis when special predicates are used.
744 * Machine-Independent Predicates:: Predicates available to all back ends.
745 * Defining Predicates:: How to write machine-specific predicate
749 @node Machine-Independent Predicates
750 @subsection Machine-Independent Predicates
751 @cindex machine-independent predicates
752 @cindex generic predicates
754 These are the generic predicates available to all back ends. They are
755 defined in @file{recog.c}. The first category of predicates allow
756 only constant, or @dfn{immediate}, operands.
758 @defun immediate_operand
759 This predicate allows any sort of constant that fits in @var{mode}.
760 It is an appropriate choice for instructions that take operands that
764 @defun const_int_operand
765 This predicate allows any @code{CONST_INT} expression that fits in
766 @var{mode}. It is an appropriate choice for an immediate operand that
767 does not allow a symbol or label.
770 @defun const_double_operand
771 This predicate accepts any @code{CONST_DOUBLE} expression that has
772 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
773 accept @code{CONST_INT}. It is intended for immediate floating point
778 The second category of predicates allow only some kind of machine
781 @defun register_operand
782 This predicate allows any @code{REG} or @code{SUBREG} expression that
783 is valid for @var{mode}. It is often suitable for arithmetic
784 instruction operands on a RISC machine.
787 @defun pmode_register_operand
788 This is a slight variant on @code{register_operand} which works around
789 a limitation in the machine-description reader.
792 (match_operand @var{n} "pmode_register_operand" @var{constraint})
799 (match_operand:P @var{n} "register_operand" @var{constraint})
803 would mean, if the machine-description reader accepted @samp{:P}
804 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
805 alias for some other mode, and might vary with machine-specific
806 options. @xref{Misc}.
809 @defun scratch_operand
810 This predicate allows hard registers and @code{SCRATCH} expressions,
811 but not pseudo-registers. It is used internally by @code{match_scratch};
812 it should not be used directly.
816 The third category of predicates allow only some kind of memory reference.
818 @defun memory_operand
819 This predicate allows any valid reference to a quantity of mode
820 @var{mode} in memory, as determined by the weak form of
821 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
824 @defun address_operand
825 This predicate is a little unusual; it allows any operand that is a
826 valid expression for the @emph{address} of a quantity of mode
827 @var{mode}, again determined by the weak form of
828 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
829 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
830 @code{memory_operand}, then @var{exp} is acceptable to
831 @code{address_operand}. Note that @var{exp} does not necessarily have
835 @defun indirect_operand
836 This is a stricter form of @code{memory_operand} which allows only
837 memory references with a @code{general_operand} as the address
838 expression. New uses of this predicate are discouraged, because
839 @code{general_operand} is very permissive, so it's hard to tell what
840 an @code{indirect_operand} does or does not allow. If a target has
841 different requirements for memory operands for different instructions,
842 it is better to define target-specific predicates which enforce the
843 hardware's requirements explicitly.
847 This predicate allows a memory reference suitable for pushing a value
848 onto the stack. This will be a @code{MEM} which refers to
849 @code{stack_pointer_rtx}, with a side-effect in its address expression
850 (@pxref{Incdec}); which one is determined by the
851 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
855 This predicate allows a memory reference suitable for popping a value
856 off the stack. Again, this will be a @code{MEM} referring to
857 @code{stack_pointer_rtx}, with a side-effect in its address
858 expression. However, this time @code{STACK_POP_CODE} is expected.
862 The fourth category of predicates allow some combination of the above
865 @defun nonmemory_operand
866 This predicate allows any immediate or register operand valid for @var{mode}.
869 @defun nonimmediate_operand
870 This predicate allows any register or memory operand valid for @var{mode}.
873 @defun general_operand
874 This predicate allows any immediate, register, or memory operand
875 valid for @var{mode}.
879 Finally, there are two generic operator predicates.
881 @defun comparison_operator
882 This predicate matches any expression which performs an arithmetic
883 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
887 @defun ordered_comparison_operator
888 This predicate matches any expression which performs an arithmetic
889 comparison in @var{mode} and whose expression code is valid for integer
890 modes; that is, the expression code will be one of @code{eq}, @code{ne},
891 @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu},
892 @code{ge}, @code{geu}.
895 @node Defining Predicates
896 @subsection Defining Machine-Specific Predicates
897 @cindex defining predicates
898 @findex define_predicate
899 @findex define_special_predicate
901 Many machines have requirements for their operands that cannot be
902 expressed precisely using the generic predicates. You can define
903 additional predicates using @code{define_predicate} and
904 @code{define_special_predicate} expressions. These expressions have
909 The name of the predicate, as it will be referred to in
910 @code{match_operand} or @code{match_operator} expressions.
913 An RTL expression which evaluates to true if the predicate allows the
914 operand @var{op}, false if it does not. This expression can only use
915 the following RTL codes:
919 When written inside a predicate expression, a @code{MATCH_OPERAND}
920 expression evaluates to true if the predicate it names would allow
921 @var{op}. The operand number and constraint are ignored. Due to
922 limitations in @command{genrecog}, you can only refer to generic
923 predicates and predicates that have already been defined.
926 This expression evaluates to true if @var{op} or a specified
927 subexpression of @var{op} has one of a given list of RTX codes.
929 The first operand of this expression is a string constant containing a
930 comma-separated list of RTX code names (in lower case). These are the
931 codes for which the @code{MATCH_CODE} will be true.
933 The second operand is a string constant which indicates what
934 subexpression of @var{op} to examine. If it is absent or the empty
935 string, @var{op} itself is examined. Otherwise, the string constant
936 must be a sequence of digits and/or lowercase letters. Each character
937 indicates a subexpression to extract from the current expression; for
938 the first character this is @var{op}, for the second and subsequent
939 characters it is the result of the previous character. A digit
940 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
941 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
942 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
943 @code{MATCH_CODE} then examines the RTX code of the subexpression
944 extracted by the complete string. It is not possible to extract
945 components of an @code{rtvec} that is not at position 0 within its RTX
949 This expression has one operand, a string constant containing a C
950 expression. The predicate's arguments, @var{op} and @var{mode}, are
951 available with those names in the C expression. The @code{MATCH_TEST}
952 evaluates to true if the C expression evaluates to a nonzero value.
953 @code{MATCH_TEST} expressions must not have side effects.
959 The basic @samp{MATCH_} expressions can be combined using these
960 logical operators, which have the semantics of the C operators
961 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
962 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
963 arbitrary number of arguments; this has exactly the same effect as
964 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
968 An optional block of C code, which should execute
969 @samp{@w{return true}} if the predicate is found to match and
970 @samp{@w{return false}} if it does not. It must not have any side
971 effects. The predicate arguments, @var{op} and @var{mode}, are
972 available with those names.
974 If a code block is present in a predicate definition, then the RTL
975 expression must evaluate to true @emph{and} the code block must
976 execute @samp{@w{return true}} for the predicate to allow the operand.
977 The RTL expression is evaluated first; do not re-check anything in the
978 code block that was checked in the RTL expression.
981 The program @command{genrecog} scans @code{define_predicate} and
982 @code{define_special_predicate} expressions to determine which RTX
983 codes are possibly allowed. You should always make this explicit in
984 the RTL predicate expression, using @code{MATCH_OPERAND} and
987 Here is an example of a simple predicate definition, from the IA64
992 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
993 (define_predicate "small_addr_symbolic_operand"
994 (and (match_code "symbol_ref")
995 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
1000 And here is another, showing the use of the C block.
1004 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
1005 (define_predicate "gr_register_operand"
1006 (match_operand 0 "register_operand")
1009 if (GET_CODE (op) == SUBREG)
1010 op = SUBREG_REG (op);
1013 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
1018 Predicates written with @code{define_predicate} automatically include
1019 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
1020 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
1021 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
1022 integer @code{CONST_DOUBLE}, nor do they test that the value of either
1023 kind of constant fits in the requested mode. This is because
1024 target-specific predicates that take constants usually have to do more
1025 stringent value checks anyway. If you need the exact same treatment
1026 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1027 provide, use a @code{MATCH_OPERAND} subexpression to call
1028 @code{const_int_operand}, @code{const_double_operand}, or
1029 @code{immediate_operand}.
1031 Predicates written with @code{define_special_predicate} do not get any
1032 automatic mode checks, and are treated as having special mode handling
1033 by @command{genrecog}.
1035 The program @command{genpreds} is responsible for generating code to
1036 test predicates. It also writes a header file containing function
1037 declarations for all machine-specific predicates. It is not necessary
1038 to declare these predicates in @file{@var{cpu}-protos.h}.
1041 @c Most of this node appears by itself (in a different place) even
1042 @c when the INTERNALS flag is clear. Passages that require the internals
1043 @c manual's context are conditionalized to appear only in the internals manual.
1046 @section Operand Constraints
1047 @cindex operand constraints
1050 Each @code{match_operand} in an instruction pattern can specify
1051 constraints for the operands allowed. The constraints allow you to
1052 fine-tune matching within the set of operands allowed by the
1058 @section Constraints for @code{asm} Operands
1059 @cindex operand constraints, @code{asm}
1060 @cindex constraints, @code{asm}
1061 @cindex @code{asm} constraints
1063 Here are specific details on what constraint letters you can use with
1064 @code{asm} operands.
1066 Constraints can say whether
1067 an operand may be in a register, and which kinds of register; whether the
1068 operand can be a memory reference, and which kinds of address; whether the
1069 operand may be an immediate constant, and which possible values it may
1070 have. Constraints can also require two operands to match.
1071 Side-effects aren't allowed in operands of inline @code{asm}, unless
1072 @samp{<} or @samp{>} constraints are used, because there is no guarantee
1073 that the side-effects will happen exactly once in an instruction that can update
1074 the addressing register.
1078 * Simple Constraints:: Basic use of constraints.
1079 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1080 * Class Preferences:: Constraints guide which hard register to put things in.
1081 * Modifiers:: More precise control over effects of constraints.
1082 * Machine Constraints:: Existing constraints for some particular machines.
1083 * Disable Insn Alternatives:: Disable insn alternatives using attributes.
1084 * Define Constraints:: How to define machine-specific constraints.
1085 * C Constraint Interface:: How to test constraints from C code.
1091 * Simple Constraints:: Basic use of constraints.
1092 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1093 * Modifiers:: More precise control over effects of constraints.
1094 * Machine Constraints:: Special constraints for some particular machines.
1098 @node Simple Constraints
1099 @subsection Simple Constraints
1100 @cindex simple constraints
1102 The simplest kind of constraint is a string full of letters, each of
1103 which describes one kind of operand that is permitted. Here are
1104 the letters that are allowed:
1108 Whitespace characters are ignored and can be inserted at any position
1109 except the first. This enables each alternative for different operands to
1110 be visually aligned in the machine description even if they have different
1111 number of constraints and modifiers.
1113 @cindex @samp{m} in constraint
1114 @cindex memory references in constraints
1116 A memory operand is allowed, with any kind of address that the machine
1117 supports in general.
1118 Note that the letter used for the general memory constraint can be
1119 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1121 @cindex offsettable address
1122 @cindex @samp{o} in constraint
1124 A memory operand is allowed, but only if the address is
1125 @dfn{offsettable}. This means that adding a small integer (actually,
1126 the width in bytes of the operand, as determined by its machine mode)
1127 may be added to the address and the result is also a valid memory
1130 @cindex autoincrement/decrement addressing
1131 For example, an address which is constant is offsettable; so is an
1132 address that is the sum of a register and a constant (as long as a
1133 slightly larger constant is also within the range of address-offsets
1134 supported by the machine); but an autoincrement or autodecrement
1135 address is not offsettable. More complicated indirect/indexed
1136 addresses may or may not be offsettable depending on the other
1137 addressing modes that the machine supports.
1139 Note that in an output operand which can be matched by another
1140 operand, the constraint letter @samp{o} is valid only when accompanied
1141 by both @samp{<} (if the target machine has predecrement addressing)
1142 and @samp{>} (if the target machine has preincrement addressing).
1144 @cindex @samp{V} in constraint
1146 A memory operand that is not offsettable. In other words, anything that
1147 would fit the @samp{m} constraint but not the @samp{o} constraint.
1149 @cindex @samp{<} in constraint
1151 A memory operand with autodecrement addressing (either predecrement or
1152 postdecrement) is allowed. In inline @code{asm} this constraint is only
1153 allowed if the operand is used exactly once in an instruction that can
1154 handle the side-effects. Not using an operand with @samp{<} in constraint
1155 string in the inline @code{asm} pattern at all or using it in multiple
1156 instructions isn't valid, because the side-effects wouldn't be performed
1157 or would be performed more than once. Furthermore, on some targets
1158 the operand with @samp{<} in constraint string must be accompanied by
1159 special instruction suffixes like @code{%U0} instruction suffix on PowerPC
1160 or @code{%P0} on IA-64.
1162 @cindex @samp{>} in constraint
1164 A memory operand with autoincrement addressing (either preincrement or
1165 postincrement) is allowed. In inline @code{asm} the same restrictions
1166 as for @samp{<} apply.
1168 @cindex @samp{r} in constraint
1169 @cindex registers in constraints
1171 A register operand is allowed provided that it is in a general
1174 @cindex constants in constraints
1175 @cindex @samp{i} in constraint
1177 An immediate integer operand (one with constant value) is allowed.
1178 This includes symbolic constants whose values will be known only at
1179 assembly time or later.
1181 @cindex @samp{n} in constraint
1183 An immediate integer operand with a known numeric value is allowed.
1184 Many systems cannot support assembly-time constants for operands less
1185 than a word wide. Constraints for these operands should use @samp{n}
1186 rather than @samp{i}.
1188 @cindex @samp{I} in constraint
1189 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1190 Other letters in the range @samp{I} through @samp{P} may be defined in
1191 a machine-dependent fashion to permit immediate integer operands with
1192 explicit integer values in specified ranges. For example, on the
1193 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1194 This is the range permitted as a shift count in the shift
1197 @cindex @samp{E} in constraint
1199 An immediate floating operand (expression code @code{const_double}) is
1200 allowed, but only if the target floating point format is the same as
1201 that of the host machine (on which the compiler is running).
1203 @cindex @samp{F} in constraint
1205 An immediate floating operand (expression code @code{const_double} or
1206 @code{const_vector}) is allowed.
1208 @cindex @samp{G} in constraint
1209 @cindex @samp{H} in constraint
1210 @item @samp{G}, @samp{H}
1211 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1212 permit immediate floating operands in particular ranges of values.
1214 @cindex @samp{s} in constraint
1216 An immediate integer operand whose value is not an explicit integer is
1219 This might appear strange; if an insn allows a constant operand with a
1220 value not known at compile time, it certainly must allow any known
1221 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1222 better code to be generated.
1224 For example, on the 68000 in a fullword instruction it is possible to
1225 use an immediate operand; but if the immediate value is between @minus{}128
1226 and 127, better code results from loading the value into a register and
1227 using the register. This is because the load into the register can be
1228 done with a @samp{moveq} instruction. We arrange for this to happen
1229 by defining the letter @samp{K} to mean ``any integer outside the
1230 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1233 @cindex @samp{g} in constraint
1235 Any register, memory or immediate integer operand is allowed, except for
1236 registers that are not general registers.
1238 @cindex @samp{X} in constraint
1241 Any operand whatsoever is allowed, even if it does not satisfy
1242 @code{general_operand}. This is normally used in the constraint of
1243 a @code{match_scratch} when certain alternatives will not actually
1244 require a scratch register.
1247 Any operand whatsoever is allowed.
1250 @cindex @samp{0} in constraint
1251 @cindex digits in constraint
1252 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1253 An operand that matches the specified operand number is allowed. If a
1254 digit is used together with letters within the same alternative, the
1255 digit should come last.
1257 This number is allowed to be more than a single digit. If multiple
1258 digits are encountered consecutively, they are interpreted as a single
1259 decimal integer. There is scant chance for ambiguity, since to-date
1260 it has never been desirable that @samp{10} be interpreted as matching
1261 either operand 1 @emph{or} operand 0. Should this be desired, one
1262 can use multiple alternatives instead.
1264 @cindex matching constraint
1265 @cindex constraint, matching
1266 This is called a @dfn{matching constraint} and what it really means is
1267 that the assembler has only a single operand that fills two roles
1269 considered separate in the RTL insn. For example, an add insn has two
1270 input operands and one output operand in the RTL, but on most CISC
1273 which @code{asm} distinguishes. For example, an add instruction uses
1274 two input operands and an output operand, but on most CISC
1276 machines an add instruction really has only two operands, one of them an
1277 input-output operand:
1283 Matching constraints are used in these circumstances.
1284 More precisely, the two operands that match must include one input-only
1285 operand and one output-only operand. Moreover, the digit must be a
1286 smaller number than the number of the operand that uses it in the
1290 For operands to match in a particular case usually means that they
1291 are identical-looking RTL expressions. But in a few special cases
1292 specific kinds of dissimilarity are allowed. For example, @code{*x}
1293 as an input operand will match @code{*x++} as an output operand.
1294 For proper results in such cases, the output template should always
1295 use the output-operand's number when printing the operand.
1298 @cindex load address instruction
1299 @cindex push address instruction
1300 @cindex address constraints
1301 @cindex @samp{p} in constraint
1303 An operand that is a valid memory address is allowed. This is
1304 for ``load address'' and ``push address'' instructions.
1306 @findex address_operand
1307 @samp{p} in the constraint must be accompanied by @code{address_operand}
1308 as the predicate in the @code{match_operand}. This predicate interprets
1309 the mode specified in the @code{match_operand} as the mode of the memory
1310 reference for which the address would be valid.
1312 @cindex other register constraints
1313 @cindex extensible constraints
1314 @item @var{other-letters}
1315 Other letters can be defined in machine-dependent fashion to stand for
1316 particular classes of registers or other arbitrary operand types.
1317 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1318 for data, address and floating point registers.
1322 In order to have valid assembler code, each operand must satisfy
1323 its constraint. But a failure to do so does not prevent the pattern
1324 from applying to an insn. Instead, it directs the compiler to modify
1325 the code so that the constraint will be satisfied. Usually this is
1326 done by copying an operand into a register.
1328 Contrast, therefore, the two instruction patterns that follow:
1332 [(set (match_operand:SI 0 "general_operand" "=r")
1333 (plus:SI (match_dup 0)
1334 (match_operand:SI 1 "general_operand" "r")))]
1340 which has two operands, one of which must appear in two places, and
1344 [(set (match_operand:SI 0 "general_operand" "=r")
1345 (plus:SI (match_operand:SI 1 "general_operand" "0")
1346 (match_operand:SI 2 "general_operand" "r")))]
1352 which has three operands, two of which are required by a constraint to be
1353 identical. If we are considering an insn of the form
1356 (insn @var{n} @var{prev} @var{next}
1358 (plus:SI (reg:SI 6) (reg:SI 109)))
1363 the first pattern would not apply at all, because this insn does not
1364 contain two identical subexpressions in the right place. The pattern would
1365 say, ``That does not look like an add instruction; try other patterns''.
1366 The second pattern would say, ``Yes, that's an add instruction, but there
1367 is something wrong with it''. It would direct the reload pass of the
1368 compiler to generate additional insns to make the constraint true. The
1369 results might look like this:
1372 (insn @var{n2} @var{prev} @var{n}
1373 (set (reg:SI 3) (reg:SI 6))
1376 (insn @var{n} @var{n2} @var{next}
1378 (plus:SI (reg:SI 3) (reg:SI 109)))
1382 It is up to you to make sure that each operand, in each pattern, has
1383 constraints that can handle any RTL expression that could be present for
1384 that operand. (When multiple alternatives are in use, each pattern must,
1385 for each possible combination of operand expressions, have at least one
1386 alternative which can handle that combination of operands.) The
1387 constraints don't need to @emph{allow} any possible operand---when this is
1388 the case, they do not constrain---but they must at least point the way to
1389 reloading any possible operand so that it will fit.
1393 If the constraint accepts whatever operands the predicate permits,
1394 there is no problem: reloading is never necessary for this operand.
1396 For example, an operand whose constraints permit everything except
1397 registers is safe provided its predicate rejects registers.
1399 An operand whose predicate accepts only constant values is safe
1400 provided its constraints include the letter @samp{i}. If any possible
1401 constant value is accepted, then nothing less than @samp{i} will do;
1402 if the predicate is more selective, then the constraints may also be
1406 Any operand expression can be reloaded by copying it into a register.
1407 So if an operand's constraints allow some kind of register, it is
1408 certain to be safe. It need not permit all classes of registers; the
1409 compiler knows how to copy a register into another register of the
1410 proper class in order to make an instruction valid.
1412 @cindex nonoffsettable memory reference
1413 @cindex memory reference, nonoffsettable
1415 A nonoffsettable memory reference can be reloaded by copying the
1416 address into a register. So if the constraint uses the letter
1417 @samp{o}, all memory references are taken care of.
1420 A constant operand can be reloaded by allocating space in memory to
1421 hold it as preinitialized data. Then the memory reference can be used
1422 in place of the constant. So if the constraint uses the letters
1423 @samp{o} or @samp{m}, constant operands are not a problem.
1426 If the constraint permits a constant and a pseudo register used in an insn
1427 was not allocated to a hard register and is equivalent to a constant,
1428 the register will be replaced with the constant. If the predicate does
1429 not permit a constant and the insn is re-recognized for some reason, the
1430 compiler will crash. Thus the predicate must always recognize any
1431 objects allowed by the constraint.
1434 If the operand's predicate can recognize registers, but the constraint does
1435 not permit them, it can make the compiler crash. When this operand happens
1436 to be a register, the reload pass will be stymied, because it does not know
1437 how to copy a register temporarily into memory.
1439 If the predicate accepts a unary operator, the constraint applies to the
1440 operand. For example, the MIPS processor at ISA level 3 supports an
1441 instruction which adds two registers in @code{SImode} to produce a
1442 @code{DImode} result, but only if the registers are correctly sign
1443 extended. This predicate for the input operands accepts a
1444 @code{sign_extend} of an @code{SImode} register. Write the constraint
1445 to indicate the type of register that is required for the operand of the
1449 @node Multi-Alternative
1450 @subsection Multiple Alternative Constraints
1451 @cindex multiple alternative constraints
1453 Sometimes a single instruction has multiple alternative sets of possible
1454 operands. For example, on the 68000, a logical-or instruction can combine
1455 register or an immediate value into memory, or it can combine any kind of
1456 operand into a register; but it cannot combine one memory location into
1459 These constraints are represented as multiple alternatives. An alternative
1460 can be described by a series of letters for each operand. The overall
1461 constraint for an operand is made from the letters for this operand
1462 from the first alternative, a comma, the letters for this operand from
1463 the second alternative, a comma, and so on until the last alternative.
1465 Here is how it is done for fullword logical-or on the 68000:
1468 (define_insn "iorsi3"
1469 [(set (match_operand:SI 0 "general_operand" "=m,d")
1470 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1471 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1475 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1476 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1477 2. The second alternative has @samp{d} (data register) for operand 0,
1478 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1479 @samp{%} in the constraints apply to all the alternatives; their
1480 meaning is explained in the next section (@pxref{Class Preferences}).
1483 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1484 If all the operands fit any one alternative, the instruction is valid.
1485 Otherwise, for each alternative, the compiler counts how many instructions
1486 must be added to copy the operands so that that alternative applies.
1487 The alternative requiring the least copying is chosen. If two alternatives
1488 need the same amount of copying, the one that comes first is chosen.
1489 These choices can be altered with the @samp{?} and @samp{!} characters:
1492 @cindex @samp{?} in constraint
1493 @cindex question mark
1495 Disparage slightly the alternative that the @samp{?} appears in,
1496 as a choice when no alternative applies exactly. The compiler regards
1497 this alternative as one unit more costly for each @samp{?} that appears
1500 @cindex @samp{!} in constraint
1501 @cindex exclamation point
1503 Disparage severely the alternative that the @samp{!} appears in.
1504 This alternative can still be used if it fits without reloading,
1505 but if reloading is needed, some other alternative will be used.
1509 When an insn pattern has multiple alternatives in its constraints, often
1510 the appearance of the assembler code is determined mostly by which
1511 alternative was matched. When this is so, the C code for writing the
1512 assembler code can use the variable @code{which_alternative}, which is
1513 the ordinal number of the alternative that was actually satisfied (0 for
1514 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1518 @node Class Preferences
1519 @subsection Register Class Preferences
1520 @cindex class preference constraints
1521 @cindex register class preference constraints
1523 @cindex voting between constraint alternatives
1524 The operand constraints have another function: they enable the compiler
1525 to decide which kind of hardware register a pseudo register is best
1526 allocated to. The compiler examines the constraints that apply to the
1527 insns that use the pseudo register, looking for the machine-dependent
1528 letters such as @samp{d} and @samp{a} that specify classes of registers.
1529 The pseudo register is put in whichever class gets the most ``votes''.
1530 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1531 favor of a general register. The machine description says which registers
1532 are considered general.
1534 Of course, on some machines all registers are equivalent, and no register
1535 classes are defined. Then none of this complexity is relevant.
1539 @subsection Constraint Modifier Characters
1540 @cindex modifiers in constraints
1541 @cindex constraint modifier characters
1543 @c prevent bad page break with this line
1544 Here are constraint modifier characters.
1547 @cindex @samp{=} in constraint
1549 Means that this operand is written to by this instruction:
1550 the previous value is discarded and replaced by new data.
1552 @cindex @samp{+} in constraint
1554 Means that this operand is both read and written by the instruction.
1556 When the compiler fixes up the operands to satisfy the constraints,
1557 it needs to know which operands are read by the instruction and
1558 which are written by it. @samp{=} identifies an operand which is only
1559 written; @samp{+} identifies an operand that is both read and written; all
1560 other operands are assumed to only be read.
1562 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1563 first character of the constraint string.
1565 @cindex @samp{&} in constraint
1566 @cindex earlyclobber operand
1568 Means (in a particular alternative) that this operand is an
1569 @dfn{earlyclobber} operand, which is written before the instruction is
1570 finished using the input operands. Therefore, this operand may not lie
1571 in a register that is read by the instruction or as part of any memory
1574 @samp{&} applies only to the alternative in which it is written. In
1575 constraints with multiple alternatives, sometimes one alternative
1576 requires @samp{&} while others do not. See, for example, the
1577 @samp{movdf} insn of the 68000.
1579 A operand which is read by the instruction can be tied to an earlyclobber
1580 operand if its only use as an input occurs before the early result is
1581 written. Adding alternatives of this form often allows GCC to produce
1582 better code when only some of the read operands can be affected by the
1583 earlyclobber. See, for example, the @samp{mulsi3} insn of the ARM@.
1585 Furthermore, if the @dfn{earlyclobber} operand is also a read/write
1586 operand, then that operand is written only after it's used.
1588 @samp{&} does not obviate the need to write @samp{=} or @samp{+}. As
1589 @dfn{earlyclobber} operands are always written, a read-only
1590 @dfn{earlyclobber} operand is ill-formed and will be rejected by the
1593 @cindex @samp{%} in constraint
1595 Declares the instruction to be commutative for this operand and the
1596 following operand. This means that the compiler may interchange the
1597 two operands if that is the cheapest way to make all operands fit the
1598 constraints. @samp{%} applies to all alternatives and must appear as
1599 the first character in the constraint. Only read-only operands can use
1603 This is often used in patterns for addition instructions
1604 that really have only two operands: the result must go in one of the
1605 arguments. Here for example, is how the 68000 halfword-add
1606 instruction is defined:
1609 (define_insn "addhi3"
1610 [(set (match_operand:HI 0 "general_operand" "=m,r")
1611 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1612 (match_operand:HI 2 "general_operand" "di,g")))]
1616 GCC can only handle one commutative pair in an asm; if you use more,
1617 the compiler may fail. Note that you need not use the modifier if
1618 the two alternatives are strictly identical; this would only waste
1619 time in the reload pass. The modifier is not operational after
1620 register allocation, so the result of @code{define_peephole2}
1621 and @code{define_split}s performed after reload cannot rely on
1622 @samp{%} to make the intended insn match.
1624 @cindex @samp{#} in constraint
1626 Says that all following characters, up to the next comma, are to be
1627 ignored as a constraint. They are significant only for choosing
1628 register preferences.
1630 @cindex @samp{*} in constraint
1632 Says that the following character should be ignored when choosing
1633 register preferences. @samp{*} has no effect on the meaning of the
1634 constraint as a constraint, and no effect on reloading. For LRA
1635 @samp{*} additionally disparages slightly the alternative if the
1636 following character matches the operand.
1639 Here is an example: the 68000 has an instruction to sign-extend a
1640 halfword in a data register, and can also sign-extend a value by
1641 copying it into an address register. While either kind of register is
1642 acceptable, the constraints on an address-register destination are
1643 less strict, so it is best if register allocation makes an address
1644 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1645 constraint letter (for data register) is ignored when computing
1646 register preferences.
1649 (define_insn "extendhisi2"
1650 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1652 (match_operand:HI 1 "general_operand" "0,g")))]
1658 @node Machine Constraints
1659 @subsection Constraints for Particular Machines
1660 @cindex machine specific constraints
1661 @cindex constraints, machine specific
1663 Whenever possible, you should use the general-purpose constraint letters
1664 in @code{asm} arguments, since they will convey meaning more readily to
1665 people reading your code. Failing that, use the constraint letters
1666 that usually have very similar meanings across architectures. The most
1667 commonly used constraints are @samp{m} and @samp{r} (for memory and
1668 general-purpose registers respectively; @pxref{Simple Constraints}), and
1669 @samp{I}, usually the letter indicating the most common
1670 immediate-constant format.
1672 Each architecture defines additional constraints. These constraints
1673 are used by the compiler itself for instruction generation, as well as
1674 for @code{asm} statements; therefore, some of the constraints are not
1675 particularly useful for @code{asm}. Here is a summary of some of the
1676 machine-dependent constraints available on some particular machines;
1677 it includes both constraints that are useful for @code{asm} and
1678 constraints that aren't. The compiler source file mentioned in the
1679 table heading for each architecture is the definitive reference for
1680 the meanings of that architecture's constraints.
1683 @item AArch64 family---@file{config/aarch64/constraints.md}
1686 The stack pointer register (@code{SP})
1689 Floating point or SIMD vector register
1692 Integer constant that is valid as an immediate operand in an @code{ADD}
1696 Integer constant that is valid as an immediate operand in a @code{SUB}
1697 instruction (once negated)
1700 Integer constant that can be used with a 32-bit logical instruction
1703 Integer constant that can be used with a 64-bit logical instruction
1706 Integer constant that is valid as an immediate operand in a 32-bit @code{MOV}
1707 pseudo instruction. The @code{MOV} may be assembled to one of several different
1708 machine instructions depending on the value
1711 Integer constant that is valid as an immediate operand in a 64-bit @code{MOV}
1715 An absolute symbolic address or a label reference
1718 Floating point constant zero
1721 Integer constant zero
1724 The high part (bits 12 and upwards) of the pc-relative address of a symbol
1725 within 4GB of the instruction
1728 A memory address which uses a single base register with no offset
1731 A memory address suitable for a load/store pair instruction in SI, DI, SF and
1737 @item ARC ---@file{config/arc/constraints.md}
1740 Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
1741 @code{r12}-@code{r15}. This constraint can only match when the @option{-mq}
1742 option is in effect.
1745 Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
1746 instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}.
1747 This constraint can only match when the @option{-mq}
1748 option is in effect.
1750 ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}.
1753 A signed 12-bit integer constant.
1756 constant for arithmetic/logical operations. This might be any constant
1757 that can be put into a long immediate by the assmbler or linker without
1758 involving a PIC relocation.
1761 A 3-bit unsigned integer constant.
1764 A 6-bit unsigned integer constant.
1767 One's complement of a 6-bit unsigned integer constant.
1770 Two's complement of a 6-bit unsigned integer constant.
1773 A 5-bit unsigned integer constant.
1776 A 7-bit unsigned integer constant.
1779 A 8-bit unsigned integer constant.
1782 Any const_double value.
1785 @item ARM family---@file{config/arm/constraints.md}
1788 VFP floating-point register
1791 The floating-point constant 0.0
1794 Integer that is valid as an immediate operand in a data processing
1795 instruction. That is, an integer in the range 0 to 255 rotated by a
1799 Integer in the range @minus{}4095 to 4095
1802 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1805 Integer that satisfies constraint @samp{I} when negated (twos complement)
1808 Integer in the range 0 to 32
1811 A memory reference where the exact address is in a single register
1812 (`@samp{m}' is preferable for @code{asm} statements)
1815 An item in the constant pool
1818 A symbol in the text segment of the current file
1821 A memory reference suitable for VFP load/store insns (reg+constant offset)
1824 A memory reference suitable for iWMMXt load/store instructions.
1827 A memory reference suitable for the ARMv4 ldrsb instruction.
1830 @item AVR family---@file{config/avr/constraints.md}
1833 Registers from r0 to r15
1836 Registers from r16 to r23
1839 Registers from r16 to r31
1842 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1845 Pointer register (r26--r31)
1848 Base pointer register (r28--r31)
1851 Stack pointer register (SPH:SPL)
1854 Temporary register r0
1857 Register pair X (r27:r26)
1860 Register pair Y (r29:r28)
1863 Register pair Z (r31:r30)
1866 Constant greater than @minus{}1, less than 64
1869 Constant greater than @minus{}64, less than 1
1878 Constant that fits in 8 bits
1881 Constant integer @minus{}1
1884 Constant integer 8, 16, or 24
1890 A floating point constant 0.0
1893 A memory address based on Y or Z pointer with displacement.
1896 @item Epiphany---@file{config/epiphany/constraints.md}
1899 An unsigned 16-bit constant.
1902 An unsigned 5-bit constant.
1905 A signed 11-bit constant.
1908 A signed 11-bit constant added to @minus{}1.
1909 Can only match when the @option{-m1reg-@var{reg}} option is active.
1912 Left-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest
1913 being a block of trailing zeroes.
1914 Can only match when the @option{-m1reg-@var{reg}} option is active.
1917 Right-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the
1918 rest being zeroes. Or to put it another way, one less than a power of two.
1919 Can only match when the @option{-m1reg-@var{reg}} option is active.
1922 Constant for arithmetic/logical operations.
1923 This is like @code{i}, except that for position independent code,
1924 no symbols / expressions needing relocations are allowed.
1927 Symbolic constant for call/jump instruction.
1930 The register class usable in short insns. This is a register class
1931 constraint, and can thus drive register allocation.
1932 This constraint won't match unless @option{-mprefer-short-insn-regs} is
1936 The the register class of registers that can be used to hold a
1937 sibcall call address. I.e., a caller-saved register.
1940 Core control register class.
1943 The register group usable in short insns.
1944 This constraint does not use a register class, so that it only
1945 passively matches suitable registers, and doesn't drive register allocation.
1949 Constant suitable for the addsi3_r pattern. This is a valid offset
1950 For byte, halfword, or word addressing.
1954 Matches the return address if it can be replaced with the link register.
1957 Matches the integer condition code register.
1960 Matches the return address if it is in a stack slot.
1963 Matches control register values to switch fp mode, which are encapsulated in
1964 @code{UNSPEC_FP_MODE}.
1967 @item CR16 Architecture---@file{config/cr16/cr16.h}
1971 Registers from r0 to r14 (registers without stack pointer)
1974 Register from r0 to r11 (all 16-bit registers)
1977 Register from r12 to r15 (all 32-bit registers)
1980 Signed constant that fits in 4 bits
1983 Signed constant that fits in 5 bits
1986 Signed constant that fits in 6 bits
1989 Unsigned constant that fits in 4 bits
1992 Signed constant that fits in 32 bits
1995 Check for 64 bits wide constants for add/sub instructions
1998 Floating point constant that is legal for store immediate
2001 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
2007 Floating point register
2010 Shift amount register
2013 Floating point register (deprecated)
2016 Upper floating point register (32-bit), floating point register (64-bit)
2022 Signed 11-bit integer constant
2025 Signed 14-bit integer constant
2028 Integer constant that can be deposited with a @code{zdepi} instruction
2031 Signed 5-bit integer constant
2037 Integer constant that can be loaded with a @code{ldil} instruction
2040 Integer constant whose value plus one is a power of 2
2043 Integer constant that can be used for @code{and} operations in @code{depi}
2044 and @code{extru} instructions
2053 Floating-point constant 0.0
2056 A @code{lo_sum} data-linkage-table memory operand
2059 A memory operand that can be used as the destination operand of an
2060 integer store instruction
2063 A scaled or unscaled indexed memory operand
2066 A memory operand for floating-point loads and stores
2069 A register indirect memory operand
2072 @item PowerPC and IBM RS6000---@file{config/rs6000/constraints.md}
2075 Address base register
2078 Floating point register (containing 64-bit value)
2081 Floating point register (containing 32-bit value)
2084 Altivec vector register
2087 Any VSX register if the -mvsx option was used or NO_REGS.
2090 VSX vector register to hold vector double data or NO_REGS.
2093 VSX vector register to hold vector float data or NO_REGS.
2096 If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
2099 Floating point register if direct moves are available, or NO_REGS.
2102 FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
2105 FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.
2108 FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.
2111 Floating point register if the LFIWAX instruction is enabled or NO_REGS.
2114 VSX register if direct move instructions are enabled, or NO_REGS.
2117 No register (NO_REGS).
2120 General purpose register if 64-bit instructions are enabled or NO_REGS.
2123 VSX vector register to hold scalar double values or NO_REGS.
2126 VSX vector register to hold 128 bit integer or NO_REGS.
2129 Altivec register to use for float/32-bit int loads/stores or NO_REGS.
2132 Altivec register to use for double loads/stores or NO_REGS.
2135 FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
2138 Floating point register if the STFIWX instruction is enabled or NO_REGS.
2141 FP or VSX register to perform ISA 2.07 float ops or NO_REGS.
2144 Floating point register if the LFIWZX instruction is enabled or NO_REGS.
2147 Int constant that is the element number of the 64-bit scalar in a vector.
2150 A memory address that will work with the @code{lq} and @code{stq}
2154 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
2163 @samp{LINK} register
2166 @samp{CR} register (condition register) number 0
2169 @samp{CR} register (condition register)
2172 @samp{XER[CA]} carry bit (part of the XER register)
2175 Signed 16-bit constant
2178 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
2179 @code{SImode} constants)
2182 Unsigned 16-bit constant
2185 Signed 16-bit constant shifted left 16 bits
2188 Constant larger than 31
2197 Constant whose negation is a signed 16-bit constant
2200 Floating point constant that can be loaded into a register with one
2201 instruction per word
2204 Integer/Floating point constant that can be loaded into a register using
2209 Normally, @code{m} does not allow addresses that update the base register.
2210 If @samp{<} or @samp{>} constraint is also used, they are allowed and
2211 therefore on PowerPC targets in that case it is only safe
2212 to use @samp{m<>} in an @code{asm} statement if that @code{asm} statement
2213 accesses the operand exactly once. The @code{asm} statement must also
2214 use @samp{%U@var{<opno>}} as a placeholder for the ``update'' flag in the
2215 corresponding load or store instruction. For example:
2218 asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
2224 asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
2230 A ``stable'' memory operand; that is, one which does not include any
2231 automodification of the base register. This used to be useful when
2232 @samp{m} allowed automodification of the base register, but as those are now only
2233 allowed when @samp{<} or @samp{>} is used, @samp{es} is basically the same
2234 as @samp{m} without @samp{<} and @samp{>}.
2237 Memory operand that is an offset from a register (it is usually better
2238 to use @samp{m} or @samp{es} in @code{asm} statements)
2241 Memory operand that is an indexed or indirect from a register (it is
2242 usually better to use @samp{m} or @samp{es} in @code{asm} statements)
2248 Address operand that is an indexed or indirect from a register (@samp{p} is
2249 preferable for @code{asm} statements)
2252 Constant suitable as a 64-bit mask operand
2255 Constant suitable as a 32-bit mask operand
2258 System V Release 4 small data area reference
2261 AND masks that can be performed by two rldic@{l, r@} instructions
2264 Vector constant that does not require memory
2267 Vector constant that is all zeros.
2271 @item Intel 386---@file{config/i386/constraints.md}
2274 Legacy register---the eight integer registers available on all
2275 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
2276 @code{si}, @code{di}, @code{bp}, @code{sp}).
2279 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
2280 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
2283 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
2284 @code{c}, and @code{d}.
2288 Any register that can be used as the index in a base+index memory
2289 access: that is, any general register except the stack pointer.
2293 The @code{a} register.
2296 The @code{b} register.
2299 The @code{c} register.
2302 The @code{d} register.
2305 The @code{si} register.
2308 The @code{di} register.
2311 The @code{a} and @code{d} registers. This class is used for instructions
2312 that return double word results in the @code{ax:dx} register pair. Single
2313 word values will be allocated either in @code{ax} or @code{dx}.
2314 For example on i386 the following implements @code{rdtsc}:
2317 unsigned long long rdtsc (void)
2319 unsigned long long tick;
2320 __asm__ __volatile__("rdtsc":"=A"(tick));
2325 This is not correct on x86_64 as it would allocate tick in either @code{ax}
2326 or @code{dx}. You have to use the following variant instead:
2329 unsigned long long rdtsc (void)
2331 unsigned int tickl, tickh;
2332 __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
2333 return ((unsigned long long)tickh << 32)|tickl;
2339 Any 80387 floating-point (stack) register.
2342 Top of 80387 floating-point stack (@code{%st(0)}).
2345 Second from top of 80387 floating-point stack (@code{%st(1)}).
2354 First SSE register (@code{%xmm0}).
2358 Any SSE register, when SSE2 is enabled.
2361 Any SSE register, when SSE2 and inter-unit moves are enabled.
2364 Any MMX register, when inter-unit moves are enabled.
2368 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
2371 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
2374 Signed 8-bit integer constant.
2377 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
2380 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
2383 Unsigned 8-bit integer constant (for @code{in} and @code{out}
2388 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
2392 Standard 80387 floating point constant.
2395 Standard SSE floating point constant.
2398 32-bit signed integer constant, or a symbolic reference known
2399 to fit that range (for immediate operands in sign-extending x86-64
2403 32-bit unsigned integer constant, or a symbolic reference known
2404 to fit that range (for immediate operands in zero-extending x86-64
2409 @item Intel IA-64---@file{config/ia64/ia64.h}
2412 General register @code{r0} to @code{r3} for @code{addl} instruction
2418 Predicate register (@samp{c} as in ``conditional'')
2421 Application register residing in M-unit
2424 Application register residing in I-unit
2427 Floating-point register
2430 Memory operand. If used together with @samp{<} or @samp{>},
2431 the operand can have postincrement and postdecrement which
2432 require printing with @samp{%Pn} on IA-64.
2435 Floating-point constant 0.0 or 1.0
2438 14-bit signed integer constant
2441 22-bit signed integer constant
2444 8-bit signed integer constant for logical instructions
2447 8-bit adjusted signed integer constant for compare pseudo-ops
2450 6-bit unsigned integer constant for shift counts
2453 9-bit signed integer constant for load and store postincrements
2459 0 or @minus{}1 for @code{dep} instruction
2462 Non-volatile memory for floating-point loads and stores
2465 Integer constant in the range 1 to 4 for @code{shladd} instruction
2468 Memory operand except postincrement and postdecrement. This is
2469 now roughly the same as @samp{m} when not used together with @samp{<}
2473 @item FRV---@file{config/frv/frv.h}
2476 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2479 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2482 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2483 @code{icc0} to @code{icc3}).
2486 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2489 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2490 Odd registers are excluded not in the class but through the use of a machine
2491 mode larger than 4 bytes.
2494 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2497 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2498 Odd registers are excluded not in the class but through the use of a machine
2499 mode larger than 4 bytes.
2502 Register in the class @code{LR_REG} (the @code{lr} register).
2505 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2506 Register numbers not divisible by 4 are excluded not in the class but through
2507 the use of a machine mode larger than 8 bytes.
2510 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2513 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2516 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2519 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2522 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2523 Register numbers not divisible by 4 are excluded not in the class but through
2524 the use of a machine mode larger than 8 bytes.
2527 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2530 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2533 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2536 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2539 Floating point constant zero
2542 6-bit signed integer constant
2545 10-bit signed integer constant
2548 16-bit signed integer constant
2551 16-bit unsigned integer constant
2554 12-bit signed integer constant that is negative---i.e.@: in the
2555 range of @minus{}2048 to @minus{}1
2561 12-bit signed integer constant that is greater than zero---i.e.@: in the
2566 @item Blackfin family---@file{config/bfin/constraints.md}
2575 A call clobbered P register.
2578 A single register. If @var{n} is in the range 0 to 7, the corresponding D
2579 register. If it is @code{A}, then the register P0.
2582 Even-numbered D register
2585 Odd-numbered D register
2588 Accumulator register.
2591 Even-numbered accumulator register.
2594 Odd-numbered accumulator register.
2606 Registers used for circular buffering, i.e. I, B, or L registers.
2621 Any D, P, B, M, I or L register.
2624 Additional registers typically used only in prologues and epilogues: RETS,
2625 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2628 Any register except accumulators or CC.
2631 Signed 16 bit integer (in the range @minus{}32768 to 32767)
2634 Unsigned 16 bit integer (in the range 0 to 65535)
2637 Signed 7 bit integer (in the range @minus{}64 to 63)
2640 Unsigned 7 bit integer (in the range 0 to 127)
2643 Unsigned 5 bit integer (in the range 0 to 31)
2646 Signed 4 bit integer (in the range @minus{}8 to 7)
2649 Signed 3 bit integer (in the range @minus{}3 to 4)
2652 Unsigned 3 bit integer (in the range 0 to 7)
2655 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2658 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2659 use with either accumulator.
2662 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2663 use only with accumulator A1.
2672 An integer constant with exactly a single bit set.
2675 An integer constant with all bits set except exactly one.
2683 @item M32C---@file{config/m32c/m32c.c}
2688 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2691 Any control register, when they're 16 bits wide (nothing if control
2692 registers are 24 bits wide)
2695 Any control register, when they're 24 bits wide.
2704 $r0 or $r2, or $r2r0 for 32 bit values.
2707 $r1 or $r3, or $r3r1 for 32 bit values.
2710 A register that can hold a 64 bit value.
2713 $r0 or $r1 (registers with addressable high/low bytes)
2722 Address registers when they're 16 bits wide.
2725 Address registers when they're 24 bits wide.
2728 Registers that can hold QI values.
2731 Registers that can be used with displacements ($a0, $a1, $sb).
2734 Registers that can hold 32 bit values.
2737 Registers that can hold 16 bit values.
2740 Registers chat can hold 16 bit values, including all control
2744 $r0 through R1, plus $a0 and $a1.
2750 The memory-based pseudo-registers $mem0 through $mem15.
2753 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2754 bit registers for m32cm, m32c).
2757 Matches multiple registers in a PARALLEL to form a larger register.
2758 Used to match function return values.
2764 @minus{}128 @dots{} 127
2767 @minus{}32768 @dots{} 32767
2773 @minus{}8 @dots{} @minus{}1 or 1 @dots{} 8
2776 @minus{}16 @dots{} @minus{}1 or 1 @dots{} 16
2779 @minus{}32 @dots{} @minus{}1 or 1 @dots{} 32
2782 @minus{}65536 @dots{} @minus{}1
2785 An 8 bit value with exactly one bit set.
2788 A 16 bit value with exactly one bit set.
2791 The common src/dest memory addressing modes.
2794 Memory addressed using $a0 or $a1.
2797 Memory addressed with immediate addresses.
2800 Memory addressed using the stack pointer ($sp).
2803 Memory addressed using the frame base register ($fb).
2806 Memory addressed using the small base register ($sb).
2812 @item MeP---@file{config/mep/constraints.md}
2822 Any control register.
2825 Either the $hi or the $lo register.
2828 Coprocessor registers that can be directly loaded ($c0-$c15).
2831 Coprocessor registers that can be moved to each other.
2834 Coprocessor registers that can be moved to core registers.
2846 Registers which can be used in $tp-relative addressing.
2852 The coprocessor registers.
2855 The coprocessor control registers.
2861 User-defined register set A.
2864 User-defined register set B.
2867 User-defined register set C.
2870 User-defined register set D.
2873 Offsets for $gp-rel addressing.
2876 Constants that can be used directly with boolean insns.
2879 Constants that can be moved directly to registers.
2882 Small constants that can be added to registers.
2888 Small constants that can be compared to registers.
2891 Constants that can be loaded into the top half of registers.
2894 Signed 8-bit immediates.
2897 Symbols encoded for $tp-rel or $gp-rel addressing.
2900 Non-constant addresses for loading/saving coprocessor registers.
2903 The top half of a symbol's value.
2906 A register indirect address without offset.
2909 Symbolic references to the control bus.
2913 @item MicroBlaze---@file{config/microblaze/constraints.md}
2916 A general register (@code{r0} to @code{r31}).
2919 A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}).
2923 @item MIPS---@file{config/mips/constraints.md}
2926 An address register. This is equivalent to @code{r} unless
2927 generating MIPS16 code.
2930 A floating-point register (if available).
2933 Formerly the @code{hi} register. This constraint is no longer supported.
2936 The @code{lo} register. Use this register to store values that are
2937 no bigger than a word.
2940 The concatenated @code{hi} and @code{lo} registers. Use this register
2941 to store doubleword values.
2944 A register suitable for use in an indirect jump. This will always be
2945 @code{$25} for @option{-mabicalls}.
2948 Register @code{$3}. Do not use this constraint in new code;
2949 it is retained only for compatibility with glibc.
2952 Equivalent to @code{r}; retained for backwards compatibility.
2955 A floating-point condition code register.
2958 A signed 16-bit constant (for arithmetic instructions).
2964 An unsigned 16-bit constant (for logic instructions).
2967 A signed 32-bit constant in which the lower 16 bits are zero.
2968 Such constants can be loaded using @code{lui}.
2971 A constant that cannot be loaded using @code{lui}, @code{addiu}
2975 A constant in the range @minus{}65535 to @minus{}1 (inclusive).
2978 A signed 15-bit constant.
2981 A constant in the range 1 to 65535 (inclusive).
2984 Floating-point zero.
2987 An address that can be used in a non-macro load or store.
2990 When compiling microMIPS code, this constraint matches a memory operand
2991 whose address is formed from a base register and a 12-bit offset. These
2992 operands can be used for microMIPS instructions such as @code{ll} and
2993 @code{sc}. When not compiling for microMIPS code, @code{ZC} is
2994 equivalent to @code{R}.
2997 An address suitable for a @code{prefetch} instruction, or for any other
2998 instruction with the same addressing mode as @code{prefetch}.
3001 @item Motorola 680x0---@file{config/m68k/constraints.md}
3010 68881 floating-point register, if available
3013 Integer in the range 1 to 8
3016 16-bit signed number
3019 Signed number whose magnitude is greater than 0x80
3022 Integer in the range @minus{}8 to @minus{}1
3025 Signed number whose magnitude is greater than 0x100
3028 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
3031 16 (for rotate using swap)
3034 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
3037 Numbers that mov3q can handle
3040 Floating point constant that is not a 68881 constant
3043 Operands that satisfy 'm' when -mpcrel is in effect
3046 Operands that satisfy 's' when -mpcrel is not in effect
3049 Address register indirect addressing mode
3052 Register offset addressing
3067 Range of signed numbers that don't fit in 16 bits
3070 Integers valid for mvq
3073 Integers valid for a moveq followed by a swap
3076 Integers valid for mvz
3079 Integers valid for mvs
3085 Non-register operands allowed in clr
3089 @item Moxie---@file{config/moxie/constraints.md}
3098 A register indirect memory operand
3101 A constant in the range of 0 to 255.
3104 A constant in the range of 0 to @minus{}255.
3108 @item MSP430--@file{config/msp430/constraints.md}
3121 Integer constant -1^20..1^19.
3124 Integer constant 1-4.
3127 Memory references which do not require an extended MOVX instruction.
3130 Memory reference, labels only.
3133 Memory reference, stack only.
3137 @item NDS32---@file{config/nds32/constraints.md}
3140 LOW register class $r0 to $r7 constraint for V3/V3M ISA.
3142 LOW register class $r0 to $r7.
3144 MIDDLE register class $r0 to $r11, $r16 to $r19.
3146 HIGH register class $r12 to $r14, $r20 to $r31.
3148 Temporary assist register $ta (i.e.@: $r15).
3152 Unsigned immediate 3-bit value.
3154 Negative immediate 3-bit value in the range of @minus{}7--0.
3156 Unsigned immediate 4-bit value.
3158 Signed immediate 5-bit value.
3160 Unsigned immediate 5-bit value.
3162 Negative immediate 5-bit value in the range of @minus{}31--0.
3164 Unsigned immediate 5-bit value for movpi45 instruction with range 16--47.
3166 Unsigned immediate 6-bit value constraint for addri36.sp instruction.
3168 Unsigned immediate 8-bit value.
3170 Unsigned immediate 9-bit value.
3172 Signed immediate 10-bit value.
3174 Signed immediate 11-bit value.
3176 Signed immediate 15-bit value.
3178 Unsigned immediate 15-bit value.
3180 A constant which is not in the range of imm15u but ok for bclr instruction.
3182 A constant which is not in the range of imm15u but ok for bset instruction.
3184 A constant which is not in the range of imm15u but ok for btgl instruction.
3186 A constant whose compliment value is in the range of imm15u
3187 and ok for bitci instruction.
3189 Signed immediate 16-bit value.
3191 Signed immediate 17-bit value.
3193 Signed immediate 19-bit value.
3195 Signed immediate 20-bit value.
3197 The immediate value that can be simply set high 20-bit.
3199 The immediate value 0xff.
3201 The immediate value 0xffff.
3203 The immediate value 0x01.
3205 The immediate value 0x7ff.
3207 The immediate value with power of 2.
3209 The immediate value with power of 2 minus 1.
3211 Memory constraint for 333 format.
3213 Memory constraint for 45 format.
3215 Memory constraint for 37 format.
3218 @item Nios II family---@file{config/nios2/constraints.md}
3222 Integer that is valid as an immediate operand in an
3223 instruction taking a signed 16-bit number. Range
3224 @minus{}32768 to 32767.
3227 Integer that is valid as an immediate operand in an
3228 instruction taking an unsigned 16-bit number. Range
3232 Integer that is valid as an immediate operand in an
3233 instruction taking only the upper 16-bits of a
3234 32-bit number. Range 32-bit numbers with the lower
3238 Integer that is valid as an immediate operand for a
3239 shift instruction. Range 0 to 31.
3242 Integer that is valid as an immediate operand for
3243 only the value 0. Can be used in conjunction with
3244 the format modifier @code{z} to use @code{r0}
3245 instead of @code{0} in the assembly output.
3248 Integer that is valid as an immediate operand for
3249 a custom instruction opcode. Range 0 to 255.
3252 Matches immediates which are addresses in the small
3253 data section and therefore can be added to @code{gp}
3254 as a 16-bit immediate to re-create their 32-bit value.
3258 A @code{const} wrapped @code{UNSPEC} expression,
3259 representing a supported PIC or TLS relocation.
3264 @item PDP-11---@file{config/pdp11/constraints.md}
3267 Floating point registers AC0 through AC3. These can be loaded from/to
3268 memory with a single instruction.
3271 Odd numbered general registers (R1, R3, R5). These are used for
3272 16-bit multiply operations.
3275 Any of the floating point registers (AC0 through AC5).
3278 Floating point constant 0.
3281 An integer constant that fits in 16 bits.
3284 An integer constant whose low order 16 bits are zero.
3287 An integer constant that does not meet the constraints for codes
3288 @samp{I} or @samp{J}.
3291 The integer constant 1.
3294 The integer constant @minus{}1.
3297 The integer constant 0.
3300 Integer constants @minus{}4 through @minus{}1 and 1 through 4; shifts by these
3301 amounts are handled as multiple single-bit shifts rather than a single
3302 variable-length shift.
3305 A memory reference which requires an additional word (address or
3306 offset) after the opcode.
3309 A memory reference that is encoded within the opcode.
3313 @item RL78---@file{config/rl78/constraints.md}
3317 An integer constant in the range 1 @dots{} 7.
3319 An integer constant in the range 0 @dots{} 255.
3321 An integer constant in the range @minus{}255 @dots{} 0
3323 The integer constant 1.
3325 The integer constant -1.
3327 The integer constant 0.
3329 The integer constant 2.
3331 The integer constant -2.
3333 An integer constant in the range 1 @dots{} 15.
3335 The built-in compare types--eq, ne, gtu, ltu, geu, and leu.
3337 The synthetic compare types--gt, lt, ge, and le.
3339 A memory reference with an absolute address.
3341 A memory reference using @code{BC} as a base register, with an optional offset.
3343 A memory reference using @code{AX}, @code{BC}, @code{DE}, or @code{HL} for the address, for calls.
3345 A memory reference using any 16-bit register pair for the address, for calls.
3347 A memory reference using @code{DE} as a base register, with an optional offset.
3349 A memory reference using @code{DE} as a base register, without any offset.
3351 Any memory reference to an address in the far address space.
3353 A memory reference using @code{HL} as a base register, with an optional one-byte offset.
3355 A memory reference using @code{HL} as a base register, with @code{B} or @code{C} as the index register.
3357 A memory reference using @code{HL} as a base register, without any offset.
3359 A memory reference using @code{SP} as a base register, with an optional one-byte offset.
3361 Any memory reference to an address in the near address space.
3363 The @code{AX} register.
3365 The @code{BC} register.
3367 The @code{DE} register.
3369 @code{A} through @code{L} registers.
3371 The @code{SP} register.
3373 The @code{HL} register.
3375 The 16-bit @code{R8} register.
3377 The 16-bit @code{R10} register.
3379 The registers reserved for interrupts (@code{R24} to @code{R31}).
3381 The @code{A} register.
3383 The @code{B} register.
3385 The @code{C} register.
3387 The @code{D} register.
3389 The @code{E} register.
3391 The @code{H} register.
3393 The @code{L} register.
3395 The virtual registers.
3397 The @code{PSW} register.
3399 The @code{X} register.
3403 @item RX---@file{config/rx/constraints.md}
3406 An address which does not involve register indirect addressing or
3407 pre/post increment/decrement addressing.
3413 A constant in the range @minus{}256 to 255, inclusive.
3416 A constant in the range @minus{}128 to 127, inclusive.
3419 A constant in the range @minus{}32768 to 32767, inclusive.
3422 A constant in the range @minus{}8388608 to 8388607, inclusive.
3425 A constant in the range 0 to 15, inclusive.
3430 @item SPARC---@file{config/sparc/sparc.h}
3433 Floating-point register on the SPARC-V8 architecture and
3434 lower floating-point register on the SPARC-V9 architecture.
3437 Floating-point register. It is equivalent to @samp{f} on the
3438 SPARC-V8 architecture and contains both lower and upper
3439 floating-point registers on the SPARC-V9 architecture.
3442 Floating-point condition code register.
3445 Lower floating-point register. It is only valid on the SPARC-V9
3446 architecture when the Visual Instruction Set is available.
3449 Floating-point register. It is only valid on the SPARC-V9 architecture
3450 when the Visual Instruction Set is available.
3453 64-bit global or out register for the SPARC-V8+ architecture.
3456 The constant all-ones, for floating-point.
3459 Signed 5-bit constant
3465 Signed 13-bit constant
3471 32-bit constant with the low 12 bits clear (a constant that can be
3472 loaded with the @code{sethi} instruction)
3475 A constant in the range supported by @code{movcc} instructions (11-bit
3479 A constant in the range supported by @code{movrcc} instructions (10-bit
3483 Same as @samp{K}, except that it verifies that bits that are not in the
3484 lower 32-bit range are all zero. Must be used instead of @samp{K} for
3485 modes wider than @code{SImode}
3494 Signed 13-bit constant, sign-extended to 32 or 64 bits
3500 Floating-point constant whose integral representation can
3501 be moved into an integer register using a single sethi
3505 Floating-point constant whose integral representation can
3506 be moved into an integer register using a single mov
3510 Floating-point constant whose integral representation can
3511 be moved into an integer register using a high/lo_sum
3512 instruction sequence
3515 Memory address aligned to an 8-byte boundary
3521 Memory address for @samp{e} constraint registers
3524 Memory address with only a base register
3531 @item SPU---@file{config/spu/spu.h}
3534 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
3537 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
3540 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
3543 An immediate which can be loaded with @code{fsmbi}.
3546 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
3549 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
3552 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
3555 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
3558 A constant in the range [@minus{}64, 63] for shift/rotate instructions.
3561 An unsigned 7-bit constant for conversion/nop/channel instructions.
3564 A signed 10-bit constant for most arithmetic instructions.
3567 A signed 16 bit immediate for @code{stop}.
3570 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
3573 An unsigned 7-bit constant whose 3 least significant bits are 0.
3576 An unsigned 3-bit constant for 16-byte rotates and shifts
3579 Call operand, reg, for indirect calls
3582 Call operand, symbol, for relative calls.
3585 Call operand, const_int, for absolute calls.
3588 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
3591 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
3594 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
3597 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
3601 @item S/390 and zSeries---@file{config/s390/s390.h}
3604 Address register (general purpose register except r0)
3607 Condition code register
3610 Data register (arbitrary general purpose register)
3613 Floating-point register
3616 Unsigned 8-bit constant (0--255)
3619 Unsigned 12-bit constant (0--4095)
3622 Signed 16-bit constant (@minus{}32768--32767)
3625 Value appropriate as displacement.
3628 for short displacement
3629 @item (@minus{}524288..524287)
3630 for long displacement
3634 Constant integer with a value of 0x7fffffff.
3637 Multiple letter constraint followed by 4 parameter letters.
3640 number of the part counting from most to least significant
3644 mode of the containing operand
3646 value of the other parts (F---all bits set)
3648 The constraint matches if the specified part of a constant
3649 has a value different from its other parts.
3652 Memory reference without index register and with short displacement.
3655 Memory reference with index register and short displacement.
3658 Memory reference without index register but with long displacement.
3661 Memory reference with index register and long displacement.
3664 Pointer with short displacement.
3667 Pointer with long displacement.
3670 Shift count operand.
3674 @item Xstormy16---@file{config/stormy16/stormy16.h}
3689 Registers r0 through r7.
3692 Registers r0 and r1.
3698 Registers r8 and r9.
3701 A constant between 0 and 3 inclusive.
3704 A constant that has exactly one bit set.
3707 A constant that has exactly one bit clear.
3710 A constant between 0 and 255 inclusive.
3713 A constant between @minus{}255 and 0 inclusive.
3716 A constant between @minus{}3 and 0 inclusive.
3719 A constant between 1 and 4 inclusive.
3722 A constant between @minus{}4 and @minus{}1 inclusive.
3725 A memory reference that is a stack push.
3728 A memory reference that is a stack pop.
3731 A memory reference that refers to a constant address of known value.
3734 The register indicated by Rx (not implemented yet).
3737 A constant that is not between 2 and 15 inclusive.
3744 @item TI C6X family---@file{config/c6x/constraints.md}
3747 Register file A (A0--A31).
3750 Register file B (B0--B31).
3753 Predicate registers in register file A (A0--A2 on C64X and
3754 higher, A1 and A2 otherwise).
3757 Predicate registers in register file B (B0--B2).
3760 A call-used register in register file B (B0--B9, B16--B31).
3763 Register file A, excluding predicate registers (A3--A31,
3764 plus A0 if not C64X or higher).
3767 Register file B, excluding predicate registers (B3--B31).
3770 Integer constant in the range 0 @dots{} 15.
3773 Integer constant in the range 0 @dots{} 31.
3776 Integer constant in the range @minus{}31 @dots{} 0.
3779 Integer constant in the range @minus{}16 @dots{} 15.
3782 Integer constant that can be the operand of an ADDA or a SUBA insn.
3785 Integer constant in the range 0 @dots{} 65535.
3788 Integer constant in the range @minus{}32768 @dots{} 32767.
3791 Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
3794 Integer constant that is a valid mask for the clr instruction.
3797 Integer constant that is a valid mask for the set instruction.
3800 Memory location with A base register.
3803 Memory location with B base register.
3807 On C64x+ targets, a GP-relative small data reference.
3810 Any kind of @code{SYMBOL_REF}, for use in a call address.
3813 Any kind of immediate operand, unless it matches the S0 constraint.
3816 Memory location with B base register, but not using a long offset.
3819 A memory operand with an address that can't be used in an unaligned access.
3823 Register B14 (aka DP).
3827 @item TILE-Gx---@file{config/tilegx/constraints.md}
3840 Each of these represents a register constraint for an individual
3841 register, from r0 to r10.
3844 Signed 8-bit integer constant.
3847 Signed 16-bit integer constant.
3850 Unsigned 16-bit integer constant.
3853 Integer constant that fits in one signed byte when incremented by one
3854 (@minus{}129 @dots{} 126).
3857 Memory operand. If used together with @samp{<} or @samp{>}, the
3858 operand can have postincrement which requires printing with @samp{%In}
3859 and @samp{%in} on TILE-Gx. For example:
3862 asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));
3866 A bit mask suitable for the BFINS instruction.
3869 Integer constant that is a byte tiled out eight times.
3872 The integer zero constant.
3875 Integer constant that is a sign-extended byte tiled out as four shorts.
3878 Integer constant that fits in one signed byte when incremented
3879 (@minus{}129 @dots{} 126), but excluding -1.
3882 Integer constant that has all 1 bits consecutive and starting at bit 0.
3885 A 16-bit fragment of a got, tls, or pc-relative reference.
3888 Memory operand except postincrement. This is roughly the same as
3889 @samp{m} when not used together with @samp{<} or @samp{>}.
3892 An 8-element vector constant with identical elements.
3895 A 4-element vector constant with identical elements.
3898 The integer constant 0xffffffff.
3901 The integer constant 0xffffffff00000000.
3905 @item TILEPro---@file{config/tilepro/constraints.md}
3918 Each of these represents a register constraint for an individual
3919 register, from r0 to r10.
3922 Signed 8-bit integer constant.
3925 Signed 16-bit integer constant.
3928 Nonzero integer constant with low 16 bits zero.
3931 Integer constant that fits in one signed byte when incremented by one
3932 (@minus{}129 @dots{} 126).
3935 Memory operand. If used together with @samp{<} or @samp{>}, the
3936 operand can have postincrement which requires printing with @samp{%In}
3937 and @samp{%in} on TILEPro. For example:
3940 asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));
3944 A bit mask suitable for the MM instruction.
3947 Integer constant that is a byte tiled out four times.
3950 The integer zero constant.
3953 Integer constant that is a sign-extended byte tiled out as two shorts.
3956 Integer constant that fits in one signed byte when incremented
3957 (@minus{}129 @dots{} 126), but excluding -1.
3960 A symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative
3964 Memory operand except postincrement. This is roughly the same as
3965 @samp{m} when not used together with @samp{<} or @samp{>}.
3968 A 4-element vector constant with identical elements.
3971 A 2-element vector constant with identical elements.
3975 @item Xtensa---@file{config/xtensa/constraints.md}
3978 General-purpose 32-bit register
3981 One-bit boolean register
3984 MAC16 40-bit accumulator register
3987 Signed 12-bit integer constant, for use in MOVI instructions
3990 Signed 8-bit integer constant, for use in ADDI instructions
3993 Integer constant valid for BccI instructions
3996 Unsigned constant valid for BccUI instructions
4003 @node Disable Insn Alternatives
4004 @subsection Disable insn alternatives using the @code{enabled} attribute
4007 There are three insn attributes that may be used to selectively disable
4008 instruction alternatives:
4012 Says whether an alternative is available on the current subtarget.
4014 @item preferred_for_size
4015 Says whether an enabled alternative should be used in code that is
4018 @item preferred_for_speed
4019 Says whether an enabled alternative should be used in code that is
4020 optimized for speed.
4023 All these attributes should use @code{(const_int 1)} to allow an alternative
4024 or @code{(const_int 0)} to disallow it. The attributes must be a static
4025 property of the subtarget; they cannot for example depend on the
4026 current operands, on the current optimization level, on the location
4027 of the insn within the body of a loop, on whether register allocation
4028 has finished, or on the current compiler pass.
4030 The @code{enabled} attribute is a correctness property. It tells GCC to act
4031 as though the disabled alternatives were never defined in the first place.
4032 This is useful when adding new instructions to an existing pattern in
4033 cases where the new instructions are only available for certain cpu
4034 architecture levels (typically mapped to the @code{-march=} command-line
4037 In contrast, the @code{preferred_for_size} and @code{preferred_for_speed}
4038 attributes are strong optimization hints rather than correctness properties.
4039 @code{preferred_for_size} tells GCC which alternatives to consider when
4040 adding or modifying an instruction that GCC wants to optimize for size.
4041 @code{preferred_for_speed} does the same thing for speed. Note that things
4042 like code motion can lead to cases where code optimized for size uses
4043 alternatives that are not preferred for size, and similarly for speed.
4045 Although @code{define_insn}s can in principle specify the @code{enabled}
4046 attribute directly, it is often clearer to have subsiduary attributes
4047 for each architectural feature of interest. The @code{define_insn}s
4048 can then use these subsiduary attributes to say which alternatives
4049 require which features. The example below does this for @code{cpu_facility}.
4051 E.g. the following two patterns could easily be merged using the @code{enabled}
4056 (define_insn "*movdi_old"
4057 [(set (match_operand:DI 0 "register_operand" "=d")
4058 (match_operand:DI 1 "register_operand" " d"))]
4062 (define_insn "*movdi_new"
4063 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4064 (match_operand:DI 1 "register_operand" " d,d,f"))]
4077 (define_insn "*movdi_combined"
4078 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4079 (match_operand:DI 1 "register_operand" " d,d,f"))]
4085 [(set_attr "cpu_facility" "*,new,new")])
4089 with the @code{enabled} attribute defined like this:
4093 (define_attr "cpu_facility" "standard,new" (const_string "standard"))
4095 (define_attr "enabled" ""
4096 (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
4097 (and (eq_attr "cpu_facility" "new")
4098 (ne (symbol_ref "TARGET_NEW") (const_int 0)))
4107 @node Define Constraints
4108 @subsection Defining Machine-Specific Constraints
4109 @cindex defining constraints
4110 @cindex constraints, defining
4112 Machine-specific constraints fall into two categories: register and
4113 non-register constraints. Within the latter category, constraints
4114 which allow subsets of all possible memory or address operands should
4115 be specially marked, to give @code{reload} more information.
4117 Machine-specific constraints can be given names of arbitrary length,
4118 but they must be entirely composed of letters, digits, underscores
4119 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
4120 must begin with a letter or underscore.
4122 In order to avoid ambiguity in operand constraint strings, no
4123 constraint can have a name that begins with any other constraint's
4124 name. For example, if @code{x} is defined as a constraint name,
4125 @code{xy} may not be, and vice versa. As a consequence of this rule,
4126 no constraint may begin with one of the generic constraint letters:
4127 @samp{E F V X g i m n o p r s}.
4129 Register constraints correspond directly to register classes.
4130 @xref{Register Classes}. There is thus not much flexibility in their
4133 @deffn {MD Expression} define_register_constraint name regclass docstring
4134 All three arguments are string constants.
4135 @var{name} is the name of the constraint, as it will appear in
4136 @code{match_operand} expressions. If @var{name} is a multi-letter
4137 constraint its length shall be the same for all constraints starting
4138 with the same letter. @var{regclass} can be either the
4139 name of the corresponding register class (@pxref{Register Classes}),
4140 or a C expression which evaluates to the appropriate register class.
4141 If it is an expression, it must have no side effects, and it cannot
4142 look at the operand. The usual use of expressions is to map some
4143 register constraints to @code{NO_REGS} when the register class
4144 is not available on a given subarchitecture.
4146 @var{docstring} is a sentence documenting the meaning of the
4147 constraint. Docstrings are explained further below.
4150 Non-register constraints are more like predicates: the constraint
4151 definition gives a Boolean expression which indicates whether the
4154 @deffn {MD Expression} define_constraint name docstring exp
4155 The @var{name} and @var{docstring} arguments are the same as for
4156 @code{define_register_constraint}, but note that the docstring comes
4157 immediately after the name for these expressions. @var{exp} is an RTL
4158 expression, obeying the same rules as the RTL expressions in predicate
4159 definitions. @xref{Defining Predicates}, for details. If it
4160 evaluates true, the constraint matches; if it evaluates false, it
4161 doesn't. Constraint expressions should indicate which RTL codes they
4162 might match, just like predicate expressions.
4164 @code{match_test} C expressions have access to the
4165 following variables:
4169 The RTL object defining the operand.
4171 The machine mode of @var{op}.
4173 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
4175 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
4176 @code{const_double}.
4178 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
4179 @code{const_double}.
4181 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
4182 @code{const_double}.
4185 The @var{*val} variables should only be used once another piece of the
4186 expression has verified that @var{op} is the appropriate kind of RTL
4190 Most non-register constraints should be defined with
4191 @code{define_constraint}. The remaining two definition expressions
4192 are only appropriate for constraints that should be handled specially
4193 by @code{reload} if they fail to match.
4195 @deffn {MD Expression} define_memory_constraint name docstring exp
4196 Use this expression for constraints that match a subset of all memory
4197 operands: that is, @code{reload} can make them match by converting the
4198 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
4199 base register (from the register class specified by
4200 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
4202 For example, on the S/390, some instructions do not accept arbitrary
4203 memory references, but only those that do not make use of an index
4204 register. The constraint letter @samp{Q} is defined to represent a
4205 memory address of this type. If @samp{Q} is defined with
4206 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
4207 memory operand, because @code{reload} knows it can simply copy the
4208 memory address into a base register if required. This is analogous to
4209 the way an @samp{o} constraint can handle any memory operand.
4211 The syntax and semantics are otherwise identical to
4212 @code{define_constraint}.
4215 @deffn {MD Expression} define_address_constraint name docstring exp
4216 Use this expression for constraints that match a subset of all address
4217 operands: that is, @code{reload} can make the constraint match by
4218 converting the operand to the form @samp{@w{(reg @var{X})}}, again
4219 with @var{X} a base register.
4221 Constraints defined with @code{define_address_constraint} can only be
4222 used with the @code{address_operand} predicate, or machine-specific
4223 predicates that work the same way. They are treated analogously to
4224 the generic @samp{p} constraint.
4226 The syntax and semantics are otherwise identical to
4227 @code{define_constraint}.
4230 For historical reasons, names beginning with the letters @samp{G H}
4231 are reserved for constraints that match only @code{const_double}s, and
4232 names beginning with the letters @samp{I J K L M N O P} are reserved
4233 for constraints that match only @code{const_int}s. This may change in
4234 the future. For the time being, constraints with these names must be
4235 written in a stylized form, so that @code{genpreds} can tell you did
4240 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
4242 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
4243 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
4246 @c the semicolons line up in the formatted manual
4248 It is fine to use names beginning with other letters for constraints
4249 that match @code{const_double}s or @code{const_int}s.
4251 Each docstring in a constraint definition should be one or more complete
4252 sentences, marked up in Texinfo format. @emph{They are currently unused.}
4253 In the future they will be copied into the GCC manual, in @ref{Machine
4254 Constraints}, replacing the hand-maintained tables currently found in
4255 that section. Also, in the future the compiler may use this to give
4256 more helpful diagnostics when poor choice of @code{asm} constraints
4257 causes a reload failure.
4259 If you put the pseudo-Texinfo directive @samp{@@internal} at the
4260 beginning of a docstring, then (in the future) it will appear only in
4261 the internals manual's version of the machine-specific constraint tables.
4262 Use this for constraints that should not appear in @code{asm} statements.
4264 @node C Constraint Interface
4265 @subsection Testing constraints from C
4266 @cindex testing constraints
4267 @cindex constraints, testing
4269 It is occasionally useful to test a constraint from C code rather than
4270 implicitly via the constraint string in a @code{match_operand}. The
4271 generated file @file{tm_p.h} declares a few interfaces for working
4272 with constraints. At present these are defined for all constraints
4273 except @code{g} (which is equivalent to @code{general_operand}).
4275 Some valid constraint names are not valid C identifiers, so there is a
4276 mangling scheme for referring to them from C@. Constraint names that
4277 do not contain angle brackets or underscores are left unchanged.
4278 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
4279 each @samp{>} with @samp{_g}. Here are some examples:
4281 @c the @c's prevent double blank lines in the printed manual.
4283 @multitable {Original} {Mangled}
4284 @item @strong{Original} @tab @strong{Mangled} @c
4285 @item @code{x} @tab @code{x} @c
4286 @item @code{P42x} @tab @code{P42x} @c
4287 @item @code{P4_x} @tab @code{P4__x} @c
4288 @item @code{P4>x} @tab @code{P4_gx} @c
4289 @item @code{P4>>} @tab @code{P4_g_g} @c
4290 @item @code{P4_g>} @tab @code{P4__g_g} @c
4294 Throughout this section, the variable @var{c} is either a constraint
4295 in the abstract sense, or a constant from @code{enum constraint_num};
4296 the variable @var{m} is a mangled constraint name (usually as part of
4297 a larger identifier).
4299 @deftp Enum constraint_num
4300 For each constraint except @code{g}, there is a corresponding
4301 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
4302 constraint. Functions that take an @code{enum constraint_num} as an
4303 argument expect one of these constants.
4306 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
4307 For each non-register constraint @var{m} except @code{g}, there is
4308 one of these functions; it returns @code{true} if @var{exp} satisfies the
4309 constraint. These functions are only visible if @file{rtl.h} was included
4310 before @file{tm_p.h}.
4313 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
4314 Like the @code{satisfies_constraint_@var{m}} functions, but the
4315 constraint to test is given as an argument, @var{c}. If @var{c}
4316 specifies a register constraint, this function will always return
4320 @deftypefun {enum reg_class} reg_class_for_constraint (enum constraint_num @var{c})
4321 Returns the register class associated with @var{c}. If @var{c} is not
4322 a register constraint, or those registers are not available for the
4323 currently selected subtarget, returns @code{NO_REGS}.
4326 Here is an example use of @code{satisfies_constraint_@var{m}}. In
4327 peephole optimizations (@pxref{Peephole Definitions}), operand
4328 constraint strings are ignored, so if there are relevant constraints,
4329 they must be tested in the C condition. In the example, the
4330 optimization is applied if operand 2 does @emph{not} satisfy the
4331 @samp{K} constraint. (This is a simplified version of a peephole
4332 definition from the i386 machine description.)
4336 [(match_scratch:SI 3 "r")
4337 (set (match_operand:SI 0 "register_operand" "")
4338 (mult:SI (match_operand:SI 1 "memory_operand" "")
4339 (match_operand:SI 2 "immediate_operand" "")))]
4341 "!satisfies_constraint_K (operands[2])"
4343 [(set (match_dup 3) (match_dup 1))
4344 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
4349 @node Standard Names
4350 @section Standard Pattern Names For Generation
4351 @cindex standard pattern names
4352 @cindex pattern names
4353 @cindex names, pattern
4355 Here is a table of the instruction names that are meaningful in the RTL
4356 generation pass of the compiler. Giving one of these names to an
4357 instruction pattern tells the RTL generation pass that it can use the
4358 pattern to accomplish a certain task.
4361 @cindex @code{mov@var{m}} instruction pattern
4362 @item @samp{mov@var{m}}
4363 Here @var{m} stands for a two-letter machine mode name, in lowercase.
4364 This instruction pattern moves data with that machine mode from operand
4365 1 to operand 0. For example, @samp{movsi} moves full-word data.
4367 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
4368 own mode is wider than @var{m}, the effect of this instruction is
4369 to store the specified value in the part of the register that corresponds
4370 to mode @var{m}. Bits outside of @var{m}, but which are within the
4371 same target word as the @code{subreg} are undefined. Bits which are
4372 outside the target word are left unchanged.
4374 This class of patterns is special in several ways. First of all, each
4375 of these names up to and including full word size @emph{must} be defined,
4376 because there is no other way to copy a datum from one place to another.
4377 If there are patterns accepting operands in larger modes,
4378 @samp{mov@var{m}} must be defined for integer modes of those sizes.
4380 Second, these patterns are not used solely in the RTL generation pass.
4381 Even the reload pass can generate move insns to copy values from stack
4382 slots into temporary registers. When it does so, one of the operands is
4383 a hard register and the other is an operand that can need to be reloaded
4387 Therefore, when given such a pair of operands, the pattern must generate
4388 RTL which needs no reloading and needs no temporary registers---no
4389 registers other than the operands. For example, if you support the
4390 pattern with a @code{define_expand}, then in such a case the
4391 @code{define_expand} mustn't call @code{force_reg} or any other such
4392 function which might generate new pseudo registers.
4394 This requirement exists even for subword modes on a RISC machine where
4395 fetching those modes from memory normally requires several insns and
4396 some temporary registers.
4398 @findex change_address
4399 During reload a memory reference with an invalid address may be passed
4400 as an operand. Such an address will be replaced with a valid address
4401 later in the reload pass. In this case, nothing may be done with the
4402 address except to use it as it stands. If it is copied, it will not be
4403 replaced with a valid address. No attempt should be made to make such
4404 an address into a valid address and no routine (such as
4405 @code{change_address}) that will do so may be called. Note that
4406 @code{general_operand} will fail when applied to such an address.
4408 @findex reload_in_progress
4409 The global variable @code{reload_in_progress} (which must be explicitly
4410 declared if required) can be used to determine whether such special
4411 handling is required.
4413 The variety of operands that have reloads depends on the rest of the
4414 machine description, but typically on a RISC machine these can only be
4415 pseudo registers that did not get hard registers, while on other
4416 machines explicit memory references will get optional reloads.
4418 If a scratch register is required to move an object to or from memory,
4419 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
4421 If there are cases which need scratch registers during or after reload,
4422 you must provide an appropriate secondary_reload target hook.
4424 @findex can_create_pseudo_p
4425 The macro @code{can_create_pseudo_p} can be used to determine if it
4426 is unsafe to create new pseudo registers. If this variable is nonzero, then
4427 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
4429 The constraints on a @samp{mov@var{m}} must permit moving any hard
4430 register to any other hard register provided that
4431 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
4432 @code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value
4435 It is obligatory to support floating point @samp{mov@var{m}}
4436 instructions into and out of any registers that can hold fixed point
4437 values, because unions and structures (which have modes @code{SImode} or
4438 @code{DImode}) can be in those registers and they may have floating
4441 There may also be a need to support fixed point @samp{mov@var{m}}
4442 instructions in and out of floating point registers. Unfortunately, I
4443 have forgotten why this was so, and I don't know whether it is still
4444 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
4445 floating point registers, then the constraints of the fixed point
4446 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
4447 reload into a floating point register.
4449 @cindex @code{reload_in} instruction pattern
4450 @cindex @code{reload_out} instruction pattern
4451 @item @samp{reload_in@var{m}}
4452 @itemx @samp{reload_out@var{m}}
4453 These named patterns have been obsoleted by the target hook
4454 @code{secondary_reload}.
4456 Like @samp{mov@var{m}}, but used when a scratch register is required to
4457 move between operand 0 and operand 1. Operand 2 describes the scratch
4458 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
4459 macro in @pxref{Register Classes}.
4461 There are special restrictions on the form of the @code{match_operand}s
4462 used in these patterns. First, only the predicate for the reload
4463 operand is examined, i.e., @code{reload_in} examines operand 1, but not
4464 the predicates for operand 0 or 2. Second, there may be only one
4465 alternative in the constraints. Third, only a single register class
4466 letter may be used for the constraint; subsequent constraint letters
4467 are ignored. As a special exception, an empty constraint string
4468 matches the @code{ALL_REGS} register class. This may relieve ports
4469 of the burden of defining an @code{ALL_REGS} constraint letter just
4472 @cindex @code{movstrict@var{m}} instruction pattern
4473 @item @samp{movstrict@var{m}}
4474 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
4475 with mode @var{m} of a register whose natural mode is wider,
4476 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
4477 any of the register except the part which belongs to mode @var{m}.
4479 @cindex @code{movmisalign@var{m}} instruction pattern
4480 @item @samp{movmisalign@var{m}}
4481 This variant of a move pattern is designed to load or store a value
4482 from a memory address that is not naturally aligned for its mode.
4483 For a store, the memory will be in operand 0; for a load, the memory
4484 will be in operand 1. The other operand is guaranteed not to be a
4485 memory, so that it's easy to tell whether this is a load or store.
4487 This pattern is used by the autovectorizer, and when expanding a
4488 @code{MISALIGNED_INDIRECT_REF} expression.
4490 @cindex @code{load_multiple} instruction pattern
4491 @item @samp{load_multiple}
4492 Load several consecutive memory locations into consecutive registers.
4493 Operand 0 is the first of the consecutive registers, operand 1
4494 is the first memory location, and operand 2 is a constant: the
4495 number of consecutive registers.
4497 Define this only if the target machine really has such an instruction;
4498 do not define this if the most efficient way of loading consecutive
4499 registers from memory is to do them one at a time.
4501 On some machines, there are restrictions as to which consecutive
4502 registers can be stored into memory, such as particular starting or
4503 ending register numbers or only a range of valid counts. For those
4504 machines, use a @code{define_expand} (@pxref{Expander Definitions})
4505 and make the pattern fail if the restrictions are not met.
4507 Write the generated insn as a @code{parallel} with elements being a
4508 @code{set} of one register from the appropriate memory location (you may
4509 also need @code{use} or @code{clobber} elements). Use a
4510 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
4511 @file{rs6000.md} for examples of the use of this insn pattern.
4513 @cindex @samp{store_multiple} instruction pattern
4514 @item @samp{store_multiple}
4515 Similar to @samp{load_multiple}, but store several consecutive registers
4516 into consecutive memory locations. Operand 0 is the first of the
4517 consecutive memory locations, operand 1 is the first register, and
4518 operand 2 is a constant: the number of consecutive registers.
4520 @cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
4521 @item @samp{vec_load_lanes@var{m}@var{n}}
4522 Perform an interleaved load of several vectors from memory operand 1
4523 into register operand 0. Both operands have mode @var{m}. The register
4524 operand is viewed as holding consecutive vectors of mode @var{n},
4525 while the memory operand is a flat array that contains the same number
4526 of elements. The operation is equivalent to:
4529 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4530 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4531 for (i = 0; i < c; i++)
4532 operand0[i][j] = operand1[j * c + i];
4535 For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
4536 from memory into a register of mode @samp{TI}@. The register
4537 contains two consecutive vectors of mode @samp{V4HI}@.
4539 This pattern can only be used if:
4541 TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
4543 is true. GCC assumes that, if a target supports this kind of
4544 instruction for some mode @var{n}, it also supports unaligned
4545 loads for vectors of mode @var{n}.
4547 @cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
4548 @item @samp{vec_store_lanes@var{m}@var{n}}
4549 Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
4550 and register operands reversed. That is, the instruction is
4554 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4555 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4556 for (i = 0; i < c; i++)
4557 operand0[j * c + i] = operand1[i][j];
4560 for a memory operand 0 and register operand 1.
4562 @cindex @code{vec_set@var{m}} instruction pattern
4563 @item @samp{vec_set@var{m}}
4564 Set given field in the vector value. Operand 0 is the vector to modify,
4565 operand 1 is new value of field and operand 2 specify the field index.
4567 @cindex @code{vec_extract@var{m}} instruction pattern
4568 @item @samp{vec_extract@var{m}}
4569 Extract given field from the vector value. Operand 1 is the vector, operand 2
4570 specify field index and operand 0 place to store value into.
4572 @cindex @code{vec_init@var{m}} instruction pattern
4573 @item @samp{vec_init@var{m}}
4574 Initialize the vector to given values. Operand 0 is the vector to initialize
4575 and operand 1 is parallel containing values for individual fields.
4577 @cindex @code{vcond@var{m}@var{n}} instruction pattern
4578 @item @samp{vcond@var{m}@var{n}}
4579 Output a conditional vector move. Operand 0 is the destination to
4580 receive a combination of operand 1 and operand 2, which are of mode @var{m},
4581 dependent on the outcome of the predicate in operand 3 which is a
4582 vector comparison with operands of mode @var{n} in operands 4 and 5. The
4583 modes @var{m} and @var{n} should have the same size. Operand 0
4584 will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
4585 where @var{msk} is computed by element-wise evaluation of the vector
4586 comparison with a truth value of all-ones and a false value of all-zeros.
4588 @cindex @code{vec_perm@var{m}} instruction pattern
4589 @item @samp{vec_perm@var{m}}
4590 Output a (variable) vector permutation. Operand 0 is the destination
4591 to receive elements from operand 1 and operand 2, which are of mode
4592 @var{m}. Operand 3 is the @dfn{selector}. It is an integral mode
4593 vector of the same width and number of elements as mode @var{m}.
4595 The input elements are numbered from 0 in operand 1 through
4596 @math{2*@var{N}-1} in operand 2. The elements of the selector must
4597 be computed modulo @math{2*@var{N}}. Note that if
4598 @code{rtx_equal_p(operand1, operand2)}, this can be implemented
4599 with just operand 1 and selector elements modulo @var{N}.
4601 In order to make things easy for a number of targets, if there is no
4602 @samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q}
4603 where @var{q} is a vector of @code{QImode} of the same width as @var{m},
4604 the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to
4607 @cindex @code{vec_perm_const@var{m}} instruction pattern
4608 @item @samp{vec_perm_const@var{m}}
4609 Like @samp{vec_perm} except that the permutation is a compile-time
4610 constant. That is, operand 3, the @dfn{selector}, is a @code{CONST_VECTOR}.
4612 Some targets cannot perform a permutation with a variable selector,
4613 but can efficiently perform a constant permutation. Further, the
4614 target hook @code{vec_perm_ok} is queried to determine if the
4615 specific constant permutation is available efficiently; the named
4616 pattern is never expanded without @code{vec_perm_ok} returning true.
4618 There is no need for a target to supply both @samp{vec_perm@var{m}}
4619 and @samp{vec_perm_const@var{m}} if the former can trivially implement
4620 the operation with, say, the vector constant loaded into a register.
4622 @cindex @code{push@var{m}1} instruction pattern
4623 @item @samp{push@var{m}1}
4624 Output a push instruction. Operand 0 is value to push. Used only when
4625 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
4626 missing and in such case an @code{mov} expander is used instead, with a
4627 @code{MEM} expression forming the push operation. The @code{mov} expander
4628 method is deprecated.
4630 @cindex @code{add@var{m}3} instruction pattern
4631 @item @samp{add@var{m}3}
4632 Add operand 2 and operand 1, storing the result in operand 0. All operands
4633 must have mode @var{m}. This can be used even on two-address machines, by
4634 means of constraints requiring operands 1 and 0 to be the same location.
4636 @cindex @code{addptr@var{m}3} instruction pattern
4637 @item @samp{addptr@var{m}3}
4638 Like @code{add@var{m}3} but is guaranteed to only be used for address
4639 calculations. The expanded code is not allowed to clobber the
4640 condition code. It only needs to be defined if @code{add@var{m}3}
4641 sets the condition code. If adds used for address calculations and
4642 normal adds are not compatible it is required to expand a distinct
4643 pattern (e.g. using an unspec). The pattern is used by LRA to emit
4644 address calculations. @code{add@var{m}3} is used if
4645 @code{addptr@var{m}3} is not defined.
4647 @cindex @code{ssadd@var{m}3} instruction pattern
4648 @cindex @code{usadd@var{m}3} instruction pattern
4649 @cindex @code{sub@var{m}3} instruction pattern
4650 @cindex @code{sssub@var{m}3} instruction pattern
4651 @cindex @code{ussub@var{m}3} instruction pattern
4652 @cindex @code{mul@var{m}3} instruction pattern
4653 @cindex @code{ssmul@var{m}3} instruction pattern
4654 @cindex @code{usmul@var{m}3} instruction pattern
4655 @cindex @code{div@var{m}3} instruction pattern
4656 @cindex @code{ssdiv@var{m}3} instruction pattern
4657 @cindex @code{udiv@var{m}3} instruction pattern
4658 @cindex @code{usdiv@var{m}3} instruction pattern
4659 @cindex @code{mod@var{m}3} instruction pattern
4660 @cindex @code{umod@var{m}3} instruction pattern
4661 @cindex @code{umin@var{m}3} instruction pattern
4662 @cindex @code{umax@var{m}3} instruction pattern
4663 @cindex @code{and@var{m}3} instruction pattern
4664 @cindex @code{ior@var{m}3} instruction pattern
4665 @cindex @code{xor@var{m}3} instruction pattern
4666 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
4667 @itemx @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
4668 @itemx @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
4669 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
4670 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
4671 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
4672 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
4673 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
4674 Similar, for other arithmetic operations.
4676 @cindex @code{fma@var{m}4} instruction pattern
4677 @item @samp{fma@var{m}4}
4678 Multiply operand 2 and operand 1, then add operand 3, storing the
4679 result in operand 0 without doing an intermediate rounding step. All
4680 operands must have mode @var{m}. This pattern is used to implement
4681 the @code{fma}, @code{fmaf}, and @code{fmal} builtin functions from
4682 the ISO C99 standard.
4684 @cindex @code{fms@var{m}4} instruction pattern
4685 @item @samp{fms@var{m}4}
4686 Like @code{fma@var{m}4}, except operand 3 subtracted from the
4687 product instead of added to the product. This is represented
4691 (fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3}))
4694 @cindex @code{fnma@var{m}4} instruction pattern
4695 @item @samp{fnma@var{m}4}
4696 Like @code{fma@var{m}4} except that the intermediate product
4697 is negated before being added to operand 3. This is represented
4701 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3})
4704 @cindex @code{fnms@var{m}4} instruction pattern
4705 @item @samp{fnms@var{m}4}
4706 Like @code{fms@var{m}4} except that the intermediate product
4707 is negated before subtracting operand 3. This is represented
4711 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3}))
4714 @cindex @code{min@var{m}3} instruction pattern
4715 @cindex @code{max@var{m}3} instruction pattern
4716 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
4717 Signed minimum and maximum operations. When used with floating point,
4718 if both operands are zeros, or if either operand is @code{NaN}, then
4719 it is unspecified which of the two operands is returned as the result.
4721 @cindex @code{reduc_smin_@var{m}} instruction pattern
4722 @cindex @code{reduc_smax_@var{m}} instruction pattern
4723 @item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
4724 Find the signed minimum/maximum of the elements of a vector. The vector is
4725 operand 1, and the result is stored in the least significant bits of
4726 operand 0 (also a vector). The output and input vector should have the same
4727 modes. These are legacy optabs, and platforms should prefer to implement
4728 @samp{reduc_smin_scal_@var{m}} and @samp{reduc_smax_scal_@var{m}}.
4730 @cindex @code{reduc_umin_@var{m}} instruction pattern
4731 @cindex @code{reduc_umax_@var{m}} instruction pattern
4732 @item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
4733 Find the unsigned minimum/maximum of the elements of a vector. The vector is
4734 operand 1, and the result is stored in the least significant bits of
4735 operand 0 (also a vector). The output and input vector should have the same
4736 modes. These are legacy optabs, and platforms should prefer to implement
4737 @samp{reduc_umin_scal_@var{m}} and @samp{reduc_umax_scal_@var{m}}.
4739 @cindex @code{reduc_splus_@var{m}} instruction pattern
4740 @cindex @code{reduc_uplus_@var{m}} instruction pattern
4741 @item @samp{reduc_splus_@var{m}}, @samp{reduc_uplus_@var{m}}
4742 Compute the sum of the signed/unsigned elements of a vector. The vector is
4743 operand 1, and the result is stored in the least significant bits of operand 0
4744 (also a vector). The output and input vector should have the same modes.
4745 These are legacy optabs, and platforms should prefer to implement
4746 @samp{reduc_plus_scal_@var{m}}.
4748 @cindex @code{reduc_smin_scal_@var{m}} instruction pattern
4749 @cindex @code{reduc_smax_scal_@var{m}} instruction pattern
4750 @item @samp{reduc_smin_scal_@var{m}}, @samp{reduc_smax_scal_@var{m}}
4751 Find the signed minimum/maximum of the elements of a vector. The vector is
4752 operand 1, and operand 0 is the scalar result, with mode equal to the mode of
4753 the elements of the input vector.
4755 @cindex @code{reduc_umin_scal_@var{m}} instruction pattern
4756 @cindex @code{reduc_umax_scal_@var{m}} instruction pattern
4757 @item @samp{reduc_umin_scal_@var{m}}, @samp{reduc_umax_scal_@var{m}}
4758 Find the unsigned minimum/maximum of the elements of a vector. The vector is
4759 operand 1, and operand 0 is the scalar result, with mode equal to the mode of
4760 the elements of the input vector.
4762 @cindex @code{reduc_plus_scal_@var{m}} instruction pattern
4763 @item @samp{reduc_plus_scal_@var{m}}
4764 Compute the sum of the elements of a vector. The vector is operand 1, and
4765 operand 0 is the scalar result, with mode equal to the mode of the elements of
4768 @cindex @code{sdot_prod@var{m}} instruction pattern
4769 @item @samp{sdot_prod@var{m}}
4770 @cindex @code{udot_prod@var{m}} instruction pattern
4771 @itemx @samp{udot_prod@var{m}}
4772 Compute the sum of the products of two signed/unsigned elements.
4773 Operand 1 and operand 2 are of the same mode. Their product, which is of a
4774 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
4775 wider than the mode of the product. The result is placed in operand 0, which
4776 is of the same mode as operand 3.
4778 @cindex @code{ssad@var{m}} instruction pattern
4779 @item @samp{ssad@var{m}}
4780 @cindex @code{usad@var{m}} instruction pattern
4781 @item @samp{usad@var{m}}
4782 Compute the sum of absolute differences of two signed/unsigned elements.
4783 Operand 1 and operand 2 are of the same mode. Their absolute difference, which
4784 is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode
4785 equal or wider than the mode of the absolute difference. The result is placed
4786 in operand 0, which is of the same mode as operand 3.
4788 @cindex @code{ssum_widen@var{m3}} instruction pattern
4789 @item @samp{ssum_widen@var{m3}}
4790 @cindex @code{usum_widen@var{m3}} instruction pattern
4791 @itemx @samp{usum_widen@var{m3}}
4792 Operands 0 and 2 are of the same mode, which is wider than the mode of
4793 operand 1. Add operand 1 to operand 2 and place the widened result in
4794 operand 0. (This is used express accumulation of elements into an accumulator
4797 @cindex @code{vec_shr_@var{m}} instruction pattern
4798 @item @samp{vec_shr_@var{m}}
4799 Whole vector right shift in bits, i.e. towards element 0.
4800 Operand 1 is a vector to be shifted.
4801 Operand 2 is an integer shift amount in bits.
4802 Operand 0 is where the resulting shifted vector is stored.
4803 The output and input vectors should have the same modes.
4805 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
4806 @item @samp{vec_pack_trunc_@var{m}}
4807 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4808 are vectors of the same mode having N integral or floating point elements
4809 of size S@. Operand 0 is the resulting vector in which 2*N elements of
4810 size N/2 are concatenated after narrowing them down using truncation.
4812 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
4813 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
4814 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
4815 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4816 are vectors of the same mode having N integral elements of size S.
4817 Operand 0 is the resulting vector in which the elements of the two input
4818 vectors are concatenated after narrowing them down using signed/unsigned
4819 saturating arithmetic.
4821 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
4822 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
4823 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
4824 Narrow, convert to signed/unsigned integral type and merge the elements
4825 of two vectors. Operands 1 and 2 are vectors of the same mode having N
4826 floating point elements of size S@. Operand 0 is the resulting vector
4827 in which 2*N elements of size N/2 are concatenated.
4829 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
4830 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
4831 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
4832 Extract and widen (promote) the high/low part of a vector of signed
4833 integral or floating point elements. The input vector (operand 1) has N
4834 elements of size S@. Widen (promote) the high/low elements of the vector
4835 using signed or floating point extension and place the resulting N/2
4836 values of size 2*S in the output vector (operand 0).
4838 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
4839 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
4840 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
4841 Extract and widen (promote) the high/low part of a vector of unsigned
4842 integral elements. The input vector (operand 1) has N elements of size S.
4843 Widen (promote) the high/low elements of the vector using zero extension and
4844 place the resulting N/2 values of size 2*S in the output vector (operand 0).
4846 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
4847 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
4848 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
4849 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
4850 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
4851 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
4852 Extract, convert to floating point type and widen the high/low part of a
4853 vector of signed/unsigned integral elements. The input vector (operand 1)
4854 has N elements of size S@. Convert the high/low elements of the vector using
4855 floating point conversion and place the resulting N/2 values of size 2*S in
4856 the output vector (operand 0).
4858 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
4859 @cindex @code{vec_widen_umult_lo_@var{m}} instruction pattern
4860 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
4861 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
4862 @cindex @code{vec_widen_umult_even_@var{m}} instruction pattern
4863 @cindex @code{vec_widen_umult_odd_@var{m}} instruction pattern
4864 @cindex @code{vec_widen_smult_even_@var{m}} instruction pattern
4865 @cindex @code{vec_widen_smult_odd_@var{m}} instruction pattern
4866 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
4867 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
4868 @itemx @samp{vec_widen_umult_even_@var{m}}, @samp{vec_widen_umult_odd_@var{m}}
4869 @itemx @samp{vec_widen_smult_even_@var{m}}, @samp{vec_widen_smult_odd_@var{m}}
4870 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
4871 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
4872 or even/odd elements of the two vectors, and put the N/2 products of size 2*S
4873 in the output vector (operand 0). A target shouldn't implement even/odd pattern
4874 pair if it is less efficient than lo/hi one.
4876 @cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern
4877 @cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern
4878 @cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern
4879 @cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern
4880 @item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}}
4881 @itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}}
4882 Signed/Unsigned widening shift left. The first input (operand 1) is a vector
4883 with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift
4884 the high/low elements of operand 1, and put the N/2 results of size 2*S in the
4885 output vector (operand 0).
4887 @cindex @code{mulhisi3} instruction pattern
4888 @item @samp{mulhisi3}
4889 Multiply operands 1 and 2, which have mode @code{HImode}, and store
4890 a @code{SImode} product in operand 0.
4892 @cindex @code{mulqihi3} instruction pattern
4893 @cindex @code{mulsidi3} instruction pattern
4894 @item @samp{mulqihi3}, @samp{mulsidi3}
4895 Similar widening-multiplication instructions of other widths.
4897 @cindex @code{umulqihi3} instruction pattern
4898 @cindex @code{umulhisi3} instruction pattern
4899 @cindex @code{umulsidi3} instruction pattern
4900 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
4901 Similar widening-multiplication instructions that do unsigned
4904 @cindex @code{usmulqihi3} instruction pattern
4905 @cindex @code{usmulhisi3} instruction pattern
4906 @cindex @code{usmulsidi3} instruction pattern
4907 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
4908 Similar widening-multiplication instructions that interpret the first
4909 operand as unsigned and the second operand as signed, then do a signed
4912 @cindex @code{smul@var{m}3_highpart} instruction pattern
4913 @item @samp{smul@var{m}3_highpart}
4914 Perform a signed multiplication of operands 1 and 2, which have mode
4915 @var{m}, and store the most significant half of the product in operand 0.
4916 The least significant half of the product is discarded.
4918 @cindex @code{umul@var{m}3_highpart} instruction pattern
4919 @item @samp{umul@var{m}3_highpart}
4920 Similar, but the multiplication is unsigned.
4922 @cindex @code{madd@var{m}@var{n}4} instruction pattern
4923 @item @samp{madd@var{m}@var{n}4}
4924 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
4925 operand 3, and store the result in operand 0. Operands 1 and 2
4926 have mode @var{m} and operands 0 and 3 have mode @var{n}.
4927 Both modes must be integer or fixed-point modes and @var{n} must be twice
4928 the size of @var{m}.
4930 In other words, @code{madd@var{m}@var{n}4} is like
4931 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
4933 These instructions are not allowed to @code{FAIL}.
4935 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
4936 @item @samp{umadd@var{m}@var{n}4}
4937 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
4938 operands instead of sign-extending them.
4940 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
4941 @item @samp{ssmadd@var{m}@var{n}4}
4942 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
4945 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
4946 @item @samp{usmadd@var{m}@var{n}4}
4947 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
4948 unsigned-saturating.
4950 @cindex @code{msub@var{m}@var{n}4} instruction pattern
4951 @item @samp{msub@var{m}@var{n}4}
4952 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
4953 result from operand 3, and store the result in operand 0. Operands 1 and 2
4954 have mode @var{m} and operands 0 and 3 have mode @var{n}.
4955 Both modes must be integer or fixed-point modes and @var{n} must be twice
4956 the size of @var{m}.
4958 In other words, @code{msub@var{m}@var{n}4} is like
4959 @code{mul@var{m}@var{n}3} except that it also subtracts the result
4962 These instructions are not allowed to @code{FAIL}.
4964 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
4965 @item @samp{umsub@var{m}@var{n}4}
4966 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
4967 operands instead of sign-extending them.
4969 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
4970 @item @samp{ssmsub@var{m}@var{n}4}
4971 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
4974 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
4975 @item @samp{usmsub@var{m}@var{n}4}
4976 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
4977 unsigned-saturating.
4979 @cindex @code{divmod@var{m}4} instruction pattern
4980 @item @samp{divmod@var{m}4}
4981 Signed division that produces both a quotient and a remainder.
4982 Operand 1 is divided by operand 2 to produce a quotient stored
4983 in operand 0 and a remainder stored in operand 3.
4985 For machines with an instruction that produces both a quotient and a
4986 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
4987 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
4988 allows optimization in the relatively common case when both the quotient
4989 and remainder are computed.
4991 If an instruction that just produces a quotient or just a remainder
4992 exists and is more efficient than the instruction that produces both,
4993 write the output routine of @samp{divmod@var{m}4} to call
4994 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
4995 quotient or remainder and generate the appropriate instruction.
4997 @cindex @code{udivmod@var{m}4} instruction pattern
4998 @item @samp{udivmod@var{m}4}
4999 Similar, but does unsigned division.
5001 @anchor{shift patterns}
5002 @cindex @code{ashl@var{m}3} instruction pattern
5003 @cindex @code{ssashl@var{m}3} instruction pattern
5004 @cindex @code{usashl@var{m}3} instruction pattern
5005 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
5006 Arithmetic-shift operand 1 left by a number of bits specified by operand
5007 2, and store the result in operand 0. Here @var{m} is the mode of
5008 operand 0 and operand 1; operand 2's mode is specified by the
5009 instruction pattern, and the compiler will convert the operand to that
5010 mode before generating the instruction. The meaning of out-of-range shift
5011 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
5012 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
5014 @cindex @code{ashr@var{m}3} instruction pattern
5015 @cindex @code{lshr@var{m}3} instruction pattern
5016 @cindex @code{rotl@var{m}3} instruction pattern
5017 @cindex @code{rotr@var{m}3} instruction pattern
5018 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
5019 Other shift and rotate instructions, analogous to the
5020 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
5022 @cindex @code{vashl@var{m}3} instruction pattern
5023 @cindex @code{vashr@var{m}3} instruction pattern
5024 @cindex @code{vlshr@var{m}3} instruction pattern
5025 @cindex @code{vrotl@var{m}3} instruction pattern
5026 @cindex @code{vrotr@var{m}3} instruction pattern
5027 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
5028 Vector shift and rotate instructions that take vectors as operand 2
5029 instead of a scalar type.
5031 @cindex @code{bswap@var{m}2} instruction pattern
5032 @item @samp{bswap@var{m}2}
5033 Reverse the order of bytes of operand 1 and store the result in operand 0.
5035 @cindex @code{neg@var{m}2} instruction pattern
5036 @cindex @code{ssneg@var{m}2} instruction pattern
5037 @cindex @code{usneg@var{m}2} instruction pattern
5038 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
5039 Negate operand 1 and store the result in operand 0.
5041 @cindex @code{abs@var{m}2} instruction pattern
5042 @item @samp{abs@var{m}2}
5043 Store the absolute value of operand 1 into operand 0.
5045 @cindex @code{sqrt@var{m}2} instruction pattern
5046 @item @samp{sqrt@var{m}2}
5047 Store the square root of operand 1 into operand 0.
5049 The @code{sqrt} built-in function of C always uses the mode which
5050 corresponds to the C data type @code{double} and the @code{sqrtf}
5051 built-in function uses the mode which corresponds to the C data
5054 @cindex @code{fmod@var{m}3} instruction pattern
5055 @item @samp{fmod@var{m}3}
5056 Store the remainder of dividing operand 1 by operand 2 into
5057 operand 0, rounded towards zero to an integer.
5059 The @code{fmod} built-in function of C always uses the mode which
5060 corresponds to the C data type @code{double} and the @code{fmodf}
5061 built-in function uses the mode which corresponds to the C data
5064 @cindex @code{remainder@var{m}3} instruction pattern
5065 @item @samp{remainder@var{m}3}
5066 Store the remainder of dividing operand 1 by operand 2 into
5067 operand 0, rounded to the nearest integer.
5069 The @code{remainder} built-in function of C always uses the mode
5070 which corresponds to the C data type @code{double} and the
5071 @code{remainderf} built-in function uses the mode which corresponds
5072 to the C data type @code{float}.
5074 @cindex @code{cos@var{m}2} instruction pattern
5075 @item @samp{cos@var{m}2}
5076 Store the cosine of operand 1 into operand 0.
5078 The @code{cos} built-in function of C always uses the mode which
5079 corresponds to the C data type @code{double} and the @code{cosf}
5080 built-in function uses the mode which corresponds to the C data
5083 @cindex @code{sin@var{m}2} instruction pattern
5084 @item @samp{sin@var{m}2}
5085 Store the sine of operand 1 into operand 0.
5087 The @code{sin} built-in function of C always uses the mode which
5088 corresponds to the C data type @code{double} and the @code{sinf}
5089 built-in function uses the mode which corresponds to the C data
5092 @cindex @code{sincos@var{m}3} instruction pattern
5093 @item @samp{sincos@var{m}3}
5094 Store the cosine of operand 2 into operand 0 and the sine of
5095 operand 2 into operand 1.
5097 The @code{sin} and @code{cos} built-in functions of C always use the
5098 mode which corresponds to the C data type @code{double} and the
5099 @code{sinf} and @code{cosf} built-in function use the mode which
5100 corresponds to the C data type @code{float}.
5101 Targets that can calculate the sine and cosine simultaneously can
5102 implement this pattern as opposed to implementing individual
5103 @code{sin@var{m}2} and @code{cos@var{m}2} patterns. The @code{sin}
5104 and @code{cos} built-in functions will then be expanded to the
5105 @code{sincos@var{m}3} pattern, with one of the output values
5108 @cindex @code{exp@var{m}2} instruction pattern
5109 @item @samp{exp@var{m}2}
5110 Store the exponential of operand 1 into operand 0.
5112 The @code{exp} built-in function of C always uses the mode which
5113 corresponds to the C data type @code{double} and the @code{expf}
5114 built-in function uses the mode which corresponds to the C data
5117 @cindex @code{log@var{m}2} instruction pattern
5118 @item @samp{log@var{m}2}
5119 Store the natural logarithm of operand 1 into operand 0.
5121 The @code{log} built-in function of C always uses the mode which
5122 corresponds to the C data type @code{double} and the @code{logf}
5123 built-in function uses the mode which corresponds to the C data
5126 @cindex @code{pow@var{m}3} instruction pattern
5127 @item @samp{pow@var{m}3}
5128 Store the value of operand 1 raised to the exponent operand 2
5131 The @code{pow} built-in function of C always uses the mode which
5132 corresponds to the C data type @code{double} and the @code{powf}
5133 built-in function uses the mode which corresponds to the C data
5136 @cindex @code{atan2@var{m}3} instruction pattern
5137 @item @samp{atan2@var{m}3}
5138 Store the arc tangent (inverse tangent) of operand 1 divided by
5139 operand 2 into operand 0, using the signs of both arguments to
5140 determine the quadrant of the result.
5142 The @code{atan2} built-in function of C always uses the mode which
5143 corresponds to the C data type @code{double} and the @code{atan2f}
5144 built-in function uses the mode which corresponds to the C data
5147 @cindex @code{floor@var{m}2} instruction pattern
5148 @item @samp{floor@var{m}2}
5149 Store the largest integral value not greater than argument.
5151 The @code{floor} built-in function of C always uses the mode which
5152 corresponds to the C data type @code{double} and the @code{floorf}
5153 built-in function uses the mode which corresponds to the C data
5156 @cindex @code{btrunc@var{m}2} instruction pattern
5157 @item @samp{btrunc@var{m}2}
5158 Store the argument rounded to integer towards zero.
5160 The @code{trunc} built-in function of C always uses the mode which
5161 corresponds to the C data type @code{double} and the @code{truncf}
5162 built-in function uses the mode which corresponds to the C data
5165 @cindex @code{round@var{m}2} instruction pattern
5166 @item @samp{round@var{m}2}
5167 Store the argument rounded to integer away from zero.
5169 The @code{round} built-in function of C always uses the mode which
5170 corresponds to the C data type @code{double} and the @code{roundf}
5171 built-in function uses the mode which corresponds to the C data
5174 @cindex @code{ceil@var{m}2} instruction pattern
5175 @item @samp{ceil@var{m}2}
5176 Store the argument rounded to integer away from zero.
5178 The @code{ceil} built-in function of C always uses the mode which
5179 corresponds to the C data type @code{double} and the @code{ceilf}
5180 built-in function uses the mode which corresponds to the C data
5183 @cindex @code{nearbyint@var{m}2} instruction pattern
5184 @item @samp{nearbyint@var{m}2}
5185 Store the argument rounded according to the default rounding mode
5187 The @code{nearbyint} built-in function of C always uses the mode which
5188 corresponds to the C data type @code{double} and the @code{nearbyintf}
5189 built-in function uses the mode which corresponds to the C data
5192 @cindex @code{rint@var{m}2} instruction pattern
5193 @item @samp{rint@var{m}2}
5194 Store the argument rounded according to the default rounding mode and
5195 raise the inexact exception when the result differs in value from
5198 The @code{rint} built-in function of C always uses the mode which
5199 corresponds to the C data type @code{double} and the @code{rintf}
5200 built-in function uses the mode which corresponds to the C data
5203 @cindex @code{lrint@var{m}@var{n}2}
5204 @item @samp{lrint@var{m}@var{n}2}
5205 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5206 point mode @var{n} as a signed number according to the current
5207 rounding mode and store in operand 0 (which has mode @var{n}).
5209 @cindex @code{lround@var{m}@var{n}2}
5210 @item @samp{lround@var{m}@var{n}2}
5211 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5212 point mode @var{n} as a signed number rounding to nearest and away
5213 from zero and store in operand 0 (which has mode @var{n}).
5215 @cindex @code{lfloor@var{m}@var{n}2}
5216 @item @samp{lfloor@var{m}@var{n}2}
5217 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5218 point mode @var{n} as a signed number rounding down and store in
5219 operand 0 (which has mode @var{n}).
5221 @cindex @code{lceil@var{m}@var{n}2}
5222 @item @samp{lceil@var{m}@var{n}2}
5223 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5224 point mode @var{n} as a signed number rounding up and store in
5225 operand 0 (which has mode @var{n}).
5227 @cindex @code{copysign@var{m}3} instruction pattern
5228 @item @samp{copysign@var{m}3}
5229 Store a value with the magnitude of operand 1 and the sign of operand
5232 The @code{copysign} built-in function of C always uses the mode which
5233 corresponds to the C data type @code{double} and the @code{copysignf}
5234 built-in function uses the mode which corresponds to the C data
5237 @cindex @code{ffs@var{m}2} instruction pattern
5238 @item @samp{ffs@var{m}2}
5239 Store into operand 0 one plus the index of the least significant 1-bit
5240 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
5241 of operand 0; operand 1's mode is specified by the instruction
5242 pattern, and the compiler will convert the operand to that mode before
5243 generating the instruction.
5245 The @code{ffs} built-in function of C always uses the mode which
5246 corresponds to the C data type @code{int}.
5248 @cindex @code{clrsb@var{m}2} instruction pattern
5249 @item @samp{clrsb@var{m}2}
5250 Count leading redundant sign bits.
5251 Store into operand 0 the number of redundant sign bits in operand 1, starting
5252 at the most significant bit position.
5253 A redundant sign bit is defined as any sign bit after the first. As such,
5254 this count will be one less than the count of leading sign bits.
5256 @cindex @code{clz@var{m}2} instruction pattern
5257 @item @samp{clz@var{m}2}
5258 Store into operand 0 the number of leading 0-bits in operand 1, starting
5259 at the most significant bit position. If operand 1 is 0, the
5260 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
5261 the result is undefined or has a useful value.
5262 @var{m} is the mode of operand 0; operand 1's mode is
5263 specified by the instruction pattern, and the compiler will convert the
5264 operand to that mode before generating the instruction.
5266 @cindex @code{ctz@var{m}2} instruction pattern
5267 @item @samp{ctz@var{m}2}
5268 Store into operand 0 the number of trailing 0-bits in operand 1, starting
5269 at the least significant bit position. If operand 1 is 0, the
5270 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
5271 the result is undefined or has a useful value.
5272 @var{m} is the mode of operand 0; operand 1's mode is
5273 specified by the instruction pattern, and the compiler will convert the
5274 operand to that mode before generating the instruction.
5276 @cindex @code{popcount@var{m}2} instruction pattern
5277 @item @samp{popcount@var{m}2}
5278 Store into operand 0 the number of 1-bits in operand 1. @var{m} is the
5279 mode of operand 0; operand 1's mode is specified by the instruction
5280 pattern, and the compiler will convert the operand to that mode before
5281 generating the instruction.
5283 @cindex @code{parity@var{m}2} instruction pattern
5284 @item @samp{parity@var{m}2}
5285 Store into operand 0 the parity of operand 1, i.e.@: the number of 1-bits
5286 in operand 1 modulo 2. @var{m} is the mode of operand 0; operand 1's mode
5287 is specified by the instruction pattern, and the compiler will convert
5288 the operand to that mode before generating the instruction.
5290 @cindex @code{one_cmpl@var{m}2} instruction pattern
5291 @item @samp{one_cmpl@var{m}2}
5292 Store the bitwise-complement of operand 1 into operand 0.
5294 @cindex @code{movmem@var{m}} instruction pattern
5295 @item @samp{movmem@var{m}}
5296 Block move instruction. The destination and source blocks of memory
5297 are the first two operands, and both are @code{mem:BLK}s with an
5298 address in mode @code{Pmode}.
5300 The number of bytes to move is the third operand, in mode @var{m}.
5301 Usually, you specify @code{Pmode} for @var{m}. However, if you can
5302 generate better code knowing the range of valid lengths is smaller than
5303 those representable in a full Pmode pointer, you should provide
5305 mode corresponding to the range of values you can handle efficiently
5306 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
5307 that appear negative) and also a pattern with @code{Pmode}.
5309 The fourth operand is the known shared alignment of the source and
5310 destination, in the form of a @code{const_int} rtx. Thus, if the
5311 compiler knows that both source and destination are word-aligned,
5312 it may provide the value 4 for this operand.
5314 Optional operands 5 and 6 specify expected alignment and size of block
5315 respectively. The expected alignment differs from alignment in operand 4
5316 in a way that the blocks are not required to be aligned according to it in
5317 all cases. This expected alignment is also in bytes, just like operand 4.
5318 Expected size, when unknown, is set to @code{(const_int -1)}.
5320 Descriptions of multiple @code{movmem@var{m}} patterns can only be
5321 beneficial if the patterns for smaller modes have fewer restrictions
5322 on their first, second and fourth operands. Note that the mode @var{m}
5323 in @code{movmem@var{m}} does not impose any restriction on the mode of
5324 individually moved data units in the block.
5326 These patterns need not give special consideration to the possibility
5327 that the source and destination strings might overlap.
5329 @cindex @code{movstr} instruction pattern
5331 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
5332 an output operand in mode @code{Pmode}. The addresses of the
5333 destination and source strings are operands 1 and 2, and both are
5334 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
5335 the expansion of this pattern should store in operand 0 the address in
5336 which the @code{NUL} terminator was stored in the destination string.
5338 This patern has also several optional operands that are same as in
5341 @cindex @code{setmem@var{m}} instruction pattern
5342 @item @samp{setmem@var{m}}
5343 Block set instruction. The destination string is the first operand,
5344 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
5345 number of bytes to set is the second operand, in mode @var{m}. The value to
5346 initialize the memory with is the third operand. Targets that only support the
5347 clearing of memory should reject any value that is not the constant 0. See
5348 @samp{movmem@var{m}} for a discussion of the choice of mode.
5350 The fourth operand is the known alignment of the destination, in the form
5351 of a @code{const_int} rtx. Thus, if the compiler knows that the
5352 destination is word-aligned, it may provide the value 4 for this
5355 Optional operands 5 and 6 specify expected alignment and size of block
5356 respectively. The expected alignment differs from alignment in operand 4
5357 in a way that the blocks are not required to be aligned according to it in
5358 all cases. This expected alignment is also in bytes, just like operand 4.
5359 Expected size, when unknown, is set to @code{(const_int -1)}.
5360 Operand 7 is the minimal size of the block and operand 8 is the
5361 maximal size of the block (NULL if it can not be represented as CONST_INT).
5362 Operand 9 is the probable maximal size (i.e. we can not rely on it for correctness,
5363 but it can be used for choosing proper code sequence for a given size).
5365 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
5367 @cindex @code{cmpstrn@var{m}} instruction pattern
5368 @item @samp{cmpstrn@var{m}}
5369 String compare instruction, with five operands. Operand 0 is the output;
5370 it has mode @var{m}. The remaining four operands are like the operands
5371 of @samp{movmem@var{m}}. The two memory blocks specified are compared
5372 byte by byte in lexicographic order starting at the beginning of each
5373 string. The instruction is not allowed to prefetch more than one byte
5374 at a time since either string may end in the first byte and reading past
5375 that may access an invalid page or segment and cause a fault. The
5376 comparison terminates early if the fetched bytes are different or if
5377 they are equal to zero. The effect of the instruction is to store a
5378 value in operand 0 whose sign indicates the result of the comparison.
5380 @cindex @code{cmpstr@var{m}} instruction pattern
5381 @item @samp{cmpstr@var{m}}
5382 String compare instruction, without known maximum length. Operand 0 is the
5383 output; it has mode @var{m}. The second and third operand are the blocks of
5384 memory to be compared; both are @code{mem:BLK} with an address in mode
5387 The fourth operand is the known shared alignment of the source and
5388 destination, in the form of a @code{const_int} rtx. Thus, if the
5389 compiler knows that both source and destination are word-aligned,
5390 it may provide the value 4 for this operand.
5392 The two memory blocks specified are compared byte by byte in lexicographic
5393 order starting at the beginning of each string. The instruction is not allowed
5394 to prefetch more than one byte at a time since either string may end in the
5395 first byte and reading past that may access an invalid page or segment and
5396 cause a fault. The comparison will terminate when the fetched bytes
5397 are different or if they are equal to zero. The effect of the
5398 instruction is to store a value in operand 0 whose sign indicates the
5399 result of the comparison.
5401 @cindex @code{cmpmem@var{m}} instruction pattern
5402 @item @samp{cmpmem@var{m}}
5403 Block compare instruction, with five operands like the operands
5404 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
5405 byte by byte in lexicographic order starting at the beginning of each
5406 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
5407 any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}}
5408 the comparison will not stop if both bytes are zero. The effect of
5409 the instruction is to store a value in operand 0 whose sign indicates
5410 the result of the comparison.
5412 @cindex @code{strlen@var{m}} instruction pattern
5413 @item @samp{strlen@var{m}}
5414 Compute the length of a string, with three operands.
5415 Operand 0 is the result (of mode @var{m}), operand 1 is
5416 a @code{mem} referring to the first character of the string,
5417 operand 2 is the character to search for (normally zero),
5418 and operand 3 is a constant describing the known alignment
5419 of the beginning of the string.
5421 @cindex @code{float@var{m}@var{n}2} instruction pattern
5422 @item @samp{float@var{m}@var{n}2}
5423 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
5424 floating point mode @var{n} and store in operand 0 (which has mode
5427 @cindex @code{floatuns@var{m}@var{n}2} instruction pattern
5428 @item @samp{floatuns@var{m}@var{n}2}
5429 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
5430 to floating point mode @var{n} and store in operand 0 (which has mode
5433 @cindex @code{fix@var{m}@var{n}2} instruction pattern
5434 @item @samp{fix@var{m}@var{n}2}
5435 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5436 point mode @var{n} as a signed number and store in operand 0 (which
5437 has mode @var{n}). This instruction's result is defined only when
5438 the value of operand 1 is an integer.
5440 If the machine description defines this pattern, it also needs to
5441 define the @code{ftrunc} pattern.
5443 @cindex @code{fixuns@var{m}@var{n}2} instruction pattern
5444 @item @samp{fixuns@var{m}@var{n}2}
5445 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5446 point mode @var{n} as an unsigned number and store in operand 0 (which
5447 has mode @var{n}). This instruction's result is defined only when the
5448 value of operand 1 is an integer.
5450 @cindex @code{ftrunc@var{m}2} instruction pattern
5451 @item @samp{ftrunc@var{m}2}
5452 Convert operand 1 (valid for floating point mode @var{m}) to an
5453 integer value, still represented in floating point mode @var{m}, and
5454 store it in operand 0 (valid for floating point mode @var{m}).
5456 @cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern
5457 @item @samp{fix_trunc@var{m}@var{n}2}
5458 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
5459 of mode @var{m} by converting the value to an integer.
5461 @cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern
5462 @item @samp{fixuns_trunc@var{m}@var{n}2}
5463 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
5464 value of mode @var{m} by converting the value to an integer.
5466 @cindex @code{trunc@var{m}@var{n}2} instruction pattern
5467 @item @samp{trunc@var{m}@var{n}2}
5468 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
5469 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5470 point or both floating point.
5472 @cindex @code{extend@var{m}@var{n}2} instruction pattern
5473 @item @samp{extend@var{m}@var{n}2}
5474 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
5475 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5476 point or both floating point.
5478 @cindex @code{zero_extend@var{m}@var{n}2} instruction pattern
5479 @item @samp{zero_extend@var{m}@var{n}2}
5480 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
5481 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5484 @cindex @code{fract@var{m}@var{n}2} instruction pattern
5485 @item @samp{fract@var{m}@var{n}2}
5486 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5487 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5488 could be fixed-point to fixed-point, signed integer to fixed-point,
5489 fixed-point to signed integer, floating-point to fixed-point,
5490 or fixed-point to floating-point.
5491 When overflows or underflows happen, the results are undefined.
5493 @cindex @code{satfract@var{m}@var{n}2} instruction pattern
5494 @item @samp{satfract@var{m}@var{n}2}
5495 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5496 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5497 could be fixed-point to fixed-point, signed integer to fixed-point,
5498 or floating-point to fixed-point.
5499 When overflows or underflows happen, the instruction saturates the
5500 results to the maximum or the minimum.
5502 @cindex @code{fractuns@var{m}@var{n}2} instruction pattern
5503 @item @samp{fractuns@var{m}@var{n}2}
5504 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5505 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5506 could be unsigned integer to fixed-point, or
5507 fixed-point to unsigned integer.
5508 When overflows or underflows happen, the results are undefined.
5510 @cindex @code{satfractuns@var{m}@var{n}2} instruction pattern
5511 @item @samp{satfractuns@var{m}@var{n}2}
5512 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
5513 @var{n} and store in operand 0 (which has mode @var{n}).
5514 When overflows or underflows happen, the instruction saturates the
5515 results to the maximum or the minimum.
5517 @cindex @code{extv@var{m}} instruction pattern
5518 @item @samp{extv@var{m}}
5519 Extract a bit-field from register operand 1, sign-extend it, and store
5520 it in operand 0. Operand 2 specifies the width of the field in bits
5521 and operand 3 the starting bit, which counts from the most significant
5522 bit if @samp{BITS_BIG_ENDIAN} is true and from the least significant bit
5525 Operands 0 and 1 both have mode @var{m}. Operands 2 and 3 have a
5526 target-specific mode.
5528 @cindex @code{extvmisalign@var{m}} instruction pattern
5529 @item @samp{extvmisalign@var{m}}
5530 Extract a bit-field from memory operand 1, sign extend it, and store
5531 it in operand 0. Operand 2 specifies the width in bits and operand 3
5532 the starting bit. The starting bit is always somewhere in the first byte of
5533 operand 1; it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5534 is true and from the least significant bit otherwise.
5536 Operand 0 has mode @var{m} while operand 1 has @code{BLK} mode.
5537 Operands 2 and 3 have a target-specific mode.
5539 The instruction must not read beyond the last byte of the bit-field.
5541 @cindex @code{extzv@var{m}} instruction pattern
5542 @item @samp{extzv@var{m}}
5543 Like @samp{extv@var{m}} except that the bit-field value is zero-extended.
5545 @cindex @code{extzvmisalign@var{m}} instruction pattern
5546 @item @samp{extzvmisalign@var{m}}
5547 Like @samp{extvmisalign@var{m}} except that the bit-field value is
5550 @cindex @code{insv@var{m}} instruction pattern
5551 @item @samp{insv@var{m}}
5552 Insert operand 3 into a bit-field of register operand 0. Operand 1
5553 specifies the width of the field in bits and operand 2 the starting bit,
5554 which counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5555 is true and from the least significant bit otherwise.
5557 Operands 0 and 3 both have mode @var{m}. Operands 1 and 2 have a
5558 target-specific mode.
5560 @cindex @code{insvmisalign@var{m}} instruction pattern
5561 @item @samp{insvmisalign@var{m}}
5562 Insert operand 3 into a bit-field of memory operand 0. Operand 1
5563 specifies the width of the field in bits and operand 2 the starting bit.
5564 The starting bit is always somewhere in the first byte of operand 0;
5565 it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5566 is true and from the least significant bit otherwise.
5568 Operand 3 has mode @var{m} while operand 0 has @code{BLK} mode.
5569 Operands 1 and 2 have a target-specific mode.
5571 The instruction must not read or write beyond the last byte of the bit-field.
5573 @cindex @code{extv} instruction pattern
5575 Extract a bit-field from operand 1 (a register or memory operand), where
5576 operand 2 specifies the width in bits and operand 3 the starting bit,
5577 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
5578 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
5579 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
5580 be valid for @code{word_mode}.
5582 The RTL generation pass generates this instruction only with constants
5583 for operands 2 and 3 and the constant is never zero for operand 2.
5585 The bit-field value is sign-extended to a full word integer
5586 before it is stored in operand 0.
5588 This pattern is deprecated; please use @samp{extv@var{m}} and
5589 @code{extvmisalign@var{m}} instead.
5591 @cindex @code{extzv} instruction pattern
5593 Like @samp{extv} except that the bit-field value is zero-extended.
5595 This pattern is deprecated; please use @samp{extzv@var{m}} and
5596 @code{extzvmisalign@var{m}} instead.
5598 @cindex @code{insv} instruction pattern
5600 Store operand 3 (which must be valid for @code{word_mode}) into a
5601 bit-field in operand 0, where operand 1 specifies the width in bits and
5602 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
5603 @code{word_mode}; often @code{word_mode} is allowed only for registers.
5604 Operands 1 and 2 must be valid for @code{word_mode}.
5606 The RTL generation pass generates this instruction only with constants
5607 for operands 1 and 2 and the constant is never zero for operand 1.
5609 This pattern is deprecated; please use @samp{insv@var{m}} and
5610 @code{insvmisalign@var{m}} instead.
5612 @cindex @code{mov@var{mode}cc} instruction pattern
5613 @item @samp{mov@var{mode}cc}
5614 Conditionally move operand 2 or operand 3 into operand 0 according to the
5615 comparison in operand 1. If the comparison is true, operand 2 is moved
5616 into operand 0, otherwise operand 3 is moved.
5618 The mode of the operands being compared need not be the same as the operands
5619 being moved. Some machines, sparc64 for example, have instructions that
5620 conditionally move an integer value based on the floating point condition
5621 codes and vice versa.
5623 If the machine does not have conditional move instructions, do not
5624 define these patterns.
5626 @cindex @code{add@var{mode}cc} instruction pattern
5627 @item @samp{add@var{mode}cc}
5628 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
5629 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
5630 comparison in operand 1. If the comparison is false, operand 2 is moved into
5631 operand 0, otherwise (operand 2 + operand 3) is moved.
5633 @cindex @code{cstore@var{mode}4} instruction pattern
5634 @item @samp{cstore@var{mode}4}
5635 Store zero or nonzero in operand 0 according to whether a comparison
5636 is true. Operand 1 is a comparison operator. Operand 2 and operand 3
5637 are the first and second operand of the comparison, respectively.
5638 You specify the mode that operand 0 must have when you write the
5639 @code{match_operand} expression. The compiler automatically sees which
5640 mode you have used and supplies an operand of that mode.
5642 The value stored for a true condition must have 1 as its low bit, or
5643 else must be negative. Otherwise the instruction is not suitable and
5644 you should omit it from the machine description. You describe to the
5645 compiler exactly which value is stored by defining the macro
5646 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
5647 found that can be used for all the possible comparison operators, you
5648 should pick one and use a @code{define_expand} to map all results
5649 onto the one you chose.
5651 These operations may @code{FAIL}, but should do so only in relatively
5652 uncommon cases; if they would @code{FAIL} for common cases involving
5653 integer comparisons, it is best to restrict the predicates to not
5654 allow these operands. Likewise if a given comparison operator will
5655 always fail, independent of the operands (for floating-point modes, the
5656 @code{ordered_comparison_operator} predicate is often useful in this case).
5658 If this pattern is omitted, the compiler will generate a conditional
5659 branch---for example, it may copy a constant one to the target and branching
5660 around an assignment of zero to the target---or a libcall. If the predicate
5661 for operand 1 only rejects some operators, it will also try reordering the
5662 operands and/or inverting the result value (e.g.@: by an exclusive OR).
5663 These possibilities could be cheaper or equivalent to the instructions
5664 used for the @samp{cstore@var{mode}4} pattern followed by those required
5665 to convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this
5666 case, you can and should make operand 1's predicate reject some operators
5667 in the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether
5668 from the machine description.
5670 @cindex @code{cbranch@var{mode}4} instruction pattern
5671 @item @samp{cbranch@var{mode}4}
5672 Conditional branch instruction combined with a compare instruction.
5673 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
5674 first and second operands of the comparison, respectively. Operand 3
5675 is a @code{label_ref} that refers to the label to jump to.
5677 @cindex @code{jump} instruction pattern
5679 A jump inside a function; an unconditional branch. Operand 0 is the
5680 @code{label_ref} of the label to jump to. This pattern name is mandatory
5683 @cindex @code{call} instruction pattern
5685 Subroutine call instruction returning no value. Operand 0 is the
5686 function to call; operand 1 is the number of bytes of arguments pushed
5687 as a @code{const_int}; operand 2 is the number of registers used as
5690 On most machines, operand 2 is not actually stored into the RTL
5691 pattern. It is supplied for the sake of some RISC machines which need
5692 to put this information into the assembler code; they can put it in
5693 the RTL instead of operand 1.
5695 Operand 0 should be a @code{mem} RTX whose address is the address of the
5696 function. Note, however, that this address can be a @code{symbol_ref}
5697 expression even if it would not be a legitimate memory address on the
5698 target machine. If it is also not a valid argument for a call
5699 instruction, the pattern for this operation should be a
5700 @code{define_expand} (@pxref{Expander Definitions}) that places the
5701 address into a register and uses that register in the call instruction.
5703 @cindex @code{call_value} instruction pattern
5704 @item @samp{call_value}
5705 Subroutine call instruction returning a value. Operand 0 is the hard
5706 register in which the value is returned. There are three more
5707 operands, the same as the three operands of the @samp{call}
5708 instruction (but with numbers increased by one).
5710 Subroutines that return @code{BLKmode} objects use the @samp{call}
5713 @cindex @code{call_pop} instruction pattern
5714 @cindex @code{call_value_pop} instruction pattern
5715 @item @samp{call_pop}, @samp{call_value_pop}
5716 Similar to @samp{call} and @samp{call_value}, except used if defined and
5717 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
5718 that contains both the function call and a @code{set} to indicate the
5719 adjustment made to the frame pointer.
5721 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
5722 patterns increases the number of functions for which the frame pointer
5723 can be eliminated, if desired.
5725 @cindex @code{untyped_call} instruction pattern
5726 @item @samp{untyped_call}
5727 Subroutine call instruction returning a value of any type. Operand 0 is
5728 the function to call; operand 1 is a memory location where the result of
5729 calling the function is to be stored; operand 2 is a @code{parallel}
5730 expression where each element is a @code{set} expression that indicates
5731 the saving of a function return value into the result block.
5733 This instruction pattern should be defined to support
5734 @code{__builtin_apply} on machines where special instructions are needed
5735 to call a subroutine with arbitrary arguments or to save the value
5736 returned. This instruction pattern is required on machines that have
5737 multiple registers that can hold a return value
5738 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
5740 @cindex @code{return} instruction pattern
5742 Subroutine return instruction. This instruction pattern name should be
5743 defined only if a single instruction can do all the work of returning
5746 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
5747 RTL generation phase. In this case it is to support machines where
5748 multiple instructions are usually needed to return from a function, but
5749 some class of functions only requires one instruction to implement a
5750 return. Normally, the applicable functions are those which do not need
5751 to save any registers or allocate stack space.
5753 It is valid for this pattern to expand to an instruction using
5754 @code{simple_return} if no epilogue is required.
5756 @cindex @code{simple_return} instruction pattern
5757 @item @samp{simple_return}
5758 Subroutine return instruction. This instruction pattern name should be
5759 defined only if a single instruction can do all the work of returning
5760 from a function on a path where no epilogue is required. This pattern
5761 is very similar to the @code{return} instruction pattern, but it is emitted
5762 only by the shrink-wrapping optimization on paths where the function
5763 prologue has not been executed, and a function return should occur without
5764 any of the effects of the epilogue. Additional uses may be introduced on
5765 paths where both the prologue and the epilogue have executed.
5767 @findex reload_completed
5768 @findex leaf_function_p
5769 For such machines, the condition specified in this pattern should only
5770 be true when @code{reload_completed} is nonzero and the function's
5771 epilogue would only be a single instruction. For machines with register
5772 windows, the routine @code{leaf_function_p} may be used to determine if
5773 a register window push is required.
5775 Machines that have conditional return instructions should define patterns
5781 (if_then_else (match_operator
5782 0 "comparison_operator"
5783 [(cc0) (const_int 0)])
5790 where @var{condition} would normally be the same condition specified on the
5791 named @samp{return} pattern.
5793 @cindex @code{untyped_return} instruction pattern
5794 @item @samp{untyped_return}
5795 Untyped subroutine return instruction. This instruction pattern should
5796 be defined to support @code{__builtin_return} on machines where special
5797 instructions are needed to return a value of any type.
5799 Operand 0 is a memory location where the result of calling a function
5800 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
5801 expression where each element is a @code{set} expression that indicates
5802 the restoring of a function return value from the result block.
5804 @cindex @code{nop} instruction pattern
5806 No-op instruction. This instruction pattern name should always be defined
5807 to output a no-op in assembler code. @code{(const_int 0)} will do as an
5810 @cindex @code{indirect_jump} instruction pattern
5811 @item @samp{indirect_jump}
5812 An instruction to jump to an address which is operand zero.
5813 This pattern name is mandatory on all machines.
5815 @cindex @code{casesi} instruction pattern
5817 Instruction to jump through a dispatch table, including bounds checking.
5818 This instruction takes five operands:
5822 The index to dispatch on, which has mode @code{SImode}.
5825 The lower bound for indices in the table, an integer constant.
5828 The total range of indices in the table---the largest index
5829 minus the smallest one (both inclusive).
5832 A label that precedes the table itself.
5835 A label to jump to if the index has a value outside the bounds.
5838 The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a
5839 @code{jump_table_data}. The number of elements in the table is one plus the
5840 difference between the upper bound and the lower bound.
5842 @cindex @code{tablejump} instruction pattern
5843 @item @samp{tablejump}
5844 Instruction to jump to a variable address. This is a low-level
5845 capability which can be used to implement a dispatch table when there
5846 is no @samp{casesi} pattern.
5848 This pattern requires two operands: the address or offset, and a label
5849 which should immediately precede the jump table. If the macro
5850 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
5851 operand is an offset which counts from the address of the table; otherwise,
5852 it is an absolute address to jump to. In either case, the first operand has
5855 The @samp{tablejump} insn is always the last insn before the jump
5856 table it uses. Its assembler code normally has no need to use the
5857 second operand, but you should incorporate it in the RTL pattern so
5858 that the jump optimizer will not delete the table as unreachable code.
5861 @cindex @code{decrement_and_branch_until_zero} instruction pattern
5862 @item @samp{decrement_and_branch_until_zero}
5863 Conditional branch instruction that decrements a register and
5864 jumps if the register is nonzero. Operand 0 is the register to
5865 decrement and test; operand 1 is the label to jump to if the
5866 register is nonzero. @xref{Looping Patterns}.
5868 This optional instruction pattern is only used by the combiner,
5869 typically for loops reversed by the loop optimizer when strength
5870 reduction is enabled.
5872 @cindex @code{doloop_end} instruction pattern
5873 @item @samp{doloop_end}
5874 Conditional branch instruction that decrements a register and
5875 jumps if the register is nonzero. Operand 0 is the register to
5876 decrement and test; operand 1 is the label to jump to if the
5877 register is nonzero.
5878 @xref{Looping Patterns}.
5880 This optional instruction pattern should be defined for machines with
5881 low-overhead looping instructions as the loop optimizer will try to
5882 modify suitable loops to utilize it. The target hook
5883 @code{TARGET_CAN_USE_DOLOOP_P} controls the conditions under which
5884 low-overhead loops can be used.
5886 @cindex @code{doloop_begin} instruction pattern
5887 @item @samp{doloop_begin}
5888 Companion instruction to @code{doloop_end} required for machines that
5889 need to perform some initialization, such as loading a special counter
5890 register. Operand 1 is the associated @code{doloop_end} pattern and
5891 operand 0 is the register that it decrements.
5893 If initialization insns do not always need to be emitted, use a
5894 @code{define_expand} (@pxref{Expander Definitions}) and make it fail.
5896 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
5897 @item @samp{canonicalize_funcptr_for_compare}
5898 Canonicalize the function pointer in operand 1 and store the result
5901 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
5902 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
5903 and also has mode @code{Pmode}.
5905 Canonicalization of a function pointer usually involves computing
5906 the address of the function which would be called if the function
5907 pointer were used in an indirect call.
5909 Only define this pattern if function pointers on the target machine
5910 can have different values but still call the same function when
5911 used in an indirect call.
5913 @cindex @code{save_stack_block} instruction pattern
5914 @cindex @code{save_stack_function} instruction pattern
5915 @cindex @code{save_stack_nonlocal} instruction pattern
5916 @cindex @code{restore_stack_block} instruction pattern
5917 @cindex @code{restore_stack_function} instruction pattern
5918 @cindex @code{restore_stack_nonlocal} instruction pattern
5919 @item @samp{save_stack_block}
5920 @itemx @samp{save_stack_function}
5921 @itemx @samp{save_stack_nonlocal}
5922 @itemx @samp{restore_stack_block}
5923 @itemx @samp{restore_stack_function}
5924 @itemx @samp{restore_stack_nonlocal}
5925 Most machines save and restore the stack pointer by copying it to or
5926 from an object of mode @code{Pmode}. Do not define these patterns on
5929 Some machines require special handling for stack pointer saves and
5930 restores. On those machines, define the patterns corresponding to the
5931 non-standard cases by using a @code{define_expand} (@pxref{Expander
5932 Definitions}) that produces the required insns. The three types of
5933 saves and restores are:
5937 @samp{save_stack_block} saves the stack pointer at the start of a block
5938 that allocates a variable-sized object, and @samp{restore_stack_block}
5939 restores the stack pointer when the block is exited.
5942 @samp{save_stack_function} and @samp{restore_stack_function} do a
5943 similar job for the outermost block of a function and are used when the
5944 function allocates variable-sized objects or calls @code{alloca}. Only
5945 the epilogue uses the restored stack pointer, allowing a simpler save or
5946 restore sequence on some machines.
5949 @samp{save_stack_nonlocal} is used in functions that contain labels
5950 branched to by nested functions. It saves the stack pointer in such a
5951 way that the inner function can use @samp{restore_stack_nonlocal} to
5952 restore the stack pointer. The compiler generates code to restore the
5953 frame and argument pointer registers, but some machines require saving
5954 and restoring additional data such as register window information or
5955 stack backchains. Place insns in these patterns to save and restore any
5959 When saving the stack pointer, operand 0 is the save area and operand 1
5960 is the stack pointer. The mode used to allocate the save area defaults
5961 to @code{Pmode} but you can override that choice by defining the
5962 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
5963 specify an integral mode, or @code{VOIDmode} if no save area is needed
5964 for a particular type of save (either because no save is needed or
5965 because a machine-specific save area can be used). Operand 0 is the
5966 stack pointer and operand 1 is the save area for restore operations. If
5967 @samp{save_stack_block} is defined, operand 0 must not be
5968 @code{VOIDmode} since these saves can be arbitrarily nested.
5970 A save area is a @code{mem} that is at a constant offset from
5971 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
5972 nonlocal gotos and a @code{reg} in the other two cases.
5974 @cindex @code{allocate_stack} instruction pattern
5975 @item @samp{allocate_stack}
5976 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
5977 the stack pointer to create space for dynamically allocated data.
5979 Store the resultant pointer to this space into operand 0. If you
5980 are allocating space from the main stack, do this by emitting a
5981 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
5982 If you are allocating the space elsewhere, generate code to copy the
5983 location of the space to operand 0. In the latter case, you must
5984 ensure this space gets freed when the corresponding space on the main
5987 Do not define this pattern if all that must be done is the subtraction.
5988 Some machines require other operations such as stack probes or
5989 maintaining the back chain. Define this pattern to emit those
5990 operations in addition to updating the stack pointer.
5992 @cindex @code{check_stack} instruction pattern
5993 @item @samp{check_stack}
5994 If stack checking (@pxref{Stack Checking}) cannot be done on your system by
5995 probing the stack, define this pattern to perform the needed check and signal
5996 an error if the stack has overflowed. The single operand is the address in
5997 the stack farthest from the current stack pointer that you need to validate.
5998 Normally, on platforms where this pattern is needed, you would obtain the
5999 stack limit from a global or thread-specific variable or register.
6001 @cindex @code{probe_stack_address} instruction pattern
6002 @item @samp{probe_stack_address}
6003 If stack checking (@pxref{Stack Checking}) can be done on your system by
6004 probing the stack but without the need to actually access it, define this
6005 pattern and signal an error if the stack has overflowed. The single operand
6006 is the memory address in the stack that needs to be probed.
6008 @cindex @code{probe_stack} instruction pattern
6009 @item @samp{probe_stack}
6010 If stack checking (@pxref{Stack Checking}) can be done on your system by
6011 probing the stack but doing it with a ``store zero'' instruction is not valid
6012 or optimal, define this pattern to do the probing differently and signal an
6013 error if the stack has overflowed. The single operand is the memory reference
6014 in the stack that needs to be probed.
6016 @cindex @code{nonlocal_goto} instruction pattern
6017 @item @samp{nonlocal_goto}
6018 Emit code to generate a non-local goto, e.g., a jump from one function
6019 to a label in an outer function. This pattern has four arguments,
6020 each representing a value to be used in the jump. The first
6021 argument is to be loaded into the frame pointer, the second is
6022 the address to branch to (code to dispatch to the actual label),
6023 the third is the address of a location where the stack is saved,
6024 and the last is the address of the label, to be placed in the
6025 location for the incoming static chain.
6027 On most machines you need not define this pattern, since GCC will
6028 already generate the correct code, which is to load the frame pointer
6029 and static chain, restore the stack (using the
6030 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
6031 to the dispatcher. You need only define this pattern if this code will
6032 not work on your machine.
6034 @cindex @code{nonlocal_goto_receiver} instruction pattern
6035 @item @samp{nonlocal_goto_receiver}
6036 This pattern, if defined, contains code needed at the target of a
6037 nonlocal goto after the code already generated by GCC@. You will not
6038 normally need to define this pattern. A typical reason why you might
6039 need this pattern is if some value, such as a pointer to a global table,
6040 must be restored when the frame pointer is restored. Note that a nonlocal
6041 goto only occurs within a unit-of-translation, so a global table pointer
6042 that is shared by all functions of a given module need not be restored.
6043 There are no arguments.
6045 @cindex @code{exception_receiver} instruction pattern
6046 @item @samp{exception_receiver}
6047 This pattern, if defined, contains code needed at the site of an
6048 exception handler that isn't needed at the site of a nonlocal goto. You
6049 will not normally need to define this pattern. A typical reason why you
6050 might need this pattern is if some value, such as a pointer to a global
6051 table, must be restored after control flow is branched to the handler of
6052 an exception. There are no arguments.
6054 @cindex @code{builtin_setjmp_setup} instruction pattern
6055 @item @samp{builtin_setjmp_setup}
6056 This pattern, if defined, contains additional code needed to initialize
6057 the @code{jmp_buf}. You will not normally need to define this pattern.
6058 A typical reason why you might need this pattern is if some value, such
6059 as a pointer to a global table, must be restored. Though it is
6060 preferred that the pointer value be recalculated if possible (given the
6061 address of a label for instance). The single argument is a pointer to
6062 the @code{jmp_buf}. Note that the buffer is five words long and that
6063 the first three are normally used by the generic mechanism.
6065 @cindex @code{builtin_setjmp_receiver} instruction pattern
6066 @item @samp{builtin_setjmp_receiver}
6067 This pattern, if defined, contains code needed at the site of a
6068 built-in setjmp that isn't needed at the site of a nonlocal goto. You
6069 will not normally need to define this pattern. A typical reason why you
6070 might need this pattern is if some value, such as a pointer to a global
6071 table, must be restored. It takes one argument, which is the label
6072 to which builtin_longjmp transferred control; this pattern may be emitted
6073 at a small offset from that label.
6075 @cindex @code{builtin_longjmp} instruction pattern
6076 @item @samp{builtin_longjmp}
6077 This pattern, if defined, performs the entire action of the longjmp.
6078 You will not normally need to define this pattern unless you also define
6079 @code{builtin_setjmp_setup}. The single argument is a pointer to the
6082 @cindex @code{eh_return} instruction pattern
6083 @item @samp{eh_return}
6084 This pattern, if defined, affects the way @code{__builtin_eh_return},
6085 and thence the call frame exception handling library routines, are
6086 built. It is intended to handle non-trivial actions needed along
6087 the abnormal return path.
6089 The address of the exception handler to which the function should return
6090 is passed as operand to this pattern. It will normally need to copied by
6091 the pattern to some special register or memory location.
6092 If the pattern needs to determine the location of the target call
6093 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
6094 if defined; it will have already been assigned.
6096 If this pattern is not defined, the default action will be to simply
6097 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
6098 that macro or this pattern needs to be defined if call frame exception
6099 handling is to be used.
6101 @cindex @code{prologue} instruction pattern
6102 @anchor{prologue instruction pattern}
6103 @item @samp{prologue}
6104 This pattern, if defined, emits RTL for entry to a function. The function
6105 entry is responsible for setting up the stack frame, initializing the frame
6106 pointer register, saving callee saved registers, etc.
6108 Using a prologue pattern is generally preferred over defining
6109 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
6111 The @code{prologue} pattern is particularly useful for targets which perform
6112 instruction scheduling.
6114 @cindex @code{window_save} instruction pattern
6115 @anchor{window_save instruction pattern}
6116 @item @samp{window_save}
6117 This pattern, if defined, emits RTL for a register window save. It should
6118 be defined if the target machine has register windows but the window events
6119 are decoupled from calls to subroutines. The canonical example is the SPARC
6122 @cindex @code{epilogue} instruction pattern
6123 @anchor{epilogue instruction pattern}
6124 @item @samp{epilogue}
6125 This pattern emits RTL for exit from a function. The function
6126 exit is responsible for deallocating the stack frame, restoring callee saved
6127 registers and emitting the return instruction.
6129 Using an epilogue pattern is generally preferred over defining
6130 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
6132 The @code{epilogue} pattern is particularly useful for targets which perform
6133 instruction scheduling or which have delay slots for their return instruction.
6135 @cindex @code{sibcall_epilogue} instruction pattern
6136 @item @samp{sibcall_epilogue}
6137 This pattern, if defined, emits RTL for exit from a function without the final
6138 branch back to the calling function. This pattern will be emitted before any
6139 sibling call (aka tail call) sites.
6141 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
6142 parameter passing or any stack slots for arguments passed to the current
6145 @cindex @code{trap} instruction pattern
6147 This pattern, if defined, signals an error, typically by causing some
6148 kind of signal to be raised. Among other places, it is used by the Java
6149 front end to signal `invalid array index' exceptions.
6151 @cindex @code{ctrap@var{MM}4} instruction pattern
6152 @item @samp{ctrap@var{MM}4}
6153 Conditional trap instruction. Operand 0 is a piece of RTL which
6154 performs a comparison, and operands 1 and 2 are the arms of the
6155 comparison. Operand 3 is the trap code, an integer.
6157 A typical @code{ctrap} pattern looks like
6160 (define_insn "ctrapsi4"
6161 [(trap_if (match_operator 0 "trap_operator"
6162 [(match_operand 1 "register_operand")
6163 (match_operand 2 "immediate_operand")])
6164 (match_operand 3 "const_int_operand" "i"))]
6169 @cindex @code{prefetch} instruction pattern
6170 @item @samp{prefetch}
6171 This pattern, if defined, emits code for a non-faulting data prefetch
6172 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
6173 is a constant 1 if the prefetch is preparing for a write to the memory
6174 address, or a constant 0 otherwise. Operand 2 is the expected degree of
6175 temporal locality of the data and is a value between 0 and 3, inclusive; 0
6176 means that the data has no temporal locality, so it need not be left in the
6177 cache after the access; 3 means that the data has a high degree of temporal
6178 locality and should be left in all levels of cache possible; 1 and 2 mean,
6179 respectively, a low or moderate degree of temporal locality.
6181 Targets that do not support write prefetches or locality hints can ignore
6182 the values of operands 1 and 2.
6184 @cindex @code{blockage} instruction pattern
6185 @item @samp{blockage}
6186 This pattern defines a pseudo insn that prevents the instruction
6187 scheduler and other passes from moving instructions and using register
6188 equivalences across the boundary defined by the blockage insn.
6189 This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM.
6191 @cindex @code{memory_barrier} instruction pattern
6192 @item @samp{memory_barrier}
6193 If the target memory model is not fully synchronous, then this pattern
6194 should be defined to an instruction that orders both loads and stores
6195 before the instruction with respect to loads and stores after the instruction.
6196 This pattern has no operands.
6198 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
6199 @item @samp{sync_compare_and_swap@var{mode}}
6200 This pattern, if defined, emits code for an atomic compare-and-swap
6201 operation. Operand 1 is the memory on which the atomic operation is
6202 performed. Operand 2 is the ``old'' value to be compared against the
6203 current contents of the memory location. Operand 3 is the ``new'' value
6204 to store in the memory if the compare succeeds. Operand 0 is the result
6205 of the operation; it should contain the contents of the memory
6206 before the operation. If the compare succeeds, this should obviously be
6207 a copy of operand 2.
6209 This pattern must show that both operand 0 and operand 1 are modified.
6211 This pattern must issue any memory barrier instructions such that all
6212 memory operations before the atomic operation occur before the atomic
6213 operation and all memory operations after the atomic operation occur
6214 after the atomic operation.
6216 For targets where the success or failure of the compare-and-swap
6217 operation is available via the status flags, it is possible to
6218 avoid a separate compare operation and issue the subsequent
6219 branch or store-flag operation immediately after the compare-and-swap.
6220 To this end, GCC will look for a @code{MODE_CC} set in the
6221 output of @code{sync_compare_and_swap@var{mode}}; if the machine
6222 description includes such a set, the target should also define special
6223 @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then
6224 be able to take the destination of the @code{MODE_CC} set and pass it
6225 to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first
6226 operand of the comparison (the second will be @code{(const_int 0)}).
6228 For targets where the operating system may provide support for this
6229 operation via library calls, the @code{sync_compare_and_swap_optab}
6230 may be initialized to a function with the same interface as the
6231 @code{__sync_val_compare_and_swap_@var{n}} built-in. If the entire
6232 set of @var{__sync} builtins are supported via library calls, the
6233 target can initialize all of the optabs at once with
6234 @code{init_sync_libfuncs}.
6235 For the purposes of C++11 @code{std::atomic::is_lock_free}, it is
6236 assumed that these library calls do @emph{not} use any kind of
6237 interruptable locking.
6239 @cindex @code{sync_add@var{mode}} instruction pattern
6240 @cindex @code{sync_sub@var{mode}} instruction pattern
6241 @cindex @code{sync_ior@var{mode}} instruction pattern
6242 @cindex @code{sync_and@var{mode}} instruction pattern
6243 @cindex @code{sync_xor@var{mode}} instruction pattern
6244 @cindex @code{sync_nand@var{mode}} instruction pattern
6245 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
6246 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
6247 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
6248 These patterns emit code for an atomic operation on memory.
6249 Operand 0 is the memory on which the atomic operation is performed.
6250 Operand 1 is the second operand to the binary operator.
6252 This pattern must issue any memory barrier instructions such that all
6253 memory operations before the atomic operation occur before the atomic
6254 operation and all memory operations after the atomic operation occur
6255 after the atomic operation.
6257 If these patterns are not defined, the operation will be constructed
6258 from a compare-and-swap operation, if defined.
6260 @cindex @code{sync_old_add@var{mode}} instruction pattern
6261 @cindex @code{sync_old_sub@var{mode}} instruction pattern
6262 @cindex @code{sync_old_ior@var{mode}} instruction pattern
6263 @cindex @code{sync_old_and@var{mode}} instruction pattern
6264 @cindex @code{sync_old_xor@var{mode}} instruction pattern
6265 @cindex @code{sync_old_nand@var{mode}} instruction pattern
6266 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
6267 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
6268 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
6269 These patterns emit code for an atomic operation on memory,
6270 and return the value that the memory contained before the operation.
6271 Operand 0 is the result value, operand 1 is the memory on which the
6272 atomic operation is performed, and operand 2 is the second operand
6273 to the binary operator.
6275 This pattern must issue any memory barrier instructions such that all
6276 memory operations before the atomic operation occur before the atomic
6277 operation and all memory operations after the atomic operation occur
6278 after the atomic operation.
6280 If these patterns are not defined, the operation will be constructed
6281 from a compare-and-swap operation, if defined.
6283 @cindex @code{sync_new_add@var{mode}} instruction pattern
6284 @cindex @code{sync_new_sub@var{mode}} instruction pattern
6285 @cindex @code{sync_new_ior@var{mode}} instruction pattern
6286 @cindex @code{sync_new_and@var{mode}} instruction pattern
6287 @cindex @code{sync_new_xor@var{mode}} instruction pattern
6288 @cindex @code{sync_new_nand@var{mode}} instruction pattern
6289 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
6290 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
6291 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
6292 These patterns are like their @code{sync_old_@var{op}} counterparts,
6293 except that they return the value that exists in the memory location
6294 after the operation, rather than before the operation.
6296 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
6297 @item @samp{sync_lock_test_and_set@var{mode}}
6298 This pattern takes two forms, based on the capabilities of the target.
6299 In either case, operand 0 is the result of the operand, operand 1 is
6300 the memory on which the atomic operation is performed, and operand 2
6301 is the value to set in the lock.
6303 In the ideal case, this operation is an atomic exchange operation, in
6304 which the previous value in memory operand is copied into the result
6305 operand, and the value operand is stored in the memory operand.
6307 For less capable targets, any value operand that is not the constant 1
6308 should be rejected with @code{FAIL}. In this case the target may use
6309 an atomic test-and-set bit operation. The result operand should contain
6310 1 if the bit was previously set and 0 if the bit was previously clear.
6311 The true contents of the memory operand are implementation defined.
6313 This pattern must issue any memory barrier instructions such that the
6314 pattern as a whole acts as an acquire barrier, that is all memory
6315 operations after the pattern do not occur until the lock is acquired.
6317 If this pattern is not defined, the operation will be constructed from
6318 a compare-and-swap operation, if defined.
6320 @cindex @code{sync_lock_release@var{mode}} instruction pattern
6321 @item @samp{sync_lock_release@var{mode}}
6322 This pattern, if defined, releases a lock set by
6323 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
6324 that contains the lock; operand 1 is the value to store in the lock.
6326 If the target doesn't implement full semantics for
6327 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
6328 the constant 0 should be rejected with @code{FAIL}, and the true contents
6329 of the memory operand are implementation defined.
6331 This pattern must issue any memory barrier instructions such that the
6332 pattern as a whole acts as a release barrier, that is the lock is
6333 released only after all previous memory operations have completed.
6335 If this pattern is not defined, then a @code{memory_barrier} pattern
6336 will be emitted, followed by a store of the value to the memory operand.
6338 @cindex @code{atomic_compare_and_swap@var{mode}} instruction pattern
6339 @item @samp{atomic_compare_and_swap@var{mode}}
6340 This pattern, if defined, emits code for an atomic compare-and-swap
6341 operation with memory model semantics. Operand 2 is the memory on which
6342 the atomic operation is performed. Operand 0 is an output operand which
6343 is set to true or false based on whether the operation succeeded. Operand
6344 1 is an output operand which is set to the contents of the memory before
6345 the operation was attempted. Operand 3 is the value that is expected to
6346 be in memory. Operand 4 is the value to put in memory if the expected
6347 value is found there. Operand 5 is set to 1 if this compare and swap is to
6348 be treated as a weak operation. Operand 6 is the memory model to be used
6349 if the operation is a success. Operand 7 is the memory model to be used
6350 if the operation fails.
6352 If memory referred to in operand 2 contains the value in operand 3, then
6353 operand 4 is stored in memory pointed to by operand 2 and fencing based on
6354 the memory model in operand 6 is issued.
6356 If memory referred to in operand 2 does not contain the value in operand 3,
6357 then fencing based on the memory model in operand 7 is issued.
6359 If a target does not support weak compare-and-swap operations, or the port
6360 elects not to implement weak operations, the argument in operand 5 can be
6361 ignored. Note a strong implementation must be provided.
6363 If this pattern is not provided, the @code{__atomic_compare_exchange}
6364 built-in functions will utilize the legacy @code{sync_compare_and_swap}
6365 pattern with an @code{__ATOMIC_SEQ_CST} memory model.
6367 @cindex @code{atomic_load@var{mode}} instruction pattern
6368 @item @samp{atomic_load@var{mode}}
6369 This pattern implements an atomic load operation with memory model
6370 semantics. Operand 1 is the memory address being loaded from. Operand 0
6371 is the result of the load. Operand 2 is the memory model to be used for
6374 If not present, the @code{__atomic_load} built-in function will either
6375 resort to a normal load with memory barriers, or a compare-and-swap
6376 operation if a normal load would not be atomic.
6378 @cindex @code{atomic_store@var{mode}} instruction pattern
6379 @item @samp{atomic_store@var{mode}}
6380 This pattern implements an atomic store operation with memory model
6381 semantics. Operand 0 is the memory address being stored to. Operand 1
6382 is the value to be written. Operand 2 is the memory model to be used for
6385 If not present, the @code{__atomic_store} built-in function will attempt to
6386 perform a normal store and surround it with any required memory fences. If
6387 the store would not be atomic, then an @code{__atomic_exchange} is
6388 attempted with the result being ignored.
6390 @cindex @code{atomic_exchange@var{mode}} instruction pattern
6391 @item @samp{atomic_exchange@var{mode}}
6392 This pattern implements an atomic exchange operation with memory model
6393 semantics. Operand 1 is the memory location the operation is performed on.
6394 Operand 0 is an output operand which is set to the original value contained
6395 in the memory pointed to by operand 1. Operand 2 is the value to be
6396 stored. Operand 3 is the memory model to be used.
6398 If this pattern is not present, the built-in function
6399 @code{__atomic_exchange} will attempt to preform the operation with a
6400 compare and swap loop.
6402 @cindex @code{atomic_add@var{mode}} instruction pattern
6403 @cindex @code{atomic_sub@var{mode}} instruction pattern
6404 @cindex @code{atomic_or@var{mode}} instruction pattern
6405 @cindex @code{atomic_and@var{mode}} instruction pattern
6406 @cindex @code{atomic_xor@var{mode}} instruction pattern
6407 @cindex @code{atomic_nand@var{mode}} instruction pattern
6408 @item @samp{atomic_add@var{mode}}, @samp{atomic_sub@var{mode}}
6409 @itemx @samp{atomic_or@var{mode}}, @samp{atomic_and@var{mode}}
6410 @itemx @samp{atomic_xor@var{mode}}, @samp{atomic_nand@var{mode}}
6411 These patterns emit code for an atomic operation on memory with memory
6412 model semantics. Operand 0 is the memory on which the atomic operation is
6413 performed. Operand 1 is the second operand to the binary operator.
6414 Operand 2 is the memory model to be used by the operation.
6416 If these patterns are not defined, attempts will be made to use legacy
6417 @code{sync} patterns, or equivalent patterns which return a result. If
6418 none of these are available a compare-and-swap loop will be used.
6420 @cindex @code{atomic_fetch_add@var{mode}} instruction pattern
6421 @cindex @code{atomic_fetch_sub@var{mode}} instruction pattern
6422 @cindex @code{atomic_fetch_or@var{mode}} instruction pattern
6423 @cindex @code{atomic_fetch_and@var{mode}} instruction pattern
6424 @cindex @code{atomic_fetch_xor@var{mode}} instruction pattern
6425 @cindex @code{atomic_fetch_nand@var{mode}} instruction pattern
6426 @item @samp{atomic_fetch_add@var{mode}}, @samp{atomic_fetch_sub@var{mode}}
6427 @itemx @samp{atomic_fetch_or@var{mode}}, @samp{atomic_fetch_and@var{mode}}
6428 @itemx @samp{atomic_fetch_xor@var{mode}}, @samp{atomic_fetch_nand@var{mode}}
6429 These patterns emit code for an atomic operation on memory with memory
6430 model semantics, and return the original value. Operand 0 is an output
6431 operand which contains the value of the memory location before the
6432 operation was performed. Operand 1 is the memory on which the atomic
6433 operation is performed. Operand 2 is the second operand to the binary
6434 operator. Operand 3 is the memory model to be used by the operation.
6436 If these patterns are not defined, attempts will be made to use legacy
6437 @code{sync} patterns. If none of these are available a compare-and-swap
6440 @cindex @code{atomic_add_fetch@var{mode}} instruction pattern
6441 @cindex @code{atomic_sub_fetch@var{mode}} instruction pattern
6442 @cindex @code{atomic_or_fetch@var{mode}} instruction pattern
6443 @cindex @code{atomic_and_fetch@var{mode}} instruction pattern
6444 @cindex @code{atomic_xor_fetch@var{mode}} instruction pattern
6445 @cindex @code{atomic_nand_fetch@var{mode}} instruction pattern
6446 @item @samp{atomic_add_fetch@var{mode}}, @samp{atomic_sub_fetch@var{mode}}
6447 @itemx @samp{atomic_or_fetch@var{mode}}, @samp{atomic_and_fetch@var{mode}}
6448 @itemx @samp{atomic_xor_fetch@var{mode}}, @samp{atomic_nand_fetch@var{mode}}
6449 These patterns emit code for an atomic operation on memory with memory
6450 model semantics and return the result after the operation is performed.
6451 Operand 0 is an output operand which contains the value after the
6452 operation. Operand 1 is the memory on which the atomic operation is
6453 performed. Operand 2 is the second operand to the binary operator.
6454 Operand 3 is the memory model to be used by the operation.
6456 If these patterns are not defined, attempts will be made to use legacy
6457 @code{sync} patterns, or equivalent patterns which return the result before
6458 the operation followed by the arithmetic operation required to produce the
6459 result. If none of these are available a compare-and-swap loop will be
6462 @cindex @code{atomic_test_and_set} instruction pattern
6463 @item @samp{atomic_test_and_set}
6464 This pattern emits code for @code{__builtin_atomic_test_and_set}.
6465 Operand 0 is an output operand which is set to true if the previous
6466 previous contents of the byte was "set", and false otherwise. Operand 1
6467 is the @code{QImode} memory to be modified. Operand 2 is the memory
6470 The specific value that defines "set" is implementation defined, and
6471 is normally based on what is performed by the native atomic test and set
6474 @cindex @code{mem_thread_fence@var{mode}} instruction pattern
6475 @item @samp{mem_thread_fence@var{mode}}
6476 This pattern emits code required to implement a thread fence with
6477 memory model semantics. Operand 0 is the memory model to be used.
6479 If this pattern is not specified, all memory models except
6480 @code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize}
6483 @cindex @code{mem_signal_fence@var{mode}} instruction pattern
6484 @item @samp{mem_signal_fence@var{mode}}
6485 This pattern emits code required to implement a signal fence with
6486 memory model semantics. Operand 0 is the memory model to be used.
6488 This pattern should impact the compiler optimizers the same way that
6489 mem_signal_fence does, but it does not need to issue any barrier
6492 If this pattern is not specified, all memory models except
6493 @code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize}
6496 @cindex @code{get_thread_pointer@var{mode}} instruction pattern
6497 @cindex @code{set_thread_pointer@var{mode}} instruction pattern
6498 @item @samp{get_thread_pointer@var{mode}}
6499 @itemx @samp{set_thread_pointer@var{mode}}
6500 These patterns emit code that reads/sets the TLS thread pointer. Currently,
6501 these are only needed if the target needs to support the
6502 @code{__builtin_thread_pointer} and @code{__builtin_set_thread_pointer}
6505 The get/set patterns have a single output/input operand respectively,
6506 with @var{mode} intended to be @code{Pmode}.
6508 @cindex @code{stack_protect_set} instruction pattern
6509 @item @samp{stack_protect_set}
6510 This pattern, if defined, moves a @code{ptr_mode} value from the memory
6511 in operand 1 to the memory in operand 0 without leaving the value in
6512 a register afterward. This is to avoid leaking the value some place
6513 that an attacker might use to rewrite the stack guard slot after
6514 having clobbered it.
6516 If this pattern is not defined, then a plain move pattern is generated.
6518 @cindex @code{stack_protect_test} instruction pattern
6519 @item @samp{stack_protect_test}
6520 This pattern, if defined, compares a @code{ptr_mode} value from the
6521 memory in operand 1 with the memory in operand 0 without leaving the
6522 value in a register afterward and branches to operand 2 if the values
6525 If this pattern is not defined, then a plain compare pattern and
6526 conditional branch pattern is used.
6528 @cindex @code{clear_cache} instruction pattern
6529 @item @samp{clear_cache}
6530 This pattern, if defined, flushes the instruction cache for a region of
6531 memory. The region is bounded to by the Pmode pointers in operand 0
6532 inclusive and operand 1 exclusive.
6534 If this pattern is not defined, a call to the library function
6535 @code{__clear_cache} is used.
6540 @c Each of the following nodes are wrapped in separate
6541 @c "@ifset INTERNALS" to work around memory limits for the default
6542 @c configuration in older tetex distributions. Known to not work:
6543 @c tetex-1.0.7, known to work: tetex-2.0.2.
6545 @node Pattern Ordering
6546 @section When the Order of Patterns Matters
6547 @cindex Pattern Ordering
6548 @cindex Ordering of Patterns
6550 Sometimes an insn can match more than one instruction pattern. Then the
6551 pattern that appears first in the machine description is the one used.
6552 Therefore, more specific patterns (patterns that will match fewer things)
6553 and faster instructions (those that will produce better code when they
6554 do match) should usually go first in the description.
6556 In some cases the effect of ordering the patterns can be used to hide
6557 a pattern when it is not valid. For example, the 68000 has an
6558 instruction for converting a fullword to floating point and another
6559 for converting a byte to floating point. An instruction converting
6560 an integer to floating point could match either one. We put the
6561 pattern to convert the fullword first to make sure that one will
6562 be used rather than the other. (Otherwise a large integer might
6563 be generated as a single-byte immediate quantity, which would not work.)
6564 Instead of using this pattern ordering it would be possible to make the
6565 pattern for convert-a-byte smart enough to deal properly with any
6570 @node Dependent Patterns
6571 @section Interdependence of Patterns
6572 @cindex Dependent Patterns
6573 @cindex Interdependence of Patterns
6575 In some cases machines support instructions identical except for the
6576 machine mode of one or more operands. For example, there may be
6577 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
6581 (set (match_operand:SI 0 @dots{})
6582 (extend:SI (match_operand:HI 1 @dots{})))
6584 (set (match_operand:SI 0 @dots{})
6585 (extend:SI (match_operand:QI 1 @dots{})))
6589 Constant integers do not specify a machine mode, so an instruction to
6590 extend a constant value could match either pattern. The pattern it
6591 actually will match is the one that appears first in the file. For correct
6592 results, this must be the one for the widest possible mode (@code{HImode},
6593 here). If the pattern matches the @code{QImode} instruction, the results
6594 will be incorrect if the constant value does not actually fit that mode.
6596 Such instructions to extend constants are rarely generated because they are
6597 optimized away, but they do occasionally happen in nonoptimized
6600 If a constraint in a pattern allows a constant, the reload pass may
6601 replace a register with a constant permitted by the constraint in some
6602 cases. Similarly for memory references. Because of this substitution,
6603 you should not provide separate patterns for increment and decrement
6604 instructions. Instead, they should be generated from the same pattern
6605 that supports register-register add insns by examining the operands and
6606 generating the appropriate machine instruction.
6611 @section Defining Jump Instruction Patterns
6612 @cindex jump instruction patterns
6613 @cindex defining jump instruction patterns
6615 GCC does not assume anything about how the machine realizes jumps.
6616 The machine description should define a single pattern, usually
6617 a @code{define_expand}, which expands to all the required insns.
6619 Usually, this would be a comparison insn to set the condition code
6620 and a separate branch insn testing the condition code and branching
6621 or not according to its value. For many machines, however,
6622 separating compares and branches is limiting, which is why the
6623 more flexible approach with one @code{define_expand} is used in GCC.
6624 The machine description becomes clearer for architectures that
6625 have compare-and-branch instructions but no condition code. It also
6626 works better when different sets of comparison operators are supported
6627 by different kinds of conditional branches (e.g. integer vs. floating-point),
6628 or by conditional branches with respect to conditional stores.
6630 Two separate insns are always used if the machine description represents
6631 a condition code register using the legacy RTL expression @code{(cc0)},
6632 and on most machines that use a separate condition code register
6633 (@pxref{Condition Code}). For machines that use @code{(cc0)}, in
6634 fact, the set and use of the condition code must be separate and
6635 adjacent@footnote{@code{note} insns can separate them, though.}, thus
6636 allowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and
6637 so that the comparison and branch insns could be located from each other
6638 by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}.
6640 Even in this case having a single entry point for conditional branches
6641 is advantageous, because it handles equally well the case where a single
6642 comparison instruction records the results of both signed and unsigned
6643 comparison of the given operands (with the branch insns coming in distinct
6644 signed and unsigned flavors) as in the x86 or SPARC, and the case where
6645 there are distinct signed and unsigned compare instructions and only
6646 one set of conditional branch instructions as in the PowerPC.
6650 @node Looping Patterns
6651 @section Defining Looping Instruction Patterns
6652 @cindex looping instruction patterns
6653 @cindex defining looping instruction patterns
6655 Some machines have special jump instructions that can be utilized to
6656 make loops more efficient. A common example is the 68000 @samp{dbra}
6657 instruction which performs a decrement of a register and a branch if the
6658 result was greater than zero. Other machines, in particular digital
6659 signal processors (DSPs), have special block repeat instructions to
6660 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
6661 DSPs have a block repeat instruction that loads special registers to
6662 mark the top and end of a loop and to count the number of loop
6663 iterations. This avoids the need for fetching and executing a
6664 @samp{dbra}-like instruction and avoids pipeline stalls associated with
6667 GCC has three special named patterns to support low overhead looping.
6668 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
6669 and @samp{doloop_end}. The first pattern,
6670 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
6671 generation but may be emitted during the instruction combination phase.
6672 This requires the assistance of the loop optimizer, using information
6673 collected during strength reduction, to reverse a loop to count down to
6674 zero. Some targets also require the loop optimizer to add a
6675 @code{REG_NONNEG} note to indicate that the iteration count is always
6676 positive. This is needed if the target performs a signed loop
6677 termination test. For example, the 68000 uses a pattern similar to the
6678 following for its @code{dbra} instruction:
6682 (define_insn "decrement_and_branch_until_zero"
6685 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6688 (label_ref (match_operand 1 "" ""))
6691 (plus:SI (match_dup 0)
6693 "find_reg_note (insn, REG_NONNEG, 0)"
6698 Note that since the insn is both a jump insn and has an output, it must
6699 deal with its own reloads, hence the `m' constraints. Also note that
6700 since this insn is generated by the instruction combination phase
6701 combining two sequential insns together into an implicit parallel insn,
6702 the iteration counter needs to be biased by the same amount as the
6703 decrement operation, in this case @minus{}1. Note that the following similar
6704 pattern will not be matched by the combiner.
6708 (define_insn "decrement_and_branch_until_zero"
6711 (ge (match_operand:SI 0 "general_operand" "+d*am")
6713 (label_ref (match_operand 1 "" ""))
6716 (plus:SI (match_dup 0)
6718 "find_reg_note (insn, REG_NONNEG, 0)"
6723 The other two special looping patterns, @samp{doloop_begin} and
6724 @samp{doloop_end}, are emitted by the loop optimizer for certain
6725 well-behaved loops with a finite number of loop iterations using
6726 information collected during strength reduction.
6728 The @samp{doloop_end} pattern describes the actual looping instruction
6729 (or the implicit looping operation) and the @samp{doloop_begin} pattern
6730 is an optional companion pattern that can be used for initialization
6731 needed for some low-overhead looping instructions.
6733 Note that some machines require the actual looping instruction to be
6734 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
6735 the true RTL for a looping instruction at the top of the loop can cause
6736 problems with flow analysis. So instead, a dummy @code{doloop} insn is
6737 emitted at the end of the loop. The machine dependent reorg pass checks
6738 for the presence of this @code{doloop} insn and then searches back to
6739 the top of the loop, where it inserts the true looping insn (provided
6740 there are no instructions in the loop which would cause problems). Any
6741 additional labels can be emitted at this point. In addition, if the
6742 desired special iteration counter register was not allocated, this
6743 machine dependent reorg pass could emit a traditional compare and jump
6746 The essential difference between the
6747 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
6748 patterns is that the loop optimizer allocates an additional pseudo
6749 register for the latter as an iteration counter. This pseudo register
6750 cannot be used within the loop (i.e., general induction variables cannot
6751 be derived from it), however, in many cases the loop induction variable
6752 may become redundant and removed by the flow pass.
6757 @node Insn Canonicalizations
6758 @section Canonicalization of Instructions
6759 @cindex canonicalization of instructions
6760 @cindex insn canonicalization
6762 There are often cases where multiple RTL expressions could represent an
6763 operation performed by a single machine instruction. This situation is
6764 most commonly encountered with logical, branch, and multiply-accumulate
6765 instructions. In such cases, the compiler attempts to convert these
6766 multiple RTL expressions into a single canonical form to reduce the
6767 number of insn patterns required.
6769 In addition to algebraic simplifications, following canonicalizations
6774 For commutative and comparison operators, a constant is always made the
6775 second operand. If a machine only supports a constant as the second
6776 operand, only patterns that match a constant in the second operand need
6780 For associative operators, a sequence of operators will always chain
6781 to the left; for instance, only the left operand of an integer @code{plus}
6782 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
6783 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
6784 @code{umax} are associative when applied to integers, and sometimes to
6788 @cindex @code{neg}, canonicalization of
6789 @cindex @code{not}, canonicalization of
6790 @cindex @code{mult}, canonicalization of
6791 @cindex @code{plus}, canonicalization of
6792 @cindex @code{minus}, canonicalization of
6793 For these operators, if only one operand is a @code{neg}, @code{not},
6794 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
6798 In combinations of @code{neg}, @code{mult}, @code{plus}, and
6799 @code{minus}, the @code{neg} operations (if any) will be moved inside
6800 the operations as far as possible. For instance,
6801 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
6802 @code{(plus (mult (neg B) C) A)} is canonicalized as
6803 @code{(minus A (mult B C))}.
6805 @cindex @code{compare}, canonicalization of
6807 For the @code{compare} operator, a constant is always the second operand
6808 if the first argument is a condition code register or @code{(cc0)}.
6811 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
6812 @code{minus} is made the first operand under the same conditions as
6816 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
6817 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
6821 @code{(minus @var{x} (const_int @var{n}))} is converted to
6822 @code{(plus @var{x} (const_int @var{-n}))}.
6825 Within address computations (i.e., inside @code{mem}), a left shift is
6826 converted into the appropriate multiplication by a power of two.
6828 @cindex @code{ior}, canonicalization of
6829 @cindex @code{and}, canonicalization of
6830 @cindex De Morgan's law
6832 De Morgan's Law is used to move bitwise negation inside a bitwise
6833 logical-and or logical-or operation. If this results in only one
6834 operand being a @code{not} expression, it will be the first one.
6836 A machine that has an instruction that performs a bitwise logical-and of one
6837 operand with the bitwise negation of the other should specify the pattern
6838 for that instruction as
6842 [(set (match_operand:@var{m} 0 @dots{})
6843 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
6844 (match_operand:@var{m} 2 @dots{})))]
6850 Similarly, a pattern for a ``NAND'' instruction should be written
6854 [(set (match_operand:@var{m} 0 @dots{})
6855 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
6856 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
6861 In both cases, it is not necessary to include patterns for the many
6862 logically equivalent RTL expressions.
6864 @cindex @code{xor}, canonicalization of
6866 The only possible RTL expressions involving both bitwise exclusive-or
6867 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
6868 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
6871 The sum of three items, one of which is a constant, will only appear in
6875 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
6878 @cindex @code{zero_extract}, canonicalization of
6879 @cindex @code{sign_extract}, canonicalization of
6881 Equality comparisons of a group of bits (usually a single bit) with zero
6882 will be written using @code{zero_extract} rather than the equivalent
6883 @code{and} or @code{sign_extract} operations.
6885 @cindex @code{mult}, canonicalization of
6887 @code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
6888 (sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
6889 (sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise
6890 for @code{zero_extend}.
6893 @code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
6894 @var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
6895 to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
6896 @var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
6897 patterns using @code{zero_extend} and @code{lshiftrt}. If the second
6898 operand of @code{mult} is also a shift, then that is extended also.
6899 This transformation is only applied when it can be proven that the
6900 original operation had sufficient precision to prevent overflow.
6904 Further canonicalization rules are defined in the function
6905 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
6909 @node Expander Definitions
6910 @section Defining RTL Sequences for Code Generation
6911 @cindex expander definitions
6912 @cindex code generation RTL sequences
6913 @cindex defining RTL sequences for code generation
6915 On some target machines, some standard pattern names for RTL generation
6916 cannot be handled with single insn, but a sequence of RTL insns can
6917 represent them. For these target machines, you can write a
6918 @code{define_expand} to specify how to generate the sequence of RTL@.
6920 @findex define_expand
6921 A @code{define_expand} is an RTL expression that looks almost like a
6922 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
6923 only for RTL generation and it can produce more than one RTL insn.
6925 A @code{define_expand} RTX has four operands:
6929 The name. Each @code{define_expand} must have a name, since the only
6930 use for it is to refer to it by name.
6933 The RTL template. This is a vector of RTL expressions representing
6934 a sequence of separate instructions. Unlike @code{define_insn}, there
6935 is no implicit surrounding @code{PARALLEL}.
6938 The condition, a string containing a C expression. This expression is
6939 used to express how the availability of this pattern depends on
6940 subclasses of target machine, selected by command-line options when GCC
6941 is run. This is just like the condition of a @code{define_insn} that
6942 has a standard name. Therefore, the condition (if present) may not
6943 depend on the data in the insn being matched, but only the
6944 target-machine-type flags. The compiler needs to test these conditions
6945 during initialization in order to learn exactly which named instructions
6946 are available in a particular run.
6949 The preparation statements, a string containing zero or more C
6950 statements which are to be executed before RTL code is generated from
6953 Usually these statements prepare temporary registers for use as
6954 internal operands in the RTL template, but they can also generate RTL
6955 insns directly by calling routines such as @code{emit_insn}, etc.
6956 Any such insns precede the ones that come from the RTL template.
6959 Optionally, a vector containing the values of attributes. @xref{Insn
6963 Every RTL insn emitted by a @code{define_expand} must match some
6964 @code{define_insn} in the machine description. Otherwise, the compiler
6965 will crash when trying to generate code for the insn or trying to optimize
6968 The RTL template, in addition to controlling generation of RTL insns,
6969 also describes the operands that need to be specified when this pattern
6970 is used. In particular, it gives a predicate for each operand.
6972 A true operand, which needs to be specified in order to generate RTL from
6973 the pattern, should be described with a @code{match_operand} in its first
6974 occurrence in the RTL template. This enters information on the operand's
6975 predicate into the tables that record such things. GCC uses the
6976 information to preload the operand into a register if that is required for
6977 valid RTL code. If the operand is referred to more than once, subsequent
6978 references should use @code{match_dup}.
6980 The RTL template may also refer to internal ``operands'' which are
6981 temporary registers or labels used only within the sequence made by the
6982 @code{define_expand}. Internal operands are substituted into the RTL
6983 template with @code{match_dup}, never with @code{match_operand}. The
6984 values of the internal operands are not passed in as arguments by the
6985 compiler when it requests use of this pattern. Instead, they are computed
6986 within the pattern, in the preparation statements. These statements
6987 compute the values and store them into the appropriate elements of
6988 @code{operands} so that @code{match_dup} can find them.
6990 There are two special macros defined for use in the preparation statements:
6991 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
6998 Use the @code{DONE} macro to end RTL generation for the pattern. The
6999 only RTL insns resulting from the pattern on this occasion will be
7000 those already emitted by explicit calls to @code{emit_insn} within the
7001 preparation statements; the RTL template will not be generated.
7005 Make the pattern fail on this occasion. When a pattern fails, it means
7006 that the pattern was not truly available. The calling routines in the
7007 compiler will try other strategies for code generation using other patterns.
7009 Failure is currently supported only for binary (addition, multiplication,
7010 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
7014 If the preparation falls through (invokes neither @code{DONE} nor
7015 @code{FAIL}), then the @code{define_expand} acts like a
7016 @code{define_insn} in that the RTL template is used to generate the
7019 The RTL template is not used for matching, only for generating the
7020 initial insn list. If the preparation statement always invokes
7021 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
7022 list of operands, such as this example:
7026 (define_expand "addsi3"
7027 [(match_operand:SI 0 "register_operand" "")
7028 (match_operand:SI 1 "register_operand" "")
7029 (match_operand:SI 2 "register_operand" "")]
7035 handle_add (operands[0], operands[1], operands[2]);
7041 Here is an example, the definition of left-shift for the SPUR chip:
7045 (define_expand "ashlsi3"
7046 [(set (match_operand:SI 0 "register_operand" "")
7050 (match_operand:SI 1 "register_operand" "")
7051 (match_operand:SI 2 "nonmemory_operand" "")))]
7060 if (GET_CODE (operands[2]) != CONST_INT
7061 || (unsigned) INTVAL (operands[2]) > 3)
7068 This example uses @code{define_expand} so that it can generate an RTL insn
7069 for shifting when the shift-count is in the supported range of 0 to 3 but
7070 fail in other cases where machine insns aren't available. When it fails,
7071 the compiler tries another strategy using different patterns (such as, a
7074 If the compiler were able to handle nontrivial condition-strings in
7075 patterns with names, then it would be possible to use a
7076 @code{define_insn} in that case. Here is another case (zero-extension
7077 on the 68000) which makes more use of the power of @code{define_expand}:
7080 (define_expand "zero_extendhisi2"
7081 [(set (match_operand:SI 0 "general_operand" "")
7083 (set (strict_low_part
7087 (match_operand:HI 1 "general_operand" ""))]
7089 "operands[1] = make_safe_from (operands[1], operands[0]);")
7093 @findex make_safe_from
7094 Here two RTL insns are generated, one to clear the entire output operand
7095 and the other to copy the input operand into its low half. This sequence
7096 is incorrect if the input operand refers to [the old value of] the output
7097 operand, so the preparation statement makes sure this isn't so. The
7098 function @code{make_safe_from} copies the @code{operands[1]} into a
7099 temporary register if it refers to @code{operands[0]}. It does this
7100 by emitting another RTL insn.
7102 Finally, a third example shows the use of an internal operand.
7103 Zero-extension on the SPUR chip is done by @code{and}-ing the result
7104 against a halfword mask. But this mask cannot be represented by a
7105 @code{const_int} because the constant value is too large to be legitimate
7106 on this machine. So it must be copied into a register with
7107 @code{force_reg} and then the register used in the @code{and}.
7110 (define_expand "zero_extendhisi2"
7111 [(set (match_operand:SI 0 "register_operand" "")
7113 (match_operand:HI 1 "register_operand" "")
7118 = force_reg (SImode, GEN_INT (65535)); ")
7121 @emph{Note:} If the @code{define_expand} is used to serve a
7122 standard binary or unary arithmetic operation or a bit-field operation,
7123 then the last insn it generates must not be a @code{code_label},
7124 @code{barrier} or @code{note}. It must be an @code{insn},
7125 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
7126 at the end, emit an insn to copy the result of the operation into
7127 itself. Such an insn will generate no code, but it can avoid problems
7132 @node Insn Splitting
7133 @section Defining How to Split Instructions
7134 @cindex insn splitting
7135 @cindex instruction splitting
7136 @cindex splitting instructions
7138 There are two cases where you should specify how to split a pattern
7139 into multiple insns. On machines that have instructions requiring
7140 delay slots (@pxref{Delay Slots}) or that have instructions whose
7141 output is not available for multiple cycles (@pxref{Processor pipeline
7142 description}), the compiler phases that optimize these cases need to
7143 be able to move insns into one-instruction delay slots. However, some
7144 insns may generate more than one machine instruction. These insns
7145 cannot be placed into a delay slot.
7147 Often you can rewrite the single insn as a list of individual insns,
7148 each corresponding to one machine instruction. The disadvantage of
7149 doing so is that it will cause the compilation to be slower and require
7150 more space. If the resulting insns are too complex, it may also
7151 suppress some optimizations. The compiler splits the insn if there is a
7152 reason to believe that it might improve instruction or delay slot
7155 The insn combiner phase also splits putative insns. If three insns are
7156 merged into one insn with a complex expression that cannot be matched by
7157 some @code{define_insn} pattern, the combiner phase attempts to split
7158 the complex pattern into two insns that are recognized. Usually it can
7159 break the complex pattern into two patterns by splitting out some
7160 subexpression. However, in some other cases, such as performing an
7161 addition of a large constant in two insns on a RISC machine, the way to
7162 split the addition into two insns is machine-dependent.
7164 @findex define_split
7165 The @code{define_split} definition tells the compiler how to split a
7166 complex insn into several simpler insns. It looks like this:
7170 [@var{insn-pattern}]
7172 [@var{new-insn-pattern-1}
7173 @var{new-insn-pattern-2}
7175 "@var{preparation-statements}")
7178 @var{insn-pattern} is a pattern that needs to be split and
7179 @var{condition} is the final condition to be tested, as in a
7180 @code{define_insn}. When an insn matching @var{insn-pattern} and
7181 satisfying @var{condition} is found, it is replaced in the insn list
7182 with the insns given by @var{new-insn-pattern-1},
7183 @var{new-insn-pattern-2}, etc.
7185 The @var{preparation-statements} are similar to those statements that
7186 are specified for @code{define_expand} (@pxref{Expander Definitions})
7187 and are executed before the new RTL is generated to prepare for the
7188 generated code or emit some insns whose pattern is not fixed. Unlike
7189 those in @code{define_expand}, however, these statements must not
7190 generate any new pseudo-registers. Once reload has completed, they also
7191 must not allocate any space in the stack frame.
7193 Patterns are matched against @var{insn-pattern} in two different
7194 circumstances. If an insn needs to be split for delay slot scheduling
7195 or insn scheduling, the insn is already known to be valid, which means
7196 that it must have been matched by some @code{define_insn} and, if
7197 @code{reload_completed} is nonzero, is known to satisfy the constraints
7198 of that @code{define_insn}. In that case, the new insn patterns must
7199 also be insns that are matched by some @code{define_insn} and, if
7200 @code{reload_completed} is nonzero, must also satisfy the constraints
7201 of those definitions.
7203 As an example of this usage of @code{define_split}, consider the following
7204 example from @file{a29k.md}, which splits a @code{sign_extend} from
7205 @code{HImode} to @code{SImode} into a pair of shift insns:
7209 [(set (match_operand:SI 0 "gen_reg_operand" "")
7210 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
7213 (ashift:SI (match_dup 1)
7216 (ashiftrt:SI (match_dup 0)
7219 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
7222 When the combiner phase tries to split an insn pattern, it is always the
7223 case that the pattern is @emph{not} matched by any @code{define_insn}.
7224 The combiner pass first tries to split a single @code{set} expression
7225 and then the same @code{set} expression inside a @code{parallel}, but
7226 followed by a @code{clobber} of a pseudo-reg to use as a scratch
7227 register. In these cases, the combiner expects exactly two new insn
7228 patterns to be generated. It will verify that these patterns match some
7229 @code{define_insn} definitions, so you need not do this test in the
7230 @code{define_split} (of course, there is no point in writing a
7231 @code{define_split} that will never produce insns that match).
7233 Here is an example of this use of @code{define_split}, taken from
7238 [(set (match_operand:SI 0 "gen_reg_operand" "")
7239 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
7240 (match_operand:SI 2 "non_add_cint_operand" "")))]
7242 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
7243 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
7246 int low = INTVAL (operands[2]) & 0xffff;
7247 int high = (unsigned) INTVAL (operands[2]) >> 16;
7250 high++, low |= 0xffff0000;
7252 operands[3] = GEN_INT (high << 16);
7253 operands[4] = GEN_INT (low);
7257 Here the predicate @code{non_add_cint_operand} matches any
7258 @code{const_int} that is @emph{not} a valid operand of a single add
7259 insn. The add with the smaller displacement is written so that it
7260 can be substituted into the address of a subsequent operation.
7262 An example that uses a scratch register, from the same file, generates
7263 an equality comparison of a register and a large constant:
7267 [(set (match_operand:CC 0 "cc_reg_operand" "")
7268 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
7269 (match_operand:SI 2 "non_short_cint_operand" "")))
7270 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
7271 "find_single_use (operands[0], insn, 0)
7272 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
7273 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
7274 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
7275 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
7278 /* @r{Get the constant we are comparing against, C, and see what it
7279 looks like sign-extended to 16 bits. Then see what constant
7280 could be XOR'ed with C to get the sign-extended value.} */
7282 int c = INTVAL (operands[2]);
7283 int sextc = (c << 16) >> 16;
7284 int xorv = c ^ sextc;
7286 operands[4] = GEN_INT (xorv);
7287 operands[5] = GEN_INT (sextc);
7291 To avoid confusion, don't write a single @code{define_split} that
7292 accepts some insns that match some @code{define_insn} as well as some
7293 insns that don't. Instead, write two separate @code{define_split}
7294 definitions, one for the insns that are valid and one for the insns that
7297 The splitter is allowed to split jump instructions into sequence of
7298 jumps or create new jumps in while splitting non-jump instructions. As
7299 the central flowgraph and branch prediction information needs to be updated,
7300 several restriction apply.
7302 Splitting of jump instruction into sequence that over by another jump
7303 instruction is always valid, as compiler expect identical behavior of new
7304 jump. When new sequence contains multiple jump instructions or new labels,
7305 more assistance is needed. Splitter is required to create only unconditional
7306 jumps, or simple conditional jump instructions. Additionally it must attach a
7307 @code{REG_BR_PROB} note to each conditional jump. A global variable
7308 @code{split_branch_probability} holds the probability of the original branch in case
7309 it was a simple conditional jump, @minus{}1 otherwise. To simplify
7310 recomputing of edge frequencies, the new sequence is required to have only
7311 forward jumps to the newly created labels.
7313 @findex define_insn_and_split
7314 For the common case where the pattern of a define_split exactly matches the
7315 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
7319 (define_insn_and_split
7320 [@var{insn-pattern}]
7322 "@var{output-template}"
7323 "@var{split-condition}"
7324 [@var{new-insn-pattern-1}
7325 @var{new-insn-pattern-2}
7327 "@var{preparation-statements}"
7328 [@var{insn-attributes}])
7332 @var{insn-pattern}, @var{condition}, @var{output-template}, and
7333 @var{insn-attributes} are used as in @code{define_insn}. The
7334 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
7335 in a @code{define_split}. The @var{split-condition} is also used as in
7336 @code{define_split}, with the additional behavior that if the condition starts
7337 with @samp{&&}, the condition used for the split will be the constructed as a
7338 logical ``and'' of the split condition with the insn condition. For example,
7342 (define_insn_and_split "zero_extendhisi2_and"
7343 [(set (match_operand:SI 0 "register_operand" "=r")
7344 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
7345 (clobber (reg:CC 17))]
7346 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
7348 "&& reload_completed"
7349 [(parallel [(set (match_dup 0)
7350 (and:SI (match_dup 0) (const_int 65535)))
7351 (clobber (reg:CC 17))])]
7353 [(set_attr "type" "alu1")])
7357 In this case, the actual split condition will be
7358 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
7360 The @code{define_insn_and_split} construction provides exactly the same
7361 functionality as two separate @code{define_insn} and @code{define_split}
7362 patterns. It exists for compactness, and as a maintenance tool to prevent
7363 having to ensure the two patterns' templates match.
7367 @node Including Patterns
7368 @section Including Patterns in Machine Descriptions.
7369 @cindex insn includes
7372 The @code{include} pattern tells the compiler tools where to
7373 look for patterns that are in files other than in the file
7374 @file{.md}. This is used only at build time and there is no preprocessing allowed.
7388 (include "filestuff")
7392 Where @var{pathname} is a string that specifies the location of the file,
7393 specifies the include file to be in @file{gcc/config/target/filestuff}. The
7394 directory @file{gcc/config/target} is regarded as the default directory.
7397 Machine descriptions may be split up into smaller more manageable subsections
7398 and placed into subdirectories.
7404 (include "BOGUS/filestuff")
7408 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
7410 Specifying an absolute path for the include file such as;
7413 (include "/u2/BOGUS/filestuff")
7416 is permitted but is not encouraged.
7418 @subsection RTL Generation Tool Options for Directory Search
7419 @cindex directory options .md
7420 @cindex options, directory search
7421 @cindex search options
7423 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
7428 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
7433 Add the directory @var{dir} to the head of the list of directories to be
7434 searched for header files. This can be used to override a system machine definition
7435 file, substituting your own version, since these directories are
7436 searched before the default machine description file directories. If you use more than
7437 one @option{-I} option, the directories are scanned in left-to-right
7438 order; the standard default directory come after.
7443 @node Peephole Definitions
7444 @section Machine-Specific Peephole Optimizers
7445 @cindex peephole optimizer definitions
7446 @cindex defining peephole optimizers
7448 In addition to instruction patterns the @file{md} file may contain
7449 definitions of machine-specific peephole optimizations.
7451 The combiner does not notice certain peephole optimizations when the data
7452 flow in the program does not suggest that it should try them. For example,
7453 sometimes two consecutive insns related in purpose can be combined even
7454 though the second one does not appear to use a register computed in the
7455 first one. A machine-specific peephole optimizer can detect such
7458 There are two forms of peephole definitions that may be used. The
7459 original @code{define_peephole} is run at assembly output time to
7460 match insns and substitute assembly text. Use of @code{define_peephole}
7463 A newer @code{define_peephole2} matches insns and substitutes new
7464 insns. The @code{peephole2} pass is run after register allocation
7465 but before scheduling, which may result in much better code for
7466 targets that do scheduling.
7469 * define_peephole:: RTL to Text Peephole Optimizers
7470 * define_peephole2:: RTL to RTL Peephole Optimizers
7475 @node define_peephole
7476 @subsection RTL to Text Peephole Optimizers
7477 @findex define_peephole
7480 A definition looks like this:
7484 [@var{insn-pattern-1}
7485 @var{insn-pattern-2}
7489 "@var{optional-insn-attributes}")
7493 The last string operand may be omitted if you are not using any
7494 machine-specific information in this machine description. If present,
7495 it must obey the same rules as in a @code{define_insn}.
7497 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
7498 consecutive insns. The optimization applies to a sequence of insns when
7499 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
7500 the next, and so on.
7502 Each of the insns matched by a peephole must also match a
7503 @code{define_insn}. Peepholes are checked only at the last stage just
7504 before code generation, and only optionally. Therefore, any insn which
7505 would match a peephole but no @code{define_insn} will cause a crash in code
7506 generation in an unoptimized compilation, or at various optimization
7509 The operands of the insns are matched with @code{match_operands},
7510 @code{match_operator}, and @code{match_dup}, as usual. What is not
7511 usual is that the operand numbers apply to all the insn patterns in the
7512 definition. So, you can check for identical operands in two insns by
7513 using @code{match_operand} in one insn and @code{match_dup} in the
7516 The operand constraints used in @code{match_operand} patterns do not have
7517 any direct effect on the applicability of the peephole, but they will
7518 be validated afterward, so make sure your constraints are general enough
7519 to apply whenever the peephole matches. If the peephole matches
7520 but the constraints are not satisfied, the compiler will crash.
7522 It is safe to omit constraints in all the operands of the peephole; or
7523 you can write constraints which serve as a double-check on the criteria
7526 Once a sequence of insns matches the patterns, the @var{condition} is
7527 checked. This is a C expression which makes the final decision whether to
7528 perform the optimization (we do so if the expression is nonzero). If
7529 @var{condition} is omitted (in other words, the string is empty) then the
7530 optimization is applied to every sequence of insns that matches the
7533 The defined peephole optimizations are applied after register allocation
7534 is complete. Therefore, the peephole definition can check which
7535 operands have ended up in which kinds of registers, just by looking at
7538 @findex prev_active_insn
7539 The way to refer to the operands in @var{condition} is to write
7540 @code{operands[@var{i}]} for operand number @var{i} (as matched by
7541 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
7542 to refer to the last of the insns being matched; use
7543 @code{prev_active_insn} to find the preceding insns.
7545 @findex dead_or_set_p
7546 When optimizing computations with intermediate results, you can use
7547 @var{condition} to match only when the intermediate results are not used
7548 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
7549 @var{op})}, where @var{insn} is the insn in which you expect the value
7550 to be used for the last time (from the value of @code{insn}, together
7551 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
7552 value (from @code{operands[@var{i}]}).
7554 Applying the optimization means replacing the sequence of insns with one
7555 new insn. The @var{template} controls ultimate output of assembler code
7556 for this combined insn. It works exactly like the template of a
7557 @code{define_insn}. Operand numbers in this template are the same ones
7558 used in matching the original sequence of insns.
7560 The result of a defined peephole optimizer does not need to match any of
7561 the insn patterns in the machine description; it does not even have an
7562 opportunity to match them. The peephole optimizer definition itself serves
7563 as the insn pattern to control how the insn is output.
7565 Defined peephole optimizers are run as assembler code is being output,
7566 so the insns they produce are never combined or rearranged in any way.
7568 Here is an example, taken from the 68000 machine description:
7572 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
7573 (set (match_operand:DF 0 "register_operand" "=f")
7574 (match_operand:DF 1 "register_operand" "ad"))]
7575 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
7578 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7580 output_asm_insn ("move.l %1,(sp)", xoperands);
7581 output_asm_insn ("move.l %1,-(sp)", operands);
7582 return "fmove.d (sp)+,%0";
7584 output_asm_insn ("movel %1,sp@@", xoperands);
7585 output_asm_insn ("movel %1,sp@@-", operands);
7586 return "fmoved sp@@+,%0";
7592 The effect of this optimization is to change
7618 If a peephole matches a sequence including one or more jump insns, you must
7619 take account of the flags such as @code{CC_REVERSED} which specify that the
7620 condition codes are represented in an unusual manner. The compiler
7621 automatically alters any ordinary conditional jumps which occur in such
7622 situations, but the compiler cannot alter jumps which have been replaced by
7623 peephole optimizations. So it is up to you to alter the assembler code
7624 that the peephole produces. Supply C code to write the assembler output,
7625 and in this C code check the condition code status flags and change the
7626 assembler code as appropriate.
7629 @var{insn-pattern-1} and so on look @emph{almost} like the second
7630 operand of @code{define_insn}. There is one important difference: the
7631 second operand of @code{define_insn} consists of one or more RTX's
7632 enclosed in square brackets. Usually, there is only one: then the same
7633 action can be written as an element of a @code{define_peephole}. But
7634 when there are multiple actions in a @code{define_insn}, they are
7635 implicitly enclosed in a @code{parallel}. Then you must explicitly
7636 write the @code{parallel}, and the square brackets within it, in the
7637 @code{define_peephole}. Thus, if an insn pattern looks like this,
7640 (define_insn "divmodsi4"
7641 [(set (match_operand:SI 0 "general_operand" "=d")
7642 (div:SI (match_operand:SI 1 "general_operand" "0")
7643 (match_operand:SI 2 "general_operand" "dmsK")))
7644 (set (match_operand:SI 3 "general_operand" "=d")
7645 (mod:SI (match_dup 1) (match_dup 2)))]
7647 "divsl%.l %2,%3:%0")
7651 then the way to mention this insn in a peephole is as follows:
7657 [(set (match_operand:SI 0 "general_operand" "=d")
7658 (div:SI (match_operand:SI 1 "general_operand" "0")
7659 (match_operand:SI 2 "general_operand" "dmsK")))
7660 (set (match_operand:SI 3 "general_operand" "=d")
7661 (mod:SI (match_dup 1) (match_dup 2)))])
7668 @node define_peephole2
7669 @subsection RTL to RTL Peephole Optimizers
7670 @findex define_peephole2
7672 The @code{define_peephole2} definition tells the compiler how to
7673 substitute one sequence of instructions for another sequence,
7674 what additional scratch registers may be needed and what their
7679 [@var{insn-pattern-1}
7680 @var{insn-pattern-2}
7683 [@var{new-insn-pattern-1}
7684 @var{new-insn-pattern-2}
7686 "@var{preparation-statements}")
7689 The definition is almost identical to @code{define_split}
7690 (@pxref{Insn Splitting}) except that the pattern to match is not a
7691 single instruction, but a sequence of instructions.
7693 It is possible to request additional scratch registers for use in the
7694 output template. If appropriate registers are not free, the pattern
7695 will simply not match.
7697 @findex match_scratch
7699 Scratch registers are requested with a @code{match_scratch} pattern at
7700 the top level of the input pattern. The allocated register (initially) will
7701 be dead at the point requested within the original sequence. If the scratch
7702 is used at more than a single point, a @code{match_dup} pattern at the
7703 top level of the input pattern marks the last position in the input sequence
7704 at which the register must be available.
7706 Here is an example from the IA-32 machine description:
7710 [(match_scratch:SI 2 "r")
7711 (parallel [(set (match_operand:SI 0 "register_operand" "")
7712 (match_operator:SI 3 "arith_or_logical_operator"
7714 (match_operand:SI 1 "memory_operand" "")]))
7715 (clobber (reg:CC 17))])]
7716 "! optimize_size && ! TARGET_READ_MODIFY"
7717 [(set (match_dup 2) (match_dup 1))
7718 (parallel [(set (match_dup 0)
7719 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
7720 (clobber (reg:CC 17))])]
7725 This pattern tries to split a load from its use in the hopes that we'll be
7726 able to schedule around the memory load latency. It allocates a single
7727 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
7728 to be live only at the point just before the arithmetic.
7730 A real example requiring extended scratch lifetimes is harder to come by,
7731 so here's a silly made-up example:
7735 [(match_scratch:SI 4 "r")
7736 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
7737 (set (match_operand:SI 2 "" "") (match_dup 1))
7739 (set (match_operand:SI 3 "" "") (match_dup 1))]
7740 "/* @r{determine 1 does not overlap 0 and 2} */"
7741 [(set (match_dup 4) (match_dup 1))
7742 (set (match_dup 0) (match_dup 4))
7743 (set (match_dup 2) (match_dup 4))
7744 (set (match_dup 3) (match_dup 4))]
7749 If we had not added the @code{(match_dup 4)} in the middle of the input
7750 sequence, it might have been the case that the register we chose at the
7751 beginning of the sequence is killed by the first or second @code{set}.
7755 @node Insn Attributes
7756 @section Instruction Attributes
7757 @cindex insn attributes
7758 @cindex instruction attributes
7760 In addition to describing the instruction supported by the target machine,
7761 the @file{md} file also defines a group of @dfn{attributes} and a set of
7762 values for each. Every generated insn is assigned a value for each attribute.
7763 One possible attribute would be the effect that the insn has on the machine's
7764 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
7765 to track the condition codes.
7768 * Defining Attributes:: Specifying attributes and their values.
7769 * Expressions:: Valid expressions for attribute values.
7770 * Tagging Insns:: Assigning attribute values to insns.
7771 * Attr Example:: An example of assigning attributes.
7772 * Insn Lengths:: Computing the length of insns.
7773 * Constant Attributes:: Defining attributes that are constant.
7774 * Mnemonic Attribute:: Obtain the instruction mnemonic as attribute value.
7775 * Delay Slots:: Defining delay slots required for a machine.
7776 * Processor pipeline description:: Specifying information for insn scheduling.
7781 @node Defining Attributes
7782 @subsection Defining Attributes and their Values
7783 @cindex defining attributes and their values
7784 @cindex attributes, defining
7787 The @code{define_attr} expression is used to define each attribute required
7788 by the target machine. It looks like:
7791 (define_attr @var{name} @var{list-of-values} @var{default})
7794 @var{name} is a string specifying the name of the attribute being
7795 defined. Some attributes are used in a special way by the rest of the
7796 compiler. The @code{enabled} attribute can be used to conditionally
7797 enable or disable insn alternatives (@pxref{Disable Insn
7798 Alternatives}). The @code{predicable} attribute, together with a
7799 suitable @code{define_cond_exec} (@pxref{Conditional Execution}), can
7800 be used to automatically generate conditional variants of instruction
7801 patterns. The @code{mnemonic} attribute can be used to check for the
7802 instruction mnemonic (@pxref{Mnemonic Attribute}). The compiler
7803 internally uses the names @code{ce_enabled} and @code{nonce_enabled},
7804 so they should not be used elsewhere as alternative names.
7806 @var{list-of-values} is either a string that specifies a comma-separated
7807 list of values that can be assigned to the attribute, or a null string to
7808 indicate that the attribute takes numeric values.
7810 @var{default} is an attribute expression that gives the value of this
7811 attribute for insns that match patterns whose definition does not include
7812 an explicit value for this attribute. @xref{Attr Example}, for more
7813 information on the handling of defaults. @xref{Constant Attributes},
7814 for information on attributes that do not depend on any particular insn.
7817 For each defined attribute, a number of definitions are written to the
7818 @file{insn-attr.h} file. For cases where an explicit set of values is
7819 specified for an attribute, the following are defined:
7823 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
7826 An enumerated class is defined for @samp{attr_@var{name}} with
7827 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
7828 the attribute name and value are first converted to uppercase.
7831 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
7832 returns the attribute value for that insn.
7835 For example, if the following is present in the @file{md} file:
7838 (define_attr "type" "branch,fp,load,store,arith" @dots{})
7842 the following lines will be written to the file @file{insn-attr.h}.
7845 #define HAVE_ATTR_type 1
7846 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
7847 TYPE_STORE, TYPE_ARITH@};
7848 extern enum attr_type get_attr_type ();
7851 If the attribute takes numeric values, no @code{enum} type will be
7852 defined and the function to obtain the attribute's value will return
7855 There are attributes which are tied to a specific meaning. These
7856 attributes are not free to use for other purposes:
7860 The @code{length} attribute is used to calculate the length of emitted
7861 code chunks. This is especially important when verifying branch
7862 distances. @xref{Insn Lengths}.
7865 The @code{enabled} attribute can be defined to prevent certain
7866 alternatives of an insn definition from being used during code
7867 generation. @xref{Disable Insn Alternatives}.
7870 The @code{mnemonic} attribute can be defined to implement instruction
7871 specific checks in e.g. the pipeline description.
7872 @xref{Mnemonic Attribute}.
7875 For each of these special attributes, the corresponding
7876 @samp{HAVE_ATTR_@var{name}} @samp{#define} is also written when the
7877 attribute is not defined; in that case, it is defined as @samp{0}.
7879 @findex define_enum_attr
7880 @anchor{define_enum_attr}
7881 Another way of defining an attribute is to use:
7884 (define_enum_attr "@var{attr}" "@var{enum}" @var{default})
7887 This works in just the same way as @code{define_attr}, except that
7888 the list of values is taken from a separate enumeration called
7889 @var{enum} (@pxref{define_enum}). This form allows you to use
7890 the same list of values for several attributes without having to
7891 repeat the list each time. For example:
7894 (define_enum "processor" [
7899 (define_enum_attr "arch" "processor"
7900 (const (symbol_ref "target_arch")))
7901 (define_enum_attr "tune" "processor"
7902 (const (symbol_ref "target_tune")))
7905 defines the same attributes as:
7908 (define_attr "arch" "model_a,model_b,@dots{}"
7909 (const (symbol_ref "target_arch")))
7910 (define_attr "tune" "model_a,model_b,@dots{}"
7911 (const (symbol_ref "target_tune")))
7914 but without duplicating the processor list. The second example defines two
7915 separate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first
7916 defines a single C enum (@code{processor}).
7920 @subsection Attribute Expressions
7921 @cindex attribute expressions
7923 RTL expressions used to define attributes use the codes described above
7924 plus a few specific to attribute definitions, to be discussed below.
7925 Attribute value expressions must have one of the following forms:
7928 @cindex @code{const_int} and attributes
7929 @item (const_int @var{i})
7930 The integer @var{i} specifies the value of a numeric attribute. @var{i}
7931 must be non-negative.
7933 The value of a numeric attribute can be specified either with a
7934 @code{const_int}, or as an integer represented as a string in
7935 @code{const_string}, @code{eq_attr} (see below), @code{attr},
7936 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
7937 overrides on specific instructions (@pxref{Tagging Insns}).
7939 @cindex @code{const_string} and attributes
7940 @item (const_string @var{value})
7941 The string @var{value} specifies a constant attribute value.
7942 If @var{value} is specified as @samp{"*"}, it means that the default value of
7943 the attribute is to be used for the insn containing this expression.
7944 @samp{"*"} obviously cannot be used in the @var{default} expression
7945 of a @code{define_attr}.
7947 If the attribute whose value is being specified is numeric, @var{value}
7948 must be a string containing a non-negative integer (normally
7949 @code{const_int} would be used in this case). Otherwise, it must
7950 contain one of the valid values for the attribute.
7952 @cindex @code{if_then_else} and attributes
7953 @item (if_then_else @var{test} @var{true-value} @var{false-value})
7954 @var{test} specifies an attribute test, whose format is defined below.
7955 The value of this expression is @var{true-value} if @var{test} is true,
7956 otherwise it is @var{false-value}.
7958 @cindex @code{cond} and attributes
7959 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
7960 The first operand of this expression is a vector containing an even
7961 number of expressions and consisting of pairs of @var{test} and @var{value}
7962 expressions. The value of the @code{cond} expression is that of the
7963 @var{value} corresponding to the first true @var{test} expression. If
7964 none of the @var{test} expressions are true, the value of the @code{cond}
7965 expression is that of the @var{default} expression.
7968 @var{test} expressions can have one of the following forms:
7971 @cindex @code{const_int} and attribute tests
7972 @item (const_int @var{i})
7973 This test is true if @var{i} is nonzero and false otherwise.
7975 @cindex @code{not} and attributes
7976 @cindex @code{ior} and attributes
7977 @cindex @code{and} and attributes
7978 @item (not @var{test})
7979 @itemx (ior @var{test1} @var{test2})
7980 @itemx (and @var{test1} @var{test2})
7981 These tests are true if the indicated logical function is true.
7983 @cindex @code{match_operand} and attributes
7984 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
7985 This test is true if operand @var{n} of the insn whose attribute value
7986 is being determined has mode @var{m} (this part of the test is ignored
7987 if @var{m} is @code{VOIDmode}) and the function specified by the string
7988 @var{pred} returns a nonzero value when passed operand @var{n} and mode
7989 @var{m} (this part of the test is ignored if @var{pred} is the null
7992 The @var{constraints} operand is ignored and should be the null string.
7994 @cindex @code{match_test} and attributes
7995 @item (match_test @var{c-expr})
7996 The test is true if C expression @var{c-expr} is true. In non-constant
7997 attributes, @var{c-expr} has access to the following variables:
8001 The rtl instruction under test.
8002 @item which_alternative
8003 The @code{define_insn} alternative that @var{insn} matches.
8004 @xref{Output Statement}.
8006 An array of @var{insn}'s rtl operands.
8009 @var{c-expr} behaves like the condition in a C @code{if} statement,
8010 so there is no need to explicitly convert the expression into a boolean
8011 0 or 1 value. For example, the following two tests are equivalent:
8014 (match_test "x & 2")
8015 (match_test "(x & 2) != 0")
8018 @cindex @code{le} and attributes
8019 @cindex @code{leu} and attributes
8020 @cindex @code{lt} and attributes
8021 @cindex @code{gt} and attributes
8022 @cindex @code{gtu} and attributes
8023 @cindex @code{ge} and attributes
8024 @cindex @code{geu} and attributes
8025 @cindex @code{ne} and attributes
8026 @cindex @code{eq} and attributes
8027 @cindex @code{plus} and attributes
8028 @cindex @code{minus} and attributes
8029 @cindex @code{mult} and attributes
8030 @cindex @code{div} and attributes
8031 @cindex @code{mod} and attributes
8032 @cindex @code{abs} and attributes
8033 @cindex @code{neg} and attributes
8034 @cindex @code{ashift} and attributes
8035 @cindex @code{lshiftrt} and attributes
8036 @cindex @code{ashiftrt} and attributes
8037 @item (le @var{arith1} @var{arith2})
8038 @itemx (leu @var{arith1} @var{arith2})
8039 @itemx (lt @var{arith1} @var{arith2})
8040 @itemx (ltu @var{arith1} @var{arith2})
8041 @itemx (gt @var{arith1} @var{arith2})
8042 @itemx (gtu @var{arith1} @var{arith2})
8043 @itemx (ge @var{arith1} @var{arith2})
8044 @itemx (geu @var{arith1} @var{arith2})
8045 @itemx (ne @var{arith1} @var{arith2})
8046 @itemx (eq @var{arith1} @var{arith2})
8047 These tests are true if the indicated comparison of the two arithmetic
8048 expressions is true. Arithmetic expressions are formed with
8049 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
8050 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
8051 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
8054 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
8055 Lengths},for additional forms). @code{symbol_ref} is a string
8056 denoting a C expression that yields an @code{int} when evaluated by the
8057 @samp{get_attr_@dots{}} routine. It should normally be a global
8061 @item (eq_attr @var{name} @var{value})
8062 @var{name} is a string specifying the name of an attribute.
8064 @var{value} is a string that is either a valid value for attribute
8065 @var{name}, a comma-separated list of values, or @samp{!} followed by a
8066 value or list. If @var{value} does not begin with a @samp{!}, this
8067 test is true if the value of the @var{name} attribute of the current
8068 insn is in the list specified by @var{value}. If @var{value} begins
8069 with a @samp{!}, this test is true if the attribute's value is
8070 @emph{not} in the specified list.
8075 (eq_attr "type" "load,store")
8082 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
8085 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
8086 value of the compiler variable @code{which_alternative}
8087 (@pxref{Output Statement}) and the values must be small integers. For
8091 (eq_attr "alternative" "2,3")
8098 (ior (eq (symbol_ref "which_alternative") (const_int 2))
8099 (eq (symbol_ref "which_alternative") (const_int 3)))
8102 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
8103 where the value of the attribute being tested is known for all insns matching
8104 a particular pattern. This is by far the most common case.
8107 @item (attr_flag @var{name})
8108 The value of an @code{attr_flag} expression is true if the flag
8109 specified by @var{name} is true for the @code{insn} currently being
8112 @var{name} is a string specifying one of a fixed set of flags to test.
8113 Test the flags @code{forward} and @code{backward} to determine the
8114 direction of a conditional branch.
8116 This example describes a conditional branch delay slot which
8117 can be nullified for forward branches that are taken (annul-true) or
8118 for backward branches which are not taken (annul-false).
8121 (define_delay (eq_attr "type" "cbranch")
8122 [(eq_attr "in_branch_delay" "true")
8123 (and (eq_attr "in_branch_delay" "true")
8124 (attr_flag "forward"))
8125 (and (eq_attr "in_branch_delay" "true")
8126 (attr_flag "backward"))])
8129 The @code{forward} and @code{backward} flags are false if the current
8130 @code{insn} being scheduled is not a conditional branch.
8132 @code{attr_flag} is only used during delay slot scheduling and has no
8133 meaning to other passes of the compiler.
8136 @item (attr @var{name})
8137 The value of another attribute is returned. This is most useful
8138 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
8139 produce more efficient code for non-numeric attributes.
8145 @subsection Assigning Attribute Values to Insns
8146 @cindex tagging insns
8147 @cindex assigning attribute values to insns
8149 The value assigned to an attribute of an insn is primarily determined by
8150 which pattern is matched by that insn (or which @code{define_peephole}
8151 generated it). Every @code{define_insn} and @code{define_peephole} can
8152 have an optional last argument to specify the values of attributes for
8153 matching insns. The value of any attribute not specified in a particular
8154 insn is set to the default value for that attribute, as specified in its
8155 @code{define_attr}. Extensive use of default values for attributes
8156 permits the specification of the values for only one or two attributes
8157 in the definition of most insn patterns, as seen in the example in the
8160 The optional last argument of @code{define_insn} and
8161 @code{define_peephole} is a vector of expressions, each of which defines
8162 the value for a single attribute. The most general way of assigning an
8163 attribute's value is to use a @code{set} expression whose first operand is an
8164 @code{attr} expression giving the name of the attribute being set. The
8165 second operand of the @code{set} is an attribute expression
8166 (@pxref{Expressions}) giving the value of the attribute.
8168 When the attribute value depends on the @samp{alternative} attribute
8169 (i.e., which is the applicable alternative in the constraint of the
8170 insn), the @code{set_attr_alternative} expression can be used. It
8171 allows the specification of a vector of attribute expressions, one for
8175 When the generality of arbitrary attribute expressions is not required,
8176 the simpler @code{set_attr} expression can be used, which allows
8177 specifying a string giving either a single attribute value or a list
8178 of attribute values, one for each alternative.
8180 The form of each of the above specifications is shown below. In each case,
8181 @var{name} is a string specifying the attribute to be set.
8184 @item (set_attr @var{name} @var{value-string})
8185 @var{value-string} is either a string giving the desired attribute value,
8186 or a string containing a comma-separated list giving the values for
8187 succeeding alternatives. The number of elements must match the number
8188 of alternatives in the constraint of the insn pattern.
8190 Note that it may be useful to specify @samp{*} for some alternative, in
8191 which case the attribute will assume its default value for insns matching
8194 @findex set_attr_alternative
8195 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
8196 Depending on the alternative of the insn, the value will be one of the
8197 specified values. This is a shorthand for using a @code{cond} with
8198 tests on the @samp{alternative} attribute.
8201 @item (set (attr @var{name}) @var{value})
8202 The first operand of this @code{set} must be the special RTL expression
8203 @code{attr}, whose sole operand is a string giving the name of the
8204 attribute being set. @var{value} is the value of the attribute.
8207 The following shows three different ways of representing the same
8208 attribute value specification:
8211 (set_attr "type" "load,store,arith")
8213 (set_attr_alternative "type"
8214 [(const_string "load") (const_string "store")
8215 (const_string "arith")])
8218 (cond [(eq_attr "alternative" "1") (const_string "load")
8219 (eq_attr "alternative" "2") (const_string "store")]
8220 (const_string "arith")))
8224 @findex define_asm_attributes
8225 The @code{define_asm_attributes} expression provides a mechanism to
8226 specify the attributes assigned to insns produced from an @code{asm}
8227 statement. It has the form:
8230 (define_asm_attributes [@var{attr-sets}])
8234 where @var{attr-sets} is specified the same as for both the
8235 @code{define_insn} and the @code{define_peephole} expressions.
8237 These values will typically be the ``worst case'' attribute values. For
8238 example, they might indicate that the condition code will be clobbered.
8240 A specification for a @code{length} attribute is handled specially. The
8241 way to compute the length of an @code{asm} insn is to multiply the
8242 length specified in the expression @code{define_asm_attributes} by the
8243 number of machine instructions specified in the @code{asm} statement,
8244 determined by counting the number of semicolons and newlines in the
8245 string. Therefore, the value of the @code{length} attribute specified
8246 in a @code{define_asm_attributes} should be the maximum possible length
8247 of a single machine instruction.
8252 @subsection Example of Attribute Specifications
8253 @cindex attribute specifications example
8254 @cindex attribute specifications
8256 The judicious use of defaulting is important in the efficient use of
8257 insn attributes. Typically, insns are divided into @dfn{types} and an
8258 attribute, customarily called @code{type}, is used to represent this
8259 value. This attribute is normally used only to define the default value
8260 for other attributes. An example will clarify this usage.
8262 Assume we have a RISC machine with a condition code and in which only
8263 full-word operations are performed in registers. Let us assume that we
8264 can divide all insns into loads, stores, (integer) arithmetic
8265 operations, floating point operations, and branches.
8267 Here we will concern ourselves with determining the effect of an insn on
8268 the condition code and will limit ourselves to the following possible
8269 effects: The condition code can be set unpredictably (clobbered), not
8270 be changed, be set to agree with the results of the operation, or only
8271 changed if the item previously set into the condition code has been
8274 Here is part of a sample @file{md} file for such a machine:
8277 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
8279 (define_attr "cc" "clobber,unchanged,set,change0"
8280 (cond [(eq_attr "type" "load")
8281 (const_string "change0")
8282 (eq_attr "type" "store,branch")
8283 (const_string "unchanged")
8284 (eq_attr "type" "arith")
8285 (if_then_else (match_operand:SI 0 "" "")
8286 (const_string "set")
8287 (const_string "clobber"))]
8288 (const_string "clobber")))
8291 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
8292 (match_operand:SI 1 "general_operand" "r,m,r"))]
8298 [(set_attr "type" "arith,load,store")])
8301 Note that we assume in the above example that arithmetic operations
8302 performed on quantities smaller than a machine word clobber the condition
8303 code since they will set the condition code to a value corresponding to the
8309 @subsection Computing the Length of an Insn
8310 @cindex insn lengths, computing
8311 @cindex computing the length of an insn
8313 For many machines, multiple types of branch instructions are provided, each
8314 for different length branch displacements. In most cases, the assembler
8315 will choose the correct instruction to use. However, when the assembler
8316 cannot do so, GCC can when a special attribute, the @code{length}
8317 attribute, is defined. This attribute must be defined to have numeric
8318 values by specifying a null string in its @code{define_attr}.
8320 In the case of the @code{length} attribute, two additional forms of
8321 arithmetic terms are allowed in test expressions:
8324 @cindex @code{match_dup} and attributes
8325 @item (match_dup @var{n})
8326 This refers to the address of operand @var{n} of the current insn, which
8327 must be a @code{label_ref}.
8329 @cindex @code{pc} and attributes
8331 For non-branch instructions and backward branch instructions, this refers
8332 to the address of the current insn. But for forward branch instructions,
8333 this refers to the address of the next insn, because the length of the
8334 current insn is to be computed.
8337 @cindex @code{addr_vec}, length of
8338 @cindex @code{addr_diff_vec}, length of
8339 For normal insns, the length will be determined by value of the
8340 @code{length} attribute. In the case of @code{addr_vec} and
8341 @code{addr_diff_vec} insn patterns, the length is computed as
8342 the number of vectors multiplied by the size of each vector.
8344 Lengths are measured in addressable storage units (bytes).
8346 Note that it is possible to call functions via the @code{symbol_ref}
8347 mechanism to compute the length of an insn. However, if you use this
8348 mechanism you must provide dummy clauses to express the maximum length
8349 without using the function call. You can an example of this in the
8350 @code{pa} machine description for the @code{call_symref} pattern.
8352 The following macros can be used to refine the length computation:
8355 @findex ADJUST_INSN_LENGTH
8356 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
8357 If defined, modifies the length assigned to instruction @var{insn} as a
8358 function of the context in which it is used. @var{length} is an lvalue
8359 that contains the initially computed length of the insn and should be
8360 updated with the correct length of the insn.
8362 This macro will normally not be required. A case in which it is
8363 required is the ROMP@. On this machine, the size of an @code{addr_vec}
8364 insn must be increased by two to compensate for the fact that alignment
8368 @findex get_attr_length
8369 The routine that returns @code{get_attr_length} (the value of the
8370 @code{length} attribute) can be used by the output routine to
8371 determine the form of the branch instruction to be written, as the
8372 example below illustrates.
8374 As an example of the specification of variable-length branches, consider
8375 the IBM 360. If we adopt the convention that a register will be set to
8376 the starting address of a function, we can jump to labels within 4k of
8377 the start using a four-byte instruction. Otherwise, we need a six-byte
8378 sequence to load the address from memory and then branch to it.
8380 On such a machine, a pattern for a branch instruction might be specified
8386 (label_ref (match_operand 0 "" "")))]
8389 return (get_attr_length (insn) == 4
8390 ? "b %l0" : "l r15,=a(%l0); br r15");
8392 [(set (attr "length")
8393 (if_then_else (lt (match_dup 0) (const_int 4096))
8400 @node Constant Attributes
8401 @subsection Constant Attributes
8402 @cindex constant attributes
8404 A special form of @code{define_attr}, where the expression for the
8405 default value is a @code{const} expression, indicates an attribute that
8406 is constant for a given run of the compiler. Constant attributes may be
8407 used to specify which variety of processor is used. For example,
8410 (define_attr "cpu" "m88100,m88110,m88000"
8412 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
8413 (symbol_ref "TARGET_88110") (const_string "m88110")]
8414 (const_string "m88000"))))
8416 (define_attr "memory" "fast,slow"
8418 (if_then_else (symbol_ref "TARGET_FAST_MEM")
8419 (const_string "fast")
8420 (const_string "slow"))))
8423 The routine generated for constant attributes has no parameters as it
8424 does not depend on any particular insn. RTL expressions used to define
8425 the value of a constant attribute may use the @code{symbol_ref} form,
8426 but may not use either the @code{match_operand} form or @code{eq_attr}
8427 forms involving insn attributes.
8431 @node Mnemonic Attribute
8432 @subsection Mnemonic Attribute
8433 @cindex mnemonic attribute
8435 The @code{mnemonic} attribute is a string type attribute holding the
8436 instruction mnemonic for an insn alternative. The attribute values
8437 will automatically be generated by the machine description parser if
8438 there is an attribute definition in the md file:
8441 (define_attr "mnemonic" "unknown" (const_string "unknown"))
8444 The default value can be freely chosen as long as it does not collide
8445 with any of the instruction mnemonics. This value will be used
8446 whenever the machine description parser is not able to determine the
8447 mnemonic string. This might be the case for output templates
8448 containing more than a single instruction as in
8449 @code{"mvcle\t%0,%1,0\;jo\t.-4"}.
8451 The @code{mnemonic} attribute set is not generated automatically if the
8452 instruction string is generated via C code.
8454 An existing @code{mnemonic} attribute set in an insn definition will not
8455 be overriden by the md file parser. That way it is possible to
8456 manually set the instruction mnemonics for the cases where the md file
8457 parser fails to determine it automatically.
8459 The @code{mnemonic} attribute is useful for dealing with instruction
8460 specific properties in the pipeline description without defining
8461 additional insn attributes.
8464 (define_attr "ooo_expanded" ""
8465 (cond [(eq_attr "mnemonic" "dlr,dsgr,d,dsgf,stam,dsgfr,dlgr")
8473 @subsection Delay Slot Scheduling
8474 @cindex delay slots, defining
8476 The insn attribute mechanism can be used to specify the requirements for
8477 delay slots, if any, on a target machine. An instruction is said to
8478 require a @dfn{delay slot} if some instructions that are physically
8479 after the instruction are executed as if they were located before it.
8480 Classic examples are branch and call instructions, which often execute
8481 the following instruction before the branch or call is performed.
8483 On some machines, conditional branch instructions can optionally
8484 @dfn{annul} instructions in the delay slot. This means that the
8485 instruction will not be executed for certain branch outcomes. Both
8486 instructions that annul if the branch is true and instructions that
8487 annul if the branch is false are supported.
8489 Delay slot scheduling differs from instruction scheduling in that
8490 determining whether an instruction needs a delay slot is dependent only
8491 on the type of instruction being generated, not on data flow between the
8492 instructions. See the next section for a discussion of data-dependent
8493 instruction scheduling.
8495 @findex define_delay
8496 The requirement of an insn needing one or more delay slots is indicated
8497 via the @code{define_delay} expression. It has the following form:
8500 (define_delay @var{test}
8501 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
8502 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
8506 @var{test} is an attribute test that indicates whether this
8507 @code{define_delay} applies to a particular insn. If so, the number of
8508 required delay slots is determined by the length of the vector specified
8509 as the second argument. An insn placed in delay slot @var{n} must
8510 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
8511 attribute test that specifies which insns may be annulled if the branch
8512 is true. Similarly, @var{annul-false-n} specifies which insns in the
8513 delay slot may be annulled if the branch is false. If annulling is not
8514 supported for that delay slot, @code{(nil)} should be coded.
8516 For example, in the common case where branch and call insns require
8517 a single delay slot, which may contain any insn other than a branch or
8518 call, the following would be placed in the @file{md} file:
8521 (define_delay (eq_attr "type" "branch,call")
8522 [(eq_attr "type" "!branch,call") (nil) (nil)])
8525 Multiple @code{define_delay} expressions may be specified. In this
8526 case, each such expression specifies different delay slot requirements
8527 and there must be no insn for which tests in two @code{define_delay}
8528 expressions are both true.
8530 For example, if we have a machine that requires one delay slot for branches
8531 but two for calls, no delay slot can contain a branch or call insn,
8532 and any valid insn in the delay slot for the branch can be annulled if the
8533 branch is true, we might represent this as follows:
8536 (define_delay (eq_attr "type" "branch")
8537 [(eq_attr "type" "!branch,call")
8538 (eq_attr "type" "!branch,call")
8541 (define_delay (eq_attr "type" "call")
8542 [(eq_attr "type" "!branch,call") (nil) (nil)
8543 (eq_attr "type" "!branch,call") (nil) (nil)])
8545 @c the above is *still* too long. --mew 4feb93
8549 @node Processor pipeline description
8550 @subsection Specifying processor pipeline description
8551 @cindex processor pipeline description
8552 @cindex processor functional units
8553 @cindex instruction latency time
8554 @cindex interlock delays
8555 @cindex data dependence delays
8556 @cindex reservation delays
8557 @cindex pipeline hazard recognizer
8558 @cindex automaton based pipeline description
8559 @cindex regular expressions
8560 @cindex deterministic finite state automaton
8561 @cindex automaton based scheduler
8565 To achieve better performance, most modern processors
8566 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
8567 processors) have many @dfn{functional units} on which several
8568 instructions can be executed simultaneously. An instruction starts
8569 execution if its issue conditions are satisfied. If not, the
8570 instruction is stalled until its conditions are satisfied. Such
8571 @dfn{interlock (pipeline) delay} causes interruption of the fetching
8572 of successor instructions (or demands nop instructions, e.g.@: for some
8575 There are two major kinds of interlock delays in modern processors.
8576 The first one is a data dependence delay determining @dfn{instruction
8577 latency time}. The instruction execution is not started until all
8578 source data have been evaluated by prior instructions (there are more
8579 complex cases when the instruction execution starts even when the data
8580 are not available but will be ready in given time after the
8581 instruction execution start). Taking the data dependence delays into
8582 account is simple. The data dependence (true, output, and
8583 anti-dependence) delay between two instructions is given by a
8584 constant. In most cases this approach is adequate. The second kind
8585 of interlock delays is a reservation delay. The reservation delay
8586 means that two instructions under execution will be in need of shared
8587 processors resources, i.e.@: buses, internal registers, and/or
8588 functional units, which are reserved for some time. Taking this kind
8589 of delay into account is complex especially for modern @acronym{RISC}
8592 The task of exploiting more processor parallelism is solved by an
8593 instruction scheduler. For a better solution to this problem, the
8594 instruction scheduler has to have an adequate description of the
8595 processor parallelism (or @dfn{pipeline description}). GCC
8596 machine descriptions describe processor parallelism and functional
8597 unit reservations for groups of instructions with the aid of
8598 @dfn{regular expressions}.
8600 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
8601 figure out the possibility of the instruction issue by the processor
8602 on a given simulated processor cycle. The pipeline hazard recognizer is
8603 automatically generated from the processor pipeline description. The
8604 pipeline hazard recognizer generated from the machine description
8605 is based on a deterministic finite state automaton (@acronym{DFA}):
8606 the instruction issue is possible if there is a transition from one
8607 automaton state to another one. This algorithm is very fast, and
8608 furthermore, its speed is not dependent on processor
8609 complexity@footnote{However, the size of the automaton depends on
8610 processor complexity. To limit this effect, machine descriptions
8611 can split orthogonal parts of the machine description among several
8612 automata: but then, since each of these must be stepped independently,
8613 this does cause a small decrease in the algorithm's performance.}.
8615 @cindex automaton based pipeline description
8616 The rest of this section describes the directives that constitute
8617 an automaton-based processor pipeline description. The order of
8618 these constructions within the machine description file is not
8621 @findex define_automaton
8622 @cindex pipeline hazard recognizer
8623 The following optional construction describes names of automata
8624 generated and used for the pipeline hazards recognition. Sometimes
8625 the generated finite state automaton used by the pipeline hazard
8626 recognizer is large. If we use more than one automaton and bind functional
8627 units to the automata, the total size of the automata is usually
8628 less than the size of the single automaton. If there is no one such
8629 construction, only one finite state automaton is generated.
8632 (define_automaton @var{automata-names})
8635 @var{automata-names} is a string giving names of the automata. The
8636 names are separated by commas. All the automata should have unique names.
8637 The automaton name is used in the constructions @code{define_cpu_unit} and
8638 @code{define_query_cpu_unit}.
8640 @findex define_cpu_unit
8641 @cindex processor functional units
8642 Each processor functional unit used in the description of instruction
8643 reservations should be described by the following construction.
8646 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
8649 @var{unit-names} is a string giving the names of the functional units
8650 separated by commas. Don't use name @samp{nothing}, it is reserved
8653 @var{automaton-name} is a string giving the name of the automaton with
8654 which the unit is bound. The automaton should be described in
8655 construction @code{define_automaton}. You should give
8656 @dfn{automaton-name}, if there is a defined automaton.
8658 The assignment of units to automata are constrained by the uses of the
8659 units in insn reservations. The most important constraint is: if a
8660 unit reservation is present on a particular cycle of an alternative
8661 for an insn reservation, then some unit from the same automaton must
8662 be present on the same cycle for the other alternatives of the insn
8663 reservation. The rest of the constraints are mentioned in the
8664 description of the subsequent constructions.
8666 @findex define_query_cpu_unit
8667 @cindex querying function unit reservations
8668 The following construction describes CPU functional units analogously
8669 to @code{define_cpu_unit}. The reservation of such units can be
8670 queried for an automaton state. The instruction scheduler never
8671 queries reservation of functional units for given automaton state. So
8672 as a rule, you don't need this construction. This construction could
8673 be used for future code generation goals (e.g.@: to generate
8674 @acronym{VLIW} insn templates).
8677 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
8680 @var{unit-names} is a string giving names of the functional units
8681 separated by commas.
8683 @var{automaton-name} is a string giving the name of the automaton with
8684 which the unit is bound.
8686 @findex define_insn_reservation
8687 @cindex instruction latency time
8688 @cindex regular expressions
8690 The following construction is the major one to describe pipeline
8691 characteristics of an instruction.
8694 (define_insn_reservation @var{insn-name} @var{default_latency}
8695 @var{condition} @var{regexp})
8698 @var{default_latency} is a number giving latency time of the
8699 instruction. There is an important difference between the old
8700 description and the automaton based pipeline description. The latency
8701 time is used for all dependencies when we use the old description. In
8702 the automaton based pipeline description, the given latency time is only
8703 used for true dependencies. The cost of anti-dependencies is always
8704 zero and the cost of output dependencies is the difference between
8705 latency times of the producing and consuming insns (if the difference
8706 is negative, the cost is considered to be zero). You can always
8707 change the default costs for any description by using the target hook
8708 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
8710 @var{insn-name} is a string giving the internal name of the insn. The
8711 internal names are used in constructions @code{define_bypass} and in
8712 the automaton description file generated for debugging. The internal
8713 name has nothing in common with the names in @code{define_insn}. It is a
8714 good practice to use insn classes described in the processor manual.
8716 @var{condition} defines what RTL insns are described by this
8717 construction. You should remember that you will be in trouble if
8718 @var{condition} for two or more different
8719 @code{define_insn_reservation} constructions is TRUE for an insn. In
8720 this case what reservation will be used for the insn is not defined.
8721 Such cases are not checked during generation of the pipeline hazards
8722 recognizer because in general recognizing that two conditions may have
8723 the same value is quite difficult (especially if the conditions
8724 contain @code{symbol_ref}). It is also not checked during the
8725 pipeline hazard recognizer work because it would slow down the
8726 recognizer considerably.
8728 @var{regexp} is a string describing the reservation of the cpu's functional
8729 units by the instruction. The reservations are described by a regular
8730 expression according to the following syntax:
8733 regexp = regexp "," oneof
8736 oneof = oneof "|" allof
8739 allof = allof "+" repeat
8742 repeat = element "*" number
8745 element = cpu_function_unit_name
8754 @samp{,} is used for describing the start of the next cycle in
8758 @samp{|} is used for describing a reservation described by the first
8759 regular expression @strong{or} a reservation described by the second
8760 regular expression @strong{or} etc.
8763 @samp{+} is used for describing a reservation described by the first
8764 regular expression @strong{and} a reservation described by the
8765 second regular expression @strong{and} etc.
8768 @samp{*} is used for convenience and simply means a sequence in which
8769 the regular expression are repeated @var{number} times with cycle
8770 advancing (see @samp{,}).
8773 @samp{cpu_function_unit_name} denotes reservation of the named
8777 @samp{reservation_name} --- see description of construction
8778 @samp{define_reservation}.
8781 @samp{nothing} denotes no unit reservations.
8784 @findex define_reservation
8785 Sometimes unit reservations for different insns contain common parts.
8786 In such case, you can simplify the pipeline description by describing
8787 the common part by the following construction
8790 (define_reservation @var{reservation-name} @var{regexp})
8793 @var{reservation-name} is a string giving name of @var{regexp}.
8794 Functional unit names and reservation names are in the same name
8795 space. So the reservation names should be different from the
8796 functional unit names and can not be the reserved name @samp{nothing}.
8798 @findex define_bypass
8799 @cindex instruction latency time
8801 The following construction is used to describe exceptions in the
8802 latency time for given instruction pair. This is so called bypasses.
8805 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
8809 @var{number} defines when the result generated by the instructions
8810 given in string @var{out_insn_names} will be ready for the
8811 instructions given in string @var{in_insn_names}. Each of these
8812 strings is a comma-separated list of filename-style globs and
8813 they refer to the names of @code{define_insn_reservation}s.
8816 (define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*")
8818 defines a bypass between instructions that start with
8819 @samp{cpu1_load_} or @samp{cpu1_store_} and those that start with
8822 @var{guard} is an optional string giving the name of a C function which
8823 defines an additional guard for the bypass. The function will get the
8824 two insns as parameters. If the function returns zero the bypass will
8825 be ignored for this case. The additional guard is necessary to
8826 recognize complicated bypasses, e.g.@: when the consumer is only an address
8827 of insn @samp{store} (not a stored value).
8829 If there are more one bypass with the same output and input insns, the
8830 chosen bypass is the first bypass with a guard in description whose
8831 guard function returns nonzero. If there is no such bypass, then
8832 bypass without the guard function is chosen.
8834 @findex exclusion_set
8835 @findex presence_set
8836 @findex final_presence_set
8838 @findex final_absence_set
8841 The following five constructions are usually used to describe
8842 @acronym{VLIW} processors, or more precisely, to describe a placement
8843 of small instructions into @acronym{VLIW} instruction slots. They
8844 can be used for @acronym{RISC} processors, too.
8847 (exclusion_set @var{unit-names} @var{unit-names})
8848 (presence_set @var{unit-names} @var{patterns})
8849 (final_presence_set @var{unit-names} @var{patterns})
8850 (absence_set @var{unit-names} @var{patterns})
8851 (final_absence_set @var{unit-names} @var{patterns})
8854 @var{unit-names} is a string giving names of functional units
8855 separated by commas.
8857 @var{patterns} is a string giving patterns of functional units
8858 separated by comma. Currently pattern is one unit or units
8859 separated by white-spaces.
8861 The first construction (@samp{exclusion_set}) means that each
8862 functional unit in the first string can not be reserved simultaneously
8863 with a unit whose name is in the second string and vice versa. For
8864 example, the construction is useful for describing processors
8865 (e.g.@: some SPARC processors) with a fully pipelined floating point
8866 functional unit which can execute simultaneously only single floating
8867 point insns or only double floating point insns.
8869 The second construction (@samp{presence_set}) means that each
8870 functional unit in the first string can not be reserved unless at
8871 least one of pattern of units whose names are in the second string is
8872 reserved. This is an asymmetric relation. For example, it is useful
8873 for description that @acronym{VLIW} @samp{slot1} is reserved after
8874 @samp{slot0} reservation. We could describe it by the following
8878 (presence_set "slot1" "slot0")
8881 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
8882 reservation. In this case we could write
8885 (presence_set "slot1" "slot0 b0")
8888 The third construction (@samp{final_presence_set}) is analogous to
8889 @samp{presence_set}. The difference between them is when checking is
8890 done. When an instruction is issued in given automaton state
8891 reflecting all current and planned unit reservations, the automaton
8892 state is changed. The first state is a source state, the second one
8893 is a result state. Checking for @samp{presence_set} is done on the
8894 source state reservation, checking for @samp{final_presence_set} is
8895 done on the result reservation. This construction is useful to
8896 describe a reservation which is actually two subsequent reservations.
8897 For example, if we use
8900 (presence_set "slot1" "slot0")
8903 the following insn will be never issued (because @samp{slot1} requires
8904 @samp{slot0} which is absent in the source state).
8907 (define_reservation "insn_and_nop" "slot0 + slot1")
8910 but it can be issued if we use analogous @samp{final_presence_set}.
8912 The forth construction (@samp{absence_set}) means that each functional
8913 unit in the first string can be reserved only if each pattern of units
8914 whose names are in the second string is not reserved. This is an
8915 asymmetric relation (actually @samp{exclusion_set} is analogous to
8916 this one but it is symmetric). For example it might be useful in a
8917 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
8918 after either @samp{slot1} or @samp{slot2} have been reserved. This
8919 can be described as:
8922 (absence_set "slot0" "slot1, slot2")
8925 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
8926 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
8927 this case we could write
8930 (absence_set "slot2" "slot0 b0, slot1 b1")
8933 All functional units mentioned in a set should belong to the same
8936 The last construction (@samp{final_absence_set}) is analogous to
8937 @samp{absence_set} but checking is done on the result (state)
8938 reservation. See comments for @samp{final_presence_set}.
8940 @findex automata_option
8941 @cindex deterministic finite state automaton
8942 @cindex nondeterministic finite state automaton
8943 @cindex finite state automaton minimization
8944 You can control the generator of the pipeline hazard recognizer with
8945 the following construction.
8948 (automata_option @var{options})
8951 @var{options} is a string giving options which affect the generated
8952 code. Currently there are the following options:
8956 @dfn{no-minimization} makes no minimization of the automaton. This is
8957 only worth to do when we are debugging the description and need to
8958 look more accurately at reservations of states.
8961 @dfn{time} means printing time statistics about the generation of
8965 @dfn{stats} means printing statistics about the generated automata
8966 such as the number of DFA states, NDFA states and arcs.
8969 @dfn{v} means a generation of the file describing the result automata.
8970 The file has suffix @samp{.dfa} and can be used for the description
8971 verification and debugging.
8974 @dfn{w} means a generation of warning instead of error for
8975 non-critical errors.
8978 @dfn{no-comb-vect} prevents the automaton generator from generating
8979 two data structures and comparing them for space efficiency. Using
8980 a comb vector to represent transitions may be better, but it can be
8981 very expensive to construct. This option is useful if the build
8982 process spends an unacceptably long time in genautomata.
8985 @dfn{ndfa} makes nondeterministic finite state automata. This affects
8986 the treatment of operator @samp{|} in the regular expressions. The
8987 usual treatment of the operator is to try the first alternative and,
8988 if the reservation is not possible, the second alternative. The
8989 nondeterministic treatment means trying all alternatives, some of them
8990 may be rejected by reservations in the subsequent insns.
8993 @dfn{collapse-ndfa} modifies the behaviour of the generator when
8994 producing an automaton. An additional state transition to collapse a
8995 nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA}
8996 state is generated. It can be triggered by passing @code{const0_rtx} to
8997 state_transition. In such an automaton, cycle advance transitions are
8998 available only for these collapsed states. This option is useful for
8999 ports that want to use the @code{ndfa} option, but also want to use
9000 @code{define_query_cpu_unit} to assign units to insns issued in a cycle.
9003 @dfn{progress} means output of a progress bar showing how many states
9004 were generated so far for automaton being processed. This is useful
9005 during debugging a @acronym{DFA} description. If you see too many
9006 generated states, you could interrupt the generator of the pipeline
9007 hazard recognizer and try to figure out a reason for generation of the
9011 As an example, consider a superscalar @acronym{RISC} machine which can
9012 issue three insns (two integer insns and one floating point insn) on
9013 the cycle but can finish only two insns. To describe this, we define
9014 the following functional units.
9017 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
9018 (define_cpu_unit "port0, port1")
9021 All simple integer insns can be executed in any integer pipeline and
9022 their result is ready in two cycles. The simple integer insns are
9023 issued into the first pipeline unless it is reserved, otherwise they
9024 are issued into the second pipeline. Integer division and
9025 multiplication insns can be executed only in the second integer
9026 pipeline and their results are ready correspondingly in 8 and 4
9027 cycles. The integer division is not pipelined, i.e.@: the subsequent
9028 integer division insn can not be issued until the current division
9029 insn finished. Floating point insns are fully pipelined and their
9030 results are ready in 3 cycles. Where the result of a floating point
9031 insn is used by an integer insn, an additional delay of one cycle is
9032 incurred. To describe all of this we could specify
9035 (define_cpu_unit "div")
9037 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
9038 "(i0_pipeline | i1_pipeline), (port0 | port1)")
9040 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
9041 "i1_pipeline, nothing*2, (port0 | port1)")
9043 (define_insn_reservation "div" 8 (eq_attr "type" "div")
9044 "i1_pipeline, div*7, div + (port0 | port1)")
9046 (define_insn_reservation "float" 3 (eq_attr "type" "float")
9047 "f_pipeline, nothing, (port0 | port1))
9049 (define_bypass 4 "float" "simple,mult,div")
9052 To simplify the description we could describe the following reservation
9055 (define_reservation "finish" "port0|port1")
9058 and use it in all @code{define_insn_reservation} as in the following
9062 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
9063 "(i0_pipeline | i1_pipeline), finish")
9069 @node Conditional Execution
9070 @section Conditional Execution
9071 @cindex conditional execution
9074 A number of architectures provide for some form of conditional
9075 execution, or predication. The hallmark of this feature is the
9076 ability to nullify most of the instructions in the instruction set.
9077 When the instruction set is large and not entirely symmetric, it
9078 can be quite tedious to describe these forms directly in the
9079 @file{.md} file. An alternative is the @code{define_cond_exec} template.
9081 @findex define_cond_exec
9084 [@var{predicate-pattern}]
9086 "@var{output-template}"
9087 "@var{optional-insn-attribues}")
9090 @var{predicate-pattern} is the condition that must be true for the
9091 insn to be executed at runtime and should match a relational operator.
9092 One can use @code{match_operator} to match several relational operators
9093 at once. Any @code{match_operand} operands must have no more than one
9096 @var{condition} is a C expression that must be true for the generated
9099 @findex current_insn_predicate
9100 @var{output-template} is a string similar to the @code{define_insn}
9101 output template (@pxref{Output Template}), except that the @samp{*}
9102 and @samp{@@} special cases do not apply. This is only useful if the
9103 assembly text for the predicate is a simple prefix to the main insn.
9104 In order to handle the general case, there is a global variable
9105 @code{current_insn_predicate} that will contain the entire predicate
9106 if the current insn is predicated, and will otherwise be @code{NULL}.
9108 @var{optional-insn-attributes} is an optional vector of attributes that gets
9109 appended to the insn attributes of the produced cond_exec rtx. It can
9110 be used to add some distinguishing attribute to cond_exec rtxs produced
9111 that way. An example usage would be to use this attribute in conjunction
9112 with attributes on the main pattern to disable particular alternatives under
9115 When @code{define_cond_exec} is used, an implicit reference to
9116 the @code{predicable} instruction attribute is made.
9117 @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
9118 exactly two elements in its @var{list-of-values}), with the possible
9119 values being @code{no} and @code{yes}. The default and all uses in
9120 the insns must be a simple constant, not a complex expressions. It
9121 may, however, depend on the alternative, by using a comma-separated
9122 list of values. If that is the case, the port should also define an
9123 @code{enabled} attribute (@pxref{Disable Insn Alternatives}), which
9124 should also allow only @code{no} and @code{yes} as its values.
9126 For each @code{define_insn} for which the @code{predicable}
9127 attribute is true, a new @code{define_insn} pattern will be
9128 generated that matches a predicated version of the instruction.
9132 (define_insn "addsi"
9133 [(set (match_operand:SI 0 "register_operand" "r")
9134 (plus:SI (match_operand:SI 1 "register_operand" "r")
9135 (match_operand:SI 2 "register_operand" "r")))]
9140 [(ne (match_operand:CC 0 "register_operand" "c")
9147 generates a new pattern
9152 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
9153 (set (match_operand:SI 0 "register_operand" "r")
9154 (plus:SI (match_operand:SI 1 "register_operand" "r")
9155 (match_operand:SI 2 "register_operand" "r"))))]
9156 "(@var{test2}) && (@var{test1})"
9157 "(%3) add %2,%1,%0")
9163 @section RTL Templates Transformations
9164 @cindex define_subst
9166 For some hardware architectures there are common cases when the RTL
9167 templates for the instructions can be derived from the other RTL
9168 templates using simple transformations. E.g., @file{i386.md} contains
9169 an RTL template for the ordinary @code{sub} instruction---
9170 @code{*subsi_1}, and for the @code{sub} instruction with subsequent
9171 zero-extension---@code{*subsi_1_zext}. Such cases can be easily
9172 implemented by a single meta-template capable of generating a modified
9173 case based on the initial one:
9175 @findex define_subst
9177 (define_subst "@var{name}"
9178 [@var{input-template}]
9180 [@var{output-template}])
9182 @var{input-template} is a pattern describing the source RTL template,
9183 which will be transformed.
9185 @var{condition} is a C expression that is conjunct with the condition
9186 from the input-template to generate a condition to be used in the
9189 @var{output-template} is a pattern that will be used in the resulting
9192 @code{define_subst} mechanism is tightly coupled with the notion of the
9193 subst attribute (@pxref{Subst Iterators}). The use of
9194 @code{define_subst} is triggered by a reference to a subst attribute in
9195 the transforming RTL template. This reference initiates duplication of
9196 the source RTL template and substitution of the attributes with their
9197 values. The source RTL template is left unchanged, while the copy is
9198 transformed by @code{define_subst}. This transformation can fail in the
9199 case when the source RTL template is not matched against the
9200 input-template of the @code{define_subst}. In such case the copy is
9203 @code{define_subst} can be used only in @code{define_insn} and
9204 @code{define_expand}, it cannot be used in other expressions (e.g. in
9205 @code{define_insn_and_split}).
9208 * Define Subst Example:: Example of @code{define_subst} work.
9209 * Define Subst Pattern Matching:: Process of template comparison.
9210 * Define Subst Output Template:: Generation of output template.
9213 @node Define Subst Example
9214 @subsection @code{define_subst} Example
9215 @cindex define_subst
9217 To illustrate how @code{define_subst} works, let us examine a simple
9218 template transformation.
9220 Suppose there are two kinds of instructions: one that touches flags and
9221 the other that does not. The instructions of the second type could be
9222 generated with the following @code{define_subst}:
9225 (define_subst "add_clobber_subst"
9226 [(set (match_operand:SI 0 "" "")
9227 (match_operand:SI 1 "" ""))]
9231 (clobber (reg:CC FLAGS_REG))]
9234 This @code{define_subst} can be applied to any RTL pattern containing
9235 @code{set} of mode SI and generates a copy with clobber when it is
9238 Assume there is an RTL template for a @code{max} instruction to be used
9239 in @code{define_subst} mentioned above:
9242 (define_insn "maxsi"
9243 [(set (match_operand:SI 0 "register_operand" "=r")
9245 (match_operand:SI 1 "register_operand" "r")
9246 (match_operand:SI 2 "register_operand" "r")))]
9248 "max\t@{%2, %1, %0|%0, %1, %2@}"
9252 To mark the RTL template for @code{define_subst} application,
9253 subst-attributes are used. They should be declared in advance:
9256 (define_subst_attr "add_clobber_name" "add_clobber_subst" "_noclobber" "_clobber")
9259 Here @samp{add_clobber_name} is the attribute name,
9260 @samp{add_clobber_subst} is the name of the corresponding
9261 @code{define_subst}, the third argument (@samp{_noclobber}) is the
9262 attribute value that would be substituted into the unchanged version of
9263 the source RTL template, and the last argument (@samp{_clobber}) is the
9264 value that would be substituted into the second, transformed,
9265 version of the RTL template.
9267 Once the subst-attribute has been defined, it should be used in RTL
9268 templates which need to be processed by the @code{define_subst}. So,
9269 the original RTL template should be changed:
9272 (define_insn "maxsi<add_clobber_name>"
9273 [(set (match_operand:SI 0 "register_operand" "=r")
9275 (match_operand:SI 1 "register_operand" "r")
9276 (match_operand:SI 2 "register_operand" "r")))]
9278 "max\t@{%2, %1, %0|%0, %1, %2@}"
9282 The result of the @code{define_subst} usage would look like the following:
9285 (define_insn "maxsi_noclobber"
9286 [(set (match_operand:SI 0 "register_operand" "=r")
9288 (match_operand:SI 1 "register_operand" "r")
9289 (match_operand:SI 2 "register_operand" "r")))]
9291 "max\t@{%2, %1, %0|%0, %1, %2@}"
9293 (define_insn "maxsi_clobber"
9294 [(set (match_operand:SI 0 "register_operand" "=r")
9296 (match_operand:SI 1 "register_operand" "r")
9297 (match_operand:SI 2 "register_operand" "r")))
9298 (clobber (reg:CC FLAGS_REG))]
9300 "max\t@{%2, %1, %0|%0, %1, %2@}"
9304 @node Define Subst Pattern Matching
9305 @subsection Pattern Matching in @code{define_subst}
9306 @cindex define_subst
9308 All expressions, allowed in @code{define_insn} or @code{define_expand},
9309 are allowed in the input-template of @code{define_subst}, except
9310 @code{match_par_dup}, @code{match_scratch}, @code{match_parallel}. The
9311 meanings of expressions in the input-template were changed:
9313 @code{match_operand} matches any expression (possibly, a subtree in
9314 RTL-template), if modes of the @code{match_operand} and this expression
9315 are the same, or mode of the @code{match_operand} is @code{VOIDmode}, or
9316 this expression is @code{match_dup}, @code{match_op_dup}. If the
9317 expression is @code{match_operand} too, and predicate of
9318 @code{match_operand} from the input pattern is not empty, then the
9319 predicates are compared. That can be used for more accurate filtering
9320 of accepted RTL-templates.
9322 @code{match_operator} matches common operators (like @code{plus},
9323 @code{minus}), @code{unspec}, @code{unspec_volatile} operators and
9324 @code{match_operator}s from the original pattern if the modes match and
9325 @code{match_operator} from the input pattern has the same number of
9326 operands as the operator from the original pattern.
9328 @node Define Subst Output Template
9329 @subsection Generation of output template in @code{define_subst}
9330 @cindex define_subst
9332 If all necessary checks for @code{define_subst} application pass, a new
9333 RTL-pattern, based on the output-template, is created to replace the old
9334 template. Like in input-patterns, meanings of some RTL expressions are
9335 changed when they are used in output-patterns of a @code{define_subst}.
9336 Thus, @code{match_dup} is used for copying the whole expression from the
9337 original pattern, which matched corresponding @code{match_operand} from
9340 @code{match_dup N} is used in the output template to be replaced with
9341 the expression from the original pattern, which matched
9342 @code{match_operand N} from the input pattern. As a consequence,
9343 @code{match_dup} cannot be used to point to @code{match_operand}s from
9344 the output pattern, it should always refer to a @code{match_operand}
9345 from the input pattern.
9347 In the output template one can refer to the expressions from the
9348 original pattern and create new ones. For instance, some operands could
9349 be added by means of standard @code{match_operand}.
9351 After replacing @code{match_dup} with some RTL-subtree from the original
9352 pattern, it could happen that several @code{match_operand}s in the
9353 output pattern have the same indexes. It is unknown, how many and what
9354 indexes would be used in the expression which would replace
9355 @code{match_dup}, so such conflicts in indexes are inevitable. To
9356 overcome this issue, @code{match_operands} and @code{match_operators},
9357 which were introduced into the output pattern, are renumerated when all
9358 @code{match_dup}s are replaced.
9360 Number of alternatives in @code{match_operand}s introduced into the
9361 output template @code{M} could differ from the number of alternatives in
9362 the original pattern @code{N}, so in the resultant pattern there would
9363 be @code{N*M} alternatives. Thus, constraints from the original pattern
9364 would be duplicated @code{N} times, constraints from the output pattern
9365 would be duplicated @code{M} times, producing all possible combinations.
9369 @node Constant Definitions
9370 @section Constant Definitions
9371 @cindex constant definitions
9372 @findex define_constants
9374 Using literal constants inside instruction patterns reduces legibility and
9375 can be a maintenance problem.
9377 To overcome this problem, you may use the @code{define_constants}
9378 expression. It contains a vector of name-value pairs. From that
9379 point on, wherever any of the names appears in the MD file, it is as
9380 if the corresponding value had been written instead. You may use
9381 @code{define_constants} multiple times; each appearance adds more
9382 constants to the table. It is an error to redefine a constant with
9385 To come back to the a29k load multiple example, instead of
9389 [(match_parallel 0 "load_multiple_operation"
9390 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
9391 (match_operand:SI 2 "memory_operand" "m"))
9393 (clobber (reg:SI 179))])]
9409 [(match_parallel 0 "load_multiple_operation"
9410 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
9411 (match_operand:SI 2 "memory_operand" "m"))
9413 (clobber (reg:SI R_CR))])]
9418 The constants that are defined with a define_constant are also output
9419 in the insn-codes.h header file as #defines.
9421 @cindex enumerations
9422 @findex define_c_enum
9423 You can also use the machine description file to define enumerations.
9424 Like the constants defined by @code{define_constant}, these enumerations
9425 are visible to both the machine description file and the main C code.
9427 The syntax is as follows:
9430 (define_c_enum "@var{name}" [
9438 This definition causes the equivalent of the following C code to appear
9439 in @file{insn-constants.h}:
9446 @var{valuen} = @var{n}
9448 #define NUM_@var{cname}_VALUES (@var{n} + 1)
9451 where @var{cname} is the capitalized form of @var{name}.
9452 It also makes each @var{valuei} available in the machine description
9453 file, just as if it had been declared with:
9456 (define_constants [(@var{valuei} @var{i})])
9459 Each @var{valuei} is usually an upper-case identifier and usually
9460 begins with @var{cname}.
9462 You can split the enumeration definition into as many statements as
9463 you like. The above example is directly equivalent to:
9466 (define_c_enum "@var{name}" [@var{value0}])
9467 (define_c_enum "@var{name}" [@var{value1}])
9469 (define_c_enum "@var{name}" [@var{valuen}])
9472 Splitting the enumeration helps to improve the modularity of each
9473 individual @code{.md} file. For example, if a port defines its
9474 synchronization instructions in a separate @file{sync.md} file,
9475 it is convenient to define all synchronization-specific enumeration
9476 values in @file{sync.md} rather than in the main @file{.md} file.
9478 Some enumeration names have special significance to GCC:
9482 @findex unspec_volatile
9483 If an enumeration called @code{unspecv} is defined, GCC will use it
9484 when printing out @code{unspec_volatile} expressions. For example:
9487 (define_c_enum "unspecv" [
9492 causes GCC to print @samp{(unspec_volatile @dots{} 0)} as:
9495 (unspec_volatile ... UNSPECV_BLOCKAGE)
9500 If an enumeration called @code{unspec} is defined, GCC will use
9501 it when printing out @code{unspec} expressions. GCC will also use
9502 it when printing out @code{unspec_volatile} expressions unless an
9503 @code{unspecv} enumeration is also defined. You can therefore
9504 decide whether to keep separate enumerations for volatile and
9505 non-volatile expressions or whether to use the same enumeration
9510 @anchor{define_enum}
9511 Another way of defining an enumeration is to use @code{define_enum}:
9514 (define_enum "@var{name}" [
9522 This directive implies:
9525 (define_c_enum "@var{name}" [
9526 @var{cname}_@var{cvalue0}
9527 @var{cname}_@var{cvalue1}
9529 @var{cname}_@var{cvaluen}
9533 @findex define_enum_attr
9534 where @var{cvaluei} is the capitalized form of @var{valuei}.
9535 However, unlike @code{define_c_enum}, the enumerations defined
9536 by @code{define_enum} can be used in attribute specifications
9537 (@pxref{define_enum_attr}).
9542 @cindex iterators in @file{.md} files
9544 Ports often need to define similar patterns for more than one machine
9545 mode or for more than one rtx code. GCC provides some simple iterator
9546 facilities to make this process easier.
9549 * Mode Iterators:: Generating variations of patterns for different modes.
9550 * Code Iterators:: Doing the same for codes.
9551 * Int Iterators:: Doing the same for integers.
9552 * Subst Iterators:: Generating variations of patterns for define_subst.
9555 @node Mode Iterators
9556 @subsection Mode Iterators
9557 @cindex mode iterators in @file{.md} files
9559 Ports often need to define similar patterns for two or more different modes.
9564 If a processor has hardware support for both single and double
9565 floating-point arithmetic, the @code{SFmode} patterns tend to be
9566 very similar to the @code{DFmode} ones.
9569 If a port uses @code{SImode} pointers in one configuration and
9570 @code{DImode} pointers in another, it will usually have very similar
9571 @code{SImode} and @code{DImode} patterns for manipulating pointers.
9574 Mode iterators allow several patterns to be instantiated from one
9575 @file{.md} file template. They can be used with any type of
9576 rtx-based construct, such as a @code{define_insn},
9577 @code{define_split}, or @code{define_peephole2}.
9580 * Defining Mode Iterators:: Defining a new mode iterator.
9581 * Substitutions:: Combining mode iterators with substitutions
9582 * Examples:: Examples
9585 @node Defining Mode Iterators
9586 @subsubsection Defining Mode Iterators
9587 @findex define_mode_iterator
9589 The syntax for defining a mode iterator is:
9592 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
9595 This allows subsequent @file{.md} file constructs to use the mode suffix
9596 @code{:@var{name}}. Every construct that does so will be expanded
9597 @var{n} times, once with every use of @code{:@var{name}} replaced by
9598 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
9599 and so on. In the expansion for a particular @var{modei}, every
9600 C condition will also require that @var{condi} be true.
9605 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
9608 defines a new mode suffix @code{:P}. Every construct that uses
9609 @code{:P} will be expanded twice, once with every @code{:P} replaced
9610 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
9611 The @code{:SI} version will only apply if @code{Pmode == SImode} and
9612 the @code{:DI} version will only apply if @code{Pmode == DImode}.
9614 As with other @file{.md} conditions, an empty string is treated
9615 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
9616 to @code{@var{mode}}. For example:
9619 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
9622 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
9623 but that the @code{:SI} expansion has no such constraint.
9625 Iterators are applied in the order they are defined. This can be
9626 significant if two iterators are used in a construct that requires
9627 substitutions. @xref{Substitutions}.
9630 @subsubsection Substitution in Mode Iterators
9631 @findex define_mode_attr
9633 If an @file{.md} file construct uses mode iterators, each version of the
9634 construct will often need slightly different strings or modes. For
9639 When a @code{define_expand} defines several @code{add@var{m}3} patterns
9640 (@pxref{Standard Names}), each expander will need to use the
9641 appropriate mode name for @var{m}.
9644 When a @code{define_insn} defines several instruction patterns,
9645 each instruction will often use a different assembler mnemonic.
9648 When a @code{define_insn} requires operands with different modes,
9649 using an iterator for one of the operand modes usually requires a specific
9650 mode for the other operand(s).
9653 GCC supports such variations through a system of ``mode attributes''.
9654 There are two standard attributes: @code{mode}, which is the name of
9655 the mode in lower case, and @code{MODE}, which is the same thing in
9656 upper case. You can define other attributes using:
9659 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
9662 where @var{name} is the name of the attribute and @var{valuei}
9663 is the value associated with @var{modei}.
9665 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
9666 each string and mode in the pattern for sequences of the form
9667 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
9668 mode attribute. If the attribute is defined for @var{mode}, the whole
9669 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
9672 For example, suppose an @file{.md} file has:
9675 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
9676 (define_mode_attr load [(SI "lw") (DI "ld")])
9679 If one of the patterns that uses @code{:P} contains the string
9680 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
9681 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
9684 Here is an example of using an attribute for a mode:
9687 (define_mode_iterator LONG [SI DI])
9688 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
9689 (define_insn @dots{}
9690 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
9693 The @code{@var{iterator}:} prefix may be omitted, in which case the
9694 substitution will be attempted for every iterator expansion.
9697 @subsubsection Mode Iterator Examples
9699 Here is an example from the MIPS port. It defines the following
9700 modes and attributes (among others):
9703 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
9704 (define_mode_attr d [(SI "") (DI "d")])
9707 and uses the following template to define both @code{subsi3}
9711 (define_insn "sub<mode>3"
9712 [(set (match_operand:GPR 0 "register_operand" "=d")
9713 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
9714 (match_operand:GPR 2 "register_operand" "d")))]
9717 [(set_attr "type" "arith")
9718 (set_attr "mode" "<MODE>")])
9721 This is exactly equivalent to:
9724 (define_insn "subsi3"
9725 [(set (match_operand:SI 0 "register_operand" "=d")
9726 (minus:SI (match_operand:SI 1 "register_operand" "d")
9727 (match_operand:SI 2 "register_operand" "d")))]
9730 [(set_attr "type" "arith")
9731 (set_attr "mode" "SI")])
9733 (define_insn "subdi3"
9734 [(set (match_operand:DI 0 "register_operand" "=d")
9735 (minus:DI (match_operand:DI 1 "register_operand" "d")
9736 (match_operand:DI 2 "register_operand" "d")))]
9739 [(set_attr "type" "arith")
9740 (set_attr "mode" "DI")])
9743 @node Code Iterators
9744 @subsection Code Iterators
9745 @cindex code iterators in @file{.md} files
9746 @findex define_code_iterator
9747 @findex define_code_attr
9749 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
9754 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
9757 defines a pseudo rtx code @var{name} that can be instantiated as
9758 @var{codei} if condition @var{condi} is true. Each @var{codei}
9759 must have the same rtx format. @xref{RTL Classes}.
9761 As with mode iterators, each pattern that uses @var{name} will be
9762 expanded @var{n} times, once with all uses of @var{name} replaced by
9763 @var{code1}, once with all uses replaced by @var{code2}, and so on.
9764 @xref{Defining Mode Iterators}.
9766 It is possible to define attributes for codes as well as for modes.
9767 There are two standard code attributes: @code{code}, the name of the
9768 code in lower case, and @code{CODE}, the name of the code in upper case.
9769 Other attributes are defined using:
9772 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
9775 Here's an example of code iterators in action, taken from the MIPS port:
9778 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
9779 eq ne gt ge lt le gtu geu ltu leu])
9781 (define_expand "b<code>"
9783 (if_then_else (any_cond:CC (cc0)
9785 (label_ref (match_operand 0 ""))
9789 gen_conditional_branch (operands, <CODE>);
9794 This is equivalent to:
9797 (define_expand "bunordered"
9799 (if_then_else (unordered:CC (cc0)
9801 (label_ref (match_operand 0 ""))
9805 gen_conditional_branch (operands, UNORDERED);
9809 (define_expand "bordered"
9811 (if_then_else (ordered:CC (cc0)
9813 (label_ref (match_operand 0 ""))
9817 gen_conditional_branch (operands, ORDERED);
9825 @subsection Int Iterators
9826 @cindex int iterators in @file{.md} files
9827 @findex define_int_iterator
9828 @findex define_int_attr
9830 Int iterators operate in a similar way to code iterators. @xref{Code Iterators}.
9835 (define_int_iterator @var{name} [(@var{int1} "@var{cond1}") @dots{} (@var{intn} "@var{condn}")])
9838 defines a pseudo integer constant @var{name} that can be instantiated as
9839 @var{inti} if condition @var{condi} is true. Each @var{int}
9840 must have the same rtx format. @xref{RTL Classes}. Int iterators can appear
9841 in only those rtx fields that have 'i' as the specifier. This means that
9842 each @var{int} has to be a constant defined using define_constant or
9845 As with mode and code iterators, each pattern that uses @var{name} will be
9846 expanded @var{n} times, once with all uses of @var{name} replaced by
9847 @var{int1}, once with all uses replaced by @var{int2}, and so on.
9848 @xref{Defining Mode Iterators}.
9850 It is possible to define attributes for ints as well as for codes and modes.
9851 Attributes are defined using:
9854 (define_int_attr @var{name} [(@var{int1} "@var{value1}") @dots{} (@var{intn} "@var{valuen}")])
9857 Here's an example of int iterators in action, taken from the ARM port:
9860 (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG])
9862 (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")])
9864 (define_insn "neon_vq<absneg><mode>"
9865 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
9866 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
9867 (match_operand:SI 2 "immediate_operand" "i")]
9870 "vq<absneg>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
9871 [(set_attr "type" "neon_vqneg_vqabs")]
9876 This is equivalent to:
9879 (define_insn "neon_vqabs<mode>"
9880 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
9881 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
9882 (match_operand:SI 2 "immediate_operand" "i")]
9885 "vqabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
9886 [(set_attr "type" "neon_vqneg_vqabs")]
9889 (define_insn "neon_vqneg<mode>"
9890 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
9891 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
9892 (match_operand:SI 2 "immediate_operand" "i")]
9895 "vqneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
9896 [(set_attr "type" "neon_vqneg_vqabs")]
9901 @node Subst Iterators
9902 @subsection Subst Iterators
9903 @cindex subst iterators in @file{.md} files
9904 @findex define_subst
9905 @findex define_subst_attr
9907 Subst iterators are special type of iterators with the following
9908 restrictions: they could not be declared explicitly, they always have
9909 only two values, and they do not have explicit dedicated name.
9910 Subst-iterators are triggered only when corresponding subst-attribute is
9911 used in RTL-pattern.
9913 Subst iterators transform templates in the following way: the templates
9914 are duplicated, the subst-attributes in these templates are replaced
9915 with the corresponding values, and a new attribute is implicitly added
9916 to the given @code{define_insn}/@code{define_expand}. The name of the
9917 added attribute matches the name of @code{define_subst}. Such
9918 attributes are declared implicitly, and it is not allowed to have a
9919 @code{define_attr} named as a @code{define_subst}.
9921 Each subst iterator is linked to a @code{define_subst}. It is declared
9922 implicitly by the first appearance of the corresponding
9923 @code{define_subst_attr}, and it is not allowed to define it explicitly.
9925 Declarations of subst-attributes have the following syntax:
9927 @findex define_subst_attr
9929 (define_subst_attr "@var{name}"
9931 "@var{no-subst-value}"
9932 "@var{subst-applied-value}")
9935 @var{name} is a string with which the given subst-attribute could be
9938 @var{subst-name} shows which @code{define_subst} should be applied to an
9939 RTL-template if the given subst-attribute is present in the
9942 @var{no-subst-value} is a value with which subst-attribute would be
9943 replaced in the first copy of the original RTL-template.
9945 @var{subst-applied-value} is a value with which subst-attribute would be
9946 replaced in the second copy of the original RTL-template.