| blob | 38b41a93c22c231dcd6071c4b3fe90ceaea96712 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
89 #ifndef CHECK_STACK_LIMIT
90 #define CHECK_STACK_LIMIT (-1)
91 #endif
93 /* Return index of given mode in mult and division cost tables. */
94 #define MODE_INDEX(mode) \
95 ((mode) == QImode ? 0 \
96 : (mode) == HImode ? 1 \
97 : (mode) == SImode ? 2 \
98 : (mode) == DImode ? 3 \
99 : 4)
101 /* Processor costs (relative to an add) */
102 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
103 #define COSTS_N_BYTES(N) ((N) * 2)
105 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
114 const
137 in QImode, HImode and SImode.
138 Relative to reg-reg move (2). */
142 in SFmode, DFmode and XFmode */
144 in SFmode, DFmode and XFmode */
147 in SImode and DImode */
149 in SImode and DImode */
152 in SImode, DImode and TImode */
154 in SImode, DImode and TImode */
167 ix86_size_memcpy,
168 ix86_size_memset,
180 };
182 /* Processor costs (relative to an add) */
185 DUMMY_STRINGOP_ALGS};
188 DUMMY_STRINGOP_ALGS};
190 static const
213 in QImode, HImode and SImode.
214 Relative to reg-reg move (2). */
218 in SFmode, DFmode and XFmode */
220 in SFmode, DFmode and XFmode */
223 in SImode and DImode */
225 in SImode and DImode */
228 in SImode, DImode and TImode */
230 in SImode, DImode and TImode */
243 i386_memcpy,
244 i386_memset,
256 };
260 DUMMY_STRINGOP_ALGS};
263 DUMMY_STRINGOP_ALGS};
265 static const
288 in QImode, HImode and SImode.
289 Relative to reg-reg move (2). */
293 in SFmode, DFmode and XFmode */
295 in SFmode, DFmode and XFmode */
298 in SImode and DImode */
300 in SImode and DImode */
303 in SImode, DImode and TImode */
305 in SImode, DImode and TImode */
308 shared for code and data, so 4kB is
309 not really precise. */
320 i486_memcpy,
321 i486_memset,
333 };
337 DUMMY_STRINGOP_ALGS};
340 DUMMY_STRINGOP_ALGS};
342 static const
365 in QImode, HImode and SImode.
366 Relative to reg-reg move (2). */
370 in SFmode, DFmode and XFmode */
372 in SFmode, DFmode and XFmode */
375 in SImode and DImode */
377 in SImode and DImode */
380 in SImode, DImode and TImode */
382 in SImode, DImode and TImode */
395 pentium_memcpy,
396 pentium_memset,
408 };
410 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
411 (we ensure the alignment). For small blocks inline loop is still a
412 noticeable win, for bigger blocks either rep movsl or rep movsb is
413 way to go. Rep movsb has apparently more expensive startup time in CPU,
414 but after 4K the difference is down in the noise. */
419 DUMMY_STRINGOP_ALGS};
424 DUMMY_STRINGOP_ALGS};
425 static const
448 in QImode, HImode and SImode.
449 Relative to reg-reg move (2). */
453 in SFmode, DFmode and XFmode */
455 in SFmode, DFmode and XFmode */
458 in SImode and DImode */
460 in SImode and DImode */
463 in SImode, DImode and TImode */
465 in SImode, DImode and TImode */
478 pentiumpro_memcpy,
479 pentiumpro_memset,
491 };
495 DUMMY_STRINGOP_ALGS};
498 DUMMY_STRINGOP_ALGS};
499 static const
522 in QImode, HImode and SImode.
523 Relative to reg-reg move (2). */
527 in SFmode, DFmode and XFmode */
529 in SFmode, DFmode and XFmode */
533 in SImode and DImode */
535 in SImode and DImode */
538 in SImode, DImode and TImode */
540 in SImode, DImode and TImode */
553 geode_memcpy,
554 geode_memset,
566 };
570 DUMMY_STRINGOP_ALGS};
573 DUMMY_STRINGOP_ALGS};
574 static const
597 in QImode, HImode and SImode.
598 Relative to reg-reg move (2). */
602 in SFmode, DFmode and XFmode */
604 in SFmode, DFmode and XFmode */
607 in SImode and DImode */
609 in SImode and DImode */
612 in SImode, DImode and TImode */
614 in SImode, DImode and TImode */
618 have integrated l2 cache, but
619 optimizing for k6 is not important
620 enough to worry about that. */
630 k6_memcpy,
631 k6_memset,
643 };
645 /* For some reason, Athlon deals better with REP prefix (relative to loops)
646 compared to K8. Alignment becomes important after 8 bytes for memcpy and
647 128 bytes for memset. */
650 DUMMY_STRINGOP_ALGS};
653 DUMMY_STRINGOP_ALGS};
654 static const
677 in QImode, HImode and SImode.
678 Relative to reg-reg move (2). */
682 in SFmode, DFmode and XFmode */
684 in SFmode, DFmode and XFmode */
687 in SImode and DImode */
689 in SImode and DImode */
692 in SImode, DImode and TImode */
694 in SImode, DImode and TImode */
707 athlon_memcpy,
708 athlon_memset,
720 };
722 /* K8 has optimized REP instruction for medium sized blocks, but for very
723 small blocks it is better to use loop. For large blocks, libcall can
724 do nontemporary accesses and beat inline considerably. */
735 static const
758 in QImode, HImode and SImode.
759 Relative to reg-reg move (2). */
763 in SFmode, DFmode and XFmode */
765 in SFmode, DFmode and XFmode */
768 in SImode and DImode */
770 in SImode and DImode */
773 in SImode, DImode and TImode */
775 in SImode, DImode and TImode */
780 /* New AMD processors never drop prefetches; if they cannot be performed
781 immediately, they are queued. We set number of simultaneous prefetches
782 to a large constant to reflect this (it probably is not a good idea not
783 to limit number of prefetches at all, as their execution also takes some
784 time). */
794 k8_memcpy,
795 k8_memset,
807 };
809 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
810 very small blocks it is better to use loop. For large blocks, libcall can
811 do nontemporary accesses and beat inline considerably. */
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
849 in SFmode, DFmode and XFmode */
851 in SFmode, DFmode and XFmode */
854 in SImode and DImode */
856 in SImode and DImode */
859 in SImode, DImode and TImode */
861 in SImode, DImode and TImode */
863 /* On K8:
864 MOVD reg64, xmmreg Double FSTORE 4
865 MOVD reg32, xmmreg Double FSTORE 4
866 On AMDFAM10:
867 MOVD reg64, xmmreg Double FADD 3
868 1/1 1/1
869 MOVD reg32, xmmreg Double FADD 3
870 1/1 1/1 */
874 /* New AMD processors never drop prefetches; if they cannot be performed
875 immediately, they are queued. We set number of simultaneous prefetches
876 to a large constant to reflect this (it probably is not a good idea not
877 to limit number of prefetches at all, as their execution also takes some
878 time). */
888 amdfam10_memcpy,
889 amdfam10_memset,
901 };
903 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
904 very small blocks it is better to use loop. For large blocks, libcall
905 can do nontemporary accesses and beat inline considerably. */
939 in QImode, HImode and SImode.
940 Relative to reg-reg move (2). */
944 in SFmode, DFmode and XFmode */
946 in SFmode, DFmode and XFmode */
949 in SImode and DImode */
951 in SImode and DImode */
954 in SImode, DImode and TImode */
956 in SImode, DImode and TImode */
958 /* On K8:
959 MOVD reg64, xmmreg Double FSTORE 4
960 MOVD reg32, xmmreg Double FSTORE 4
961 On AMDFAM10:
962 MOVD reg64, xmmreg Double FADD 3
963 1/1 1/1
964 MOVD reg32, xmmreg Double FADD 3
965 1/1 1/1 */
969 /* New AMD processors never drop prefetches; if they cannot be performed
970 immediately, they are queued. We set number of simultaneous prefetches
971 to a large constant to reflect this (it probably is not a good idea not
972 to limit number of prefetches at all, as their execution also takes some
973 time). */
983 bdver1_memcpy,
984 bdver1_memset,
996 };
998 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
999 very small blocks it is better to use loop. For large blocks, libcall
1000 can do nontemporary accesses and beat inline considerably. */
1035 in QImode, HImode and SImode.
1036 Relative to reg-reg move (2). */
1040 in SFmode, DFmode and XFmode */
1042 in SFmode, DFmode and XFmode */
1045 in SImode and DImode */
1047 in SImode and DImode */
1050 in SImode, DImode and TImode */
1052 in SImode, DImode and TImode */
1054 /* On K8:
1055 MOVD reg64, xmmreg Double FSTORE 4
1056 MOVD reg32, xmmreg Double FSTORE 4
1057 On AMDFAM10:
1058 MOVD reg64, xmmreg Double FADD 3
1059 1/1 1/1
1060 MOVD reg32, xmmreg Double FADD 3
1061 1/1 1/1 */
1065 /* New AMD processors never drop prefetches; if they cannot be performed
1066 immediately, they are queued. We set number of simultaneous prefetches
1067 to a large constant to reflect this (it probably is not a good idea not
1068 to limit number of prefetches at all, as their execution also takes some
1069 time). */
1079 bdver2_memcpy,
1080 bdver2_memset,
1092 };
1095 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1096 very small blocks it is better to use loop. For large blocks, libcall
1097 can do nontemporary accesses and beat inline considerably. */
1130 in QImode, HImode and SImode.
1131 Relative to reg-reg move (2). */
1135 in SFmode, DFmode and XFmode */
1137 in SFmode, DFmode and XFmode */
1140 in SImode and DImode */
1142 in SImode and DImode */
1145 in SImode, DImode and TImode */
1147 in SImode, DImode and TImode */
1152 /* New AMD processors never drop prefetches; if they cannot be performed
1153 immediately, they are queued. We set number of simultaneous prefetches
1154 to a large constant to reflect this (it probably is not a good idea not
1155 to limit number of prefetches at all, as their execution also takes some
1156 time). */
1166 bdver3_memcpy,
1167 bdver3_memset,
1179 };
1181 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1182 very small blocks it is better to use loop. For large blocks, libcall
1183 can do nontemporary accesses and beat inline considerably. */
1216 in QImode, HImode and SImode.
1217 Relative to reg-reg move (2). */
1221 in SFmode, DFmode and XFmode */
1223 in SFmode, DFmode and XFmode */
1226 in SImode and DImode */
1228 in SImode and DImode */
1231 in SImode, DImode and TImode */
1233 in SImode, DImode and TImode */
1238 /* New AMD processors never drop prefetches; if they cannot be performed
1239 immediately, they are queued. We set number of simultaneous prefetches
1240 to a large constant to reflect this (it probably is not a good idea not
1241 to limit number of prefetches at all, as their execution also takes some
1242 time). */
1252 bdver4_memcpy,
1253 bdver4_memset,
1265 };
1267 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1268 very small blocks it is better to use loop. For large blocks, libcall can
1269 do nontemporary accesses and beat inline considerably. */
1302 in QImode, HImode and SImode.
1303 Relative to reg-reg move (2). */
1307 in SFmode, DFmode and XFmode */
1309 in SFmode, DFmode and XFmode */
1312 in SImode and DImode */
1314 in SImode and DImode */
1317 in SImode, DImode and TImode */
1319 in SImode, DImode and TImode */
1321 /* On K8:
1322 MOVD reg64, xmmreg Double FSTORE 4
1323 MOVD reg32, xmmreg Double FSTORE 4
1324 On AMDFAM10:
1325 MOVD reg64, xmmreg Double FADD 3
1326 1/1 1/1
1327 MOVD reg32, xmmreg Double FADD 3
1328 1/1 1/1 */
1341 btver1_memcpy,
1342 btver1_memset,
1354 };
1388 in QImode, HImode and SImode.
1389 Relative to reg-reg move (2). */
1393 in SFmode, DFmode and XFmode */
1395 in SFmode, DFmode and XFmode */
1398 in SImode and DImode */
1400 in SImode and DImode */
1403 in SImode, DImode and TImode */
1405 in SImode, DImode and TImode */
1407 /* On K8:
1408 MOVD reg64, xmmreg Double FSTORE 4
1409 MOVD reg32, xmmreg Double FSTORE 4
1410 On AMDFAM10:
1411 MOVD reg64, xmmreg Double FADD 3
1412 1/1 1/1
1413 MOVD reg32, xmmreg Double FADD 3
1414 1/1 1/1 */
1426 btver2_memcpy,
1427 btver2_memset,
1439 };
1443 DUMMY_STRINGOP_ALGS};
1447 DUMMY_STRINGOP_ALGS};
1449 static const
1472 in QImode, HImode and SImode.
1473 Relative to reg-reg move (2). */
1477 in SFmode, DFmode and XFmode */
1479 in SFmode, DFmode and XFmode */
1482 in SImode and DImode */
1484 in SImode and DImode */
1487 in SImode, DImode and TImode */
1489 in SImode, DImode and TImode */
1502 pentium4_memcpy,
1503 pentium4_memset,
1515 };
1528 static const
1551 in QImode, HImode and SImode.
1552 Relative to reg-reg move (2). */
1556 in SFmode, DFmode and XFmode */
1558 in SFmode, DFmode and XFmode */
1561 in SImode and DImode */
1563 in SImode and DImode */
1566 in SImode, DImode and TImode */
1568 in SImode, DImode and TImode */
1581 nocona_memcpy,
1582 nocona_memset,
1594 };
1605 static const
1628 in QImode, HImode and SImode.
1629 Relative to reg-reg move (2). */
1633 in SFmode, DFmode and XFmode */
1635 in SFmode, DFmode and XFmode */
1638 in SImode and DImode */
1640 in SImode and DImode */
1643 in SImode, DImode and TImode */
1645 in SImode, DImode and TImode */
1658 atom_memcpy,
1659 atom_memset,
1671 };
1682 static const
1705 in QImode, HImode and SImode.
1706 Relative to reg-reg move (2). */
1710 in SFmode, DFmode and XFmode */
1712 in SFmode, DFmode and XFmode */
1715 in SImode and DImode */
1717 in SImode and DImode */
1720 in SImode, DImode and TImode */
1722 in SImode, DImode and TImode */
1735 slm_memcpy,
1736 slm_memset,
1748 };
1759 static const
1782 in QImode, HImode and SImode.
1783 Relative to reg-reg move (2). */
1787 in SFmode, DFmode and XFmode */
1789 in SFmode, DFmode and XFmode */
1792 in SImode and DImode */
1794 in SImode and DImode */
1797 in SImode, DImode and TImode */
1799 in SImode, DImode and TImode */
1812 intel_memcpy,
1813 intel_memset,
1825 };
1827 /* Generic should produce code tuned for Core-i7 (and newer chips)
1828 and btver1 (and newer chips). */
1840 static const
1843 /* On all chips taken into consideration lea is 2 cycles and more. With
1844 this cost however our current implementation of synth_mult results in
1845 use of unnecessary temporary registers causing regression on several
1846 SPECfp benchmarks. */
1867 in QImode, HImode and SImode.
1868 Relative to reg-reg move (2). */
1872 in SFmode, DFmode and XFmode */
1874 in SFmode, DFmode and XFmode */
1877 in SImode and DImode */
1879 in SImode and DImode */
1882 in SImode, DImode and TImode */
1884 in SImode, DImode and TImode */
1890 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1891 value is increased to perhaps more appropriate value of 5. */
1899 generic_memcpy,
1900 generic_memset,
1912 };
1914 /* core_cost should produce code tuned for Core familly of CPUs. */
1927 static const
1930 /* On all chips taken into consideration lea is 2 cycles and more. With
1931 this cost however our current implementation of synth_mult results in
1932 use of unnecessary temporary registers causing regression on several
1933 SPECfp benchmarks. */
1954 in QImode, HImode and SImode.
1955 Relative to reg-reg move (2). */
1959 in SFmode, DFmode and XFmode */
1961 in SFmode, DFmode and XFmode */
1964 in SImode and DImode */
1966 in SImode and DImode */
1969 in SImode, DImode and TImode */
1971 in SImode, DImode and TImode */
1977 /* FIXME perhaps more appropriate value is 5. */
1985 core_memcpy,
1986 core_memset,
1998 };
2001 /* Set by -mtune. */
2004 /* Set by -mtune or -Os. */
2007 /* Processor feature/optimization bitmasks. */
2008 #define m_386 (1<<PROCESSOR_I386)
2009 #define m_486 (1<<PROCESSOR_I486)
2010 #define m_PENT (1<<PROCESSOR_PENTIUM)
2011 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2012 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2013 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2014 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2015 #define m_CORE2 (1<<PROCESSOR_CORE2)
2016 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2017 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2018 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2019 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2020 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2021 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2022 #define m_INTEL (1<<PROCESSOR_INTEL)
2024 #define m_GEODE (1<<PROCESSOR_GEODE)
2025 #define m_K6 (1<<PROCESSOR_K6)
2026 #define m_K6_GEODE (m_K6 | m_GEODE)
2027 #define m_K8 (1<<PROCESSOR_K8)
2028 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2029 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2030 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2031 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2032 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2033 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2034 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2035 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2036 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2037 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2038 #define m_BTVER (m_BTVER1 | m_BTVER2)
2039 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2041 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2044 #undef DEF_TUNE
2045 #define DEF_TUNE(tune, name, selector) name,
2047 #undef DEF_TUNE
2048 };
2050 /* Feature tests against the various tunings. */
2053 /* Feature tests against the various tunings used to create ix86_tune_features
2054 based on the processor mask. */
2056 #undef DEF_TUNE
2057 #define DEF_TUNE(tune, name, selector) selector,
2059 #undef DEF_TUNE
2060 };
2062 /* Feature tests against the various architecture variations. */
2065 /* Feature tests against the various architecture variations, used to create
2066 ix86_arch_features based on the processor mask. */
2068 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2071 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2074 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2077 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2080 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2082 };
2084 /* In case the average insn count for single function invocation is
2085 lower than this constant, emit fast (but longer) prologue and
2086 epilogue code. */
2087 #define FAST_PROLOGUE_INSN_COUNT 20
2089 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2094 /* Array of the smallest class containing reg number REGNO, indexed by
2095 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2098 {
2099 /* ax, dx, cx, bx */
2101 /* si, di, bp, sp */
2103 /* FP registers */
2106 /* arg pointer */
2107 NON_Q_REGS,
2108 /* flags, fpsr, fpcr, frame */
2110 /* SSE registers */
2113 /* MMX registers */
2116 /* REX registers */
2119 /* SSE REX registers */
2122 /* AVX-512 SSE registers */
2127 /* Mask registers. */
2130 };
2132 /* The "default" register map used in 32bit mode. */
2135 {
2146 };
2148 /* The "default" register map used in 64bit mode. */
2151 {
2162 };
2164 /* Define the register numbers to be used in Dwarf debugging information.
2165 The SVR4 reference port C compiler uses the following register numbers
2166 in its Dwarf output code:
2167 0 for %eax (gcc regno = 0)
2168 1 for %ecx (gcc regno = 2)
2169 2 for %edx (gcc regno = 1)
2170 3 for %ebx (gcc regno = 3)
2171 4 for %esp (gcc regno = 7)
2172 5 for %ebp (gcc regno = 6)
2173 6 for %esi (gcc regno = 4)
2174 7 for %edi (gcc regno = 5)
2175 The following three DWARF register numbers are never generated by
2176 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2177 believes these numbers have these meanings.
2178 8 for %eip (no gcc equivalent)
2179 9 for %eflags (gcc regno = 17)
2180 10 for %trapno (no gcc equivalent)
2181 It is not at all clear how we should number the FP stack registers
2182 for the x86 architecture. If the version of SDB on x86/svr4 were
2183 a bit less brain dead with respect to floating-point then we would
2184 have a precedent to follow with respect to DWARF register numbers
2185 for x86 FP registers, but the SDB on x86/svr4 is so completely
2186 broken with respect to FP registers that it is hardly worth thinking
2187 of it as something to strive for compatibility with.
2188 The version of x86/svr4 SDB I have at the moment does (partially)
2189 seem to believe that DWARF register number 11 is associated with
2190 the x86 register %st(0), but that's about all. Higher DWARF
2191 register numbers don't seem to be associated with anything in
2192 particular, and even for DWARF regno 11, SDB only seems to under-
2193 stand that it should say that a variable lives in %st(0) (when
2194 asked via an `=' command) if we said it was in DWARF regno 11,
2195 but SDB still prints garbage when asked for the value of the
2196 variable in question (via a `/' command).
2197 (Also note that the labels SDB prints for various FP stack regs
2198 when doing an `x' command are all wrong.)
2199 Note that these problems generally don't affect the native SVR4
2200 C compiler because it doesn't allow the use of -O with -g and
2201 because when it is *not* optimizing, it allocates a memory
2202 location for each floating-point variable, and the memory
2203 location is what gets described in the DWARF AT_location
2204 attribute for the variable in question.
2205 Regardless of the severe mental illness of the x86/svr4 SDB, we
2206 do something sensible here and we use the following DWARF
2207 register numbers. Note that these are all stack-top-relative
2208 numbers.
2209 11 for %st(0) (gcc regno = 8)
2210 12 for %st(1) (gcc regno = 9)
2211 13 for %st(2) (gcc regno = 10)
2212 14 for %st(3) (gcc regno = 11)
2213 15 for %st(4) (gcc regno = 12)
2214 16 for %st(5) (gcc regno = 13)
2215 17 for %st(6) (gcc regno = 14)
2216 18 for %st(7) (gcc regno = 15)
2217 */
2219 {
2230 };
2232 /* Define parameter passing and return registers. */
2235 {
2237 };
2240 {
2242 };
2245 {
2247 };
2249 /* Additional registers that are clobbered by SYSV calls. */
2252 {
2257 };
2259 /* Define the structure for the machine field in struct function. */
2264 rtx rtl;
2266 };
2268 /* Structure describing stack frame layout.
2269 Stack grows downward:
2271 [arguments]
2272 <- ARG_POINTER
2273 saved pc
2275 saved static chain if ix86_static_chain_on_stack
2277 saved frame pointer if frame_pointer_needed
2278 <- HARD_FRAME_POINTER
2279 [saved regs]
2280 <- regs_save_offset
2281 [padding0]
2283 [saved SSE regs]
2284 <- sse_regs_save_offset
2285 [padding1] |
2286 | <- FRAME_POINTER
2287 [va_arg registers] |
2288 |
2289 [frame] |
2290 |
2291 [padding2] | = to_allocate
2292 <- STACK_POINTER
2293 */
2294 struct ix86_frame
2295 {
2302 /* The offsets relative to ARG_POINTER. */
2303 HOST_WIDE_INT frame_pointer_offset;
2304 HOST_WIDE_INT hard_frame_pointer_offset;
2305 HOST_WIDE_INT stack_pointer_offset;
2306 HOST_WIDE_INT hfp_save_offset;
2307 HOST_WIDE_INT reg_save_offset;
2308 HOST_WIDE_INT sse_reg_save_offset;
2310 /* When save_regs_using_mov is set, emit prologue using
2311 move instead of push instructions. */
2313 };
2315 /* Which cpu are we scheduling for. */
2318 /* Which cpu are we optimizing for. */
2321 /* Which instruction set architecture to use. */
2324 /* True if processor has SSE prefetch instruction. */
2327 /* -mstackrealign option */
2344 /* Preferred alignment for stack boundary in bits. */
2347 /* Alignment for incoming stack boundary in bits specified at
2348 command line. */
2351 /* Default alignment for incoming stack boundary in bits. */
2354 /* Alignment for incoming stack boundary in bits. */
2357 /* Calling abi specific va_list type nodes. */
2361 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2365 /* Fence to use after loop using movnt. */
2366 tree x86_mfence;
2368 /* Register class used for passing given 64bit part of the argument.
2369 These represent classes as documented by the PS ABI, with the exception
2370 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2371 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2373 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2374 whenever possible (upper half does contain padding). */
2375 enum x86_64_reg_class
2376 {
2377 X86_64_NO_CLASS,
2378 X86_64_INTEGER_CLASS,
2379 X86_64_INTEGERSI_CLASS,
2380 X86_64_SSE_CLASS,
2381 X86_64_SSESF_CLASS,
2382 X86_64_SSEDF_CLASS,
2383 X86_64_SSEUP_CLASS,
2384 X86_64_X87_CLASS,
2385 X86_64_X87UP_CLASS,
2386 X86_64_COMPLEX_X87_CLASS,
2387 X86_64_MEMORY_CLASS
2388 };
2390 #define MAX_CLASSES 8
2392 /* Table of constants used by fldpi, fldln2, etc.... */
2396 \f
2401 const_tree);
2413 enum ix86_function_specific_strings
2414 {
2415 IX86_FUNCTION_SPECIFIC_ARCH,
2416 IX86_FUNCTION_SPECIFIC_TUNE,
2417 IX86_FUNCTION_SPECIFIC_MAX
2418 };
2439 \f
2440 #ifndef SUBTARGET32_DEFAULT_CPU
2442 #endif
2444 /* Whether -mtune= or -march= were specified */
2448 /* Vectorization library interface and handlers. */
2454 /* Processor target table, indexed by processor number */
2455 struct ptt
2456 {
2464 };
2466 /* This table must be in sync with enum processor_type in i386.h. */
2468 {
2494 };
2495 \f
2496 static bool
2498 {
2500 }
2502 static unsigned int
2504 {
2507 /* vzeroupper instructions are inserted immediately after reload to
2508 account for possible spills from 256bit registers. The pass
2509 reuses mode switching infrastructure by re-running mode insertion
2510 pass, so disable entities that have already been processed. */
2516 /* Call optimize_mode_switching. */
2519 }
2524 {
2536 };
2539 {
2543 {}
2545 /* opt_pass methods: */
2553 rtl_opt_pass *
2555 {
2557 }
2559 /* Return true if a red-zone is in use. */
2563 {
2565 }
2566 \f
2567 /* Return a string that documents the current -m options. The caller is
2568 responsible for freeing the string. */
2574 {
2575 struct ix86_target_opts
2576 {
2579 };
2581 /* This table is ordered so that options like -msse4.2 that imply
2582 preceding options while match those first. */
2584 {
2626 };
2628 /* Flag options. */
2630 {
2659 };
2676 /* Add -march= option. */
2678 {
2681 }
2683 /* Add -mtune= option. */
2685 {
2688 }
2690 /* Add -m32/-m64/-mx32. */
2692 {
2695 else
2697 isa &= ~ (OPTION_MASK_ISA_64BIT
2698 | OPTION_MASK_ABI_64
2700 }
2701 else
2705 /* Pick out the options in isa options. */
2707 {
2709 {
2712 }
2713 }
2716 {
2719 isa);
2720 }
2722 /* Add flag options. */
2724 {
2726 {
2729 }
2730 }
2733 {
2736 }
2738 /* Add -fpmath= option. */
2740 {
2743 {
2758 }
2759 }
2761 /* Any options? */
2767 /* Size the string. */
2771 {
2776 }
2778 /* Build the string. */
2783 {
2790 {
2792 line_len++;
2795 {
2799 }
2800 }
2804 {
2808 }
2809 }
2815 }
2817 /* Return true, if profiling code should be emitted before
2818 prologue. Otherwise it returns false.
2819 Note: For x86 with "hotfix" it is sorried. */
2820 static bool
2822 {
2824 }
2826 /* Function that is callable from the debugger to print the current
2827 options. */
2828 void ATTRIBUTE_UNUSED
2830 {
2836 {
2839 }
2840 else
2844 }
2847 #define DEF_ENUM
2848 #define DEF_ALG(alg, name) #name,
2850 #undef DEF_ENUM
2851 #undef DEF_ALG
2852 };
2854 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2855 The string is of the following form (or comma separated list of it):
2857 strategy_alg:max_size:[align|noalign]
2859 where the full size range for the strategy is either [0, max_size] or
2860 [min_size, max_size], in which min_size is the max_size + 1 of the
2861 preceding range. The last size range must have max_size == -1.
2863 Examples:
2865 1.
2866 -mmemcpy-strategy=libcall:-1:noalign
2868 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2871 2.
2872 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2874 This is to tell the compiler to use the following strategy for memset
2875 1) when the expected size is between [1, 16], use rep_8byte strategy;
2876 2) when the size is between [17, 2048], use vector_loop;
2877 3) when the size is > 2048, use libcall. */
2879 struct stringop_size_range
2880 {
2882 stringop_alg alg;
2884 };
2886 static void
2888 {
2896 else
2901 do
2902 {
2912 {
2916 }
2919 {
2923 }
2930 {
2932 alg_name,
2935 }
2943 else
2944 {
2948 }
2949 n++;
2951 }
2955 {
2960 }
2963 {
2967 }
2969 /* Now override the default algs array. */
2971 {
2977 }
2978 }
2980 \f
2981 /* parse -mtune-ctrl= option. When DUMP is true,
2982 print the features that are explicitly set. */
2984 static void
2986 {
2994 do
2995 {
3002 {
3003 curr_feature_string++;
3005 }
3007 {
3009 {
3015 }
3016 }
3021 }
3024 }
3026 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3027 processor type. */
3029 static void
3031 {
3036 {
3039 else
3041 }
3044 {
3049 }
3052 }
3055 /* Override various settings based on options. If MAIN_ARGS_P, the
3056 options are from the command line, otherwise they are from
3057 attributes. */
3059 static void
3063 {
3071 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3072 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3073 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3074 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3075 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3076 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3077 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3078 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3079 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3080 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3081 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3082 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3083 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3084 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3085 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3086 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3087 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3088 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3089 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3090 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3091 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3092 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3093 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3094 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3095 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3096 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3097 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3098 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3099 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3100 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3101 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3102 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3103 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3104 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3105 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3106 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3107 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3108 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3109 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3110 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3111 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3112 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3113 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3114 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3115 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3116 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3118 #define PTA_CORE2 \
3119 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3120 | PTA_CX16 | PTA_FXSR)
3121 #define PTA_NEHALEM \
3122 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3123 #define PTA_WESTMERE \
3124 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3125 #define PTA_SANDYBRIDGE \
3126 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3127 #define PTA_IVYBRIDGE \
3128 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3129 #define PTA_HASWELL \
3130 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3131 | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE)
3132 #define PTA_BROADWELL \
3133 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3134 #define PTA_BONNELL \
3135 (PTA_CORE2 | PTA_MOVBE)
3136 #define PTA_SILVERMONT \
3137 (PTA_WESTMERE | PTA_MOVBE)
3139 /* if this reaches 64, need to widen struct pta flags below */
3141 static struct pta
3142 {
3147 }
3149 {
3183 PTA_SANDYBRIDGE},
3185 PTA_SANDYBRIDGE},
3187 PTA_IVYBRIDGE},
3189 PTA_IVYBRIDGE},
3279 PTA_64BIT
3281 };
3283 /* -mrecip options. */
3284 static struct
3285 {
3288 }
3290 {
3297 };
3301 /* Set up prefix/suffix so the error messages refer to either the command
3302 line argument, or the attribute(target). */
3304 {
3308 }
3309 else
3310 {
3314 }
3316 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3317 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3320 #ifdef TARGET_BI_ARCH
3321 else
3322 {
3323 #if TARGET_BI_ARCH == 1
3324 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3325 is on and OPTION_MASK_ABI_X32 is off. We turn off
3326 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3327 -mx32. */
3330 #else
3331 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3332 on and OPTION_MASK_ABI_64 is off. We turn off
3333 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3334 -m64. */
3337 #endif
3338 }
3339 #endif
3342 {
3343 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3344 OPTION_MASK_ABI_64 for TARGET_X32. */
3347 }
3350 | OPTION_MASK_ABI_X32
3353 {
3354 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3355 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3358 }
3360 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3361 SUBTARGET_OVERRIDE_OPTIONS;
3362 #endif
3364 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3365 SUBSUBTARGET_OVERRIDE_OPTIONS;
3366 #endif
3368 /* -fPIC is the default for x86_64. */
3372 /* Need to check -mtune=generic first. */
3374 {
3375 /* As special support for cross compilers we read -mtune=native
3376 as -mtune=generic. With native compilers we won't see the
3377 -mtune=native, as it was changed by the driver. */
3379 {
3381 }
3386 }
3387 else
3388 {
3392 {
3393 opts->x_ix86_tune_string
3396 }
3398 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3399 or defaulted. We need to use a sensible tune option. */
3401 {
3403 }
3404 }
3408 {
3409 /* rep; movq isn't available in 32-bit code. */
3412 }
3415 opts->x_ix86_arch_string
3418 else
3422 {
3430 }
3431 else
3438 /* For targets using ms ABI enable ms-extensions, if not
3439 explicit turned off. For non-ms ABI we turn off this
3440 option. */
3445 {
3447 {
3491 {
3494 }
3502 }
3503 }
3504 else
3505 {
3506 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3507 use of rip-relative addressing. This eliminates fixups that
3508 would otherwise be needed if this object is to be placed in a
3509 DLL, and is essentially just as efficient as direct addressing. */
3515 else
3517 }
3519 {
3522 }
3530 {
3533 /* Default cpu tuning to the architecture. */
3678 }
3696 {
3700 {
3702 {
3704 {
3712 }
3713 else
3716 }
3717 }
3718 /* Intel CPUs have always interpreted SSE prefetch instructions as
3719 NOPs; so, we can enable SSE prefetch instructions even when
3720 -mtune (rather than -march) points us to a processor that has them.
3721 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3722 higher processors. */
3727 }
3735 #ifndef USE_IX86_FRAME_POINTER
3736 #define USE_IX86_FRAME_POINTER 0
3737 #endif
3739 #ifndef USE_X86_64_FRAME_POINTER
3740 #define USE_X86_64_FRAME_POINTER 0
3741 #endif
3743 /* Set the default values for switches whose default depends on TARGET_64BIT
3744 in case they weren't overwritten by command line options. */
3746 {
3754 opts->x_flag_unwind_tables
3758 }
3759 else
3760 {
3762 opts->x_flag_omit_frame_pointer
3768 }
3773 else
3776 /* Arrange to set up i386_stack_locals for all functions. */
3779 /* Validate -mregparm= value. */
3781 {
3785 {
3789 }
3790 }
3794 /* Default align_* from the processor table. */
3796 {
3799 }
3801 {
3804 }
3806 {
3808 }
3810 /* Provide default for -mbranch-cost= value. */
3815 {
3816 opts->x_target_flags
3819 /* Enable by default the SSE and MMX builtins. Do allow the user to
3820 explicitly disable any of these. In particular, disabling SSE and
3821 MMX for kernel code is extremely useful. */
3823 opts->x_ix86_isa_flags
3830 }
3831 else
3832 {
3833 opts->x_target_flags
3837 opts->x_ix86_isa_flags
3840 /* i386 ABI does not specify red zone. It still makes sense to use it
3841 when programmer takes care to stack from being destroyed. */
3844 }
3846 /* Keep nonleaf frame pointers. */
3852 /* If we're doing fast math, we don't care about comparison order
3853 wrt NaNs. This lets us use a shorter comparison sequence. */
3857 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3858 since the insns won't need emulation. */
3862 /* Likewise, if the target doesn't have a 387, or we've specified
3863 software floating point, don't use 387 inline intrinsics. */
3867 /* Turn on MMX builtins for -msse. */
3869 opts->x_ix86_isa_flags
3872 /* Enable SSE prefetch. */
3877 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
3880 opts->x_ix86_isa_flags
3883 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3886 opts->x_ix86_isa_flags
3889 /* Enable lzcnt instruction for -mabm. */
3891 opts->x_ix86_isa_flags
3894 /* Validate -mpreferred-stack-boundary= value or default it to
3895 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3898 {
3905 {
3909 else
3912 }
3913 else
3914 ix86_preferred_stack_boundary
3916 }
3918 /* Set the default value for -mstackrealign. */
3924 /* Validate -mincoming-stack-boundary= value or default it to
3925 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3928 {
3935 else
3936 {
3937 ix86_user_incoming_stack_boundary
3939 ix86_incoming_stack_boundary
3941 }
3942 }
3944 /* Accept -msseregparm only if at least SSE support is enabled. */
3950 {
3952 {
3954 {
3957 }
3960 {
3963 }
3964 }
3965 }
3966 /* For all chips supporting SSE2, -mfpmath=sse performs better than
3967 fpmath=387. The second is however default at many targets since the
3968 extra 80bit precision of temporaries is considered to be part of ABI.
3969 Overwrite the default at least for -ffast-math.
3970 TODO: -mfpmath=both seems to produce same performing code with bit
3971 smaller binaries. It is however not clear if register allocation is
3972 ready for this setting.
3973 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
3974 codegen. We may switch to 387 with -ffast-math for size optimized
3975 functions. */
3979 else
3982 /* If the i387 is disabled, then do not return values in it. */
3986 /* Use external vectorized library in vectorizing intrinsics. */
3989 {
4000 }
4007 /* If stack probes are required, the space used for large function
4008 arguments on the stack must also be probed, so enable
4009 -maccumulate-outgoing-args so this happens in the prologue. */
4012 {
4017 }
4019 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4020 {
4026 }
4028 /* When scheduling description is not available, disable scheduler pass
4029 so it won't slow down the compilation and make x87 code slower. */
4050 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4052 && HAVE_prefetch
4057 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4058 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4063 {
4066 {
4068 ix86_gen_tls_local_dynamic_base_64
4070 }
4071 else
4072 {
4074 ix86_gen_tls_local_dynamic_base_64
4076 }
4077 }
4078 else
4082 {
4092 }
4093 else
4094 {
4104 }
4106 #ifdef USE_IX86_CLD
4107 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4110 #endif
4113 {
4118 }
4120 {
4124 }
4126 {
4127 #if defined(PROFILE_BEFORE_PROLOGUE)
4129 #else
4131 #endif
4132 }
4134 /* When not opts->x_optimize for size, enable vzeroupper optimization for
4135 TARGET_AVX with -fexpensive-optimizations and split 32-byte
4136 AVX unaligned load/store. */
4138 {
4148 /* Enable 128-bit AVX instruction generation
4149 for the auto-vectorizer. */
4153 }
4156 {
4163 {
4166 {
4168 q++;
4169 }
4170 else
4175 else
4176 {
4179 {
4182 }
4185 {
4189 }
4190 }
4195 else
4197 }
4198 }
4205 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4206 for 64-bit Bionic. */
4211 ? MASK_LONG_DOUBLE_128
4214 /* Only one of them can be active. */
4218 /* Save the initial options in case the user does function specific
4219 options. */
4221 target_option_default_node = target_option_current_node
4224 /* Handle stack protector */
4226 opts->x_ix86_stack_protector_guard
4229 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4231 {
4235 }
4238 {
4242 }
4243 }
4245 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4247 static void
4249 {
4251 static struct register_pass_info insert_vzeroupper_info
4254 };
4259 /* This needs to be done at start up. It's convenient to do it here. */
4261 }
4263 /* Update register usage after having seen the compiler flags. */
4265 static void
4267 {
4271 /* The PIC register, if it exists, is fixed. */
4276 /* For 32-bit targets, squash the REX registers. */
4278 {
4285 }
4287 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4295 {
4296 /* Set/reset conditionally defined registers from
4297 CALL_USED_REGISTERS initializer. */
4301 /* Calculate registers of CLOBBERED_REGS register set
4302 as call used registers from GENERAL_REGS register set. */
4306 }
4308 /* If MMX is disabled, squash the registers. */
4314 /* If SSE is disabled, squash the registers. */
4320 /* If the FPU is disabled, squash the registers. */
4326 /* If AVX512F is disabled, squash the registers. */
4328 {
4334 }
4335 }
4337 \f
4338 /* Save the current options */
4340 static void
4343 {
4378 /* The fields are char but the variables are not; make sure the
4379 values fit in the fields. */
4384 }
4386 /* Restore the current options */
4388 static void
4391 {
4397 /* We don't change -fPIC. */
4434 /* Recreate the arch feature tests if the arch changed */
4436 {
4441 }
4443 /* Recreate the tune optimization tests */
4446 }
4448 /* Print the current options */
4450 static void
4453 {
4471 {
4474 }
4475 }
4477 \f
4478 /* Inner function to process the attribute((target(...))), take an argument and
4479 set the current options from the argument. If we have a list, recursively go
4480 over the list. */
4482 static bool
4487 {
4491 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4492 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4493 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4494 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4495 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4497 enum ix86_opt_type
4498 {
4499 ix86_opt_unknown,
4500 ix86_opt_yes,
4501 ix86_opt_no,
4502 ix86_opt_str,
4503 ix86_opt_enum,
4504 ix86_opt_isa
4505 };
4507 static const struct
4508 {
4515 /* isa options */
4558 /* enum options */
4561 /* string options */
4565 /* flag options */
4567 OPT_mcld,
4568 MASK_CLD),
4571 OPT_mfancy_math_387,
4572 MASK_NO_FANCY_MATH_387),
4575 OPT_mieee_fp,
4576 MASK_IEEE_FP),
4579 OPT_minline_all_stringops,
4580 MASK_INLINE_ALL_STRINGOPS),
4583 OPT_minline_stringops_dynamically,
4584 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4587 OPT_mno_align_stringops,
4588 MASK_NO_ALIGN_STRINGOPS),
4591 OPT_mrecip,
4592 MASK_RECIP),
4594 };
4596 /* If this is a list, recurse to get the options. */
4598 {
4605 enum_opts_set))
4609 }
4612 {
4615 }
4617 /* Handle multiple arguments separated by commas. */
4621 {
4635 {
4639 }
4640 else
4641 {
4644 }
4646 /* Recognize no-xxx. */
4648 {
4652 }
4653 else
4656 /* Find the option. */
4660 {
4668 {
4673 }
4674 }
4676 /* Process the option. */
4678 {
4681 }
4684 {
4690 }
4693 {
4699 else
4701 }
4704 {
4706 {
4709 }
4710 else
4712 }
4715 {
4723 global_dc);
4724 else
4725 {
4728 }
4729 }
4731 else
4733 }
4736 }
4738 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4740 tree
4744 {
4759 /* Process each of the options on the chain. */
4764 /* If the changed options are different from the default, rerun
4765 ix86_option_override_internal, and then save the options away.
4766 The string options are are attribute options, and will be undone
4767 when we copy the save structure. */
4773 {
4774 /* If we are using the default tune= or arch=, undo the string assigned,
4775 and use the default. */
4786 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4791 {
4794 }
4796 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4799 /* Add any builtin functions with the new isa if any. */
4802 /* Save the current options unless we are validating options for
4803 #pragma. */
4810 /* Free up memory allocated to hold the strings */
4813 }
4816 }
4818 /* Hook to validate attribute((target("string"))). */
4820 static bool
4823 tree args,
4825 {
4830 /* attribute((target("default"))) does nothing, beyond
4831 affecting multi-versioning. */
4840 /* Get the optimization options of the current function. */
4846 /* Init func_options. */
4854 /* Initialize func_options to the default before its target options can
4855 be set. */
4868 {
4873 }
4876 }
4878 \f
4879 /* Hook to determine if one function can safely inline another. */
4881 static bool
4883 {
4888 /* If callee has no option attributes, then it is ok to inline. */
4892 /* If caller has no option attributes, but callee does then it is not ok to
4893 inline. */
4897 else
4898 {
4902 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4903 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4904 function. */
4909 /* See if we have the same non-isa options. */
4913 /* See if arch, tune, etc. are the same. */
4926 else
4928 }
4931 }
4933 \f
4934 /* Remember the last target of ix86_set_current_function. */
4937 /* Invalidate ix86_previous_fndecl cache. */
4938 void
4940 {
4942 }
4944 /* Establish appropriate back-end context for processing the function
4945 FNDECL. The argument might be NULL to indicate processing at top
4946 level, outside of any function scope. */
4947 static void
4949 {
4950 /* Only change the context if the function changes. This hook is called
4951 several times in the course of compiling a function, and we don't want to
4952 slow things down too much or call target_reinit when it isn't safe. */
4954 {
4955 tree old_tree = (ix86_previous_fndecl
4959 tree new_tree = (fndecl
4965 ;
4968 {
4973 else
4976 }
4979 {
4987 else
4990 }
4991 }
4992 }
4994 \f
4995 /* Return true if this goes in large data/bss. */
4997 static bool
4999 {
5003 /* Functions are never large data. */
5008 {
5014 }
5015 else
5016 {
5019 /* If this is an incomplete type with size 0, then we can't put it
5020 in data because it might be too big when completed. */
5023 }
5026 }
5028 /* Switch to the appropriate section for output of DECL.
5029 DECL is either a `VAR_DECL' node or a constant of some sort.
5030 RELOC indicates whether forming the initial value of DECL requires
5031 link-time relocations. */
5036 {
5039 {
5043 {
5077 /* We don't split these for medium model. Place them into
5078 default sections and hope for best. */
5080 }
5082 {
5083 /* We might get called with string constants, but get_named_section
5084 doesn't like them as they are not DECLs. Also, we need to set
5085 flags in that case. */
5089 }
5090 }
5092 }
5094 /* Select a set of attributes for section NAME based on the properties
5095 of DECL and whether or not RELOC indicates that DECL's initializer
5096 might contain runtime relocations. */
5098 static unsigned int ATTRIBUTE_UNUSED
5100 {
5114 }
5116 /* Build up a unique section name, expressed as a
5117 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5118 RELOC indicates whether the initial value of EXP requires
5119 link-time relocations. */
5121 static void ATTRIBUTE_UNUSED
5123 {
5126 {
5128 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5132 {
5156 /* We don't split these for medium model. Place them into
5157 default sections and hope for best. */
5159 }
5161 {
5168 /* If we're using one_only, then there needs to be a .gnu.linkonce
5169 prefix to the section name. */
5176 }
5177 }
5179 }
5181 #ifdef COMMON_ASM_OP
5182 /* This says how to output assembler code to declare an
5183 uninitialized external linkage data object.
5185 For medium model x86-64 we need to use .largecomm opcode for
5186 large objects. */
5187 void
5191 {
5195 else
5200 }
5201 #endif
5203 /* Utility function for targets to use in implementing
5204 ASM_OUTPUT_ALIGNED_BSS. */
5206 void
5210 {
5214 else
5217 #ifdef ASM_DECLARE_OBJECT_NAME
5220 #else
5221 /* Standard thing is just output label for the object. */
5225 }
5226 \f
5227 /* Decide whether we must probe the stack before any space allocation
5228 on this target. It's essentially TARGET_STACK_PROBE except when
5229 -fstack-check causes the stack to be already probed differently. */
5231 bool
5233 {
5234 /* Do not probe the stack twice if static stack checking is enabled. */
5239 }
5240 \f
5241 /* Decide whether we can make a sibling call to a function. DECL is the
5242 declaration of the function being targeted by the call and EXP is the
5243 CALL_EXPR representing the call. */
5245 static bool
5247 {
5251 /* If we are generating position-independent code, we cannot sibcall
5252 optimize any indirect call, or a direct call to a global function,
5253 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5255 && !TARGET_64BIT
5256 && flag_pic
5260 /* If we need to align the outgoing stack, then sibcalling would
5261 unalign the stack, which may break the called function. */
5267 {
5270 }
5271 else
5272 {
5273 /* We're looking at the CALL_EXPR, we need the type of the function. */
5278 }
5280 /* Check that the return value locations are the same. Like
5281 if we are returning floats on the 80387 register stack, we cannot
5282 make a sibcall from a function that doesn't return a float to a
5283 function that does or, conversely, from a function that does return
5284 a float to a function that doesn't; the necessary stack adjustment
5285 would not be executed. This is also the place we notice
5286 differences in the return value ABI. Note that it is ok for one
5287 of the functions to have void return type as long as the return
5288 value of the other is passed in a register. */
5293 {
5296 }
5298 ;
5303 {
5304 /* The SYSV ABI has more call-clobbered registers;
5305 disallow sibcalls from MS to SYSV. */
5309 }
5310 else
5311 {
5312 /* If this call is indirect, we'll need to be able to use a
5313 call-clobbered register for the address of the target function.
5314 Make sure that all such registers are not used for passing
5315 parameters. Note that DLLIMPORT functions are indirect. */
5318 {
5320 {
5321 /* ??? Need to count the actual number of registers to be used,
5322 not the possible number of registers. Fix later. */
5324 }
5325 }
5326 }
5328 /* Otherwise okay. That also includes certain types of indirect calls. */
5330 }
5332 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5333 and "sseregparm" calling convention attributes;
5334 arguments as in struct attribute_spec.handler. */
5336 static tree
5338 tree args,
5341 {
5346 {
5348 name);
5351 }
5353 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5355 {
5356 tree cst;
5359 {
5361 }
5364 {
5366 }
5370 {
5373 name);
5375 }
5377 {
5381 }
5384 }
5387 {
5388 /* Do not warn when emulating the MS ABI. */
5393 name);
5396 }
5398 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5400 {
5402 {
5404 }
5406 {
5408 }
5410 {
5412 }
5414 {
5416 }
5417 }
5419 /* Can combine stdcall with fastcall (redundant), regparm and
5420 sseregparm. */
5422 {
5424 {
5426 }
5428 {
5430 }
5432 {
5434 }
5435 }
5437 /* Can combine cdecl with regparm and sseregparm. */
5439 {
5441 {
5443 }
5445 {
5447 }
5449 {
5451 }
5452 }
5454 {
5457 name);
5459 {
5461 }
5463 {
5465 }
5467 {
5469 }
5470 }
5472 /* Can combine sseregparm with all attributes. */
5475 }
5477 /* The transactional memory builtins are implicitly regparm or fastcall
5478 depending on the ABI. Override the generic do-nothing attribute that
5479 these builtins were declared with, and replace it with one of the two
5480 attributes that we expect elsewhere. */
5482 static tree
5484 tree args ATTRIBUTE_UNUSED,
5486 {
5487 tree alt;
5489 /* In no case do we want to add the placeholder attribute. */
5492 /* The 64-bit ABI is unchanged for transactional memory. */
5496 /* ??? Is there a better way to validate 32-bit windows? We have
5497 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5500 else
5501 {
5504 }
5508 }
5510 /* This function determines from TYPE the calling-convention. */
5512 unsigned int
5514 {
5517 tree attrs;
5524 {
5534 /* Regparam isn't allowed for thiscall and fastcall. */
5536 {
5541 }
5545 }
5552 || is_stdarg
5558 }
5560 /* Return 0 if the attributes for two types are incompatible, 1 if they
5561 are compatible, and 2 if they are nearly compatible (which causes a
5562 warning to be generated). */
5564 static int
5566 {
5582 }
5583 \f
5584 /* Return the regparm value for a function with the indicated TYPE and DECL.
5585 DECL may be NULL when calling function indirectly
5586 or considering a libcall. */
5588 static int
5590 {
5591 tree attr;
5602 {
5605 {
5608 }
5609 }
5615 /* Use register calling convention for local functions when possible. */
5618 /* Caller and callee must agree on the calling convention, so
5619 checking here just optimize means that with
5620 __attribute__((optimize (...))) caller could use regparm convention
5621 and callee not, or vice versa. Instead look at whether the callee
5622 is optimized or not. */
5625 {
5626 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5629 {
5632 /* Make sure no regparm register is taken by a
5633 fixed register variable. */
5638 /* We don't want to use regparm(3) for nested functions as
5639 these use a static chain pointer in the third argument. */
5643 /* In 32-bit mode save a register for the split stack. */
5647 /* Each fixed register usage increases register pressure,
5648 so less registers should be used for argument passing.
5649 This functionality can be overriden by an explicit
5650 regparm value. */
5653 globals++;
5655 local_regparm
5660 }
5661 }
5664 }
5666 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5667 DFmode (2) arguments in SSE registers for a function with the
5668 indicated TYPE and DECL. DECL may be NULL when calling function
5669 indirectly or considering a libcall. Otherwise return 0. */
5671 static int
5673 {
5676 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5677 by the sseregparm attribute. */
5680 {
5682 {
5684 {
5688 else
5691 }
5693 }
5696 }
5698 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5699 (and DFmode for SSE2) arguments in SSE registers. */
5702 {
5703 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5707 }
5710 }
5712 /* Return true if EAX is live at the start of the function. Used by
5713 ix86_expand_prologue to determine if we need special help before
5714 calling allocate_stack_worker. */
5716 static bool
5718 {
5719 /* Cheat. Don't bother working forward from ix86_function_regparm
5720 to the function type to whether an actual argument is located in
5721 eax. Instead just look at cfg info, which is still close enough
5722 to correct at this point. This gives false positives for broken
5723 functions that might use uninitialized data that happens to be
5724 allocated in eax, but who cares? */
5726 }
5728 static bool
5730 {
5731 tree attr;
5734 {
5740 /* For 32-bit MS-ABI the default is to keep aggregate
5741 return pointer. */
5744 }
5746 }
5748 /* Value is the number of bytes of arguments automatically
5749 popped when returning from a subroutine call.
5750 FUNDECL is the declaration node of the function (as a tree),
5751 FUNTYPE is the data type of the function (as a tree),
5752 or for a library call it is an identifier node for the subroutine name.
5753 SIZE is the number of bytes of arguments passed on the stack.
5755 On the 80386, the RTD insn may be used to pop them if the number
5756 of args is fixed, but if the number is variable then the caller
5757 must pop them all. RTD can't be used for library calls now
5758 because the library is compiled with the Unix compiler.
5759 Use of RTD is a selectable option, since it is incompatible with
5760 standard Unix calling sequences. If the option is not selected,
5761 the caller must always pop the args.
5763 The attribute stdcall is equivalent to RTD on a per module basis. */
5765 static int
5767 {
5770 /* None of the 64-bit ABIs pop arguments. */
5781 /* Lose any fake structure return argument if it is passed on the stack. */
5784 {
5788 }
5791 }
5793 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5795 static bool
5797 {
5798 /* Check operand constraints in case hard registers were propagated
5799 into insn pattern. This check prevents combine pass from
5800 generating insn patterns with invalid hard register operands.
5801 These invalid insns can eventually confuse reload to error out
5802 with a spill failure. See also PRs 46829 and 46843. */
5804 {
5811 {
5819 /* For pre-AVX disallow unaligned loads/stores where the
5820 instructions don't support it. */
5824 {
5828 }
5830 /* A unary operator may be accepted by the predicate, but it
5831 is irrelevant for matching constraints. */
5836 {
5844 }
5851 /* Operand has no constraints, anything is OK. */
5855 {
5858 && operands_match_p
5862 {
5865 }
5866 }
5870 }
5871 }
5874 }
5875 \f
5876 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5878 static unsigned HOST_WIDE_INT
5880 {
5884 }
5885 \f
5886 /* Argument support functions. */
5888 /* Return true when register may be used to pass function parameters. */
5889 bool
5891 {
5896 {
5900 else
5906 }
5912 /* TODO: The function should depend on current function ABI but
5913 builtins.c would need updating then. Therefore we use the
5914 default ABI. */
5916 /* RAX is used as hidden argument to va_arg functions. */
5922 else
5929 }
5931 /* Return if we do not know how to pass TYPE solely in registers. */
5933 static bool
5935 {
5939 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5940 The layout_type routine is crafty and tries to trick us into passing
5941 currently unsupported vector types on the stack by using TImode. */
5944 }
5946 /* It returns the size, in bytes, of the area reserved for arguments passed
5947 in registers for the function represented by fndecl dependent to the used
5948 abi format. */
5949 int
5951 {
5955 else
5960 }
5962 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5963 call abi used. */
5964 enum calling_abi
5966 {
5968 {
5971 {
5974 }
5978 }
5980 }
5982 /* We add this as a workaround in order to use libc_has_function
5983 hook in i386.md. */
5984 bool
5986 {
5988 }
5990 static bool
5992 {
5994 {
5998 else
6000 }
6002 }
6004 static enum calling_abi
6006 {
6010 }
6012 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6013 call abi used. */
6014 enum calling_abi
6016 {
6020 }
6022 /* Write the extra assembler code needed to declare a function properly. */
6024 void
6026 tree decl)
6027 {
6031 {
6037 }
6039 #ifdef SUBTARGET_ASM_UNWIND_INIT
6041 #endif
6045 /* Output magic byte marker, if hot-patch attribute is set. */
6047 {
6049 {
6050 /* leaq [%rsp + 0], %rsp */
6053 }
6054 else
6055 {
6056 /* movl.s %edi, %edi
6057 push %ebp
6058 movl.s %esp, %ebp */
6061 }
6062 }
6063 }
6065 /* regclass.c */
6068 /* Implementation of call abi switching target hook. Specific to FNDECL
6069 the specific call register sets are set. See also
6070 ix86_conditional_register_usage for more details. */
6071 void
6073 {
6076 else
6078 }
6080 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6081 expensive re-initialization of init_regs each time we switch function context
6082 since this is needed only during RTL expansion. */
6083 static void
6085 {
6089 }
6091 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6092 for a call to a function whose data type is FNTYPE.
6093 For a library call, FNTYPE is 0. */
6095 void
6099 tree fndecl,
6101 {
6107 {
6110 }
6111 else
6112 {
6115 }
6119 /* Set up the number of registers to use for passing arguments. */
6122 {
6124 ? X86_64_REGPARM_MAX
6126 }
6128 {
6131 {
6133 ? X86_64_SSE_REGPARM_MAX
6135 }
6136 }
6144 /* Because type might mismatch in between caller and callee, we need to
6145 use actual type of function for local calls.
6146 FIXME: cgraph_analyze can be told to actually record if function uses
6147 va_start so for local functions maybe_vaarg can be made aggressive
6148 helping K&R code.
6149 FIXME: once typesytem is fixed, we won't need this code anymore. */
6157 {
6158 /* If there are variable arguments, then we won't pass anything
6159 in registers in 32-bit mode. */
6161 {
6170 }
6172 /* Use ecx and edx registers if function has fastcall attribute,
6173 else look for regparm information. */
6175 {
6178 {
6181 }
6183 {
6186 }
6187 else
6189 }
6191 /* Set up the number of SSE registers used for passing SFmode
6192 and DFmode arguments. Warn for mismatching ABI. */
6194 }
6195 }
6197 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6198 But in the case of vector types, it is some vector mode.
6200 When we have only some of our vector isa extensions enabled, then there
6201 are some modes for which vector_mode_supported_p is false. For these
6202 modes, the generic vector support in gcc will choose some non-vector mode
6203 in order to implement the type. By computing the natural mode, we'll
6204 select the proper ABI location for the operand and not depend on whatever
6205 the middle-end decides to do with these vector types.
6207 The midde-end can't deal with the vector types > 16 bytes. In this
6208 case, we return the original mode and warn ABI change if CUM isn't
6209 NULL.
6211 If INT_RETURN is true, warn ABI change if the vector mode isn't
6212 available for function return value. */
6214 static enum machine_mode
6217 {
6221 {
6224 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6226 {
6231 else
6234 /* Get the mode which has this inner mode and number of units. */
6238 {
6240 {
6245 {
6249 }
6251 {
6255 }
6258 }
6260 {
6265 {
6269 }
6271 {
6275 }
6278 }
6281 {
6286 {
6290 }
6292 {
6296 }
6297 }
6299 {
6304 {
6308 }
6310 {
6314 }
6315 }
6317 }
6320 }
6321 }
6324 }
6326 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6327 this may not agree with the mode that the type system has chosen for the
6328 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6329 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6331 static rtx
6334 {
6335 rtx tmp;
6339 else
6340 {
6344 }
6347 }
6349 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6350 of this code is to classify each 8bytes of incoming argument by the register
6351 class and assign registers accordingly. */
6353 /* Return the union class of CLASS1 and CLASS2.
6354 See the x86-64 PS ABI for details. */
6356 static enum x86_64_reg_class
6358 {
6359 /* Rule #1: If both classes are equal, this is the resulting class. */
6363 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6364 the other class. */
6370 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6374 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6382 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6383 MEMORY is used. */
6392 /* Rule #6: Otherwise class SSE is used. */
6394 }
6396 /* Classify the argument of type TYPE and mode MODE.
6397 CLASSES will be filled by the register class used to pass each word
6398 of the operand. The number of words is returned. In case the parameter
6399 should be passed in memory, 0 is returned. As a special case for zero
6400 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6402 BIT_OFFSET is used internally for handling records and specifies offset
6403 of the offset in bits modulo 512 to avoid overflow cases.
6405 See the x86-64 PS ABI for details.
6406 */
6408 static int
6411 {
6412 HOST_WIDE_INT bytes =
6414 int words
6417 /* Variable sized entities are always passed/returned in memory. */
6426 {
6428 tree field;
6431 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6438 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6439 signalize memory class, so handle it as special case. */
6441 {
6444 }
6446 /* Classify each field of record and merge classes. */
6448 {
6450 /* And now merge the fields of structure. */
6452 {
6454 {
6460 /* Bitfields are always classified as integer. Handle them
6461 early, since later code would consider them to be
6462 misaligned integers. */
6464 {
6473 }
6474 else
6475 {
6480 /* Flexible array member is ignored. */
6487 {
6491 {
6494 "the ABI of passing struct with"
6495 " a flexible array member has"
6497 }
6499 }
6501 subclasses,
6511 }
6512 }
6513 }
6517 /* Arrays are handled as small records. */
6518 {
6525 /* The partial classes are now full classes. */
6536 }
6539 /* Unions are similar to RECORD_TYPE but offset is always 0.
6540 */
6542 {
6544 {
6552 bit_offset);
6557 }
6558 }
6563 }
6566 {
6567 /* When size > 16 bytes, if the first one isn't
6568 X86_64_SSE_CLASS or any other ones aren't
6569 X86_64_SSEUP_CLASS, everything should be passed in
6570 memory. */
6577 }
6579 /* Final merger cleanup. */
6581 {
6582 /* If one class is MEMORY, everything should be passed in
6583 memory. */
6587 /* The X86_64_SSEUP_CLASS should be always preceded by
6588 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6592 {
6593 /* The first one should never be X86_64_SSEUP_CLASS. */
6596 }
6598 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6599 everything should be passed in memory. */
6602 {
6605 /* The first one should never be X86_64_X87UP_CLASS. */
6608 {
6611 "the ABI of passing union with long double"
6613 }
6615 }
6616 }
6618 }
6620 /* Compute alignment needed. We align all types to natural boundaries with
6621 exception of XFmode that is aligned to 64bits. */
6623 {
6632 /* Misaligned fields are always returned in memory. */
6635 }
6637 /* for V1xx modes, just use the base mode */
6642 /* Classification of atomic types. */
6644 {
6660 {
6663 /* Analyze last 128 bits only. */
6667 {
6670 }
6672 {
6675 }
6677 {
6681 }
6683 {
6686 }
6687 else
6689 }
6696 /* OImode shouldn't be used directly. */
6703 else
6721 else
6722 {
6726 {
6729 "the ABI of passing structure with complex float"
6731 }
6734 }
6743 /* This modes is larger than 16 bytes. */
6801 else
6805 }
6806 }
6808 /* Examine the argument and return set number of register required in each
6809 class. Return 0 iff parameter should be passed in memory. */
6810 static int
6813 {
6823 {
6845 }
6847 }
6849 /* Construct container for the argument used by GCC interface. See
6850 FUNCTION_ARG for the detailed description. */
6852 static rtx
6856 {
6857 /* The following variables hold the static issued_error state. */
6871 rtx ret;
6882 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6883 some less clueful developer tries to use floating-point anyway. */
6885 {
6887 {
6889 {
6892 }
6893 }
6895 {
6898 }
6900 }
6902 /* Likewise, error if the ABI requires us to return values in the
6903 x87 registers and the user specified -mno-80387. */
6909 {
6911 {
6914 }
6916 }
6918 /* First construct simple cases. Avoid SCmode, since we want to use
6919 single register to pass this type. */
6922 {
6937 /* Zero sized array, struct or class. */
6941 }
6980 /* Otherwise figure out the entries of the PARALLEL. */
6982 {
6986 {
6991 /* Merge TImodes on aligned occasions here too. */
6993 tmpmode
6997 else
6999 /* We've requested 24 bytes we
7000 don't have mode for. Use DImode. */
7007 intreg++;
7015 sse_regno++;
7023 sse_regno++;
7028 {
7034 {
7036 i++;
7037 }
7038 else
7063 }
7069 sse_regno++;
7073 }
7074 }
7076 /* Empty aligned struct, union or class. */
7084 }
7086 /* Update the data in CUM to advance over an argument of mode MODE
7087 and data type TYPE. (TYPE is null for libcalls where that information
7088 may not be available.) */
7090 static void
7093 HOST_WIDE_INT words)
7094 {
7096 {
7103 /* FALLTHRU */
7114 {
7117 }
7121 /* OImode shouldn't be used directly. */
7130 /* FALLTHRU */
7152 {
7157 {
7160 }
7161 }
7171 {
7176 {
7179 }
7180 }
7182 }
7183 }
7185 static void
7188 {
7191 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7198 {
7203 }
7204 else
7205 {
7209 }
7210 }
7212 static void
7214 HOST_WIDE_INT words)
7215 {
7216 /* Otherwise, this should be passed indirect. */
7221 {
7224 }
7225 }
7227 /* Update the data in CUM to advance over an argument of mode MODE and
7228 data type TYPE. (TYPE is null for libcalls where that information
7229 may not be available.) */
7231 static void
7234 {
7240 else
7251 else
7253 }
7255 /* Define where to put the arguments to a function.
7256 Value is zero to push the argument on the stack,
7257 or a hard register in which to store the argument.
7259 MODE is the argument's machine mode.
7260 TYPE is the data type of the argument (as a tree).
7261 This is null for libcalls where that information may
7262 not be available.
7263 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7264 the preceding args and about the function being called.
7265 NAMED is nonzero if this argument is a named parameter
7266 (otherwise it is an extra parameter matching an ellipsis). */
7268 static rtx
7272 {
7273 /* Avoid the AL settings for the Unix64 ABI. */
7278 {
7285 /* FALLTHRU */
7291 {
7294 /* Fastcall allocates the first two DWORD (SImode) or
7295 smaller arguments to ECX and EDX if it isn't an
7296 aggregate type . */
7298 {
7304 /* ECX not EAX is the first allocated register. */
7307 }
7309 }
7318 /* FALLTHRU */
7320 /* In 32bit, we pass TImode in xmm registers. */
7328 {
7332 }
7337 /* OImode and XImode shouldn't be used directly. */
7353 {
7357 }
7367 {
7371 }
7373 }
7376 }
7378 static rtx
7381 {
7382 /* Handle a hidden AL argument containing number of registers
7383 for varargs x86-64 functions. */
7387 ? X86_64_SSE_REGPARM_MAX
7392 {
7408 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7412 }
7418 }
7420 static rtx
7423 HOST_WIDE_INT bytes)
7424 {
7427 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7428 We use value of -2 to specify that current function call is MSABI. */
7432 /* If we've run out of registers, it goes on the stack. */
7438 /* Only floating point modes are passed in anything but integer regs. */
7440 {
7443 else
7444 {
7447 /* Unnamed floating parameters are passed in both the
7448 SSE and integer registers. */
7454 }
7455 }
7456 /* Handle aggregated types passed in register. */
7458 {
7463 }
7466 }
7468 /* Return where to put the arguments to a function.
7469 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7471 MODE is the argument's machine mode. TYPE is the data type of the
7472 argument. It is null for libcalls where that information may not be
7473 available. CUM gives information about the preceding args and about
7474 the function being called. NAMED is nonzero if this argument is a
7475 named parameter (otherwise it is an extra parameter matching an
7476 ellipsis). */
7478 static rtx
7481 {
7485 rtx arg;
7489 else
7493 /* To simplify the code below, represent vector types with a vector mode
7494 even if MMX/SSE are not active. */
7502 else
7506 }
7508 /* A C expression that indicates when an argument must be passed by
7509 reference. If nonzero for an argument, a copy of that argument is
7510 made in memory and a pointer to the argument is passed instead of
7511 the argument itself. The pointer is passed in whatever way is
7512 appropriate for passing a pointer to that type. */
7514 static bool
7517 {
7520 /* See Windows x64 Software Convention. */
7522 {
7525 {
7526 /* Arrays are passed by reference. */
7531 {
7532 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7533 are passed by reference. */
7535 }
7536 }
7538 /* __m128 is passed by reference. */
7544 }
7545 }
7550 }
7552 /* Return true when TYPE should be 128bit aligned for 32bit argument
7553 passing ABI. XXX: This function is obsolete and is only used for
7554 checking psABI compatibility with previous versions of GCC. */
7556 static bool
7558 {
7570 {
7571 /* Walk the aggregates recursively. */
7573 {
7577 {
7578 tree field;
7580 /* Walk all the structure fields. */
7582 {
7586 }
7588 }
7591 /* Just for use if some languages passes arrays by value. */
7598 }
7599 }
7601 }
7603 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7604 XXX: This function is obsolete and is only used for checking psABI
7605 compatibility with previous versions of GCC. */
7607 static unsigned int
7610 {
7611 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7612 natural boundaries. */
7614 {
7615 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7616 make an exception for SSE modes since these require 128bit
7617 alignment.
7619 The handling here differs from field_alignment. ICC aligns MMX
7620 arguments to 4 byte boundaries, while structure fields are aligned
7621 to 8 byte boundaries. */
7623 {
7626 }
7627 else
7628 {
7631 }
7632 }
7636 }
7638 /* Return true when TYPE should be 128bit aligned for 32bit argument
7639 passing ABI. */
7641 static bool
7643 {
7653 {
7654 /* Walk the aggregates recursively. */
7656 {
7660 {
7661 tree field;
7663 /* Walk all the structure fields. */
7665 field;
7667 {
7671 }
7673 }
7676 /* Just for use if some languages passes arrays by value. */
7683 }
7684 }
7685 else
7689 }
7691 /* Gives the alignment boundary, in bits, of an argument with the
7692 specified mode and type. */
7694 static unsigned int
7696 {
7699 {
7700 /* Since the main variant type is used for call, we convert it to
7701 the main variant type. */
7704 }
7705 else
7709 else
7710 {
7715 {
7716 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7718 {
7721 }
7727 }
7730 && !warned
7732 saved_align))
7733 {
7736 "The ABI for passing parameters with %d-byte"
7739 }
7740 }
7743 }
7745 /* Return true if N is a possible register number of function value. */
7747 static bool
7749 {
7751 {
7759 /* Complex values are returned in %st(0)/%st(1) pair. */
7762 /* TODO: The function should depend on current function ABI but
7763 builtins.c would need updating then. Therefore we use the
7764 default ABI. */
7769 /* Complex values are returned in %xmm0/%xmm1 pair. */
7778 }
7781 }
7783 /* Define how to find the value returned by a function.
7784 VALTYPE is the data type of the value (as a tree).
7785 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7786 otherwise, FUNC is 0. */
7788 static rtx
7791 {
7794 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7795 we normally prevent this case when mmx is not available. However
7796 some ABIs may require the result to be returned like DImode. */
7800 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7801 we prevent this case when sse is not available. However some ABIs
7802 may require the result to be returned like integer TImode. */
7807 /* 32-byte vector modes in %ymm0. */
7811 /* 64-byte vector modes in %zmm0. */
7815 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7818 else
7819 /* Most things go in %eax. */
7822 /* Override FP return register with %xmm0 for local functions when
7823 SSE math is enabled or for functions with sseregparm attribute. */
7825 {
7830 }
7832 /* OImode shouldn't be used directly. */
7836 }
7838 static rtx
7840 const_tree valtype)
7841 {
7842 rtx ret;
7844 /* Handle libcalls, which don't provide a type node. */
7846 {
7850 {
7869 }
7872 }
7874 {
7875 /* Pointers are always returned in word_mode. */
7877 }
7883 /* For zero sized structures, construct_container returns NULL, but we
7884 need to keep rest of compiler happy by returning meaningful value. */
7889 }
7891 static rtx
7893 const_tree valtype)
7894 {
7898 {
7900 {
7919 }
7920 }
7922 }
7924 static rtx
7927 {
7939 else
7941 }
7943 static rtx
7946 {
7952 }
7954 /* Pointer function arguments and return values are promoted to
7955 word_mode. */
7957 static enum machine_mode
7961 {
7963 {
7966 }
7968 for_return);
7969 }
7971 /* Return true if a structure, union or array with MODE containing FIELD
7972 should be accessed using BLKmode. */
7974 static bool
7976 {
7977 /* Union with XFmode must be in BLKmode. */
7981 }
7983 rtx
7985 {
7987 }
7989 /* Return true iff type is returned in memory. */
7991 static bool ATTRIBUTE_UNUSED
7993 {
7994 HOST_WIDE_INT size;
8005 {
8006 /* User-created vectors small enough to fit in EAX. */
8010 /* MMX/3dNow values are returned in MM0,
8011 except when it doesn't exits or the ABI prescribes otherwise. */
8015 /* SSE values are returned in XMM0, except when it doesn't exist. */
8019 /* AVX values are returned in YMM0, except when it doesn't exist. */
8023 /* AVX512F values are returned in ZMM0, except when it doesn't exist. */
8026 }
8034 /* OImode shouldn't be used directly. */
8038 }
8040 static bool ATTRIBUTE_UNUSED
8042 {
8045 }
8047 static bool ATTRIBUTE_UNUSED
8049 {
8052 /* __m128 is returned in xmm0. */
8059 /* Otherwise, the size must be exactly in [1248]. */
8061 }
8063 static bool
8065 {
8066 #ifdef SUBTARGET_RETURN_IN_MEMORY
8068 #else
8072 {
8075 else
8077 }
8078 else
8080 #endif
8081 }
8083 \f
8084 /* Create the va_list data type. */
8086 /* Returns the calling convention specific va_list date type.
8087 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8089 static tree
8091 {
8094 /* For i386 we use plain pointer to argument area. */
8104 unsigned_type_node);
8107 unsigned_type_node);
8110 ptr_type_node);
8113 ptr_type_node);
8132 /* The correct type is an array type of one element. */
8134 }
8136 /* Setup the builtin va_list data type and for 64-bit the additional
8137 calling convention specific va_list data types. */
8139 static tree
8141 {
8144 /* Initialize abi specific va_list builtin types. */
8146 {
8147 tree t;
8149 {
8154 }
8155 else
8156 {
8161 }
8163 {
8168 }
8169 else
8170 {
8175 }
8176 }
8179 }
8181 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8183 static void
8185 {
8187 alias_set_type set;
8190 /* GPR size of varargs save area. */
8193 else
8196 /* FPR size of varargs save area. We don't need it if we don't pass
8197 anything in SSE registers. */
8200 else
8214 {
8222 }
8225 {
8229 /* Now emit code to save SSE registers. The AX parameter contains number
8230 of SSE parameter registers used to call this function, though all we
8231 actually check here is the zero/non-zero status. */
8236 label));
8238 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8239 we used movdqa (i.e. TImode) instead? Perhaps even better would
8240 be if we could determine the real mode of the data, via a hook
8241 into pass_stdarg. Ignore all that for now. */
8251 {
8260 }
8263 }
8264 }
8266 static void
8268 {
8272 /* Reset to zero, as there might be a sysv vaarg used
8273 before. */
8278 {
8289 }
8290 }
8292 static void
8296 {
8298 CUMULATIVE_ARGS next_cum;
8299 tree fntype;
8301 /* This argument doesn't appear to be used anymore. Which is good,
8302 because the old code here didn't suppress rtl generation. */
8310 /* For varargs, we do not want to skip the dummy va_dcl argument.
8311 For stdargs, we do want to skip the last named argument. */
8319 else
8321 }
8323 /* Checks if TYPE is of kind va_list char *. */
8325 static bool
8327 {
8328 tree canonic;
8330 /* For 32-bit it is always true. */
8336 }
8338 /* Implement va_start. */
8340 static void
8342 {
8346 tree type;
8347 rtx ovf_rtx;
8351 {
8354 /* When we are splitting the stack, we can't refer to the stack
8355 arguments using internal_arg_pointer, because they may be on
8356 the old stack. The split stack prologue will arrange to
8357 leave a pointer to the old stack arguments in a scratch
8358 register, which we here copy to a pseudo-register. The split
8359 stack prologue can't set the pseudo-register directly because
8360 it (the prologue) runs before any registers have been saved. */
8364 {
8378 }
8379 }
8381 /* Only 64bit target needs something special. */
8383 {
8386 else
8387 {
8396 }
8398 }
8407 /* The following should be folded into the MEM_REF offset. */
8417 /* Count number of gp and fp argument registers used. */
8423 {
8429 }
8432 {
8438 }
8440 /* Find the overflow area. */
8444 else
8454 {
8455 /* Find the register save area.
8456 Prologue of the function save it right above stack frame. */
8464 }
8465 }
8467 /* Implement va_arg. */
8469 static tree
8472 {
8479 rtx container;
8481 tree ptrtype;
8485 /* Only 64bit target needs something special. */
8509 {
8522 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
8524 {
8527 }
8535 }
8537 /* Pull the value out of the saved registers. */
8542 {
8556 /* In case we are passing structure, verify that it is consecutive block
8557 on the register save area. If not we need to do moves. */
8559 {
8560 /* Verify that all registers are strictly consecutive */
8562 {
8566 {
8571 }
8572 }
8573 else
8574 {
8578 {
8583 }
8584 }
8585 }
8587 {
8590 }
8591 else
8592 {
8595 }
8597 /* First ensure that we fit completely in registers. */
8599 {
8606 }
8608 {
8616 }
8618 /* Compute index to start of area used for integer regs. */
8620 {
8621 /* int_addr = gpr + sav; */
8624 }
8626 {
8627 /* sse_addr = fpr + sav; */
8630 }
8632 {
8636 /* addr = &temp; */
8641 {
8645 tree piece_type;
8646 tree addr_type;
8647 tree daddr_type;
8656 {
8661 }
8665 else
8672 {
8675 }
8676 else
8677 {
8680 }
8687 {
8692 }
8693 else
8694 {
8695 tree copy
8700 }
8702 }
8703 }
8706 {
8710 }
8713 {
8717 }
8722 }
8724 /* ... otherwise out of the overflow area. */
8726 /* When we align parameter on stack for caller, if the parameter
8727 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8728 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8729 here with caller. */
8734 /* Care for on-stack alignment if needed. */
8737 else
8738 {
8743 }
8760 }
8761 \f
8762 /* Return true if OPNUM's MEM should be matched
8763 in movabs* patterns. */
8765 bool
8767 {
8779 }
8780 \f
8781 /* Initialize the table of extra 80387 mathematical constants. */
8783 static void
8785 {
8787 {
8793 };
8797 {
8799 /* Ensure each constant is rounded to XFmode precision. */
8802 }
8805 }
8807 /* Return non-zero if the constant is something that
8808 can be loaded with a special instruction. */
8810 int
8812 {
8815 REAL_VALUE_TYPE r;
8827 /* For XFmode constants, try to find a special 80387 instruction when
8828 optimizing for size or on those CPUs that benefit from them. */
8831 {
8840 }
8842 /* Load of the constant -0.0 or -1.0 will be split as
8843 fldz;fchs or fld1;fchs sequence. */
8850 }
8852 /* Return the opcode of the special instruction to be used to load
8853 the constant X. */
8857 {
8859 {
8879 }
8880 }
8882 /* Return the CONST_DOUBLE representing the 80387 constant that is
8883 loaded by the specified special instruction. The argument IDX
8884 matches the return value from standard_80387_constant_p. */
8886 rtx
8888 {
8895 {
8906 }
8909 XFmode);
8910 }
8912 /* Return 1 if X is all 0s and 2 if x is all 1s
8913 in supported SSE/AVX vector mode. */
8915 int
8917 {
8924 {
8945 }
8948 }
8950 /* Return the opcode of the special instruction to be used to load
8951 the constant X. */
8955 {
8957 {
8960 {
8982 }
8991 else
8996 }
8998 }
9000 /* Returns true if OP contains a symbol reference */
9002 bool
9004 {
9013 {
9015 {
9021 }
9025 }
9028 }
9030 /* Return true if it is appropriate to emit `ret' instructions in the
9031 body of a function. Do this only if the epilogue is simple, needing a
9032 couple of insns. Prior to reloading, we can't tell how many registers
9033 must be saved, so return false then. Return false if there is no frame
9034 marker to de-allocate. */
9036 bool
9038 {
9044 /* Don't allow more than 32k pop, since that's all we can do
9045 with one instruction. */
9052 }
9053 \f
9054 /* Value should be nonzero if functions must have frame pointers.
9055 Zero means the frame pointer need not be set up (and parms may
9056 be accessed via the stack pointer) in functions that seem suitable. */
9058 static bool
9060 {
9061 /* If we accessed previous frames, then the generated code expects
9062 to be able to access the saved ebp value in our frame. */
9066 /* Several x86 os'es need a frame pointer for other reasons,
9067 usually pertaining to setjmp. */
9071 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9075 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9076 allocation is 4GB. */
9080 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9081 turns off the frame pointer by default. Turn it back on now if
9082 we've not got a leaf function. */
9092 }
9094 /* Record that the current function accesses previous call frames. */
9096 void
9098 {
9100 }
9101 \f
9102 #ifndef USE_HIDDEN_LINKONCE
9103 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9104 # define USE_HIDDEN_LINKONCE 1
9105 # else
9106 # define USE_HIDDEN_LINKONCE 0
9107 # endif
9108 #endif
9112 /* Fills in the label name that should be used for a pc thunk for
9113 the given register. */
9115 static void
9117 {
9122 else
9124 }
9127 /* This function generates code for -fpic that loads %ebx with
9128 the return address of the caller and then returns. */
9130 static void
9132 {
9137 {
9139 tree decl;
9155 #if TARGET_MACHO
9157 {
9166 }
9167 else
9168 #endif
9170 {
9181 }
9182 else
9183 {
9186 }
9192 /* Make sure unwind info is emitted for the thunk if needed. */
9195 /* Pad stack IP move with 4 instructions (two NOPs count
9196 as one instruction). */
9198 {
9203 }
9214 }
9218 }
9220 /* Emit code for the SET_GOT patterns. */
9224 {
9230 {
9231 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9236 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9237 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9238 an unadorned address. */
9243 }
9248 {
9250 /* We don't need a pic base, we're not producing pic. */
9257 }
9258 else
9259 {
9268 #if TARGET_MACHO
9269 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9270 This is what will be referenced by the Mach-O PIC subsystem. */
9274 /* When we are restoring the pic base at the site of a nonlocal label,
9275 and we decided to emit the pic base above, we will still output a
9276 local label used for calculating the correction offset (even though
9277 the offset will be 0 in that case). */
9281 #endif
9282 }
9288 }
9290 /* Generate an "push" pattern for input ARG. */
9292 static rtx
9294 {
9307 stack_pointer_rtx)),
9308 arg);
9309 }
9311 /* Generate an "pop" pattern for input ARG. */
9313 static rtx
9315 {
9320 arg,
9323 stack_pointer_rtx)));
9324 }
9326 /* Return >= 0 if there is an unused call-clobbered register available
9327 for the entire function. */
9329 static unsigned int
9331 {
9335 {
9337 /* Can't use the same register for both PIC and DRAP. */
9340 else
9345 }
9348 }
9350 /* Return TRUE if we need to save REGNO. */
9352 static bool
9354 {
9365 {
9368 {
9374 }
9375 }
9386 }
9388 /* Return number of saved general prupose registers. */
9390 static int
9392 {
9398 nregs ++;
9400 }
9402 /* Return number of saved SSE registrers. */
9404 static int
9406 {
9414 nregs ++;
9416 }
9418 /* Given FROM and TO register numbers, say whether this elimination is
9419 allowed. If stack alignment is needed, we can only replace argument
9420 pointer with hard frame pointer, or replace frame pointer with stack
9421 pointer. Otherwise, frame pointer elimination is automatically
9422 handled and all other eliminations are valid. */
9424 static bool
9426 {
9432 else
9434 }
9436 /* Return the offset between two registers, one to be eliminated, and the other
9437 its replacement, at the start of a routine. */
9439 HOST_WIDE_INT
9441 {
9450 else
9451 {
9459 }
9460 }
9462 /* In a dynamically-aligned function, we can't know the offset from
9463 stack pointer to frame pointer, so we must ensure that setjmp
9464 eliminates fp against the hard fp (%ebp) rather than trying to
9465 index from %esp up to the top of the frame across a gap that is
9466 of unknown (at compile-time) size. */
9467 static rtx
9469 {
9471 }
9473 /* When using -fsplit-stack, the allocation routines set a field in
9474 the TCB to the bottom of the stack plus this much space, measured
9475 in bytes. */
9477 #define SPLIT_STACK_AVAILABLE 256
9479 /* Fill structure ix86_frame about frame of currently computed function. */
9481 static void
9483 {
9485 HOST_WIDE_INT offset;
9488 HOST_WIDE_INT to_allocate;
9496 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
9497 function prologues and leaf. */
9501 {
9506 }
9512 /* For SEH we have to limit the amount of code movement into the prologue.
9513 At present we do this via a BLOCKAGE, at which point there's very little
9514 scheduling that can be done, which means that there's very little point
9515 in doing anything except PUSHs. */
9519 /* During reload iteration the amount of registers saved can change.
9520 Recompute the value as needed. Do not recompute when amount of registers
9521 didn't change as reload does multiple calls to the function and does not
9522 expect the decision to change within single iteration. */
9525 {
9531 /* The fast prologue uses move instead of push to save registers. This
9532 is significantly longer, but also executes faster as modern hardware
9533 can execute the moves in parallel, but can't do that for push/pop.
9535 Be careful about choosing what prologue to emit: When function takes
9536 many instructions to execute we may use slow version as well as in
9537 case function is known to be outside hot spot (this is known with
9538 feedback only). Weight the size of function by number of registers
9539 to save as it is cheap to use one or two push instructions but very
9540 slow to use many of them. */
9544 || (flag_branch_probabilities
9547 else
9550 }
9552 frame->save_regs_using_mov
9554 /* If static stack checking is enabled and done with probes,
9555 the registers need to be saved before allocating the frame. */
9558 /* Skip return address. */
9561 /* Skip pushed static chain. */
9565 /* Skip saved base pointer. */
9570 /* The traditional frame pointer location is at the top of the frame. */
9573 /* Register save area */
9577 /* On SEH target, registers are pushed just before the frame pointer
9578 location. */
9582 /* Align and set SSE register save area. */
9584 {
9585 /* The only ABI that has saved SSE registers (Win64) also has a
9586 16-byte aligned default stack, and thus we don't need to be
9587 within the re-aligned local stack frame to save them. */
9591 }
9594 /* The re-aligned stack starts here. Values before this point are not
9595 directly comparable with values below this point. In order to make
9596 sure that no value happens to be the same before and after, force
9597 the alignment computation below to add a non-zero value. */
9601 /* Va-arg area */
9605 /* Align start of frame for local function. */
9614 /* Frame pointer points here. */
9619 /* Add outgoing arguments area. Can be skipped if we eliminated
9620 all the function calls as dead code.
9621 Skipping is however impossible when function calls alloca. Alloca
9622 expander assumes that last crtl->outgoing_args_size
9623 of stack frame are unused. */
9627 {
9630 }
9631 else
9634 /* Align stack boundary. Only needed if we're calling another function
9635 or using alloca. */
9640 /* We've reached end of stack frame. */
9643 /* Size prologue needs to allocate. */
9654 {
9660 }
9661 else
9665 /* The SEH frame pointer location is near the bottom of the frame.
9666 This is enforced by the fact that the difference between the
9667 stack pointer and the frame pointer is limited to 240 bytes in
9668 the unwind data structure. */
9670 {
9671 HOST_WIDE_INT diff;
9673 /* If we can leave the frame pointer where it is, do so. Also, returns
9674 the establisher frame for __builtin_frame_address (0). */
9679 {
9680 /* Ideally we'd determine what portion of the local stack frame
9681 (within the constraint of the lowest 240) is most heavily used.
9682 But without that complication, simply bias the frame pointer
9683 by 128 bytes so as to maximize the amount of the local stack
9684 frame that is addressable with 8-bit offsets. */
9686 }
9687 }
9688 }
9690 /* This is semi-inlined memory_address_length, but simplified
9691 since we know that we're always dealing with reg+offset, and
9692 to avoid having to create and discard all that rtl. */
9696 {
9700 {
9701 /* EBP and R13 cannot be encoded without an offset. */
9703 }
9707 /* ESP and R12 must be encoded with a SIB byte. */
9709 len++;
9712 }
9714 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9715 The valid base registers are taken from CFUN->MACHINE->FS. */
9717 static rtx
9719 {
9725 {
9726 /* Choose the base register most likely to allow the most scheduling
9727 opportunities. Generally FP is valid throughout the function,
9728 while DRAP must be reloaded within the epilogue. But choose either
9729 over the SP due to increased encoding size. */
9732 {
9735 }
9737 {
9740 }
9742 {
9745 }
9746 }
9747 else
9748 {
9749 HOST_WIDE_INT toffset;
9752 /* Choose the base register with the smallest address encoding.
9753 With a tie, choose FP > DRAP > SP. */
9755 {
9759 }
9761 {
9765 {
9769 }
9770 }
9772 {
9776 {
9780 }
9781 }
9782 }
9786 }
9788 /* Emit code to save registers in the prologue. */
9790 static void
9792 {
9794 rtx insn;
9798 {
9801 }
9802 }
9804 /* Emit a single register save at CFA - CFA_OFFSET. */
9806 static void
9808 HOST_WIDE_INT cfa_offset)
9809 {
9817 /* For SSE saves, we need to indicate the 128-bit alignment. */
9828 /* When saving registers into a re-aligned local stack frame, avoid
9829 any tricky guessing by dwarf2out. */
9831 {
9835 {
9836 /* A bit of a hack. We force the DRAP register to be saved in
9837 the re-aligned stack frame, which provides us with a copy
9838 of the CFA that will last past the prologue. Install it. */
9844 }
9845 else
9846 {
9847 /* The frame pointer is a stable reference within the
9848 aligned frame. Use it. */
9855 }
9856 }
9858 /* The memory may not be relative to the current CFA register,
9859 which means that we may need to generate a new pattern for
9860 use by the unwind info. */
9862 {
9867 }
9868 }
9870 /* Emit code to save registers using MOV insns.
9871 First register is stored at CFA - CFA_OFFSET. */
9872 static void
9874 {
9879 {
9882 }
9883 }
9885 /* Emit code to save SSE registers using MOV insns.
9886 First register is stored at CFA - CFA_OFFSET. */
9887 static void
9889 {
9894 {
9897 }
9898 }
9902 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9903 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9904 Don't add the note if the previously saved value will be left untouched
9905 within stack red-zone till return, as unwinders can find the same value
9906 in the register and on the stack. */
9908 static void
9910 {
9916 {
9919 }
9920 else
9921 queued_cfa_restores
9923 }
9925 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9927 static void
9929 {
9930 rtx last;
9934 ;
9939 }
9941 /* Expand prologue or epilogue stack adjustment.
9942 The pattern exist to put a dependency on all ebp-based memory accesses.
9943 STYLE should be negative if instructions should be marked as frame related,
9944 zero if %r11 register is live and cannot be freely used and positive
9945 otherwise. */
9947 static void
9950 {
9952 rtx insn;
9959 else
9960 {
9961 rtx tmp;
9962 /* r11 is used by indirect sibcall return as well, set before the
9963 epilogue and used after the epilogue. */
9966 else
9967 {
9971 }
9977 }
9984 {
9985 rtx r;
9995 }
9997 {
10000 {
10004 }
10005 }
10008 {
10013 {
10016 }
10018 {
10021 }
10022 else
10023 {
10024 /* Else there are two possibilities: SP itself, which we set
10025 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10026 taken care of this by hand along the eh_return path. */
10029 }
10033 }
10034 }
10036 /* Find an available register to be used as dynamic realign argument
10037 pointer regsiter. Such a register will be written in prologue and
10038 used in begin of body, so it must not be
10039 1. parameter passing register.
10040 2. GOT pointer.
10041 We reuse static-chain register if it is available. Otherwise, we
10042 use DI for i386 and R13 for x86-64. We chose R13 since it has
10043 shorter encoding.
10045 Return: the regno of chosen register. */
10047 static unsigned int
10049 {
10053 {
10054 /* Use R13 for nested function or function need static chain.
10055 Since function with tail call may use any caller-saved
10056 registers in epilogue, DRAP must not use caller-saved
10057 register in such case. */
10062 }
10063 else
10064 {
10065 /* Use DI for nested function or function need static chain.
10066 Since function with tail call may use any caller-saved
10067 registers in epilogue, DRAP must not use caller-saved
10068 register in such case. */
10072 /* Reuse static chain register if it isn't used for parameter
10073 passing. */
10075 {
10079 }
10081 }
10082 }
10084 /* Return minimum incoming stack alignment. */
10086 static unsigned int
10088 {
10091 /* Prefer the one specified at command line. */
10094 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10095 if -mstackrealign is used, it isn't used for sibcall check and
10096 estimated stack alignment is 128bit. */
10098 && !TARGET_64BIT
10099 && ix86_force_align_arg_pointer
10102 else
10105 /* Incoming stack alignment can be changed on individual functions
10106 via force_align_arg_pointer attribute. We use the smallest
10107 incoming stack boundary. */
10113 /* The incoming stack frame has to be aligned at least at
10114 parm_stack_boundary. */
10118 /* Stack at entrance of main is aligned by runtime. We use the
10119 smallest incoming stack boundary. */
10127 }
10129 /* Update incoming stack boundary and estimated stack alignment. */
10131 static void
10133 {
10134 ix86_incoming_stack_boundary
10137 /* x86_64 vararg needs 16byte stack alignment for register save
10138 area. */
10143 }
10145 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10146 needed or an rtx for DRAP otherwise. */
10148 static rtx
10150 {
10155 {
10156 /* Assign DRAP to vDRAP and returns vDRAP */
10158 rtx drap_vreg;
10159 rtx arg_ptr;
10172 {
10175 }
10177 }
10178 else
10180 }
10182 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10184 static rtx
10186 {
10188 }
10191 rtx reg;
10193 };
10195 /* Return a short-lived scratch register for use on function entry.
10196 In 32-bit mode, it is valid only after the registers are saved
10197 in the prologue. This register must be released by means of
10198 release_scratch_register_on_entry once it is dead. */
10200 static void
10202 {
10208 {
10209 /* We always use R11 in 64-bit mode. */
10211 }
10212 else
10213 {
10215 bool fastcall_p
10217 bool thiscall_p
10221 int drap_regno
10224 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10225 for the static chain register. */
10229 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10230 for the static chain register. */
10235 /* ecx is the static chain register. */
10237 && !static_chain_p
10242 /* esi is the static chain register. */
10248 else
10249 {
10252 }
10253 }
10257 {
10260 }
10261 }
10263 /* Release a scratch register obtained from the preceding function. */
10265 static void
10267 {
10269 {
10273 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10279 }
10280 }
10282 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10284 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10286 static void
10288 {
10289 /* We skip the probe for the first interval + a small dope of 4 words and
10290 probe that many bytes past the specified size to maintain a protection
10291 area at the botton of the stack. */
10295 /* See if we have a constant small number of probes to generate. If so,
10296 that's the easy case. The run-time loop is made up of 11 insns in the
10297 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10298 for n # of intervals. */
10300 {
10304 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10305 values of N from 1 until it exceeds SIZE. If only one probe is
10306 needed, this will not generate any code. Then adjust and probe
10307 to PROBE_INTERVAL + SIZE. */
10309 {
10311 {
10314 }
10315 else
10322 }
10326 else
10334 /* Adjust back to account for the additional first interval. */
10338 }
10340 /* Otherwise, do the same as above, but in a loop. Note that we must be
10341 extra careful with variables wrapping around because we might be at
10342 the very top (or the very bottom) of the address space and we have
10343 to be able to handle this case properly; in particular, we use an
10344 equality test for the loop condition. */
10345 else
10346 {
10347 HOST_WIDE_INT rounded_size;
10353 /* Step 1: round SIZE to the previous multiple of the interval. */
10358 /* Step 2: compute initial and final value of the loop counter. */
10360 /* SP = SP_0 + PROBE_INTERVAL. */
10365 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10369 stack_pointer_rtx)));
10372 /* Step 3: the loop
10374 while (SP != LAST_ADDR)
10375 {
10376 SP = SP + PROBE_INTERVAL
10377 probe at SP
10378 }
10380 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10381 values of N from 1 until it is equal to ROUNDED_SIZE. */
10386 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10387 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10390 {
10395 }
10397 /* Adjust back to account for the additional first interval. */
10403 }
10407 /* Even if the stack pointer isn't the CFA register, we need to correctly
10408 describe the adjustments made to it, in particular differentiate the
10409 frame-related ones from the frame-unrelated ones. */
10411 {
10424 }
10426 /* Make sure nothing is scheduled before we are done. */
10428 }
10430 /* Adjust the stack pointer up to REG while probing it. */
10434 {
10444 /* Jump to END_LAB if SP == LAST_ADDR. */
10452 /* SP = SP + PROBE_INTERVAL. */
10456 /* Probe at SP. */
10467 }
10469 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10470 inclusive. These are offsets from the current stack pointer. */
10472 static void
10474 {
10475 /* See if we have a constant small number of probes to generate. If so,
10476 that's the easy case. The run-time loop is made up of 7 insns in the
10477 generic case while the compile-time loop is made up of n insns for n #
10478 of intervals. */
10480 {
10481 HOST_WIDE_INT i;
10483 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10484 it exceeds SIZE. If only one probe is needed, this will not
10485 generate any code. Then probe at FIRST + SIZE. */
10492 }
10494 /* Otherwise, do the same as above, but in a loop. Note that we must be
10495 extra careful with variables wrapping around because we might be at
10496 the very top (or the very bottom) of the address space and we have
10497 to be able to handle this case properly; in particular, we use an
10498 equality test for the loop condition. */
10499 else
10500 {
10507 /* Step 1: round SIZE to the previous multiple of the interval. */
10512 /* Step 2: compute initial and final value of the loop counter. */
10514 /* TEST_OFFSET = FIRST. */
10517 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10521 /* Step 3: the loop
10523 while (TEST_ADDR != LAST_ADDR)
10524 {
10525 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10526 probe at TEST_ADDR
10527 }
10529 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10530 until it is equal to ROUNDED_SIZE. */
10535 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10536 that SIZE is equal to ROUNDED_SIZE. */
10541 stack_pointer_rtx,
10546 }
10548 /* Make sure nothing is scheduled before we are done. */
10550 }
10552 /* Probe a range of stack addresses from REG to END, inclusive. These are
10553 offsets from the current stack pointer. */
10557 {
10567 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10575 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10579 /* Probe at TEST_ADDR. */
10592 }
10594 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10595 to be generated in correct form. */
10596 static void
10598 {
10599 /* Check if stack realign is really needed after reload, and
10600 stores result in cfun */
10601 unsigned int incoming_stack_boundary
10610 {
10611 /* After stack_realign_needed is finalized, we can't no longer
10612 change it. */
10615 }
10617 /* If the only reason for frame_pointer_needed is that we conservatively
10618 assumed stack realignment might be needed, but in the end nothing that
10619 needed the stack alignment had been spilled, clear frame_pointer_needed
10620 and say we don't need stack realignment. */
10622 && frame_pointer_needed
10624 && flag_omit_frame_pointer
10626 && !ix86_current_function_calls_tls_descriptor
10635 {
10637 basic_block bb;
10644 HARD_FRAME_POINTER_REGNUM);
10646 {
10647 rtx insn;
10651 set_up_by_prologue))
10652 {
10656 }
10657 }
10659 /* If drap has been set, but it actually isn't live at the start
10660 of the function, there is no reason to set it up. */
10662 {
10665 {
10668 }
10669 }
10670 else
10685 }
10689 }
10691 /* Expand the prologue into a bunch of separate insns. */
10693 void
10695 {
10700 HOST_WIDE_INT allocate;
10706 /* DRAP should not coexist with stack_realign_fp */
10711 /* Initialize CFA state for before the prologue. */
10715 /* Track SP offset to the CFA. We continue tracking this after we've
10716 swapped the CFA register away from SP. In the case of re-alignment
10717 this is fudged; we're interested to offsets within the local frame. */
10724 {
10725 /* We should have already generated an error for any use of
10726 ms_hook on a nested function. */
10729 /* Check if profiling is active and we shall use profiling before
10730 prologue variant. If so sorry. */
10735 /* In ix86_asm_output_function_label we emitted:
10736 8b ff movl.s %edi,%edi
10737 55 push %ebp
10738 8b ec movl.s %esp,%ebp
10740 This matches the hookable function prologue in Win32 API
10741 functions in Microsoft Windows XP Service Pack 2 and newer.
10742 Wine uses this to enable Windows apps to hook the Win32 API
10743 functions provided by Wine.
10745 What that means is that we've already set up the frame pointer. */
10749 {
10752 /* We've decided to use the frame pointer already set up.
10753 Describe this to the unwinder by pretending that both
10754 push and mov insns happen right here.
10756 Putting the unwind info here at the end of the ms_hook
10757 is done so that we can make absolutely certain we get
10758 the required byte sequence at the start of the function,
10759 rather than relying on an assembler that can produce
10760 the exact encoding required.
10762 However it does mean (in the unpatched case) that we have
10763 a 1 insn window where the asynchronous unwind info is
10764 incorrect. However, if we placed the unwind info at
10765 its correct location we would have incorrect unwind info
10766 in the patched case. Which is probably all moot since
10767 I don't expect Wine generates dwarf2 unwind info for the
10768 system libraries that use this feature. */
10774 stack_pointer_rtx);
10782 /* Note that gen_push incremented m->fs.cfa_offset, even
10783 though we didn't emit the push insn here. */
10787 }
10788 else
10789 {
10790 /* The frame pointer is not needed so pop %ebp again.
10791 This leaves us with a pristine state. */
10793 }
10794 }
10796 /* The first insn of a function that accepts its static chain on the
10797 stack is to push the register that would be filled in by a direct
10798 call. This insn will be skipped by the trampoline. */
10800 {
10804 /* We don't want to interpret this push insn as a register save,
10805 only as a stack adjustment. The real copy of the register as
10806 a save will be done later, if needed. */
10811 }
10813 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10814 of DRAP is needed and stack realignment is really needed after reload */
10816 {
10819 /* Only need to push parameter pointer reg if it is caller saved. */
10821 {
10822 /* Push arg pointer reg */
10825 }
10827 /* Grab the argument pointer. */
10834 /* Align the stack. */
10836 stack_pointer_rtx,
10840 /* Replicate the return address on the stack so that return
10841 address can be reached via (argp - 1) slot. This is needed
10842 to implement macro RETURN_ADDR_RTX and intrinsic function
10843 expand_builtin_return_addr etc. */
10849 /* For the purposes of frame and register save area addressing,
10850 we've started over with a new frame. */
10853 }
10859 {
10860 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10861 slower on all targets. Also sdb doesn't like it. */
10865 /* Push registers now, before setting the frame pointer
10866 on SEH target. */
10868 && TARGET_SEH
10870 {
10874 }
10877 {
10885 }
10886 }
10889 {
10890 /* If saving registers via PUSH, do so now. */
10892 {
10896 }
10898 /* When using red zone we may start register saving before allocating
10899 the stack frame saving one cycle of the prologue. However, avoid
10900 doing this if we have to probe the stack; at least on x86_64 the
10901 stack probe can turn into a call that clobbers a red zone location. */
10903 && (! TARGET_STACK_PROBE
10905 {
10908 }
10909 }
10912 {
10916 /* The computation of the size of the re-aligned stack frame means
10917 that we must allocate the size of the register save area before
10918 performing the actual alignment. Otherwise we cannot guarantee
10919 that there's enough storage above the realignment point. */
10926 /* Align the stack. */
10928 stack_pointer_rtx,
10931 /* For the purposes of register save area addressing, the stack
10932 pointer is no longer valid. As for the value of sp_offset,
10933 see ix86_compute_frame_layout, which we need to match in order
10934 to pass verification of stack_pointer_offset at the end. */
10937 }
10942 {
10943 /* We start to count from ARG_POINTER. */
10946 /* If it was realigned, take into account the fake frame. */
10948 {
10955 /* This over-estimates by 1 minimal-stack-alignment-unit but
10956 mitigates that by counting in the new return address slot. */
10957 current_function_dynamic_stack_size
10959 }
10962 }
10964 /* On SEH target with very large frame size, allocate an area to save
10965 SSE registers (as the very large allocation won't be described). */
10969 {
10970 HOST_WIDE_INT sse_size =
10975 /* No need to do stack checking as the area will be immediately
10976 written. */
10983 }
10985 /* The stack has already been decremented by the instruction calling us
10986 so probe if the size is non-negative to preserve the protection area. */
10988 {
10989 /* We expect the registers to be saved when probes are used. */
10993 {
10996 {
10999 }
11000 }
11001 else
11002 {
11009 {
11011 {
11014 }
11015 else
11017 }
11018 else
11019 {
11021 {
11025 }
11026 else
11028 }
11029 }
11030 }
11033 ;
11036 {
11040 }
11041 else
11042 {
11054 {
11057 /* Note that SEH directives need to continue tracking the stack
11058 pointer even after the frame pointer has been set up. */
11060 {
11064 }
11065 }
11068 {
11073 {
11077 }
11078 }
11083 /* Use the fact that AX still contains ALLOCATE. */
11085 ? gen_pro_epilogue_adjust_stack_di_sub
11092 {
11100 }
11103 /* Use stack_pointer_rtx for relative addressing so that code
11104 works for realigned stack, too. */
11106 {
11113 }
11115 {
11120 }
11121 }
11124 /* If we havn't already set up the frame pointer, do so now. */
11126 {
11138 }
11146 /* We don't use pic-register for pe-coff target. */
11148 && !TARGET_PECOFF
11151 {
11158 }
11161 {
11163 {
11165 {
11175 label));
11179 }
11180 else
11182 }
11183 else
11184 {
11188 }
11189 }
11191 /* In the pic_reg_used case, make sure that the got load isn't deleted
11192 when mcount needs it. Blockage to avoid call movement across mcount
11193 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
11194 note. */
11199 {
11200 /* vDRAP is setup but after reload it turns out stack realign
11201 isn't necessary, here we will emit prologue to setup DRAP
11202 without stack realign adjustment */
11205 }
11207 /* Prevent instructions from being scheduled into register save push
11208 sequence when access to the redzone area is done through frame pointer.
11209 The offset between the frame pointer and the stack pointer is calculated
11210 relative to the value of the stack pointer at the end of the function
11211 prologue, and moving instructions that access redzone area via frame
11212 pointer inside push sequence violates this assumption. */
11216 /* Emit cld instruction if stringops are used in the function. */
11220 /* SEH requires that the prologue end within 256 bytes of the start of
11221 the function. Prevent instruction schedules that would extend that.
11222 Further, prevent alloca modifications to the stack pointer from being
11223 combined with prologue modifications. */
11226 }
11228 /* Emit code to restore REG using a POP insn. */
11230 static void
11232 {
11241 {
11242 /* Previously we'd represented the CFA as an expression
11243 like *(%ebp - 8). We've just popped that value from
11244 the stack, which means we need to reset the CFA to
11245 the drap register. This will remain until we restore
11246 the stack pointer. */
11250 /* This means that the DRAP register is valid for addressing too. */
11253 }
11256 {
11263 }
11265 /* When the frame pointer is the CFA, and we pop it, we are
11266 swapping back to the stack pointer as the CFA. This happens
11267 for stack frames that don't allocate other data, so we assume
11268 the stack pointer is now pointing at the return address, i.e.
11269 the function entry state, which makes the offset be 1 word. */
11271 {
11274 {
11282 }
11283 }
11284 }
11286 /* Emit code to restore saved registers using POP insns. */
11288 static void
11290 {
11296 }
11298 /* Emit code and notes for the LEAVE instruction. */
11300 static void
11302 {
11314 {
11322 }
11325 }
11327 /* Emit code to restore saved registers using MOV insns.
11328 First register is restored from CFA - CFA_OFFSET. */
11329 static void
11332 {
11338 {
11347 {
11348 /* Previously we'd represented the CFA as an expression
11349 like *(%ebp - 8). We've just popped that value from
11350 the stack, which means we need to reset the CFA to
11351 the drap register. This will remain until we restore
11352 the stack pointer. */
11356 /* This means that the DRAP register is valid for addressing. */
11358 }
11359 else
11363 }
11364 }
11366 /* Emit code to restore saved registers using MOV insns.
11367 First register is restored from CFA - CFA_OFFSET. */
11368 static void
11371 {
11376 {
11378 rtx mem;
11388 }
11389 }
11391 /* Restore function stack, frame, and registers. */
11393 void
11395 {
11411 /* The FP must be valid if the frame pointer is present. */
11416 /* We must have *some* valid pointer to the stack frame. */
11419 /* The DRAP is never valid at this point. */
11422 /* See the comment about red zone and frame
11423 pointer usage in ix86_expand_prologue. */
11430 /* Determine the CFA offset of the end of the red-zone. */
11433 {
11434 /* The red-zone begins below the return address. */
11437 /* When the register save area is in the aligned portion of
11438 the stack, determine the maximum runtime displacement that
11439 matches up with the aligned frame. */
11443 }
11445 /* Special care must be taken for the normal return case of a function
11446 using eh_return: the eax and edx registers are marked as saved, but
11447 not restored along this path. Adjust the save location to match. */
11451 /* EH_RETURN requires the use of moves to function properly. */
11454 /* SEH requires the use of pops to identify the epilogue. */
11457 /* If we're only restoring one register and sp is not valid then
11458 using a move instruction to restore the register since it's
11459 less work than reloading sp and popping the register. */
11472 && TARGET_USE_LEAVE
11476 else
11480 {
11481 /* Ensure that the entire register save area is addressable via
11482 the stack pointer, if we will restore via sp. */
11487 {
11491 style,
11493 }
11494 }
11496 /* If there are any SSE registers to restore, then we have to do it
11497 via moves, since there's obviously no pop for SSE regs. */
11503 {
11504 rtx t;
11509 /* eh_return epilogues need %ecx added to the stack pointer. */
11511 {
11514 /* Stack align doesn't work with eh_return. */
11516 /* Neither does regparm nested functions. */
11520 {
11528 /* Note that we use SA as a temporary CFA, as the return
11529 address is at the proper place relative to it. We
11530 pretend this happens at the FP restore insn because
11531 prior to this insn the FP would be stored at the wrong
11532 offset relative to SA, and after this insn we have no
11533 other reasonable register to use for the CFA. We don't
11534 bother resetting the CFA to the SP for the duration of
11535 the return insn. */
11548 }
11549 else
11550 {
11558 {
11562 UNITS_PER_WORD));
11564 }
11565 }
11568 }
11569 }
11570 else
11571 {
11572 /* SEH requires that the function end with (1) a stack adjustment
11573 if necessary, (2) a sequence of pops, and (3) a return or
11574 jump instruction. Prevent insns from the function body from
11575 being scheduled into this sequence. */
11577 {
11578 /* Prevent a catch region from being adjacent to the standard
11579 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11580 several other flags that would be interesting to test are
11581 not yet set up. */
11584 else
11586 }
11588 /* First step is to deallocate the stack frame so that we can
11589 pop the registers. Also do it on SEH target for very large
11590 frame as the emitted instructions aren't allowed by the ABI in
11591 epilogues. */
11593 || (TARGET_SEH
11596 {
11601 }
11603 {
11607 style,
11609 }
11612 }
11614 /* If we used a stack pointer and haven't already got rid of it,
11615 then do so now. */
11617 {
11618 /* If the stack pointer is valid and pointing at the frame
11619 pointer store address, then we only need a pop. */
11622 /* Leave results in shorter dependency chains on CPUs that are
11623 able to grok it fast. */
11628 else
11629 {
11631 hard_frame_pointer_rtx,
11634 }
11635 }
11638 {
11640 rtx insn;
11666 }
11668 /* At this point the stack pointer must be valid, and we must have
11669 restored all of the registers. We may not have deallocated the
11670 entire stack frame. We've delayed this until now because it may
11671 be possible to merge the local stack deallocation with the
11672 deallocation forced by ix86_static_chain_on_stack. */
11677 {
11681 }
11682 else
11685 /* Sibcall epilogues don't want a return instruction. */
11687 {
11690 }
11693 {
11696 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11697 address, do explicit add, and jump indirectly to the caller. */
11700 {
11702 rtx insn;
11704 /* There is no "pascal" calling convention in any 64bit ABI. */
11720 }
11721 else
11723 }
11724 else
11727 /* Restore the state back to the state from the prologue,
11728 so that it's correct for the next epilogue. */
11730 }
11732 /* Reset from the function's potential modifications. */
11734 static void
11736 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11737 {
11740 #if TARGET_MACHO
11741 /* Mach-O doesn't support labels at the end of objects, so if
11742 it looks like we might want one, insert a NOP. */
11743 {
11749 {
11750 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11751 notes only, instead set their CODE_LABEL_NUMBER to -1,
11752 otherwise there would be code generation differences
11753 in between -g and -g0. */
11757 }
11767 }
11768 #endif
11770 }
11772 /* Return a scratch register to use in the split stack prologue. The
11773 split stack prologue is used for -fsplit-stack. It is the first
11774 instructions in the function, even before the regular prologue.
11775 The scratch register can be any caller-saved register which is not
11776 used for parameters or for the static chain. */
11778 static unsigned int
11780 {
11783 else
11784 {
11797 {
11799 {
11803 }
11805 }
11807 {
11811 }
11813 {
11816 else
11817 {
11819 {
11823 }
11825 }
11826 }
11827 else
11828 {
11829 /* FIXME: We could make this work by pushing a register
11830 around the addition and comparison. */
11833 }
11834 }
11835 }
11837 /* A SYMBOL_REF for the function which allocates new stackspace for
11838 -fsplit-stack. */
11842 /* A SYMBOL_REF for the more stack function when using the large
11843 model. */
11847 /* Handle -fsplit-stack. These are the first instructions in the
11848 function, even before the regular prologue. */
11850 void
11852 {
11854 HOST_WIDE_INT allocate;
11859 rtx fn;
11867 /* This is the label we will branch to if we have enough stack
11868 space. We expect the basic block reordering pass to reverse this
11869 branch if optimizing, so that we branch in the unlikely case. */
11872 /* We need to compare the stack pointer minus the frame size with
11873 the stack boundary in the TCB. The stack boundary always gives
11874 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11875 can compare directly. Otherwise we need to do an addition. */
11878 UNSPEC_STACK_CHECK);
11883 else
11884 {
11886 rtx offset;
11888 /* We need a scratch register to hold the stack pointer minus
11889 the required frame size. Since this is the very start of the
11890 function, the scratch register can be any caller-saved
11891 register which is not used for parameters. */
11898 {
11899 /* We don't use ix86_gen_add3 in this case because it will
11900 want to split to lea, but when not optimizing the insn
11901 will not be split after this point. */
11904 offset)));
11905 }
11906 else
11907 {
11910 stack_pointer_rtx));
11911 }
11913 }
11919 /* Mark the jump as very likely to be taken. */
11927 /* Get more stack space. We pass in the desired stack space and the
11928 size of the arguments to copy to the new stack. In 32-bit mode
11929 we push the parameters; __morestack will return on a new stack
11930 anyhow. In 64-bit mode we pass the parameters in r10 and
11931 r11. */
11936 {
11942 /* If this function uses a static chain, it will be in %r10.
11943 Preserve it across the call to __morestack. */
11945 {
11946 rtx rax;
11951 }
11955 {
11956 HOST_WIDE_INT argval;
11959 /* When using the large model we need to load the address
11960 into a register, and we've run out of registers. So we
11961 switch to a different calling convention, and we call a
11962 different function: __morestack_large. We pass the
11963 argument size in the upper 32 bits of r10 and pass the
11964 frame size in the lower 32 bits. */
11969 split_stack_fn_large =
11973 {
11983 UNSPEC_GOT);
11989 }
11990 else
11997 }
11998 else
11999 {
12003 }
12006 }
12007 else
12008 {
12011 }
12017 /* In order to make call/return prediction work right, we now need
12018 to execute a return instruction. See
12019 libgcc/config/i386/morestack.S for the details on how this works.
12021 For flow purposes gcc must not see this as a return
12022 instruction--we need control flow to continue at the subsequent
12023 label. Therefore, we use an unspec. */
12027 /* If we are in 64-bit mode and this function uses a static chain,
12028 we saved %r10 in %rax before calling _morestack. */
12033 /* If this function calls va_start, we need to store a pointer to
12034 the arguments on the old stack, because they may not have been
12035 all copied to the new stack. At this point the old stack can be
12036 found at the frame pointer value used by __morestack, because
12037 __morestack has set that up before calling back to us. Here we
12038 store that pointer in a scratch register, and in
12039 ix86_expand_prologue we store the scratch register in a stack
12040 slot. */
12042 {
12044 rtx frame_reg;
12051 /* 64-bit:
12052 fp -> old fp value
12053 return address within this function
12054 return address of caller of this function
12055 stack arguments
12056 So we add three words to get to the stack arguments.
12058 32-bit:
12059 fp -> old fp value
12060 return address within this function
12061 first argument to __morestack
12062 second argument to __morestack
12063 return address of caller of this function
12064 stack arguments
12065 So we add five words to get to the stack arguments.
12066 */
12077 }
12082 /* If this function calls va_start, we now have to set the scratch
12083 register for the case where we do not call __morestack. In this
12084 case we need to set it based on the stack pointer. */
12086 {
12093 }
12094 }
12096 /* We may have to tell the dataflow pass that the split stack prologue
12097 is initializing a scratch register. */
12099 static void
12101 {
12103 {
12106 }
12107 }
12108 \f
12109 /* Extract the parts of an RTL expression that is a valid memory address
12110 for an instruction. Return 0 if the structure of the address is
12111 grossly off. Return -1 if the address contains ASHIFT, so it is not
12112 strictly valid, but still used for computing length of lea instruction. */
12114 int
12116 {
12121 rtx tmp;
12125 /* Allow zero-extended SImode addresses,
12126 they will be emitted with addr32 prefix. */
12128 {
12131 {
12135 }
12138 {
12145 }
12146 }
12148 /* Allow SImode subregs of DImode addresses,
12149 they will be emitted with addr32 prefix. */
12151 {
12154 {
12158 }
12159 }
12164 {
12167 else
12169 }
12171 {
12176 do
12177 {
12182 }
12189 {
12192 {
12217 /* FALLTHRU */
12221 && TARGET_TLS_DIRECT_SEG_REFS
12224 else
12231 /* FALLTHRU */
12238 else
12253 }
12254 }
12255 }
12257 {
12260 }
12262 {
12263 /* We're called for lea too, which implements ashift on occasion. */
12273 }
12274 else
12278 {
12280 ;
12283 ;
12284 else
12286 }
12288 /* Extract the integral value of scale. */
12290 {
12294 }
12299 /* Avoid useless 0 displacement. */
12303 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12308 {
12309 rtx tmp;
12312 }
12314 /* Special case: %ebp cannot be encoded as a base without a displacement.
12315 Similarly %r13. */
12317 && base_reg
12326 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12327 Avoid this by transforming to [%esi+0].
12328 Reload calls address legitimization without cfun defined, so we need
12329 to test cfun for being non-NULL. */
12335 /* Special case: encode reg+reg instead of reg*2. */
12339 /* Special case: scaling cannot be encoded without base or displacement. */
12350 }
12351 \f
12352 /* Return cost of the memory address x.
12353 For i386, it is better to use a complex address than let gcc copy
12354 the address into a reg and make a new pseudo. But not if the address
12355 requires to two regs - that would mean more pseudos with longer
12356 lifetimes. */
12357 static int
12359 addr_space_t as ATTRIBUTE_UNUSED,
12361 {
12373 /* Attempt to minimize number of registers in the address. */
12379 cost++;
12386 cost++;
12388 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12389 since it's predecode logic can't detect the length of instructions
12390 and it degenerates to vector decoded. Increase cost of such
12391 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12392 to split such addresses or even refuse such addresses at all.
12394 Following addressing modes are affected:
12395 [base+scale*index]
12396 [scale*index+disp]
12397 [base+index]
12399 The first and last case may be avoidable by explicitly coding the zero in
12400 memory address, but I don't have AMD-K6 machine handy to check this
12401 theory. */
12410 }
12411 \f
12412 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12413 this is used for to form addresses to local data when -fPIC is in
12414 use. */
12416 static bool
12418 {
12421 }
12423 /* Determine if a given RTX is a valid constant. We already know this
12424 satisfies CONSTANT_P. */
12426 static bool
12428 {
12430 {
12435 {
12439 }
12444 /* Only some unspecs are valid as "constants". */
12447 {
12463 }
12465 /* We must have drilled down to a symbol. */
12470 /* FALLTHRU */
12473 /* TLS symbols are never valid. */
12477 /* DLLIMPORT symbols are never valid. */
12482 #if TARGET_MACHO
12483 /* mdynamic-no-pic */
12486 #endif
12502 }
12504 /* Otherwise we handle everything else in the move patterns. */
12506 }
12508 /* Determine if it's legal to put X into the constant pool. This
12509 is not possible for the address of thread-local symbols, which
12510 is checked above. */
12512 static bool
12514 {
12515 /* We can always put integral constants and vectors in memory. */
12517 {
12525 }
12527 }
12529 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
12530 otherwise zero. */
12532 static bool
12534 {
12540 }
12543 /* Nonzero if the constant value X is a legitimate general operand
12544 when generating PIC code. It is given that flag_pic is on and
12545 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12547 bool
12549 {
12550 rtx inner;
12553 {
12560 /* Only some unspecs are valid as "constants". */
12563 {
12576 }
12577 /* FALLTHRU */
12585 }
12586 }
12588 /* Determine if a given CONST RTX is a valid memory displacement
12589 in PIC mode. */
12591 bool
12593 {
12596 /* In 64bit mode we can allow direct addresses of symbols and labels
12597 when they are not dynamic symbols. */
12599 {
12603 {
12627 /* FALLTHRU */
12630 /* TLS references should always be enclosed in UNSPEC.
12631 The dllimported symbol needs always to be resolved. */
12637 {
12645 /* Function-symbols need to be resolved only for
12646 large-model.
12647 For the small-model we don't need to resolve anything
12648 here. */
12653 /* Non-external symbols don't need to be resolved for
12654 large, and medium-model. */
12659 }
12668 }
12669 }
12675 {
12676 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12677 of GOT tables. We should not need these anyway. */
12689 }
12693 {
12698 }
12707 {
12711 /* We need to check for both symbols and labels because VxWorks loads
12712 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12713 details. */
12717 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12718 While ABI specify also 32bit relocation but we don't produce it in
12719 small PIC model at all. */
12741 }
12744 }
12746 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12747 replace the input X, or the original X if no replacement is called for.
12748 The output parameter *WIN is 1 if the calling macro should goto WIN,
12749 0 if it should not. */
12751 bool
12756 {
12757 /* Reload can generate:
12759 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12760 (reg:DI 97))
12761 (reg:DI 2 cx))
12763 This RTX is rejected from ix86_legitimate_address_p due to
12764 non-strictness of base register 97. Following this rejection,
12765 reload pushes all three components into separate registers,
12766 creating invalid memory address RTX.
12768 Following code reloads only the invalid part of the
12769 memory address RTX. */
12775 {
12781 {
12786 }
12790 {
12795 }
12799 }
12802 }
12804 /* Determine if op is suitable RTX for an address register.
12805 Return naked register if a register or a register subreg is
12806 found, otherwise return NULL_RTX. */
12808 static rtx
12810 {
12813 /* Only SImode or DImode registers can form the address. */
12820 {
12828 /* Don't allow SUBREGs that span more than a word. It can
12829 lead to spill failures when the register is one word out
12830 of a two word structure. */
12834 /* Allow only SUBREGs of non-eliminable hard registers. */
12837 }
12839 /* Op is not a register. */
12841 }
12843 /* Recognizes RTL expressions that are valid memory addresses for an
12844 instruction. The MODE argument is the machine mode for the MEM
12845 expression that wants to use this address.
12847 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12848 convert common non-canonical forms to canonical form so that they will
12849 be recognized. */
12851 static bool
12854 {
12857 HOST_WIDE_INT scale;
12861 /* Decomposition failed. */
12870 /* Validate base register. */
12872 {
12880 /* Base is not valid. */
12882 }
12884 /* Validate index register. */
12886 {
12894 /* Index is not valid. */
12896 }
12898 /* Index and base should have the same mode. */
12903 /* Address override works only on the (%reg) part of %fs:(%reg). */
12909 /* Validate scale factor. */
12911 {
12913 /* Scale without index. */
12917 /* Scale is not a valid multiplier. */
12919 }
12921 /* Validate displacement. */
12923 {
12928 {
12929 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12930 used. While ABI specify also 32bit relocations, we don't produce
12931 them at all and use IP relative instead. */
12938 /* 64bit address unspec. */
12958 /* Invalid address unspec. */
12960 }
12963 && (flag_pic
12964 || (TARGET_MACHO
12965 #if TARGET_MACHO
12966 && MACHOPIC_INDIRECT
12968 #endif
12969 )))
12970 {
12972 is_legitimate_pic:
12974 {
12975 /* foo@dtpoff(%rX) is ok. */
12982 /* Non-constant pic memory reference. */
12984 }
12987 /* Displacement is an invalid pic construct. */
12989 #if TARGET_MACHO
12992 /* displacment must be referenced via non_lazy_pointer */
12994 #endif
12996 /* This code used to verify that a symbolic pic displacement
12997 includes the pic_offset_table_rtx register.
12999 While this is good idea, unfortunately these constructs may
13000 be created by "adds using lea" optimization for incorrect
13001 code like:
13003 int a;
13004 int foo(int i)
13005 {
13006 return *(&a+i);
13007 }
13009 This code is nonsensical, but results in addressing
13010 GOT table with pic_offset_table_rtx base. We can't
13011 just refuse it easily, since it gets matched by
13012 "addsi3" pattern, that later gets split to lea in the
13013 case output register differs from input. While this
13014 can be handled by separate addsi pattern for this case
13015 that never results in lea, this seems to be easier and
13016 correct fix for crash to disable this test. */
13017 }
13024 /* Displacement is not constant. */
13028 /* Displacement is out of range. */
13030 /* In x32 mode, constant addresses are sign extended to 64bit, so
13031 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13036 }
13038 /* Everything looks valid. */
13040 }
13042 /* Determine if a given RTX is a valid constant address. */
13044 bool
13046 {
13048 }
13049 \f
13050 /* Return a unique alias set for the GOT. */
13052 static alias_set_type
13054 {
13059 }
13061 /* Return a legitimate reference for ORIG (an address) using the
13062 register REG. If REG is 0, a new pseudo is generated.
13064 There are two types of references that must be handled:
13066 1. Global data references must load the address from the GOT, via
13067 the PIC reg. An insn is emitted to do this load, and the reg is
13068 returned.
13070 2. Static data references, constant pool addresses, and code labels
13071 compute the address as an offset from the GOT, whose base is in
13072 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13073 differentiate them from global data objects. The returned
13074 address is the PIC reg + an unspec constant.
13076 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13077 reg also appears in the address. */
13079 static rtx
13081 {
13085 #if TARGET_MACHO
13087 {
13090 /* Use the generic Mach-O PIC machinery. */
13092 }
13093 #endif
13096 {
13100 }
13106 {
13107 rtx tmpreg;
13108 /* This symbol may be referenced via a displacement from the PIC
13109 base address (@GOTOFF). */
13116 {
13118 UNSPEC_GOTOFF);
13120 }
13121 else
13126 else
13131 {
13135 }
13136 else
13138 }
13140 {
13141 /* This symbol may be referenced via a displacement from the PIC
13142 base address (@GOTOFF). */
13149 {
13151 UNSPEC_GOTOFF);
13153 }
13154 else
13160 {
13163 }
13164 }
13166 /* We can't use @GOTOFF for text labels on VxWorks;
13167 see gotoff_operand. */
13169 {
13174 /* For x64 PE-COFF there is no GOT table. So we use address
13175 directly. */
13177 {
13185 }
13187 {
13195 /* Use directly gen_movsi, otherwise the address is loaded
13196 into register for CSE. We don't want to CSE this addresses,
13197 instead we CSE addresses from the GOT table, so skip this. */
13200 }
13201 else
13202 {
13203 /* This symbol must be referenced via a load from the
13204 Global Offset Table (@GOT). */
13220 }
13221 }
13222 else
13223 {
13226 {
13228 {
13231 }
13232 else
13234 }
13236 {
13239 /* We must match stuff we generate before. Assume the only
13240 unspecs that can get here are ours. Not that we could do
13241 anything with them anyway.... */
13247 }
13249 {
13252 /* Check first to see if this is a constant offset from a @GOTOFF
13253 symbol reference. */
13256 {
13258 {
13262 UNSPEC_GOTOFF);
13268 {
13271 }
13272 }
13273 else
13274 {
13277 {
13281 }
13282 }
13283 }
13284 else
13285 {
13288 new_rtx
13292 {
13295 {
13298 new_rtx
13300 }
13301 else
13303 }
13304 else
13305 {
13308 {
13311 }
13313 }
13314 }
13315 }
13316 }
13318 }
13319 \f
13320 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13322 static rtx
13324 {
13328 {
13333 }
13339 }
13341 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13345 static rtx
13347 {
13349 {
13355 }
13358 {
13360 UNSPEC_PLTOFF);
13363 }
13366 }
13368 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13372 rtx
13374 {
13376 {
13377 ix86_tls_module_base_symbol
13382 }
13385 }
13387 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13388 false if we expect this to be used for a memory address and true if
13389 we expect to load the address into a register. */
13391 static rtx
13393 {
13400 {
13405 {
13408 else
13409 {
13412 }
13413 }
13416 {
13419 else
13429 }
13430 else
13431 {
13435 {
13437 rtx insns;
13440 emit_call_insn
13450 }
13451 else
13453 }
13460 {
13463 else
13464 {
13467 }
13468 }
13471 {
13476 else
13482 }
13483 else
13484 {
13488 {
13493 emit_call_insn
13498 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
13499 share the LD_BASE result with other LD model accesses. */
13501 UNSPEC_TLS_LD_BASE);
13505 }
13506 else
13508 }
13516 {
13523 }
13528 {
13530 {
13531 /* The Sun linker took the AMD64 TLS spec literally
13532 and can only handle %rax as destination of the
13533 initial executable code sequence. */
13538 }
13540 /* Generate DImode references to avoid %fs:(%reg32)
13541 problems and linker IE->LE relaxation bug. */
13545 }
13547 {
13552 }
13554 {
13558 }
13559 else
13560 {
13563 }
13573 {
13578 }
13579 else
13580 {
13584 }
13594 {
13598 }
13599 else
13600 {
13604 }
13609 }
13612 }
13614 /* Create or return the unique __imp_DECL dllimport symbol corresponding
13615 to symbol DECL if BEIMPORT is true. Otherwise create or return the
13616 unique refptr-DECL symbol corresponding to symbol DECL. */
13619 htab_t dllimport_map;
13621 static tree
13623 {
13630 tree to;
13631 rtx rtl;
13658 else
13671 {
13673 #ifdef SUB_TARGET_RECORD_STUB
13675 #endif
13676 }
13685 }
13687 /* Expand SYMBOL into its corresponding far-addresse symbol.
13688 WANT_REG is true if we require the result be a register. */
13690 static rtx
13692 {
13693 tree imp_decl;
13694 rtx x;
13703 }
13705 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13706 true if we require the result be a register. */
13708 static rtx
13710 {
13711 tree imp_decl;
13712 rtx x;
13721 }
13723 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
13724 is true if we require the result be a register. */
13726 static rtx
13728 {
13733 {
13740 {
13743 }
13744 }
13760 {
13763 }
13765 }
13767 /* Try machine-dependent ways of modifying an illegitimate address
13768 to be legitimate. If we find one, return the new, valid address.
13769 This macro is used in only one place: `memory_address' in explow.c.
13771 OLDX is the address as it was before break_out_memory_refs was called.
13772 In some cases it is useful to look at this to decide what needs to be done.
13774 It is always safe for this macro to do nothing. It exists to recognize
13775 opportunities to optimize the output.
13777 For the 80386, we handle X+REG by loading X into a register R and
13778 using R+REG. R will go in a general reg and indexing will be used.
13779 However, if REG is a broken-out memory address or multiplication,
13780 nothing needs to be done because REG can certainly go in a general reg.
13782 When -fpic is used, special handling is needed for symbolic references.
13783 See comments by legitimize_pic_address in i386.c for details. */
13785 static rtx
13788 {
13799 {
13803 }
13806 {
13810 }
13815 #if TARGET_MACHO
13818 #endif
13820 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13824 {
13829 }
13832 {
13833 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13838 {
13844 }
13849 {
13855 }
13857 /* Put multiply first if it isn't already. */
13859 {
13864 }
13866 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13867 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13868 created by virtual register instantiation, register elimination, and
13869 similar optimizations. */
13871 {
13877 }
13879 /* Canonicalize
13880 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13881 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13886 {
13887 rtx constant;
13891 {
13894 }
13896 {
13899 }
13900 else
13904 {
13911 }
13912 }
13918 {
13921 }
13924 {
13927 }
13935 {
13938 }
13944 {
13948 {
13951 }
13955 }
13958 {
13962 {
13965 }
13969 }
13970 }
13973 }
13974 \f
13975 /* Print an integer constant expression in assembler syntax. Addition
13976 and subtraction are the only arithmetic that may appear in these
13977 expressions. FILE is the stdio stream to write to, X is the rtx, and
13978 CODE is the operand print code from the output string. */
13980 static void
13982 {
13986 {
13995 else
13996 {
13999 /* Mark the decl as referenced so that cgraph will
14000 output the function. */
14004 #if TARGET_MACHO
14008 #endif
14010 }
14018 /* FALLTHRU */
14029 /* This used to output parentheses around the expression,
14030 but that does not work on the 386 (either ATT or BSD assembler). */
14036 {
14037 /* We can use %d if the number is <32 bits and positive. */
14042 else
14044 }
14045 else
14046 /* We can't handle floating point constants;
14047 TARGET_PRINT_OPERAND must handle them. */
14052 /* Some assemblers need integer constants to appear first. */
14054 {
14058 }
14059 else
14060 {
14065 }
14080 {
14084 }
14089 {
14108 /* FIXME: This might be @TPOFF in Sun ld too. */
14117 else
14127 else
14133 #if TARGET_MACHO
14138 #endif
14142 }
14147 }
14148 }
14150 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14151 We need to emit DTP-relative relocations. */
14153 static void ATTRIBUTE_UNUSED
14155 {
14160 {
14168 }
14169 }
14171 /* Return true if X is a representation of the PIC register. This copes
14172 with calls from ix86_find_base_term, where the register might have
14173 been replaced by a cselib value. */
14175 static bool
14177 {
14181 else
14183 }
14185 /* Helper function for ix86_delegitimize_address.
14186 Attempt to delegitimize TLS local-exec accesses. */
14188 static rtx
14190 {
14215 {
14220 }
14226 }
14228 /* In the name of slightly smaller debug output, and to cater to
14229 general assembler lossage, recognize PIC+GOTOFF and turn it back
14230 into a direct symbol reference.
14232 On Darwin, this is necessary to avoid a crash, because Darwin
14233 has a different PIC label for each routine but the DWARF debugging
14234 information is not associated with any particular routine, so it's
14235 necessary to remove references to the PIC label from RTL stored by
14236 the DWARF output code. */
14238 static rtx
14240 {
14242 /* addend is NULL or some rtx if x is something+GOTOFF where
14243 something doesn't include the PIC register. */
14245 /* reg_addend is NULL or a multiple of some register. */
14247 /* const_addend is NULL or a const_int. */
14249 /* This is the result, or NULL. */
14258 {
14265 {
14271 }
14278 {
14281 {
14286 }
14288 }
14293 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14294 and -mcmodel=medium -fpic. */
14295 }
14302 /* %ebx + GOT/GOTOFF */
14303 ;
14305 {
14306 /* %ebx + %reg * scale + GOT/GOTOFF */
14312 else
14313 {
14316 }
14317 }
14318 else
14324 {
14327 }
14348 {
14349 /* If the rest of original X doesn't involve the PIC register, add
14350 addend and subtract pic_offset_table_rtx. This can happen e.g.
14351 for code like:
14352 leal (%ebx, %ecx, 4), %ecx
14353 ...
14354 movl foo@GOTOFF(%ecx), %edx
14355 in which case we return (%ecx - %ebx) + foo. */
14358 pic_offset_table_rtx),
14359 result);
14360 else
14362 }
14364 {
14368 }
14370 }
14372 /* If X is a machine specific address (i.e. a symbol or label being
14373 referenced as a displacement from the GOT implemented using an
14374 UNSPEC), then return the base term. Otherwise return X. */
14376 rtx
14378 {
14379 rtx term;
14382 {
14396 }
14399 }
14400 \f
14401 static void
14404 {
14408 {
14411 }
14416 {
14419 {
14438 }
14442 {
14461 }
14468 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
14469 Those same assemblers have the same but opposite lossage on cmov. */
14472 else
14477 {
14490 }
14497 else
14502 {
14515 }
14522 else
14532 else
14543 }
14545 }
14547 /* Print the name of register X to FILE based on its machine mode and number.
14548 If CODE is 'w', pretend the mode is HImode.
14549 If CODE is 'b', pretend the mode is QImode.
14550 If CODE is 'k', pretend the mode is SImode.
14551 If CODE is 'q', pretend the mode is DImode.
14552 If CODE is 'x', pretend the mode is V4SFmode.
14553 If CODE is 't', pretend the mode is V8SFmode.
14554 If CODE is 'g', pretend the mode is V16SFmode.
14555 If CODE is 'h', pretend the reg is the 'high' byte register.
14556 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
14557 If CODE is 'd', duplicate the operand for AVX instruction.
14558 */
14560 void
14562 {
14571 {
14575 }
14602 else
14605 /* Irritatingly, AMD extended registers use different naming convention
14606 from the normal registers: "r%d[bwd]" */
14608 {
14613 {
14627 /* no suffix */
14632 }
14634 }
14638 {
14641 {
14644 }
14645 /* FALLTHRU */
14651 /* FALLTHRU */
14654 normal:
14669 {
14674 }
14677 {
14682 }
14686 }
14690 {
14693 else
14695 }
14696 }
14698 /* Locate some local-dynamic symbol still in use by this function
14699 so that we can print its name in some tls_local_dynamic_base
14700 pattern. */
14702 static int
14704 {
14709 {
14712 }
14715 }
14719 {
14720 rtx insn;
14731 }
14733 /* Meaning of CODE:
14734 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14735 C -- print opcode suffix for set/cmov insn.
14736 c -- like C, but print reversed condition
14737 F,f -- likewise, but for floating-point.
14738 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14739 otherwise nothing
14740 R -- print embeded rounding and sae.
14741 r -- print only sae.
14742 z -- print the opcode suffix for the size of the current operand.
14743 Z -- likewise, with special suffixes for x87 instructions.
14744 * -- print a star (in certain assembler syntax)
14745 A -- print an absolute memory reference.
14746 E -- print address with DImode register names if TARGET_64BIT.
14747 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14748 s -- print a shift double count, followed by the assemblers argument
14749 delimiter.
14750 b -- print the QImode name of the register for the indicated operand.
14751 %b0 would print %al if operands[0] is reg 0.
14752 w -- likewise, print the HImode name of the register.
14753 k -- likewise, print the SImode name of the register.
14754 q -- likewise, print the DImode name of the register.
14755 x -- likewise, print the V4SFmode name of the register.
14756 t -- likewise, print the V8SFmode name of the register.
14757 g -- likewise, print the V16SFmode name of the register.
14758 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14759 y -- print "st(0)" instead of "st" as a register.
14760 d -- print duplicated register operand for AVX instruction.
14761 D -- print condition for SSE cmp instruction.
14762 P -- if PIC, print an @PLT suffix.
14763 p -- print raw symbol name.
14764 X -- don't print any sort of PIC '@' suffix for a symbol.
14765 & -- print some in-use local-dynamic symbol name.
14766 H -- print a memory address offset by 8; used for sse high-parts
14767 Y -- print condition for XOP pcom* instruction.
14768 + -- print a branch hint as 'cs' or 'ds' prefix
14769 ; -- print a semicolon (after prefixes due to bug in older gas).
14770 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14771 @ -- print a segment register of thread base pointer load
14772 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14773 */
14775 void
14777 {
14779 {
14781 {
14784 {
14790 /* Intel syntax. For absolute addresses, registers should not
14791 be surrounded by braces. */
14793 {
14798 }
14803 }
14809 /* Wrap address in an UNSPEC to declare special handling. */
14847 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14852 {
14866 output_operand_lossage
14869 }
14872 #endif
14877 {
14878 /* Opcodes don't get size suffixes if using Intel opcodes. */
14883 {
14901 output_operand_lossage
14904 }
14905 }
14908 warning
14910 /* FALLTHRU */
14913 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14918 {
14920 {
14922 #ifdef HAVE_AS_IX86_FILDS
14924 #endif
14932 #ifdef HAVE_AS_IX86_FILDQ
14934 #else
14936 #endif
14941 }
14942 }
14944 {
14945 /* 387 opcodes don't get size suffixes
14946 if the operands are registers. */
14951 {
14967 }
14968 }
14969 else
14970 {
14971 output_operand_lossage
14974 }
14976 output_operand_lossage
14997 {
15000 }
15005 {
15056 }
15060 /* Little bit of braindamage here. The SSE compare instructions
15061 does use completely different names for the comparisons that the
15062 fp conditional moves. */
15064 {
15067 {
15070 }
15076 {
15079 }
15085 {
15088 }
15097 {
15100 }
15106 {
15109 }
15115 {
15118 }
15129 }
15134 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15137 #endif
15142 {
15146 }
15150 file);
15155 {
15159 }
15160 /* It doesn't actually matter what mode we use here, as we're
15161 only going to use this for printing. */
15163 /* Output 'qword ptr' for intel assembler dialect. */
15172 #ifdef HAVE_AS_IX86_HLE
15174 #else
15176 #endif
15178 #ifdef HAVE_AS_IX86_HLE
15180 #else
15182 #endif
15183 /* We do not want to print value of the operand. */
15212 {
15227 }
15240 {
15245 else
15248 }
15251 {
15252 rtx x;
15261 {
15266 {
15268 bool cputaken
15271 /* Emit hints only in the case default branch prediction
15272 heuristics would fail. */
15274 {
15275 /* We use 3e (DS) prefix for taken branches and
15276 2e (CS) prefix for not taken branches. */
15279 else
15281 }
15282 }
15283 }
15285 }
15288 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15290 #endif
15297 /* The kernel uses a different segment register for performance
15298 reasons; a system call would not have to trash the userspace
15299 segment register, which would be expensive. */
15302 else
15317 }
15318 }
15324 {
15325 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15328 {
15331 {
15340 else
15347 }
15349 /* Check for explicit size override (codes 'b', 'w', 'k',
15350 'q' and 'x') */
15364 }
15367 /* Avoid (%rip) for call operands. */
15373 else
15375 }
15378 {
15379 REAL_VALUE_TYPE r;
15387 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15391 else
15393 }
15396 {
15397 REAL_VALUE_TYPE r;
15406 }
15408 /* These float cases don't actually occur as immediate operands. */
15410 {
15415 }
15417 else
15418 {
15419 /* We have patterns that allow zero sets of memory, for instance.
15420 In 64-bit mode, we should probably support all 8-byte vectors,
15421 since we can in fact encode that into an immediate. */
15423 {
15426 }
15429 {
15431 {
15434 }
15437 {
15440 else
15442 }
15443 }
15448 else
15450 }
15451 }
15453 static bool
15455 {
15458 }
15459 \f
15460 /* Print a memory operand whose address is ADDR. */
15462 static void
15464 {
15473 {
15480 }
15482 {
15486 }
15487 else
15498 {
15509 }
15511 /* Use one byte shorter RIP relative addressing for 64bit mode. */
15513 {
15525 }
15527 {
15528 /* Displacement only requires special attention. */
15531 {
15535 }
15538 else
15540 }
15541 else
15542 {
15543 /* Print SImode register names to force addr32 prefix. */
15545 {
15546 #ifdef ENABLE_CHECKING
15549 {
15560 }
15561 #endif
15564 }
15566 && TARGET_X32
15567 && disp
15570 {
15571 /* X32 runs in 64-bit mode, where displacement, DISP, in
15572 address DISP(%r64), is encoded as 32-bit immediate sign-
15573 extended from 32-bit to 64-bit. For -0x40000300(%r64),
15574 address is %r64 + 0xffffffffbffffd00. When %r64 <
15575 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
15576 which is invalid for x32. The correct address is %r64
15577 - 0x40000300 == 0xf7ffdd64. To properly encode
15578 -0x40000300(%r64) for x32, we zero-extend negative
15579 displacement by forcing addr32 prefix which truncates
15580 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
15581 zero-extend all negative displacements, including -1(%rsp).
15582 However, for small negative displacements, sign-extension
15583 won't cause overflow. We only zero-extend negative
15584 displacements if they < -16*1024*1024, which is also used
15585 to check legitimate address displacements for PIC. */
15587 }
15590 {
15592 {
15597 else
15599 }
15605 {
15610 }
15612 }
15613 else
15614 {
15618 {
15619 /* Pull out the offset of a symbol; print any symbol itself. */
15623 {
15627 }
15635 else
15637 }
15641 {
15644 {
15648 }
15649 }
15652 else
15656 {
15661 }
15663 }
15664 }
15665 }
15667 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
15669 static bool
15671 {
15672 rtx op;
15679 {
15682 /* FIXME: This might be @TPOFF in Sun ld. */
15693 else
15705 else
15712 #if TARGET_MACHO
15718 #endif
15721 {
15726 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
15728 #else
15730 #endif
15733 }
15738 }
15741 }
15742 \f
15743 /* Split one or more double-mode RTL references into pairs of half-mode
15744 references. The RTL can be REG, offsettable MEM, integer constant, or
15745 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
15746 split and "num" is its length. lo_half and hi_half are output arrays
15747 that parallel "operands". */
15749 void
15752 {
15757 {
15766 }
15771 {
15774 /* simplify_subreg refuse to split volatile memory addresses,
15775 but we still have to handle it. */
15777 {
15780 }
15781 else
15782 {
15789 }
15790 }
15791 }
15792 \f
15793 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15794 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15795 is the expression of the binary operation. The output may either be
15796 emitted here, or returned to the caller, like all output_* functions.
15798 There is no guarantee that the operands are the same mode, as they
15799 might be within FLOAT or FLOAT_EXTEND expressions. */
15801 #ifndef SYSV386_COMPAT
15802 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15803 wants to fix the assemblers because that causes incompatibility
15804 with gcc. No-one wants to fix gcc because that causes
15805 incompatibility with assemblers... You can use the option of
15806 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15807 #define SYSV386_COMPAT 1
15808 #endif
15812 {
15818 #ifdef ENABLE_CHECKING
15819 /* Even if we do not want to check the inputs, this documents input
15820 constraints. Which helps in understanding the following code. */
15830 else
15832 #endif
15835 {
15840 else
15849 else
15858 else
15867 else
15874 }
15877 {
15879 {
15883 else
15885 }
15886 else
15887 {
15891 else
15893 }
15895 }
15899 {
15903 {
15907 }
15909 /* know operands[0] == operands[1]. */
15912 {
15915 }
15918 {
15920 /* How is it that we are storing to a dead operand[2]?
15921 Well, presumably operands[1] is dead too. We can't
15922 store the result to st(0) as st(0) gets popped on this
15923 instruction. Instead store to operands[2] (which I
15924 think has to be st(1)). st(1) will be popped later.
15925 gcc <= 2.8.1 didn't have this check and generated
15926 assembly code that the Unixware assembler rejected. */
15928 else
15931 }
15935 else
15942 {
15945 }
15948 {
15951 }
15954 {
15955 #if SYSV386_COMPAT
15956 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
15957 derived assemblers, confusingly reverse the direction of
15958 the operation for fsub{r} and fdiv{r} when the
15959 destination register is not st(0). The Intel assembler
15960 doesn't have this brain damage. Read !SYSV386_COMPAT to
15961 figure out what the hardware really does. */
15964 else
15966 #else
15968 /* As above for fmul/fadd, we can't store to st(0). */
15970 else
15972 #endif
15974 }
15977 {
15978 #if SYSV386_COMPAT
15981 else
15983 #else
15986 else
15988 #endif
15990 }
15993 {
15996 else
15999 }
16001 {
16002 #if SYSV386_COMPAT
16004 #else
16006 #endif
16007 }
16008 else
16009 {
16010 #if SYSV386_COMPAT
16012 #else
16014 #endif
16015 }
16020 }
16024 }
16026 /* Check if a 256bit AVX register is referenced inside of EXP. */
16028 static int
16030 {
16041 }
16043 /* Return needed mode for entity in optimize_mode_switching pass. */
16045 static int
16047 {
16049 {
16050 rtx link;
16052 /* Needed mode is set to AVX_U128_CLEAN if there are
16053 no 256bit modes used in function arguments. */
16055 link;
16057 {
16059 {
16064 }
16065 }
16068 }
16070 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16071 changes state only when a 256bit register is written to, but we need
16072 to prevent the compiler from moving optimal insertion point above
16073 eventual read from 256bit register. */
16078 }
16080 /* Return mode that i387 must be switched into
16081 prior to the execution of insn. */
16083 static int
16085 {
16088 /* The mode UNINITIALIZED is used to store control word after a
16089 function call or ASM pattern. The mode ANY specify that function
16090 has no requirements on the control word and make no changes in the
16091 bits we are interested in. */
16105 {
16128 }
16131 }
16133 /* Return mode that entity must be switched into
16134 prior to the execution of insn. */
16136 int
16138 {
16140 {
16150 }
16152 }
16154 /* Check if a 256bit AVX register is referenced in stores. */
16156 static void
16158 {
16160 {
16163 }
16164 }
16166 /* Calculate mode of upper 128bit AVX registers after the insn. */
16168 static int
16170 {
16177 /* We know that state is clean after CALL insn if there are no
16178 256bit registers used in the function return register. */
16180 {
16185 }
16187 /* Otherwise, return current mode. Remember that if insn
16188 references AVX 256bit registers, the mode was already changed
16189 to DIRTY from MODE_NEEDED. */
16191 }
16193 /* Return the mode that an insn results in. */
16195 int
16197 {
16199 {
16209 }
16210 }
16212 static int
16214 {
16215 tree arg;
16217 /* Entry mode is set to AVX_U128_DIRTY if there are
16218 256bit modes used in function arguments. */
16221 {
16226 }
16229 }
16231 /* Return a mode that ENTITY is assumed to be
16232 switched to at function entry. */
16234 int
16236 {
16238 {
16248 }
16249 }
16251 static int
16253 {
16256 /* Exit mode is set to AVX_U128_DIRTY if there are
16257 256bit modes used in the function return register. */
16262 }
16264 /* Return a mode that ENTITY is assumed to be
16265 switched to at function exit. */
16267 int
16269 {
16271 {
16281 }
16282 }
16284 /* Output code to initialize control word copies used by trunc?f?i and
16285 rounding patterns. CURRENT_MODE is set to current control word,
16286 while NEW_MODE is set to new control word. */
16288 static void
16290 {
16292 rtx new_mode;
16303 {
16305 {
16307 /* round toward zero (truncate) */
16313 /* round down toward -oo */
16320 /* round up toward +oo */
16327 /* mask precision exception for nearbyint() */
16334 }
16335 }
16336 else
16337 {
16339 {
16341 /* round toward zero (truncate) */
16347 /* round down toward -oo */
16353 /* round up toward +oo */
16359 /* mask precision exception for nearbyint() */
16366 }
16367 }
16373 }
16375 /* Emit vzeroupper. */
16377 void
16379 {
16382 /* Cancel automatic vzeroupper insertion if there are
16383 live call-saved SSE registers at the insertion point. */
16395 }
16397 /* Generate one or more insns to set ENTITY to MODE. */
16399 void
16401 {
16403 {
16418 }
16419 }
16421 /* Output code for INSN to convert a float to a signed int. OPERANDS
16422 are the insn operands. The output may be [HSD]Imode and the input
16423 operand may be [SDX]Fmode. */
16427 {
16432 /* Jump through a hoop or two for DImode, since the hardware has no
16433 non-popping instruction. We used to do this a different way, but
16434 that was somewhat fragile and broke with post-reload splitters. */
16444 else
16445 {
16450 else
16454 }
16457 }
16459 /* Output code for x87 ffreep insn. The OPNO argument, which may only
16460 have the values zero or one, indicates the ffreep insn's operand
16461 from the OPERANDS array. */
16465 {
16467 #ifdef HAVE_AS_IX86_FFREEP
16469 #else
16470 {
16480 }
16481 #endif
16484 }
16487 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
16488 should be used. UNORDERED_P is true when fucom should be used. */
16492 {
16498 {
16501 }
16502 else
16503 {
16506 }
16509 {
16513 else
16515 else
16518 else
16520 }
16527 {
16529 {
16532 }
16533 else
16535 }
16538 && stack_top_dies
16541 {
16542 /* If both the top of the 387 stack dies, and the other operand
16543 is also a stack register that dies, then this must be a
16544 `fcompp' float compare */
16547 {
16548 /* There is no double popping fcomi variant. Fortunately,
16549 eflags is immune from the fstp's cc clobbering. */
16552 else
16555 }
16556 else
16557 {
16560 else
16562 }
16563 }
16564 else
16565 {
16566 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
16569 {
16577 NULL,
16578 NULL,
16585 NULL,
16586 NULL,
16587 NULL,
16588 NULL
16589 };
16604 }
16605 }
16607 void
16609 {
16612 #ifdef ASM_QUAD
16615 #else
16617 #endif
16620 }
16622 void
16624 {
16627 #ifdef ASM_QUAD
16630 #else
16632 #endif
16633 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
16639 #if TARGET_MACHO
16641 {
16645 }
16646 #endif
16647 else
16650 }
16651 \f
16652 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
16653 for the target. */
16655 void
16657 {
16658 rtx tmp;
16660 /* We play register width games, which are only valid after reload. */
16663 /* Avoid HImode and its attendant prefix byte. */
16668 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
16670 {
16673 }
16676 }
16678 /* X is an unchanging MEM. If it is a constant pool reference, return
16679 the constant pool rtx, else NULL. */
16681 rtx
16683 {
16690 }
16692 void
16694 {
16702 {
16703 rtx tmp;
16707 {
16713 }
16716 }
16720 {
16723 rtx tmp;
16728 else
16732 {
16739 }
16740 }
16744 {
16746 {
16747 #if TARGET_MACHO
16748 /* dynamic-no-pic */
16750 {
16751 rtx temp = ((reload_in_progress
16759 }
16761 {
16765 }
16768 else
16769 {
16777 }
16778 /* dynamic-no-pic */
16779 #endif
16780 }
16781 else
16782 {
16786 {
16792 }
16793 }
16794 }
16795 else
16796 {
16807 /* Force large constants in 64bit compilation into register
16808 to get them CSEed. */
16820 {
16821 /* If we are loading a floating point constant to a register,
16822 force the value to memory now, since we'll get better code
16823 out the back end. */
16827 {
16832 }
16833 }
16834 }
16837 }
16839 void
16841 {
16848 /* Force constants other than zero into memory. We do not know how
16849 the instructions used to build constants modify the upper 64 bits
16850 of the register, once we have that information we may be able
16851 to handle some of them more efficiently. */
16860 /* We need to check memory alignment for SSE mode since attribute
16861 can make operands unaligned. */
16866 {
16869 /* ix86_expand_vector_move_misalign() does not like constants ... */
16875 /* ... nor both arguments in memory. */
16883 }
16885 /* Make operand1 a register if it isn't already. */
16889 {
16892 }
16895 }
16897 /* Split 32-byte AVX unaligned load and store if needed. */
16899 static void
16901 {
16902 rtx m;
16909 {
16930 }
16933 {
16935 {
16942 }
16943 /* Normal *mov<mode>_internal pattern will handle
16944 unaligned loads just fine if misaligned_operand
16945 is true, and without the UNSPEC it can be combined
16946 with arithmetic instructions. */
16949 else
16951 }
16953 {
16955 {
16960 }
16961 else
16963 }
16964 else
16966 }
16968 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
16969 straight to ix86_expand_vector_move. */
16970 /* Code generation for scalar reg-reg moves of single and double precision data:
16971 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
16972 movaps reg, reg
16973 else
16974 movss reg, reg
16975 if (x86_sse_partial_reg_dependency == true)
16976 movapd reg, reg
16977 else
16978 movsd reg, reg
16980 Code generation for scalar loads of double precision data:
16981 if (x86_sse_split_regs == true)
16982 movlpd mem, reg (gas syntax)
16983 else
16984 movsd mem, reg
16986 Code generation for unaligned packed loads of single precision data
16987 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
16988 if (x86_sse_unaligned_move_optimal)
16989 movups mem, reg
16991 if (x86_sse_partial_reg_dependency == true)
16992 {
16993 xorps reg, reg
16994 movlps mem, reg
16995 movhps mem+8, reg
16996 }
16997 else
16998 {
16999 movlps mem, reg
17000 movhps mem+8, reg
17001 }
17003 Code generation for unaligned packed loads of double precision data
17004 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17005 if (x86_sse_unaligned_move_optimal)
17006 movupd mem, reg
17008 if (x86_sse_split_regs == true)
17009 {
17010 movlpd mem, reg
17011 movhpd mem+8, reg
17012 }
17013 else
17014 {
17015 movsd mem, reg
17016 movhpd mem+8, reg
17017 }
17018 */
17020 void
17022 {
17031 {
17033 {
17037 {
17039 {
17042 }
17043 else
17045 }
17047 /* FALLTHRU */
17051 {
17066 }
17072 else
17080 }
17083 }
17087 {
17089 {
17093 {
17095 {
17098 }
17099 else
17101 }
17103 /* FALLTHRU */
17113 }
17116 }
17119 {
17120 /* Normal *mov<mode>_internal pattern will handle
17121 unaligned loads just fine if misaligned_operand
17122 is true, and without the UNSPEC it can be combined
17123 with arithmetic instructions. */
17129 /* ??? If we have typed data, then it would appear that using
17130 movdqu is the only way to get unaligned data loaded with
17131 integer type. */
17133 {
17135 {
17138 }
17140 /* We will eventually emit movups based on insn attributes. */
17144 }
17146 {
17147 rtx zero;
17150 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17151 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17153 {
17154 /* We will eventually emit movups based on insn attributes. */
17157 }
17159 /* When SSE registers are split into halves, we can avoid
17160 writing to the top half twice. */
17162 {
17165 }
17166 else
17167 {
17168 /* ??? Not sure about the best option for the Intel chips.
17169 The following would seem to satisfy; the register is
17170 entirely cleared, breaking the dependency chain. We
17171 then store to the upper half, with a dependency depth
17172 of one. A rumor has it that Intel recommends two movsd
17173 followed by an unpacklpd, but this is unconfirmed. And
17174 given that the dependency depth of the unpacklpd would
17175 still be one, I'm not sure why this would be better. */
17177 }
17183 }
17184 else
17185 {
17186 rtx t;
17189 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17190 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17192 {
17194 {
17197 }
17204 }
17208 else
17213 else
17222 }
17223 }
17225 {
17227 {
17230 /* We will eventually emit movups based on insn attributes. */
17232 }
17234 {
17236 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17237 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17239 /* We will eventually emit movups based on insn attributes. */
17241 else
17242 {
17247 }
17248 }
17249 else
17250 {
17255 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17256 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17258 {
17261 }
17262 else
17263 {
17268 }
17269 }
17270 }
17271 else
17273 }
17275 /* Helper function of ix86_fixup_binary_operands to canonicalize
17276 operand order. Returns true if the operands should be swapped. */
17278 static bool
17280 rtx operands[])
17281 {
17286 /* If the operation is not commutative, we can't do anything. */
17290 /* Highest priority is that src1 should match dst. */
17296 /* Next highest priority is that immediate constants come second. */
17302 /* Lowest priority is that memory references should come second. */
17309 }
17312 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17313 destination to use for the operation. If different from the true
17314 destination in operands[0], a copy operation will be required. */
17316 rtx
17318 rtx operands[])
17319 {
17324 /* Canonicalize operand order. */
17326 {
17327 rtx temp;
17329 /* It is invalid to swap operands of different modes. */
17335 }
17337 /* Both source operands cannot be in memory. */
17339 {
17340 /* Optimization: Only read from memory once. */
17342 {
17345 }
17348 else
17350 }
17352 /* If the destination is memory, and we do not have matching source
17353 operands, do things in registers. */
17357 /* Source 1 cannot be a constant. */
17361 /* Source 1 cannot be a non-matching memory. */
17365 /* Improve address combine. */
17374 }
17376 /* Similarly, but assume that the destination has already been
17377 set up properly. */
17379 void
17382 {
17385 }
17387 /* Attempt to expand a binary operator. Make the expansion closer to the
17388 actual machine, then just general_operand, which will allow 3 separate
17389 memory references (one output, two input) in a single insn. */
17391 void
17393 rtx operands[])
17394 {
17401 /* Emit the instruction. */
17405 {
17406 /* Reload doesn't know about the flags register, and doesn't know that
17407 it doesn't want to clobber it. We can only do this with PLUS. */
17410 }
17414 {
17415 /* This is going to be an LEA; avoid splitting it later. */
17417 }
17418 else
17419 {
17422 }
17424 /* Fix up the destination if needed. */
17427 }
17429 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
17430 the given OPERANDS. */
17432 void
17434 rtx operands[])
17435 {
17438 {
17441 }
17443 {
17446 }
17447 /* Optimize (__m128i) d | (__m128i) e and similar code
17448 when d and e are float vectors into float vector logical
17449 insn. In C/C++ without using intrinsics there is no other way
17450 to express vector logical operation on float vectors than
17451 to cast them temporarily to integer vectors. */
17453 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17462 {
17463 rtx dst;
17465 {
17472 {
17475 }
17476 else
17477 {
17482 }
17493 }
17494 }
17503 }
17505 /* Return TRUE or FALSE depending on whether the binary operator meets the
17506 appropriate constraints. */
17508 bool
17511 {
17516 /* Both source operands cannot be in memory. */
17520 /* Canonicalize operand order for commutative operators. */
17522 {
17526 }
17528 /* If the destination is memory, we must have a matching source operand. */
17532 /* Source 1 cannot be a constant. */
17536 /* Source 1 cannot be a non-matching memory. */
17538 /* Support "andhi/andsi/anddi" as a zero-extending move. */
17546 }
17548 /* Attempt to expand a unary operator. Make the expansion closer to the
17549 actual machine, then just general_operand, which will allow 2 separate
17550 memory references (one output, one input) in a single insn. */
17552 void
17554 rtx operands[])
17555 {
17562 /* If the destination is memory, and we do not have matching source
17563 operands, do things in registers. */
17566 {
17569 else
17571 }
17573 /* When source operand is memory, destination must match. */
17577 /* Emit the instruction. */
17581 {
17582 /* Reload doesn't know about the flags register, and doesn't know that
17583 it doesn't want to clobber it. */
17586 }
17587 else
17588 {
17591 }
17593 /* Fix up the destination if needed. */
17596 }
17598 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
17599 divisor are within the range [0-255]. */
17601 void
17604 {
17613 {
17626 }
17633 /* Use 8bit unsigned divimod if dividend and divisor are within
17634 the range [0-255]. */
17643 pc_rtx);
17648 /* Generate original signed/unsigned divimod. */
17653 /* Branch to the end. */
17657 /* Generate 8bit unsigned divide. */
17659 /* Don't use operands[0] for result of 8bit divide since not all
17660 registers support QImode ZERO_EXTRACT. */
17667 {
17670 }
17671 else
17672 {
17675 }
17677 /* Extract remainder from AH. */
17681 else
17682 {
17683 /* Need a new scratch register since the old one has result
17684 of 8bit divide. */
17688 }
17691 /* Zero extend quotient from AL. */
17697 }
17699 /* Whether it is OK to emit CFI directives when emitting asm code. */
17701 bool
17703 {
17705 }
17707 #define LEA_MAX_STALL (3)
17708 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
17710 /* Increase given DISTANCE in half-cycles according to
17711 dependencies between PREV and NEXT instructions.
17712 Add 1 half-cycle if there is no dependency and
17713 go to next cycle if there is some dependecy. */
17715 static unsigned int
17717 {
17734 }
17736 /* Function checks if instruction INSN defines register number
17737 REGNO1 or REGNO2. */
17739 static bool
17741 rtx insn)
17742 {
17750 {
17752 }
17755 }
17757 /* Function checks if instruction INSN uses register number
17758 REGNO as a part of address expression. */
17760 static bool
17762 {
17770 }
17772 /* Search backward for non-agu definition of register number REGNO1
17773 or register number REGNO2 in basic block starting from instruction
17774 START up to head of basic block or instruction INSN.
17776 Function puts true value into *FOUND var if definition was found
17777 and false otherwise.
17779 Distance in half-cycles between START and found instruction or head
17780 of BB is added to DISTANCE and returned. */
17782 static int
17786 {
17796 {
17798 {
17801 {
17804 {
17807 }
17808 }
17811 }
17816 }
17819 }
17821 /* Search backward for non-agu definition of register number REGNO1
17822 or register number REGNO2 in INSN's basic block until
17823 1. Pass LEA_SEARCH_THRESHOLD instructions, or
17824 2. Reach neighbour BBs boundary, or
17825 3. Reach agu definition.
17826 Returns the distance between the non-agu definition point and INSN.
17827 If no definition point, returns -1. */
17829 static int
17831 rtx insn)
17832 {
17843 {
17844 edge e;
17845 edge_iterator ei;
17850 {
17853 }
17859 else
17860 {
17865 {
17866 int bb_dist
17872 {
17879 }
17880 }
17883 }
17884 }
17886 /* get_attr_type may modify recog data. We want to make sure
17887 that recog data is valid for instruction INSN, on which
17888 distance_non_agu_define is called. INSN is unchanged here. */
17895 }
17897 /* Return the distance in half-cycles between INSN and the next
17898 insn that uses register number REGNO in memory address added
17899 to DISTANCE. Return -1 if REGNO0 is set.
17901 Put true value into *FOUND if register usage was found and
17902 false otherwise.
17903 Put true value into *REDEFINED if register redefinition was
17904 found and false otherwise. */
17906 static int
17910 {
17919 {
17922 /* If insn and start belong to the same bb, set prev to insn,
17923 so the call to increase_distance will increase the distance
17924 between insns by 1. */
17926 }
17931 {
17933 {
17936 {
17937 /* Return DISTANCE if OP0 is used in memory
17938 address in NEXT. */
17941 }
17944 {
17945 /* Return -1 if OP0 is set in NEXT. */
17948 }
17951 }
17957 }
17960 }
17962 /* Return the distance between INSN and the next insn that uses
17963 register number REGNO0 in memory address. Return -1 if no such
17964 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
17966 static int
17968 {
17980 {
17981 edge e;
17982 edge_iterator ei;
17987 {
17990 }
17996 else
17997 {
18003 {
18004 int bb_dist
18009 {
18016 }
18017 }
18020 }
18021 }
18027 }
18029 /* Define this macro to tune LEA priority vs ADD, it take effect when
18030 there is a dilemma of choicing LEA or ADD
18031 Negative value: ADD is more preferred than LEA
18032 Zero: Netrual
18033 Positive value: LEA is more preferred than ADD*/
18034 #define IX86_LEA_PRIORITY 0
18036 /* Return true if usage of lea INSN has performance advantage
18037 over a sequence of instructions. Instructions sequence has
18038 SPLIT_COST cycles higher latency than lea latency. */
18040 static bool
18043 {
18046 /* For Silvermont if using a 2-source or 3-source LEA for
18047 non-destructive destination purposes, or due to wanting
18048 ability to use SCALE, the use of LEA is justified. */
18050 {
18058 }
18064 {
18065 /* If there is no non AGU operand definition, no AGU
18066 operand usage and split cost is 0 then both lea
18067 and non lea variants have same priority. Currently
18068 we prefer lea for 64 bit code and non lea on 32 bit
18069 code. */
18072 else
18074 }
18076 /* With longer definitions distance lea is more preferable.
18077 Here we change it to take into account splitting cost and
18078 lea priority. */
18081 /* If there is no use in memory addess then we just check
18082 that split cost exceeds AGU stall. */
18086 /* If this insn has both backward non-agu dependence and forward
18087 agu dependence, the one with short distance takes effect. */
18089 }
18091 /* Return true if it is legal to clobber flags by INSN and
18092 false otherwise. */
18094 static bool
18096 {
18099 bitmap live;
18102 {
18104 {
18111 }
18117 }
18121 }
18123 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18124 move and add to avoid AGU stalls. */
18126 bool
18128 {
18131 /* Check if we need to optimize. */
18135 /* Check it is correct to split here. */
18143 /* We need to split only adds with non destructive
18144 destination operand. */
18147 else
18149 }
18151 /* Return true if we should emit lea instruction instead of mov
18152 instruction. */
18154 bool
18156 {
18159 /* Check if we need to optimize. */
18163 /* Use lea for reg to reg moves only. */
18171 }
18173 /* Return true if we need to split lea into a sequence of
18174 instructions to avoid AGU stalls. */
18176 bool
18178 {
18184 /* Check we need to optimize. */
18188 /* The "at least two components" test below might not catch simple
18189 move or zero extension insns if parts.base is non-NULL and parts.disp
18190 is const0_rtx as the only components in the address, e.g. if the
18191 register is %rbp or %r13. As this test is much cheaper and moves or
18192 zero extensions are the common case, do this check first. */
18198 /* Check if it is OK to split here. */
18205 /* There should be at least two components in the address. */
18210 /* We should not split into add if non legitimate pic
18211 operand is used as displacement. */
18226 /* Compute how many cycles we will add to execution time
18227 if split lea into a sequence of instructions. */
18229 {
18230 /* Have to use mov instruction if non desctructive
18231 destination form is used. */
18235 /* Have to add index to base if both exist. */
18239 /* Have to use shift and adds if scale is 2 or greater. */
18241 {
18246 else
18248 }
18250 /* Have to use add instruction with immediate if
18251 disp is non zero. */
18255 /* Subtract the price of lea. */
18257 }
18261 }
18263 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18264 matches destination. RTX includes clobber of FLAGS_REG. */
18266 static void
18269 {
18276 }
18278 /* Return true if regno1 def is nearest to the insn. */
18280 static bool
18282 {
18289 {
18291 {
18294 }
18300 }
18302 /* None of the regs is defined in the bb. */
18304 }
18306 /* Split lea instructions into a sequence of instructions
18307 which are executed on ALU to avoid AGU stalls.
18308 It is assumed that it is allowed to clobber flags register
18309 at lea position. */
18311 void
18313 {
18329 {
18332 }
18335 {
18338 }
18344 {
18345 /* Case r1 = r1 + ... */
18347 {
18348 /* If we have a case r1 = r1 + C * r2 then we
18349 should use multiplication which is very
18350 expensive. Assume cost model is wrong if we
18351 have such case here. */
18356 }
18357 else
18358 {
18359 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18363 /* Use shift for scaling. */
18372 }
18373 }
18375 {
18378 }
18379 else
18380 {
18382 {
18385 }
18387 {
18390 }
18391 else
18392 {
18397 else
18398 {
18399 rtx tmp1;
18401 /* Find better operand for SET instruction, depending
18402 on which definition is farther from the insn. */
18405 else
18415 }
18418 }
18422 }
18423 }
18425 /* Return true if it is ok to optimize an ADD operation to LEA
18426 operation to avoid flag register consumation. For most processors,
18427 ADD is faster than LEA. For the processors like BONNELL, if the
18428 destination register of LEA holds an actual address which will be
18429 used soon, LEA is better and otherwise ADD is better. */
18431 bool
18433 {
18438 /* If a = b + c, (a!=b && a!=c), must use lea form. */
18446 }
18448 /* Return true if destination reg of SET_BODY is shift count of
18449 USE_BODY. */
18451 static bool
18453 {
18454 rtx set_dest;
18455 rtx shift_rtx;
18458 /* Retrieve destination of SET_BODY. */
18460 {
18469 use_body))
18474 }
18476 /* Retrieve shift count of USE_BODY. */
18478 {
18490 }
18498 {
18501 /* Return true if shift count is dest of SET_BODY. */
18503 {
18504 /* Add check since it can be invoked before register
18505 allocation in pre-reload schedule. */
18511 }
18512 }
18515 }
18517 /* Return true if destination reg of SET_INSN is shift count of
18518 USE_INSN. */
18520 bool
18522 {
18525 }
18527 /* Return TRUE or FALSE depending on whether the unary operator meets the
18528 appropriate constraints. */
18530 bool
18534 {
18535 /* If one of operands is memory, source and destination must match. */
18541 }
18543 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
18544 are ok, keeping in mind the possible movddup alternative. */
18546 bool
18548 {
18554 }
18556 /* Post-reload splitter for converting an SF or DFmode value in an
18557 SSE register into an unsigned SImode. */
18559 void
18561 {
18572 /* Load up the value into the low element. We must ensure that the other
18573 elements are valid floats -- zero is the easiest such value. */
18575 {
18578 else
18580 }
18581 else
18582 {
18587 else
18589 }
18609 else
18614 }
18616 /* Convert an unsigned DImode value into a DFmode, using only SSE.
18617 Expects the 64-bit DImode to be supplied in a pair of integral
18618 registers. Requires SSE2; will use SSE3 if available. For x86_32,
18619 -mfpmath=sse, !optimize_size only. */
18621 void
18623 {
18627 rtx x;
18633 {
18636 }
18637 else
18638 {
18642 }
18650 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
18653 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
18654 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
18655 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
18656 (0x1.0p84 + double(fp_value_hi_xmm)).
18657 Note these exponents differ by 32. */
18661 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
18662 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
18671 /* Add the upper and lower DFmode values together. */
18674 else
18675 {
18679 }
18682 }
18684 /* Not used, but eases macroization of patterns. */
18685 void
18687 rtx input ATTRIBUTE_UNUSED)
18688 {
18690 }
18692 /* Convert an unsigned SImode value into a DFmode. Only currently used
18693 for SSE, but applicable anywhere. */
18695 void
18697 {
18698 REAL_VALUE_TYPE TWO31r;
18713 }
18715 /* Convert a signed DImode value into a DFmode. Only used for SSE in
18716 32-bit mode; otherwise we have a direct convert instruction. */
18718 void
18720 {
18721 REAL_VALUE_TYPE TWO32r;
18739 }
18741 /* Convert an unsigned SImode value into a SFmode, using only SSE.
18742 For x86_32, -mfpmath=sse, !optimize_size only. */
18743 void
18745 {
18746 REAL_VALUE_TYPE ONE16r;
18765 }
18767 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
18768 a vector of unsigned ints VAL to vector of floats TARGET. */
18770 void
18772 {
18774 REAL_VALUE_TYPE TWO16r;
18781 else
18786 OPTAB_DIRECT);
18797 OPTAB_DIRECT);
18799 OPTAB_DIRECT);
18802 }
18804 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
18805 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
18806 This is done by doing just signed conversion if < 0x1p31, and otherwise by
18807 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
18809 rtx
18811 {
18812 REAL_VALUE_TYPE TWO31r;
18827 {
18833 }
18842 OPTAB_DIRECT);
18843 else
18844 {
18850 OPTAB_DIRECT);
18851 }
18854 }
18856 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
18857 then replicate the value for all elements of the vector
18858 register. */
18860 rtx
18862 {
18864 rtvec v;
18868 {
18901 }
18902 }
18904 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
18905 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
18906 for an SSE register. If VECT is true, then replicate the mask for
18907 all elements of the vector register. If INVERT is true, then create
18908 a mask excluding the sign bit. */
18910 rtx
18912 {
18916 rtx v;
18917 rtx mask;
18919 /* Find the sign bit, sign extended to 2*HWI. */
18921 {
18945 else
18953 {
18956 }
18957 else
18958 {
18959 rtvec vec;
18965 {
18968 }
18969 else
18979 }
18984 }
18989 /* Force this value into the low part of a fp vector constant. */
18998 }
19000 /* Generate code for floating point ABS or NEG. */
19002 void
19004 rtx operands[])
19005 {
19016 {
19022 }
19024 /* NEG and ABS performed with SSE use bitwise mask operations.
19025 Create the appropriate mask now. */
19028 else
19038 {
19040 rtvec par;
19045 else
19046 {
19049 }
19051 }
19052 else
19054 }
19056 /* Expand a copysign operation. Special case operand 0 being a constant. */
19058 void
19060 {
19074 else
19078 {
19085 {
19088 else
19089 {
19093 }
19094 }
19104 else
19108 }
19109 else
19110 {
19120 else
19124 }
19125 }
19127 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19128 be a constant, and so has already been expanded into a vector constant. */
19130 void
19132 {
19148 {
19151 }
19152 }
19154 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19155 so we have to do two masks. */
19157 void
19159 {
19174 {
19175 /* Shouldn't happen often (it's useless, obviously), but when it does
19176 we'd generate incorrect code if we continue below. */
19179 }
19182 {
19193 }
19194 else
19195 {
19197 {
19199 }
19201 {
19205 }
19209 {
19212 }
19214 {
19219 }
19221 }
19225 }
19227 /* Return TRUE or FALSE depending on whether the first SET in INSN
19228 has source and destination with matching CC modes, and that the
19229 CC mode is at least as constrained as REQ_MODE. */
19231 bool
19233 {
19234 rtx set;
19245 {
19255 /* FALLTHRU */
19259 /* FALLTHRU */
19263 /* FALLTHRU */
19277 }
19280 }
19282 /* Generate insn patterns to do an integer compare of OPERANDS. */
19284 static rtx
19286 {
19293 /* This is very simple, but making the interface the same as in the
19294 FP case makes the rest of the code easier. */
19298 /* Return the test that should be put into the flags user, i.e.
19299 the bcc, scc, or cmov instruction. */
19301 }
19303 /* Figure out whether to use ordered or unordered fp comparisons.
19304 Return the appropriate mode to use. */
19306 enum machine_mode
19308 {
19309 /* ??? In order to make all comparisons reversible, we do all comparisons
19310 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19311 all forms trapping and nontrapping comparisons, we can make inequality
19312 comparisons trapping again, since it results in better code when using
19313 FCOM based compares. */
19315 }
19317 enum machine_mode
19319 {
19323 {
19326 }
19329 {
19330 /* Only zero flag is needed. */
19334 /* Codes needing carry flag. */
19337 /* Detect overflow checks. They need just the carry flag. */
19341 else
19346 /* Codes possibly doable only with sign flag when
19347 comparing against zero. */
19352 else
19353 /* For other cases Carry flag is not required. */
19355 /* Codes doable only with sign flag when comparing
19356 against zero, but we miss jump instruction for it
19357 so we need to use relational tests against overflow
19358 that thus needs to be zero. */
19363 else
19365 /* strcmp pattern do (use flags) and combine may ask us for proper
19366 mode. */
19371 }
19372 }
19374 /* Return the fixed registers used for condition codes. */
19376 static bool
19378 {
19382 }
19384 /* If two condition code modes are compatible, return a condition code
19385 mode which is compatible with both. Otherwise, return
19386 VOIDmode. */
19388 static enum machine_mode
19390 {
19407 {
19421 {
19435 }
19439 /* These are only compatible with themselves, which we already
19440 checked above. */
19442 }
19443 }
19446 /* Return a comparison we can do and that it is equivalent to
19447 swap_condition (code) apart possibly from orderedness.
19448 But, never change orderedness if TARGET_IEEE_FP, returning
19449 UNKNOWN in that case if necessary. */
19451 static enum rtx_code
19453 {
19455 {
19466 }
19467 }
19469 /* Return cost of comparison CODE using the best strategy for performance.
19470 All following functions do use number of instructions as a cost metrics.
19471 In future this should be tweaked to compute bytes for optimize_size and
19472 take into account performance of various instructions on various CPUs. */
19474 static int
19476 {
19479 /* The cost of code using bit-twiddling on %ah. */
19481 {
19504 }
19507 {
19514 }
19515 }
19517 /* Return strategy to use for floating-point. We assume that fcomi is always
19518 preferrable where available, since that is also true when looking at size
19519 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
19521 enum ix86_fpcmp_strategy
19523 {
19524 /* Do fcomi/sahf based test when profitable. */
19533 }
19535 /* Swap, force into registers, or otherwise massage the two operands
19536 to a fp comparison. The operands are updated in place; the new
19537 comparison code is returned. */
19539 static enum rtx_code
19541 {
19547 /* All of the unordered compare instructions only work on registers.
19548 The same is true of the fcomi compare instructions. The XFmode
19549 compare instructions require registers except when comparing
19550 against zero or when converting operand 1 from fixed point to
19551 floating point. */
19560 {
19563 }
19564 else
19565 {
19566 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
19567 things around if they appear profitable, otherwise force op0
19568 into a register. */
19574 {
19577 {
19578 rtx tmp;
19581 }
19582 }
19588 {
19593 {
19596 }
19597 else
19599 }
19600 }
19602 /* Try to rearrange the comparison to make it cheaper. */
19606 {
19607 rtx tmp;
19612 }
19617 }
19619 /* Convert comparison codes we use to represent FP comparison to integer
19620 code that will result in proper branch. Return UNKNOWN if no such code
19621 is available. */
19623 enum rtx_code
19625 {
19627 {
19650 }
19651 }
19653 /* Generate insn patterns to do a floating point compare of OPERANDS. */
19655 static rtx
19657 {
19664 /* Do fcomi/sahf based test when profitable. */
19666 {
19671 tmp);
19679 tmp);
19688 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
19695 /* In the unordered case, we have to check C2 for NaN's, which
19696 doesn't happen to work out to anything nice combination-wise.
19697 So do some bit twiddling on the value we've got in AH to come
19698 up with an appropriate set of condition codes. */
19702 {
19706 {
19709 }
19710 else
19711 {
19717 }
19722 {
19727 }
19728 else
19729 {
19732 }
19737 {
19740 }
19741 else
19742 {
19746 }
19751 {
19757 }
19758 else
19759 {
19762 }
19767 {
19772 }
19773 else
19774 {
19777 }
19782 {
19787 }
19788 else
19789 {
19792 }
19806 }
19811 }
19813 /* Return the test that should be put into the flags user, i.e.
19814 the bcc, scc, or cmov instruction. */
19817 const0_rtx);
19818 }
19820 static rtx
19822 {
19823 rtx ret;
19829 {
19832 }
19833 else
19837 }
19839 void
19841 {
19843 rtx tmp;
19846 {
19853 simple:
19857 pc_rtx);
19865 /* Expand DImode branch into multiple compare+branch. */
19866 {
19872 {
19875 }
19882 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
19883 avoid two branches. This costs one extra insn, so disable when
19884 optimizing for size. */
19889 {
19907 }
19909 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19910 op1 is a constant and the low word is zero, then we can just
19911 examine the high word. Similarly for low word -1 and
19912 less-or-equal-than or greater-than. */
19916 {
19919 {
19922 }
19926 {
19929 }
19933 }
19935 /* Otherwise, we need two or three jumps. */
19944 {
19958 }
19960 /*
19961 * a < b =>
19962 * if (hi(a) < hi(b)) goto true;
19963 * if (hi(a) > hi(b)) goto false;
19964 * if (lo(a) < lo(b)) goto true;
19965 * false:
19966 */
19978 }
19983 }
19984 }
19986 /* Split branch based on floating point condition. */
19987 void
19990 {
19991 rtx condition;
19992 rtx i;
19995 {
20000 }
20003 tmp);
20005 /* Remove pushed operand from stack. */
20015 }
20017 void
20019 {
20020 rtx ret;
20027 }
20029 /* Expand comparison setting or clearing carry flag. Return true when
20030 successful and set pop for the operation. */
20031 static bool
20033 {
20037 /* Do not handle double-mode compares that go through special path. */
20042 {
20047 /* Shortcut: following common codes never translate
20048 into carry flag compares. */
20053 /* These comparisons require zero flag; swap operands so they won't. */
20056 {
20061 }
20063 /* Try to expand the comparison and verify that we end up with
20064 carry flag based comparison. This fails to be true only when
20065 we decide to expand comparison using arithmetic that is not
20066 too common scenario. */
20075 else
20084 }
20090 {
20095 /* Convert a==0 into (unsigned)a<1. */
20104 /* Convert a>b into b<a or a>=b-1. */
20108 {
20110 /* Bail out on overflow. We still can swap operands but that
20111 would force loading of the constant into register. */
20116 }
20117 else
20118 {
20123 }
20126 /* Convert a>=0 into (unsigned)a<0x80000000. */
20144 }
20145 /* Swapping operands may cause constant to appear as first operand. */
20147 {
20151 }
20155 }
20157 bool
20159 {
20183 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20184 HImode insns, we'd be swallowed in word prefix ops. */
20190 {
20194 HOST_WIDE_INT diff;
20197 /* Sign bit compares are better done using shifts than we do by using
20198 sbb. */
20201 {
20202 /* Detect overlap between destination and compare sources. */
20206 {
20207 rtx flags;
20216 {
20218 compare_code
20220 }
20222 /* To simplify rest of code, restrict to the GEU case. */
20224 {
20230 }
20231 else
20232 {
20235 reverse_condition_maybe_unordered
20237 else
20240 }
20249 else
20252 }
20253 else
20254 {
20257 else
20258 {
20263 }
20265 }
20268 {
20269 /*
20270 * cmpl op0,op1
20271 * sbbl dest,dest
20272 * [addl dest, ct]
20273 *
20274 * Size 5 - 8.
20275 */
20280 }
20282 {
20283 /*
20284 * cmpl op0,op1
20285 * sbbl dest,dest
20286 * orl $ct, dest
20287 *
20288 * Size 8.
20289 */
20293 }
20295 {
20296 /*
20297 * cmpl op0,op1
20298 * sbbl dest,dest
20299 * notl dest
20300 * [addl dest, cf]
20301 *
20302 * Size 8 - 11.
20303 */
20309 }
20310 else
20311 {
20312 /*
20313 * cmpl op0,op1
20314 * sbbl dest,dest
20315 * [notl dest]
20316 * andl cf - ct, dest
20317 * [addl dest, ct]
20318 *
20319 * Size 8 - 11.
20320 */
20323 {
20327 }
20337 }
20343 }
20346 {
20349 HOST_WIDE_INT tmp;
20354 {
20357 /* We may be reversing unordered compare to normal compare, that
20358 is not valid in general (we may convert non-trapping condition
20359 to trapping one), however on i386 we currently emit all
20360 comparisons unordered. */
20363 }
20364 else
20365 {
20368 }
20369 }
20374 {
20379 {
20384 }
20385 }
20387 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20391 {
20392 /* If lea code below could be used, only optimize
20393 if it results in a 2 insn sequence. */
20399 {
20400 /*
20401 * notl op1 (if necessary)
20402 * sarl $31, op1
20403 * orl cf, op1
20404 */
20406 {
20410 }
20421 }
20422 }
20430 {
20431 /*
20432 * xorl dest,dest
20433 * cmpl op1,op2
20434 * setcc dest
20435 * lea cf(dest*(ct-cf)),dest
20436 *
20437 * Size 14.
20438 *
20439 * This also catches the degenerate setcc-only case.
20440 */
20442 rtx tmp;
20448 /* On x86_64 the lea instruction operates on Pmode, so we need
20449 to get arithmetics done in proper mode to match. */
20452 else
20453 {
20454 rtx out1;
20457 nops++;
20459 {
20461 nops++;
20462 }
20463 }
20465 {
20467 nops++;
20468 }
20470 {
20473 else
20475 }
20480 }
20482 /*
20483 * General case: Jumpful:
20484 * xorl dest,dest cmpl op1, op2
20485 * cmpl op1, op2 movl ct, dest
20486 * setcc dest jcc 1f
20487 * decl dest movl cf, dest
20488 * andl (cf-ct),dest 1:
20489 * addl ct,dest
20490 *
20491 * Size 20. Size 14.
20492 *
20493 * This is reasonably steep, but branch mispredict costs are
20494 * high on modern cpus, so consider failing only if optimizing
20495 * for space.
20496 */
20501 {
20503 {
20510 {
20513 /* We may be reversing unordered compare to normal compare,
20514 that is not valid in general (we may convert non-trapping
20515 condition to trapping one), however on i386 we currently
20516 emit all comparisons unordered. */
20518 }
20519 else
20520 {
20524 }
20525 }
20528 {
20529 /* notl op1 (if needed)
20530 sarl $31, op1
20531 andl (cf-ct), op1
20532 addl ct, op1
20534 For x < 0 (resp. x <= -1) there will be no notl,
20535 so if possible swap the constants to get rid of the
20536 complement.
20537 True/false will be -1/0 while code below (store flag
20538 followed by decrement) is 0/-1, so the constants need
20539 to be exchanged once more. */
20542 {
20545 }
20546 else
20547 {
20551 }
20554 }
20555 else
20556 {
20560 constm1_rtx,
20562 }
20574 }
20575 }
20578 {
20579 /* Try a few things more with specific constants and a variable. */
20581 optab op;
20587 /* If one of the two operands is an interesting constant, load a
20588 constant with the above and mask it in with a logical operation. */
20591 {
20597 else
20599 }
20601 {
20607 else
20609 }
20610 else
20617 /* Recurse to get the constant loaded. */
20621 /* Mask in the interesting variable. */
20623 OPTAB_WIDEN);
20628 }
20630 /*
20631 * For comparison with above,
20632 *
20633 * movl cf,dest
20634 * movl ct,tmp
20635 * cmpl op1,op2
20636 * cmovcc tmp,dest
20637 *
20638 * Size 15.
20639 */
20661 }
20663 /* Swap, force into registers, or otherwise massage the two operands
20664 to an sse comparison with a mask result. Thus we differ a bit from
20665 ix86_prepare_fp_compare_args which expects to produce a flags result.
20667 The DEST operand exists to help determine whether to commute commutative
20668 operators. The POP0/POP1 operands are updated in place. The new
20669 comparison code is returned, or UNKNOWN if not implementable. */
20671 static enum rtx_code
20674 {
20675 rtx tmp;
20678 {
20681 /* AVX supports all the needed comparisons. */
20684 /* We have no LTGT as an operator. We could implement it with
20685 NE & ORDERED, but this requires an extra temporary. It's
20686 not clear that it's worth it. */
20693 /* These are supported directly. */
20700 /* AVX has 3 operand comparisons, no need to swap anything. */
20703 /* For commutative operators, try to canonicalize the destination
20704 operand to be first in the comparison - this helps reload to
20705 avoid extra moves. */
20708 /* FALLTHRU */
20714 /* These are not supported directly before AVX, and furthermore
20715 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
20716 comparison operands to transform into something that is
20717 supported. */
20726 }
20729 }
20731 /* Detect conditional moves that exactly match min/max operational
20732 semantics. Note that this is IEEE safe, as long as we don't
20733 interchange the operands.
20735 Returns FALSE if this conditional move doesn't match a MIN/MAX,
20736 and TRUE if the operation is successful and instructions are emitted. */
20738 static bool
20741 {
20744 rtx tmp;
20747 ;
20749 {
20753 }
20754 else
20761 else
20766 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
20767 but MODE may be a vector mode and thus not appropriate. */
20769 {
20771 rtvec v;
20776 }
20777 else
20778 {
20781 }
20785 }
20787 /* Expand an sse vector comparison. Return the register with the result. */
20789 static rtx
20792 {
20796 /* In general case result of comparison can differ from operands' type. */
20799 /* In AVX512F the result of comparison is an integer mask. */
20801 rtx x;
20804 {
20809 }
20810 else
20823 /* Compare patterns for int modes are unspec in AVX512F only. */
20825 {
20829 {
20838 }
20841 {
20844 }
20845 }
20849 {
20852 }
20853 else
20857 }
20859 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
20860 operations. This is used for both scalar and vector conditional moves. */
20862 static void
20864 {
20868 /* In AVX512F the result of comparison is an integer mask. */
20876 {
20878 }
20881 {
20885 }
20888 {
20893 }
20896 {
20900 }
20903 {
20911 op_true,
20912 op_false)));
20913 }
20914 else
20915 {
20925 {
20939 {
20946 }
20961 {
20968 }
20986 }
20989 {
20993 }
20994 else
20995 {
21001 else
21013 }
21014 }
21015 }
21017 /* Expand a floating-point conditional move. Return true if successful. */
21019 bool
21021 {
21029 {
21032 /* Since we've no cmove for sse registers, don't force bad register
21033 allocation just to gain access to it. Deny movcc when the
21034 comparison mode doesn't match the move mode. */
21053 }
21060 /* The floating point conditional move instructions don't directly
21061 support conditions resulting from a signed integer comparison. */
21065 {
21070 }
21077 }
21079 /* Expand a floating-point vector conditional move; a vcond operation
21080 rather than a movcc operation. */
21082 bool
21084 {
21086 rtx cmp;
21091 {
21092 rtx temp;
21094 {
21111 }
21113 OPTAB_DIRECT);
21116 }
21126 }
21128 /* Expand a signed/unsigned integral vector conditional move. */
21130 bool
21132 {
21142 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21143 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21152 {
21156 {
21162 }
21165 {
21171 }
21172 }
21181 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21185 ;
21186 else
21187 {
21188 /* Canonicalize the comparison to EQ, GT, GTU. */
21190 {
21207 /* FALLTHRU */
21217 }
21219 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21221 {
21223 {
21225 /* SSE4.1 supports EQ. */
21232 /* SSE4.2 supports GT/GTU. */
21239 }
21240 }
21242 /* Unsigned parallel compare is not supported by the hardware.
21243 Play some tricks to turn this into a signed comparison
21244 against 0. */
21246 {
21250 {
21257 {
21262 {
21271 }
21272 /* Subtract (-(INT MAX) - 1) from both operands to make
21273 them signed. */
21284 }
21291 /* Perform a parallel unsigned saturating subtraction. */
21304 }
21305 }
21306 }
21308 /* Allow the comparison to be done in one mode, but the movcc to
21309 happen in another mode. */
21311 {
21314 }
21315 else
21316 {
21322 }
21327 }
21329 static bool
21331 {
21334 {
21338 op1));
21343 op1));
21355 }
21356 }
21358 /* Expand a variable vector permutation. */
21360 void
21362 {
21373 /* Number of elements in the vector. */
21382 {
21384 {
21385 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
21386 an constant shuffle operand. With a tiny bit of effort we can
21387 use VPERMD instead. A re-interpretation stall for V4DFmode is
21388 unfortunate but there's no avoiding it.
21389 Similarly for V16HImode we don't have instructions for variable
21390 shuffling, while for V32QImode we can use after preparing suitable
21391 masks vpshufb; vpshufb; vpermq; vpor. */
21394 {
21398 }
21399 else
21400 {
21404 }
21407 /* Replicate the low bits of the V4DImode mask into V8SImode:
21408 mask = { A B C D }
21409 t1 = { A A B B C C D D }. */
21417 else
21420 /* Multiply the shuffle indicies by two. */
21422 OPTAB_DIRECT);
21424 /* Add one to the odd shuffle indicies:
21425 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
21427 {
21430 }
21434 OPTAB_DIRECT);
21436 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
21441 }
21444 {
21446 /* The VPERMD and VPERMPS instructions already properly ignore
21447 the high bits of the shuffle elements. No need for us to
21448 perform an AND ourselves. */
21450 {
21455 }
21456 else
21457 {
21463 }
21470 else
21471 {
21477 }
21481 /* By combining the two 128-bit input vectors into one 256-bit
21482 input vector, we can use VPERMD and VPERMPS for the full
21483 two-operand shuffle. */
21515 /* From mask create two adjusted masks, which contain the same
21516 bits as mask in the low 7 bits of each vector element.
21517 The first mask will have the most significant bit clear
21518 if it requests element from the same 128-bit lane
21519 and MSB set if it requests element from the other 128-bit lane.
21520 The second mask will have the opposite values of the MSB,
21521 and additionally will have its 128-bit lanes swapped.
21522 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
21523 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
21524 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
21525 stands for other 12 bytes. */
21526 /* The bit whether element is from the same lane or the other
21527 lane is bit 4, so shift it up by 3 to the MSB position. */
21531 /* Clear MSB bits from the mask just in case it had them set. */
21533 /* After this t1 will have MSB set for elements from other lane. */
21535 /* Clear bits other than MSB. */
21537 /* Or in the lower bits from mask into t3. */
21539 /* And invert MSB bits in t1, so MSB is set for elements from the same
21540 lane. */
21542 /* Swap 128-bit lanes in t3. */
21547 /* And or in the lower bits from mask into t1. */
21550 {
21551 /* Each of these shuffles will put 0s in places where
21552 element from the other 128-bit lane is needed, otherwise
21553 will shuffle in the requested value. */
21557 /* For t3 the 128-bit lanes are swapped again. */
21562 /* And oring both together leads to the result. */
21569 }
21572 /* Similarly to the above one_operand_shuffle code,
21573 just for repeated twice for each operand. merge_two:
21574 code will merge the two results together. */
21598 }
21599 }
21602 {
21603 /* The XOP VPPERM insn supports three inputs. By ignoring the
21604 one_operand_shuffle special case, we avoid creating another
21605 set of constant vectors in memory. */
21608 /* mask = mask & {2*w-1, ...} */
21610 }
21611 else
21612 {
21613 /* mask = mask & {w-1, ...} */
21615 }
21623 /* For non-QImode operations, convert the word permutation control
21624 into a byte permutation control. */
21626 {
21631 /* Convert mask to vector of chars. */
21634 /* Replicate each of the input bytes into byte positions:
21635 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
21636 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
21637 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
21644 else
21647 /* Convert it into the byte positions by doing
21648 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
21654 }
21656 /* The actual shuffle operations all operate on V16QImode. */
21661 {
21668 }
21670 {
21677 }
21678 else
21679 {
21683 /* Shuffle the two input vectors independently. */
21689 merge_two:
21690 /* Then merge them together. The key is whether any given control
21691 element contained a bit set that indicates the second word. */
21695 {
21696 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
21697 more shuffle to convert the V2DI input mask into a V4SI
21698 input mask. At which point the masking that expand_int_vcond
21699 will work as desired. */
21707 }
21729 }
21730 }
21732 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
21733 true if we should do zero extension, else sign extension. HIGH_P is
21734 true if we want the N/2 high elements, else the low elements. */
21736 void
21738 {
21740 rtx tmp;
21743 {
21749 {
21753 else
21756 extract
21762 else
21765 extract
21771 else
21774 extract
21780 else
21783 extract
21789 else
21792 extract
21798 else
21804 else
21810 else
21815 }
21818 {
21821 }
21823 {
21824 /* Shift higher 8 bytes to lower 8 bytes. */
21829 }
21830 else
21834 }
21835 else
21836 {
21840 {
21844 else
21850 else
21856 else
21861 }
21865 else
21872 }
21873 }
21875 /* Expand conditional increment or decrement using adb/sbb instructions.
21876 The default case using setcc followed by the conditional move can be
21877 done by generic code. */
21878 bool
21880 {
21882 rtx flags;
21884 rtx compare_op;
21902 {
21905 }
21908 {
21912 reverse_condition_maybe_unordered
21914 else
21916 }
21920 /* Construct either adc or sbb insn. */
21922 {
21924 {
21939 }
21940 }
21941 else
21942 {
21944 {
21959 }
21960 }
21964 }
21967 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
21968 but works for floating pointer parameters and nonoffsetable memories.
21969 For pushes, it returns just stack offsets; the values will be saved
21970 in the right order. Maximally three parts are generated. */
21972 static int
21974 {
21979 else
21985 /* Optimize constant pool reference to immediates. This is used by fp
21986 moves, that force all constants to memory to allow combining. */
21988 {
21992 }
21995 {
21996 /* The only non-offsetable memories we handle are pushes. */
22005 }
22008 {
22010 /* Caution: if we looked through a constant pool memory above,
22011 the operand may actually have a different mode now. That's
22012 ok, since we want to pun this all the way back to an integer. */
22016 }
22019 {
22022 else
22023 {
22027 {
22031 }
22033 {
22038 }
22040 {
22041 REAL_VALUE_TYPE r;
22046 {
22053 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22054 long double may not be 80-bit. */
22063 }
22066 }
22067 else
22069 }
22070 }
22071 else
22072 {
22076 {
22079 {
22083 }
22085 {
22089 }
22091 {
22092 REAL_VALUE_TYPE r;
22098 /* Do not use shift by 32 to avoid warning on 32bit systems. */
22101 = gen_int_mode
22104 DImode);
22105 else
22112 = gen_int_mode
22115 DImode);
22116 else
22118 }
22119 else
22121 }
22122 }
22125 }
22127 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22128 Return false when normal moves are needed; true when all required
22129 insns have been emitted. Operands 2-4 contain the input values
22130 int the correct order; operands 5-7 contain the output values. */
22132 void
22134 {
22142 /* The DFmode expanders may ask us to move double.
22143 For 64bit target this is single move. By hiding the fact
22144 here we simplify i386.md splitters. */
22146 {
22147 /* Optimize constant pool reference to immediates. This is used by
22148 fp moves, that force all constants to memory to allow combining. */
22155 {
22158 }
22159 else
22164 }
22166 /* The only non-offsettable memory we handle is push. */
22169 else
22176 /* When emitting push, take care for source operands on the stack. */
22179 {
22182 /* Compensate for the stack decrement by 4. */
22187 /* src_base refers to the stack pointer and is
22188 automatically decreased by emitted push. */
22192 }
22194 /* We need to do copy in the right order in case an address register
22195 of the source overlaps the destination. */
22197 {
22198 rtx tmp;
22201 {
22205 collisions++;
22206 }
22208 /* Collision in the middle part can be handled by reordering. */
22210 {
22213 }
22217 {
22219 {
22222 }
22223 else
22224 {
22227 }
22228 }
22230 /* If there are more collisions, we can't handle it by reordering.
22231 Do an lea to the last part and use only one colliding move. */
22233 {
22234 rtx base;
22240 /* Handle the case when the last part isn't valid for lea.
22241 Happens in 64-bit mode storing the 12-byte XFmode. */
22248 {
22251 }
22252 }
22253 }
22256 {
22258 {
22260 {
22265 }
22267 {
22270 }
22271 }
22272 else
22273 {
22274 /* In 64bit mode we don't have 32bit push available. In case this is
22275 register, it is OK - we will just use larger counterpart. We also
22276 retype memory - these comes from attempt to avoid REX prefix on
22277 moving of second half of TFmode value. */
22279 {
22281 {
22292 }
22296 }
22297 }
22301 }
22303 /* Choose correct order to not overwrite the source before it is copied. */
22313 {
22315 {
22318 }
22319 }
22320 else
22321 {
22323 {
22326 }
22327 }
22329 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
22331 {
22340 }
22346 }
22348 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
22349 left shift by a constant, either using a single shift or
22350 a sequence of add instructions. */
22352 static void
22354 {
22360 {
22364 }
22365 else
22366 {
22369 }
22370 }
22372 void
22374 {
22383 {
22388 {
22394 }
22395 else
22396 {
22404 }
22406 }
22413 {
22414 /* Assuming we've chosen a QImode capable registers, then 1 << N
22415 can be done with two 32/64-bit shifts, no branches, no cmoves. */
22417 {
22433 }
22435 /* Otherwise, we can get the same results by manually performing
22436 a bit extract operation on bit 5/6, and then performing the two
22437 shifts. The two methods of getting 0/1 into low/high are exactly
22438 the same size. Avoiding the shift in the bit extract case helps
22439 pentium4 a bit; no one else seems to care much either way. */
22440 else
22441 {
22446 HOST_WIDE_INT bits;
22447 rtx x;
22450 {
22456 }
22457 else
22458 {
22464 }
22468 else
22476 }
22481 }
22484 {
22485 /* For -1 << N, we can avoid the shld instruction, because we
22486 know that we're shifting 0...31/63 ones into a -1. */
22490 else
22492 }
22493 else
22494 {
22502 }
22507 {
22513 }
22514 else
22515 {
22520 }
22521 }
22523 void
22525 {
22535 {
22540 {
22546 }
22548 {
22557 }
22558 else
22559 {
22567 }
22568 }
22569 else
22570 {
22582 {
22590 scratch));
22591 }
22592 else
22593 {
22598 }
22599 }
22600 }
22602 void
22604 {
22614 {
22619 {
22626 }
22627 else
22628 {
22636 }
22637 }
22638 else
22639 {
22651 {
22657 scratch));
22658 }
22659 else
22660 {
22665 }
22666 }
22667 }
22669 /* Predict just emitted jump instruction to be taken with probability PROB. */
22670 static void
22672 {
22676 }
22678 /* Helper function for the string operations below. Dest VARIABLE whether
22679 it is aligned to VALUE bytes. If true, jump to the label. */
22680 static rtx
22682 {
22687 else
22693 else
22696 }
22698 /* Adjust COUNTER by the VALUE. */
22699 static void
22701 {
22706 }
22708 /* Zero extend possibly SImode EXP to Pmode register. */
22709 rtx
22711 {
22713 }
22715 /* Divide COUNTREG by SCALE. */
22716 static rtx
22718 {
22719 rtx sc;
22731 }
22733 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
22734 DImode for constant loop counts. */
22736 static enum machine_mode
22738 {
22746 }
22748 /* Copy the address to a Pmode register. This is used for x32 to
22749 truncate DImode TLS address to a SImode register. */
22751 static rtx
22753 {
22756 else
22757 {
22760 }
22761 }
22763 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
22764 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
22765 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
22766 memory by VALUE (supposed to be in MODE).
22768 The size is rounded down to whole number of chunk size moved at once.
22769 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
22772 static void
22777 {
22783 rtx size;
22792 /* Those two should combine. */
22794 {
22798 }
22805 /* This assert could be relaxed - in this case we'll need to compute
22806 smallest power of two, containing in PIECE_SIZE_N and pass it to
22807 offset_address. */
22813 {
22817 /* When unrolling for chips that reorder memory reads and writes,
22818 we can save registers by using single temporary.
22819 Also using 4 temporaries is overkill in 32bit mode. */
22821 {
22823 {
22825 {
22826 destmem =
22828 srcmem =
22830 }
22832 }
22833 }
22834 else
22835 {
22839 {
22842 {
22843 srcmem =
22845 }
22847 }
22849 {
22851 {
22852 destmem =
22854 }
22856 }
22857 }
22858 }
22859 else
22861 {
22863 destmem =
22866 }
22876 {
22882 else
22884 }
22885 else
22893 {
22898 }
22900 }
22902 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
22903 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
22904 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
22905 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
22906 ORIG_VALUE is the original value passed to memset to fill the memory with.
22907 Other arguments have same meaning as for previous function. */
22909 static void
22912 rtx count,
22914 {
22915 rtx destexp;
22916 rtx srcexp;
22917 rtx countreg;
22918 HOST_WIDE_INT rounded_count;
22920 /* If possible, it is shorter to use rep movs.
22921 TODO: Maybe it is better to move this logic to decide_alg. */
22932 {
22936 }
22937 else
22940 {
22945 }
22950 {
22953 }
22954 else
22955 {
22959 {
22963 }
22964 else
22967 {
22972 }
22973 else
22974 {
22977 }
22980 }
22981 }
22983 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
22984 DESTMEM.
22985 SRC is passed by pointer to be updated on return.
22986 Return value is updated DST. */
22987 static rtx
22989 HOST_WIDE_INT size_to_move)
22990 {
22996 /* Find the widest mode in which we could perform moves.
22997 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
22998 it until move of such size is supported. */
23003 {
23007 }
23009 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23010 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23012 {
23017 {
23021 }
23022 }
23028 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23032 {
23033 /* We move from memory to memory, so we'll need to do it via
23034 a temporary register. */
23045 piece_size);
23047 piece_size);
23048 }
23050 /* Update DST and SRC rtx. */
23053 }
23055 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23056 static void
23059 {
23062 {
23067 /* For now MAX_SIZE should be a power of 2. This assert could be
23068 relaxed, but it'll require a bit more complicated epilogue
23069 expanding. */
23072 {
23075 }
23077 }
23079 {
23085 }
23087 /* When there are stringops, we can cheaply increase dest and src pointers.
23088 Otherwise we save code size by maintaining offset (zero is readily
23089 available from preceding rep operation) and using x86 addressing modes.
23090 */
23092 {
23094 {
23101 }
23103 {
23110 }
23112 {
23119 }
23120 }
23121 else
23122 {
23124 rtx tmp;
23127 {
23138 }
23140 {
23153 }
23155 {
23164 }
23165 }
23166 }
23168 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23169 with value PROMOTED_VAL.
23170 SRC is passed by pointer to be updated on return.
23171 Return value is updated DST. */
23172 static rtx
23174 HOST_WIDE_INT size_to_move)
23175 {
23181 /* Find the widest mode in which we could perform moves.
23182 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23183 it until move of such size is supported. */
23188 {
23191 }
23198 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23202 {
23204 {
23207 piece_size);
23209 }
23217 piece_size);
23218 }
23220 /* Update DST rtx. */
23222 }
23223 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23224 static void
23227 {
23228 count =
23234 }
23236 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23237 static void
23240 {
23241 rtx dest;
23244 {
23249 /* For now MAX_SIZE should be a power of 2. This assert could be
23250 relaxed, but it'll require a bit more complicated epilogue
23251 expanding. */
23254 {
23256 {
23259 else
23261 }
23262 }
23264 }
23266 {
23269 }
23271 {
23274 {
23279 }
23280 else
23281 {
23290 }
23293 }
23295 {
23298 {
23301 }
23302 else
23303 {
23308 }
23311 }
23313 {
23319 }
23321 {
23327 }
23329 {
23335 }
23336 }
23338 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
23339 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
23340 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
23341 ignored.
23342 Return value is updated DESTMEM. */
23343 static rtx
23348 {
23351 {
23353 {
23356 {
23359 else
23361 }
23362 else
23368 }
23369 }
23371 }
23373 /* Test if COUNT&SIZE is nonzero and if so, expand movme
23374 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
23375 and jump to DONE_LABEL. */
23376 static void
23382 {
23385 rtx modesize;
23388 /* If we do not have vector value to copy, we must reduce size. */
23390 {
23392 {
23397 }
23398 else
23400 }
23401 else
23402 {
23403 /* Choose appropriate vector mode. */
23409 }
23414 {
23417 else
23418 {
23421 }
23423 }
23429 {
23433 }
23435 {
23438 else
23439 {
23442 }
23444 }
23450 }
23452 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
23453 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
23454 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
23455 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
23456 DONE_LABEL is a label after the whole copying sequence. The label is created
23457 on demand if *DONE_LABEL is NULL.
23458 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
23459 bounds after the initial copies.
23461 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
23462 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
23463 we will dispatch to a library call for large blocks.
23465 In pseudocode we do:
23467 if (COUNT < SIZE)
23468 {
23469 Assume that SIZE is 4. Bigger sizes are handled analogously
23470 if (COUNT & 4)
23471 {
23472 copy 4 bytes from SRCPTR to DESTPTR
23473 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
23474 goto done_label
23475 }
23476 if (!COUNT)
23477 goto done_label;
23478 copy 1 byte from SRCPTR to DESTPTR
23479 if (COUNT & 2)
23480 {
23481 copy 2 bytes from SRCPTR to DESTPTR
23482 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
23483 }
23484 }
23485 else
23486 {
23487 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
23488 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
23490 OLD_DESPTR = DESTPTR;
23491 Align DESTPTR up to DESIRED_ALIGN
23492 SRCPTR += DESTPTR - OLD_DESTPTR
23493 COUNT -= DEST_PTR - OLD_DESTPTR
23494 if (DYNAMIC_CHECK)
23495 Round COUNT down to multiple of SIZE
23496 << optional caller supplied zero size guard is here >>
23497 << optional caller suppplied dynamic check is here >>
23498 << caller supplied main copy loop is here >>
23499 }
23500 done_label:
23501 */
23502 static void
23515 {
23518 rtx modesize;
23520 rtx mode_value;
23522 /* Chose proper value to copy. */
23525 else
23529 /* See if block is big or small, handle small blocks. */
23531 {
23542 /* Handle sizes > 3. */
23549 /* Nothing to copy? Jump to DONE_LABEL if so */
23553 /* Do a byte copy. */
23557 else
23558 {
23561 }
23563 /* Handle sizes 2 and 3. */
23570 else
23571 {
23576 }
23582 }
23583 else
23587 /* Start memcpy for COUNT >= SIZE. */
23589 {
23592 }
23594 /* Copy first desired_align bytes. */
23600 {
23603 else
23604 {
23607 }
23610 }
23613 /* Copy last SIZE bytes. */
23620 else
23621 {
23627 }
23629 {
23633 else
23634 {
23637 }
23638 }
23640 /* Align destination. */
23642 {
23646 /* Align destptr up, place it to new register. */
23653 /* See how many bytes we skipped. */
23657 /* Adjust srcptr and count. */
23663 /* We copied at most size + prolog_size. */
23666 else
23669 /* Our loops always round down the bock size, but for dispatch to library
23670 we need precise value. */
23674 }
23675 else
23676 {
23678 /* Decrease count, so we won't end up copying last word twice. */
23682 else
23686 }
23687 }
23690 /* This function is like the previous one, except here we know how many bytes
23691 need to be copied. That allows us to update alignment not only of DST, which
23692 is returned, but also of SRC, which is passed as a pointer for that
23693 reason. */
23694 static rtx
23699 {
23707 {
23711 }
23716 {
23718 {
23720 {
23723 else
23725 }
23726 else
23729 }
23730 }
23737 {
23743 {
23746 {
23750 }
23755 }
23759 }
23762 }
23764 /* Return true if ALG can be used in current context.
23765 Assume we expand memset if MEMSET is true. */
23766 static bool
23768 {
23773 /* Algorithms using the rep prefix want at least edi and ecx;
23774 additionally, memset wants eax and memcpy wants esi. Don't
23775 consider such algorithms if the user has appropriated those
23776 registers for their own purposes. */
23783 }
23785 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
23786 static enum stringop_alg
23790 {
23801 /* Even if the string operation call is cold, we still might spend a lot
23802 of time processing large blocks. */
23808 else
23814 else
23817 /* See maximal size for user defined algorithm. */
23819 {
23826 }
23828 /* If expected size is not known but max size is small enough
23829 so inline version is a win, set expected size into
23830 the range. */
23835 /* If user specified the algorithm, honnor it if possible. */
23839 /* rep; movq or rep; movl is the smallest variant. */
23841 {
23846 else
23849 }
23850 /* Very tiny blocks are best handled via the loop, REP is expensive to
23851 setup. */
23855 {
23859 {
23860 /* We get here if the algorithms that were not libcall-based
23861 were rep-prefix based and we are unable to use rep prefixes
23862 based on global register usage. Break out of the loop and
23863 use the heuristic below. */
23867 {
23871 {
23874 }
23875 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
23876 last non-libcall inline algorithm. */
23878 {
23879 /* When the current size is best to be copied by a libcall,
23880 but we are still forced to inline, run the heuristic below
23881 that will pick code for medium sized blocks. */
23883 {
23886 }
23888 }
23890 {
23893 }
23894 }
23895 }
23896 }
23897 /* When asked to inline the call anyway, try to pick meaningful choice.
23898 We look for maximal size of block that is faster to copy by hand and
23899 take blocks of at most of that size guessing that average size will
23900 be roughly half of the block.
23902 If this turns out to be bad, we might simply specify the preferred
23903 choice in ix86_costs. */
23907 {
23910 /* If there aren't any usable algorithms, then recursing on
23911 smaller sizes isn't going to find anything. Just return the
23912 simple byte-at-a-time copy loop. */
23914 {
23915 /* Pick something reasonable. */
23919 }
23929 }
23932 }
23934 /* Decide on alignment. We know that the operand is already aligned to ALIGN
23935 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
23936 static int
23941 {
23952 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
23953 copying whole cacheline at once. */
23966 }
23969 /* Helper function for memcpy. For QImode value 0xXY produce
23970 0xXYXYXYXY of wide specified by MODE. This is essentially
23971 a * 0x10101010, but we can do slightly better than
23972 synth_mult by unwinding the sequence by hand on CPUs with
23973 slow multiply. */
23974 static rtx
23976 {
23978 rtx tmp;
23985 {
23993 }
24002 nops--;
24007 {
24011 OPTAB_DIRECT);
24012 }
24013 else
24014 {
24020 else
24022 else
24023 {
24026 reg =
24028 }
24038 }
24039 }
24041 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24042 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24043 alignment from ALIGN to DESIRED_ALIGN. */
24044 static rtx
24047 {
24048 rtx promoted_val;
24057 else
24061 }
24063 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24064 operations when profitable. The code depends upon architecture, block size
24065 and alignment, but always has one of the following overall structures:
24067 Aligned move sequence:
24069 1) Prologue guard: Conditional that jumps up to epilogues for small
24070 blocks that can be handled by epilogue alone. This is faster
24071 but also needed for correctness, since prologue assume the block
24072 is larger than the desired alignment.
24074 Optional dynamic check for size and libcall for large
24075 blocks is emitted here too, with -minline-stringops-dynamically.
24077 2) Prologue: copy first few bytes in order to get destination
24078 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24079 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24080 copied. We emit either a jump tree on power of two sized
24081 blocks, or a byte loop.
24083 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24084 with specified algorithm.
24086 4) Epilogue: code copying tail of the block that is too small to be
24087 handled by main body (or up to size guarded by prologue guard).
24089 Misaligned move sequence
24091 1) missaligned move prologue/epilogue containing:
24092 a) Prologue handling small memory blocks and jumping to done_label
24093 (skipped if blocks are known to be large enough)
24094 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24095 needed by single possibly misaligned move
24096 (skipped if alignment is not needed)
24097 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24099 2) Zero size guard dispatching to done_label, if needed
24101 3) dispatch to library call, if needed,
24103 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24104 with specified algorithm. */
24105 bool
24111 {
24112 rtx destreg;
24115 rtx tmp;
24131 /* TODO: Once value ranges are available, fill in proper data. */
24139 /* i386 can do misaligned access on reasonably increased cost. */
24143 /* ALIGN is the minimum of destination and source alignment, but we care here
24144 just about destination alignment. */
24152 else
24153 {
24162 }
24164 /* Make sure we don't need to care about overflow later on. */
24168 /* Step 0: Decide on preferred algorithm, desired alignment and
24169 size of chunks to be copied by main loop. */
24171 issetmem,
24178 /* For now vector-version of memset is generated only for memory zeroing, as
24179 creating of promoted vector value is very cheap in this case. */
24192 {
24211 /* Find the widest supported mode. */
24217 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24218 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24220 {
24225 }
24237 }
24245 /* Step 1: Prologue guard. */
24247 /* Alignment code needs count to be in register. */
24249 {
24252 {
24253 align_bytes
24257 else
24259 }
24262 }
24265 /* Misaligned move sequences handle both prologue and epilogue at once.
24266 Default code generation results in a smaller code for large alignments
24267 and also avoids redundant job when sizes are known precisely. */
24268 misaligned_prologue_used
24269 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24275 /* Do the cheap promotion to allow better CSE across the
24276 main loop and epilogue (ie one load of the big constant in the
24277 front of all code.
24278 For now the misaligned move sequences do not have fast path
24279 without broadcasting. */
24281 {
24283 {
24289 }
24290 else
24291 {
24294 }
24295 }
24296 /* Misaligned move sequences handles both prologues and epilogues at once.
24297 Default code generation results in smaller code for large alignments and
24298 also avoids redundant job when sizes are known precisely. */
24300 {
24301 /* Misaligned move prologue handled small blocks by itself. */
24302 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
24307 desired_align < align
24316 {
24317 /* It is possible that we copied enough so the main loop will not
24318 execute. */
24328 else
24330 }
24331 }
24332 /* Ensure that alignment prologue won't copy past end of block. */
24334 {
24336 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
24337 Make sure it is power of 2. */
24340 /* To improve performance of small blocks, we jump around the VAL
24341 promoting mode. This mean that if the promoted VAL is not constant,
24342 we might not use it in the epilogue and have to use byte
24343 loop variant. */
24348 {
24349 /* If main algorithm works on QImode, no epilogue is needed.
24350 For small sizes just don't align anything. */
24353 else
24355 }
24358 {
24365 else
24367 }
24368 }
24370 /* Emit code to decide on runtime whether library call or inline should be
24371 used. */
24373 {
24375 {
24377 {
24381 }
24382 }
24383 else
24384 {
24393 else
24397 }
24398 }
24400 /* Step 2: Alignment prologue. */
24401 /* Do the expensive promotion once we branched off the small blocks. */
24407 {
24409 {
24410 /* Except for the first move in prologue, we no longer know
24411 constant offset in aliasing info. It don't seems to worth
24412 the pain to maintain it for the first move, so throw away
24413 the info early. */
24420 issetmem);
24421 /* At most desired_align - align bytes are copied. */
24424 else
24426 }
24427 else
24428 {
24429 /* If we know how many bytes need to be stored before dst is
24430 sufficiently aligned, maintain aliasing info accurately. */
24432 srcreg,
24433 promoted_val,
24434 vec_promoted_val,
24435 desired_align,
24436 align_bytes,
24437 issetmem);
24444 }
24446 && !min_size
24451 {
24452 /* It is possible that we copied enough so the main loop will not
24453 execute. */
24463 else
24465 }
24466 }
24468 {
24475 }
24479 /* Step 3: Main loop. */
24482 {
24505 }
24506 /* Adjust properly the offset of src and dest memory for aliasing. */
24508 {
24514 }
24515 else
24516 {
24520 }
24522 /* Step 4: Epilogue to copy the remaining bytes. */
24523 epilogue:
24525 {
24526 /* When the main loop is done, COUNT_EXP might hold original count,
24527 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
24528 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
24529 bytes. Compensate if needed. */
24532 {
24533 tmp =
24536 OPTAB_DIRECT);
24539 }
24542 }
24545 {
24548 epilogue_size_needed);
24549 else
24550 {
24554 epilogue_size_needed);
24555 else
24557 epilogue_size_needed);
24558 }
24559 }
24563 }
24566 /* Expand the appropriate insns for doing strlen if not just doing
24567 repnz; scasb
24569 out = result, initialized with the start address
24570 align_rtx = alignment of the address.
24571 scratch = scratch register, initialized with the startaddress when
24572 not aligned, otherwise undefined
24574 This is just the body. It needs the initializations mentioned above and
24575 some address computing at the end. These things are done in i386.md. */
24577 static void
24579 {
24581 rtx tmp;
24586 rtx mem;
24589 rtx cmp;
24595 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
24597 /* Is there a known alignment and is it less than 4? */
24599 {
24602 /* Is there a known alignment and is it not 2? */
24604 {
24608 /* Leave just the 3 lower bits. */
24618 }
24619 else
24620 {
24621 /* Since the alignment is 2, we have to check 2 or 0 bytes;
24622 check if is aligned to 4 - byte. */
24629 }
24633 /* Now compare the bytes. */
24635 /* Compare the first n unaligned byte on a byte per byte basis. */
24639 /* Increment the address. */
24642 /* Not needed with an alignment of 2 */
24644 {
24648 end_0_label);
24653 }
24656 end_0_label);
24659 }
24661 /* Generate loop to check 4 bytes at a time. It is not a good idea to
24662 align this loop. It gives only huge programs, but does not help to
24663 speed up. */
24670 /* This formula yields a nonzero result iff one of the bytes is zero.
24671 This saves three branches inside loop and many cycles. */
24679 align_4_label);
24682 {
24688 /* If zero is not in the first two bytes, move two bytes forward. */
24694 reg,
24695 tmpreg)));
24696 /* Emit lea manually to avoid clobbering of flags. */
24704 reg2,
24705 out)));
24706 }
24707 else
24708 {
24710 /* Is zero in the first two bytes? */
24717 pc_rtx);
24721 /* Not in the first two. Move two bytes forward. */
24727 }
24729 /* Avoid branch in fixing the byte. */
24737 }
24739 /* Expand strlen. */
24741 bool
24743 {
24746 /* The generic case of strlen expander is long. Avoid it's
24747 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
24750 && !TARGET_INLINE_ALL_STRINGOPS
24760 {
24761 /* Well it seems that some optimizer does not combine a call like
24762 foo(strlen(bar), strlen(bar));
24763 when the move and the subtraction is done here. It does calculate
24764 the length just once when these instructions are done inside of
24765 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
24766 often used and I use one fewer register for the lifetime of
24767 output_strlen_unroll() this is better. */
24773 /* strlensi_unroll_1 returns the address of the zero at the end of
24774 the string, like memchr(), so compute the length by subtracting
24775 the start address. */
24777 }
24778 else
24779 {
24780 rtx unspec;
24782 /* Can't use this if the user has appropriated eax, ecx, or edi. */
24795 /* If .md starts supporting :P, this can be done in .md. */
24801 }
24803 }
24805 /* For given symbol (function) construct code to compute address of it's PLT
24806 entry in large x86-64 PIC model. */
24807 static rtx
24809 {
24822 }
24824 rtx
24826 rtx callarg2,
24828 {
24829 unsigned int const cregs_size
24840 {
24841 #if TARGET_MACHO
24844 #endif
24845 }
24846 else
24847 {
24848 /* Static functions and indirect calls don't need the pic register. */
24850 && (!TARGET_64BIT
24856 }
24859 {
24863 }
24866 && !TARGET_PECOFF
24874 {
24877 }
24885 {
24889 }
24893 {
24897 UNSPEC_MS_TO_SYSV_CALL);
24900 {
24906 }
24907 }
24916 }
24918 /* Output the assembly for a call instruction. */
24922 {
24928 {
24931 /* SEH epilogue detection requires the indirect branch case
24932 to include REX.W. */
24935 else
24940 }
24942 /* SEH unwinding can require an extra nop to be emitted in several
24943 circumstances. Determine if we have one of those. */
24945 {
24946 rtx i;
24949 {
24950 /* If we get to another real insn, we don't need the nop. */
24954 /* If we get to the epilogue note, prevent a catch region from
24955 being adjacent to the standard epilogue sequence. If non-
24956 call-exceptions, we'll have done this during epilogue emission. */
24958 && !flag_non_call_exceptions
24960 {
24963 }
24964 }
24966 /* If we didn't find a real insn following the call, prevent the
24967 unwinder from looking into the next function. */
24970 }
24974 else
24983 }
24984 \f
24985 /* Clear stack slot assignments remembered from previous functions.
24986 This is called from INIT_EXPANDERS once before RTL is emitted for each
24987 function. */
24991 {
24999 }
25001 /* Return a MEM corresponding to a stack slot with mode MODE.
25002 Allocate a new slot if necessary.
25004 The RTL for a function can have several slots available: N is
25005 which slot to use. */
25007 rtx
25009 {
25026 }
25028 static void
25030 {
25036 }
25037 \f
25038 /* Check whether x86 address PARTS is a pc-relative address. */
25040 static bool
25042 {
25050 {
25052 {
25069 }
25070 }
25072 }
25074 /* Calculate the length of the memory address in the instruction encoding.
25075 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25076 or other prefixes. We never generate addr32 prefix for LEA insn. */
25078 int
25080 {
25097 /* If this is not LEA instruction, add the length of addr32 prefix. */
25102 len++;
25116 /* Rule of thumb:
25117 - esp as the base always wants an index,
25118 - ebp as the base always wants a displacement,
25119 - r12 as the base always wants an index,
25120 - r13 as the base always wants a displacement. */
25122 /* Register Indirect. */
25124 {
25125 /* esp (for its index) and ebp (for its displacement) need
25126 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25127 code. */
25134 len++;
25135 }
25137 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25138 is not disp32, but disp32(%rip), so for disp32
25139 SIB byte is needed, unless print_operand_address
25140 optimizes it into disp32(%rip) or (%rip) is implied
25141 by UNSPEC. */
25143 {
25146 len++;
25147 }
25148 else
25149 {
25150 /* Find the length of the displacement constant. */
25152 {
25155 else
25157 }
25158 /* ebp always wants a displacement. Similarly r13. */
25160 len++;
25162 /* An index requires the two-byte modrm form.... */
25164 /* ...like esp (or r12), which always wants an index. */
25168 len++;
25169 }
25172 }
25174 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25175 is set, expect that insn have 8bit immediate alternative. */
25176 int
25178 {
25184 {
25189 {
25192 {
25204 }
25206 {
25209 }
25210 }
25212 {
25222 /* Immediates for DImode instructions are encoded
25223 as 32bit sign extended values. */
25229 }
25230 }
25232 }
25234 /* Compute default value for "length_address" attribute. */
25235 int
25237 {
25241 {
25252 }
25257 {
25260 {
25265 constraints++;
25268 ;
25269 /* Skip ignored operands. */
25272 }
25274 }
25276 }
25278 /* Compute default value for "length_vex" attribute. It includes
25279 2 or 3 byte VEX prefix and 1 opcode byte. */
25281 int
25283 {
25286 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
25287 byte VEX prefix. */
25291 /* We can always use 2 byte VEX prefix in 32bit. */
25299 {
25300 /* REX.W bit uses 3 byte VEX prefix. */
25304 }
25305 else
25306 {
25307 /* REX.X or REX.B bits use 3 byte VEX prefix. */
25311 }
25314 }
25315 \f
25316 /* Return the maximum number of instructions a cpu can issue. */
25318 static int
25320 {
25322 {
25353 }
25354 }
25356 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
25357 by DEP_INSN and nothing set by DEP_INSN. */
25359 static bool
25361 {
25364 /* Simplify the test for uninteresting insns. */
25372 {
25375 }
25380 {
25383 }
25384 else
25390 /* This test is true if the dependent insn reads the flags but
25391 not any other potentially set register. */
25399 }
25401 /* Return true iff USE_INSN has a memory address with operands set by
25402 SET_INSN. */
25404 bool
25406 {
25411 {
25414 }
25416 }
25418 /* Helper function for exact_store_load_dependency.
25419 Return true if addr is found in insn. */
25420 static bool
25422 {
25429 {
25435 CASE_CONST_ANY:
25444 }
25448 {
25450 {
25460 }
25461 }
25463 }
25465 /* Return true if there exists exact dependency for store & load, i.e.
25466 the same memory address is used in them. */
25467 static bool
25469 {
25483 }
25485 static int
25487 {
25493 /* Anti and output dependencies have zero cost on all CPUs. */
25499 /* If we can't recognize the insns, we can't really do anything. */
25507 {
25509 /* Address Generation Interlock adds a cycle of latency. */
25511 {
25522 }
25526 /* ??? Compares pair with jump/setcc. */
25530 /* Floating point stores require value to be ready one cycle earlier. */
25538 /* INT->FP conversion is expensive. */
25542 /* There is one cycle extra latency between an FP op and a store. */
25552 /* Show ability of reorder buffer to hide latency of load by executing
25553 in parallel with previous instruction in case
25554 previous instruction is not needed to compute the address. */
25557 {
25558 /* Claim moves to take one cycle, as core can issue one load
25559 at time and the next load can start cycle later. */
25564 cost--;
25565 }
25569 /* The esp dependency is resolved before
25570 the instruction is really finished. */
25575 /* INT->FP conversion is expensive. */
25581 /* Show ability of reorder buffer to hide latency of load by executing
25582 in parallel with previous instruction in case
25583 previous instruction is not needed to compute the address. */
25586 {
25587 /* Claim moves to take one cycle, as core can issue one load
25588 at time and the next load can start cycle later. */
25594 else
25596 }
25607 /* Stack engine allows to execute push&pop instructions in parall. */
25611 /* FALLTHRU */
25617 /* Show ability of reorder buffer to hide latency of load by executing
25618 in parallel with previous instruction in case
25619 previous instruction is not needed to compute the address. */
25622 {
25626 /* Because of the difference between the length of integer and
25627 floating unit pipeline preparation stages, the memory operands
25628 for floating point are cheaper.
25630 ??? For Athlon it the difference is most probably 2. */
25633 else
25638 else
25640 }
25647 /* Stack engine allows to execute push&pop instructions in parall. */
25654 /* Show ability of reorder buffer to hide latency of load by executing
25655 in parallel with previous instruction in case
25656 previous instruction is not needed to compute the address. */
25659 {
25662 else
25664 }
25672 /* Increase cost of integer loads. */
25675 {
25678 {
25681 else
25682 {
25683 /* Increase cost of ld/st for short int types only
25684 because of store forwarding issue. */
25688 {
25689 /* Increase cost of store/load insn if exact
25690 dependence exists and it is load insn. */
25695 }
25696 }
25697 }
25698 }
25702 }
25705 }
25707 /* How many alternative schedules to try. This should be as wide as the
25708 scheduling freedom in the DFA, but no wider. Making this value too
25709 large results extra work for the scheduler. */
25711 static int
25713 {
25715 {
25727 /* We use lookahead value 4 for BD both before and after reload
25728 schedules. Plan is to have value 8 included for O3. */
25738 /* Generally, we want haifa-sched:max_issue() to look ahead as far
25739 as many instructions can be executed on a cycle, i.e.,
25740 issue_rate. I wonder why tuning for many CPUs does not do this. */
25743 /* Don't use lookahead for pre-reload schedule to save compile time. */
25748 }
25749 }
25751 /* Return true if target platform supports macro-fusion. */
25753 static bool
25755 {
25757 }
25759 /* Check whether current microarchitecture support macro fusion
25760 for insn pair "CONDGEN + CONDJMP". Refer to
25761 "Intel Architectures Optimization Reference Manual". */
25763 static bool
25765 {
25784 else
25785 {
25790 {
25794 else
25796 }
25797 }
25804 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
25805 supported. */
25812 /* No fusion for RIP-relative address. */
25819 ix86_address parts;
25825 }
25830 /* Check whether conditional jump use Sign or Overflow Flags. */
25838 /* Return true for TYPE_TEST and TYPE_ICMP. */
25843 /* The following is the case that macro-fusion for alu + jmp. */
25847 /* No fusion for alu op with memory destination operand. */
25852 /* Macro-fusion for inc/dec + unsigned conditional jump is not
25853 supported. */
25862 }
25864 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
25865 execution. It is applied if
25866 (1) IMUL instruction is on the top of list;
25867 (2) There exists the only producer of independent IMUL instruction in
25868 ready list.
25869 Return index of IMUL producer if it was found and -1 otherwise. */
25870 static int
25872 {
25874 sd_iterator_def sd_it;
25875 dep_t dep;
25882 /* Check that IMUL instruction is on the top of ready list. */
25891 /* Search for producer of independent IMUL instruction. */
25893 {
25897 /* Skip IMUL instruction. */
25907 {
25908 rtx con;
25919 {
25920 sd_iterator_def sd_it1;
25921 dep_t dep1;
25922 /* Check if there is no other dependee for IMUL. */
25925 {
25926 rtx pro;
25932 }
25935 }
25936 }
25939 }
25941 }
25943 /* Try to find the best candidate on the top of ready list if two insns
25944 have the same priority - candidate is best if its dependees were
25945 scheduled earlier. Applied for Silvermont only.
25946 Return true if top 2 insns must be interchanged. */
25947 static bool
25949 {
25952 rtx set;
25953 sd_iterator_def sd_it;
25954 dep_t dep;
25957 #define INSN_TICK(INSN) (HID (INSN)->tick)
25978 {
25981 /* Determine winner more precise. */
25983 {
25984 rtx pro;
25990 }
25992 {
25993 rtx pro;
25999 }
26002 {
26003 /* Determine winner - load must win. */
26009 }
26011 }
26013 #undef INSN_TICK
26014 }
26016 /* Perform possible reodering of ready list for Atom/Silvermont only.
26017 Return issue rate. */
26018 static int
26021 {
26025 rtx insn;
26028 /* Set up issue rate. */
26031 /* Do reodering for BONNELL/SILVERMONT only. */
26035 /* Nothing to do if ready list contains only 1 instruction. */
26039 /* Do reodering for post-reload scheduler only. */
26044 {
26049 /* Put IMUL producer (ready[index]) at the top of ready list. */
26055 }
26057 {
26061 /* Swap 2 top elements of ready list. */
26065 }
26067 }
26069 static bool
26072 /* Returns true if lhs of insn is HW function argument register and set up
26073 is_spilled to true if it is likely spilled HW register. */
26074 static bool
26076 {
26077 rtx dst;
26081 /* Call instructions are not movable, ignore it. */
26092 {
26093 /* Is it likely spilled HW register? */
26098 }
26100 }
26102 /* Add output dependencies for chain of function adjacent arguments if only
26103 there is a move to likely spilled HW register. Return first argument
26104 if at least one dependence was added or NULL otherwise. */
26105 static rtx
26107 {
26108 rtx insn;
26115 /* Find nearest to call argument passing instruction. */
26117 {
26126 }
26130 {
26137 {
26140 }
26142 {
26143 /* Add output depdendence between two function arguments if chain
26144 of output arguments contains likely spilled HW registers. */
26148 }
26149 else
26151 }
26155 }
26157 /* Add output or anti dependency from insn to first_arg to restrict its code
26158 motion. */
26159 static void
26161 {
26162 rtx set;
26163 rtx tmp;
26170 {
26171 /* Add output dependency to the first function argument. */
26174 }
26175 /* Add anti dependency. */
26177 }
26179 /* Avoid cross block motion of function argument through adding dependency
26180 from the first non-jump instruction in bb. */
26181 static void
26183 {
26187 {
26189 {
26192 {
26195 }
26196 }
26200 }
26201 }
26203 /* Hook for pre-reload schedule - avoid motion of function arguments
26204 passed in likely spilled HW registers. */
26205 static void
26207 {
26208 rtx insn;
26216 {
26219 {
26220 /* Add dependee for first argument to predecessors if only
26221 region contains more than one block. */
26225 /* Skip trivial regions and region head blocks that can have
26226 predecessors outside of region. */
26228 {
26229 edge e;
26230 edge_iterator ei;
26231 /* Assume that region is SCC, i.e. all immediate predecessors
26232 of non-head block are in the same region. */
26234 {
26235 /* Avoid creating of loop-carried dependencies through
26236 using topological odering in region. */
26239 }
26240 }
26244 }
26245 }
26248 }
26250 /* Hook for pre-reload schedule - set priority of moves from likely spilled
26251 HW registers to maximum, to schedule them at soon as possible. These are
26252 moves from function argument registers at the top of the function entry
26253 and moves from function return value registers after call. */
26254 static int
26256 {
26257 rtx set;
26267 {
26274 }
26277 }
26279 /* Model decoder of Core 2/i7.
26280 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
26281 track the instruction fetch block boundaries and make sure that long
26282 (9+ bytes) instructions are assigned to D0. */
26284 /* Maximum length of an insn that can be handled by
26285 a secondary decoder unit. '8' for Core 2/i7. */
26288 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
26289 '16' for Core 2/i7. */
26292 /* Maximum number of instructions decoder can handle per cycle.
26293 '6' for Core 2/i7. */
26297 ix86_first_cycle_multipass_data_t;
26299 const_ix86_first_cycle_multipass_data_t;
26301 /* A variable to store target state across calls to max_issue within
26302 one cycle. */
26306 /* Initialize DATA. */
26307 static void
26309 {
26310 ix86_first_cycle_multipass_data_t data
26317 }
26319 /* Advancing the cycle; reset ifetch block counts. */
26320 static void
26322 {
26329 }
26333 /* Filter out insns from ready_try that the core will not be able to issue
26334 on current cycle due to decoder. */
26335 static void
26336 core2i7_first_cycle_multipass_filter_ready_try
26339 {
26341 {
26342 rtx insn;
26352 (!first_cycle_insn_p
26354 /* ... or it would not fit into the ifetch block ... */
26356 /* ... or the decoder is full already ... */
26358 /* ... mask the insn out. */
26359 {
26364 }
26365 }
26366 }
26368 /* Prepare for a new round of multipass lookahead scheduling. */
26369 static void
26372 {
26373 ix86_first_cycle_multipass_data_t data
26375 const_ix86_first_cycle_multipass_data_t prev_data
26378 /* Restore the state from the end of the previous round. */
26382 /* Filter instructions that cannot be issued on current cycle due to
26383 decoder restrictions. */
26385 first_cycle_insn_p);
26386 }
26388 /* INSN is being issued in current solution. Account for its impact on
26389 the decoder model. */
26390 static void
26393 {
26394 ix86_first_cycle_multipass_data_t data
26396 const_ix86_first_cycle_multipass_data_t prev_data
26406 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
26408 {
26411 }
26413 {
26417 }
26420 /* Filter out insns from ready_try that the core will not be able to issue
26421 on current cycle due to decoder. */
26424 }
26426 /* Revert the effect on ready_try. */
26427 static void
26431 {
26432 const_ix86_first_cycle_multipass_data_t data
26435 sbitmap_iterator sbi;
26439 {
26441 }
26442 }
26444 /* Save the result of multipass lookahead scheduling for the next round. */
26445 static void
26447 {
26448 const_ix86_first_cycle_multipass_data_t data
26450 ix86_first_cycle_multipass_data_t next_data
26454 {
26457 }
26458 }
26460 /* Deallocate target data. */
26461 static void
26463 {
26464 ix86_first_cycle_multipass_data_t data
26468 {
26472 }
26473 }
26475 /* Prepare for scheduling pass. */
26476 static void
26480 {
26481 /* Install scheduling hooks for current CPU. Some of these hooks are used
26482 in time-critical parts of the scheduler, so we only set them up when
26483 they are actually used. */
26485 {
26490 /* Do not perform multipass scheduling for pre-reload schedule
26491 to save compile time. */
26493 {
26509 /* Set decoder parameters. */
26514 }
26515 /* ... Fall through ... */
26525 }
26526 }
26528 \f
26529 /* Compute the alignment given to a constant that is being placed in memory.
26530 EXP is the constant and ALIGN is the alignment that the object would
26531 ordinarily have.
26532 The value of this function is used instead of that alignment to align
26533 the object. */
26535 int
26537 {
26540 {
26545 }
26551 }
26553 /* Compute the alignment for a static variable.
26554 TYPE is the data type, and ALIGN is the alignment that
26555 the object would ordinarily have. The value of this function is used
26556 instead of that alignment to align the object. */
26558 int
26560 {
26561 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
26562 for symbols from other compilation units or symbols that don't need
26563 to bind locally. In order to preserve some ABI compatibility with
26564 those compilers, ensure we don't decrease alignment from what we
26565 used to assume. */
26567 int max_align_compat
26570 /* A data structure, equal or greater than the size of a cache line
26571 (64 bytes in the Pentium 4 and other recent Intel processors, including
26572 processors based on Intel Core microarchitecture) should be aligned
26573 so that its base address is a multiple of a cache line size. */
26575 int max_align
26585 {
26594 }
26596 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
26597 to 16byte boundary. */
26599 {
26606 }
26612 {
26617 }
26619 {
26626 }
26631 {
26636 }
26639 {
26644 }
26647 }
26649 /* Compute the alignment for a local variable or a stack slot. EXP is
26650 the data type or decl itself, MODE is the widest mode available and
26651 ALIGN is the alignment that the object would ordinarily have. The
26652 value of this macro is used instead of that alignment to align the
26653 object. */
26655 unsigned int
26658 {
26662 {
26665 }
26666 else
26667 {
26670 }
26672 /* Don't do dynamic stack realignment for long long objects with
26673 -mpreferred-stack-boundary=2. */
26682 /* If TYPE is NULL, we are allocating a stack slot for caller-save
26683 register in MODE. We will return the largest alignment of XF
26684 and DF. */
26686 {
26690 }
26692 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
26693 to 16byte boundary. Exact wording is:
26695 An array uses the same alignment as its elements, except that a local or
26696 global array variable of length at least 16 bytes or
26697 a C99 variable-length array variable always has alignment of at least 16 bytes.
26699 This was added to allow use of aligned SSE instructions at arrays. This
26700 rule is meant for static storage (where compiler can not do the analysis
26701 by itself). We follow it for automatic variables only when convenient.
26702 We fully control everything in the function compiled and functions from
26703 other unit can not rely on the alignment.
26705 Exclude va_list type. It is the common case of local array where
26706 we can not benefit from the alignment.
26708 TODO: Probably one should optimize for size only when var is not escaping. */
26711 {
26721 }
26723 {
26728 }
26730 {
26736 }
26741 {
26746 }
26749 {
26755 }
26757 }
26759 /* Compute the minimum required alignment for dynamic stack realignment
26760 purposes for a local variable, parameter or a stack slot. EXP is
26761 the data type or decl itself, MODE is its mode and ALIGN is the
26762 alignment that the object would ordinarily have. */
26764 unsigned int
26767 {
26771 {
26774 }
26775 else
26776 {
26779 }
26784 /* Don't do dynamic stack realignment for long long objects with
26785 -mpreferred-stack-boundary=2. */
26792 }
26793 \f
26794 /* Find a location for the static chain incoming to a nested function.
26795 This is a register, unless all free registers are used by arguments. */
26797 static rtx
26799 {
26806 {
26807 /* We always use R10 in 64-bit mode. */
26809 }
26810 else
26811 {
26812 tree fntype;
26815 /* By default in 32-bit mode we use ECX to pass the static chain. */
26821 {
26822 /* Fastcall functions use ecx/edx for arguments, which leaves
26823 us with EAX for the static chain.
26824 Thiscall functions use ecx for arguments, which also
26825 leaves us with EAX for the static chain. */
26827 }
26829 {
26830 /* Thiscall functions use ecx for arguments, which leaves
26831 us with EAX and EDX for the static chain.
26832 We are using for abi-compatibility EAX. */
26834 }
26836 {
26837 /* For regparm 3, we have no free call-clobbered registers in
26838 which to store the static chain. In order to implement this,
26839 we have the trampoline push the static chain to the stack.
26840 However, we can't push a value below the return address when
26841 we call the nested function directly, so we have to use an
26842 alternate entry point. For this we use ESI, and have the
26843 alternate entry point push ESI, so that things appear the
26844 same once we're executing the nested function. */
26846 {
26852 }
26854 }
26855 }
26858 }
26860 /* Emit RTL insns to initialize the variable parts of a trampoline.
26861 FNDECL is the decl of the target address; M_TRAMP is a MEM for
26862 the trampoline, and CHAIN_VALUE is an RTX for the static chain
26863 to be passed to the target function. */
26865 static void
26867 {
26875 {
26878 /* Load the function address to r11. Try to load address using
26879 the shorter movl instead of movabs. We may want to support
26880 movq for kernel mode, but kernel does not use trampolines at
26881 the moment. FNADDR is a 32bit address and may not be in
26882 DImode when ptr_mode == SImode. Always use movl in this
26883 case. */
26886 {
26895 }
26896 else
26897 {
26904 }
26906 /* Load static chain using movabs to r10. Use the shorter movl
26907 instead of movabs when ptr_mode == SImode. */
26909 {
26912 }
26913 else
26914 {
26917 }
26926 /* Jump to r11; the last (unused) byte is a nop, only there to
26927 pad the write out to a single 32-bit store. */
26931 }
26932 else
26933 {
26936 /* Depending on the static chain location, either load a register
26937 with a constant, or push the constant to the stack. All of the
26938 instructions are the same size. */
26941 {
26943 {
26950 }
26951 }
26952 else
26967 /* Compute offset from the end of the jmp to the target function.
26968 In the case in which the trampoline stores the static chain on
26969 the stack, we need to skip the first insn which pushes the
26970 (call-saved) register static chain; this push is 1 byte. */
26977 }
26981 #ifdef HAVE_ENABLE_EXECUTE_STACK
26982 #ifdef CHECK_EXECUTE_STACK_ENABLED
26984 #endif
26987 #endif
26988 }
26989 \f
26990 /* The following file contains several enumerations and data structures
26991 built from the definitions in i386-builtin-types.def. */
26995 /* Table for the ix86 builtin non-function types. */
26998 /* Retrieve an element from the above table, building some of
26999 the types lazily. */
27001 static tree
27003 {
27015 {
27023 }
27024 else
27025 {
27031 else
27039 }
27043 }
27045 /* Table for the ix86 builtin function types. */
27048 /* Retrieve an element from the above table, building some of
27049 the types lazily. */
27051 static tree
27053 {
27054 tree type;
27063 {
27071 {
27074 }
27077 }
27078 else
27079 {
27085 }
27089 }
27092 /* Codes for all the SSE/MMX builtins. */
27093 enum ix86_builtins
27094 {
27095 IX86_BUILTIN_ADDPS,
27096 IX86_BUILTIN_ADDSS,
27097 IX86_BUILTIN_DIVPS,
27098 IX86_BUILTIN_DIVSS,
27099 IX86_BUILTIN_MULPS,
27100 IX86_BUILTIN_MULSS,
27101 IX86_BUILTIN_SUBPS,
27102 IX86_BUILTIN_SUBSS,
27104 IX86_BUILTIN_CMPEQPS,
27105 IX86_BUILTIN_CMPLTPS,
27106 IX86_BUILTIN_CMPLEPS,
27107 IX86_BUILTIN_CMPGTPS,
27108 IX86_BUILTIN_CMPGEPS,
27109 IX86_BUILTIN_CMPNEQPS,
27110 IX86_BUILTIN_CMPNLTPS,
27111 IX86_BUILTIN_CMPNLEPS,
27112 IX86_BUILTIN_CMPNGTPS,
27113 IX86_BUILTIN_CMPNGEPS,
27114 IX86_BUILTIN_CMPORDPS,
27115 IX86_BUILTIN_CMPUNORDPS,
27116 IX86_BUILTIN_CMPEQSS,
27117 IX86_BUILTIN_CMPLTSS,
27118 IX86_BUILTIN_CMPLESS,
27119 IX86_BUILTIN_CMPNEQSS,
27120 IX86_BUILTIN_CMPNLTSS,
27121 IX86_BUILTIN_CMPNLESS,
27122 IX86_BUILTIN_CMPORDSS,
27123 IX86_BUILTIN_CMPUNORDSS,
27125 IX86_BUILTIN_COMIEQSS,
27126 IX86_BUILTIN_COMILTSS,
27127 IX86_BUILTIN_COMILESS,
27128 IX86_BUILTIN_COMIGTSS,
27129 IX86_BUILTIN_COMIGESS,
27130 IX86_BUILTIN_COMINEQSS,
27131 IX86_BUILTIN_UCOMIEQSS,
27132 IX86_BUILTIN_UCOMILTSS,
27133 IX86_BUILTIN_UCOMILESS,
27134 IX86_BUILTIN_UCOMIGTSS,
27135 IX86_BUILTIN_UCOMIGESS,
27136 IX86_BUILTIN_UCOMINEQSS,
27138 IX86_BUILTIN_CVTPI2PS,
27139 IX86_BUILTIN_CVTPS2PI,
27140 IX86_BUILTIN_CVTSI2SS,
27141 IX86_BUILTIN_CVTSI642SS,
27142 IX86_BUILTIN_CVTSS2SI,
27143 IX86_BUILTIN_CVTSS2SI64,
27144 IX86_BUILTIN_CVTTPS2PI,
27145 IX86_BUILTIN_CVTTSS2SI,
27146 IX86_BUILTIN_CVTTSS2SI64,
27148 IX86_BUILTIN_MAXPS,
27149 IX86_BUILTIN_MAXSS,
27150 IX86_BUILTIN_MINPS,
27151 IX86_BUILTIN_MINSS,
27153 IX86_BUILTIN_LOADUPS,
27154 IX86_BUILTIN_STOREUPS,
27155 IX86_BUILTIN_MOVSS,
27157 IX86_BUILTIN_MOVHLPS,
27158 IX86_BUILTIN_MOVLHPS,
27159 IX86_BUILTIN_LOADHPS,
27160 IX86_BUILTIN_LOADLPS,
27161 IX86_BUILTIN_STOREHPS,
27162 IX86_BUILTIN_STORELPS,
27164 IX86_BUILTIN_MASKMOVQ,
27165 IX86_BUILTIN_MOVMSKPS,
27166 IX86_BUILTIN_PMOVMSKB,
27168 IX86_BUILTIN_MOVNTPS,
27169 IX86_BUILTIN_MOVNTQ,
27171 IX86_BUILTIN_LOADDQU,
27172 IX86_BUILTIN_STOREDQU,
27174 IX86_BUILTIN_PACKSSWB,
27175 IX86_BUILTIN_PACKSSDW,
27176 IX86_BUILTIN_PACKUSWB,
27178 IX86_BUILTIN_PADDB,
27179 IX86_BUILTIN_PADDW,
27180 IX86_BUILTIN_PADDD,
27181 IX86_BUILTIN_PADDQ,
27182 IX86_BUILTIN_PADDSB,
27183 IX86_BUILTIN_PADDSW,
27184 IX86_BUILTIN_PADDUSB,
27185 IX86_BUILTIN_PADDUSW,
27186 IX86_BUILTIN_PSUBB,
27187 IX86_BUILTIN_PSUBW,
27188 IX86_BUILTIN_PSUBD,
27189 IX86_BUILTIN_PSUBQ,
27190 IX86_BUILTIN_PSUBSB,
27191 IX86_BUILTIN_PSUBSW,
27192 IX86_BUILTIN_PSUBUSB,
27193 IX86_BUILTIN_PSUBUSW,
27195 IX86_BUILTIN_PAND,
27196 IX86_BUILTIN_PANDN,
27197 IX86_BUILTIN_POR,
27198 IX86_BUILTIN_PXOR,
27200 IX86_BUILTIN_PAVGB,
27201 IX86_BUILTIN_PAVGW,
27203 IX86_BUILTIN_PCMPEQB,
27204 IX86_BUILTIN_PCMPEQW,
27205 IX86_BUILTIN_PCMPEQD,
27206 IX86_BUILTIN_PCMPGTB,
27207 IX86_BUILTIN_PCMPGTW,
27208 IX86_BUILTIN_PCMPGTD,
27210 IX86_BUILTIN_PMADDWD,
27212 IX86_BUILTIN_PMAXSW,
27213 IX86_BUILTIN_PMAXUB,
27214 IX86_BUILTIN_PMINSW,
27215 IX86_BUILTIN_PMINUB,
27217 IX86_BUILTIN_PMULHUW,
27218 IX86_BUILTIN_PMULHW,
27219 IX86_BUILTIN_PMULLW,
27221 IX86_BUILTIN_PSADBW,
27222 IX86_BUILTIN_PSHUFW,
27224 IX86_BUILTIN_PSLLW,
27225 IX86_BUILTIN_PSLLD,
27226 IX86_BUILTIN_PSLLQ,
27227 IX86_BUILTIN_PSRAW,
27228 IX86_BUILTIN_PSRAD,
27229 IX86_BUILTIN_PSRLW,
27230 IX86_BUILTIN_PSRLD,
27231 IX86_BUILTIN_PSRLQ,
27232 IX86_BUILTIN_PSLLWI,
27233 IX86_BUILTIN_PSLLDI,
27234 IX86_BUILTIN_PSLLQI,
27235 IX86_BUILTIN_PSRAWI,
27236 IX86_BUILTIN_PSRADI,
27237 IX86_BUILTIN_PSRLWI,
27238 IX86_BUILTIN_PSRLDI,
27239 IX86_BUILTIN_PSRLQI,
27241 IX86_BUILTIN_PUNPCKHBW,
27242 IX86_BUILTIN_PUNPCKHWD,
27243 IX86_BUILTIN_PUNPCKHDQ,
27244 IX86_BUILTIN_PUNPCKLBW,
27245 IX86_BUILTIN_PUNPCKLWD,
27246 IX86_BUILTIN_PUNPCKLDQ,
27248 IX86_BUILTIN_SHUFPS,
27250 IX86_BUILTIN_RCPPS,
27251 IX86_BUILTIN_RCPSS,
27252 IX86_BUILTIN_RSQRTPS,
27253 IX86_BUILTIN_RSQRTPS_NR,
27254 IX86_BUILTIN_RSQRTSS,
27255 IX86_BUILTIN_RSQRTF,
27256 IX86_BUILTIN_SQRTPS,
27257 IX86_BUILTIN_SQRTPS_NR,
27258 IX86_BUILTIN_SQRTSS,
27260 IX86_BUILTIN_UNPCKHPS,
27261 IX86_BUILTIN_UNPCKLPS,
27263 IX86_BUILTIN_ANDPS,
27264 IX86_BUILTIN_ANDNPS,
27265 IX86_BUILTIN_ORPS,
27266 IX86_BUILTIN_XORPS,
27268 IX86_BUILTIN_EMMS,
27269 IX86_BUILTIN_LDMXCSR,
27270 IX86_BUILTIN_STMXCSR,
27271 IX86_BUILTIN_SFENCE,
27273 IX86_BUILTIN_FXSAVE,
27274 IX86_BUILTIN_FXRSTOR,
27275 IX86_BUILTIN_FXSAVE64,
27276 IX86_BUILTIN_FXRSTOR64,
27278 IX86_BUILTIN_XSAVE,
27279 IX86_BUILTIN_XRSTOR,
27280 IX86_BUILTIN_XSAVE64,
27281 IX86_BUILTIN_XRSTOR64,
27283 IX86_BUILTIN_XSAVEOPT,
27284 IX86_BUILTIN_XSAVEOPT64,
27286 /* 3DNow! Original */
27287 IX86_BUILTIN_FEMMS,
27288 IX86_BUILTIN_PAVGUSB,
27289 IX86_BUILTIN_PF2ID,
27290 IX86_BUILTIN_PFACC,
27291 IX86_BUILTIN_PFADD,
27292 IX86_BUILTIN_PFCMPEQ,
27293 IX86_BUILTIN_PFCMPGE,
27294 IX86_BUILTIN_PFCMPGT,
27295 IX86_BUILTIN_PFMAX,
27296 IX86_BUILTIN_PFMIN,
27297 IX86_BUILTIN_PFMUL,
27298 IX86_BUILTIN_PFRCP,
27299 IX86_BUILTIN_PFRCPIT1,
27300 IX86_BUILTIN_PFRCPIT2,
27301 IX86_BUILTIN_PFRSQIT1,
27302 IX86_BUILTIN_PFRSQRT,
27303 IX86_BUILTIN_PFSUB,
27304 IX86_BUILTIN_PFSUBR,
27305 IX86_BUILTIN_PI2FD,
27306 IX86_BUILTIN_PMULHRW,
27308 /* 3DNow! Athlon Extensions */
27309 IX86_BUILTIN_PF2IW,
27310 IX86_BUILTIN_PFNACC,
27311 IX86_BUILTIN_PFPNACC,
27312 IX86_BUILTIN_PI2FW,
27313 IX86_BUILTIN_PSWAPDSI,
27314 IX86_BUILTIN_PSWAPDSF,
27316 /* SSE2 */
27317 IX86_BUILTIN_ADDPD,
27318 IX86_BUILTIN_ADDSD,
27319 IX86_BUILTIN_DIVPD,
27320 IX86_BUILTIN_DIVSD,
27321 IX86_BUILTIN_MULPD,
27322 IX86_BUILTIN_MULSD,
27323 IX86_BUILTIN_SUBPD,
27324 IX86_BUILTIN_SUBSD,
27326 IX86_BUILTIN_CMPEQPD,
27327 IX86_BUILTIN_CMPLTPD,
27328 IX86_BUILTIN_CMPLEPD,
27329 IX86_BUILTIN_CMPGTPD,
27330 IX86_BUILTIN_CMPGEPD,
27331 IX86_BUILTIN_CMPNEQPD,
27332 IX86_BUILTIN_CMPNLTPD,
27333 IX86_BUILTIN_CMPNLEPD,
27334 IX86_BUILTIN_CMPNGTPD,
27335 IX86_BUILTIN_CMPNGEPD,
27336 IX86_BUILTIN_CMPORDPD,
27337 IX86_BUILTIN_CMPUNORDPD,
27338 IX86_BUILTIN_CMPEQSD,
27339 IX86_BUILTIN_CMPLTSD,
27340 IX86_BUILTIN_CMPLESD,
27341 IX86_BUILTIN_CMPNEQSD,
27342 IX86_BUILTIN_CMPNLTSD,
27343 IX86_BUILTIN_CMPNLESD,
27344 IX86_BUILTIN_CMPORDSD,
27345 IX86_BUILTIN_CMPUNORDSD,
27347 IX86_BUILTIN_COMIEQSD,
27348 IX86_BUILTIN_COMILTSD,
27349 IX86_BUILTIN_COMILESD,
27350 IX86_BUILTIN_COMIGTSD,
27351 IX86_BUILTIN_COMIGESD,
27352 IX86_BUILTIN_COMINEQSD,
27353 IX86_BUILTIN_UCOMIEQSD,
27354 IX86_BUILTIN_UCOMILTSD,
27355 IX86_BUILTIN_UCOMILESD,
27356 IX86_BUILTIN_UCOMIGTSD,
27357 IX86_BUILTIN_UCOMIGESD,
27358 IX86_BUILTIN_UCOMINEQSD,
27360 IX86_BUILTIN_MAXPD,
27361 IX86_BUILTIN_MAXSD,
27362 IX86_BUILTIN_MINPD,
27363 IX86_BUILTIN_MINSD,
27365 IX86_BUILTIN_ANDPD,
27366 IX86_BUILTIN_ANDNPD,
27367 IX86_BUILTIN_ORPD,
27368 IX86_BUILTIN_XORPD,
27370 IX86_BUILTIN_SQRTPD,
27371 IX86_BUILTIN_SQRTSD,
27373 IX86_BUILTIN_UNPCKHPD,
27374 IX86_BUILTIN_UNPCKLPD,
27376 IX86_BUILTIN_SHUFPD,
27378 IX86_BUILTIN_LOADUPD,
27379 IX86_BUILTIN_STOREUPD,
27380 IX86_BUILTIN_MOVSD,
27382 IX86_BUILTIN_LOADHPD,
27383 IX86_BUILTIN_LOADLPD,
27385 IX86_BUILTIN_CVTDQ2PD,
27386 IX86_BUILTIN_CVTDQ2PS,
27388 IX86_BUILTIN_CVTPD2DQ,
27389 IX86_BUILTIN_CVTPD2PI,
27390 IX86_BUILTIN_CVTPD2PS,
27391 IX86_BUILTIN_CVTTPD2DQ,
27392 IX86_BUILTIN_CVTTPD2PI,
27394 IX86_BUILTIN_CVTPI2PD,
27395 IX86_BUILTIN_CVTSI2SD,
27396 IX86_BUILTIN_CVTSI642SD,
27398 IX86_BUILTIN_CVTSD2SI,
27399 IX86_BUILTIN_CVTSD2SI64,
27400 IX86_BUILTIN_CVTSD2SS,
27401 IX86_BUILTIN_CVTSS2SD,
27402 IX86_BUILTIN_CVTTSD2SI,
27403 IX86_BUILTIN_CVTTSD2SI64,
27405 IX86_BUILTIN_CVTPS2DQ,
27406 IX86_BUILTIN_CVTPS2PD,
27407 IX86_BUILTIN_CVTTPS2DQ,
27409 IX86_BUILTIN_MOVNTI,
27410 IX86_BUILTIN_MOVNTI64,
27411 IX86_BUILTIN_MOVNTPD,
27412 IX86_BUILTIN_MOVNTDQ,
27414 IX86_BUILTIN_MOVQ128,
27416 /* SSE2 MMX */
27417 IX86_BUILTIN_MASKMOVDQU,
27418 IX86_BUILTIN_MOVMSKPD,
27419 IX86_BUILTIN_PMOVMSKB128,
27421 IX86_BUILTIN_PACKSSWB128,
27422 IX86_BUILTIN_PACKSSDW128,
27423 IX86_BUILTIN_PACKUSWB128,
27425 IX86_BUILTIN_PADDB128,
27426 IX86_BUILTIN_PADDW128,
27427 IX86_BUILTIN_PADDD128,
27428 IX86_BUILTIN_PADDQ128,
27429 IX86_BUILTIN_PADDSB128,
27430 IX86_BUILTIN_PADDSW128,
27431 IX86_BUILTIN_PADDUSB128,
27432 IX86_BUILTIN_PADDUSW128,
27433 IX86_BUILTIN_PSUBB128,
27434 IX86_BUILTIN_PSUBW128,
27435 IX86_BUILTIN_PSUBD128,
27436 IX86_BUILTIN_PSUBQ128,
27437 IX86_BUILTIN_PSUBSB128,
27438 IX86_BUILTIN_PSUBSW128,
27439 IX86_BUILTIN_PSUBUSB128,
27440 IX86_BUILTIN_PSUBUSW128,
27442 IX86_BUILTIN_PAND128,
27443 IX86_BUILTIN_PANDN128,
27444 IX86_BUILTIN_POR128,
27445 IX86_BUILTIN_PXOR128,
27447 IX86_BUILTIN_PAVGB128,
27448 IX86_BUILTIN_PAVGW128,
27450 IX86_BUILTIN_PCMPEQB128,
27451 IX86_BUILTIN_PCMPEQW128,
27452 IX86_BUILTIN_PCMPEQD128,
27453 IX86_BUILTIN_PCMPGTB128,
27454 IX86_BUILTIN_PCMPGTW128,
27455 IX86_BUILTIN_PCMPGTD128,
27457 IX86_BUILTIN_PMADDWD128,
27459 IX86_BUILTIN_PMAXSW128,
27460 IX86_BUILTIN_PMAXUB128,
27461 IX86_BUILTIN_PMINSW128,
27462 IX86_BUILTIN_PMINUB128,
27464 IX86_BUILTIN_PMULUDQ,
27465 IX86_BUILTIN_PMULUDQ128,
27466 IX86_BUILTIN_PMULHUW128,
27467 IX86_BUILTIN_PMULHW128,
27468 IX86_BUILTIN_PMULLW128,
27470 IX86_BUILTIN_PSADBW128,
27471 IX86_BUILTIN_PSHUFHW,
27472 IX86_BUILTIN_PSHUFLW,
27473 IX86_BUILTIN_PSHUFD,
27475 IX86_BUILTIN_PSLLDQI128,
27476 IX86_BUILTIN_PSLLWI128,
27477 IX86_BUILTIN_PSLLDI128,
27478 IX86_BUILTIN_PSLLQI128,
27479 IX86_BUILTIN_PSRAWI128,
27480 IX86_BUILTIN_PSRADI128,
27481 IX86_BUILTIN_PSRLDQI128,
27482 IX86_BUILTIN_PSRLWI128,
27483 IX86_BUILTIN_PSRLDI128,
27484 IX86_BUILTIN_PSRLQI128,
27486 IX86_BUILTIN_PSLLDQ128,
27487 IX86_BUILTIN_PSLLW128,
27488 IX86_BUILTIN_PSLLD128,
27489 IX86_BUILTIN_PSLLQ128,
27490 IX86_BUILTIN_PSRAW128,
27491 IX86_BUILTIN_PSRAD128,
27492 IX86_BUILTIN_PSRLW128,
27493 IX86_BUILTIN_PSRLD128,
27494 IX86_BUILTIN_PSRLQ128,
27496 IX86_BUILTIN_PUNPCKHBW128,
27497 IX86_BUILTIN_PUNPCKHWD128,
27498 IX86_BUILTIN_PUNPCKHDQ128,
27499 IX86_BUILTIN_PUNPCKHQDQ128,
27500 IX86_BUILTIN_PUNPCKLBW128,
27501 IX86_BUILTIN_PUNPCKLWD128,
27502 IX86_BUILTIN_PUNPCKLDQ128,
27503 IX86_BUILTIN_PUNPCKLQDQ128,
27505 IX86_BUILTIN_CLFLUSH,
27506 IX86_BUILTIN_MFENCE,
27507 IX86_BUILTIN_LFENCE,
27508 IX86_BUILTIN_PAUSE,
27510 IX86_BUILTIN_FNSTENV,
27511 IX86_BUILTIN_FLDENV,
27512 IX86_BUILTIN_FNSTSW,
27513 IX86_BUILTIN_FNCLEX,
27515 IX86_BUILTIN_BSRSI,
27516 IX86_BUILTIN_BSRDI,
27517 IX86_BUILTIN_RDPMC,
27518 IX86_BUILTIN_RDTSC,
27519 IX86_BUILTIN_RDTSCP,
27520 IX86_BUILTIN_ROLQI,
27521 IX86_BUILTIN_ROLHI,
27522 IX86_BUILTIN_RORQI,
27523 IX86_BUILTIN_RORHI,
27525 /* SSE3. */
27526 IX86_BUILTIN_ADDSUBPS,
27527 IX86_BUILTIN_HADDPS,
27528 IX86_BUILTIN_HSUBPS,
27529 IX86_BUILTIN_MOVSHDUP,
27530 IX86_BUILTIN_MOVSLDUP,
27531 IX86_BUILTIN_ADDSUBPD,
27532 IX86_BUILTIN_HADDPD,
27533 IX86_BUILTIN_HSUBPD,
27534 IX86_BUILTIN_LDDQU,
27536 IX86_BUILTIN_MONITOR,
27537 IX86_BUILTIN_MWAIT,
27539 /* SSSE3. */
27540 IX86_BUILTIN_PHADDW,
27541 IX86_BUILTIN_PHADDD,
27542 IX86_BUILTIN_PHADDSW,
27543 IX86_BUILTIN_PHSUBW,
27544 IX86_BUILTIN_PHSUBD,
27545 IX86_BUILTIN_PHSUBSW,
27546 IX86_BUILTIN_PMADDUBSW,
27547 IX86_BUILTIN_PMULHRSW,
27548 IX86_BUILTIN_PSHUFB,
27549 IX86_BUILTIN_PSIGNB,
27550 IX86_BUILTIN_PSIGNW,
27551 IX86_BUILTIN_PSIGND,
27552 IX86_BUILTIN_PALIGNR,
27553 IX86_BUILTIN_PABSB,
27554 IX86_BUILTIN_PABSW,
27555 IX86_BUILTIN_PABSD,
27557 IX86_BUILTIN_PHADDW128,
27558 IX86_BUILTIN_PHADDD128,
27559 IX86_BUILTIN_PHADDSW128,
27560 IX86_BUILTIN_PHSUBW128,
27561 IX86_BUILTIN_PHSUBD128,
27562 IX86_BUILTIN_PHSUBSW128,
27563 IX86_BUILTIN_PMADDUBSW128,
27564 IX86_BUILTIN_PMULHRSW128,
27565 IX86_BUILTIN_PSHUFB128,
27566 IX86_BUILTIN_PSIGNB128,
27567 IX86_BUILTIN_PSIGNW128,
27568 IX86_BUILTIN_PSIGND128,
27569 IX86_BUILTIN_PALIGNR128,
27570 IX86_BUILTIN_PABSB128,
27571 IX86_BUILTIN_PABSW128,
27572 IX86_BUILTIN_PABSD128,
27574 /* AMDFAM10 - SSE4A New Instructions. */
27575 IX86_BUILTIN_MOVNTSD,
27576 IX86_BUILTIN_MOVNTSS,
27577 IX86_BUILTIN_EXTRQI,
27578 IX86_BUILTIN_EXTRQ,
27579 IX86_BUILTIN_INSERTQI,
27580 IX86_BUILTIN_INSERTQ,
27582 /* SSE4.1. */
27583 IX86_BUILTIN_BLENDPD,
27584 IX86_BUILTIN_BLENDPS,
27585 IX86_BUILTIN_BLENDVPD,
27586 IX86_BUILTIN_BLENDVPS,
27587 IX86_BUILTIN_PBLENDVB128,
27588 IX86_BUILTIN_PBLENDW128,
27590 IX86_BUILTIN_DPPD,
27591 IX86_BUILTIN_DPPS,
27593 IX86_BUILTIN_INSERTPS128,
27595 IX86_BUILTIN_MOVNTDQA,
27596 IX86_BUILTIN_MPSADBW128,
27597 IX86_BUILTIN_PACKUSDW128,
27598 IX86_BUILTIN_PCMPEQQ,
27599 IX86_BUILTIN_PHMINPOSUW128,
27601 IX86_BUILTIN_PMAXSB128,
27602 IX86_BUILTIN_PMAXSD128,
27603 IX86_BUILTIN_PMAXUD128,
27604 IX86_BUILTIN_PMAXUW128,
27606 IX86_BUILTIN_PMINSB128,
27607 IX86_BUILTIN_PMINSD128,
27608 IX86_BUILTIN_PMINUD128,
27609 IX86_BUILTIN_PMINUW128,
27611 IX86_BUILTIN_PMOVSXBW128,
27612 IX86_BUILTIN_PMOVSXBD128,
27613 IX86_BUILTIN_PMOVSXBQ128,
27614 IX86_BUILTIN_PMOVSXWD128,
27615 IX86_BUILTIN_PMOVSXWQ128,
27616 IX86_BUILTIN_PMOVSXDQ128,
27618 IX86_BUILTIN_PMOVZXBW128,
27619 IX86_BUILTIN_PMOVZXBD128,
27620 IX86_BUILTIN_PMOVZXBQ128,
27621 IX86_BUILTIN_PMOVZXWD128,
27622 IX86_BUILTIN_PMOVZXWQ128,
27623 IX86_BUILTIN_PMOVZXDQ128,
27625 IX86_BUILTIN_PMULDQ128,
27626 IX86_BUILTIN_PMULLD128,
27628 IX86_BUILTIN_ROUNDSD,
27629 IX86_BUILTIN_ROUNDSS,
27631 IX86_BUILTIN_ROUNDPD,
27632 IX86_BUILTIN_ROUNDPS,
27634 IX86_BUILTIN_FLOORPD,
27635 IX86_BUILTIN_CEILPD,
27636 IX86_BUILTIN_TRUNCPD,
27637 IX86_BUILTIN_RINTPD,
27638 IX86_BUILTIN_ROUNDPD_AZ,
27640 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
27641 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
27642 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
27644 IX86_BUILTIN_FLOORPS,
27645 IX86_BUILTIN_CEILPS,
27646 IX86_BUILTIN_TRUNCPS,
27647 IX86_BUILTIN_RINTPS,
27648 IX86_BUILTIN_ROUNDPS_AZ,
27650 IX86_BUILTIN_FLOORPS_SFIX,
27651 IX86_BUILTIN_CEILPS_SFIX,
27652 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
27654 IX86_BUILTIN_PTESTZ,
27655 IX86_BUILTIN_PTESTC,
27656 IX86_BUILTIN_PTESTNZC,
27658 IX86_BUILTIN_VEC_INIT_V2SI,
27659 IX86_BUILTIN_VEC_INIT_V4HI,
27660 IX86_BUILTIN_VEC_INIT_V8QI,
27661 IX86_BUILTIN_VEC_EXT_V2DF,
27662 IX86_BUILTIN_VEC_EXT_V2DI,
27663 IX86_BUILTIN_VEC_EXT_V4SF,
27664 IX86_BUILTIN_VEC_EXT_V4SI,
27665 IX86_BUILTIN_VEC_EXT_V8HI,
27666 IX86_BUILTIN_VEC_EXT_V2SI,
27667 IX86_BUILTIN_VEC_EXT_V4HI,
27668 IX86_BUILTIN_VEC_EXT_V16QI,
27669 IX86_BUILTIN_VEC_SET_V2DI,
27670 IX86_BUILTIN_VEC_SET_V4SF,
27671 IX86_BUILTIN_VEC_SET_V4SI,
27672 IX86_BUILTIN_VEC_SET_V8HI,
27673 IX86_BUILTIN_VEC_SET_V4HI,
27674 IX86_BUILTIN_VEC_SET_V16QI,
27676 IX86_BUILTIN_VEC_PACK_SFIX,
27677 IX86_BUILTIN_VEC_PACK_SFIX256,
27679 /* SSE4.2. */
27680 IX86_BUILTIN_CRC32QI,
27681 IX86_BUILTIN_CRC32HI,
27682 IX86_BUILTIN_CRC32SI,
27683 IX86_BUILTIN_CRC32DI,
27685 IX86_BUILTIN_PCMPESTRI128,
27686 IX86_BUILTIN_PCMPESTRM128,
27687 IX86_BUILTIN_PCMPESTRA128,
27688 IX86_BUILTIN_PCMPESTRC128,
27689 IX86_BUILTIN_PCMPESTRO128,
27690 IX86_BUILTIN_PCMPESTRS128,
27691 IX86_BUILTIN_PCMPESTRZ128,
27692 IX86_BUILTIN_PCMPISTRI128,
27693 IX86_BUILTIN_PCMPISTRM128,
27694 IX86_BUILTIN_PCMPISTRA128,
27695 IX86_BUILTIN_PCMPISTRC128,
27696 IX86_BUILTIN_PCMPISTRO128,
27697 IX86_BUILTIN_PCMPISTRS128,
27698 IX86_BUILTIN_PCMPISTRZ128,
27700 IX86_BUILTIN_PCMPGTQ,
27702 /* AES instructions */
27703 IX86_BUILTIN_AESENC128,
27704 IX86_BUILTIN_AESENCLAST128,
27705 IX86_BUILTIN_AESDEC128,
27706 IX86_BUILTIN_AESDECLAST128,
27707 IX86_BUILTIN_AESIMC128,
27708 IX86_BUILTIN_AESKEYGENASSIST128,
27710 /* PCLMUL instruction */
27711 IX86_BUILTIN_PCLMULQDQ128,
27713 /* AVX */
27714 IX86_BUILTIN_ADDPD256,
27715 IX86_BUILTIN_ADDPS256,
27716 IX86_BUILTIN_ADDSUBPD256,
27717 IX86_BUILTIN_ADDSUBPS256,
27718 IX86_BUILTIN_ANDPD256,
27719 IX86_BUILTIN_ANDPS256,
27720 IX86_BUILTIN_ANDNPD256,
27721 IX86_BUILTIN_ANDNPS256,
27722 IX86_BUILTIN_BLENDPD256,
27723 IX86_BUILTIN_BLENDPS256,
27724 IX86_BUILTIN_BLENDVPD256,
27725 IX86_BUILTIN_BLENDVPS256,
27726 IX86_BUILTIN_DIVPD256,
27727 IX86_BUILTIN_DIVPS256,
27728 IX86_BUILTIN_DPPS256,
27729 IX86_BUILTIN_HADDPD256,
27730 IX86_BUILTIN_HADDPS256,
27731 IX86_BUILTIN_HSUBPD256,
27732 IX86_BUILTIN_HSUBPS256,
27733 IX86_BUILTIN_MAXPD256,
27734 IX86_BUILTIN_MAXPS256,
27735 IX86_BUILTIN_MINPD256,
27736 IX86_BUILTIN_MINPS256,
27737 IX86_BUILTIN_MULPD256,
27738 IX86_BUILTIN_MULPS256,
27739 IX86_BUILTIN_ORPD256,
27740 IX86_BUILTIN_ORPS256,
27741 IX86_BUILTIN_SHUFPD256,
27742 IX86_BUILTIN_SHUFPS256,
27743 IX86_BUILTIN_SUBPD256,
27744 IX86_BUILTIN_SUBPS256,
27745 IX86_BUILTIN_XORPD256,
27746 IX86_BUILTIN_XORPS256,
27747 IX86_BUILTIN_CMPSD,
27748 IX86_BUILTIN_CMPSS,
27749 IX86_BUILTIN_CMPPD,
27750 IX86_BUILTIN_CMPPS,
27751 IX86_BUILTIN_CMPPD256,
27752 IX86_BUILTIN_CMPPS256,
27753 IX86_BUILTIN_CVTDQ2PD256,
27754 IX86_BUILTIN_CVTDQ2PS256,
27755 IX86_BUILTIN_CVTPD2PS256,
27756 IX86_BUILTIN_CVTPS2DQ256,
27757 IX86_BUILTIN_CVTPS2PD256,
27758 IX86_BUILTIN_CVTTPD2DQ256,
27759 IX86_BUILTIN_CVTPD2DQ256,
27760 IX86_BUILTIN_CVTTPS2DQ256,
27761 IX86_BUILTIN_EXTRACTF128PD256,
27762 IX86_BUILTIN_EXTRACTF128PS256,
27763 IX86_BUILTIN_EXTRACTF128SI256,
27764 IX86_BUILTIN_VZEROALL,
27765 IX86_BUILTIN_VZEROUPPER,
27766 IX86_BUILTIN_VPERMILVARPD,
27767 IX86_BUILTIN_VPERMILVARPS,
27768 IX86_BUILTIN_VPERMILVARPD256,
27769 IX86_BUILTIN_VPERMILVARPS256,
27770 IX86_BUILTIN_VPERMILPD,
27771 IX86_BUILTIN_VPERMILPS,
27772 IX86_BUILTIN_VPERMILPD256,
27773 IX86_BUILTIN_VPERMILPS256,
27774 IX86_BUILTIN_VPERMIL2PD,
27775 IX86_BUILTIN_VPERMIL2PS,
27776 IX86_BUILTIN_VPERMIL2PD256,
27777 IX86_BUILTIN_VPERMIL2PS256,
27778 IX86_BUILTIN_VPERM2F128PD256,
27779 IX86_BUILTIN_VPERM2F128PS256,
27780 IX86_BUILTIN_VPERM2F128SI256,
27781 IX86_BUILTIN_VBROADCASTSS,
27782 IX86_BUILTIN_VBROADCASTSD256,
27783 IX86_BUILTIN_VBROADCASTSS256,
27784 IX86_BUILTIN_VBROADCASTPD256,
27785 IX86_BUILTIN_VBROADCASTPS256,
27786 IX86_BUILTIN_VINSERTF128PD256,
27787 IX86_BUILTIN_VINSERTF128PS256,
27788 IX86_BUILTIN_VINSERTF128SI256,
27789 IX86_BUILTIN_LOADUPD256,
27790 IX86_BUILTIN_LOADUPS256,
27791 IX86_BUILTIN_STOREUPD256,
27792 IX86_BUILTIN_STOREUPS256,
27793 IX86_BUILTIN_LDDQU256,
27794 IX86_BUILTIN_MOVNTDQ256,
27795 IX86_BUILTIN_MOVNTPD256,
27796 IX86_BUILTIN_MOVNTPS256,
27797 IX86_BUILTIN_LOADDQU256,
27798 IX86_BUILTIN_STOREDQU256,
27799 IX86_BUILTIN_MASKLOADPD,
27800 IX86_BUILTIN_MASKLOADPS,
27801 IX86_BUILTIN_MASKSTOREPD,
27802 IX86_BUILTIN_MASKSTOREPS,
27803 IX86_BUILTIN_MASKLOADPD256,
27804 IX86_BUILTIN_MASKLOADPS256,
27805 IX86_BUILTIN_MASKSTOREPD256,
27806 IX86_BUILTIN_MASKSTOREPS256,
27807 IX86_BUILTIN_MOVSHDUP256,
27808 IX86_BUILTIN_MOVSLDUP256,
27809 IX86_BUILTIN_MOVDDUP256,
27811 IX86_BUILTIN_SQRTPD256,
27812 IX86_BUILTIN_SQRTPS256,
27813 IX86_BUILTIN_SQRTPS_NR256,
27814 IX86_BUILTIN_RSQRTPS256,
27815 IX86_BUILTIN_RSQRTPS_NR256,
27817 IX86_BUILTIN_RCPPS256,
27819 IX86_BUILTIN_ROUNDPD256,
27820 IX86_BUILTIN_ROUNDPS256,
27822 IX86_BUILTIN_FLOORPD256,
27823 IX86_BUILTIN_CEILPD256,
27824 IX86_BUILTIN_TRUNCPD256,
27825 IX86_BUILTIN_RINTPD256,
27826 IX86_BUILTIN_ROUNDPD_AZ256,
27828 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
27829 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
27830 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
27832 IX86_BUILTIN_FLOORPS256,
27833 IX86_BUILTIN_CEILPS256,
27834 IX86_BUILTIN_TRUNCPS256,
27835 IX86_BUILTIN_RINTPS256,
27836 IX86_BUILTIN_ROUNDPS_AZ256,
27838 IX86_BUILTIN_FLOORPS_SFIX256,
27839 IX86_BUILTIN_CEILPS_SFIX256,
27840 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
27842 IX86_BUILTIN_UNPCKHPD256,
27843 IX86_BUILTIN_UNPCKLPD256,
27844 IX86_BUILTIN_UNPCKHPS256,
27845 IX86_BUILTIN_UNPCKLPS256,
27847 IX86_BUILTIN_SI256_SI,
27848 IX86_BUILTIN_PS256_PS,
27849 IX86_BUILTIN_PD256_PD,
27850 IX86_BUILTIN_SI_SI256,
27851 IX86_BUILTIN_PS_PS256,
27852 IX86_BUILTIN_PD_PD256,
27854 IX86_BUILTIN_VTESTZPD,
27855 IX86_BUILTIN_VTESTCPD,
27856 IX86_BUILTIN_VTESTNZCPD,
27857 IX86_BUILTIN_VTESTZPS,
27858 IX86_BUILTIN_VTESTCPS,
27859 IX86_BUILTIN_VTESTNZCPS,
27860 IX86_BUILTIN_VTESTZPD256,
27861 IX86_BUILTIN_VTESTCPD256,
27862 IX86_BUILTIN_VTESTNZCPD256,
27863 IX86_BUILTIN_VTESTZPS256,
27864 IX86_BUILTIN_VTESTCPS256,
27865 IX86_BUILTIN_VTESTNZCPS256,
27866 IX86_BUILTIN_PTESTZ256,
27867 IX86_BUILTIN_PTESTC256,
27868 IX86_BUILTIN_PTESTNZC256,
27870 IX86_BUILTIN_MOVMSKPD256,
27871 IX86_BUILTIN_MOVMSKPS256,
27873 /* AVX2 */
27874 IX86_BUILTIN_MPSADBW256,
27875 IX86_BUILTIN_PABSB256,
27876 IX86_BUILTIN_PABSW256,
27877 IX86_BUILTIN_PABSD256,
27878 IX86_BUILTIN_PACKSSDW256,
27879 IX86_BUILTIN_PACKSSWB256,
27880 IX86_BUILTIN_PACKUSDW256,
27881 IX86_BUILTIN_PACKUSWB256,
27882 IX86_BUILTIN_PADDB256,
27883 IX86_BUILTIN_PADDW256,
27884 IX86_BUILTIN_PADDD256,
27885 IX86_BUILTIN_PADDQ256,
27886 IX86_BUILTIN_PADDSB256,
27887 IX86_BUILTIN_PADDSW256,
27888 IX86_BUILTIN_PADDUSB256,
27889 IX86_BUILTIN_PADDUSW256,
27890 IX86_BUILTIN_PALIGNR256,
27891 IX86_BUILTIN_AND256I,
27892 IX86_BUILTIN_ANDNOT256I,
27893 IX86_BUILTIN_PAVGB256,
27894 IX86_BUILTIN_PAVGW256,
27895 IX86_BUILTIN_PBLENDVB256,
27896 IX86_BUILTIN_PBLENDVW256,
27897 IX86_BUILTIN_PCMPEQB256,
27898 IX86_BUILTIN_PCMPEQW256,
27899 IX86_BUILTIN_PCMPEQD256,
27900 IX86_BUILTIN_PCMPEQQ256,
27901 IX86_BUILTIN_PCMPGTB256,
27902 IX86_BUILTIN_PCMPGTW256,
27903 IX86_BUILTIN_PCMPGTD256,
27904 IX86_BUILTIN_PCMPGTQ256,
27905 IX86_BUILTIN_PHADDW256,
27906 IX86_BUILTIN_PHADDD256,
27907 IX86_BUILTIN_PHADDSW256,
27908 IX86_BUILTIN_PHSUBW256,
27909 IX86_BUILTIN_PHSUBD256,
27910 IX86_BUILTIN_PHSUBSW256,
27911 IX86_BUILTIN_PMADDUBSW256,
27912 IX86_BUILTIN_PMADDWD256,
27913 IX86_BUILTIN_PMAXSB256,
27914 IX86_BUILTIN_PMAXSW256,
27915 IX86_BUILTIN_PMAXSD256,
27916 IX86_BUILTIN_PMAXUB256,
27917 IX86_BUILTIN_PMAXUW256,
27918 IX86_BUILTIN_PMAXUD256,
27919 IX86_BUILTIN_PMINSB256,
27920 IX86_BUILTIN_PMINSW256,
27921 IX86_BUILTIN_PMINSD256,
27922 IX86_BUILTIN_PMINUB256,
27923 IX86_BUILTIN_PMINUW256,
27924 IX86_BUILTIN_PMINUD256,
27925 IX86_BUILTIN_PMOVMSKB256,
27926 IX86_BUILTIN_PMOVSXBW256,
27927 IX86_BUILTIN_PMOVSXBD256,
27928 IX86_BUILTIN_PMOVSXBQ256,
27929 IX86_BUILTIN_PMOVSXWD256,
27930 IX86_BUILTIN_PMOVSXWQ256,
27931 IX86_BUILTIN_PMOVSXDQ256,
27932 IX86_BUILTIN_PMOVZXBW256,
27933 IX86_BUILTIN_PMOVZXBD256,
27934 IX86_BUILTIN_PMOVZXBQ256,
27935 IX86_BUILTIN_PMOVZXWD256,
27936 IX86_BUILTIN_PMOVZXWQ256,
27937 IX86_BUILTIN_PMOVZXDQ256,
27938 IX86_BUILTIN_PMULDQ256,
27939 IX86_BUILTIN_PMULHRSW256,
27940 IX86_BUILTIN_PMULHUW256,
27941 IX86_BUILTIN_PMULHW256,
27942 IX86_BUILTIN_PMULLW256,
27943 IX86_BUILTIN_PMULLD256,
27944 IX86_BUILTIN_PMULUDQ256,
27945 IX86_BUILTIN_POR256,
27946 IX86_BUILTIN_PSADBW256,
27947 IX86_BUILTIN_PSHUFB256,
27948 IX86_BUILTIN_PSHUFD256,
27949 IX86_BUILTIN_PSHUFHW256,
27950 IX86_BUILTIN_PSHUFLW256,
27951 IX86_BUILTIN_PSIGNB256,
27952 IX86_BUILTIN_PSIGNW256,
27953 IX86_BUILTIN_PSIGND256,
27954 IX86_BUILTIN_PSLLDQI256,
27955 IX86_BUILTIN_PSLLWI256,
27956 IX86_BUILTIN_PSLLW256,
27957 IX86_BUILTIN_PSLLDI256,
27958 IX86_BUILTIN_PSLLD256,
27959 IX86_BUILTIN_PSLLQI256,
27960 IX86_BUILTIN_PSLLQ256,
27961 IX86_BUILTIN_PSRAWI256,
27962 IX86_BUILTIN_PSRAW256,
27963 IX86_BUILTIN_PSRADI256,
27964 IX86_BUILTIN_PSRAD256,
27965 IX86_BUILTIN_PSRLDQI256,
27966 IX86_BUILTIN_PSRLWI256,
27967 IX86_BUILTIN_PSRLW256,
27968 IX86_BUILTIN_PSRLDI256,
27969 IX86_BUILTIN_PSRLD256,
27970 IX86_BUILTIN_PSRLQI256,
27971 IX86_BUILTIN_PSRLQ256,
27972 IX86_BUILTIN_PSUBB256,
27973 IX86_BUILTIN_PSUBW256,
27974 IX86_BUILTIN_PSUBD256,
27975 IX86_BUILTIN_PSUBQ256,
27976 IX86_BUILTIN_PSUBSB256,
27977 IX86_BUILTIN_PSUBSW256,
27978 IX86_BUILTIN_PSUBUSB256,
27979 IX86_BUILTIN_PSUBUSW256,
27980 IX86_BUILTIN_PUNPCKHBW256,
27981 IX86_BUILTIN_PUNPCKHWD256,
27982 IX86_BUILTIN_PUNPCKHDQ256,
27983 IX86_BUILTIN_PUNPCKHQDQ256,
27984 IX86_BUILTIN_PUNPCKLBW256,
27985 IX86_BUILTIN_PUNPCKLWD256,
27986 IX86_BUILTIN_PUNPCKLDQ256,
27987 IX86_BUILTIN_PUNPCKLQDQ256,
27988 IX86_BUILTIN_PXOR256,
27989 IX86_BUILTIN_MOVNTDQA256,
27990 IX86_BUILTIN_VBROADCASTSS_PS,
27991 IX86_BUILTIN_VBROADCASTSS_PS256,
27992 IX86_BUILTIN_VBROADCASTSD_PD256,
27993 IX86_BUILTIN_VBROADCASTSI256,
27994 IX86_BUILTIN_PBLENDD256,
27995 IX86_BUILTIN_PBLENDD128,
27996 IX86_BUILTIN_PBROADCASTB256,
27997 IX86_BUILTIN_PBROADCASTW256,
27998 IX86_BUILTIN_PBROADCASTD256,
27999 IX86_BUILTIN_PBROADCASTQ256,
28000 IX86_BUILTIN_PBROADCASTB128,
28001 IX86_BUILTIN_PBROADCASTW128,
28002 IX86_BUILTIN_PBROADCASTD128,
28003 IX86_BUILTIN_PBROADCASTQ128,
28004 IX86_BUILTIN_VPERMVARSI256,
28005 IX86_BUILTIN_VPERMDF256,
28006 IX86_BUILTIN_VPERMVARSF256,
28007 IX86_BUILTIN_VPERMDI256,
28008 IX86_BUILTIN_VPERMTI256,
28009 IX86_BUILTIN_VEXTRACT128I256,
28010 IX86_BUILTIN_VINSERT128I256,
28011 IX86_BUILTIN_MASKLOADD,
28012 IX86_BUILTIN_MASKLOADQ,
28013 IX86_BUILTIN_MASKLOADD256,
28014 IX86_BUILTIN_MASKLOADQ256,
28015 IX86_BUILTIN_MASKSTORED,
28016 IX86_BUILTIN_MASKSTOREQ,
28017 IX86_BUILTIN_MASKSTORED256,
28018 IX86_BUILTIN_MASKSTOREQ256,
28019 IX86_BUILTIN_PSLLVV4DI,
28020 IX86_BUILTIN_PSLLVV2DI,
28021 IX86_BUILTIN_PSLLVV8SI,
28022 IX86_BUILTIN_PSLLVV4SI,
28023 IX86_BUILTIN_PSRAVV8SI,
28024 IX86_BUILTIN_PSRAVV4SI,
28025 IX86_BUILTIN_PSRLVV4DI,
28026 IX86_BUILTIN_PSRLVV2DI,
28027 IX86_BUILTIN_PSRLVV8SI,
28028 IX86_BUILTIN_PSRLVV4SI,
28030 IX86_BUILTIN_GATHERSIV2DF,
28031 IX86_BUILTIN_GATHERSIV4DF,
28032 IX86_BUILTIN_GATHERDIV2DF,
28033 IX86_BUILTIN_GATHERDIV4DF,
28034 IX86_BUILTIN_GATHERSIV4SF,
28035 IX86_BUILTIN_GATHERSIV8SF,
28036 IX86_BUILTIN_GATHERDIV4SF,
28037 IX86_BUILTIN_GATHERDIV8SF,
28038 IX86_BUILTIN_GATHERSIV2DI,
28039 IX86_BUILTIN_GATHERSIV4DI,
28040 IX86_BUILTIN_GATHERDIV2DI,
28041 IX86_BUILTIN_GATHERDIV4DI,
28042 IX86_BUILTIN_GATHERSIV4SI,
28043 IX86_BUILTIN_GATHERSIV8SI,
28044 IX86_BUILTIN_GATHERDIV4SI,
28045 IX86_BUILTIN_GATHERDIV8SI,
28047 /* AVX512F */
28048 IX86_BUILTIN_ADDPD512,
28049 IX86_BUILTIN_ADDPS512,
28050 IX86_BUILTIN_ADDSD_ROUND,
28051 IX86_BUILTIN_ADDSS_ROUND,
28052 IX86_BUILTIN_ALIGND512,
28053 IX86_BUILTIN_ALIGNQ512,
28054 IX86_BUILTIN_BLENDMD512,
28055 IX86_BUILTIN_BLENDMPD512,
28056 IX86_BUILTIN_BLENDMPS512,
28057 IX86_BUILTIN_BLENDMQ512,
28058 IX86_BUILTIN_BROADCASTF32X4_512,
28059 IX86_BUILTIN_BROADCASTF64X4_512,
28060 IX86_BUILTIN_BROADCASTI32X4_512,
28061 IX86_BUILTIN_BROADCASTI64X4_512,
28062 IX86_BUILTIN_BROADCASTSD512,
28063 IX86_BUILTIN_BROADCASTSS512,
28064 IX86_BUILTIN_CMPD512,
28065 IX86_BUILTIN_CMPPD512,
28066 IX86_BUILTIN_CMPPS512,
28067 IX86_BUILTIN_CMPQ512,
28068 IX86_BUILTIN_CMPSD_MASK,
28069 IX86_BUILTIN_CMPSS_MASK,
28070 IX86_BUILTIN_COMIDF,
28071 IX86_BUILTIN_COMISF,
28072 IX86_BUILTIN_COMPRESSPD512,
28073 IX86_BUILTIN_COMPRESSPDSTORE512,
28074 IX86_BUILTIN_COMPRESSPS512,
28075 IX86_BUILTIN_COMPRESSPSSTORE512,
28076 IX86_BUILTIN_CVTDQ2PD512,
28077 IX86_BUILTIN_CVTDQ2PS512,
28078 IX86_BUILTIN_CVTPD2DQ512,
28079 IX86_BUILTIN_CVTPD2PS512,
28080 IX86_BUILTIN_CVTPD2UDQ512,
28081 IX86_BUILTIN_CVTPH2PS512,
28082 IX86_BUILTIN_CVTPS2DQ512,
28083 IX86_BUILTIN_CVTPS2PD512,
28084 IX86_BUILTIN_CVTPS2PH512,
28085 IX86_BUILTIN_CVTPS2UDQ512,
28086 IX86_BUILTIN_CVTSD2SS_ROUND,
28087 IX86_BUILTIN_CVTSI2SD64,
28088 IX86_BUILTIN_CVTSI2SS32,
28089 IX86_BUILTIN_CVTSI2SS64,
28090 IX86_BUILTIN_CVTSS2SD_ROUND,
28091 IX86_BUILTIN_CVTTPD2DQ512,
28092 IX86_BUILTIN_CVTTPD2UDQ512,
28093 IX86_BUILTIN_CVTTPS2DQ512,
28094 IX86_BUILTIN_CVTTPS2UDQ512,
28095 IX86_BUILTIN_CVTUDQ2PD512,
28096 IX86_BUILTIN_CVTUDQ2PS512,
28097 IX86_BUILTIN_CVTUSI2SD32,
28098 IX86_BUILTIN_CVTUSI2SD64,
28099 IX86_BUILTIN_CVTUSI2SS32,
28100 IX86_BUILTIN_CVTUSI2SS64,
28101 IX86_BUILTIN_DIVPD512,
28102 IX86_BUILTIN_DIVPS512,
28103 IX86_BUILTIN_DIVSD_ROUND,
28104 IX86_BUILTIN_DIVSS_ROUND,
28105 IX86_BUILTIN_EXPANDPD512,
28106 IX86_BUILTIN_EXPANDPD512Z,
28107 IX86_BUILTIN_EXPANDPDLOAD512,
28108 IX86_BUILTIN_EXPANDPDLOAD512Z,
28109 IX86_BUILTIN_EXPANDPS512,
28110 IX86_BUILTIN_EXPANDPS512Z,
28111 IX86_BUILTIN_EXPANDPSLOAD512,
28112 IX86_BUILTIN_EXPANDPSLOAD512Z,
28113 IX86_BUILTIN_EXTRACTF32X4,
28114 IX86_BUILTIN_EXTRACTF64X4,
28115 IX86_BUILTIN_EXTRACTI32X4,
28116 IX86_BUILTIN_EXTRACTI64X4,
28117 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28118 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28119 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28120 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28121 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28122 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28123 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28124 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28125 IX86_BUILTIN_GETEXPPD512,
28126 IX86_BUILTIN_GETEXPPS512,
28127 IX86_BUILTIN_GETEXPSD128,
28128 IX86_BUILTIN_GETEXPSS128,
28129 IX86_BUILTIN_GETMANTPD512,
28130 IX86_BUILTIN_GETMANTPS512,
28131 IX86_BUILTIN_GETMANTSD128,
28132 IX86_BUILTIN_GETMANTSS128,
28133 IX86_BUILTIN_INSERTF32X4,
28134 IX86_BUILTIN_INSERTF64X4,
28135 IX86_BUILTIN_INSERTI32X4,
28136 IX86_BUILTIN_INSERTI64X4,
28137 IX86_BUILTIN_LOADAPD512,
28138 IX86_BUILTIN_LOADAPS512,
28139 IX86_BUILTIN_LOADDQUDI512,
28140 IX86_BUILTIN_LOADDQUSI512,
28141 IX86_BUILTIN_LOADUPD512,
28142 IX86_BUILTIN_LOADUPS512,
28143 IX86_BUILTIN_MAXPD512,
28144 IX86_BUILTIN_MAXPS512,
28145 IX86_BUILTIN_MAXSD_ROUND,
28146 IX86_BUILTIN_MAXSS_ROUND,
28147 IX86_BUILTIN_MINPD512,
28148 IX86_BUILTIN_MINPS512,
28149 IX86_BUILTIN_MINSD_ROUND,
28150 IX86_BUILTIN_MINSS_ROUND,
28151 IX86_BUILTIN_MOVAPD512,
28152 IX86_BUILTIN_MOVAPS512,
28153 IX86_BUILTIN_MOVDDUP512,
28154 IX86_BUILTIN_MOVDQA32LOAD512,
28155 IX86_BUILTIN_MOVDQA32STORE512,
28156 IX86_BUILTIN_MOVDQA32_512,
28157 IX86_BUILTIN_MOVDQA64LOAD512,
28158 IX86_BUILTIN_MOVDQA64STORE512,
28159 IX86_BUILTIN_MOVDQA64_512,
28160 IX86_BUILTIN_MOVNTDQ512,
28161 IX86_BUILTIN_MOVNTDQA512,
28162 IX86_BUILTIN_MOVNTPD512,
28163 IX86_BUILTIN_MOVNTPS512,
28164 IX86_BUILTIN_MOVSHDUP512,
28165 IX86_BUILTIN_MOVSLDUP512,
28166 IX86_BUILTIN_MULPD512,
28167 IX86_BUILTIN_MULPS512,
28168 IX86_BUILTIN_MULSD_ROUND,
28169 IX86_BUILTIN_MULSS_ROUND,
28170 IX86_BUILTIN_PABSD512,
28171 IX86_BUILTIN_PABSQ512,
28172 IX86_BUILTIN_PADDD512,
28173 IX86_BUILTIN_PADDQ512,
28174 IX86_BUILTIN_PANDD512,
28175 IX86_BUILTIN_PANDND512,
28176 IX86_BUILTIN_PANDNQ512,
28177 IX86_BUILTIN_PANDQ512,
28178 IX86_BUILTIN_PBROADCASTD512,
28179 IX86_BUILTIN_PBROADCASTD512_GPR,
28180 IX86_BUILTIN_PBROADCASTMB512,
28181 IX86_BUILTIN_PBROADCASTMW512,
28182 IX86_BUILTIN_PBROADCASTQ512,
28183 IX86_BUILTIN_PBROADCASTQ512_GPR,
28184 IX86_BUILTIN_PBROADCASTQ512_MEM,
28185 IX86_BUILTIN_PCMPEQD512_MASK,
28186 IX86_BUILTIN_PCMPEQQ512_MASK,
28187 IX86_BUILTIN_PCMPGTD512_MASK,
28188 IX86_BUILTIN_PCMPGTQ512_MASK,
28189 IX86_BUILTIN_PCOMPRESSD512,
28190 IX86_BUILTIN_PCOMPRESSDSTORE512,
28191 IX86_BUILTIN_PCOMPRESSQ512,
28192 IX86_BUILTIN_PCOMPRESSQSTORE512,
28193 IX86_BUILTIN_PEXPANDD512,
28194 IX86_BUILTIN_PEXPANDD512Z,
28195 IX86_BUILTIN_PEXPANDDLOAD512,
28196 IX86_BUILTIN_PEXPANDDLOAD512Z,
28197 IX86_BUILTIN_PEXPANDQ512,
28198 IX86_BUILTIN_PEXPANDQ512Z,
28199 IX86_BUILTIN_PEXPANDQLOAD512,
28200 IX86_BUILTIN_PEXPANDQLOAD512Z,
28201 IX86_BUILTIN_PMAXSD512,
28202 IX86_BUILTIN_PMAXSQ512,
28203 IX86_BUILTIN_PMAXUD512,
28204 IX86_BUILTIN_PMAXUQ512,
28205 IX86_BUILTIN_PMINSD512,
28206 IX86_BUILTIN_PMINSQ512,
28207 IX86_BUILTIN_PMINUD512,
28208 IX86_BUILTIN_PMINUQ512,
28209 IX86_BUILTIN_PMOVDB512,
28210 IX86_BUILTIN_PMOVDB512_MEM,
28211 IX86_BUILTIN_PMOVDW512,
28212 IX86_BUILTIN_PMOVDW512_MEM,
28213 IX86_BUILTIN_PMOVQB512,
28214 IX86_BUILTIN_PMOVQB512_MEM,
28215 IX86_BUILTIN_PMOVQD512,
28216 IX86_BUILTIN_PMOVQD512_MEM,
28217 IX86_BUILTIN_PMOVQW512,
28218 IX86_BUILTIN_PMOVQW512_MEM,
28219 IX86_BUILTIN_PMOVSDB512,
28220 IX86_BUILTIN_PMOVSDB512_MEM,
28221 IX86_BUILTIN_PMOVSDW512,
28222 IX86_BUILTIN_PMOVSDW512_MEM,
28223 IX86_BUILTIN_PMOVSQB512,
28224 IX86_BUILTIN_PMOVSQB512_MEM,
28225 IX86_BUILTIN_PMOVSQD512,
28226 IX86_BUILTIN_PMOVSQD512_MEM,
28227 IX86_BUILTIN_PMOVSQW512,
28228 IX86_BUILTIN_PMOVSQW512_MEM,
28229 IX86_BUILTIN_PMOVSXBD512,
28230 IX86_BUILTIN_PMOVSXBQ512,
28231 IX86_BUILTIN_PMOVSXDQ512,
28232 IX86_BUILTIN_PMOVSXWD512,
28233 IX86_BUILTIN_PMOVSXWQ512,
28234 IX86_BUILTIN_PMOVUSDB512,
28235 IX86_BUILTIN_PMOVUSDB512_MEM,
28236 IX86_BUILTIN_PMOVUSDW512,
28237 IX86_BUILTIN_PMOVUSDW512_MEM,
28238 IX86_BUILTIN_PMOVUSQB512,
28239 IX86_BUILTIN_PMOVUSQB512_MEM,
28240 IX86_BUILTIN_PMOVUSQD512,
28241 IX86_BUILTIN_PMOVUSQD512_MEM,
28242 IX86_BUILTIN_PMOVUSQW512,
28243 IX86_BUILTIN_PMOVUSQW512_MEM,
28244 IX86_BUILTIN_PMOVZXBD512,
28245 IX86_BUILTIN_PMOVZXBQ512,
28246 IX86_BUILTIN_PMOVZXDQ512,
28247 IX86_BUILTIN_PMOVZXWD512,
28248 IX86_BUILTIN_PMOVZXWQ512,
28249 IX86_BUILTIN_PMULDQ512,
28250 IX86_BUILTIN_PMULLD512,
28251 IX86_BUILTIN_PMULUDQ512,
28252 IX86_BUILTIN_PORD512,
28253 IX86_BUILTIN_PORQ512,
28254 IX86_BUILTIN_PROLD512,
28255 IX86_BUILTIN_PROLQ512,
28256 IX86_BUILTIN_PROLVD512,
28257 IX86_BUILTIN_PROLVQ512,
28258 IX86_BUILTIN_PRORD512,
28259 IX86_BUILTIN_PRORQ512,
28260 IX86_BUILTIN_PRORVD512,
28261 IX86_BUILTIN_PRORVQ512,
28262 IX86_BUILTIN_PSHUFD512,
28263 IX86_BUILTIN_PSLLD512,
28264 IX86_BUILTIN_PSLLDI512,
28265 IX86_BUILTIN_PSLLQ512,
28266 IX86_BUILTIN_PSLLQI512,
28267 IX86_BUILTIN_PSLLVV16SI,
28268 IX86_BUILTIN_PSLLVV8DI,
28269 IX86_BUILTIN_PSRAD512,
28270 IX86_BUILTIN_PSRADI512,
28271 IX86_BUILTIN_PSRAQ512,
28272 IX86_BUILTIN_PSRAQI512,
28273 IX86_BUILTIN_PSRAVV16SI,
28274 IX86_BUILTIN_PSRAVV8DI,
28275 IX86_BUILTIN_PSRLD512,
28276 IX86_BUILTIN_PSRLDI512,
28277 IX86_BUILTIN_PSRLQ512,
28278 IX86_BUILTIN_PSRLQI512,
28279 IX86_BUILTIN_PSRLVV16SI,
28280 IX86_BUILTIN_PSRLVV8DI,
28281 IX86_BUILTIN_PSUBD512,
28282 IX86_BUILTIN_PSUBQ512,
28283 IX86_BUILTIN_PTESTMD512,
28284 IX86_BUILTIN_PTESTMQ512,
28285 IX86_BUILTIN_PTESTNMD512,
28286 IX86_BUILTIN_PTESTNMQ512,
28287 IX86_BUILTIN_PUNPCKHDQ512,
28288 IX86_BUILTIN_PUNPCKHQDQ512,
28289 IX86_BUILTIN_PUNPCKLDQ512,
28290 IX86_BUILTIN_PUNPCKLQDQ512,
28291 IX86_BUILTIN_PXORD512,
28292 IX86_BUILTIN_PXORQ512,
28293 IX86_BUILTIN_RCP14PD512,
28294 IX86_BUILTIN_RCP14PS512,
28295 IX86_BUILTIN_RCP14SD,
28296 IX86_BUILTIN_RCP14SS,
28297 IX86_BUILTIN_RNDSCALEPD,
28298 IX86_BUILTIN_RNDSCALEPS,
28299 IX86_BUILTIN_RNDSCALESD,
28300 IX86_BUILTIN_RNDSCALESS,
28301 IX86_BUILTIN_RSQRT14PD512,
28302 IX86_BUILTIN_RSQRT14PS512,
28303 IX86_BUILTIN_RSQRT14SD,
28304 IX86_BUILTIN_RSQRT14SS,
28305 IX86_BUILTIN_SCALEFPD512,
28306 IX86_BUILTIN_SCALEFPS512,
28307 IX86_BUILTIN_SCALEFSD,
28308 IX86_BUILTIN_SCALEFSS,
28309 IX86_BUILTIN_SHUFPD512,
28310 IX86_BUILTIN_SHUFPS512,
28311 IX86_BUILTIN_SHUF_F32x4,
28312 IX86_BUILTIN_SHUF_F64x2,
28313 IX86_BUILTIN_SHUF_I32x4,
28314 IX86_BUILTIN_SHUF_I64x2,
28315 IX86_BUILTIN_SQRTPD512,
28316 IX86_BUILTIN_SQRTPD512_MASK,
28317 IX86_BUILTIN_SQRTPS512_MASK,
28318 IX86_BUILTIN_SQRTPS_NR512,
28319 IX86_BUILTIN_SQRTSD_ROUND,
28320 IX86_BUILTIN_SQRTSS_ROUND,
28321 IX86_BUILTIN_STOREAPD512,
28322 IX86_BUILTIN_STOREAPS512,
28323 IX86_BUILTIN_STOREDQUDI512,
28324 IX86_BUILTIN_STOREDQUSI512,
28325 IX86_BUILTIN_STOREUPD512,
28326 IX86_BUILTIN_STOREUPS512,
28327 IX86_BUILTIN_SUBPD512,
28328 IX86_BUILTIN_SUBPS512,
28329 IX86_BUILTIN_SUBSD_ROUND,
28330 IX86_BUILTIN_SUBSS_ROUND,
28331 IX86_BUILTIN_UCMPD512,
28332 IX86_BUILTIN_UCMPQ512,
28333 IX86_BUILTIN_UNPCKHPD512,
28334 IX86_BUILTIN_UNPCKHPS512,
28335 IX86_BUILTIN_UNPCKLPD512,
28336 IX86_BUILTIN_UNPCKLPS512,
28337 IX86_BUILTIN_VCVTSD2SI32,
28338 IX86_BUILTIN_VCVTSD2SI64,
28339 IX86_BUILTIN_VCVTSD2USI32,
28340 IX86_BUILTIN_VCVTSD2USI64,
28341 IX86_BUILTIN_VCVTSS2SI32,
28342 IX86_BUILTIN_VCVTSS2SI64,
28343 IX86_BUILTIN_VCVTSS2USI32,
28344 IX86_BUILTIN_VCVTSS2USI64,
28345 IX86_BUILTIN_VCVTTSD2SI32,
28346 IX86_BUILTIN_VCVTTSD2SI64,
28347 IX86_BUILTIN_VCVTTSD2USI32,
28348 IX86_BUILTIN_VCVTTSD2USI64,
28349 IX86_BUILTIN_VCVTTSS2SI32,
28350 IX86_BUILTIN_VCVTTSS2SI64,
28351 IX86_BUILTIN_VCVTTSS2USI32,
28352 IX86_BUILTIN_VCVTTSS2USI64,
28353 IX86_BUILTIN_VFMADDPD512_MASK,
28354 IX86_BUILTIN_VFMADDPD512_MASK3,
28355 IX86_BUILTIN_VFMADDPD512_MASKZ,
28356 IX86_BUILTIN_VFMADDPS512_MASK,
28357 IX86_BUILTIN_VFMADDPS512_MASK3,
28358 IX86_BUILTIN_VFMADDPS512_MASKZ,
28359 IX86_BUILTIN_VFMADDSD3_ROUND,
28360 IX86_BUILTIN_VFMADDSS3_ROUND,
28361 IX86_BUILTIN_VFMADDSUBPD512_MASK,
28362 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
28363 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
28364 IX86_BUILTIN_VFMADDSUBPS512_MASK,
28365 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
28366 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
28367 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
28368 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
28369 IX86_BUILTIN_VFMSUBPD512_MASK3,
28370 IX86_BUILTIN_VFMSUBPS512_MASK3,
28371 IX86_BUILTIN_VFMSUBSD3_MASK3,
28372 IX86_BUILTIN_VFMSUBSS3_MASK3,
28373 IX86_BUILTIN_VFNMADDPD512_MASK,
28374 IX86_BUILTIN_VFNMADDPS512_MASK,
28375 IX86_BUILTIN_VFNMSUBPD512_MASK,
28376 IX86_BUILTIN_VFNMSUBPD512_MASK3,
28377 IX86_BUILTIN_VFNMSUBPS512_MASK,
28378 IX86_BUILTIN_VFNMSUBPS512_MASK3,
28379 IX86_BUILTIN_VPCLZCNTD512,
28380 IX86_BUILTIN_VPCLZCNTQ512,
28381 IX86_BUILTIN_VPCONFLICTD512,
28382 IX86_BUILTIN_VPCONFLICTQ512,
28383 IX86_BUILTIN_VPERMDF512,
28384 IX86_BUILTIN_VPERMDI512,
28385 IX86_BUILTIN_VPERMI2VARD512,
28386 IX86_BUILTIN_VPERMI2VARPD512,
28387 IX86_BUILTIN_VPERMI2VARPS512,
28388 IX86_BUILTIN_VPERMI2VARQ512,
28389 IX86_BUILTIN_VPERMILPD512,
28390 IX86_BUILTIN_VPERMILPS512,
28391 IX86_BUILTIN_VPERMILVARPD512,
28392 IX86_BUILTIN_VPERMILVARPS512,
28393 IX86_BUILTIN_VPERMT2VARD512,
28394 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
28395 IX86_BUILTIN_VPERMT2VARPD512,
28396 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
28397 IX86_BUILTIN_VPERMT2VARPS512,
28398 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
28399 IX86_BUILTIN_VPERMT2VARQ512,
28400 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
28401 IX86_BUILTIN_VPERMVARDF512,
28402 IX86_BUILTIN_VPERMVARDI512,
28403 IX86_BUILTIN_VPERMVARSF512,
28404 IX86_BUILTIN_VPERMVARSI512,
28405 IX86_BUILTIN_VTERNLOGD512_MASK,
28406 IX86_BUILTIN_VTERNLOGD512_MASKZ,
28407 IX86_BUILTIN_VTERNLOGQ512_MASK,
28408 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
28410 /* Mask arithmetic operations */
28411 IX86_BUILTIN_KAND16,
28412 IX86_BUILTIN_KANDN16,
28413 IX86_BUILTIN_KNOT16,
28414 IX86_BUILTIN_KOR16,
28415 IX86_BUILTIN_KORTESTC16,
28416 IX86_BUILTIN_KORTESTZ16,
28417 IX86_BUILTIN_KUNPCKBW,
28418 IX86_BUILTIN_KXNOR16,
28419 IX86_BUILTIN_KXOR16,
28420 IX86_BUILTIN_KMOV16,
28422 /* Alternate 4 and 8 element gather/scatter for the vectorizer
28423 where all operands are 32-byte or 64-byte wide respectively. */
28424 IX86_BUILTIN_GATHERALTSIV4DF,
28425 IX86_BUILTIN_GATHERALTDIV8SF,
28426 IX86_BUILTIN_GATHERALTSIV4DI,
28427 IX86_BUILTIN_GATHERALTDIV8SI,
28428 IX86_BUILTIN_GATHER3ALTDIV16SF,
28429 IX86_BUILTIN_GATHER3ALTDIV16SI,
28430 IX86_BUILTIN_GATHER3ALTSIV8DF,
28431 IX86_BUILTIN_GATHER3ALTSIV8DI,
28432 IX86_BUILTIN_GATHER3DIV16SF,
28433 IX86_BUILTIN_GATHER3DIV16SI,
28434 IX86_BUILTIN_GATHER3DIV8DF,
28435 IX86_BUILTIN_GATHER3DIV8DI,
28436 IX86_BUILTIN_GATHER3SIV16SF,
28437 IX86_BUILTIN_GATHER3SIV16SI,
28438 IX86_BUILTIN_GATHER3SIV8DF,
28439 IX86_BUILTIN_GATHER3SIV8DI,
28440 IX86_BUILTIN_SCATTERDIV16SF,
28441 IX86_BUILTIN_SCATTERDIV16SI,
28442 IX86_BUILTIN_SCATTERDIV8DF,
28443 IX86_BUILTIN_SCATTERDIV8DI,
28444 IX86_BUILTIN_SCATTERSIV16SF,
28445 IX86_BUILTIN_SCATTERSIV16SI,
28446 IX86_BUILTIN_SCATTERSIV8DF,
28447 IX86_BUILTIN_SCATTERSIV8DI,
28449 /* AVX512PF */
28450 IX86_BUILTIN_GATHERPFQPD,
28451 IX86_BUILTIN_GATHERPFDPS,
28452 IX86_BUILTIN_GATHERPFDPD,
28453 IX86_BUILTIN_GATHERPFQPS,
28454 IX86_BUILTIN_SCATTERPFDPD,
28455 IX86_BUILTIN_SCATTERPFDPS,
28456 IX86_BUILTIN_SCATTERPFQPD,
28457 IX86_BUILTIN_SCATTERPFQPS,
28459 /* AVX-512ER */
28460 IX86_BUILTIN_EXP2PD_MASK,
28461 IX86_BUILTIN_EXP2PS_MASK,
28462 IX86_BUILTIN_EXP2PS,
28463 IX86_BUILTIN_RCP28PD,
28464 IX86_BUILTIN_RCP28PS,
28465 IX86_BUILTIN_RCP28SD,
28466 IX86_BUILTIN_RCP28SS,
28467 IX86_BUILTIN_RSQRT28PD,
28468 IX86_BUILTIN_RSQRT28PS,
28469 IX86_BUILTIN_RSQRT28SD,
28470 IX86_BUILTIN_RSQRT28SS,
28472 /* SHA builtins. */
28473 IX86_BUILTIN_SHA1MSG1,
28474 IX86_BUILTIN_SHA1MSG2,
28475 IX86_BUILTIN_SHA1NEXTE,
28476 IX86_BUILTIN_SHA1RNDS4,
28477 IX86_BUILTIN_SHA256MSG1,
28478 IX86_BUILTIN_SHA256MSG2,
28479 IX86_BUILTIN_SHA256RNDS2,
28481 /* TFmode support builtins. */
28482 IX86_BUILTIN_INFQ,
28483 IX86_BUILTIN_HUGE_VALQ,
28484 IX86_BUILTIN_FABSQ,
28485 IX86_BUILTIN_COPYSIGNQ,
28487 /* Vectorizer support builtins. */
28488 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
28489 IX86_BUILTIN_CPYSGNPS,
28490 IX86_BUILTIN_CPYSGNPD,
28491 IX86_BUILTIN_CPYSGNPS256,
28492 IX86_BUILTIN_CPYSGNPS512,
28493 IX86_BUILTIN_CPYSGNPD256,
28494 IX86_BUILTIN_CPYSGNPD512,
28495 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
28496 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
28499 /* FMA4 instructions. */
28500 IX86_BUILTIN_VFMADDSS,
28501 IX86_BUILTIN_VFMADDSD,
28502 IX86_BUILTIN_VFMADDPS,
28503 IX86_BUILTIN_VFMADDPD,
28504 IX86_BUILTIN_VFMADDPS256,
28505 IX86_BUILTIN_VFMADDPD256,
28506 IX86_BUILTIN_VFMADDSUBPS,
28507 IX86_BUILTIN_VFMADDSUBPD,
28508 IX86_BUILTIN_VFMADDSUBPS256,
28509 IX86_BUILTIN_VFMADDSUBPD256,
28511 /* FMA3 instructions. */
28512 IX86_BUILTIN_VFMADDSS3,
28513 IX86_BUILTIN_VFMADDSD3,
28515 /* XOP instructions. */
28516 IX86_BUILTIN_VPCMOV,
28517 IX86_BUILTIN_VPCMOV_V2DI,
28518 IX86_BUILTIN_VPCMOV_V4SI,
28519 IX86_BUILTIN_VPCMOV_V8HI,
28520 IX86_BUILTIN_VPCMOV_V16QI,
28521 IX86_BUILTIN_VPCMOV_V4SF,
28522 IX86_BUILTIN_VPCMOV_V2DF,
28523 IX86_BUILTIN_VPCMOV256,
28524 IX86_BUILTIN_VPCMOV_V4DI256,
28525 IX86_BUILTIN_VPCMOV_V8SI256,
28526 IX86_BUILTIN_VPCMOV_V16HI256,
28527 IX86_BUILTIN_VPCMOV_V32QI256,
28528 IX86_BUILTIN_VPCMOV_V8SF256,
28529 IX86_BUILTIN_VPCMOV_V4DF256,
28531 IX86_BUILTIN_VPPERM,
28533 IX86_BUILTIN_VPMACSSWW,
28534 IX86_BUILTIN_VPMACSWW,
28535 IX86_BUILTIN_VPMACSSWD,
28536 IX86_BUILTIN_VPMACSWD,
28537 IX86_BUILTIN_VPMACSSDD,
28538 IX86_BUILTIN_VPMACSDD,
28539 IX86_BUILTIN_VPMACSSDQL,
28540 IX86_BUILTIN_VPMACSSDQH,
28541 IX86_BUILTIN_VPMACSDQL,
28542 IX86_BUILTIN_VPMACSDQH,
28543 IX86_BUILTIN_VPMADCSSWD,
28544 IX86_BUILTIN_VPMADCSWD,
28546 IX86_BUILTIN_VPHADDBW,
28547 IX86_BUILTIN_VPHADDBD,
28548 IX86_BUILTIN_VPHADDBQ,
28549 IX86_BUILTIN_VPHADDWD,
28550 IX86_BUILTIN_VPHADDWQ,
28551 IX86_BUILTIN_VPHADDDQ,
28552 IX86_BUILTIN_VPHADDUBW,
28553 IX86_BUILTIN_VPHADDUBD,
28554 IX86_BUILTIN_VPHADDUBQ,
28555 IX86_BUILTIN_VPHADDUWD,
28556 IX86_BUILTIN_VPHADDUWQ,
28557 IX86_BUILTIN_VPHADDUDQ,
28558 IX86_BUILTIN_VPHSUBBW,
28559 IX86_BUILTIN_VPHSUBWD,
28560 IX86_BUILTIN_VPHSUBDQ,
28562 IX86_BUILTIN_VPROTB,
28563 IX86_BUILTIN_VPROTW,
28564 IX86_BUILTIN_VPROTD,
28565 IX86_BUILTIN_VPROTQ,
28566 IX86_BUILTIN_VPROTB_IMM,
28567 IX86_BUILTIN_VPROTW_IMM,
28568 IX86_BUILTIN_VPROTD_IMM,
28569 IX86_BUILTIN_VPROTQ_IMM,
28571 IX86_BUILTIN_VPSHLB,
28572 IX86_BUILTIN_VPSHLW,
28573 IX86_BUILTIN_VPSHLD,
28574 IX86_BUILTIN_VPSHLQ,
28575 IX86_BUILTIN_VPSHAB,
28576 IX86_BUILTIN_VPSHAW,
28577 IX86_BUILTIN_VPSHAD,
28578 IX86_BUILTIN_VPSHAQ,
28580 IX86_BUILTIN_VFRCZSS,
28581 IX86_BUILTIN_VFRCZSD,
28582 IX86_BUILTIN_VFRCZPS,
28583 IX86_BUILTIN_VFRCZPD,
28584 IX86_BUILTIN_VFRCZPS256,
28585 IX86_BUILTIN_VFRCZPD256,
28587 IX86_BUILTIN_VPCOMEQUB,
28588 IX86_BUILTIN_VPCOMNEUB,
28589 IX86_BUILTIN_VPCOMLTUB,
28590 IX86_BUILTIN_VPCOMLEUB,
28591 IX86_BUILTIN_VPCOMGTUB,
28592 IX86_BUILTIN_VPCOMGEUB,
28593 IX86_BUILTIN_VPCOMFALSEUB,
28594 IX86_BUILTIN_VPCOMTRUEUB,
28596 IX86_BUILTIN_VPCOMEQUW,
28597 IX86_BUILTIN_VPCOMNEUW,
28598 IX86_BUILTIN_VPCOMLTUW,
28599 IX86_BUILTIN_VPCOMLEUW,
28600 IX86_BUILTIN_VPCOMGTUW,
28601 IX86_BUILTIN_VPCOMGEUW,
28602 IX86_BUILTIN_VPCOMFALSEUW,
28603 IX86_BUILTIN_VPCOMTRUEUW,
28605 IX86_BUILTIN_VPCOMEQUD,
28606 IX86_BUILTIN_VPCOMNEUD,
28607 IX86_BUILTIN_VPCOMLTUD,
28608 IX86_BUILTIN_VPCOMLEUD,
28609 IX86_BUILTIN_VPCOMGTUD,
28610 IX86_BUILTIN_VPCOMGEUD,
28611 IX86_BUILTIN_VPCOMFALSEUD,
28612 IX86_BUILTIN_VPCOMTRUEUD,
28614 IX86_BUILTIN_VPCOMEQUQ,
28615 IX86_BUILTIN_VPCOMNEUQ,
28616 IX86_BUILTIN_VPCOMLTUQ,
28617 IX86_BUILTIN_VPCOMLEUQ,
28618 IX86_BUILTIN_VPCOMGTUQ,
28619 IX86_BUILTIN_VPCOMGEUQ,
28620 IX86_BUILTIN_VPCOMFALSEUQ,
28621 IX86_BUILTIN_VPCOMTRUEUQ,
28623 IX86_BUILTIN_VPCOMEQB,
28624 IX86_BUILTIN_VPCOMNEB,
28625 IX86_BUILTIN_VPCOMLTB,
28626 IX86_BUILTIN_VPCOMLEB,
28627 IX86_BUILTIN_VPCOMGTB,
28628 IX86_BUILTIN_VPCOMGEB,
28629 IX86_BUILTIN_VPCOMFALSEB,
28630 IX86_BUILTIN_VPCOMTRUEB,
28632 IX86_BUILTIN_VPCOMEQW,
28633 IX86_BUILTIN_VPCOMNEW,
28634 IX86_BUILTIN_VPCOMLTW,
28635 IX86_BUILTIN_VPCOMLEW,
28636 IX86_BUILTIN_VPCOMGTW,
28637 IX86_BUILTIN_VPCOMGEW,
28638 IX86_BUILTIN_VPCOMFALSEW,
28639 IX86_BUILTIN_VPCOMTRUEW,
28641 IX86_BUILTIN_VPCOMEQD,
28642 IX86_BUILTIN_VPCOMNED,
28643 IX86_BUILTIN_VPCOMLTD,
28644 IX86_BUILTIN_VPCOMLED,
28645 IX86_BUILTIN_VPCOMGTD,
28646 IX86_BUILTIN_VPCOMGED,
28647 IX86_BUILTIN_VPCOMFALSED,
28648 IX86_BUILTIN_VPCOMTRUED,
28650 IX86_BUILTIN_VPCOMEQQ,
28651 IX86_BUILTIN_VPCOMNEQ,
28652 IX86_BUILTIN_VPCOMLTQ,
28653 IX86_BUILTIN_VPCOMLEQ,
28654 IX86_BUILTIN_VPCOMGTQ,
28655 IX86_BUILTIN_VPCOMGEQ,
28656 IX86_BUILTIN_VPCOMFALSEQ,
28657 IX86_BUILTIN_VPCOMTRUEQ,
28659 /* LWP instructions. */
28660 IX86_BUILTIN_LLWPCB,
28661 IX86_BUILTIN_SLWPCB,
28662 IX86_BUILTIN_LWPVAL32,
28663 IX86_BUILTIN_LWPVAL64,
28664 IX86_BUILTIN_LWPINS32,
28665 IX86_BUILTIN_LWPINS64,
28667 IX86_BUILTIN_CLZS,
28669 /* RTM */
28670 IX86_BUILTIN_XBEGIN,
28671 IX86_BUILTIN_XEND,
28672 IX86_BUILTIN_XABORT,
28673 IX86_BUILTIN_XTEST,
28675 /* BMI instructions. */
28676 IX86_BUILTIN_BEXTR32,
28677 IX86_BUILTIN_BEXTR64,
28678 IX86_BUILTIN_CTZS,
28680 /* TBM instructions. */
28681 IX86_BUILTIN_BEXTRI32,
28682 IX86_BUILTIN_BEXTRI64,
28684 /* BMI2 instructions. */
28685 IX86_BUILTIN_BZHI32,
28686 IX86_BUILTIN_BZHI64,
28687 IX86_BUILTIN_PDEP32,
28688 IX86_BUILTIN_PDEP64,
28689 IX86_BUILTIN_PEXT32,
28690 IX86_BUILTIN_PEXT64,
28692 /* ADX instructions. */
28693 IX86_BUILTIN_ADDCARRYX32,
28694 IX86_BUILTIN_ADDCARRYX64,
28696 /* FSGSBASE instructions. */
28697 IX86_BUILTIN_RDFSBASE32,
28698 IX86_BUILTIN_RDFSBASE64,
28699 IX86_BUILTIN_RDGSBASE32,
28700 IX86_BUILTIN_RDGSBASE64,
28701 IX86_BUILTIN_WRFSBASE32,
28702 IX86_BUILTIN_WRFSBASE64,
28703 IX86_BUILTIN_WRGSBASE32,
28704 IX86_BUILTIN_WRGSBASE64,
28706 /* RDRND instructions. */
28707 IX86_BUILTIN_RDRAND16_STEP,
28708 IX86_BUILTIN_RDRAND32_STEP,
28709 IX86_BUILTIN_RDRAND64_STEP,
28711 /* RDSEED instructions. */
28712 IX86_BUILTIN_RDSEED16_STEP,
28713 IX86_BUILTIN_RDSEED32_STEP,
28714 IX86_BUILTIN_RDSEED64_STEP,
28716 /* F16C instructions. */
28717 IX86_BUILTIN_CVTPH2PS,
28718 IX86_BUILTIN_CVTPH2PS256,
28719 IX86_BUILTIN_CVTPS2PH,
28720 IX86_BUILTIN_CVTPS2PH256,
28722 /* CFString built-in for darwin */
28723 IX86_BUILTIN_CFSTRING,
28725 /* Builtins to get CPU type and supported features. */
28726 IX86_BUILTIN_CPU_INIT,
28727 IX86_BUILTIN_CPU_IS,
28728 IX86_BUILTIN_CPU_SUPPORTS,
28730 /* Read/write FLAGS register built-ins. */
28731 IX86_BUILTIN_READ_FLAGS,
28732 IX86_BUILTIN_WRITE_FLAGS,
28734 IX86_BUILTIN_MAX
28735 };
28737 /* Table for the ix86 builtin decls. */
28740 /* Table of all of the builtin functions that are possible with different ISA's
28741 but are waiting to be built until a function is declared to use that
28742 ISA. */
28749 };
28754 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
28755 of which isa_flags to use in the ix86_builtins_isa array. Stores the
28756 function decl in the ix86_builtins array. Returns the function decl or
28757 NULL_TREE, if the builtin was not added.
28759 If the front end has a special hook for builtin functions, delay adding
28760 builtin functions that aren't in the current ISA until the ISA is changed
28761 with function specific optimization. Doing so, can save about 300K for the
28762 default compiler. When the builtin is expanded, check at that time whether
28763 it is valid.
28765 If the front end doesn't have a special hook, record all builtins, even if
28766 it isn't an instruction set in the current ISA in case the user uses
28767 function specific options for a different ISA, so that we don't get scope
28768 errors if a builtin is added in the middle of a function scope. */
28774 {
28778 {
28787 {
28793 }
28794 else
28795 {
28801 }
28802 }
28805 }
28807 /* Like def_builtin, but also marks the function decl "const". */
28812 {
28816 else
28820 }
28822 /* Add any new builtin functions for a given ISA that may not have been
28823 declared. This saves a bit of space compared to adding all of the
28824 declarations to the tree, even if we didn't use them. */
28826 static void
28828 {
28832 {
28835 {
28838 /* Don't define the builtin again. */
28844 NULL_TREE);
28849 }
28850 }
28851 }
28853 /* Bits for builtin_description.flag. */
28855 /* Set when we don't support the comparison natively, and should
28856 swap_comparison in order to support it. */
28857 #define BUILTIN_DESC_SWAP_OPERANDS 1
28859 struct builtin_description
28860 {
28867 };
28870 {
28871 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
28872 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
28873 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
28874 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
28875 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
28876 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
28877 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
28878 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
28879 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
28880 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
28881 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
28882 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
28883 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
28884 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
28885 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
28886 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
28887 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
28888 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
28889 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
28890 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
28891 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
28892 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
28893 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
28894 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
28895 };
28898 {
28899 /* SSE4.2 */
28900 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
28901 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
28902 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
28903 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
28904 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
28905 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
28906 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
28907 };
28910 {
28911 /* SSE4.2 */
28912 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
28913 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
28914 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
28915 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
28916 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
28917 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
28918 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
28919 };
28921 /* Special builtins with variable number of arguments. */
28923 {
28924 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
28925 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
28926 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
28928 /* 80387 (for use internally for atomic compound assignment). */
28929 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
28930 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
28931 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) VOID_FTYPE_PUSHORT },
28932 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
28934 /* MMX */
28935 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
28937 /* 3DNow! */
28938 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
28940 /* FXSR, XSAVE and XSAVEOPT */
28941 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
28942 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
28943 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28944 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28945 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28947 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
28948 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
28949 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28950 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28951 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
28953 /* SSE */
28954 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
28955 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
28956 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
28958 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
28959 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
28960 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
28961 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
28963 /* SSE or 3DNow!A */
28964 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
28965 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
28967 /* SSE2 */
28968 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
28969 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
28970 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
28971 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
28972 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
28973 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
28974 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
28975 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
28976 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
28977 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
28979 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
28980 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
28982 /* SSE3 */
28983 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
28985 /* SSE4.1 */
28986 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
28988 /* SSE4A */
28989 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
28990 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
28992 /* AVX */
28993 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
28994 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
28996 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
28997 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
28998 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
28999 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
29000 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
29002 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
29003 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
29004 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
29005 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
29006 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
29007 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
29008 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
29010 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
29011 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
29012 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
29014 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
29015 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
29016 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
29017 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
29018 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
29019 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
29020 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
29021 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
29023 /* AVX2 */
29024 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
29025 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
29026 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
29027 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
29028 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
29029 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
29030 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
29031 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
29032 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
29034 /* AVX512F */
29035 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29036 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29037 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29038 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29039 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29040 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29041 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29042 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29044 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29047 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29048 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29049 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29050 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29051 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29052 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29053 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29054 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29055 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
29056 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
29057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
29058 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
29059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29062 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29063 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29069 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29070 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29071 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29072 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29075 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29077 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29078 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29079 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29080 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29083 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
29084 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
29085 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
29086 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
29087 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
29088 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
29090 /* FSGSBASE */
29091 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29092 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
29093 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29094 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
29095 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
29096 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
29097 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
29098 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
29100 /* RTM */
29101 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29102 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
29103 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
29104 };
29106 /* Builtins with variable number of arguments. */
29108 {
29109 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
29110 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
29111 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
29112 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
29113 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
29114 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
29115 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
29117 /* MMX */
29118 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29119 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29120 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29121 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29122 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29123 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29125 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29126 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29127 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29128 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29129 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29130 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29131 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29132 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29134 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29135 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29137 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29138 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29139 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29140 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29142 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29143 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29144 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29145 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29146 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29147 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29149 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29150 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29151 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29152 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29153 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
29154 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
29156 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
29157 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
29158 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
29160 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
29162 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29163 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29164 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
29165 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29166 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29167 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
29169 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29170 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29171 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
29172 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29173 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29174 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
29176 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29177 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29178 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29179 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29181 /* 3DNow! */
29182 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
29183 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
29184 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29185 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29187 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29188 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29189 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29190 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29191 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29192 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29193 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29194 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29195 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29196 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29197 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29198 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29199 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29200 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29201 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29203 /* 3DNow!A */
29204 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
29205 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
29206 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
29207 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29208 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29209 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29211 /* SSE */
29212 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
29213 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29214 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29215 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29216 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29217 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29218 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
29219 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
29220 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
29221 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
29222 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
29223 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
29225 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29227 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29228 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29229 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29230 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29231 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29232 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29233 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29234 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29236 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
29237 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
29238 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
29239 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29240 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29241 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29242 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
29243 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
29244 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
29245 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29246 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
29247 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29248 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
29249 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
29250 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
29251 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29252 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
29253 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
29254 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
29255 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29257 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29258 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29259 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29260 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29262 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29263 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29264 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29265 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29267 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29269 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29270 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29271 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29272 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29273 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29275 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
29276 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
29277 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
29279 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
29281 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29282 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29283 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29285 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
29286 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
29288 /* SSE MMX or 3Dnow!A */
29289 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29290 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29291 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29293 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29294 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29295 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29296 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29298 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
29299 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
29301 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
29303 /* SSE2 */
29304 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29306 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
29307 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
29308 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
29309 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
29310 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
29312 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
29313 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
29314 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
29315 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
29316 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
29318 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
29320 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
29321 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
29322 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
29323 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
29325 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29326 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
29327 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29329 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29330 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29331 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29332 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29333 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29334 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29335 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29336 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29338 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
29339 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
29340 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
29341 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29342 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
29343 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29344 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
29345 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
29346 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
29347 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29348 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29349 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29350 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
29351 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
29352 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
29353 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29354 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
29355 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
29356 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
29357 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29359 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29360 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29361 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29362 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29364 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29365 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29366 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29367 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29369 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29371 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29372 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29373 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29375 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
29377 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29378 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29379 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29380 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29381 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29382 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29383 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29384 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29386 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29387 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29388 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29389 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29390 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29391 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29392 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29393 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29395 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29396 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
29398 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29399 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29400 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29401 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29403 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29404 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29406 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29407 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29408 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29409 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29410 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29411 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29413 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29414 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29415 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29416 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29418 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29419 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29420 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29421 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29422 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29423 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29424 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29425 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29427 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
29428 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
29429 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
29431 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29432 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
29434 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
29435 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
29437 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
29439 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
29440 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
29441 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
29442 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
29444 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
29445 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29446 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29447 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
29448 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29449 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29450 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
29452 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
29453 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29454 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29455 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
29456 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29457 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29458 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
29460 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29461 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29462 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29463 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29465 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
29466 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
29467 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
29469 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
29471 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29473 /* SSE2 MMX */
29474 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
29475 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
29477 /* SSE3 */
29478 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
29479 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29481 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29482 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29483 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29484 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29485 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29486 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29488 /* SSSE3 */
29489 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
29490 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
29491 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29492 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
29493 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
29494 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
29496 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29497 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29498 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29499 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29500 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29501 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29502 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29503 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29504 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29505 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29506 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29507 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29508 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
29509 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
29510 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29511 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29512 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29513 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29514 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29515 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29516 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29517 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29518 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29519 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29521 /* SSSE3. */
29522 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
29523 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
29525 /* SSE4.1 */
29526 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29527 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29528 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
29529 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
29530 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29531 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29532 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29533 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
29534 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
29535 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
29537 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
29538 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
29539 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
29540 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
29541 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
29542 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
29543 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
29544 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
29545 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
29546 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
29547 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
29548 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
29549 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29551 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
29552 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29553 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29554 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29555 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29556 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29557 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29558 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29559 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29560 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29561 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
29562 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29564 /* SSE4.1 */
29565 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
29566 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
29567 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29568 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29570 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
29571 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
29572 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
29573 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
29575 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
29576 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
29578 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
29579 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
29581 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
29582 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
29583 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
29584 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
29586 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
29587 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
29589 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29590 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29592 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29593 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29594 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29596 /* SSE4.2 */
29597 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29598 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
29599 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
29600 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29601 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29603 /* SSE4A */
29604 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
29605 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
29606 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
29607 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29609 /* AES */
29610 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
29611 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29613 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29614 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29615 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29616 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29618 /* PCLMUL */
29619 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
29621 /* AVX */
29622 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29623 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29624 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29625 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29626 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29627 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29628 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29629 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29630 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29631 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29632 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29633 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29634 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29635 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29636 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29637 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29638 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29639 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29640 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29641 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29642 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29643 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29644 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29645 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29646 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29647 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29649 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
29650 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
29651 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
29652 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
29654 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29655 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29656 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
29657 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
29658 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29659 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29660 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29661 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29662 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29663 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29664 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29665 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29666 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29667 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
29668 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
29669 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
29670 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
29671 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
29672 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
29673 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29674 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
29675 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
29676 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
29677 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29678 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29679 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29680 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
29681 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
29682 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
29683 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29684 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
29685 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
29686 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
29687 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
29689 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29690 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29691 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29693 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29694 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29695 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29696 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29697 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29699 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29701 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29702 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
29704 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
29705 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
29706 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
29707 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
29709 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29710 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
29712 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
29713 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
29715 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
29716 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
29717 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
29718 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
29720 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
29721 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
29723 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29724 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29726 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29727 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29728 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29729 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29731 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
29732 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
29733 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
29734 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
29735 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
29736 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
29738 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29739 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29740 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29741 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29742 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29743 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29744 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29745 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29746 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29747 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29748 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29749 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29750 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29751 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29752 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29754 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
29755 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
29757 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29758 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29760 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
29762 /* AVX2 */
29763 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
29764 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
29765 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
29766 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
29767 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
29768 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
29769 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
29770 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
29771 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29772 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29773 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29774 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29775 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29776 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29777 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29778 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29779 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
29780 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29781 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29782 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29783 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29784 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
29785 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
29786 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29787 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29788 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29789 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29790 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29791 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29792 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29793 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29794 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29795 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29796 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29797 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29798 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29799 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29800 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
29801 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
29802 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29803 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29804 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29805 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29806 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29807 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29808 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29809 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29810 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29811 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29812 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29813 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29814 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
29815 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
29816 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
29817 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
29818 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
29819 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
29820 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
29821 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
29822 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
29823 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
29824 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
29825 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
29826 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
29827 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
29828 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29829 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29830 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29831 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29832 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29833 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
29834 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29835 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
29836 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29837 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
29838 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
29839 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
29840 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29841 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29842 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29843 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
29844 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29845 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29846 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29847 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29848 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
29849 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
29850 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29851 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29852 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29853 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29854 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
29855 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29856 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29857 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29858 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29859 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
29860 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
29861 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29862 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29863 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29864 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29865 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29866 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29867 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29868 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29869 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29870 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29871 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29872 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29873 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29874 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29875 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29876 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29877 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29878 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29879 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
29880 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
29881 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
29882 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
29883 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
29884 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
29885 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
29886 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
29887 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
29888 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
29889 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29890 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
29891 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29892 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29893 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
29894 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29895 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
29896 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
29897 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
29898 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
29899 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29900 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29901 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29902 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29903 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29904 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29905 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29906 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29907 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29908 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29910 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
29912 /* BMI */
29913 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29914 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29915 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
29917 /* TBM */
29918 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29919 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29921 /* F16C */
29922 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
29923 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
29924 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
29925 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
29927 /* BMI2 */
29928 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29929 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29930 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29931 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29932 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29933 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29935 /* AVX512F */
29936 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
29937 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
29938 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
29942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
29943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
29944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
29945 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
29946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
29947 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
29948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
29949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
29950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
29953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
29954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
29955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
29956 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29958 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29960 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
29961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
29962 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
29963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
29964 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
29965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
29966 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
29967 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
29968 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29970 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
29971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29972 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
29973 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29974 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
29975 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29976 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
29977 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
29978 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
29979 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
29980 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
29981 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
29982 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
29983 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
29984 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
29985 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
29986 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
29987 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
29988 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
29989 { OPTION_MASK_ISA_AVX512F & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_memv8di_mask, "__builtin_ia32_pbroadcastq512_mem_mask", IX86_BUILTIN_PBROADCASTQ512_MEM, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
29990 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
29991 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
29992 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
29993 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
29994 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29995 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
29996 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29997 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
29998 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
29999 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30000 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30001 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30002 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30003 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30004 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30005 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30006 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30007 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30008 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30009 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30010 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30011 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30012 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30013 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30014 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30015 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30016 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30017 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30018 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
30019 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
30020 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
30021 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
30022 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
30023 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30024 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30025 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30026 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30027 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30028 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
30029 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
30030 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
30031 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
30032 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
30033 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
30034 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30035 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
30036 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30037 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30038 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30039 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30040 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30041 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30042 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30044 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30047 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30048 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30049 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30050 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30051 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30052 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30053 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30054 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30055 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30056 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30058 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30062 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30063 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30069 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30070 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30071 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30072 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30075 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30077 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30078 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30079 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30080 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30083 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30084 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
30086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
30087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
30088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
30089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
30090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
30091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
30092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
30093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
30094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
30095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
30096 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
30097 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30098 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30099 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30100 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
30102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
30108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
30109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
30114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
30115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
30116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
30117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
30124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
30125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
30126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
30128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
30129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
30130 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
30131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
30132 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
30133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
30134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
30135 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
30137 /* Mask arithmetic operations */
30138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
30141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30144 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
30145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30147 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
30149 /* SHA */
30150 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30151 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30152 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30153 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
30154 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30155 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30156 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
30157 };
30159 /* Builtins with rounding support. */
30161 {
30162 /* AVX512F */
30163 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30164 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30165 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30166 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30167 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
30168 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
30169 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
30170 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
30171 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
30172 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
30173 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
30174 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30175 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
30176 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30177 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
30178 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30179 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
30180 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30181 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
30182 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
30183 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
30184 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
30185 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
30186 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30187 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30188 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30189 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30190 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
30191 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
30192 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
30193 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
30194 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30195 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30196 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30197 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30198 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
30199 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
30200 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
30201 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
30202 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
30203 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
30204 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
30205 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
30206 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30207 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30208 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30209 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30210 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
30211 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
30212 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
30213 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
30214 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30215 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30216 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30217 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30218 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30219 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30220 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30221 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30222 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30223 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30224 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30225 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30226 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
30227 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
30228 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
30229 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
30230 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30231 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30232 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30233 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30234 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30235 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30236 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30237 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30238 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30239 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30240 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30241 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30242 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
30243 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
30244 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
30245 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
30246 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
30247 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
30248 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
30249 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
30250 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
30251 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
30252 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
30253 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
30254 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
30255 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
30256 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
30257 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
30258 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30259 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30260 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30261 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30262 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30263 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30264 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
30265 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
30266 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30267 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30268 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30269 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30270 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30271 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30272 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30273 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30274 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30275 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30276 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30277 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30278 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30279 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30280 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30281 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30283 /* AVX512ER */
30284 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30285 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30286 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30287 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30288 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30289 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30290 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30291 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30292 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30293 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30294 };
30296 /* FMA4 and XOP. */
30297 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
30298 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
30299 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
30300 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
30301 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
30302 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
30303 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
30304 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
30305 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
30306 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
30307 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
30308 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
30309 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
30310 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
30311 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
30312 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
30313 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
30314 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
30315 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
30316 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
30317 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
30318 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
30319 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
30320 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
30321 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
30322 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
30323 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
30324 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
30325 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
30326 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
30327 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
30328 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
30329 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
30330 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
30331 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
30332 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
30333 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
30334 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
30335 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
30336 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
30337 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
30338 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
30339 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
30340 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
30341 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
30342 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
30343 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
30344 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
30345 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
30346 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
30347 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
30348 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
30351 {
30392 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
30393 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
30394 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
30395 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
30396 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
30397 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
30398 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
30400 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
30401 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
30402 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
30403 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
30404 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
30405 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
30406 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
30408 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
30410 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
30411 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
30412 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30413 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30414 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
30415 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
30416 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30417 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30418 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30419 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30420 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30421 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30423 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30424 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
30425 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
30426 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
30427 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
30428 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
30429 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
30430 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
30431 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30432 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
30433 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
30434 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
30435 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30436 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
30437 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
30438 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
30440 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
30441 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
30442 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
30443 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
30444 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
30445 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
30447 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30448 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
30449 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
30450 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30451 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
30452 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30453 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30454 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
30455 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
30456 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30457 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
30458 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30459 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30460 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30461 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30463 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
30464 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
30465 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
30466 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
30467 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
30468 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
30469 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
30471 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
30472 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
30473 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
30474 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
30475 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
30476 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
30477 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
30479 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
30480 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
30481 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
30482 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
30483 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
30484 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
30485 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
30487 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
30488 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
30489 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
30490 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
30491 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
30492 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
30493 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
30495 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
30496 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
30497 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
30498 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
30499 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
30500 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
30501 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
30503 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
30504 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
30505 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
30506 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
30507 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
30508 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
30509 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
30511 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
30512 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
30513 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
30514 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
30515 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
30516 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
30517 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
30519 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
30520 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
30521 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
30522 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
30523 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
30524 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
30525 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
30527 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
30528 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
30529 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
30530 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
30531 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
30532 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
30533 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
30534 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
30536 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
30537 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
30538 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
30539 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
30540 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
30541 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
30542 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
30543 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
30545 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
30546 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
30547 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
30548 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
30550 };
30551 \f
30552 /* TM vector builtins. */
30554 /* Reuse the existing x86-specific `struct builtin_description' cause
30555 we're lazy. Add casts to make them fit. */
30557 {
30558 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30559 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30560 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30561 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30562 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30563 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30564 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30566 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30567 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30568 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30569 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30570 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30571 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30572 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30574 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30575 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30576 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30577 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30578 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30579 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30580 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30582 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
30583 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
30584 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
30585 };
30587 /* TM callbacks. */
30589 /* Return the builtin decl needed to load a vector of TYPE. */
30591 static tree
30593 {
30595 {
30597 {
30604 }
30605 }
30607 }
30609 /* Return the builtin decl needed to store a vector of TYPE. */
30611 static tree
30613 {
30615 {
30617 {
30624 }
30625 }
30627 }
30628 \f
30629 /* Initialize the transactional memory vector load/store builtins. */
30631 static void
30633 {
30637 tree decl;
30644 /* If there are no builtins defined, we must be compiling in a
30645 language without trans-mem support. */
30649 /* Use whatever attributes a normal TM load has. */
30653 /* Use whatever attributes a normal TM store has. */
30657 /* Use whatever attributes a normal TM log has. */
30665 {
30669 {
30677 {
30680 }
30682 {
30685 }
30686 else
30687 {
30690 }
30692 /* The builtin without the prefix for
30693 calling it directly. */
30695 attrs);
30696 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
30697 set the TYPE_ATTRIBUTES. */
30701 }
30702 }
30703 }
30705 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
30706 in the current target ISA to allow the user to compile particular modules
30707 with different target specific options that differ from the command line
30708 options. */
30709 static void
30711 {
30716 /* Add all special builtins with variable number of operands. */
30720 {
30726 }
30728 /* Add all builtins with variable number of operands. */
30732 {
30738 }
30740 /* Add all builtins with rounding. */
30744 {
30750 }
30752 /* pcmpestr[im] insns. */
30756 {
30759 else
30762 }
30764 /* pcmpistr[im] insns. */
30768 {
30771 else
30774 }
30776 /* comi/ucomi insns. */
30778 {
30781 else
30784 }
30786 /* SSE */
30792 /* SSE or 3DNow!A */
30795 IX86_BUILTIN_MASKMOVQ);
30797 /* SSE2 */
30806 /* SSE3. */
30812 /* AES */
30826 /* PCLMUL */
30830 /* RDRND */
30837 IX86_BUILTIN_RDRAND64_STEP);
30839 /* AVX2 */
30841 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
30842 IX86_BUILTIN_GATHERSIV2DF);
30845 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
30846 IX86_BUILTIN_GATHERSIV4DF);
30849 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
30850 IX86_BUILTIN_GATHERDIV2DF);
30853 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
30854 IX86_BUILTIN_GATHERDIV4DF);
30857 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
30858 IX86_BUILTIN_GATHERSIV4SF);
30861 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
30862 IX86_BUILTIN_GATHERSIV8SF);
30865 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
30866 IX86_BUILTIN_GATHERDIV4SF);
30869 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
30870 IX86_BUILTIN_GATHERDIV8SF);
30873 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
30874 IX86_BUILTIN_GATHERSIV2DI);
30877 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
30878 IX86_BUILTIN_GATHERSIV4DI);
30881 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
30882 IX86_BUILTIN_GATHERDIV2DI);
30885 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
30886 IX86_BUILTIN_GATHERDIV4DI);
30889 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
30890 IX86_BUILTIN_GATHERSIV4SI);
30893 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
30894 IX86_BUILTIN_GATHERSIV8SI);
30897 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
30898 IX86_BUILTIN_GATHERDIV4SI);
30901 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
30902 IX86_BUILTIN_GATHERDIV8SI);
30905 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
30906 IX86_BUILTIN_GATHERALTSIV4DF);
30909 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
30910 IX86_BUILTIN_GATHERALTDIV8SF);
30913 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
30914 IX86_BUILTIN_GATHERALTSIV4DI);
30917 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
30918 IX86_BUILTIN_GATHERALTDIV8SI);
30920 /* AVX512F */
30922 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
30923 IX86_BUILTIN_GATHER3SIV16SF);
30926 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
30927 IX86_BUILTIN_GATHER3SIV8DF);
30930 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
30931 IX86_BUILTIN_GATHER3DIV16SF);
30934 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
30935 IX86_BUILTIN_GATHER3DIV8DF);
30938 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
30939 IX86_BUILTIN_GATHER3SIV16SI);
30942 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
30943 IX86_BUILTIN_GATHER3SIV8DI);
30946 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
30947 IX86_BUILTIN_GATHER3DIV16SI);
30950 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
30951 IX86_BUILTIN_GATHER3DIV8DI);
30954 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
30955 IX86_BUILTIN_GATHER3ALTSIV8DF);
30958 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
30959 IX86_BUILTIN_GATHER3ALTDIV16SF);
30962 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
30963 IX86_BUILTIN_GATHER3ALTSIV8DI);
30966 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
30967 IX86_BUILTIN_GATHER3ALTDIV16SI);
30970 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
30971 IX86_BUILTIN_SCATTERSIV16SF);
30974 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
30975 IX86_BUILTIN_SCATTERSIV8DF);
30978 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
30979 IX86_BUILTIN_SCATTERDIV16SF);
30982 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
30983 IX86_BUILTIN_SCATTERDIV8DF);
30986 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
30987 IX86_BUILTIN_SCATTERSIV16SI);
30990 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
30991 IX86_BUILTIN_SCATTERSIV8DI);
30994 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
30995 IX86_BUILTIN_SCATTERDIV16SI);
30998 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
30999 IX86_BUILTIN_SCATTERDIV8DI);
31001 /* AVX512PF */
31003 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
31004 IX86_BUILTIN_GATHERPFDPD);
31006 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
31007 IX86_BUILTIN_GATHERPFDPS);
31009 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
31010 IX86_BUILTIN_GATHERPFQPD);
31012 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
31013 IX86_BUILTIN_GATHERPFQPS);
31015 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
31016 IX86_BUILTIN_SCATTERPFDPD);
31018 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
31019 IX86_BUILTIN_SCATTERPFDPS);
31021 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
31022 IX86_BUILTIN_SCATTERPFQPD);
31024 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
31025 IX86_BUILTIN_SCATTERPFQPS);
31027 /* SHA */
31043 /* RTM. */
31047 /* MMX access to the vec_init patterns. */
31052 V4HI_FTYPE_HI_HI_HI_HI,
31053 IX86_BUILTIN_VEC_INIT_V4HI);
31056 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
31057 IX86_BUILTIN_VEC_INIT_V8QI);
31059 /* Access to the vec_extract patterns. */
31081 /* Access to the vec_set patterns. */
31102 /* RDSEED */
31111 /* ADCX */
31116 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
31117 IX86_BUILTIN_ADDCARRYX64);
31119 /* Read/write FLAGS. */
31130 /* Add FMA4 multi-arg argument instructions */
31132 {
31138 }
31139 }
31141 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
31142 to return a pointer to VERSION_DECL if the outcome of the expression
31143 formed by PREDICATE_CHAIN is true. This function will be called during
31144 version dispatch to decide which function version to execute. It returns
31145 the basic block at the end, to which more conditions can be added. */
31147 static basic_block
31150 {
31151 gimple return_stmt;
31153 gimple convert_stmt;
31154 gimple call_cond_stmt;
31155 gimple if_else_stmt;
31161 gimple_seq gseq;
31178 {
31186 }
31189 {
31204 else
31205 {
31206 gimple assign_stmt;
31207 /* Use MIN_EXPR to check if any integer is zero?.
31208 and_expr_var = min_expr <cond_var, and_expr_var> */
31216 }
31217 }
31220 integer_zero_node,
31250 }
31252 /* This parses the attribute arguments to target in DECL and determines
31253 the right builtin to use to match the platform specification.
31254 It returns the priority value for this version decl. If PREDICATE_LIST
31255 is not NULL, it stores the list of cpu features that need to be checked
31256 before dispatching this function. */
31258 static unsigned int
31260 {
31261 tree attrs;
31263 tree target_node;
31270 /* Priority of i386 features, greater value is higher priority. This is
31271 used to decide the order in which function dispatch must happen. For
31272 instance, a version specialized for SSE4.2 should be checked for dispatch
31273 before a version for SSE3, as SSE4.2 implies SSE3. */
31274 enum feature_priority
31275 {
31277 P_MMX,
31278 P_SSE,
31279 P_SSE2,
31280 P_SSE3,
31281 P_SSSE3,
31282 P_PROC_SSSE3,
31283 P_SSE4_A,
31284 P_PROC_SSE4_A,
31285 P_SSE4_1,
31286 P_SSE4_2,
31287 P_PROC_SSE4_2,
31288 P_POPCNT,
31289 P_AVX,
31290 P_PROC_AVX,
31291 P_FMA4,
31292 P_XOP,
31293 P_PROC_XOP,
31294 P_FMA,
31295 P_PROC_FMA,
31296 P_AVX2,
31297 P_PROC_AVX2
31298 };
31302 /* These are the target attribute strings for which a dispatcher is
31303 available, from fold_builtin_cpu. */
31305 static struct _feature_list
31306 {
31309 }
31311 {
31326 };
31329 static unsigned int NUM_FEATURES
31345 /* Return priority zero for default function. */
31349 /* Handle arch= if specified. For priority, set it to be 1 more than
31350 the best instruction set the processor can handle. For instance, if
31351 there is a version for atom and a version for ssse3 (the highest ISA
31352 priority for atom), the atom version must be checked for dispatch
31353 before the ssse3 version. */
31355 {
31365 {
31367 {
31375 else
31376 /* We translate "arch=corei7" and "arch=nehalem" to
31377 "corei7" so that it will be mapped to M_INTEL_COREI7
31378 as cpu type to cover all M_INTEL_COREI7_XXXs. */
31385 else
31392 else
31432 }
31433 }
31438 {
31442 }
31445 {
31447 /* For a C string literal the length includes the trailing NULL. */
31450 predicate_chain);
31451 }
31452 }
31454 /* Process feature name. */
31461 {
31462 /* Do not process "arch=" */
31464 {
31467 }
31469 {
31471 {
31473 {
31478 predicate_chain);
31479 }
31480 /* Find the maximum priority feature. */
31485 }
31486 }
31488 {
31492 }
31494 }
31498 {
31501 attrs_str);
31503 }
31505 {
31508 }
31511 }
31513 /* This compares the priority of target features in function DECL1
31514 and DECL2. It returns positive value if DECL1 is higher priority,
31515 negative value if DECL2 is higher priority and 0 if they are the
31516 same. */
31518 static int
31520 {
31525 }
31527 /* V1 and V2 point to function versions with different priorities
31528 based on the target ISA. This function compares their priorities. */
31530 static int
31532 {
31534 {
31535 tree version_decl;
31536 tree predicate_chain;
31543 }
31545 /* This function generates the dispatch function for
31546 multi-versioned functions. DISPATCH_DECL is the function which will
31547 contain the dispatch logic. FNDECLS are the function choices for
31548 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
31549 in DISPATCH_DECL in which the dispatch code is generated. */
31551 static int
31555 {
31556 tree default_decl;
31557 gimple ifunc_cpu_init_stmt;
31558 gimple_seq gseq;
31560 tree ele;
31566 struct _function_version_info
31567 {
31568 tree version_decl;
31569 tree predicate_chain;
31577 /*fndecls_p is actually a vector. */
31580 /* At least one more version other than the default. */
31587 /* The first version in the vector is the default decl. */
31593 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
31594 constructors, so explicity call __builtin_cpu_init here. */
31605 {
31609 /* Get attribute string, parse it and find the right predicate decl.
31610 The predicate function could be a lengthy combination of many
31611 features, like arch-type and various isa-variants. */
31622 actual_versions++;
31623 }
31625 /* Sort the versions according to descending order of dispatch priority. The
31626 priority is based on the ISA. This is not a perfect solution. There
31627 could still be ambiguity. If more than one function version is suitable
31628 to execute, which one should be dispatched? In future, allow the user
31629 to specify a dispatch priority next to the version. */
31639 /* dispatch default version at the end. */
31645 }
31647 /* Comparator function to be used in qsort routine to sort attribute
31648 specification strings to "target". */
31650 static int
31652 {
31656 }
31658 /* ARGLIST is the argument to target attribute. This function tokenizes
31659 the comma separated arguments, sorts them and returns a string which
31660 is a unique identifier for the comma separated arguments. It also
31661 replaces non-identifier characters "=,-" with "_". */
31665 {
31666 tree arg;
31675 {
31680 argnum++;
31683 argnum++;
31684 }
31689 {
31695 }
31697 /* Replace "=,-" with "_". */
31710 {
31712 i++;
31714 }
31721 {
31726 }
31731 }
31733 /* This function changes the assembler name for functions that are
31734 versions. If DECL is a function version and has a "target"
31735 attribute, it appends the attribute string to its assembler name. */
31737 static tree
31739 {
31740 tree version_attr;
31748 "Function versions cannot be marked as gnu_inline,"
31757 /* target attribute string cannot be NULL. */
31761 version_string
31772 /* Allow assembler name to be modified if already set. */
31780 }
31782 /* This function returns true if FN1 and FN2 are versions of the same function,
31783 that is, the target strings of the function decls are different. This assumes
31784 that FN1 and FN2 have the same signature. */
31786 static bool
31788 {
31800 /* At least one function decl should have the target attribute specified. */
31804 /* Diagnose missing target attribute if one of the decls is already
31805 multi-versioned. */
31807 {
31809 {
31811 {
31816 }
31819 fn2);
31822 /* Prevent diagnosing of the same error multiple times. */
31827 }
31829 }
31834 /* The sorted target strings must be different for fn1 and fn2
31835 to be versions. */
31838 else
31845 }
31847 static tree
31849 {
31850 /* For function version, add the target suffix to the assembler name. */
31854 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
31856 #endif
31859 }
31861 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
31862 is true, append the full path name of the source file. */
31866 {
31874 /* Get a unique name that can be used globally without any chances
31875 of collision at link time. */
31885 /* Use '.' to concatenate names as it is demangler friendly. */
31888 suffix);
31889 else
31893 }
31895 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
31897 /* Make a dispatcher declaration for the multi-versioned function DECL.
31898 Calls to DECL function will be replaced with calls to the dispatcher
31899 by the front-end. Return the decl created. */
31901 static tree
31903 {
31904 tree func_decl;
31924 /* Mark this func as external, the resolver will flip it again if
31925 it gets generated. */
31927 /* This will be of type IFUNCs have to be externally visible. */
31931 }
31933 #endif
31935 /* Returns true if decl is multi-versioned and DECL is the default function,
31936 that is it is not tagged with target specific optimization. */
31938 static bool
31940 {
31949 }
31951 /* Make a dispatcher declaration for the multi-versioned function DECL.
31952 Calls to DECL function will be replaced with calls to the dispatcher
31953 by the front-end. Returns the decl of the dispatcher function. */
31955 static tree
31957 {
31979 /* Find the default version and make it the first node. */
31981 /* Go to the beginning of the chain. */
31986 {
31991 }
31993 /* If there is no default node, just return NULL. */
31997 /* Make default info the first node. */
31999 {
32006 }
32010 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
32012 {
32017 /* Right now, the dispatching is done via ifunc. */
32023 dispatcher_version_info
32028 /* Set the dispatcher for all the versions. */
32031 {
32034 }
32035 }
32036 else
32037 #endif
32038 {
32040 "multiversioning needs ifunc which is not supported "
32042 }
32045 }
32047 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
32048 it to CHAIN. */
32050 static tree
32052 {
32053 tree attr_name;
32054 tree attr_arg_name;
32055 tree attr_args;
32056 tree attr;
32063 }
32065 /* Make the resolver function decl to dispatch the versions of
32066 a multi-versioned function, DEFAULT_DECL. Create an
32067 empty basic block in the resolver and store the pointer in
32068 EMPTY_BB. Return the decl of the resolver function. */
32070 static tree
32074 {
32079 /* IFUNC's have to be globally visible. So, if the default_decl is
32080 not, then the name of the IFUNC should be made unique. */
32084 /* Append the filename to the resolver function if the versions are
32085 not externally visible. This is because the resolver function has
32086 to be externally visible for the loader to find it. So, appending
32087 the filename will prevent conflicts with a resolver function from
32088 another module which is based on the same version name. */
32091 /* The resolver function should return a (void *). */
32102 /* IFUNC resolvers have to be externally visible. */
32106 /* Resolver is not external, body is generated. */
32116 {
32117 /* In this case, each translation unit with a call to this
32118 versioned function will put out a resolver. Ensure it
32119 is comdat to keep just one copy. */
32122 }
32123 /* Build result decl and add to function_decl. */
32139 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
32143 /* Create the alias for dispatch to resolver here. */
32144 /*cgraph_create_function_alias (dispatch_decl, decl);*/
32148 }
32150 /* Generate the dispatching code body to dispatch multi-versioned function
32151 DECL. The target hook is called to process the "target" attributes and
32152 provide the code to dispatch the right function at run-time. NODE points
32153 to the dispatcher decl whose body will be created. */
32155 static tree
32157 {
32158 tree resolver_decl;
32159 basic_block empty_bb;
32160 tree default_ver_decl;
32176 /* The first version in the chain corresponds to the default version. */
32179 /* node is going to be an alias, so remove the finalized bit. */
32193 {
32195 /* Check for virtual functions here again, as by this time it should
32196 have been determined if this function needs a vtable index or
32197 not. This happens for methods in derived classes that override
32198 virtual methods in base classes but are not explicitly marked as
32199 virtual. */
32204 }
32210 }
32211 /* This builds the processor_model struct type defined in
32212 libgcc/config/i386/cpuinfo.c */
32214 static tree
32216 {
32223 /* The first 3 fields are unsigned int. */
32225 {
32231 }
32233 /* The last field is an array of unsigned integers of size one. */
32244 }
32246 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
32248 static tree
32250 {
32251 tree new_decl;
32254 VAR_DECL,
32256 type);
32269 }
32271 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
32272 into an integer defined in libgcc/config/i386/cpuinfo.c */
32274 static tree
32276 {
32282 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
32283 enum processor_features
32284 {
32286 F_MMX,
32287 F_POPCNT,
32288 F_SSE,
32289 F_SSE2,
32290 F_SSE3,
32291 F_SSSE3,
32292 F_SSE4_1,
32293 F_SSE4_2,
32294 F_AVX,
32295 F_AVX2,
32296 F_SSE4_A,
32297 F_FMA4,
32298 F_XOP,
32299 F_FMA,
32300 F_MAX
32301 };
32303 /* These are the values for vendor types and cpu types and subtypes
32304 in cpuinfo.c. Cpu types and subtypes should be subtracted by
32305 the corresponding start value. */
32306 enum processor_model
32307 {
32309 M_AMD,
32310 M_CPU_TYPE_START,
32311 M_INTEL_BONNELL,
32312 M_INTEL_CORE2,
32313 M_INTEL_COREI7,
32314 M_AMDFAM10H,
32315 M_AMDFAM15H,
32316 M_INTEL_SILVERMONT,
32317 M_AMD_BTVER1,
32318 M_AMD_BTVER2,
32319 M_CPU_SUBTYPE_START,
32320 M_INTEL_COREI7_NEHALEM,
32321 M_INTEL_COREI7_WESTMERE,
32322 M_INTEL_COREI7_SANDYBRIDGE,
32323 M_AMDFAM10H_BARCELONA,
32324 M_AMDFAM10H_SHANGHAI,
32325 M_AMDFAM10H_ISTANBUL,
32326 M_AMDFAM15H_BDVER1,
32327 M_AMDFAM15H_BDVER2,
32328 M_AMDFAM15H_BDVER3,
32329 M_AMDFAM15H_BDVER4,
32330 M_INTEL_COREI7_IVYBRIDGE,
32331 M_INTEL_COREI7_HASWELL
32332 };
32334 static struct _arch_names_table
32335 {
32338 }
32340 {
32365 };
32367 static struct _isa_names_table
32368 {
32371 }
32373 {
32389 };
32403 {
32404 /* *args must be a expr that can contain other EXPRS leading to a
32405 STRING_CST. */
32407 {
32410 }
32412 }
32417 {
32418 tree ref;
32419 tree field;
32420 tree final;
32423 unsigned int NUM_ARCH_NAMES
32432 {
32436 }
32441 /* CPU types are stored in the next field. */
32444 {
32447 }
32449 /* CPU subtypes are stored in the next field. */
32451 {
32454 }
32456 /* Get the appropriate field in __cpu_model. */
32460 /* Check the value. */
32464 }
32466 {
32467 tree ref;
32468 tree array_elt;
32469 tree field;
32470 tree final;
32473 unsigned int NUM_ISA_NAMES
32482 {
32486 }
32489 /* Get the last field, which is __cpu_features. */
32493 /* Get the appropriate field: __cpu_model.__cpu_features */
32497 /* Access the 0th element of __cpu_features array. */
32502 /* Return __cpu_model.__cpu_features[0] & field_val */
32506 }
32508 }
32510 static tree
32513 {
32515 {
32520 {
32523 }
32524 }
32526 #ifdef SUBTARGET_FOLD_BUILTIN
32528 #endif
32531 }
32533 /* Make builtins to detect cpu type and features supported. NAME is
32534 the builtin name, CODE is the builtin code, and FTYPE is the function
32535 type of the builtin. */
32537 static void
32540 {
32541 tree decl;
32542 tree type;
32550 }
32552 /* Make builtins to get CPU type and features supported. The created
32553 builtins are :
32555 __builtin_cpu_init (), to detect cpu type and features,
32556 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
32557 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
32558 */
32560 static void
32562 {
32569 }
32571 /* Internal method for ix86_init_builtins. */
32573 static void
32575 {
32587 sysv_va_ref =
32590 fnvoid_va_end_ms =
32592 fnvoid_va_start_ms =
32594 fnvoid_va_end_sysv =
32596 fnvoid_va_start_sysv =
32598 NULL_TREE);
32599 fnvoid_va_copy_ms =
32601 NULL_TREE);
32602 fnvoid_va_copy_sysv =
32618 }
32620 static void
32622 {
32625 /* The __float80 type. */
32628 {
32629 /* The __float80 type. */
32634 }
32637 /* The __float128 type. */
32643 /* This macro is built by i386-builtin-types.awk. */
32644 DEFINE_BUILTIN_PRIMITIVE_TYPES;
32645 }
32647 static void
32649 {
32650 tree t;
32654 /* Builtins to get CPU type and features. */
32657 /* TFmode support builtins. */
32663 /* We will expand them to normal call if SSE isn't available since
32664 they are used by libgcc. */
32683 #ifdef SUBTARGET_INIT_BUILTINS
32684 SUBTARGET_INIT_BUILTINS;
32685 #endif
32686 }
32688 /* Return the ix86 builtin for CODE. */
32690 static tree
32692 {
32697 }
32699 /* Errors in the source file can cause expand_expr to return const0_rtx
32700 where we expect a vector. To avoid crashing, use one of the vector
32701 clear instructions. */
32702 static rtx
32704 {
32708 }
32710 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
32712 static rtx
32714 {
32715 rtx pat;
32735 {
32739 }
32753 }
32755 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
32757 static rtx
32761 {
32762 rtx pat;
32770 rtx op;
32777 {
32857 }
32867 {
32874 {
32876 {
32879 {
32897 xop_rotl:
32899 {
32902 gcc_checking_assert
32904 }
32905 else
32906 {
32907 gcc_checking_assert
32918 }
32922 }
32923 }
32924 }
32925 else
32926 {
32927 non_constant:
32931 /* If we aren't optimizing, only allow one memory operand to be
32932 generated. */
32934 num_memory++;
32942 }
32946 }
32949 {
32960 else
32961 {
32967 }
32980 }
32987 }
32989 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
32990 insns with vec_merge. */
32992 static rtx
32994 rtx target)
32995 {
32996 rtx pat;
33023 }
33025 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
33027 static rtx
33030 {
33031 rtx pat;
33036 rtx op2;
33047 /* Swap operands if we have a comparison that isn't available in
33048 hardware. */
33050 {
33055 }
33075 }
33077 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
33079 static rtx
33081 rtx target)
33082 {
33083 rtx pat;
33097 /* Swap operands if we have a comparison that isn't available in
33098 hardware. */
33100 {
33104 }
33125 const0_rtx)));
33128 }
33130 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
33132 static rtx
33134 rtx target)
33135 {
33136 rtx pat;
33161 }
33163 static rtx
33166 {
33167 rtx pat;
33172 rtx op2;
33199 }
33201 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
33203 static rtx
33205 rtx target)
33206 {
33207 rtx pat;
33240 const0_rtx)));
33243 }
33245 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
33247 static rtx
33250 {
33251 rtx pat;
33289 {
33292 }
33295 {
33304 }
33306 {
33315 }
33316 else
33317 {
33324 }
33332 {
33337 emit_insn
33341 FLAGS_REG),
33342 const0_rtx)));
33344 }
33345 else
33347 }
33350 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
33352 static rtx
33355 {
33356 rtx pat;
33384 {
33387 }
33390 {
33399 }
33401 {
33410 }
33411 else
33412 {
33419 }
33427 {
33432 emit_insn
33436 FLAGS_REG),
33437 const0_rtx)));
33439 }
33440 else
33442 }
33444 /* Subroutine of ix86_expand_builtin to take care of insns with
33445 variable number of operands. */
33447 static rtx
33450 {
33456 struct
33457 {
33458 rtx op;
33470 {
33918 }
33923 {
33926 }
33929 {
33936 }
33937 else
33938 {
33941 }
33944 {
33951 {
33952 /* SIMD shift insns take either an 8-bit immediate or
33953 register as count. But builtin functions take int as
33954 count. If count doesn't match, we put it in register. */
33956 {
33960 }
33961 }
33964 {
33967 {
34043 {
34047 {
34050 }
34056 }
34058 }
34059 }
34060 else
34061 {
34065 /* If we aren't optimizing, only allow one memory operand to
34066 be generated. */
34068 num_memory++;
34071 {
34074 }
34075 else
34076 {
34079 }
34080 }
34084 }
34087 {
34112 }
34119 }
34121 /* Transform pattern of following layout:
34122 (parallel [
34123 set (A B)
34124 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
34125 ])
34126 into:
34127 (set (A B))
34129 Or:
34130 (parallel [ A B
34131 ...
34132 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
34133 ...
34134 ])
34135 into:
34136 (parallel [ A B ... ]) */
34138 static rtx
34140 {
34147 {
34156 }
34157 else
34158 {
34164 {
34169 }
34171 /* No more than 1 occurence was removed. */
34175 }
34176 }
34178 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
34179 with rounding. */
34180 static rtx
34183 {
34200 /* See avxintrin.h for values. */
34202 {
34206 };
34208 {
34213 };
34216 {
34219 }
34221 {
34224 }
34227 {
34230 }
34253 ? CODE_FOR_sse_ucomi_round
34260 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
34262 {
34268 }
34269 else
34270 {
34273 }
34279 set_dst,
34280 const0_rtx)));
34283 }
34285 static rtx
34288 {
34289 rtx pat;
34291 struct
34292 {
34293 rtx op;
34303 {
34380 }
34390 {
34397 {
34399 {
34401 {
34417 }
34418 }
34419 }
34421 {
34423 {
34426 }
34428 /* If there is no rounding use normal version of the pattern. */
34431 }
34432 else
34433 {
34438 {
34441 }
34442 else
34443 {
34446 }
34447 }
34451 }
34454 {
34479 }
34489 }
34491 /* Subroutine of ix86_expand_builtin to take care of special insns
34492 with variable number of operands. */
34494 static rtx
34497 {
34498 tree arg;
34502 struct
34503 {
34504 rtx op;
34514 {
34553 {
34561 }
34580 /* Reserve memory operand for target. */
34583 {
34584 /* These builtins and instructions require the memory
34585 to be properly aligned. */
34604 }
34629 {
34630 /* These builtins and instructions require the memory
34631 to be properly aligned. */
34640 }
34641 /* FALLTHRU */
34659 /* Reserve memory operand for target. */
34672 {
34673 /* These builtins and instructions require the memory
34674 to be properly aligned. */
34683 }
34696 }
34701 {
34706 {
34709 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
34710 on it. Try to improve it using get_pointer_alignment,
34711 and if the special builtin is one that requires strict
34712 mode alignment, also from it's GET_MODE_ALIGNMENT.
34713 Failure to do so could lead to ix86_legitimate_combined_insn
34714 rejecting all changes to such insns. */
34720 }
34721 else
34724 }
34725 else
34726 {
34733 }
34736 {
34745 {
34747 {
34753 else
34756 }
34757 }
34758 else
34759 {
34761 {
34762 /* This must be the memory operand. */
34765 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
34766 on it. Try to improve it using get_pointer_alignment,
34767 and if the special builtin is one that requires strict
34768 mode alignment, also from it's GET_MODE_ALIGNMENT.
34769 Failure to do so could lead to ix86_legitimate_combined_insn
34770 rejecting all changes to such insns. */
34776 }
34777 else
34778 {
34779 /* This must be register. */
34785 else
34786 {
34789 }
34790 }
34791 }
34795 }
34798 {
34813 }
34819 }
34821 /* Return the integer constant in ARG. Constrain it to be in the range
34822 of the subparts of VEC_TYPE; issue an error if not. */
34824 static int
34826 {
34831 {
34834 }
34837 }
34839 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34840 ix86_expand_vector_init. We DO have language-level syntax for this, in
34841 the form of (type){ init-list }. Except that since we can't place emms
34842 instructions from inside the compiler, we can't allow the use of MMX
34843 registers unless the user explicitly asks for it. So we do *not* define
34844 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
34845 we have builtins invoked by mmintrin.h that gives us license to emit
34846 these sorts of instructions. */
34848 static rtx
34850 {
34860 {
34863 }
34870 }
34872 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34873 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
34874 had a language-level syntax for referencing vector elements. */
34876 static rtx
34878 {
34882 rtx op0;
34902 }
34904 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34905 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
34906 a language-level syntax for referencing vector elements. */
34908 static rtx
34910 {
34934 /* OP0 is the source of these builtin functions and shouldn't be
34935 modified. Create a copy, use it and return it as target. */
34941 }
34943 /* Expand an expression EXP that calls a built-in function,
34944 with result going to TARGET if that's convenient
34945 (and in mode MODE if that's convenient).
34946 SUBTARGET may be used as the target for computing one of EXP's operands.
34947 IGNORE is nonzero if the value is to be ignored. */
34949 static rtx
34952 {
34962 /* For CPU builtins that can be folded, fold first and expand the fold. */
34964 {
34966 {
34967 /* Make it call __cpu_indicator_init in libgcc. */
34973 }
34976 {
34981 }
34982 }
34984 /* Determine whether the builtin function is available under the current ISA.
34985 Originally the builtin was not created if it wasn't applicable to the
34986 current ISA based on the command line switches. With function specific
34987 options, we need to check in the context of the function making the call
34988 whether it is supported. */
34991 {
34997 else
34998 {
35002 }
35004 }
35007 {
35011 ? CODE_FOR_mmx_maskmovq
35013 /* Note the arg order is different from the operand order. */
35114 {
35115 REAL_VALUE_TYPE inf;
35116 rtx tmp;
35128 }
35138 {
35144 insn = (TARGET_64BIT
35148 }
35150 {
35151 insn = (TARGET_64BIT
35155 }
35156 else
35157 {
35160 insn = (TARGET_64BIT
35168 {
35171 }
35173 }
35176 {
35177 /* mode is VOIDmode if __builtin_rd* has been called
35178 without lhs. */
35182 }
35185 {
35190 }
35204 {
35229 }
35235 {
35238 }
35258 {
35261 }
35267 {
35271 {
35292 }
35297 }
35298 else
35299 {
35301 {
35313 }
35315 }
35345 ? CODE_FOR_tbm_bextri_si
35348 {
35351 }
35352 else
35353 {
35362 }
35378 rdrand_step:
35385 {
35388 }
35394 /* Emit SImode conditional move. */
35396 {
35399 }
35402 else
35409 const0_rtx);
35428 rdseed_step:
35435 {
35438 }
35444 const0_rtx);
35462 addcarryx:
35470 /* Generate CF from input operand. */
35475 /* Gen ADCX instruction to compute X+Y+CF. */
35490 /* Store the result. */
35493 {
35496 }
35499 /* Return current CF value. */
35541 kortest:
35555 /* Emit kortest. */
35557 /* And use setcc to return result from flags. */
35708 gather_gen:
35709 rtx half;
35722 /* Note the arg order is different from the operand order. */
35733 else
35737 {
35759 else
35766 {
35771 }
35778 else
35785 {
35790 }
35794 }
35796 /* Force memory operand only with base register here. But we
35797 don't want to do it on memory operand for other builtin
35798 functions. */
35808 {
35811 }
35812 else
35813 {
35816 }
35818 {
35821 }
35823 /* Optimize. If mask is known to have all high bits set,
35824 replace op0 with pc_rtx to signal that the instruction
35825 overwrites the whole destination and doesn't use its
35826 previous contents. */
35828 {
35830 {
35833 }
35835 {
35838 {
35842 negative++;
35845 negative++;
35846 }
35849 }
35852 {
35853 /* Recognize also when mask is like:
35854 __v2df src = _mm_setzero_pd ();
35855 __v2df mask = _mm_cmpeq_pd (src, src);
35856 or
35857 __v8sf src = _mm256_setzero_ps ();
35858 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
35859 as that is a cheaper way to load all ones into
35860 a register than having to load a constant from
35861 memory. */
35864 {
35869 {
35876 /* FALLTHRU */
35886 }
35887 }
35888 }
35889 }
35897 {
35921 }
35924 scatter_gen:
35940 /* Force memory operand only with base register here. But we
35941 don't want to do it on memory operand for other builtin
35942 functions. */
35949 {
35952 }
35953 else
35954 {
35957 }
35966 {
35969 }
35978 vec_prefetch_gen:
35996 {
35999 }
36001 {
36004 }
36009 /* Force memory operand only with base register here. But we
36010 don't want to do it on memory operand for other builtin
36011 functions. */
36018 {
36021 }
36024 {
36027 }
36043 {
36046 }
36052 }
36065 {
36069 /* Emit a normal call if SSE isn't available. */
36073 }
36102 }
36104 /* This returns the target-specific builtin with code CODE if
36105 current_function_decl has visibility on this builtin, which is checked
36106 using isa flags. Returns NULL_TREE otherwise. */
36109 {
36113 /* Determine the isa flags of current_function_decl. */
36125 else
36127 }
36129 /* Returns a function decl for a vectorized version of the builtin function
36130 with builtin function code FN and the result vector type TYPE, or NULL_TREE
36131 if it is not available. */
36133 static tree
36135 tree type_in)
36136 {
36152 {
36155 {
36162 }
36167 {
36170 }
36175 {
36182 }
36188 /* The round insn does not trap on denormals. */
36193 {
36200 }
36206 /* The round insn does not trap on denormals. */
36211 {
36216 }
36222 /* The round insn does not trap on denormals. */
36227 {
36234 }
36240 /* The round insn does not trap on denormals. */
36245 {
36250 }
36257 {
36262 }
36269 {
36274 }
36280 /* The round insn does not trap on denormals. */
36285 {
36292 }
36298 /* The round insn does not trap on denormals. */
36303 {
36308 }
36313 {
36320 }
36325 {
36332 }
36336 /* The round insn does not trap on denormals. */
36341 {
36346 }
36350 /* The round insn does not trap on denormals. */
36355 {
36360 }
36364 /* The round insn does not trap on denormals. */
36369 {
36374 }
36378 /* The round insn does not trap on denormals. */
36383 {
36388 }
36392 /* The round insn does not trap on denormals. */
36397 {
36402 }
36406 /* The round insn does not trap on denormals. */
36411 {
36416 }
36420 /* The round insn does not trap on denormals. */
36425 {
36430 }
36434 /* The round insn does not trap on denormals. */
36439 {
36444 }
36448 /* The round insn does not trap on denormals. */
36453 {
36458 }
36462 /* The round insn does not trap on denormals. */
36467 {
36472 }
36477 {
36482 }
36487 {
36492 }
36497 }
36499 /* Dispatch to a handler for a vectorization library. */
36502 type_in);
36505 }
36507 /* Handler for an SVML-style interface to
36508 a library with vectorized intrinsics. */
36510 static tree
36512 {
36520 /* The SVML is suitable for unsafe math only. */
36533 {
36580 }
36589 {
36592 }
36593 else
36596 /* Convert to uppercase. */
36601 args;
36603 arity++;
36607 else
36610 /* Build a function declaration for the vectorized function. */
36619 }
36621 /* Handler for an ACML-style interface to
36622 a library with vectorized intrinsics. */
36624 static tree
36626 {
36634 /* The ACML is 64bits only and suitable for unsafe math only as
36635 it does not correctly support parts of IEEE with the required
36636 precision such as denormals. */
36650 {
36680 }
36687 args;
36689 arity++;
36693 else
36696 /* Build a function declaration for the vectorized function. */
36705 }
36707 /* Returns a decl of a function that implements gather load with
36708 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
36709 Return NULL_TREE if it is not available. */
36711 static tree
36714 {
36730 /* v*gather* insn sign extends index to pointer mode. */
36742 {
36770 else
36776 else
36782 else
36788 else
36793 }
36796 }
36798 /* Returns a code for a target-specific builtin that implements
36799 reciprocal of the function, or NULL_TREE if not available. */
36801 static tree
36804 {
36811 /* Machine dependent builtins. */
36813 {
36814 /* Vectorized version of sqrt to rsqrt conversion. */
36823 }
36824 else
36825 /* Normal builtins. */
36827 {
36828 /* Sqrt to rsqrt conversion. */
36834 }
36835 }
36836 \f
36837 /* Helper for avx_vpermilps256_operand et al. This is also used by
36838 the expansion functions to turn the parallel back into a mask.
36839 The return value is 0 for no match and the imm8+1 for a match. */
36841 int
36843 {
36851 /* Validate that all of the elements are constants, and not totally
36852 out of range. Copy the data into an integral array to make the
36853 subsequent checks easier. */
36855 {
36865 }
36868 {
36870 /* In the 512-bit DFmode case, we can only move elements within
36871 a 128-bit lane. First fill the second part of the mask,
36872 then fallthru. */
36874 {
36878 }
36880 {
36884 }
36885 /* FALLTHRU */
36888 /* In the 256-bit DFmode case, we can only move elements within
36889 a 128-bit lane. */
36891 {
36895 }
36897 {
36901 }
36905 /* In 512 bit SFmode case, permutation in the upper 256 bits
36906 must mirror the permutation in the lower 256-bits. */
36910 /* FALLTHRU */
36913 /* In 256 bit SFmode case, we have full freedom of
36914 movement within the low 128-bit lane, but the high 128-bit
36915 lane must mirror the exact same pattern. */
36920 /* FALLTHRU */
36924 /* In the 128-bit case, we've full freedom in the placement of
36925 the elements from the source operand. */
36932 }
36934 /* Make sure success has a non-zero value by adding one. */
36936 }
36938 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
36939 the expansion functions to turn the parallel back into a mask.
36940 The return value is 0 for no match and the imm8+1 for a match. */
36942 int
36944 {
36952 /* Validate that all of the elements are constants, and not totally
36953 out of range. Copy the data into an integral array to make the
36954 subsequent checks easier. */
36956 {
36966 }
36968 /* Validate that the halves of the permute are halves. */
36976 /* Reconstruct the mask. */
36978 {
36984 }
36986 /* Make sure success has a non-zero value by adding one. */
36988 }
36989 \f
36990 /* Store OPERAND to the memory after reload is completed. This means
36991 that we can't easily use assign_stack_local. */
36992 rtx
36994 {
36995 rtx result;
36999 {
37002 stack_pointer_rtx,
37005 }
37007 {
37009 {
37013 /* FALLTHRU */
37019 stack_pointer_rtx)),
37020 operand));
37024 }
37026 }
37027 else
37028 {
37030 {
37032 {
37039 stack_pointer_rtx)),
37045 stack_pointer_rtx)),
37047 }
37050 /* Store HImodes as SImodes. */
37052 /* FALLTHRU */
37058 stack_pointer_rtx)),
37059 operand));
37063 }
37065 }
37067 }
37069 /* Free operand from the memory. */
37070 void
37072 {
37074 {
37079 else
37081 /* Use LEA to deallocate stack space. In peephole2 it will be converted
37082 to pop or add instruction if registers are available. */
37086 }
37087 }
37089 /* Return a register priority for hard reg REGNO. */
37090 static int
37092 {
37093 /* ebp and r13 as the base always wants a displacement, r12 as the
37094 base always wants an index. So discourage their usage in an
37095 address. */
37100 /* New x86-64 int registers result in bigger code size. Discourage
37101 them. */
37104 /* New x86-64 SSE registers result in bigger code size. Discourage
37105 them. */
37108 /* Usage of AX register results in smaller code. Prefer it. */
37112 }
37114 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
37116 Put float CONST_DOUBLE in the constant pool instead of fp regs.
37117 QImode must go into class Q_REGS.
37118 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
37119 movdf to do mem-to-mem moves through integer regs. */
37121 static reg_class_t
37123 {
37126 /* We're only allowed to return a subclass of CLASS. Many of the
37127 following checks fail for NO_REGS, so eliminate that early. */
37131 /* All classes can load zeros. */
37135 /* Force constants into memory if we are loading a (nonzero) constant into
37136 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
37137 instructions to load from a constant. */
37144 /* Prefer SSE regs only, if we can use them for math. */
37148 /* Floating-point constants need more complex checks. */
37150 {
37151 /* General regs can load everything. */
37155 /* Floats can load 0 and 1 plus some others. Note that we eliminated
37156 zero above. We only want to wind up preferring 80387 registers if
37157 we plan on doing computation with them. */
37160 {
37161 /* Limit class to non-sse. */
37170 }
37173 }
37175 /* Generally when we see PLUS here, it's the function invariant
37176 (plus soft-fp const_int). Which can only be computed into general
37177 regs. */
37181 /* QImode constants are easy to load, but non-constant QImode data
37182 must go into Q_REGS. */
37184 {
37190 }
37193 }
37195 /* Discourage putting floating-point values in SSE registers unless
37196 SSE math is being used, and likewise for the 387 registers. */
37197 static reg_class_t
37199 {
37202 /* Restrict the output reload class to the register bank that we are doing
37203 math on. If we would like not to return a subset of CLASS, reject this
37204 alternative: if reload cannot do this, it will still use its choice. */
37210 {
37215 else
37217 }
37220 }
37222 static reg_class_t
37225 {
37226 /* Double-word spills from general registers to non-offsettable memory
37227 references (zero-extended addresses) require special handling. */
37233 {
37235 ? CODE_FOR_reload_noff_load
37237 /* Add the cost of moving address to a temporary. */
37241 }
37243 /* QImode spills from non-QI registers require
37244 intermediate register on 32bit targets. */
37250 {
37255 else
37261 /* Return Q_REGS if the operand is in memory. */
37264 }
37266 /* This condition handles corner case where an expression involving
37267 pointers gets vectorized. We're trying to use the address of a
37268 stack slot as a vector initializer.
37270 (set (reg:V2DI 74 [ vect_cst_.2 ])
37271 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
37273 Eventually frame gets turned into sp+offset like this:
37275 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37276 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
37277 (const_int 392 [0x188]))))
37279 That later gets turned into:
37281 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37282 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
37283 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
37285 We'll have the following reload recorded:
37287 Reload 0: reload_in (DI) =
37288 (plus:DI (reg/f:DI 7 sp)
37289 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
37290 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37291 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
37292 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
37293 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37294 reload_reg_rtx: (reg:V2DI 22 xmm1)
37296 Which isn't going to work since SSE instructions can't handle scalar
37297 additions. Returning GENERAL_REGS forces the addition into integer
37298 register and reload can handle subsequent reloads without problems. */
37306 }
37308 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
37310 static bool
37312 {
37314 {
37329 }
37332 }
37334 /* If we are copying between general and FP registers, we need a memory
37335 location. The same is true for SSE and MMX registers.
37337 To optimize register_move_cost performance, allow inline variant.
37339 The macro can't work reliably when one of the CLASSES is class containing
37340 registers from multiple units (SSE, MMX, integer). We avoid this by never
37341 combining those units in single alternative in the machine description.
37342 Ensure that this constraint holds to avoid unexpected surprises.
37344 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
37345 enforce these sanity checks. */
37350 {
37359 {
37362 }
37367 /* ??? This is a lie. We do have moves between mmx/general, and for
37368 mmx/sse2. But by saying we need secondary memory we discourage the
37369 register allocator from using the mmx registers unless needed. */
37374 {
37375 /* SSE1 doesn't have any direct moves from other classes. */
37379 /* If the target says that inter-unit moves are more expensive
37380 than moving through memory, then don't generate them. */
37385 /* Between SSE and general, we have moves no larger than word size. */
37388 }
37391 }
37393 bool
37396 {
37398 }
37400 /* Implement the TARGET_CLASS_MAX_NREGS hook.
37402 On the 80386, this is the size of MODE in words,
37403 except in the FP regs, where a single reg is always enough. */
37405 static unsigned char
37407 {
37409 {
37414 else
37416 }
37417 else
37418 {
37421 else
37423 }
37424 }
37426 /* Return true if the registers in CLASS cannot represent the change from
37427 modes FROM to TO. */
37429 bool
37432 {
37436 /* x87 registers can't do subreg at all, as all values are reformatted
37437 to extended precision. */
37442 {
37443 /* Vector registers do not support QI or HImode loads. If we don't
37444 disallow a change to these modes, reload will assume it's ok to
37445 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
37446 the vec_dupv4hi pattern. */
37450 /* Vector registers do not support subreg with nonzero offsets, which
37451 are otherwise valid for integer registers. Since we can't see
37452 whether we have a nonzero offset from here, prohibit all
37453 nonparadoxical subregs changing size. */
37456 }
37459 }
37461 /* Return the cost of moving data of mode M between a
37462 register and memory. A value of 2 is the default; this cost is
37463 relative to those in `REGISTER_MOVE_COST'.
37465 This function is used extensively by register_move_cost that is used to
37466 build tables at startup. Make it inline in this case.
37467 When IN is 2, return maximum of in and out move cost.
37469 If moving between registers and memory is more expensive than
37470 between two registers, you should define this macro to express the
37471 relative cost.
37473 Model also increased moving costs of QImode registers in non
37474 Q_REGS classes.
37475 */
37479 {
37482 {
37485 {
37497 }
37501 }
37503 {
37506 {
37518 }
37522 }
37524 {
37527 {
37536 }
37540 }
37542 {
37545 {
37551 else
37556 }
37557 else
37558 {
37563 else
37565 }
37572 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
37579 else
37583 }
37584 }
37586 static int
37589 {
37591 }
37594 /* Return the cost of moving data from a register in class CLASS1 to
37595 one in class CLASS2.
37597 It is not required that the cost always equal 2 when FROM is the same as TO;
37598 on some machines it is expensive to move between registers if they are not
37599 general registers. */
37601 static int
37603 reg_class_t class2_i)
37604 {
37608 /* In case we require secondary memory, compute cost of the store followed
37609 by load. In order to avoid bad register allocation choices, we need
37610 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
37613 {
37619 /* In case of copying from general_purpose_register we may emit multiple
37620 stores followed by single load causing memory size mismatch stall.
37621 Count this as arbitrarily high cost of 20. */
37626 /* In the case of FP/MMX moves, the registers actually overlap, and we
37627 have to switch modes in order to treat them differently. */
37633 }
37635 /* Moves between SSE/MMX and integer unit are expensive. */
37639 /* ??? By keeping returned value relatively high, we limit the number
37640 of moves between integer and MMX/SSE registers for all targets.
37641 Additionally, high value prevents problem with x86_modes_tieable_p(),
37642 where integer modes in MMX/SSE registers are not tieable
37643 because of missing QImode and HImode moves to, from or between
37644 MMX/SSE registers. */
37654 }
37656 /* Return TRUE if hard register REGNO can hold a value of machine-mode
37657 MODE. */
37659 bool
37661 {
37662 /* Flags and only flags can only hold CCmode values. */
37674 {
37675 /* We implement the move patterns for all vector modes into and
37676 out of SSE registers, even when no operation instructions
37677 are available. */
37679 /* For AVX-512 we allow, regardless of regno:
37680 - XI mode
37681 - any of 512-bit wide vector mode
37682 - any scalar mode. */
37689 /* xmm16-xmm31 are only available for AVX-512. */
37693 /* OImode and AVX modes are available only when AVX is enabled. */
37700 }
37702 {
37703 /* We implement the move patterns for 3DNOW modes even in MMX mode,
37704 so if the register is available at all, then we can move data of
37705 the given mode into or out of it. */
37708 }
37711 {
37712 /* Take care for QImode values - they can be in non-QI regs,
37713 but then they do cause partial register stalls. */
37718 /* LRA checks if the hard register is OK for the given mode.
37719 QImode values can live in non-QI regs, so we allow all
37720 registers here. */
37724 }
37725 /* We handle both integer and floats in the general purpose registers. */
37732 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
37733 on to use that value in smaller contexts, this can easily force a
37734 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
37735 supporting DImode, allow it. */
37740 }
37742 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
37743 tieable integer mode. */
37745 static bool
37747 {
37749 {
37762 }
37763 }
37765 /* Return true if MODE1 is accessible in a register that can hold MODE2
37766 without copying. That is, all register classes that can hold MODE2
37767 can also hold MODE1. */
37769 bool
37771 {
37779 /* MODE2 being XFmode implies fp stack or general regs, which means we
37780 can tie any smaller floating point modes to it. Note that we do not
37781 tie this with TFmode. */
37785 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
37786 that we can tie it with SFmode. */
37790 /* If MODE2 is only appropriate for an SSE register, then tie with
37791 any other mode acceptable to SSE registers. */
37801 /* If MODE2 is appropriate for an MMX register, then tie
37802 with any other mode acceptable to MMX registers. */
37809 }
37811 /* Return the cost of moving between two registers of mode MODE. */
37813 static int
37815 {
37819 {
37851 }
37853 /* Return the cost of moving between two registers of mode MODE,
37854 assuming that the move will be in pieces of at most UNITS bytes. */
37856 }
37858 /* Compute a (partial) cost for rtx X. Return true if the complete
37859 cost has been computed, and false if subexpressions should be
37860 scanned. In either case, *TOTAL contains the cost result. */
37862 static bool
37865 {
37866 rtx mask;
37873 {
37877 {
37880 }
37892 && (!TARGET_64BIT
37897 else
37903 {
37906 }
37908 {
37918 }
37920 {
37923 {
37932 }
37933 }
37934 /* Fall back to (MEM (SYMBOL_REF)), since that's where
37935 it'll probably end up. Add a penalty for size. */
37942 /* The zero extensions is often completely free on x86_64, so make
37943 it as cheap as possible. */
37949 else
37961 {
37964 {
37967 }
37970 {
37973 }
37974 }
37975 /* FALLTHRU */
37982 {
37983 /* ??? Should be SSE vector operation cost. */
37984 /* At least for published AMD latencies, this really is the same
37985 as the latency for a simple fpu operation like fabs. */
37986 /* V*QImode is emulated with 1-11 insns. */
37988 {
37991 {
37992 /* For XOP we use vpshab, which requires a broadcast of the
37993 value to the variable shift insn. For constants this
37994 means a V16Q const in mem; even when we can perform the
37995 shift with one insn set the cost to prefer paddb. */
37997 {
38002 }
38004 }
38008 }
38009 else
38011 }
38013 {
38015 {
38018 else
38020 }
38021 else
38022 {
38025 else
38027 }
38028 }
38029 else
38030 {
38035 {
38036 /* Return the cost after shift-and truncation. */
38039 }
38040 else
38042 }
38046 {
38047 rtx sub;
38052 /* ??? SSE scalar/vector cost should be used here. */
38053 /* ??? Bald assumption that fma has the same cost as fmul. */
38057 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
38068 }
38072 {
38073 /* ??? SSE scalar cost should be used here. */
38076 }
38078 {
38081 }
38083 {
38084 /* ??? SSE vector cost should be used here. */
38087 }
38089 {
38090 /* V*QImode is emulated with 7-13 insns. */
38092 {
38099 }
38100 /* V*DImode is emulated with 5-8 insns. */
38102 {
38105 else
38107 }
38108 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
38109 insns, including two PMULUDQ. */
38112 else
38115 }
38116 else
38117 {
38122 {
38125 nbits++;
38126 }
38127 else
38128 /* This is arbitrary. */
38131 /* Compute costs correctly for widening multiplication. */
38135 {
38142 {
38146 else
38148 }
38152 }
38160 }
38167 /* ??? SSE cost should be used here. */
38172 /* ??? SSE vector cost should be used here. */
38174 else
38181 {
38186 {
38189 {
38197 }
38198 }
38201 {
38204 {
38210 }
38211 }
38213 {
38221 }
38222 }
38223 /* FALLTHRU */
38227 {
38228 /* ??? SSE cost should be used here. */
38231 }
38233 {
38236 }
38238 {
38239 /* ??? SSE vector cost should be used here. */
38242 }
38243 /* FALLTHRU */
38250 {
38257 }
38258 /* FALLTHRU */
38262 {
38263 /* ??? SSE cost should be used here. */
38266 }
38268 {
38271 }
38273 {
38274 /* ??? SSE vector cost should be used here. */
38277 }
38278 /* FALLTHRU */
38282 {
38283 /* ??? Should be SSE vector operation cost. */
38284 /* At least for published AMD latencies, this really is the same
38285 as the latency for a simple fpu operation like fabs. */
38287 }
38290 else
38299 {
38300 /* This kind of construct is implemented using test[bwl].
38301 Treat it as if we had an AND. */
38306 }
38316 /* ??? SSE cost should be used here. */
38321 /* ??? SSE vector cost should be used here. */
38327 /* ??? SSE cost should be used here. */
38332 /* ??? SSE vector cost should be used here. */
38344 /* ??? Assume all of these vector manipulation patterns are
38345 recognizable. In which case they all pretty much have the
38346 same cost. */
38351 /* This is masked instruction, assume the same cost,
38352 as nonmasked variant. */
38355 else
38361 }
38362 }
38364 #if TARGET_MACHO
38368 /* Given a symbol name and its associated stub, write out the
38369 definition of the stub. */
38371 void
38373 {
38378 /* For 64-bit we shouldn't get here. */
38381 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
38398 else
38405 {
38407 }
38409 {
38410 /* PIC stub. */
38411 /* 25-byte PIC stub using "CALL get_pc_thunk". */
38417 }
38418 else
38421 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
38422 it needs no stub-binding-helper. */
38429 {
38432 }
38433 else
38438 /* N.B. Keep the correspondence of these
38439 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
38440 old-pic/new-pic/non-pic stubs; altering this will break
38441 compatibility with existing dylibs. */
38443 {
38444 /* 25-byte PIC stub using "CALL get_pc_thunk". */
38446 }
38447 else
38448 /* 16-byte -mdynamic-no-pic stub. */
38454 }
38457 /* Order the registers for register allocator. */
38459 void
38461 {
38465 /* First allocate the local general purpose registers. */
38470 /* Global general purpose registers. */
38475 /* x87 registers come first in case we are doing FP math
38476 using them. */
38481 /* SSE registers. */
38487 /* Extended REX SSE registers. */
38491 /* Mask register. */
38495 /* x87 registers. */
38503 /* Initialize the rest of array as we do not allocate some registers
38504 at all. */
38507 }
38509 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
38510 in struct attribute_spec handler. */
38511 static tree
38513 tree args,
38516 {
38521 {
38523 name);
38526 }
38528 {
38530 name);
38533 }
38535 {
38536 tree cst;
38540 {
38543 name);
38545 }
38548 {
38551 name);
38553 }
38556 }
38559 }
38561 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
38562 struct attribute_spec.handler. */
38563 static tree
38565 tree args ATTRIBUTE_UNUSED,
38567 {
38572 {
38574 name);
38577 }
38579 /* Can combine regparm with all attributes but fastcall. */
38581 {
38583 {
38585 }
38588 }
38590 {
38592 {
38594 }
38597 }
38600 }
38602 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
38603 struct attribute_spec.handler. */
38604 static tree
38606 tree args ATTRIBUTE_UNUSED,
38608 {
38611 {
38614 }
38615 else
38619 {
38621 name);
38623 }
38629 {
38631 name);
38633 }
38636 }
38638 static tree
38640 tree args ATTRIBUTE_UNUSED,
38642 {
38644 {
38646 name);
38648 }
38650 }
38652 static bool
38654 {
38658 }
38660 /* Returns an expression indicating where the this parameter is
38661 located on entry to the FUNCTION. */
38663 static rtx
38665 {
38671 {
38676 else
38679 }
38684 {
38691 {
38696 }
38697 else
38698 {
38701 {
38707 }
38708 }
38710 }
38714 }
38716 /* Determine whether x86_output_mi_thunk can succeed. */
38718 static bool
38720 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
38722 {
38723 /* 64-bit can handle anything. */
38727 /* For 32-bit, everything's fine if we have one free register. */
38731 /* Need a free register for vcall_offset. */
38735 /* Need a free register for GOT references. */
38739 /* Otherwise ok. */
38741 }
38743 /* Output the assembler code for a thunk function. THUNK_DECL is the
38744 declaration for the thunk function itself, FUNCTION is the decl for
38745 the target function. DELTA is an immediate constant offset to be
38746 added to THIS. If VCALL_OFFSET is nonzero, the word at
38747 *(*this + vcall_offset) should be added to THIS. */
38749 static void
38753 {
38760 else
38761 {
38767 else
38769 }
38773 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
38774 pull it in now and let DELTA benefit. */
38778 {
38779 /* Put the this parameter into %eax. */
38782 }
38783 else
38786 /* Adjust the this parameter by a fixed constant. */
38788 {
38793 {
38795 {
38799 }
38800 }
38803 }
38805 /* Adjust the this parameter by a value stored in the vtable. */
38807 {
38817 /* Adjust the this parameter. */
38821 {
38825 }
38832 vcall_mem));
38833 else
38835 }
38837 /* If necessary, drop THIS back to its stack slot. */
38843 {
38846 ;
38847 else
38848 {
38852 }
38853 }
38854 else
38855 {
38857 ;
38858 #if TARGET_MACHO
38860 {
38863 }
38865 else
38866 {
38873 }
38874 }
38876 /* Our sibling call patterns do not allow memories, because we have no
38877 predicate that can distinguish between frame and non-frame memory.
38878 For our purposes here, we can get away with (ab)using a jump pattern,
38879 because we're going to do no optimization. */
38882 else
38883 {
38889 {
38895 }
38901 }
38904 /* Emit just enough of rest_of_compilation to get the insns emitted.
38905 Note that use_thunk calls assemble_start_function et al. */
38911 }
38913 static void
38915 {
38919 #if TARGET_MACHO
38921 #endif
38928 }
38930 int
38932 {
38944 }
38946 /* Output assembler code to FILE to increment profiler label # LABELNO
38947 for profiling a function entry. */
38948 void
38950 {
38955 {
38956 #ifndef NO_PROFILE_COUNTERS
38958 #endif
38962 else
38964 }
38966 {
38967 #ifndef NO_PROFILE_COUNTERS
38970 #endif
38972 }
38973 else
38974 {
38975 #ifndef NO_PROFILE_COUNTERS
38978 #endif
38980 }
38981 }
38983 /* We don't have exact information about the insn sizes, but we may assume
38984 quite safely that we are informed about all 1 byte insns and memory
38985 address sizes. This is enough to eliminate unnecessary padding in
38986 99% of cases. */
38988 static int
38990 {
38996 /* Discard alignments we've emit and jump instructions. */
39001 /* Important case - calls are always 5 bytes.
39002 It is common to have many calls in the row. */
39011 /* For normal instructions we rely on get_attr_length being exact,
39012 with a few exceptions. */
39014 {
39018 {
39028 /* Otherwise trust get_attr_length. */
39030 }
39035 }
39038 else
39040 }
39042 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
39044 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
39045 window. */
39047 static void
39049 {
39054 /* Look for all minimal intervals of instructions containing 4 jumps.
39055 The intervals are bounded by START and INSN. NBYTES is the total
39056 size of instructions in the interval including INSN and not including
39057 START. When the NBYTES is smaller than 16 bytes, it is possible
39058 that the end of START and INSN ends up in the same 16byte page.
39060 The smallest offset in the page INSN can start is the case where START
39061 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
39062 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
39064 Don't consider asm goto as jump, while it can contain a jump, it doesn't
39065 have to, control transfer to label(s) can be performed through other
39066 means, and also we estimate minimum length of all asm stmts as 0. */
39068 {
39072 {
39078 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
39079 already in the current 16 byte page, because otherwise
39080 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
39081 bytes to reach 16 byte boundary. */
39089 {
39091 {
39096 else
39099 }
39100 }
39102 }
39111 njumps++;
39112 else
39116 {
39121 else
39124 }
39131 {
39138 }
39139 }
39140 }
39141 #endif
39143 /* AMD Athlon works faster
39144 when RET is not destination of conditional jump or directly preceded
39145 by other jump instruction. We avoid the penalty by inserting NOP just
39146 before the RET instructions in such cases. */
39147 static void
39149 {
39150 edge e;
39151 edge_iterator ei;
39154 {
39157 rtx prev;
39167 {
39168 edge e;
39169 edge_iterator ei;
39174 {
39177 }
39178 }
39180 {
39186 /* Empty functions get branch mispredict even when
39187 the jump destination is not visible to us. */
39190 }
39192 {
39195 }
39196 }
39197 }
39199 /* Count the minimum number of instructions in BB. Return 4 if the
39200 number of instructions >= 4. */
39202 static int
39204 {
39205 rtx insn;
39208 /* Count number of instructions in this block. Return 4 if the number
39209 of instructions >= 4. */
39211 {
39212 /* Only happen in exit blocks. */
39220 {
39221 insn_count++;
39224 }
39225 }
39228 }
39231 /* Count the minimum number of instructions in code path in BB.
39232 Return 4 if the number of instructions >= 4. */
39234 static int
39236 {
39237 edge e;
39238 edge_iterator ei;
39241 /* Only bother counting instructions along paths with no
39242 more than 2 basic blocks between entry and exit. Given
39243 that BB has an edge to exit, determine if a predecessor
39244 of BB has an edge from entry. If so, compute the number
39245 of instructions in the predecessor block. If there
39246 happen to be multiple such blocks, compute the minimum. */
39249 {
39250 edge prev_e;
39251 edge_iterator prev_ei;
39254 {
39257 }
39259 {
39261 {
39266 }
39267 }
39268 }
39274 }
39276 /* Pad short function to 4 instructions. */
39278 static void
39280 {
39281 edge e;
39282 edge_iterator ei;
39285 {
39288 {
39291 /* Pad short function. */
39293 {
39296 /* Find epilogue. */
39305 /* Two NOPs count as one instruction. */
39308 }
39309 }
39310 }
39311 }
39313 /* Fix up a Windows system unwinder issue. If an EH region falls through into
39314 the epilogue, the Windows system unwinder will apply epilogue logic and
39315 produce incorrect offsets. This can be avoided by adding a nop between
39316 the last insn that can throw and the first insn of the epilogue. */
39318 static void
39320 {
39321 edge e;
39322 edge_iterator ei;
39325 {
39328 /* Find the beginning of the epilogue. */
39335 /* We only care about preceding insns that can throw. */
39340 /* Do not separate calls from their debug information. */
39346 else
39350 }
39351 }
39353 /* Implement machine specific optimizations. We implement padding of returns
39354 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
39355 static void
39357 {
39358 /* We are freeing block_for_insn in the toplev to keep compatibility
39359 with old MDEP_REORGS that are not CFG based. Recompute it now. */
39366 {
39371 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
39374 #endif
39375 }
39376 }
39378 /* Return nonzero when QImode register that must be represented via REX prefix
39379 is used. */
39380 bool
39382 {
39390 }
39392 /* Return nonzero when P points to register encoded via REX prefix.
39393 Called via for_each_rtx. */
39394 static int
39396 {
39402 }
39404 /* Return true when INSN mentions register that must be encoded using REX
39405 prefix. */
39406 bool
39408 {
39411 }
39413 /* If profitable, negate (without causing overflow) integer constant
39414 of mode MODE at location LOC. Return true in this case. */
39415 bool
39417 {
39418 HOST_WIDE_INT val;
39424 {
39426 /* DImode x86_64 constants must fit in 32 bits. */
39439 }
39441 /* Avoid overflows. */
39447 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
39448 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
39451 {
39454 }
39457 }
39459 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
39460 optabs would emit if we didn't have TFmode patterns. */
39462 void
39464 {
39498 }
39499 \f
39500 /* AVX512F does support 64-byte integer vector operations,
39501 thus the longest vector we are faced with is V64QImode. */
39502 #define MAX_VECT_LEN 64
39504 struct expand_vec_perm_d
39505 {
39512 };
39518 /* Get a vector mode of the same size as the original but with elements
39519 twice as wide. This is only guaranteed to apply to integral vectors. */
39523 {
39524 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
39529 }
39531 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
39532 fill target with val via vec_duplicate. */
39534 static bool
39536 {
39540 /* First attempt to recognize VAL as-is. */
39544 {
39545 rtx seq;
39546 /* If that fails, force VAL into a register. */
39557 }
39559 }
39561 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39562 with all elements equal to VAR. Return true if successful. */
39564 static bool
39567 {
39571 {
39576 /* FALLTHRU */
39596 {
39597 rtx x;
39604 }
39614 {
39618 permute:
39626 /* Extend to SImode using a paradoxical SUBREG. */
39630 /* Insert the SImode value as low element of a V4SImode vector. */
39639 }
39647 widen:
39648 /* Replicate the value once into the next wider mode and recurse. */
39649 {
39651 rtx x;
39668 }
39672 {
39681 }
39686 }
39687 }
39689 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39690 whose ONE_VAR element is VAR, and other elements are zero. Return true
39691 if successful. */
39693 static bool
39696 {
39698 rtx new_target;
39703 {
39705 /* For SSE4.1, we normally use vector set. But if the second
39706 element is zero and inter-unit moves are OK, we use movq
39707 instead. */
39709 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
39731 /* Use ix86_expand_vector_set in 64bit mode only. */
39736 }
39739 {
39744 }
39747 {
39752 /* FALLTHRU */
39767 else
39774 {
39775 /* We need to shuffle the value to the correct position, so
39776 create a new pseudo to store the intermediate result. */
39778 /* With SSE2, we can use the integer shuffle insns. */
39780 {
39782 const1_rtx,
39789 }
39791 /* Otherwise convert the intermediate result to V4SFmode and
39792 use the SSE1 shuffle instructions. */
39794 {
39797 }
39798 else
39802 const1_rtx,
39811 }
39826 widen:
39830 /* Zero extend the variable element to SImode and recurse. */
39843 }
39844 }
39846 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39847 consisting of the values in VALS. It is known that all elements
39848 except ONE_VAR are constants. Return true if successful. */
39850 static bool
39853 {
39863 {
39868 /* For the two element vectors, it's just as easy to use
39869 the general case. */
39873 /* Use ix86_expand_vector_set in 64bit mode only. */
39895 widen:
39896 /* There's no way to set one QImode entry easily. Combine
39897 the variable value with its adjacent constant value, and
39898 promote to an HImode set. */
39901 {
39906 }
39907 else
39908 {
39911 }
39925 }
39930 }
39932 /* A subroutine of ix86_expand_vector_init_general. Use vector
39933 concatenate to handle the most general case: all values variable,
39934 and none identical. */
39936 static void
39939 {
39942 rtvec v;
39946 {
39949 {
39994 }
40007 {
40022 }
40027 {
40046 }
40051 {
40064 }
40067 half:
40068 /* FIXME: We process inputs backward to help RA. PR 36222. */
40072 {
40077 }
40081 {
40085 {
40089 }
40092 {
40096 }
40099 }
40101 {
40104 {
40108 }
40111 }
40112 else
40118 }
40119 }
40121 /* A subroutine of ix86_expand_vector_init_general. Use vector
40122 interleave to handle the most general case: all values variable,
40123 and none identical. */
40125 static void
40128 {
40137 {
40158 }
40161 {
40162 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
40166 /* Insert the SImode value as low element of V4SImode vector. */
40170 op0),
40172 const1_rtx);
40175 /* Cast the V4SImode vector back to a vector in orignal mode. */
40179 /* Load even elements into the second position. */
40183 const1_rtx));
40185 /* Cast vector to FIRST_IMODE vector. */
40188 }
40190 /* Interleave low FIRST_IMODE vectors. */
40192 {
40196 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
40199 }
40201 /* Interleave low SECOND_IMODE vectors. */
40203 {
40206 {
40211 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
40212 vector. */
40215 }
40218 /* FALLTHRU */
40225 /* Cast the SECOND_IMODE vector back to a vector on original
40226 mode. */
40233 }
40234 }
40236 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
40237 all values variable, and none identical. */
40239 static void
40242 {
40248 {
40253 /* FALLTHRU */
40281 half:
40298 /* FALLTHRU */
40304 /* Don't use ix86_expand_vector_init_interleave if we can't
40305 move from GPR to SSE register directly. */
40321 }
40323 {
40335 {
40339 {
40345 else
40346 {
40351 }
40352 }
40355 }
40360 {
40366 }
40368 {
40374 }
40375 else
40377 }
40378 }
40380 /* Initialize vector TARGET via VALS. Suppress the use of MMX
40381 instructions unless MMX_OK is true. */
40383 void
40385 {
40392 rtx x;
40395 {
40405 }
40407 /* Constants are best loaded from the constant pool. */
40409 {
40412 }
40414 /* If all values are identical, broadcast the value. */
40420 /* Values where only one field is non-constant are best loaded from
40421 the pool and overwritten via move later. */
40423 {
40427 one_var))
40432 }
40435 }
40437 void
40439 {
40444 rtx tmp;
40446 = {
40453 };
40455 = {
40462 };
40466 {
40470 {
40475 else
40479 }
40491 else
40497 {
40500 /* For the two element vectors, we implement a VEC_CONCAT with
40501 the extraction of the other element. */
40508 else
40513 }
40522 {
40528 /* tmp = target = A B C D */
40530 /* target = A A B B */
40532 /* target = X A B B */
40534 /* target = A X C D */
40541 /* tmp = target = A B C D */
40543 /* tmp = X B C D */
40545 /* target = A B X D */
40552 /* tmp = target = A B C D */
40554 /* tmp = X B C D */
40556 /* target = A B X D */
40564 }
40572 /* Element 0 handled by vec_merge below. */
40574 {
40577 }
40580 {
40581 /* With SSE2, use integer shuffles to swap element 0 and ELT,
40582 store into element 0, then shuffle them back. */
40599 }
40600 else
40601 {
40602 /* For SSE1, we have to reuse the V4SF code. */
40606 }
40659 half:
40660 /* Compute offset. */
40666 /* Extract the half. */
40670 /* Put val in tmp at elt. */
40673 /* Put it back. */
40679 }
40682 {
40686 }
40687 else
40688 {
40697 }
40698 }
40700 void
40702 {
40706 rtx tmp;
40709 {
40714 /* FALLTHRU */
40727 {
40747 }
40759 {
40761 {
40781 }
40785 }
40786 else
40787 {
40788 /* For SSE1, we have to reuse the V4SF code. */
40792 }
40808 {
40812 else
40816 }
40821 {
40825 else
40829 }
40834 {
40838 else
40842 }
40847 {
40851 else
40855 }
40860 {
40864 else
40868 }
40873 {
40877 else
40881 }
40888 else
40897 else
40906 else
40915 else
40921 /* ??? Could extract the appropriate HImode element and shift. */
40924 }
40927 {
40931 /* Let the rtl optimizers know about the zero extension performed. */
40933 {
40936 }
40939 }
40940 else
40941 {
40948 }
40949 }
40951 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
40952 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
40953 The upper bits of DEST are undefined, though they shouldn't cause
40954 exceptions (some bits from src or all zeros are ok). */
40956 static void
40958 {
40961 {
40965 else
40983 else
40990 else
40998 {
41003 const1_rtx);
41004 }
41005 else
41006 {
41010 }
41030 else
41052 }
41056 }
41058 /* Expand a vector reduction. FN is the binary pattern to reduce;
41059 DEST is the destination; IN is the input vector. */
41061 void
41063 {
41068 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
41072 {
41075 }
41080 {
41085 else
41089 }
41090 }
41091 \f
41092 /* Target hook for scalar_mode_supported_p. */
41093 static bool
41095 {
41100 else
41102 }
41104 /* Implements target hook vector_mode_supported_p. */
41105 static bool
41107 {
41121 }
41123 /* Target hook for c_mode_for_suffix. */
41124 static enum machine_mode
41126 {
41133 }
41135 /* Worker function for TARGET_MD_ASM_CLOBBERS.
41137 We do this in the new i386 backend to maintain source compatibility
41138 with the old cc0-based compiler. */
41140 static tree
41142 tree inputs ATTRIBUTE_UNUSED,
41143 tree clobbers)
41144 {
41146 clobbers);
41148 clobbers);
41150 }
41152 /* Implements target vector targetm.asm.encode_section_info. */
41154 static void ATTRIBUTE_UNUSED
41156 {
41163 }
41165 /* Worker function for REVERSE_CONDITION. */
41167 enum rtx_code
41169 {
41173 }
41175 /* Output code to perform an x87 FP register move, from OPERANDS[1]
41176 to OPERANDS[0]. */
41180 {
41182 {
41185 {
41189 }
41193 }
41195 {
41199 else
41200 {
41201 /* There is no non-popping store to memory for XFmode.
41202 So if we need one, follow the store with a load. */
41205 else
41207 }
41208 }
41209 else
41211 }
41213 /* Output code to perform a conditional jump to LABEL, if C2 flag in
41214 FP status register is set. */
41216 void
41218 {
41220 rtx temp;
41225 {
41230 }
41231 else
41232 {
41237 }
41241 pc_rtx);
41246 }
41248 /* Output code to perform a log1p XFmode calculation. */
41251 {
41257 rtx test;
41263 XFmode));
41277 }
41279 /* Emit code for round calculation. */
41281 {
41288 rtx insn;
41293 {
41305 }
41308 {
41329 }
41337 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
41339 /* scratch = fxam(op1) */
41342 UNSPEC_FXAM)));
41343 /* e1 = fabs(op1) */
41346 /* e2 = e1 + 0.5 */
41351 /* res = floor(e2) */
41353 {
41358 }
41359 else
41363 {
41366 {
41373 UNSPEC_TRUNC_NOOP)));
41374 }
41390 }
41392 /* flags = signbit(a) */
41395 /* if (flags) then res = -res */
41399 pc_rtx);
41410 }
41412 /* Output code to perform a Newton-Rhapson approximation of a single precision
41413 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
41416 {
41424 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
41428 /* x0 = rcp(b) estimate */
41432 UNSPEC_RCP14)));
41433 else
41436 UNSPEC_RCP)));
41438 /* e0 = x0 * b */
41442 /* e0 = x0 * e0 */
41446 /* e1 = x0 + x0 */
41450 /* x1 = e1 - e0 */
41454 /* res = a * x1 */
41457 }
41459 /* Output code to perform a Newton-Rhapson approximation of a
41460 single precision floating point [reciprocal] square root. */
41464 {
41466 REAL_VALUE_TYPE r;
41483 {
41486 /* There is no 512-bit rsqrt. There is however rsqrt14. */
41489 }
41491 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
41492 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
41496 /* x0 = rsqrt(a) estimate */
41499 unspec)));
41501 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
41503 {
41511 /* Handle masked compare. */
41513 {
41515 /* Imm value 0x4 corresponds to not-equal comparison. */
41518 }
41519 else
41520 {
41526 }
41527 }
41529 /* e0 = x0 * a */
41532 /* e1 = e0 * x0 */
41536 /* e2 = e1 - 3. */
41543 /* e3 = -.5 * x0 */
41546 else
41547 /* e3 = -.5 * e0 */
41550 /* ret = e2 * e3 */
41553 }
41555 #ifdef TARGET_SOLARIS
41556 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
41558 static void
41560 tree decl)
41561 {
41562 /* With Binutils 2.15, the "@unwind" marker must be specified on
41563 every occurrence of the ".eh_frame" section, not just the first
41564 one. */
41567 {
41571 }
41573 #ifndef USE_GAS
41575 {
41578 }
41579 #endif
41582 }
41585 /* Return the mangling of TYPE if it is an extended fundamental type. */
41589 {
41597 {
41599 /* __float128 is "g". */
41602 /* "long double" or __float80 is "e". */
41606 }
41607 }
41609 /* For 32-bit code we can save PIC register setup by using
41610 __stack_chk_fail_local hidden function instead of calling
41611 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
41612 register, so it is better to call __stack_chk_fail directly. */
41614 static tree ATTRIBUTE_UNUSED
41616 {
41617 return TARGET_64BIT
41620 }
41622 /* Select a format to encode pointers in exception handling data. CODE
41623 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
41624 true if the symbol may be affected by dynamic relocations.
41626 ??? All x86 object file formats are capable of representing this.
41627 After all, the relocation needed is the same as for the call insn.
41628 Whether or not a particular assembler allows us to enter such, I
41629 guess we'll have to see. */
41630 int
41632 {
41634 {
41641 }
41646 }
41647 \f
41648 /* Expand copysign from SIGN to the positive value ABS_VALUE
41649 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
41650 the sign-bit. */
41651 static void
41653 {
41657 {
41664 else
41669 {
41670 /* We need to generate a scalar mode mask in this case. */
41675 }
41676 }
41677 else
41683 }
41685 /* Expand fabs (OP0) and return a new rtx that holds the result. The
41686 mask for masking out the sign-bit is stored in *SMASK, if that is
41687 non-null. */
41688 static rtx
41690 {
41699 else
41703 {
41704 /* We need to generate a scalar mode mask in this case. */
41709 }
41717 }
41719 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
41720 swapping the operands if SWAP_OPERANDS is true. The expanded
41721 code is a forward jump to a newly created label in case the
41722 comparison is true. The generated label rtx is returned. */
41723 static rtx
41726 {
41731 {
41735 }
41748 }
41750 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
41751 using comparison code CODE. Operands are swapped for the comparison if
41752 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
41753 static rtx
41756 {
41762 {
41766 }
41773 }
41775 /* Generate and return a rtx of mode MODE for 2**n where n is the number
41776 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
41777 static rtx
41779 {
41780 REAL_VALUE_TYPE TWO52r;
41781 rtx TWO52;
41788 }
41790 /* Expand SSE sequence for computing lround from OP1 storing
41791 into OP0. */
41792 void
41794 {
41795 /* C code for the stuff we're doing below:
41796 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
41797 return (long)tmp;
41798 */
41802 rtx adj;
41804 /* load nextafter (0.5, 0.0) */
41809 /* adj = copysign (0.5, op1) */
41813 /* adj = op1 + adj */
41816 /* op0 = (imode)adj */
41818 }
41820 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
41821 into OPERAND0. */
41822 void
41824 {
41825 /* C code for the stuff we're doing below (for do_floor):
41826 xi = (long)op1;
41827 xi -= (double)xi > op1 ? 1 : 0;
41828 return xi;
41829 */
41834 /* reg = (long)op1 */
41838 /* freg = (double)reg */
41842 /* ireg = (freg > op1) ? ireg - 1 : ireg */
41853 }
41855 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
41856 result in OPERAND0. */
41857 void
41859 {
41860 /* C code for the stuff we're doing below:
41861 xa = fabs (operand1);
41862 if (!isless (xa, 2**52))
41863 return operand1;
41864 xa = xa + 2**52 - 2**52;
41865 return copysign (xa, operand1);
41866 */
41873 /* xa = abs (operand1) */
41876 /* if (!isless (xa, TWO52)) goto label; */
41889 }
41891 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
41892 into OPERAND0. */
41893 void
41895 {
41896 /* C code for the stuff we expand below.
41897 double xa = fabs (x), x2;
41898 if (!isless (xa, TWO52))
41899 return x;
41900 xa = xa + TWO52 - TWO52;
41901 x2 = copysign (xa, x);
41902 Compensate. Floor:
41903 if (x2 > x)
41904 x2 -= 1;
41905 Compensate. Ceil:
41906 if (x2 < x)
41907 x2 -= -1;
41908 return x2;
41909 */
41915 /* Temporary for holding the result, initialized to the input
41916 operand to ease control flow. */
41920 /* xa = abs (operand1) */
41923 /* if (!isless (xa, TWO52)) goto label; */
41926 /* xa = xa + TWO52 - TWO52; */
41930 /* xa = copysign (xa, operand1) */
41933 /* generate 1.0 or -1.0 */
41938 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
41942 /* We always need to subtract here to preserve signed zero. */
41951 }
41953 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
41954 into OPERAND0. */
41955 void
41957 {
41958 /* C code for the stuff we expand below.
41959 double xa = fabs (x), x2;
41960 if (!isless (xa, TWO52))
41961 return x;
41962 x2 = (double)(long)x;
41963 Compensate. Floor:
41964 if (x2 > x)
41965 x2 -= 1;
41966 Compensate. Ceil:
41967 if (x2 < x)
41968 x2 += 1;
41969 if (HONOR_SIGNED_ZEROS (mode))
41970 return copysign (x2, x);
41971 return x2;
41972 */
41978 /* Temporary for holding the result, initialized to the input
41979 operand to ease control flow. */
41983 /* xa = abs (operand1) */
41986 /* if (!isless (xa, TWO52)) goto label; */
41989 /* xa = (double)(long)x */
41994 /* generate 1.0 */
41997 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
42012 }
42014 /* Expand SSE sequence for computing round from OPERAND1 storing
42015 into OPERAND0. Sequence that works without relying on DImode truncation
42016 via cvttsd2siq that is only available on 64bit targets. */
42017 void
42019 {
42020 /* C code for the stuff we expand below.
42021 double xa = fabs (x), xa2, x2;
42022 if (!isless (xa, TWO52))
42023 return x;
42024 Using the absolute value and copying back sign makes
42025 -0.0 -> -0.0 correct.
42026 xa2 = xa + TWO52 - TWO52;
42027 Compensate.
42028 dxa = xa2 - xa;
42029 if (dxa <= -0.5)
42030 xa2 += 1;
42031 else if (dxa > 0.5)
42032 xa2 -= 1;
42033 x2 = copysign (xa2, x);
42034 return x2;
42035 */
42041 /* Temporary for holding the result, initialized to the input
42042 operand to ease control flow. */
42046 /* xa = abs (operand1) */
42049 /* if (!isless (xa, TWO52)) goto label; */
42052 /* xa2 = xa + TWO52 - TWO52; */
42056 /* dxa = xa2 - xa; */
42059 /* generate 0.5, 1.0 and -0.5 */
42065 /* Compensate. */
42067 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
42072 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
42078 /* res = copysign (xa2, operand1) */
42085 }
42087 /* Expand SSE sequence for computing trunc from OPERAND1 storing
42088 into OPERAND0. */
42089 void
42091 {
42092 /* C code for SSE variant we expand below.
42093 double xa = fabs (x), x2;
42094 if (!isless (xa, TWO52))
42095 return x;
42096 x2 = (double)(long)x;
42097 if (HONOR_SIGNED_ZEROS (mode))
42098 return copysign (x2, x);
42099 return x2;
42100 */
42106 /* Temporary for holding the result, initialized to the input
42107 operand to ease control flow. */
42111 /* xa = abs (operand1) */
42114 /* if (!isless (xa, TWO52)) goto label; */
42117 /* x = (double)(long)x */
42129 }
42131 /* Expand SSE sequence for computing trunc from OPERAND1 storing
42132 into OPERAND0. */
42133 void
42135 {
42139 /* C code for SSE variant we expand below.
42140 double xa = fabs (x), x2;
42141 if (!isless (xa, TWO52))
42142 return x;
42143 xa2 = xa + TWO52 - TWO52;
42144 Compensate:
42145 if (xa2 > xa)
42146 xa2 -= 1.0;
42147 x2 = copysign (xa2, x);
42148 return x2;
42149 */
42153 /* Temporary for holding the result, initialized to the input
42154 operand to ease control flow. */
42158 /* xa = abs (operand1) */
42161 /* if (!isless (xa, TWO52)) goto label; */
42164 /* res = xa + TWO52 - TWO52; */
42169 /* generate 1.0 */
42172 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
42180 /* res = copysign (res, operand1) */
42187 }
42189 /* Expand SSE sequence for computing round from OPERAND1 storing
42190 into OPERAND0. */
42191 void
42193 {
42194 /* C code for the stuff we're doing below:
42195 double xa = fabs (x);
42196 if (!isless (xa, TWO52))
42197 return x;
42198 xa = (double)(long)(xa + nextafter (0.5, 0.0));
42199 return copysign (xa, x);
42200 */
42206 /* Temporary for holding the result, initialized to the input
42207 operand to ease control flow. */
42215 /* load nextafter (0.5, 0.0) */
42220 /* xa = xa + 0.5 */
42224 /* xa = (double)(int64_t)xa */
42229 /* res = copysign (xa, operand1) */
42236 }
42238 /* Expand SSE sequence for computing round
42239 from OP1 storing into OP0 using sse4 round insn. */
42240 void
42242 {
42251 {
42262 }
42264 /* round (a) = trunc (a + copysign (0.5, a)) */
42266 /* load nextafter (0.5, 0.0) */
42272 /* e1 = copysign (0.5, op1) */
42276 /* e2 = op1 + e1 */
42279 /* res = trunc (e2) */
42284 }
42285 \f
42287 /* Table of valid machine attributes. */
42289 {
42290 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
42291 affects_type_identity } */
42292 /* Stdcall attribute says callee is responsible for popping arguments
42293 if they are not variable. */
42296 /* Fastcall attribute says callee is responsible for popping arguments
42297 if they are not variable. */
42300 /* Thiscall attribute says callee is responsible for popping arguments
42301 if they are not variable. */
42304 /* Cdecl attribute says the callee is a normal C declaration */
42307 /* Regparm attribute specifies how many integer arguments are to be
42308 passed in registers. */
42311 /* Sseregparm attribute says we are using x86_64 calling conventions
42312 for FP arguments. */
42315 /* The transactional memory builtins are implicitly regparm or fastcall
42316 depending on the ABI. Override the generic do-nothing attribute that
42317 these builtins were declared with. */
42320 /* force_align_arg_pointer says this function realigns the stack at entry. */
42323 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42328 #endif
42333 #ifdef SUBTARGET_ATTRIBUTE_TABLE
42334 SUBTARGET_ATTRIBUTE_TABLE,
42335 #endif
42336 /* ms_abi and sysv_abi calling convention function attributes. */
42343 /* End element. */
42345 };
42347 /* Implement targetm.vectorize.builtin_vectorization_cost. */
42348 static int
42350 tree vectype,
42352 {
42356 {
42401 }
42402 }
42404 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
42405 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
42406 insn every time. */
42410 /* Initialize vselect_insn. */
42412 static void
42414 {
42416 rtx x;
42427 }
42429 /* Construct (set target (vec_select op0 (parallel perm))) and
42430 return true if that's a valid instruction in the active ISA. */
42432 static bool
42435 {
42461 }
42463 /* Similar, but generate a vec_concat from op0 and op1 as well. */
42465 static bool
42469 {
42471 rtx x;
42486 }
42488 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42489 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
42491 static bool
42493 {
42502 ;
42504 ;
42506 ;
42507 else
42510 /* This is a blend, not a permute. Elements must stay in their
42511 respective lanes. */
42513 {
42517 }
42522 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
42523 decision should be extracted elsewhere, so that we only try that
42524 sequence once all budget==3 options have been tried. */
42531 {
42555 /* See if bytes move in pairs so we can use pblendw with
42556 an immediate argument, rather than pblendvb with a vector
42557 argument. */
42560 {
42561 use_pblendvb:
42565 finish_pblendvb:
42571 else
42576 }
42581 /* FALLTHRU */
42583 do_subreg:
42590 /* See if bytes move in pairs. If not, vpblendvb must be used. */
42594 /* See if bytes move in quadruplets. If yes, vpblendd
42595 with immediate can be used. */
42600 {
42601 /* See if bytes move the same in both lanes. If yes,
42602 vpblendw with immediate can be used. */
42607 /* Use vpblendw. */
42612 }
42614 /* Use vpblendd. */
42621 /* See if words move in pairs. If yes, vpblendd can be used. */
42626 {
42627 /* See if words move the same in both lanes. If not,
42628 vpblendvb must be used. */
42631 {
42632 /* Use vpblendvb. */
42642 }
42644 /* Use vpblendw. */
42648 }
42650 /* Use vpblendd. */
42657 /* Use vpblendd. */
42665 }
42667 /* This matches five different patterns with the different modes. */
42675 }
42677 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42678 in terms of the variable form of vpermilps.
42680 Note that we will have already failed the immediate input vpermilps,
42681 which requires that the high and low part shuffle be identical; the
42682 variable form doesn't require that. */
42684 static bool
42686 {
42693 /* We can only permute within the 128-bit lane. */
42695 {
42699 }
42705 {
42708 /* Within each 128-bit lane, the elements of op0 are numbered
42709 from 0 and the elements of op1 are numbered from 4. */
42716 }
42723 }
42725 /* Return true if permutation D can be performed as VMODE permutation
42726 instead. */
42728 static bool
42730 {
42745 else
42751 }
42753 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42754 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
42756 static bool
42758 {
42767 {
42769 {
42772 {
42776 /* Use vperm2i128 insn. The pattern uses
42777 V4DImode instead of V2TImode. */
42790 }
42792 }
42793 }
42794 else
42795 {
42797 {
42800 }
42802 {
42806 /* V4DImode should be already handled through
42807 expand_vselect by vpermq instruction. */
42814 {
42815 /* First see if vpermq can be used for
42816 V8SImode/V16HImode/V32QImode. */
42818 {
42826 {
42830 }
42832 }
42834 /* Next see if vpermd can be used. */
42837 }
42838 /* Or if vpermps can be used. */
42843 {
42844 /* vpshufb only works intra lanes, it is not
42845 possible to shuffle bytes in between the lanes. */
42849 }
42850 }
42851 else
42853 }
42861 else
42862 {
42868 else
42872 {
42876 }
42877 }
42888 {
42895 else
42897 }
42898 else
42899 {
42902 }
42907 }
42909 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
42910 in a single instruction. */
42912 static bool
42914 {
42918 /* Check plain VEC_SELECT first, because AVX has instructions that could
42919 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
42920 input where SEL+CONCAT may not. */
42922 {
42928 {
42934 }
42937 {
42941 }
42943 {
42944 /* Use vpbroadcast{b,w,d}. */
42947 {
42966 /* For other modes prefer other shuffles this function creates. */
42968 }
42970 {
42974 }
42975 }
42980 /* There are plenty of patterns in sse.md that are written for
42981 SEL+CONCAT and are not replicated for a single op. Perhaps
42982 that should be changed, to avoid the nastiness here. */
42984 /* Recognize interleave style patterns, which means incrementing
42985 every other permutation operand. */
42987 {
42990 }
42995 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
42997 {
42999 {
43004 }
43009 }
43010 }
43012 /* Finally, try the fully general two operand permute. */
43017 /* Recognize interleave style patterns with reversed operands. */
43019 {
43021 {
43025 else
43028 }
43033 }
43035 /* Try the SSE4.1 blend variable merge instructions. */
43039 /* Try one of the AVX vpermil variable permutations. */
43043 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
43044 vpshufb, vpermd, vpermps or vpermq variable permutation. */
43048 /* Try the AVX512F vpermi2 instructions. */
43062 }
43064 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
43065 in terms of a pair of pshuflw + pshufhw instructions. */
43067 static bool
43069 {
43077 /* The two permutations only operate in 64-bit lanes. */
43088 /* Emit the pshuflw. */
43095 /* Emit the pshufhw. */
43103 }
43105 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43106 the permutation using the SSSE3 palignr instruction. This succeeds
43107 when all of the elements in PERM fit within one vector and we merely
43108 need to shift them down so that a single vector permutation has a
43109 chance to succeed. */
43111 static bool
43113 {
43120 /* Even with AVX, palignr only operates on 128-bit vectors. */
43126 {
43132 }
43136 /* Given that we have SSSE3, we know we'll be able to implement the
43137 single operand permutation after the palignr with pshufb. */
43152 {
43157 }
43159 /* Test for the degenerate case where the alignment by itself
43160 produces the desired permutation. */
43162 {
43165 }
43171 }
43175 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43176 a two vector permutation into a single vector permutation by using
43177 an interleave operation to merge the vectors. */
43179 static bool
43181 {
43186 rtx seq;
43190 {
43193 }
43195 {
43198 /* For 32-byte modes allow even d->one_operand_p.
43199 The lack of cross-lane shuffling in some instructions
43200 might prevent a single insn shuffle. */
43203 /* If expand_vec_perm_interleave3 can expand this into
43204 a 3 insn sequence, give up and let it be expanded as
43205 3 insn sequence. While that is one insn longer,
43206 it doesn't need a memory operand and in the common
43207 case that both interleave low and high permutations
43208 with the same operands are adjacent needs 4 insns
43209 for both after CSE. */
43212 }
43213 else
43216 /* Examine from whence the elements come. */
43225 {
43228 /* Split the two input vectors into 4 halves. */
43234 /* If the elements from the low halves use interleave low, and similarly
43235 for interleave high. If the elements are from mis-matched halves, we
43236 can use shufps for V4SF/V4SI or do a DImode shuffle. */
43238 {
43239 /* punpckl* */
43241 {
43246 }
43249 }
43251 {
43252 /* punpckh* */
43254 {
43259 }
43262 }
43264 {
43265 /* shufps */
43267 {
43272 }
43274 {
43275 /* shufpd */
43280 }
43281 }
43283 {
43284 /* shufps */
43286 {
43291 }
43293 {
43294 /* shufpd */
43299 }
43300 }
43301 else
43303 }
43304 else
43305 {
43310 /* Split the two input vectors into 8 quarters. */
43316 {
43319 }
43322 {
43326 }
43328 {
43331 }
43334 {
43336 {
43337 /* Attempt to increase the likelihood that dfinal
43338 shuffle will be intra-lane. */
43342 }
43344 /* vperm2f128 or vperm2i128. */
43346 {
43351 }
43356 {
43360 {
43363 }
43364 }
43365 }
43370 {
43371 /* vpunpckl* */
43373 {
43382 }
43383 }
43386 {
43387 /* vpunpckh* */
43389 {
43398 }
43399 }
43400 else
43402 }
43404 /* Use the remapping array set up above to move the elements from their
43405 swizzled locations into their final destinations. */
43408 {
43411 /* If same_halves is true, both halves of the remapped vector are the
43412 same. Avoid cross-lane accesses if possible. */
43414 {
43417 }
43418 else
43420 }
43422 {
43425 }
43429 /* Test if the final remap can be done with a single insn. For V4SFmode or
43430 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
43443 {
43446 }
43453 }
43455 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43456 a single vector cross-lane permutation into vpermq followed
43457 by any of the single insn permutations. */
43459 static bool
43461 {
43475 {
43478 }
43481 {
43486 }
43499 {
43506 }
43513 {
43518 ;
43521 else
43523 }
43532 }
43534 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
43535 a vector permutation using two instructions, vperm2f128 resp.
43536 vperm2i128 followed by any single in-lane permutation. */
43538 static bool
43540 {
43554 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
43555 immediate. For perm < 16 the second permutation uses
43556 d->op0 as first operand, for perm >= 16 it uses d->op1
43557 as first operand. The second operand is the result of
43558 vperm2[fi]128. */
43560 {
43561 /* Ignore permutations which do not move anything cross-lane. */
43563 {
43564 /* The second shuffle for e.g. V4DFmode has
43565 0123 and ABCD operands.
43566 Ignore AB23, as 23 is already in the second lane
43567 of the first operand. */
43569 /* And 01CD, as 01 is in the first lane of the first
43570 operand. */
43572 /* And 4567, as then the vperm2[fi]128 doesn't change
43573 anything on the original 4567 second operand. */
43575 }
43576 else
43577 {
43578 /* The second shuffle for e.g. V4DFmode has
43579 4567 and ABCD operands.
43580 Ignore AB67, as 67 is already in the second lane
43581 of the first operand. */
43583 /* And 45CD, as 45 is in the first lane of the first
43584 operand. */
43586 /* And 0123, as then the vperm2[fi]128 doesn't change
43587 anything on the original 0123 first operand. */
43589 }
43592 {
43598 else
43600 }
43603 {
43607 }
43608 else
43612 {
43616 /* Found a usable second shuffle. dfirst will be
43617 vperm2f128 on d->op0 and d->op1. */
43628 /* And dsecond is some single insn shuffle, taking
43629 d->op0 and result of vperm2f128 (if perm < 16) or
43630 d->op1 and result of vperm2f128 (otherwise). */
43639 }
43641 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
43644 }
43647 }
43649 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43650 a two vector permutation using 2 intra-lane interleave insns
43651 and cross-lane shuffle for 32-byte vectors. */
43653 static bool
43655 {
43662 ;
43664 ;
43665 else
43680 {
43684 else
43690 else
43696 else
43702 else
43708 else
43714 else
43719 }
43723 }
43725 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
43726 a single vector permutation using a single intra-lane vector
43727 permutation, vperm2f128 swapping the lanes and vblend* insn blending
43728 the non-swapped and swapped vectors together. */
43730 static bool
43732 {
43735 rtx seq;
43740 || TARGET_AVX2
43749 {
43756 }
43791 }
43793 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
43794 permutation using two vperm2f128, followed by a vshufpd insn blending
43795 the two vectors together. */
43797 static bool
43799 {
43842 }
43844 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
43845 permutation with two pshufb insns and an ior. We should have already
43846 failed all two instruction sequences. */
43848 static bool
43850 {
43864 /* Generate two permutation masks. If the required element is within
43865 the given vector it is shuffled into the proper lane. If the required
43866 element is in the other vector, force a zero into the lane by setting
43867 bit 7 in the permutation mask. */
43870 {
43877 {
43880 }
43881 }
43905 }
43907 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
43908 with two vpshufb insns, vpermq and vpor. We should have already failed
43909 all two or three instruction sequences. */
43911 static bool
43913 {
43928 /* Generate two permutation masks. If the required element is within
43929 the same lane, it is shuffled in. If the required element from the
43930 other lane, force a zero by setting bit 7 in the permutation mask.
43931 In the other mask the mask has non-negative elements if element
43932 is requested from the other lane, but also moved to the other lane,
43933 so that the result of vpshufb can have the two V2TImode halves
43934 swapped. */
43937 {
43942 {
43945 }
43946 }
43955 /* Swap the 128-byte lanes of h into hp. */
43959 const1_rtx));
43976 }
43978 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
43979 and extract-odd permutations of two V32QImode and V16QImode operand
43980 with two vpshufb insns, vpor and vpermq. We should have already
43981 failed all two or three instruction sequences. */
43983 static bool
43985 {
44004 /* Generate two permutation masks. In the first permutation mask
44005 the first quarter will contain indexes for the first half
44006 of the op0, the second quarter will contain bit 7 set, third quarter
44007 will contain indexes for the second half of the op0 and the
44008 last quarter bit 7 set. In the second permutation mask
44009 the first quarter will contain bit 7 set, the second quarter
44010 indexes for the first half of the op1, the third quarter bit 7 set
44011 and last quarter indexes for the second half of the op1.
44012 I.e. the first mask e.g. for V32QImode extract even will be:
44013 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
44014 (all values masked with 0xf except for -128) and second mask
44015 for extract even will be
44016 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
44019 {
44025 {
44028 }
44029 }
44048 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
44056 }
44058 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
44059 and extract-odd permutations. */
44061 static bool
44063 {
44067 {
44074 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
44078 /* Now an unpck[lh]pd will produce the result required. */
44081 else
44087 {
44096 /* Shuffle within the 128-bit lanes to produce:
44097 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
44101 /* Shuffle the lanes around to produce:
44102 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
44106 /* Shuffle within the 128-bit lanes to produce:
44107 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
44110 /* Shuffle within the 128-bit lanes to produce:
44111 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
44114 /* Shuffle the lanes around to produce:
44115 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
44118 }
44125 /* These are always directly implementable by expand_vec_perm_1. */
44131 else
44132 {
44135 /* We need 2*log2(N)-1 operations to achieve odd/even
44136 with interleave. */
44145 else
44148 }
44154 else
44155 {
44169 else
44172 }
44181 {
44186 else
44191 {
44196 }
44198 }
44206 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
44210 /* Now an vpunpck[lh]qdq will produce the result required. */
44213 else
44220 {
44225 else
44230 {
44235 }
44237 }
44248 /* Shuffle the lanes around into
44249 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
44257 /* Swap the 2nd and 3rd position in each lane into
44258 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
44264 /* Now an vpunpck[lh]qdq will produce
44265 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
44269 else
44278 }
44281 }
44283 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
44284 extract-even and extract-odd permutations. */
44286 static bool
44288 {
44300 }
44302 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
44303 permutations. We assume that expand_vec_perm_1 has already failed. */
44305 static bool
44307 {
44315 {
44318 /* These are special-cased in sse.md so that we can optionally
44319 use the vbroadcast instruction. They expand to two insns
44320 if the input happens to be in a register. */
44327 /* These are always implementable using standard shuffle patterns. */
44332 /* These can be implemented via interleave. We save one insn by
44333 stopping once we have promoted to V4SImode and then use pshufd. */
44336 do
44337 {
44338 rtx dest;
44344 {
44348 }
44355 }
44370 /* For AVX2 broadcasts of the first element vpbroadcast* or
44371 vpermq should be used by expand_vec_perm_1. */
44377 }
44378 }
44380 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
44381 broadcast permutations. */
44383 static bool
44385 {
44397 }
44399 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
44400 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
44401 all the shorter instruction sequences. */
44403 static bool
44405 {
44421 /* Generate 4 permutation masks. If the required element is within
44422 the same lane, it is shuffled in. If the required element from the
44423 other lane, force a zero by setting bit 7 in the permutation mask.
44424 In the other mask the mask has non-negative elements if element
44425 is requested from the other lane, but also moved to the other lane,
44426 so that the result of vpshufb can have the two V2TImode halves
44427 swapped. */
44430 {
44435 }
44441 {
44449 }
44452 {
44454 {
44457 }
44464 }
44466 /* Swap the 128-byte lanes of h[X]. */
44468 {
44474 const1_rtx));
44476 }
44479 {
44481 {
44484 }
44490 }
44493 {
44495 {
44499 }
44502 }
44512 }
44514 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
44515 With all of the interface bits taken care of, perform the expansion
44516 in D and return true on success. */
44518 static bool
44520 {
44521 /* Try a single instruction expansion. */
44525 /* Try sequences of two instructions. */
44545 /* Try sequences of three instructions. */
44559 /* Try sequences of four instructions. */
44567 /* ??? Look for narrow permutations whose element orderings would
44568 allow the promotion to a wider mode. */
44570 /* ??? Look for sequences of interleave or a wider permute that place
44571 the data into the correct lanes for a half-vector shuffle like
44572 pshuf[lh]w or vpermilps. */
44574 /* ??? Look for sequences of interleave that produce the desired results.
44575 The combinatorics of punpck[lh] get pretty ugly... */
44580 /* Even longer sequences. */
44585 }
44587 /* If a permutation only uses one operand, make it clear. Returns true
44588 if the permutation references both operands. */
44590 static bool
44592 {
44600 {
44606 {
44609 }
44610 /* The elements of PERM do not suggest that only the first operand
44611 is used, but both operands are identical. Allow easier matching
44612 of the permutation by folding the permutation into the single
44613 input vector. */
44614 /* FALLTHRU */
44625 }
44628 }
44630 bool
44632 {
44637 rtx sel;
44654 {
44659 }
44666 /* If the selector says both arguments are needed, but the operands are the
44667 same, the above tried to expand with one_operand_p and flattened selector.
44668 If that didn't work, retry without one_operand_p; we succeeded with that
44669 during testing. */
44671 {
44675 }
44678 }
44680 /* Implement targetm.vectorize.vec_perm_const_ok. */
44682 static bool
44685 {
44694 /* Given sufficient ISA support we can just return true here
44695 for selected vector modes. */
44698 /* All implementable with a single vpermi2 insn. */
44701 {
44702 /* All implementable with a single vpperm insn. */
44705 /* All implementable with 2 pshufb + 1 ior. */
44708 /* All implementable with shufpd or unpck[lh]pd. */
44711 }
44713 /* Extract the values from the vector CST into the permutation
44714 array in D. */
44717 {
44721 }
44723 /* For all elements from second vector, fold the elements to first. */
44728 /* Check whether the mask can be applied to the vector type. */
44731 /* Implementable with shufps or pshufd. */
44735 /* Otherwise we have to go through the motions and see if we can
44736 figure out how to generate the requested permutation. */
44747 }
44749 void
44751 {
44766 /* We'll either be able to implement the permutation directly... */
44770 /* ... or we use the special-case patterns. */
44772 }
44774 static void
44776 {
44791 {
44794 }
44796 /* Note that for AVX this isn't one instruction. */
44799 }
44802 /* Expand a vector operation CODE for a V*QImode in terms of the
44803 same operation on V*HImode. */
44805 void
44807 {
44819 {
44832 }
44836 {
44838 /* Unpack data such that we've got a source byte in each low byte of
44839 each word. We don't care what goes into the high byte of each word.
44840 Rather than trying to get zero in there, most convenient is to let
44841 it be a copy of the low byte. */
44846 /* FALLTHRU */
44858 /* FALLTHRU */
44868 }
44870 /* Perform the operation. */
44877 /* Merge the data back into the right place. */
44887 {
44888 /* For SSE2, we used an full interleave, so the desired
44889 results are in the even elements. */
44892 }
44893 else
44894 {
44895 /* For AVX, the interleave used above was not cross-lane. So the
44896 extraction is evens but with the second and third quarter swapped.
44897 Happily, that is even one insn shorter than even extraction. */
44900 }
44907 }
44909 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
44910 if op is CONST_VECTOR with all odd elements equal to their
44911 preceding element. */
44913 static bool
44915 {
44925 }
44927 void
44930 {
44933 rtx x;
44941 /* We only play even/odd games with vectors of SImode. */
44944 /* If we're looking for the odd results, shift those members down to
44945 the even slots. For some cpus this is faster than a PSHUFD. */
44947 {
44948 /* For XOP use vpmacsdqh, but only for smult, as it is only
44949 signed. */
44951 {
44955 }
44966 }
44969 {
44972 else
44974 }
44976 {
44979 else
44981 }
44986 else
44987 {
44990 /* The easiest way to implement this without PMULDQ is to go through
44991 the motions as if we are performing a full 64-bit multiply. With
44992 the exception that we need to do less shuffling of the elements. */
44994 /* Compute the sign-extension, aka highparts, of the two operands. */
45000 /* Multiply LO(A) * HI(B), and vice-versa. */
45006 /* Multiply LO(A) * LO(B). */
45010 /* Combine and shift the highparts into place. */
45015 /* Combine high and low parts. */
45018 }
45020 }
45022 void
45025 {
45031 {
45036 {
45037 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
45038 shuffle the elements once so that all elements are in the right
45039 place for immediate use: { A C B D }. */
45044 }
45045 else
45046 {
45047 /* Put the elements into place for the multiply. */
45051 }
45056 /* Shuffle the elements between the lanes. After this we
45057 have { A B E F | C D G H } for each operand. */
45067 /* Shuffle the elements within the lanes. After this we
45068 have { A A B B | C C D D } or { E E F F | G G H H }. */
45106 }
45107 }
45109 void
45111 {
45121 /* Move the results in element 2 down to element 1; we don't care
45122 what goes in elements 2 and 3. Then we can merge the parts
45123 back together with an interleave.
45125 Note that two other sequences were tried:
45126 (1) Use interleaves at the start instead of psrldq, which allows
45127 us to use a single shufps to merge things back at the end.
45128 (2) Use shufps here to combine the two vectors, then pshufd to
45129 put the elements in the correct order.
45130 In both cases the cost of the reformatting stall was too high
45131 and the overall sequence slower. */
45142 }
45144 void
45146 {
45151 {
45152 /* op1: A,B,C,D, op2: E,F,G,H */
45161 /* t1: B,A,D,C */
45168 /* t2: (B*E),(A*F),(D*G),(C*H) */
45171 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
45174 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
45177 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
45179 }
45180 else
45181 {
45186 {
45189 }
45191 {
45194 }
45196 {
45199 }
45200 else
45204 /* Multiply low parts. */
45208 /* Shift input vectors right 32 bits so we can multiply high parts. */
45213 /* Multiply high parts by low parts. */
45219 /* Combine and shift the highparts back. */
45223 /* Combine high and low parts. */
45225 }
45229 }
45231 /* Calculate integer abs() using only SSE2 instructions. */
45233 void
45235 {
45240 {
45241 /* For 32-bit signed integer X, the best way to calculate the absolute
45242 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
45254 /* For 16-bit signed integer X, the best way to calculate the absolute
45255 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
45263 /* For 8-bit signed integer X, the best way to calculate the absolute
45264 value of X is min ((unsigned char) X, (unsigned char) (-X)),
45265 as SSE2 provides the PMINUB insn. */
45275 }
45279 }
45281 /* Expand an insert into a vector register through pinsr insn.
45282 Return true if successful. */
45284 bool
45286 {
45294 {
45297 }
45303 {
45308 {
45315 {
45347 }
45361 }
45365 }
45366 }
45367 \f
45368 /* This function returns the calling abi specific va_list type node.
45369 It returns the FNDECL specific va_list type. */
45371 static tree
45373 {
45380 else
45382 }
45384 /* Returns the canonical va_list type specified by TYPE. If there
45385 is no valid TYPE provided, it return NULL_TREE. */
45387 static tree
45389 {
45392 /* Resolve references and pointers to va_list type. */
45401 {
45406 {
45407 /* If va_list is an array type, the argument may have decayed
45408 to a pointer type, e.g. by being passed to another function.
45409 In that case, unwrap both types so that we can compare the
45410 underlying records. */
45413 {
45416 }
45417 }
45424 {
45425 /* If va_list is an array type, the argument may have decayed
45426 to a pointer type, e.g. by being passed to another function.
45427 In that case, unwrap both types so that we can compare the
45428 underlying records. */
45431 {
45434 }
45435 }
45442 {
45443 /* If va_list is an array type, the argument may have decayed
45444 to a pointer type, e.g. by being passed to another function.
45445 In that case, unwrap both types so that we can compare the
45446 underlying records. */
45449 {
45452 }
45453 }
45457 }
45459 }
45461 /* Iterate through the target-specific builtin types for va_list.
45462 IDX denotes the iterator, *PTREE is set to the result type of
45463 the va_list builtin, and *PNAME to its internal type.
45464 Returns zero if there is no element for this index, otherwise
45465 IDX should be increased upon the next call.
45466 Note, do not iterate a base builtin's name like __builtin_va_list.
45467 Used from c_common_nodes_and_builtins. */
45469 static int
45471 {
45473 {
45475 {
45488 }
45489 }
45492 }
45494 #undef TARGET_SCHED_DISPATCH
45495 #define TARGET_SCHED_DISPATCH has_dispatch
45496 #undef TARGET_SCHED_DISPATCH_DO
45497 #define TARGET_SCHED_DISPATCH_DO do_dispatch
45498 #undef TARGET_SCHED_REASSOCIATION_WIDTH
45499 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
45500 #undef TARGET_SCHED_REORDER
45501 #define TARGET_SCHED_REORDER ix86_sched_reorder
45502 #undef TARGET_SCHED_ADJUST_PRIORITY
45503 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
45504 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
45505 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
45506 ix86_dependencies_evaluation_hook
45508 /* The size of the dispatch window is the total number of bytes of
45509 object code allowed in a window. */
45510 #define DISPATCH_WINDOW_SIZE 16
45512 /* Number of dispatch windows considered for scheduling. */
45513 #define MAX_DISPATCH_WINDOWS 3
45515 /* Maximum number of instructions in a window. */
45516 #define MAX_INSN 4
45518 /* Maximum number of immediate operands in a window. */
45519 #define MAX_IMM 4
45521 /* Maximum number of immediate bits allowed in a window. */
45522 #define MAX_IMM_SIZE 128
45524 /* Maximum number of 32 bit immediates allowed in a window. */
45525 #define MAX_IMM_32 4
45527 /* Maximum number of 64 bit immediates allowed in a window. */
45528 #define MAX_IMM_64 2
45530 /* Maximum total of loads or prefetches allowed in a window. */
45531 #define MAX_LOAD 2
45533 /* Maximum total of stores allowed in a window. */
45534 #define MAX_STORE 1
45536 #undef BIG
45537 #define BIG 100
45540 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
45543 disp_load,
45544 disp_store,
45545 disp_load_store,
45546 disp_prefetch,
45547 disp_imm,
45548 disp_imm_32,
45549 disp_imm_64,
45550 disp_branch,
45551 disp_cmp,
45552 disp_jcc,
45553 disp_last
45554 };
45556 /* Number of allowable groups in a dispatch window. It is an array
45557 indexed by dispatch_group enum. 100 is used as a big number,
45558 because the number of these kind of operations does not have any
45559 effect in dispatch window, but we need them for other reasons in
45560 the table. */
45563 };
45569 };
45571 /* Instruction path. */
45577 last_path
45578 };
45580 /* sched_insn_info defines a window to the instructions scheduled in
45581 the basic block. It contains a pointer to the insn_info table and
45582 the instruction scheduled.
45584 Windows are allocated for each basic block and are linked
45585 together. */
45587 rtx insn;
45594 /* Linked list of dispatch windows. This is a two way list of
45595 dispatch windows of a basic block. It contains information about
45596 the number of uops in the window and the total number of
45597 instructions and of bytes in the object code for this dispatch
45598 window. */
45616 /* Immediate valuse used in an insn. */
45618 {
45627 /* Get dispatch group of insn. */
45629 static enum dispatch_group
45631 {
45647 }
45649 /* Return true if insn is a compare instruction. */
45651 static bool
45653 {
45661 }
45663 /* Return true if a dispatch violation encountered. */
45665 static bool
45667 {
45671 }
45673 /* Return true if insn is a branch instruction. */
45675 static bool
45677 {
45679 }
45681 /* Return true if insn is a prefetch instruction. */
45683 static bool
45685 {
45687 }
45689 /* This function initializes a dispatch window and the list container holding a
45690 pointer to the window. */
45692 static void
45694 {
45700 else
45718 {
45724 }
45726 }
45728 /* This function allocates and initializes a dispatch window and the
45729 list container holding a pointer to the window. */
45733 {
45738 }
45740 /* This routine initializes the dispatch scheduling information. It
45741 initiates building dispatch scheduler tables and constructs the
45742 first dispatch window. */
45744 static void
45746 {
45747 /* Allocate a dispatch list and a window. */
45752 }
45754 /* This function returns true if a branch is detected. End of a basic block
45755 does not have to be a branch, but here we assume only branches end a
45756 window. */
45758 static bool
45760 {
45762 }
45764 /* This function is called when the end of a window processing is reached. */
45766 static void
45768 {
45771 {
45776 }
45778 }
45780 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
45781 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
45782 for 48 bytes of instructions. Note that these windows are not dispatch
45783 windows that their sizes are DISPATCH_WINDOW_SIZE. */
45787 {
45789 {
45794 }
45800 }
45802 /* Increment the number of immediate operands of an instruction. */
45804 static int
45806 {
45811 {
45818 else
45829 {
45832 }
45837 }
45840 }
45842 /* Compute number of immediate operands of an instruction. */
45844 static void
45846 {
45849 }
45851 /* Return total size of immediate operands of an instruction along with number
45852 of corresponding immediate-operands. It initializes its parameters to zero
45853 befor calling FIND_CONSTANT.
45854 INSN is the input instruction. IMM is the total of immediates.
45855 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
45856 bit immediates. */
45858 static int
45860 {
45868 }
45870 /* This function indicates if an operand of an instruction is an
45871 immediate. */
45873 static bool
45875 {
45884 }
45886 /* Return single or double path for instructions. */
45888 static enum insn_path
45890 {
45900 }
45902 /* Return insn dispatch group. */
45904 static enum dispatch_group
45906 {
45924 }
45926 /* Count number of GROUP restricted instructions in a dispatch
45927 window WINDOW_LIST. */
45929 static int
45931 {
45942 {
45961 }
45974 }
45976 /* This function returns true if insn satisfies dispatch rules on the
45977 last window scheduled. */
45979 static bool
45981 {
45989 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
45990 instructions should be given the lowest priority in the
45991 scheduling process in Haifa scheduler to make sure they will be
45992 scheduled in the same dispatch window as the reference to them. */
45996 /* Check nonrestricted. */
46000 /* Get last dispatch window. */
46005 {
46010 /* Window 1 is full. Go for next window. */
46012 }
46019 /* See if it fits in the first window. */
46021 {
46022 /* The first widow should have only single and double path
46023 uops. */
46029 }
46031 }
46033 /* Add an instruction INSN with NUM_UOPS micro-operations to the
46034 dispatch window WINDOW_LIST. */
46036 static void
46038 {
46056 /* Initialize window with new instruction. */
46077 {
46080 }
46081 }
46083 /* Adds a scheduled instruction, INSN, to the current dispatch window.
46084 If the total bytes of instructions or the number of instructions in
46085 the window exceed allowable, it allocates a new window. */
46087 static void
46089 {
46112 /* Get the last dispatch window. */
46120 else
46123 /* If current window is full, get a new window.
46124 Window number zero is full, if MAX_INSN uops are scheduled in it.
46125 Window number one is full, if window zero's bytes plus window
46126 one's bytes is 32, or if the bytes of the new instruction added
46127 to the total makes it greater than 48, or it has already MAX_INSN
46128 instructions in it. */
46137 {
46140 }
46143 {
46147 {
46150 }
46151 }
46153 {
46158 {
46161 }
46164 }
46165 else
46169 {
46170 /* End of basic block is reached do end-basic-block process. */
46173 }
46174 }
46176 /* Print the dispatch window, WINDOW_NUM, to FILE. */
46178 DEBUG_FUNCTION static void
46180 {
46186 else
46200 {
46203 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
46209 }
46210 }
46212 /* Print to stdout a dispatch window. */
46214 DEBUG_FUNCTION void
46216 {
46218 }
46220 /* Print INSN dispatch information to FILE. */
46222 DEBUG_FUNCTION static void
46224 {
46247 }
46249 /* Print to STDERR the status of the ready list with respect to
46250 dispatch windows. */
46252 DEBUG_FUNCTION void
46254 {
46262 }
46264 /* This routine is the driver of the dispatch scheduler. */
46266 static void
46268 {
46273 }
46275 /* Return TRUE if Dispatch Scheduling is supported. */
46277 static bool
46279 {
46283 {
46299 }
46302 }
46304 /* Implementation of reassociation_width target hook used by
46305 reassoc phase to identify parallelism level in reassociated
46306 tree. Statements tree_code is passed in OPC. Arguments type
46307 is passed in MODE.
46309 Currently parallel reassociation is enabled for Atom
46310 processors only and we set reassociation width to be 2
46311 because Atom may issue up to 2 instructions per cycle.
46313 Return value should be fixed if parallel reassociation is
46314 enabled for other processors. */
46316 static int
46319 {
46328 }
46330 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
46331 place emms and femms instructions. */
46333 static enum machine_mode
46335 {
46340 {
46357 else
46369 /* FALLTHRU */
46373 }
46374 }
46376 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
46377 vectors. If AVX512F is enabled then try vectorizing with 512bit,
46378 256bit and 128bit vectors. */
46380 static unsigned int
46382 {
46385 }
46387 \f
46389 /* Return class of registers which could be used for pseudo of MODE
46390 and of class RCLASS for spilling instead of memory. Return NO_REGS
46391 if it is not possible or non-profitable. */
46392 static reg_class_t
46394 {
46400 }
46402 /* Implement targetm.vectorize.init_cost. */
46406 {
46410 }
46412 /* Implement targetm.vectorize.add_stmt_cost. */
46414 static unsigned
46418 {
46425 /* Statements in an inner loop relative to the loop being
46426 vectorized are weighted more heavily. The value here is
46427 arbitrary and could potentially be improved with analysis. */
46435 }
46437 /* Implement targetm.vectorize.finish_cost. */
46439 static void
46442 {
46447 }
46449 /* Implement targetm.vectorize.destroy_cost_data. */
46451 static void
46453 {
46455 }
46457 /* Validate target specific memory model bits in VAL. */
46459 static unsigned HOST_WIDE_INT
46461 {
46468 {
46472 }
46475 {
46479 }
46481 {
46485 }
46487 }
46489 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
46490 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
46491 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
46492 or number of vecsize_mangle variants that should be emitted. */
46494 static int
46498 {
46505 {
46509 }
46514 {
46521 /* case SCmode: */
46522 /* case DCmode: */
46528 }
46530 tree t;
46534 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
46536 {
46543 /* case SCmode: */
46544 /* case DCmode: */
46550 }
46553 {
46554 /* Parse here processor clause. If not present, default to 'b'. */
46556 }
46558 {
46559 /* If the function isn't exported, we can pick up just one ISA
46560 for the clones. */
46565 else
46568 }
46569 else
46570 {
46573 }
46575 {
46588 }
46590 {
46593 else
46598 }
46600 }
46602 /* Add target attribute to SIMD clone NODE if needed. */
46604 static void
46606 {
46610 {
46625 }
46635 }
46637 /* If SIMD clone NODE can't be used in a vectorized loop
46638 in current function, return -1, otherwise return a badness of using it
46639 (0 if it is most desirable from vecsize_mangle point of view, 1
46640 slightly less desirable, etc.). */
46642 static int
46644 {
46646 {
46664 }
46665 }
46667 /* This function gives out the number of memory references.
46668 This value determines the unrolling factor for
46669 bdver3 and bdver4 architectures. */
46671 static int
46673 {
46675 {
46684 else
46686 }
46688 }
46690 /* This function adjusts the unroll factor based on
46691 the hardware capabilities. For ex, bdver3 has
46692 a loop buffer which makes unrolling of smaller
46693 loops less important. This function decides the
46694 unroll factor using number of memory references
46695 (value 32 is used) as a heuristic. */
46697 static unsigned
46699 {
46701 rtx insn;
46708 /* Count the number of memory references within the loop body. */
46711 {
46715 }
46722 }
46725 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
46727 static bool
46729 {
46730 /* For x87 floating point with standard excess precision handling,
46731 there is no adddf3 pattern (since x87 floating point only has
46732 XFmode operations) so the default hook implementation gets this
46733 wrong. */
46735 }
46737 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
46739 static void
46741 {
46746 {
46761 hold_fnclex);
46775 }
46777 {
46786 mxcsr_orig_var,
46796 ldmxcsr_hold_call);
46799 else
46804 ldmxcsr_clear_call);
46805 else
46809 stxmcsr_update_call);
46811 {
46817 exceptions_assign);
46818 }
46819 else
46824 ldmxcsr_update_call);
46825 }
46826 tree atomic_feraiseexcept
46831 atomic_feraiseexcept_call);
46832 }
46834 /* Initialize the GCC target structure. */
46835 #undef TARGET_RETURN_IN_MEMORY
46836 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
46838 #undef TARGET_LEGITIMIZE_ADDRESS
46839 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
46841 #undef TARGET_ATTRIBUTE_TABLE
46842 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
46843 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
46844 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
46845 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46846 # undef TARGET_MERGE_DECL_ATTRIBUTES
46847 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
46848 #endif
46850 #undef TARGET_COMP_TYPE_ATTRIBUTES
46851 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
46853 #undef TARGET_INIT_BUILTINS
46854 #define TARGET_INIT_BUILTINS ix86_init_builtins
46855 #undef TARGET_BUILTIN_DECL
46856 #define TARGET_BUILTIN_DECL ix86_builtin_decl
46857 #undef TARGET_EXPAND_BUILTIN
46858 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
46860 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
46861 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
46862 ix86_builtin_vectorized_function
46864 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
46865 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
46867 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
46868 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
46870 #undef TARGET_VECTORIZE_BUILTIN_GATHER
46871 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
46873 #undef TARGET_BUILTIN_RECIPROCAL
46874 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
46876 #undef TARGET_ASM_FUNCTION_EPILOGUE
46877 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
46879 #undef TARGET_ENCODE_SECTION_INFO
46880 #ifndef SUBTARGET_ENCODE_SECTION_INFO
46881 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
46882 #else
46883 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
46884 #endif
46886 #undef TARGET_ASM_OPEN_PAREN
46888 #undef TARGET_ASM_CLOSE_PAREN
46891 #undef TARGET_ASM_BYTE_OP
46892 #define TARGET_ASM_BYTE_OP ASM_BYTE
46894 #undef TARGET_ASM_ALIGNED_HI_OP
46895 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
46896 #undef TARGET_ASM_ALIGNED_SI_OP
46897 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
46898 #ifdef ASM_QUAD
46899 #undef TARGET_ASM_ALIGNED_DI_OP
46900 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
46901 #endif
46903 #undef TARGET_PROFILE_BEFORE_PROLOGUE
46904 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
46906 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
46907 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
46909 #undef TARGET_ASM_UNALIGNED_HI_OP
46910 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
46911 #undef TARGET_ASM_UNALIGNED_SI_OP
46912 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
46913 #undef TARGET_ASM_UNALIGNED_DI_OP
46914 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
46916 #undef TARGET_PRINT_OPERAND
46917 #define TARGET_PRINT_OPERAND ix86_print_operand
46918 #undef TARGET_PRINT_OPERAND_ADDRESS
46919 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
46920 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
46921 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
46922 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
46923 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
46925 #undef TARGET_SCHED_INIT_GLOBAL
46926 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
46927 #undef TARGET_SCHED_ADJUST_COST
46928 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
46929 #undef TARGET_SCHED_ISSUE_RATE
46930 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
46931 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
46932 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
46933 ia32_multipass_dfa_lookahead
46934 #undef TARGET_SCHED_MACRO_FUSION_P
46935 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
46936 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
46937 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
46939 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
46940 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
46942 #undef TARGET_MEMMODEL_CHECK
46943 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
46945 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
46946 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
46948 #ifdef HAVE_AS_TLS
46949 #undef TARGET_HAVE_TLS
46950 #define TARGET_HAVE_TLS true
46951 #endif
46952 #undef TARGET_CANNOT_FORCE_CONST_MEM
46953 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
46954 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
46955 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
46957 #undef TARGET_DELEGITIMIZE_ADDRESS
46958 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
46960 #undef TARGET_MS_BITFIELD_LAYOUT_P
46961 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
46963 #if TARGET_MACHO
46964 #undef TARGET_BINDS_LOCAL_P
46965 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
46966 #endif
46967 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46968 #undef TARGET_BINDS_LOCAL_P
46969 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
46970 #endif
46972 #undef TARGET_ASM_OUTPUT_MI_THUNK
46973 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
46974 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
46975 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
46977 #undef TARGET_ASM_FILE_START
46978 #define TARGET_ASM_FILE_START x86_file_start
46980 #undef TARGET_OPTION_OVERRIDE
46981 #define TARGET_OPTION_OVERRIDE ix86_option_override
46983 #undef TARGET_REGISTER_MOVE_COST
46984 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
46985 #undef TARGET_MEMORY_MOVE_COST
46986 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
46987 #undef TARGET_RTX_COSTS
46988 #define TARGET_RTX_COSTS ix86_rtx_costs
46989 #undef TARGET_ADDRESS_COST
46990 #define TARGET_ADDRESS_COST ix86_address_cost
46992 #undef TARGET_FIXED_CONDITION_CODE_REGS
46993 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
46994 #undef TARGET_CC_MODES_COMPATIBLE
46995 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
46997 #undef TARGET_MACHINE_DEPENDENT_REORG
46998 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
47000 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
47001 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
47003 #undef TARGET_BUILD_BUILTIN_VA_LIST
47004 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
47006 #undef TARGET_FOLD_BUILTIN
47007 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
47009 #undef TARGET_COMPARE_VERSION_PRIORITY
47010 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
47012 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
47013 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
47014 ix86_generate_version_dispatcher_body
47016 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
47017 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
47018 ix86_get_function_versions_dispatcher
47020 #undef TARGET_ENUM_VA_LIST_P
47021 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
47023 #undef TARGET_FN_ABI_VA_LIST
47024 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
47026 #undef TARGET_CANONICAL_VA_LIST_TYPE
47027 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
47029 #undef TARGET_EXPAND_BUILTIN_VA_START
47030 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
47032 #undef TARGET_MD_ASM_CLOBBERS
47033 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
47035 #undef TARGET_PROMOTE_PROTOTYPES
47036 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
47037 #undef TARGET_SETUP_INCOMING_VARARGS
47038 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
47039 #undef TARGET_MUST_PASS_IN_STACK
47040 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
47041 #undef TARGET_FUNCTION_ARG_ADVANCE
47042 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
47043 #undef TARGET_FUNCTION_ARG
47044 #define TARGET_FUNCTION_ARG ix86_function_arg
47045 #undef TARGET_FUNCTION_ARG_BOUNDARY
47046 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
47047 #undef TARGET_PASS_BY_REFERENCE
47048 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
47049 #undef TARGET_INTERNAL_ARG_POINTER
47050 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
47051 #undef TARGET_UPDATE_STACK_BOUNDARY
47052 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
47053 #undef TARGET_GET_DRAP_RTX
47054 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
47055 #undef TARGET_STRICT_ARGUMENT_NAMING
47056 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
47057 #undef TARGET_STATIC_CHAIN
47058 #define TARGET_STATIC_CHAIN ix86_static_chain
47059 #undef TARGET_TRAMPOLINE_INIT
47060 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
47061 #undef TARGET_RETURN_POPS_ARGS
47062 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
47064 #undef TARGET_LEGITIMATE_COMBINED_INSN
47065 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
47067 #undef TARGET_ASAN_SHADOW_OFFSET
47068 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
47070 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
47071 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
47073 #undef TARGET_SCALAR_MODE_SUPPORTED_P
47074 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
47076 #undef TARGET_VECTOR_MODE_SUPPORTED_P
47077 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
47079 #undef TARGET_C_MODE_FOR_SUFFIX
47080 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
47082 #ifdef HAVE_AS_TLS
47083 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
47084 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
47085 #endif
47087 #ifdef SUBTARGET_INSERT_ATTRIBUTES
47088 #undef TARGET_INSERT_ATTRIBUTES
47089 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
47090 #endif
47092 #undef TARGET_MANGLE_TYPE
47093 #define TARGET_MANGLE_TYPE ix86_mangle_type
47095 #if !TARGET_MACHO
47096 #undef TARGET_STACK_PROTECT_FAIL
47097 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
47098 #endif
47100 #undef TARGET_FUNCTION_VALUE
47101 #define TARGET_FUNCTION_VALUE ix86_function_value
47103 #undef TARGET_FUNCTION_VALUE_REGNO_P
47104 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
47106 #undef TARGET_PROMOTE_FUNCTION_MODE
47107 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
47109 #undef TARGET_MEMBER_TYPE_FORCES_BLK
47110 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
47112 #undef TARGET_INSTANTIATE_DECLS
47113 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
47115 #undef TARGET_SECONDARY_RELOAD
47116 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
47118 #undef TARGET_CLASS_MAX_NREGS
47119 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
47121 #undef TARGET_PREFERRED_RELOAD_CLASS
47122 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
47123 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
47124 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
47125 #undef TARGET_CLASS_LIKELY_SPILLED_P
47126 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
47128 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
47129 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
47130 ix86_builtin_vectorization_cost
47131 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
47132 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
47133 ix86_vectorize_vec_perm_const_ok
47134 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
47135 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
47136 ix86_preferred_simd_mode
47137 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
47138 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
47139 ix86_autovectorize_vector_sizes
47140 #undef TARGET_VECTORIZE_INIT_COST
47141 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
47142 #undef TARGET_VECTORIZE_ADD_STMT_COST
47143 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
47144 #undef TARGET_VECTORIZE_FINISH_COST
47145 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
47146 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
47147 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
47149 #undef TARGET_SET_CURRENT_FUNCTION
47150 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
47152 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
47153 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
47155 #undef TARGET_OPTION_SAVE
47156 #define TARGET_OPTION_SAVE ix86_function_specific_save
47158 #undef TARGET_OPTION_RESTORE
47159 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
47161 #undef TARGET_OPTION_PRINT
47162 #define TARGET_OPTION_PRINT ix86_function_specific_print
47164 #undef TARGET_OPTION_FUNCTION_VERSIONS
47165 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
47167 #undef TARGET_CAN_INLINE_P
47168 #define TARGET_CAN_INLINE_P ix86_can_inline_p
47170 #undef TARGET_EXPAND_TO_RTL_HOOK
47171 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
47173 #undef TARGET_LEGITIMATE_ADDRESS_P
47174 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
47176 #undef TARGET_LRA_P
47177 #define TARGET_LRA_P hook_bool_void_true
47179 #undef TARGET_REGISTER_PRIORITY
47180 #define TARGET_REGISTER_PRIORITY ix86_register_priority
47182 #undef TARGET_REGISTER_USAGE_LEVELING_P
47183 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
47185 #undef TARGET_LEGITIMATE_CONSTANT_P
47186 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
47188 #undef TARGET_FRAME_POINTER_REQUIRED
47189 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
47191 #undef TARGET_CAN_ELIMINATE
47192 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
47194 #undef TARGET_EXTRA_LIVE_ON_ENTRY
47195 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
47197 #undef TARGET_ASM_CODE_END
47198 #define TARGET_ASM_CODE_END ix86_code_end
47200 #undef TARGET_CONDITIONAL_REGISTER_USAGE
47201 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
47203 #if TARGET_MACHO
47204 #undef TARGET_INIT_LIBFUNCS
47205 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
47206 #endif
47208 #undef TARGET_LOOP_UNROLL_ADJUST
47209 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
47211 #undef TARGET_SPILL_CLASS
47212 #define TARGET_SPILL_CLASS ix86_spill_class
47214 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
47215 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
47216 ix86_simd_clone_compute_vecsize_and_simdlen
47218 #undef TARGET_SIMD_CLONE_ADJUST
47219 #define TARGET_SIMD_CLONE_ADJUST \
47220 ix86_simd_clone_adjust
47222 #undef TARGET_SIMD_CLONE_USABLE
47223 #define TARGET_SIMD_CLONE_USABLE \
47224 ix86_simd_clone_usable
47226 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
47227 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
47228 ix86_float_exceptions_rounding_supported_p
47231 \f