1 /* Subroutines for the gcc driver.
2 Copyright (C) 2006, 2007 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
26 const char *host_detect_local_cpu (int argc
, const char **argv
);
31 /* Returns parameters that describe L1_ASSOC associative cache of size
32 L1_SIZEKB with lines of size L1_LINE. */
35 describe_cache (unsigned l1_sizekb
, unsigned l1_line
,
36 unsigned l1_assoc ATTRIBUTE_UNUSED
, unsigned l2_sizekb
)
38 char size
[100], line
[100], size2
[100];
40 /* At the moment, gcc middle-end does not use the information about the
41 associativity of the cache. */
43 sprintf (size
, "--param l1-cache-size=%u", l1_sizekb
);
44 sprintf (line
, "--param l1-cache-line-size=%u", l1_line
);
45 sprintf (size2
, "--param l2-cache-size=%u", l2_sizekb
);
47 return concat (size
, " ", line
, " ", size2
, " ", NULL
);
51 decode_l2_cache (unsigned *l2_size
, unsigned *l2_line
, unsigned *l2_assoc
)
53 unsigned eax
, ebx
, ecx
, edx
, assoc
;
55 __cpuid (0x80000006, eax
, ebx
, ecx
, edx
);
57 *l2_size
= (ecx
>> 16) & 0xffff;
58 *l2_line
= ecx
& 0xff;
59 assoc
= (ecx
>> 12) & 0xf;
64 else if (assoc
>= 0xa && assoc
<= 0xc)
65 assoc
= 32 + (assoc
- 0xa) * 16;
66 else if (assoc
>= 0xd && assoc
<= 0xe)
67 assoc
= 96 + (assoc
- 0xd) * 32;
71 /* Returns the description of caches for an AMD processor. */
74 detect_caches_amd (unsigned max_ext_level
)
76 unsigned eax
, ebx
, ecx
, edx
;
77 unsigned l1_sizekb
, l1_line
, l1_assoc
;
78 unsigned l2_sizekb
, l2_line
, l2_assoc
;
80 if (max_ext_level
< 0x80000005)
83 __cpuid (0x80000005, eax
, ebx
, ecx
, edx
);
86 l1_sizekb
= (ecx
>> 24) & 0xff;
87 l1_assoc
= (ecx
>> 16) & 0xff;
89 if (max_ext_level
>= 0x80000006)
90 decode_l2_cache (&l2_sizekb
, &l2_line
, &l2_assoc
);
92 return describe_cache (l1_sizekb
, l1_line
, l1_assoc
, l2_sizekb
);
95 /* Stores the size of the L1/2 cache and cache line, and the associativity
96 of the cache according to REG to L1_SIZEKB, L1_LINE, L1_ASSOC and
100 decode_caches_intel (unsigned reg
, unsigned *l1_sizekb
, unsigned *l1_line
,
101 unsigned *l1_assoc
, unsigned *l2_sizekb
,
102 unsigned *l2_line
, unsigned *l2_assoc
)
106 if (((reg
>> 31) & 1) != 0)
109 for (i
= 0; i
< 4; i
++)
283 /* Returns the description of caches for an intel processor. */
286 detect_caches_intel (unsigned max_level
, unsigned max_ext_level
)
288 unsigned eax
, ebx
, ecx
, edx
;
289 unsigned l1_sizekb
= 0, l1_line
= 0, assoc
= 0;
290 unsigned l2_sizekb
= 0, l2_line
= 0, l2_assoc
= 0;
295 __cpuid (2, eax
, ebx
, ecx
, edx
);
297 decode_caches_intel (eax
, &l1_sizekb
, &l1_line
, &assoc
,
298 &l2_sizekb
, &l2_line
, &l2_assoc
);
299 decode_caches_intel (ebx
, &l1_sizekb
, &l1_line
, &assoc
,
300 &l2_sizekb
, &l2_line
, &l2_assoc
);
301 decode_caches_intel (ecx
, &l1_sizekb
, &l1_line
, &assoc
,
302 &l2_sizekb
, &l2_line
, &l2_assoc
);
303 decode_caches_intel (edx
, &l1_sizekb
, &l1_line
, &assoc
,
304 &l2_sizekb
, &l2_line
, &l2_assoc
);
309 /* Newer Intel CPUs are equipped with AMD style L2 cache info */
310 if (max_ext_level
>= 0x80000006)
311 decode_l2_cache (&l2_sizekb
, &l2_line
, &l2_assoc
);
313 return describe_cache (l1_sizekb
, l1_line
, assoc
, l2_sizekb
);
316 /* This will be called by the spec parser in gcc.c when it sees
317 a %:local_cpu_detect(args) construct. Currently it will be called
318 with either "arch" or "tune" as argument depending on if -march=native
319 or -mtune=native is to be substituted.
321 It returns a string containing new command line parameters to be
322 put at the place of the above two options, depending on what CPU
323 this is executed. E.g. "-march=k8" on an AMD64 machine
326 ARGC and ARGV are set depending on the actual arguments given
329 const char *host_detect_local_cpu (int argc
, const char **argv
)
331 enum processor_type processor
= PROCESSOR_I386
;
332 const char *cpu
= "i386";
334 const char *cache
= "";
335 const char *options
= "";
337 unsigned int eax
, ebx
, ecx
, edx
;
339 unsigned int max_level
, ext_level
;
343 unsigned int has_sse3
, has_ssse3
, has_cmpxchg16b
;
344 unsigned int has_cmpxchg8b
, has_cmov
, has_mmx
, has_sse
, has_sse2
;
346 /* Extended features */
347 unsigned int has_lahf_lm
= 0, has_sse4a
= 0;
348 unsigned int has_longmode
= 0, has_3dnowp
= 0, has_3dnow
= 0;
355 arch
= !strcmp (argv
[0], "arch");
357 if (!arch
&& strcmp (argv
[0], "tune"))
360 max_level
= __get_cpuid_max (0, &vendor
);
364 __cpuid (1, eax
, ebx
, ecx
, edx
);
366 /* We don't care for extended family. */
367 family
= (eax
>> 8) & 0x0f;
369 has_sse3
= ecx
& bit_SSE3
;
370 has_ssse3
= ecx
& bit_SSSE3
;
371 has_cmpxchg16b
= ecx
& bit_CMPXCHG16B
;
373 has_cmpxchg8b
= edx
& bit_CMPXCHG8B
;
374 has_cmov
= edx
& bit_CMOV
;
375 has_mmx
= edx
& bit_MMX
;
376 has_sse
= edx
& bit_SSE
;
377 has_sse2
= edx
& bit_SSE2
;
379 /* Check cpuid level of extended features. */
380 __cpuid (0x80000000, ext_level
, ebx
, ecx
, edx
);
382 if (ext_level
> 0x80000000)
384 __cpuid (0x80000001, eax
, ebx
, ecx
, edx
);
386 has_lahf_lm
= ecx
& bit_LAHF_LM
;
387 has_sse4a
= ecx
& bit_SSE4a
;
389 has_longmode
= edx
& bit_LM
;
390 has_3dnowp
= edx
& bit_3DNOWP
;
391 has_3dnow
= edx
& bit_3DNOW
;
396 if (vendor
== *(const unsigned int*) "Auth")
397 cache
= detect_caches_amd (ext_level
);
398 else if (vendor
== *(const unsigned int*) "Genu")
399 cache
= detect_caches_intel (max_level
, ext_level
);
402 if (vendor
== *(const unsigned int*) "Auth")
404 processor
= PROCESSOR_PENTIUM
;
407 processor
= PROCESSOR_K6
;
409 processor
= PROCESSOR_ATHLON
;
410 if (has_sse2
|| has_longmode
)
411 processor
= PROCESSOR_K8
;
413 processor
= PROCESSOR_AMDFAM10
;
415 else if (vendor
== *(const unsigned int*) "Geod")
416 processor
= PROCESSOR_GEODE
;
422 processor
= PROCESSOR_I486
;
425 processor
= PROCESSOR_PENTIUM
;
428 processor
= PROCESSOR_PENTIUMPRO
;
431 processor
= PROCESSOR_PENTIUM4
;
434 /* We have no idea. */
435 processor
= PROCESSOR_GENERIC32
;
447 case PROCESSOR_PENTIUM
:
453 case PROCESSOR_PENTIUMPRO
:
455 /* It is Core 2 Duo. */
460 /* It is Core Duo. */
463 /* It is Pentium M. */
466 /* It is Pentium III. */
469 /* It is Pentium II. */
472 /* Default to Pentium Pro. */
476 /* For -mtune, we default to -mtune=generic. */
479 case PROCESSOR_PENTIUM4
:
490 case PROCESSOR_GEODE
:
494 if (arch
&& has_3dnow
)
499 case PROCESSOR_ATHLON
:
506 if (arch
&& has_sse3
)
511 case PROCESSOR_AMDFAM10
:
516 /* Use something reasonable. */
534 else if (has_cmpxchg8b
)
544 options
= concat (options
, "-mcx16 ", NULL
);
546 options
= concat (options
, "-msahf ", NULL
);
550 return concat (cache
, "-m", argv
[0], "=", cpu
, " ", options
, NULL
);
554 /* If we aren't compiling with GCC we just provide a minimal
557 const char *host_detect_local_cpu (int argc
, const char **argv
)
565 arch
= !strcmp (argv
[0], "arch");
567 if (!arch
&& strcmp (argv
[0], "tune"))
572 /* FIXME: i386 is wrong for 64bit compiler. How can we tell if
573 we are generating 64bit or 32bit code? */
579 return concat ("-m", argv
[0], "=", cpu
, NULL
);
581 #endif /* __GNUC__ */