1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005-2014 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return 1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return 1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return 1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return 1 if op is an Altivec register.
35 (define_predicate "altivec_register_operand"
36 (match_operand 0 "register_operand")
38 if (GET_CODE (op) == SUBREG)
44 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
47 return ALTIVEC_REGNO_P (REGNO (op));
50 ;; Return 1 if op is a VSX register.
51 (define_predicate "vsx_register_operand"
52 (match_operand 0 "register_operand")
54 if (GET_CODE (op) == SUBREG)
60 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
63 return VSX_REGNO_P (REGNO (op));
66 ;; Return 1 if op is a vector register that operates on floating point vectors
67 ;; (either altivec or VSX).
68 (define_predicate "vfloat_operand"
69 (match_operand 0 "register_operand")
71 if (GET_CODE (op) == SUBREG)
77 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
80 return VFLOAT_REGNO_P (REGNO (op));
83 ;; Return 1 if op is a vector register that operates on integer vectors
84 ;; (only altivec, VSX doesn't support integer vectors)
85 (define_predicate "vint_operand"
86 (match_operand 0 "register_operand")
88 if (GET_CODE (op) == SUBREG)
94 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
97 return VINT_REGNO_P (REGNO (op));
100 ;; Return 1 if op is a vector register to do logical operations on (and, or,
102 (define_predicate "vlogical_operand"
103 (match_operand 0 "register_operand")
105 if (GET_CODE (op) == SUBREG)
106 op = SUBREG_REG (op);
111 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
114 return VLOGICAL_REGNO_P (REGNO (op));
117 ;; Return 1 if op is the carry register.
118 (define_predicate "ca_operand"
119 (and (match_code "reg")
120 (match_test "CA_REGNO_P (REGNO (op))")))
122 ;; Return 1 if op is a signed 5-bit constant integer.
123 (define_predicate "s5bit_cint_operand"
124 (and (match_code "const_int")
125 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
127 ;; Return 1 if op is a unsigned 3-bit constant integer.
128 (define_predicate "u3bit_cint_operand"
129 (and (match_code "const_int")
130 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
132 ;; Return 1 if op is a unsigned 5-bit constant integer.
133 (define_predicate "u5bit_cint_operand"
134 (and (match_code "const_int")
135 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
137 ;; Return 1 if op is a signed 8-bit constant integer.
138 ;; Integer multiplication complete more quickly
139 (define_predicate "s8bit_cint_operand"
140 (and (match_code "const_int")
141 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
143 ;; Return 1 if op is a unsigned 10-bit constant integer.
144 (define_predicate "u10bit_cint_operand"
145 (and (match_code "const_int")
146 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023")))
148 ;; Return 1 if op is a constant integer that can fit in a D field.
149 (define_predicate "short_cint_operand"
150 (and (match_code "const_int")
151 (match_test "satisfies_constraint_I (op)")))
153 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
154 (define_predicate "u_short_cint_operand"
155 (and (match_code "const_int")
156 (match_test "satisfies_constraint_K (op)")))
158 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
159 (define_predicate "non_short_cint_operand"
160 (and (match_code "const_int")
161 (match_test "(unsigned HOST_WIDE_INT)
162 (INTVAL (op) + 0x8000) >= 0x10000")))
164 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
165 (define_predicate "exact_log2_cint_operand"
166 (and (match_code "const_int")
167 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
169 ;; Match op = 0 or op = 1.
170 (define_predicate "const_0_to_1_operand"
171 (and (match_code "const_int")
172 (match_test "IN_RANGE (INTVAL (op), 0, 1)")))
174 ;; Match op = 2 or op = 3.
175 (define_predicate "const_2_to_3_operand"
176 (and (match_code "const_int")
177 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
180 (define_predicate "const_0_to_15_operand"
181 (and (match_code "const_int")
182 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
184 ;; Return 1 if op is a register that is not special.
185 (define_predicate "gpc_reg_operand"
186 (match_operand 0 "register_operand")
188 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
191 if (GET_CODE (op) == SUBREG)
192 op = SUBREG_REG (op);
197 if (REGNO (op) >= ARG_POINTER_REGNUM && !CA_REGNO_P (REGNO (op)))
200 if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))
203 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
206 ;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't
207 ;; allow floating point or vector registers.
208 (define_predicate "int_reg_operand"
209 (match_operand 0 "register_operand")
211 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
214 if (GET_CODE (op) == SUBREG)
215 op = SUBREG_REG (op);
220 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
223 return INT_REGNO_P (REGNO (op));
226 ;; Like int_reg_operand, but only return true for base registers
227 (define_predicate "base_reg_operand"
228 (match_operand 0 "int_reg_operand")
230 if (GET_CODE (op) == SUBREG)
231 op = SUBREG_REG (op);
236 return (REGNO (op) != FIRST_GPR_REGNO);
239 ;; Return 1 if op is a HTM specific SPR register.
240 (define_predicate "htm_spr_reg_operand"
241 (match_operand 0 "register_operand")
246 if (GET_CODE (op) == SUBREG)
247 op = SUBREG_REG (op);
266 ;; Return 1 if op is a general purpose register that is an even register
267 ;; which suitable for a load/store quad operation
268 (define_predicate "quad_int_reg_operand"
269 (match_operand 0 "register_operand")
273 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)
276 if (GET_CODE (op) == SUBREG)
277 op = SUBREG_REG (op);
283 if (r >= FIRST_PSEUDO_REGISTER)
286 return (INT_REGNO_P (r) && ((r & 1) == 0));
289 ;; Return 1 if op is a register that is a condition register field.
290 (define_predicate "cc_reg_operand"
291 (match_operand 0 "register_operand")
293 if (GET_CODE (op) == SUBREG)
294 op = SUBREG_REG (op);
299 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
302 return CR_REGNO_P (REGNO (op));
305 ;; Return 1 if op is a register that is a condition register field not cr0.
306 (define_predicate "cc_reg_not_cr0_operand"
307 (match_operand 0 "register_operand")
309 if (GET_CODE (op) == SUBREG)
310 op = SUBREG_REG (op);
315 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
318 return CR_REGNO_NOT_CR0_P (REGNO (op));
321 ;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0.
322 (define_predicate "cc_reg_not_micro_cr0_operand"
323 (match_operand 0 "register_operand")
325 if (GET_CODE (op) == SUBREG)
326 op = SUBREG_REG (op);
331 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
334 if (rs6000_gen_cell_microcode)
335 return CR_REGNO_NOT_CR0_P (REGNO (op));
337 return CR_REGNO_P (REGNO (op));
340 ;; Return 1 if op is a constant integer valid for D field
341 ;; or non-special register register.
342 (define_predicate "reg_or_short_operand"
343 (if_then_else (match_code "const_int")
344 (match_operand 0 "short_cint_operand")
345 (match_operand 0 "gpc_reg_operand")))
347 ;; Return 1 if op is a constant integer valid whose negation is valid for
348 ;; D field or non-special register register.
349 ;; Do not allow a constant zero because all patterns that call this
350 ;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than
351 ;; or equal to const, which does not work for zero.
352 (define_predicate "reg_or_neg_short_operand"
353 (if_then_else (match_code "const_int")
354 (match_test "satisfies_constraint_P (op)
355 && INTVAL (op) != 0")
356 (match_operand 0 "gpc_reg_operand")))
358 ;; Return 1 if op is a constant integer valid for DS field
359 ;; or non-special register.
360 (define_predicate "reg_or_aligned_short_operand"
361 (if_then_else (match_code "const_int")
362 (and (match_operand 0 "short_cint_operand")
363 (match_test "!(INTVAL (op) & 3)"))
364 (match_operand 0 "gpc_reg_operand")))
366 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
367 ;; or non-special register.
368 (define_predicate "reg_or_u_short_operand"
369 (if_then_else (match_code "const_int")
370 (match_operand 0 "u_short_cint_operand")
371 (match_operand 0 "gpc_reg_operand")))
373 ;; Return 1 if op is any constant integer
374 ;; or non-special register.
375 (define_predicate "reg_or_cint_operand"
376 (ior (match_code "const_int")
377 (match_operand 0 "gpc_reg_operand")))
379 ;; Return 1 if op is a constant integer valid for addition with addis, addi.
380 (define_predicate "add_cint_operand"
381 (and (match_code "const_int")
382 (match_test "(unsigned HOST_WIDE_INT)
383 (INTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000))
384 < (unsigned HOST_WIDE_INT) 0x100000000ll")))
386 ;; Return 1 if op is a constant integer valid for addition
387 ;; or non-special register.
388 (define_predicate "reg_or_add_cint_operand"
389 (if_then_else (match_code "const_int")
390 (match_operand 0 "add_cint_operand")
391 (match_operand 0 "gpc_reg_operand")))
393 ;; Return 1 if op is a constant integer valid for subtraction
394 ;; or non-special register.
395 (define_predicate "reg_or_sub_cint_operand"
396 (if_then_else (match_code "const_int")
397 (match_test "(unsigned HOST_WIDE_INT)
398 (- INTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000))
399 < (unsigned HOST_WIDE_INT) 0x100000000ll")
400 (match_operand 0 "gpc_reg_operand")))
402 ;; Return 1 if op is any 32-bit unsigned constant integer
403 ;; or non-special register.
404 (define_predicate "reg_or_logical_cint_operand"
405 (if_then_else (match_code "const_int")
406 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
408 || ((INTVAL (op) & GET_MODE_MASK (mode)
409 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
410 (match_operand 0 "gpc_reg_operand")))
412 ;; Like reg_or_logical_cint_operand, but allow vsx registers
413 (define_predicate "vsx_reg_or_cint_operand"
414 (ior (match_operand 0 "vsx_register_operand")
415 (match_operand 0 "reg_or_logical_cint_operand")))
417 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
418 ;; with no more than one instruction per word.
419 (define_predicate "easy_fp_constant"
420 (match_code "const_double")
425 if (GET_MODE (op) != mode
426 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
429 /* Consider all constants with -msoft-float to be easy. */
430 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
431 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
435 /* The constant 0.0 is easy under VSX. */
436 if ((mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode)
437 && VECTOR_UNIT_VSX_P (DFmode) && op == CONST0_RTX (mode))
440 if (DECIMAL_FLOAT_MODE_P (mode))
443 /* If we are using V.4 style PIC, consider all constants to be hard. */
444 if (flag_pic && DEFAULT_ABI == ABI_V4)
447 #ifdef TARGET_RELOCATABLE
448 /* Similarly if we are using -mrelocatable, consider all constants
450 if (TARGET_RELOCATABLE)
457 if (TARGET_E500_DOUBLE)
460 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
461 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
463 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
464 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
465 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
466 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
469 /* The constant 0.f is easy under VSX. */
470 if (op == CONST0_RTX (DFmode) && VECTOR_UNIT_VSX_P (DFmode))
473 /* Force constants to memory before reload to utilize
474 compress_float_constant.
475 Avoid this when flag_unsafe_math_optimizations is enabled
476 because RDIV division to reciprocal optimization is not able
477 to regenerate the division. */
478 if (TARGET_E500_DOUBLE
479 || (!reload_in_progress && !reload_completed
480 && !flag_unsafe_math_optimizations))
483 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
484 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
486 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
487 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
490 /* The constant 0.f is easy. */
491 if (op == CONST0_RTX (SFmode))
494 /* Force constants to memory before reload to utilize
495 compress_float_constant.
496 Avoid this when flag_unsafe_math_optimizations is enabled
497 because RDIV division to reciprocal optimization is not able
498 to regenerate the division. */
499 if (!reload_in_progress && !reload_completed
500 && !flag_unsafe_math_optimizations)
503 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
504 REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]);
506 return num_insns_constant_wide (k[0]) == 1;
509 return (num_insns_constant (op, DImode) <= 2);
519 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
520 ;; vector register without using memory.
521 (define_predicate "easy_vector_constant"
522 (match_code "const_vector")
524 /* As the paired vectors are actually FPRs it seems that there is
525 no easy way to load a CONST_VECTOR without using memory. */
526 if (TARGET_PAIRED_FLOAT)
529 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
531 if (zero_constant (op, mode))
534 return easy_altivec_constant (op, mode);
537 if (SPE_VECTOR_MODE (mode))
540 if (zero_constant (op, mode))
542 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
545 /* Limit SPE vectors to 15 bits signed. These we can generate with:
550 I don't know how efficient it would be to allow bigger constants,
551 considering we'll have an extra 'ori' for every 'li'. I doubt 5
552 instructions is better than a 64-bit memory load, but I don't
553 have the e500 timing specs. */
554 if (mode == V2SImode)
556 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
557 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
558 return cst >= -0x7fff && cst <= 0x7fff
559 && cst2 >= -0x7fff && cst2 <= 0x7fff;
566 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
567 (define_predicate "easy_vector_constant_add_self"
568 (and (match_code "const_vector")
569 (and (match_test "TARGET_ALTIVEC")
570 (match_test "easy_altivec_constant (op, mode)")))
574 if (mode == V2DImode || mode == V2DFmode)
576 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
577 val = const_vector_elt_as_int (op, elt);
578 val = ((val & 0xff) ^ 0x80) - 0x80;
579 return EASY_VECTOR_15_ADD_SELF (val);
582 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
583 (define_predicate "easy_vector_constant_msb"
584 (and (match_code "const_vector")
585 (and (match_test "TARGET_ALTIVEC")
586 (match_test "easy_altivec_constant (op, mode)")))
590 if (mode == V2DImode || mode == V2DFmode)
592 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
593 val = const_vector_elt_as_int (op, elt);
594 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
597 ;; Return 1 if operand is constant zero (scalars and vectors).
598 (define_predicate "zero_constant"
599 (and (match_code "const_int,const_double,const_vector")
600 (match_test "op == CONST0_RTX (mode)")))
602 ;; Return 1 if operand is 0.0.
603 (define_predicate "zero_fp_constant"
604 (and (match_code "const_double")
605 (match_test "SCALAR_FLOAT_MODE_P (mode)
606 && op == CONST0_RTX (mode)")))
608 ;; Return 1 if the operand is in volatile memory. Note that during the
609 ;; RTL generation phase, memory_operand does not return TRUE for volatile
610 ;; memory references. So this function allows us to recognize volatile
611 ;; references where it's safe.
612 (define_predicate "volatile_mem_operand"
613 (and (and (match_code "mem")
614 (match_test "MEM_VOLATILE_P (op)"))
615 (if_then_else (match_test "reload_completed")
616 (match_operand 0 "memory_operand")
617 (if_then_else (match_test "reload_in_progress")
618 (match_test "strict_memory_address_p (mode, XEXP (op, 0))")
619 (match_test "memory_address_p (mode, XEXP (op, 0))")))))
621 ;; Return 1 if the operand is an offsettable memory operand.
622 (define_predicate "offsettable_mem_operand"
623 (and (match_operand 0 "memory_operand")
624 (match_test "offsettable_nonstrict_memref_p (op)")))
626 ;; Return 1 if the operand is suitable for load/store quad memory.
627 ;; This predicate only checks for non-atomic loads/stores.
628 (define_predicate "quad_memory_operand"
634 if (!TARGET_QUAD_MEMORY)
637 else if (!memory_operand (op, mode))
640 else if (GET_MODE_SIZE (GET_MODE (op)) != 16)
643 else if (MEM_ALIGN (op) < 128)
649 if (int_reg_operand (addr, Pmode))
652 else if (GET_CODE (addr) != PLUS)
657 op0 = XEXP (addr, 0);
658 op1 = XEXP (addr, 1);
659 ret = (int_reg_operand (op0, Pmode)
660 && GET_CODE (op1) == CONST_INT
661 && IN_RANGE (INTVAL (op1), -32768, 32767)
662 && (INTVAL (op1) & 15) == 0);
666 if (TARGET_DEBUG_ADDR)
668 fprintf (stderr, "\nquad_memory_operand, ret = %s\n", ret ? "true" : "false");
675 ;; Return 1 if the operand is an indexed or indirect memory operand.
676 (define_predicate "indexed_or_indirect_operand"
680 if (VECTOR_MEM_ALTIVEC_P (mode)
681 && GET_CODE (op) == AND
682 && GET_CODE (XEXP (op, 1)) == CONST_INT
683 && INTVAL (XEXP (op, 1)) == -16)
686 return indexed_or_indirect_address (op, mode);
689 ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
690 ;; moves are supported.
691 (define_predicate "reg_or_indexed_operand"
692 (match_code "mem,reg")
695 return indexed_or_indirect_operand (op, mode);
696 else if (TARGET_DIRECT_MOVE)
697 return register_operand (op, mode);
702 ;; Return 1 if the operand is an indexed or indirect memory operand with an
703 ;; AND -16 in it, used to recognize when we need to switch to Altivec loads
704 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
705 ;; while VSX uses the full address and traps)
706 (define_predicate "altivec_indexed_or_indirect_operand"
710 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
711 && GET_CODE (op) == AND
712 && GET_CODE (XEXP (op, 1)) == CONST_INT
713 && INTVAL (XEXP (op, 1)) == -16)
714 return indexed_or_indirect_address (XEXP (op, 0), mode);
719 ;; Return 1 if the operand is an indexed or indirect address.
720 (define_special_predicate "indexed_or_indirect_address"
721 (and (match_test "REG_P (op)
722 || (GET_CODE (op) == PLUS
723 /* Omit testing REG_P (XEXP (op, 0)). */
724 && REG_P (XEXP (op, 1)))")
725 (match_operand 0 "address_operand")))
727 ;; Return 1 if the operand is an index-form address.
728 (define_special_predicate "indexed_address"
729 (match_test "(GET_CODE (op) == PLUS
730 && REG_P (XEXP (op, 0))
731 && REG_P (XEXP (op, 1)))"))
733 ;; Return 1 if the operand is a MEM with an update-form address. This may
734 ;; also include update-indexed form.
735 (define_special_predicate "update_address_mem"
736 (match_test "(MEM_P (op)
737 && (GET_CODE (XEXP (op, 0)) == PRE_INC
738 || GET_CODE (XEXP (op, 0)) == PRE_DEC
739 || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))"))
741 ;; Return 1 if the operand is a MEM with an update-indexed-form address. Note
742 ;; that PRE_INC/PRE_DEC will always be non-indexed (i.e. non X-form) since the
743 ;; increment is based on the mode size and will therefor always be a const.
744 (define_special_predicate "update_indexed_address_mem"
745 (match_test "(MEM_P (op)
746 && GET_CODE (XEXP (op, 0)) == PRE_MODIFY
747 && indexed_address (XEXP (XEXP (op, 0), 1), mode))"))
749 ;; Used for the destination of the fix_truncdfsi2 expander.
750 ;; If stfiwx will be used, the result goes to memory; otherwise,
751 ;; we're going to emit a store and a load of a subreg, so the dest is a
753 (define_predicate "fix_trunc_dest_operand"
754 (if_then_else (match_test "! TARGET_E500_DOUBLE && TARGET_PPC_GFXOPT")
755 (match_operand 0 "memory_operand")
756 (match_operand 0 "gpc_reg_operand")))
758 ;; Return 1 if the operand is either a non-special register or can be used
759 ;; as the operand of a `mode' add insn.
760 (define_predicate "add_operand"
761 (if_then_else (match_code "const_int")
762 (match_test "satisfies_constraint_I (op)
763 || satisfies_constraint_L (op)")
764 (match_operand 0 "gpc_reg_operand")))
766 ;; Return 1 if OP is a constant but not a valid add_operand.
767 (define_predicate "non_add_cint_operand"
768 (and (match_code "const_int")
769 (match_test "!satisfies_constraint_I (op)
770 && !satisfies_constraint_L (op)")))
772 ;; Return 1 if the operand is a constant that can be used as the operand
774 (define_predicate "logical_const_operand"
775 (match_code "const_int")
779 opl = INTVAL (op) & GET_MODE_MASK (mode);
781 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
782 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
785 ;; Return 1 if the operand is a non-special register or a constant that
786 ;; can be used as the operand of an OR or XOR.
787 (define_predicate "logical_operand"
788 (ior (match_operand 0 "gpc_reg_operand")
789 (match_operand 0 "logical_const_operand")))
791 ;; Return 1 if op is a constant that is not a logical operand, but could
792 ;; be split into one.
793 (define_predicate "non_logical_cint_operand"
794 (and (match_code "const_int,const_double")
795 (and (not (match_operand 0 "logical_operand"))
796 (match_operand 0 "reg_or_logical_cint_operand"))))
798 ;; Return 1 if op is a constant that can be encoded in a 32-bit mask,
799 ;; suitable for use with rlwinm (no more than two 1->0 or 0->1
800 ;; transitions). Reject all ones and all zeros, since these should have
801 ;; been optimized away and confuse the making of MB and ME.
802 (define_predicate "mask_operand"
803 (match_code "const_int")
805 HOST_WIDE_INT c, lsb;
809 if (TARGET_POWERPC64)
811 /* Fail if the mask is not 32-bit. */
812 if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0)
815 /* Fail if the mask wraps around because the upper 32-bits of the
816 mask will all be 1s, contrary to GCC's internal view. */
817 if ((c & 0x80000001) == 0x80000001)
821 /* We don't change the number of transitions by inverting,
822 so make sure we start with the LS bit zero. */
826 /* Reject all zeros or all ones. */
830 /* Find the first transition. */
833 /* Invert to look for a second transition. */
836 /* Erase first transition. */
839 /* Find the second transition (if any). */
842 /* Match if all the bits above are 1's (or c is zero). */
846 ;; Return 1 for the PowerPC64 rlwinm corner case.
847 (define_predicate "mask_operand_wrap"
848 (match_code "const_int")
850 HOST_WIDE_INT c, lsb;
854 if ((c & 0x80000001) != 0x80000001)
868 ;; Return 1 if the operand is a constant that is a PowerPC64 mask
869 ;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1
870 ;; transition). Reject all zeros, since zero should have been
871 ;; optimized away and confuses the making of MB and ME.
872 (define_predicate "mask64_operand"
873 (match_code "const_int")
875 HOST_WIDE_INT c, lsb;
879 /* Reject all zeros. */
883 /* We don't change the number of transitions by inverting,
884 so make sure we start with the LS bit zero. */
888 /* Find the first transition. */
891 /* Match if all the bits above are 1's (or c is zero). */
895 ;; Like mask64_operand, but allow up to three transitions. This
896 ;; predicate is used by insn patterns that generate two rldicl or
897 ;; rldicr machine insns.
898 (define_predicate "mask64_2_operand"
899 (match_code "const_int")
901 HOST_WIDE_INT c, lsb;
905 /* Disallow all zeros. */
909 /* We don't change the number of transitions by inverting,
910 so make sure we start with the LS bit zero. */
914 /* Find the first transition. */
917 /* Invert to look for a second transition. */
920 /* Erase first transition. */
923 /* Find the second transition. */
926 /* Invert to look for a third transition. */
929 /* Erase second transition. */
932 /* Find the third transition (if any). */
935 /* Match if all the bits above are 1's (or c is zero). */
939 ;; Like and_operand, but also match constants that can be implemented
940 ;; with two rldicl or rldicr insns.
941 (define_predicate "and64_2_operand"
942 (ior (match_operand 0 "mask64_2_operand")
943 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
944 (match_operand 0 "gpc_reg_operand")
945 (match_operand 0 "logical_operand"))))
947 ;; Return 1 if the operand is either a non-special register or a
948 ;; constant that can be used as the operand of a logical AND.
949 (define_predicate "and_operand"
950 (ior (match_operand 0 "mask_operand")
951 (ior (and (match_test "TARGET_POWERPC64 && mode == DImode")
952 (match_operand 0 "mask64_operand"))
953 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
954 (match_operand 0 "gpc_reg_operand")
955 (match_operand 0 "logical_operand")))))
957 ;; Return 1 if the operand is either a logical operand or a short cint operand.
958 (define_predicate "scc_eq_operand"
959 (ior (match_operand 0 "logical_operand")
960 (match_operand 0 "short_cint_operand")))
962 ;; Return 1 if the operand is a general non-special register or memory operand.
963 (define_predicate "reg_or_mem_operand"
964 (ior (match_operand 0 "memory_operand")
965 (ior (and (match_code "mem")
966 (match_test "macho_lo_sum_memory_operand (op, mode)"))
967 (ior (match_operand 0 "volatile_mem_operand")
968 (match_operand 0 "gpc_reg_operand")))))
970 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
971 (define_predicate "reg_or_none500mem_operand"
972 (if_then_else (match_code "mem")
973 (and (match_test "!TARGET_E500_DOUBLE")
974 (ior (match_operand 0 "memory_operand")
975 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
976 (match_operand 0 "volatile_mem_operand"))))
977 (match_operand 0 "gpc_reg_operand")))
979 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
980 (define_predicate "zero_reg_mem_operand"
981 (ior (match_operand 0 "zero_fp_constant")
982 (match_operand 0 "reg_or_mem_operand")))
984 ;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit
985 ;; data types inside of a vector that scalar instructions operate on
986 (define_predicate "vsx_scalar_64bit"
987 (match_code "const_int")
989 return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT);
992 ;; Return 1 if the operand is a general register or memory operand without
993 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
995 (define_predicate "lwa_operand"
996 (match_code "reg,subreg,mem")
998 rtx inner, addr, offset;
1001 if (reload_completed && GET_CODE (inner) == SUBREG)
1002 inner = SUBREG_REG (inner);
1004 if (gpc_reg_operand (inner, mode))
1006 if (!memory_operand (inner, mode))
1008 addr = XEXP (inner, 0);
1009 if (GET_CODE (addr) == PRE_INC
1010 || GET_CODE (addr) == PRE_DEC
1011 || (GET_CODE (addr) == PRE_MODIFY
1012 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
1014 if (GET_CODE (addr) == LO_SUM
1015 && GET_CODE (XEXP (addr, 0)) == REG
1016 && GET_CODE (XEXP (addr, 1)) == CONST)
1017 addr = XEXP (XEXP (addr, 1), 0);
1018 if (GET_CODE (addr) != PLUS)
1020 offset = XEXP (addr, 1);
1021 if (GET_CODE (offset) != CONST_INT)
1023 return INTVAL (offset) % 4 == 0;
1026 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
1027 (define_predicate "symbol_ref_operand"
1028 (and (match_code "symbol_ref")
1029 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
1030 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
1032 ;; Return 1 if op is an operand that can be loaded via the GOT.
1033 ;; or non-special register register field no cr0
1034 (define_predicate "got_operand"
1035 (match_code "symbol_ref,const,label_ref"))
1037 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
1038 ;; excluding labels involving addition.
1039 (define_predicate "got_no_const_operand"
1040 (match_code "symbol_ref,label_ref"))
1042 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
1043 (define_predicate "rs6000_tls_symbol_ref"
1044 (and (match_code "symbol_ref")
1045 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
1047 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
1048 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
1049 (define_predicate "call_operand"
1050 (if_then_else (match_code "reg")
1051 (match_test "REGNO (op) == LR_REGNO
1052 || REGNO (op) == CTR_REGNO
1053 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
1054 (match_code "symbol_ref")))
1056 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
1058 (define_predicate "current_file_function_operand"
1059 (and (match_code "symbol_ref")
1060 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
1061 && ((SYMBOL_REF_LOCAL_P (op)
1062 && ((DEFAULT_ABI != ABI_AIX
1063 && DEFAULT_ABI != ABI_ELFv2)
1064 || !SYMBOL_REF_EXTERNAL_P (op)))
1065 || (op == XEXP (DECL_RTL (current_function_decl),
1068 ;; Return 1 if this operand is a valid input for a move insn.
1069 (define_predicate "input_operand"
1070 (match_code "symbol_ref,const,reg,subreg,mem,
1071 const_double,const_vector,const_int")
1073 /* Memory is always valid. */
1074 if (memory_operand (op, mode))
1077 /* For floating-point, easy constants are valid. */
1078 if (SCALAR_FLOAT_MODE_P (mode)
1079 && easy_fp_constant (op, mode))
1082 /* Allow any integer constant. */
1083 if (GET_MODE_CLASS (mode) == MODE_INT
1084 && (GET_CODE (op) == CONST_INT
1085 || GET_CODE (op) == CONST_DOUBLE))
1088 /* Allow easy vector constants. */
1089 if (GET_CODE (op) == CONST_VECTOR
1090 && easy_vector_constant (op, mode))
1093 /* Do not allow invalid E500 subregs. */
1094 if ((TARGET_E500_DOUBLE || TARGET_SPE)
1095 && GET_CODE (op) == SUBREG
1096 && invalid_e500_subreg (op, mode))
1099 /* For floating-point or multi-word mode, the only remaining valid type
1101 if (SCALAR_FLOAT_MODE_P (mode)
1102 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1103 return register_operand (op, mode);
1105 /* The only cases left are integral modes one word or smaller (we
1106 do not get called for MODE_CC values). These can be in any
1108 if (register_operand (op, mode))
1111 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1113 if (DEFAULT_ABI == ABI_V4
1114 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
1115 && small_data_operand (op, Pmode))
1121 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
1122 (define_predicate "splat_input_operand"
1123 (match_code "symbol_ref,const,reg,subreg,mem,
1124 const_double,const_vector,const_int")
1128 if (! volatile_ok && MEM_VOLATILE_P (op))
1132 else if (mode == DImode)
1136 return memory_address_addr_space_p (mode, XEXP (op, 0),
1137 MEM_ADDR_SPACE (op));
1139 return input_operand (op, mode);
1142 ;; Return true if OP is a non-immediate operand and not an invalid
1143 ;; SUBREG operation on the e500.
1144 (define_predicate "rs6000_nonimmediate_operand"
1145 (match_code "reg,subreg,mem")
1147 if ((TARGET_E500_DOUBLE || TARGET_SPE)
1148 && GET_CODE (op) == SUBREG
1149 && invalid_e500_subreg (op, mode))
1152 return nonimmediate_operand (op, mode);
1155 ;; Return true if operand is boolean operator.
1156 (define_predicate "boolean_operator"
1157 (match_code "and,ior,xor"))
1159 ;; Return true if operand is OR-form of boolean operator.
1160 (define_predicate "boolean_or_operator"
1161 (match_code "ior,xor"))
1163 ;; Return true if operand is an equality operator.
1164 (define_special_predicate "equality_operator"
1165 (match_code "eq,ne"))
1167 ;; Return true if operand is MIN or MAX operator.
1168 (define_predicate "min_max_operator"
1169 (match_code "smin,smax,umin,umax"))
1171 ;; Return 1 if OP is a comparison operation that is valid for a branch
1172 ;; instruction. We check the opcode against the mode of the CC value.
1173 ;; validate_condition_mode is an assertion.
1174 (define_predicate "branch_comparison_operator"
1175 (and (match_operand 0 "comparison_operator")
1176 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
1177 (match_test "validate_condition_mode (GET_CODE (op),
1178 GET_MODE (XEXP (op, 0))),
1181 ;; Return 1 if OP is a valid comparison operator for "cbranch" instructions.
1182 ;; If we're assuming that FP operations cannot generate user-visible traps,
1183 ;; then on e500 we can use the ordered-signaling instructions to implement
1184 ;; the unordered-quiet FP comparison predicates modulo a reversal.
1185 (define_predicate "rs6000_cbranch_operator"
1186 (if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS")
1187 (if_then_else (match_test "flag_trapping_math")
1188 (match_operand 0 "ordered_comparison_operator")
1189 (ior (match_operand 0 "ordered_comparison_operator")
1190 (match_code ("unlt,unle,ungt,unge"))))
1191 (match_operand 0 "comparison_operator")))
1193 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
1194 ;; it must be a positive comparison.
1195 (define_predicate "scc_comparison_operator"
1196 (and (match_operand 0 "branch_comparison_operator")
1197 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1199 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
1201 (define_predicate "scc_rev_comparison_operator"
1202 (and (match_operand 0 "branch_comparison_operator")
1203 (match_code "ne,le,ge,leu,geu,ordered")))
1205 ;; Return 1 if OP is a comparison operation that is valid for a branch
1206 ;; insn, which is true if the corresponding bit in the CC register is set.
1207 (define_predicate "branch_positive_comparison_operator"
1208 (and (match_operand 0 "branch_comparison_operator")
1209 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1211 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
1212 (define_predicate "load_multiple_operation"
1213 (match_code "parallel")
1215 int count = XVECLEN (op, 0);
1216 unsigned int dest_regno;
1220 /* Perform a quick check so we don't blow up below. */
1222 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1223 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1224 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1227 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1228 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1230 for (i = 1; i < count; i++)
1232 rtx elt = XVECEXP (op, 0, i);
1234 if (GET_CODE (elt) != SET
1235 || GET_CODE (SET_DEST (elt)) != REG
1236 || GET_MODE (SET_DEST (elt)) != SImode
1237 || REGNO (SET_DEST (elt)) != dest_regno + i
1238 || GET_CODE (SET_SRC (elt)) != MEM
1239 || GET_MODE (SET_SRC (elt)) != SImode
1240 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1241 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1242 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1243 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1250 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
1251 ;; The second vector element is a CLOBBER.
1252 (define_predicate "store_multiple_operation"
1253 (match_code "parallel")
1255 int count = XVECLEN (op, 0) - 1;
1256 unsigned int src_regno;
1260 /* Perform a quick check so we don't blow up below. */
1262 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1263 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1264 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1267 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1268 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1270 for (i = 1; i < count; i++)
1272 rtx elt = XVECEXP (op, 0, i + 1);
1274 if (GET_CODE (elt) != SET
1275 || GET_CODE (SET_SRC (elt)) != REG
1276 || GET_MODE (SET_SRC (elt)) != SImode
1277 || REGNO (SET_SRC (elt)) != src_regno + i
1278 || GET_CODE (SET_DEST (elt)) != MEM
1279 || GET_MODE (SET_DEST (elt)) != SImode
1280 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1281 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1282 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1283 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1290 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1292 (define_predicate "save_world_operation"
1293 (match_code "parallel")
1298 int count = XVECLEN (op, 0);
1304 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1305 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1308 for (i=1; i <= 18; i++)
1310 elt = XVECEXP (op, 0, index++);
1311 if (GET_CODE (elt) != SET
1312 || GET_CODE (SET_DEST (elt)) != MEM
1313 || ! memory_operand (SET_DEST (elt), DFmode)
1314 || GET_CODE (SET_SRC (elt)) != REG
1315 || GET_MODE (SET_SRC (elt)) != DFmode)
1319 for (i=1; i <= 12; i++)
1321 elt = XVECEXP (op, 0, index++);
1322 if (GET_CODE (elt) != SET
1323 || GET_CODE (SET_DEST (elt)) != MEM
1324 || GET_CODE (SET_SRC (elt)) != REG
1325 || GET_MODE (SET_SRC (elt)) != V4SImode)
1329 for (i=1; i <= 19; i++)
1331 elt = XVECEXP (op, 0, index++);
1332 if (GET_CODE (elt) != SET
1333 || GET_CODE (SET_DEST (elt)) != MEM
1334 || ! memory_operand (SET_DEST (elt), Pmode)
1335 || GET_CODE (SET_SRC (elt)) != REG
1336 || GET_MODE (SET_SRC (elt)) != Pmode)
1340 elt = XVECEXP (op, 0, index++);
1341 if (GET_CODE (elt) != SET
1342 || GET_CODE (SET_DEST (elt)) != MEM
1343 || ! memory_operand (SET_DEST (elt), Pmode)
1344 || GET_CODE (SET_SRC (elt)) != REG
1345 || REGNO (SET_SRC (elt)) != CR2_REGNO
1346 || GET_MODE (SET_SRC (elt)) != Pmode)
1349 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1350 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1355 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1357 (define_predicate "restore_world_operation"
1358 (match_code "parallel")
1363 int count = XVECLEN (op, 0);
1369 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1370 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1371 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1372 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1375 elt = XVECEXP (op, 0, index++);
1376 if (GET_CODE (elt) != SET
1377 || GET_CODE (SET_SRC (elt)) != MEM
1378 || ! memory_operand (SET_SRC (elt), Pmode)
1379 || GET_CODE (SET_DEST (elt)) != REG
1380 || REGNO (SET_DEST (elt)) != CR2_REGNO
1381 || GET_MODE (SET_DEST (elt)) != Pmode)
1384 for (i=1; i <= 19; i++)
1386 elt = XVECEXP (op, 0, index++);
1387 if (GET_CODE (elt) != SET
1388 || GET_CODE (SET_SRC (elt)) != MEM
1389 || ! memory_operand (SET_SRC (elt), Pmode)
1390 || GET_CODE (SET_DEST (elt)) != REG
1391 || GET_MODE (SET_DEST (elt)) != Pmode)
1395 for (i=1; i <= 12; i++)
1397 elt = XVECEXP (op, 0, index++);
1398 if (GET_CODE (elt) != SET
1399 || GET_CODE (SET_SRC (elt)) != MEM
1400 || GET_CODE (SET_DEST (elt)) != REG
1401 || GET_MODE (SET_DEST (elt)) != V4SImode)
1405 for (i=1; i <= 18; i++)
1407 elt = XVECEXP (op, 0, index++);
1408 if (GET_CODE (elt) != SET
1409 || GET_CODE (SET_SRC (elt)) != MEM
1410 || ! memory_operand (SET_SRC (elt), DFmode)
1411 || GET_CODE (SET_DEST (elt)) != REG
1412 || GET_MODE (SET_DEST (elt)) != DFmode)
1416 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1417 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1418 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1419 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1420 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1425 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1426 (define_predicate "vrsave_operation"
1427 (match_code "parallel")
1429 int count = XVECLEN (op, 0);
1430 unsigned int dest_regno, src_regno;
1434 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1435 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1436 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1437 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1440 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1441 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1443 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1446 for (i = 1; i < count; i++)
1448 rtx elt = XVECEXP (op, 0, i);
1450 if (GET_CODE (elt) != CLOBBER
1451 && GET_CODE (elt) != SET)
1458 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1459 (define_predicate "mfcr_operation"
1460 (match_code "parallel")
1462 int count = XVECLEN (op, 0);
1465 /* Perform a quick check so we don't blow up below. */
1467 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1468 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1469 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1472 for (i = 0; i < count; i++)
1474 rtx exp = XVECEXP (op, 0, i);
1479 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1481 if (GET_CODE (src_reg) != REG
1482 || GET_MODE (src_reg) != CCmode
1483 || ! CR_REGNO_P (REGNO (src_reg)))
1486 if (GET_CODE (exp) != SET
1487 || GET_CODE (SET_DEST (exp)) != REG
1488 || GET_MODE (SET_DEST (exp)) != SImode
1489 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1491 unspec = SET_SRC (exp);
1492 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1494 if (GET_CODE (unspec) != UNSPEC
1495 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1496 || XVECLEN (unspec, 0) != 2
1497 || XVECEXP (unspec, 0, 0) != src_reg
1498 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1499 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1505 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1506 (define_predicate "mtcrf_operation"
1507 (match_code "parallel")
1509 int count = XVECLEN (op, 0);
1513 /* Perform a quick check so we don't blow up below. */
1515 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1516 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1517 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1519 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1521 if (GET_CODE (src_reg) != REG
1522 || GET_MODE (src_reg) != SImode
1523 || ! INT_REGNO_P (REGNO (src_reg)))
1526 for (i = 0; i < count; i++)
1528 rtx exp = XVECEXP (op, 0, i);
1532 if (GET_CODE (exp) != SET
1533 || GET_CODE (SET_DEST (exp)) != REG
1534 || GET_MODE (SET_DEST (exp)) != CCmode
1535 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1537 unspec = SET_SRC (exp);
1538 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1540 if (GET_CODE (unspec) != UNSPEC
1541 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1542 || XVECLEN (unspec, 0) != 2
1543 || XVECEXP (unspec, 0, 0) != src_reg
1544 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1545 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1551 ;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL.
1552 (define_predicate "crsave_operation"
1553 (match_code "parallel")
1555 int count = XVECLEN (op, 0);
1558 for (i = 1; i < count; i++)
1560 rtx exp = XVECEXP (op, 0, i);
1562 if (GET_CODE (exp) != USE
1563 || GET_CODE (XEXP (exp, 0)) != REG
1564 || GET_MODE (XEXP (exp, 0)) != CCmode
1565 || ! CR_REGNO_P (REGNO (XEXP (exp, 0))))
1571 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1572 (define_predicate "lmw_operation"
1573 (match_code "parallel")
1575 int count = XVECLEN (op, 0);
1576 unsigned int dest_regno;
1578 unsigned int base_regno;
1579 HOST_WIDE_INT offset;
1582 /* Perform a quick check so we don't blow up below. */
1584 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1585 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1586 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1589 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1590 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1593 || count != 32 - (int) dest_regno)
1596 if (legitimate_indirect_address_p (src_addr, 0))
1599 base_regno = REGNO (src_addr);
1600 if (base_regno == 0)
1603 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false))
1605 offset = INTVAL (XEXP (src_addr, 1));
1606 base_regno = REGNO (XEXP (src_addr, 0));
1611 for (i = 0; i < count; i++)
1613 rtx elt = XVECEXP (op, 0, i);
1616 HOST_WIDE_INT newoffset;
1618 if (GET_CODE (elt) != SET
1619 || GET_CODE (SET_DEST (elt)) != REG
1620 || GET_MODE (SET_DEST (elt)) != SImode
1621 || REGNO (SET_DEST (elt)) != dest_regno + i
1622 || GET_CODE (SET_SRC (elt)) != MEM
1623 || GET_MODE (SET_SRC (elt)) != SImode)
1625 newaddr = XEXP (SET_SRC (elt), 0);
1626 if (legitimate_indirect_address_p (newaddr, 0))
1631 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1633 addr_reg = XEXP (newaddr, 0);
1634 newoffset = INTVAL (XEXP (newaddr, 1));
1638 if (REGNO (addr_reg) != base_regno
1639 || newoffset != offset + 4 * i)
1646 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1647 (define_predicate "stmw_operation"
1648 (match_code "parallel")
1650 int count = XVECLEN (op, 0);
1651 unsigned int src_regno;
1653 unsigned int base_regno;
1654 HOST_WIDE_INT offset;
1657 /* Perform a quick check so we don't blow up below. */
1659 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1660 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1661 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1664 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1665 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1668 || count != 32 - (int) src_regno)
1671 if (legitimate_indirect_address_p (dest_addr, 0))
1674 base_regno = REGNO (dest_addr);
1675 if (base_regno == 0)
1678 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false))
1680 offset = INTVAL (XEXP (dest_addr, 1));
1681 base_regno = REGNO (XEXP (dest_addr, 0));
1686 for (i = 0; i < count; i++)
1688 rtx elt = XVECEXP (op, 0, i);
1691 HOST_WIDE_INT newoffset;
1693 if (GET_CODE (elt) != SET
1694 || GET_CODE (SET_SRC (elt)) != REG
1695 || GET_MODE (SET_SRC (elt)) != SImode
1696 || REGNO (SET_SRC (elt)) != src_regno + i
1697 || GET_CODE (SET_DEST (elt)) != MEM
1698 || GET_MODE (SET_DEST (elt)) != SImode)
1700 newaddr = XEXP (SET_DEST (elt), 0);
1701 if (legitimate_indirect_address_p (newaddr, 0))
1706 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1708 addr_reg = XEXP (newaddr, 0);
1709 newoffset = INTVAL (XEXP (newaddr, 1));
1713 if (REGNO (addr_reg) != base_regno
1714 || newoffset != offset + 4 * i)
1721 ;; Return 1 if OP is a stack tie operand.
1722 (define_predicate "tie_operand"
1723 (match_code "parallel")
1725 return (GET_CODE (XVECEXP (op, 0, 0)) == SET
1726 && GET_CODE (XEXP (XVECEXP (op, 0, 0), 0)) == MEM
1727 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode
1728 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx);
1731 ;; Match a small code model toc reference (or medium and large
1732 ;; model toc references before reload).
1733 (define_predicate "small_toc_ref"
1734 (match_code "unspec,plus")
1736 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode))
1739 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;
1742 ;; Match the first insn (addis) in fusing the combination of addis and loads to
1743 ;; GPR registers on power8.
1744 (define_predicate "fusion_gpr_addis"
1745 (match_code "const_int,high,plus")
1747 HOST_WIDE_INT value;
1750 if (GET_CODE (op) == HIGH)
1753 if (CONST_INT_P (op))
1756 else if (GET_CODE (op) == PLUS
1757 && base_reg_operand (XEXP (op, 0), Pmode)
1758 && CONST_INT_P (XEXP (op, 1)))
1759 int_const = XEXP (op, 1);
1764 /* Power8 currently will only do the fusion if the top 11 bits of the addis
1765 value are all 1's or 0's. */
1766 value = INTVAL (int_const);
1767 if ((value & (HOST_WIDE_INT)0xffff) != 0)
1770 if ((value & (HOST_WIDE_INT)0xffff0000) == 0)
1773 return (IN_RANGE (value >> 16, -32, 31));
1776 ;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis
1777 ;; and loads to GPR registers on power8.
1778 (define_predicate "fusion_gpr_mem_load"
1779 (match_code "mem,sign_extend,zero_extend")
1783 /* Handle sign/zero extend. */
1784 if (GET_CODE (op) == ZERO_EXTEND
1785 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND))
1788 mode = GET_MODE (op);
1802 if (!TARGET_POWERPC64)
1810 addr = XEXP (op, 0);
1811 if (GET_CODE (addr) == PLUS)
1813 rtx base = XEXP (addr, 0);
1814 rtx offset = XEXP (addr, 1);
1816 return (base_reg_operand (base, GET_MODE (base))
1817 && satisfies_constraint_I (offset));
1820 else if (GET_CODE (addr) == LO_SUM)
1822 rtx base = XEXP (addr, 0);
1823 rtx offset = XEXP (addr, 1);
1825 if (!base_reg_operand (base, GET_MODE (base)))
1828 else if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1829 return small_toc_ref (offset, GET_MODE (offset));
1831 else if (TARGET_ELF && !TARGET_POWERPC64)
1832 return CONSTANT_P (offset);