1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
38 #include "stringpool.h"
39 #include "stor-layout.h"
50 #include "hash-table.h"
53 #include "target-def.h"
54 #include "common/common-target.h"
55 #include "langhooks.h"
56 #include "sched-int.h"
57 #include "pointer-set.h"
59 #include "basic-block.h"
60 #include "tree-ssa-alias.h"
61 #include "internal-fn.h"
62 #include "gimple-fold.h"
64 #include "gimple-expr.h"
69 #include "diagnostic.h"
70 #include "target-globals.h"
72 #include "tree-pass.h"
75 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
76 #define UNSPEC_ADDRESS_P(X) \
77 (GET_CODE (X) == UNSPEC \
78 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
79 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
81 /* Extract the symbol or label from UNSPEC wrapper X. */
82 #define UNSPEC_ADDRESS(X) \
85 /* Extract the symbol type from UNSPEC wrapper X. */
86 #define UNSPEC_ADDRESS_TYPE(X) \
87 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
89 /* The maximum distance between the top of the stack frame and the
90 value $sp has when we save and restore registers.
92 The value for normal-mode code must be a SMALL_OPERAND and must
93 preserve the maximum stack alignment. We therefore use a value
94 of 0x7ff0 in this case.
96 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
97 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
99 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
100 up to 0x7f8 bytes and can usually save or restore all the registers
101 that we need to save or restore. (Note that we can only use these
102 instructions for o32, for which the stack alignment is 8 bytes.)
104 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
105 RESTORE are not available. We can then use unextended instructions
106 to save and restore registers, and to allocate and deallocate the top
107 part of the frame. */
108 #define MIPS_MAX_FIRST_STACK_STEP \
109 (!TARGET_COMPRESSION ? 0x7ff0 \
110 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
111 : TARGET_64BIT ? 0x100 : 0x400)
113 /* True if INSN is a mips.md pattern or asm statement. */
114 /* ??? This test exists through the compiler, perhaps it should be
116 #define USEFUL_INSN_P(INSN) \
117 (NONDEBUG_INSN_P (INSN) \
118 && GET_CODE (PATTERN (INSN)) != USE \
119 && GET_CODE (PATTERN (INSN)) != CLOBBER)
121 /* If INSN is a delayed branch sequence, return the first instruction
122 in the sequence, otherwise return INSN itself. */
123 #define SEQ_BEGIN(INSN) \
124 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
125 ? XVECEXP (PATTERN (INSN), 0, 0) \
128 /* Likewise for the last instruction in a delayed branch sequence. */
129 #define SEQ_END(INSN) \
130 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
131 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
134 /* Execute the following loop body with SUBINSN set to each instruction
135 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
136 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
137 for ((SUBINSN) = SEQ_BEGIN (INSN); \
138 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
139 (SUBINSN) = NEXT_INSN (SUBINSN))
141 /* True if bit BIT is set in VALUE. */
142 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
144 /* Return the opcode for a ptr_mode load of the form:
146 l[wd] DEST, OFFSET(BASE). */
147 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
148 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
153 /* Return the opcode to move register SRC into register DEST. */
154 #define MIPS_MOVE(DEST, SRC) \
155 ((TARGET_64BIT ? 0x2d : 0x21) \
159 /* Return the opcode for:
162 #define MIPS_LUI(DEST, VALUE) \
163 ((0xf << 26) | ((DEST) << 16) | (VALUE))
165 /* Return the opcode to jump to register DEST. */
166 #define MIPS_JR(DEST) \
167 (((DEST) << 21) | 0x8)
169 /* Return the opcode for:
171 bal . + (1 + OFFSET) * 4. */
172 #define MIPS_BAL(OFFSET) \
173 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
175 /* Return the usual opcode for a nop. */
178 /* Classifies an address.
181 A natural register + offset address. The register satisfies
182 mips_valid_base_register_p and the offset is a const_arith_operand.
185 A LO_SUM rtx. The first operand is a valid base register and
186 the second operand is a symbolic address.
189 A signed 16-bit constant address.
192 A constant symbolic address. */
193 enum mips_address_type
{
200 /* Macros to create an enumeration identifier for a function prototype. */
201 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
202 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
203 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
204 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
206 /* Classifies the prototype of a built-in function. */
207 enum mips_function_type
{
208 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
209 #include "config/mips/mips-ftypes.def"
210 #undef DEF_MIPS_FTYPE
214 /* Specifies how a built-in function should be converted into rtl. */
215 enum mips_builtin_type
{
216 /* The function corresponds directly to an .md pattern. The return
217 value is mapped to operand 0 and the arguments are mapped to
218 operands 1 and above. */
221 /* The function corresponds directly to an .md pattern. There is no return
222 value and the arguments are mapped to operands 0 and above. */
223 MIPS_BUILTIN_DIRECT_NO_TARGET
,
225 /* The function corresponds to a comparison instruction followed by
226 a mips_cond_move_tf_ps pattern. The first two arguments are the
227 values to compare and the second two arguments are the vector
228 operands for the movt.ps or movf.ps instruction (in assembly order). */
232 /* The function corresponds to a V2SF comparison instruction. Operand 0
233 of this instruction is the result of the comparison, which has mode
234 CCV2 or CCV4. The function arguments are mapped to operands 1 and
235 above. The function's return value is an SImode boolean that is
236 true under the following conditions:
238 MIPS_BUILTIN_CMP_ANY: one of the registers is true
239 MIPS_BUILTIN_CMP_ALL: all of the registers are true
240 MIPS_BUILTIN_CMP_LOWER: the first register is true
241 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
242 MIPS_BUILTIN_CMP_ANY
,
243 MIPS_BUILTIN_CMP_ALL
,
244 MIPS_BUILTIN_CMP_UPPER
,
245 MIPS_BUILTIN_CMP_LOWER
,
247 /* As above, but the instruction only sets a single $fcc register. */
248 MIPS_BUILTIN_CMP_SINGLE
,
250 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
251 MIPS_BUILTIN_BPOSGE32
254 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
255 #define MIPS_FP_CONDITIONS(MACRO) \
273 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
274 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
275 enum mips_fp_condition
{
276 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
278 #undef DECLARE_MIPS_COND
280 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
281 #define STRINGIFY(X) #X
282 static const char *const mips_fp_conditions
[] = {
283 MIPS_FP_CONDITIONS (STRINGIFY
)
287 /* A class used to control a comdat-style stub that we output in each
288 translation unit that needs it. */
289 class mips_one_only_stub
{
291 virtual ~mips_one_only_stub () {}
293 /* Return the name of the stub. */
294 virtual const char *get_name () = 0;
296 /* Output the body of the function to asm_out_file. */
297 virtual void output_body () = 0;
300 /* Tuning information that is automatically derived from other sources
301 (such as the scheduler). */
303 /* The architecture and tuning settings that this structure describes. */
307 /* True if this structure describes MIPS16 settings. */
310 /* True if the structure has been initialized. */
313 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
314 when optimizing for speed. */
315 bool fast_mult_zero_zero_p
;
318 /* Information about a function's frame layout. */
319 struct GTY(()) mips_frame_info
{
320 /* The size of the frame in bytes. */
321 HOST_WIDE_INT total_size
;
323 /* The number of bytes allocated to variables. */
324 HOST_WIDE_INT var_size
;
326 /* The number of bytes allocated to outgoing function arguments. */
327 HOST_WIDE_INT args_size
;
329 /* The number of bytes allocated to the .cprestore slot, or 0 if there
331 HOST_WIDE_INT cprestore_size
;
333 /* Bit X is set if the function saves or restores GPR X. */
336 /* Likewise FPR X. */
339 /* Likewise doubleword accumulator X ($acX). */
340 unsigned int acc_mask
;
342 /* The number of GPRs, FPRs, doubleword accumulators and COP0
346 unsigned int num_acc
;
347 unsigned int num_cop0_regs
;
349 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
350 save slots from the top of the frame, or zero if no such slots are
352 HOST_WIDE_INT gp_save_offset
;
353 HOST_WIDE_INT fp_save_offset
;
354 HOST_WIDE_INT acc_save_offset
;
355 HOST_WIDE_INT cop0_save_offset
;
357 /* Likewise, but giving offsets from the bottom of the frame. */
358 HOST_WIDE_INT gp_sp_offset
;
359 HOST_WIDE_INT fp_sp_offset
;
360 HOST_WIDE_INT acc_sp_offset
;
361 HOST_WIDE_INT cop0_sp_offset
;
363 /* Similar, but the value passed to _mcount. */
364 HOST_WIDE_INT ra_fp_offset
;
366 /* The offset of arg_pointer_rtx from the bottom of the frame. */
367 HOST_WIDE_INT arg_pointer_offset
;
369 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
370 HOST_WIDE_INT hard_frame_pointer_offset
;
373 struct GTY(()) machine_function
{
374 /* The next floating-point condition-code register to allocate
375 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
376 unsigned int next_fcc
;
378 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
379 rtx mips16_gp_pseudo_rtx
;
381 /* The number of extra stack bytes taken up by register varargs.
382 This area is allocated by the callee at the very top of the frame. */
385 /* The current frame information, calculated by mips_compute_frame_info. */
386 struct mips_frame_info frame
;
388 /* The register to use as the function's global pointer, or INVALID_REGNUM
389 if the function doesn't need one. */
390 unsigned int global_pointer
;
392 /* How many instructions it takes to load a label into $AT, or 0 if
393 this property hasn't yet been calculated. */
394 unsigned int load_label_num_insns
;
396 /* True if mips_adjust_insn_length should ignore an instruction's
398 bool ignore_hazard_length_p
;
400 /* True if the whole function is suitable for .set noreorder and
402 bool all_noreorder_p
;
404 /* True if the function has "inflexible" and "flexible" references
405 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
406 and mips_cfun_has_flexible_gp_ref_p for details. */
407 bool has_inflexible_gp_insn_p
;
408 bool has_flexible_gp_insn_p
;
410 /* True if the function's prologue must load the global pointer
411 value into pic_offset_table_rtx and store the same value in
412 the function's cprestore slot (if any). Even if this value
413 is currently false, we may decide to set it to true later;
414 see mips_must_initialize_gp_p () for details. */
415 bool must_initialize_gp_p
;
417 /* True if the current function must restore $gp after any potential
418 clobber. This value is only meaningful during the first post-epilogue
419 split_insns pass; see mips_must_initialize_gp_p () for details. */
420 bool must_restore_gp_when_clobbered_p
;
422 /* True if this is an interrupt handler. */
423 bool interrupt_handler_p
;
425 /* True if this is an interrupt handler that uses shadow registers. */
426 bool use_shadow_register_set_p
;
428 /* True if this is an interrupt handler that should keep interrupts
430 bool keep_interrupts_masked_p
;
432 /* True if this is an interrupt handler that should use DERET
434 bool use_debug_exception_return_p
;
437 /* Information about a single argument. */
438 struct mips_arg_info
{
439 /* True if the argument is passed in a floating-point register, or
440 would have been if we hadn't run out of registers. */
443 /* The number of words passed in registers, rounded up. */
444 unsigned int reg_words
;
446 /* For EABI, the offset of the first register from GP_ARG_FIRST or
447 FP_ARG_FIRST. For other ABIs, the offset of the first register from
448 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
449 comment for details).
451 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
453 unsigned int reg_offset
;
455 /* The number of words that must be passed on the stack, rounded up. */
456 unsigned int stack_words
;
458 /* The offset from the start of the stack overflow area of the argument's
459 first stack word. Only meaningful when STACK_WORDS is nonzero. */
460 unsigned int stack_offset
;
463 /* Information about an address described by mips_address_type.
469 REG is the base register and OFFSET is the constant offset.
472 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
473 is the type of symbol it references.
476 SYMBOL_TYPE is the type of symbol that the address references. */
477 struct mips_address_info
{
478 enum mips_address_type type
;
481 enum mips_symbol_type symbol_type
;
484 /* One stage in a constant building sequence. These sequences have
488 A = A CODE[1] VALUE[1]
489 A = A CODE[2] VALUE[2]
492 where A is an accumulator, each CODE[i] is a binary rtl operation
493 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
494 struct mips_integer_op
{
496 unsigned HOST_WIDE_INT value
;
499 /* The largest number of operations needed to load an integer constant.
500 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
501 When the lowest bit is clear, we can try, but reject a sequence with
502 an extra SLL at the end. */
503 #define MIPS_MAX_INTEGER_OPS 7
505 /* Information about a MIPS16e SAVE or RESTORE instruction. */
506 struct mips16e_save_restore_info
{
507 /* The number of argument registers saved by a SAVE instruction.
508 0 for RESTORE instructions. */
511 /* Bit X is set if the instruction saves or restores GPR X. */
514 /* The total number of bytes to allocate. */
518 /* Costs of various operations on the different architectures. */
520 struct mips_rtx_cost_data
522 unsigned short fp_add
;
523 unsigned short fp_mult_sf
;
524 unsigned short fp_mult_df
;
525 unsigned short fp_div_sf
;
526 unsigned short fp_div_df
;
527 unsigned short int_mult_si
;
528 unsigned short int_mult_di
;
529 unsigned short int_div_si
;
530 unsigned short int_div_di
;
531 unsigned short branch_cost
;
532 unsigned short memory_latency
;
535 /* Global variables for machine-dependent things. */
537 /* The -G setting, or the configuration's default small-data limit if
538 no -G option is given. */
539 static unsigned int mips_small_data_threshold
;
541 /* The number of file directives written by mips_output_filename. */
542 int num_source_filenames
;
544 /* The name that appeared in the last .file directive written by
545 mips_output_filename, or "" if mips_output_filename hasn't
546 written anything yet. */
547 const char *current_function_file
= "";
549 /* Arrays that map GCC register numbers to debugger register numbers. */
550 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
551 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
553 /* Information about the current function's epilogue, used only while
556 /* A list of queued REG_CFA_RESTORE notes. */
559 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
561 HOST_WIDE_INT cfa_offset
;
563 /* The offset of the CFA from the stack pointer while restoring
565 HOST_WIDE_INT cfa_restore_sp_offset
;
568 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
569 struct mips_asm_switch mips_noreorder
= { "reorder", 0 };
570 struct mips_asm_switch mips_nomacro
= { "macro", 0 };
571 struct mips_asm_switch mips_noat
= { "at", 0 };
573 /* True if we're writing out a branch-likely instruction rather than a
575 static bool mips_branch_likely
;
577 /* The current instruction-set architecture. */
578 enum processor mips_arch
;
579 const struct mips_cpu_info
*mips_arch_info
;
581 /* The processor that we should tune the code for. */
582 enum processor mips_tune
;
583 const struct mips_cpu_info
*mips_tune_info
;
585 /* The ISA level associated with mips_arch. */
588 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
589 static const struct mips_cpu_info
*mips_isa_option_info
;
591 /* Which cost information to use. */
592 static const struct mips_rtx_cost_data
*mips_cost
;
594 /* The ambient target flags, excluding MASK_MIPS16. */
595 static int mips_base_target_flags
;
597 /* The default compression mode. */
598 unsigned int mips_base_compression_flags
;
600 /* The ambient values of other global variables. */
601 static int mips_base_schedule_insns
; /* flag_schedule_insns */
602 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
603 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
604 static int mips_base_align_loops
; /* align_loops */
605 static int mips_base_align_jumps
; /* align_jumps */
606 static int mips_base_align_functions
; /* align_functions */
608 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
609 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
611 /* Index C is true if character C is a valid PRINT_OPERAND punctation
613 static bool mips_print_operand_punct
[256];
615 static GTY (()) int mips_output_filename_first_time
= 1;
617 /* mips_split_p[X] is true if symbols of type X can be split by
618 mips_split_symbol. */
619 bool mips_split_p
[NUM_SYMBOL_TYPES
];
621 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
622 can be split by mips_split_symbol. */
623 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
625 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
626 forced into a PC-relative constant pool. */
627 bool mips_use_pcrel_pool_p
[NUM_SYMBOL_TYPES
];
629 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
630 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
631 if they are matched by a special .md file pattern. */
632 const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
634 /* Likewise for HIGHs. */
635 const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
637 /* Target state for MIPS16. */
638 struct target_globals
*mips16_globals
;
640 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
641 and returned from mips_sched_reorder2. */
642 static int cached_can_issue_more
;
644 /* The stubs for various MIPS16 support functions, if used. */
645 static mips_one_only_stub
*mips16_rdhwr_stub
;
646 static mips_one_only_stub
*mips16_get_fcsr_stub
;
647 static mips_one_only_stub
*mips16_set_fcsr_stub
;
649 /* Index R is the smallest register class that contains register R. */
650 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
651 LEA_REGS
, LEA_REGS
, M16_REGS
, V1_REG
,
652 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
653 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
654 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
655 M16_REGS
, M16_REGS
, LEA_REGS
, LEA_REGS
,
656 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
657 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
658 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
659 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
660 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
661 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
662 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
663 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
664 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
665 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
666 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
667 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
668 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
669 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
670 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
671 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
672 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
673 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
674 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
675 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
676 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
677 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
678 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
679 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
680 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
681 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
682 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
683 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
684 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
685 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
686 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
687 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
688 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
689 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
690 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
691 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
692 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
693 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
694 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
695 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
696 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
697 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
700 /* The value of TARGET_ATTRIBUTE_TABLE. */
701 static const struct attribute_spec mips_attribute_table
[] = {
702 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
704 { "long_call", 0, 0, false, true, true, NULL
, false },
705 { "far", 0, 0, false, true, true, NULL
, false },
706 { "near", 0, 0, false, true, true, NULL
, false },
707 /* We would really like to treat "mips16" and "nomips16" as type
708 attributes, but GCC doesn't provide the hooks we need to support
709 the right conversion rules. As declaration attributes, they affect
710 code generation but don't carry other semantics. */
711 { "mips16", 0, 0, true, false, false, NULL
, false },
712 { "nomips16", 0, 0, true, false, false, NULL
, false },
713 { "micromips", 0, 0, true, false, false, NULL
, false },
714 { "nomicromips", 0, 0, true, false, false, NULL
, false },
715 { "nocompression", 0, 0, true, false, false, NULL
, false },
716 /* Allow functions to be specified as interrupt handlers */
717 { "interrupt", 0, 0, false, true, true, NULL
, false },
718 { "use_shadow_register_set", 0, 0, false, true, true, NULL
, false },
719 { "keep_interrupts_masked", 0, 0, false, true, true, NULL
, false },
720 { "use_debug_exception_return", 0, 0, false, true, true, NULL
, false },
721 { NULL
, 0, 0, false, false, false, NULL
, false }
724 /* A table describing all the processors GCC knows about; see
725 mips-cpus.def for details. */
726 static const struct mips_cpu_info mips_cpu_info_table
[] = {
727 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
728 { NAME, CPU, ISA, FLAGS },
729 #include "mips-cpus.def"
733 /* Default costs. If these are used for a processor we should look
734 up the actual costs. */
735 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
736 COSTS_N_INSNS (7), /* fp_mult_sf */ \
737 COSTS_N_INSNS (8), /* fp_mult_df */ \
738 COSTS_N_INSNS (23), /* fp_div_sf */ \
739 COSTS_N_INSNS (36), /* fp_div_df */ \
740 COSTS_N_INSNS (10), /* int_mult_si */ \
741 COSTS_N_INSNS (10), /* int_mult_di */ \
742 COSTS_N_INSNS (69), /* int_div_si */ \
743 COSTS_N_INSNS (69), /* int_div_di */ \
744 2, /* branch_cost */ \
745 4 /* memory_latency */
747 /* Floating-point costs for processors without an FPU. Just assume that
748 all floating-point libcalls are very expensive. */
749 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
750 COSTS_N_INSNS (256), /* fp_mult_sf */ \
751 COSTS_N_INSNS (256), /* fp_mult_df */ \
752 COSTS_N_INSNS (256), /* fp_div_sf */ \
753 COSTS_N_INSNS (256) /* fp_div_df */
755 /* Costs to use when optimizing for size. */
756 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
757 COSTS_N_INSNS (1), /* fp_add */
758 COSTS_N_INSNS (1), /* fp_mult_sf */
759 COSTS_N_INSNS (1), /* fp_mult_df */
760 COSTS_N_INSNS (1), /* fp_div_sf */
761 COSTS_N_INSNS (1), /* fp_div_df */
762 COSTS_N_INSNS (1), /* int_mult_si */
763 COSTS_N_INSNS (1), /* int_mult_di */
764 COSTS_N_INSNS (1), /* int_div_si */
765 COSTS_N_INSNS (1), /* int_div_di */
767 4 /* memory_latency */
770 /* Costs to use when optimizing for speed, indexed by processor. */
771 static const struct mips_rtx_cost_data
772 mips_rtx_cost_data
[NUM_PROCESSOR_VALUES
] = {
774 COSTS_N_INSNS (2), /* fp_add */
775 COSTS_N_INSNS (4), /* fp_mult_sf */
776 COSTS_N_INSNS (5), /* fp_mult_df */
777 COSTS_N_INSNS (12), /* fp_div_sf */
778 COSTS_N_INSNS (19), /* fp_div_df */
779 COSTS_N_INSNS (12), /* int_mult_si */
780 COSTS_N_INSNS (12), /* int_mult_di */
781 COSTS_N_INSNS (35), /* int_div_si */
782 COSTS_N_INSNS (35), /* int_div_di */
784 4 /* memory_latency */
788 COSTS_N_INSNS (6), /* int_mult_si */
789 COSTS_N_INSNS (6), /* int_mult_di */
790 COSTS_N_INSNS (36), /* int_div_si */
791 COSTS_N_INSNS (36), /* int_div_di */
793 4 /* memory_latency */
797 COSTS_N_INSNS (36), /* int_mult_si */
798 COSTS_N_INSNS (36), /* int_mult_di */
799 COSTS_N_INSNS (37), /* int_div_si */
800 COSTS_N_INSNS (37), /* int_div_di */
802 4 /* memory_latency */
806 COSTS_N_INSNS (4), /* int_mult_si */
807 COSTS_N_INSNS (11), /* int_mult_di */
808 COSTS_N_INSNS (36), /* int_div_si */
809 COSTS_N_INSNS (68), /* int_div_di */
811 4 /* memory_latency */
814 COSTS_N_INSNS (4), /* fp_add */
815 COSTS_N_INSNS (4), /* fp_mult_sf */
816 COSTS_N_INSNS (5), /* fp_mult_df */
817 COSTS_N_INSNS (17), /* fp_div_sf */
818 COSTS_N_INSNS (32), /* fp_div_df */
819 COSTS_N_INSNS (4), /* int_mult_si */
820 COSTS_N_INSNS (11), /* int_mult_di */
821 COSTS_N_INSNS (36), /* int_div_si */
822 COSTS_N_INSNS (68), /* int_div_di */
824 4 /* memory_latency */
827 COSTS_N_INSNS (4), /* fp_add */
828 COSTS_N_INSNS (4), /* fp_mult_sf */
829 COSTS_N_INSNS (5), /* fp_mult_df */
830 COSTS_N_INSNS (17), /* fp_div_sf */
831 COSTS_N_INSNS (32), /* fp_div_df */
832 COSTS_N_INSNS (4), /* int_mult_si */
833 COSTS_N_INSNS (7), /* int_mult_di */
834 COSTS_N_INSNS (42), /* int_div_si */
835 COSTS_N_INSNS (72), /* int_div_di */
837 4 /* memory_latency */
841 COSTS_N_INSNS (5), /* int_mult_si */
842 COSTS_N_INSNS (5), /* int_mult_di */
843 COSTS_N_INSNS (41), /* int_div_si */
844 COSTS_N_INSNS (41), /* int_div_di */
846 4 /* memory_latency */
849 COSTS_N_INSNS (8), /* fp_add */
850 COSTS_N_INSNS (8), /* fp_mult_sf */
851 COSTS_N_INSNS (10), /* fp_mult_df */
852 COSTS_N_INSNS (34), /* fp_div_sf */
853 COSTS_N_INSNS (64), /* fp_div_df */
854 COSTS_N_INSNS (5), /* int_mult_si */
855 COSTS_N_INSNS (5), /* int_mult_di */
856 COSTS_N_INSNS (41), /* int_div_si */
857 COSTS_N_INSNS (41), /* int_div_di */
859 4 /* memory_latency */
862 COSTS_N_INSNS (4), /* fp_add */
863 COSTS_N_INSNS (4), /* fp_mult_sf */
864 COSTS_N_INSNS (5), /* fp_mult_df */
865 COSTS_N_INSNS (17), /* fp_div_sf */
866 COSTS_N_INSNS (32), /* fp_div_df */
867 COSTS_N_INSNS (5), /* int_mult_si */
868 COSTS_N_INSNS (5), /* int_mult_di */
869 COSTS_N_INSNS (41), /* int_div_si */
870 COSTS_N_INSNS (41), /* int_div_di */
872 4 /* memory_latency */
876 COSTS_N_INSNS (5), /* int_mult_si */
877 COSTS_N_INSNS (5), /* int_mult_di */
878 COSTS_N_INSNS (41), /* int_div_si */
879 COSTS_N_INSNS (41), /* int_div_di */
881 4 /* memory_latency */
884 COSTS_N_INSNS (8), /* fp_add */
885 COSTS_N_INSNS (8), /* fp_mult_sf */
886 COSTS_N_INSNS (10), /* fp_mult_df */
887 COSTS_N_INSNS (34), /* fp_div_sf */
888 COSTS_N_INSNS (64), /* fp_div_df */
889 COSTS_N_INSNS (5), /* int_mult_si */
890 COSTS_N_INSNS (5), /* int_mult_di */
891 COSTS_N_INSNS (41), /* int_div_si */
892 COSTS_N_INSNS (41), /* int_div_di */
894 4 /* memory_latency */
897 COSTS_N_INSNS (4), /* fp_add */
898 COSTS_N_INSNS (4), /* fp_mult_sf */
899 COSTS_N_INSNS (5), /* fp_mult_df */
900 COSTS_N_INSNS (17), /* fp_div_sf */
901 COSTS_N_INSNS (32), /* fp_div_df */
902 COSTS_N_INSNS (5), /* int_mult_si */
903 COSTS_N_INSNS (5), /* int_mult_di */
904 COSTS_N_INSNS (41), /* int_div_si */
905 COSTS_N_INSNS (41), /* int_div_di */
907 4 /* memory_latency */
910 COSTS_N_INSNS (6), /* fp_add */
911 COSTS_N_INSNS (6), /* fp_mult_sf */
912 COSTS_N_INSNS (7), /* fp_mult_df */
913 COSTS_N_INSNS (25), /* fp_div_sf */
914 COSTS_N_INSNS (48), /* fp_div_df */
915 COSTS_N_INSNS (5), /* int_mult_si */
916 COSTS_N_INSNS (5), /* int_mult_di */
917 COSTS_N_INSNS (41), /* int_div_si */
918 COSTS_N_INSNS (41), /* int_div_di */
920 4 /* memory_latency */
937 COSTS_N_INSNS (5), /* int_mult_si */
938 COSTS_N_INSNS (5), /* int_mult_di */
939 COSTS_N_INSNS (72), /* int_div_si */
940 COSTS_N_INSNS (72), /* int_div_di */
942 4 /* memory_latency */
947 COSTS_N_INSNS (6), /* int_mult_si */
948 COSTS_N_INSNS (6), /* int_mult_di */
949 COSTS_N_INSNS (18), /* int_div_si */
950 COSTS_N_INSNS (35), /* int_div_di */
952 4 /* memory_latency */
955 COSTS_N_INSNS (2), /* fp_add */
956 COSTS_N_INSNS (4), /* fp_mult_sf */
957 COSTS_N_INSNS (5), /* fp_mult_df */
958 COSTS_N_INSNS (12), /* fp_div_sf */
959 COSTS_N_INSNS (19), /* fp_div_df */
960 COSTS_N_INSNS (2), /* int_mult_si */
961 COSTS_N_INSNS (2), /* int_mult_di */
962 COSTS_N_INSNS (35), /* int_div_si */
963 COSTS_N_INSNS (35), /* int_div_di */
965 4 /* memory_latency */
968 COSTS_N_INSNS (3), /* fp_add */
969 COSTS_N_INSNS (5), /* fp_mult_sf */
970 COSTS_N_INSNS (6), /* fp_mult_df */
971 COSTS_N_INSNS (15), /* fp_div_sf */
972 COSTS_N_INSNS (16), /* fp_div_df */
973 COSTS_N_INSNS (17), /* int_mult_si */
974 COSTS_N_INSNS (17), /* int_mult_di */
975 COSTS_N_INSNS (38), /* int_div_si */
976 COSTS_N_INSNS (38), /* int_div_di */
978 6 /* memory_latency */
981 COSTS_N_INSNS (6), /* fp_add */
982 COSTS_N_INSNS (7), /* fp_mult_sf */
983 COSTS_N_INSNS (8), /* fp_mult_df */
984 COSTS_N_INSNS (23), /* fp_div_sf */
985 COSTS_N_INSNS (36), /* fp_div_df */
986 COSTS_N_INSNS (10), /* int_mult_si */
987 COSTS_N_INSNS (10), /* int_mult_di */
988 COSTS_N_INSNS (69), /* int_div_si */
989 COSTS_N_INSNS (69), /* int_div_di */
991 6 /* memory_latency */
1003 /* The only costs that appear to be updated here are
1004 integer multiplication. */
1006 COSTS_N_INSNS (4), /* int_mult_si */
1007 COSTS_N_INSNS (6), /* int_mult_di */
1008 COSTS_N_INSNS (69), /* int_div_si */
1009 COSTS_N_INSNS (69), /* int_div_di */
1010 1, /* branch_cost */
1011 4 /* memory_latency */
1026 COSTS_N_INSNS (6), /* fp_add */
1027 COSTS_N_INSNS (4), /* fp_mult_sf */
1028 COSTS_N_INSNS (5), /* fp_mult_df */
1029 COSTS_N_INSNS (23), /* fp_div_sf */
1030 COSTS_N_INSNS (36), /* fp_div_df */
1031 COSTS_N_INSNS (5), /* int_mult_si */
1032 COSTS_N_INSNS (5), /* int_mult_di */
1033 COSTS_N_INSNS (36), /* int_div_si */
1034 COSTS_N_INSNS (36), /* int_div_di */
1035 1, /* branch_cost */
1036 4 /* memory_latency */
1039 COSTS_N_INSNS (6), /* fp_add */
1040 COSTS_N_INSNS (5), /* fp_mult_sf */
1041 COSTS_N_INSNS (6), /* fp_mult_df */
1042 COSTS_N_INSNS (30), /* fp_div_sf */
1043 COSTS_N_INSNS (59), /* fp_div_df */
1044 COSTS_N_INSNS (3), /* int_mult_si */
1045 COSTS_N_INSNS (4), /* int_mult_di */
1046 COSTS_N_INSNS (42), /* int_div_si */
1047 COSTS_N_INSNS (74), /* int_div_di */
1048 1, /* branch_cost */
1049 4 /* memory_latency */
1052 COSTS_N_INSNS (6), /* fp_add */
1053 COSTS_N_INSNS (5), /* fp_mult_sf */
1054 COSTS_N_INSNS (6), /* fp_mult_df */
1055 COSTS_N_INSNS (30), /* fp_div_sf */
1056 COSTS_N_INSNS (59), /* fp_div_df */
1057 COSTS_N_INSNS (5), /* int_mult_si */
1058 COSTS_N_INSNS (9), /* int_mult_di */
1059 COSTS_N_INSNS (42), /* int_div_si */
1060 COSTS_N_INSNS (74), /* int_div_di */
1061 1, /* branch_cost */
1062 4 /* memory_latency */
1065 COSTS_N_INSNS (4), /* fp_add */
1066 COSTS_N_INSNS (4), /* fp_mult_sf */
1067 COSTS_N_INSNS (256), /* fp_mult_df */
1068 COSTS_N_INSNS (8), /* fp_div_sf */
1069 COSTS_N_INSNS (256), /* fp_div_df */
1070 COSTS_N_INSNS (4), /* int_mult_si */
1071 COSTS_N_INSNS (256), /* int_mult_di */
1072 COSTS_N_INSNS (37), /* int_div_si */
1073 COSTS_N_INSNS (256), /* int_div_di */
1074 1, /* branch_cost */
1075 4 /* memory_latency */
1078 /* The only costs that are changed here are
1079 integer multiplication. */
1080 COSTS_N_INSNS (6), /* fp_add */
1081 COSTS_N_INSNS (7), /* fp_mult_sf */
1082 COSTS_N_INSNS (8), /* fp_mult_df */
1083 COSTS_N_INSNS (23), /* fp_div_sf */
1084 COSTS_N_INSNS (36), /* fp_div_df */
1085 COSTS_N_INSNS (5), /* int_mult_si */
1086 COSTS_N_INSNS (9), /* int_mult_di */
1087 COSTS_N_INSNS (69), /* int_div_si */
1088 COSTS_N_INSNS (69), /* int_div_di */
1089 1, /* branch_cost */
1090 4 /* memory_latency */
1096 /* The only costs that are changed here are
1097 integer multiplication. */
1098 COSTS_N_INSNS (6), /* fp_add */
1099 COSTS_N_INSNS (7), /* fp_mult_sf */
1100 COSTS_N_INSNS (8), /* fp_mult_df */
1101 COSTS_N_INSNS (23), /* fp_div_sf */
1102 COSTS_N_INSNS (36), /* fp_div_df */
1103 COSTS_N_INSNS (3), /* int_mult_si */
1104 COSTS_N_INSNS (8), /* int_mult_di */
1105 COSTS_N_INSNS (69), /* int_div_si */
1106 COSTS_N_INSNS (69), /* int_div_di */
1107 1, /* branch_cost */
1108 4 /* memory_latency */
1111 COSTS_N_INSNS (2), /* fp_add */
1112 COSTS_N_INSNS (2), /* fp_mult_sf */
1113 COSTS_N_INSNS (2), /* fp_mult_df */
1114 COSTS_N_INSNS (12), /* fp_div_sf */
1115 COSTS_N_INSNS (19), /* fp_div_df */
1116 COSTS_N_INSNS (5), /* int_mult_si */
1117 COSTS_N_INSNS (9), /* int_mult_di */
1118 COSTS_N_INSNS (34), /* int_div_si */
1119 COSTS_N_INSNS (66), /* int_div_di */
1120 1, /* branch_cost */
1121 4 /* memory_latency */
1124 /* These costs are the same as the SB-1A below. */
1125 COSTS_N_INSNS (4), /* fp_add */
1126 COSTS_N_INSNS (4), /* fp_mult_sf */
1127 COSTS_N_INSNS (4), /* fp_mult_df */
1128 COSTS_N_INSNS (24), /* fp_div_sf */
1129 COSTS_N_INSNS (32), /* fp_div_df */
1130 COSTS_N_INSNS (3), /* int_mult_si */
1131 COSTS_N_INSNS (4), /* int_mult_di */
1132 COSTS_N_INSNS (36), /* int_div_si */
1133 COSTS_N_INSNS (68), /* int_div_di */
1134 1, /* branch_cost */
1135 4 /* memory_latency */
1138 /* These costs are the same as the SB-1 above. */
1139 COSTS_N_INSNS (4), /* fp_add */
1140 COSTS_N_INSNS (4), /* fp_mult_sf */
1141 COSTS_N_INSNS (4), /* fp_mult_df */
1142 COSTS_N_INSNS (24), /* fp_div_sf */
1143 COSTS_N_INSNS (32), /* fp_div_df */
1144 COSTS_N_INSNS (3), /* int_mult_si */
1145 COSTS_N_INSNS (4), /* int_mult_di */
1146 COSTS_N_INSNS (36), /* int_div_si */
1147 COSTS_N_INSNS (68), /* int_div_di */
1148 1, /* branch_cost */
1149 4 /* memory_latency */
1156 COSTS_N_INSNS (8), /* int_mult_si */
1157 COSTS_N_INSNS (8), /* int_mult_di */
1158 COSTS_N_INSNS (72), /* int_div_si */
1159 COSTS_N_INSNS (72), /* int_div_di */
1160 1, /* branch_cost */
1161 4 /* memory_latency */
1164 /* These costs are the same as 5KF above. */
1165 COSTS_N_INSNS (4), /* fp_add */
1166 COSTS_N_INSNS (4), /* fp_mult_sf */
1167 COSTS_N_INSNS (5), /* fp_mult_df */
1168 COSTS_N_INSNS (17), /* fp_div_sf */
1169 COSTS_N_INSNS (32), /* fp_div_df */
1170 COSTS_N_INSNS (4), /* int_mult_si */
1171 COSTS_N_INSNS (11), /* int_mult_di */
1172 COSTS_N_INSNS (36), /* int_div_si */
1173 COSTS_N_INSNS (68), /* int_div_di */
1174 1, /* branch_cost */
1175 4 /* memory_latency */
1179 static rtx
mips_find_pic_call_symbol (rtx
, rtx
, bool);
1180 static int mips_register_move_cost (enum machine_mode
, reg_class_t
,
1182 static unsigned int mips_function_arg_boundary (enum machine_mode
, const_tree
);
1184 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1185 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1186 struct GTY (()) mflip_mips16_entry
{
1190 static GTY ((param_is (struct mflip_mips16_entry
))) htab_t mflip_mips16_htab
;
1192 /* Hash table callbacks for mflip_mips16_htab. */
1195 mflip_mips16_htab_hash (const void *entry
)
1197 return htab_hash_string (((const struct mflip_mips16_entry
*) entry
)->name
);
1201 mflip_mips16_htab_eq (const void *entry
, const void *name
)
1203 return strcmp (((const struct mflip_mips16_entry
*) entry
)->name
,
1204 (const char *) name
) == 0;
1207 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1208 mode, false if it should next add an attribute for the opposite mode. */
1209 static GTY(()) bool mips16_flipper
;
1211 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1212 for -mflip-mips16. Return true if it should use "mips16" and false if
1213 it should use "nomips16". */
1216 mflip_mips16_use_mips16_p (tree decl
)
1218 struct mflip_mips16_entry
*entry
;
1222 bool base_is_mips16
= (mips_base_compression_flags
& MASK_MIPS16
) != 0;
1224 /* Use the opposite of the command-line setting for anonymous decls. */
1225 if (!DECL_NAME (decl
))
1226 return !base_is_mips16
;
1228 if (!mflip_mips16_htab
)
1229 mflip_mips16_htab
= htab_create_ggc (37, mflip_mips16_htab_hash
,
1230 mflip_mips16_htab_eq
, NULL
);
1232 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1233 hash
= htab_hash_string (name
);
1234 slot
= htab_find_slot_with_hash (mflip_mips16_htab
, name
, hash
, INSERT
);
1235 entry
= (struct mflip_mips16_entry
*) *slot
;
1238 mips16_flipper
= !mips16_flipper
;
1239 entry
= ggc_alloc_mflip_mips16_entry ();
1241 entry
->mips16_p
= mips16_flipper
? !base_is_mips16
: base_is_mips16
;
1244 return entry
->mips16_p
;
1247 /* Predicates to test for presence of "near" and "far"/"long_call"
1248 attributes on the given TYPE. */
1251 mips_near_type_p (const_tree type
)
1253 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1257 mips_far_type_p (const_tree type
)
1259 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1260 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1264 /* Check if the interrupt attribute is set for a function. */
1267 mips_interrupt_type_p (tree type
)
1269 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1272 /* Check if the attribute to use shadow register set is set for a function. */
1275 mips_use_shadow_register_set_p (tree type
)
1277 return lookup_attribute ("use_shadow_register_set",
1278 TYPE_ATTRIBUTES (type
)) != NULL
;
1281 /* Check if the attribute to keep interrupts masked is set for a function. */
1284 mips_keep_interrupts_masked_p (tree type
)
1286 return lookup_attribute ("keep_interrupts_masked",
1287 TYPE_ATTRIBUTES (type
)) != NULL
;
1290 /* Check if the attribute to use debug exception return is set for
1294 mips_use_debug_exception_return_p (tree type
)
1296 return lookup_attribute ("use_debug_exception_return",
1297 TYPE_ATTRIBUTES (type
)) != NULL
;
1300 /* Return the set of compression modes that are explicitly required
1301 by the attributes in ATTRIBUTES. */
1304 mips_get_compress_on_flags (tree attributes
)
1306 unsigned int flags
= 0;
1308 if (lookup_attribute ("mips16", attributes
) != NULL
)
1309 flags
|= MASK_MIPS16
;
1311 if (lookup_attribute ("micromips", attributes
) != NULL
)
1312 flags
|= MASK_MICROMIPS
;
1317 /* Return the set of compression modes that are explicitly forbidden
1318 by the attributes in ATTRIBUTES. */
1321 mips_get_compress_off_flags (tree attributes
)
1323 unsigned int flags
= 0;
1325 if (lookup_attribute ("nocompression", attributes
) != NULL
)
1326 flags
|= MASK_MIPS16
| MASK_MICROMIPS
;
1328 if (lookup_attribute ("nomips16", attributes
) != NULL
)
1329 flags
|= MASK_MIPS16
;
1331 if (lookup_attribute ("nomicromips", attributes
) != NULL
)
1332 flags
|= MASK_MICROMIPS
;
1337 /* Return the compression mode that should be used for function DECL.
1338 Return the ambient setting if DECL is null. */
1341 mips_get_compress_mode (tree decl
)
1343 unsigned int flags
, force_on
;
1345 flags
= mips_base_compression_flags
;
1348 /* Nested functions must use the same frame pointer as their
1349 parent and must therefore use the same ISA mode. */
1350 tree parent
= decl_function_context (decl
);
1353 force_on
= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1356 flags
&= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1361 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1365 mips_get_compress_on_name (unsigned int flags
)
1367 if (flags
== MASK_MIPS16
)
1372 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1376 mips_get_compress_off_name (unsigned int flags
)
1378 if (flags
== MASK_MIPS16
)
1380 if (flags
== MASK_MICROMIPS
)
1381 return "nomicromips";
1382 return "nocompression";
1385 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1388 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1390 /* Disallow mixed near/far attributes. */
1391 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1393 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1398 /* Implement TARGET_INSERT_ATTRIBUTES. */
1401 mips_insert_attributes (tree decl
, tree
*attributes
)
1404 unsigned int compression_flags
, nocompression_flags
;
1406 /* Check for "mips16" and "nomips16" attributes. */
1407 compression_flags
= mips_get_compress_on_flags (*attributes
);
1408 nocompression_flags
= mips_get_compress_off_flags (*attributes
);
1410 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1412 if (nocompression_flags
)
1413 error ("%qs attribute only applies to functions",
1414 mips_get_compress_off_name (nocompression_flags
));
1416 if (compression_flags
)
1417 error ("%qs attribute only applies to functions",
1418 mips_get_compress_on_name (nocompression_flags
));
1422 compression_flags
|= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1423 nocompression_flags
|=
1424 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1426 if (compression_flags
&& nocompression_flags
)
1427 error ("%qE cannot have both %qs and %qs attributes",
1428 DECL_NAME (decl
), mips_get_compress_on_name (compression_flags
),
1429 mips_get_compress_off_name (nocompression_flags
));
1431 if (compression_flags
& MASK_MIPS16
1432 && compression_flags
& MASK_MICROMIPS
)
1433 error ("%qE cannot have both %qs and %qs attributes",
1434 DECL_NAME (decl
), "mips16", "micromips");
1436 if (TARGET_FLIP_MIPS16
1437 && !DECL_ARTIFICIAL (decl
)
1438 && compression_flags
== 0
1439 && nocompression_flags
== 0)
1441 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1442 "mips16" attribute, arbitrarily pick one. We must pick the same
1443 setting for duplicate declarations of a function. */
1444 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1445 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1446 name
= "nomicromips";
1447 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1452 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1455 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1459 diff
= (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl
))
1460 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl
)));
1462 error ("%qE redeclared with conflicting %qs attributes",
1463 DECL_NAME (newdecl
), mips_get_compress_on_name (diff
));
1465 diff
= (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl
))
1466 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl
)));
1468 error ("%qE redeclared with conflicting %qs attributes",
1469 DECL_NAME (newdecl
), mips_get_compress_off_name (diff
));
1471 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1472 DECL_ATTRIBUTES (newdecl
));
1475 /* Implement TARGET_CAN_INLINE_P. */
1478 mips_can_inline_p (tree caller
, tree callee
)
1480 if (mips_get_compress_mode (callee
) != mips_get_compress_mode (caller
))
1482 return default_target_can_inline_p (caller
, callee
);
1485 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1486 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1489 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1491 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
1493 *base_ptr
= XEXP (x
, 0);
1494 *offset_ptr
= INTVAL (XEXP (x
, 1));
1503 static unsigned int mips_build_integer (struct mips_integer_op
*,
1504 unsigned HOST_WIDE_INT
);
1506 /* A subroutine of mips_build_integer, with the same interface.
1507 Assume that the final action in the sequence should be a left shift. */
1510 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1512 unsigned int i
, shift
;
1514 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1515 since signed numbers are easier to load than unsigned ones. */
1517 while ((value
& 1) == 0)
1518 value
/= 2, shift
++;
1520 i
= mips_build_integer (codes
, value
);
1521 codes
[i
].code
= ASHIFT
;
1522 codes
[i
].value
= shift
;
1526 /* As for mips_build_shift, but assume that the final action will be
1527 an IOR or PLUS operation. */
1530 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1532 unsigned HOST_WIDE_INT high
;
1535 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1536 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1538 /* The constant is too complex to load with a simple LUI/ORI pair,
1539 so we want to give the recursive call as many trailing zeros as
1540 possible. In this case, we know bit 16 is set and that the
1541 low 16 bits form a negative number. If we subtract that number
1542 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1543 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1544 codes
[i
].code
= PLUS
;
1545 codes
[i
].value
= CONST_LOW_PART (value
);
1549 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1550 bits gives a value with at least 17 trailing zeros. */
1551 i
= mips_build_integer (codes
, high
);
1552 codes
[i
].code
= IOR
;
1553 codes
[i
].value
= value
& 0xffff;
1558 /* Fill CODES with a sequence of rtl operations to load VALUE.
1559 Return the number of operations needed. */
1562 mips_build_integer (struct mips_integer_op
*codes
,
1563 unsigned HOST_WIDE_INT value
)
1565 if (SMALL_OPERAND (value
)
1566 || SMALL_OPERAND_UNSIGNED (value
)
1567 || LUI_OPERAND (value
))
1569 /* The value can be loaded with a single instruction. */
1570 codes
[0].code
= UNKNOWN
;
1571 codes
[0].value
= value
;
1574 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1576 /* Either the constant is a simple LUI/ORI combination or its
1577 lowest bit is set. We don't want to shift in this case. */
1578 return mips_build_lower (codes
, value
);
1580 else if ((value
& 0xffff) == 0)
1582 /* The constant will need at least three actions. The lowest
1583 16 bits are clear, so the final action will be a shift. */
1584 return mips_build_shift (codes
, value
);
1588 /* The final action could be a shift, add or inclusive OR.
1589 Rather than use a complex condition to select the best
1590 approach, try both mips_build_shift and mips_build_lower
1591 and pick the one that gives the shortest sequence.
1592 Note that this case is only used once per constant. */
1593 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1594 unsigned int cost
, alt_cost
;
1596 cost
= mips_build_shift (codes
, value
);
1597 alt_cost
= mips_build_lower (alt_codes
, value
);
1598 if (alt_cost
< cost
)
1600 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1607 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1610 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1612 return mips_const_insns (x
) > 0;
1615 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1618 mips16_stub_function (const char *name
)
1622 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
1623 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
1627 /* Return a legitimate call address for STUB, given that STUB is a MIPS16
1628 support function. */
1631 mips16_stub_call_address (mips_one_only_stub
*stub
)
1633 rtx fn
= mips16_stub_function (stub
->get_name ());
1634 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_LOCAL
;
1635 if (!call_insn_operand (fn
, VOIDmode
))
1636 fn
= force_reg (Pmode
, fn
);
1640 /* A stub for moving the thread pointer into TLS_GET_TP_REGNUM. */
1642 class mips16_rdhwr_one_only_stub
: public mips_one_only_stub
1644 virtual const char *get_name ();
1645 virtual void output_body ();
1649 mips16_rdhwr_one_only_stub::get_name ()
1651 return "__mips16_rdhwr";
1655 mips16_rdhwr_one_only_stub::output_body ()
1657 fprintf (asm_out_file
,
1659 "\t.set\tmips32r2\n"
1660 "\t.set\tnoreorder\n"
1666 /* A stub for moving the FCSR into GET_FCSR_REGNUM. */
1667 class mips16_get_fcsr_one_only_stub
: public mips_one_only_stub
1669 virtual const char *get_name ();
1670 virtual void output_body ();
1674 mips16_get_fcsr_one_only_stub::get_name ()
1676 return "__mips16_get_fcsr";
1680 mips16_get_fcsr_one_only_stub::output_body ()
1682 fprintf (asm_out_file
,
1684 "\tj\t$31\n", reg_names
[GET_FCSR_REGNUM
]);
1687 /* A stub for moving SET_FCSR_REGNUM into the FCSR. */
1688 class mips16_set_fcsr_one_only_stub
: public mips_one_only_stub
1690 virtual const char *get_name ();
1691 virtual void output_body ();
1695 mips16_set_fcsr_one_only_stub::get_name ()
1697 return "__mips16_set_fcsr";
1701 mips16_set_fcsr_one_only_stub::output_body ()
1703 fprintf (asm_out_file
,
1705 "\tj\t$31\n", reg_names
[SET_FCSR_REGNUM
]);
1708 /* Return true if symbols of type TYPE require a GOT access. */
1711 mips_got_symbol_type_p (enum mips_symbol_type type
)
1715 case SYMBOL_GOT_PAGE_OFST
:
1716 case SYMBOL_GOT_DISP
:
1724 /* Return true if X is a thread-local symbol. */
1727 mips_tls_symbol_p (rtx x
)
1729 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1732 /* Return true if SYMBOL_REF X is associated with a global symbol
1733 (in the STB_GLOBAL sense). */
1736 mips_global_symbol_p (const_rtx x
)
1738 const_tree decl
= SYMBOL_REF_DECL (x
);
1741 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1743 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1744 or weak symbols. Relocations in the object file will be against
1745 the target symbol, so it's that symbol's binding that matters here. */
1746 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1749 /* Return true if function X is a libgcc MIPS16 stub function. */
1752 mips16_stub_function_p (const_rtx x
)
1754 return (GET_CODE (x
) == SYMBOL_REF
1755 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1758 /* Return true if function X is a locally-defined and locally-binding
1762 mips16_local_function_p (const_rtx x
)
1764 return (GET_CODE (x
) == SYMBOL_REF
1765 && SYMBOL_REF_LOCAL_P (x
)
1766 && !SYMBOL_REF_EXTERNAL_P (x
)
1767 && (mips_get_compress_mode (SYMBOL_REF_DECL (x
)) & MASK_MIPS16
));
1770 /* Return true if SYMBOL_REF X binds locally. */
1773 mips_symbol_binds_local_p (const_rtx x
)
1775 return (SYMBOL_REF_DECL (x
)
1776 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1777 : SYMBOL_REF_LOCAL_P (x
));
1780 /* Return true if rtx constants of mode MODE should be put into a small
1784 mips_rtx_constant_in_small_data_p (enum machine_mode mode
)
1786 return (!TARGET_EMBEDDED_DATA
1787 && TARGET_LOCAL_SDATA
1788 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1791 /* Return true if X should not be moved directly into register $25.
1792 We need this because many versions of GAS will treat "la $25,foo" as
1793 part of a call sequence and so allow a global "foo" to be lazily bound. */
1796 mips_dangerous_for_la25_p (rtx x
)
1798 return (!TARGET_EXPLICIT_RELOCS
1800 && GET_CODE (x
) == SYMBOL_REF
1801 && mips_global_symbol_p (x
));
1804 /* Return true if calls to X might need $25 to be valid on entry. */
1807 mips_use_pic_fn_addr_reg_p (const_rtx x
)
1809 if (!TARGET_USE_PIC_FN_ADDR_REG
)
1812 /* MIPS16 stub functions are guaranteed not to use $25. */
1813 if (mips16_stub_function_p (x
))
1816 if (GET_CODE (x
) == SYMBOL_REF
)
1818 /* If PLTs and copy relocations are available, the static linker
1819 will make sure that $25 is valid on entry to the target function. */
1820 if (TARGET_ABICALLS_PIC0
)
1823 /* Locally-defined functions use absolute accesses to set up
1824 the global pointer. */
1825 if (TARGET_ABSOLUTE_ABICALLS
1826 && mips_symbol_binds_local_p (x
)
1827 && !SYMBOL_REF_EXTERNAL_P (x
))
1834 /* Return the method that should be used to access SYMBOL_REF or
1835 LABEL_REF X in context CONTEXT. */
1837 static enum mips_symbol_type
1838 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1841 return SYMBOL_GOT_DISP
;
1843 if (GET_CODE (x
) == LABEL_REF
)
1845 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1846 code and if we know that the label is in the current function's
1847 text section. LABEL_REFs are used for jump tables as well as
1848 text labels, so we must check whether jump tables live in the
1850 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1851 && !LABEL_REF_NONLOCAL_P (x
))
1852 return SYMBOL_PC_RELATIVE
;
1854 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1855 return SYMBOL_GOT_PAGE_OFST
;
1857 return SYMBOL_ABSOLUTE
;
1860 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1862 if (SYMBOL_REF_TLS_MODEL (x
))
1865 if (CONSTANT_POOL_ADDRESS_P (x
))
1867 if (TARGET_MIPS16_TEXT_LOADS
)
1868 return SYMBOL_PC_RELATIVE
;
1870 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1871 return SYMBOL_PC_RELATIVE
;
1873 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1874 return SYMBOL_GP_RELATIVE
;
1877 /* Do not use small-data accesses for weak symbols; they may end up
1879 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
1880 return SYMBOL_GP_RELATIVE
;
1882 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1884 if (TARGET_ABICALLS_PIC2
1885 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1887 /* There are three cases to consider:
1889 - o32 PIC (either with or without explicit relocs)
1890 - n32/n64 PIC without explicit relocs
1891 - n32/n64 PIC with explicit relocs
1893 In the first case, both local and global accesses will use an
1894 R_MIPS_GOT16 relocation. We must correctly predict which of
1895 the two semantics (local or global) the assembler and linker
1896 will apply. The choice depends on the symbol's binding rather
1897 than its visibility.
1899 In the second case, the assembler will not use R_MIPS_GOT16
1900 relocations, but it chooses between local and global accesses
1901 in the same way as for o32 PIC.
1903 In the third case we have more freedom since both forms of
1904 access will work for any kind of symbol. However, there seems
1905 little point in doing things differently. */
1906 if (mips_global_symbol_p (x
))
1907 return SYMBOL_GOT_DISP
;
1909 return SYMBOL_GOT_PAGE_OFST
;
1912 return SYMBOL_ABSOLUTE
;
1915 /* Classify the base of symbolic expression X, given that X appears in
1918 static enum mips_symbol_type
1919 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
1923 split_const (x
, &x
, &offset
);
1924 if (UNSPEC_ADDRESS_P (x
))
1925 return UNSPEC_ADDRESS_TYPE (x
);
1927 return mips_classify_symbol (x
, context
);
1930 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1931 is the alignment in bytes of SYMBOL_REF X. */
1934 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
1936 HOST_WIDE_INT align
;
1938 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
1939 return IN_RANGE (offset
, 0, align
- 1);
1942 /* Return true if X is a symbolic constant that can be used in context
1943 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1946 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
1947 enum mips_symbol_type
*symbol_type
)
1951 split_const (x
, &x
, &offset
);
1952 if (UNSPEC_ADDRESS_P (x
))
1954 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
1955 x
= UNSPEC_ADDRESS (x
);
1957 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1959 *symbol_type
= mips_classify_symbol (x
, context
);
1960 if (*symbol_type
== SYMBOL_TLS
)
1966 if (offset
== const0_rtx
)
1969 /* Check whether a nonzero offset is valid for the underlying
1971 switch (*symbol_type
)
1973 case SYMBOL_ABSOLUTE
:
1974 case SYMBOL_64_HIGH
:
1977 /* If the target has 64-bit pointers and the object file only
1978 supports 32-bit symbols, the values of those symbols will be
1979 sign-extended. In this case we can't allow an arbitrary offset
1980 in case the 32-bit value X + OFFSET has a different sign from X. */
1981 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
1982 return offset_within_block_p (x
, INTVAL (offset
));
1984 /* In other cases the relocations can handle any offset. */
1987 case SYMBOL_PC_RELATIVE
:
1988 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1989 In this case, we no longer have access to the underlying constant,
1990 but the original symbol-based access was known to be valid. */
1991 if (GET_CODE (x
) == LABEL_REF
)
1996 case SYMBOL_GP_RELATIVE
:
1997 /* Make sure that the offset refers to something within the
1998 same object block. This should guarantee that the final
1999 PC- or GP-relative offset is within the 16-bit limit. */
2000 return offset_within_block_p (x
, INTVAL (offset
));
2002 case SYMBOL_GOT_PAGE_OFST
:
2003 case SYMBOL_GOTOFF_PAGE
:
2004 /* If the symbol is global, the GOT entry will contain the symbol's
2005 address, and we will apply a 16-bit offset after loading it.
2006 If the symbol is local, the linker should provide enough local
2007 GOT entries for a 16-bit offset, but larger offsets may lead
2009 return SMALL_INT (offset
);
2013 /* There is no carry between the HI and LO REL relocations, so the
2014 offset is only valid if we know it won't lead to such a carry. */
2015 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
2017 case SYMBOL_GOT_DISP
:
2018 case SYMBOL_GOTOFF_DISP
:
2019 case SYMBOL_GOTOFF_CALL
:
2020 case SYMBOL_GOTOFF_LOADGP
:
2023 case SYMBOL_GOTTPREL
:
2031 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
2032 single instruction. We rely on the fact that, in the worst case,
2033 all instructions involved in a MIPS16 address calculation are usually
2037 mips_symbol_insns_1 (enum mips_symbol_type type
, enum machine_mode mode
)
2039 if (mips_use_pcrel_pool_p
[(int) type
])
2041 if (mode
== MAX_MACHINE_MODE
)
2042 /* LEAs will be converted into constant-pool references by
2044 type
= SYMBOL_PC_RELATIVE
;
2046 /* The constant must be loaded and then dereferenced. */
2052 case SYMBOL_ABSOLUTE
:
2053 /* When using 64-bit symbols, we need 5 preparatory instructions,
2056 lui $at,%highest(symbol)
2057 daddiu $at,$at,%higher(symbol)
2059 daddiu $at,$at,%hi(symbol)
2062 The final address is then $at + %lo(symbol). With 32-bit
2063 symbols we just need a preparatory LUI for normal mode and
2064 a preparatory LI and SLL for MIPS16. */
2065 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
2067 case SYMBOL_GP_RELATIVE
:
2068 /* Treat GP-relative accesses as taking a single instruction on
2069 MIPS16 too; the copy of $gp can often be shared. */
2072 case SYMBOL_PC_RELATIVE
:
2073 /* PC-relative constants can be only be used with ADDIUPC,
2074 DADDIUPC, LWPC and LDPC. */
2075 if (mode
== MAX_MACHINE_MODE
2076 || GET_MODE_SIZE (mode
) == 4
2077 || GET_MODE_SIZE (mode
) == 8)
2080 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
2083 case SYMBOL_GOT_DISP
:
2084 /* The constant will have to be loaded from the GOT before it
2085 is used in an address. */
2086 if (mode
!= MAX_MACHINE_MODE
)
2091 case SYMBOL_GOT_PAGE_OFST
:
2092 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
2093 local/global classification is accurate. The worst cases are:
2095 (1) For local symbols when generating o32 or o64 code. The assembler
2101 ...and the final address will be $at + %lo(symbol).
2103 (2) For global symbols when -mxgot. The assembler will use:
2105 lui $at,%got_hi(symbol)
2108 ...and the final address will be $at + %got_lo(symbol). */
2111 case SYMBOL_GOTOFF_PAGE
:
2112 case SYMBOL_GOTOFF_DISP
:
2113 case SYMBOL_GOTOFF_CALL
:
2114 case SYMBOL_GOTOFF_LOADGP
:
2115 case SYMBOL_64_HIGH
:
2121 case SYMBOL_GOTTPREL
:
2124 /* A 16-bit constant formed by a single relocation, or a 32-bit
2125 constant formed from a high 16-bit relocation and a low 16-bit
2126 relocation. Use mips_split_p to determine which. 32-bit
2127 constants need an "lui; addiu" sequence for normal mode and
2128 an "li; sll; addiu" sequence for MIPS16 mode. */
2129 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
2132 /* We don't treat a bare TLS symbol as a constant. */
2138 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2139 to load symbols of type TYPE into a register. Return 0 if the given
2140 type of symbol cannot be used as an immediate operand.
2142 Otherwise, return the number of instructions needed to load or store
2143 values of mode MODE to or from addresses of type TYPE. Return 0 if
2144 the given type of symbol is not valid in addresses.
2146 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2149 mips_symbol_insns (enum mips_symbol_type type
, enum machine_mode mode
)
2151 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
2154 /* A for_each_rtx callback. Stop the search if *X references a
2155 thread-local symbol. */
2158 mips_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
2160 return mips_tls_symbol_p (*x
);
2163 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2166 mips_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
2168 enum mips_symbol_type type
;
2171 /* There is no assembler syntax for expressing an address-sized
2173 if (GET_CODE (x
) == HIGH
)
2176 /* As an optimization, reject constants that mips_legitimize_move
2179 Suppose we have a multi-instruction sequence that loads constant C
2180 into register R. If R does not get allocated a hard register, and
2181 R is used in an operand that allows both registers and memory
2182 references, reload will consider forcing C into memory and using
2183 one of the instruction's memory alternatives. Returning false
2184 here will force it to use an input reload instead. */
2185 if (CONST_INT_P (x
) && mips_legitimate_constant_p (mode
, x
))
2188 split_const (x
, &base
, &offset
);
2189 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
))
2191 /* See whether we explicitly want these symbols in the pool. */
2192 if (mips_use_pcrel_pool_p
[(int) type
])
2195 /* The same optimization as for CONST_INT. */
2196 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
2199 /* If MIPS16 constant pools live in the text section, they should
2200 not refer to anything that might need run-time relocation. */
2201 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
2205 /* TLS symbols must be computed by mips_legitimize_move. */
2206 if (for_each_rtx (&x
, &mips_tls_symbol_ref_1
, NULL
))
2212 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2213 constants when we're using a per-function constant pool. */
2216 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2217 const_rtx x ATTRIBUTE_UNUSED
)
2219 return !TARGET_MIPS16_PCREL_LOADS
;
2222 /* Return true if register REGNO is a valid base register for mode MODE.
2223 STRICT_P is true if REG_OK_STRICT is in effect. */
2226 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
,
2229 if (!HARD_REGISTER_NUM_P (regno
))
2233 regno
= reg_renumber
[regno
];
2236 /* These fake registers will be eliminated to either the stack or
2237 hard frame pointer, both of which are usually valid base registers.
2238 Reload deals with the cases where the eliminated form isn't valid. */
2239 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
2242 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2243 values, nothing smaller. There are two problems here:
2245 (a) Instantiating virtual registers can introduce new uses of the
2246 stack pointer. If these virtual registers are valid addresses,
2247 the stack pointer should be too.
2249 (b) Most uses of the stack pointer are not made explicit until
2250 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2251 We don't know until that stage whether we'll be eliminating to the
2252 stack pointer (which needs the restriction) or the hard frame
2253 pointer (which doesn't).
2255 All in all, it seems more consistent to only enforce this restriction
2256 during and after reload. */
2257 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
2258 return !strict_p
|| GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
2260 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
2263 /* Return true if X is a valid base register for mode MODE.
2264 STRICT_P is true if REG_OK_STRICT is in effect. */
2267 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, bool strict_p
)
2269 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2273 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
2276 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2277 can address a value of mode MODE. */
2280 mips_valid_offset_p (rtx x
, enum machine_mode mode
)
2282 /* Check that X is a signed 16-bit number. */
2283 if (!const_arith_operand (x
, Pmode
))
2286 /* We may need to split multiword moves, so make sure that every word
2288 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2289 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2295 /* Return true if a LO_SUM can address a value of mode MODE when the
2296 LO_SUM symbol has type SYMBOL_TYPE. */
2299 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, enum machine_mode mode
)
2301 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2303 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2306 /* Check that there is a known low-part relocation. */
2307 if (mips_lo_relocs
[symbol_type
] == NULL
)
2310 /* We may need to split multiword moves, so make sure that each word
2311 can be accessed without inducing a carry. This is mainly needed
2312 for o64, which has historically only guaranteed 64-bit alignment
2313 for 128-bit types. */
2314 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2315 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2321 /* Return true if X is a valid address for machine mode MODE. If it is,
2322 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2326 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2327 enum machine_mode mode
, bool strict_p
)
2329 switch (GET_CODE (x
))
2333 info
->type
= ADDRESS_REG
;
2335 info
->offset
= const0_rtx
;
2336 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2339 info
->type
= ADDRESS_REG
;
2340 info
->reg
= XEXP (x
, 0);
2341 info
->offset
= XEXP (x
, 1);
2342 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2343 && mips_valid_offset_p (info
->offset
, mode
));
2346 info
->type
= ADDRESS_LO_SUM
;
2347 info
->reg
= XEXP (x
, 0);
2348 info
->offset
= XEXP (x
, 1);
2349 /* We have to trust the creator of the LO_SUM to do something vaguely
2350 sane. Target-independent code that creates a LO_SUM should also
2351 create and verify the matching HIGH. Target-independent code that
2352 adds an offset to a LO_SUM must prove that the offset will not
2353 induce a carry. Failure to do either of these things would be
2354 a bug, and we are not required to check for it here. The MIPS
2355 backend itself should only create LO_SUMs for valid symbolic
2356 constants, with the high part being either a HIGH or a copy
2359 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2360 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2361 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2364 /* Small-integer addresses don't occur very often, but they
2365 are legitimate if $0 is a valid base register. */
2366 info
->type
= ADDRESS_CONST_INT
;
2367 return !TARGET_MIPS16
&& SMALL_INT (x
);
2372 info
->type
= ADDRESS_SYMBOLIC
;
2373 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2375 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2376 && !mips_split_p
[info
->symbol_type
]);
2383 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2386 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2388 struct mips_address_info addr
;
2390 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2393 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2396 mips_stack_address_p (rtx x
, enum machine_mode mode
)
2398 struct mips_address_info addr
;
2400 return (mips_classify_address (&addr
, x
, mode
, false)
2401 && addr
.type
== ADDRESS_REG
2402 && addr
.reg
== stack_pointer_rtx
);
2405 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2406 address instruction. Note that such addresses are not considered
2407 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2408 is so restricted. */
2411 mips_lwxs_address_p (rtx addr
)
2414 && GET_CODE (addr
) == PLUS
2415 && REG_P (XEXP (addr
, 1)))
2417 rtx offset
= XEXP (addr
, 0);
2418 if (GET_CODE (offset
) == MULT
2419 && REG_P (XEXP (offset
, 0))
2420 && CONST_INT_P (XEXP (offset
, 1))
2421 && INTVAL (XEXP (offset
, 1)) == 4)
2427 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2428 indexed address instruction. Note that such addresses are
2429 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2430 sense, because their use is so restricted. */
2433 mips_lx_address_p (rtx addr
, enum machine_mode mode
)
2435 if (GET_CODE (addr
) != PLUS
2436 || !REG_P (XEXP (addr
, 0))
2437 || !REG_P (XEXP (addr
, 1)))
2439 if (ISA_HAS_LBX
&& mode
== QImode
)
2441 if (ISA_HAS_LHX
&& mode
== HImode
)
2443 if (ISA_HAS_LWX
&& mode
== SImode
)
2445 if (ISA_HAS_LDX
&& mode
== DImode
)
2450 /* Return true if a value at OFFSET bytes from base register BASE can be
2451 accessed using an unextended MIPS16 instruction. MODE is the mode of
2454 Usually the offset in an unextended instruction is a 5-bit field.
2455 The offset is unsigned and shifted left once for LH and SH, twice
2456 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2457 an 8-bit immediate field that's shifted left twice. */
2460 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
,
2461 unsigned HOST_WIDE_INT offset
)
2463 if (mode
!= BLKmode
&& offset
% GET_MODE_SIZE (mode
) == 0)
2465 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2466 return offset
< 256U * GET_MODE_SIZE (mode
);
2467 return offset
< 32U * GET_MODE_SIZE (mode
);
2472 /* Return the number of instructions needed to load or store a value
2473 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2474 length of one instruction. Return 0 if X isn't valid for MODE.
2475 Assume that multiword moves may need to be split into word moves
2476 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2480 mips_address_insns (rtx x
, enum machine_mode mode
, bool might_split_p
)
2482 struct mips_address_info addr
;
2485 /* BLKmode is used for single unaligned loads and stores and should
2486 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2487 meaningless, so we have to single it out as a special case one way
2489 if (mode
!= BLKmode
&& might_split_p
)
2490 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2494 if (mips_classify_address (&addr
, x
, mode
, false))
2499 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2500 UINTVAL (addr
.offset
)))
2504 case ADDRESS_LO_SUM
:
2505 return TARGET_MIPS16
? factor
* 2 : factor
;
2507 case ADDRESS_CONST_INT
:
2510 case ADDRESS_SYMBOLIC
:
2511 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2516 /* Return true if X fits within an unsigned field of BITS bits that is
2517 shifted left SHIFT bits before being used. */
2520 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2522 return (x
& ((1 << shift
) - 1)) == 0 && x
< ((unsigned) 1 << (shift
+ bits
));
2525 /* Return true if X fits within a signed field of BITS bits that is
2526 shifted left SHIFT bits before being used. */
2529 mips_signed_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2531 x
+= 1 << (bits
+ shift
- 1);
2532 return mips_unsigned_immediate_p (x
, bits
, shift
);
2535 /* Return true if X is legitimate for accessing values of mode MODE,
2536 if it is based on a MIPS16 register, and if the offset satisfies
2537 OFFSET_PREDICATE. */
2540 m16_based_address_p (rtx x
, enum machine_mode mode
,
2541 insn_operand_predicate_fn offset_predicate
)
2543 struct mips_address_info addr
;
2545 return (mips_classify_address (&addr
, x
, mode
, false)
2546 && addr
.type
== ADDRESS_REG
2547 && M16_REG_P (REGNO (addr
.reg
))
2548 && offset_predicate (addr
.offset
, mode
));
2551 /* Return true if X is a legitimate address that conforms to the requirements
2552 for a microMIPS LWSP or SWSP insn. */
2555 lwsp_swsp_address_p (rtx x
, enum machine_mode mode
)
2557 struct mips_address_info addr
;
2559 return (mips_classify_address (&addr
, x
, mode
, false)
2560 && addr
.type
== ADDRESS_REG
2561 && REGNO (addr
.reg
) == STACK_POINTER_REGNUM
2562 && uw5_operand (addr
.offset
, mode
));
2565 /* Return true if X is a legitimate address with a 12-bit offset.
2566 MODE is the mode of the value being accessed. */
2569 umips_12bit_offset_address_p (rtx x
, enum machine_mode mode
)
2571 struct mips_address_info addr
;
2573 return (mips_classify_address (&addr
, x
, mode
, false)
2574 && addr
.type
== ADDRESS_REG
2575 && CONST_INT_P (addr
.offset
)
2576 && UMIPS_12BIT_OFFSET_P (INTVAL (addr
.offset
)));
2579 /* Return the number of instructions needed to load constant X,
2580 assuming that BASE_INSN_LENGTH is the length of one instruction.
2581 Return 0 if X isn't a valid constant. */
2584 mips_const_insns (rtx x
)
2586 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2587 enum mips_symbol_type symbol_type
;
2590 switch (GET_CODE (x
))
2593 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2595 || !mips_split_p
[symbol_type
])
2598 /* This is simply an LUI for normal mode. It is an extended
2599 LI followed by an extended SLL for MIPS16. */
2600 return TARGET_MIPS16
? 4 : 1;
2604 /* Unsigned 8-bit constants can be loaded using an unextended
2605 LI instruction. Unsigned 16-bit constants can be loaded
2606 using an extended LI. Negative constants must be loaded
2607 using LI and then negated. */
2608 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2609 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2610 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2611 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2614 return mips_build_integer (codes
, INTVAL (x
));
2618 /* Allow zeros for normal mode, where we can use $0. */
2619 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2625 /* See if we can refer to X directly. */
2626 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2627 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2629 /* Otherwise try splitting the constant into a base and offset.
2630 If the offset is a 16-bit value, we can load the base address
2631 into a register and then use (D)ADDIU to add in the offset.
2632 If the offset is larger, we can load the base and offset
2633 into separate registers and add them together with (D)ADDU.
2634 However, the latter is only possible before reload; during
2635 and after reload, we must have the option of forcing the
2636 constant into the pool instead. */
2637 split_const (x
, &x
, &offset
);
2640 int n
= mips_const_insns (x
);
2643 if (SMALL_INT (offset
))
2645 else if (!targetm
.cannot_force_const_mem (GET_MODE (x
), x
))
2646 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2653 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2661 /* X is a doubleword constant that can be handled by splitting it into
2662 two words and loading each word separately. Return the number of
2663 instructions required to do this, assuming that BASE_INSN_LENGTH
2664 is the length of one instruction. */
2667 mips_split_const_insns (rtx x
)
2669 unsigned int low
, high
;
2671 low
= mips_const_insns (mips_subword (x
, false));
2672 high
= mips_const_insns (mips_subword (x
, true));
2673 gcc_assert (low
> 0 && high
> 0);
2677 /* Return the number of instructions needed to implement INSN,
2678 given that it loads from or stores to MEM. Assume that
2679 BASE_INSN_LENGTH is the length of one instruction. */
2682 mips_load_store_insns (rtx mem
, rtx insn
)
2684 enum machine_mode mode
;
2688 gcc_assert (MEM_P (mem
));
2689 mode
= GET_MODE (mem
);
2691 /* Try to prove that INSN does not need to be split. */
2692 might_split_p
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
;
2695 set
= single_set (insn
);
2696 if (set
&& !mips_split_move_insn_p (SET_DEST (set
), SET_SRC (set
), insn
))
2697 might_split_p
= false;
2700 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2703 /* Return the number of instructions needed for an integer division,
2704 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2707 mips_idiv_insns (void)
2712 if (TARGET_CHECK_ZERO_DIV
)
2714 if (GENERATE_DIVIDE_TRAPS
)
2720 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2725 /* Emit a move from SRC to DEST. Assume that the move expanders can
2726 handle all moves if !can_create_pseudo_p (). The distinction is
2727 important because, unlike emit_move_insn, the move expanders know
2728 how to force Pmode objects into the constant pool even when the
2729 constant pool address is not itself legitimate. */
2732 mips_emit_move (rtx dest
, rtx src
)
2734 return (can_create_pseudo_p ()
2735 ? emit_move_insn (dest
, src
)
2736 : emit_move_insn_1 (dest
, src
));
2739 /* Emit a move from SRC to DEST, splitting compound moves into individual
2740 instructions. SPLIT_TYPE is the type of split to perform. */
2743 mips_emit_move_or_split (rtx dest
, rtx src
, enum mips_split_type split_type
)
2745 if (mips_split_move_p (dest
, src
, split_type
))
2746 mips_split_move (dest
, src
, split_type
);
2748 mips_emit_move (dest
, src
);
2751 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2754 mips_emit_unary (enum rtx_code code
, rtx target
, rtx op0
)
2756 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2757 gen_rtx_fmt_e (code
, GET_MODE (op0
), op0
)));
2760 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2761 Return that new register. */
2764 mips_force_unary (enum machine_mode mode
, enum rtx_code code
, rtx op0
)
2768 reg
= gen_reg_rtx (mode
);
2769 mips_emit_unary (code
, reg
, op0
);
2773 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2776 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2778 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2779 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
2782 /* Compute (CODE OP0 OP1) and store the result in a new register
2783 of mode MODE. Return that new register. */
2786 mips_force_binary (enum machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
2790 reg
= gen_reg_rtx (mode
);
2791 mips_emit_binary (code
, reg
, op0
, op1
);
2795 /* Copy VALUE to a register and return that register. If new pseudos
2796 are allowed, copy it into a new register, otherwise use DEST. */
2799 mips_force_temporary (rtx dest
, rtx value
)
2801 if (can_create_pseudo_p ())
2802 return force_reg (Pmode
, value
);
2805 mips_emit_move (dest
, value
);
2810 /* Emit a call sequence with call pattern PATTERN and return the call
2811 instruction itself (which is not necessarily the last instruction
2812 emitted). ORIG_ADDR is the original, unlegitimized address,
2813 ADDR is the legitimized form, and LAZY_P is true if the call
2814 address is lazily-bound. */
2817 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
2821 insn
= emit_call_insn (pattern
);
2823 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
2825 /* MIPS16 JALRs only take MIPS16 registers. If the target
2826 function requires $25 to be valid on entry, we must copy it
2827 there separately. The move instruction can be put in the
2828 call's delay slot. */
2829 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
2830 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
2831 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
2835 /* Lazy-binding stubs require $gp to be valid on entry. */
2836 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2840 /* See the comment above load_call<mode> for details. */
2841 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2842 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
2843 emit_insn (gen_update_got_version ());
2848 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2849 then add CONST_INT OFFSET to the result. */
2852 mips_unspec_address_offset (rtx base
, rtx offset
,
2853 enum mips_symbol_type symbol_type
)
2855 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2856 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2857 if (offset
!= const0_rtx
)
2858 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2859 return gen_rtx_CONST (Pmode
, base
);
2862 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2863 type SYMBOL_TYPE. */
2866 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2870 split_const (address
, &base
, &offset
);
2871 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2874 /* If OP is an UNSPEC address, return the address to which it refers,
2875 otherwise return OP itself. */
2878 mips_strip_unspec_address (rtx op
)
2882 split_const (op
, &base
, &offset
);
2883 if (UNSPEC_ADDRESS_P (base
))
2884 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
2888 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2889 high part to BASE and return the result. Just return BASE otherwise.
2890 TEMP is as for mips_force_temporary.
2892 The returned expression can be used as the first operand to a LO_SUM. */
2895 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2896 enum mips_symbol_type symbol_type
)
2898 if (mips_split_p
[symbol_type
])
2900 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2901 addr
= mips_force_temporary (temp
, addr
);
2902 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2907 /* Return an instruction that copies $gp into register REG. We want
2908 GCC to treat the register's value as constant, so that its value
2909 can be rematerialized on demand. */
2912 gen_load_const_gp (rtx reg
)
2914 return PMODE_INSN (gen_load_const_gp
, (reg
));
2917 /* Return a pseudo register that contains the value of $gp throughout
2918 the current function. Such registers are needed by MIPS16 functions,
2919 for which $gp itself is not a valid base register or addition operand. */
2922 mips16_gp_pseudo_reg (void)
2924 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
2928 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
2930 push_topmost_sequence ();
2932 scan
= get_insns ();
2933 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
2934 scan
= NEXT_INSN (scan
);
2936 insn
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
2937 insn
= emit_insn_after (insn
, scan
);
2938 INSN_LOCATION (insn
) = 0;
2940 pop_topmost_sequence ();
2943 return cfun
->machine
->mips16_gp_pseudo_rtx
;
2946 /* Return a base register that holds pic_offset_table_rtx.
2947 TEMP, if nonnull, is a scratch Pmode base register. */
2950 mips_pic_base_register (rtx temp
)
2953 return pic_offset_table_rtx
;
2955 if (currently_expanding_to_rtl
)
2956 return mips16_gp_pseudo_reg ();
2958 if (can_create_pseudo_p ())
2959 temp
= gen_reg_rtx (Pmode
);
2962 /* The first post-reload split exposes all references to $gp
2963 (both uses and definitions). All references must remain
2964 explicit after that point.
2966 It is safe to introduce uses of $gp at any time, so for
2967 simplicity, we do that before the split too. */
2968 mips_emit_move (temp
, pic_offset_table_rtx
);
2970 emit_insn (gen_load_const_gp (temp
));
2974 /* Return the RHS of a load_call<mode> insn. */
2977 mips_unspec_call (rtx reg
, rtx symbol
)
2981 vec
= gen_rtvec (3, reg
, symbol
, gen_rtx_REG (SImode
, GOT_VERSION_REGNUM
));
2982 return gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_LOAD_CALL
);
2985 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2986 reference. Return NULL_RTX otherwise. */
2989 mips_strip_unspec_call (rtx src
)
2991 if (GET_CODE (src
) == UNSPEC
&& XINT (src
, 1) == UNSPEC_LOAD_CALL
)
2992 return mips_strip_unspec_address (XVECEXP (src
, 0, 1));
2996 /* Create and return a GOT reference of type TYPE for address ADDR.
2997 TEMP, if nonnull, is a scratch Pmode base register. */
3000 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
3002 rtx base
, high
, lo_sum_symbol
;
3004 base
= mips_pic_base_register (temp
);
3006 /* If we used the temporary register to load $gp, we can't use
3007 it for the high part as well. */
3008 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
3011 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
3012 lo_sum_symbol
= mips_unspec_address (addr
, type
);
3014 if (type
== SYMBOL_GOTOFF_CALL
)
3015 return mips_unspec_call (high
, lo_sum_symbol
);
3017 return PMODE_INSN (gen_unspec_got
, (high
, lo_sum_symbol
));
3020 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
3021 it appears in a MEM of that mode. Return true if ADDR is a legitimate
3022 constant in that context and can be split into high and low parts.
3023 If so, and if LOW_OUT is nonnull, emit the high part and store the
3024 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
3026 TEMP is as for mips_force_temporary and is used to load the high
3027 part into a register.
3029 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
3030 a legitimize SET_SRC for an .md pattern, otherwise the low part
3031 is guaranteed to be a legitimate address for mode MODE. */
3034 mips_split_symbol (rtx temp
, rtx addr
, enum machine_mode mode
, rtx
*low_out
)
3036 enum mips_symbol_context context
;
3037 enum mips_symbol_type symbol_type
;
3040 context
= (mode
== MAX_MACHINE_MODE
3041 ? SYMBOL_CONTEXT_LEA
3042 : SYMBOL_CONTEXT_MEM
);
3043 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
3045 addr
= XEXP (addr
, 0);
3046 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
3047 && mips_symbol_insns (symbol_type
, mode
) > 0
3048 && mips_split_hi_p
[symbol_type
])
3051 switch (symbol_type
)
3053 case SYMBOL_GOT_PAGE_OFST
:
3054 /* The high part of a page/ofst pair is loaded from the GOT. */
3055 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
3066 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
3067 && mips_symbol_insns (symbol_type
, mode
) > 0
3068 && mips_split_p
[symbol_type
])
3071 switch (symbol_type
)
3073 case SYMBOL_GOT_DISP
:
3074 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
3075 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
3078 case SYMBOL_GP_RELATIVE
:
3079 high
= mips_pic_base_register (temp
);
3080 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
3084 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
3085 high
= mips_force_temporary (temp
, high
);
3086 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
3095 /* Return a legitimate address for REG + OFFSET. TEMP is as for
3096 mips_force_temporary; it is only needed when OFFSET is not a
3100 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
3102 if (!SMALL_OPERAND (offset
))
3108 /* Load the full offset into a register so that we can use
3109 an unextended instruction for the address itself. */
3110 high
= GEN_INT (offset
);
3115 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3116 The addition inside the macro CONST_HIGH_PART may cause an
3117 overflow, so we need to force a sign-extension check. */
3118 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
3119 offset
= CONST_LOW_PART (offset
);
3121 high
= mips_force_temporary (temp
, high
);
3122 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
3124 return plus_constant (Pmode
, reg
, offset
);
3127 /* The __tls_get_attr symbol. */
3128 static GTY(()) rtx mips_tls_symbol
;
3130 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3131 the TLS symbol we are referencing and TYPE is the symbol type to use
3132 (either global dynamic or local dynamic). V0 is an RTX for the
3133 return value location. */
3136 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
3140 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
3142 if (!mips_tls_symbol
)
3143 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3145 loc
= mips_unspec_address (sym
, type
);
3149 emit_insn (gen_rtx_SET (Pmode
, a0
,
3150 gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, loc
)));
3151 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
3152 const0_rtx
, NULL_RTX
, false);
3153 RTL_CONST_CALL_P (insn
) = 1;
3154 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
3155 insn
= get_insns ();
3162 /* Return a pseudo register that contains the current thread pointer. */
3165 mips_expand_thread_pointer (rtx tp
)
3171 if (!mips16_rdhwr_stub
)
3172 mips16_rdhwr_stub
= new mips16_rdhwr_one_only_stub ();
3173 fn
= mips16_stub_call_address (mips16_rdhwr_stub
);
3174 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16
, (tp
, fn
)));
3177 emit_insn (PMODE_INSN (gen_tls_get_tp
, (tp
)));
3184 return mips_expand_thread_pointer (gen_reg_rtx (Pmode
));
3187 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3188 its address. The return value will be both a valid address and a valid
3189 SET_SRC (either a REG or a LO_SUM). */
3192 mips_legitimize_tls_address (rtx loc
)
3194 rtx dest
, insn
, v0
, tp
, tmp1
, tmp2
, eqv
, offset
;
3195 enum tls_model model
;
3197 model
= SYMBOL_REF_TLS_MODEL (loc
);
3198 /* Only TARGET_ABICALLS code can have more than one module; other
3199 code must be be static and should not use a GOT. All TLS models
3200 reduce to local exec in this situation. */
3201 if (!TARGET_ABICALLS
)
3202 model
= TLS_MODEL_LOCAL_EXEC
;
3206 case TLS_MODEL_GLOBAL_DYNAMIC
:
3207 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3208 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
3209 dest
= gen_reg_rtx (Pmode
);
3210 emit_libcall_block (insn
, dest
, v0
, loc
);
3213 case TLS_MODEL_LOCAL_DYNAMIC
:
3214 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3215 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
3216 tmp1
= gen_reg_rtx (Pmode
);
3218 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3219 share the LDM result with other LD model accesses. */
3220 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3222 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
3224 offset
= mips_unspec_address (loc
, SYMBOL_DTPREL
);
3225 if (mips_split_p
[SYMBOL_DTPREL
])
3227 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
3228 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3231 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3232 0, 0, OPTAB_DIRECT
);
3235 case TLS_MODEL_INITIAL_EXEC
:
3236 tp
= mips_get_tp ();
3237 tmp1
= gen_reg_rtx (Pmode
);
3238 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
3239 if (Pmode
== DImode
)
3240 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
3242 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
3243 dest
= gen_reg_rtx (Pmode
);
3244 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
3247 case TLS_MODEL_LOCAL_EXEC
:
3248 tmp1
= mips_get_tp ();
3249 offset
= mips_unspec_address (loc
, SYMBOL_TPREL
);
3250 if (mips_split_p
[SYMBOL_TPREL
])
3252 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_TPREL
);
3253 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3256 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3257 0, 0, OPTAB_DIRECT
);
3266 /* Implement "TARGET = __builtin_mips_get_fcsr ()" for MIPS16,
3270 mips16_expand_get_fcsr (rtx target
)
3272 if (!mips16_get_fcsr_stub
)
3273 mips16_get_fcsr_stub
= new mips16_get_fcsr_one_only_stub ();
3274 rtx fn
= mips16_stub_call_address (mips16_get_fcsr_stub
);
3275 emit_insn (PMODE_INSN (gen_mips_get_fcsr_mips16
, (fn
)));
3276 emit_move_insn (target
, gen_rtx_REG (SImode
, GET_FCSR_REGNUM
));
3279 /* Implement __builtin_mips_set_fcsr (TARGET) for MIPS16, using a stub. */
3282 mips16_expand_set_fcsr (rtx newval
)
3284 if (!mips16_set_fcsr_stub
)
3285 mips16_set_fcsr_stub
= new mips16_set_fcsr_one_only_stub ();
3286 rtx fn
= mips16_stub_call_address (mips16_set_fcsr_stub
);
3287 emit_move_insn (gen_rtx_REG (SImode
, SET_FCSR_REGNUM
), newval
);
3288 emit_insn (PMODE_INSN (gen_mips_set_fcsr_mips16
, (fn
)));
3291 /* If X is not a valid address for mode MODE, force it into a register. */
3294 mips_force_address (rtx x
, enum machine_mode mode
)
3296 if (!mips_legitimate_address_p (mode
, x
, false))
3297 x
= force_reg (Pmode
, x
);
3301 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3302 be legitimized in a way that the generic machinery might not expect,
3303 return a new address, otherwise return NULL. MODE is the mode of
3304 the memory being accessed. */
3307 mips_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3308 enum machine_mode mode
)
3311 HOST_WIDE_INT offset
;
3313 if (mips_tls_symbol_p (x
))
3314 return mips_legitimize_tls_address (x
);
3316 /* See if the address can split into a high part and a LO_SUM. */
3317 if (mips_split_symbol (NULL
, x
, mode
, &addr
))
3318 return mips_force_address (addr
, mode
);
3320 /* Handle BASE + OFFSET using mips_add_offset. */
3321 mips_split_plus (x
, &base
, &offset
);
3324 if (!mips_valid_base_register_p (base
, mode
, false))
3325 base
= copy_to_mode_reg (Pmode
, base
);
3326 addr
= mips_add_offset (NULL
, base
, offset
);
3327 return mips_force_address (addr
, mode
);
3333 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3336 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
3338 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
3339 enum machine_mode mode
;
3340 unsigned int i
, num_ops
;
3343 mode
= GET_MODE (dest
);
3344 num_ops
= mips_build_integer (codes
, value
);
3346 /* Apply each binary operation to X. Invariant: X is a legitimate
3347 source operand for a SET pattern. */
3348 x
= GEN_INT (codes
[0].value
);
3349 for (i
= 1; i
< num_ops
; i
++)
3351 if (!can_create_pseudo_p ())
3353 emit_insn (gen_rtx_SET (VOIDmode
, temp
, x
));
3357 x
= force_reg (mode
, x
);
3358 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
3361 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
3364 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3365 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3369 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
3373 /* Split moves of big integers into smaller pieces. */
3374 if (splittable_const_int_operand (src
, mode
))
3376 mips_move_integer (dest
, dest
, INTVAL (src
));
3380 /* Split moves of symbolic constants into high/low pairs. */
3381 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
3383 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
3387 /* Generate the appropriate access sequences for TLS symbols. */
3388 if (mips_tls_symbol_p (src
))
3390 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
3394 /* If we have (const (plus symbol offset)), and that expression cannot
3395 be forced into memory, load the symbol first and add in the offset.
3396 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3397 forced into memory, as it usually produces better code. */
3398 split_const (src
, &base
, &offset
);
3399 if (offset
!= const0_rtx
3400 && (targetm
.cannot_force_const_mem (mode
, src
)
3401 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
3403 base
= mips_force_temporary (dest
, base
);
3404 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
3408 src
= force_const_mem (mode
, src
);
3410 /* When using explicit relocs, constant pool references are sometimes
3411 not legitimate addresses. */
3412 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
3413 mips_emit_move (dest
, src
);
3416 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3417 sequence that is valid. */
3420 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
3422 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
3424 mips_emit_move (dest
, force_reg (mode
, src
));
3428 /* We need to deal with constants that would be legitimate
3429 immediate_operands but aren't legitimate move_operands. */
3430 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
3432 mips_legitimize_const_move (mode
, dest
, src
);
3433 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
3439 /* Return true if value X in context CONTEXT is a small-data address
3440 that can be rewritten as a LO_SUM. */
3443 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3445 enum mips_symbol_type symbol_type
;
3447 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3448 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3449 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3450 && symbol_type
== SYMBOL_GP_RELATIVE
);
3453 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3454 containing MEM, or null if none. */
3457 mips_small_data_pattern_1 (rtx
*loc
, void *data
)
3459 enum mips_symbol_context context
;
3461 /* Ignore things like "g" constraints in asms. We make no particular
3462 guarantee about which symbolic constants are acceptable as asm operands
3463 versus which must be forced into a GPR. */
3464 if (GET_CODE (*loc
) == LO_SUM
|| GET_CODE (*loc
) == ASM_OPERANDS
)
3469 if (for_each_rtx (&XEXP (*loc
, 0), mips_small_data_pattern_1
, *loc
))
3474 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3475 return mips_rewrite_small_data_p (*loc
, context
);
3478 /* Return true if OP refers to small data symbols directly, not through
3482 mips_small_data_pattern_p (rtx op
)
3484 return for_each_rtx (&op
, mips_small_data_pattern_1
, NULL
);
3487 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3488 DATA is the containing MEM, or null if none. */
3491 mips_rewrite_small_data_1 (rtx
*loc
, void *data
)
3493 enum mips_symbol_context context
;
3497 for_each_rtx (&XEXP (*loc
, 0), mips_rewrite_small_data_1
, *loc
);
3501 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3502 if (mips_rewrite_small_data_p (*loc
, context
))
3503 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3505 if (GET_CODE (*loc
) == LO_SUM
)
3511 /* Rewrite instruction pattern PATTERN so that it refers to small data
3512 using explicit relocations. */
3515 mips_rewrite_small_data (rtx pattern
)
3517 pattern
= copy_insn (pattern
);
3518 for_each_rtx (&pattern
, mips_rewrite_small_data_1
, NULL
);
3522 /* The cost of loading values from the constant pool. It should be
3523 larger than the cost of any constant we want to synthesize inline. */
3524 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3526 /* Return the cost of X when used as an operand to the MIPS16 instruction
3527 that implements CODE. Return -1 if there is no such instruction, or if
3528 X is not a valid immediate operand for it. */
3531 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3538 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3539 other shifts are extended. The shift patterns truncate the shift
3540 count to the right size, so there are no out-of-range values. */
3541 if (IN_RANGE (x
, 1, 8))
3543 return COSTS_N_INSNS (1);
3546 if (IN_RANGE (x
, -128, 127))
3548 if (SMALL_OPERAND (x
))
3549 return COSTS_N_INSNS (1);
3553 /* Like LE, but reject the always-true case. */
3557 /* We add 1 to the immediate and use SLT. */
3560 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3563 if (IN_RANGE (x
, 0, 255))
3565 if (SMALL_OPERAND_UNSIGNED (x
))
3566 return COSTS_N_INSNS (1);
3571 /* Equality comparisons with 0 are cheap. */
3581 /* Return true if there is a non-MIPS16 instruction that implements CODE
3582 and if that instruction accepts X as an immediate operand. */
3585 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3592 /* All shift counts are truncated to a valid constant. */
3597 /* Likewise rotates, if the target supports rotates at all. */
3603 /* These instructions take 16-bit unsigned immediates. */
3604 return SMALL_OPERAND_UNSIGNED (x
);
3609 /* These instructions take 16-bit signed immediates. */
3610 return SMALL_OPERAND (x
);
3616 /* The "immediate" forms of these instructions are really
3617 implemented as comparisons with register 0. */
3622 /* Likewise, meaning that the only valid immediate operand is 1. */
3626 /* We add 1 to the immediate and use SLT. */
3627 return SMALL_OPERAND (x
+ 1);
3630 /* Likewise SLTU, but reject the always-true case. */
3631 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3635 /* The bit position and size are immediate operands. */
3636 return ISA_HAS_EXT_INS
;
3639 /* By default assume that $0 can be used for 0. */
3644 /* Return the cost of binary operation X, given that the instruction
3645 sequence for a word-sized or smaller operation has cost SINGLE_COST
3646 and that the sequence of a double-word operation has cost DOUBLE_COST.
3647 If SPEED is true, optimize for speed otherwise optimize for size. */
3650 mips_binary_cost (rtx x
, int single_cost
, int double_cost
, bool speed
)
3654 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3659 + set_src_cost (XEXP (x
, 0), speed
)
3660 + rtx_cost (XEXP (x
, 1), GET_CODE (x
), 1, speed
));
3663 /* Return the cost of floating-point multiplications of mode MODE. */
3666 mips_fp_mult_cost (enum machine_mode mode
)
3668 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3671 /* Return the cost of floating-point divisions of mode MODE. */
3674 mips_fp_div_cost (enum machine_mode mode
)
3676 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3679 /* Return the cost of sign-extending OP to mode MODE, not including the
3680 cost of OP itself. */
3683 mips_sign_extend_cost (enum machine_mode mode
, rtx op
)
3686 /* Extended loads are as cheap as unextended ones. */
3689 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3690 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3693 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3694 /* We can use SEB or SEH. */
3695 return COSTS_N_INSNS (1);
3697 /* We need to use a shift left and a shift right. */
3698 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3701 /* Return the cost of zero-extending OP to mode MODE, not including the
3702 cost of OP itself. */
3705 mips_zero_extend_cost (enum machine_mode mode
, rtx op
)
3708 /* Extended loads are as cheap as unextended ones. */
3711 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3712 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3713 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3715 if (GENERATE_MIPS16E
)
3716 /* We can use ZEB or ZEH. */
3717 return COSTS_N_INSNS (1);
3720 /* We need to load 0xff or 0xffff into a register and use AND. */
3721 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
3723 /* We can use ANDI. */
3724 return COSTS_N_INSNS (1);
3727 /* Return the cost of moving between two registers of mode MODE,
3728 assuming that the move will be in pieces of at most UNITS bytes. */
3731 mips_set_reg_reg_piece_cost (enum machine_mode mode
, unsigned int units
)
3733 return COSTS_N_INSNS ((GET_MODE_SIZE (mode
) + units
- 1) / units
);
3736 /* Return the cost of moving between two registers of mode MODE. */
3739 mips_set_reg_reg_cost (enum machine_mode mode
)
3741 switch (GET_MODE_CLASS (mode
))
3744 return mips_set_reg_reg_piece_cost (mode
, GET_MODE_SIZE (CCmode
));
3747 case MODE_COMPLEX_FLOAT
:
3748 case MODE_VECTOR_FLOAT
:
3749 if (TARGET_HARD_FLOAT
)
3750 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_HWFPVALUE
);
3754 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_WORD
);
3758 /* Implement TARGET_RTX_COSTS. */
3761 mips_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
3762 int *total
, bool speed
)
3764 enum machine_mode mode
= GET_MODE (x
);
3765 bool float_mode_p
= FLOAT_MODE_P (mode
);
3769 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3770 appear in the instruction stream, and the cost of a comparison is
3771 really the cost of the branch or scc condition. At the time of
3772 writing, GCC only uses an explicit outer COMPARE code when optabs
3773 is testing whether a constant is expensive enough to force into a
3774 register. We want optabs to pass such constants through the MIPS
3775 expanders instead, so make all constants very cheap here. */
3776 if (outer_code
== COMPARE
)
3778 gcc_assert (CONSTANT_P (x
));
3786 /* Treat *clear_upper32-style ANDs as having zero cost in the
3787 second operand. The cost is entirely in the first operand.
3789 ??? This is needed because we would otherwise try to CSE
3790 the constant operand. Although that's the right thing for
3791 instructions that continue to be a register operation throughout
3792 compilation, it is disastrous for instructions that could
3793 later be converted into a memory operation. */
3795 && outer_code
== AND
3796 && UINTVAL (x
) == 0xffffffff)
3804 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3813 /* When not optimizing for size, we care more about the cost
3814 of hot code, and hot code is often in a loop. If a constant
3815 operand needs to be forced into a register, we will often be
3816 able to hoist the constant load out of the loop, so the load
3817 should not contribute to the cost. */
3818 if (speed
|| mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3830 if (force_to_mem_operand (x
, VOIDmode
))
3832 *total
= COSTS_N_INSNS (1);
3835 cost
= mips_const_insns (x
);
3838 /* If the constant is likely to be stored in a GPR, SETs of
3839 single-insn constants are as cheap as register sets; we
3840 never want to CSE them.
3842 Don't reduce the cost of storing a floating-point zero in
3843 FPRs. If we have a zero in an FPR for other reasons, we
3844 can get better cfg-cleanup and delayed-branch results by
3845 using it consistently, rather than using $0 sometimes and
3846 an FPR at other times. Also, moves between floating-point
3847 registers are sometimes cheaper than (D)MTC1 $0. */
3849 && outer_code
== SET
3850 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3852 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3853 want to CSE the constant itself. It is usually better to
3854 have N copies of the last operation in the sequence and one
3855 shared copy of the other operations. (Note that this is
3856 not true for MIPS16 code, where the final operation in the
3857 sequence is often an extended instruction.)
3859 Also, if we have a CONST_INT, we don't know whether it is
3860 for a word or doubleword operation, so we cannot rely on
3861 the result of mips_build_integer. */
3862 else if (!TARGET_MIPS16
3863 && (outer_code
== SET
|| mode
== VOIDmode
))
3865 *total
= COSTS_N_INSNS (cost
);
3868 /* The value will need to be fetched from the constant pool. */
3869 *total
= CONSTANT_POOL_COST
;
3873 /* If the address is legitimate, return the number of
3874 instructions it needs. */
3876 cost
= mips_address_insns (addr
, mode
, true);
3879 *total
= COSTS_N_INSNS (cost
+ 1);
3882 /* Check for a scaled indexed address. */
3883 if (mips_lwxs_address_p (addr
)
3884 || mips_lx_address_p (addr
, mode
))
3886 *total
= COSTS_N_INSNS (2);
3889 /* Otherwise use the default handling. */
3893 *total
= COSTS_N_INSNS (6);
3897 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3901 /* Check for a *clear_upper32 pattern and treat it like a zero
3902 extension. See the pattern's comment for details. */
3905 && CONST_INT_P (XEXP (x
, 1))
3906 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3908 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3909 + set_src_cost (XEXP (x
, 0), speed
));
3912 if (ISA_HAS_CINS
&& CONST_INT_P (XEXP (x
, 1)))
3914 rtx op
= XEXP (x
, 0);
3915 if (GET_CODE (op
) == ASHIFT
3916 && CONST_INT_P (XEXP (op
, 1))
3917 && mask_low_and_shift_p (mode
, XEXP (x
, 1), XEXP (op
, 1), 32))
3919 *total
= COSTS_N_INSNS (1) + set_src_cost (XEXP (op
, 0), speed
);
3923 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
3924 a single instruction. */
3926 && GET_CODE (XEXP (x
, 0)) == NOT
3927 && GET_CODE (XEXP (x
, 1)) == NOT
)
3929 cost
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1;
3930 *total
= (COSTS_N_INSNS (cost
)
3931 + set_src_cost (XEXP (XEXP (x
, 0), 0), speed
)
3932 + set_src_cost (XEXP (XEXP (x
, 1), 0), speed
));
3940 /* Double-word operations use two single-word operations. */
3941 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3950 if (CONSTANT_P (XEXP (x
, 1)))
3951 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3954 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3960 *total
= mips_cost
->fp_add
;
3962 *total
= COSTS_N_INSNS (4);
3966 /* Low-part immediates need an extended MIPS16 instruction. */
3967 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
3968 + set_src_cost (XEXP (x
, 0), speed
));
3983 /* Branch comparisons have VOIDmode, so use the first operand's
3985 mode
= GET_MODE (XEXP (x
, 0));
3986 if (FLOAT_MODE_P (mode
))
3988 *total
= mips_cost
->fp_add
;
3991 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3997 && (ISA_HAS_NMADD4_NMSUB4
|| ISA_HAS_NMADD3_NMSUB3
)
3998 && TARGET_FUSED_MADD
3999 && !HONOR_NANS (mode
)
4000 && !HONOR_SIGNED_ZEROS (mode
))
4002 /* See if we can use NMADD or NMSUB. See mips.md for the
4003 associated patterns. */
4004 rtx op0
= XEXP (x
, 0);
4005 rtx op1
= XEXP (x
, 1);
4006 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
4008 *total
= (mips_fp_mult_cost (mode
)
4009 + set_src_cost (XEXP (XEXP (op0
, 0), 0), speed
)
4010 + set_src_cost (XEXP (op0
, 1), speed
)
4011 + set_src_cost (op1
, speed
));
4014 if (GET_CODE (op1
) == MULT
)
4016 *total
= (mips_fp_mult_cost (mode
)
4017 + set_src_cost (op0
, speed
)
4018 + set_src_cost (XEXP (op1
, 0), speed
)
4019 + set_src_cost (XEXP (op1
, 1), speed
));
4028 /* If this is part of a MADD or MSUB, treat the PLUS as
4030 if ((ISA_HAS_FP_MADD4_MSUB4
|| ISA_HAS_FP_MADD3_MSUB3
)
4031 && TARGET_FUSED_MADD
4032 && GET_CODE (XEXP (x
, 0)) == MULT
)
4035 *total
= mips_cost
->fp_add
;
4039 /* Double-word operations require three single-word operations and
4040 an SLTU. The MIPS16 version then needs to move the result of
4041 the SLTU from $24 to a MIPS16 register. */
4042 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
4043 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4),
4049 && (ISA_HAS_NMADD4_NMSUB4
|| ISA_HAS_NMADD3_NMSUB3
)
4050 && TARGET_FUSED_MADD
4051 && !HONOR_NANS (mode
)
4052 && HONOR_SIGNED_ZEROS (mode
))
4054 /* See if we can use NMADD or NMSUB. See mips.md for the
4055 associated patterns. */
4056 rtx op
= XEXP (x
, 0);
4057 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
4058 && GET_CODE (XEXP (op
, 0)) == MULT
)
4060 *total
= (mips_fp_mult_cost (mode
)
4061 + set_src_cost (XEXP (XEXP (op
, 0), 0), speed
)
4062 + set_src_cost (XEXP (XEXP (op
, 0), 1), speed
)
4063 + set_src_cost (XEXP (op
, 1), speed
));
4069 *total
= mips_cost
->fp_add
;
4071 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
4076 *total
= mips_fp_mult_cost (mode
);
4077 else if (mode
== DImode
&& !TARGET_64BIT
)
4078 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
4079 where the mulsidi3 always includes an MFHI and an MFLO. */
4081 ? mips_cost
->int_mult_si
* 3 + 6
4082 : COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9));
4084 *total
= COSTS_N_INSNS (ISA_HAS_MUL3
? 1 : 2) + 1;
4085 else if (mode
== DImode
)
4086 *total
= mips_cost
->int_mult_di
;
4088 *total
= mips_cost
->int_mult_si
;
4092 /* Check for a reciprocal. */
4094 && ISA_HAS_FP_RECIP_RSQRT (mode
)
4095 && flag_unsafe_math_optimizations
4096 && XEXP (x
, 0) == CONST1_RTX (mode
))
4098 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
4099 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
4100 division as being free. */
4101 *total
= set_src_cost (XEXP (x
, 1), speed
);
4103 *total
= (mips_fp_div_cost (mode
)
4104 + set_src_cost (XEXP (x
, 1), speed
));
4113 *total
= mips_fp_div_cost (mode
);
4122 /* It is our responsibility to make division by a power of 2
4123 as cheap as 2 register additions if we want the division
4124 expanders to be used for such operations; see the setting
4125 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4126 should always produce shorter code than using
4127 expand_sdiv2_pow2. */
4129 && CONST_INT_P (XEXP (x
, 1))
4130 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
4132 *total
= COSTS_N_INSNS (2) + set_src_cost (XEXP (x
, 0), speed
);
4135 *total
= COSTS_N_INSNS (mips_idiv_insns ());
4137 else if (mode
== DImode
)
4138 *total
= mips_cost
->int_div_di
;
4140 *total
= mips_cost
->int_div_si
;
4144 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
4148 if (outer_code
== SET
4150 && (GET_CODE (XEXP (x
, 0)) == TRUNCATE
4151 || GET_CODE (XEXP (x
, 0)) == SUBREG
)
4152 && GET_MODE (XEXP (x
, 0)) == QImode
4153 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
4155 *total
= set_src_cost (XEXP (XEXP (x
, 0), 0), speed
);
4158 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
4162 case UNSIGNED_FLOAT
:
4165 case FLOAT_TRUNCATE
:
4166 *total
= mips_cost
->fp_add
;
4170 if (register_operand (SET_DEST (x
), VOIDmode
)
4171 && reg_or_0_operand (SET_SRC (x
), VOIDmode
))
4173 *total
= mips_set_reg_reg_cost (GET_MODE (SET_DEST (x
)));
4183 /* Implement TARGET_ADDRESS_COST. */
4186 mips_address_cost (rtx addr
, enum machine_mode mode
,
4187 addr_space_t as ATTRIBUTE_UNUSED
,
4188 bool speed ATTRIBUTE_UNUSED
)
4190 return mips_address_insns (addr
, mode
, false);
4193 /* Information about a single instruction in a multi-instruction
4195 struct mips_multi_member
{
4196 /* True if this is a label, false if it is code. */
4199 /* The output_asm_insn format of the instruction. */
4202 /* The operands to the instruction. */
4203 rtx operands
[MAX_RECOG_OPERANDS
];
4205 typedef struct mips_multi_member mips_multi_member
;
4207 /* The instructions that make up the current multi-insn sequence. */
4208 static vec
<mips_multi_member
> mips_multi_members
;
4210 /* How many instructions (as opposed to labels) are in the current
4211 multi-insn sequence. */
4212 static unsigned int mips_multi_num_insns
;
4214 /* Start a new multi-insn sequence. */
4217 mips_multi_start (void)
4219 mips_multi_members
.truncate (0);
4220 mips_multi_num_insns
= 0;
4223 /* Add a new, uninitialized member to the current multi-insn sequence. */
4225 static struct mips_multi_member
*
4226 mips_multi_add (void)
4228 mips_multi_member empty
;
4229 return mips_multi_members
.safe_push (empty
);
4232 /* Add a normal insn with the given asm format to the current multi-insn
4233 sequence. The other arguments are a null-terminated list of operands. */
4236 mips_multi_add_insn (const char *format
, ...)
4238 struct mips_multi_member
*member
;
4243 member
= mips_multi_add ();
4244 member
->is_label_p
= false;
4245 member
->format
= format
;
4246 va_start (ap
, format
);
4248 while ((op
= va_arg (ap
, rtx
)))
4249 member
->operands
[i
++] = op
;
4251 mips_multi_num_insns
++;
4254 /* Add the given label definition to the current multi-insn sequence.
4255 The definition should include the colon. */
4258 mips_multi_add_label (const char *label
)
4260 struct mips_multi_member
*member
;
4262 member
= mips_multi_add ();
4263 member
->is_label_p
= true;
4264 member
->format
= label
;
4267 /* Return the index of the last member of the current multi-insn sequence. */
4270 mips_multi_last_index (void)
4272 return mips_multi_members
.length () - 1;
4275 /* Add a copy of an existing instruction to the current multi-insn
4276 sequence. I is the index of the instruction that should be copied. */
4279 mips_multi_copy_insn (unsigned int i
)
4281 struct mips_multi_member
*member
;
4283 member
= mips_multi_add ();
4284 memcpy (member
, &mips_multi_members
[i
], sizeof (*member
));
4285 gcc_assert (!member
->is_label_p
);
4288 /* Change the operand of an existing instruction in the current
4289 multi-insn sequence. I is the index of the instruction,
4290 OP is the index of the operand, and X is the new value. */
4293 mips_multi_set_operand (unsigned int i
, unsigned int op
, rtx x
)
4295 mips_multi_members
[i
].operands
[op
] = x
;
4298 /* Write out the asm code for the current multi-insn sequence. */
4301 mips_multi_write (void)
4303 struct mips_multi_member
*member
;
4306 FOR_EACH_VEC_ELT (mips_multi_members
, i
, member
)
4307 if (member
->is_label_p
)
4308 fprintf (asm_out_file
, "%s\n", member
->format
);
4310 output_asm_insn (member
->format
, member
->operands
);
4313 /* Return one word of double-word value OP, taking into account the fixed
4314 endianness of certain registers. HIGH_P is true to select the high part,
4315 false to select the low part. */
4318 mips_subword (rtx op
, bool high_p
)
4320 unsigned int byte
, offset
;
4321 enum machine_mode mode
;
4323 mode
= GET_MODE (op
);
4324 if (mode
== VOIDmode
)
4325 mode
= TARGET_64BIT
? TImode
: DImode
;
4327 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
4328 byte
= UNITS_PER_WORD
;
4332 if (FP_REG_RTX_P (op
))
4334 /* Paired FPRs are always ordered little-endian. */
4335 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
4336 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
4340 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
4342 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
4345 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4346 SPLIT_TYPE is the condition under which moves should be split. */
4349 mips_mult_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4351 return ((split_type
!= SPLIT_FOR_SPEED
4352 || mips_tuning_info
.fast_mult_zero_zero_p
)
4353 && src
== const0_rtx
4355 && GET_MODE_SIZE (GET_MODE (dest
)) == 2 * UNITS_PER_WORD
4356 && (ISA_HAS_DSP_MULT
4357 ? ACC_REG_P (REGNO (dest
))
4358 : MD_REG_P (REGNO (dest
))));
4361 /* Return true if a move from SRC to DEST should be split into two.
4362 SPLIT_TYPE describes the split condition. */
4365 mips_split_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4367 /* Check whether the move can be done using some variant of MULT $0,$0. */
4368 if (mips_mult_move_p (dest
, src
, split_type
))
4371 /* FPR-to-FPR moves can be done in a single instruction, if they're
4373 unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
4374 if (size
== 8 && FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4377 /* Check for floating-point loads and stores. */
4378 if (size
== 8 && ISA_HAS_LDC1_SDC1
)
4380 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4382 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4386 /* Otherwise split all multiword moves. */
4387 return size
> UNITS_PER_WORD
;
4390 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4391 SPLIT_TYPE describes the split condition. */
4394 mips_split_move (rtx dest
, rtx src
, enum mips_split_type split_type
)
4398 gcc_checking_assert (mips_split_move_p (dest
, src
, split_type
));
4399 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
4401 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
4402 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
4403 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
4404 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
4405 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
4406 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
4407 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
4408 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
4409 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
4410 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
4411 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
4412 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
4413 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
4414 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
4418 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
4420 low_dest
= mips_subword (dest
, false);
4421 mips_emit_move (low_dest
, mips_subword (src
, false));
4423 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
4425 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
4427 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
4429 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
4431 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
4433 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
4437 /* The operation can be split into two normal moves. Decide in
4438 which order to do them. */
4439 low_dest
= mips_subword (dest
, false);
4440 if (REG_P (low_dest
)
4441 && reg_overlap_mentioned_p (low_dest
, src
))
4443 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4444 mips_emit_move (low_dest
, mips_subword (src
, false));
4448 mips_emit_move (low_dest
, mips_subword (src
, false));
4449 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4454 /* Return the split type for instruction INSN. */
4456 static enum mips_split_type
4457 mips_insn_split_type (rtx insn
)
4459 basic_block bb
= BLOCK_FOR_INSN (insn
);
4462 if (optimize_bb_for_speed_p (bb
))
4463 return SPLIT_FOR_SPEED
;
4465 return SPLIT_FOR_SIZE
;
4467 /* Once CFG information has been removed, we should trust the optimization
4468 decisions made by previous passes and only split where necessary. */
4469 return SPLIT_IF_NECESSARY
;
4472 /* Return true if a move from SRC to DEST in INSN should be split. */
4475 mips_split_move_insn_p (rtx dest
, rtx src
, rtx insn
)
4477 return mips_split_move_p (dest
, src
, mips_insn_split_type (insn
));
4480 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4484 mips_split_move_insn (rtx dest
, rtx src
, rtx insn
)
4486 mips_split_move (dest
, src
, mips_insn_split_type (insn
));
4489 /* Return the appropriate instructions to move SRC into DEST. Assume
4490 that SRC is operand 1 and DEST is operand 0. */
4493 mips_output_move (rtx dest
, rtx src
)
4495 enum rtx_code dest_code
, src_code
;
4496 enum machine_mode mode
;
4497 enum mips_symbol_type symbol_type
;
4500 dest_code
= GET_CODE (dest
);
4501 src_code
= GET_CODE (src
);
4502 mode
= GET_MODE (dest
);
4503 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
4505 if (mips_split_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4508 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
4509 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
4511 if (dest_code
== REG
)
4513 if (GP_REG_P (REGNO (dest
)))
4514 return "move\t%0,%z1";
4516 if (mips_mult_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4518 if (ISA_HAS_DSP_MULT
)
4519 return "mult\t%q0,%.,%.";
4521 return "mult\t%.,%.";
4524 /* Moves to HI are handled by special .md insns. */
4525 if (REGNO (dest
) == LO_REGNUM
)
4528 if (DSP_ACC_REG_P (REGNO (dest
)))
4530 static char retval
[] = "mt__\t%z1,%q0";
4532 retval
[2] = reg_names
[REGNO (dest
)][4];
4533 retval
[3] = reg_names
[REGNO (dest
)][5];
4537 if (FP_REG_P (REGNO (dest
)))
4538 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4540 if (ALL_COP_REG_P (REGNO (dest
)))
4542 static char retval
[] = "dmtc_\t%z1,%0";
4544 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4545 return dbl_p
? retval
: retval
+ 1;
4548 if (dest_code
== MEM
)
4549 switch (GET_MODE_SIZE (mode
))
4551 case 1: return "sb\t%z1,%0";
4552 case 2: return "sh\t%z1,%0";
4553 case 4: return "sw\t%z1,%0";
4554 case 8: return "sd\t%z1,%0";
4557 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
4559 if (src_code
== REG
)
4561 /* Moves from HI are handled by special .md insns. */
4562 if (REGNO (src
) == LO_REGNUM
)
4564 /* When generating VR4120 or VR4130 code, we use MACC and
4565 DMACC instead of MFLO. This avoids both the normal
4566 MIPS III HI/LO hazards and the errata related to
4569 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4573 if (DSP_ACC_REG_P (REGNO (src
)))
4575 static char retval
[] = "mf__\t%0,%q1";
4577 retval
[2] = reg_names
[REGNO (src
)][4];
4578 retval
[3] = reg_names
[REGNO (src
)][5];
4582 if (FP_REG_P (REGNO (src
)))
4583 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4585 if (ALL_COP_REG_P (REGNO (src
)))
4587 static char retval
[] = "dmfc_\t%0,%1";
4589 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4590 return dbl_p
? retval
: retval
+ 1;
4594 if (src_code
== MEM
)
4595 switch (GET_MODE_SIZE (mode
))
4597 case 1: return "lbu\t%0,%1";
4598 case 2: return "lhu\t%0,%1";
4599 case 4: return "lw\t%0,%1";
4600 case 8: return "ld\t%0,%1";
4603 if (src_code
== CONST_INT
)
4605 /* Don't use the X format for the operand itself, because that
4606 will give out-of-range numbers for 64-bit hosts and 32-bit
4609 return "li\t%0,%1\t\t\t# %X1";
4611 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
4614 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
4618 if (src_code
== HIGH
)
4619 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
4621 if (CONST_GP_P (src
))
4622 return "move\t%0,%1";
4624 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
4625 && mips_lo_relocs
[symbol_type
] != 0)
4627 /* A signed 16-bit constant formed by applying a relocation
4628 operator to a symbolic address. */
4629 gcc_assert (!mips_split_p
[symbol_type
]);
4630 return "li\t%0,%R1";
4633 if (symbolic_operand (src
, VOIDmode
))
4635 gcc_assert (TARGET_MIPS16
4636 ? TARGET_MIPS16_TEXT_LOADS
4637 : !TARGET_EXPLICIT_RELOCS
);
4638 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
4641 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
4643 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4645 if (GET_MODE (dest
) == V2SFmode
)
4646 return "mov.ps\t%0,%1";
4648 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4651 if (dest_code
== MEM
)
4652 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
4654 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4656 if (src_code
== MEM
)
4657 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4659 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
4661 static char retval
[] = "l_c_\t%0,%1";
4663 retval
[1] = (dbl_p
? 'd' : 'w');
4664 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4667 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
4669 static char retval
[] = "s_c_\t%1,%0";
4671 retval
[1] = (dbl_p
? 'd' : 'w');
4672 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4678 /* Return true if CMP1 is a suitable second operand for integer ordering
4679 test CODE. See also the *sCC patterns in mips.md. */
4682 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
4688 return reg_or_0_operand (cmp1
, VOIDmode
);
4692 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
4696 return arith_operand (cmp1
, VOIDmode
);
4699 return sle_operand (cmp1
, VOIDmode
);
4702 return sleu_operand (cmp1
, VOIDmode
);
4709 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4710 integer ordering test *CODE, or if an equivalent combination can
4711 be formed by adjusting *CODE and *CMP1. When returning true, update
4712 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4716 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
4717 enum machine_mode mode
)
4719 HOST_WIDE_INT plus_one
;
4721 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
4724 if (CONST_INT_P (*cmp1
))
4728 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4729 if (INTVAL (*cmp1
) < plus_one
)
4732 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4738 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4742 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4753 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4754 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4755 is nonnull, it's OK to set TARGET to the inverse of the result and
4756 flip *INVERT_PTR instead. */
4759 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
4760 rtx target
, rtx cmp0
, rtx cmp1
)
4762 enum machine_mode mode
;
4764 /* First see if there is a MIPS instruction that can do this operation.
4765 If not, try doing the same for the inverse operation. If that also
4766 fails, force CMP1 into a register and try again. */
4767 mode
= GET_MODE (cmp0
);
4768 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
4769 mips_emit_binary (code
, target
, cmp0
, cmp1
);
4772 enum rtx_code inv_code
= reverse_condition (code
);
4773 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
4775 cmp1
= force_reg (mode
, cmp1
);
4776 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
4778 else if (invert_ptr
== 0)
4782 inv_target
= mips_force_binary (GET_MODE (target
),
4783 inv_code
, cmp0
, cmp1
);
4784 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
4788 *invert_ptr
= !*invert_ptr
;
4789 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
4794 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4795 The register will have the same mode as CMP0. */
4798 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
4800 if (cmp1
== const0_rtx
)
4803 if (uns_arith_operand (cmp1
, VOIDmode
))
4804 return expand_binop (GET_MODE (cmp0
), xor_optab
,
4805 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4807 return expand_binop (GET_MODE (cmp0
), sub_optab
,
4808 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4811 /* Convert *CODE into a code that can be used in a floating-point
4812 scc instruction (C.cond.fmt). Return true if the values of
4813 the condition code registers will be inverted, with 0 indicating
4814 that the condition holds. */
4817 mips_reversed_fp_cond (enum rtx_code
*code
)
4824 *code
= reverse_condition_maybe_unordered (*code
);
4832 /* Allocate a floating-point condition-code register of mode MODE.
4834 These condition code registers are used for certain kinds
4835 of compound operation, such as compare and branches, vconds,
4836 and built-in functions. At expand time, their use is entirely
4837 controlled by MIPS-specific code and is entirely internal
4838 to these compound operations.
4840 We could (and did in the past) expose condition-code values
4841 as pseudo registers and leave the register allocator to pick
4842 appropriate registers. The problem is that it is not practically
4843 possible for the rtl optimizers to guarantee that no spills will
4844 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4845 therefore need spill and reload sequences to handle the worst case.
4847 Although such sequences do exist, they are very expensive and are
4848 not something we'd want to use. This is especially true of CCV2 and
4849 CCV4, where all the shuffling would greatly outweigh whatever benefit
4850 the vectorization itself provides.
4852 The main benefit of having more than one condition-code register
4853 is to allow the pipelining of operations, especially those involving
4854 comparisons and conditional moves. We don't really expect the
4855 registers to be live for long periods, and certainly never want
4856 them to be live across calls.
4858 Also, there should be no penalty attached to using all the available
4859 registers. They are simply bits in the same underlying FPU control
4862 We therefore expose the hardware registers from the outset and use
4863 a simple round-robin allocation scheme. */
4866 mips_allocate_fcc (enum machine_mode mode
)
4868 unsigned int regno
, count
;
4870 gcc_assert (TARGET_HARD_FLOAT
&& ISA_HAS_8CC
);
4874 else if (mode
== CCV2mode
)
4876 else if (mode
== CCV4mode
)
4881 cfun
->machine
->next_fcc
+= -cfun
->machine
->next_fcc
& (count
- 1);
4882 if (cfun
->machine
->next_fcc
> ST_REG_LAST
- ST_REG_FIRST
)
4883 cfun
->machine
->next_fcc
= 0;
4884 regno
= ST_REG_FIRST
+ cfun
->machine
->next_fcc
;
4885 cfun
->machine
->next_fcc
+= count
;
4886 return gen_rtx_REG (mode
, regno
);
4889 /* Convert a comparison into something that can be used in a branch or
4890 conditional move. On entry, *OP0 and *OP1 are the values being
4891 compared and *CODE is the code used to compare them.
4893 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4894 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4895 otherwise any standard branch condition can be used. The standard branch
4898 - EQ or NE between two registers.
4899 - any comparison between a register and zero. */
4902 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
4907 if (GET_MODE_CLASS (GET_MODE (*op0
)) == MODE_INT
)
4909 if (!need_eq_ne_p
&& *op1
== const0_rtx
)
4911 else if (*code
== EQ
|| *code
== NE
)
4915 *op0
= mips_zero_if_equal (cmp_op0
, cmp_op1
);
4919 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
4923 /* The comparison needs a separate scc instruction. Store the
4924 result of the scc in *OP0 and compare it against zero. */
4925 bool invert
= false;
4926 *op0
= gen_reg_rtx (GET_MODE (cmp_op0
));
4927 mips_emit_int_order_test (*code
, &invert
, *op0
, cmp_op0
, cmp_op1
);
4928 *code
= (invert
? EQ
: NE
);
4932 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0
)))
4934 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
4935 mips_emit_binary (*code
, *op0
, cmp_op0
, cmp_op1
);
4941 enum rtx_code cmp_code
;
4943 /* Floating-point tests use a separate C.cond.fmt comparison to
4944 set a condition code register. The branch or conditional move
4945 will then compare that register against zero.
4947 Set CMP_CODE to the code of the comparison instruction and
4948 *CODE to the code that the branch or move should use. */
4950 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
4952 ? mips_allocate_fcc (CCmode
)
4953 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
4955 mips_emit_binary (cmp_code
, *op0
, cmp_op0
, cmp_op1
);
4959 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4960 and OPERAND[3]. Store the result in OPERANDS[0].
4962 On 64-bit targets, the mode of the comparison and target will always be
4963 SImode, thus possibly narrower than that of the comparison's operands. */
4966 mips_expand_scc (rtx operands
[])
4968 rtx target
= operands
[0];
4969 enum rtx_code code
= GET_CODE (operands
[1]);
4970 rtx op0
= operands
[2];
4971 rtx op1
= operands
[3];
4973 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
);
4975 if (code
== EQ
|| code
== NE
)
4978 && reg_imm10_operand (op1
, GET_MODE (op1
)))
4979 mips_emit_binary (code
, target
, op0
, op1
);
4982 rtx zie
= mips_zero_if_equal (op0
, op1
);
4983 mips_emit_binary (code
, target
, zie
, const0_rtx
);
4987 mips_emit_int_order_test (code
, 0, target
, op0
, op1
);
4990 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4991 CODE and jump to OPERANDS[3] if the condition holds. */
4994 mips_expand_conditional_branch (rtx
*operands
)
4996 enum rtx_code code
= GET_CODE (operands
[0]);
4997 rtx op0
= operands
[1];
4998 rtx op1
= operands
[2];
5001 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
5002 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5003 emit_jump_insn (gen_condjump (condition
, operands
[3]));
5008 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
5009 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
5012 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
5013 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
5018 reversed_p
= mips_reversed_fp_cond (&cond
);
5019 cmp_result
= mips_allocate_fcc (CCV2mode
);
5020 emit_insn (gen_scc_ps (cmp_result
,
5021 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
5023 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
5026 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
5030 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
5031 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
5034 mips_expand_conditional_move (rtx
*operands
)
5037 enum rtx_code code
= GET_CODE (operands
[1]);
5038 rtx op0
= XEXP (operands
[1], 0);
5039 rtx op1
= XEXP (operands
[1], 1);
5041 mips_emit_compare (&code
, &op0
, &op1
, true);
5042 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
5043 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
5044 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
5045 operands
[2], operands
[3])));
5048 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
5051 mips_expand_conditional_trap (rtx comparison
)
5054 enum machine_mode mode
;
5057 /* MIPS conditional trap instructions don't have GT or LE flavors,
5058 so we must swap the operands and convert to LT and GE respectively. */
5059 code
= GET_CODE (comparison
);
5066 code
= swap_condition (code
);
5067 op0
= XEXP (comparison
, 1);
5068 op1
= XEXP (comparison
, 0);
5072 op0
= XEXP (comparison
, 0);
5073 op1
= XEXP (comparison
, 1);
5077 mode
= GET_MODE (XEXP (comparison
, 0));
5078 op0
= force_reg (mode
, op0
);
5079 if (!arith_operand (op1
, mode
))
5080 op1
= force_reg (mode
, op1
);
5082 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
5083 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
5087 /* Initialize *CUM for a call to a function of type FNTYPE. */
5090 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
5092 memset (cum
, 0, sizeof (*cum
));
5093 cum
->prototype
= (fntype
&& prototype_p (fntype
));
5094 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
5097 /* Fill INFO with information about a single argument. CUM is the
5098 cumulative state for earlier arguments. MODE is the mode of this
5099 argument and TYPE is its type (if known). NAMED is true if this
5100 is a named (fixed) argument rather than a variable one. */
5103 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
5104 enum machine_mode mode
, const_tree type
, bool named
)
5106 bool doubleword_aligned_p
;
5107 unsigned int num_bytes
, num_words
, max_regs
;
5109 /* Work out the size of the argument. */
5110 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5111 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5113 /* Decide whether it should go in a floating-point register, assuming
5114 one is free. Later code checks for availability.
5116 The checks against UNITS_PER_FPVALUE handle the soft-float and
5117 single-float cases. */
5121 /* The EABI conventions have traditionally been defined in terms
5122 of TYPE_MODE, regardless of the actual type. */
5123 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5124 || mode
== V2SFmode
)
5125 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5130 /* Only leading floating-point scalars are passed in
5131 floating-point registers. We also handle vector floats the same
5132 say, which is OK because they are not covered by the standard ABI. */
5133 info
->fpr_p
= (!cum
->gp_reg_found
5134 && cum
->arg_number
< 2
5136 || SCALAR_FLOAT_TYPE_P (type
)
5137 || VECTOR_FLOAT_TYPE_P (type
))
5138 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5139 || mode
== V2SFmode
)
5140 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5145 /* Scalar, complex and vector floating-point types are passed in
5146 floating-point registers, as long as this is a named rather
5147 than a variable argument. */
5148 info
->fpr_p
= (named
5149 && (type
== 0 || FLOAT_TYPE_P (type
))
5150 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5151 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5152 || mode
== V2SFmode
)
5153 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5155 /* ??? According to the ABI documentation, the real and imaginary
5156 parts of complex floats should be passed in individual registers.
5157 The real and imaginary parts of stack arguments are supposed
5158 to be contiguous and there should be an extra word of padding
5161 This has two problems. First, it makes it impossible to use a
5162 single "void *" va_list type, since register and stack arguments
5163 are passed differently. (At the time of writing, MIPSpro cannot
5164 handle complex float varargs correctly.) Second, it's unclear
5165 what should happen when there is only one register free.
5167 For now, we assume that named complex floats should go into FPRs
5168 if there are two FPRs free, otherwise they should be passed in the
5169 same way as a struct containing two floats. */
5171 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5172 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
5174 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
5175 info
->fpr_p
= false;
5185 /* See whether the argument has doubleword alignment. */
5186 doubleword_aligned_p
= (mips_function_arg_boundary (mode
, type
)
5189 /* Set REG_OFFSET to the register count we're interested in.
5190 The EABI allocates the floating-point registers separately,
5191 but the other ABIs allocate them like integer registers. */
5192 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
5196 /* Advance to an even register if the argument is doubleword-aligned. */
5197 if (doubleword_aligned_p
)
5198 info
->reg_offset
+= info
->reg_offset
& 1;
5200 /* Work out the offset of a stack argument. */
5201 info
->stack_offset
= cum
->stack_words
;
5202 if (doubleword_aligned_p
)
5203 info
->stack_offset
+= info
->stack_offset
& 1;
5205 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
5207 /* Partition the argument between registers and stack. */
5208 info
->reg_words
= MIN (num_words
, max_regs
);
5209 info
->stack_words
= num_words
- info
->reg_words
;
5212 /* INFO describes a register argument that has the normal format for the
5213 argument's mode. Return the register it uses, assuming that FPRs are
5214 available if HARD_FLOAT_P. */
5217 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
5219 if (!info
->fpr_p
|| !hard_float_p
)
5220 return GP_ARG_FIRST
+ info
->reg_offset
;
5221 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
5222 /* In o32, the second argument is always passed in $f14
5223 for TARGET_DOUBLE_FLOAT, regardless of whether the
5224 first argument was a word or doubleword. */
5225 return FP_ARG_FIRST
+ 2;
5227 return FP_ARG_FIRST
+ info
->reg_offset
;
5230 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5233 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5235 return !TARGET_OLDABI
;
5238 /* Implement TARGET_FUNCTION_ARG. */
5241 mips_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
5242 const_tree type
, bool named
)
5244 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5245 struct mips_arg_info info
;
5247 /* We will be called with a mode of VOIDmode after the last argument
5248 has been seen. Whatever we return will be passed to the call expander.
5249 If we need a MIPS16 fp_code, return a REG with the code stored as
5251 if (mode
== VOIDmode
)
5253 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
5254 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
5259 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5261 /* Return straight away if the whole argument is passed on the stack. */
5262 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
5265 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5266 contains a double in its entirety, then that 64-bit chunk is passed
5267 in a floating-point register. */
5269 && TARGET_HARD_FLOAT
5272 && TREE_CODE (type
) == RECORD_TYPE
5273 && TYPE_SIZE_UNIT (type
)
5274 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type
)))
5278 /* First check to see if there is any such field. */
5279 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5280 if (TREE_CODE (field
) == FIELD_DECL
5281 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5282 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
5283 && tree_fits_shwi_p (bit_position (field
))
5284 && int_bit_position (field
) % BITS_PER_WORD
== 0)
5289 /* Now handle the special case by returning a PARALLEL
5290 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5291 chunks are passed in registers. */
5293 HOST_WIDE_INT bitpos
;
5296 /* assign_parms checks the mode of ENTRY_PARM, so we must
5297 use the actual mode here. */
5298 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
5301 field
= TYPE_FIELDS (type
);
5302 for (i
= 0; i
< info
.reg_words
; i
++)
5306 for (; field
; field
= DECL_CHAIN (field
))
5307 if (TREE_CODE (field
) == FIELD_DECL
5308 && int_bit_position (field
) >= bitpos
)
5312 && int_bit_position (field
) == bitpos
5313 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5314 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
5315 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
5317 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
5320 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
5321 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5323 bitpos
+= BITS_PER_WORD
;
5329 /* Handle the n32/n64 conventions for passing complex floating-point
5330 arguments in FPR pairs. The real part goes in the lower register
5331 and the imaginary part goes in the upper register. */
5334 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5337 enum machine_mode inner
;
5340 inner
= GET_MODE_INNER (mode
);
5341 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
5342 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
5344 /* Real part in registers, imaginary part on stack. */
5345 gcc_assert (info
.stack_words
== info
.reg_words
);
5346 return gen_rtx_REG (inner
, regno
);
5350 gcc_assert (info
.stack_words
== 0);
5351 real
= gen_rtx_EXPR_LIST (VOIDmode
,
5352 gen_rtx_REG (inner
, regno
),
5354 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
5356 regno
+ info
.reg_words
/ 2),
5357 GEN_INT (GET_MODE_SIZE (inner
)));
5358 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
5362 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
5365 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5368 mips_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
5369 const_tree type
, bool named
)
5371 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5372 struct mips_arg_info info
;
5374 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5377 cum
->gp_reg_found
= true;
5379 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5380 an explanation of what this code does. It assumes that we're using
5381 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5383 if (cum
->arg_number
< 2 && info
.fpr_p
)
5384 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
5386 /* Advance the register count. This has the effect of setting
5387 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5388 argument required us to skip the final GPR and pass the whole
5389 argument on the stack. */
5390 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
5391 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
5392 else if (info
.reg_words
> 0)
5393 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
5395 /* Advance the stack word count. */
5396 if (info
.stack_words
> 0)
5397 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
5402 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5405 mips_arg_partial_bytes (cumulative_args_t cum
,
5406 enum machine_mode mode
, tree type
, bool named
)
5408 struct mips_arg_info info
;
5410 mips_get_arg_info (&info
, get_cumulative_args (cum
), mode
, type
, named
);
5411 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
5414 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5415 least PARM_BOUNDARY bits of alignment, but will be given anything up
5416 to STACK_BOUNDARY bits if the type requires it. */
5419 mips_function_arg_boundary (enum machine_mode mode
, const_tree type
)
5421 unsigned int alignment
;
5423 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
5424 if (alignment
< PARM_BOUNDARY
)
5425 alignment
= PARM_BOUNDARY
;
5426 if (alignment
> STACK_BOUNDARY
)
5427 alignment
= STACK_BOUNDARY
;
5431 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5432 upward rather than downward. In other words, return true if the
5433 first byte of the stack slot has useful data, false if the last
5437 mips_pad_arg_upward (enum machine_mode mode
, const_tree type
)
5439 /* On little-endian targets, the first byte of every stack argument
5440 is passed in the first byte of the stack slot. */
5441 if (!BYTES_BIG_ENDIAN
)
5444 /* Otherwise, integral types are padded downward: the last byte of a
5445 stack argument is passed in the last byte of the stack slot. */
5447 ? (INTEGRAL_TYPE_P (type
)
5448 || POINTER_TYPE_P (type
)
5449 || FIXED_POINT_TYPE_P (type
))
5450 : (SCALAR_INT_MODE_P (mode
)
5451 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
5454 /* Big-endian o64 pads floating-point arguments downward. */
5455 if (mips_abi
== ABI_O64
)
5456 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5459 /* Other types are padded upward for o32, o64, n32 and n64. */
5460 if (mips_abi
!= ABI_EABI
)
5463 /* Arguments smaller than a stack slot are padded downward. */
5464 if (mode
!= BLKmode
)
5465 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
5467 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
5470 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5471 if the least significant byte of the register has useful data. Return
5472 the opposite if the most significant byte does. */
5475 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
5477 /* No shifting is required for floating-point arguments. */
5478 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5479 return !BYTES_BIG_ENDIAN
;
5481 /* Otherwise, apply the same padding to register arguments as we do
5482 to stack arguments. */
5483 return mips_pad_arg_upward (mode
, type
);
5486 /* Return nonzero when an argument must be passed by reference. */
5489 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5490 enum machine_mode mode
, const_tree type
,
5491 bool named ATTRIBUTE_UNUSED
)
5493 if (mips_abi
== ABI_EABI
)
5497 /* ??? How should SCmode be handled? */
5498 if (mode
== DImode
|| mode
== DFmode
5499 || mode
== DQmode
|| mode
== UDQmode
5500 || mode
== DAmode
|| mode
== UDAmode
)
5503 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5504 return size
== -1 || size
> UNITS_PER_WORD
;
5508 /* If we have a variable-sized parameter, we have no choice. */
5509 return targetm
.calls
.must_pass_in_stack (mode
, type
);
5513 /* Implement TARGET_CALLEE_COPIES. */
5516 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5517 enum machine_mode mode ATTRIBUTE_UNUSED
,
5518 const_tree type ATTRIBUTE_UNUSED
, bool named
)
5520 return mips_abi
== ABI_EABI
&& named
;
5523 /* See whether VALTYPE is a record whose fields should be returned in
5524 floating-point registers. If so, return the number of fields and
5525 list them in FIELDS (which should have two elements). Return 0
5528 For n32 & n64, a structure with one or two fields is returned in
5529 floating-point registers as long as every field has a floating-point
5533 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
5541 if (TREE_CODE (valtype
) != RECORD_TYPE
)
5545 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= DECL_CHAIN (field
))
5547 if (TREE_CODE (field
) != FIELD_DECL
)
5550 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
5556 fields
[i
++] = field
;
5561 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5562 a value in the most significant part of $2/$3 if:
5564 - the target is big-endian;
5566 - the value has a structure or union type (we generalize this to
5567 cover aggregates from other languages too); and
5569 - the structure is not returned in floating-point registers. */
5572 mips_return_in_msb (const_tree valtype
)
5576 return (TARGET_NEWABI
5577 && TARGET_BIG_ENDIAN
5578 && AGGREGATE_TYPE_P (valtype
)
5579 && mips_fpr_return_fields (valtype
, fields
) == 0);
5582 /* Return true if the function return value MODE will get returned in a
5583 floating-point register. */
5586 mips_return_mode_in_fpr_p (enum machine_mode mode
)
5588 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5590 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5591 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
5594 /* Return the representation of an FPR return register when the
5595 value being returned in FP_RETURN has mode VALUE_MODE and the
5596 return type itself has mode TYPE_MODE. On NewABI targets,
5597 the two modes may be different for structures like:
5599 struct __attribute__((packed)) foo { float f; }
5601 where we return the SFmode value of "f" in FP_RETURN, but where
5602 the structure itself has mode BLKmode. */
5605 mips_return_fpr_single (enum machine_mode type_mode
,
5606 enum machine_mode value_mode
)
5610 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
5611 if (type_mode
!= value_mode
)
5613 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
5614 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
5619 /* Return a composite value in a pair of floating-point registers.
5620 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5621 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5624 For n32 & n64, $f0 always holds the first value and $f2 the second.
5625 Otherwise the values are packed together as closely as possible. */
5628 mips_return_fpr_pair (enum machine_mode mode
,
5629 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
5630 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
5634 inc
= (TARGET_NEWABI
? 2 : MAX_FPRS_PER_FMT
);
5635 return gen_rtx_PARALLEL
5638 gen_rtx_EXPR_LIST (VOIDmode
,
5639 gen_rtx_REG (mode1
, FP_RETURN
),
5641 gen_rtx_EXPR_LIST (VOIDmode
,
5642 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
5643 GEN_INT (offset2
))));
5647 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5648 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5649 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5652 mips_function_value_1 (const_tree valtype
, const_tree fn_decl_or_type
,
5653 enum machine_mode mode
)
5661 if (fn_decl_or_type
&& DECL_P (fn_decl_or_type
))
5662 func
= fn_decl_or_type
;
5666 mode
= TYPE_MODE (valtype
);
5667 unsigned_p
= TYPE_UNSIGNED (valtype
);
5669 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5670 return values, promote the mode here too. */
5671 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
5673 /* Handle structures whose fields are returned in $f0/$f2. */
5674 switch (mips_fpr_return_fields (valtype
, fields
))
5677 return mips_return_fpr_single (mode
,
5678 TYPE_MODE (TREE_TYPE (fields
[0])));
5681 return mips_return_fpr_pair (mode
,
5682 TYPE_MODE (TREE_TYPE (fields
[0])),
5683 int_byte_position (fields
[0]),
5684 TYPE_MODE (TREE_TYPE (fields
[1])),
5685 int_byte_position (fields
[1]));
5688 /* If a value is passed in the most significant part of a register, see
5689 whether we have to round the mode up to a whole number of words. */
5690 if (mips_return_in_msb (valtype
))
5692 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
5693 if (size
% UNITS_PER_WORD
!= 0)
5695 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
5696 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5700 /* For EABI, the class of return register depends entirely on MODE.
5701 For example, "struct { some_type x; }" and "union { some_type x; }"
5702 are returned in the same way as a bare "some_type" would be.
5703 Other ABIs only use FPRs for scalar, complex or vector types. */
5704 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
5705 return gen_rtx_REG (mode
, GP_RETURN
);
5710 /* Handle long doubles for n32 & n64. */
5712 return mips_return_fpr_pair (mode
,
5714 DImode
, GET_MODE_SIZE (mode
) / 2);
5716 if (mips_return_mode_in_fpr_p (mode
))
5718 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5719 return mips_return_fpr_pair (mode
,
5720 GET_MODE_INNER (mode
), 0,
5721 GET_MODE_INNER (mode
),
5722 GET_MODE_SIZE (mode
) / 2);
5724 return gen_rtx_REG (mode
, FP_RETURN
);
5728 return gen_rtx_REG (mode
, GP_RETURN
);
5731 /* Implement TARGET_FUNCTION_VALUE. */
5734 mips_function_value (const_tree valtype
, const_tree fn_decl_or_type
,
5735 bool outgoing ATTRIBUTE_UNUSED
)
5737 return mips_function_value_1 (valtype
, fn_decl_or_type
, VOIDmode
);
5740 /* Implement TARGET_LIBCALL_VALUE. */
5743 mips_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5745 return mips_function_value_1 (NULL_TREE
, NULL_TREE
, mode
);
5748 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5750 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5751 Currently, R2 and F0 are only implemented here (C has no complex type). */
5754 mips_function_value_regno_p (const unsigned int regno
)
5756 if (regno
== GP_RETURN
5757 || regno
== FP_RETURN
5758 || (LONG_DOUBLE_TYPE_SIZE
== 128
5759 && FP_RETURN
!= GP_RETURN
5760 && regno
== FP_RETURN
+ 2))
5766 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5767 all BLKmode objects are returned in memory. Under the n32, n64
5768 and embedded ABIs, small structures are returned in a register.
5769 Objects with varying size must still be returned in memory, of
5773 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
5775 return (TARGET_OLDABI
5776 ? TYPE_MODE (type
) == BLKmode
5777 : !IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
5780 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5783 mips_setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
5784 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5787 CUMULATIVE_ARGS local_cum
;
5788 int gp_saved
, fp_saved
;
5790 /* The caller has advanced CUM up to, but not beyond, the last named
5791 argument. Advance a local copy of CUM past the last "real" named
5792 argument, to find out how many registers are left over. */
5793 local_cum
= *get_cumulative_args (cum
);
5794 mips_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
,
5797 /* Found out how many registers we need to save. */
5798 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
5799 fp_saved
= (EABI_FLOAT_VARARGS_P
5800 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
5809 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
5810 REG_PARM_STACK_SPACE (cfun
->decl
)
5811 - gp_saved
* UNITS_PER_WORD
);
5812 mem
= gen_frame_mem (BLKmode
, ptr
);
5813 set_mem_alias_set (mem
, get_varargs_alias_set ());
5815 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
5820 /* We can't use move_block_from_reg, because it will use
5822 enum machine_mode mode
;
5825 /* Set OFF to the offset from virtual_incoming_args_rtx of
5826 the first float register. The FP save area lies below
5827 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5828 off
= (-gp_saved
* UNITS_PER_WORD
) & -UNITS_PER_FPVALUE
;
5829 off
-= fp_saved
* UNITS_PER_FPREG
;
5831 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5833 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
5834 i
+= MAX_FPRS_PER_FMT
)
5838 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
, off
);
5839 mem
= gen_frame_mem (mode
, ptr
);
5840 set_mem_alias_set (mem
, get_varargs_alias_set ());
5841 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
5842 off
+= UNITS_PER_HWFPVALUE
;
5846 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
5847 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
5848 + fp_saved
* UNITS_PER_FPREG
);
5851 /* Implement TARGET_BUILTIN_VA_LIST. */
5854 mips_build_builtin_va_list (void)
5856 if (EABI_FLOAT_VARARGS_P
)
5858 /* We keep 3 pointers, and two offsets.
5860 Two pointers are to the overflow area, which starts at the CFA.
5861 One of these is constant, for addressing into the GPR save area
5862 below it. The other is advanced up the stack through the
5865 The third pointer is to the bottom of the GPR save area.
5866 Since the FPR save area is just below it, we can address
5867 FPR slots off this pointer.
5869 We also keep two one-byte offsets, which are to be subtracted
5870 from the constant pointers to yield addresses in the GPR and
5871 FPR save areas. These are downcounted as float or non-float
5872 arguments are used, and when they get to zero, the argument
5873 must be obtained from the overflow region. */
5874 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
5877 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
5879 f_ovfl
= build_decl (BUILTINS_LOCATION
,
5880 FIELD_DECL
, get_identifier ("__overflow_argptr"),
5882 f_gtop
= build_decl (BUILTINS_LOCATION
,
5883 FIELD_DECL
, get_identifier ("__gpr_top"),
5885 f_ftop
= build_decl (BUILTINS_LOCATION
,
5886 FIELD_DECL
, get_identifier ("__fpr_top"),
5888 f_goff
= build_decl (BUILTINS_LOCATION
,
5889 FIELD_DECL
, get_identifier ("__gpr_offset"),
5890 unsigned_char_type_node
);
5891 f_foff
= build_decl (BUILTINS_LOCATION
,
5892 FIELD_DECL
, get_identifier ("__fpr_offset"),
5893 unsigned_char_type_node
);
5894 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5895 warn on every user file. */
5896 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
5897 array
= build_array_type (unsigned_char_type_node
,
5898 build_index_type (index
));
5899 f_res
= build_decl (BUILTINS_LOCATION
,
5900 FIELD_DECL
, get_identifier ("__reserved"), array
);
5902 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
5903 DECL_FIELD_CONTEXT (f_gtop
) = record
;
5904 DECL_FIELD_CONTEXT (f_ftop
) = record
;
5905 DECL_FIELD_CONTEXT (f_goff
) = record
;
5906 DECL_FIELD_CONTEXT (f_foff
) = record
;
5907 DECL_FIELD_CONTEXT (f_res
) = record
;
5909 TYPE_FIELDS (record
) = f_ovfl
;
5910 DECL_CHAIN (f_ovfl
) = f_gtop
;
5911 DECL_CHAIN (f_gtop
) = f_ftop
;
5912 DECL_CHAIN (f_ftop
) = f_goff
;
5913 DECL_CHAIN (f_goff
) = f_foff
;
5914 DECL_CHAIN (f_foff
) = f_res
;
5916 layout_type (record
);
5920 /* Otherwise, we use 'void *'. */
5921 return ptr_type_node
;
5924 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5927 mips_va_start (tree valist
, rtx nextarg
)
5929 if (EABI_FLOAT_VARARGS_P
)
5931 const CUMULATIVE_ARGS
*cum
;
5932 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5933 tree ovfl
, gtop
, ftop
, goff
, foff
;
5935 int gpr_save_area_size
;
5936 int fpr_save_area_size
;
5939 cum
= &crtl
->args
.info
;
5941 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
5943 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
5945 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5946 f_gtop
= DECL_CHAIN (f_ovfl
);
5947 f_ftop
= DECL_CHAIN (f_gtop
);
5948 f_goff
= DECL_CHAIN (f_ftop
);
5949 f_foff
= DECL_CHAIN (f_goff
);
5951 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5953 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
5955 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
5957 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
5959 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
5962 /* Emit code to initialize OVFL, which points to the next varargs
5963 stack argument. CUM->STACK_WORDS gives the number of stack
5964 words used by named arguments. */
5965 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
5966 if (cum
->stack_words
> 0)
5967 t
= fold_build_pointer_plus_hwi (t
, cum
->stack_words
* UNITS_PER_WORD
);
5968 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
5969 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5971 /* Emit code to initialize GTOP, the top of the GPR save area. */
5972 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
5973 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
5974 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5976 /* Emit code to initialize FTOP, the top of the FPR save area.
5977 This address is gpr_save_area_bytes below GTOP, rounded
5978 down to the next fp-aligned boundary. */
5979 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
5980 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
5981 fpr_offset
&= -UNITS_PER_FPVALUE
;
5983 t
= fold_build_pointer_plus_hwi (t
, -fpr_offset
);
5984 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
5985 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5987 /* Emit code to initialize GOFF, the offset from GTOP of the
5988 next GPR argument. */
5989 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
5990 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
5991 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5993 /* Likewise emit code to initialize FOFF, the offset from FTOP
5994 of the next FPR argument. */
5995 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
5996 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
5997 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6001 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
6002 std_expand_builtin_va_start (valist
, nextarg
);
6006 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
6010 mips_std_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6013 tree addr
, t
, type_size
, rounded_size
, valist_tmp
;
6014 unsigned HOST_WIDE_INT align
, boundary
;
6017 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
6019 type
= build_pointer_type (type
);
6021 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
6022 boundary
= targetm
.calls
.function_arg_boundary (TYPE_MODE (type
), type
);
6024 /* When we align parameter on stack for caller, if the parameter
6025 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6026 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6027 here with caller. */
6028 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
6029 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
6031 boundary
/= BITS_PER_UNIT
;
6033 /* Hoist the valist value into a temporary for the moment. */
6034 valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
6036 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
6037 requires greater alignment, we must perform dynamic alignment. */
6038 if (boundary
> align
)
6040 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
6041 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
6042 gimplify_and_add (t
, pre_p
);
6044 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
6045 fold_build2 (BIT_AND_EXPR
, TREE_TYPE (valist
),
6047 build_int_cst (TREE_TYPE (valist
), -boundary
)));
6048 gimplify_and_add (t
, pre_p
);
6053 /* If the actual alignment is less than the alignment of the type,
6054 adjust the type accordingly so that we don't assume strict alignment
6055 when dereferencing the pointer. */
6056 boundary
*= BITS_PER_UNIT
;
6057 if (boundary
< TYPE_ALIGN (type
))
6059 type
= build_variant_type_copy (type
);
6060 TYPE_ALIGN (type
) = boundary
;
6063 /* Compute the rounded size of the type. */
6064 type_size
= size_in_bytes (type
);
6065 rounded_size
= round_up (type_size
, align
);
6067 /* Reduce rounded_size so it's sharable with the postqueue. */
6068 gimplify_expr (&rounded_size
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
6072 if (PAD_VARARGS_DOWN
&& !integer_zerop (rounded_size
))
6074 /* Small args are padded downward. */
6075 t
= fold_build2_loc (input_location
, GT_EXPR
, sizetype
,
6076 rounded_size
, size_int (align
));
6077 t
= fold_build3 (COND_EXPR
, sizetype
, t
, size_zero_node
,
6078 size_binop (MINUS_EXPR
, rounded_size
, type_size
));
6079 addr
= fold_build_pointer_plus (addr
, t
);
6082 /* Compute new value for AP. */
6083 t
= fold_build_pointer_plus (valist_tmp
, rounded_size
);
6084 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
6085 gimplify_and_add (t
, pre_p
);
6087 addr
= fold_convert (build_pointer_type (type
), addr
);
6090 addr
= build_va_arg_indirect_ref (addr
);
6092 return build_va_arg_indirect_ref (addr
);
6095 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
6098 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6104 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
6106 type
= build_pointer_type (type
);
6108 if (!EABI_FLOAT_VARARGS_P
)
6109 addr
= mips_std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6112 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
6113 tree ovfl
, top
, off
, align
;
6114 HOST_WIDE_INT size
, rsize
, osize
;
6117 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
6118 f_gtop
= DECL_CHAIN (f_ovfl
);
6119 f_ftop
= DECL_CHAIN (f_gtop
);
6120 f_goff
= DECL_CHAIN (f_ftop
);
6121 f_foff
= DECL_CHAIN (f_goff
);
6125 TOP be the top of the GPR or FPR save area;
6126 OFF be the offset from TOP of the next register;
6127 ADDR_RTX be the address of the argument;
6128 SIZE be the number of bytes in the argument type;
6129 RSIZE be the number of bytes used to store the argument
6130 when it's in the register save area; and
6131 OSIZE be the number of bytes used to store it when it's
6132 in the stack overflow area.
6134 The code we want is:
6136 1: off &= -rsize; // round down
6139 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6144 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6145 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6149 [1] and [9] can sometimes be optimized away. */
6151 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
6153 size
= int_size_in_bytes (type
);
6155 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
6156 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
6158 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
6159 unshare_expr (valist
), f_ftop
, NULL_TREE
);
6160 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
6161 unshare_expr (valist
), f_foff
, NULL_TREE
);
6163 /* When va_start saves FPR arguments to the stack, each slot
6164 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6165 argument's precision. */
6166 rsize
= UNITS_PER_HWFPVALUE
;
6168 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6169 (= PARM_BOUNDARY bits). This can be different from RSIZE
6172 (1) On 32-bit targets when TYPE is a structure such as:
6174 struct s { float f; };
6176 Such structures are passed in paired FPRs, so RSIZE
6177 will be 8 bytes. However, the structure only takes
6178 up 4 bytes of memory, so OSIZE will only be 4.
6180 (2) In combinations such as -mgp64 -msingle-float
6181 -fshort-double. Doubles passed in registers will then take
6182 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6183 stack take up UNITS_PER_WORD bytes. */
6184 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
6188 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
6189 unshare_expr (valist
), f_gtop
, NULL_TREE
);
6190 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
6191 unshare_expr (valist
), f_goff
, NULL_TREE
);
6192 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6193 if (rsize
> UNITS_PER_WORD
)
6195 /* [1] Emit code for: off &= -rsize. */
6196 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
6197 build_int_cst (TREE_TYPE (off
), -rsize
));
6198 gimplify_assign (unshare_expr (off
), t
, pre_p
);
6203 /* [2] Emit code to branch if off == 0. */
6204 t
= build2 (NE_EXPR
, boolean_type_node
, unshare_expr (off
),
6205 build_int_cst (TREE_TYPE (off
), 0));
6206 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
6208 /* [5] Emit code for: off -= rsize. We do this as a form of
6209 post-decrement not available to C. */
6210 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
6211 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
6213 /* [4] Emit code for:
6214 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6215 t
= fold_convert (sizetype
, t
);
6216 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
6217 t
= fold_build_pointer_plus (top
, t
);
6218 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
6219 t
= fold_build_pointer_plus_hwi (t
, rsize
- size
);
6220 COND_EXPR_THEN (addr
) = t
;
6222 if (osize
> UNITS_PER_WORD
)
6224 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6225 t
= fold_build_pointer_plus_hwi (unshare_expr (ovfl
), osize
- 1);
6226 u
= build_int_cst (TREE_TYPE (t
), -osize
);
6227 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
, u
);
6228 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
6229 unshare_expr (ovfl
), t
);
6234 /* [10, 11] Emit code for:
6235 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6237 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
6238 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
6239 if (BYTES_BIG_ENDIAN
&& osize
> size
)
6240 t
= fold_build_pointer_plus_hwi (t
, osize
- size
);
6242 /* String [9] and [10, 11] together. */
6244 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
6245 COND_EXPR_ELSE (addr
) = t
;
6247 addr
= fold_convert (build_pointer_type (type
), addr
);
6248 addr
= build_va_arg_indirect_ref (addr
);
6252 addr
= build_va_arg_indirect_ref (addr
);
6257 /* Declare a unique, locally-binding function called NAME, then start
6261 mips_start_unique_function (const char *name
)
6265 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
6266 get_identifier (name
),
6267 build_function_type_list (void_type_node
, NULL_TREE
));
6268 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
6269 NULL_TREE
, void_type_node
);
6270 TREE_PUBLIC (decl
) = 1;
6271 TREE_STATIC (decl
) = 1;
6273 DECL_COMDAT_GROUP (decl
) = DECL_ASSEMBLER_NAME (decl
);
6275 targetm
.asm_out
.unique_section (decl
, 0);
6276 switch_to_section (get_named_section (decl
, NULL
, 0));
6278 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
6279 fputs ("\t.hidden\t", asm_out_file
);
6280 assemble_name (asm_out_file
, name
);
6281 putc ('\n', asm_out_file
);
6284 /* Start a definition of function NAME. MIPS16_P indicates whether the
6285 function contains MIPS16 code. */
6288 mips_start_function_definition (const char *name
, bool mips16_p
)
6291 fprintf (asm_out_file
, "\t.set\tmips16\n");
6293 fprintf (asm_out_file
, "\t.set\tnomips16\n");
6295 if (TARGET_MICROMIPS
)
6296 fprintf (asm_out_file
, "\t.set\tmicromips\n");
6297 #ifdef HAVE_GAS_MICROMIPS
6299 fprintf (asm_out_file
, "\t.set\tnomicromips\n");
6302 if (!flag_inhibit_size_directive
)
6304 fputs ("\t.ent\t", asm_out_file
);
6305 assemble_name (asm_out_file
, name
);
6306 fputs ("\n", asm_out_file
);
6309 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
6311 /* Start the definition proper. */
6312 assemble_name (asm_out_file
, name
);
6313 fputs (":\n", asm_out_file
);
6316 /* End a function definition started by mips_start_function_definition. */
6319 mips_end_function_definition (const char *name
)
6321 if (!flag_inhibit_size_directive
)
6323 fputs ("\t.end\t", asm_out_file
);
6324 assemble_name (asm_out_file
, name
);
6325 fputs ("\n", asm_out_file
);
6329 /* If *STUB_PTR points to a stub, output a comdat-style definition for it,
6330 then free *STUB_PTR. */
6333 mips_finish_stub (mips_one_only_stub
**stub_ptr
)
6335 mips_one_only_stub
*stub
= *stub_ptr
;
6339 const char *name
= stub
->get_name ();
6340 mips_start_unique_function (name
);
6341 mips_start_function_definition (name
, false);
6342 stub
->output_body ();
6343 mips_end_function_definition (name
);
6348 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6351 mips_ok_for_lazy_binding_p (rtx x
)
6353 return (TARGET_USE_GOT
6354 && GET_CODE (x
) == SYMBOL_REF
6355 && !SYMBOL_REF_BIND_NOW_P (x
)
6356 && !mips_symbol_binds_local_p (x
));
6359 /* Load function address ADDR into register DEST. TYPE is as for
6360 mips_expand_call. Return true if we used an explicit lazy-binding
6364 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
6366 /* If we're generating PIC, and this call is to a global function,
6367 try to allow its address to be resolved lazily. This isn't
6368 possible for sibcalls when $gp is call-saved because the value
6369 of $gp on entry to the stub would be our caller's gp, not ours. */
6370 if (TARGET_EXPLICIT_RELOCS
6371 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
6372 && mips_ok_for_lazy_binding_p (addr
))
6374 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
6375 emit_insn (gen_rtx_SET (VOIDmode
, dest
, addr
));
6380 mips_emit_move (dest
, addr
);
6385 /* Each locally-defined hard-float MIPS16 function has a local symbol
6386 associated with it. This hash table maps the function symbol (FUNC)
6387 to the local symbol (LOCAL). */
6388 struct GTY(()) mips16_local_alias
{
6392 static GTY ((param_is (struct mips16_local_alias
))) htab_t mips16_local_aliases
;
6394 /* Hash table callbacks for mips16_local_aliases. */
6397 mips16_local_aliases_hash (const void *entry
)
6399 const struct mips16_local_alias
*alias
;
6401 alias
= (const struct mips16_local_alias
*) entry
;
6402 return htab_hash_string (XSTR (alias
->func
, 0));
6406 mips16_local_aliases_eq (const void *entry1
, const void *entry2
)
6408 const struct mips16_local_alias
*alias1
, *alias2
;
6410 alias1
= (const struct mips16_local_alias
*) entry1
;
6411 alias2
= (const struct mips16_local_alias
*) entry2
;
6412 return rtx_equal_p (alias1
->func
, alias2
->func
);
6415 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6416 Return a local alias for it, creating a new one if necessary. */
6419 mips16_local_alias (rtx func
)
6421 struct mips16_local_alias
*alias
, tmp_alias
;
6424 /* Create the hash table if this is the first call. */
6425 if (mips16_local_aliases
== NULL
)
6426 mips16_local_aliases
= htab_create_ggc (37, mips16_local_aliases_hash
,
6427 mips16_local_aliases_eq
, NULL
);
6429 /* Look up the function symbol, creating a new entry if need be. */
6430 tmp_alias
.func
= func
;
6431 slot
= htab_find_slot (mips16_local_aliases
, &tmp_alias
, INSERT
);
6432 gcc_assert (slot
!= NULL
);
6434 alias
= (struct mips16_local_alias
*) *slot
;
6437 const char *func_name
, *local_name
;
6440 /* Create a new SYMBOL_REF for the local symbol. The choice of
6441 __fn_local_* is based on the __fn_stub_* names that we've
6442 traditionally used for the non-MIPS16 stub. */
6443 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
6444 local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
6445 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
6446 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
6448 /* Create a new structure to represent the mapping. */
6449 alias
= ggc_alloc_mips16_local_alias ();
6451 alias
->local
= local
;
6454 return alias
->local
;
6457 /* A chained list of functions for which mips16_build_call_stub has already
6458 generated a stub. NAME is the name of the function and FP_RET_P is true
6459 if the function returns a value in floating-point registers. */
6460 struct mips16_stub
{
6461 struct mips16_stub
*next
;
6465 static struct mips16_stub
*mips16_stubs
;
6467 /* Return the two-character string that identifies floating-point
6468 return mode MODE in the name of a MIPS16 function stub. */
6471 mips16_call_stub_mode_suffix (enum machine_mode mode
)
6475 else if (mode
== DFmode
)
6477 else if (mode
== SCmode
)
6479 else if (mode
== DCmode
)
6481 else if (mode
== V2SFmode
)
6487 /* Write instructions to move a 32-bit value between general register
6488 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6489 from GPREG to FPREG and 'f' to move in the opposite direction. */
6492 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6494 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6495 reg_names
[gpreg
], reg_names
[fpreg
]);
6498 /* Likewise for 64-bit values. */
6501 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6504 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
6505 reg_names
[gpreg
], reg_names
[fpreg
]);
6506 else if (TARGET_FLOAT64
)
6508 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6509 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6510 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
6511 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
6515 /* Move the least-significant word. */
6516 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6517 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6518 /* ...then the most significant word. */
6519 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6520 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
6524 /* Write out code to move floating-point arguments into or out of
6525 general registers. FP_CODE is the code describing which arguments
6526 are present (see the comment above the definition of CUMULATIVE_ARGS
6527 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6530 mips_output_args_xfer (int fp_code
, char direction
)
6532 unsigned int gparg
, fparg
, f
;
6533 CUMULATIVE_ARGS cum
;
6535 /* This code only works for o32 and o64. */
6536 gcc_assert (TARGET_OLDABI
);
6538 mips_init_cumulative_args (&cum
, NULL
);
6540 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6542 enum machine_mode mode
;
6543 struct mips_arg_info info
;
6547 else if ((f
& 3) == 2)
6552 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
6553 gparg
= mips_arg_regno (&info
, false);
6554 fparg
= mips_arg_regno (&info
, true);
6557 mips_output_32bit_xfer (direction
, gparg
, fparg
);
6559 mips_output_64bit_xfer (direction
, gparg
, fparg
);
6561 mips_function_arg_advance (pack_cumulative_args (&cum
), mode
, NULL
, true);
6565 /* Write a MIPS16 stub for the current function. This stub is used
6566 for functions which take arguments in the floating-point registers.
6567 It is normal-mode code that moves the floating-point arguments
6568 into the general registers and then jumps to the MIPS16 code. */
6571 mips16_build_function_stub (void)
6573 const char *fnname
, *alias_name
, *separator
;
6574 char *secname
, *stubname
;
6579 /* Create the name of the stub, and its unique section. */
6580 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
6581 alias
= mips16_local_alias (symbol
);
6583 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
6584 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
6585 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
6586 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
6588 /* Build a decl for the stub. */
6589 stubdecl
= build_decl (BUILTINS_LOCATION
,
6590 FUNCTION_DECL
, get_identifier (stubname
),
6591 build_function_type_list (void_type_node
, NULL_TREE
));
6592 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6593 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6594 RESULT_DECL
, NULL_TREE
, void_type_node
);
6596 /* Output a comment. */
6597 fprintf (asm_out_file
, "\t# Stub function for %s (",
6598 current_function_name ());
6600 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
6602 fprintf (asm_out_file
, "%s%s", separator
,
6603 (f
& 3) == 1 ? "float" : "double");
6606 fprintf (asm_out_file
, ")\n");
6608 /* Start the function definition. */
6609 assemble_start_function (stubdecl
, stubname
);
6610 mips_start_function_definition (stubname
, false);
6612 /* If generating pic2 code, either set up the global pointer or
6614 if (TARGET_ABICALLS_PIC2
)
6616 if (TARGET_ABSOLUTE_ABICALLS
)
6617 fprintf (asm_out_file
, "\t.option\tpic0\n");
6620 output_asm_insn ("%(.cpload\t%^%)", NULL
);
6621 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6622 target function is. Use a local GOT access when loading the
6623 symbol, to cut down on the number of unnecessary GOT entries
6624 for stubs that aren't needed. */
6625 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
6630 /* Load the address of the MIPS16 function into $25. Do this first so
6631 that targets with coprocessor interlocks can use an MFC1 to fill the
6633 output_asm_insn ("la\t%^,%0", &symbol
);
6635 /* Move the arguments from floating-point registers to general registers. */
6636 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
6638 /* Jump to the MIPS16 function. */
6639 output_asm_insn ("jr\t%^", NULL
);
6641 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
6642 fprintf (asm_out_file
, "\t.option\tpic2\n");
6644 mips_end_function_definition (stubname
);
6646 /* If the linker needs to create a dynamic symbol for the target
6647 function, it will associate the symbol with the stub (which,
6648 unlike the target function, follows the proper calling conventions).
6649 It is therefore useful to have a local alias for the target function,
6650 so that it can still be identified as MIPS16 code. As an optimization,
6651 this symbol can also be used for indirect MIPS16 references from
6652 within this file. */
6653 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
6655 switch_to_section (function_section (current_function_decl
));
6658 /* The current function is a MIPS16 function that returns a value in an FPR.
6659 Copy the return value from its soft-float to its hard-float location.
6660 libgcc2 has special non-MIPS16 helper functions for each case. */
6663 mips16_copy_fpr_return_value (void)
6665 rtx fn
, insn
, retval
;
6667 enum machine_mode return_mode
;
6670 return_type
= DECL_RESULT (current_function_decl
);
6671 return_mode
= DECL_MODE (return_type
);
6673 name
= ACONCAT (("__mips16_ret_",
6674 mips16_call_stub_mode_suffix (return_mode
),
6676 fn
= mips16_stub_function (name
);
6678 /* The function takes arguments in $2 (and possibly $3), so calls
6679 to it cannot be lazily bound. */
6680 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
6682 /* Model the call as something that takes the GPR return value as
6683 argument and returns an "updated" value. */
6684 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
6685 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
6686 const0_rtx
, NULL_RTX
, false);
6687 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
6690 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6691 RETVAL is the location of the return value, or null if this is
6692 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6693 arguments and FP_CODE is the code built by mips_function_arg;
6694 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6696 There are three alternatives:
6698 - If a stub was needed, emit the call and return the call insn itself.
6700 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6701 to the new target and return null.
6703 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6706 A stub is needed for calls to functions that, in normal mode,
6707 receive arguments in FPRs or return values in FPRs. The stub
6708 copies the arguments from their soft-float positions to their
6709 hard-float positions, calls the real function, then copies the
6710 return value from its hard-float position to its soft-float
6713 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6714 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6715 automatically redirects the JAL to the stub, otherwise the JAL
6716 continues to call FN directly. */
6719 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
6723 struct mips16_stub
*l
;
6726 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6727 we were invoked with the -msoft-float option. */
6728 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
6731 /* Figure out whether the value might come back in a floating-point
6733 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
6735 /* We don't need to do anything if there were no floating-point
6736 arguments and the value will not be returned in a floating-point
6738 if (fp_code
== 0 && !fp_ret_p
)
6741 /* We don't need to do anything if this is a call to a special
6742 MIPS16 support function. */
6744 if (mips16_stub_function_p (fn
))
6747 /* If we're calling a locally-defined MIPS16 function, we know that
6748 it will return values in both the "soft-float" and "hard-float"
6749 registers. There is no need to use a stub to move the latter
6751 if (fp_code
== 0 && mips16_local_function_p (fn
))
6754 /* This code will only work for o32 and o64 abis. The other ABI's
6755 require more sophisticated support. */
6756 gcc_assert (TARGET_OLDABI
);
6758 /* If we're calling via a function pointer, use one of the magic
6759 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6760 Each stub expects the function address to arrive in register $2. */
6761 if (GET_CODE (fn
) != SYMBOL_REF
6762 || !call_insn_operand (fn
, VOIDmode
))
6765 rtx stub_fn
, insn
, addr
;
6768 /* If this is a locally-defined and locally-binding function,
6769 avoid the stub by calling the local alias directly. */
6770 if (mips16_local_function_p (fn
))
6772 *fn_ptr
= mips16_local_alias (fn
);
6776 /* Create a SYMBOL_REF for the libgcc.a function. */
6778 sprintf (buf
, "__mips16_call_stub_%s_%d",
6779 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
6782 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
6783 stub_fn
= mips16_stub_function (buf
);
6785 /* The function uses $2 as an argument, so calls to it
6786 cannot be lazily bound. */
6787 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
6789 /* Load the target function into $2. */
6790 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
6791 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
6793 /* Emit the call. */
6794 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
6795 args_size
, NULL_RTX
, lazy_p
);
6797 /* Tell GCC that this call does indeed use the value of $2. */
6798 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
6800 /* If we are handling a floating-point return value, we need to
6801 save $18 in the function prologue. Putting a note on the
6802 call will mean that df_regs_ever_live_p ($18) will be true if the
6803 call is not eliminated, and we can check that in the prologue
6806 CALL_INSN_FUNCTION_USAGE (insn
) =
6807 gen_rtx_EXPR_LIST (VOIDmode
,
6808 gen_rtx_CLOBBER (VOIDmode
,
6809 gen_rtx_REG (word_mode
, 18)),
6810 CALL_INSN_FUNCTION_USAGE (insn
));
6815 /* We know the function we are going to call. If we have already
6816 built a stub, we don't need to do anything further. */
6817 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
6818 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
6819 if (strcmp (l
->name
, fnname
) == 0)
6824 const char *separator
;
6825 char *secname
, *stubname
;
6826 tree stubid
, stubdecl
;
6829 /* If the function does not return in FPRs, the special stub
6833 If the function does return in FPRs, the stub section is named
6834 .mips16.call.fp.FNNAME
6836 Build a decl for the stub. */
6837 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
6839 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
6841 stubid
= get_identifier (stubname
);
6842 stubdecl
= build_decl (BUILTINS_LOCATION
,
6843 FUNCTION_DECL
, stubid
,
6844 build_function_type_list (void_type_node
,
6846 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6847 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6848 RESULT_DECL
, NULL_TREE
,
6851 /* Output a comment. */
6852 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
6854 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
6858 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6860 fprintf (asm_out_file
, "%s%s", separator
,
6861 (f
& 3) == 1 ? "float" : "double");
6864 fprintf (asm_out_file
, ")\n");
6866 /* Start the function definition. */
6867 assemble_start_function (stubdecl
, stubname
);
6868 mips_start_function_definition (stubname
, false);
6872 fprintf (asm_out_file
, "\t.cfi_startproc\n");
6874 /* Create a fake CFA 4 bytes below the stack pointer.
6875 This works around unwinders (like libgcc's) that expect
6876 the CFA for non-signal frames to be unique. */
6877 fprintf (asm_out_file
, "\t.cfi_def_cfa 29,-4\n");
6879 /* "Save" $sp in itself so we don't use the fake CFA.
6880 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6881 fprintf (asm_out_file
, "\t.cfi_escape 0x16,29,1,0x6d\n");
6885 /* Load the address of the MIPS16 function into $25. Do this
6886 first so that targets with coprocessor interlocks can use
6887 an MFC1 to fill the delay slot. */
6888 if (TARGET_EXPLICIT_RELOCS
)
6890 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
6891 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
6894 output_asm_insn ("la\t%^,%0", &fn
);
6897 /* Move the arguments from general registers to floating-point
6899 mips_output_args_xfer (fp_code
, 't');
6903 /* Save the return address in $18 and call the non-MIPS16 function.
6904 The stub's caller knows that $18 might be clobbered, even though
6905 $18 is usually a call-saved register. */
6906 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
6907 reg_names
[GP_REG_FIRST
+ 18], reg_names
[RETURN_ADDR_REGNUM
]);
6908 output_asm_insn (MIPS_CALL ("jal", &fn
, 0, -1), &fn
);
6909 fprintf (asm_out_file
, "\t.cfi_register 31,18\n");
6911 /* Move the result from floating-point registers to
6912 general registers. */
6913 switch (GET_MODE (retval
))
6916 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_BIG_ENDIAN
,
6918 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6920 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_LITTLE_ENDIAN
,
6921 TARGET_LITTLE_ENDIAN
6922 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6924 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
6926 /* On 64-bit targets, complex floats are returned in
6927 a single GPR, such that "sd" on a suitably-aligned
6928 target would store the value correctly. */
6929 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6930 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6931 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6932 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6933 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
6934 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
6935 fprintf (asm_out_file
, "\tdsrl\t%s,%s,32\n",
6936 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6937 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6938 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
6939 reg_names
[GP_RETURN
],
6940 reg_names
[GP_RETURN
],
6941 reg_names
[GP_RETURN
+ 1]);
6946 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6950 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
6951 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
6955 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6961 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
6962 fprintf (asm_out_file
, "\t.cfi_endproc\n");
6966 /* Jump to the previously-loaded address. */
6967 output_asm_insn ("jr\t%^", NULL
);
6970 #ifdef ASM_DECLARE_FUNCTION_SIZE
6971 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
6974 mips_end_function_definition (stubname
);
6976 /* Record this stub. */
6977 l
= XNEW (struct mips16_stub
);
6978 l
->name
= xstrdup (fnname
);
6979 l
->fp_ret_p
= fp_ret_p
;
6980 l
->next
= mips16_stubs
;
6984 /* If we expect a floating-point return value, but we've built a
6985 stub which does not expect one, then we're in trouble. We can't
6986 use the existing stub, because it won't handle the floating-point
6987 value. We can't build a new stub, because the linker won't know
6988 which stub to use for the various calls in this object file.
6989 Fortunately, this case is illegal, since it means that a function
6990 was declared in two different ways in a single compilation. */
6991 if (fp_ret_p
&& !l
->fp_ret_p
)
6992 error ("cannot handle inconsistent calls to %qs", fnname
);
6994 if (retval
== NULL_RTX
)
6995 insn
= gen_call_internal_direct (fn
, args_size
);
6997 insn
= gen_call_value_internal_direct (retval
, fn
, args_size
);
6998 insn
= mips_emit_call_insn (insn
, fn
, fn
, false);
7000 /* If we are calling a stub which handles a floating-point return
7001 value, we need to arrange to save $18 in the prologue. We do this
7002 by marking the function call as using the register. The prologue
7003 will later see that it is used, and emit code to save it. */
7005 CALL_INSN_FUNCTION_USAGE (insn
) =
7006 gen_rtx_EXPR_LIST (VOIDmode
,
7007 gen_rtx_CLOBBER (VOIDmode
,
7008 gen_rtx_REG (word_mode
, 18)),
7009 CALL_INSN_FUNCTION_USAGE (insn
));
7014 /* Expand a call of type TYPE. RESULT is where the result will go (null
7015 for "call"s and "sibcall"s), ADDR is the address of the function,
7016 ARGS_SIZE is the size of the arguments and AUX is the value passed
7017 to us by mips_function_arg. LAZY_P is true if this call already
7018 involves a lazily-bound function address (such as when calling
7019 functions through a MIPS16 hard-float stub).
7021 Return the call itself. */
7024 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
7025 rtx args_size
, rtx aux
, bool lazy_p
)
7027 rtx orig_addr
, pattern
, insn
;
7030 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
7031 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
7034 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
7039 if (!call_insn_operand (addr
, VOIDmode
))
7041 if (type
== MIPS_CALL_EPILOGUE
)
7042 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
7044 addr
= gen_reg_rtx (Pmode
);
7045 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
7050 rtx (*fn
) (rtx
, rtx
);
7052 if (type
== MIPS_CALL_SIBCALL
)
7053 fn
= gen_sibcall_internal
;
7055 fn
= gen_call_internal
;
7057 pattern
= fn (addr
, args_size
);
7059 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
7061 /* Handle return values created by mips_return_fpr_pair. */
7062 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
7065 if (type
== MIPS_CALL_SIBCALL
)
7066 fn
= gen_sibcall_value_multiple_internal
;
7068 fn
= gen_call_value_multiple_internal
;
7070 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
7071 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
7072 pattern
= fn (reg1
, addr
, args_size
, reg2
);
7076 rtx (*fn
) (rtx
, rtx
, rtx
);
7078 if (type
== MIPS_CALL_SIBCALL
)
7079 fn
= gen_sibcall_value_internal
;
7081 fn
= gen_call_value_internal
;
7083 /* Handle return values created by mips_return_fpr_single. */
7084 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
7085 result
= XEXP (XVECEXP (result
, 0, 0), 0);
7086 pattern
= fn (result
, addr
, args_size
);
7089 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
7092 /* Split call instruction INSN into a $gp-clobbering call and
7093 (where necessary) an instruction to restore $gp from its save slot.
7094 CALL_PATTERN is the pattern of the new call. */
7097 mips_split_call (rtx insn
, rtx call_pattern
)
7099 emit_call_insn (call_pattern
);
7100 if (!find_reg_note (insn
, REG_NORETURN
, 0))
7101 /* Pick a temporary register that is suitable for both MIPS16 and
7102 non-MIPS16 code. $4 and $5 are used for returning complex double
7103 values in soft-float code, so $6 is the first suitable candidate. */
7104 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 2));
7107 /* Return true if a call to DECL may need to use JALX. */
7110 mips_call_may_need_jalx_p (tree decl
)
7112 /* If the current translation unit would use a different mode for DECL,
7113 assume that the call needs JALX. */
7114 if (mips_get_compress_mode (decl
) != TARGET_COMPRESSION
)
7117 /* mips_get_compress_mode is always accurate for locally-binding
7118 functions in the current translation unit. */
7119 if (!DECL_EXTERNAL (decl
) && targetm
.binds_local_p (decl
))
7122 /* When -minterlink-compressed is in effect, assume that functions
7123 could use a different encoding mode unless an attribute explicitly
7124 tells us otherwise. */
7125 if (TARGET_INTERLINK_COMPRESSED
)
7127 if (!TARGET_COMPRESSION
7128 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
)) ==0)
7130 if (TARGET_COMPRESSION
7131 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
)) == 0)
7138 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7141 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
7143 if (!TARGET_SIBCALLS
)
7146 /* Interrupt handlers need special epilogue code and therefore can't
7148 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
7151 /* Direct Js are only possible to functions that use the same ISA encoding.
7152 There is no JX counterpoart of JALX. */
7154 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
)
7155 && mips_call_may_need_jalx_p (decl
))
7158 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7159 require $gp to be valid on entry, so sibcalls can only use stubs
7160 if $gp is call-clobbered. */
7162 && TARGET_CALL_SAVED_GP
7163 && !TARGET_ABICALLS_PIC0
7164 && !targetm
.binds_local_p (decl
))
7171 /* Emit code to move general operand SRC into condition-code
7172 register DEST given that SCRATCH is a scratch TFmode FPR.
7179 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
7182 mips_expand_fcc_reload (rtx dest
, rtx src
, rtx scratch
)
7186 /* Change the source to SFmode. */
7188 src
= adjust_address (src
, SFmode
, 0);
7189 else if (REG_P (src
) || GET_CODE (src
) == SUBREG
)
7190 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
7192 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
7193 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + MAX_FPRS_PER_FMT
);
7195 mips_emit_move (copy_rtx (fp1
), src
);
7196 mips_emit_move (copy_rtx (fp2
), CONST0_RTX (SFmode
));
7197 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
7200 /* Implement MOVE_BY_PIECES_P. */
7203 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7207 /* movmemsi is meant to generate code that is at least as good as
7208 move_by_pieces. However, movmemsi effectively uses a by-pieces
7209 implementation both for moves smaller than a word and for
7210 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7211 bytes. We should allow the tree-level optimisers to do such
7212 moves by pieces, as it often exposes other optimization
7213 opportunities. We might as well continue to use movmemsi at
7214 the rtl level though, as it produces better code when
7215 scheduling is disabled (such as at -O). */
7216 if (currently_expanding_to_rtl
)
7218 if (align
< BITS_PER_WORD
)
7219 return size
< UNITS_PER_WORD
;
7220 return size
<= MIPS_MAX_MOVE_BYTES_STRAIGHT
;
7222 /* The default value. If this becomes a target hook, we should
7223 call the default definition instead. */
7224 return (move_by_pieces_ninsns (size
, align
, MOVE_MAX_PIECES
+ 1)
7225 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
7228 /* Implement STORE_BY_PIECES_P. */
7231 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7233 /* Storing by pieces involves moving constants into registers
7234 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7235 We need to decide whether it is cheaper to load the address of
7236 constant data into a register and use a block move instead. */
7238 /* If the data is only byte aligned, then:
7240 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7241 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7244 (a2) A block move of 4 bytes from aligned source data can use an
7245 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7246 4 SBs that we would generate when storing by pieces. */
7247 if (align
<= BITS_PER_UNIT
)
7250 /* If the data is 2-byte aligned, then:
7252 (b1) A block move of less than 4 bytes would use a combination of LBs,
7253 LHs, SBs and SHs. We get better code by using single-instruction
7254 LIs, SBs and SHs instead.
7256 (b2) A block move of 4 bytes from aligned source data would again use
7257 an LW/SWL/SWR sequence. In most cases, loading the address of
7258 the source data would require at least one extra instruction.
7259 It is often more efficient to use 2 single-instruction LIs and
7262 (b3) A block move of up to 3 additional bytes would be like (b1).
7264 (b4) A block move of 8 bytes from aligned source data can use two
7265 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7266 sequences are better than the 4 LIs and 4 SHs that we'd generate
7267 when storing by pieces.
7269 The reasoning for higher alignments is similar:
7271 (c1) A block move of less than 4 bytes would be the same as (b1).
7273 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7274 loading the address of the source data would typically require
7275 at least one extra instruction. It is generally better to use
7278 (c3) A block move of up to 3 additional bytes would be like (b1).
7280 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7281 LD/SD sequence, and in these cases we've traditionally preferred
7282 the memory copy over the more bulky constant moves. */
7286 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7287 Assume that the areas do not overlap. */
7290 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
7292 HOST_WIDE_INT offset
, delta
;
7293 unsigned HOST_WIDE_INT bits
;
7295 enum machine_mode mode
;
7298 /* Work out how many bits to move at a time. If both operands have
7299 half-word alignment, it is usually better to move in half words.
7300 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7301 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7302 Otherwise move word-sized chunks. */
7303 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
7304 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
7305 bits
= BITS_PER_WORD
/ 2;
7307 bits
= BITS_PER_WORD
;
7309 mode
= mode_for_size (bits
, MODE_INT
, 0);
7310 delta
= bits
/ BITS_PER_UNIT
;
7312 /* Allocate a buffer for the temporary registers. */
7313 regs
= XALLOCAVEC (rtx
, length
/ delta
);
7315 /* Load as many BITS-sized chunks as possible. Use a normal load if
7316 the source has enough alignment, otherwise use left/right pairs. */
7317 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7319 regs
[i
] = gen_reg_rtx (mode
);
7320 if (MEM_ALIGN (src
) >= bits
)
7321 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
7324 rtx part
= adjust_address (src
, BLKmode
, offset
);
7325 set_mem_size (part
, delta
);
7326 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0, 0))
7331 /* Copy the chunks to the destination. */
7332 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7333 if (MEM_ALIGN (dest
) >= bits
)
7334 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
7337 rtx part
= adjust_address (dest
, BLKmode
, offset
);
7338 set_mem_size (part
, delta
);
7339 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
7343 /* Mop up any left-over bytes. */
7344 if (offset
< length
)
7346 src
= adjust_address (src
, BLKmode
, offset
);
7347 dest
= adjust_address (dest
, BLKmode
, offset
);
7348 move_by_pieces (dest
, src
, length
- offset
,
7349 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
7353 /* Helper function for doing a loop-based block operation on memory
7354 reference MEM. Each iteration of the loop will operate on LENGTH
7357 Create a new base register for use within the loop and point it to
7358 the start of MEM. Create a new memory reference that uses this
7359 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7362 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
7363 rtx
*loop_reg
, rtx
*loop_mem
)
7365 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
7367 /* Although the new mem does not refer to a known location,
7368 it does keep up to LENGTH bytes of alignment. */
7369 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
7370 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
7373 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7374 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7375 the memory regions do not overlap. */
7378 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
7379 HOST_WIDE_INT bytes_per_iter
)
7381 rtx label
, src_reg
, dest_reg
, final_src
, test
;
7382 HOST_WIDE_INT leftover
;
7384 leftover
= length
% bytes_per_iter
;
7387 /* Create registers and memory references for use within the loop. */
7388 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
7389 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
7391 /* Calculate the value that SRC_REG should have after the last iteration
7393 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
7396 /* Emit the start of the loop. */
7397 label
= gen_label_rtx ();
7400 /* Emit the loop body. */
7401 mips_block_move_straight (dest
, src
, bytes_per_iter
);
7403 /* Move on to the next block. */
7404 mips_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
7405 mips_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
7407 /* Emit the loop condition. */
7408 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
7409 if (Pmode
== DImode
)
7410 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
7412 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
7414 /* Mop up any left-over bytes. */
7416 mips_block_move_straight (dest
, src
, leftover
);
7419 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7420 memory reference SRC to memory reference DEST. */
7423 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
7425 if (CONST_INT_P (length
))
7427 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
7429 mips_block_move_straight (dest
, src
, INTVAL (length
));
7434 mips_block_move_loop (dest
, src
, INTVAL (length
),
7435 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
7442 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7445 mips_expand_synci_loop (rtx begin
, rtx end
)
7447 rtx inc
, label
, end_label
, cmp_result
, mask
, length
;
7449 /* Create end_label. */
7450 end_label
= gen_label_rtx ();
7452 /* Check if begin equals end. */
7453 cmp_result
= gen_rtx_EQ (VOIDmode
, begin
, end
);
7454 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7456 /* Load INC with the cache line size (rdhwr INC,$1). */
7457 inc
= gen_reg_rtx (Pmode
);
7458 emit_insn (PMODE_INSN (gen_rdhwr_synci_step
, (inc
)));
7460 /* Check if inc is 0. */
7461 cmp_result
= gen_rtx_EQ (VOIDmode
, inc
, const0_rtx
);
7462 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7464 /* Calculate mask. */
7465 mask
= mips_force_unary (Pmode
, NEG
, inc
);
7467 /* Mask out begin by mask. */
7468 begin
= mips_force_binary (Pmode
, AND
, begin
, mask
);
7470 /* Calculate length. */
7471 length
= mips_force_binary (Pmode
, MINUS
, end
, begin
);
7473 /* Loop back to here. */
7474 label
= gen_label_rtx ();
7477 emit_insn (gen_synci (begin
));
7479 /* Update length. */
7480 mips_emit_binary (MINUS
, length
, length
, inc
);
7483 mips_emit_binary (PLUS
, begin
, begin
, inc
);
7485 /* Check if length is greater than 0. */
7486 cmp_result
= gen_rtx_GT (VOIDmode
, length
, const0_rtx
);
7487 emit_jump_insn (gen_condjump (cmp_result
, label
));
7489 emit_label (end_label
);
7492 /* Expand a QI or HI mode atomic memory operation.
7494 GENERATOR contains a pointer to the gen_* function that generates
7495 the SI mode underlying atomic operation using masks that we
7498 RESULT is the return register for the operation. Its value is NULL
7501 MEM is the location of the atomic access.
7503 OLDVAL is the first operand for the operation.
7505 NEWVAL is the optional second operand for the operation. Its value
7506 is NULL if unused. */
7509 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
7510 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
7512 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
7513 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
7515 enum machine_mode mode
;
7517 mode
= GET_MODE (mem
);
7519 /* Compute the address of the containing SImode value. */
7520 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
7521 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
7522 force_reg (Pmode
, GEN_INT (-4)));
7524 /* Create a memory reference for it. */
7525 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
7526 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
7527 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
7529 /* Work out the byte offset of the QImode or HImode value,
7530 counting from the least significant byte. */
7531 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
7532 if (TARGET_BIG_ENDIAN
)
7533 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
7535 /* Multiply by eight to convert the shift value from bytes to bits. */
7536 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
7538 /* Make the final shift an SImode value, so that it can be used in
7539 SImode operations. */
7540 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
7542 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7543 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
7544 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
7545 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
7547 /* Compute the equivalent exclusive mask. */
7548 inverted_mask
= gen_reg_rtx (SImode
);
7549 emit_insn (gen_rtx_SET (VOIDmode
, inverted_mask
,
7550 gen_rtx_NOT (SImode
, mask
)));
7552 /* Shift the old value into place. */
7553 if (oldval
!= const0_rtx
)
7555 oldval
= convert_modes (SImode
, mode
, oldval
, true);
7556 oldval
= force_reg (SImode
, oldval
);
7557 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
7560 /* Do the same for the new value. */
7561 if (newval
&& newval
!= const0_rtx
)
7563 newval
= convert_modes (SImode
, mode
, newval
, true);
7564 newval
= force_reg (SImode
, newval
);
7565 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
7568 /* Do the SImode atomic access. */
7570 res
= gen_reg_rtx (SImode
);
7572 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
7574 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
7576 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
7582 /* Shift and convert the result. */
7583 mips_emit_binary (AND
, res
, res
, mask
);
7584 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
7585 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
7589 /* Return true if it is possible to use left/right accesses for a
7590 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7591 When returning true, update *LEFT and *RIGHT as follows:
7593 *LEFT is a QImode reference to the first byte if big endian or
7594 the last byte if little endian. This address can be used in the
7595 left-side instructions (LWL, SWL, LDL, SDL).
7597 *RIGHT is a QImode reference to the opposite end of the field and
7598 can be used in the patterning right-side instruction. */
7601 mips_get_unaligned_mem (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
7602 rtx
*left
, rtx
*right
)
7606 /* Check that the size is valid. */
7607 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
7610 /* We can only access byte-aligned values. Since we are always passed
7611 a reference to the first byte of the field, it is not necessary to
7612 do anything with BITPOS after this check. */
7613 if (bitpos
% BITS_PER_UNIT
!= 0)
7616 /* Reject aligned bitfields: we want to use a normal load or store
7617 instead of a left/right pair. */
7618 if (MEM_ALIGN (op
) >= width
)
7621 /* Get references to both ends of the field. */
7622 first
= adjust_address (op
, QImode
, 0);
7623 last
= adjust_address (op
, QImode
, width
/ BITS_PER_UNIT
- 1);
7625 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7626 correspond to the MSB and RIGHT to the LSB. */
7627 if (TARGET_BIG_ENDIAN
)
7628 *left
= first
, *right
= last
;
7630 *left
= last
, *right
= first
;
7635 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7636 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7637 the operation is the equivalent of:
7639 (set DEST (*_extract SRC WIDTH BITPOS))
7641 Return true on success. */
7644 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7645 HOST_WIDE_INT bitpos
, bool unsigned_p
)
7647 rtx left
, right
, temp
;
7648 rtx dest1
= NULL_RTX
;
7650 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7651 be a DImode, create a new temp and emit a zero extend at the end. */
7652 if (GET_MODE (dest
) == DImode
7654 && GET_MODE_BITSIZE (SImode
) == width
)
7657 dest
= gen_reg_rtx (SImode
);
7660 if (!mips_get_unaligned_mem (src
, width
, bitpos
, &left
, &right
))
7663 temp
= gen_reg_rtx (GET_MODE (dest
));
7664 if (GET_MODE (dest
) == DImode
)
7666 emit_insn (gen_mov_ldl (temp
, src
, left
));
7667 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
7671 emit_insn (gen_mov_lwl (temp
, src
, left
));
7672 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
7675 /* If we were loading 32bits and the original register was DI then
7676 sign/zero extend into the orignal dest. */
7680 emit_insn (gen_zero_extendsidi2 (dest1
, dest
));
7682 emit_insn (gen_extendsidi2 (dest1
, dest
));
7687 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7688 BITPOS and SRC are the operands passed to the expander; the operation
7689 is the equivalent of:
7691 (set (zero_extract DEST WIDTH BITPOS) SRC)
7693 Return true on success. */
7696 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7697 HOST_WIDE_INT bitpos
)
7700 enum machine_mode mode
;
7702 if (!mips_get_unaligned_mem (dest
, width
, bitpos
, &left
, &right
))
7705 mode
= mode_for_size (width
, MODE_INT
, 0);
7706 src
= gen_lowpart (mode
, src
);
7709 emit_insn (gen_mov_sdl (dest
, src
, left
));
7710 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
7714 emit_insn (gen_mov_swl (dest
, src
, left
));
7715 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
7720 /* Return true if X is a MEM with the same size as MODE. */
7723 mips_mem_fits_mode_p (enum machine_mode mode
, rtx x
)
7726 && MEM_SIZE_KNOWN_P (x
)
7727 && MEM_SIZE (x
) == GET_MODE_SIZE (mode
));
7730 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7731 source of an "ext" instruction or the destination of an "ins"
7732 instruction. OP must be a register operand and the following
7733 conditions must hold:
7735 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7736 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7737 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7739 Also reject lengths equal to a word as they are better handled
7740 by the move patterns. */
7743 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
7745 if (!ISA_HAS_EXT_INS
7746 || !register_operand (op
, VOIDmode
)
7747 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
7750 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
7753 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
7759 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7760 operation if MAXLEN is the maxium length of consecutive bits that
7761 can make up MASK. MODE is the mode of the operation. See
7762 mask_low_and_shift_len for the actual definition. */
7765 mask_low_and_shift_p (enum machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
7767 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
7770 /* Return true iff OP1 and OP2 are valid operands together for the
7771 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7772 see the table in the comment before the pattern. */
7775 and_operands_ok (enum machine_mode mode
, rtx op1
, rtx op2
)
7777 return (memory_operand (op1
, mode
)
7778 ? and_load_operand (op2
, mode
)
7779 : and_reg_operand (op2
, mode
));
7782 /* The canonical form of a mask-low-and-shift-left operation is
7783 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7784 cleared. Thus we need to shift MASK to the right before checking if it
7785 is a valid mask value. MODE is the mode of the operation. If true
7786 return the length of the mask, otherwise return -1. */
7789 mask_low_and_shift_len (enum machine_mode mode
, rtx mask
, rtx shift
)
7791 HOST_WIDE_INT shval
;
7793 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
7794 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
7797 /* Return true if -msplit-addresses is selected and should be honored.
7799 -msplit-addresses is a half-way house between explicit relocations
7800 and the traditional assembler macros. It can split absolute 32-bit
7801 symbolic constants into a high/lo_sum pair but uses macros for other
7804 Like explicit relocation support for REL targets, it relies
7805 on GNU extensions in the assembler and the linker.
7807 Although this code should work for -O0, it has traditionally
7808 been treated as an optimization. */
7811 mips_split_addresses_p (void)
7813 return (TARGET_SPLIT_ADDRESSES
7817 && !ABI_HAS_64BIT_SYMBOLS
);
7820 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7823 mips_init_relocs (void)
7825 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
7826 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
7827 memset (mips_use_pcrel_pool_p
, '\0', sizeof (mips_use_pcrel_pool_p
));
7828 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
7829 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
7831 if (TARGET_MIPS16_PCREL_LOADS
)
7832 mips_use_pcrel_pool_p
[SYMBOL_ABSOLUTE
] = true;
7835 if (ABI_HAS_64BIT_SYMBOLS
)
7837 if (TARGET_EXPLICIT_RELOCS
)
7839 mips_split_p
[SYMBOL_64_HIGH
] = true;
7840 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
7841 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
7843 mips_split_p
[SYMBOL_64_MID
] = true;
7844 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
7845 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
7847 mips_split_p
[SYMBOL_64_LOW
] = true;
7848 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
7849 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
7851 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7852 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7857 if (TARGET_EXPLICIT_RELOCS
7858 || mips_split_addresses_p ()
7861 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7862 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
7863 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7870 /* The high part is provided by a pseudo copy of $gp. */
7871 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
7872 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
7874 else if (TARGET_EXPLICIT_RELOCS
)
7875 /* Small data constants are kept whole until after reload,
7876 then lowered by mips_rewrite_small_data. */
7877 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
7879 if (TARGET_EXPLICIT_RELOCS
)
7881 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7884 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
7885 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
7889 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
7890 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
7893 /* Expose the use of $28 as soon as possible. */
7894 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7898 /* The HIGH and LO_SUM are matched by special .md patterns. */
7899 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7901 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
7902 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
7903 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
7905 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
7906 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
7907 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
7912 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
7914 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
7915 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
7917 /* Expose the use of $28 as soon as possible. */
7918 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7924 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
7925 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
7926 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
7929 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
7930 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
7932 if (TARGET_MIPS16_PCREL_LOADS
)
7934 mips_use_pcrel_pool_p
[SYMBOL_DTPREL
] = true;
7935 mips_use_pcrel_pool_p
[SYMBOL_TPREL
] = true;
7939 mips_split_p
[SYMBOL_DTPREL
] = true;
7940 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
7941 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
7943 mips_split_p
[SYMBOL_TPREL
] = true;
7944 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
7945 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
7948 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
7949 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
7952 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7953 in context CONTEXT. RELOCS is the array of relocations to use. */
7956 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
7957 const char **relocs
)
7959 enum mips_symbol_type symbol_type
;
7962 symbol_type
= mips_classify_symbolic_expression (op
, context
);
7963 gcc_assert (relocs
[symbol_type
]);
7965 fputs (relocs
[symbol_type
], file
);
7966 output_addr_const (file
, mips_strip_unspec_address (op
));
7967 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
7972 /* Start a new block with the given asm switch enabled. If we need
7973 to print a directive, emit PREFIX before it and SUFFIX after it. */
7976 mips_push_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7977 const char *prefix
, const char *suffix
)
7979 if (asm_switch
->nesting_level
== 0)
7980 fprintf (asm_out_file
, "%s.set\tno%s%s", prefix
, asm_switch
->name
, suffix
);
7981 asm_switch
->nesting_level
++;
7984 /* Likewise, but end a block. */
7987 mips_pop_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7988 const char *prefix
, const char *suffix
)
7990 gcc_assert (asm_switch
->nesting_level
);
7991 asm_switch
->nesting_level
--;
7992 if (asm_switch
->nesting_level
== 0)
7993 fprintf (asm_out_file
, "%s.set\t%s%s", prefix
, asm_switch
->name
, suffix
);
7996 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7997 that either print a complete line or print nothing. */
8000 mips_push_asm_switch (struct mips_asm_switch
*asm_switch
)
8002 mips_push_asm_switch_1 (asm_switch
, "\t", "\n");
8006 mips_pop_asm_switch (struct mips_asm_switch
*asm_switch
)
8008 mips_pop_asm_switch_1 (asm_switch
, "\t", "\n");
8011 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
8012 The punctuation characters are:
8014 '(' Start a nested ".set noreorder" block.
8015 ')' End a nested ".set noreorder" block.
8016 '[' Start a nested ".set noat" block.
8017 ']' End a nested ".set noat" block.
8018 '<' Start a nested ".set nomacro" block.
8019 '>' End a nested ".set nomacro" block.
8020 '*' Behave like %(%< if generating a delayed-branch sequence.
8021 '#' Print a nop if in a ".set noreorder" block.
8022 '/' Like '#', but do nothing within a delayed-branch sequence.
8023 '?' Print "l" if mips_branch_likely is true
8024 '~' Print a nop if mips_branch_likely is true
8025 '.' Print the name of the register with a hard-wired zero (zero or $0).
8026 '@' Print the name of the assembler temporary register (at or $1).
8027 '^' Print the name of the pic call-through register (t9 or $25).
8028 '+' Print the name of the gp register (usually gp or $28).
8029 '$' Print the name of the stack pointer register (sp or $29).
8030 ':' Print "c" to use the compact version if the delay slot is a nop.
8031 '!' Print "s" to use the short version if the delay slot contains a
8034 See also mips_init_print_operand_pucnt. */
8037 mips_print_operand_punctuation (FILE *file
, int ch
)
8042 mips_push_asm_switch_1 (&mips_noreorder
, "", "\n\t");
8046 mips_pop_asm_switch_1 (&mips_noreorder
, "\n\t", "");
8050 mips_push_asm_switch_1 (&mips_noat
, "", "\n\t");
8054 mips_pop_asm_switch_1 (&mips_noat
, "\n\t", "");
8058 mips_push_asm_switch_1 (&mips_nomacro
, "", "\n\t");
8062 mips_pop_asm_switch_1 (&mips_nomacro
, "\n\t", "");
8066 if (final_sequence
!= 0)
8068 mips_print_operand_punctuation (file
, '(');
8069 mips_print_operand_punctuation (file
, '<');
8074 if (mips_noreorder
.nesting_level
> 0)
8075 fputs ("\n\tnop", file
);
8079 /* Print an extra newline so that the delayed insn is separated
8080 from the following ones. This looks neater and is consistent
8081 with non-nop delayed sequences. */
8082 if (mips_noreorder
.nesting_level
> 0 && final_sequence
== 0)
8083 fputs ("\n\tnop\n", file
);
8087 if (mips_branch_likely
)
8092 if (mips_branch_likely
)
8093 fputs ("\n\tnop", file
);
8097 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
8101 fputs (reg_names
[AT_REGNUM
], file
);
8105 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
8109 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
8113 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
8117 /* When final_sequence is 0, the delay slot will be a nop. We can
8118 use the compact version for microMIPS. */
8119 if (final_sequence
== 0)
8124 /* If the delay slot instruction is short, then use the
8126 if (final_sequence
== 0
8127 || get_attr_length (XVECEXP (final_sequence
, 0, 1)) == 2)
8137 /* Initialize mips_print_operand_punct. */
8140 mips_init_print_operand_punct (void)
8144 for (p
= "()[]<>*#/?~.@^+$:!"; *p
; p
++)
8145 mips_print_operand_punct
[(unsigned char) *p
] = true;
8148 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8149 associated with condition CODE. Print the condition part of the
8153 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8167 /* Conveniently, the MIPS names for these conditions are the same
8168 as their RTL equivalents. */
8169 fputs (GET_RTX_NAME (code
), file
);
8173 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8178 /* Likewise floating-point branches. */
8181 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8186 fputs ("c1f", file
);
8190 fputs ("c1t", file
);
8194 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8199 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8202 mips_print_operand_punct_valid_p (unsigned char code
)
8204 return mips_print_operand_punct
[code
];
8207 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8209 'X' Print CONST_INT OP in hexadecimal format.
8210 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8211 'd' Print CONST_INT OP in decimal.
8212 'm' Print one less than CONST_INT OP in decimal.
8213 'h' Print the high-part relocation associated with OP, after stripping
8215 'R' Print the low-part relocation associated with OP.
8216 'C' Print the integer branch condition for comparison OP.
8217 'N' Print the inverse of the integer branch condition for comparison OP.
8218 'F' Print the FPU branch condition for comparison OP.
8219 'W' Print the inverse of the FPU branch condition for comparison OP.
8220 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8221 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8222 't' Like 'T', but with the EQ/NE cases reversed
8223 'Y' Print mips_fp_conditions[INTVAL (OP)]
8224 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8225 'q' Print a DSP accumulator register.
8226 'D' Print the second part of a double-word register or memory operand.
8227 'L' Print the low-order register in a double-word register operand.
8228 'M' Print high-order register in a double-word register operand.
8229 'z' Print $0 if OP is zero, otherwise print OP normally.
8230 'b' Print the address of a memory operand, without offset. */
8233 mips_print_operand (FILE *file
, rtx op
, int letter
)
8237 if (mips_print_operand_punct_valid_p (letter
))
8239 mips_print_operand_punctuation (file
, letter
);
8244 code
= GET_CODE (op
);
8249 if (CONST_INT_P (op
))
8250 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
8252 output_operand_lossage ("invalid use of '%%%c'", letter
);
8256 if (CONST_INT_P (op
))
8257 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
8259 output_operand_lossage ("invalid use of '%%%c'", letter
);
8263 if (CONST_INT_P (op
))
8264 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
8266 output_operand_lossage ("invalid use of '%%%c'", letter
);
8270 if (CONST_INT_P (op
))
8271 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
8273 output_operand_lossage ("invalid use of '%%%c'", letter
);
8279 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
8283 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
8287 mips_print_int_branch_condition (file
, code
, letter
);
8291 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
8295 mips_print_float_branch_condition (file
, code
, letter
);
8299 mips_print_float_branch_condition (file
, reverse_condition (code
),
8306 int truth
= (code
== NE
) == (letter
== 'T');
8307 fputc ("zfnt"[truth
* 2 + ST_REG_P (REGNO (XEXP (op
, 0)))], file
);
8312 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
8313 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
8315 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8322 mips_print_operand (file
, op
, 0);
8328 if (code
== REG
&& MD_REG_P (REGNO (op
)))
8329 fprintf (file
, "$ac0");
8330 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
8331 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
8333 output_operand_lossage ("invalid use of '%%%c'", letter
);
8341 unsigned int regno
= REGNO (op
);
8342 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
8343 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
8346 else if (letter
&& letter
!= 'z' && letter
!= 'M' && letter
!= 'L')
8347 output_operand_lossage ("invalid use of '%%%c'", letter
);
8348 /* We need to print $0 .. $31 for COP0 registers. */
8349 if (COP0_REG_P (regno
))
8350 fprintf (file
, "$%s", ®_names
[regno
][4]);
8352 fprintf (file
, "%s", reg_names
[regno
]);
8358 output_address (plus_constant (Pmode
, XEXP (op
, 0), 4));
8359 else if (letter
== 'b')
8361 gcc_assert (REG_P (XEXP (op
, 0)));
8362 mips_print_operand (file
, XEXP (op
, 0), 0);
8364 else if (letter
&& letter
!= 'z')
8365 output_operand_lossage ("invalid use of '%%%c'", letter
);
8367 output_address (XEXP (op
, 0));
8371 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
8372 fputs (reg_names
[GP_REG_FIRST
], file
);
8373 else if (letter
&& letter
!= 'z')
8374 output_operand_lossage ("invalid use of '%%%c'", letter
);
8375 else if (CONST_GP_P (op
))
8376 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
8378 output_addr_const (file
, mips_strip_unspec_address (op
));
8384 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8387 mips_print_operand_address (FILE *file
, rtx x
)
8389 struct mips_address_info addr
;
8391 if (mips_classify_address (&addr
, x
, word_mode
, true))
8395 mips_print_operand (file
, addr
.offset
, 0);
8396 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8399 case ADDRESS_LO_SUM
:
8400 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
8402 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8405 case ADDRESS_CONST_INT
:
8406 output_addr_const (file
, x
);
8407 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
8410 case ADDRESS_SYMBOLIC
:
8411 output_addr_const (file
, mips_strip_unspec_address (x
));
8417 /* Implement TARGET_ENCODE_SECTION_INFO. */
8420 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
8422 default_encode_section_info (decl
, rtl
, first
);
8424 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8426 rtx symbol
= XEXP (rtl
, 0);
8427 tree type
= TREE_TYPE (decl
);
8429 /* Encode whether the symbol is short or long. */
8430 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
8431 || mips_far_type_p (type
))
8432 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
8436 /* Implement TARGET_SELECT_RTX_SECTION. */
8439 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
8440 unsigned HOST_WIDE_INT align
)
8442 /* ??? Consider using mergeable small data sections. */
8443 if (mips_rtx_constant_in_small_data_p (mode
))
8444 return get_named_section (NULL
, ".sdata", 0);
8446 return default_elf_select_rtx_section (mode
, x
, align
);
8449 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8451 The complication here is that, with the combination TARGET_ABICALLS
8452 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8453 absolute addresses, and should therefore not be included in the
8454 read-only part of a DSO. Handle such cases by selecting a normal
8455 data section instead of a read-only one. The logic apes that in
8456 default_function_rodata_section. */
8459 mips_function_rodata_section (tree decl
)
8461 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
8462 return default_function_rodata_section (decl
);
8464 if (decl
&& DECL_SECTION_NAME (decl
))
8466 const char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
8467 if (DECL_ONE_ONLY (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
8469 char *rname
= ASTRDUP (name
);
8471 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
8473 else if (flag_function_sections
8474 && flag_data_sections
8475 && strncmp (name
, ".text.", 6) == 0)
8477 char *rname
= ASTRDUP (name
);
8478 memcpy (rname
+ 1, "data", 4);
8479 return get_section (rname
, SECTION_WRITE
, decl
);
8482 return data_section
;
8485 /* Implement TARGET_IN_SMALL_DATA_P. */
8488 mips_in_small_data_p (const_tree decl
)
8490 unsigned HOST_WIDE_INT size
;
8492 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
8495 /* We don't yet generate small-data references for -mabicalls
8496 or VxWorks RTP code. See the related -G handling in
8497 mips_option_override. */
8498 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
8501 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
8505 /* Reject anything that isn't in a known small-data section. */
8506 name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
8507 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
8510 /* If a symbol is defined externally, the assembler will use the
8511 usual -G rules when deciding how to implement macros. */
8512 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
8515 else if (TARGET_EMBEDDED_DATA
)
8517 /* Don't put constants into the small data section: we want them
8518 to be in ROM rather than RAM. */
8519 if (TREE_CODE (decl
) != VAR_DECL
)
8522 if (TREE_READONLY (decl
)
8523 && !TREE_SIDE_EFFECTS (decl
)
8524 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
8528 /* Enforce -mlocal-sdata. */
8529 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
8532 /* Enforce -mextern-sdata. */
8533 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
8535 if (DECL_EXTERNAL (decl
))
8537 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
8541 /* We have traditionally not treated zero-sized objects as small data,
8542 so this is now effectively part of the ABI. */
8543 size
= int_size_in_bytes (TREE_TYPE (decl
));
8544 return size
> 0 && size
<= mips_small_data_threshold
;
8547 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8548 anchors for small data: the GP register acts as an anchor in that
8549 case. We also don't want to use them for PC-relative accesses,
8550 where the PC acts as an anchor. */
8553 mips_use_anchors_for_symbol_p (const_rtx symbol
)
8555 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
8557 case SYMBOL_PC_RELATIVE
:
8558 case SYMBOL_GP_RELATIVE
:
8562 return default_use_anchors_for_symbol_p (symbol
);
8566 /* The MIPS debug format wants all automatic variables and arguments
8567 to be in terms of the virtual frame pointer (stack pointer before
8568 any adjustment in the function), while the MIPS 3.0 linker wants
8569 the frame pointer to be the stack pointer after the initial
8570 adjustment. So, we do the adjustment here. The arg pointer (which
8571 is eliminated) points to the virtual frame pointer, while the frame
8572 pointer (which may be eliminated) points to the stack pointer after
8573 the initial adjustments. */
8576 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
8578 rtx offset2
= const0_rtx
;
8579 rtx reg
= eliminate_constant_term (addr
, &offset2
);
8582 offset
= INTVAL (offset2
);
8584 if (reg
== stack_pointer_rtx
8585 || reg
== frame_pointer_rtx
8586 || reg
== hard_frame_pointer_rtx
)
8588 offset
-= cfun
->machine
->frame
.total_size
;
8589 if (reg
== hard_frame_pointer_rtx
)
8590 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8596 /* Implement ASM_OUTPUT_EXTERNAL. */
8599 mips_output_external (FILE *file
, tree decl
, const char *name
)
8601 default_elf_asm_output_external (file
, decl
, name
);
8603 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8604 set in order to avoid putting out names that are never really
8606 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
8608 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
8610 /* When using assembler macros, emit .extern directives for
8611 all small-data externs so that the assembler knows how
8614 In most cases it would be safe (though pointless) to emit
8615 .externs for other symbols too. One exception is when an
8616 object is within the -G limit but declared by the user to
8617 be in a section other than .sbss or .sdata. */
8618 fputs ("\t.extern\t", file
);
8619 assemble_name (file
, name
);
8620 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
8621 int_size_in_bytes (TREE_TYPE (decl
)));
8626 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8629 mips_output_filename (FILE *stream
, const char *name
)
8631 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8633 if (write_symbols
== DWARF2_DEBUG
)
8635 else if (mips_output_filename_first_time
)
8637 mips_output_filename_first_time
= 0;
8638 num_source_filenames
+= 1;
8639 current_function_file
= name
;
8640 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8641 output_quoted_string (stream
, name
);
8642 putc ('\n', stream
);
8644 /* If we are emitting stabs, let dbxout.c handle this (except for
8645 the mips_output_filename_first_time case). */
8646 else if (write_symbols
== DBX_DEBUG
)
8648 else if (name
!= current_function_file
8649 && strcmp (name
, current_function_file
) != 0)
8651 num_source_filenames
+= 1;
8652 current_function_file
= name
;
8653 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8654 output_quoted_string (stream
, name
);
8655 putc ('\n', stream
);
8659 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8661 static void ATTRIBUTE_UNUSED
8662 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8667 fputs ("\t.dtprelword\t", file
);
8671 fputs ("\t.dtpreldword\t", file
);
8677 output_addr_const (file
, x
);
8678 fputs ("+0x8000", file
);
8681 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8684 mips_dwarf_register_span (rtx reg
)
8687 enum machine_mode mode
;
8689 /* By default, GCC maps increasing register numbers to increasing
8690 memory locations, but paired FPRs are always little-endian,
8691 regardless of the prevailing endianness. */
8692 mode
= GET_MODE (reg
);
8693 if (FP_REG_P (REGNO (reg
))
8694 && TARGET_BIG_ENDIAN
8695 && MAX_FPRS_PER_FMT
> 1
8696 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
8698 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
8699 high
= mips_subword (reg
, true);
8700 low
= mips_subword (reg
, false);
8701 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
8707 /* DSP ALU can bypass data with no delays for the following pairs. */
8708 enum insn_code dspalu_bypass_table
[][2] =
8710 {CODE_FOR_mips_addsc
, CODE_FOR_mips_addwc
},
8711 {CODE_FOR_mips_cmpu_eq_qb
, CODE_FOR_mips_pick_qb
},
8712 {CODE_FOR_mips_cmpu_lt_qb
, CODE_FOR_mips_pick_qb
},
8713 {CODE_FOR_mips_cmpu_le_qb
, CODE_FOR_mips_pick_qb
},
8714 {CODE_FOR_mips_cmp_eq_ph
, CODE_FOR_mips_pick_ph
},
8715 {CODE_FOR_mips_cmp_lt_ph
, CODE_FOR_mips_pick_ph
},
8716 {CODE_FOR_mips_cmp_le_ph
, CODE_FOR_mips_pick_ph
},
8717 {CODE_FOR_mips_wrdsp
, CODE_FOR_mips_insv
}
8721 mips_dspalu_bypass_p (rtx out_insn
, rtx in_insn
)
8724 int num_bypass
= ARRAY_SIZE (dspalu_bypass_table
);
8725 enum insn_code out_icode
= (enum insn_code
) INSN_CODE (out_insn
);
8726 enum insn_code in_icode
= (enum insn_code
) INSN_CODE (in_insn
);
8728 for (i
= 0; i
< num_bypass
; i
++)
8730 if (out_icode
== dspalu_bypass_table
[i
][0]
8731 && in_icode
== dspalu_bypass_table
[i
][1])
8737 /* Implement ASM_OUTPUT_ASCII. */
8740 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
8746 fprintf (stream
, "\t.ascii\t\"");
8747 for (i
= 0; i
< len
; i
++)
8751 c
= (unsigned char) string
[i
];
8754 if (c
== '\\' || c
== '\"')
8756 putc ('\\', stream
);
8764 fprintf (stream
, "\\%03o", c
);
8768 if (cur_pos
> 72 && i
+1 < len
)
8771 fprintf (stream
, "\"\n\t.ascii\t\"");
8774 fprintf (stream
, "\"\n");
8777 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8778 Update *ADDR with the operand that should be printed. */
8781 mips_output_tls_reloc_directive (rtx
*addr
)
8783 enum mips_symbol_type type
;
8785 type
= mips_classify_symbolic_expression (*addr
, SYMBOL_CONTEXT_LEA
);
8786 *addr
= mips_strip_unspec_address (*addr
);
8790 return Pmode
== SImode
? ".dtprelword\t%0" : ".dtpreldword\t%0";
8793 return Pmode
== SImode
? ".tprelword\t%0" : ".tpreldword\t%0";
8800 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8801 macros, mark the symbol as written so that mips_asm_output_external
8802 won't emit an .extern for it. STREAM is the output file, NAME is the
8803 name of the symbol, INIT_STRING is the string that should be written
8804 before the symbol and FINAL_STRING is the string that should be
8805 written after it. FINAL_STRING is a printf format that consumes the
8806 remaining arguments. */
8809 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
8810 const char *final_string
, ...)
8814 fputs (init_string
, stream
);
8815 assemble_name (stream
, name
);
8816 va_start (ap
, final_string
);
8817 vfprintf (stream
, final_string
, ap
);
8820 if (!TARGET_EXPLICIT_RELOCS
)
8822 tree name_tree
= get_identifier (name
);
8823 TREE_ASM_WRITTEN (name_tree
) = 1;
8827 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8828 NAME is the name of the object and ALIGN is the required alignment
8829 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8830 alignment argument. */
8833 mips_declare_common_object (FILE *stream
, const char *name
,
8834 const char *init_string
,
8835 unsigned HOST_WIDE_INT size
,
8836 unsigned int align
, bool takes_alignment_p
)
8838 if (!takes_alignment_p
)
8840 size
+= (align
/ BITS_PER_UNIT
) - 1;
8841 size
-= size
% (align
/ BITS_PER_UNIT
);
8842 mips_declare_object (stream
, name
, init_string
,
8843 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
8846 mips_declare_object (stream
, name
, init_string
,
8847 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
8848 size
, align
/ BITS_PER_UNIT
);
8851 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8852 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8855 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
8856 unsigned HOST_WIDE_INT size
,
8859 /* If the target wants uninitialized const declarations in
8860 .rdata then don't put them in .comm. */
8861 if (TARGET_EMBEDDED_DATA
8862 && TARGET_UNINIT_CONST_IN_RODATA
8863 && TREE_CODE (decl
) == VAR_DECL
8864 && TREE_READONLY (decl
)
8865 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
8867 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
8868 targetm
.asm_out
.globalize_label (stream
, name
);
8870 switch_to_section (readonly_data_section
);
8871 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
8872 mips_declare_object (stream
, name
, "",
8873 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
8877 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
8881 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8882 extern int size_directive_output
;
8884 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8885 definitions except that it uses mips_declare_object to emit the label. */
8888 mips_declare_object_name (FILE *stream
, const char *name
,
8889 tree decl ATTRIBUTE_UNUSED
)
8891 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8892 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
8895 size_directive_output
= 0;
8896 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
8900 size_directive_output
= 1;
8901 size
= int_size_in_bytes (TREE_TYPE (decl
));
8902 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8905 mips_declare_object (stream
, name
, "", ":\n");
8908 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8911 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
8915 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
8916 if (!flag_inhibit_size_directive
8917 && DECL_SIZE (decl
) != 0
8920 && DECL_INITIAL (decl
) == error_mark_node
8921 && !size_directive_output
)
8925 size_directive_output
= 1;
8926 size
= int_size_in_bytes (TREE_TYPE (decl
));
8927 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8932 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8933 with the current ABI. */
8936 mips_mdebug_abi_name (void)
8949 return TARGET_64BIT
? "eabi64" : "eabi32";
8955 /* Implement TARGET_ASM_FILE_START. */
8958 mips_file_start (void)
8960 default_file_start ();
8962 /* Generate a special section to describe the ABI switches used to
8963 produce the resultant binary. */
8965 /* Record the ABI itself. Modern versions of binutils encode
8966 this information in the ELF header flags, but GDB needs the
8967 information in order to correctly debug binaries produced by
8968 older binutils. See the function mips_gdbarch_init in
8970 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
8971 mips_mdebug_abi_name ());
8973 /* There is no ELF header flag to distinguish long32 forms of the
8974 EABI from long64 forms. Emit a special section to help tools
8975 such as GDB. Do the same for o64, which is sometimes used with
8977 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
8978 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
8979 "\t.previous\n", TARGET_LONG64
? 64 : 32);
8981 /* Record the NaN encoding. */
8982 if (HAVE_AS_NAN
|| mips_nan
!= MIPS_IEEE_754_DEFAULT
)
8983 fprintf (asm_out_file
, "\t.nan\t%s\n",
8984 mips_nan
== MIPS_IEEE_754_2008
? "2008" : "legacy");
8986 #ifdef HAVE_AS_GNU_ATTRIBUTE
8990 /* No floating-point operations, -mno-float. */
8991 if (TARGET_NO_FLOAT
)
8993 /* Soft-float code, -msoft-float. */
8994 else if (!TARGET_HARD_FLOAT_ABI
)
8996 /* Single-float code, -msingle-float. */
8997 else if (!TARGET_DOUBLE_FLOAT
)
8999 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
9000 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
9002 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
9006 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", attr
);
9010 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
9011 if (TARGET_ABICALLS
)
9013 fprintf (asm_out_file
, "\t.abicalls\n");
9014 if (TARGET_ABICALLS_PIC0
)
9015 fprintf (asm_out_file
, "\t.option\tpic0\n");
9018 if (flag_verbose_asm
)
9019 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
9021 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
9024 /* Implement TARGET_ASM_CODE_END. */
9027 mips_code_end (void)
9029 mips_finish_stub (&mips16_rdhwr_stub
);
9030 mips_finish_stub (&mips16_get_fcsr_stub
);
9031 mips_finish_stub (&mips16_set_fcsr_stub
);
9034 /* Make the last instruction frame-related and note that it performs
9035 the operation described by FRAME_PATTERN. */
9038 mips_set_frame_expr (rtx frame_pattern
)
9042 insn
= get_last_insn ();
9043 RTX_FRAME_RELATED_P (insn
) = 1;
9044 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
9049 /* Return a frame-related rtx that stores REG at MEM.
9050 REG must be a single register. */
9053 mips_frame_set (rtx mem
, rtx reg
)
9057 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
9058 RTX_FRAME_RELATED_P (set
) = 1;
9063 /* Record that the epilogue has restored call-saved register REG. */
9066 mips_add_cfa_restore (rtx reg
)
9068 mips_epilogue
.cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
9069 mips_epilogue
.cfa_restores
);
9072 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
9073 mips16e_s2_s8_regs[X], it must also save the registers in indexes
9074 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
9075 static const unsigned char mips16e_s2_s8_regs
[] = {
9076 30, 23, 22, 21, 20, 19, 18
9078 static const unsigned char mips16e_a0_a3_regs
[] = {
9082 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
9083 ordered from the uppermost in memory to the lowest in memory. */
9084 static const unsigned char mips16e_save_restore_regs
[] = {
9085 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
9088 /* Return the index of the lowest X in the range [0, SIZE) for which
9089 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
9092 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
9097 for (i
= 0; i
< size
; i
++)
9098 if (BITSET_P (mask
, regs
[i
]))
9104 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
9105 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
9106 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
9107 is true for all indexes (X, SIZE). */
9110 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
9111 unsigned int size
, unsigned int *num_regs_ptr
)
9115 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
9116 for (i
++; i
< size
; i
++)
9117 if (!BITSET_P (*mask_ptr
, regs
[i
]))
9120 *mask_ptr
|= 1 << regs
[i
];
9124 /* Return a simplified form of X using the register values in REG_VALUES.
9125 REG_VALUES[R] is the last value assigned to hard register R, or null
9126 if R has not been modified.
9128 This function is rather limited, but is good enough for our purposes. */
9131 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
9133 x
= avoid_constant_pool_reference (x
);
9137 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
9138 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
9139 x0
, GET_MODE (XEXP (x
, 0)));
9142 if (ARITHMETIC_P (x
))
9144 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
9145 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
9146 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
9150 && reg_values
[REGNO (x
)]
9151 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
9152 return reg_values
[REGNO (x
)];
9157 /* Return true if (set DEST SRC) stores an argument register into its
9158 caller-allocated save slot, storing the number of that argument
9159 register in *REGNO_PTR if so. REG_VALUES is as for
9160 mips16e_collect_propagate_value. */
9163 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
9164 unsigned int *regno_ptr
)
9166 unsigned int argno
, regno
;
9167 HOST_WIDE_INT offset
, required_offset
;
9170 /* Check that this is a word-mode store. */
9171 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
9174 /* Check that the register being saved is an unmodified argument
9176 regno
= REGNO (src
);
9177 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
9179 argno
= regno
- GP_ARG_FIRST
;
9181 /* Check whether the address is an appropriate stack-pointer or
9182 frame-pointer access. */
9183 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
9184 mips_split_plus (addr
, &base
, &offset
);
9185 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
9186 if (base
== hard_frame_pointer_rtx
)
9187 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
9188 else if (base
!= stack_pointer_rtx
)
9190 if (offset
!= required_offset
)
9197 /* A subroutine of mips_expand_prologue, called only when generating
9198 MIPS16e SAVE instructions. Search the start of the function for any
9199 instructions that save argument registers into their caller-allocated
9200 save slots. Delete such instructions and return a value N such that
9201 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
9202 instructions redundant. */
9205 mips16e_collect_argument_saves (void)
9207 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
9208 rtx insn
, next
, set
, dest
, src
;
9209 unsigned int nargs
, regno
;
9211 push_topmost_sequence ();
9213 memset (reg_values
, 0, sizeof (reg_values
));
9214 for (insn
= get_insns (); insn
; insn
= next
)
9216 next
= NEXT_INSN (insn
);
9217 if (NOTE_P (insn
) || DEBUG_INSN_P (insn
))
9223 set
= PATTERN (insn
);
9224 if (GET_CODE (set
) != SET
)
9227 dest
= SET_DEST (set
);
9228 src
= SET_SRC (set
);
9229 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
9231 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
9234 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
9237 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
9238 reg_values
[REGNO (dest
)]
9239 = mips16e_collect_propagate_value (src
, reg_values
);
9243 pop_topmost_sequence ();
9248 /* Return a move between register REGNO and memory location SP + OFFSET.
9249 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9250 Make the move a load if RESTORE_P, otherwise make it a store. */
9253 mips16e_save_restore_reg (bool restore_p
, bool reg_parm_p
,
9254 HOST_WIDE_INT offset
, unsigned int regno
)
9258 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, stack_pointer_rtx
,
9260 reg
= gen_rtx_REG (SImode
, regno
);
9263 mips_add_cfa_restore (reg
);
9264 return gen_rtx_SET (VOIDmode
, reg
, mem
);
9267 return gen_rtx_SET (VOIDmode
, mem
, reg
);
9268 return mips_frame_set (mem
, reg
);
9271 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9272 The instruction must:
9274 - Allocate or deallocate SIZE bytes in total; SIZE is known
9277 - Save or restore as many registers in *MASK_PTR as possible.
9278 The instruction saves the first registers at the top of the
9279 allocated area, with the other registers below it.
9281 - Save NARGS argument registers above the allocated area.
9283 (NARGS is always zero if RESTORE_P.)
9285 The SAVE and RESTORE instructions cannot save and restore all general
9286 registers, so there may be some registers left over for the caller to
9287 handle. Destructively modify *MASK_PTR so that it contains the registers
9288 that still need to be saved or restored. The caller can save these
9289 registers in the memory immediately below *OFFSET_PTR, which is a
9290 byte offset from the bottom of the allocated stack area. */
9293 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
9294 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
9298 HOST_WIDE_INT offset
, top_offset
;
9299 unsigned int i
, regno
;
9302 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
9304 /* Calculate the number of elements in the PARALLEL. We need one element
9305 for the stack adjustment, one for each argument register save, and one
9306 for each additional register move. */
9308 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9309 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
9312 /* Create the final PARALLEL. */
9313 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
9316 /* Add the stack pointer adjustment. */
9317 set
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
9318 plus_constant (Pmode
, stack_pointer_rtx
,
9319 restore_p
? size
: -size
));
9320 RTX_FRAME_RELATED_P (set
) = 1;
9321 XVECEXP (pattern
, 0, n
++) = set
;
9323 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9324 top_offset
= restore_p
? size
: 0;
9326 /* Save the arguments. */
9327 for (i
= 0; i
< nargs
; i
++)
9329 offset
= top_offset
+ i
* UNITS_PER_WORD
;
9330 set
= mips16e_save_restore_reg (restore_p
, true, offset
,
9332 XVECEXP (pattern
, 0, n
++) = set
;
9335 /* Then fill in the other register moves. */
9336 offset
= top_offset
;
9337 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9339 regno
= mips16e_save_restore_regs
[i
];
9340 if (BITSET_P (*mask_ptr
, regno
))
9342 offset
-= UNITS_PER_WORD
;
9343 set
= mips16e_save_restore_reg (restore_p
, false, offset
, regno
);
9344 XVECEXP (pattern
, 0, n
++) = set
;
9345 *mask_ptr
&= ~(1 << regno
);
9349 /* Tell the caller what offset it should use for the remaining registers. */
9350 *offset_ptr
= size
+ (offset
- top_offset
);
9352 gcc_assert (n
== XVECLEN (pattern
, 0));
9357 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9358 pointer. Return true if PATTERN matches the kind of instruction
9359 generated by mips16e_build_save_restore. If INFO is nonnull,
9360 initialize it when returning true. */
9363 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
9364 struct mips16e_save_restore_info
*info
)
9366 unsigned int i
, nargs
, mask
, extra
;
9367 HOST_WIDE_INT top_offset
, save_offset
, offset
;
9368 rtx set
, reg
, mem
, base
;
9371 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
9374 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9375 top_offset
= adjust
> 0 ? adjust
: 0;
9377 /* Interpret all other members of the PARALLEL. */
9378 save_offset
= top_offset
- UNITS_PER_WORD
;
9382 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
9384 /* Check that we have a SET. */
9385 set
= XVECEXP (pattern
, 0, n
);
9386 if (GET_CODE (set
) != SET
)
9389 /* Check that the SET is a load (if restoring) or a store
9391 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
9395 /* Check that the address is the sum of the stack pointer and a
9396 possibly-zero constant offset. */
9397 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
9398 if (base
!= stack_pointer_rtx
)
9401 /* Check that SET's other operand is a register. */
9402 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
9406 /* Check for argument saves. */
9407 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
9408 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
9410 else if (offset
== save_offset
)
9412 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
9413 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
9416 mask
|= 1 << REGNO (reg
);
9417 save_offset
-= UNITS_PER_WORD
;
9423 /* Check that the restrictions on register ranges are met. */
9425 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
9426 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
9427 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
9428 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
9432 /* Make sure that the topmost argument register is not saved twice.
9433 The checks above ensure that the same is then true for the other
9434 argument registers. */
9435 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
9438 /* Pass back information, if requested. */
9441 info
->nargs
= nargs
;
9443 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
9449 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9450 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9451 the null terminator. */
9454 mips16e_add_register_range (char *s
, unsigned int min_reg
,
9455 unsigned int max_reg
)
9457 if (min_reg
!= max_reg
)
9458 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
9460 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
9464 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9465 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9468 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
9470 static char buffer
[300];
9472 struct mips16e_save_restore_info info
;
9473 unsigned int i
, end
;
9476 /* Parse the pattern. */
9477 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
9480 /* Add the mnemonic. */
9481 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
9484 /* Save the arguments. */
9486 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
9487 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
9488 else if (info
.nargs
== 1)
9489 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
9491 /* Emit the amount of stack space to allocate or deallocate. */
9492 s
+= sprintf (s
, "%d", (int) info
.size
);
9494 /* Save or restore $16. */
9495 if (BITSET_P (info
.mask
, 16))
9496 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
9498 /* Save or restore $17. */
9499 if (BITSET_P (info
.mask
, 17))
9500 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
9502 /* Save or restore registers in the range $s2...$s8, which
9503 mips16e_s2_s8_regs lists in decreasing order. Note that this
9504 is a software register range; the hardware registers are not
9505 numbered consecutively. */
9506 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
9507 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
9509 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
9510 mips16e_s2_s8_regs
[i
]);
9512 /* Save or restore registers in the range $a0...$a3. */
9513 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
9514 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
9516 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
9517 mips16e_a0_a3_regs
[end
- 1]);
9519 /* Save or restore $31. */
9520 if (BITSET_P (info
.mask
, RETURN_ADDR_REGNUM
))
9521 s
+= sprintf (s
, ",%s", reg_names
[RETURN_ADDR_REGNUM
]);
9526 /* Return true if the current function returns its value in a floating-point
9527 register in MIPS16 mode. */
9530 mips16_cfun_returns_in_fpr_p (void)
9532 tree return_type
= DECL_RESULT (current_function_decl
);
9533 return (TARGET_MIPS16
9534 && TARGET_HARD_FLOAT_ABI
9535 && !aggregate_value_p (return_type
, current_function_decl
)
9536 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
9539 /* Return true if predicate PRED is true for at least one instruction.
9540 Cache the result in *CACHE, and assume that the result is true
9541 if *CACHE is already true. */
9544 mips_find_gp_ref (bool *cache
, bool (*pred
) (rtx
))
9550 push_topmost_sequence ();
9551 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9552 if (USEFUL_INSN_P (insn
) && pred (insn
))
9557 pop_topmost_sequence ();
9562 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9563 See mips_cfun_has_inflexible_gp_ref_p for details. */
9566 mips_insn_has_inflexible_gp_ref_p (rtx insn
)
9568 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9569 indicate that the target could be a traditional MIPS
9570 lazily-binding stub. */
9571 return find_reg_fusage (insn
, USE
, pic_offset_table_rtx
);
9574 /* Return true if the current function refers to the global pointer
9575 in a way that forces $28 to be valid. This means that we can't
9576 change the choice of global pointer, even for NewABI code.
9578 One example of this (and one which needs several checks) is that
9579 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9580 (This restriction does not apply to PLTs.) */
9583 mips_cfun_has_inflexible_gp_ref_p (void)
9585 /* If the function has a nonlocal goto, $28 must hold the correct
9586 global pointer for the target function. That is, the target
9587 of the goto implicitly uses $28. */
9588 if (crtl
->has_nonlocal_goto
)
9591 if (TARGET_ABICALLS_PIC2
)
9593 /* Symbolic accesses implicitly use the global pointer unless
9594 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9595 might go to traditional MIPS lazy-binding stubs. */
9596 if (!TARGET_EXPLICIT_RELOCS
)
9599 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9600 can be lazily-bound. */
9604 /* MIPS16 functions that return in FPRs need to call an
9605 external libgcc routine. This call is only made explict
9606 during mips_expand_epilogue, and it too might be lazily bound. */
9607 if (mips16_cfun_returns_in_fpr_p ())
9611 return mips_find_gp_ref (&cfun
->machine
->has_inflexible_gp_insn_p
,
9612 mips_insn_has_inflexible_gp_ref_p
);
9615 /* Return true if INSN refers to the global pointer in a "flexible" way.
9616 See mips_cfun_has_flexible_gp_ref_p for details. */
9619 mips_insn_has_flexible_gp_ref_p (rtx insn
)
9621 return (get_attr_got (insn
) != GOT_UNSET
9622 || mips_small_data_pattern_p (PATTERN (insn
))
9623 || reg_overlap_mentioned_p (pic_offset_table_rtx
, PATTERN (insn
)));
9626 /* Return true if the current function references the global pointer,
9627 but if those references do not inherently require the global pointer
9628 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9631 mips_cfun_has_flexible_gp_ref_p (void)
9633 /* Reload can sometimes introduce constant pool references
9634 into a function that otherwise didn't need them. For example,
9635 suppose we have an instruction like:
9637 (set (reg:DF R1) (float:DF (reg:SI R2)))
9639 If R2 turns out to be a constant such as 1, the instruction may
9640 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9641 the option of using this constant if R2 doesn't get allocated
9644 In cases like these, reload will have added the constant to the
9645 pool but no instruction will yet refer to it. */
9646 if (TARGET_ABICALLS_PIC2
&& !reload_completed
&& crtl
->uses_const_pool
)
9649 return mips_find_gp_ref (&cfun
->machine
->has_flexible_gp_insn_p
,
9650 mips_insn_has_flexible_gp_ref_p
);
9653 /* Return the register that should be used as the global pointer
9654 within this function. Return INVALID_REGNUM if the function
9655 doesn't need a global pointer. */
9658 mips_global_pointer (void)
9662 /* $gp is always available unless we're using a GOT. */
9663 if (!TARGET_USE_GOT
)
9664 return GLOBAL_POINTER_REGNUM
;
9666 /* If there are inflexible references to $gp, we must use the
9667 standard register. */
9668 if (mips_cfun_has_inflexible_gp_ref_p ())
9669 return GLOBAL_POINTER_REGNUM
;
9671 /* If there are no current references to $gp, then the only uses
9672 we can introduce later are those involved in long branches. */
9673 if (TARGET_ABSOLUTE_JUMPS
&& !mips_cfun_has_flexible_gp_ref_p ())
9674 return INVALID_REGNUM
;
9676 /* If the global pointer is call-saved, try to use a call-clobbered
9678 if (TARGET_CALL_SAVED_GP
&& crtl
->is_leaf
)
9679 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9680 if (!df_regs_ever_live_p (regno
)
9681 && call_really_used_regs
[regno
]
9682 && !fixed_regs
[regno
]
9683 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
9686 return GLOBAL_POINTER_REGNUM
;
9689 /* Return true if the current function's prologue must load the global
9690 pointer value into pic_offset_table_rtx and store the same value in
9691 the function's cprestore slot (if any).
9693 One problem we have to deal with is that, when emitting GOT-based
9694 position independent code, long-branch sequences will need to load
9695 the address of the branch target from the GOT. We don't know until
9696 the very end of compilation whether (and where) the function needs
9697 long branches, so we must ensure that _any_ branch can access the
9698 global pointer in some form. However, we do not want to pessimize
9699 the usual case in which all branches are short.
9701 We handle this as follows:
9703 (1) During reload, we set cfun->machine->global_pointer to
9704 INVALID_REGNUM if we _know_ that the current function
9705 doesn't need a global pointer. This is only valid if
9706 long branches don't need the GOT.
9708 Otherwise, we assume that we might need a global pointer
9709 and pick an appropriate register.
9711 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9712 we ensure that the global pointer is available at every
9713 block boundary bar entry and exit. We do this in one of two ways:
9715 - If the function has a cprestore slot, we ensure that this
9716 slot is valid at every branch. However, as explained in
9717 point (6) below, there is no guarantee that pic_offset_table_rtx
9718 itself is valid if new uses of the global pointer are introduced
9719 after the first post-epilogue split.
9721 We guarantee that the cprestore slot is valid by loading it
9722 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9723 this register live at every block boundary bar function entry
9724 and exit. It is then invalid to move the load (and thus the
9725 preceding store) across a block boundary.
9727 - If the function has no cprestore slot, we guarantee that
9728 pic_offset_table_rtx itself is valid at every branch.
9730 See mips_eh_uses for the handling of the register liveness.
9732 (3) During prologue and epilogue generation, we emit "ghost"
9733 placeholder instructions to manipulate the global pointer.
9735 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9736 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9737 that the function needs a global pointer. (There is no need to set
9738 them earlier than this, and doing it as late as possible leads to
9739 fewer false positives.)
9741 (5) If cfun->machine->must_initialize_gp_p is true during a
9742 split_insns pass, we split the ghost instructions into real
9743 instructions. These split instructions can then be optimized in
9744 the usual way. Otherwise, we keep the ghost instructions intact,
9745 and optimize for the case where they aren't needed. We still
9746 have the option of splitting them later, if we need to introduce
9747 new uses of the global pointer.
9749 For example, the scheduler ignores a ghost instruction that
9750 stores $28 to the stack, but it handles the split form of
9751 the ghost instruction as an ordinary store.
9753 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9754 is true during the first post-epilogue split_insns pass, we split
9755 calls and restore_gp patterns into instructions that explicitly
9756 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9757 we split these patterns into instructions that _don't_ load from
9760 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9761 time of the split, then any instructions that exist at that time
9762 can make free use of pic_offset_table_rtx. However, if we want
9763 to introduce new uses of the global pointer after the split,
9764 we must explicitly load the value from the cprestore slot, since
9765 pic_offset_table_rtx itself might not be valid at a given point
9768 The idea is that we want to be able to delete redundant
9769 loads from the cprestore slot in the usual case where no
9770 long branches are needed.
9772 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9773 of md_reorg, we decide whether the global pointer is needed for
9774 long branches. If so, we set cfun->machine->must_initialize_gp_p
9775 to true and split the ghost instructions into real instructions
9778 Note that the ghost instructions must have a zero length for three reasons:
9780 - Giving the length of the underlying $gp sequence might cause
9781 us to use long branches in cases where they aren't really needed.
9783 - They would perturb things like alignment calculations.
9785 - More importantly, the hazard detection in md_reorg relies on
9786 empty instructions having a zero length.
9788 If we find a long branch and split the ghost instructions at the
9789 end of md_reorg, the split could introduce more long branches.
9790 That isn't a problem though, because we still do the split before
9791 the final shorten_branches pass.
9793 This is extremely ugly, but it seems like the best compromise between
9794 correctness and efficiency. */
9797 mips_must_initialize_gp_p (void)
9799 return cfun
->machine
->must_initialize_gp_p
;
9802 /* Return true if REGNO is a register that is ordinarily call-clobbered
9803 but must nevertheless be preserved by an interrupt handler. */
9806 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
9808 if (MD_REG_P (regno
))
9811 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
9814 if (GP_REG_P (regno
) && !cfun
->machine
->use_shadow_register_set_p
)
9816 /* $0 is hard-wired. */
9817 if (regno
== GP_REG_FIRST
)
9820 /* The interrupt handler can treat kernel registers as
9821 scratch registers. */
9822 if (KERNEL_REG_P (regno
))
9825 /* The function will return the stack pointer to its original value
9827 if (regno
== STACK_POINTER_REGNUM
)
9830 /* Otherwise, return true for registers that aren't ordinarily
9832 return call_really_used_regs
[regno
];
9838 /* Return true if the current function should treat register REGNO
9842 mips_cfun_call_saved_reg_p (unsigned int regno
)
9844 /* If the user makes an ordinarily-call-saved register global,
9845 that register is no longer call-saved. */
9846 if (global_regs
[regno
])
9849 /* Interrupt handlers need to save extra registers. */
9850 if (cfun
->machine
->interrupt_handler_p
9851 && mips_interrupt_extra_call_saved_reg_p (regno
))
9854 /* call_insns preserve $28 unless they explicitly say otherwise,
9855 so call_really_used_regs[] treats $28 as call-saved. However,
9856 we want the ABI property rather than the default call_insn
9858 return (regno
== GLOBAL_POINTER_REGNUM
9859 ? TARGET_CALL_SAVED_GP
9860 : !call_really_used_regs
[regno
]);
9863 /* Return true if the function body might clobber register REGNO.
9864 We know that REGNO is call-saved. */
9867 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
9869 /* Some functions should be treated as clobbering all call-saved
9871 if (crtl
->saves_all_registers
)
9874 /* DF handles cases where a register is explicitly referenced in
9875 the rtl. Incoming values are passed in call-clobbered registers,
9876 so we can assume that any live call-saved register is set within
9878 if (df_regs_ever_live_p (regno
))
9881 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9882 These clobbers are not explicit in the rtl. */
9883 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
9886 /* If we're using a call-saved global pointer, the function's
9887 prologue will need to set it up. */
9888 if (cfun
->machine
->global_pointer
== regno
)
9891 /* The function's prologue will need to set the frame pointer if
9892 frame_pointer_needed. */
9893 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
9896 /* If a MIPS16 function returns a value in FPRs, its epilogue
9897 will need to call an external libgcc routine. This yet-to-be
9898 generated call_insn will clobber $31. */
9899 if (regno
== RETURN_ADDR_REGNUM
&& mips16_cfun_returns_in_fpr_p ())
9902 /* If REGNO is ordinarily call-clobbered, we must assume that any
9903 called function could modify it. */
9904 if (cfun
->machine
->interrupt_handler_p
9906 && mips_interrupt_extra_call_saved_reg_p (regno
))
9912 /* Return true if the current function must save register REGNO. */
9915 mips_save_reg_p (unsigned int regno
)
9917 if (mips_cfun_call_saved_reg_p (regno
))
9919 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
9922 /* Save both registers in an FPR pair if either one is used. This is
9923 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9924 register to be used without the even register. */
9925 if (FP_REG_P (regno
)
9926 && MAX_FPRS_PER_FMT
== 2
9927 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
9931 /* We need to save the incoming return address if __builtin_eh_return
9932 is being used to set a different return address. */
9933 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
9939 /* Populate the current function's mips_frame_info structure.
9941 MIPS stack frames look like:
9943 +-------------------------------+
9945 | incoming stack arguments |
9947 +-------------------------------+
9949 | caller-allocated save area |
9950 A | for register arguments |
9952 +-------------------------------+ <-- incoming stack pointer
9954 | callee-allocated save area |
9955 B | for arguments that are |
9956 | split between registers and |
9959 +-------------------------------+ <-- arg_pointer_rtx
9961 C | callee-allocated save area |
9962 | for register varargs |
9964 +-------------------------------+ <-- frame_pointer_rtx
9965 | | + cop0_sp_offset
9966 | COP0 reg save area | + UNITS_PER_WORD
9968 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9969 | | + UNITS_PER_WORD
9970 | accumulator save area |
9972 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9973 | | + UNITS_PER_HWFPVALUE
9976 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9977 | | + UNITS_PER_WORD
9980 +-------------------------------+ <-- frame_pointer_rtx with
9981 | | \ -fstack-protector
9982 | local variables | | var_size
9984 +-------------------------------+
9986 | $gp save area | | cprestore_size
9988 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9990 | outgoing stack arguments | |
9992 +-------------------------------+ | args_size
9994 | caller-allocated save area | |
9995 | for register arguments | |
9997 +-------------------------------+ <-- stack_pointer_rtx
9998 frame_pointer_rtx without
10000 hard_frame_pointer_rtx for
10003 At least two of A, B and C will be empty.
10005 Dynamic stack allocations such as alloca insert data at point P.
10006 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
10007 hard_frame_pointer_rtx unchanged. */
10010 mips_compute_frame_info (void)
10012 struct mips_frame_info
*frame
;
10013 HOST_WIDE_INT offset
, size
;
10014 unsigned int regno
, i
;
10016 /* Set this function's interrupt properties. */
10017 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
10020 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
10021 else if (TARGET_HARD_FLOAT
)
10022 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
10023 else if (TARGET_MIPS16
)
10024 error ("interrupt handlers cannot be MIPS16 functions");
10027 cfun
->machine
->interrupt_handler_p
= true;
10028 cfun
->machine
->use_shadow_register_set_p
=
10029 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl
));
10030 cfun
->machine
->keep_interrupts_masked_p
=
10031 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
10032 cfun
->machine
->use_debug_exception_return_p
=
10033 mips_use_debug_exception_return_p (TREE_TYPE
10034 (current_function_decl
));
10038 frame
= &cfun
->machine
->frame
;
10039 memset (frame
, 0, sizeof (*frame
));
10040 size
= get_frame_size ();
10042 cfun
->machine
->global_pointer
= mips_global_pointer ();
10044 /* The first two blocks contain the outgoing argument area and the $gp save
10045 slot. This area isn't needed in leaf functions, but if the
10046 target-independent frame size is nonzero, we have already committed to
10047 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
10048 if ((size
== 0 || FRAME_GROWS_DOWNWARD
) && crtl
->is_leaf
)
10050 /* The MIPS 3.0 linker does not like functions that dynamically
10051 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
10052 looks like we are trying to create a second frame pointer to the
10053 function, so allocate some stack space to make it happy. */
10054 if (cfun
->calls_alloca
)
10055 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
10057 frame
->args_size
= 0;
10058 frame
->cprestore_size
= 0;
10062 frame
->args_size
= crtl
->outgoing_args_size
;
10063 frame
->cprestore_size
= MIPS_GP_SAVE_AREA_SIZE
;
10065 offset
= frame
->args_size
+ frame
->cprestore_size
;
10067 /* Move above the local variables. */
10068 frame
->var_size
= MIPS_STACK_ALIGN (size
);
10069 offset
+= frame
->var_size
;
10071 /* Find out which GPRs we need to save. */
10072 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
10073 if (mips_save_reg_p (regno
))
10076 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
10079 /* If this function calls eh_return, we must also save and restore the
10080 EH data registers. */
10081 if (crtl
->calls_eh_return
)
10082 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
10085 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
10088 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
10089 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
10090 save all later registers too. */
10091 if (GENERATE_MIPS16E_SAVE_RESTORE
)
10093 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
10094 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
10095 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
10096 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
10099 /* Move above the GPR save area. */
10100 if (frame
->num_gp
> 0)
10102 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
10103 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
10106 /* Find out which FPRs we need to save. This loop must iterate over
10107 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
10108 if (TARGET_HARD_FLOAT
)
10109 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
10110 if (mips_save_reg_p (regno
))
10112 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
10113 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
10116 /* Move above the FPR save area. */
10117 if (frame
->num_fp
> 0)
10119 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
10120 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
10123 /* Add in space for the interrupt context information. */
10124 if (cfun
->machine
->interrupt_handler_p
)
10127 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
10130 frame
->acc_mask
|= (1 << 0);
10133 /* Check accumulators 1, 2, 3. */
10134 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
10135 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
10138 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
10141 /* All interrupt context functions need space to preserve STATUS. */
10142 frame
->num_cop0_regs
++;
10144 /* If we don't keep interrupts masked, we need to save EPC. */
10145 if (!cfun
->machine
->keep_interrupts_masked_p
)
10146 frame
->num_cop0_regs
++;
10149 /* Move above the accumulator save area. */
10150 if (frame
->num_acc
> 0)
10152 /* Each accumulator needs 2 words. */
10153 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
10154 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
10157 /* Move above the COP0 register save area. */
10158 if (frame
->num_cop0_regs
> 0)
10160 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
10161 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
10164 /* Move above the callee-allocated varargs save area. */
10165 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
10166 frame
->arg_pointer_offset
= offset
;
10168 /* Move above the callee-allocated area for pretend stack arguments. */
10169 offset
+= crtl
->args
.pretend_args_size
;
10170 frame
->total_size
= offset
;
10172 /* Work out the offsets of the save areas from the top of the frame. */
10173 if (frame
->gp_sp_offset
> 0)
10174 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
10175 if (frame
->fp_sp_offset
> 0)
10176 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
10177 if (frame
->acc_sp_offset
> 0)
10178 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
10179 if (frame
->num_cop0_regs
> 0)
10180 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
10182 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10183 arguments. This tends to increase the chances of using unextended
10184 instructions for local variables and incoming arguments. */
10186 frame
->hard_frame_pointer_offset
= frame
->args_size
;
10189 /* Return the style of GP load sequence that is being used for the
10190 current function. */
10192 enum mips_loadgp_style
10193 mips_current_loadgp_style (void)
10195 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
10196 return LOADGP_NONE
;
10198 if (TARGET_RTP_PIC
)
10201 if (TARGET_ABSOLUTE_ABICALLS
)
10202 return LOADGP_ABSOLUTE
;
10204 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
10207 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10210 mips_frame_pointer_required (void)
10212 /* If the function contains dynamic stack allocations, we need to
10213 use the frame pointer to access the static parts of the frame. */
10214 if (cfun
->calls_alloca
)
10217 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
10218 reload may be unable to compute the address of a local variable,
10219 since there is no way to add a large constant to the stack pointer
10220 without using a second temporary register. */
10223 mips_compute_frame_info ();
10224 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
10231 /* Make sure that we're not trying to eliminate to the wrong hard frame
10235 mips_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
10237 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
10240 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10241 or argument pointer. TO is either the stack pointer or hard frame
10245 mips_initial_elimination_offset (int from
, int to
)
10247 HOST_WIDE_INT offset
;
10249 mips_compute_frame_info ();
10251 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10254 case FRAME_POINTER_REGNUM
:
10255 if (FRAME_GROWS_DOWNWARD
)
10256 offset
= (cfun
->machine
->frame
.args_size
10257 + cfun
->machine
->frame
.cprestore_size
10258 + cfun
->machine
->frame
.var_size
);
10263 case ARG_POINTER_REGNUM
:
10264 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
10268 gcc_unreachable ();
10271 if (to
== HARD_FRAME_POINTER_REGNUM
)
10272 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
10277 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10280 mips_extra_live_on_entry (bitmap regs
)
10282 if (TARGET_USE_GOT
)
10284 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10285 the global pointer. */
10286 if (!TARGET_ABSOLUTE_ABICALLS
)
10287 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
10289 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10290 the global pointer. */
10292 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
10294 /* See the comment above load_call<mode> for details. */
10295 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
10299 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10303 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
10308 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
10311 /* Emit code to change the current function's return address to
10312 ADDRESS. SCRATCH is available as a scratch register, if needed.
10313 ADDRESS and SCRATCH are both word-mode GPRs. */
10316 mips_set_return_address (rtx address
, rtx scratch
)
10320 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
10321 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
10322 cfun
->machine
->frame
.gp_sp_offset
);
10323 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
10326 /* Return true if the current function has a cprestore slot. */
10329 mips_cfun_has_cprestore_slot_p (void)
10331 return (cfun
->machine
->global_pointer
!= INVALID_REGNUM
10332 && cfun
->machine
->frame
.cprestore_size
> 0);
10335 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10336 cprestore slot. LOAD_P is true if the caller wants to load from
10337 the cprestore slot; it is false if the caller wants to store to
10341 mips_get_cprestore_base_and_offset (rtx
*base
, HOST_WIDE_INT
*offset
,
10344 const struct mips_frame_info
*frame
;
10346 frame
= &cfun
->machine
->frame
;
10347 /* .cprestore always uses the stack pointer instead of the frame pointer.
10348 We have a free choice for direct stores for non-MIPS16 functions,
10349 and for MIPS16 functions whose cprestore slot is in range of the
10350 stack pointer. Using the stack pointer would sometimes give more
10351 (early) scheduling freedom, but using the frame pointer would
10352 sometimes give more (late) scheduling freedom. It's hard to
10353 predict which applies to a given function, so let's keep things
10356 Loads must always use the frame pointer in functions that call
10357 alloca, and there's little benefit to using the stack pointer
10359 if (frame_pointer_needed
&& !(TARGET_CPRESTORE_DIRECTIVE
&& !load_p
))
10361 *base
= hard_frame_pointer_rtx
;
10362 *offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
10366 *base
= stack_pointer_rtx
;
10367 *offset
= frame
->args_size
;
10371 /* Return true if X is the load or store address of the cprestore slot;
10372 LOAD_P says which. */
10375 mips_cprestore_address_p (rtx x
, bool load_p
)
10377 rtx given_base
, required_base
;
10378 HOST_WIDE_INT given_offset
, required_offset
;
10380 mips_split_plus (x
, &given_base
, &given_offset
);
10381 mips_get_cprestore_base_and_offset (&required_base
, &required_offset
, load_p
);
10382 return given_base
== required_base
&& given_offset
== required_offset
;
10385 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10386 going to load from it, false if we are going to store to it.
10387 Use TEMP as a temporary register if need be. */
10390 mips_cprestore_slot (rtx temp
, bool load_p
)
10393 HOST_WIDE_INT offset
;
10395 mips_get_cprestore_base_and_offset (&base
, &offset
, load_p
);
10396 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
10399 /* Emit instructions to save global pointer value GP into cprestore
10400 slot MEM. OFFSET is the offset that MEM applies to the base register.
10402 MEM may not be a legitimate address. If it isn't, TEMP is a
10403 temporary register that can be used, otherwise it is a SCRATCH. */
10406 mips_save_gp_to_cprestore_slot (rtx mem
, rtx offset
, rtx gp
, rtx temp
)
10408 if (TARGET_CPRESTORE_DIRECTIVE
)
10410 gcc_assert (gp
== pic_offset_table_rtx
);
10411 emit_insn (PMODE_INSN (gen_cprestore
, (mem
, offset
)));
10414 mips_emit_move (mips_cprestore_slot (temp
, false), gp
);
10417 /* Restore $gp from its save slot, using TEMP as a temporary base register
10418 if need be. This function is for o32 and o64 abicalls only.
10420 See mips_must_initialize_gp_p for details about how we manage the
10424 mips_restore_gp_from_cprestore_slot (rtx temp
)
10426 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
&& epilogue_completed
);
10428 if (!cfun
->machine
->must_restore_gp_when_clobbered_p
)
10430 emit_note (NOTE_INSN_DELETED
);
10436 mips_emit_move (temp
, mips_cprestore_slot (temp
, true));
10437 mips_emit_move (pic_offset_table_rtx
, temp
);
10440 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
, true));
10441 if (!TARGET_EXPLICIT_RELOCS
)
10442 emit_insn (gen_blockage ());
10445 /* A function to save or store a register. The first argument is the
10446 register and the second is the stack slot. */
10447 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
10449 /* Use FN to save or restore register REGNO. MODE is the register's
10450 mode and OFFSET is the offset of its save slot from the current
10454 mips_save_restore_reg (enum machine_mode mode
, int regno
,
10455 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
10459 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
,
10461 fn (gen_rtx_REG (mode
, regno
), mem
);
10464 /* Call FN for each accumlator that is saved by the current function.
10465 SP_OFFSET is the offset of the current stack pointer from the start
10469 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
10471 HOST_WIDE_INT offset
;
10474 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
10475 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
10477 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
10478 offset
-= UNITS_PER_WORD
;
10479 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
10480 offset
-= UNITS_PER_WORD
;
10483 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
10484 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
10485 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
10487 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10488 offset
-= UNITS_PER_WORD
;
10492 /* Save register REG to MEM. Make the instruction frame-related. */
10495 mips_save_reg (rtx reg
, rtx mem
)
10497 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
10501 mips_emit_move_or_split (mem
, reg
, SPLIT_IF_NECESSARY
);
10503 x1
= mips_frame_set (mips_subword (mem
, false),
10504 mips_subword (reg
, false));
10505 x2
= mips_frame_set (mips_subword (mem
, true),
10506 mips_subword (reg
, true));
10507 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
10510 mips_emit_save_slot_move (mem
, reg
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
10513 /* Capture the register combinations that are allowed in a SWM or LWM
10514 instruction. The entries are ordered by number of registers set in
10515 the mask. We also ignore the single register encodings because a
10516 normal SW/LW is preferred. */
10518 static const unsigned int umips_swm_mask
[17] = {
10519 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
10520 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
10521 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
10522 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
10526 static const unsigned int umips_swm_encoding
[17] = {
10527 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
10530 /* Try to use a microMIPS LWM or SWM instruction to save or restore
10531 as many GPRs in *MASK as possible. *OFFSET is the offset from the
10532 stack pointer of the topmost save slot.
10534 Remove from *MASK all registers that were handled using LWM and SWM.
10535 Update *OFFSET so that it points to the first unused save slot. */
10538 umips_build_save_restore (mips_save_restore_fn fn
,
10539 unsigned *mask
, HOST_WIDE_INT
*offset
)
10543 rtx pattern
, set
, reg
, mem
;
10544 HOST_WIDE_INT this_offset
;
10547 /* Try matching $16 to $31 (s0 to ra). */
10548 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
10549 if ((*mask
& 0xffff0000) == umips_swm_mask
[i
])
10552 if (i
== ARRAY_SIZE (umips_swm_mask
))
10555 /* Get the offset of the lowest save slot. */
10556 nregs
= (umips_swm_encoding
[i
] & 0xf) + (umips_swm_encoding
[i
] >> 4);
10557 this_offset
= *offset
- UNITS_PER_WORD
* (nregs
- 1);
10559 /* LWM/SWM can only support offsets from -2048 to 2047. */
10560 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
10563 /* Create the final PARALLEL. */
10564 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nregs
));
10565 this_base
= stack_pointer_rtx
;
10567 /* For registers $16-$23 and $30. */
10568 for (j
= 0; j
< (umips_swm_encoding
[i
] & 0xf); j
++)
10570 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10571 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10572 unsigned int regno
= (j
!= 8) ? 16 + j
: 30;
10573 *mask
&= ~(1 << regno
);
10574 reg
= gen_rtx_REG (SImode
, regno
);
10575 if (fn
== mips_save_reg
)
10576 set
= mips_frame_set (mem
, reg
);
10579 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
10580 mips_add_cfa_restore (reg
);
10582 XVECEXP (pattern
, 0, j
) = set
;
10585 /* For register $31. */
10586 if (umips_swm_encoding
[i
] >> 4)
10588 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10589 *mask
&= ~(1 << 31);
10590 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10591 reg
= gen_rtx_REG (SImode
, 31);
10592 if (fn
== mips_save_reg
)
10593 set
= mips_frame_set (mem
, reg
);
10596 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
10597 mips_add_cfa_restore (reg
);
10599 XVECEXP (pattern
, 0, j
) = set
;
10602 pattern
= emit_insn (pattern
);
10603 if (fn
== mips_save_reg
)
10604 RTX_FRAME_RELATED_P (pattern
) = 1;
10606 /* Adjust the last offset. */
10607 *offset
-= UNITS_PER_WORD
* nregs
;
10612 /* Call FN for each register that is saved by the current function.
10613 SP_OFFSET is the offset of the current stack pointer from the start
10617 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
10618 mips_save_restore_fn fn
)
10620 enum machine_mode fpr_mode
;
10622 const struct mips_frame_info
*frame
= &cfun
->machine
->frame
;
10623 HOST_WIDE_INT offset
;
10626 /* Save registers starting from high to low. The debuggers prefer at least
10627 the return register be stored at func+4, and also it allows us not to
10628 need a nop in the epilogue if at least one register is reloaded in
10629 addition to return address. */
10630 offset
= frame
->gp_sp_offset
- sp_offset
;
10631 mask
= frame
->mask
;
10633 if (TARGET_MICROMIPS
)
10634 umips_build_save_restore (fn
, &mask
, &offset
);
10636 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
10637 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10639 /* Record the ra offset for use by mips_function_profiler. */
10640 if (regno
== RETURN_ADDR_REGNUM
)
10641 cfun
->machine
->frame
.ra_fp_offset
= offset
+ sp_offset
;
10642 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10643 offset
-= UNITS_PER_WORD
;
10646 /* This loop must iterate over the same space as its companion in
10647 mips_compute_frame_info. */
10648 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
10649 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
10650 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
10651 regno
>= FP_REG_FIRST
;
10652 regno
-= MAX_FPRS_PER_FMT
)
10653 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
10655 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
10656 offset
-= GET_MODE_SIZE (fpr_mode
);
10660 /* Return true if a move between register REGNO and its save slot (MEM)
10661 can be done in a single move. LOAD_P is true if we are loading
10662 from the slot, false if we are storing to it. */
10665 mips_direct_save_slot_move_p (unsigned int regno
, rtx mem
, bool load_p
)
10667 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10668 if (TARGET_MIPS16
&& !load_p
&& regno
== RETURN_ADDR_REGNUM
)
10671 return mips_secondary_reload_class (REGNO_REG_CLASS (regno
),
10672 GET_MODE (mem
), mem
, load_p
) == NO_REGS
;
10675 /* Emit a move from SRC to DEST, given that one of them is a register
10676 save slot and that the other is a register. TEMP is a temporary
10677 GPR of the same mode that is available if need be. */
10680 mips_emit_save_slot_move (rtx dest
, rtx src
, rtx temp
)
10682 unsigned int regno
;
10687 regno
= REGNO (src
);
10692 regno
= REGNO (dest
);
10696 if (regno
== cfun
->machine
->global_pointer
&& !mips_must_initialize_gp_p ())
10698 /* We don't yet know whether we'll need this instruction or not.
10699 Postpone the decision by emitting a ghost move. This move
10700 is specifically not frame-related; only the split version is. */
10702 emit_insn (gen_move_gpdi (dest
, src
));
10704 emit_insn (gen_move_gpsi (dest
, src
));
10708 if (regno
== HI_REGNUM
)
10712 mips_emit_move (temp
, src
);
10714 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode
, MD_REG_FIRST
),
10715 temp
, gen_rtx_REG (DImode
, LO_REGNUM
)));
10717 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
10718 temp
, gen_rtx_REG (SImode
, LO_REGNUM
)));
10723 emit_insn (gen_mfhidi_ti (temp
,
10724 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
10726 emit_insn (gen_mfhisi_di (temp
,
10727 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
10728 mips_emit_move (dest
, temp
);
10731 else if (mips_direct_save_slot_move_p (regno
, mem
, mem
== src
))
10732 mips_emit_move (dest
, src
);
10735 gcc_assert (!reg_overlap_mentioned_p (dest
, temp
));
10736 mips_emit_move (temp
, src
);
10737 mips_emit_move (dest
, temp
);
10740 mips_set_frame_expr (mips_frame_set (dest
, src
));
10743 /* If we're generating n32 or n64 abicalls, and the current function
10744 does not use $28 as its global pointer, emit a cplocal directive.
10745 Use pic_offset_table_rtx as the argument to the directive. */
10748 mips_output_cplocal (void)
10750 if (!TARGET_EXPLICIT_RELOCS
10751 && mips_must_initialize_gp_p ()
10752 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
10753 output_asm_insn (".cplocal %+", 0);
10756 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10759 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10761 const char *fnname
;
10763 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10764 floating-point arguments. */
10766 && TARGET_HARD_FLOAT_ABI
10767 && crtl
->args
.info
.fp_code
!= 0)
10768 mips16_build_function_stub ();
10770 /* Get the function name the same way that toplev.c does before calling
10771 assemble_start_function. This is needed so that the name used here
10772 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10773 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10774 mips_start_function_definition (fnname
, TARGET_MIPS16
);
10776 /* Output MIPS-specific frame information. */
10777 if (!flag_inhibit_size_directive
)
10779 const struct mips_frame_info
*frame
;
10781 frame
= &cfun
->machine
->frame
;
10783 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10785 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
10786 "# vars= " HOST_WIDE_INT_PRINT_DEC
10788 ", args= " HOST_WIDE_INT_PRINT_DEC
10789 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
10790 reg_names
[frame_pointer_needed
10791 ? HARD_FRAME_POINTER_REGNUM
10792 : STACK_POINTER_REGNUM
],
10793 (frame_pointer_needed
10794 ? frame
->total_size
- frame
->hard_frame_pointer_offset
10795 : frame
->total_size
),
10796 reg_names
[RETURN_ADDR_REGNUM
],
10798 frame
->num_gp
, frame
->num_fp
,
10800 frame
->cprestore_size
);
10802 /* .mask MASK, OFFSET. */
10803 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10804 frame
->mask
, frame
->gp_save_offset
);
10806 /* .fmask MASK, OFFSET. */
10807 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10808 frame
->fmask
, frame
->fp_save_offset
);
10811 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10812 Also emit the ".set noreorder; .set nomacro" sequence for functions
10814 if (mips_must_initialize_gp_p ()
10815 && mips_current_loadgp_style () == LOADGP_OLDABI
)
10819 /* This is a fixed-form sequence. The position of the
10820 first two instructions is important because of the
10821 way _gp_disp is defined. */
10822 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10823 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10824 output_asm_insn ("sll\t$2,16", 0);
10825 output_asm_insn ("addu\t$2,$3", 0);
10829 /* .cpload must be in a .set noreorder but not a
10830 .set nomacro block. */
10831 mips_push_asm_switch (&mips_noreorder
);
10832 output_asm_insn (".cpload\t%^", 0);
10833 if (!cfun
->machine
->all_noreorder_p
)
10834 mips_pop_asm_switch (&mips_noreorder
);
10836 mips_push_asm_switch (&mips_nomacro
);
10839 else if (cfun
->machine
->all_noreorder_p
)
10841 mips_push_asm_switch (&mips_noreorder
);
10842 mips_push_asm_switch (&mips_nomacro
);
10845 /* Tell the assembler which register we're using as the global
10846 pointer. This is needed for thunks, since they can use either
10847 explicit relocs or assembler macros. */
10848 mips_output_cplocal ();
10851 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10854 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
10855 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10857 const char *fnname
;
10859 /* Reinstate the normal $gp. */
10860 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
10861 mips_output_cplocal ();
10863 if (cfun
->machine
->all_noreorder_p
)
10865 mips_pop_asm_switch (&mips_nomacro
);
10866 mips_pop_asm_switch (&mips_noreorder
);
10869 /* Get the function name the same way that toplev.c does before calling
10870 assemble_start_function. This is needed so that the name used here
10871 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10872 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10873 mips_end_function_definition (fnname
);
10876 /* Emit an optimisation barrier for accesses to the current frame. */
10879 mips_frame_barrier (void)
10881 emit_clobber (gen_frame_mem (BLKmode
, stack_pointer_rtx
));
10885 /* The __gnu_local_gp symbol. */
10887 static GTY(()) rtx mips_gnu_local_gp
;
10889 /* If we're generating n32 or n64 abicalls, emit instructions
10890 to set up the global pointer. */
10893 mips_emit_loadgp (void)
10895 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
10897 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
10898 switch (mips_current_loadgp_style ())
10900 case LOADGP_ABSOLUTE
:
10901 if (mips_gnu_local_gp
== NULL
)
10903 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
10904 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
10906 emit_insn (PMODE_INSN (gen_loadgp_absolute
,
10907 (pic_reg
, mips_gnu_local_gp
)));
10910 case LOADGP_OLDABI
:
10911 /* Added by mips_output_function_prologue. */
10914 case LOADGP_NEWABI
:
10915 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
10916 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
10917 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
10918 emit_insn (PMODE_INSN (gen_loadgp_newabi
,
10919 (pic_reg
, offset
, incoming_address
)));
10923 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
10924 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
10925 emit_insn (PMODE_INSN (gen_loadgp_rtp
, (pic_reg
, base
, index
)));
10933 emit_insn (PMODE_INSN (gen_copygp_mips16
,
10934 (pic_offset_table_rtx
, pic_reg
)));
10936 /* Emit a blockage if there are implicit uses of the GP register.
10937 This includes profiled functions, because FUNCTION_PROFILE uses
10939 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
10940 emit_insn (gen_loadgp_blockage ());
10943 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10945 #if PROBE_INTERVAL > 32768
10946 #error Cannot use indexed addressing mode for stack probing
10949 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10950 inclusive. These are offsets from the current stack pointer. */
10953 mips_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
10956 sorry ("-fstack-check=specific not implemented for MIPS16");
10958 /* See if we have a constant small number of probes to generate. If so,
10959 that's the easy case. */
10960 if (first
+ size
<= 32768)
10964 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10965 it exceeds SIZE. If only one probe is needed, this will not
10966 generate any code. Then probe at FIRST + SIZE. */
10967 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
10968 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
10971 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
10975 /* Otherwise, do the same as above, but in a loop. Note that we must be
10976 extra careful with variables wrapping around because we might be at
10977 the very top (or the very bottom) of the address space and we have
10978 to be able to handle this case properly; in particular, we use an
10979 equality test for the loop condition. */
10982 HOST_WIDE_INT rounded_size
;
10983 rtx r3
= MIPS_PROLOGUE_TEMP (Pmode
);
10984 rtx r12
= MIPS_PROLOGUE_TEMP2 (Pmode
);
10986 /* Sanity check for the addressing mode we're going to use. */
10987 gcc_assert (first
<= 32768);
10990 /* Step 1: round SIZE to the previous multiple of the interval. */
10992 rounded_size
= size
& -PROBE_INTERVAL
;
10995 /* Step 2: compute initial and final value of the loop counter. */
10997 /* TEST_ADDR = SP + FIRST. */
10998 emit_insn (gen_rtx_SET (VOIDmode
, r3
,
10999 plus_constant (Pmode
, stack_pointer_rtx
,
11002 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
11003 if (rounded_size
> 32768)
11005 emit_move_insn (r12
, GEN_INT (rounded_size
));
11006 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
11007 gen_rtx_MINUS (Pmode
, r3
, r12
)));
11010 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
11011 plus_constant (Pmode
, r3
, -rounded_size
)));
11014 /* Step 3: the loop
11016 while (TEST_ADDR != LAST_ADDR)
11018 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11022 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11023 until it is equal to ROUNDED_SIZE. */
11025 emit_insn (PMODE_INSN (gen_probe_stack_range
, (r3
, r3
, r12
)));
11028 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11029 that SIZE is equal to ROUNDED_SIZE. */
11031 if (size
!= rounded_size
)
11032 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
11035 /* Make sure nothing is scheduled before we are done. */
11036 emit_insn (gen_blockage ());
11039 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
11040 absolute addresses. */
11043 mips_output_probe_stack_range (rtx reg1
, rtx reg2
)
11045 static int labelno
= 0;
11046 char loop_lab
[32], end_lab
[32], tmp
[64];
11049 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
11050 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
11052 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
11054 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11057 strcpy (tmp
, "%(%<beq\t%0,%1,");
11058 output_asm_insn (strcat (tmp
, &end_lab
[1]), xops
);
11060 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11061 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
11062 if (TARGET_64BIT
&& TARGET_LONG64
)
11063 output_asm_insn ("daddiu\t%0,%0,%1", xops
);
11065 output_asm_insn ("addiu\t%0,%0,%1", xops
);
11067 /* Probe at TEST_ADDR and branch. */
11068 fprintf (asm_out_file
, "\tb\t");
11069 assemble_name_raw (asm_out_file
, loop_lab
);
11070 fputc ('\n', asm_out_file
);
11072 output_asm_insn ("sd\t$0,0(%0)%)", xops
);
11074 output_asm_insn ("sw\t$0,0(%0)%)", xops
);
11076 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
11081 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
11084 mips_kernel_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
11086 return REG_P (*x
) && KERNEL_REG_P (REGNO (*x
));
11089 /* Expand the "prologue" pattern. */
11092 mips_expand_prologue (void)
11094 const struct mips_frame_info
*frame
;
11095 HOST_WIDE_INT size
;
11096 unsigned int nargs
;
11099 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
11101 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
11102 or implicitly. If so, we can commit to using a global pointer
11103 straight away, otherwise we need to defer the decision. */
11104 if (mips_cfun_has_inflexible_gp_ref_p ()
11105 || mips_cfun_has_flexible_gp_ref_p ())
11107 cfun
->machine
->must_initialize_gp_p
= true;
11108 cfun
->machine
->must_restore_gp_when_clobbered_p
= true;
11111 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
11114 frame
= &cfun
->machine
->frame
;
11115 size
= frame
->total_size
;
11117 if (flag_stack_usage_info
)
11118 current_function_static_stack_size
= size
;
11120 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
11122 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
11124 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
11125 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
,
11126 size
- STACK_CHECK_PROTECT
);
11129 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
11132 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
11133 bytes beforehand; this is enough to cover the register save area
11134 without going out of range. */
11135 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
11136 || frame
->num_cop0_regs
> 0)
11138 HOST_WIDE_INT step1
;
11140 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
11141 if (GENERATE_MIPS16E_SAVE_RESTORE
)
11143 HOST_WIDE_INT offset
;
11144 unsigned int mask
, regno
;
11146 /* Try to merge argument stores into the save instruction. */
11147 nargs
= mips16e_collect_argument_saves ();
11149 /* Build the save instruction. */
11150 mask
= frame
->mask
;
11151 insn
= mips16e_build_save_restore (false, &mask
, &offset
,
11153 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11154 mips_frame_barrier ();
11157 /* Check if we need to save other registers. */
11158 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11159 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11161 offset
-= UNITS_PER_WORD
;
11162 mips_save_restore_reg (word_mode
, regno
,
11163 offset
, mips_save_reg
);
11168 if (cfun
->machine
->interrupt_handler_p
)
11170 HOST_WIDE_INT offset
;
11173 /* If this interrupt is using a shadow register set, we need to
11174 get the stack pointer from the previous register set. */
11175 if (cfun
->machine
->use_shadow_register_set_p
)
11176 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx
,
11177 stack_pointer_rtx
));
11179 if (!cfun
->machine
->keep_interrupts_masked_p
)
11181 /* Move from COP0 Cause to K0. */
11182 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
11183 gen_rtx_REG (SImode
,
11184 COP0_CAUSE_REG_NUM
)));
11185 /* Move from COP0 EPC to K1. */
11186 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11187 gen_rtx_REG (SImode
,
11188 COP0_EPC_REG_NUM
)));
11191 /* Allocate the first part of the frame. */
11192 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
11194 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11195 mips_frame_barrier ();
11198 /* Start at the uppermost location for saving. */
11199 offset
= frame
->cop0_sp_offset
- size
;
11200 if (!cfun
->machine
->keep_interrupts_masked_p
)
11202 /* Push EPC into its stack slot. */
11203 mem
= gen_frame_mem (word_mode
,
11204 plus_constant (Pmode
, stack_pointer_rtx
,
11206 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11207 offset
-= UNITS_PER_WORD
;
11210 /* Move from COP0 Status to K1. */
11211 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11212 gen_rtx_REG (SImode
,
11213 COP0_STATUS_REG_NUM
)));
11215 /* Right justify the RIPL in k0. */
11216 if (!cfun
->machine
->keep_interrupts_masked_p
)
11217 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
11218 gen_rtx_REG (SImode
, K0_REG_NUM
),
11219 GEN_INT (CAUSE_IPL
)));
11221 /* Push Status into its stack slot. */
11222 mem
= gen_frame_mem (word_mode
,
11223 plus_constant (Pmode
, stack_pointer_rtx
,
11225 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11226 offset
-= UNITS_PER_WORD
;
11228 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
11229 if (!cfun
->machine
->keep_interrupts_masked_p
)
11230 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11233 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11235 if (!cfun
->machine
->keep_interrupts_masked_p
)
11236 /* Enable interrupts by clearing the KSU ERL and EXL bits.
11237 IE is already the correct value, so we don't have to do
11238 anything explicit. */
11239 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11242 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11244 /* Disable interrupts by clearing the KSU, ERL, EXL,
11246 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11249 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11253 insn
= gen_add3_insn (stack_pointer_rtx
,
11256 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11257 mips_frame_barrier ();
11260 mips_for_each_saved_acc (size
, mips_save_reg
);
11261 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
11265 /* Allocate the rest of the frame. */
11268 if (SMALL_OPERAND (-size
))
11269 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
11271 GEN_INT (-size
)))) = 1;
11274 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
11277 /* There are no instructions to add or subtract registers
11278 from the stack pointer, so use the frame pointer as a
11279 temporary. We should always be using a frame pointer
11280 in this case anyway. */
11281 gcc_assert (frame_pointer_needed
);
11282 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11283 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
11284 hard_frame_pointer_rtx
,
11285 MIPS_PROLOGUE_TEMP (Pmode
)));
11286 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
11289 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
11291 MIPS_PROLOGUE_TEMP (Pmode
)));
11293 /* Describe the combined effect of the previous instructions. */
11294 mips_set_frame_expr
11295 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
11296 plus_constant (Pmode
, stack_pointer_rtx
, -size
)));
11298 mips_frame_barrier ();
11301 /* Set up the frame pointer, if we're using one. */
11302 if (frame_pointer_needed
)
11304 HOST_WIDE_INT offset
;
11306 offset
= frame
->hard_frame_pointer_offset
;
11309 insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11310 RTX_FRAME_RELATED_P (insn
) = 1;
11312 else if (SMALL_OPERAND (offset
))
11314 insn
= gen_add3_insn (hard_frame_pointer_rtx
,
11315 stack_pointer_rtx
, GEN_INT (offset
));
11316 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11320 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
11321 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11322 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
11323 hard_frame_pointer_rtx
,
11324 MIPS_PROLOGUE_TEMP (Pmode
)));
11325 mips_set_frame_expr
11326 (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
11327 plus_constant (Pmode
, stack_pointer_rtx
, offset
)));
11331 mips_emit_loadgp ();
11333 /* Initialize the $gp save slot. */
11334 if (mips_cfun_has_cprestore_slot_p ())
11336 rtx base
, mem
, gp
, temp
;
11337 HOST_WIDE_INT offset
;
11339 mips_get_cprestore_base_and_offset (&base
, &offset
, false);
11340 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11341 gp
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
11342 temp
= (SMALL_OPERAND (offset
)
11343 ? gen_rtx_SCRATCH (Pmode
)
11344 : MIPS_PROLOGUE_TEMP (Pmode
));
11345 emit_insn (PMODE_INSN (gen_potential_cprestore
,
11346 (mem
, GEN_INT (offset
), gp
, temp
)));
11348 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
11349 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11350 emit_insn (PMODE_INSN (gen_use_cprestore
, (mem
)));
11353 /* We need to search back to the last use of K0 or K1. */
11354 if (cfun
->machine
->interrupt_handler_p
)
11356 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
11358 && for_each_rtx (&PATTERN (insn
), mips_kernel_reg_p
, NULL
))
11360 /* Emit a move from K1 to COP0 Status after insn. */
11361 gcc_assert (insn
!= NULL_RTX
);
11362 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11363 gen_rtx_REG (SImode
, K1_REG_NUM
)),
11367 /* If we are profiling, make sure no instructions are scheduled before
11368 the call to mcount. */
11370 emit_insn (gen_blockage ());
11373 /* Attach all pending register saves to the previous instruction.
11374 Return that instruction. */
11377 mips_epilogue_emit_cfa_restores (void)
11381 insn
= get_last_insn ();
11382 gcc_assert (insn
&& !REG_NOTES (insn
));
11383 if (mips_epilogue
.cfa_restores
)
11385 RTX_FRAME_RELATED_P (insn
) = 1;
11386 REG_NOTES (insn
) = mips_epilogue
.cfa_restores
;
11387 mips_epilogue
.cfa_restores
= 0;
11392 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11393 now at REG + OFFSET. */
11396 mips_epilogue_set_cfa (rtx reg
, HOST_WIDE_INT offset
)
11400 insn
= mips_epilogue_emit_cfa_restores ();
11401 if (reg
!= mips_epilogue
.cfa_reg
|| offset
!= mips_epilogue
.cfa_offset
)
11403 RTX_FRAME_RELATED_P (insn
) = 1;
11404 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_DEF_CFA
,
11405 plus_constant (Pmode
, reg
, offset
),
11407 mips_epilogue
.cfa_reg
= reg
;
11408 mips_epilogue
.cfa_offset
= offset
;
11412 /* Emit instructions to restore register REG from slot MEM. Also update
11413 the cfa_restores list. */
11416 mips_restore_reg (rtx reg
, rtx mem
)
11418 /* There's no MIPS16 instruction to load $31 directly. Load into
11419 $7 instead and adjust the return insn appropriately. */
11420 if (TARGET_MIPS16
&& REGNO (reg
) == RETURN_ADDR_REGNUM
)
11421 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
11422 else if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
11424 mips_add_cfa_restore (mips_subword (reg
, true));
11425 mips_add_cfa_restore (mips_subword (reg
, false));
11428 mips_add_cfa_restore (reg
);
11430 mips_emit_save_slot_move (reg
, mem
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
11431 if (REGNO (reg
) == REGNO (mips_epilogue
.cfa_reg
))
11432 /* The CFA is currently defined in terms of the register whose
11433 value we have just restored. Redefine the CFA in terms of
11434 the stack pointer. */
11435 mips_epilogue_set_cfa (stack_pointer_rtx
,
11436 mips_epilogue
.cfa_restore_sp_offset
);
11439 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11440 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11441 BASE, if not the stack pointer, is available as a temporary. */
11444 mips_deallocate_stack (rtx base
, rtx offset
, HOST_WIDE_INT new_frame_size
)
11446 if (base
== stack_pointer_rtx
&& offset
== const0_rtx
)
11449 mips_frame_barrier ();
11450 if (offset
== const0_rtx
)
11452 emit_move_insn (stack_pointer_rtx
, base
);
11453 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11455 else if (TARGET_MIPS16
&& base
!= stack_pointer_rtx
)
11457 emit_insn (gen_add3_insn (base
, base
, offset
));
11458 mips_epilogue_set_cfa (base
, new_frame_size
);
11459 emit_move_insn (stack_pointer_rtx
, base
);
11463 emit_insn (gen_add3_insn (stack_pointer_rtx
, base
, offset
));
11464 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11468 /* Emit any instructions needed before a return. */
11471 mips_expand_before_return (void)
11473 /* When using a call-clobbered gp, we start out with unified call
11474 insns that include instructions to restore the gp. We then split
11475 these unified calls after reload. These split calls explicitly
11476 clobber gp, so there is no need to define
11477 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11479 For consistency, we should also insert an explicit clobber of $28
11480 before return insns, so that the post-reload optimizers know that
11481 the register is not live on exit. */
11482 if (TARGET_CALL_CLOBBERED_GP
)
11483 emit_clobber (pic_offset_table_rtx
);
11486 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11490 mips_expand_epilogue (bool sibcall_p
)
11492 const struct mips_frame_info
*frame
;
11493 HOST_WIDE_INT step1
, step2
;
11494 rtx base
, adjust
, insn
;
11495 bool use_jraddiusp_p
= false;
11497 if (!sibcall_p
&& mips_can_use_return_insn ())
11499 emit_jump_insn (gen_return ());
11503 /* In MIPS16 mode, if the return value should go into a floating-point
11504 register, we need to call a helper routine to copy it over. */
11505 if (mips16_cfun_returns_in_fpr_p ())
11506 mips16_copy_fpr_return_value ();
11508 /* Split the frame into two. STEP1 is the amount of stack we should
11509 deallocate before restoring the registers. STEP2 is the amount we
11510 should deallocate afterwards.
11512 Start off by assuming that no registers need to be restored. */
11513 frame
= &cfun
->machine
->frame
;
11514 step1
= frame
->total_size
;
11517 /* Work out which register holds the frame address. */
11518 if (!frame_pointer_needed
)
11519 base
= stack_pointer_rtx
;
11522 base
= hard_frame_pointer_rtx
;
11523 step1
-= frame
->hard_frame_pointer_offset
;
11525 mips_epilogue
.cfa_reg
= base
;
11526 mips_epilogue
.cfa_offset
= step1
;
11527 mips_epilogue
.cfa_restores
= NULL_RTX
;
11529 /* If we need to restore registers, deallocate as much stack as
11530 possible in the second step without going out of range. */
11531 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
11532 || frame
->num_cop0_regs
> 0)
11534 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
11538 /* Get an rtx for STEP1 that we can add to BASE. */
11539 adjust
= GEN_INT (step1
);
11540 if (!SMALL_OPERAND (step1
))
11542 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
11543 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
11545 mips_deallocate_stack (base
, adjust
, step2
);
11547 /* If we're using addressing macros, $gp is implicitly used by all
11548 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11550 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
11551 emit_insn (gen_blockage ());
11553 mips_epilogue
.cfa_restore_sp_offset
= step2
;
11554 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
11556 unsigned int regno
, mask
;
11557 HOST_WIDE_INT offset
;
11560 /* Generate the restore instruction. */
11561 mask
= frame
->mask
;
11562 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
11564 /* Restore any other registers manually. */
11565 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11566 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11568 offset
-= UNITS_PER_WORD
;
11569 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
11572 /* Restore the remaining registers and deallocate the final bit
11574 mips_frame_barrier ();
11575 emit_insn (restore
);
11576 mips_epilogue_set_cfa (stack_pointer_rtx
, 0);
11580 /* Restore the registers. */
11581 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
11582 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
11585 if (cfun
->machine
->interrupt_handler_p
)
11587 HOST_WIDE_INT offset
;
11590 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
11591 if (!cfun
->machine
->keep_interrupts_masked_p
)
11593 /* Restore the original EPC. */
11594 mem
= gen_frame_mem (word_mode
,
11595 plus_constant (Pmode
, stack_pointer_rtx
,
11597 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11598 offset
-= UNITS_PER_WORD
;
11600 /* Move to COP0 EPC. */
11601 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
11602 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11605 /* Restore the original Status. */
11606 mem
= gen_frame_mem (word_mode
,
11607 plus_constant (Pmode
, stack_pointer_rtx
,
11609 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11610 offset
-= UNITS_PER_WORD
;
11612 /* If we don't use shadow register set, we need to update SP. */
11613 if (!cfun
->machine
->use_shadow_register_set_p
)
11614 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11616 /* The choice of position is somewhat arbitrary in this case. */
11617 mips_epilogue_emit_cfa_restores ();
11619 /* Move to COP0 Status. */
11620 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11621 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11623 else if (TARGET_MICROMIPS
11624 && !crtl
->calls_eh_return
11627 && mips_unsigned_immediate_p (step2
, 5, 2))
11628 use_jraddiusp_p
= true;
11630 /* Deallocate the final bit of the frame. */
11631 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11634 if (!use_jraddiusp_p
)
11635 gcc_assert (!mips_epilogue
.cfa_restores
);
11637 /* Add in the __builtin_eh_return stack adjustment. We need to
11638 use a temporary in MIPS16 code. */
11639 if (crtl
->calls_eh_return
)
11643 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
11644 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
11645 MIPS_EPILOGUE_TEMP (Pmode
),
11646 EH_RETURN_STACKADJ_RTX
));
11647 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
11650 emit_insn (gen_add3_insn (stack_pointer_rtx
,
11652 EH_RETURN_STACKADJ_RTX
));
11657 mips_expand_before_return ();
11658 if (cfun
->machine
->interrupt_handler_p
)
11660 /* Interrupt handlers generate eret or deret. */
11661 if (cfun
->machine
->use_debug_exception_return_p
)
11662 emit_jump_insn (gen_mips_deret ());
11664 emit_jump_insn (gen_mips_eret ());
11670 /* When generating MIPS16 code, the normal
11671 mips_for_each_saved_gpr_and_fpr path will restore the return
11672 address into $7 rather than $31. */
11674 && !GENERATE_MIPS16E_SAVE_RESTORE
11675 && BITSET_P (frame
->mask
, RETURN_ADDR_REGNUM
))
11677 /* simple_returns cannot rely on values that are only available
11678 on paths through the epilogue (because return paths that do
11679 not pass through the epilogue may nevertheless reuse a
11680 simple_return that occurs at the end of the epilogue).
11681 Use a normal return here instead. */
11682 rtx reg
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 7);
11683 pat
= gen_return_internal (reg
);
11685 else if (use_jraddiusp_p
)
11686 pat
= gen_jraddiusp (GEN_INT (step2
));
11689 rtx reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
11690 pat
= gen_simple_return_internal (reg
);
11692 emit_jump_insn (pat
);
11693 if (use_jraddiusp_p
)
11694 mips_epilogue_set_cfa (stack_pointer_rtx
, step2
);
11698 /* Search from the beginning to the first use of K0 or K1. */
11699 if (cfun
->machine
->interrupt_handler_p
11700 && !cfun
->machine
->keep_interrupts_masked_p
)
11702 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
11704 && for_each_rtx (&PATTERN(insn
), mips_kernel_reg_p
, NULL
))
11706 gcc_assert (insn
!= NULL_RTX
);
11707 /* Insert disable interrupts before the first use of K0 or K1. */
11708 emit_insn_before (gen_mips_di (), insn
);
11709 emit_insn_before (gen_mips_ehb (), insn
);
11713 /* Return nonzero if this function is known to have a null epilogue.
11714 This allows the optimizer to omit jumps to jumps if no stack
11718 mips_can_use_return_insn (void)
11720 /* Interrupt handlers need to go through the epilogue. */
11721 if (cfun
->machine
->interrupt_handler_p
)
11724 if (!reload_completed
)
11730 /* In MIPS16 mode, a function that returns a floating-point value
11731 needs to arrange to copy the return value into the floating-point
11733 if (mips16_cfun_returns_in_fpr_p ())
11736 return cfun
->machine
->frame
.total_size
== 0;
11739 /* Return true if register REGNO can store a value of mode MODE.
11740 The result of this function is cached in mips_hard_regno_mode_ok. */
11743 mips_hard_regno_mode_ok_p (unsigned int regno
, enum machine_mode mode
)
11746 enum mode_class mclass
;
11748 if (mode
== CCV2mode
)
11749 return (ISA_HAS_8CC
11750 && ST_REG_P (regno
)
11751 && (regno
- ST_REG_FIRST
) % 2 == 0);
11753 if (mode
== CCV4mode
)
11754 return (ISA_HAS_8CC
11755 && ST_REG_P (regno
)
11756 && (regno
- ST_REG_FIRST
) % 4 == 0);
11758 if (mode
== CCmode
)
11759 return ISA_HAS_8CC
? ST_REG_P (regno
) : regno
== FPSW_REGNUM
;
11761 size
= GET_MODE_SIZE (mode
);
11762 mclass
= GET_MODE_CLASS (mode
);
11764 if (GP_REG_P (regno
))
11765 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
11767 if (FP_REG_P (regno
)
11768 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
11769 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
11771 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11772 if (TARGET_LOONGSON_VECTORS
11773 && (mode
== V2SImode
11774 || mode
== V4HImode
11775 || mode
== V8QImode
11776 || mode
== DImode
))
11779 if (mclass
== MODE_FLOAT
11780 || mclass
== MODE_COMPLEX_FLOAT
11781 || mclass
== MODE_VECTOR_FLOAT
)
11782 return size
<= UNITS_PER_FPVALUE
;
11784 /* Allow integer modes that fit into a single register. We need
11785 to put integers into FPRs when using instructions like CVT
11786 and TRUNC. There's no point allowing sizes smaller than a word,
11787 because the FPU has no appropriate load/store instructions. */
11788 if (mclass
== MODE_INT
)
11789 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
11792 if (ACC_REG_P (regno
)
11793 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
11795 if (MD_REG_P (regno
))
11797 /* After a multiplication or division, clobbering HI makes
11798 the value of LO unpredictable, and vice versa. This means
11799 that, for all interesting cases, HI and LO are effectively
11802 We model this by requiring that any value that uses HI
11804 if (size
<= UNITS_PER_WORD
* 2)
11805 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
11809 /* DSP accumulators do not have the same restrictions as
11810 HI and LO, so we can treat them as normal doubleword
11812 if (size
<= UNITS_PER_WORD
)
11815 if (size
<= UNITS_PER_WORD
* 2
11816 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
11821 if (ALL_COP_REG_P (regno
))
11822 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
11824 if (regno
== GOT_VERSION_REGNUM
)
11825 return mode
== SImode
;
11830 /* Implement HARD_REGNO_NREGS. */
11833 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
11835 if (ST_REG_P (regno
))
11836 /* The size of FP status registers is always 4, because they only hold
11837 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11838 return (GET_MODE_SIZE (mode
) + 3) / 4;
11840 if (FP_REG_P (regno
))
11841 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
11843 /* All other registers are word-sized. */
11844 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
11847 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11848 in mips_hard_regno_nregs. */
11851 mips_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
11857 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
11858 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
11860 if (HARD_REGNO_MODE_OK (ST_REG_FIRST
, mode
))
11861 size
= MIN (size
, 4);
11862 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
11864 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
11866 if (HARD_REGNO_MODE_OK (FP_REG_FIRST
, mode
))
11867 size
= MIN (size
, UNITS_PER_FPREG
);
11868 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
11870 if (!hard_reg_set_empty_p (left
))
11871 size
= MIN (size
, UNITS_PER_WORD
);
11872 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
11875 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11878 mips_cannot_change_mode_class (enum machine_mode from
,
11879 enum machine_mode to
,
11880 enum reg_class rclass
)
11882 /* Allow conversions between different Loongson integer vectors,
11883 and between those vectors and DImode. */
11884 if (GET_MODE_SIZE (from
) == 8 && GET_MODE_SIZE (to
) == 8
11885 && INTEGRAL_MODE_P (from
) && INTEGRAL_MODE_P (to
))
11888 /* Otherwise, there are several problems with changing the modes of
11889 values in floating-point registers:
11891 - When a multi-word value is stored in paired floating-point
11892 registers, the first register always holds the low word. We
11893 therefore can't allow FPRs to change between single-word and
11894 multi-word modes on big-endian targets.
11896 - GCC assumes that each word of a multiword register can be
11897 accessed individually using SUBREGs. This is not true for
11898 floating-point registers if they are bigger than a word.
11900 - Loading a 32-bit value into a 64-bit floating-point register
11901 will not sign-extend the value, despite what LOAD_EXTEND_OP
11902 says. We can't allow FPRs to change from SImode to a wider
11903 mode on 64-bit targets.
11905 - If the FPU has already interpreted a value in one format, we
11906 must not ask it to treat the value as having a different
11909 We therefore disallow all mode changes involving FPRs. */
11911 return reg_classes_intersect_p (FP_REGS
, rclass
);
11914 /* Implement target hook small_register_classes_for_mode_p. */
11917 mips_small_register_classes_for_mode_p (enum machine_mode mode
11920 return TARGET_MIPS16
;
11923 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11926 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode
)
11931 return TARGET_HARD_FLOAT
;
11934 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
11937 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
11944 /* Implement MODES_TIEABLE_P. */
11947 mips_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
11949 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11950 prefer to put one of them in FPRs. */
11951 return (mode1
== mode2
11952 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
11953 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
11956 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11959 mips_preferred_reload_class (rtx x
, reg_class_t rclass
)
11961 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
11964 if (reg_class_subset_p (FP_REGS
, rclass
)
11965 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
11968 if (reg_class_subset_p (GR_REGS
, rclass
))
11971 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
11977 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11978 Return a "canonical" class to represent it in later calculations. */
11981 mips_canonicalize_move_class (reg_class_t rclass
)
11983 /* All moves involving accumulator registers have the same cost. */
11984 if (reg_class_subset_p (rclass
, ACC_REGS
))
11987 /* Likewise promote subclasses of general registers to the most
11988 interesting containing class. */
11989 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
11991 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
11992 rclass
= GENERAL_REGS
;
11997 /* Return the cost of moving a value of mode MODE from a register of
11998 class FROM to a GPR. Return 0 for classes that are unions of other
11999 classes handled by this function. */
12002 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
12009 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
12013 /* MFLO and MFHI. */
12021 /* LUI followed by MOVF. */
12027 /* This choice of value is historical. */
12035 /* Return the cost of moving a value of mode MODE from a GPR to a
12036 register of class TO. Return 0 for classes that are unions of
12037 other classes handled by this function. */
12040 mips_move_from_gpr_cost (enum machine_mode mode
, reg_class_t to
)
12046 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
12050 /* MTLO and MTHI. */
12058 /* A secondary reload through an FPR scratch. */
12059 return (mips_register_move_cost (mode
, GENERAL_REGS
, FP_REGS
)
12060 + mips_register_move_cost (mode
, FP_REGS
, ST_REGS
));
12065 /* This choice of value is historical. */
12073 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
12074 maximum of the move costs for subclasses; regclass will work out
12075 the maximum for us. */
12078 mips_register_move_cost (enum machine_mode mode
,
12079 reg_class_t from
, reg_class_t to
)
12084 from
= mips_canonicalize_move_class (from
);
12085 to
= mips_canonicalize_move_class (to
);
12087 /* Handle moves that can be done without using general-purpose registers. */
12088 if (from
== FP_REGS
)
12090 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
12094 /* The sequence generated by mips_expand_fcc_reload. */
12098 /* Handle cases in which only one class deviates from the ideal. */
12099 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
12101 return mips_move_from_gpr_cost (mode
, to
);
12103 return mips_move_to_gpr_cost (mode
, from
);
12105 /* Handles cases that require a GPR temporary. */
12106 cost1
= mips_move_to_gpr_cost (mode
, from
);
12109 cost2
= mips_move_from_gpr_cost (mode
, to
);
12111 return cost1
+ cost2
;
12117 /* Implement TARGET_MEMORY_MOVE_COST. */
12120 mips_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
, bool in
)
12122 return (mips_cost
->memory_latency
12123 + memory_move_secondary_cost (mode
, rclass
, in
));
12126 /* Return the register class required for a secondary register when
12127 copying between one of the registers in RCLASS and value X, which
12128 has mode MODE. X is the source of the move if IN_P, otherwise it
12129 is the destination. Return NO_REGS if no secondary register is
12133 mips_secondary_reload_class (enum reg_class rclass
,
12134 enum machine_mode mode
, rtx x
, bool in_p
)
12138 /* If X is a constant that cannot be loaded into $25, it must be loaded
12139 into some other GPR. No other register class allows a direct move. */
12140 if (mips_dangerous_for_la25_p (x
))
12141 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
12143 regno
= true_regnum (x
);
12146 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
12147 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
12153 /* Copying from accumulator registers to anywhere other than a general
12154 register requires a temporary general register. */
12155 if (reg_class_subset_p (rclass
, ACC_REGS
))
12156 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
12157 if (ACC_REG_P (regno
))
12158 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12160 /* We can only copy a value to a condition code register from a
12161 floating-point register, and even then we require a scratch
12162 floating-point register. We can only copy a value out of a
12163 condition-code register into a general register. */
12164 if (reg_class_subset_p (rclass
, ST_REGS
))
12168 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
12170 if (ST_REG_P (regno
))
12174 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12177 if (reg_class_subset_p (rclass
, FP_REGS
))
12180 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8))
12181 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
12182 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
12185 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
12186 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
12189 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (mode
, x
))
12190 /* We can force the constant to memory and use lwc1
12191 and ldc1. As above, we will use pairs of lwc1s if
12192 ldc1 is not supported. */
12195 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
12196 /* In this case we can use mov.fmt. */
12199 /* Otherwise, we need to reload through an integer register. */
12202 if (FP_REG_P (regno
))
12203 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12208 /* Implement TARGET_MODE_REP_EXTENDED. */
12211 mips_mode_rep_extended (enum machine_mode mode
, enum machine_mode mode_rep
)
12213 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
12214 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
12215 return SIGN_EXTEND
;
12220 /* Implement TARGET_VALID_POINTER_MODE. */
12223 mips_valid_pointer_mode (enum machine_mode mode
)
12225 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
12228 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
12231 mips_vector_mode_supported_p (enum machine_mode mode
)
12236 return TARGET_PAIRED_SINGLE_FLOAT
;
12251 return TARGET_LOONGSON_VECTORS
;
12258 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
12261 mips_scalar_mode_supported_p (enum machine_mode mode
)
12263 if (ALL_FIXED_POINT_MODE_P (mode
)
12264 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
12267 return default_scalar_mode_supported_p (mode
);
12270 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
12272 static enum machine_mode
12273 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED
)
12275 if (TARGET_PAIRED_SINGLE_FLOAT
12281 /* Implement TARGET_INIT_LIBFUNCS. */
12284 mips_init_libfuncs (void)
12286 if (TARGET_FIX_VR4120
)
12288 /* Register the special divsi3 and modsi3 functions needed to work
12289 around VR4120 division errata. */
12290 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
12291 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
12294 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
12296 /* Register the MIPS16 -mhard-float stubs. */
12297 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
12298 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
12299 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
12300 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
12302 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
12303 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
12304 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
12305 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
12306 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
12307 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
12308 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
12310 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
12311 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
12312 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
12314 if (TARGET_DOUBLE_FLOAT
)
12316 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
12317 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
12318 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
12319 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
12321 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
12322 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
12323 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
12324 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
12325 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
12326 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
12327 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
12329 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
12330 "__mips16_extendsfdf2");
12331 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
12332 "__mips16_truncdfsf2");
12333 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
12334 "__mips16_fix_truncdfsi");
12335 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
12336 "__mips16_floatsidf");
12337 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
12338 "__mips16_floatunsidf");
12342 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
12343 on an external non-MIPS16 routine to implement __sync_synchronize.
12344 Similarly for the rest of the ll/sc libfuncs. */
12347 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
12348 init_sync_libfuncs (UNITS_PER_WORD
);
12352 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12355 mips_process_load_label (rtx target
)
12357 rtx base
, gp
, intop
;
12358 HOST_WIDE_INT offset
;
12360 mips_multi_start ();
12364 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target
, 0);
12365 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12369 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target
, 0);
12370 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12374 gp
= pic_offset_table_rtx
;
12375 if (mips_cfun_has_cprestore_slot_p ())
12377 gp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
12378 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
12379 if (!SMALL_OPERAND (offset
))
12381 intop
= GEN_INT (CONST_HIGH_PART (offset
));
12382 mips_multi_add_insn ("lui\t%0,%1", gp
, intop
, 0);
12383 mips_multi_add_insn ("addu\t%0,%0,%1", gp
, base
, 0);
12386 offset
= CONST_LOW_PART (offset
);
12388 intop
= GEN_INT (offset
);
12389 if (ISA_HAS_LOAD_DELAY
)
12390 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp
, intop
, base
, 0);
12392 mips_multi_add_insn ("lw\t%0,%1(%2)", gp
, intop
, base
, 0);
12394 if (ISA_HAS_LOAD_DELAY
)
12395 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target
, gp
, 0);
12397 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target
, gp
, 0);
12398 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target
, 0);
12403 /* Return the number of instructions needed to load a label into $AT. */
12405 static unsigned int
12406 mips_load_label_num_insns (void)
12408 if (cfun
->machine
->load_label_num_insns
== 0)
12410 mips_process_load_label (pc_rtx
);
12411 cfun
->machine
->load_label_num_insns
= mips_multi_num_insns
;
12413 return cfun
->machine
->load_label_num_insns
;
12416 /* Emit an asm sequence to start a noat block and load the address
12417 of a label into $1. */
12420 mips_output_load_label (rtx target
)
12422 mips_push_asm_switch (&mips_noat
);
12423 if (TARGET_EXPLICIT_RELOCS
)
12425 mips_process_load_label (target
);
12426 mips_multi_write ();
12430 if (Pmode
== DImode
)
12431 output_asm_insn ("dla\t%@,%0", &target
);
12433 output_asm_insn ("la\t%@,%0", &target
);
12437 /* Return the length of INSN. LENGTH is the initial length computed by
12438 attributes in the machine-description file. */
12441 mips_adjust_insn_length (rtx insn
, int length
)
12443 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12444 of a PIC long-branch sequence. Substitute the correct value. */
12445 if (length
== MAX_PIC_BRANCH_LENGTH
12447 && INSN_CODE (insn
) >= 0
12448 && get_attr_type (insn
) == TYPE_BRANCH
)
12450 /* Add the branch-over instruction and its delay slot, if this
12451 is a conditional branch. */
12452 length
= simplejump_p (insn
) ? 0 : 8;
12454 /* Add the size of a load into $AT. */
12455 length
+= BASE_INSN_LENGTH
* mips_load_label_num_insns ();
12457 /* Add the length of an indirect jump, ignoring the delay slot. */
12458 length
+= TARGET_COMPRESSION
? 2 : 4;
12461 /* A unconditional jump has an unfilled delay slot if it is not part
12462 of a sequence. A conditional jump normally has a delay slot, but
12463 does not on MIPS16. */
12464 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
12465 length
+= TARGET_MIPS16
? 2 : 4;
12467 /* See how many nops might be needed to avoid hardware hazards. */
12468 if (!cfun
->machine
->ignore_hazard_length_p
12470 && INSN_CODE (insn
) >= 0)
12471 switch (get_attr_hazard (insn
))
12477 length
+= NOP_INSN_LENGTH
;
12481 length
+= NOP_INSN_LENGTH
* 2;
12488 /* Return the assembly code for INSN, which has the operands given by
12489 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12490 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12491 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12492 version of BRANCH_IF_TRUE. */
12495 mips_output_conditional_branch (rtx insn
, rtx
*operands
,
12496 const char *branch_if_true
,
12497 const char *branch_if_false
)
12499 unsigned int length
;
12500 rtx taken
, not_taken
;
12502 gcc_assert (LABEL_P (operands
[0]));
12504 length
= get_attr_length (insn
);
12507 /* Just a simple conditional branch. */
12508 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
12509 return branch_if_true
;
12512 /* Generate a reversed branch around a direct jump. This fallback does
12513 not use branch-likely instructions. */
12514 mips_branch_likely
= false;
12515 not_taken
= gen_label_rtx ();
12516 taken
= operands
[0];
12518 /* Generate the reversed branch to NOT_TAKEN. */
12519 operands
[0] = not_taken
;
12520 output_asm_insn (branch_if_false
, operands
);
12522 /* If INSN has a delay slot, we must provide delay slots for both the
12523 branch to NOT_TAKEN and the conditional jump. We must also ensure
12524 that INSN's delay slot is executed in the appropriate cases. */
12525 if (final_sequence
)
12527 /* This first delay slot will always be executed, so use INSN's
12528 delay slot if is not annulled. */
12529 if (!INSN_ANNULLED_BRANCH_P (insn
))
12531 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
12532 asm_out_file
, optimize
, 1, NULL
);
12533 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
12536 output_asm_insn ("nop", 0);
12537 fprintf (asm_out_file
, "\n");
12540 /* Output the unconditional branch to TAKEN. */
12541 if (TARGET_ABSOLUTE_JUMPS
)
12542 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken
);
12545 mips_output_load_label (taken
);
12546 output_asm_insn ("jr\t%@%]%/", 0);
12549 /* Now deal with its delay slot; see above. */
12550 if (final_sequence
)
12552 /* This delay slot will only be executed if the branch is taken.
12553 Use INSN's delay slot if is annulled. */
12554 if (INSN_ANNULLED_BRANCH_P (insn
))
12556 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
12557 asm_out_file
, optimize
, 1, NULL
);
12558 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
12561 output_asm_insn ("nop", 0);
12562 fprintf (asm_out_file
, "\n");
12565 /* Output NOT_TAKEN. */
12566 targetm
.asm_out
.internal_label (asm_out_file
, "L",
12567 CODE_LABEL_NUMBER (not_taken
));
12571 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12572 if some ordering condition is true. The condition is given by
12573 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12574 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12575 its second is always zero. */
12578 mips_output_order_conditional_branch (rtx insn
, rtx
*operands
, bool inverted_p
)
12580 const char *branch
[2];
12582 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12583 Make BRANCH[0] branch on the inverse condition. */
12584 switch (GET_CODE (operands
[1]))
12586 /* These cases are equivalent to comparisons against zero. */
12588 inverted_p
= !inverted_p
;
12589 /* Fall through. */
12591 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%0");
12592 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%0");
12595 /* These cases are always true or always false. */
12597 inverted_p
= !inverted_p
;
12598 /* Fall through. */
12600 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%0");
12601 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%0");
12605 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1z", "%2,%0");
12606 branch
[inverted_p
] = MIPS_BRANCH ("b%N1z", "%2,%0");
12609 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
12612 /* Start a block of code that needs access to the LL, SC and SYNC
12616 mips_start_ll_sc_sync_block (void)
12618 if (!ISA_HAS_LL_SC
)
12620 output_asm_insn (".set\tpush", 0);
12622 output_asm_insn (".set\tmips3", 0);
12624 output_asm_insn (".set\tmips2", 0);
12628 /* End a block started by mips_start_ll_sc_sync_block. */
12631 mips_end_ll_sc_sync_block (void)
12633 if (!ISA_HAS_LL_SC
)
12634 output_asm_insn (".set\tpop", 0);
12637 /* Output and/or return the asm template for a sync instruction. */
12640 mips_output_sync (void)
12642 mips_start_ll_sc_sync_block ();
12643 output_asm_insn ("sync", 0);
12644 mips_end_ll_sc_sync_block ();
12648 /* Return the asm template associated with sync_insn1 value TYPE.
12649 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12651 static const char *
12652 mips_sync_insn1_template (enum attr_sync_insn1 type
, bool is_64bit_p
)
12656 case SYNC_INSN1_MOVE
:
12657 return "move\t%0,%z2";
12658 case SYNC_INSN1_LI
:
12659 return "li\t%0,%2";
12660 case SYNC_INSN1_ADDU
:
12661 return is_64bit_p
? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12662 case SYNC_INSN1_ADDIU
:
12663 return is_64bit_p
? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12664 case SYNC_INSN1_SUBU
:
12665 return is_64bit_p
? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12666 case SYNC_INSN1_AND
:
12667 return "and\t%0,%1,%z2";
12668 case SYNC_INSN1_ANDI
:
12669 return "andi\t%0,%1,%2";
12670 case SYNC_INSN1_OR
:
12671 return "or\t%0,%1,%z2";
12672 case SYNC_INSN1_ORI
:
12673 return "ori\t%0,%1,%2";
12674 case SYNC_INSN1_XOR
:
12675 return "xor\t%0,%1,%z2";
12676 case SYNC_INSN1_XORI
:
12677 return "xori\t%0,%1,%2";
12679 gcc_unreachable ();
12682 /* Return the asm template associated with sync_insn2 value TYPE. */
12684 static const char *
12685 mips_sync_insn2_template (enum attr_sync_insn2 type
)
12689 case SYNC_INSN2_NOP
:
12690 gcc_unreachable ();
12691 case SYNC_INSN2_AND
:
12692 return "and\t%0,%1,%z2";
12693 case SYNC_INSN2_XOR
:
12694 return "xor\t%0,%1,%z2";
12695 case SYNC_INSN2_NOT
:
12696 return "nor\t%0,%1,%.";
12698 gcc_unreachable ();
12701 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12702 the value of the one of the sync_* attributes. Return the operand
12703 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12704 have the associated attribute. */
12707 mips_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
12710 default_value
= operands
[index
- 1];
12711 return default_value
;
12714 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12715 sequence for it. */
12718 mips_process_sync_loop (rtx insn
, rtx
*operands
)
12720 rtx at
, mem
, oldval
, newval
, inclusive_mask
, exclusive_mask
;
12721 rtx required_oldval
, insn1_op2
, tmp1
, tmp2
, tmp3
, cmp
;
12722 unsigned int tmp3_insn
;
12723 enum attr_sync_insn1 insn1
;
12724 enum attr_sync_insn2 insn2
;
12727 enum memmodel model
;
12729 /* Read an operand from the sync_WHAT attribute and store it in
12730 variable WHAT. DEFAULT is the default value if no attribute
12732 #define READ_OPERAND(WHAT, DEFAULT) \
12733 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12736 /* Read the memory. */
12737 READ_OPERAND (mem
, 0);
12739 is_64bit_p
= (GET_MODE_BITSIZE (GET_MODE (mem
)) == 64);
12741 /* Read the other attributes. */
12742 at
= gen_rtx_REG (GET_MODE (mem
), AT_REGNUM
);
12743 READ_OPERAND (oldval
, at
);
12744 READ_OPERAND (cmp
, 0);
12745 READ_OPERAND (newval
, at
);
12746 READ_OPERAND (inclusive_mask
, 0);
12747 READ_OPERAND (exclusive_mask
, 0);
12748 READ_OPERAND (required_oldval
, 0);
12749 READ_OPERAND (insn1_op2
, 0);
12750 insn1
= get_attr_sync_insn1 (insn
);
12751 insn2
= get_attr_sync_insn2 (insn
);
12753 /* Don't bother setting CMP result that is never used. */
12754 if (cmp
&& find_reg_note (insn
, REG_UNUSED
, cmp
))
12757 memmodel_attr
= get_attr_sync_memmodel (insn
);
12758 switch (memmodel_attr
)
12761 model
= MEMMODEL_ACQ_REL
;
12764 model
= MEMMODEL_ACQUIRE
;
12767 model
= (enum memmodel
) INTVAL (operands
[memmodel_attr
]);
12770 mips_multi_start ();
12772 /* Output the release side of the memory barrier. */
12773 if (need_atomic_barrier_p (model
, true))
12775 if (required_oldval
== 0 && TARGET_OCTEON
)
12777 /* Octeon doesn't reorder reads, so a full barrier can be
12778 created by using SYNCW to order writes combined with the
12779 write from the following SC. When the SC successfully
12780 completes, we know that all preceding writes are also
12781 committed to the coherent memory system. It is possible
12782 for a single SYNCW to fail, but a pair of them will never
12783 fail, so we use two. */
12784 mips_multi_add_insn ("syncw", NULL
);
12785 mips_multi_add_insn ("syncw", NULL
);
12788 mips_multi_add_insn ("sync", NULL
);
12791 /* Output the branch-back label. */
12792 mips_multi_add_label ("1:");
12794 /* OLDVAL = *MEM. */
12795 mips_multi_add_insn (is_64bit_p
? "lld\t%0,%1" : "ll\t%0,%1",
12796 oldval
, mem
, NULL
);
12798 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12799 if (required_oldval
)
12801 if (inclusive_mask
== 0)
12805 gcc_assert (oldval
!= at
);
12806 mips_multi_add_insn ("and\t%0,%1,%2",
12807 at
, oldval
, inclusive_mask
, NULL
);
12810 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1
, required_oldval
, NULL
);
12812 /* CMP = 0 [delay slot]. */
12814 mips_multi_add_insn ("li\t%0,0", cmp
, NULL
);
12817 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12818 if (exclusive_mask
== 0)
12822 gcc_assert (oldval
!= at
);
12823 mips_multi_add_insn ("and\t%0,%1,%z2",
12824 at
, oldval
, exclusive_mask
, NULL
);
12828 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12830 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12831 at least one instruction in that case. */
12832 if (insn1
== SYNC_INSN1_MOVE
12833 && (tmp1
!= const0_rtx
|| insn2
!= SYNC_INSN2_NOP
))
12837 mips_multi_add_insn (mips_sync_insn1_template (insn1
, is_64bit_p
),
12838 newval
, oldval
, insn1_op2
, NULL
);
12842 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12843 if (insn2
== SYNC_INSN2_NOP
)
12847 mips_multi_add_insn (mips_sync_insn2_template (insn2
),
12848 newval
, tmp2
, inclusive_mask
, NULL
);
12851 tmp3_insn
= mips_multi_last_index ();
12853 /* $AT = $TMP1 | $TMP3. */
12854 if (tmp1
== const0_rtx
|| tmp3
== const0_rtx
)
12856 mips_multi_set_operand (tmp3_insn
, 0, at
);
12861 gcc_assert (tmp1
!= tmp3
);
12862 mips_multi_add_insn ("or\t%0,%1,%2", at
, tmp1
, tmp3
, NULL
);
12865 /* if (!commit (*MEM = $AT)) goto 1.
12867 This will sometimes be a delayed branch; see the write code below
12869 mips_multi_add_insn (is_64bit_p
? "scd\t%0,%1" : "sc\t%0,%1", at
, mem
, NULL
);
12870 mips_multi_add_insn ("beq%?\t%0,%.,1b", at
, NULL
);
12872 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12873 if (insn1
!= SYNC_INSN1_MOVE
&& insn1
!= SYNC_INSN1_LI
&& tmp3
!= newval
)
12875 mips_multi_copy_insn (tmp3_insn
);
12876 mips_multi_set_operand (mips_multi_last_index (), 0, newval
);
12878 else if (!(required_oldval
&& cmp
))
12879 mips_multi_add_insn ("nop", NULL
);
12881 /* CMP = 1 -- either standalone or in a delay slot. */
12882 if (required_oldval
&& cmp
)
12883 mips_multi_add_insn ("li\t%0,1", cmp
, NULL
);
12885 /* Output the acquire side of the memory barrier. */
12886 if (TARGET_SYNC_AFTER_SC
&& need_atomic_barrier_p (model
, false))
12887 mips_multi_add_insn ("sync", NULL
);
12889 /* Output the exit label, if needed. */
12890 if (required_oldval
)
12891 mips_multi_add_label ("2:");
12893 #undef READ_OPERAND
12896 /* Output and/or return the asm template for sync loop INSN, which has
12897 the operands given by OPERANDS. */
12900 mips_output_sync_loop (rtx insn
, rtx
*operands
)
12902 mips_process_sync_loop (insn
, operands
);
12904 /* Use branch-likely instructions to work around the LL/SC R10000
12906 mips_branch_likely
= TARGET_FIX_R10000
;
12908 mips_push_asm_switch (&mips_noreorder
);
12909 mips_push_asm_switch (&mips_nomacro
);
12910 mips_push_asm_switch (&mips_noat
);
12911 mips_start_ll_sc_sync_block ();
12913 mips_multi_write ();
12915 mips_end_ll_sc_sync_block ();
12916 mips_pop_asm_switch (&mips_noat
);
12917 mips_pop_asm_switch (&mips_nomacro
);
12918 mips_pop_asm_switch (&mips_noreorder
);
12923 /* Return the number of individual instructions in sync loop INSN,
12924 which has the operands given by OPERANDS. */
12927 mips_sync_loop_insns (rtx insn
, rtx
*operands
)
12929 mips_process_sync_loop (insn
, operands
);
12930 return mips_multi_num_insns
;
12933 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12934 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12936 When working around R4000 and R4400 errata, we need to make sure that
12937 the division is not immediately followed by a shift[1][2]. We also
12938 need to stop the division from being put into a branch delay slot[3].
12939 The easiest way to avoid both problems is to add a nop after the
12940 division. When a divide-by-zero check is needed, this nop can be
12941 used to fill the branch delay slot.
12943 [1] If a double-word or a variable shift executes immediately
12944 after starting an integer division, the shift may give an
12945 incorrect result. See quotations of errata #16 and #28 from
12946 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12947 in mips.md for details.
12949 [2] A similar bug to [1] exists for all revisions of the
12950 R4000 and the R4400 when run in an MC configuration.
12951 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12953 "19. In this following sequence:
12955 ddiv (or ddivu or div or divu)
12956 dsll32 (or dsrl32, dsra32)
12958 if an MPT stall occurs, while the divide is slipping the cpu
12959 pipeline, then the following double shift would end up with an
12962 Workaround: The compiler needs to avoid generating any
12963 sequence with divide followed by extended double shift."
12965 This erratum is also present in "MIPS R4400MC Errata, Processor
12966 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12967 & 3.0" as errata #10 and #4, respectively.
12969 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12970 (also valid for MIPS R4000MC processors):
12972 "52. R4000SC: This bug does not apply for the R4000PC.
12974 There are two flavors of this bug:
12976 1) If the instruction just after divide takes an RF exception
12977 (tlb-refill, tlb-invalid) and gets an instruction cache
12978 miss (both primary and secondary) and the line which is
12979 currently in secondary cache at this index had the first
12980 data word, where the bits 5..2 are set, then R4000 would
12981 get a wrong result for the div.
12986 ------------------- # end-of page. -tlb-refill
12991 ------------------- # end-of page. -tlb-invalid
12994 2) If the divide is in the taken branch delay slot, where the
12995 target takes RF exception and gets an I-cache miss for the
12996 exception vector or where I-cache miss occurs for the
12997 target address, under the above mentioned scenarios, the
12998 div would get wrong results.
13001 j r2 # to next page mapped or unmapped
13002 div r8,r9 # this bug would be there as long
13003 # as there is an ICache miss and
13004 nop # the "data pattern" is present
13007 beq r0, r0, NextPage # to Next page
13011 This bug is present for div, divu, ddiv, and ddivu
13014 Workaround: For item 1), OS could make sure that the next page
13015 after the divide instruction is also mapped. For item 2), the
13016 compiler could make sure that the divide instruction is not in
13017 the branch delay slot."
13019 These processors have PRId values of 0x00004220 and 0x00004300 for
13020 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
13023 mips_output_division (const char *division
, rtx
*operands
)
13028 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
13030 output_asm_insn (s
, operands
);
13033 if (TARGET_CHECK_ZERO_DIV
)
13037 output_asm_insn (s
, operands
);
13038 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
13040 else if (GENERATE_DIVIDE_TRAPS
)
13042 /* Avoid long replay penalty on load miss by putting the trap before
13045 output_asm_insn ("teq\t%2,%.,7", operands
);
13048 output_asm_insn (s
, operands
);
13049 s
= "teq\t%2,%.,7";
13054 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
13055 output_asm_insn (s
, operands
);
13056 s
= "break\t7%)\n1:";
13062 /* Return true if IN_INSN is a multiply-add or multiply-subtract
13063 instruction and if OUT_INSN assigns to the accumulator operand. */
13066 mips_linked_madd_p (rtx out_insn
, rtx in_insn
)
13068 enum attr_accum_in accum_in
;
13069 int accum_in_opnum
;
13072 if (recog_memoized (in_insn
) < 0)
13075 accum_in
= get_attr_accum_in (in_insn
);
13076 if (accum_in
== ACCUM_IN_NONE
)
13079 accum_in_opnum
= accum_in
- ACCUM_IN_0
;
13081 extract_insn (in_insn
);
13082 gcc_assert (accum_in_opnum
< recog_data
.n_operands
);
13083 accum_in_op
= recog_data
.operand
[accum_in_opnum
];
13085 return reg_set_p (accum_in_op
, out_insn
);
13088 /* True if the dependency between OUT_INSN and IN_INSN is on the store
13089 data rather than the address. We need this because the cprestore
13090 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
13091 which causes the default routine to abort. We just return false
13095 mips_store_data_bypass_p (rtx out_insn
, rtx in_insn
)
13097 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
13100 return !store_data_bypass_p (out_insn
, in_insn
);
13104 /* Variables and flags used in scheduler hooks when tuning for
13108 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
13111 /* If true, then next ALU1/2 instruction will go to ALU1. */
13114 /* If true, then next FALU1/2 unstruction will go to FALU1. */
13117 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
13118 int alu1_core_unit_code
;
13119 int alu2_core_unit_code
;
13120 int falu1_core_unit_code
;
13121 int falu2_core_unit_code
;
13123 /* True if current cycle has a multi instruction.
13124 This flag is used in mips_ls2_dfa_post_advance_cycle. */
13125 bool cycle_has_multi_p
;
13127 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
13128 These are used in mips_ls2_dfa_post_advance_cycle to initialize
13130 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
13131 instruction to go ALU1. */
13132 rtx alu1_turn_enabled_insn
;
13133 rtx alu2_turn_enabled_insn
;
13134 rtx falu1_turn_enabled_insn
;
13135 rtx falu2_turn_enabled_insn
;
13138 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
13139 dependencies have no cost, except on the 20Kc where output-dependence
13140 is treated like input-dependence. */
13143 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED
, rtx link
,
13144 rtx dep ATTRIBUTE_UNUSED
, int cost
)
13146 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
13149 if (REG_NOTE_KIND (link
) != 0)
13154 /* Return the number of instructions that can be issued per cycle. */
13157 mips_issue_rate (void)
13161 case PROCESSOR_74KC
:
13162 case PROCESSOR_74KF2_1
:
13163 case PROCESSOR_74KF1_1
:
13164 case PROCESSOR_74KF3_2
:
13165 /* The 74k is not strictly quad-issue cpu, but can be seen as one
13166 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
13167 but in reality only a maximum of 3 insns can be issued as
13168 floating-point loads and stores also require a slot in the
13170 case PROCESSOR_R10000
:
13171 /* All R10K Processors are quad-issue (being the first MIPS
13172 processors to support this feature). */
13175 case PROCESSOR_20KC
:
13176 case PROCESSOR_R4130
:
13177 case PROCESSOR_R5400
:
13178 case PROCESSOR_R5500
:
13179 case PROCESSOR_R5900
:
13180 case PROCESSOR_R7000
:
13181 case PROCESSOR_R9000
:
13182 case PROCESSOR_OCTEON
:
13183 case PROCESSOR_OCTEON2
:
13186 case PROCESSOR_SB1
:
13187 case PROCESSOR_SB1A
:
13188 /* This is actually 4, but we get better performance if we claim 3.
13189 This is partly because of unwanted speculative code motion with the
13190 larger number, and partly because in most common cases we can't
13191 reach the theoretical max of 4. */
13194 case PROCESSOR_LOONGSON_2E
:
13195 case PROCESSOR_LOONGSON_2F
:
13196 case PROCESSOR_LOONGSON_3A
:
13199 case PROCESSOR_XLP
:
13200 return (reload_completed
? 4 : 3);
13207 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
13210 mips_ls2_init_dfa_post_cycle_insn (void)
13213 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
13214 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
13218 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
13219 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
13223 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
13224 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
13228 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
13229 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
13232 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
13233 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
13234 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
13235 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
13238 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
13239 Init data used in mips_dfa_post_advance_cycle. */
13242 mips_init_dfa_post_cycle_insn (void)
13244 if (TUNE_LOONGSON_2EF
)
13245 mips_ls2_init_dfa_post_cycle_insn ();
13248 /* Initialize STATE when scheduling for Loongson 2E/2F.
13249 Support round-robin dispatch scheme by enabling only one of
13250 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
13254 mips_ls2_dfa_post_advance_cycle (state_t state
)
13256 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
13258 /* Though there are no non-pipelined ALU1 insns,
13259 we can get an instruction of type 'multi' before reload. */
13260 gcc_assert (mips_ls2
.cycle_has_multi_p
);
13261 mips_ls2
.alu1_turn_p
= false;
13264 mips_ls2
.cycle_has_multi_p
= false;
13266 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
13267 /* We have a non-pipelined alu instruction in the core,
13268 adjust round-robin counter. */
13269 mips_ls2
.alu1_turn_p
= true;
13271 if (mips_ls2
.alu1_turn_p
)
13273 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
13274 gcc_unreachable ();
13278 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
13279 gcc_unreachable ();
13282 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
13284 /* There are no non-pipelined FALU1 insns. */
13285 gcc_unreachable ();
13286 mips_ls2
.falu1_turn_p
= false;
13289 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
13290 /* We have a non-pipelined falu instruction in the core,
13291 adjust round-robin counter. */
13292 mips_ls2
.falu1_turn_p
= true;
13294 if (mips_ls2
.falu1_turn_p
)
13296 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
13297 gcc_unreachable ();
13301 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
13302 gcc_unreachable ();
13306 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
13307 This hook is being called at the start of each cycle. */
13310 mips_dfa_post_advance_cycle (void)
13312 if (TUNE_LOONGSON_2EF
)
13313 mips_ls2_dfa_post_advance_cycle (curr_state
);
13316 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
13317 be as wide as the scheduling freedom in the DFA. */
13320 mips_multipass_dfa_lookahead (void)
13322 /* Can schedule up to 4 of the 6 function units in any one cycle. */
13326 if (TUNE_LOONGSON_2EF
|| TUNE_LOONGSON_3A
)
13335 /* Remove the instruction at index LOWER from ready queue READY and
13336 reinsert it in front of the instruction at index HIGHER. LOWER must
13340 mips_promote_ready (rtx
*ready
, int lower
, int higher
)
13345 new_head
= ready
[lower
];
13346 for (i
= lower
; i
< higher
; i
++)
13347 ready
[i
] = ready
[i
+ 1];
13348 ready
[i
] = new_head
;
13351 /* If the priority of the instruction at POS2 in the ready queue READY
13352 is within LIMIT units of that of the instruction at POS1, swap the
13353 instructions if POS2 is not already less than POS1. */
13356 mips_maybe_swap_ready (rtx
*ready
, int pos1
, int pos2
, int limit
)
13359 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
13363 temp
= ready
[pos1
];
13364 ready
[pos1
] = ready
[pos2
];
13365 ready
[pos2
] = temp
;
13369 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
13370 that may clobber hi or lo. */
13371 static rtx mips_macc_chains_last_hilo
;
13373 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
13374 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
13377 mips_macc_chains_record (rtx insn
)
13379 if (get_attr_may_clobber_hilo (insn
))
13380 mips_macc_chains_last_hilo
= insn
;
13383 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13384 has NREADY elements, looking for a multiply-add or multiply-subtract
13385 instruction that is cumulative with mips_macc_chains_last_hilo.
13386 If there is one, promote it ahead of anything else that might
13387 clobber hi or lo. */
13390 mips_macc_chains_reorder (rtx
*ready
, int nready
)
13394 if (mips_macc_chains_last_hilo
!= 0)
13395 for (i
= nready
- 1; i
>= 0; i
--)
13396 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
13398 for (j
= nready
- 1; j
> i
; j
--)
13399 if (recog_memoized (ready
[j
]) >= 0
13400 && get_attr_may_clobber_hilo (ready
[j
]))
13402 mips_promote_ready (ready
, i
, j
);
13409 /* The last instruction to be scheduled. */
13410 static rtx vr4130_last_insn
;
13412 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13413 points to an rtx that is initially an instruction. Nullify the rtx
13414 if the instruction uses the value of register X. */
13417 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
13422 insn_ptr
= (rtx
*) data
;
13425 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
13429 /* Return true if there is true register dependence between vr4130_last_insn
13433 vr4130_true_reg_dependence_p (rtx insn
)
13435 note_stores (PATTERN (vr4130_last_insn
),
13436 vr4130_true_reg_dependence_p_1
, &insn
);
13440 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13441 the ready queue and that INSN2 is the instruction after it, return
13442 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13443 in which INSN1 and INSN2 can probably issue in parallel, but for
13444 which (INSN2, INSN1) should be less sensitive to instruction
13445 alignment than (INSN1, INSN2). See 4130.md for more details. */
13448 vr4130_swap_insns_p (rtx insn1
, rtx insn2
)
13450 sd_iterator_def sd_it
;
13453 /* Check for the following case:
13455 1) there is some other instruction X with an anti dependence on INSN1;
13456 2) X has a higher priority than INSN2; and
13457 3) X is an arithmetic instruction (and thus has no unit restrictions).
13459 If INSN1 is the last instruction blocking X, it would better to
13460 choose (INSN1, X) over (INSN2, INSN1). */
13461 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
13462 if (DEP_TYPE (dep
) == REG_DEP_ANTI
13463 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
13464 && recog_memoized (DEP_CON (dep
)) >= 0
13465 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
13468 if (vr4130_last_insn
!= 0
13469 && recog_memoized (insn1
) >= 0
13470 && recog_memoized (insn2
) >= 0)
13472 /* See whether INSN1 and INSN2 use different execution units,
13473 or if they are both ALU-type instructions. If so, they can
13474 probably execute in parallel. */
13475 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
13476 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
13477 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
13479 /* If only one of the instructions has a dependence on
13480 vr4130_last_insn, prefer to schedule the other one first. */
13481 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
13482 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
13483 if (dep1_p
!= dep2_p
)
13486 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13487 is not an ALU-type instruction and if INSN1 uses the same
13488 execution unit. (Note that if this condition holds, we already
13489 know that INSN2 uses a different execution unit.) */
13490 if (class1
!= VR4130_CLASS_ALU
13491 && recog_memoized (vr4130_last_insn
) >= 0
13492 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
13499 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13500 queue with at least two instructions. Swap the first two if
13501 vr4130_swap_insns_p says that it could be worthwhile. */
13504 vr4130_reorder (rtx
*ready
, int nready
)
13506 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
13507 mips_promote_ready (ready
, nready
- 2, nready
- 1);
13510 /* Record whether last 74k AGEN instruction was a load or store. */
13511 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13513 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13514 resets to TYPE_UNKNOWN state. */
13517 mips_74k_agen_init (rtx insn
)
13519 if (!insn
|| CALL_P (insn
) || JUMP_P (insn
))
13520 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13523 enum attr_type type
= get_attr_type (insn
);
13524 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
13525 mips_last_74k_agen_insn
= type
;
13529 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13530 loads to be grouped together, and multiple stores to be grouped
13531 together. Swap things around in the ready queue to make this happen. */
13534 mips_74k_agen_reorder (rtx
*ready
, int nready
)
13537 int store_pos
, load_pos
;
13542 for (i
= nready
- 1; i
>= 0; i
--)
13544 rtx insn
= ready
[i
];
13545 if (USEFUL_INSN_P (insn
))
13546 switch (get_attr_type (insn
))
13549 if (store_pos
== -1)
13554 if (load_pos
== -1)
13563 if (load_pos
== -1 || store_pos
== -1)
13566 switch (mips_last_74k_agen_insn
)
13569 /* Prefer to schedule loads since they have a higher latency. */
13571 /* Swap loads to the front of the queue. */
13572 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
13575 /* Swap stores to the front of the queue. */
13576 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
13583 /* Implement TARGET_SCHED_INIT. */
13586 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13587 int max_ready ATTRIBUTE_UNUSED
)
13589 mips_macc_chains_last_hilo
= 0;
13590 vr4130_last_insn
= 0;
13591 mips_74k_agen_init (NULL_RTX
);
13593 /* When scheduling for Loongson2, branch instructions go to ALU1,
13594 therefore basic block is most likely to start with round-robin counter
13595 pointed to ALU2. */
13596 mips_ls2
.alu1_turn_p
= false;
13597 mips_ls2
.falu1_turn_p
= true;
13600 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13603 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13604 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13606 if (!reload_completed
13607 && TUNE_MACC_CHAINS
13609 mips_macc_chains_reorder (ready
, *nreadyp
);
13611 if (reload_completed
13613 && !TARGET_VR4130_ALIGN
13615 vr4130_reorder (ready
, *nreadyp
);
13618 mips_74k_agen_reorder (ready
, *nreadyp
);
13621 /* Implement TARGET_SCHED_REORDER. */
13624 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13625 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13627 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13628 return mips_issue_rate ();
13631 /* Implement TARGET_SCHED_REORDER2. */
13634 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13635 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13637 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13638 return cached_can_issue_more
;
13641 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13644 mips_ls2_variable_issue (rtx insn
)
13646 if (mips_ls2
.alu1_turn_p
)
13648 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
13649 mips_ls2
.alu1_turn_p
= false;
13653 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
13654 mips_ls2
.alu1_turn_p
= true;
13657 if (mips_ls2
.falu1_turn_p
)
13659 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
13660 mips_ls2
.falu1_turn_p
= false;
13664 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
13665 mips_ls2
.falu1_turn_p
= true;
13668 if (recog_memoized (insn
) >= 0)
13669 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
13672 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13675 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13676 rtx insn
, int more
)
13678 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13679 if (USEFUL_INSN_P (insn
))
13681 if (get_attr_type (insn
) != TYPE_GHOST
)
13683 if (!reload_completed
&& TUNE_MACC_CHAINS
)
13684 mips_macc_chains_record (insn
);
13685 vr4130_last_insn
= insn
;
13687 mips_74k_agen_init (insn
);
13688 else if (TUNE_LOONGSON_2EF
)
13689 mips_ls2_variable_issue (insn
);
13692 /* Instructions of type 'multi' should all be split before
13693 the second scheduling pass. */
13694 gcc_assert (!reload_completed
13695 || recog_memoized (insn
) < 0
13696 || get_attr_type (insn
) != TYPE_MULTI
);
13698 cached_can_issue_more
= more
;
13702 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13703 return the first operand of the associated PREF or PREFX insn. */
13706 mips_prefetch_cookie (rtx write
, rtx locality
)
13708 /* store_streamed / load_streamed. */
13709 if (INTVAL (locality
) <= 0)
13710 return GEN_INT (INTVAL (write
) + 4);
13712 /* store / load. */
13713 if (INTVAL (locality
) <= 2)
13716 /* store_retained / load_retained. */
13717 return GEN_INT (INTVAL (write
) + 6);
13720 /* Flags that indicate when a built-in function is available.
13722 BUILTIN_AVAIL_NON_MIPS16
13723 The function is available on the current target if !TARGET_MIPS16.
13725 BUILTIN_AVAIL_MIPS16
13726 The function is available on the current target if TARGET_MIPS16. */
13727 #define BUILTIN_AVAIL_NON_MIPS16 1
13728 #define BUILTIN_AVAIL_MIPS16 2
13730 /* Declare an availability predicate for built-in functions that
13731 require non-MIPS16 mode and also require COND to be true.
13732 NAME is the main part of the predicate's name. */
13733 #define AVAIL_NON_MIPS16(NAME, COND) \
13734 static unsigned int \
13735 mips_builtin_avail_##NAME (void) \
13737 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13740 /* Declare an availability predicate for built-in functions that
13741 support both MIPS16 and non-MIPS16 code and also require COND
13742 to be true. NAME is the main part of the predicate's name. */
13743 #define AVAIL_ALL(NAME, COND) \
13744 static unsigned int \
13745 mips_builtin_avail_##NAME (void) \
13747 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16 : 0; \
13750 /* This structure describes a single built-in function. */
13751 struct mips_builtin_description
{
13752 /* The code of the main .md file instruction. See mips_builtin_type
13753 for more information. */
13754 enum insn_code icode
;
13756 /* The floating-point comparison code to use with ICODE, if any. */
13757 enum mips_fp_condition cond
;
13759 /* The name of the built-in function. */
13762 /* Specifies how the function should be expanded. */
13763 enum mips_builtin_type builtin_type
;
13765 /* The function's prototype. */
13766 enum mips_function_type function_type
;
13768 /* Whether the function is available. */
13769 unsigned int (*avail
) (void);
13772 AVAIL_ALL (hard_float
, TARGET_HARD_FLOAT_ABI
)
13773 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
13774 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
13775 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
13776 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
13777 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
13778 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
13779 AVAIL_NON_MIPS16 (dsp_64
, TARGET_64BIT
&& TARGET_DSP
)
13780 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
13781 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_VECTORS
)
13782 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
13784 /* Construct a mips_builtin_description from the given arguments.
13786 INSN is the name of the associated instruction pattern, without the
13787 leading CODE_FOR_mips_.
13789 CODE is the floating-point condition code associated with the
13790 function. It can be 'f' if the field is not applicable.
13792 NAME is the name of the function itself, without the leading
13795 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13797 AVAIL is the name of the availability predicate, without the leading
13798 mips_builtin_avail_. */
13799 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13800 FUNCTION_TYPE, AVAIL) \
13801 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13802 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13803 mips_builtin_avail_ ## AVAIL }
13805 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13806 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13807 are as for MIPS_BUILTIN. */
13808 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13809 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13811 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13812 are subject to mips_builtin_avail_<AVAIL>. */
13813 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13814 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13815 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13816 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13817 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13819 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13820 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13821 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13822 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13823 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13824 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13826 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13827 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13829 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13830 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13832 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13833 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13836 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13837 are subject to mips_builtin_avail_mips3d. */
13838 #define CMP_4S_BUILTINS(INSN, COND) \
13839 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13840 MIPS_BUILTIN_CMP_ANY, \
13841 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13842 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13843 MIPS_BUILTIN_CMP_ALL, \
13844 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13846 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13847 instruction requires mips_builtin_avail_<AVAIL>. */
13848 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13849 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13850 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13852 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13853 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13856 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13857 #define CMP_BUILTINS(COND) \
13858 MOVTF_BUILTINS (c, COND, paired_single), \
13859 MOVTF_BUILTINS (cabs, COND, mips3d), \
13860 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13861 CMP_PS_BUILTINS (c, COND, paired_single), \
13862 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13863 CMP_4S_BUILTINS (c, COND), \
13864 CMP_4S_BUILTINS (cabs, COND)
13866 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13867 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13868 and AVAIL are as for MIPS_BUILTIN. */
13869 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13870 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13871 FUNCTION_TYPE, AVAIL)
13873 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13874 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13875 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13876 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13877 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13879 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13880 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13881 builtin_description field. */
13882 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13883 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13884 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13885 FUNCTION_TYPE, mips_builtin_avail_loongson }
13887 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13888 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13889 builtin_description field. */
13890 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13891 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13893 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13894 We use functions of this form when the same insn can be usefully applied
13895 to more than one datatype. */
13896 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13897 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13899 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13900 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13901 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13902 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13903 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13904 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13905 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13906 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13908 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13909 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13910 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13911 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13912 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13913 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13914 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13915 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13916 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13917 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13918 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13919 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13920 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13921 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13922 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13923 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13924 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13925 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13926 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13927 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13928 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13929 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13930 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13931 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13932 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13933 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13934 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13935 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13936 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13937 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13939 static const struct mips_builtin_description mips_builtins
[] = {
13940 #define MIPS_GET_FCSR 0
13941 DIRECT_BUILTIN (get_fcsr
, MIPS_USI_FTYPE_VOID
, hard_float
),
13942 #define MIPS_SET_FCSR 1
13943 DIRECT_NO_TARGET_BUILTIN (set_fcsr
, MIPS_VOID_FTYPE_USI
, hard_float
),
13945 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13946 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13947 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13948 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13949 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
13950 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
13951 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
13952 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
13954 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
13955 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13956 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13957 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13958 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13960 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
13961 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
13962 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13963 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
13964 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
13965 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13967 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
13968 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
13969 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13970 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
13971 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
13972 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13974 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
13976 /* Built-in functions for the SB-1 processor. */
13977 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
13979 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13980 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13981 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13982 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13983 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13984 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13985 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13986 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13987 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13988 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13989 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13990 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13991 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13992 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13993 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
13994 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
13995 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
13996 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
13997 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
13998 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
13999 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
14000 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
14001 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
14002 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14003 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14004 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14005 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14006 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14007 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14008 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14009 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14010 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
14011 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14012 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14013 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14014 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
14015 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14016 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14017 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14018 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
14019 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
14020 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14021 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
14022 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
14023 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
14024 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14025 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
14026 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
14027 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
14028 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
14029 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
14030 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
14031 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
14032 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
14033 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
14034 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
14035 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
14036 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14037 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14038 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14039 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
14040 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
14041 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
14042 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
14043 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
14044 BPOSGE_BUILTIN (32, dsp
),
14046 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
14047 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
14048 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14049 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14050 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14051 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14052 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
14053 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
14054 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
14055 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
14056 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
14057 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14058 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14059 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14060 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14061 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14062 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
14063 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
14064 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
14065 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
14066 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
14067 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
14068 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
14069 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14070 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14071 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14072 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14073 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14074 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14075 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14076 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14077 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14078 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14079 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14080 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14082 /* Built-in functions for the DSP ASE (32-bit only). */
14083 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14084 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14085 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14086 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14087 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14088 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14089 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14090 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14091 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14092 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14093 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14094 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14095 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14096 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14097 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14098 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14099 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14100 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14101 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14102 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
14103 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
14104 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14105 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
14106 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14107 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
14108 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dsp_32
),
14109 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dsp_32
),
14111 /* Built-in functions for the DSP ASE (64-bit only). */
14112 DIRECT_BUILTIN (ldx
, MIPS_DI_FTYPE_POINTER_SI
, dsp_64
),
14114 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
14115 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14116 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14117 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14118 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14119 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14120 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14121 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14122 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14123 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14125 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
14126 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
14127 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
14128 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
14129 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14130 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14131 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14132 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14133 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14134 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14135 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
14136 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
14137 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14138 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14139 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14140 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14141 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
14142 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14143 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14144 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14145 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
14146 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14147 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14148 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14149 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14150 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14151 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14152 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14153 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14154 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14155 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14156 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14157 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14158 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14159 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14160 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14161 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14162 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14163 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
14164 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
14165 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14166 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14167 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14168 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14169 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14170 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14171 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14172 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14173 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
14174 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14175 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14176 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14177 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14178 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
14179 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
14180 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14181 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14182 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14183 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
14184 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14185 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
14186 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
14187 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14188 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14189 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14190 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14191 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14192 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14193 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14194 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14195 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14196 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14197 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14198 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14199 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14200 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14201 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14202 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14203 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14204 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14205 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14206 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14207 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
14208 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
14209 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14210 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14211 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14212 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14213 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14214 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14215 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14216 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14217 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14218 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14219 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14220 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14221 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14222 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14223 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14224 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14226 /* Sundry other built-in functions. */
14227 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
)
14230 /* Index I is the function declaration for mips_builtins[I], or null if the
14231 function isn't defined on this target. */
14232 static GTY(()) tree mips_builtin_decls
[ARRAY_SIZE (mips_builtins
)];
14234 /* MODE is a vector mode whose elements have type TYPE. Return the type
14235 of the vector itself. */
14238 mips_builtin_vector_type (tree type
, enum machine_mode mode
)
14240 static tree types
[2 * (int) MAX_MACHINE_MODE
];
14243 mode_index
= (int) mode
;
14245 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
14246 mode_index
+= MAX_MACHINE_MODE
;
14248 if (types
[mode_index
] == NULL_TREE
)
14249 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
14250 return types
[mode_index
];
14253 /* Return a type for 'const volatile void *'. */
14256 mips_build_cvpointer_type (void)
14260 if (cache
== NULL_TREE
)
14261 cache
= build_pointer_type (build_qualified_type
14263 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
14267 /* Source-level argument types. */
14268 #define MIPS_ATYPE_VOID void_type_node
14269 #define MIPS_ATYPE_INT integer_type_node
14270 #define MIPS_ATYPE_POINTER ptr_type_node
14271 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
14273 /* Standard mode-based argument types. */
14274 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
14275 #define MIPS_ATYPE_SI intSI_type_node
14276 #define MIPS_ATYPE_USI unsigned_intSI_type_node
14277 #define MIPS_ATYPE_DI intDI_type_node
14278 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
14279 #define MIPS_ATYPE_SF float_type_node
14280 #define MIPS_ATYPE_DF double_type_node
14282 /* Vector argument types. */
14283 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
14284 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
14285 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
14286 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
14287 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
14288 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
14289 #define MIPS_ATYPE_UV2SI \
14290 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
14291 #define MIPS_ATYPE_UV4HI \
14292 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
14293 #define MIPS_ATYPE_UV8QI \
14294 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
14296 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
14297 their associated MIPS_ATYPEs. */
14298 #define MIPS_FTYPE_ATYPES1(A, B) \
14299 MIPS_ATYPE_##A, MIPS_ATYPE_##B
14301 #define MIPS_FTYPE_ATYPES2(A, B, C) \
14302 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
14304 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
14305 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
14307 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
14308 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
14311 /* Return the function type associated with function prototype TYPE. */
14314 mips_build_function_type (enum mips_function_type type
)
14316 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
14318 if (types
[(int) type
] == NULL_TREE
)
14321 #define DEF_MIPS_FTYPE(NUM, ARGS) \
14322 case MIPS_FTYPE_NAME##NUM ARGS: \
14323 types[(int) type] \
14324 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
14327 #include "config/mips/mips-ftypes.def"
14328 #undef DEF_MIPS_FTYPE
14330 gcc_unreachable ();
14333 return types
[(int) type
];
14336 /* Implement TARGET_INIT_BUILTINS. */
14339 mips_init_builtins (void)
14341 const struct mips_builtin_description
*d
;
14344 /* Iterate through all of the bdesc arrays, initializing all of the
14345 builtin functions. */
14346 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
14348 d
= &mips_builtins
[i
];
14350 mips_builtin_decls
[i
]
14351 = add_builtin_function (d
->name
,
14352 mips_build_function_type (d
->function_type
),
14353 i
, BUILT_IN_MD
, NULL
, NULL
);
14357 /* Implement TARGET_BUILTIN_DECL. */
14360 mips_builtin_decl (unsigned int code
, bool initialize_p ATTRIBUTE_UNUSED
)
14362 if (code
>= ARRAY_SIZE (mips_builtins
))
14363 return error_mark_node
;
14364 return mips_builtin_decls
[code
];
14367 /* Take argument ARGNO from EXP's argument list and convert it into
14368 an expand operand. Store the operand in *OP. */
14371 mips_prepare_builtin_arg (struct expand_operand
*op
, tree exp
,
14372 unsigned int argno
)
14377 arg
= CALL_EXPR_ARG (exp
, argno
);
14378 value
= expand_normal (arg
);
14379 create_input_operand (op
, value
, TYPE_MODE (TREE_TYPE (arg
)));
14382 /* Expand instruction ICODE as part of a built-in function sequence.
14383 Use the first NOPS elements of OPS as the instruction's operands.
14384 HAS_TARGET_P is true if operand 0 is a target; it is false if the
14385 instruction has no target.
14387 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
14390 mips_expand_builtin_insn (enum insn_code icode
, unsigned int nops
,
14391 struct expand_operand
*ops
, bool has_target_p
)
14393 if (!maybe_expand_insn (icode
, nops
, ops
))
14395 error ("invalid argument to built-in function");
14396 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
14398 return has_target_p
? ops
[0].value
: const0_rtx
;
14401 /* Expand a floating-point comparison for built-in function call EXP.
14402 The first NARGS arguments are the values to be compared. ICODE is
14403 the .md pattern that does the comparison and COND is the condition
14404 that is being tested. Return an rtx for the result. */
14407 mips_expand_builtin_compare_1 (enum insn_code icode
,
14408 enum mips_fp_condition cond
,
14409 tree exp
, int nargs
)
14411 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14415 /* The instruction should have a target operand, an operand for each
14416 argument, and an operand for COND. */
14417 gcc_assert (nargs
+ 2 == insn_data
[(int) icode
].n_generator_args
);
14419 output
= mips_allocate_fcc (insn_data
[(int) icode
].operand
[0].mode
);
14421 create_fixed_operand (&ops
[opno
++], output
);
14422 for (argno
= 0; argno
< nargs
; argno
++)
14423 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14424 create_integer_operand (&ops
[opno
++], (int) cond
);
14425 return mips_expand_builtin_insn (icode
, opno
, ops
, true);
14428 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14429 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14430 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14431 suggests a good place to put the result. */
14434 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
14437 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14440 /* Map any target to operand 0. */
14443 create_output_operand (&ops
[opno
++], target
, TYPE_MODE (TREE_TYPE (exp
)));
14445 /* Map the arguments to the other operands. */
14446 gcc_assert (opno
+ call_expr_nargs (exp
)
14447 == insn_data
[icode
].n_generator_args
);
14448 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
14449 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14451 return mips_expand_builtin_insn (icode
, opno
, ops
, has_target_p
);
14454 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14455 function; TYPE says which. EXP is the CALL_EXPR that calls the
14456 function, ICODE is the instruction that should be used to compare
14457 the first two arguments, and COND is the condition it should test.
14458 TARGET, if nonnull, suggests a good place to put the result. */
14461 mips_expand_builtin_movtf (enum mips_builtin_type type
,
14462 enum insn_code icode
, enum mips_fp_condition cond
,
14463 rtx target
, tree exp
)
14465 struct expand_operand ops
[4];
14468 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
, 2);
14469 create_output_operand (&ops
[0], target
, TYPE_MODE (TREE_TYPE (exp
)));
14470 if (type
== MIPS_BUILTIN_MOVT
)
14472 mips_prepare_builtin_arg (&ops
[2], exp
, 2);
14473 mips_prepare_builtin_arg (&ops
[1], exp
, 3);
14477 mips_prepare_builtin_arg (&ops
[1], exp
, 2);
14478 mips_prepare_builtin_arg (&ops
[2], exp
, 3);
14480 create_fixed_operand (&ops
[3], cmp_result
);
14481 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps
,
14485 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14486 into TARGET otherwise. Return TARGET. */
14489 mips_builtin_branch_and_move (rtx condition
, rtx target
,
14490 rtx value_if_true
, rtx value_if_false
)
14492 rtx true_label
, done_label
;
14494 true_label
= gen_label_rtx ();
14495 done_label
= gen_label_rtx ();
14497 /* First assume that CONDITION is false. */
14498 mips_emit_move (target
, value_if_false
);
14500 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14501 emit_jump_insn (gen_condjump (condition
, true_label
));
14502 emit_jump_insn (gen_jump (done_label
));
14505 /* Fix TARGET if CONDITION is true. */
14506 emit_label (true_label
);
14507 mips_emit_move (target
, value_if_true
);
14509 emit_label (done_label
);
14513 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14514 the CALL_EXPR that calls the function, ICODE is the code of the
14515 comparison instruction, and COND is the condition it should test.
14516 TARGET, if nonnull, suggests a good place to put the boolean result. */
14519 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
14520 enum insn_code icode
, enum mips_fp_condition cond
,
14521 rtx target
, tree exp
)
14523 rtx offset
, condition
, cmp_result
;
14525 if (target
== 0 || GET_MODE (target
) != SImode
)
14526 target
= gen_reg_rtx (SImode
);
14527 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
,
14528 call_expr_nargs (exp
));
14530 /* If the comparison sets more than one register, we define the result
14531 to be 0 if all registers are false and -1 if all registers are true.
14532 The value of the complete result is indeterminate otherwise. */
14533 switch (builtin_type
)
14535 case MIPS_BUILTIN_CMP_ALL
:
14536 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
14537 return mips_builtin_branch_and_move (condition
, target
,
14538 const0_rtx
, const1_rtx
);
14540 case MIPS_BUILTIN_CMP_UPPER
:
14541 case MIPS_BUILTIN_CMP_LOWER
:
14542 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
14543 condition
= gen_single_cc (cmp_result
, offset
);
14544 return mips_builtin_branch_and_move (condition
, target
,
14545 const1_rtx
, const0_rtx
);
14548 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
14549 return mips_builtin_branch_and_move (condition
, target
,
14550 const1_rtx
, const0_rtx
);
14554 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14555 if nonnull, suggests a good place to put the boolean result. */
14558 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
14560 rtx condition
, cmp_result
;
14563 if (target
== 0 || GET_MODE (target
) != SImode
)
14564 target
= gen_reg_rtx (SImode
);
14566 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
14568 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
14573 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
14574 return mips_builtin_branch_and_move (condition
, target
,
14575 const1_rtx
, const0_rtx
);
14578 /* Implement TARGET_EXPAND_BUILTIN. */
14581 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
14582 enum machine_mode mode
, int ignore
)
14585 unsigned int fcode
, avail
;
14586 const struct mips_builtin_description
*d
;
14588 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14589 fcode
= DECL_FUNCTION_CODE (fndecl
);
14590 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
14591 d
= &mips_builtins
[fcode
];
14592 avail
= d
->avail ();
14593 gcc_assert (avail
!= 0);
14594 if (TARGET_MIPS16
&& !(avail
& BUILTIN_AVAIL_MIPS16
))
14596 error ("built-in function %qE not supported for MIPS16",
14597 DECL_NAME (fndecl
));
14598 return ignore
? const0_rtx
: CONST0_RTX (mode
);
14600 switch (d
->builtin_type
)
14602 case MIPS_BUILTIN_DIRECT
:
14603 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
14605 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
14606 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
14608 case MIPS_BUILTIN_MOVT
:
14609 case MIPS_BUILTIN_MOVF
:
14610 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
14611 d
->cond
, target
, exp
);
14613 case MIPS_BUILTIN_CMP_ANY
:
14614 case MIPS_BUILTIN_CMP_ALL
:
14615 case MIPS_BUILTIN_CMP_UPPER
:
14616 case MIPS_BUILTIN_CMP_LOWER
:
14617 case MIPS_BUILTIN_CMP_SINGLE
:
14618 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
14619 d
->cond
, target
, exp
);
14621 case MIPS_BUILTIN_BPOSGE32
:
14622 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
14624 gcc_unreachable ();
14627 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14628 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14629 struct mips16_constant
{
14630 struct mips16_constant
*next
;
14633 enum machine_mode mode
;
14636 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14637 first constant, HIGHEST_ADDRESS is the highest address that the first
14638 byte of the pool can have, and INSN_ADDRESS is the current instruction
14640 struct mips16_constant_pool
{
14641 struct mips16_constant
*first
;
14642 int highest_address
;
14646 /* Add constant VALUE to POOL and return its label. MODE is the
14647 value's mode (used for CONST_INTs, etc.). */
14650 mips16_add_constant (struct mips16_constant_pool
*pool
,
14651 rtx value
, enum machine_mode mode
)
14653 struct mips16_constant
**p
, *c
;
14654 bool first_of_size_p
;
14656 /* See whether the constant is already in the pool. If so, return the
14657 existing label, otherwise leave P pointing to the place where the
14658 constant should be added.
14660 Keep the pool sorted in increasing order of mode size so that we can
14661 reduce the number of alignments needed. */
14662 first_of_size_p
= true;
14663 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
14665 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
14666 return (*p
)->label
;
14667 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
14669 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
14670 first_of_size_p
= false;
14673 /* In the worst case, the constant needed by the earliest instruction
14674 will end up at the end of the pool. The entire pool must then be
14675 accessible from that instruction.
14677 When adding the first constant, set the pool's highest address to
14678 the address of the first out-of-range byte. Adjust this address
14679 downwards each time a new constant is added. */
14680 if (pool
->first
== 0)
14681 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14682 of the instruction with the lowest two bits clear. The base PC
14683 value for LDPC has the lowest three bits clear. Assume the worst
14684 case here; namely that the PC-relative instruction occupies the
14685 last 2 bytes in an aligned word. */
14686 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
14687 pool
->highest_address
-= GET_MODE_SIZE (mode
);
14688 if (first_of_size_p
)
14689 /* Take into account the worst possible padding due to alignment. */
14690 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
14692 /* Create a new entry. */
14693 c
= XNEW (struct mips16_constant
);
14696 c
->label
= gen_label_rtx ();
14703 /* Output constant VALUE after instruction INSN and return the last
14704 instruction emitted. MODE is the mode of the constant. */
14707 mips16_emit_constants_1 (enum machine_mode mode
, rtx value
, rtx insn
)
14709 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
14711 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
14712 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
14715 if (SCALAR_FLOAT_MODE_P (mode
))
14716 return emit_insn_after (gen_consttable_float (value
), insn
);
14718 if (VECTOR_MODE_P (mode
))
14722 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
14723 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
14724 CONST_VECTOR_ELT (value
, i
), insn
);
14728 gcc_unreachable ();
14731 /* Dump out the constants in CONSTANTS after INSN. */
14734 mips16_emit_constants (struct mips16_constant
*constants
, rtx insn
)
14736 struct mips16_constant
*c
, *next
;
14740 for (c
= constants
; c
!= NULL
; c
= next
)
14742 /* If necessary, increase the alignment of PC. */
14743 if (align
< GET_MODE_SIZE (c
->mode
))
14745 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
14746 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
14748 align
= GET_MODE_SIZE (c
->mode
);
14750 insn
= emit_label_after (c
->label
, insn
);
14751 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
14757 emit_barrier_after (insn
);
14760 /* Return the length of instruction INSN. */
14763 mips16_insn_length (rtx insn
)
14765 if (JUMP_TABLE_DATA_P (insn
))
14767 rtx body
= PATTERN (insn
);
14768 if (GET_CODE (body
) == ADDR_VEC
)
14769 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
14770 else if (GET_CODE (body
) == ADDR_DIFF_VEC
)
14771 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
14773 gcc_unreachable ();
14775 return get_attr_length (insn
);
14778 /* If *X is a symbolic constant that refers to the constant pool, add
14779 the constant to POOL and rewrite *X to use the constant's label. */
14782 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
14784 rtx base
, offset
, label
;
14786 split_const (*x
, &base
, &offset
);
14787 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
14789 label
= mips16_add_constant (pool
, copy_rtx (get_pool_constant (base
)),
14790 get_pool_mode (base
));
14791 base
= gen_rtx_LABEL_REF (Pmode
, label
);
14792 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
14796 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14797 INSN is the instruction we're rewriting and POOL points to the current
14799 struct mips16_rewrite_pool_refs_info
{
14801 struct mips16_constant_pool
*pool
;
14804 /* Rewrite *X so that constant pool references refer to the constant's
14805 label instead. DATA points to a mips16_rewrite_pool_refs_info
14809 mips16_rewrite_pool_refs (rtx
*x
, void *data
)
14811 struct mips16_rewrite_pool_refs_info
*info
=
14812 (struct mips16_rewrite_pool_refs_info
*) data
;
14814 if (force_to_mem_operand (*x
, Pmode
))
14816 rtx mem
= force_const_mem (GET_MODE (*x
), *x
);
14817 validate_change (info
->insn
, x
, mem
, false);
14822 mips16_rewrite_pool_constant (info
->pool
, &XEXP (*x
, 0));
14826 /* Don't rewrite the __mips16_rdwr symbol. */
14827 if (GET_CODE (*x
) == UNSPEC
&& XINT (*x
, 1) == UNSPEC_TLS_GET_TP
)
14830 if (TARGET_MIPS16_TEXT_LOADS
)
14831 mips16_rewrite_pool_constant (info
->pool
, x
);
14833 return GET_CODE (*x
) == CONST
? -1 : 0;
14836 /* Return whether CFG is used in mips_reorg. */
14839 mips_cfg_in_reorg (void)
14841 return (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
14842 || TARGET_RELAX_PIC_CALLS
);
14845 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14846 otherwise assume that they are already split. */
14849 mips16_lay_out_constants (bool split_p
)
14851 struct mips16_constant_pool pool
;
14852 struct mips16_rewrite_pool_refs_info info
;
14855 if (!TARGET_MIPS16_PCREL_LOADS
)
14860 if (mips_cfg_in_reorg ())
14861 split_all_insns ();
14863 split_all_insns_noflow ();
14866 memset (&pool
, 0, sizeof (pool
));
14867 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14869 /* Rewrite constant pool references in INSN. */
14870 if (USEFUL_INSN_P (insn
))
14874 for_each_rtx (&PATTERN (insn
), mips16_rewrite_pool_refs
, &info
);
14877 pool
.insn_address
+= mips16_insn_length (insn
);
14879 if (pool
.first
!= NULL
)
14881 /* If there are no natural barriers between the first user of
14882 the pool and the highest acceptable address, we'll need to
14883 create a new instruction to jump around the constant pool.
14884 In the worst case, this instruction will be 4 bytes long.
14886 If it's too late to do this transformation after INSN,
14887 do it immediately before INSN. */
14888 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
14892 label
= gen_label_rtx ();
14894 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
14895 JUMP_LABEL (jump
) = label
;
14896 LABEL_NUSES (label
) = 1;
14897 barrier
= emit_barrier_after (jump
);
14899 emit_label_after (label
, barrier
);
14900 pool
.insn_address
+= 4;
14903 /* See whether the constant pool is now out of range of the first
14904 user. If so, output the constants after the previous barrier.
14905 Note that any instructions between BARRIER and INSN (inclusive)
14906 will use negative offsets to refer to the pool. */
14907 if (pool
.insn_address
> pool
.highest_address
)
14909 mips16_emit_constants (pool
.first
, barrier
);
14913 else if (BARRIER_P (insn
))
14917 mips16_emit_constants (pool
.first
, get_last_insn ());
14920 /* Return true if it is worth r10k_simplify_address's while replacing
14921 an address with X. We are looking for constants, and for addresses
14922 at a known offset from the incoming stack pointer. */
14925 r10k_simplified_address_p (rtx x
)
14927 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
14929 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
14932 /* X is an expression that appears in INSN. Try to use the UD chains
14933 to simplify it, returning the simplified form on success and the
14934 original form otherwise. Replace the incoming value of $sp with
14935 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14938 r10k_simplify_address (rtx x
, rtx insn
)
14940 rtx newx
, op0
, op1
, set
, def_insn
, note
;
14942 struct df_link
*defs
;
14947 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14948 if (op0
!= XEXP (x
, 0))
14949 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
14950 op0
, GET_MODE (XEXP (x
, 0)));
14952 else if (BINARY_P (x
))
14954 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14955 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
14956 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
14957 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
14959 else if (GET_CODE (x
) == LO_SUM
)
14961 /* LO_SUMs can be offset from HIGHs, if we know they won't
14962 overflow. See mips_classify_address for the rationale behind
14964 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14965 if (GET_CODE (op0
) == HIGH
)
14966 newx
= XEXP (x
, 1);
14968 else if (REG_P (x
))
14970 /* Uses are recorded by regno_reg_rtx, not X itself. */
14971 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
14973 defs
= DF_REF_CHAIN (use
);
14975 /* Require a single definition. */
14976 if (defs
&& defs
->next
== NULL
)
14979 if (DF_REF_IS_ARTIFICIAL (def
))
14981 /* Replace the incoming value of $sp with
14982 virtual_incoming_args_rtx. */
14983 if (x
== stack_pointer_rtx
14984 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR_FOR_FN (cfun
))
14985 newx
= virtual_incoming_args_rtx
;
14987 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
14990 /* Make sure that DEF_INSN is a single set of REG. */
14991 def_insn
= DF_REF_INSN (def
);
14992 if (NONJUMP_INSN_P (def_insn
))
14994 set
= single_set (def_insn
);
14995 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
14997 /* Prefer to use notes, since the def-use chains
14998 are often shorter. */
14999 note
= find_reg_equal_equiv_note (def_insn
);
15001 newx
= XEXP (note
, 0);
15003 newx
= SET_SRC (set
);
15004 newx
= r10k_simplify_address (newx
, def_insn
);
15010 if (newx
&& r10k_simplified_address_p (newx
))
15015 /* Return true if ADDRESS is known to be an uncached address
15016 on R10K systems. */
15019 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
15021 unsigned HOST_WIDE_INT upper
;
15023 /* Check for KSEG1. */
15024 if (address
+ 0x60000000 < 0x20000000)
15027 /* Check for uncached XKPHYS addresses. */
15028 if (Pmode
== DImode
)
15030 upper
= (address
>> 40) & 0xf9ffff;
15031 if (upper
== 0x900000 || upper
== 0xb80000)
15037 /* Return true if we can prove that an access to address X in instruction
15038 INSN would be safe from R10K speculation. This X is a general
15039 expression; it might not be a legitimate address. */
15042 r10k_safe_address_p (rtx x
, rtx insn
)
15045 HOST_WIDE_INT offset_val
;
15047 x
= r10k_simplify_address (x
, insn
);
15049 /* Check for references to the stack frame. It doesn't really matter
15050 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
15051 allows us to assume that accesses to any part of the eventual frame
15052 is safe from speculation at any point in the function. */
15053 mips_split_plus (x
, &base
, &offset_val
);
15054 if (base
== virtual_incoming_args_rtx
15055 && offset_val
>= -cfun
->machine
->frame
.total_size
15056 && offset_val
< cfun
->machine
->frame
.args_size
)
15059 /* Check for uncached addresses. */
15060 if (CONST_INT_P (x
))
15061 return r10k_uncached_address_p (INTVAL (x
));
15063 /* Check for accesses to a static object. */
15064 split_const (x
, &base
, &offset
);
15065 return offset_within_block_p (base
, INTVAL (offset
));
15068 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
15069 an in-range access to an automatic variable, or to an object with
15070 a link-time-constant address. */
15073 r10k_safe_mem_expr_p (tree expr
, unsigned HOST_WIDE_INT offset
)
15075 HOST_WIDE_INT bitoffset
, bitsize
;
15076 tree inner
, var_offset
;
15077 enum machine_mode mode
;
15078 int unsigned_p
, volatile_p
;
15080 inner
= get_inner_reference (expr
, &bitsize
, &bitoffset
, &var_offset
, &mode
,
15081 &unsigned_p
, &volatile_p
, false);
15082 if (!DECL_P (inner
) || !DECL_SIZE_UNIT (inner
) || var_offset
)
15085 offset
+= bitoffset
/ BITS_PER_UNIT
;
15086 return offset
< tree_to_uhwi (DECL_SIZE_UNIT (inner
));
15089 /* A for_each_rtx callback for which DATA points to the instruction
15090 containing *X. Stop the search if we find a MEM that is not safe
15091 from R10K speculation. */
15094 r10k_needs_protection_p_1 (rtx
*loc
, void *data
)
15103 && MEM_OFFSET_KNOWN_P (mem
)
15104 && r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
15107 if (r10k_safe_address_p (XEXP (mem
, 0), (rtx
) data
))
15113 /* A note_stores callback for which DATA points to an instruction pointer.
15114 If *DATA is nonnull, make it null if it X contains a MEM that is not
15115 safe from R10K speculation. */
15118 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
15123 insn_ptr
= (rtx
*) data
;
15124 if (*insn_ptr
&& for_each_rtx (&x
, r10k_needs_protection_p_1
, *insn_ptr
))
15125 *insn_ptr
= NULL_RTX
;
15128 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
15129 Return nonzero if the call is not to a declared function. */
15132 r10k_needs_protection_p_call (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
15141 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_DECL (x
))
15147 /* Return true if instruction INSN needs to be protected by an R10K
15151 r10k_needs_protection_p (rtx insn
)
15154 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_call
, NULL
);
15156 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
15158 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
15159 return insn
== NULL_RTX
;
15162 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_1
, insn
);
15165 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
15166 edge is unconditional. */
15169 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
15174 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
15175 if (!single_succ_p (e
->src
)
15176 || !bitmap_bit_p (protected_bbs
, e
->src
->index
)
15177 || (e
->flags
& EDGE_COMPLEX
) != 0)
15182 /* Implement -mr10k-cache-barrier= for the current function. */
15185 r10k_insert_cache_barriers (void)
15187 int *rev_post_order
;
15190 sbitmap protected_bbs
;
15191 rtx insn
, end
, unprotected_region
;
15195 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
15199 /* Calculate dominators. */
15200 calculate_dominance_info (CDI_DOMINATORS
);
15202 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
15203 X is protected by a cache barrier. */
15204 protected_bbs
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
15205 bitmap_clear (protected_bbs
);
15207 /* Iterate over the basic blocks in reverse post-order. */
15208 rev_post_order
= XNEWVEC (int, last_basic_block_for_fn (cfun
));
15209 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
15210 for (i
= 0; i
< n
; i
++)
15212 bb
= BASIC_BLOCK_FOR_FN (cfun
, rev_post_order
[i
]);
15214 /* If this block is only reached by unconditional edges, and if the
15215 source of every edge is protected, the beginning of the block is
15217 if (r10k_protected_bb_p (bb
, protected_bbs
))
15218 unprotected_region
= NULL_RTX
;
15220 unprotected_region
= pc_rtx
;
15221 end
= NEXT_INSN (BB_END (bb
));
15223 /* UNPROTECTED_REGION is:
15225 - null if we are processing a protected region,
15226 - pc_rtx if we are processing an unprotected region but have
15227 not yet found the first instruction in it
15228 - the first instruction in an unprotected region otherwise. */
15229 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
15231 if (unprotected_region
&& USEFUL_INSN_P (insn
))
15233 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
15234 /* This CACHE instruction protects the following code. */
15235 unprotected_region
= NULL_RTX
;
15238 /* See if INSN is the first instruction in this
15239 unprotected region. */
15240 if (unprotected_region
== pc_rtx
)
15241 unprotected_region
= insn
;
15243 /* See if INSN needs to be protected. If so,
15244 we must insert a cache barrier somewhere between
15245 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
15246 clear which position is better performance-wise,
15247 but as a tie-breaker, we assume that it is better
15248 to allow delay slots to be back-filled where
15249 possible, and that it is better not to insert
15250 barriers in the middle of already-scheduled code.
15251 We therefore insert the barrier at the beginning
15253 if (r10k_needs_protection_p (insn
))
15255 emit_insn_before (gen_r10k_cache_barrier (),
15256 unprotected_region
);
15257 unprotected_region
= NULL_RTX
;
15263 /* The called function is not required to protect the exit path.
15264 The code that follows a call is therefore unprotected. */
15265 unprotected_region
= pc_rtx
;
15268 /* Record whether the end of this block is protected. */
15269 if (unprotected_region
== NULL_RTX
)
15270 bitmap_set_bit (protected_bbs
, bb
->index
);
15272 XDELETEVEC (rev_post_order
);
15274 sbitmap_free (protected_bbs
);
15276 free_dominance_info (CDI_DOMINATORS
);
15279 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
15280 otherwise. If INSN has two call rtx, then store the second one in
15284 mips_call_expr_from_insn (rtx insn
, rtx
*second_call
)
15289 if (!CALL_P (insn
))
15292 x
= PATTERN (insn
);
15293 if (GET_CODE (x
) == PARALLEL
)
15295 /* Calls returning complex values have two CALL rtx. Look for the second
15296 one here, and return it via the SECOND_CALL arg. */
15297 x2
= XVECEXP (x
, 0, 1);
15298 if (GET_CODE (x2
) == SET
)
15300 if (GET_CODE (x2
) == CALL
)
15303 x
= XVECEXP (x
, 0, 0);
15305 if (GET_CODE (x
) == SET
)
15307 gcc_assert (GET_CODE (x
) == CALL
);
15312 /* REG is set in DEF. See if the definition is one of the ways we load a
15313 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
15314 If it is, return the symbol reference of the function, otherwise return
15317 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
15318 the values of source registers, otherwise treat such registers as
15319 having an unknown value. */
15322 mips_pic_call_symbol_from_set (df_ref def
, rtx reg
, bool recurse_p
)
15326 if (DF_REF_IS_ARTIFICIAL (def
))
15329 def_insn
= DF_REF_INSN (def
);
15330 set
= single_set (def_insn
);
15331 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
15333 rtx note
, src
, symbol
;
15335 /* First see whether the source is a plain symbol. This is used
15336 when calling symbols that are not lazily bound. */
15337 src
= SET_SRC (set
);
15338 if (GET_CODE (src
) == SYMBOL_REF
)
15341 /* Handle %call16 references. */
15342 symbol
= mips_strip_unspec_call (src
);
15345 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15349 /* If we have something more complicated, look for a
15350 REG_EQUAL or REG_EQUIV note. */
15351 note
= find_reg_equal_equiv_note (def_insn
);
15352 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
15353 return XEXP (note
, 0);
15355 /* Follow at most one simple register copy. Such copies are
15356 interesting in cases like:
15360 locally_binding_fn (...);
15365 locally_binding_fn (...);
15367 locally_binding_fn (...);
15369 where the load of locally_binding_fn can legitimately be
15370 hoisted or shared. However, we do not expect to see complex
15371 chains of copies, so a full worklist solution to the problem
15372 would probably be overkill. */
15373 if (recurse_p
&& REG_P (src
))
15374 return mips_find_pic_call_symbol (def_insn
, src
, false);
15380 /* Find the definition of the use of REG in INSN. See if the definition
15381 is one of the ways we load a register with a symbol address for a
15382 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
15383 of the function, otherwise return NULL_RTX. RECURSE_P is as for
15384 mips_pic_call_symbol_from_set. */
15387 mips_find_pic_call_symbol (rtx insn
, rtx reg
, bool recurse_p
)
15390 struct df_link
*defs
;
15393 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (reg
)]);
15396 defs
= DF_REF_CHAIN (use
);
15399 symbol
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15403 /* If we have more than one definition, they need to be identical. */
15404 for (defs
= defs
->next
; defs
; defs
= defs
->next
)
15408 other
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15409 if (!rtx_equal_p (symbol
, other
))
15416 /* Replace the args_size operand of the call expression CALL with the
15417 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15420 mips_annotate_pic_call_expr (rtx call
, rtx symbol
)
15424 args_size
= XEXP (call
, 1);
15425 XEXP (call
, 1) = gen_rtx_UNSPEC (GET_MODE (args_size
),
15426 gen_rtvec (2, args_size
, symbol
),
15430 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15431 if instead of the arg_size argument it contains the call attributes. If
15432 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15433 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15437 mips_get_pic_call_symbol (rtx
*operands
, int args_size_opno
)
15439 rtx args_size
, symbol
;
15441 if (!TARGET_RELAX_PIC_CALLS
|| args_size_opno
== -1)
15444 args_size
= operands
[args_size_opno
];
15445 if (GET_CODE (args_size
) != UNSPEC
)
15447 gcc_assert (XINT (args_size
, 1) == UNSPEC_CALL_ATTR
);
15449 symbol
= XVECEXP (args_size
, 0, 1);
15450 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15452 operands
[args_size_opno
] = symbol
;
15456 /* Use DF to annotate PIC indirect calls with the function symbol they
15460 mips_annotate_pic_calls (void)
15465 FOR_EACH_BB_FN (bb
, cfun
)
15466 FOR_BB_INSNS (bb
, insn
)
15468 rtx call
, reg
, symbol
, second_call
;
15471 call
= mips_call_expr_from_insn (insn
, &second_call
);
15474 gcc_assert (MEM_P (XEXP (call
, 0)));
15475 reg
= XEXP (XEXP (call
, 0), 0);
15479 symbol
= mips_find_pic_call_symbol (insn
, reg
, true);
15482 mips_annotate_pic_call_expr (call
, symbol
);
15484 mips_annotate_pic_call_expr (second_call
, symbol
);
15489 /* A temporary variable used by for_each_rtx callbacks, etc. */
15490 static rtx mips_sim_insn
;
15492 /* A structure representing the state of the processor pipeline.
15493 Used by the mips_sim_* family of functions. */
15495 /* The maximum number of instructions that can be issued in a cycle.
15496 (Caches mips_issue_rate.) */
15497 unsigned int issue_rate
;
15499 /* The current simulation time. */
15502 /* How many more instructions can be issued in the current cycle. */
15503 unsigned int insns_left
;
15505 /* LAST_SET[X].INSN is the last instruction to set register X.
15506 LAST_SET[X].TIME is the time at which that instruction was issued.
15507 INSN is null if no instruction has yet set register X. */
15511 } last_set
[FIRST_PSEUDO_REGISTER
];
15513 /* The pipeline's current DFA state. */
15517 /* Reset STATE to the initial simulation state. */
15520 mips_sim_reset (struct mips_sim
*state
)
15522 curr_state
= state
->dfa_state
;
15525 state
->insns_left
= state
->issue_rate
;
15526 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
15527 state_reset (curr_state
);
15529 targetm
.sched
.init (0, false, 0);
15530 advance_state (curr_state
);
15533 /* Initialize STATE before its first use. DFA_STATE points to an
15534 allocated but uninitialized DFA state. */
15537 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
15539 if (targetm
.sched
.init_dfa_pre_cycle_insn
)
15540 targetm
.sched
.init_dfa_pre_cycle_insn ();
15542 if (targetm
.sched
.init_dfa_post_cycle_insn
)
15543 targetm
.sched
.init_dfa_post_cycle_insn ();
15545 state
->issue_rate
= mips_issue_rate ();
15546 state
->dfa_state
= dfa_state
;
15547 mips_sim_reset (state
);
15550 /* Advance STATE by one clock cycle. */
15553 mips_sim_next_cycle (struct mips_sim
*state
)
15555 curr_state
= state
->dfa_state
;
15558 state
->insns_left
= state
->issue_rate
;
15559 advance_state (curr_state
);
15562 /* Advance simulation state STATE until instruction INSN can read
15566 mips_sim_wait_reg (struct mips_sim
*state
, rtx insn
, rtx reg
)
15568 unsigned int regno
, end_regno
;
15570 end_regno
= END_REGNO (reg
);
15571 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
15572 if (state
->last_set
[regno
].insn
!= 0)
15576 t
= (state
->last_set
[regno
].time
15577 + insn_latency (state
->last_set
[regno
].insn
, insn
));
15578 while (state
->time
< t
)
15579 mips_sim_next_cycle (state
);
15583 /* A for_each_rtx callback. If *X is a register, advance simulation state
15584 DATA until mips_sim_insn can read the register's value. */
15587 mips_sim_wait_regs_2 (rtx
*x
, void *data
)
15590 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *x
);
15594 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
15597 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
15599 for_each_rtx (x
, mips_sim_wait_regs_2
, data
);
15602 /* Advance simulation state STATE until all of INSN's register
15603 dependencies are satisfied. */
15606 mips_sim_wait_regs (struct mips_sim
*state
, rtx insn
)
15608 mips_sim_insn
= insn
;
15609 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
15612 /* Advance simulation state STATE until the units required by
15613 instruction INSN are available. */
15616 mips_sim_wait_units (struct mips_sim
*state
, rtx insn
)
15620 tmp_state
= alloca (state_size ());
15621 while (state
->insns_left
== 0
15622 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
15623 state_transition (tmp_state
, insn
) >= 0))
15624 mips_sim_next_cycle (state
);
15627 /* Advance simulation state STATE until INSN is ready to issue. */
15630 mips_sim_wait_insn (struct mips_sim
*state
, rtx insn
)
15632 mips_sim_wait_regs (state
, insn
);
15633 mips_sim_wait_units (state
, insn
);
15636 /* mips_sim_insn has just set X. Update the LAST_SET array
15637 in simulation state DATA. */
15640 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
15642 struct mips_sim
*state
;
15644 state
= (struct mips_sim
*) data
;
15647 unsigned int regno
, end_regno
;
15649 end_regno
= END_REGNO (x
);
15650 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
15652 state
->last_set
[regno
].insn
= mips_sim_insn
;
15653 state
->last_set
[regno
].time
= state
->time
;
15658 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15659 can issue immediately (i.e., that mips_sim_wait_insn has already
15663 mips_sim_issue_insn (struct mips_sim
*state
, rtx insn
)
15665 curr_state
= state
->dfa_state
;
15667 state_transition (curr_state
, insn
);
15668 state
->insns_left
= targetm
.sched
.variable_issue (0, false, insn
,
15669 state
->insns_left
);
15671 mips_sim_insn
= insn
;
15672 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
15675 /* Simulate issuing a NOP in state STATE. */
15678 mips_sim_issue_nop (struct mips_sim
*state
)
15680 if (state
->insns_left
== 0)
15681 mips_sim_next_cycle (state
);
15682 state
->insns_left
--;
15685 /* Update simulation state STATE so that it's ready to accept the instruction
15686 after INSN. INSN should be part of the main rtl chain, not a member of a
15690 mips_sim_finish_insn (struct mips_sim
*state
, rtx insn
)
15692 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15694 mips_sim_issue_nop (state
);
15696 switch (GET_CODE (SEQ_BEGIN (insn
)))
15700 /* We can't predict the processor state after a call or label. */
15701 mips_sim_reset (state
);
15705 /* The delay slots of branch likely instructions are only executed
15706 when the branch is taken. Therefore, if the caller has simulated
15707 the delay slot instruction, STATE does not really reflect the state
15708 of the pipeline for the instruction after the delay slot. Also,
15709 branch likely instructions tend to incur a penalty when not taken,
15710 so there will probably be an extra delay between the branch and
15711 the instruction after the delay slot. */
15712 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
15713 mips_sim_reset (state
);
15721 /* Use simulator state STATE to calculate the execution time of
15722 instruction sequence SEQ. */
15724 static unsigned int
15725 mips_seq_time (struct mips_sim
*state
, rtx seq
)
15727 mips_sim_reset (state
);
15728 for (rtx insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
15730 mips_sim_wait_insn (state
, insn
);
15731 mips_sim_issue_insn (state
, insn
);
15733 return state
->time
;
15736 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
15737 setting SETTING, using STATE to simulate instruction sequences. */
15739 static unsigned int
15740 mips_mult_zero_zero_cost (struct mips_sim
*state
, bool setting
)
15742 mips_tuning_info
.fast_mult_zero_zero_p
= setting
;
15745 enum machine_mode dword_mode
= TARGET_64BIT
? TImode
: DImode
;
15746 rtx hilo
= gen_rtx_REG (dword_mode
, MD_REG_FIRST
);
15747 mips_emit_move_or_split (hilo
, const0_rtx
, SPLIT_FOR_SPEED
);
15749 /* If the target provides mulsidi3_32bit then that's the most likely
15750 consumer of the result. Test for bypasses. */
15751 if (dword_mode
== DImode
&& HAVE_maddsidi4
)
15753 rtx gpr
= gen_rtx_REG (SImode
, GP_REG_FIRST
+ 4);
15754 emit_insn (gen_maddsidi4 (hilo
, gpr
, gpr
, hilo
));
15757 unsigned int time
= mips_seq_time (state
, get_insns ());
15762 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
15763 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
15764 Prefer MULT -- which is shorter -- in the event of a tie. */
15767 mips_set_fast_mult_zero_zero_p (struct mips_sim
*state
)
15770 /* No MTLO or MTHI available. */
15771 mips_tuning_info
.fast_mult_zero_zero_p
= true;
15774 unsigned int true_time
= mips_mult_zero_zero_cost (state
, true);
15775 unsigned int false_time
= mips_mult_zero_zero_cost (state
, false);
15776 mips_tuning_info
.fast_mult_zero_zero_p
= (true_time
<= false_time
);
15780 /* Set up costs based on the current architecture and tuning settings. */
15783 mips_set_tuning_info (void)
15785 if (mips_tuning_info
.initialized_p
15786 && mips_tuning_info
.arch
== mips_arch
15787 && mips_tuning_info
.tune
== mips_tune
15788 && mips_tuning_info
.mips16_p
== TARGET_MIPS16
)
15791 mips_tuning_info
.arch
= mips_arch
;
15792 mips_tuning_info
.tune
= mips_tune
;
15793 mips_tuning_info
.mips16_p
= TARGET_MIPS16
;
15794 mips_tuning_info
.initialized_p
= true;
15798 struct mips_sim state
;
15799 mips_sim_init (&state
, alloca (state_size ()));
15801 mips_set_fast_mult_zero_zero_p (&state
);
15806 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
15809 mips_expand_to_rtl_hook (void)
15811 /* We need to call this at a point where we can safely create sequences
15812 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
15813 need to call it at a point where the DFA infrastructure is not
15814 already in use, so we can't just call it lazily on demand.
15816 At present, mips_tuning_info is only needed during post-expand
15817 RTL passes such as split_insns, so this hook should be early enough.
15818 We may need to move the call elsewhere if mips_tuning_info starts
15819 to be used for other things (such as rtx_costs, or expanders that
15820 could be called during gimple optimization). */
15821 mips_set_tuning_info ();
15824 /* The VR4130 pipeline issues aligned pairs of instructions together,
15825 but it stalls the second instruction if it depends on the first.
15826 In order to cut down the amount of logic required, this dependence
15827 check is not based on a full instruction decode. Instead, any non-SPECIAL
15828 instruction is assumed to modify the register specified by bits 20-16
15829 (which is usually the "rt" field).
15831 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15832 input, so we can end up with a false dependence between the branch
15833 and its delay slot. If this situation occurs in instruction INSN,
15834 try to avoid it by swapping rs and rt. */
15837 vr4130_avoid_branch_rt_conflict (rtx insn
)
15841 first
= SEQ_BEGIN (insn
);
15842 second
= SEQ_END (insn
);
15844 && NONJUMP_INSN_P (second
)
15845 && GET_CODE (PATTERN (first
)) == SET
15846 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
15847 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
15849 /* Check for the right kind of condition. */
15850 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
15851 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
15852 && REG_P (XEXP (cond
, 0))
15853 && REG_P (XEXP (cond
, 1))
15854 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
15855 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
15857 /* SECOND mentions the rt register but not the rs register. */
15858 rtx tmp
= XEXP (cond
, 0);
15859 XEXP (cond
, 0) = XEXP (cond
, 1);
15860 XEXP (cond
, 1) = tmp
;
15865 /* Implement -mvr4130-align. Go through each basic block and simulate the
15866 processor pipeline. If we find that a pair of instructions could execute
15867 in parallel, and the first of those instructions is not 8-byte aligned,
15868 insert a nop to make it aligned. */
15871 vr4130_align_insns (void)
15873 struct mips_sim state
;
15874 rtx insn
, subinsn
, last
, last2
, next
;
15879 /* LAST is the last instruction before INSN to have a nonzero length.
15880 LAST2 is the last such instruction before LAST. */
15884 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15887 mips_sim_init (&state
, alloca (state_size ()));
15888 for (insn
= get_insns (); insn
!= 0; insn
= next
)
15890 unsigned int length
;
15892 next
= NEXT_INSN (insn
);
15894 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15895 This isn't really related to the alignment pass, but we do it on
15896 the fly to avoid a separate instruction walk. */
15897 vr4130_avoid_branch_rt_conflict (insn
);
15899 length
= get_attr_length (insn
);
15900 if (length
> 0 && USEFUL_INSN_P (insn
))
15901 FOR_EACH_SUBINSN (subinsn
, insn
)
15903 mips_sim_wait_insn (&state
, subinsn
);
15905 /* If we want this instruction to issue in parallel with the
15906 previous one, make sure that the previous instruction is
15907 aligned. There are several reasons why this isn't worthwhile
15908 when the second instruction is a call:
15910 - Calls are less likely to be performance critical,
15911 - There's a good chance that the delay slot can execute
15912 in parallel with the call.
15913 - The return address would then be unaligned.
15915 In general, if we're going to insert a nop between instructions
15916 X and Y, it's better to insert it immediately after X. That
15917 way, if the nop makes Y aligned, it will also align any labels
15918 between X and Y. */
15919 if (state
.insns_left
!= state
.issue_rate
15920 && !CALL_P (subinsn
))
15922 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
15924 /* SUBINSN is the first instruction in INSN and INSN is
15925 aligned. We want to align the previous instruction
15926 instead, so insert a nop between LAST2 and LAST.
15928 Note that LAST could be either a single instruction
15929 or a branch with a delay slot. In the latter case,
15930 LAST, like INSN, is already aligned, but the delay
15931 slot must have some extra delay that stops it from
15932 issuing at the same time as the branch. We therefore
15933 insert a nop before the branch in order to align its
15935 gcc_assert (last2
);
15936 emit_insn_after (gen_nop (), last2
);
15939 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
15941 /* SUBINSN is the delay slot of INSN, but INSN is
15942 currently unaligned. Insert a nop between
15943 LAST and INSN to align it. */
15945 emit_insn_after (gen_nop (), last
);
15949 mips_sim_issue_insn (&state
, subinsn
);
15951 mips_sim_finish_insn (&state
, insn
);
15953 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15954 length
= get_attr_length (insn
);
15957 /* If the instruction is an asm statement or multi-instruction
15958 mips.md patern, the length is only an estimate. Insert an
15959 8 byte alignment after it so that the following instructions
15960 can be handled correctly. */
15961 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
15962 && (recog_memoized (insn
) < 0 || length
>= 8))
15964 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
15965 next
= NEXT_INSN (next
);
15966 mips_sim_next_cycle (&state
);
15969 else if (length
& 4)
15970 aligned_p
= !aligned_p
;
15975 /* See whether INSN is an aligned label. */
15976 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
15982 /* This structure records that the current function has a LO_SUM
15983 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15984 the largest offset applied to BASE by all such LO_SUMs. */
15985 struct mips_lo_sum_offset
{
15987 HOST_WIDE_INT offset
;
15990 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15993 mips_hash_base (rtx base
)
15995 int do_not_record_p
;
15997 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
16000 /* Hashtable helpers. */
16002 struct mips_lo_sum_offset_hasher
: typed_free_remove
<mips_lo_sum_offset
>
16004 typedef mips_lo_sum_offset value_type
;
16005 typedef rtx_def compare_type
;
16006 static inline hashval_t
hash (const value_type
*);
16007 static inline bool equal (const value_type
*, const compare_type
*);
16010 /* Hash-table callbacks for mips_lo_sum_offsets. */
16013 mips_lo_sum_offset_hasher::hash (const value_type
*entry
)
16015 return mips_hash_base (entry
->base
);
16019 mips_lo_sum_offset_hasher::equal (const value_type
*entry
,
16020 const compare_type
*value
)
16022 return rtx_equal_p (entry
->base
, value
);
16025 typedef hash_table
<mips_lo_sum_offset_hasher
> mips_offset_table
;
16027 /* Look up symbolic constant X in HTAB, which is a hash table of
16028 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
16029 paired with a recorded LO_SUM, otherwise record X in the table. */
16032 mips_lo_sum_offset_lookup (mips_offset_table htab
, rtx x
,
16033 enum insert_option option
)
16036 mips_lo_sum_offset
**slot
;
16037 struct mips_lo_sum_offset
*entry
;
16039 /* Split X into a base and offset. */
16040 split_const (x
, &base
, &offset
);
16041 if (UNSPEC_ADDRESS_P (base
))
16042 base
= UNSPEC_ADDRESS (base
);
16044 /* Look up the base in the hash table. */
16045 slot
= htab
.find_slot_with_hash (base
, mips_hash_base (base
), option
);
16049 entry
= (struct mips_lo_sum_offset
*) *slot
;
16050 if (option
== INSERT
)
16054 entry
= XNEW (struct mips_lo_sum_offset
);
16055 entry
->base
= base
;
16056 entry
->offset
= INTVAL (offset
);
16061 if (INTVAL (offset
) > entry
->offset
)
16062 entry
->offset
= INTVAL (offset
);
16065 return INTVAL (offset
) <= entry
->offset
;
16068 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
16069 Record every LO_SUM in *LOC. */
16072 mips_record_lo_sum (rtx
*loc
, void *data
)
16074 if (GET_CODE (*loc
) == LO_SUM
)
16075 mips_lo_sum_offset_lookup (*(mips_offset_table
*) data
,
16076 XEXP (*loc
, 1), INSERT
);
16080 /* Return true if INSN is a SET of an orphaned high-part relocation.
16081 HTAB is a hash table of mips_lo_sum_offsets that describes all the
16082 LO_SUMs in the current function. */
16085 mips_orphaned_high_part_p (mips_offset_table htab
, rtx insn
)
16087 enum mips_symbol_type type
;
16090 set
= single_set (insn
);
16093 /* Check for %his. */
16095 if (GET_CODE (x
) == HIGH
16096 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
16097 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
16099 /* Check for local %gots (and %got_pages, which is redundant but OK). */
16100 if (GET_CODE (x
) == UNSPEC
16101 && XINT (x
, 1) == UNSPEC_LOAD_GOT
16102 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
16103 SYMBOL_CONTEXT_LEA
, &type
)
16104 && type
== SYMBOL_GOTOFF_PAGE
)
16105 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
16110 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
16111 INSN and a previous instruction, avoid it by inserting nops after
16114 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
16115 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
16116 before using the value of that register. *HILO_DELAY counts the
16117 number of instructions since the last hilo hazard (that is,
16118 the number of instructions since the last MFLO or MFHI).
16120 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
16121 for the next instruction.
16123 LO_REG is an rtx for the LO register, used in dependence checking. */
16126 mips_avoid_hazard (rtx after
, rtx insn
, int *hilo_delay
,
16127 rtx
*delayed_reg
, rtx lo_reg
)
16132 pattern
= PATTERN (insn
);
16134 /* Do not put the whole function in .set noreorder if it contains
16135 an asm statement. We don't know whether there will be hazards
16136 between the asm statement and the gcc-generated code. */
16137 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
16138 cfun
->machine
->all_noreorder_p
= false;
16140 /* Ignore zero-length instructions (barriers and the like). */
16141 ninsns
= get_attr_length (insn
) / 4;
16145 /* Work out how many nops are needed. Note that we only care about
16146 registers that are explicitly mentioned in the instruction's pattern.
16147 It doesn't matter that calls use the argument registers or that they
16148 clobber hi and lo. */
16149 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
16150 nops
= 2 - *hilo_delay
;
16151 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
16156 /* Insert the nops between this instruction and the previous one.
16157 Each new nop takes us further from the last hilo hazard. */
16158 *hilo_delay
+= nops
;
16160 emit_insn_after (gen_hazard_nop (), after
);
16162 /* Set up the state for the next instruction. */
16163 *hilo_delay
+= ninsns
;
16165 if (INSN_CODE (insn
) >= 0)
16166 switch (get_attr_hazard (insn
))
16176 set
= single_set (insn
);
16178 *delayed_reg
= SET_DEST (set
);
16183 /* Go through the instruction stream and insert nops where necessary.
16184 Also delete any high-part relocations whose partnering low parts
16185 are now all dead. See if the whole function can then be put into
16186 .set noreorder and .set nomacro. */
16189 mips_reorg_process_insns (void)
16191 rtx insn
, last_insn
, subinsn
, next_insn
, lo_reg
, delayed_reg
;
16193 mips_offset_table htab
;
16195 /* Force all instructions to be split into their final form. */
16196 split_all_insns_noflow ();
16198 /* Recalculate instruction lengths without taking nops into account. */
16199 cfun
->machine
->ignore_hazard_length_p
= true;
16200 shorten_branches (get_insns ());
16202 cfun
->machine
->all_noreorder_p
= true;
16204 /* We don't track MIPS16 PC-relative offsets closely enough to make
16205 a good job of "set .noreorder" code in MIPS16 mode. */
16207 cfun
->machine
->all_noreorder_p
= false;
16209 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
16210 if (!TARGET_EXPLICIT_RELOCS
)
16211 cfun
->machine
->all_noreorder_p
= false;
16213 /* Profiled functions can't be all noreorder because the profiler
16214 support uses assembler macros. */
16216 cfun
->machine
->all_noreorder_p
= false;
16218 /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be
16219 all noreorder because we rely on the assembler to work around some
16220 errata. The R5900 too has several bugs. */
16221 if (TARGET_FIX_VR4120
16222 || TARGET_FIX_RM7000
16224 || TARGET_MIPS5900
)
16225 cfun
->machine
->all_noreorder_p
= false;
16227 /* The same is true for -mfix-vr4130 if we might generate MFLO or
16228 MFHI instructions. Note that we avoid using MFLO and MFHI if
16229 the VR4130 MACC and DMACC instructions are available instead;
16230 see the *mfhilo_{si,di}_macc patterns. */
16231 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
16232 cfun
->machine
->all_noreorder_p
= false;
16236 /* Make a first pass over the instructions, recording all the LO_SUMs. */
16237 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
16238 FOR_EACH_SUBINSN (subinsn
, insn
)
16239 if (USEFUL_INSN_P (subinsn
))
16241 rtx body
= PATTERN (insn
);
16242 int noperands
= asm_noperands (body
);
16243 if (noperands
>= 0)
16245 rtx
*ops
= XALLOCAVEC (rtx
, noperands
);
16246 bool *used
= XALLOCAVEC (bool, noperands
);
16247 const char *string
= decode_asm_operands (body
, ops
, NULL
, NULL
,
16249 get_referenced_operands (string
, used
, noperands
);
16250 for (int i
= 0; i
< noperands
; ++i
)
16252 for_each_rtx (&ops
[i
], mips_record_lo_sum
, &htab
);
16255 for_each_rtx (&PATTERN (subinsn
), mips_record_lo_sum
, &htab
);
16261 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
16263 /* Make a second pass over the instructions. Delete orphaned
16264 high-part relocations or turn them into NOPs. Avoid hazards
16265 by inserting NOPs. */
16266 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
16268 next_insn
= NEXT_INSN (insn
);
16269 if (USEFUL_INSN_P (insn
))
16271 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
16273 /* If we find an orphaned high-part relocation in a delay
16274 slot, it's easier to turn that instruction into a NOP than
16275 to delete it. The delay slot will be a NOP either way. */
16276 FOR_EACH_SUBINSN (subinsn
, insn
)
16277 if (INSN_P (subinsn
))
16279 if (mips_orphaned_high_part_p (htab
, subinsn
))
16281 PATTERN (subinsn
) = gen_nop ();
16282 INSN_CODE (subinsn
) = CODE_FOR_nop
;
16284 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
16285 &delayed_reg
, lo_reg
);
16291 /* INSN is a single instruction. Delete it if it's an
16292 orphaned high-part relocation. */
16293 if (mips_orphaned_high_part_p (htab
, insn
))
16294 delete_insn (insn
);
16295 /* Also delete cache barriers if the last instruction
16296 was an annulled branch. INSN will not be speculatively
16298 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
16300 && JUMP_P (SEQ_BEGIN (last_insn
))
16301 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
16302 delete_insn (insn
);
16305 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
16306 &delayed_reg
, lo_reg
);
16316 /* Return true if the function has a long branch instruction. */
16319 mips_has_long_branch_p (void)
16324 /* We need up-to-date instruction lengths. */
16325 shorten_branches (get_insns ());
16327 /* Look for a branch that is longer than normal. The normal length for
16328 non-MIPS16 branches is 8, because the length includes the delay slot.
16329 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
16330 but they have no delay slot. */
16331 normal_length
= (TARGET_MIPS16
? 4 : 8);
16332 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16333 FOR_EACH_SUBINSN (subinsn
, insn
)
16334 if (JUMP_P (subinsn
)
16335 && get_attr_length (subinsn
) > normal_length
16336 && (any_condjump_p (subinsn
) || any_uncondjump_p (subinsn
)))
16342 /* If we are using a GOT, but have not decided to use a global pointer yet,
16343 see whether we need one to implement long branches. Convert the ghost
16344 global-pointer instructions into real ones if so. */
16347 mips_expand_ghost_gp_insns (void)
16349 /* Quick exit if we already know that we will or won't need a
16351 if (!TARGET_USE_GOT
16352 || cfun
->machine
->global_pointer
== INVALID_REGNUM
16353 || mips_must_initialize_gp_p ())
16356 /* Run a full check for long branches. */
16357 if (!mips_has_long_branch_p ())
16360 /* We've now established that we need $gp. */
16361 cfun
->machine
->must_initialize_gp_p
= true;
16362 split_all_insns_noflow ();
16367 /* Subroutine of mips_reorg to manage passes that require DF. */
16370 mips_df_reorg (void)
16372 /* Create def-use chains. */
16373 df_set_flags (DF_EQ_NOTES
);
16374 df_chain_add_problem (DF_UD_CHAIN
);
16377 if (TARGET_RELAX_PIC_CALLS
)
16378 mips_annotate_pic_calls ();
16380 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
16381 r10k_insert_cache_barriers ();
16383 df_finish_pass (false);
16386 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
16387 called very late in mips_reorg, but the caller is required to run
16388 mips16_lay_out_constants on the result. */
16391 mips16_load_branch_target (rtx dest
, rtx src
)
16393 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
16397 if (mips_cfun_has_cprestore_slot_p ())
16398 mips_emit_move (dest
, mips_cprestore_slot (dest
, true));
16400 mips_emit_move (dest
, pic_offset_table_rtx
);
16401 page
= mips_unspec_address (src
, SYMBOL_GOTOFF_PAGE
);
16402 low
= mips_unspec_address (src
, SYMBOL_GOT_PAGE_OFST
);
16403 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
16404 PMODE_INSN (gen_unspec_got
, (dest
, page
))));
16405 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
16406 gen_rtx_LO_SUM (Pmode
, dest
, low
)));
16410 src
= mips_unspec_address (src
, SYMBOL_ABSOLUTE
);
16411 mips_emit_move (dest
, src
);
16415 /* If we're compiling a MIPS16 function, look for and split any long branches.
16416 This must be called after all other instruction modifications in
16420 mips16_split_long_branches (void)
16422 bool something_changed
;
16424 if (!TARGET_MIPS16
)
16427 /* Loop until the alignments for all targets are sufficient. */
16432 shorten_branches (get_insns ());
16433 something_changed
= false;
16434 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16436 && get_attr_length (insn
) > 4
16437 && (any_condjump_p (insn
) || any_uncondjump_p (insn
)))
16439 rtx old_label
, new_label
, temp
, saved_temp
;
16440 rtx target
, jump
, jump_sequence
;
16444 /* Free up a MIPS16 register by saving it in $1. */
16445 saved_temp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
16446 temp
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
16447 emit_move_insn (saved_temp
, temp
);
16449 /* Load the branch target into TEMP. */
16450 old_label
= JUMP_LABEL (insn
);
16451 target
= gen_rtx_LABEL_REF (Pmode
, old_label
);
16452 mips16_load_branch_target (temp
, target
);
16454 /* Jump to the target and restore the register's
16456 jump
= emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore
,
16457 (temp
, temp
, saved_temp
)));
16458 JUMP_LABEL (jump
) = old_label
;
16459 LABEL_NUSES (old_label
)++;
16461 /* Rewrite any symbolic references that are supposed to use
16462 a PC-relative constant pool. */
16463 mips16_lay_out_constants (false);
16465 if (simplejump_p (insn
))
16466 /* We're going to replace INSN with a longer form. */
16467 new_label
= NULL_RTX
;
16470 /* Create a branch-around label for the original
16472 new_label
= gen_label_rtx ();
16473 emit_label (new_label
);
16476 jump_sequence
= get_insns ();
16479 emit_insn_after (jump_sequence
, insn
);
16481 invert_jump (insn
, new_label
, false);
16483 delete_insn (insn
);
16484 something_changed
= true;
16487 while (something_changed
);
16490 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16495 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16496 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16497 to date if the CFG is available. */
16498 if (mips_cfg_in_reorg ())
16499 compute_bb_for_insn ();
16500 mips16_lay_out_constants (true);
16501 if (mips_cfg_in_reorg ())
16504 free_bb_for_insn ();
16508 /* We use a machine specific pass to do a second machine dependent reorg
16509 pass after delay branch scheduling. */
16511 static unsigned int
16512 mips_machine_reorg2 (void)
16514 mips_reorg_process_insns ();
16516 && TARGET_EXPLICIT_RELOCS
16518 && TARGET_VR4130_ALIGN
)
16519 vr4130_align_insns ();
16520 if (mips_expand_ghost_gp_insns ())
16521 /* The expansion could invalidate some of the VR4130 alignment
16522 optimizations, but this should be an extremely rare case anyhow. */
16523 mips_reorg_process_insns ();
16524 mips16_split_long_branches ();
16530 const pass_data pass_data_mips_machine_reorg2
=
16532 RTL_PASS
, /* type */
16533 "mach2", /* name */
16534 OPTGROUP_NONE
, /* optinfo_flags */
16535 false, /* has_gate */
16536 true, /* has_execute */
16537 TV_MACH_DEP
, /* tv_id */
16538 0, /* properties_required */
16539 0, /* properties_provided */
16540 0, /* properties_destroyed */
16541 0, /* todo_flags_start */
16542 TODO_verify_rtl_sharing
, /* todo_flags_finish */
16545 class pass_mips_machine_reorg2
: public rtl_opt_pass
16548 pass_mips_machine_reorg2(gcc::context
*ctxt
)
16549 : rtl_opt_pass(pass_data_mips_machine_reorg2
, ctxt
)
16552 /* opt_pass methods: */
16553 unsigned int execute () { return mips_machine_reorg2 (); }
16555 }; // class pass_mips_machine_reorg2
16557 } // anon namespace
16560 make_pass_mips_machine_reorg2 (gcc::context
*ctxt
)
16562 return new pass_mips_machine_reorg2 (ctxt
);
16566 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16567 in order to avoid duplicating too much logic from elsewhere. */
16570 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
16571 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
16574 rtx this_rtx
, temp1
, temp2
, insn
, fnaddr
;
16575 bool use_sibcall_p
;
16577 /* Pretend to be a post-reload pass while generating rtl. */
16578 reload_completed
= 1;
16580 /* Mark the end of the (empty) prologue. */
16581 emit_note (NOTE_INSN_PROLOGUE_END
);
16583 /* Determine if we can use a sibcall to call FUNCTION directly. */
16584 fnaddr
= XEXP (DECL_RTL (function
), 0);
16585 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
16586 && const_call_insn_operand (fnaddr
, Pmode
));
16588 /* Determine if we need to load FNADDR from the GOT. */
16590 && (mips_got_symbol_type_p
16591 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
16593 /* Pick a global pointer. Use a call-clobbered register if
16594 TARGET_CALL_SAVED_GP. */
16595 cfun
->machine
->global_pointer
16596 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
16597 cfun
->machine
->must_initialize_gp_p
= true;
16598 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
16600 /* Set up the global pointer for n32 or n64 abicalls. */
16601 mips_emit_loadgp ();
16604 /* We need two temporary registers in some cases. */
16605 temp1
= gen_rtx_REG (Pmode
, 2);
16606 temp2
= gen_rtx_REG (Pmode
, 3);
16608 /* Find out which register contains the "this" pointer. */
16609 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
16610 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
16612 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
16614 /* Add DELTA to THIS_RTX. */
16617 rtx offset
= GEN_INT (delta
);
16618 if (!SMALL_OPERAND (delta
))
16620 mips_emit_move (temp1
, offset
);
16623 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
16626 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16627 if (vcall_offset
!= 0)
16631 /* Set TEMP1 to *THIS_RTX. */
16632 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
16634 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16635 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
16637 /* Load the offset and add it to THIS_RTX. */
16638 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
16639 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
16642 /* Jump to the target function. Use a sibcall if direct jumps are
16643 allowed, otherwise load the address into a register first. */
16646 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
16647 SIBLING_CALL_P (insn
) = 1;
16651 /* This is messy. GAS treats "la $25,foo" as part of a call
16652 sequence and may allow a global "foo" to be lazily bound.
16653 The general move patterns therefore reject this combination.
16655 In this context, lazy binding would actually be OK
16656 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16657 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16658 We must therefore load the address via a temporary
16659 register if mips_dangerous_for_la25_p.
16661 If we jump to the temporary register rather than $25,
16662 the assembler can use the move insn to fill the jump's
16665 We can use the same technique for MIPS16 code, where $25
16666 is not a valid JR register. */
16667 if (TARGET_USE_PIC_FN_ADDR_REG
16669 && !mips_dangerous_for_la25_p (fnaddr
))
16670 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
16671 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
16673 if (TARGET_USE_PIC_FN_ADDR_REG
16674 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
16675 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
16676 emit_jump_insn (gen_indirect_jump (temp1
));
16679 /* Run just enough of rest_of_compilation. This sequence was
16680 "borrowed" from alpha.c. */
16681 insn
= get_insns ();
16682 split_all_insns_noflow ();
16683 mips16_lay_out_constants (true);
16684 shorten_branches (insn
);
16685 final_start_function (insn
, file
, 1);
16686 final (insn
, file
, 1);
16687 final_end_function ();
16689 /* Clean up the vars set above. Note that final_end_function resets
16690 the global pointer for us. */
16691 reload_completed
= 0;
16695 /* The last argument passed to mips_set_compression_mode,
16696 or negative if the function hasn't been called yet. */
16697 static unsigned int old_compression_mode
= -1;
16699 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
16700 which is either MASK_MIPS16 or MASK_MICROMIPS. */
16703 mips_set_compression_mode (unsigned int compression_mode
)
16706 if (compression_mode
== old_compression_mode
)
16709 /* Restore base settings of various flags. */
16710 target_flags
= mips_base_target_flags
;
16711 flag_schedule_insns
= mips_base_schedule_insns
;
16712 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
16713 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
16714 align_loops
= mips_base_align_loops
;
16715 align_jumps
= mips_base_align_jumps
;
16716 align_functions
= mips_base_align_functions
;
16717 target_flags
&= ~(MASK_MIPS16
| MASK_MICROMIPS
);
16718 target_flags
|= compression_mode
;
16720 if (compression_mode
& MASK_MIPS16
)
16722 /* Switch to MIPS16 mode. */
16723 target_flags
|= MASK_MIPS16
;
16725 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
16726 target_flags
&= ~MASK_SYNCI
;
16728 /* Don't run the scheduler before reload, since it tends to
16729 increase register pressure. */
16730 flag_schedule_insns
= 0;
16732 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
16733 the whole function to be in a single section. */
16734 flag_reorder_blocks_and_partition
= 0;
16736 /* Don't move loop invariants, because it tends to increase
16737 register pressure. It also introduces an extra move in cases
16738 where the constant is the first operand in a two-operand binary
16739 instruction, or when it forms a register argument to a functon
16741 flag_move_loop_invariants
= 0;
16743 target_flags
|= MASK_EXPLICIT_RELOCS
;
16745 /* Experiments suggest we get the best overall section-anchor
16746 results from using the range of an unextended LW or SW. Code
16747 that makes heavy use of byte or short accesses can do better
16748 with ranges of 0...31 and 0...63 respectively, but most code is
16749 sensitive to the range of LW and SW instead. */
16750 targetm
.min_anchor_offset
= 0;
16751 targetm
.max_anchor_offset
= 127;
16753 targetm
.const_anchor
= 0;
16755 /* MIPS16 has no BAL instruction. */
16756 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
16758 /* The R4000 errata don't apply to any known MIPS16 cores.
16759 It's simpler to make the R4000 fixes and MIPS16 mode
16760 mutually exclusive. */
16761 target_flags
&= ~MASK_FIX_R4000
;
16763 if (flag_pic
&& !TARGET_OLDABI
)
16764 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
16767 sorry ("MIPS16 -mxgot code");
16769 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
16770 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
16774 /* Switch to microMIPS or the standard encoding. */
16776 if (TARGET_MICROMIPS
)
16777 /* Avoid branch likely. */
16778 target_flags
&= ~MASK_BRANCHLIKELY
;
16780 /* Provide default values for align_* for 64-bit targets. */
16783 if (align_loops
== 0)
16785 if (align_jumps
== 0)
16787 if (align_functions
== 0)
16788 align_functions
= 8;
16791 targetm
.min_anchor_offset
= -32768;
16792 targetm
.max_anchor_offset
= 32767;
16794 targetm
.const_anchor
= 0x8000;
16797 /* (Re)initialize MIPS target internals for new ISA. */
16798 mips_init_relocs ();
16800 if (compression_mode
& MASK_MIPS16
)
16802 if (!mips16_globals
)
16803 mips16_globals
= save_target_globals_default_opts ();
16805 restore_target_globals (mips16_globals
);
16808 restore_target_globals (&default_target_globals
);
16810 old_compression_mode
= compression_mode
;
16813 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
16814 function should use the MIPS16 or microMIPS ISA and switch modes
16818 mips_set_current_function (tree fndecl
)
16820 mips_set_compression_mode (mips_get_compress_mode (fndecl
));
16823 /* Allocate a chunk of memory for per-function machine-dependent data. */
16825 static struct machine_function
*
16826 mips_init_machine_status (void)
16828 return ggc_alloc_cleared_machine_function ();
16831 /* Return the processor associated with the given ISA level, or null
16832 if the ISA isn't valid. */
16834 static const struct mips_cpu_info
*
16835 mips_cpu_info_from_isa (int isa
)
16839 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
16840 if (mips_cpu_info_table
[i
].isa
== isa
)
16841 return mips_cpu_info_table
+ i
;
16846 /* Return a mips_cpu_info entry determined by an option valued
16849 static const struct mips_cpu_info
*
16850 mips_cpu_info_from_opt (int opt
)
16854 case MIPS_ARCH_OPTION_FROM_ABI
:
16855 /* 'from-abi' selects the most compatible architecture for the
16856 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
16857 ABIs. For the EABIs, we have to decide whether we're using
16858 the 32-bit or 64-bit version. */
16859 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
16860 : ABI_NEEDS_64BIT_REGS
? 3
16861 : (TARGET_64BIT
? 3 : 1));
16863 case MIPS_ARCH_OPTION_NATIVE
:
16864 gcc_unreachable ();
16867 return &mips_cpu_info_table
[opt
];
16871 /* Return a default mips_cpu_info entry, given that no -march= option
16872 was explicitly specified. */
16874 static const struct mips_cpu_info
*
16875 mips_default_arch (void)
16877 #if defined (MIPS_CPU_STRING_DEFAULT)
16879 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
16880 if (strcmp (mips_cpu_info_table
[i
].name
, MIPS_CPU_STRING_DEFAULT
) == 0)
16881 return mips_cpu_info_table
+ i
;
16882 gcc_unreachable ();
16883 #elif defined (MIPS_ISA_DEFAULT)
16884 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
);
16886 /* 'from-abi' makes a good default: you get whatever the ABI
16888 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI
);
16892 /* Set up globals to generate code for the ISA or processor
16893 described by INFO. */
16896 mips_set_architecture (const struct mips_cpu_info
*info
)
16900 mips_arch_info
= info
;
16901 mips_arch
= info
->cpu
;
16902 mips_isa
= info
->isa
;
16906 /* Likewise for tuning. */
16909 mips_set_tune (const struct mips_cpu_info
*info
)
16913 mips_tune_info
= info
;
16914 mips_tune
= info
->cpu
;
16918 /* Implement TARGET_OPTION_OVERRIDE. */
16921 mips_option_override (void)
16923 int i
, start
, regno
, mode
;
16925 if (global_options_set
.x_mips_isa_option
)
16926 mips_isa_option_info
= &mips_cpu_info_table
[mips_isa_option
];
16928 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16929 SUBTARGET_OVERRIDE_OPTIONS
;
16932 /* MIPS16 and microMIPS cannot coexist. */
16933 if (TARGET_MICROMIPS
&& TARGET_MIPS16
)
16934 error ("unsupported combination: %s", "-mips16 -mmicromips");
16936 /* Save the base compression state and process flags as though we
16937 were generating uncompressed code. */
16938 mips_base_compression_flags
= TARGET_COMPRESSION
;
16939 target_flags
&= ~TARGET_COMPRESSION
;
16941 /* -mno-float overrides -mhard-float and -msoft-float. */
16942 if (TARGET_NO_FLOAT
)
16944 target_flags
|= MASK_SOFT_FLOAT_ABI
;
16945 target_flags_explicit
|= MASK_SOFT_FLOAT_ABI
;
16948 if (TARGET_FLIP_MIPS16
)
16949 TARGET_INTERLINK_COMPRESSED
= 1;
16951 /* Set the small data limit. */
16952 mips_small_data_threshold
= (global_options_set
.x_g_switch_value
16954 : MIPS_DEFAULT_GVALUE
);
16956 /* The following code determines the architecture and register size.
16957 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
16958 The GAS and GCC code should be kept in sync as much as possible. */
16960 if (global_options_set
.x_mips_arch_option
)
16961 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option
));
16963 if (mips_isa_option_info
!= 0)
16965 if (mips_arch_info
== 0)
16966 mips_set_architecture (mips_isa_option_info
);
16967 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
16968 error ("%<-%s%> conflicts with the other architecture options, "
16969 "which specify a %s processor",
16970 mips_isa_option_info
->name
,
16971 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
16974 if (mips_arch_info
== 0)
16975 mips_set_architecture (mips_default_arch ());
16977 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
16978 error ("%<-march=%s%> is not compatible with the selected ABI",
16979 mips_arch_info
->name
);
16981 /* Optimize for mips_arch, unless -mtune selects a different processor. */
16982 if (global_options_set
.x_mips_tune_option
)
16983 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option
));
16985 if (mips_tune_info
== 0)
16986 mips_set_tune (mips_arch_info
);
16988 if ((target_flags_explicit
& MASK_64BIT
) != 0)
16990 /* The user specified the size of the integer registers. Make sure
16991 it agrees with the ABI and ISA. */
16992 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
16993 error ("%<-mgp64%> used with a 32-bit processor");
16994 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
16995 error ("%<-mgp32%> used with a 64-bit ABI");
16996 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
16997 error ("%<-mgp64%> used with a 32-bit ABI");
17001 /* Infer the integer register size from the ABI and processor.
17002 Restrict ourselves to 32-bit registers if that's all the
17003 processor has, or if the ABI cannot handle 64-bit registers. */
17004 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
17005 target_flags
&= ~MASK_64BIT
;
17007 target_flags
|= MASK_64BIT
;
17010 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
17012 if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
17013 error ("unsupported combination: %s", "-mfp64 -msingle-float");
17014 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
17015 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
17016 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
17018 if (!ISA_HAS_MXHC1
)
17019 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
17020 " the target supports the mfhc1 and mthc1 instructions");
17021 else if (mips_abi
!= ABI_32
)
17022 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
17028 /* -msingle-float selects 32-bit float registers. Otherwise the
17029 float registers should be the same size as the integer ones. */
17030 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
17031 target_flags
|= MASK_FLOAT64
;
17033 target_flags
&= ~MASK_FLOAT64
;
17036 /* End of code shared with GAS. */
17038 /* The R5900 FPU only supports single precision. */
17039 if (TARGET_MIPS5900
&& TARGET_HARD_FLOAT_ABI
&& TARGET_DOUBLE_FLOAT
)
17040 error ("unsupported combination: %s",
17041 "-march=r5900 -mhard-float -mdouble-float");
17043 /* If a -mlong* option was given, check that it matches the ABI,
17044 otherwise infer the -mlong* setting from the other options. */
17045 if ((target_flags_explicit
& MASK_LONG64
) != 0)
17049 if (mips_abi
== ABI_N32
)
17050 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
17051 else if (mips_abi
== ABI_32
)
17052 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
17053 else if (mips_abi
== ABI_O64
&& TARGET_ABICALLS
)
17054 /* We have traditionally allowed non-abicalls code to use
17055 an LP64 form of o64. However, it would take a bit more
17056 effort to support the combination of 32-bit GOT entries
17057 and 64-bit pointers, so we treat the abicalls case as
17059 error ("the combination of %qs and %qs is incompatible with %qs",
17060 "-mabi=o64", "-mabicalls", "-mlong64");
17064 if (mips_abi
== ABI_64
)
17065 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
17070 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
17071 target_flags
|= MASK_LONG64
;
17073 target_flags
&= ~MASK_LONG64
;
17076 if (!TARGET_OLDABI
)
17077 flag_pcc_struct_return
= 0;
17079 /* Decide which rtx_costs structure to use. */
17081 mips_cost
= &mips_rtx_cost_optimize_size
;
17083 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
17085 /* If the user hasn't specified a branch cost, use the processor's
17087 if (mips_branch_cost
== 0)
17088 mips_branch_cost
= mips_cost
->branch_cost
;
17090 /* If neither -mbranch-likely nor -mno-branch-likely was given
17091 on the command line, set MASK_BRANCHLIKELY based on the target
17092 architecture and tuning flags. Annulled delay slots are a
17093 size win, so we only consider the processor-specific tuning
17094 for !optimize_size. */
17095 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
17097 if (ISA_HAS_BRANCHLIKELY
17099 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
17100 target_flags
|= MASK_BRANCHLIKELY
;
17102 target_flags
&= ~MASK_BRANCHLIKELY
;
17104 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
17105 warning (0, "the %qs architecture does not support branch-likely"
17106 " instructions", mips_arch_info
->name
);
17108 /* If the user hasn't specified -mimadd or -mno-imadd set
17109 MASK_IMADD based on the target architecture and tuning
17111 if ((target_flags_explicit
& MASK_IMADD
) == 0)
17113 if (ISA_HAS_MADD_MSUB
&&
17114 (mips_tune_info
->tune_flags
& PTF_AVOID_IMADD
) == 0)
17115 target_flags
|= MASK_IMADD
;
17117 target_flags
&= ~MASK_IMADD
;
17119 else if (TARGET_IMADD
&& !ISA_HAS_MADD_MSUB
)
17120 warning (0, "the %qs architecture does not support madd or msub"
17121 " instructions", mips_arch_info
->name
);
17123 /* The effect of -mabicalls isn't defined for the EABI. */
17124 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
17126 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
17127 target_flags
&= ~MASK_ABICALLS
;
17130 /* PIC requires -mabicalls. */
17133 if (mips_abi
== ABI_EABI
)
17134 error ("cannot generate position-independent code for %qs",
17136 else if (!TARGET_ABICALLS
)
17137 error ("position-independent code requires %qs", "-mabicalls");
17140 if (TARGET_ABICALLS_PIC2
)
17141 /* We need to set flag_pic for executables as well as DSOs
17142 because we may reference symbols that are not defined in
17143 the final executable. (MIPS does not use things like
17144 copy relocs, for example.)
17146 There is a body of code that uses __PIC__ to distinguish
17147 between -mabicalls and -mno-abicalls code. The non-__PIC__
17148 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
17149 long as any indirect jumps use $25. */
17152 /* -mvr4130-align is a "speed over size" optimization: it usually produces
17153 faster code, but at the expense of more nops. Enable it at -O3 and
17155 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
17156 target_flags
|= MASK_VR4130_ALIGN
;
17158 /* Prefer a call to memcpy over inline code when optimizing for size,
17159 though see MOVE_RATIO in mips.h. */
17160 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
17161 target_flags
|= MASK_MEMCPY
;
17163 /* If we have a nonzero small-data limit, check that the -mgpopt
17164 setting is consistent with the other target flags. */
17165 if (mips_small_data_threshold
> 0)
17169 if (!TARGET_EXPLICIT_RELOCS
)
17170 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
17172 TARGET_LOCAL_SDATA
= false;
17173 TARGET_EXTERN_SDATA
= false;
17177 if (TARGET_VXWORKS_RTP
)
17178 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
17180 if (TARGET_ABICALLS
)
17181 warning (0, "cannot use small-data accesses for %qs",
17186 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
17187 for all its floating point. */
17188 if (mips_nan
!= MIPS_IEEE_754_2008
)
17190 REAL_MODE_FORMAT (SFmode
) = &mips_single_format
;
17191 REAL_MODE_FORMAT (DFmode
) = &mips_double_format
;
17192 REAL_MODE_FORMAT (TFmode
) = &mips_quad_format
;
17195 /* Make sure that the user didn't turn off paired single support when
17196 MIPS-3D support is requested. */
17198 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
17199 && !TARGET_PAIRED_SINGLE_FLOAT
)
17200 error ("%<-mips3d%> requires %<-mpaired-single%>");
17202 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
17204 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
17206 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
17207 and TARGET_HARD_FLOAT_ABI are both true. */
17208 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
17210 error ("%qs must be used with %qs",
17211 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
17212 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
17213 target_flags
&= ~MASK_PAIRED_SINGLE_FLOAT
;
17217 /* Make sure that -mpaired-single is only used on ISAs that support it.
17218 We must disable it otherwise since it relies on other ISA properties
17219 like ISA_HAS_8CC having their normal values. */
17220 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
17222 error ("the %qs architecture does not support paired-single"
17223 " instructions", mips_arch_info
->name
);
17224 target_flags
&= ~MASK_PAIRED_SINGLE_FLOAT
;
17228 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
17229 && !TARGET_CACHE_BUILTIN
)
17231 error ("%qs requires a target that provides the %qs instruction",
17232 "-mr10k-cache-barrier", "cache");
17233 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
17236 /* If TARGET_DSPR2, enable TARGET_DSP. */
17240 /* .eh_frame addresses should be the same width as a C pointer.
17241 Most MIPS ABIs support only one pointer size, so the assembler
17242 will usually know exactly how big an .eh_frame address is.
17244 Unfortunately, this is not true of the 64-bit EABI. The ABI was
17245 originally defined to use 64-bit pointers (i.e. it is LP64), and
17246 this is still the default mode. However, we also support an n32-like
17247 ILP32 mode, which is selected by -mlong32. The problem is that the
17248 assembler has traditionally not had an -mlong option, so it has
17249 traditionally not known whether we're using the ILP32 or LP64 form.
17251 As it happens, gas versions up to and including 2.19 use _32-bit_
17252 addresses for EABI64 .cfi_* directives. This is wrong for the
17253 default LP64 mode, so we can't use the directives by default.
17254 Moreover, since gas's current behavior is at odds with gcc's
17255 default behavior, it seems unwise to rely on future versions
17256 of gas behaving the same way. We therefore avoid using .cfi
17257 directives for -mlong32 as well. */
17258 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
17259 flag_dwarf2_cfi_asm
= 0;
17261 /* .cfi_* directives generate a read-only section, so fall back on
17262 manual .eh_frame creation if we need the section to be writable. */
17263 if (TARGET_WRITABLE_EH_FRAME
)
17264 flag_dwarf2_cfi_asm
= 0;
17266 mips_init_print_operand_punct ();
17268 /* Set up array to map GCC register number to debug register number.
17269 Ignore the special purpose register numbers. */
17271 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
17273 mips_dbx_regno
[i
] = IGNORED_DWARF_REGNUM
;
17274 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
17275 mips_dwarf_regno
[i
] = i
;
17277 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
17280 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
17281 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
17282 mips_dbx_regno
[i
] = i
+ start
;
17284 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
17285 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
17286 mips_dbx_regno
[i
] = i
+ start
;
17288 /* Accumulator debug registers use big-endian ordering. */
17289 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
17290 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
17291 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
17292 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
17293 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
17295 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
17296 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
17299 /* Set up mips_hard_regno_mode_ok. */
17300 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
17301 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
17302 mips_hard_regno_mode_ok
[mode
][regno
]
17303 = mips_hard_regno_mode_ok_p (regno
, (enum machine_mode
) mode
);
17305 /* Function to allocate machine-dependent function status. */
17306 init_machine_status
= &mips_init_machine_status
;
17308 /* Default to working around R4000 errata only if the processor
17309 was selected explicitly. */
17310 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
17311 && strcmp (mips_arch_info
->name
, "r4000") == 0)
17312 target_flags
|= MASK_FIX_R4000
;
17314 /* Default to working around R4400 errata only if the processor
17315 was selected explicitly. */
17316 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
17317 && strcmp (mips_arch_info
->name
, "r4400") == 0)
17318 target_flags
|= MASK_FIX_R4400
;
17320 /* Default to working around R10000 errata only if the processor
17321 was selected explicitly. */
17322 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
17323 && strcmp (mips_arch_info
->name
, "r10000") == 0)
17324 target_flags
|= MASK_FIX_R10000
;
17326 /* Make sure that branch-likely instructions available when using
17327 -mfix-r10000. The instructions are not available if either:
17329 1. -mno-branch-likely was passed.
17330 2. The selected ISA does not support branch-likely and
17331 the command line does not include -mbranch-likely. */
17332 if (TARGET_FIX_R10000
17333 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
17334 ? !ISA_HAS_BRANCHLIKELY
17335 : !TARGET_BRANCHLIKELY
))
17336 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
17338 if (TARGET_SYNCI
&& !ISA_HAS_SYNCI
)
17340 warning (0, "the %qs architecture does not support the synci "
17341 "instruction", mips_arch_info
->name
);
17342 target_flags
&= ~MASK_SYNCI
;
17345 /* Only optimize PIC indirect calls if they are actually required. */
17346 if (!TARGET_USE_GOT
|| !TARGET_EXPLICIT_RELOCS
)
17347 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
17349 /* Save base state of options. */
17350 mips_base_target_flags
= target_flags
;
17351 mips_base_schedule_insns
= flag_schedule_insns
;
17352 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
17353 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
17354 mips_base_align_loops
= align_loops
;
17355 mips_base_align_jumps
= align_jumps
;
17356 mips_base_align_functions
= align_functions
;
17358 /* Now select the ISA mode.
17360 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
17361 later if required. */
17362 mips_set_compression_mode (0);
17364 /* We register a second machine specific reorg pass after delay slot
17365 filling. Registering the pass must be done at start up. It's
17366 convenient to do it here. */
17367 opt_pass
*new_pass
= make_pass_mips_machine_reorg2 (g
);
17368 struct register_pass_info insert_pass_mips_machine_reorg2
=
17370 new_pass
, /* pass */
17371 "dbr", /* reference_pass_name */
17372 1, /* ref_pass_instance_number */
17373 PASS_POS_INSERT_AFTER
/* po_op */
17375 register_pass (&insert_pass_mips_machine_reorg2
);
17377 if (TARGET_HARD_FLOAT_ABI
&& TARGET_MIPS5900
)
17378 REAL_MODE_FORMAT (SFmode
) = &spu_single_format
;
17381 /* Swap the register information for registers I and I + 1, which
17382 currently have the wrong endianness. Note that the registers'
17383 fixedness and call-clobberedness might have been set on the
17387 mips_swap_registers (unsigned int i
)
17392 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
17393 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
17395 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
17396 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
17397 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
17398 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
17404 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
17407 mips_conditional_register_usage (void)
17412 /* These DSP control register fields are global. */
17413 global_regs
[CCDSP_PO_REGNUM
] = 1;
17414 global_regs
[CCDSP_SC_REGNUM
] = 1;
17417 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17418 reg_class_contents
[(int) DSP_ACC_REGS
]);
17420 if (!TARGET_HARD_FLOAT
)
17422 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17423 reg_class_contents
[(int) FP_REGS
]);
17424 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17425 reg_class_contents
[(int) ST_REGS
]);
17427 else if (!ISA_HAS_8CC
)
17429 /* We only have a single condition-code register. We implement
17430 this by fixing all the condition-code registers and generating
17431 RTL that refers directly to ST_REG_FIRST. */
17432 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17433 reg_class_contents
[(int) ST_REGS
]);
17434 SET_HARD_REG_BIT (accessible_reg_set
, FPSW_REGNUM
);
17435 fixed_regs
[FPSW_REGNUM
] = call_used_regs
[FPSW_REGNUM
] = 1;
17439 /* In MIPS16 mode, we prohibit the unused $s registers, since they
17440 are call-saved, and saving them via a MIPS16 register would
17441 probably waste more time than just reloading the value.
17443 We permit the $t temporary registers when optimizing for speed
17444 but not when optimizing for space because using them results in
17445 code that is larger (but faster) then not using them. We do
17446 allow $24 (t8) because it is used in CMP and CMPI instructions
17447 and $25 (t9) because it is used as the function call address in
17450 fixed_regs
[18] = call_used_regs
[18] = 1;
17451 fixed_regs
[19] = call_used_regs
[19] = 1;
17452 fixed_regs
[20] = call_used_regs
[20] = 1;
17453 fixed_regs
[21] = call_used_regs
[21] = 1;
17454 fixed_regs
[22] = call_used_regs
[22] = 1;
17455 fixed_regs
[23] = call_used_regs
[23] = 1;
17456 fixed_regs
[26] = call_used_regs
[26] = 1;
17457 fixed_regs
[27] = call_used_regs
[27] = 1;
17458 fixed_regs
[30] = call_used_regs
[30] = 1;
17461 fixed_regs
[8] = call_used_regs
[8] = 1;
17462 fixed_regs
[9] = call_used_regs
[9] = 1;
17463 fixed_regs
[10] = call_used_regs
[10] = 1;
17464 fixed_regs
[11] = call_used_regs
[11] = 1;
17465 fixed_regs
[12] = call_used_regs
[12] = 1;
17466 fixed_regs
[13] = call_used_regs
[13] = 1;
17467 fixed_regs
[14] = call_used_regs
[14] = 1;
17468 fixed_regs
[15] = call_used_regs
[15] = 1;
17471 /* Do not allow HI and LO to be treated as register operands.
17472 There are no MTHI or MTLO instructions (or any real need
17473 for them) and one-way registers cannot easily be reloaded. */
17474 AND_COMPL_HARD_REG_SET (operand_reg_set
,
17475 reg_class_contents
[(int) MD_REGS
]);
17477 /* $f20-$f23 are call-clobbered for n64. */
17478 if (mips_abi
== ABI_64
)
17481 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
17482 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17484 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
17486 if (mips_abi
== ABI_N32
)
17489 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
17490 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17492 /* Make sure that double-register accumulator values are correctly
17493 ordered for the current endianness. */
17494 if (TARGET_LITTLE_ENDIAN
)
17496 unsigned int regno
;
17498 mips_swap_registers (MD_REG_FIRST
);
17499 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
17500 mips_swap_registers (regno
);
17504 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
17505 other registers for instructions for which it is possible. This
17506 encourages the compiler to use CMP in cases where an XOR would
17507 require some register shuffling. */
17510 mips_order_regs_for_local_alloc (void)
17514 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
17515 reg_alloc_order
[i
] = i
;
17519 /* It really doesn't matter where we put register 0, since it is
17520 a fixed register anyhow. */
17521 reg_alloc_order
[0] = 24;
17522 reg_alloc_order
[24] = 0;
17526 /* Implement EH_USES. */
17529 mips_eh_uses (unsigned int regno
)
17531 if (reload_completed
&& !TARGET_ABSOLUTE_JUMPS
)
17533 /* We need to force certain registers to be live in order to handle
17534 PIC long branches correctly. See mips_must_initialize_gp_p for
17536 if (mips_cfun_has_cprestore_slot_p ())
17538 if (regno
== CPRESTORE_SLOT_REGNUM
)
17543 if (cfun
->machine
->global_pointer
== regno
)
17551 /* Implement EPILOGUE_USES. */
17554 mips_epilogue_uses (unsigned int regno
)
17556 /* Say that the epilogue uses the return address register. Note that
17557 in the case of sibcalls, the values "used by the epilogue" are
17558 considered live at the start of the called function. */
17559 if (regno
== RETURN_ADDR_REGNUM
)
17562 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17563 See the comment above load_call<mode> for details. */
17564 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
17567 /* An interrupt handler must preserve some registers that are
17568 ordinarily call-clobbered. */
17569 if (cfun
->machine
->interrupt_handler_p
17570 && mips_interrupt_extra_call_saved_reg_p (regno
))
17576 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
17579 mips_at_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
17581 return REG_P (*x
) && REGNO (*x
) == AT_REGNUM
;
17584 /* Return true if INSN needs to be wrapped in ".set noat".
17585 INSN has NOPERANDS operands, stored in OPVEC. */
17588 mips_need_noat_wrapper_p (rtx insn
, rtx
*opvec
, int noperands
)
17592 if (recog_memoized (insn
) >= 0)
17593 for (i
= 0; i
< noperands
; i
++)
17594 if (for_each_rtx (&opvec
[i
], mips_at_reg_p
, NULL
))
17599 /* Implement FINAL_PRESCAN_INSN. */
17602 mips_final_prescan_insn (rtx insn
, rtx
*opvec
, int noperands
)
17604 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17605 mips_push_asm_switch (&mips_noat
);
17608 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
17611 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED
, rtx insn
,
17612 rtx
*opvec
, int noperands
)
17614 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17615 mips_pop_asm_switch (&mips_noat
);
17618 /* Return the function that is used to expand the <u>mulsidi3 pattern.
17619 EXT_CODE is the code of the extension used. Return NULL if widening
17620 multiplication shouldn't be used. */
17623 mips_mulsidi3_gen_fn (enum rtx_code ext_code
)
17627 signed_p
= ext_code
== SIGN_EXTEND
;
17630 /* Don't use widening multiplication with MULT when we have DMUL. Even
17631 with the extension of its input operands DMUL is faster. Note that
17632 the extension is not needed for signed multiplication. In order to
17633 ensure that we always remove the redundant sign-extension in this
17634 case we still expand mulsidi3 for DMUL. */
17636 return signed_p
? gen_mulsidi3_64bit_dmul
: NULL
;
17639 ? gen_mulsidi3_64bit_mips16
17640 : gen_umulsidi3_64bit_mips16
);
17641 if (TARGET_FIX_R4000
)
17643 return signed_p
? gen_mulsidi3_64bit
: gen_umulsidi3_64bit
;
17649 ? gen_mulsidi3_32bit_mips16
17650 : gen_umulsidi3_32bit_mips16
);
17651 if (TARGET_FIX_R4000
&& !ISA_HAS_DSP
)
17652 return signed_p
? gen_mulsidi3_32bit_r4000
: gen_umulsidi3_32bit_r4000
;
17653 return signed_p
? gen_mulsidi3_32bit
: gen_umulsidi3_32bit
;
17657 /* Return true if PATTERN matches the kind of instruction generated by
17658 umips_build_save_restore. SAVE_P is true for store. */
17661 umips_save_restore_pattern_p (bool save_p
, rtx pattern
)
17665 HOST_WIDE_INT first_offset
= 0;
17666 rtx first_base
= 0;
17667 unsigned int regmask
= 0;
17669 for (n
= 0; n
< XVECLEN (pattern
, 0); n
++)
17671 rtx set
, reg
, mem
, this_base
;
17672 HOST_WIDE_INT this_offset
;
17674 /* Check that we have a SET. */
17675 set
= XVECEXP (pattern
, 0, n
);
17676 if (GET_CODE (set
) != SET
)
17679 /* Check that the SET is a load (if restoring) or a store
17681 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
17682 if (!MEM_P (mem
) || MEM_VOLATILE_P (mem
))
17685 /* Check that the address is the sum of base and a possibly-zero
17686 constant offset. Determine if the offset is in range. */
17687 mips_split_plus (XEXP (mem
, 0), &this_base
, &this_offset
);
17688 if (!REG_P (this_base
))
17693 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
17695 first_base
= this_base
;
17696 first_offset
= this_offset
;
17700 /* Check that the save slots are consecutive. */
17701 if (REGNO (this_base
) != REGNO (first_base
)
17702 || this_offset
!= first_offset
+ UNITS_PER_WORD
* n
)
17706 /* Check that SET's other operand is a register. */
17707 reg
= save_p
? SET_SRC (set
) : SET_DEST (set
);
17711 regmask
|= 1 << REGNO (reg
);
17714 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
17715 if (regmask
== umips_swm_mask
[i
])
17721 /* Return the assembly instruction for microMIPS LWM or SWM.
17722 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
17725 umips_output_save_restore (bool save_p
, rtx pattern
)
17727 static char buffer
[300];
17730 HOST_WIDE_INT offset
;
17731 rtx base
, mem
, set
, last_set
, last_reg
;
17733 /* Parse the pattern. */
17734 gcc_assert (umips_save_restore_pattern_p (save_p
, pattern
));
17736 s
= strcpy (buffer
, save_p
? "swm\t" : "lwm\t");
17738 n
= XVECLEN (pattern
, 0);
17740 set
= XVECEXP (pattern
, 0, 0);
17741 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
17742 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
17744 last_set
= XVECEXP (pattern
, 0, n
- 1);
17745 last_reg
= save_p
? SET_SRC (last_set
) : SET_DEST (last_set
);
17747 if (REGNO (last_reg
) == 31)
17750 gcc_assert (n
<= 9);
17754 s
+= sprintf (s
, "%s,", reg_names
[16]);
17756 s
+= sprintf (s
, "%s-%s,", reg_names
[16], reg_names
[15 + n
]);
17758 s
+= sprintf (s
, "%s-%s,%s,", reg_names
[16], reg_names
[23],
17761 if (REGNO (last_reg
) == 31)
17762 s
+= sprintf (s
, "%s,", reg_names
[31]);
17764 s
+= sprintf (s
, "%d(%s)", (int)offset
, reg_names
[REGNO (base
)]);
17768 /* Return true if MEM1 and MEM2 use the same base register, and the
17769 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
17770 register into (from) which the contents of MEM1 will be loaded
17771 (stored), depending on the value of LOAD_P.
17772 SWAP_P is true when the 1st and 2nd instructions are swapped. */
17775 umips_load_store_pair_p_1 (bool load_p
, bool swap_p
,
17776 rtx first_reg
, rtx mem1
, rtx mem2
)
17779 HOST_WIDE_INT offset1
, offset2
;
17781 if (!MEM_P (mem1
) || !MEM_P (mem2
))
17784 mips_split_plus (XEXP (mem1
, 0), &base1
, &offset1
);
17785 mips_split_plus (XEXP (mem2
, 0), &base2
, &offset2
);
17787 if (!REG_P (base1
) || !rtx_equal_p (base1
, base2
))
17790 /* Avoid invalid load pair instructions. */
17791 if (load_p
&& REGNO (first_reg
) == REGNO (base1
))
17794 /* We must avoid this case for anti-dependence.
17797 first_reg is $2, but the base is $3. */
17800 && REGNO (first_reg
) + 1 == REGNO (base1
))
17803 if (offset2
!= offset1
+ 4)
17806 if (!UMIPS_12BIT_OFFSET_P (offset1
))
17812 /* OPERANDS describes the operands to a pair of SETs, in the order
17813 dest1, src1, dest2, src2. Return true if the operands can be used
17814 in an LWP or SWP instruction; LOAD_P says which. */
17817 umips_load_store_pair_p (bool load_p
, rtx
*operands
)
17819 rtx reg1
, reg2
, mem1
, mem2
;
17823 reg1
= operands
[0];
17824 reg2
= operands
[2];
17825 mem1
= operands
[1];
17826 mem2
= operands
[3];
17830 reg1
= operands
[1];
17831 reg2
= operands
[3];
17832 mem1
= operands
[0];
17833 mem2
= operands
[2];
17836 if (REGNO (reg2
) == REGNO (reg1
) + 1)
17837 return umips_load_store_pair_p_1 (load_p
, false, reg1
, mem1
, mem2
);
17839 if (REGNO (reg1
) == REGNO (reg2
) + 1)
17840 return umips_load_store_pair_p_1 (load_p
, true, reg2
, mem2
, mem1
);
17845 /* Return the assembly instruction for a microMIPS LWP or SWP in which
17846 the first register is REG and the first memory slot is MEM.
17847 LOAD_P is true for LWP. */
17850 umips_output_load_store_pair_1 (bool load_p
, rtx reg
, rtx mem
)
17852 rtx ops
[] = {reg
, mem
};
17855 output_asm_insn ("lwp\t%0,%1", ops
);
17857 output_asm_insn ("swp\t%0,%1", ops
);
17860 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
17861 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
17864 umips_output_load_store_pair (bool load_p
, rtx
*operands
)
17866 rtx reg1
, reg2
, mem1
, mem2
;
17869 reg1
= operands
[0];
17870 reg2
= operands
[2];
17871 mem1
= operands
[1];
17872 mem2
= operands
[3];
17876 reg1
= operands
[1];
17877 reg2
= operands
[3];
17878 mem1
= operands
[0];
17879 mem2
= operands
[2];
17882 if (REGNO (reg2
) == REGNO (reg1
) + 1)
17884 umips_output_load_store_pair_1 (load_p
, reg1
, mem1
);
17888 gcc_assert (REGNO (reg1
) == REGNO (reg2
) + 1);
17889 umips_output_load_store_pair_1 (load_p
, reg2
, mem2
);
17892 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
17895 umips_movep_target_p (rtx reg1
, rtx reg2
)
17897 int regno1
, regno2
, pair
;
17899 static const int match
[8] = {
17900 0x00000060, /* 5, 6 */
17901 0x000000a0, /* 5, 7 */
17902 0x000000c0, /* 6, 7 */
17903 0x00200010, /* 4, 21 */
17904 0x00400010, /* 4, 22 */
17905 0x00000030, /* 4, 5 */
17906 0x00000050, /* 4, 6 */
17907 0x00000090 /* 4, 7 */
17910 if (!REG_P (reg1
) || !REG_P (reg2
))
17913 regno1
= REGNO (reg1
);
17914 regno2
= REGNO (reg2
);
17916 if (!GP_REG_P (regno1
) || !GP_REG_P (regno2
))
17919 pair
= (1 << regno1
) | (1 << regno2
);
17921 for (i
= 0; i
< ARRAY_SIZE (match
); i
++)
17922 if (pair
== match
[i
])
17928 /* Return the size in bytes of the trampoline code, padded to
17929 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
17930 function address immediately follow. */
17933 mips_trampoline_code_size (void)
17935 if (TARGET_USE_PIC_FN_ADDR_REG
)
17937 else if (ptr_mode
== DImode
)
17939 else if (ISA_HAS_LOAD_DELAY
)
17945 /* Implement TARGET_TRAMPOLINE_INIT. */
17948 mips_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
17950 rtx addr
, end_addr
, high
, low
, opcode
, mem
;
17953 HOST_WIDE_INT end_addr_offset
, static_chain_offset
, target_function_offset
;
17955 /* Work out the offsets of the pointers from the start of the
17956 trampoline code. */
17957 end_addr_offset
= mips_trampoline_code_size ();
17958 static_chain_offset
= end_addr_offset
;
17959 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
17961 /* Get pointers to the beginning and end of the code block. */
17962 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
17963 end_addr
= mips_force_binary (Pmode
, PLUS
, addr
, GEN_INT (end_addr_offset
));
17965 #define OP(X) gen_int_mode (X, SImode)
17967 /* Build up the code in TRAMPOLINE. */
17969 if (TARGET_USE_PIC_FN_ADDR_REG
)
17971 /* $25 contains the address of the trampoline. Emit code of the form:
17973 l[wd] $1, target_function_offset($25)
17974 l[wd] $static_chain, static_chain_offset($25)
17977 trampoline
[i
++] = OP (MIPS_LOAD_PTR (AT_REGNUM
,
17978 target_function_offset
,
17979 PIC_FUNCTION_ADDR_REGNUM
));
17980 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17981 static_chain_offset
,
17982 PIC_FUNCTION_ADDR_REGNUM
));
17983 trampoline
[i
++] = OP (MIPS_JR (AT_REGNUM
));
17984 trampoline
[i
++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM
, AT_REGNUM
));
17986 else if (ptr_mode
== DImode
)
17988 /* It's too cumbersome to create the full 64-bit address, so let's
17994 1: l[wd] $25, target_function_offset - 12($31)
17995 l[wd] $static_chain, static_chain_offset - 12($31)
17999 where 12 is the offset of "1:" from the start of the code block. */
18000 trampoline
[i
++] = OP (MIPS_MOVE (AT_REGNUM
, RETURN_ADDR_REGNUM
));
18001 trampoline
[i
++] = OP (MIPS_BAL (1));
18002 trampoline
[i
++] = OP (MIPS_NOP
);
18003 trampoline
[i
++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
18004 target_function_offset
- 12,
18005 RETURN_ADDR_REGNUM
));
18006 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
18007 static_chain_offset
- 12,
18008 RETURN_ADDR_REGNUM
));
18009 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
18010 trampoline
[i
++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM
, AT_REGNUM
));
18014 /* If the target has load delays, emit:
18016 lui $1, %hi(end_addr)
18017 lw $25, %lo(end_addr + ...)($1)
18018 lw $static_chain, %lo(end_addr + ...)($1)
18024 lui $1, %hi(end_addr)
18025 lw $25, %lo(end_addr + ...)($1)
18027 lw $static_chain, %lo(end_addr + ...)($1). */
18029 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
18030 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
18031 high
= expand_simple_binop (SImode
, PLUS
, end_addr
, GEN_INT (0x8000),
18032 NULL
, false, OPTAB_WIDEN
);
18033 high
= expand_simple_binop (SImode
, LSHIFTRT
, high
, GEN_INT (16),
18034 NULL
, false, OPTAB_WIDEN
);
18035 low
= convert_to_mode (SImode
, gen_lowpart (HImode
, end_addr
), true);
18037 /* Emit the LUI. */
18038 opcode
= OP (MIPS_LUI (AT_REGNUM
, 0));
18039 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, high
,
18040 NULL
, false, OPTAB_WIDEN
);
18042 /* Emit the load of the target function. */
18043 opcode
= OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
18044 target_function_offset
- end_addr_offset
,
18046 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
18047 NULL
, false, OPTAB_WIDEN
);
18049 /* Emit the JR here, if we can. */
18050 if (!ISA_HAS_LOAD_DELAY
)
18051 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
18053 /* Emit the load of the static chain register. */
18054 opcode
= OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
18055 static_chain_offset
- end_addr_offset
,
18057 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
18058 NULL
, false, OPTAB_WIDEN
);
18060 /* Emit the JR, if we couldn't above. */
18061 if (ISA_HAS_LOAD_DELAY
)
18063 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
18064 trampoline
[i
++] = OP (MIPS_NOP
);
18070 /* Copy the trampoline code. Leave any padding uninitialized. */
18071 for (j
= 0; j
< i
; j
++)
18073 mem
= adjust_address (m_tramp
, SImode
, j
* GET_MODE_SIZE (SImode
));
18074 mips_emit_move (mem
, trampoline
[j
]);
18077 /* Set up the static chain pointer field. */
18078 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
18079 mips_emit_move (mem
, chain_value
);
18081 /* Set up the target function field. */
18082 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
18083 mips_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
18085 /* Flush the code part of the trampoline. */
18086 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
18087 emit_insn (gen_clear_cache (addr
, end_addr
));
18090 /* Implement FUNCTION_PROFILER. */
18092 void mips_function_profiler (FILE *file
)
18095 sorry ("mips16 function profiling");
18096 if (TARGET_LONG_CALLS
)
18098 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
18099 if (Pmode
== DImode
)
18100 fprintf (file
, "\tdla\t%s,_mcount\n", reg_names
[3]);
18102 fprintf (file
, "\tla\t%s,_mcount\n", reg_names
[3]);
18104 mips_push_asm_switch (&mips_noat
);
18105 fprintf (file
, "\tmove\t%s,%s\t\t# save current return address\n",
18106 reg_names
[AT_REGNUM
], reg_names
[RETURN_ADDR_REGNUM
]);
18107 /* _mcount treats $2 as the static chain register. */
18108 if (cfun
->static_chain_decl
!= NULL
)
18109 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[2],
18110 reg_names
[STATIC_CHAIN_REGNUM
]);
18111 if (TARGET_MCOUNT_RA_ADDRESS
)
18113 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
18114 ra save location. */
18115 if (cfun
->machine
->frame
.ra_fp_offset
== 0)
18116 /* ra not saved, pass zero. */
18117 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[12], reg_names
[0]);
18119 fprintf (file
, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC
"(%s)\n",
18120 Pmode
== DImode
? "dla" : "la", reg_names
[12],
18121 cfun
->machine
->frame
.ra_fp_offset
,
18122 reg_names
[STACK_POINTER_REGNUM
]);
18124 if (!TARGET_NEWABI
)
18126 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
18127 TARGET_64BIT
? "dsubu" : "subu",
18128 reg_names
[STACK_POINTER_REGNUM
],
18129 reg_names
[STACK_POINTER_REGNUM
],
18130 Pmode
== DImode
? 16 : 8);
18132 if (TARGET_LONG_CALLS
)
18133 fprintf (file
, "\tjalr\t%s\n", reg_names
[3]);
18135 fprintf (file
, "\tjal\t_mcount\n");
18136 mips_pop_asm_switch (&mips_noat
);
18137 /* _mcount treats $2 as the static chain register. */
18138 if (cfun
->static_chain_decl
!= NULL
)
18139 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[STATIC_CHAIN_REGNUM
],
18143 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
18144 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
18145 when TARGET_LOONGSON_VECTORS is true. */
18147 static unsigned HOST_WIDE_INT
18148 mips_shift_truncation_mask (enum machine_mode mode
)
18150 if (TARGET_LOONGSON_VECTORS
&& VECTOR_MODE_P (mode
))
18153 return GET_MODE_BITSIZE (mode
) - 1;
18156 /* Implement TARGET_PREPARE_PCH_SAVE. */
18159 mips_prepare_pch_save (void)
18161 /* We are called in a context where the current MIPS16 vs. non-MIPS16
18162 setting should be irrelevant. The question then is: which setting
18163 makes most sense at load time?
18165 The PCH is loaded before the first token is read. We should never
18166 have switched into MIPS16 mode by that point, and thus should not
18167 have populated mips16_globals. Nor can we load the entire contents
18168 of mips16_globals from the PCH file, because mips16_globals contains
18169 a combination of GGC and non-GGC data.
18171 There is therefore no point in trying save the GGC part of
18172 mips16_globals to the PCH file, or to preserve MIPS16ness across
18173 the PCH save and load. The loading compiler would not have access
18174 to the non-GGC parts of mips16_globals (either from the PCH file,
18175 or from a copy that the loading compiler generated itself) and would
18176 have to call target_reinit anyway.
18178 It therefore seems best to switch back to non-MIPS16 mode at
18179 save time, and to ensure that mips16_globals remains null after
18181 mips_set_compression_mode (0);
18182 mips16_globals
= 0;
18185 /* Generate or test for an insn that supports a constant permutation. */
18187 #define MAX_VECT_LEN 8
18189 struct expand_vec_perm_d
18191 rtx target
, op0
, op1
;
18192 unsigned char perm
[MAX_VECT_LEN
];
18193 enum machine_mode vmode
;
18194 unsigned char nelt
;
18199 /* Construct (set target (vec_select op0 (parallel perm))) and
18200 return true if that's a valid instruction in the active ISA. */
18203 mips_expand_vselect (rtx target
, rtx op0
,
18204 const unsigned char *perm
, unsigned nelt
)
18206 rtx rperm
[MAX_VECT_LEN
], x
;
18209 for (i
= 0; i
< nelt
; ++i
)
18210 rperm
[i
] = GEN_INT (perm
[i
]);
18212 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nelt
, rperm
));
18213 x
= gen_rtx_VEC_SELECT (GET_MODE (target
), op0
, x
);
18214 x
= gen_rtx_SET (VOIDmode
, target
, x
);
18217 if (recog_memoized (x
) < 0)
18225 /* Similar, but generate a vec_concat from op0 and op1 as well. */
18228 mips_expand_vselect_vconcat (rtx target
, rtx op0
, rtx op1
,
18229 const unsigned char *perm
, unsigned nelt
)
18231 enum machine_mode v2mode
;
18234 v2mode
= GET_MODE_2XWIDER_MODE (GET_MODE (op0
));
18235 x
= gen_rtx_VEC_CONCAT (v2mode
, op0
, op1
);
18236 return mips_expand_vselect (target
, x
, perm
, nelt
);
18239 /* Recognize patterns for even-odd extraction. */
18242 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d
*d
)
18244 unsigned i
, odd
, nelt
= d
->nelt
;
18245 rtx t0
, t1
, t2
, t3
;
18247 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18249 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
18256 for (i
= 1; i
< nelt
; ++i
)
18257 if (d
->perm
[i
] != i
* 2 + odd
)
18263 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
18264 t0
= gen_reg_rtx (d
->vmode
);
18265 t1
= gen_reg_rtx (d
->vmode
);
18269 emit_insn (gen_loongson_punpckhhw (t0
, d
->op0
, d
->op1
));
18270 emit_insn (gen_loongson_punpcklhw (t1
, d
->op0
, d
->op1
));
18272 emit_insn (gen_loongson_punpckhhw (d
->target
, t1
, t0
));
18274 emit_insn (gen_loongson_punpcklhw (d
->target
, t1
, t0
));
18278 t2
= gen_reg_rtx (d
->vmode
);
18279 t3
= gen_reg_rtx (d
->vmode
);
18280 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op1
));
18281 emit_insn (gen_loongson_punpcklbh (t1
, d
->op0
, d
->op1
));
18282 emit_insn (gen_loongson_punpckhbh (t2
, t1
, t0
));
18283 emit_insn (gen_loongson_punpcklbh (t3
, t1
, t0
));
18285 emit_insn (gen_loongson_punpckhbh (d
->target
, t3
, t2
));
18287 emit_insn (gen_loongson_punpcklbh (d
->target
, t3
, t2
));
18291 gcc_unreachable ();
18296 /* Recognize patterns for the Loongson PSHUFH instruction. */
18299 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d
*d
)
18304 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18306 if (d
->vmode
!= V4HImode
)
18311 /* Convert the selector into the packed 8-bit form for pshufh. */
18312 /* Recall that loongson is little-endian only. No big-endian
18313 adjustment required. */
18314 for (i
= mask
= 0; i
< 4; i
++)
18315 mask
|= (d
->perm
[i
] & 3) << (i
* 2);
18316 rmask
= force_reg (SImode
, GEN_INT (mask
));
18318 if (d
->one_vector_p
)
18319 emit_insn (gen_loongson_pshufh (d
->target
, d
->op0
, rmask
));
18322 rtx t0
, t1
, x
, merge
, rmerge
[4];
18324 t0
= gen_reg_rtx (V4HImode
);
18325 t1
= gen_reg_rtx (V4HImode
);
18326 emit_insn (gen_loongson_pshufh (t1
, d
->op1
, rmask
));
18327 emit_insn (gen_loongson_pshufh (t0
, d
->op0
, rmask
));
18329 for (i
= 0; i
< 4; ++i
)
18330 rmerge
[i
] = (d
->perm
[i
] & 4 ? constm1_rtx
: const0_rtx
);
18331 merge
= gen_rtx_CONST_VECTOR (V4HImode
, gen_rtvec_v (4, rmerge
));
18332 merge
= force_reg (V4HImode
, merge
);
18334 x
= gen_rtx_AND (V4HImode
, merge
, t1
);
18335 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
18337 x
= gen_rtx_NOT (V4HImode
, merge
);
18338 x
= gen_rtx_AND (V4HImode
, x
, t0
);
18339 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
18341 x
= gen_rtx_IOR (V4HImode
, t0
, t1
);
18342 emit_insn (gen_rtx_SET (VOIDmode
, d
->target
, x
));
18348 /* Recognize broadcast patterns for the Loongson. */
18351 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d
*d
)
18356 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18358 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
18359 if (d
->vmode
!= V8QImode
)
18361 if (!d
->one_vector_p
)
18365 for (i
= 1; i
< 8; ++i
)
18366 if (d
->perm
[i
] != elt
)
18372 /* With one interleave we put two of the desired element adjacent. */
18373 t0
= gen_reg_rtx (V8QImode
);
18375 emit_insn (gen_loongson_punpcklbh (t0
, d
->op0
, d
->op0
));
18377 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op0
));
18379 /* Shuffle that one HImode element into all locations. */
18382 t1
= gen_reg_rtx (V4HImode
);
18383 emit_insn (gen_loongson_pshufh (t1
, gen_lowpart (V4HImode
, t0
),
18384 force_reg (SImode
, GEN_INT (elt
))));
18386 emit_move_insn (d
->target
, gen_lowpart (V8QImode
, t1
));
18391 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
18393 unsigned int i
, nelt
= d
->nelt
;
18394 unsigned char perm2
[MAX_VECT_LEN
];
18396 if (d
->one_vector_p
)
18398 /* Try interleave with alternating operands. */
18399 memcpy (perm2
, d
->perm
, sizeof(perm2
));
18400 for (i
= 1; i
< nelt
; i
+= 2)
18402 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
, perm2
, nelt
))
18407 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
,
18411 /* Try again with swapped operands. */
18412 for (i
= 0; i
< nelt
; ++i
)
18413 perm2
[i
] = (d
->perm
[i
] + nelt
) & (2 * nelt
- 1);
18414 if (mips_expand_vselect_vconcat (d
->target
, d
->op1
, d
->op0
, perm2
, nelt
))
18418 if (mips_expand_vpc_loongson_even_odd (d
))
18420 if (mips_expand_vpc_loongson_pshufh (d
))
18422 if (mips_expand_vpc_loongson_bcast (d
))
18427 /* Expand a vec_perm_const pattern. */
18430 mips_expand_vec_perm_const (rtx operands
[4])
18432 struct expand_vec_perm_d d
;
18433 int i
, nelt
, which
;
18434 unsigned char orig_perm
[MAX_VECT_LEN
];
18438 d
.target
= operands
[0];
18439 d
.op0
= operands
[1];
18440 d
.op1
= operands
[2];
18443 d
.vmode
= GET_MODE (d
.target
);
18444 gcc_assert (VECTOR_MODE_P (d
.vmode
));
18445 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18446 d
.testing_p
= false;
18448 for (i
= which
= 0; i
< nelt
; ++i
)
18450 rtx e
= XVECEXP (sel
, 0, i
);
18451 int ei
= INTVAL (e
) & (2 * nelt
- 1);
18452 which
|= (ei
< nelt
? 1 : 2);
18455 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18463 d
.one_vector_p
= false;
18464 if (!rtx_equal_p (d
.op0
, d
.op1
))
18469 for (i
= 0; i
< nelt
; ++i
)
18470 d
.perm
[i
] &= nelt
- 1;
18472 d
.one_vector_p
= true;
18477 d
.one_vector_p
= true;
18481 ok
= mips_expand_vec_perm_const_1 (&d
);
18483 /* If we were given a two-vector permutation which just happened to
18484 have both input vectors equal, we folded this into a one-vector
18485 permutation. There are several loongson patterns that are matched
18486 via direct vec_select+vec_concat expansion, but we do not have
18487 support in mips_expand_vec_perm_const_1 to guess the adjustment
18488 that should be made for a single operand. Just try again with
18489 the original permutation. */
18490 if (!ok
&& which
== 3)
18492 d
.op0
= operands
[1];
18493 d
.op1
= operands
[2];
18494 d
.one_vector_p
= false;
18495 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18496 ok
= mips_expand_vec_perm_const_1 (&d
);
18502 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
18505 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
18506 const unsigned char *sel
)
18508 struct expand_vec_perm_d d
;
18509 unsigned int i
, nelt
, which
;
18513 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18514 d
.testing_p
= true;
18515 memcpy (d
.perm
, sel
, nelt
);
18517 /* Categorize the set of elements in the selector. */
18518 for (i
= which
= 0; i
< nelt
; ++i
)
18520 unsigned char e
= d
.perm
[i
];
18521 gcc_assert (e
< 2 * nelt
);
18522 which
|= (e
< nelt
? 1 : 2);
18525 /* For all elements from second vector, fold the elements to first. */
18527 for (i
= 0; i
< nelt
; ++i
)
18530 /* Check whether the mask can be applied to the vector type. */
18531 d
.one_vector_p
= (which
!= 3);
18533 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
18534 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
18535 if (!d
.one_vector_p
)
18536 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
18539 ret
= mips_expand_vec_perm_const_1 (&d
);
18545 /* Expand an integral vector unpack operation. */
18548 mips_expand_vec_unpack (rtx operands
[2], bool unsigned_p
, bool high_p
)
18550 enum machine_mode imode
= GET_MODE (operands
[1]);
18551 rtx (*unpack
) (rtx
, rtx
, rtx
);
18552 rtx (*cmpgt
) (rtx
, rtx
, rtx
);
18553 rtx tmp
, dest
, zero
;
18559 unpack
= gen_loongson_punpckhbh
;
18561 unpack
= gen_loongson_punpcklbh
;
18562 cmpgt
= gen_loongson_pcmpgtb
;
18566 unpack
= gen_loongson_punpckhhw
;
18568 unpack
= gen_loongson_punpcklhw
;
18569 cmpgt
= gen_loongson_pcmpgth
;
18572 gcc_unreachable ();
18575 zero
= force_reg (imode
, CONST0_RTX (imode
));
18580 tmp
= gen_reg_rtx (imode
);
18581 emit_insn (cmpgt (tmp
, zero
, operands
[1]));
18584 dest
= gen_reg_rtx (imode
);
18585 emit_insn (unpack (dest
, operands
[1], tmp
));
18587 emit_move_insn (operands
[0], gen_lowpart (GET_MODE (operands
[0]), dest
));
18590 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
18593 mips_constant_elt_p (rtx x
)
18595 return CONST_INT_P (x
) || GET_CODE (x
) == CONST_DOUBLE
;
18598 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
18601 mips_expand_vi_broadcast (enum machine_mode vmode
, rtx target
, rtx elt
)
18603 struct expand_vec_perm_d d
;
18607 if (elt
!= const0_rtx
)
18608 elt
= force_reg (GET_MODE_INNER (vmode
), elt
);
18610 elt
= gen_lowpart (DImode
, elt
);
18612 t1
= gen_reg_rtx (vmode
);
18616 emit_insn (gen_loongson_vec_init1_v8qi (t1
, elt
));
18619 emit_insn (gen_loongson_vec_init1_v4hi (t1
, elt
));
18622 gcc_unreachable ();
18625 memset (&d
, 0, sizeof (d
));
18630 d
.nelt
= GET_MODE_NUNITS (vmode
);
18631 d
.one_vector_p
= true;
18633 ok
= mips_expand_vec_perm_const_1 (&d
);
18637 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
18638 elements of VALS with zeros, copy the constant vector to TARGET. */
18641 mips_expand_vi_constant (enum machine_mode vmode
, unsigned nelt
,
18642 rtx target
, rtx vals
)
18644 rtvec vec
= shallow_copy_rtvec (XVEC (vals
, 0));
18647 for (i
= 0; i
< nelt
; ++i
)
18649 if (!mips_constant_elt_p (RTVEC_ELT (vec
, i
)))
18650 RTVEC_ELT (vec
, i
) = const0_rtx
;
18653 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, vec
));
18657 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
18660 mips_expand_vi_loongson_one_pinsrh (rtx target
, rtx vals
, unsigned one_var
)
18662 mips_expand_vi_constant (V4HImode
, 4, target
, vals
);
18664 emit_insn (gen_vec_setv4hi (target
, target
, XVECEXP (vals
, 0, one_var
),
18665 GEN_INT (one_var
)));
18668 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
18671 mips_expand_vi_general (enum machine_mode vmode
, enum machine_mode imode
,
18672 unsigned nelt
, unsigned nvar
, rtx target
, rtx vals
)
18674 rtx mem
= assign_stack_temp (vmode
, GET_MODE_SIZE (vmode
));
18675 unsigned int i
, isize
= GET_MODE_SIZE (imode
);
18678 mips_expand_vi_constant (vmode
, nelt
, mem
, vals
);
18680 for (i
= 0; i
< nelt
; ++i
)
18682 rtx x
= XVECEXP (vals
, 0, i
);
18683 if (!mips_constant_elt_p (x
))
18684 emit_move_insn (adjust_address (mem
, imode
, i
* isize
), x
);
18687 emit_move_insn (target
, mem
);
18690 /* Expand a vector initialization. */
18693 mips_expand_vector_init (rtx target
, rtx vals
)
18695 enum machine_mode vmode
= GET_MODE (target
);
18696 enum machine_mode imode
= GET_MODE_INNER (vmode
);
18697 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
18698 unsigned nvar
= 0, one_var
= -1u;
18699 bool all_same
= true;
18702 for (i
= 0; i
< nelt
; ++i
)
18704 x
= XVECEXP (vals
, 0, i
);
18705 if (!mips_constant_elt_p (x
))
18706 nvar
++, one_var
= i
;
18707 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
18711 /* Load constants from the pool, or whatever's handy. */
18714 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, XVEC (vals
, 0)));
18718 /* For two-part initialization, always use CONCAT. */
18721 rtx op0
= force_reg (imode
, XVECEXP (vals
, 0, 0));
18722 rtx op1
= force_reg (imode
, XVECEXP (vals
, 0, 1));
18723 x
= gen_rtx_VEC_CONCAT (vmode
, op0
, op1
);
18724 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
18728 /* Loongson is the only cpu with vectors with more elements. */
18729 gcc_assert (TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
);
18731 /* If all values are identical, broadcast the value. */
18734 mips_expand_vi_broadcast (vmode
, target
, XVECEXP (vals
, 0, 0));
18738 /* If we've only got one non-variable V4HImode, use PINSRH. */
18739 if (nvar
== 1 && vmode
== V4HImode
)
18741 mips_expand_vi_loongson_one_pinsrh (target
, vals
, one_var
);
18745 mips_expand_vi_general (vmode
, imode
, nelt
, nvar
, target
, vals
);
18748 /* Expand a vector reduction. */
18751 mips_expand_vec_reduc (rtx target
, rtx in
, rtx (*gen
)(rtx
, rtx
, rtx
))
18753 enum machine_mode vmode
= GET_MODE (in
);
18754 unsigned char perm2
[2];
18755 rtx last
, next
, fold
, x
;
18759 fold
= gen_reg_rtx (vmode
);
18763 /* Use PUL/PLU to produce { L, H } op { H, L }.
18764 By reversing the pair order, rather than a pure interleave high,
18765 we avoid erroneous exceptional conditions that we might otherwise
18766 produce from the computation of H op H. */
18769 ok
= mips_expand_vselect_vconcat (fold
, last
, last
, perm2
, 2);
18774 /* Use interleave to produce { H, L } op { H, H }. */
18775 emit_insn (gen_loongson_punpckhwd (fold
, last
, last
));
18779 /* Perform the first reduction with interleave,
18780 and subsequent reductions with shifts. */
18781 emit_insn (gen_loongson_punpckhwd_hi (fold
, last
, last
));
18783 next
= gen_reg_rtx (vmode
);
18784 emit_insn (gen (next
, last
, fold
));
18787 fold
= gen_reg_rtx (vmode
);
18788 x
= force_reg (SImode
, GEN_INT (16));
18789 emit_insn (gen_vec_shr_v4hi (fold
, last
, x
));
18793 emit_insn (gen_loongson_punpckhwd_qi (fold
, last
, last
));
18795 next
= gen_reg_rtx (vmode
);
18796 emit_insn (gen (next
, last
, fold
));
18799 fold
= gen_reg_rtx (vmode
);
18800 x
= force_reg (SImode
, GEN_INT (16));
18801 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
18803 next
= gen_reg_rtx (vmode
);
18804 emit_insn (gen (next
, last
, fold
));
18807 fold
= gen_reg_rtx (vmode
);
18808 x
= force_reg (SImode
, GEN_INT (8));
18809 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
18813 gcc_unreachable ();
18816 emit_insn (gen (target
, last
, fold
));
18819 /* Expand a vector minimum/maximum. */
18822 mips_expand_vec_minmax (rtx target
, rtx op0
, rtx op1
,
18823 rtx (*cmp
) (rtx
, rtx
, rtx
), bool min_p
)
18825 enum machine_mode vmode
= GET_MODE (target
);
18828 tc
= gen_reg_rtx (vmode
);
18829 t0
= gen_reg_rtx (vmode
);
18830 t1
= gen_reg_rtx (vmode
);
18833 emit_insn (cmp (tc
, op0
, op1
));
18835 x
= gen_rtx_AND (vmode
, tc
, (min_p
? op1
: op0
));
18836 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
18838 x
= gen_rtx_NOT (vmode
, tc
);
18839 x
= gen_rtx_AND (vmode
, x
, (min_p
? op0
: op1
));
18840 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
18842 x
= gen_rtx_IOR (vmode
, t0
, t1
);
18843 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
18846 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
18849 mips_case_values_threshold (void)
18851 /* In MIPS16 mode using a larger case threshold generates smaller code. */
18852 if (TARGET_MIPS16
&& optimize_size
)
18855 return default_case_values_threshold ();
18858 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
18861 mips_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
18863 if (!TARGET_HARD_FLOAT_ABI
)
18865 tree exceptions_var
= create_tmp_var (MIPS_ATYPE_USI
, NULL
);
18866 tree fcsr_orig_var
= create_tmp_var (MIPS_ATYPE_USI
, NULL
);
18867 tree fcsr_mod_var
= create_tmp_var (MIPS_ATYPE_USI
, NULL
);
18868 tree get_fcsr
= mips_builtin_decls
[MIPS_GET_FCSR
];
18869 tree set_fcsr
= mips_builtin_decls
[MIPS_SET_FCSR
];
18870 tree get_fcsr_hold_call
= build_call_expr (get_fcsr
, 0);
18871 tree hold_assign_orig
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
18872 fcsr_orig_var
, get_fcsr_hold_call
);
18873 tree hold_mod_val
= build2 (BIT_AND_EXPR
, MIPS_ATYPE_USI
, fcsr_orig_var
,
18874 build_int_cst (MIPS_ATYPE_USI
, 0xfffff003));
18875 tree hold_assign_mod
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
18876 fcsr_mod_var
, hold_mod_val
);
18877 tree set_fcsr_hold_call
= build_call_expr (set_fcsr
, 1, fcsr_mod_var
);
18878 tree hold_all
= build2 (COMPOUND_EXPR
, MIPS_ATYPE_USI
,
18879 hold_assign_orig
, hold_assign_mod
);
18880 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, hold_all
,
18881 set_fcsr_hold_call
);
18883 *clear
= build_call_expr (set_fcsr
, 1, fcsr_mod_var
);
18885 tree get_fcsr_update_call
= build_call_expr (get_fcsr
, 0);
18886 *update
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
18887 exceptions_var
, get_fcsr_update_call
);
18888 tree set_fcsr_update_call
= build_call_expr (set_fcsr
, 1, fcsr_orig_var
);
18889 *update
= build2 (COMPOUND_EXPR
, void_type_node
, *update
,
18890 set_fcsr_update_call
);
18891 tree atomic_feraiseexcept
18892 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
18893 tree int_exceptions_var
= fold_convert (integer_type_node
,
18895 tree atomic_feraiseexcept_call
= build_call_expr (atomic_feraiseexcept
,
18896 1, int_exceptions_var
);
18897 *update
= build2 (COMPOUND_EXPR
, void_type_node
, *update
,
18898 atomic_feraiseexcept_call
);
18901 /* Initialize the GCC target structure. */
18902 #undef TARGET_ASM_ALIGNED_HI_OP
18903 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
18904 #undef TARGET_ASM_ALIGNED_SI_OP
18905 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
18906 #undef TARGET_ASM_ALIGNED_DI_OP
18907 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
18909 #undef TARGET_OPTION_OVERRIDE
18910 #define TARGET_OPTION_OVERRIDE mips_option_override
18912 #undef TARGET_LEGITIMIZE_ADDRESS
18913 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
18915 #undef TARGET_ASM_FUNCTION_PROLOGUE
18916 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
18917 #undef TARGET_ASM_FUNCTION_EPILOGUE
18918 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
18919 #undef TARGET_ASM_SELECT_RTX_SECTION
18920 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
18921 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
18922 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
18924 #undef TARGET_SCHED_INIT
18925 #define TARGET_SCHED_INIT mips_sched_init
18926 #undef TARGET_SCHED_REORDER
18927 #define TARGET_SCHED_REORDER mips_sched_reorder
18928 #undef TARGET_SCHED_REORDER2
18929 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
18930 #undef TARGET_SCHED_VARIABLE_ISSUE
18931 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
18932 #undef TARGET_SCHED_ADJUST_COST
18933 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
18934 #undef TARGET_SCHED_ISSUE_RATE
18935 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
18936 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
18937 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
18938 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
18939 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
18940 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
18941 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
18942 mips_multipass_dfa_lookahead
18943 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
18944 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
18945 mips_small_register_classes_for_mode_p
18947 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
18948 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
18950 #undef TARGET_INSERT_ATTRIBUTES
18951 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
18952 #undef TARGET_MERGE_DECL_ATTRIBUTES
18953 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
18954 #undef TARGET_CAN_INLINE_P
18955 #define TARGET_CAN_INLINE_P mips_can_inline_p
18956 #undef TARGET_SET_CURRENT_FUNCTION
18957 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
18959 #undef TARGET_VALID_POINTER_MODE
18960 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
18961 #undef TARGET_REGISTER_MOVE_COST
18962 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
18963 #undef TARGET_MEMORY_MOVE_COST
18964 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
18965 #undef TARGET_RTX_COSTS
18966 #define TARGET_RTX_COSTS mips_rtx_costs
18967 #undef TARGET_ADDRESS_COST
18968 #define TARGET_ADDRESS_COST mips_address_cost
18970 #undef TARGET_IN_SMALL_DATA_P
18971 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
18973 #undef TARGET_MACHINE_DEPENDENT_REORG
18974 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
18976 #undef TARGET_PREFERRED_RELOAD_CLASS
18977 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
18979 #undef TARGET_EXPAND_TO_RTL_HOOK
18980 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
18981 #undef TARGET_ASM_FILE_START
18982 #define TARGET_ASM_FILE_START mips_file_start
18983 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
18984 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
18985 #undef TARGET_ASM_CODE_END
18986 #define TARGET_ASM_CODE_END mips_code_end
18988 #undef TARGET_INIT_LIBFUNCS
18989 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
18991 #undef TARGET_BUILD_BUILTIN_VA_LIST
18992 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
18993 #undef TARGET_EXPAND_BUILTIN_VA_START
18994 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
18995 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
18996 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
18998 #undef TARGET_PROMOTE_FUNCTION_MODE
18999 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
19000 #undef TARGET_PROMOTE_PROTOTYPES
19001 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
19003 #undef TARGET_FUNCTION_VALUE
19004 #define TARGET_FUNCTION_VALUE mips_function_value
19005 #undef TARGET_LIBCALL_VALUE
19006 #define TARGET_LIBCALL_VALUE mips_libcall_value
19007 #undef TARGET_FUNCTION_VALUE_REGNO_P
19008 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
19009 #undef TARGET_RETURN_IN_MEMORY
19010 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
19011 #undef TARGET_RETURN_IN_MSB
19012 #define TARGET_RETURN_IN_MSB mips_return_in_msb
19014 #undef TARGET_ASM_OUTPUT_MI_THUNK
19015 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
19016 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
19017 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
19019 #undef TARGET_PRINT_OPERAND
19020 #define TARGET_PRINT_OPERAND mips_print_operand
19021 #undef TARGET_PRINT_OPERAND_ADDRESS
19022 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
19023 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
19024 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
19026 #undef TARGET_SETUP_INCOMING_VARARGS
19027 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
19028 #undef TARGET_STRICT_ARGUMENT_NAMING
19029 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
19030 #undef TARGET_MUST_PASS_IN_STACK
19031 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
19032 #undef TARGET_PASS_BY_REFERENCE
19033 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
19034 #undef TARGET_CALLEE_COPIES
19035 #define TARGET_CALLEE_COPIES mips_callee_copies
19036 #undef TARGET_ARG_PARTIAL_BYTES
19037 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
19038 #undef TARGET_FUNCTION_ARG
19039 #define TARGET_FUNCTION_ARG mips_function_arg
19040 #undef TARGET_FUNCTION_ARG_ADVANCE
19041 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
19042 #undef TARGET_FUNCTION_ARG_BOUNDARY
19043 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
19045 #undef TARGET_MODE_REP_EXTENDED
19046 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
19048 #undef TARGET_VECTOR_MODE_SUPPORTED_P
19049 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
19051 #undef TARGET_SCALAR_MODE_SUPPORTED_P
19052 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
19054 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
19055 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
19057 #undef TARGET_INIT_BUILTINS
19058 #define TARGET_INIT_BUILTINS mips_init_builtins
19059 #undef TARGET_BUILTIN_DECL
19060 #define TARGET_BUILTIN_DECL mips_builtin_decl
19061 #undef TARGET_EXPAND_BUILTIN
19062 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
19064 #undef TARGET_HAVE_TLS
19065 #define TARGET_HAVE_TLS HAVE_AS_TLS
19067 #undef TARGET_CANNOT_FORCE_CONST_MEM
19068 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
19070 #undef TARGET_LEGITIMATE_CONSTANT_P
19071 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
19073 #undef TARGET_ENCODE_SECTION_INFO
19074 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
19076 #undef TARGET_ATTRIBUTE_TABLE
19077 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
19078 /* All our function attributes are related to how out-of-line copies should
19079 be compiled or called. They don't in themselves prevent inlining. */
19080 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
19081 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
19083 #undef TARGET_EXTRA_LIVE_ON_ENTRY
19084 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
19086 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
19087 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
19088 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
19089 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
19091 #undef TARGET_COMP_TYPE_ATTRIBUTES
19092 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
19094 #ifdef HAVE_AS_DTPRELWORD
19095 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
19096 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
19098 #undef TARGET_DWARF_REGISTER_SPAN
19099 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
19101 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
19102 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
19104 #undef TARGET_LEGITIMATE_ADDRESS_P
19105 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
19107 #undef TARGET_FRAME_POINTER_REQUIRED
19108 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
19110 #undef TARGET_CAN_ELIMINATE
19111 #define TARGET_CAN_ELIMINATE mips_can_eliminate
19113 #undef TARGET_CONDITIONAL_REGISTER_USAGE
19114 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
19116 #undef TARGET_TRAMPOLINE_INIT
19117 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
19119 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
19120 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
19122 #undef TARGET_SHIFT_TRUNCATION_MASK
19123 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
19125 #undef TARGET_PREPARE_PCH_SAVE
19126 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
19128 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
19129 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
19131 #undef TARGET_CASE_VALUES_THRESHOLD
19132 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
19134 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
19135 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV mips_atomic_assign_expand_fenv
19137 struct gcc_target targetm
= TARGET_INITIALIZER
;
19139 #include "gt-mips.h"