1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
26 #include "stor-layout.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
37 #include "diagnostic-core.h"
42 #include "target-def.h"
46 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
47 #include "sched-int.h"
48 #include "insn-codes.h"
53 enum reg_class regno_reg_class
[] =
55 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
56 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
57 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
58 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
59 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
60 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
65 /* The minimum number of integer registers that we want to save with the
66 movem instruction. Using two movel instructions instead of a single
67 moveml is about 15% faster for the 68020 and 68030 at no expense in
69 #define MIN_MOVEM_REGS 3
71 /* The minimum number of floating point registers that we want to save
72 with the fmovem instruction. */
73 #define MIN_FMOVEM_REGS 1
75 /* Structure describing stack frame layout. */
78 /* Stack pointer to frame pointer offset. */
81 /* Offset of FPU registers. */
82 HOST_WIDE_INT foffset
;
84 /* Frame size in bytes (rounded up). */
87 /* Data and address register. */
89 unsigned int reg_mask
;
93 unsigned int fpu_mask
;
95 /* Offsets relative to ARG_POINTER. */
96 HOST_WIDE_INT frame_pointer_offset
;
97 HOST_WIDE_INT stack_pointer_offset
;
99 /* Function which the above information refers to. */
103 /* Current frame information calculated by m68k_compute_frame_layout(). */
104 static struct m68k_frame current_frame
;
106 /* Structure describing an m68k address.
108 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
109 with null fields evaluating to 0. Here:
111 - BASE satisfies m68k_legitimate_base_reg_p
112 - INDEX satisfies m68k_legitimate_index_reg_p
113 - OFFSET satisfies m68k_legitimate_constant_address_p
115 INDEX is either HImode or SImode. The other fields are SImode.
117 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
118 the address is (BASE)+. */
119 struct m68k_address
{
127 static int m68k_sched_adjust_cost (rtx
, rtx
, rtx
, int);
128 static int m68k_sched_issue_rate (void);
129 static int m68k_sched_variable_issue (FILE *, int, rtx
, int);
130 static void m68k_sched_md_init_global (FILE *, int, int);
131 static void m68k_sched_md_finish_global (FILE *, int);
132 static void m68k_sched_md_init (FILE *, int, int);
133 static void m68k_sched_dfa_pre_advance_cycle (void);
134 static void m68k_sched_dfa_post_advance_cycle (void);
135 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
137 static bool m68k_can_eliminate (const int, const int);
138 static void m68k_conditional_register_usage (void);
139 static bool m68k_legitimate_address_p (enum machine_mode
, rtx
, bool);
140 static void m68k_option_override (void);
141 static void m68k_override_options_after_change (void);
142 static rtx
find_addr_reg (rtx
);
143 static const char *singlemove_string (rtx
*);
144 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
145 HOST_WIDE_INT
, tree
);
146 static rtx
m68k_struct_value_rtx (tree
, int);
147 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
148 tree args
, int flags
,
150 static void m68k_compute_frame_layout (void);
151 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
152 static bool m68k_ok_for_sibcall_p (tree
, tree
);
153 static bool m68k_tls_symbol_p (rtx
);
154 static rtx
m68k_legitimize_address (rtx
, rtx
, enum machine_mode
);
155 static bool m68k_rtx_costs (rtx
, int, int, int, int *, bool);
156 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
157 static bool m68k_return_in_memory (const_tree
, const_tree
);
159 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
160 static void m68k_trampoline_init (rtx
, tree
, rtx
);
161 static int m68k_return_pops_args (tree
, tree
, int);
162 static rtx
m68k_delegitimize_address (rtx
);
163 static void m68k_function_arg_advance (cumulative_args_t
, enum machine_mode
,
165 static rtx
m68k_function_arg (cumulative_args_t
, enum machine_mode
,
167 static bool m68k_cannot_force_const_mem (enum machine_mode mode
, rtx x
);
168 static bool m68k_output_addr_const_extra (FILE *, rtx
);
169 static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED
;
171 /* Initialize the GCC target structure. */
173 #if INT_OP_GROUP == INT_OP_DOT_WORD
174 #undef TARGET_ASM_ALIGNED_HI_OP
175 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
178 #if INT_OP_GROUP == INT_OP_NO_DOT
179 #undef TARGET_ASM_BYTE_OP
180 #define TARGET_ASM_BYTE_OP "\tbyte\t"
181 #undef TARGET_ASM_ALIGNED_HI_OP
182 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
183 #undef TARGET_ASM_ALIGNED_SI_OP
184 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
187 #if INT_OP_GROUP == INT_OP_DC
188 #undef TARGET_ASM_BYTE_OP
189 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
190 #undef TARGET_ASM_ALIGNED_HI_OP
191 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
192 #undef TARGET_ASM_ALIGNED_SI_OP
193 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
196 #undef TARGET_ASM_UNALIGNED_HI_OP
197 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
198 #undef TARGET_ASM_UNALIGNED_SI_OP
199 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
201 #undef TARGET_ASM_OUTPUT_MI_THUNK
202 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
203 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
204 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
206 #undef TARGET_ASM_FILE_START_APP_OFF
207 #define TARGET_ASM_FILE_START_APP_OFF true
209 #undef TARGET_LEGITIMIZE_ADDRESS
210 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
212 #undef TARGET_SCHED_ADJUST_COST
213 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
215 #undef TARGET_SCHED_ISSUE_RATE
216 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
218 #undef TARGET_SCHED_VARIABLE_ISSUE
219 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
221 #undef TARGET_SCHED_INIT_GLOBAL
222 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
224 #undef TARGET_SCHED_FINISH_GLOBAL
225 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
227 #undef TARGET_SCHED_INIT
228 #define TARGET_SCHED_INIT m68k_sched_md_init
230 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
231 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
233 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
234 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
236 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
237 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
238 m68k_sched_first_cycle_multipass_dfa_lookahead
240 #undef TARGET_OPTION_OVERRIDE
241 #define TARGET_OPTION_OVERRIDE m68k_option_override
243 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
244 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change
246 #undef TARGET_RTX_COSTS
247 #define TARGET_RTX_COSTS m68k_rtx_costs
249 #undef TARGET_ATTRIBUTE_TABLE
250 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
252 #undef TARGET_PROMOTE_PROTOTYPES
253 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
255 #undef TARGET_STRUCT_VALUE_RTX
256 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
258 #undef TARGET_CANNOT_FORCE_CONST_MEM
259 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
261 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
262 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
264 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
265 #undef TARGET_RETURN_IN_MEMORY
266 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
270 #undef TARGET_HAVE_TLS
271 #define TARGET_HAVE_TLS (true)
273 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
274 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
277 #undef TARGET_LEGITIMATE_ADDRESS_P
278 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
280 #undef TARGET_CAN_ELIMINATE
281 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
283 #undef TARGET_CONDITIONAL_REGISTER_USAGE
284 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
286 #undef TARGET_TRAMPOLINE_INIT
287 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
289 #undef TARGET_RETURN_POPS_ARGS
290 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
292 #undef TARGET_DELEGITIMIZE_ADDRESS
293 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
295 #undef TARGET_FUNCTION_ARG
296 #define TARGET_FUNCTION_ARG m68k_function_arg
298 #undef TARGET_FUNCTION_ARG_ADVANCE
299 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
301 #undef TARGET_LEGITIMATE_CONSTANT_P
302 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
304 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
305 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
307 /* The value stored by TAS. */
308 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
309 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
311 static const struct attribute_spec m68k_attribute_table
[] =
313 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
314 affects_type_identity } */
315 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute
,
317 { "interrupt_handler", 0, 0, true, false, false,
318 m68k_handle_fndecl_attribute
, false },
319 { "interrupt_thread", 0, 0, true, false, false,
320 m68k_handle_fndecl_attribute
, false },
321 { NULL
, 0, 0, false, false, false, NULL
, false }
324 struct gcc_target targetm
= TARGET_INITIALIZER
;
326 /* Base flags for 68k ISAs. */
327 #define FL_FOR_isa_00 FL_ISA_68000
328 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
329 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
330 generated 68881 code for 68020 and 68030 targets unless explicitly told
332 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
333 | FL_BITFIELD | FL_68881 | FL_CAS)
334 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
335 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
337 /* Base flags for ColdFire ISAs. */
338 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
339 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
340 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
341 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
342 /* ISA_C is not upwardly compatible with ISA_B. */
343 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
347 /* Traditional 68000 instruction sets. */
353 /* ColdFire instruction set variants. */
361 /* Information about one of the -march, -mcpu or -mtune arguments. */
362 struct m68k_target_selection
364 /* The argument being described. */
367 /* For -mcpu, this is the device selected by the option.
368 For -mtune and -march, it is a representative device
369 for the microarchitecture or ISA respectively. */
370 enum target_device device
;
372 /* The M68K_DEVICE fields associated with DEVICE. See the comment
373 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
375 enum uarch_type microarch
;
380 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
381 static const struct m68k_target_selection all_devices
[] =
383 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
384 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
385 #include "m68k-devices.def"
387 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
390 /* A list of all ISAs, mapping each one to a representative device.
391 Used for -march selection. */
392 static const struct m68k_target_selection all_isas
[] =
394 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
395 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
396 #include "m68k-isas.def"
398 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
401 /* A list of all microarchitectures, mapping each one to a representative
402 device. Used for -mtune selection. */
403 static const struct m68k_target_selection all_microarchs
[] =
405 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
406 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
407 #include "m68k-microarchs.def"
408 #undef M68K_MICROARCH
409 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
412 /* The entries associated with the -mcpu, -march and -mtune settings,
413 or null for options that have not been used. */
414 const struct m68k_target_selection
*m68k_cpu_entry
;
415 const struct m68k_target_selection
*m68k_arch_entry
;
416 const struct m68k_target_selection
*m68k_tune_entry
;
418 /* Which CPU we are generating code for. */
419 enum target_device m68k_cpu
;
421 /* Which microarchitecture to tune for. */
422 enum uarch_type m68k_tune
;
424 /* Which FPU to use. */
425 enum fpu_type m68k_fpu
;
427 /* The set of FL_* flags that apply to the target processor. */
428 unsigned int m68k_cpu_flags
;
430 /* The set of FL_* flags that apply to the processor to be tuned for. */
431 unsigned int m68k_tune_flags
;
433 /* Asm templates for calling or jumping to an arbitrary symbolic address,
434 or NULL if such calls or jumps are not supported. The address is held
436 const char *m68k_symbolic_call
;
437 const char *m68k_symbolic_jump
;
439 /* Enum variable that corresponds to m68k_symbolic_call values. */
440 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
443 /* Implement TARGET_OPTION_OVERRIDE. */
446 m68k_option_override (void)
448 const struct m68k_target_selection
*entry
;
449 unsigned long target_mask
;
451 if (global_options_set
.x_m68k_arch_option
)
452 m68k_arch_entry
= &all_isas
[m68k_arch_option
];
454 if (global_options_set
.x_m68k_cpu_option
)
455 m68k_cpu_entry
= &all_devices
[(int) m68k_cpu_option
];
457 if (global_options_set
.x_m68k_tune_option
)
458 m68k_tune_entry
= &all_microarchs
[(int) m68k_tune_option
];
466 -march=ARCH should generate code that runs any processor
467 implementing architecture ARCH. -mcpu=CPU should override -march
468 and should generate code that runs on processor CPU, making free
469 use of any instructions that CPU understands. -mtune=UARCH applies
470 on top of -mcpu or -march and optimizes the code for UARCH. It does
471 not change the target architecture. */
474 /* Complain if the -march setting is for a different microarchitecture,
475 or includes flags that the -mcpu setting doesn't. */
477 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
478 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
479 warning (0, "-mcpu=%s conflicts with -march=%s",
480 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
482 entry
= m68k_cpu_entry
;
485 entry
= m68k_arch_entry
;
488 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
490 m68k_cpu_flags
= entry
->flags
;
492 /* Use the architecture setting to derive default values for
496 /* ColdFire is lenient about alignment. */
497 if (!TARGET_COLDFIRE
)
498 target_mask
|= MASK_STRICT_ALIGNMENT
;
500 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
501 target_mask
|= MASK_BITFIELD
;
502 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
503 target_mask
|= MASK_CF_HWDIV
;
504 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
505 target_mask
|= MASK_HARD_FLOAT
;
506 target_flags
|= target_mask
& ~target_flags_explicit
;
508 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
509 m68k_cpu
= entry
->device
;
512 m68k_tune
= m68k_tune_entry
->microarch
;
513 m68k_tune_flags
= m68k_tune_entry
->flags
;
515 #ifdef M68K_DEFAULT_TUNE
516 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
518 enum target_device dev
;
519 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
520 m68k_tune_flags
= all_devices
[dev
].flags
;
525 m68k_tune
= entry
->microarch
;
526 m68k_tune_flags
= entry
->flags
;
529 /* Set the type of FPU. */
530 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
531 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
534 /* Sanity check to ensure that msep-data and mid-sahred-library are not
535 * both specified together. Doing so simply doesn't make sense.
537 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
538 error ("cannot specify both -msep-data and -mid-shared-library");
540 /* If we're generating code for a separate A5 relative data segment,
541 * we've got to enable -fPIC as well. This might be relaxable to
542 * -fpic but it hasn't been tested properly.
544 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
547 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
548 error if the target does not support them. */
549 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
550 error ("-mpcrel -fPIC is not currently supported on selected cpu");
552 /* ??? A historic way of turning on pic, or is this intended to
553 be an embedded thing that doesn't have the same name binding
554 significance that it does on hosted ELF systems? */
555 if (TARGET_PCREL
&& flag_pic
== 0)
560 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
562 m68k_symbolic_jump
= "jra %a0";
564 else if (TARGET_ID_SHARED_LIBRARY
)
565 /* All addresses must be loaded from the GOT. */
567 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
570 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
572 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
575 /* No unconditional long branch */;
576 else if (TARGET_PCREL
)
577 m68k_symbolic_jump
= "bra%.l %c0";
579 m68k_symbolic_jump
= "bra%.l %p0";
580 /* Turn off function cse if we are doing PIC. We always want
581 function call to be done as `bsr foo@PLTPC'. */
582 /* ??? It's traditional to do this for -mpcrel too, but it isn't
583 clear how intentional that is. */
584 flag_no_function_cse
= 1;
587 switch (m68k_symbolic_call_var
)
589 case M68K_SYMBOLIC_CALL_JSR
:
590 m68k_symbolic_call
= "jsr %a0";
593 case M68K_SYMBOLIC_CALL_BSR_C
:
594 m68k_symbolic_call
= "bsr%.l %c0";
597 case M68K_SYMBOLIC_CALL_BSR_P
:
598 m68k_symbolic_call
= "bsr%.l %p0";
601 case M68K_SYMBOLIC_CALL_NONE
:
602 gcc_assert (m68k_symbolic_call
== NULL
);
609 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
610 if (align_labels
> 2)
612 warning (0, "-falign-labels=%d is not supported", align_labels
);
617 warning (0, "-falign-loops=%d is not supported", align_loops
);
622 if (stack_limit_rtx
!= NULL_RTX
&& !TARGET_68020
)
624 warning (0, "-fstack-limit- options are not supported on this cpu");
625 stack_limit_rtx
= NULL_RTX
;
628 SUBTARGET_OVERRIDE_OPTIONS
;
630 /* Setup scheduling options. */
632 m68k_sched_cpu
= CPU_CFV1
;
634 m68k_sched_cpu
= CPU_CFV2
;
636 m68k_sched_cpu
= CPU_CFV3
;
638 m68k_sched_cpu
= CPU_CFV4
;
641 m68k_sched_cpu
= CPU_UNKNOWN
;
642 flag_schedule_insns
= 0;
643 flag_schedule_insns_after_reload
= 0;
644 flag_modulo_sched
= 0;
645 flag_live_range_shrinkage
= 0;
648 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
650 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
651 m68k_sched_mac
= MAC_CF_EMAC
;
652 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
653 m68k_sched_mac
= MAC_CF_MAC
;
655 m68k_sched_mac
= MAC_NO
;
659 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
662 m68k_override_options_after_change (void)
664 if (m68k_sched_cpu
== CPU_UNKNOWN
)
666 flag_schedule_insns
= 0;
667 flag_schedule_insns_after_reload
= 0;
668 flag_modulo_sched
= 0;
669 flag_live_range_shrinkage
= 0;
673 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
674 given argument and NAME is the argument passed to -mcpu. Return NULL
675 if -mcpu was not passed. */
678 m68k_cpp_cpu_ident (const char *prefix
)
682 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
685 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
686 given argument and NAME is the name of the representative device for
687 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
690 m68k_cpp_cpu_family (const char *prefix
)
694 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
697 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
698 "interrupt_handler" attribute and interrupt_thread if FUNC has an
699 "interrupt_thread" attribute. Otherwise, return
700 m68k_fk_normal_function. */
702 enum m68k_function_kind
703 m68k_get_function_kind (tree func
)
707 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
709 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
711 return m68k_fk_interrupt_handler
;
713 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
715 return m68k_fk_interrupt_handler
;
717 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
719 return m68k_fk_interrupt_thread
;
721 return m68k_fk_normal_function
;
724 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
725 struct attribute_spec.handler. */
727 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
728 tree args ATTRIBUTE_UNUSED
,
729 int flags ATTRIBUTE_UNUSED
,
732 if (TREE_CODE (*node
) != FUNCTION_DECL
)
734 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
736 *no_add_attrs
= true;
739 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
741 error ("multiple interrupt attributes not allowed");
742 *no_add_attrs
= true;
746 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
748 error ("interrupt_thread is available only on fido");
749 *no_add_attrs
= true;
756 m68k_compute_frame_layout (void)
760 enum m68k_function_kind func_kind
=
761 m68k_get_function_kind (current_function_decl
);
762 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
763 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
765 /* Only compute the frame once per function.
766 Don't cache information until reload has been completed. */
767 if (current_frame
.funcdef_no
== current_function_funcdef_no
771 current_frame
.size
= (get_frame_size () + 3) & -4;
775 /* Interrupt thread does not need to save any register. */
776 if (!interrupt_thread
)
777 for (regno
= 0; regno
< 16; regno
++)
778 if (m68k_save_reg (regno
, interrupt_handler
))
780 mask
|= 1 << (regno
- D0_REG
);
783 current_frame
.offset
= saved
* 4;
784 current_frame
.reg_no
= saved
;
785 current_frame
.reg_mask
= mask
;
787 current_frame
.foffset
= 0;
789 if (TARGET_HARD_FLOAT
)
791 /* Interrupt thread does not need to save any register. */
792 if (!interrupt_thread
)
793 for (regno
= 16; regno
< 24; regno
++)
794 if (m68k_save_reg (regno
, interrupt_handler
))
796 mask
|= 1 << (regno
- FP0_REG
);
799 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
800 current_frame
.offset
+= current_frame
.foffset
;
802 current_frame
.fpu_no
= saved
;
803 current_frame
.fpu_mask
= mask
;
805 /* Remember what function this frame refers to. */
806 current_frame
.funcdef_no
= current_function_funcdef_no
;
809 /* Worker function for TARGET_CAN_ELIMINATE. */
812 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
814 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
818 m68k_initial_elimination_offset (int from
, int to
)
821 /* The arg pointer points 8 bytes before the start of the arguments,
822 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
823 frame pointer in most frames. */
824 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
825 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
826 return argptr_offset
;
828 m68k_compute_frame_layout ();
830 gcc_assert (to
== STACK_POINTER_REGNUM
);
833 case ARG_POINTER_REGNUM
:
834 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
835 case FRAME_POINTER_REGNUM
:
836 return current_frame
.offset
+ current_frame
.size
;
842 /* Refer to the array `regs_ever_live' to determine which registers
843 to save; `regs_ever_live[I]' is nonzero if register number I
844 is ever used in the function. This function is responsible for
845 knowing which registers should not be saved even if used.
846 Return true if we need to save REGNO. */
849 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
851 if (flag_pic
&& regno
== PIC_REG
)
853 if (crtl
->saves_all_registers
)
855 if (crtl
->uses_pic_offset_table
)
857 /* Reload may introduce constant pool references into a function
858 that thitherto didn't need a PIC register. Note that the test
859 above will not catch that case because we will only set
860 crtl->uses_pic_offset_table when emitting
861 the address reloads. */
862 if (crtl
->uses_const_pool
)
866 if (crtl
->calls_eh_return
)
871 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
872 if (test
== INVALID_REGNUM
)
879 /* Fixed regs we never touch. */
880 if (fixed_regs
[regno
])
883 /* The frame pointer (if it is such) is handled specially. */
884 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
887 /* Interrupt handlers must also save call_used_regs
888 if they are live or when calling nested functions. */
889 if (interrupt_handler
)
891 if (df_regs_ever_live_p (regno
))
894 if (!crtl
->is_leaf
&& call_used_regs
[regno
])
898 /* Never need to save registers that aren't touched. */
899 if (!df_regs_ever_live_p (regno
))
902 /* Otherwise save everything that isn't call-clobbered. */
903 return !call_used_regs
[regno
];
906 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
907 the lowest memory address. COUNT is the number of registers to be
908 moved, with register REGNO + I being moved if bit I of MASK is set.
909 STORE_P specifies the direction of the move and ADJUST_STACK_P says
910 whether or not this is pre-decrement (if STORE_P) or post-increment
911 (if !STORE_P) operation. */
914 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
915 unsigned int count
, unsigned int regno
,
916 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
919 rtx body
, addr
, src
, operands
[2];
920 enum machine_mode mode
;
922 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
923 mode
= reg_raw_mode
[regno
];
928 src
= plus_constant (Pmode
, base
,
930 * GET_MODE_SIZE (mode
)
931 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
932 XVECEXP (body
, 0, i
++) = gen_rtx_SET (VOIDmode
, base
, src
);
935 for (; mask
!= 0; mask
>>= 1, regno
++)
938 addr
= plus_constant (Pmode
, base
, offset
);
939 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
940 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
941 XVECEXP (body
, 0, i
++)
942 = gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
943 offset
+= GET_MODE_SIZE (mode
);
945 gcc_assert (i
== XVECLEN (body
, 0));
947 return emit_insn (body
);
950 /* Make INSN a frame-related instruction. */
953 m68k_set_frame_related (rtx insn
)
958 RTX_FRAME_RELATED_P (insn
) = 1;
959 body
= PATTERN (insn
);
960 if (GET_CODE (body
) == PARALLEL
)
961 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
962 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
965 /* Emit RTL for the "prologue" define_expand. */
968 m68k_expand_prologue (void)
970 HOST_WIDE_INT fsize_with_regs
;
971 rtx limit
, src
, dest
;
973 m68k_compute_frame_layout ();
975 if (flag_stack_usage_info
)
976 current_function_static_stack_size
977 = current_frame
.size
+ current_frame
.offset
;
979 /* If the stack limit is a symbol, we can check it here,
980 before actually allocating the space. */
981 if (crtl
->limit_stack
982 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
984 limit
= plus_constant (Pmode
, stack_limit_rtx
, current_frame
.size
+ 4);
985 if (!m68k_legitimate_constant_p (Pmode
, limit
))
987 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
988 limit
= gen_rtx_REG (Pmode
, D0_REG
);
990 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
991 stack_pointer_rtx
, limit
),
992 stack_pointer_rtx
, limit
,
996 fsize_with_regs
= current_frame
.size
;
999 /* ColdFire's move multiple instructions do not allow pre-decrement
1000 addressing. Add the size of movem saves to the initial stack
1001 allocation instead. */
1002 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1003 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1004 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1005 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1008 if (frame_pointer_needed
)
1010 if (fsize_with_regs
== 0 && TUNE_68040
)
1012 /* On the 68040, two separate moves are faster than link.w 0. */
1013 dest
= gen_frame_mem (Pmode
,
1014 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1015 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1016 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1017 stack_pointer_rtx
));
1019 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1020 m68k_set_frame_related
1021 (emit_insn (gen_link (frame_pointer_rtx
,
1022 GEN_INT (-4 - fsize_with_regs
))));
1025 m68k_set_frame_related
1026 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1027 m68k_set_frame_related
1028 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1030 GEN_INT (-fsize_with_regs
))));
1033 /* If the frame pointer is needed, emit a special barrier that
1034 will prevent the scheduler from moving stores to the frame
1035 before the stack adjustment. */
1036 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1038 else if (fsize_with_regs
!= 0)
1039 m68k_set_frame_related
1040 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1042 GEN_INT (-fsize_with_regs
))));
1044 if (current_frame
.fpu_mask
)
1046 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1048 m68k_set_frame_related
1049 (m68k_emit_movem (stack_pointer_rtx
,
1050 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1051 current_frame
.fpu_no
, FP0_REG
,
1052 current_frame
.fpu_mask
, true, true));
1057 /* If we're using moveml to save the integer registers,
1058 the stack pointer will point to the bottom of the moveml
1059 save area. Find the stack offset of the first FP register. */
1060 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1063 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1064 m68k_set_frame_related
1065 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1066 current_frame
.fpu_no
, FP0_REG
,
1067 current_frame
.fpu_mask
, true, false));
1071 /* If the stack limit is not a symbol, check it here.
1072 This has the disadvantage that it may be too late... */
1073 if (crtl
->limit_stack
)
1075 if (REG_P (stack_limit_rtx
))
1076 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1078 stack_pointer_rtx
, stack_limit_rtx
,
1081 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1082 warning (0, "stack limit expression is not supported");
1085 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1087 /* Store each register separately in the same order moveml does. */
1090 for (i
= 16; i
-- > 0; )
1091 if (current_frame
.reg_mask
& (1 << i
))
1093 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1094 dest
= gen_frame_mem (SImode
,
1095 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1096 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1101 if (TARGET_COLDFIRE
)
1102 /* The required register save space has already been allocated.
1103 The first register should be stored at (%sp). */
1104 m68k_set_frame_related
1105 (m68k_emit_movem (stack_pointer_rtx
, 0,
1106 current_frame
.reg_no
, D0_REG
,
1107 current_frame
.reg_mask
, true, false));
1109 m68k_set_frame_related
1110 (m68k_emit_movem (stack_pointer_rtx
,
1111 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1112 current_frame
.reg_no
, D0_REG
,
1113 current_frame
.reg_mask
, true, true));
1116 if (!TARGET_SEP_DATA
1117 && crtl
->uses_pic_offset_table
)
1118 emit_insn (gen_load_got (pic_offset_table_rtx
));
1121 /* Return true if a simple (return) instruction is sufficient for this
1122 instruction (i.e. if no epilogue is needed). */
1125 m68k_use_return_insn (void)
1127 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1130 m68k_compute_frame_layout ();
1131 return current_frame
.offset
== 0;
1134 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1135 SIBCALL_P says which.
1137 The function epilogue should not depend on the current stack pointer!
1138 It should use the frame pointer only, if there is a frame pointer.
1139 This is mandatory because of alloca; we also take advantage of it to
1140 omit stack adjustments before returning. */
1143 m68k_expand_epilogue (bool sibcall_p
)
1145 HOST_WIDE_INT fsize
, fsize_with_regs
;
1146 bool big
, restore_from_sp
;
1148 m68k_compute_frame_layout ();
1150 fsize
= current_frame
.size
;
1152 restore_from_sp
= false;
1154 /* FIXME : crtl->is_leaf below is too strong.
1155 What we really need to know there is if there could be pending
1156 stack adjustment needed at that point. */
1157 restore_from_sp
= (!frame_pointer_needed
1158 || (!cfun
->calls_alloca
&& crtl
->is_leaf
));
1160 /* fsize_with_regs is the size we need to adjust the sp when
1161 popping the frame. */
1162 fsize_with_regs
= fsize
;
1163 if (TARGET_COLDFIRE
&& restore_from_sp
)
1165 /* ColdFire's move multiple instructions do not allow post-increment
1166 addressing. Add the size of movem loads to the final deallocation
1168 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1169 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1170 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1171 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1174 if (current_frame
.offset
+ fsize
>= 0x8000
1176 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1179 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1180 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1182 /* ColdFire's move multiple instructions do not support the
1183 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1184 stack-based restore. */
1185 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1186 GEN_INT (-(current_frame
.offset
+ fsize
)));
1187 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1188 gen_rtx_REG (Pmode
, A1_REG
),
1189 frame_pointer_rtx
));
1190 restore_from_sp
= true;
1194 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1200 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1202 /* Restore each register separately in the same order moveml does. */
1204 HOST_WIDE_INT offset
;
1206 offset
= current_frame
.offset
+ fsize
;
1207 for (i
= 0; i
< 16; i
++)
1208 if (current_frame
.reg_mask
& (1 << i
))
1214 /* Generate the address -OFFSET(%fp,%a1.l). */
1215 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1216 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1217 addr
= plus_constant (Pmode
, addr
, -offset
);
1219 else if (restore_from_sp
)
1220 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1222 addr
= plus_constant (Pmode
, frame_pointer_rtx
, -offset
);
1223 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1224 gen_frame_mem (SImode
, addr
));
1225 offset
-= GET_MODE_SIZE (SImode
);
1228 else if (current_frame
.reg_mask
)
1231 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1232 gen_rtx_REG (Pmode
, A1_REG
),
1234 -(current_frame
.offset
+ fsize
),
1235 current_frame
.reg_no
, D0_REG
,
1236 current_frame
.reg_mask
, false, false);
1237 else if (restore_from_sp
)
1238 m68k_emit_movem (stack_pointer_rtx
, 0,
1239 current_frame
.reg_no
, D0_REG
,
1240 current_frame
.reg_mask
, false,
1243 m68k_emit_movem (frame_pointer_rtx
,
1244 -(current_frame
.offset
+ fsize
),
1245 current_frame
.reg_no
, D0_REG
,
1246 current_frame
.reg_mask
, false, false);
1249 if (current_frame
.fpu_no
> 0)
1252 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1253 gen_rtx_REG (Pmode
, A1_REG
),
1255 -(current_frame
.foffset
+ fsize
),
1256 current_frame
.fpu_no
, FP0_REG
,
1257 current_frame
.fpu_mask
, false, false);
1258 else if (restore_from_sp
)
1260 if (TARGET_COLDFIRE
)
1264 /* If we used moveml to restore the integer registers, the
1265 stack pointer will still point to the bottom of the moveml
1266 save area. Find the stack offset of the first FP
1268 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1271 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1272 m68k_emit_movem (stack_pointer_rtx
, offset
,
1273 current_frame
.fpu_no
, FP0_REG
,
1274 current_frame
.fpu_mask
, false, false);
1277 m68k_emit_movem (stack_pointer_rtx
, 0,
1278 current_frame
.fpu_no
, FP0_REG
,
1279 current_frame
.fpu_mask
, false, true);
1282 m68k_emit_movem (frame_pointer_rtx
,
1283 -(current_frame
.foffset
+ fsize
),
1284 current_frame
.fpu_no
, FP0_REG
,
1285 current_frame
.fpu_mask
, false, false);
1288 if (frame_pointer_needed
)
1289 emit_insn (gen_unlink (frame_pointer_rtx
));
1290 else if (fsize_with_regs
)
1291 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1293 GEN_INT (fsize_with_regs
)));
1295 if (crtl
->calls_eh_return
)
1296 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1298 EH_RETURN_STACKADJ_RTX
));
1301 emit_jump_insn (ret_rtx
);
1304 /* Return true if X is a valid comparison operator for the dbcc
1307 Note it rejects floating point comparison operators.
1308 (In the future we could use Fdbcc).
1310 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1313 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1315 switch (GET_CODE (x
))
1317 case EQ
: case NE
: case GTU
: case LTU
:
1321 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1323 case GT
: case LT
: case GE
: case LE
:
1324 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1330 /* Return nonzero if flags are currently in the 68881 flag register. */
1332 flags_in_68881 (void)
1334 /* We could add support for these in the future */
1335 return cc_status
.flags
& CC_IN_68881
;
1338 /* Return true if PARALLEL contains register REGNO. */
1340 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1344 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1347 if (GET_CODE (parallel
) != PARALLEL
)
1350 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1354 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1355 if (REG_P (x
) && REGNO (x
) == regno
)
1362 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1365 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1367 enum m68k_function_kind kind
;
1369 /* We cannot use sibcalls for nested functions because we use the
1370 static chain register for indirect calls. */
1371 if (CALL_EXPR_STATIC_CHAIN (exp
))
1374 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1376 /* Check that the return value locations are the same. For
1377 example that we aren't returning a value from the sibling in
1378 a D0 register but then need to transfer it to a A0 register. */
1382 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1384 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1386 /* Check that the values are equal or that the result the callee
1387 function returns is superset of what the current function returns. */
1388 if (!(rtx_equal_p (cfun_value
, call_value
)
1389 || (REG_P (cfun_value
)
1390 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1394 kind
= m68k_get_function_kind (current_function_decl
);
1395 if (kind
== m68k_fk_normal_function
)
1396 /* We can always sibcall from a normal function, because it's
1397 undefined if it is calling an interrupt function. */
1400 /* Otherwise we can only sibcall if the function kind is known to be
1402 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1408 /* On the m68k all args are always pushed. */
1411 m68k_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1412 enum machine_mode mode ATTRIBUTE_UNUSED
,
1413 const_tree type ATTRIBUTE_UNUSED
,
1414 bool named ATTRIBUTE_UNUSED
)
1420 m68k_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
1421 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1423 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1425 *cum
+= (mode
!= BLKmode
1426 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1427 : (int_size_in_bytes (type
) + 3) & ~3);
1430 /* Convert X to a legitimate function call memory reference and return the
1434 m68k_legitimize_call_address (rtx x
)
1436 gcc_assert (MEM_P (x
));
1437 if (call_operand (XEXP (x
, 0), VOIDmode
))
1439 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1442 /* Likewise for sibling calls. */
1445 m68k_legitimize_sibcall_address (rtx x
)
1447 gcc_assert (MEM_P (x
));
1448 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1451 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1452 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1455 /* Convert X to a legitimate address and return it if successful. Otherwise
1458 For the 68000, we handle X+REG by loading X into a register R and
1459 using R+REG. R will go in an address reg and indexing will be used.
1460 However, if REG is a broken-out memory address or multiplication,
1461 nothing needs to be done because REG can certainly go in an address reg. */
1464 m68k_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
1466 if (m68k_tls_symbol_p (x
))
1467 return m68k_legitimize_tls_address (x
);
1469 if (GET_CODE (x
) == PLUS
)
1471 int ch
= (x
) != (oldx
);
1474 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1476 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1479 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1481 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1484 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1488 if (GET_CODE (XEXP (x
, 1)) == REG
1489 && GET_CODE (XEXP (x
, 0)) == REG
)
1491 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1494 x
= force_operand (x
, 0);
1498 if (memory_address_p (mode
, x
))
1501 if (GET_CODE (XEXP (x
, 0)) == REG
1502 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1503 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1504 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1506 rtx temp
= gen_reg_rtx (Pmode
);
1507 rtx val
= force_operand (XEXP (x
, 1), 0);
1508 emit_move_insn (temp
, val
);
1511 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1512 && GET_CODE (XEXP (x
, 0)) == REG
)
1513 x
= force_operand (x
, 0);
1515 else if (GET_CODE (XEXP (x
, 1)) == REG
1516 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1517 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1518 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1520 rtx temp
= gen_reg_rtx (Pmode
);
1521 rtx val
= force_operand (XEXP (x
, 0), 0);
1522 emit_move_insn (temp
, val
);
1525 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1526 && GET_CODE (XEXP (x
, 1)) == REG
)
1527 x
= force_operand (x
, 0);
1535 /* Output a dbCC; jCC sequence. Note we do not handle the
1536 floating point version of this sequence (Fdbcc). We also
1537 do not handle alternative conditions when CC_NO_OVERFLOW is
1538 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1539 kick those out before we get here. */
1542 output_dbcc_and_branch (rtx
*operands
)
1544 switch (GET_CODE (operands
[3]))
1547 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1551 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1555 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1559 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1563 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1567 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1571 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1575 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1579 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1583 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1590 /* If the decrement is to be done in SImode, then we have
1591 to compensate for the fact that dbcc decrements in HImode. */
1592 switch (GET_MODE (operands
[0]))
1595 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1607 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1610 enum rtx_code op_code
= GET_CODE (op
);
1612 /* This does not produce a useful cc. */
1615 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1616 below. Swap the operands and change the op if these requirements
1617 are not fulfilled. */
1618 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1622 operand1
= operand2
;
1624 op_code
= swap_condition (op_code
);
1626 loperands
[0] = operand1
;
1627 if (GET_CODE (operand1
) == REG
)
1628 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1630 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1631 if (operand2
!= const0_rtx
)
1633 loperands
[2] = operand2
;
1634 if (GET_CODE (operand2
) == REG
)
1635 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1637 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1639 loperands
[4] = gen_label_rtx ();
1640 if (operand2
!= const0_rtx
)
1641 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1644 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1645 output_asm_insn ("tst%.l %0", loperands
);
1647 output_asm_insn ("cmp%.w #0,%0", loperands
);
1649 output_asm_insn ("jne %l4", loperands
);
1651 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1652 output_asm_insn ("tst%.l %1", loperands
);
1654 output_asm_insn ("cmp%.w #0,%1", loperands
);
1657 loperands
[5] = dest
;
1662 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1663 CODE_LABEL_NUMBER (loperands
[4]));
1664 output_asm_insn ("seq %5", loperands
);
1668 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1669 CODE_LABEL_NUMBER (loperands
[4]));
1670 output_asm_insn ("sne %5", loperands
);
1674 loperands
[6] = gen_label_rtx ();
1675 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1676 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1677 CODE_LABEL_NUMBER (loperands
[4]));
1678 output_asm_insn ("sgt %5", loperands
);
1679 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1680 CODE_LABEL_NUMBER (loperands
[6]));
1684 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1685 CODE_LABEL_NUMBER (loperands
[4]));
1686 output_asm_insn ("shi %5", loperands
);
1690 loperands
[6] = gen_label_rtx ();
1691 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1692 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1693 CODE_LABEL_NUMBER (loperands
[4]));
1694 output_asm_insn ("slt %5", loperands
);
1695 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1696 CODE_LABEL_NUMBER (loperands
[6]));
1700 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1701 CODE_LABEL_NUMBER (loperands
[4]));
1702 output_asm_insn ("scs %5", loperands
);
1706 loperands
[6] = gen_label_rtx ();
1707 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1708 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1709 CODE_LABEL_NUMBER (loperands
[4]));
1710 output_asm_insn ("sge %5", loperands
);
1711 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1712 CODE_LABEL_NUMBER (loperands
[6]));
1716 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1717 CODE_LABEL_NUMBER (loperands
[4]));
1718 output_asm_insn ("scc %5", loperands
);
1722 loperands
[6] = gen_label_rtx ();
1723 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1724 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1725 CODE_LABEL_NUMBER (loperands
[4]));
1726 output_asm_insn ("sle %5", loperands
);
1727 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1728 CODE_LABEL_NUMBER (loperands
[6]));
1732 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1733 CODE_LABEL_NUMBER (loperands
[4]));
1734 output_asm_insn ("sls %5", loperands
);
1744 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1746 operands
[0] = countop
;
1747 operands
[1] = dataop
;
1749 if (GET_CODE (countop
) == CONST_INT
)
1751 register int count
= INTVAL (countop
);
1752 /* If COUNT is bigger than size of storage unit in use,
1753 advance to the containing unit of same size. */
1754 if (count
> signpos
)
1756 int offset
= (count
& ~signpos
) / 8;
1757 count
= count
& signpos
;
1758 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1760 if (count
== signpos
)
1761 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1763 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1765 /* These three statements used to use next_insns_test_no...
1766 but it appears that this should do the same job. */
1768 && next_insn_tests_no_inequality (insn
))
1771 && next_insn_tests_no_inequality (insn
))
1774 && next_insn_tests_no_inequality (insn
))
1776 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1777 On some m68k variants unfortunately that's slower than btst.
1778 On 68000 and higher, that should also work for all HImode operands. */
1779 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1781 if (count
== 3 && DATA_REG_P (operands
[1])
1782 && next_insn_tests_no_inequality (insn
))
1784 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1785 return "move%.w %1,%%ccr";
1787 if (count
== 2 && DATA_REG_P (operands
[1])
1788 && next_insn_tests_no_inequality (insn
))
1790 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1791 return "move%.w %1,%%ccr";
1793 /* count == 1 followed by bvc/bvs and
1794 count == 0 followed by bcc/bcs are also possible, but need
1795 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1798 cc_status
.flags
= CC_NOT_NEGATIVE
;
1800 return "btst %0,%1";
1803 /* Return true if X is a legitimate base register. STRICT_P says
1804 whether we need strict checking. */
1807 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1809 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1810 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1815 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1816 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1819 /* Return true if X is a legitimate index register. STRICT_P says
1820 whether we need strict checking. */
1823 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1825 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1830 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1831 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1834 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1835 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1836 ADDRESS if so. STRICT_P says whether we need strict checking. */
1839 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1843 /* Check for a scale factor. */
1845 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1846 && GET_CODE (x
) == MULT
1847 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1848 && (INTVAL (XEXP (x
, 1)) == 2
1849 || INTVAL (XEXP (x
, 1)) == 4
1850 || (INTVAL (XEXP (x
, 1)) == 8
1851 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1853 scale
= INTVAL (XEXP (x
, 1));
1857 /* Check for a word extension. */
1858 if (!TARGET_COLDFIRE
1859 && GET_CODE (x
) == SIGN_EXTEND
1860 && GET_MODE (XEXP (x
, 0)) == HImode
)
1863 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1865 address
->scale
= scale
;
1873 /* Return true if X is an illegitimate symbolic constant. */
1876 m68k_illegitimate_symbolic_constant_p (rtx x
)
1880 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1882 split_const (x
, &base
, &offset
);
1883 if (GET_CODE (base
) == SYMBOL_REF
1884 && !offset_within_block_p (base
, INTVAL (offset
)))
1887 return m68k_tls_reference_p (x
, false);
1890 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1893 m68k_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1895 return m68k_illegitimate_symbolic_constant_p (x
);
1898 /* Return true if X is a legitimate constant address that can reach
1899 bytes in the range [X, X + REACH). STRICT_P says whether we need
1903 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1907 if (!CONSTANT_ADDRESS_P (x
))
1911 && !(strict_p
&& TARGET_PCREL
)
1912 && symbolic_operand (x
, VOIDmode
))
1915 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1917 split_const (x
, &base
, &offset
);
1918 if (GET_CODE (base
) == SYMBOL_REF
1919 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1923 return !m68k_tls_reference_p (x
, false);
1926 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1927 labels will become jump tables. */
1930 m68k_jump_table_ref_p (rtx x
)
1932 if (GET_CODE (x
) != LABEL_REF
)
1936 if (!NEXT_INSN (x
) && !PREV_INSN (x
))
1939 x
= next_nonnote_insn (x
);
1940 return x
&& JUMP_TABLE_DATA_P (x
);
1943 /* Return true if X is a legitimate address for values of mode MODE.
1944 STRICT_P says whether strict checking is needed. If the address
1945 is valid, describe its components in *ADDRESS. */
1948 m68k_decompose_address (enum machine_mode mode
, rtx x
,
1949 bool strict_p
, struct m68k_address
*address
)
1953 memset (address
, 0, sizeof (*address
));
1955 if (mode
== BLKmode
)
1958 reach
= GET_MODE_SIZE (mode
);
1960 /* Check for (An) (mode 2). */
1961 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1967 /* Check for -(An) and (An)+ (modes 3 and 4). */
1968 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1969 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1971 address
->code
= GET_CODE (x
);
1972 address
->base
= XEXP (x
, 0);
1976 /* Check for (d16,An) (mode 5). */
1977 if (GET_CODE (x
) == PLUS
1978 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1979 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
1980 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1982 address
->base
= XEXP (x
, 0);
1983 address
->offset
= XEXP (x
, 1);
1987 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1988 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1990 if (GET_CODE (x
) == PLUS
1991 && XEXP (x
, 0) == pic_offset_table_rtx
)
1993 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
1994 they are invalid in this context. */
1995 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
1997 address
->base
= XEXP (x
, 0);
1998 address
->offset
= XEXP (x
, 1);
2003 /* The ColdFire FPU only accepts addressing modes 2-5. */
2004 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2007 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2008 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2009 All these modes are variations of mode 7. */
2010 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
2012 address
->offset
= x
;
2016 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2019 ??? do_tablejump creates these addresses before placing the target
2020 label, so we have to assume that unplaced labels are jump table
2021 references. It seems unlikely that we would ever generate indexed
2022 accesses to unplaced labels in other cases. */
2023 if (GET_CODE (x
) == PLUS
2024 && m68k_jump_table_ref_p (XEXP (x
, 1))
2025 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2027 address
->offset
= XEXP (x
, 1);
2031 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2032 (bd,An,Xn.SIZE*SCALE) addresses. */
2036 /* Check for a nonzero base displacement. */
2037 if (GET_CODE (x
) == PLUS
2038 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2040 address
->offset
= XEXP (x
, 1);
2044 /* Check for a suppressed index register. */
2045 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2051 /* Check for a suppressed base register. Do not allow this case
2052 for non-symbolic offsets as it effectively gives gcc freedom
2053 to treat data registers as base registers, which can generate
2056 && symbolic_operand (address
->offset
, VOIDmode
)
2057 && m68k_decompose_index (x
, strict_p
, address
))
2062 /* Check for a nonzero base displacement. */
2063 if (GET_CODE (x
) == PLUS
2064 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2065 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2067 address
->offset
= XEXP (x
, 1);
2072 /* We now expect the sum of a base and an index. */
2073 if (GET_CODE (x
) == PLUS
)
2075 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2076 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2078 address
->base
= XEXP (x
, 0);
2082 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2083 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2085 address
->base
= XEXP (x
, 1);
2092 /* Return true if X is a legitimate address for values of mode MODE.
2093 STRICT_P says whether strict checking is needed. */
2096 m68k_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2098 struct m68k_address address
;
2100 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2103 /* Return true if X is a memory, describing its address in ADDRESS if so.
2104 Apply strict checking if called during or after reload. */
2107 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2110 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2111 reload_in_progress
|| reload_completed
,
2115 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2118 m68k_legitimate_constant_p (enum machine_mode mode
, rtx x
)
2120 return mode
!= XFmode
&& !m68k_illegitimate_symbolic_constant_p (x
);
2123 /* Return true if X matches the 'Q' constraint. It must be a memory
2124 with a base address and no constant offset or index. */
2127 m68k_matches_q_p (rtx x
)
2129 struct m68k_address address
;
2131 return (m68k_legitimate_mem_p (x
, &address
)
2132 && address
.code
== UNKNOWN
2138 /* Return true if X matches the 'U' constraint. It must be a base address
2139 with a constant offset and no index. */
2142 m68k_matches_u_p (rtx x
)
2144 struct m68k_address address
;
2146 return (m68k_legitimate_mem_p (x
, &address
)
2147 && address
.code
== UNKNOWN
2153 /* Return GOT pointer. */
2158 if (pic_offset_table_rtx
== NULL_RTX
)
2159 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2161 crtl
->uses_pic_offset_table
= 1;
2163 return pic_offset_table_rtx
;
2166 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2168 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2169 RELOC_TLSIE
, RELOC_TLSLE
};
2171 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2173 /* Wrap symbol X into unspec representing relocation RELOC.
2174 BASE_REG - register that should be added to the result.
2175 TEMP_REG - if non-null, temporary register. */
2178 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2182 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2184 if (TARGET_COLDFIRE
&& use_x_p
)
2185 /* When compiling with -mx{got, tls} switch the code will look like this:
2187 move.l <X>@<RELOC>,<TEMP_REG>
2188 add.l <BASE_REG>,<TEMP_REG> */
2190 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2191 to put @RELOC after reference. */
2192 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2194 x
= gen_rtx_CONST (Pmode
, x
);
2196 if (temp_reg
== NULL
)
2198 gcc_assert (can_create_pseudo_p ());
2199 temp_reg
= gen_reg_rtx (Pmode
);
2202 emit_move_insn (temp_reg
, x
);
2203 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2208 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2210 x
= gen_rtx_CONST (Pmode
, x
);
2212 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2218 /* Helper for m68k_unwrap_symbol.
2219 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2220 sets *RELOC_PTR to relocation type for the symbol. */
2223 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2224 enum m68k_reloc
*reloc_ptr
)
2226 if (GET_CODE (orig
) == CONST
)
2229 enum m68k_reloc dummy
;
2233 if (reloc_ptr
== NULL
)
2236 /* Handle an addend. */
2237 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2238 && CONST_INT_P (XEXP (x
, 1)))
2241 if (GET_CODE (x
) == UNSPEC
)
2243 switch (XINT (x
, 1))
2245 case UNSPEC_RELOC16
:
2246 orig
= XVECEXP (x
, 0, 0);
2247 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2250 case UNSPEC_RELOC32
:
2251 if (unwrap_reloc32_p
)
2253 orig
= XVECEXP (x
, 0, 0);
2254 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2267 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2268 UNSPEC_RELOC32 wrappers. */
2271 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2273 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2276 /* Helper for m68k_final_prescan_insn. */
2279 m68k_final_prescan_insn_1 (rtx
*x_ptr
, void *data ATTRIBUTE_UNUSED
)
2283 if (m68k_unwrap_symbol (x
, true) != x
)
2284 /* For rationale of the below, see comment in m68k_final_prescan_insn. */
2288 gcc_assert (GET_CODE (x
) == CONST
);
2291 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2296 unspec
= XEXP (plus
, 0);
2297 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2298 addend
= XEXP (plus
, 1);
2299 gcc_assert (CONST_INT_P (addend
));
2301 /* We now have all the pieces, rearrange them. */
2303 /* Move symbol to plus. */
2304 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2306 /* Move plus inside unspec. */
2307 XVECEXP (unspec
, 0, 0) = plus
;
2309 /* Move unspec to top level of const. */
2310 XEXP (x
, 0) = unspec
;
2319 /* Prescan insn before outputing assembler for it. */
2322 m68k_final_prescan_insn (rtx insn ATTRIBUTE_UNUSED
,
2323 rtx
*operands
, int n_operands
)
2327 /* Combine and, possibly, other optimizations may do good job
2329 (const (unspec [(symbol)]))
2331 (const (plus (unspec [(symbol)])
2333 The problem with this is emitting @TLS or @GOT decorations.
2334 The decoration is emitted when processing (unspec), so the
2335 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2337 It seems that the easiest solution to this is to convert such
2339 (const (unspec [(plus (symbol)
2341 Note, that the top level of operand remains intact, so we don't have
2342 to patch up anything outside of the operand. */
2344 for (i
= 0; i
< n_operands
; ++i
)
2350 for_each_rtx (&op
, m68k_final_prescan_insn_1
, NULL
);
2354 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2355 If REG is non-null, use it; generate new pseudo otherwise. */
2358 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2362 if (reg
== NULL_RTX
)
2364 gcc_assert (can_create_pseudo_p ());
2365 reg
= gen_reg_rtx (Pmode
);
2368 insn
= emit_move_insn (reg
, x
);
2369 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2371 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2376 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2380 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2382 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2384 x
= gen_rtx_MEM (Pmode
, x
);
2385 MEM_READONLY_P (x
) = 1;
2390 /* Legitimize PIC addresses. If the address is already
2391 position-independent, we return ORIG. Newly generated
2392 position-independent addresses go to REG. If we need more
2393 than one register, we lose.
2395 An address is legitimized by making an indirect reference
2396 through the Global Offset Table with the name of the symbol
2399 The assembler and linker are responsible for placing the
2400 address of the symbol in the GOT. The function prologue
2401 is responsible for initializing a5 to the starting address
2404 The assembler is also responsible for translating a symbol name
2405 into a constant displacement from the start of the GOT.
2407 A quick example may make things a little clearer:
2409 When not generating PIC code to store the value 12345 into _foo
2410 we would generate the following code:
2414 When generating PIC two transformations are made. First, the compiler
2415 loads the address of foo into a register. So the first transformation makes:
2420 The code in movsi will intercept the lea instruction and call this
2421 routine which will transform the instructions into:
2423 movel a5@(_foo:w), a0
2427 That (in a nutshell) is how *all* symbol and label references are
2431 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
2436 /* First handle a simple SYMBOL_REF or LABEL_REF */
2437 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2441 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2442 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2444 else if (GET_CODE (orig
) == CONST
)
2448 /* Make sure this has not already been legitimized. */
2449 if (m68k_unwrap_symbol (orig
, true) != orig
)
2454 /* legitimize both operands of the PLUS */
2455 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2457 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2458 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2459 base
== reg
? 0 : reg
);
2461 if (GET_CODE (orig
) == CONST_INT
)
2462 pic_ref
= plus_constant (Pmode
, base
, INTVAL (orig
));
2464 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2470 /* The __tls_get_addr symbol. */
2471 static GTY(()) rtx m68k_tls_get_addr
;
2473 /* Return SYMBOL_REF for __tls_get_addr. */
2476 m68k_get_tls_get_addr (void)
2478 if (m68k_tls_get_addr
== NULL_RTX
)
2479 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2481 return m68k_tls_get_addr
;
2484 /* Return libcall result in A0 instead of usual D0. */
2485 static bool m68k_libcall_value_in_a0_p
= false;
2487 /* Emit instruction sequence that calls __tls_get_addr. X is
2488 the TLS symbol we are referencing and RELOC is the symbol type to use
2489 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2490 emitted. A pseudo register with result of __tls_get_addr call is
2494 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2500 /* Emit the call sequence. */
2503 /* FIXME: Unfortunately, emit_library_call_value does not
2504 consider (plus (%a5) (const (unspec))) to be a good enough
2505 operand for push, so it forces it into a register. The bad
2506 thing about this is that combiner, due to copy propagation and other
2507 optimizations, sometimes can not later fix this. As a consequence,
2508 additional register may be allocated resulting in a spill.
2509 For reference, see args processing loops in
2510 calls.c:emit_library_call_value_1.
2511 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2512 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2514 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2515 is the simpliest way of generating a call. The difference between
2516 __tls_get_addr() and libcall is that the result is returned in D0
2517 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2518 which temporarily switches returning the result to A0. */
2520 m68k_libcall_value_in_a0_p
= true;
2521 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2522 Pmode
, 1, x
, Pmode
);
2523 m68k_libcall_value_in_a0_p
= false;
2525 insns
= get_insns ();
2528 gcc_assert (can_create_pseudo_p ());
2529 dest
= gen_reg_rtx (Pmode
);
2530 emit_libcall_block (insns
, dest
, a0
, eqv
);
2535 /* The __tls_get_addr symbol. */
2536 static GTY(()) rtx m68k_read_tp
;
2538 /* Return SYMBOL_REF for __m68k_read_tp. */
2541 m68k_get_m68k_read_tp (void)
2543 if (m68k_read_tp
== NULL_RTX
)
2544 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2546 return m68k_read_tp
;
2549 /* Emit instruction sequence that calls __m68k_read_tp.
2550 A pseudo register with result of __m68k_read_tp call is returned. */
2553 m68k_call_m68k_read_tp (void)
2562 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2563 is the simpliest way of generating a call. The difference between
2564 __m68k_read_tp() and libcall is that the result is returned in D0
2565 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2566 which temporarily switches returning the result to A0. */
2568 /* Emit the call sequence. */
2569 m68k_libcall_value_in_a0_p
= true;
2570 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2572 m68k_libcall_value_in_a0_p
= false;
2573 insns
= get_insns ();
2576 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2577 share the m68k_read_tp result with other IE/LE model accesses. */
2578 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2580 gcc_assert (can_create_pseudo_p ());
2581 dest
= gen_reg_rtx (Pmode
);
2582 emit_libcall_block (insns
, dest
, a0
, eqv
);
2587 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2588 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2592 m68k_legitimize_tls_address (rtx orig
)
2594 switch (SYMBOL_REF_TLS_MODEL (orig
))
2596 case TLS_MODEL_GLOBAL_DYNAMIC
:
2597 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2600 case TLS_MODEL_LOCAL_DYNAMIC
:
2606 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2607 share the LDM result with other LD model accesses. */
2608 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2611 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2613 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2615 if (can_create_pseudo_p ())
2616 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2622 case TLS_MODEL_INITIAL_EXEC
:
2627 a0
= m68k_call_m68k_read_tp ();
2629 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2630 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2632 if (can_create_pseudo_p ())
2633 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2639 case TLS_MODEL_LOCAL_EXEC
:
2644 a0
= m68k_call_m68k_read_tp ();
2646 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2648 if (can_create_pseudo_p ())
2649 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2662 /* Return true if X is a TLS symbol. */
2665 m68k_tls_symbol_p (rtx x
)
2667 if (!TARGET_HAVE_TLS
)
2670 if (GET_CODE (x
) != SYMBOL_REF
)
2673 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2676 /* Helper for m68k_tls_referenced_p. */
2679 m68k_tls_reference_p_1 (rtx
*x_ptr
, void *data ATTRIBUTE_UNUSED
)
2681 /* Note: this is not the same as m68k_tls_symbol_p. */
2682 if (GET_CODE (*x_ptr
) == SYMBOL_REF
)
2683 return SYMBOL_REF_TLS_MODEL (*x_ptr
) != 0 ? 1 : 0;
2685 /* Don't recurse into legitimate TLS references. */
2686 if (m68k_tls_reference_p (*x_ptr
, true))
2692 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2693 though illegitimate one.
2694 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2697 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2699 if (!TARGET_HAVE_TLS
)
2703 return for_each_rtx (&x
, m68k_tls_reference_p_1
, NULL
) == 1 ? true : false;
2706 enum m68k_reloc reloc
= RELOC_GOT
;
2708 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2709 && TLS_RELOC_P (reloc
));
2715 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2717 /* Return the type of move that should be used for integer I. */
2720 m68k_const_method (HOST_WIDE_INT i
)
2727 /* The ColdFire doesn't have byte or word operations. */
2728 /* FIXME: This may not be useful for the m68060 either. */
2729 if (!TARGET_COLDFIRE
)
2731 /* if -256 < N < 256 but N is not in range for a moveq
2732 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2733 if (USE_MOVQ (i
^ 0xff))
2735 /* Likewise, try with not.w */
2736 if (USE_MOVQ (i
^ 0xffff))
2738 /* This is the only value where neg.w is useful */
2743 /* Try also with swap. */
2745 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2750 /* Try using MVZ/MVS with an immediate value to load constants. */
2751 if (i
>= 0 && i
<= 65535)
2753 if (i
>= -32768 && i
<= 32767)
2757 /* Otherwise, use move.l */
2761 /* Return the cost of moving constant I into a data register. */
2764 const_int_cost (HOST_WIDE_INT i
)
2766 switch (m68k_const_method (i
))
2769 /* Constants between -128 and 127 are cheap due to moveq. */
2777 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2787 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
2788 int *total
, bool speed ATTRIBUTE_UNUSED
)
2793 /* Constant zero is super cheap due to clr instruction. */
2794 if (x
== const0_rtx
)
2797 *total
= const_int_cost (INTVAL (x
));
2807 /* Make 0.0 cheaper than other floating constants to
2808 encourage creating tstsf and tstdf insns. */
2809 if (outer_code
== COMPARE
2810 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2816 /* These are vaguely right for a 68020. */
2817 /* The costs for long multiply have been adjusted to work properly
2818 in synth_mult on the 68020, relative to an average of the time
2819 for add and the time for shift, taking away a little more because
2820 sometimes move insns are needed. */
2821 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2826 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2827 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2829 : TARGET_COLDFIRE ? 3 : 13)
2834 : TUNE_68000_10 ? 5 \
2835 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2836 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2838 : TARGET_COLDFIRE ? 2 : 8)
2841 (TARGET_CF_HWDIV ? 11 \
2842 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2845 /* An lea costs about three times as much as a simple add. */
2846 if (GET_MODE (x
) == SImode
2847 && GET_CODE (XEXP (x
, 1)) == REG
2848 && GET_CODE (XEXP (x
, 0)) == MULT
2849 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2850 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2851 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2852 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2853 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2855 /* lea an@(dx:l:i),am */
2856 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2866 *total
= COSTS_N_INSNS(1);
2871 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2873 if (INTVAL (XEXP (x
, 1)) < 16)
2874 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2876 /* We're using clrw + swap for these cases. */
2877 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2880 *total
= COSTS_N_INSNS (10); /* Worst case. */
2883 /* A shift by a big integer takes an extra instruction. */
2884 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2885 && (INTVAL (XEXP (x
, 1)) == 16))
2887 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2890 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2891 && !(INTVAL (XEXP (x
, 1)) > 0
2892 && INTVAL (XEXP (x
, 1)) <= 8))
2894 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2900 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2901 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2902 && GET_MODE (x
) == SImode
)
2903 *total
= COSTS_N_INSNS (MULW_COST
);
2904 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2905 *total
= COSTS_N_INSNS (MULW_COST
);
2907 *total
= COSTS_N_INSNS (MULL_COST
);
2914 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2915 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2916 else if (TARGET_CF_HWDIV
)
2917 *total
= COSTS_N_INSNS (18);
2919 *total
= COSTS_N_INSNS (43); /* div.l */
2923 if (outer_code
== COMPARE
)
2932 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2936 output_move_const_into_data_reg (rtx
*operands
)
2940 i
= INTVAL (operands
[1]);
2941 switch (m68k_const_method (i
))
2944 return "mvzw %1,%0";
2946 return "mvsw %1,%0";
2948 return "moveq %1,%0";
2951 operands
[1] = GEN_INT (i
^ 0xff);
2952 return "moveq %1,%0\n\tnot%.b %0";
2955 operands
[1] = GEN_INT (i
^ 0xffff);
2956 return "moveq %1,%0\n\tnot%.w %0";
2959 return "moveq #-128,%0\n\tneg%.w %0";
2964 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2965 return "moveq %1,%0\n\tswap %0";
2968 return "move%.l %1,%0";
2974 /* Return true if I can be handled by ISA B's mov3q instruction. */
2977 valid_mov3q_const (HOST_WIDE_INT i
)
2979 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2982 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2983 I is the value of OPERANDS[1]. */
2986 output_move_simode_const (rtx
*operands
)
2992 src
= INTVAL (operands
[1]);
2994 && (DATA_REG_P (dest
) || MEM_P (dest
))
2995 /* clr insns on 68000 read before writing. */
2996 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2997 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
2999 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
3000 return "mov3q%.l %1,%0";
3001 else if (src
== 0 && ADDRESS_REG_P (dest
))
3002 return "sub%.l %0,%0";
3003 else if (DATA_REG_P (dest
))
3004 return output_move_const_into_data_reg (operands
);
3005 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
3007 if (valid_mov3q_const (src
))
3008 return "mov3q%.l %1,%0";
3009 return "move%.w %1,%0";
3011 else if (MEM_P (dest
)
3012 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
3013 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
3014 && IN_RANGE (src
, -0x8000, 0x7fff))
3016 if (valid_mov3q_const (src
))
3017 return "mov3q%.l %1,%-";
3020 return "move%.l %1,%0";
3024 output_move_simode (rtx
*operands
)
3026 if (GET_CODE (operands
[1]) == CONST_INT
)
3027 return output_move_simode_const (operands
);
3028 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3029 || GET_CODE (operands
[1]) == CONST
)
3030 && push_operand (operands
[0], SImode
))
3032 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3033 || GET_CODE (operands
[1]) == CONST
)
3034 && ADDRESS_REG_P (operands
[0]))
3035 return "lea %a1,%0";
3036 return "move%.l %1,%0";
3040 output_move_himode (rtx
*operands
)
3042 if (GET_CODE (operands
[1]) == CONST_INT
)
3044 if (operands
[1] == const0_rtx
3045 && (DATA_REG_P (operands
[0])
3046 || GET_CODE (operands
[0]) == MEM
)
3047 /* clr insns on 68000 read before writing. */
3048 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3049 || !(GET_CODE (operands
[0]) == MEM
3050 && MEM_VOLATILE_P (operands
[0]))))
3052 else if (operands
[1] == const0_rtx
3053 && ADDRESS_REG_P (operands
[0]))
3054 return "sub%.l %0,%0";
3055 else if (DATA_REG_P (operands
[0])
3056 && INTVAL (operands
[1]) < 128
3057 && INTVAL (operands
[1]) >= -128)
3058 return "moveq %1,%0";
3059 else if (INTVAL (operands
[1]) < 0x8000
3060 && INTVAL (operands
[1]) >= -0x8000)
3061 return "move%.w %1,%0";
3063 else if (CONSTANT_P (operands
[1]))
3064 return "move%.l %1,%0";
3065 return "move%.w %1,%0";
3069 output_move_qimode (rtx
*operands
)
3071 /* 68k family always modifies the stack pointer by at least 2, even for
3072 byte pushes. The 5200 (ColdFire) does not do this. */
3074 /* This case is generated by pushqi1 pattern now. */
3075 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3076 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3077 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3078 && ! ADDRESS_REG_P (operands
[1])
3079 && ! TARGET_COLDFIRE
));
3081 /* clr and st insns on 68000 read before writing. */
3082 if (!ADDRESS_REG_P (operands
[0])
3083 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3084 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3086 if (operands
[1] == const0_rtx
)
3088 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3089 && GET_CODE (operands
[1]) == CONST_INT
3090 && (INTVAL (operands
[1]) & 255) == 255)
3096 if (GET_CODE (operands
[1]) == CONST_INT
3097 && DATA_REG_P (operands
[0])
3098 && INTVAL (operands
[1]) < 128
3099 && INTVAL (operands
[1]) >= -128)
3100 return "moveq %1,%0";
3101 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3102 return "sub%.l %0,%0";
3103 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3104 return "move%.l %1,%0";
3105 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3106 from address registers. */
3107 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3108 return "move%.w %1,%0";
3109 return "move%.b %1,%0";
3113 output_move_stricthi (rtx
*operands
)
3115 if (operands
[1] == const0_rtx
3116 /* clr insns on 68000 read before writing. */
3117 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3118 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3120 return "move%.w %1,%0";
3124 output_move_strictqi (rtx
*operands
)
3126 if (operands
[1] == const0_rtx
3127 /* clr insns on 68000 read before writing. */
3128 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3129 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3131 return "move%.b %1,%0";
3134 /* Return the best assembler insn template
3135 for moving operands[1] into operands[0] as a fullword. */
3138 singlemove_string (rtx
*operands
)
3140 if (GET_CODE (operands
[1]) == CONST_INT
)
3141 return output_move_simode_const (operands
);
3142 return "move%.l %1,%0";
3146 /* Output assembler or rtl code to perform a doubleword move insn
3147 with operands OPERANDS.
3148 Pointers to 3 helper functions should be specified:
3149 HANDLE_REG_ADJUST to adjust a register by a small value,
3150 HANDLE_COMPADR to compute an address and
3151 HANDLE_MOVSI to move 4 bytes. */
3154 handle_move_double (rtx operands
[2],
3155 void (*handle_reg_adjust
) (rtx
, int),
3156 void (*handle_compadr
) (rtx
[2]),
3157 void (*handle_movsi
) (rtx
[2]))
3161 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3166 rtx addreg0
= 0, addreg1
= 0;
3167 int dest_overlapped_low
= 0;
3168 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3173 /* First classify both operands. */
3175 if (REG_P (operands
[0]))
3177 else if (offsettable_memref_p (operands
[0]))
3179 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3181 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3183 else if (GET_CODE (operands
[0]) == MEM
)
3188 if (REG_P (operands
[1]))
3190 else if (CONSTANT_P (operands
[1]))
3192 else if (offsettable_memref_p (operands
[1]))
3194 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3196 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3198 else if (GET_CODE (operands
[1]) == MEM
)
3203 /* Check for the cases that the operand constraints are not supposed
3204 to allow to happen. Generating code for these cases is
3206 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3208 /* If one operand is decrementing and one is incrementing
3209 decrement the former register explicitly
3210 and change that operand into ordinary indexing. */
3212 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3214 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3216 handle_reg_adjust (operands
[0], -size
);
3218 if (GET_MODE (operands
[1]) == XFmode
)
3219 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3220 else if (GET_MODE (operands
[0]) == DFmode
)
3221 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3223 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3226 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3228 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3230 handle_reg_adjust (operands
[1], -size
);
3232 if (GET_MODE (operands
[1]) == XFmode
)
3233 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3234 else if (GET_MODE (operands
[1]) == DFmode
)
3235 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3237 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3241 /* If an operand is an unoffsettable memory ref, find a register
3242 we can increment temporarily to make it refer to the second word. */
3244 if (optype0
== MEMOP
)
3245 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3247 if (optype1
== MEMOP
)
3248 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3250 /* Ok, we can do one word at a time.
3251 Normally we do the low-numbered word first,
3252 but if either operand is autodecrementing then we
3253 do the high-numbered word first.
3255 In either case, set up in LATEHALF the operands to use
3256 for the high-numbered word and in some cases alter the
3257 operands in OPERANDS to be suitable for the low-numbered word. */
3261 if (optype0
== REGOP
)
3263 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3264 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3266 else if (optype0
== OFFSOP
)
3268 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3269 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3273 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3274 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3277 if (optype1
== REGOP
)
3279 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3280 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3282 else if (optype1
== OFFSOP
)
3284 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3285 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3287 else if (optype1
== CNSTOP
)
3289 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3294 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
3295 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
3296 operands
[1] = GEN_INT (l
[0]);
3297 middlehalf
[1] = GEN_INT (l
[1]);
3298 latehalf
[1] = GEN_INT (l
[2]);
3302 /* No non-CONST_DOUBLE constant should ever appear
3304 gcc_assert (!CONSTANT_P (operands
[1]));
3309 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3310 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3314 /* size is not 12: */
3316 if (optype0
== REGOP
)
3317 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3318 else if (optype0
== OFFSOP
)
3319 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3321 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3323 if (optype1
== REGOP
)
3324 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3325 else if (optype1
== OFFSOP
)
3326 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3327 else if (optype1
== CNSTOP
)
3328 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3330 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3333 /* If insn is effectively movd N(REG),-(REG) then we will do the high
3334 word first. We should use the adjusted operand 1 (which is N+4(REG))
3335 for the low word as well, to compensate for the first decrement of
3337 if (optype0
== PUSHOP
3338 && reg_overlap_mentioned_p (XEXP (XEXP (operands
[0], 0), 0), operands
[1]))
3339 operands
[1] = middlehalf
[1] = latehalf
[1];
3341 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3342 if the upper part of reg N does not appear in the MEM, arrange to
3343 emit the move late-half first. Otherwise, compute the MEM address
3344 into the upper part of N and use that as a pointer to the memory
3346 if (optype0
== REGOP
3347 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3349 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3351 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3352 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3354 /* If both halves of dest are used in the src memory address,
3355 compute the address into latehalf of dest.
3356 Note that this can't happen if the dest is two data regs. */
3358 xops
[0] = latehalf
[0];
3359 xops
[1] = XEXP (operands
[1], 0);
3361 handle_compadr (xops
);
3362 if (GET_MODE (operands
[1]) == XFmode
)
3364 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3365 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3366 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3370 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3371 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3375 && reg_overlap_mentioned_p (middlehalf
[0],
3376 XEXP (operands
[1], 0)))
3378 /* Check for two regs used by both source and dest.
3379 Note that this can't happen if the dest is all data regs.
3380 It can happen if the dest is d6, d7, a0.
3381 But in that case, latehalf is an addr reg, so
3382 the code at compadr does ok. */
3384 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3385 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3388 /* JRV says this can't happen: */
3389 gcc_assert (!addreg0
&& !addreg1
);
3391 /* Only the middle reg conflicts; simply put it last. */
3392 handle_movsi (operands
);
3393 handle_movsi (latehalf
);
3394 handle_movsi (middlehalf
);
3398 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3399 /* If the low half of dest is mentioned in the source memory
3400 address, the arrange to emit the move late half first. */
3401 dest_overlapped_low
= 1;
3404 /* If one or both operands autodecrementing,
3405 do the two words, high-numbered first. */
3407 /* Likewise, the first move would clobber the source of the second one,
3408 do them in the other order. This happens only for registers;
3409 such overlap can't happen in memory unless the user explicitly
3410 sets it up, and that is an undefined circumstance. */
3412 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3413 || (optype0
== REGOP
&& optype1
== REGOP
3414 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3415 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3416 || dest_overlapped_low
)
3418 /* Make any unoffsettable addresses point at high-numbered word. */
3420 handle_reg_adjust (addreg0
, size
- 4);
3422 handle_reg_adjust (addreg1
, size
- 4);
3425 handle_movsi (latehalf
);
3427 /* Undo the adds we just did. */
3429 handle_reg_adjust (addreg0
, -4);
3431 handle_reg_adjust (addreg1
, -4);
3435 handle_movsi (middlehalf
);
3438 handle_reg_adjust (addreg0
, -4);
3440 handle_reg_adjust (addreg1
, -4);
3443 /* Do low-numbered word. */
3445 handle_movsi (operands
);
3449 /* Normal case: do the two words, low-numbered first. */
3451 m68k_final_prescan_insn (NULL
, operands
, 2);
3452 handle_movsi (operands
);
3454 /* Do the middle one of the three words for long double */
3458 handle_reg_adjust (addreg0
, 4);
3460 handle_reg_adjust (addreg1
, 4);
3462 m68k_final_prescan_insn (NULL
, middlehalf
, 2);
3463 handle_movsi (middlehalf
);
3466 /* Make any unoffsettable addresses point at high-numbered word. */
3468 handle_reg_adjust (addreg0
, 4);
3470 handle_reg_adjust (addreg1
, 4);
3473 m68k_final_prescan_insn (NULL
, latehalf
, 2);
3474 handle_movsi (latehalf
);
3476 /* Undo the adds we just did. */
3478 handle_reg_adjust (addreg0
, -(size
- 4));
3480 handle_reg_adjust (addreg1
, -(size
- 4));
3485 /* Output assembler code to adjust REG by N. */
3487 output_reg_adjust (rtx reg
, int n
)
3491 gcc_assert (GET_MODE (reg
) == SImode
3492 && -12 <= n
&& n
!= 0 && n
<= 12);
3497 s
= "add%.l #12,%0";
3501 s
= "addq%.l #8,%0";
3505 s
= "addq%.l #4,%0";
3509 s
= "sub%.l #12,%0";
3513 s
= "subq%.l #8,%0";
3517 s
= "subq%.l #4,%0";
3525 output_asm_insn (s
, ®
);
3528 /* Emit rtl code to adjust REG by N. */
3530 emit_reg_adjust (rtx reg1
, int n
)
3534 gcc_assert (GET_MODE (reg1
) == SImode
3535 && -12 <= n
&& n
!= 0 && n
<= 12);
3537 reg1
= copy_rtx (reg1
);
3538 reg2
= copy_rtx (reg1
);
3541 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3543 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3548 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3550 output_compadr (rtx operands
[2])
3552 output_asm_insn ("lea %a1,%0", operands
);
3555 /* Output the best assembler insn for moving operands[1] into operands[0]
3558 output_movsi (rtx operands
[2])
3560 output_asm_insn (singlemove_string (operands
), operands
);
3563 /* Copy OP and change its mode to MODE. */
3565 copy_operand (rtx op
, enum machine_mode mode
)
3567 /* ??? This looks really ugly. There must be a better way
3568 to change a mode on the operand. */
3569 if (GET_MODE (op
) != VOIDmode
)
3572 op
= gen_rtx_REG (mode
, REGNO (op
));
3576 PUT_MODE (op
, mode
);
3583 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3585 emit_movsi (rtx operands
[2])
3587 operands
[0] = copy_operand (operands
[0], SImode
);
3588 operands
[1] = copy_operand (operands
[1], SImode
);
3590 emit_insn (gen_movsi (operands
[0], operands
[1]));
3593 /* Output assembler code to perform a doubleword move insn
3594 with operands OPERANDS. */
3596 output_move_double (rtx
*operands
)
3598 handle_move_double (operands
,
3599 output_reg_adjust
, output_compadr
, output_movsi
);
3604 /* Output rtl code to perform a doubleword move insn
3605 with operands OPERANDS. */
3607 m68k_emit_move_double (rtx operands
[2])
3609 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3612 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3613 new rtx with the correct mode. */
3616 force_mode (enum machine_mode mode
, rtx orig
)
3618 if (mode
== GET_MODE (orig
))
3621 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3624 return gen_rtx_REG (mode
, REGNO (orig
));
3628 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3630 return reg_renumber
&& FP_REG_P (op
);
3633 /* Emit insns to move operands[1] into operands[0].
3635 Return 1 if we have written out everything that needs to be done to
3636 do the move. Otherwise, return 0 and the caller will emit the move
3639 Note SCRATCH_REG may not be in the proper mode depending on how it
3640 will be used. This routine is responsible for creating a new copy
3641 of SCRATCH_REG in the proper mode. */
3644 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
3646 register rtx operand0
= operands
[0];
3647 register rtx operand1
= operands
[1];
3651 && reload_in_progress
&& GET_CODE (operand0
) == REG
3652 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3653 operand0
= reg_equiv_mem (REGNO (operand0
));
3654 else if (scratch_reg
3655 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3656 && GET_CODE (SUBREG_REG (operand0
)) == REG
3657 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3659 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3660 the code which tracks sets/uses for delete_output_reload. */
3661 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3662 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
3663 SUBREG_BYTE (operand0
));
3664 operand0
= alter_subreg (&temp
, true);
3668 && reload_in_progress
&& GET_CODE (operand1
) == REG
3669 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3670 operand1
= reg_equiv_mem (REGNO (operand1
));
3671 else if (scratch_reg
3672 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3673 && GET_CODE (SUBREG_REG (operand1
)) == REG
3674 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3676 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3677 the code which tracks sets/uses for delete_output_reload. */
3678 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3679 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
3680 SUBREG_BYTE (operand1
));
3681 operand1
= alter_subreg (&temp
, true);
3684 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3685 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3686 != XEXP (operand0
, 0)))
3687 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3688 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3689 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3690 != XEXP (operand1
, 0)))
3691 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3693 /* Handle secondary reloads for loads/stores of FP registers where
3694 the address is symbolic by using the scratch register */
3695 if (fp_reg_operand (operand0
, mode
)
3696 && ((GET_CODE (operand1
) == MEM
3697 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3698 || ((GET_CODE (operand1
) == SUBREG
3699 && GET_CODE (XEXP (operand1
, 0)) == MEM
3700 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3703 if (GET_CODE (operand1
) == SUBREG
)
3704 operand1
= XEXP (operand1
, 0);
3706 /* SCRATCH_REG will hold an address. We want
3707 it in SImode regardless of what mode it was originally given
3709 scratch_reg
= force_mode (SImode
, scratch_reg
);
3711 /* D might not fit in 14 bits either; for such cases load D into
3713 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3715 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3716 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3718 XEXP (XEXP (operand1
, 0), 0),
3722 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3723 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
3724 gen_rtx_MEM (mode
, scratch_reg
)));
3727 else if (fp_reg_operand (operand1
, mode
)
3728 && ((GET_CODE (operand0
) == MEM
3729 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3730 || ((GET_CODE (operand0
) == SUBREG
)
3731 && GET_CODE (XEXP (operand0
, 0)) == MEM
3732 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3735 if (GET_CODE (operand0
) == SUBREG
)
3736 operand0
= XEXP (operand0
, 0);
3738 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3739 it in SIMODE regardless of what mode it was originally given
3741 scratch_reg
= force_mode (SImode
, scratch_reg
);
3743 /* D might not fit in 14 bits either; for such cases load D into
3745 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3747 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3748 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3751 XEXP (XEXP (operand0
, 0),
3756 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3757 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
3761 /* Handle secondary reloads for loads of FP registers from constant
3762 expressions by forcing the constant into memory.
3764 use scratch_reg to hold the address of the memory location.
3766 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3767 NO_REGS when presented with a const_int and an register class
3768 containing only FP registers. Doing so unfortunately creates
3769 more problems than it solves. Fix this for 2.5. */
3770 else if (fp_reg_operand (operand0
, mode
)
3771 && CONSTANT_P (operand1
)
3776 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3777 it in SIMODE regardless of what mode it was originally given
3779 scratch_reg
= force_mode (SImode
, scratch_reg
);
3781 /* Force the constant into memory and put the address of the
3782 memory location into scratch_reg. */
3783 xoperands
[0] = scratch_reg
;
3784 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3785 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
3787 /* Now load the destination register. */
3788 emit_insn (gen_rtx_SET (mode
, operand0
,
3789 gen_rtx_MEM (mode
, scratch_reg
)));
3793 /* Now have insn-emit do whatever it normally does. */
3797 /* Split one or more DImode RTL references into pairs of SImode
3798 references. The RTL can be REG, offsettable MEM, integer constant, or
3799 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3800 split and "num" is its length. lo_half and hi_half are output arrays
3801 that parallel "operands". */
3804 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3808 rtx op
= operands
[num
];
3810 /* simplify_subreg refuses to split volatile memory addresses,
3811 but we still have to handle it. */
3812 if (GET_CODE (op
) == MEM
)
3814 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3815 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3819 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3820 GET_MODE (op
) == VOIDmode
3821 ? DImode
: GET_MODE (op
), 4);
3822 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3823 GET_MODE (op
) == VOIDmode
3824 ? DImode
: GET_MODE (op
), 0);
3829 /* Split X into a base and a constant offset, storing them in *BASE
3830 and *OFFSET respectively. */
3833 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3836 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3838 *offset
+= INTVAL (XEXP (x
, 1));
3844 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3845 instruction. STORE_P says whether the move is a load or store.
3847 If the instruction uses post-increment or pre-decrement addressing,
3848 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3849 adjustment. This adjustment will be made by the first element of
3850 PARALLEL, with the loads or stores starting at element 1. If the
3851 instruction does not use post-increment or pre-decrement addressing,
3852 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3853 start at element 0. */
3856 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3857 HOST_WIDE_INT automod_offset
, bool store_p
)
3859 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3860 HOST_WIDE_INT offset
, mem_offset
;
3862 enum reg_class rclass
;
3864 len
= XVECLEN (pattern
, 0);
3865 first
= (automod_base
!= NULL
);
3869 /* Stores must be pre-decrement and loads must be post-increment. */
3870 if (store_p
!= (automod_offset
< 0))
3873 /* Work out the base and offset for lowest memory location. */
3874 base
= automod_base
;
3875 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3879 /* Allow any valid base and offset in the first access. */
3886 for (i
= first
; i
< len
; i
++)
3888 /* We need a plain SET. */
3889 set
= XVECEXP (pattern
, 0, i
);
3890 if (GET_CODE (set
) != SET
)
3893 /* Check that we have a memory location... */
3894 mem
= XEXP (set
, !store_p
);
3895 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3898 /* ...with the right address. */
3901 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3902 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3903 There are no mode restrictions for 680x0 besides the
3904 automodification rules enforced above. */
3906 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3911 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3912 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3916 /* Check that we have a register of the required mode and class. */
3917 reg
= XEXP (set
, store_p
);
3919 || !HARD_REGISTER_P (reg
)
3920 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3925 /* The register must belong to RCLASS and have a higher number
3926 than the register in the previous SET. */
3927 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3928 || REGNO (last_reg
) >= REGNO (reg
))
3933 /* Work out which register class we need. */
3934 if (INT_REGNO_P (REGNO (reg
)))
3935 rclass
= GENERAL_REGS
;
3936 else if (FP_REGNO_P (REGNO (reg
)))
3943 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3946 /* If we have an automodification, check whether the final offset is OK. */
3947 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3950 /* Reject unprofitable cases. */
3951 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3957 /* Return the assembly code template for a movem or fmovem instruction
3958 whose pattern is given by PATTERN. Store the template's operands
3961 If the instruction uses post-increment or pre-decrement addressing,
3962 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3963 is true if this is a store instruction. */
3966 m68k_output_movem (rtx
*operands
, rtx pattern
,
3967 HOST_WIDE_INT automod_offset
, bool store_p
)
3972 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3974 first
= (automod_offset
!= 0);
3975 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3977 /* When using movem with pre-decrement addressing, register X + D0_REG
3978 is controlled by bit 15 - X. For all other addressing modes,
3979 register X + D0_REG is controlled by bit X. Confusingly, the
3980 register mask for fmovem is in the opposite order to that for
3984 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
3985 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
3986 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
3987 if (automod_offset
< 0)
3989 if (FP_REGNO_P (regno
))
3990 mask
|= 1 << (regno
- FP0_REG
);
3992 mask
|= 1 << (15 - (regno
- D0_REG
));
3996 if (FP_REGNO_P (regno
))
3997 mask
|= 1 << (7 - (regno
- FP0_REG
));
3999 mask
|= 1 << (regno
- D0_REG
);
4004 if (automod_offset
== 0)
4005 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
4006 else if (automod_offset
< 0)
4007 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4009 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4010 operands
[1] = GEN_INT (mask
);
4011 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
4014 return "fmovem %1,%a0";
4016 return "fmovem %a0,%1";
4021 return "movem%.l %1,%a0";
4023 return "movem%.l %a0,%1";
4027 /* Return a REG that occurs in ADDR with coefficient 1.
4028 ADDR can be effectively incremented by incrementing REG. */
4031 find_addr_reg (rtx addr
)
4033 while (GET_CODE (addr
) == PLUS
)
4035 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4036 addr
= XEXP (addr
, 0);
4037 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4038 addr
= XEXP (addr
, 1);
4039 else if (CONSTANT_P (XEXP (addr
, 0)))
4040 addr
= XEXP (addr
, 1);
4041 else if (CONSTANT_P (XEXP (addr
, 1)))
4042 addr
= XEXP (addr
, 0);
4046 gcc_assert (GET_CODE (addr
) == REG
);
4050 /* Output assembler code to perform a 32-bit 3-operand add. */
4053 output_addsi3 (rtx
*operands
)
4055 if (! operands_match_p (operands
[0], operands
[1]))
4057 if (!ADDRESS_REG_P (operands
[1]))
4059 rtx tmp
= operands
[1];
4061 operands
[1] = operands
[2];
4065 /* These insns can result from reloads to access
4066 stack slots over 64k from the frame pointer. */
4067 if (GET_CODE (operands
[2]) == CONST_INT
4068 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4069 return "move%.l %2,%0\n\tadd%.l %1,%0";
4070 if (GET_CODE (operands
[2]) == REG
)
4071 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4072 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4074 if (GET_CODE (operands
[2]) == CONST_INT
)
4076 if (INTVAL (operands
[2]) > 0
4077 && INTVAL (operands
[2]) <= 8)
4078 return "addq%.l %2,%0";
4079 if (INTVAL (operands
[2]) < 0
4080 && INTVAL (operands
[2]) >= -8)
4082 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4083 return "subq%.l %2,%0";
4085 /* On the CPU32 it is faster to use two addql instructions to
4086 add a small integer (8 < N <= 16) to a register.
4087 Likewise for subql. */
4088 if (TUNE_CPU32
&& REG_P (operands
[0]))
4090 if (INTVAL (operands
[2]) > 8
4091 && INTVAL (operands
[2]) <= 16)
4093 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4094 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4096 if (INTVAL (operands
[2]) < -8
4097 && INTVAL (operands
[2]) >= -16)
4099 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4100 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4103 if (ADDRESS_REG_P (operands
[0])
4104 && INTVAL (operands
[2]) >= -0x8000
4105 && INTVAL (operands
[2]) < 0x8000)
4108 return "add%.w %2,%0";
4110 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4113 return "add%.l %2,%0";
4116 /* Store in cc_status the expressions that the condition codes will
4117 describe after execution of an instruction whose pattern is EXP.
4118 Do not alter them if the instruction would not alter the cc's. */
4120 /* On the 68000, all the insns to store in an address register fail to
4121 set the cc's. However, in some cases these instructions can make it
4122 possibly invalid to use the saved cc's. In those cases we clear out
4123 some or all of the saved cc's so they won't be used. */
4126 notice_update_cc (rtx exp
, rtx insn
)
4128 if (GET_CODE (exp
) == SET
)
4130 if (GET_CODE (SET_SRC (exp
)) == CALL
)
4132 else if (ADDRESS_REG_P (SET_DEST (exp
)))
4134 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
4135 cc_status
.value1
= 0;
4136 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
4137 cc_status
.value2
= 0;
4139 /* fmoves to memory or data registers do not set the condition
4140 codes. Normal moves _do_ set the condition codes, but not in
4141 a way that is appropriate for comparison with 0, because -0.0
4142 would be treated as a negative nonzero number. Note that it
4143 isn't appropriate to conditionalize this restriction on
4144 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4145 we care about the difference between -0.0 and +0.0. */
4146 else if (!FP_REG_P (SET_DEST (exp
))
4147 && SET_DEST (exp
) != cc0_rtx
4148 && (FP_REG_P (SET_SRC (exp
))
4149 || GET_CODE (SET_SRC (exp
)) == FIX
4150 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
4152 /* A pair of move insns doesn't produce a useful overall cc. */
4153 else if (!FP_REG_P (SET_DEST (exp
))
4154 && !FP_REG_P (SET_SRC (exp
))
4155 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
4156 && (GET_CODE (SET_SRC (exp
)) == REG
4157 || GET_CODE (SET_SRC (exp
)) == MEM
4158 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
4160 else if (SET_DEST (exp
) != pc_rtx
)
4162 cc_status
.flags
= 0;
4163 cc_status
.value1
= SET_DEST (exp
);
4164 cc_status
.value2
= SET_SRC (exp
);
4167 else if (GET_CODE (exp
) == PARALLEL
4168 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
4170 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
4171 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
4173 if (ADDRESS_REG_P (dest
))
4175 else if (dest
!= pc_rtx
)
4177 cc_status
.flags
= 0;
4178 cc_status
.value1
= dest
;
4179 cc_status
.value2
= src
;
4184 if (cc_status
.value2
!= 0
4185 && ADDRESS_REG_P (cc_status
.value2
)
4186 && GET_MODE (cc_status
.value2
) == QImode
)
4188 if (cc_status
.value2
!= 0)
4189 switch (GET_CODE (cc_status
.value2
))
4191 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
4192 case ROTATE
: case ROTATERT
:
4193 /* These instructions always clear the overflow bit, and set
4194 the carry to the bit shifted out. */
4195 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
4198 case PLUS
: case MINUS
: case MULT
:
4199 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
4200 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4201 cc_status
.flags
|= CC_NO_OVERFLOW
;
4204 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4205 ends with a move insn moving r2 in r2's mode.
4206 Thus, the cc's are set for r2.
4207 This can set N bit spuriously. */
4208 cc_status
.flags
|= CC_NOT_NEGATIVE
;
4213 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4215 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4216 cc_status
.value2
= 0;
4217 /* Check for PRE_DEC in dest modifying a register used in src. */
4218 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == MEM
4219 && GET_CODE (XEXP (cc_status
.value1
, 0)) == PRE_DEC
4221 && reg_overlap_mentioned_p (XEXP (XEXP (cc_status
.value1
, 0), 0),
4223 cc_status
.value2
= 0;
4224 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
4225 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
4226 cc_status
.flags
= CC_IN_68881
;
4227 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
4228 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
4230 cc_status
.flags
= CC_IN_68881
;
4231 if (!FP_REG_P (XEXP (cc_status
.value2
, 0))
4232 && FP_REG_P (XEXP (cc_status
.value2
, 1)))
4233 cc_status
.flags
|= CC_REVERSED
;
4238 output_move_const_double (rtx
*operands
)
4240 int code
= standard_68881_constant_p (operands
[1]);
4244 static char buf
[40];
4246 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4249 return "fmove%.d %1,%0";
4253 output_move_const_single (rtx
*operands
)
4255 int code
= standard_68881_constant_p (operands
[1]);
4259 static char buf
[40];
4261 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4264 return "fmove%.s %f1,%0";
4267 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4268 from the "fmovecr" instruction.
4269 The value, anded with 0xff, gives the code to use in fmovecr
4270 to get the desired constant. */
4272 /* This code has been fixed for cross-compilation. */
4274 static int inited_68881_table
= 0;
4276 static const char *const strings_68881
[7] = {
4286 static const int codes_68881
[7] = {
4296 REAL_VALUE_TYPE values_68881
[7];
4298 /* Set up values_68881 array by converting the decimal values
4299 strings_68881 to binary. */
4302 init_68881_table (void)
4306 enum machine_mode mode
;
4309 for (i
= 0; i
< 7; i
++)
4313 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4314 values_68881
[i
] = r
;
4316 inited_68881_table
= 1;
4320 standard_68881_constant_p (rtx x
)
4325 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4326 used at all on those chips. */
4330 if (! inited_68881_table
)
4331 init_68881_table ();
4333 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4335 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
4337 for (i
= 0; i
< 6; i
++)
4339 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
4340 return (codes_68881
[i
]);
4343 if (GET_MODE (x
) == SFmode
)
4346 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
4347 return (codes_68881
[6]);
4349 /* larger powers of ten in the constants ram are not used
4350 because they are not equal to a `double' C constant. */
4354 /* If X is a floating-point constant, return the logarithm of X base 2,
4355 or 0 if X is not a power of 2. */
4358 floating_exact_log2 (rtx x
)
4360 REAL_VALUE_TYPE r
, r1
;
4363 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4365 if (REAL_VALUES_LESS (r
, dconst1
))
4368 exp
= real_exponent (&r
);
4369 real_2expN (&r1
, exp
, DFmode
);
4370 if (REAL_VALUES_EQUAL (r1
, r
))
4376 /* A C compound statement to output to stdio stream STREAM the
4377 assembler syntax for an instruction operand X. X is an RTL
4380 CODE is a value that can be used to specify one of several ways
4381 of printing the operand. It is used when identical operands
4382 must be printed differently depending on the context. CODE
4383 comes from the `%' specification that was used to request
4384 printing of the operand. If the specification was just `%DIGIT'
4385 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4386 is the ASCII code for LTR.
4388 If X is a register, this macro should print the register's name.
4389 The names can be found in an array `reg_names' whose type is
4390 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4392 When the machine description has a specification `%PUNCT' (a `%'
4393 followed by a punctuation character), this macro is called with
4394 a null pointer for X and the punctuation character for CODE.
4396 The m68k specific codes are:
4398 '.' for dot needed in Motorola-style opcode names.
4399 '-' for an operand pushing on the stack:
4400 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4401 '+' for an operand pushing on the stack:
4402 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4403 '@' for a reference to the top word on the stack:
4404 sp@, (sp) or (%sp) depending on the style of syntax.
4405 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4406 but & in SGS syntax).
4407 '!' for the cc register (used in an `and to cc' insn).
4408 '$' for the letter `s' in an op code, but only on the 68040.
4409 '&' for the letter `d' in an op code, but only on the 68040.
4410 '/' for register prefix needed by longlong.h.
4411 '?' for m68k_library_id_string
4413 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4414 'd' to force memory addressing to be absolute, not relative.
4415 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4416 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4417 or print pair of registers as rx:ry.
4418 'p' print an address with @PLTPC attached, but only if the operand
4419 is not locally-bound. */
4422 print_operand (FILE *file
, rtx op
, int letter
)
4427 fprintf (file
, ".");
4429 else if (letter
== '#')
4430 asm_fprintf (file
, "%I");
4431 else if (letter
== '-')
4432 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4433 else if (letter
== '+')
4434 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4435 else if (letter
== '@')
4436 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4437 else if (letter
== '!')
4438 asm_fprintf (file
, "%Rfpcr");
4439 else if (letter
== '$')
4442 fprintf (file
, "s");
4444 else if (letter
== '&')
4447 fprintf (file
, "d");
4449 else if (letter
== '/')
4450 asm_fprintf (file
, "%R");
4451 else if (letter
== '?')
4452 asm_fprintf (file
, m68k_library_id_string
);
4453 else if (letter
== 'p')
4455 output_addr_const (file
, op
);
4456 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4457 fprintf (file
, "@PLTPC");
4459 else if (GET_CODE (op
) == REG
)
4462 /* Print out the second register name of a register pair.
4463 I.e., R (6) => 7. */
4464 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4466 fputs (M68K_REGNAME(REGNO (op
)), file
);
4468 else if (GET_CODE (op
) == MEM
)
4470 output_address (XEXP (op
, 0));
4471 if (letter
== 'd' && ! TARGET_68020
4472 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4473 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4474 && INTVAL (XEXP (op
, 0)) < 0x8000
4475 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4476 fprintf (file
, MOTOROLA
? ".l" : ":l");
4478 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
4482 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4483 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
4484 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
4486 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
4490 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4491 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
4492 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
4493 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
4495 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
4499 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4500 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
4501 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
4505 /* Use `print_operand_address' instead of `output_addr_const'
4506 to ensure that we print relevant PIC stuff. */
4507 asm_fprintf (file
, "%I");
4509 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
4510 print_operand_address (file
, op
);
4512 output_addr_const (file
, op
);
4516 /* Return string for TLS relocation RELOC. */
4519 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
4521 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4522 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
4529 if (flag_pic
== 1 && TARGET_68020
)
4570 /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */
4573 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4575 if (GET_CODE (x
) == UNSPEC
)
4577 switch (XINT (x
, 1))
4579 case UNSPEC_RELOC16
:
4580 case UNSPEC_RELOC32
:
4581 output_addr_const (file
, XVECEXP (x
, 0, 0));
4582 fputs (m68k_get_reloc_decoration
4583 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
4594 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4597 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4599 gcc_assert (size
== 4);
4600 fputs ("\t.long\t", file
);
4601 output_addr_const (file
, x
);
4602 fputs ("@TLSLDO+0x8000", file
);
4605 /* In the name of slightly smaller debug output, and to cater to
4606 general assembler lossage, recognize various UNSPEC sequences
4607 and turn them back into a direct symbol reference. */
4610 m68k_delegitimize_address (rtx orig_x
)
4613 struct m68k_address addr
;
4616 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4621 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
4624 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
4625 || addr
.offset
== NULL_RTX
4626 || GET_CODE (addr
.offset
) != CONST
)
4629 unspec
= XEXP (addr
.offset
, 0);
4630 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
4631 unspec
= XEXP (unspec
, 0);
4632 if (GET_CODE (unspec
) != UNSPEC
4633 || (XINT (unspec
, 1) != UNSPEC_RELOC16
4634 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
4636 x
= XVECEXP (unspec
, 0, 0);
4637 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
4638 if (unspec
!= XEXP (addr
.offset
, 0))
4639 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
4642 rtx idx
= addr
.index
;
4643 if (addr
.scale
!= 1)
4644 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
4645 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
4648 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
4650 x
= replace_equiv_address_nv (orig_x
, x
);
4655 /* A C compound statement to output to stdio stream STREAM the
4656 assembler syntax for an instruction operand that is a memory
4657 reference whose address is ADDR. ADDR is an RTL expression.
4659 Note that this contains a kludge that knows that the only reason
4660 we have an address (plus (label_ref...) (reg...)) when not generating
4661 PIC code is in the insn before a tablejump, and we know that m68k.md
4662 generates a label LInnn: on such an insn.
4664 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4665 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4667 This routine is responsible for distinguishing between -fpic and -fPIC
4668 style relocations in an address. When generating -fpic code the
4669 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4670 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4673 print_operand_address (FILE *file
, rtx addr
)
4675 struct m68k_address address
;
4677 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4680 if (address
.code
== PRE_DEC
)
4681 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4682 M68K_REGNAME (REGNO (address
.base
)));
4683 else if (address
.code
== POST_INC
)
4684 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4685 M68K_REGNAME (REGNO (address
.base
)));
4686 else if (!address
.base
&& !address
.index
)
4688 /* A constant address. */
4689 gcc_assert (address
.offset
== addr
);
4690 if (GET_CODE (addr
) == CONST_INT
)
4692 /* (xxx).w or (xxx).l. */
4693 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4694 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4696 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4698 else if (TARGET_PCREL
)
4700 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4702 output_addr_const (file
, addr
);
4703 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4707 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4708 name ends in `.<letter>', as the last 2 characters can be
4709 mistaken as a size suffix. Put the name in parentheses. */
4710 if (GET_CODE (addr
) == SYMBOL_REF
4711 && strlen (XSTR (addr
, 0)) > 2
4712 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4715 output_addr_const (file
, addr
);
4719 output_addr_const (file
, addr
);
4726 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4727 label being accessed, otherwise it is -1. */
4728 labelno
= (address
.offset
4730 && GET_CODE (address
.offset
) == LABEL_REF
4731 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4735 /* Print the "offset(base" component. */
4737 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4741 output_addr_const (file
, address
.offset
);
4745 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4747 /* Print the ",index" component, if any. */
4752 fprintf (file
, "%s.%c",
4753 M68K_REGNAME (REGNO (address
.index
)),
4754 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4755 if (address
.scale
!= 1)
4756 fprintf (file
, "*%d", address
.scale
);
4760 else /* !MOTOROLA */
4762 if (!address
.offset
&& !address
.index
)
4763 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4766 /* Print the "base@(offset" component. */
4768 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4772 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4773 fprintf (file
, "@(");
4775 output_addr_const (file
, address
.offset
);
4777 /* Print the ",index" component, if any. */
4780 fprintf (file
, ",%s:%c",
4781 M68K_REGNAME (REGNO (address
.index
)),
4782 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4783 if (address
.scale
!= 1)
4784 fprintf (file
, ":%d", address
.scale
);
4792 /* Check for cases where a clr insns can be omitted from code using
4793 strict_low_part sets. For example, the second clrl here is not needed:
4794 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4796 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4797 insn we are checking for redundancy. TARGET is the register set by the
4801 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
4806 while ((p
= PREV_INSN (p
)))
4808 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4814 /* If it isn't an insn, then give up. */
4818 if (reg_set_p (target
, p
))
4820 rtx set
= single_set (p
);
4823 /* If it isn't an easy to recognize insn, then give up. */
4827 dest
= SET_DEST (set
);
4829 /* If this sets the entire target register to zero, then our
4830 first_insn is redundant. */
4831 if (rtx_equal_p (dest
, target
)
4832 && SET_SRC (set
) == const0_rtx
)
4834 else if (GET_CODE (dest
) == STRICT_LOW_PART
4835 && GET_CODE (XEXP (dest
, 0)) == REG
4836 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4837 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4838 <= GET_MODE_SIZE (mode
)))
4839 /* This is a strict low part set which modifies less than
4840 we are using, so it is safe. */
4850 /* Operand predicates for implementing asymmetric pc-relative addressing
4851 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4852 when used as a source operand, but not as a destination operand.
4854 We model this by restricting the meaning of the basic predicates
4855 (general_operand, memory_operand, etc) to forbid the use of this
4856 addressing mode, and then define the following predicates that permit
4857 this addressing mode. These predicates can then be used for the
4858 source operands of the appropriate instructions.
4860 n.b. While it is theoretically possible to change all machine patterns
4861 to use this addressing more where permitted by the architecture,
4862 it has only been implemented for "common" cases: SImode, HImode, and
4863 QImode operands, and only for the principle operations that would
4864 require this addressing mode: data movement and simple integer operations.
4866 In parallel with these new predicates, two new constraint letters
4867 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4868 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4869 In the pcrel case 's' is only valid in combination with 'a' registers.
4870 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4871 of how these constraints are used.
4873 The use of these predicates is strictly optional, though patterns that
4874 don't will cause an extra reload register to be allocated where one
4877 lea (abc:w,%pc),%a0 ; need to reload address
4878 moveq &1,%d1 ; since write to pc-relative space
4879 movel %d1,%a0@ ; is not allowed
4881 lea (abc:w,%pc),%a1 ; no need to reload address here
4882 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4884 For more info, consult tiemann@cygnus.com.
4887 All of the ugliness with predicates and constraints is due to the
4888 simple fact that the m68k does not allow a pc-relative addressing
4889 mode as a destination. gcc does not distinguish between source and
4890 destination addresses. Hence, if we claim that pc-relative address
4891 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4892 end up with invalid code. To get around this problem, we left
4893 pc-relative modes as invalid addresses, and then added special
4894 predicates and constraints to accept them.
4896 A cleaner way to handle this is to modify gcc to distinguish
4897 between source and destination addresses. We can then say that
4898 pc-relative is a valid source address but not a valid destination
4899 address, and hopefully avoid a lot of the predicate and constraint
4900 hackery. Unfortunately, this would be a pretty big change. It would
4901 be a useful change for a number of ports, but there aren't any current
4902 plans to undertake this.
4904 ***************************************************************************/
4908 output_andsi3 (rtx
*operands
)
4911 if (GET_CODE (operands
[2]) == CONST_INT
4912 && (INTVAL (operands
[2]) | 0xffff) == -1
4913 && (DATA_REG_P (operands
[0])
4914 || offsettable_memref_p (operands
[0]))
4915 && !TARGET_COLDFIRE
)
4917 if (GET_CODE (operands
[0]) != REG
)
4918 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4919 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4920 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4922 if (operands
[2] == const0_rtx
)
4924 return "and%.w %2,%0";
4926 if (GET_CODE (operands
[2]) == CONST_INT
4927 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
4928 && (DATA_REG_P (operands
[0])
4929 || offsettable_memref_p (operands
[0])))
4931 if (DATA_REG_P (operands
[0]))
4932 operands
[1] = GEN_INT (logval
);
4935 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4936 operands
[1] = GEN_INT (logval
% 8);
4938 /* This does not set condition codes in a standard way. */
4940 return "bclr %1,%0";
4942 return "and%.l %2,%0";
4946 output_iorsi3 (rtx
*operands
)
4948 register int logval
;
4949 if (GET_CODE (operands
[2]) == CONST_INT
4950 && INTVAL (operands
[2]) >> 16 == 0
4951 && (DATA_REG_P (operands
[0])
4952 || offsettable_memref_p (operands
[0]))
4953 && !TARGET_COLDFIRE
)
4955 if (GET_CODE (operands
[0]) != REG
)
4956 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4957 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4959 if (INTVAL (operands
[2]) == 0xffff)
4960 return "mov%.w %2,%0";
4961 return "or%.w %2,%0";
4963 if (GET_CODE (operands
[2]) == CONST_INT
4964 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4965 && (DATA_REG_P (operands
[0])
4966 || offsettable_memref_p (operands
[0])))
4968 if (DATA_REG_P (operands
[0]))
4969 operands
[1] = GEN_INT (logval
);
4972 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4973 operands
[1] = GEN_INT (logval
% 8);
4976 return "bset %1,%0";
4978 return "or%.l %2,%0";
4982 output_xorsi3 (rtx
*operands
)
4984 register int logval
;
4985 if (GET_CODE (operands
[2]) == CONST_INT
4986 && INTVAL (operands
[2]) >> 16 == 0
4987 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
4988 && !TARGET_COLDFIRE
)
4990 if (! DATA_REG_P (operands
[0]))
4991 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4992 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4994 if (INTVAL (operands
[2]) == 0xffff)
4996 return "eor%.w %2,%0";
4998 if (GET_CODE (operands
[2]) == CONST_INT
4999 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
5000 && (DATA_REG_P (operands
[0])
5001 || offsettable_memref_p (operands
[0])))
5003 if (DATA_REG_P (operands
[0]))
5004 operands
[1] = GEN_INT (logval
);
5007 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
5008 operands
[1] = GEN_INT (logval
% 8);
5011 return "bchg %1,%0";
5013 return "eor%.l %2,%0";
5016 /* Return the instruction that should be used for a call to address X,
5017 which is known to be in operand 0. */
5022 if (symbolic_operand (x
, VOIDmode
))
5023 return m68k_symbolic_call
;
5028 /* Likewise sibling calls. */
5031 output_sibcall (rtx x
)
5033 if (symbolic_operand (x
, VOIDmode
))
5034 return m68k_symbolic_jump
;
5040 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
5041 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
5044 rtx this_slot
, offset
, addr
, mem
, insn
, tmp
;
5046 /* Avoid clobbering the struct value reg by using the
5047 static chain reg as a temporary. */
5048 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5050 /* Pretend to be a post-reload pass while generating rtl. */
5051 reload_completed
= 1;
5053 /* The "this" pointer is stored at 4(%sp). */
5054 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
,
5055 stack_pointer_rtx
, 4));
5057 /* Add DELTA to THIS. */
5060 /* Make the offset a legitimate operand for memory addition. */
5061 offset
= GEN_INT (delta
);
5062 if ((delta
< -8 || delta
> 8)
5063 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5065 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5066 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5068 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5069 copy_rtx (this_slot
), offset
));
5072 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5073 if (vcall_offset
!= 0)
5075 /* Set the static chain register to *THIS. */
5076 emit_move_insn (tmp
, this_slot
);
5077 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5079 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5080 addr
= plus_constant (Pmode
, tmp
, vcall_offset
);
5081 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5083 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, addr
));
5087 /* Load the offset into %d0 and add it to THIS. */
5088 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5089 gen_rtx_MEM (Pmode
, addr
));
5090 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5091 copy_rtx (this_slot
),
5092 gen_rtx_REG (Pmode
, D0_REG
)));
5095 /* Jump to the target function. Use a sibcall if direct jumps are
5096 allowed, otherwise load the address into a register first. */
5097 mem
= DECL_RTL (function
);
5098 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5100 gcc_assert (flag_pic
);
5102 if (!TARGET_SEP_DATA
)
5104 /* Use the static chain register as a temporary (call-clobbered)
5105 GOT pointer for this function. We can use the static chain
5106 register because it isn't live on entry to the thunk. */
5107 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5108 emit_insn (gen_load_got (pic_offset_table_rtx
));
5110 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5111 mem
= replace_equiv_address (mem
, tmp
);
5113 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5114 SIBLING_CALL_P (insn
) = 1;
5116 /* Run just enough of rest_of_compilation. */
5117 insn
= get_insns ();
5118 split_all_insns_noflow ();
5119 final_start_function (insn
, file
, 1);
5120 final (insn
, file
, 1);
5121 final_end_function ();
5123 /* Clean up the vars set above. */
5124 reload_completed
= 0;
5126 /* Restore the original PIC register. */
5128 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5131 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5134 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5135 int incoming ATTRIBUTE_UNUSED
)
5137 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5140 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5142 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5143 unsigned int new_reg
)
5146 /* Interrupt functions can only use registers that have already been
5147 saved by the prologue, even if they would normally be
5150 if ((m68k_get_function_kind (current_function_decl
)
5151 == m68k_fk_interrupt_handler
)
5152 && !df_regs_ever_live_p (new_reg
))
5158 /* Value is true if hard register REGNO can hold a value of machine-mode
5159 MODE. On the 68000, we let the cpu registers can hold any mode, but
5160 restrict the 68881 registers to floating-point modes. */
5163 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
5165 if (DATA_REGNO_P (regno
))
5167 /* Data Registers, can hold aggregate if fits in. */
5168 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5171 else if (ADDRESS_REGNO_P (regno
))
5173 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5176 else if (FP_REGNO_P (regno
))
5178 /* FPU registers, hold float or complex float of long double or
5180 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5181 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5182 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5188 /* Implement SECONDARY_RELOAD_CLASS. */
5191 m68k_secondary_reload_class (enum reg_class rclass
,
5192 enum machine_mode mode
, rtx x
)
5196 regno
= true_regnum (x
);
5198 /* If one operand of a movqi is an address register, the other
5199 operand must be a general register or constant. Other types
5200 of operand must be reloaded through a data register. */
5201 if (GET_MODE_SIZE (mode
) == 1
5202 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5203 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5206 /* PC-relative addresses must be loaded into an address register first. */
5208 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5209 && symbolic_operand (x
, VOIDmode
))
5215 /* Implement PREFERRED_RELOAD_CLASS. */
5218 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5220 enum reg_class secondary_class
;
5222 /* If RCLASS might need a secondary reload, try restricting it to
5223 a class that doesn't. */
5224 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5225 if (secondary_class
!= NO_REGS
5226 && reg_class_subset_p (secondary_class
, rclass
))
5227 return secondary_class
;
5229 /* Prefer to use moveq for in-range constants. */
5230 if (GET_CODE (x
) == CONST_INT
5231 && reg_class_subset_p (DATA_REGS
, rclass
)
5232 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5235 /* ??? Do we really need this now? */
5236 if (GET_CODE (x
) == CONST_DOUBLE
5237 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5239 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5248 /* Return floating point values in a 68881 register. This makes 68881 code
5249 a little bit faster. It also makes -msoft-float code incompatible with
5250 hard-float code, so people have to be careful not to mix the two.
5251 For ColdFire it was decided the ABI incompatibility is undesirable.
5252 If there is need for a hard-float ABI it is probably worth doing it
5253 properly and also passing function arguments in FP registers. */
5255 m68k_libcall_value (enum machine_mode mode
)
5262 return gen_rtx_REG (mode
, FP0_REG
);
5268 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5271 /* Location in which function value is returned.
5272 NOTE: Due to differences in ABIs, don't call this function directly,
5273 use FUNCTION_VALUE instead. */
5275 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5277 enum machine_mode mode
;
5279 mode
= TYPE_MODE (valtype
);
5285 return gen_rtx_REG (mode
, FP0_REG
);
5291 /* If the function returns a pointer, push that into %a0. */
5292 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5293 /* For compatibility with the large body of existing code which
5294 does not always properly declare external functions returning
5295 pointer types, the m68k/SVR4 convention is to copy the value
5296 returned for pointer functions from a0 to d0 in the function
5297 epilogue, so that callers that have neglected to properly
5298 declare the callee can still find the correct return value in
5300 return gen_rtx_PARALLEL
5303 gen_rtx_EXPR_LIST (VOIDmode
,
5304 gen_rtx_REG (mode
, A0_REG
),
5306 gen_rtx_EXPR_LIST (VOIDmode
,
5307 gen_rtx_REG (mode
, D0_REG
),
5309 else if (POINTER_TYPE_P (valtype
))
5310 return gen_rtx_REG (mode
, A0_REG
);
5312 return gen_rtx_REG (mode
, D0_REG
);
5315 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5316 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5318 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5320 enum machine_mode mode
= TYPE_MODE (type
);
5322 if (mode
== BLKmode
)
5325 /* If TYPE's known alignment is less than the alignment of MODE that
5326 would contain the structure, then return in memory. We need to
5327 do so to maintain the compatibility between code compiled with
5328 -mstrict-align and that compiled with -mno-strict-align. */
5329 if (AGGREGATE_TYPE_P (type
)
5330 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5337 /* CPU to schedule the program for. */
5338 enum attr_cpu m68k_sched_cpu
;
5340 /* MAC to schedule the program for. */
5341 enum attr_mac m68k_sched_mac
;
5349 /* Integer register. */
5355 /* Implicit mem reference (e.g. stack). */
5358 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5361 /* Memory with offset but without indexing. EA mode 5. */
5364 /* Memory with indexing. EA mode 6. */
5367 /* Memory referenced by absolute address. EA mode 7. */
5370 /* Immediate operand that doesn't require extension word. */
5373 /* Immediate 16 bit operand. */
5376 /* Immediate 32 bit operand. */
5380 /* Return type of memory ADDR_RTX refers to. */
5381 static enum attr_op_type
5382 sched_address_type (enum machine_mode mode
, rtx addr_rtx
)
5384 struct m68k_address address
;
5386 if (symbolic_operand (addr_rtx
, VOIDmode
))
5387 return OP_TYPE_MEM7
;
5389 if (!m68k_decompose_address (mode
, addr_rtx
,
5390 reload_completed
, &address
))
5392 gcc_assert (!reload_completed
);
5393 /* Reload will likely fix the address to be in the register. */
5394 return OP_TYPE_MEM234
;
5397 if (address
.scale
!= 0)
5398 return OP_TYPE_MEM6
;
5400 if (address
.base
!= NULL_RTX
)
5402 if (address
.offset
== NULL_RTX
)
5403 return OP_TYPE_MEM234
;
5405 return OP_TYPE_MEM5
;
5408 gcc_assert (address
.offset
!= NULL_RTX
);
5410 return OP_TYPE_MEM7
;
5413 /* Return X or Y (depending on OPX_P) operand of INSN. */
5415 sched_get_operand (rtx insn
, bool opx_p
)
5419 if (recog_memoized (insn
) < 0)
5422 extract_constrain_insn_cached (insn
);
5425 i
= get_attr_opx (insn
);
5427 i
= get_attr_opy (insn
);
5429 if (i
>= recog_data
.n_operands
)
5432 return recog_data
.operand
[i
];
5435 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5436 If ADDRESS_P is true, return type of memory location operand refers to. */
5437 static enum attr_op_type
5438 sched_attr_op_type (rtx insn
, bool opx_p
, bool address_p
)
5442 op
= sched_get_operand (insn
, opx_p
);
5446 gcc_assert (!reload_completed
);
5451 return sched_address_type (QImode
, op
);
5453 if (memory_operand (op
, VOIDmode
))
5454 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
5456 if (register_operand (op
, VOIDmode
))
5458 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
5459 || (reload_completed
&& FP_REG_P (op
)))
5465 if (GET_CODE (op
) == CONST_INT
)
5471 /* Check for quick constants. */
5472 switch (get_attr_type (insn
))
5475 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
5476 return OP_TYPE_IMM_Q
;
5478 gcc_assert (!reload_completed
);
5482 if (USE_MOVQ (ival
))
5483 return OP_TYPE_IMM_Q
;
5485 gcc_assert (!reload_completed
);
5489 if (valid_mov3q_const (ival
))
5490 return OP_TYPE_IMM_Q
;
5492 gcc_assert (!reload_completed
);
5499 if (IN_RANGE (ival
, -0x8000, 0x7fff))
5500 return OP_TYPE_IMM_W
;
5502 return OP_TYPE_IMM_L
;
5505 if (GET_CODE (op
) == CONST_DOUBLE
)
5507 switch (GET_MODE (op
))
5510 return OP_TYPE_IMM_W
;
5514 return OP_TYPE_IMM_L
;
5521 if (GET_CODE (op
) == CONST
5522 || symbolic_operand (op
, VOIDmode
)
5525 switch (GET_MODE (op
))
5528 return OP_TYPE_IMM_Q
;
5531 return OP_TYPE_IMM_W
;
5534 return OP_TYPE_IMM_L
;
5537 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
5539 return OP_TYPE_IMM_W
;
5541 return OP_TYPE_IMM_L
;
5545 gcc_assert (!reload_completed
);
5547 if (FLOAT_MODE_P (GET_MODE (op
)))
5553 /* Implement opx_type attribute.
5554 Return type of INSN's operand X.
5555 If ADDRESS_P is true, return type of memory location operand refers to. */
5557 m68k_sched_attr_opx_type (rtx insn
, int address_p
)
5559 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
5565 return OPX_TYPE_FPN
;
5568 return OPX_TYPE_MEM1
;
5570 case OP_TYPE_MEM234
:
5571 return OPX_TYPE_MEM234
;
5574 return OPX_TYPE_MEM5
;
5577 return OPX_TYPE_MEM6
;
5580 return OPX_TYPE_MEM7
;
5583 return OPX_TYPE_IMM_Q
;
5586 return OPX_TYPE_IMM_W
;
5589 return OPX_TYPE_IMM_L
;
5596 /* Implement opy_type attribute.
5597 Return type of INSN's operand Y.
5598 If ADDRESS_P is true, return type of memory location operand refers to. */
5600 m68k_sched_attr_opy_type (rtx insn
, int address_p
)
5602 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
5608 return OPY_TYPE_FPN
;
5611 return OPY_TYPE_MEM1
;
5613 case OP_TYPE_MEM234
:
5614 return OPY_TYPE_MEM234
;
5617 return OPY_TYPE_MEM5
;
5620 return OPY_TYPE_MEM6
;
5623 return OPY_TYPE_MEM7
;
5626 return OPY_TYPE_IMM_Q
;
5629 return OPY_TYPE_IMM_W
;
5632 return OPY_TYPE_IMM_L
;
5639 /* Return size of INSN as int. */
5641 sched_get_attr_size_int (rtx insn
)
5645 switch (get_attr_type (insn
))
5648 /* There should be no references to m68k_sched_attr_size for 'ignore'
5662 switch (get_attr_opx_type (insn
))
5668 case OPX_TYPE_MEM234
:
5669 case OPY_TYPE_IMM_Q
:
5674 /* Here we assume that most absolute references are short. */
5676 case OPY_TYPE_IMM_W
:
5680 case OPY_TYPE_IMM_L
:
5688 switch (get_attr_opy_type (insn
))
5694 case OPY_TYPE_MEM234
:
5695 case OPY_TYPE_IMM_Q
:
5700 /* Here we assume that most absolute references are short. */
5702 case OPY_TYPE_IMM_W
:
5706 case OPY_TYPE_IMM_L
:
5716 gcc_assert (!reload_completed
);
5724 /* Return size of INSN as attribute enum value. */
5726 m68k_sched_attr_size (rtx insn
)
5728 switch (sched_get_attr_size_int (insn
))
5744 /* Return operand X or Y (depending on OPX_P) of INSN,
5745 if it is a MEM, or NULL overwise. */
5746 static enum attr_op_type
5747 sched_get_opxy_mem_type (rtx insn
, bool opx_p
)
5751 switch (get_attr_opx_type (insn
))
5756 case OPX_TYPE_IMM_Q
:
5757 case OPX_TYPE_IMM_W
:
5758 case OPX_TYPE_IMM_L
:
5762 case OPX_TYPE_MEM234
:
5765 return OP_TYPE_MEM1
;
5768 return OP_TYPE_MEM6
;
5776 switch (get_attr_opy_type (insn
))
5781 case OPY_TYPE_IMM_Q
:
5782 case OPY_TYPE_IMM_W
:
5783 case OPY_TYPE_IMM_L
:
5787 case OPY_TYPE_MEM234
:
5790 return OP_TYPE_MEM1
;
5793 return OP_TYPE_MEM6
;
5801 /* Implement op_mem attribute. */
5803 m68k_sched_attr_op_mem (rtx insn
)
5805 enum attr_op_type opx
;
5806 enum attr_op_type opy
;
5808 opx
= sched_get_opxy_mem_type (insn
, true);
5809 opy
= sched_get_opxy_mem_type (insn
, false);
5811 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5814 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5816 switch (get_attr_opx_access (insn
))
5832 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5834 switch (get_attr_opx_access (insn
))
5850 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5853 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5855 switch (get_attr_opx_access (insn
))
5861 gcc_assert (!reload_completed
);
5866 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5868 switch (get_attr_opx_access (insn
))
5874 gcc_assert (!reload_completed
);
5879 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5882 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5884 switch (get_attr_opx_access (insn
))
5890 gcc_assert (!reload_completed
);
5895 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5896 gcc_assert (!reload_completed
);
5900 /* Data for ColdFire V4 index bypass.
5901 Producer modifies register that is used as index in consumer with
5905 /* Producer instruction. */
5908 /* Consumer instruction. */
5911 /* Scale of indexed memory access within consumer.
5912 Or zero if bypass should not be effective at the moment. */
5914 } sched_cfv4_bypass_data
;
5916 /* An empty state that is used in m68k_sched_adjust_cost. */
5917 static state_t sched_adjust_cost_state
;
5919 /* Implement adjust_cost scheduler hook.
5920 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5922 m68k_sched_adjust_cost (rtx insn
, rtx link ATTRIBUTE_UNUSED
, rtx def_insn
,
5927 if (recog_memoized (def_insn
) < 0
5928 || recog_memoized (insn
) < 0)
5931 if (sched_cfv4_bypass_data
.scale
== 1)
5932 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5934 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5935 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5936 that the data in sched_cfv4_bypass_data is up to date. */
5937 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5938 && sched_cfv4_bypass_data
.con
== insn
);
5943 sched_cfv4_bypass_data
.pro
= NULL
;
5944 sched_cfv4_bypass_data
.con
= NULL
;
5945 sched_cfv4_bypass_data
.scale
= 0;
5948 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
5949 && sched_cfv4_bypass_data
.con
== NULL
5950 && sched_cfv4_bypass_data
.scale
== 0);
5952 /* Don't try to issue INSN earlier than DFA permits.
5953 This is especially useful for instructions that write to memory,
5954 as their true dependence (default) latency is better to be set to 0
5955 to workaround alias analysis limitations.
5956 This is, in fact, a machine independent tweak, so, probably,
5957 it should be moved to haifa-sched.c: insn_cost (). */
5958 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
5965 /* Return maximal number of insns that can be scheduled on a single cycle. */
5967 m68k_sched_issue_rate (void)
5969 switch (m68k_sched_cpu
)
5985 /* Maximal length of instruction for current CPU.
5986 E.g. it is 3 for any ColdFire core. */
5987 static int max_insn_size
;
5989 /* Data to model instruction buffer of CPU. */
5992 /* True if instruction buffer model is modeled for current CPU. */
5995 /* Size of the instruction buffer in words. */
5998 /* Number of filled words in the instruction buffer. */
6001 /* Additional information about instruction buffer for CPUs that have
6002 a buffer of instruction records, rather then a plain buffer
6003 of instruction words. */
6004 struct _sched_ib_records
6006 /* Size of buffer in records. */
6009 /* Array to hold data on adjustements made to the size of the buffer. */
6012 /* Index of the above array. */
6016 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6020 static struct _sched_ib sched_ib
;
6022 /* ID of memory unit. */
6023 static int sched_mem_unit_code
;
6025 /* Implementation of the targetm.sched.variable_issue () hook.
6026 It is called after INSN was issued. It returns the number of insns
6027 that can possibly get scheduled on the current cycle.
6028 It is used here to determine the effect of INSN on the instruction
6031 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6032 int sched_verbose ATTRIBUTE_UNUSED
,
6033 rtx insn
, int can_issue_more
)
6037 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6039 switch (m68k_sched_cpu
)
6043 insn_size
= sched_get_attr_size_int (insn
);
6047 insn_size
= sched_get_attr_size_int (insn
);
6049 /* ColdFire V3 and V4 cores have instruction buffers that can
6050 accumulate up to 8 instructions regardless of instructions'
6051 sizes. So we should take care not to "prefetch" 24 one-word
6052 or 12 two-words instructions.
6053 To model this behavior we temporarily decrease size of the
6054 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6058 adjust
= max_insn_size
- insn_size
;
6059 sched_ib
.size
-= adjust
;
6061 if (sched_ib
.filled
> sched_ib
.size
)
6062 sched_ib
.filled
= sched_ib
.size
;
6064 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6067 ++sched_ib
.records
.adjust_index
;
6068 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6069 sched_ib
.records
.adjust_index
= 0;
6071 /* Undo adjustement we did 7 instructions ago. */
6073 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6078 gcc_assert (!sched_ib
.enabled_p
);
6086 if (insn_size
> sched_ib
.filled
)
6087 /* Scheduling for register pressure does not always take DFA into
6088 account. Workaround instruction buffer not being filled enough. */
6090 gcc_assert (sched_pressure
== SCHED_PRESSURE_WEIGHTED
);
6091 insn_size
= sched_ib
.filled
;
6096 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6097 || asm_noperands (PATTERN (insn
)) >= 0)
6098 insn_size
= sched_ib
.filled
;
6102 sched_ib
.filled
-= insn_size
;
6104 return can_issue_more
;
6107 /* Return how many instructions should scheduler lookahead to choose the
6110 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6112 return m68k_sched_issue_rate () - 1;
6115 /* Implementation of targetm.sched.init_global () hook.
6116 It is invoked once per scheduling pass and is used here
6117 to initialize scheduler constants. */
6119 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6120 int sched_verbose ATTRIBUTE_UNUSED
,
6121 int n_insns ATTRIBUTE_UNUSED
)
6123 #ifdef ENABLE_CHECKING
6124 /* Check that all instructions have DFA reservations and
6125 that all instructions can be issued from a clean state. */
6130 state
= alloca (state_size ());
6132 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
6134 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6136 gcc_assert (insn_has_dfa_reservation_p (insn
));
6138 state_reset (state
);
6139 if (state_transition (state
, insn
) >= 0)
6146 /* Setup target cpu. */
6148 /* ColdFire V4 has a set of features to keep its instruction buffer full
6149 (e.g., a separate memory bus for instructions) and, hence, we do not model
6150 buffer for this CPU. */
6151 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6153 switch (m68k_sched_cpu
)
6156 sched_ib
.filled
= 0;
6163 sched_ib
.records
.n_insns
= 0;
6164 sched_ib
.records
.adjust
= NULL
;
6169 sched_ib
.records
.n_insns
= 8;
6170 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6177 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6179 sched_adjust_cost_state
= xmalloc (state_size ());
6180 state_reset (sched_adjust_cost_state
);
6183 emit_insn (gen_ib ());
6184 sched_ib
.insn
= get_insns ();
6188 /* Scheduling pass is now finished. Free/reset static variables. */
6190 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6191 int verbose ATTRIBUTE_UNUSED
)
6193 sched_ib
.insn
= NULL
;
6195 free (sched_adjust_cost_state
);
6196 sched_adjust_cost_state
= NULL
;
6198 sched_mem_unit_code
= 0;
6200 free (sched_ib
.records
.adjust
);
6201 sched_ib
.records
.adjust
= NULL
;
6202 sched_ib
.records
.n_insns
= 0;
6206 /* Implementation of targetm.sched.init () hook.
6207 It is invoked each time scheduler starts on the new block (basic block or
6208 extended basic block). */
6210 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6211 int sched_verbose ATTRIBUTE_UNUSED
,
6212 int n_insns ATTRIBUTE_UNUSED
)
6214 switch (m68k_sched_cpu
)
6222 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6224 memset (sched_ib
.records
.adjust
, 0,
6225 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6226 sched_ib
.records
.adjust_index
= 0;
6230 gcc_assert (!sched_ib
.enabled_p
);
6238 if (sched_ib
.enabled_p
)
6239 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6240 the first cycle. Workaround that. */
6241 sched_ib
.filled
= -2;
6244 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6245 It is invoked just before current cycle finishes and is used here
6246 to track if instruction buffer got its two words this cycle. */
6248 m68k_sched_dfa_pre_advance_cycle (void)
6250 if (!sched_ib
.enabled_p
)
6253 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6255 sched_ib
.filled
+= 2;
6257 if (sched_ib
.filled
> sched_ib
.size
)
6258 sched_ib
.filled
= sched_ib
.size
;
6262 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6263 It is invoked just after new cycle begins and is used here
6264 to setup number of filled words in the instruction buffer so that
6265 instructions which won't have all their words prefetched would be
6266 stalled for a cycle. */
6268 m68k_sched_dfa_post_advance_cycle (void)
6272 if (!sched_ib
.enabled_p
)
6275 /* Setup number of prefetched instruction words in the instruction
6277 i
= max_insn_size
- sched_ib
.filled
;
6281 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6282 /* Pick up scheduler state. */
6287 /* Return X or Y (depending on OPX_P) operand of INSN,
6288 if it is an integer register, or NULL overwise. */
6290 sched_get_reg_operand (rtx insn
, bool opx_p
)
6296 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6298 op
= sched_get_operand (insn
, true);
6299 gcc_assert (op
!= NULL
);
6301 if (!reload_completed
&& !REG_P (op
))
6307 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6309 op
= sched_get_operand (insn
, false);
6310 gcc_assert (op
!= NULL
);
6312 if (!reload_completed
&& !REG_P (op
))
6320 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6323 sched_mem_operand_p (rtx insn
, bool opx_p
)
6325 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6336 /* Return X or Y (depending on OPX_P) operand of INSN,
6337 if it is a MEM, or NULL overwise. */
6339 sched_get_mem_operand (rtx insn
, bool must_read_p
, bool must_write_p
)
6359 if (opy_p
&& sched_mem_operand_p (insn
, false))
6360 return sched_get_operand (insn
, false);
6362 if (opx_p
&& sched_mem_operand_p (insn
, true))
6363 return sched_get_operand (insn
, true);
6369 /* Return non-zero if PRO modifies register used as part of
6372 m68k_sched_address_bypass_p (rtx pro
, rtx con
)
6377 pro_x
= sched_get_reg_operand (pro
, true);
6381 con_mem_read
= sched_get_mem_operand (con
, true, false);
6382 gcc_assert (con_mem_read
!= NULL
);
6384 if (reg_mentioned_p (pro_x
, con_mem_read
))
6390 /* Helper function for m68k_sched_indexed_address_bypass_p.
6391 if PRO modifies register used as index in CON,
6392 return scale of indexed memory access in CON. Return zero overwise. */
6394 sched_get_indexed_address_scale (rtx pro
, rtx con
)
6398 struct m68k_address address
;
6400 reg
= sched_get_reg_operand (pro
, true);
6404 mem
= sched_get_mem_operand (con
, true, false);
6405 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6407 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6411 if (REGNO (reg
) == REGNO (address
.index
))
6413 gcc_assert (address
.scale
!= 0);
6414 return address
.scale
;
6420 /* Return non-zero if PRO modifies register used
6421 as index with scale 2 or 4 in CON. */
6423 m68k_sched_indexed_address_bypass_p (rtx pro
, rtx con
)
6425 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6426 && sched_cfv4_bypass_data
.con
== NULL
6427 && sched_cfv4_bypass_data
.scale
== 0);
6429 switch (sched_get_indexed_address_scale (pro
, con
))
6432 /* We can't have a variable latency bypass, so
6433 remember to adjust the insn cost in adjust_cost hook. */
6434 sched_cfv4_bypass_data
.pro
= pro
;
6435 sched_cfv4_bypass_data
.con
= con
;
6436 sched_cfv4_bypass_data
.scale
= 1;
6448 /* We generate a two-instructions program at M_TRAMP :
6449 movea.l &CHAIN_VALUE,%a0
6451 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6454 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
6456 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6459 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
6461 mem
= adjust_address (m_tramp
, HImode
, 0);
6462 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
6463 mem
= adjust_address (m_tramp
, SImode
, 2);
6464 emit_move_insn (mem
, chain_value
);
6466 mem
= adjust_address (m_tramp
, HImode
, 6);
6467 emit_move_insn (mem
, GEN_INT(0x4EF9));
6468 mem
= adjust_address (m_tramp
, SImode
, 8);
6469 emit_move_insn (mem
, fnaddr
);
6471 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
6474 /* On the 68000, the RTS insn cannot pop anything.
6475 On the 68010, the RTD insn may be used to pop them if the number
6476 of args is fixed, but if the number is variable then the caller
6477 must pop them all. RTD can't be used for library calls now
6478 because the library is compiled with the Unix compiler.
6479 Use of RTD is a selectable option, since it is incompatible with
6480 standard Unix calling sequences. If the option is not selected,
6481 the caller must always pop the args. */
6484 m68k_return_pops_args (tree fundecl
, tree funtype
, int size
)
6488 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
6489 && (!stdarg_p (funtype
)))
6493 /* Make sure everything's fine if we *don't* have a given processor.
6494 This assumes that putting a register in fixed_regs will keep the
6495 compiler's mitts completely off it. We don't bother to zero it out
6496 of register classes. */
6499 m68k_conditional_register_usage (void)
6503 if (!TARGET_HARD_FLOAT
)
6505 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FP_REGS
]);
6506 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6507 if (TEST_HARD_REG_BIT (x
, i
))
6508 fixed_regs
[i
] = call_used_regs
[i
] = 1;
6511 fixed_regs
[PIC_REG
] = call_used_regs
[PIC_REG
] = 1;
6515 m68k_init_sync_libfuncs (void)
6517 init_sync_libfuncs (UNITS_PER_WORD
);
6520 /* Implements EPILOGUE_USES. All registers are live on exit from an
6521 interrupt routine. */
6523 m68k_epilogue_uses (int regno ATTRIBUTE_UNUSED
)
6525 return (reload_completed
6526 && (m68k_get_function_kind (current_function_decl
)
6527 == m68k_fk_interrupt_handler
));
6530 #include "gt-m68k.h"