1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 #include "insn-codes.h"
95 #include "rtlhooks-def.h"
96 /* Include output.h for dump_file. */
100 /* Number of attempts to combine instructions in this function. */
102 static int combine_attempts
;
104 /* Number of attempts that got as far as substitution in this function. */
106 static int combine_merges
;
108 /* Number of instructions combined with added SETs in this function. */
110 static int combine_extras
;
112 /* Number of instructions combined in this function. */
114 static int combine_successes
;
116 /* Totals over entire compilation. */
118 static int total_attempts
, total_merges
, total_extras
, total_successes
;
121 /* Vector mapping INSN_UIDs to cuids.
122 The cuids are like uids but increase monotonically always.
123 Combine always uses cuids so that it can compare them.
124 But actually renumbering the uids, which we used to do,
125 proves to be a bad idea because it makes it hard to compare
126 the dumps produced by earlier passes with those from later passes. */
128 static int *uid_cuid
;
129 static int max_uid_cuid
;
131 /* Get the cuid of an insn. */
133 #define INSN_CUID(INSN) \
134 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
136 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
137 BITS_PER_WORD would invoke undefined behavior. Work around it. */
139 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
140 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
142 /* Maximum register number, which is the size of the tables below. */
144 static unsigned int combine_max_regno
;
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick
;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
216 char last_set_sign_bit_copies
;
217 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid
;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies
;
239 unsigned HOST_WIDE_INT nonzero_bits
;
242 static struct reg_stat
*reg_stat
;
244 /* Record the cuid of the last insn that invalidated memory
245 (anything that writes memory, and subroutine calls, but not pushes). */
247 static int mem_last_set
;
249 /* Record the cuid of the last CALL_INSN
250 so we can tell whether a potential combination crosses any calls. */
252 static int last_call_cuid
;
254 /* When `subst' is called, this is the insn that is being modified
255 (by combining in a previous insn). The PATTERN of this insn
256 is still the old pattern partially modified and it should not be
257 looked at, but this may be used to examine the successors of the insn
258 to judge whether a simplification is valid. */
260 static rtx subst_insn
;
262 /* This is the lowest CUID that `subst' is currently dealing with.
263 get_last_value will not return a value if the register was set at or
264 after this CUID. If not for this mechanism, we could get confused if
265 I2 or I1 in try_combine were an insn that used the old value of a register
266 to obtain a new value. In that case, we might erroneously get the
267 new value of the register when we wanted the old one. */
269 static int subst_low_cuid
;
271 /* This contains any hard registers that are used in newpat; reg_dead_at_p
272 must consider all these registers to be always live. */
274 static HARD_REG_SET newpat_used_regs
;
276 /* This is an insn to which a LOG_LINKS entry has been added. If this
277 insn is the earlier than I2 or I3, combine should rescan starting at
280 static rtx added_links_insn
;
282 /* Basic block in which we are performing combines. */
283 static basic_block this_basic_block
;
285 /* A bitmap indicating which blocks had registers go dead at entry.
286 After combine, we'll need to re-do global life analysis with
287 those blocks as starting points. */
288 static sbitmap refresh_blocks
;
290 /* The following array records the insn_rtx_cost for every insn
291 in the instruction stream. */
293 static int *uid_insn_cost
;
295 /* Length of the currently allocated uid_insn_cost array. */
297 static int last_insn_cost
;
299 /* Incremented for each label. */
301 static int label_tick
;
303 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
304 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
306 static enum machine_mode nonzero_bits_mode
;
308 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
309 be safely used. It is zero while computing them and after combine has
310 completed. This former test prevents propagating values based on
311 previously set values, which can be incorrect if a variable is modified
314 static int nonzero_sign_valid
;
317 /* Record one modification to rtl structure
318 to be undone by storing old_contents into *where.
319 is_int is 1 if the contents are an int. */
325 union {rtx r
; int i
;} old_contents
;
326 union {rtx
*r
; int *i
;} where
;
329 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
330 num_undo says how many are currently recorded.
332 other_insn is nonzero if we have modified some other insn in the process
333 of working on subst_insn. It must be verified too. */
342 static struct undobuf undobuf
;
344 /* Number of times the pseudo being substituted for
345 was found and replaced. */
347 static int n_occurrences
;
349 static rtx
reg_nonzero_bits_for_combine (rtx
, enum machine_mode
, rtx
,
351 unsigned HOST_WIDE_INT
,
352 unsigned HOST_WIDE_INT
*);
353 static rtx
reg_num_sign_bit_copies_for_combine (rtx
, enum machine_mode
, rtx
,
355 unsigned int, unsigned int *);
356 static void do_SUBST (rtx
*, rtx
);
357 static void do_SUBST_INT (int *, int);
358 static void init_reg_last (void);
359 static void setup_incoming_promotions (void);
360 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
361 static int cant_combine_insn_p (rtx
);
362 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
363 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
364 static int contains_muldiv (rtx
);
365 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
366 static void undo_all (void);
367 static void undo_commit (void);
368 static rtx
*find_split_point (rtx
*, rtx
);
369 static rtx
subst (rtx
, rtx
, rtx
, int, int);
370 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int);
371 static rtx
simplify_if_then_else (rtx
);
372 static rtx
simplify_set (rtx
);
373 static rtx
simplify_logical (rtx
);
374 static rtx
expand_compound_operation (rtx
);
375 static rtx
expand_field_assignment (rtx
);
376 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
377 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
378 static rtx
extract_left_shift (rtx
, int);
379 static rtx
make_compound_operation (rtx
, enum rtx_code
);
380 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
381 unsigned HOST_WIDE_INT
*);
382 static rtx
force_to_mode (rtx
, enum machine_mode
,
383 unsigned HOST_WIDE_INT
, rtx
, int);
384 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
385 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
386 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
387 static rtx
make_field_assignment (rtx
);
388 static rtx
apply_distributive_law (rtx
);
389 static rtx
distribute_and_simplify_rtx (rtx
, int);
390 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
391 unsigned HOST_WIDE_INT
);
392 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
393 HOST_WIDE_INT
, enum machine_mode
, int *);
394 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
396 static int recog_for_combine (rtx
*, rtx
, rtx
*);
397 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
398 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
399 static void update_table_tick (rtx
);
400 static void record_value_for_reg (rtx
, rtx
, rtx
);
401 static void check_promoted_subreg (rtx
, rtx
);
402 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
403 static void record_dead_and_set_regs (rtx
);
404 static int get_last_value_validate (rtx
*, rtx
, int, int);
405 static rtx
get_last_value (rtx
);
406 static int use_crosses_set_p (rtx
, int);
407 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
408 static int reg_dead_at_p (rtx
, rtx
);
409 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
410 static int reg_bitfield_target_p (rtx
, rtx
);
411 static void distribute_notes (rtx
, rtx
, rtx
, rtx
);
412 static void distribute_links (rtx
);
413 static void mark_used_regs_combine (rtx
);
414 static int insn_cuid (rtx
);
415 static void record_promoted_value (rtx
, rtx
);
416 static int unmentioned_reg_p_1 (rtx
*, void *);
417 static bool unmentioned_reg_p (rtx
, rtx
);
420 /* It is not safe to use ordinary gen_lowpart in combine.
421 See comments in gen_lowpart_for_combine. */
422 #undef RTL_HOOKS_GEN_LOWPART
423 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
425 /* Our implementation of gen_lowpart never emits a new pseudo. */
426 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
427 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
429 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
430 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
432 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
433 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
435 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
438 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
439 insn. The substitution can be undone by undo_all. If INTO is already
440 set to NEWVAL, do not record this change. Because computing NEWVAL might
441 also call SUBST, we have to compute it before we put anything into
445 do_SUBST (rtx
*into
, rtx newval
)
450 if (oldval
== newval
)
453 /* We'd like to catch as many invalid transformations here as
454 possible. Unfortunately, there are way too many mode changes
455 that are perfectly valid, so we'd waste too much effort for
456 little gain doing the checks here. Focus on catching invalid
457 transformations involving integer constants. */
458 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
459 && GET_CODE (newval
) == CONST_INT
)
461 /* Sanity check that we're replacing oldval with a CONST_INT
462 that is a valid sign-extension for the original mode. */
463 gcc_assert (INTVAL (newval
)
464 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
466 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
467 CONST_INT is not valid, because after the replacement, the
468 original mode would be gone. Unfortunately, we can't tell
469 when do_SUBST is called to replace the operand thereof, so we
470 perform this test on oldval instead, checking whether an
471 invalid replacement took place before we got here. */
472 gcc_assert (!(GET_CODE (oldval
) == SUBREG
473 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
));
474 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
475 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
));
479 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
481 buf
= xmalloc (sizeof (struct undo
));
485 buf
->old_contents
.r
= oldval
;
488 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
491 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
493 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
494 for the value of a HOST_WIDE_INT value (including CONST_INT) is
498 do_SUBST_INT (int *into
, int newval
)
503 if (oldval
== newval
)
507 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
509 buf
= xmalloc (sizeof (struct undo
));
513 buf
->old_contents
.i
= oldval
;
516 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
519 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
521 /* Subroutine of try_combine. Determine whether the combine replacement
522 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
523 that the original instruction sequence I1, I2 and I3. Note that I1
524 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
525 costs of all instructions can be estimated, and the replacements are
526 more expensive than the original sequence. */
529 combine_validate_cost (rtx i1
, rtx i2
, rtx i3
, rtx newpat
, rtx newi2pat
)
531 int i1_cost
, i2_cost
, i3_cost
;
532 int new_i2_cost
, new_i3_cost
;
533 int old_cost
, new_cost
;
535 /* Lookup the original insn_rtx_costs. */
536 i2_cost
= INSN_UID (i2
) <= last_insn_cost
537 ? uid_insn_cost
[INSN_UID (i2
)] : 0;
538 i3_cost
= INSN_UID (i3
) <= last_insn_cost
539 ? uid_insn_cost
[INSN_UID (i3
)] : 0;
543 i1_cost
= INSN_UID (i1
) <= last_insn_cost
544 ? uid_insn_cost
[INSN_UID (i1
)] : 0;
545 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0)
546 ? i1_cost
+ i2_cost
+ i3_cost
: 0;
550 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
554 /* Calculate the replacement insn_rtx_costs. */
555 new_i3_cost
= insn_rtx_cost (newpat
);
558 new_i2_cost
= insn_rtx_cost (newi2pat
);
559 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
560 ? new_i2_cost
+ new_i3_cost
: 0;
564 new_cost
= new_i3_cost
;
568 if (undobuf
.other_insn
)
570 int old_other_cost
, new_other_cost
;
572 old_other_cost
= (INSN_UID (undobuf
.other_insn
) <= last_insn_cost
573 ? uid_insn_cost
[INSN_UID (undobuf
.other_insn
)] : 0);
574 new_other_cost
= insn_rtx_cost (PATTERN (undobuf
.other_insn
));
575 if (old_other_cost
> 0 && new_other_cost
> 0)
577 old_cost
+= old_other_cost
;
578 new_cost
+= new_other_cost
;
584 /* Disallow this recombination if both new_cost and old_cost are
585 greater than zero, and new_cost is greater than old cost. */
587 && new_cost
> old_cost
)
594 "rejecting combination of insns %d, %d and %d\n",
595 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
596 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
597 i1_cost
, i2_cost
, i3_cost
, old_cost
);
602 "rejecting combination of insns %d and %d\n",
603 INSN_UID (i2
), INSN_UID (i3
));
604 fprintf (dump_file
, "original costs %d + %d = %d\n",
605 i2_cost
, i3_cost
, old_cost
);
610 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
611 new_i2_cost
, new_i3_cost
, new_cost
);
614 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
620 /* Update the uid_insn_cost array with the replacement costs. */
621 uid_insn_cost
[INSN_UID (i2
)] = new_i2_cost
;
622 uid_insn_cost
[INSN_UID (i3
)] = new_i3_cost
;
624 uid_insn_cost
[INSN_UID (i1
)] = 0;
629 /* Main entry point for combiner. F is the first insn of the function.
630 NREGS is the first unused pseudo-reg number.
632 Return nonzero if the combiner has turned an indirect jump
633 instruction into a direct jump. */
635 combine_instructions (rtx f
, unsigned int nregs
)
643 rtx links
, nextlinks
;
644 sbitmap_iterator sbi
;
646 int new_direct_jump_p
= 0;
648 combine_attempts
= 0;
651 combine_successes
= 0;
653 combine_max_regno
= nregs
;
655 rtl_hooks
= combine_rtl_hooks
;
657 reg_stat
= xcalloc (nregs
, sizeof (struct reg_stat
));
659 init_recog_no_volatile ();
661 /* Compute maximum uid value so uid_cuid can be allocated. */
663 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
664 if (INSN_UID (insn
) > i
)
667 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
670 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
672 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
673 problems when, for example, we have j <<= 1 in a loop. */
675 nonzero_sign_valid
= 0;
677 /* Compute the mapping from uids to cuids.
678 Cuids are numbers assigned to insns, like uids,
679 except that cuids increase monotonically through the code.
681 Scan all SETs and see if we can deduce anything about what
682 bits are known to be zero for some registers and how many copies
683 of the sign bit are known to exist for those registers.
685 Also set any known values so that we can use it while searching
686 for what bits are known to be set. */
690 setup_incoming_promotions ();
692 refresh_blocks
= sbitmap_alloc (last_basic_block
);
693 sbitmap_zero (refresh_blocks
);
695 /* Allocate array of current insn_rtx_costs. */
696 uid_insn_cost
= xcalloc (max_uid_cuid
+ 1, sizeof (int));
697 last_insn_cost
= max_uid_cuid
;
699 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
701 uid_cuid
[INSN_UID (insn
)] = ++i
;
707 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
709 record_dead_and_set_regs (insn
);
712 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
713 if (REG_NOTE_KIND (links
) == REG_INC
)
714 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
718 /* Record the current insn_rtx_cost of this instruction. */
719 if (NONJUMP_INSN_P (insn
))
720 uid_insn_cost
[INSN_UID (insn
)] = insn_rtx_cost (PATTERN (insn
));
722 fprintf(dump_file
, "insn_cost %d: %d\n",
723 INSN_UID (insn
), uid_insn_cost
[INSN_UID (insn
)]);
730 nonzero_sign_valid
= 1;
732 /* Now scan all the insns in forward order. */
738 setup_incoming_promotions ();
740 FOR_EACH_BB (this_basic_block
)
742 for (insn
= BB_HEAD (this_basic_block
);
743 insn
!= NEXT_INSN (BB_END (this_basic_block
));
744 insn
= next
? next
: NEXT_INSN (insn
))
751 else if (INSN_P (insn
))
753 /* See if we know about function return values before this
754 insn based upon SUBREG flags. */
755 check_promoted_subreg (insn
, PATTERN (insn
));
757 /* Try this insn with each insn it links back to. */
759 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
760 if ((next
= try_combine (insn
, XEXP (links
, 0),
761 NULL_RTX
, &new_direct_jump_p
)) != 0)
764 /* Try each sequence of three linked insns ending with this one. */
766 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
768 rtx link
= XEXP (links
, 0);
770 /* If the linked insn has been replaced by a note, then there
771 is no point in pursuing this chain any further. */
775 for (nextlinks
= LOG_LINKS (link
);
777 nextlinks
= XEXP (nextlinks
, 1))
778 if ((next
= try_combine (insn
, link
,
780 &new_direct_jump_p
)) != 0)
785 /* Try to combine a jump insn that uses CC0
786 with a preceding insn that sets CC0, and maybe with its
787 logical predecessor as well.
788 This is how we make decrement-and-branch insns.
789 We need this special code because data flow connections
790 via CC0 do not get entered in LOG_LINKS. */
793 && (prev
= prev_nonnote_insn (insn
)) != 0
794 && NONJUMP_INSN_P (prev
)
795 && sets_cc0_p (PATTERN (prev
)))
797 if ((next
= try_combine (insn
, prev
,
798 NULL_RTX
, &new_direct_jump_p
)) != 0)
801 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
802 nextlinks
= XEXP (nextlinks
, 1))
803 if ((next
= try_combine (insn
, prev
,
805 &new_direct_jump_p
)) != 0)
809 /* Do the same for an insn that explicitly references CC0. */
810 if (NONJUMP_INSN_P (insn
)
811 && (prev
= prev_nonnote_insn (insn
)) != 0
812 && NONJUMP_INSN_P (prev
)
813 && sets_cc0_p (PATTERN (prev
))
814 && GET_CODE (PATTERN (insn
)) == SET
815 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
817 if ((next
= try_combine (insn
, prev
,
818 NULL_RTX
, &new_direct_jump_p
)) != 0)
821 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
822 nextlinks
= XEXP (nextlinks
, 1))
823 if ((next
= try_combine (insn
, prev
,
825 &new_direct_jump_p
)) != 0)
829 /* Finally, see if any of the insns that this insn links to
830 explicitly references CC0. If so, try this insn, that insn,
831 and its predecessor if it sets CC0. */
832 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
833 if (NONJUMP_INSN_P (XEXP (links
, 0))
834 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
835 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
836 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
837 && NONJUMP_INSN_P (prev
)
838 && sets_cc0_p (PATTERN (prev
))
839 && (next
= try_combine (insn
, XEXP (links
, 0),
840 prev
, &new_direct_jump_p
)) != 0)
844 /* Try combining an insn with two different insns whose results it
846 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
847 for (nextlinks
= XEXP (links
, 1); nextlinks
;
848 nextlinks
= XEXP (nextlinks
, 1))
849 if ((next
= try_combine (insn
, XEXP (links
, 0),
851 &new_direct_jump_p
)) != 0)
854 /* Try this insn with each REG_EQUAL note it links back to. */
855 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
858 rtx temp
= XEXP (links
, 0);
859 if ((set
= single_set (temp
)) != 0
860 && (note
= find_reg_equal_equiv_note (temp
)) != 0
861 && GET_CODE (XEXP (note
, 0)) != EXPR_LIST
862 /* Avoid using a register that may already been marked
863 dead by an earlier instruction. */
864 && ! unmentioned_reg_p (XEXP (note
, 0), SET_SRC (set
)))
866 /* Temporarily replace the set's source with the
867 contents of the REG_EQUAL note. The insn will
868 be deleted or recognized by try_combine. */
869 rtx orig
= SET_SRC (set
);
870 SET_SRC (set
) = XEXP (note
, 0);
871 next
= try_combine (insn
, temp
, NULL_RTX
,
875 SET_SRC (set
) = orig
;
880 record_dead_and_set_regs (insn
);
889 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, j
, sbi
)
890 BASIC_BLOCK (j
)->flags
|= BB_DIRTY
;
891 new_direct_jump_p
|= purge_all_dead_edges ();
892 delete_noop_moves ();
894 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
895 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
896 | PROP_KILL_DEAD_CODE
);
899 sbitmap_free (refresh_blocks
);
900 free (uid_insn_cost
);
905 struct undo
*undo
, *next
;
906 for (undo
= undobuf
.frees
; undo
; undo
= next
)
914 total_attempts
+= combine_attempts
;
915 total_merges
+= combine_merges
;
916 total_extras
+= combine_extras
;
917 total_successes
+= combine_successes
;
919 nonzero_sign_valid
= 0;
920 rtl_hooks
= general_rtl_hooks
;
922 /* Make recognizer allow volatile MEMs again. */
925 return new_direct_jump_p
;
928 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
934 for (i
= 0; i
< combine_max_regno
; i
++)
935 memset (reg_stat
+ i
, 0, offsetof (struct reg_stat
, sign_bit_copies
));
938 /* Set up any promoted values for incoming argument registers. */
941 setup_incoming_promotions (void)
945 enum machine_mode mode
;
947 rtx first
= get_insns ();
949 if (targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
951 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
952 /* Check whether this register can hold an incoming pointer
953 argument. FUNCTION_ARG_REGNO_P tests outgoing register
954 numbers, so translate if necessary due to register windows. */
955 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
956 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
959 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
962 gen_rtx_CLOBBER (mode
, const0_rtx
)));
967 /* Called via note_stores. If X is a pseudo that is narrower than
968 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
970 If we are setting only a portion of X and we can't figure out what
971 portion, assume all bits will be used since we don't know what will
974 Similarly, set how many bits of X are known to be copies of the sign bit
975 at all locations in the function. This is the smallest number implied
979 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
980 void *data ATTRIBUTE_UNUSED
)
985 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
986 /* If this register is undefined at the start of the file, we can't
987 say what its contents were. */
989 (ENTRY_BLOCK_PTR
->next_bb
->il
.rtl
->global_live_at_start
, REGNO (x
))
990 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
992 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
994 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
995 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
999 /* If this is a complex assignment, see if we can convert it into a
1000 simple assignment. */
1001 set
= expand_field_assignment (set
);
1003 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1004 set what we know about X. */
1006 if (SET_DEST (set
) == x
1007 || (GET_CODE (SET_DEST (set
)) == SUBREG
1008 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
1009 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
1010 && SUBREG_REG (SET_DEST (set
)) == x
))
1012 rtx src
= SET_SRC (set
);
1014 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1015 /* If X is narrower than a word and SRC is a non-negative
1016 constant that would appear negative in the mode of X,
1017 sign-extend it for use in reg_stat[].nonzero_bits because some
1018 machines (maybe most) will actually do the sign-extension
1019 and this is the conservative approach.
1021 ??? For 2.5, try to tighten up the MD files in this regard
1022 instead of this kludge. */
1024 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
1025 && GET_CODE (src
) == CONST_INT
1027 && 0 != (INTVAL (src
)
1028 & ((HOST_WIDE_INT
) 1
1029 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
1030 src
= GEN_INT (INTVAL (src
)
1031 | ((HOST_WIDE_INT
) (-1)
1032 << GET_MODE_BITSIZE (GET_MODE (x
))));
1035 /* Don't call nonzero_bits if it cannot change anything. */
1036 if (reg_stat
[REGNO (x
)].nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1037 reg_stat
[REGNO (x
)].nonzero_bits
1038 |= nonzero_bits (src
, nonzero_bits_mode
);
1039 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1040 if (reg_stat
[REGNO (x
)].sign_bit_copies
== 0
1041 || reg_stat
[REGNO (x
)].sign_bit_copies
> num
)
1042 reg_stat
[REGNO (x
)].sign_bit_copies
= num
;
1046 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1047 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
1052 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1053 insns that were previously combined into I3 or that will be combined
1054 into the merger of INSN and I3.
1056 Return 0 if the combination is not allowed for any reason.
1058 If the combination is allowed, *PDEST will be set to the single
1059 destination of INSN and *PSRC to the single source, and this function
1063 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
1064 rtx
*pdest
, rtx
*psrc
)
1067 rtx set
= 0, src
, dest
;
1072 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
1073 && next_active_insn (succ
) == i3
)
1074 : next_active_insn (insn
) == i3
);
1076 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1077 or a PARALLEL consisting of such a SET and CLOBBERs.
1079 If INSN has CLOBBER parallel parts, ignore them for our processing.
1080 By definition, these happen during the execution of the insn. When it
1081 is merged with another insn, all bets are off. If they are, in fact,
1082 needed and aren't also supplied in I3, they may be added by
1083 recog_for_combine. Otherwise, it won't match.
1085 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1088 Get the source and destination of INSN. If more than one, can't
1091 if (GET_CODE (PATTERN (insn
)) == SET
)
1092 set
= PATTERN (insn
);
1093 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1094 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1096 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1098 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1101 switch (GET_CODE (elt
))
1103 /* This is important to combine floating point insns
1104 for the SH4 port. */
1106 /* Combining an isolated USE doesn't make sense.
1107 We depend here on combinable_i3pat to reject them. */
1108 /* The code below this loop only verifies that the inputs of
1109 the SET in INSN do not change. We call reg_set_between_p
1110 to verify that the REG in the USE does not change between
1112 If the USE in INSN was for a pseudo register, the matching
1113 insn pattern will likely match any register; combining this
1114 with any other USE would only be safe if we knew that the
1115 used registers have identical values, or if there was
1116 something to tell them apart, e.g. different modes. For
1117 now, we forgo such complicated tests and simply disallow
1118 combining of USES of pseudo registers with any other USE. */
1119 if (REG_P (XEXP (elt
, 0))
1120 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1122 rtx i3pat
= PATTERN (i3
);
1123 int i
= XVECLEN (i3pat
, 0) - 1;
1124 unsigned int regno
= REGNO (XEXP (elt
, 0));
1128 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1130 if (GET_CODE (i3elt
) == USE
1131 && REG_P (XEXP (i3elt
, 0))
1132 && (REGNO (XEXP (i3elt
, 0)) == regno
1133 ? reg_set_between_p (XEXP (elt
, 0),
1134 PREV_INSN (insn
), i3
)
1135 : regno
>= FIRST_PSEUDO_REGISTER
))
1142 /* We can ignore CLOBBERs. */
1147 /* Ignore SETs whose result isn't used but not those that
1148 have side-effects. */
1149 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1150 && (!(note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
))
1151 || INTVAL (XEXP (note
, 0)) <= 0)
1152 && ! side_effects_p (elt
))
1155 /* If we have already found a SET, this is a second one and
1156 so we cannot combine with this insn. */
1164 /* Anything else means we can't combine. */
1170 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1171 so don't do anything with it. */
1172 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1181 set
= expand_field_assignment (set
);
1182 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1184 /* Don't eliminate a store in the stack pointer. */
1185 if (dest
== stack_pointer_rtx
1186 /* Don't combine with an insn that sets a register to itself if it has
1187 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1188 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1189 /* Can't merge an ASM_OPERANDS. */
1190 || GET_CODE (src
) == ASM_OPERANDS
1191 /* Can't merge a function call. */
1192 || GET_CODE (src
) == CALL
1193 /* Don't eliminate a function call argument. */
1195 && (find_reg_fusage (i3
, USE
, dest
)
1197 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1198 && global_regs
[REGNO (dest
)])))
1199 /* Don't substitute into an incremented register. */
1200 || FIND_REG_INC_NOTE (i3
, dest
)
1201 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1202 /* Don't substitute into a non-local goto, this confuses CFG. */
1203 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1205 /* Don't combine the end of a libcall into anything. */
1206 /* ??? This gives worse code, and appears to be unnecessary, since no
1207 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1208 use REG_RETVAL notes for noconflict blocks, but other code here
1209 makes sure that those insns don't disappear. */
1210 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1212 /* Make sure that DEST is not used after SUCC but before I3. */
1213 || (succ
&& ! all_adjacent
1214 && reg_used_between_p (dest
, succ
, i3
))
1215 /* Make sure that the value that is to be substituted for the register
1216 does not use any registers whose values alter in between. However,
1217 If the insns are adjacent, a use can't cross a set even though we
1218 think it might (this can happen for a sequence of insns each setting
1219 the same destination; last_set of that register might point to
1220 a NOTE). If INSN has a REG_EQUIV note, the register is always
1221 equivalent to the memory so the substitution is valid even if there
1222 are intervening stores. Also, don't move a volatile asm or
1223 UNSPEC_VOLATILE across any other insns. */
1226 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1227 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1228 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1229 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1230 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1231 better register allocation by not doing the combine. */
1232 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1233 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1234 /* Don't combine across a CALL_INSN, because that would possibly
1235 change whether the life span of some REGs crosses calls or not,
1236 and it is a pain to update that information.
1237 Exception: if source is a constant, moving it later can't hurt.
1238 Accept that special case, because it helps -fforce-addr a lot. */
1239 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1242 /* DEST must either be a REG or CC0. */
1245 /* If register alignment is being enforced for multi-word items in all
1246 cases except for parameters, it is possible to have a register copy
1247 insn referencing a hard register that is not allowed to contain the
1248 mode being copied and which would not be valid as an operand of most
1249 insns. Eliminate this problem by not combining with such an insn.
1251 Also, on some machines we don't want to extend the life of a hard
1255 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1256 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1257 /* Don't extend the life of a hard register unless it is
1258 user variable (if we have few registers) or it can't
1259 fit into the desired register (meaning something special
1261 Also avoid substituting a return register into I3, because
1262 reload can't handle a conflict with constraints of other
1264 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1265 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1268 else if (GET_CODE (dest
) != CC0
)
1272 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1273 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1274 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1276 /* Don't substitute for a register intended as a clobberable
1278 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1279 if (rtx_equal_p (reg
, dest
))
1282 /* If the clobber represents an earlyclobber operand, we must not
1283 substitute an expression containing the clobbered register.
1284 As we do not analyze the constraint strings here, we have to
1285 make the conservative assumption. However, if the register is
1286 a fixed hard reg, the clobber cannot represent any operand;
1287 we leave it up to the machine description to either accept or
1288 reject use-and-clobber patterns. */
1290 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1291 || !fixed_regs
[REGNO (reg
)])
1292 if (reg_overlap_mentioned_p (reg
, src
))
1296 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1297 or not), reject, unless nothing volatile comes between it and I3 */
1299 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1301 /* Make sure succ doesn't contain a volatile reference. */
1302 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1305 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1306 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1310 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1311 to be an explicit register variable, and was chosen for a reason. */
1313 if (GET_CODE (src
) == ASM_OPERANDS
1314 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1317 /* If there are any volatile insns between INSN and I3, reject, because
1318 they might affect machine state. */
1320 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1321 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1324 /* If INSN contains an autoincrement or autodecrement, make sure that
1325 register is not used between there and I3, and not already used in
1326 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1327 Also insist that I3 not be a jump; if it were one
1328 and the incremented register were spilled, we would lose. */
1331 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1332 if (REG_NOTE_KIND (link
) == REG_INC
1334 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1335 || (pred
!= NULL_RTX
1336 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1337 || (succ
!= NULL_RTX
1338 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1339 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1344 /* Don't combine an insn that follows a CC0-setting insn.
1345 An insn that uses CC0 must not be separated from the one that sets it.
1346 We do, however, allow I2 to follow a CC0-setting insn if that insn
1347 is passed as I1; in that case it will be deleted also.
1348 We also allow combining in this case if all the insns are adjacent
1349 because that would leave the two CC0 insns adjacent as well.
1350 It would be more logical to test whether CC0 occurs inside I1 or I2,
1351 but that would be much slower, and this ought to be equivalent. */
1353 p
= prev_nonnote_insn (insn
);
1354 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
1359 /* If we get here, we have passed all the tests and the combination is
1368 /* LOC is the location within I3 that contains its pattern or the component
1369 of a PARALLEL of the pattern. We validate that it is valid for combining.
1371 One problem is if I3 modifies its output, as opposed to replacing it
1372 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1373 so would produce an insn that is not equivalent to the original insns.
1377 (set (reg:DI 101) (reg:DI 100))
1378 (set (subreg:SI (reg:DI 101) 0) <foo>)
1380 This is NOT equivalent to:
1382 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1383 (set (reg:DI 101) (reg:DI 100))])
1385 Not only does this modify 100 (in which case it might still be valid
1386 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1388 We can also run into a problem if I2 sets a register that I1
1389 uses and I1 gets directly substituted into I3 (not via I2). In that
1390 case, we would be getting the wrong value of I2DEST into I3, so we
1391 must reject the combination. This case occurs when I2 and I1 both
1392 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1393 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1394 of a SET must prevent combination from occurring.
1396 Before doing the above check, we first try to expand a field assignment
1397 into a set of logical operations.
1399 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1400 we place a register that is both set and used within I3. If more than one
1401 such register is detected, we fail.
1403 Return 1 if the combination is valid, zero otherwise. */
1406 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1407 int i1_not_in_src
, rtx
*pi3dest_killed
)
1411 if (GET_CODE (x
) == SET
)
1414 rtx dest
= SET_DEST (set
);
1415 rtx src
= SET_SRC (set
);
1416 rtx inner_dest
= dest
;
1418 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1419 || GET_CODE (inner_dest
) == SUBREG
1420 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1421 inner_dest
= XEXP (inner_dest
, 0);
1423 /* Check for the case where I3 modifies its output, as discussed
1424 above. We don't want to prevent pseudos from being combined
1425 into the address of a MEM, so only prevent the combination if
1426 i1 or i2 set the same MEM. */
1427 if ((inner_dest
!= dest
&&
1428 (!MEM_P (inner_dest
)
1429 || rtx_equal_p (i2dest
, inner_dest
)
1430 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1431 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1432 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1434 /* This is the same test done in can_combine_p except we can't test
1435 all_adjacent; we don't have to, since this instruction will stay
1436 in place, thus we are not considering increasing the lifetime of
1439 Also, if this insn sets a function argument, combining it with
1440 something that might need a spill could clobber a previous
1441 function argument; the all_adjacent test in can_combine_p also
1442 checks this; here, we do a more specific test for this case. */
1444 || (REG_P (inner_dest
)
1445 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1446 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1447 GET_MODE (inner_dest
))))
1448 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1451 /* If DEST is used in I3, it is being killed in this insn,
1452 so record that for later.
1453 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1454 STACK_POINTER_REGNUM, since these are always considered to be
1455 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1456 if (pi3dest_killed
&& REG_P (dest
)
1457 && reg_referenced_p (dest
, PATTERN (i3
))
1458 && REGNO (dest
) != FRAME_POINTER_REGNUM
1459 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1460 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1462 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1463 && (REGNO (dest
) != ARG_POINTER_REGNUM
1464 || ! fixed_regs
[REGNO (dest
)])
1466 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1468 if (*pi3dest_killed
)
1471 *pi3dest_killed
= dest
;
1475 else if (GET_CODE (x
) == PARALLEL
)
1479 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1480 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1481 i1_not_in_src
, pi3dest_killed
))
1488 /* Return 1 if X is an arithmetic expression that contains a multiplication
1489 and division. We don't count multiplications by powers of two here. */
1492 contains_muldiv (rtx x
)
1494 switch (GET_CODE (x
))
1496 case MOD
: case DIV
: case UMOD
: case UDIV
:
1500 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1501 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1504 return contains_muldiv (XEXP (x
, 0))
1505 || contains_muldiv (XEXP (x
, 1));
1508 return contains_muldiv (XEXP (x
, 0));
1514 /* Determine whether INSN can be used in a combination. Return nonzero if
1515 not. This is used in try_combine to detect early some cases where we
1516 can't perform combinations. */
1519 cant_combine_insn_p (rtx insn
)
1524 /* If this isn't really an insn, we can't do anything.
1525 This can occur when flow deletes an insn that it has merged into an
1526 auto-increment address. */
1527 if (! INSN_P (insn
))
1530 /* Never combine loads and stores involving hard regs that are likely
1531 to be spilled. The register allocator can usually handle such
1532 reg-reg moves by tying. If we allow the combiner to make
1533 substitutions of likely-spilled regs, reload might die.
1534 As an exception, we allow combinations involving fixed regs; these are
1535 not available to the register allocator so there's no risk involved. */
1537 set
= single_set (insn
);
1540 src
= SET_SRC (set
);
1541 dest
= SET_DEST (set
);
1542 if (GET_CODE (src
) == SUBREG
)
1543 src
= SUBREG_REG (src
);
1544 if (GET_CODE (dest
) == SUBREG
)
1545 dest
= SUBREG_REG (dest
);
1546 if (REG_P (src
) && REG_P (dest
)
1547 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1548 && ! fixed_regs
[REGNO (src
)]
1549 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1550 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1551 && ! fixed_regs
[REGNO (dest
)]
1552 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1558 /* Adjust INSN after we made a change to its destination.
1560 Changing the destination can invalidate notes that say something about
1561 the results of the insn and a LOG_LINK pointing to the insn. */
1564 adjust_for_new_dest (rtx insn
)
1568 /* For notes, be conservative and simply remove them. */
1569 loc
= ®_NOTES (insn
);
1572 enum reg_note kind
= REG_NOTE_KIND (*loc
);
1573 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
1574 *loc
= XEXP (*loc
, 1);
1576 loc
= &XEXP (*loc
, 1);
1579 /* The new insn will have a destination that was previously the destination
1580 of an insn just above it. Call distribute_links to make a LOG_LINK from
1581 the next use of that destination. */
1582 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
1585 /* Try to combine the insns I1 and I2 into I3.
1586 Here I1 and I2 appear earlier than I3.
1587 I1 can be zero; then we combine just I2 into I3.
1589 If we are combining three insns and the resulting insn is not recognized,
1590 try splitting it into two insns. If that happens, I2 and I3 are retained
1591 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1594 Return 0 if the combination does not work. Then nothing is changed.
1595 If we did the combination, return the insn at which combine should
1598 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1599 new direct jump instruction. */
1602 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1604 /* New patterns for I3 and I2, respectively. */
1605 rtx newpat
, newi2pat
= 0;
1606 rtvec newpat_vec_with_clobbers
= 0;
1607 int substed_i2
= 0, substed_i1
= 0;
1608 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1609 int added_sets_1
, added_sets_2
;
1610 /* Total number of SETs to put into I3. */
1612 /* Nonzero if I2's body now appears in I3. */
1614 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1615 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1616 /* Contains I3 if the destination of I3 is used in its source, which means
1617 that the old life of I3 is being killed. If that usage is placed into
1618 I2 and not in I3, a REG_DEAD note must be made. */
1619 rtx i3dest_killed
= 0;
1620 /* SET_DEST and SET_SRC of I2 and I1. */
1621 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1622 /* PATTERN (I2), or a copy of it in certain cases. */
1624 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1625 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1626 int i1_feeds_i3
= 0;
1627 /* Notes that must be added to REG_NOTES in I3 and I2. */
1628 rtx new_i3_notes
, new_i2_notes
;
1629 /* Notes that we substituted I3 into I2 instead of the normal case. */
1630 int i3_subst_into_i2
= 0;
1631 /* Notes that I1, I2 or I3 is a MULT operation. */
1640 /* Exit early if one of the insns involved can't be used for
1642 if (cant_combine_insn_p (i3
)
1643 || cant_combine_insn_p (i2
)
1644 || (i1
&& cant_combine_insn_p (i1
))
1645 /* We also can't do anything if I3 has a
1646 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1649 /* ??? This gives worse code, and appears to be unnecessary, since no
1650 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1651 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1657 undobuf
.other_insn
= 0;
1659 /* Reset the hard register usage information. */
1660 CLEAR_HARD_REG_SET (newpat_used_regs
);
1662 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1663 code below, set I1 to be the earlier of the two insns. */
1664 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1665 temp
= i1
, i1
= i2
, i2
= temp
;
1667 added_links_insn
= 0;
1669 /* First check for one important special-case that the code below will
1670 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1671 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1672 we may be able to replace that destination with the destination of I3.
1673 This occurs in the common code where we compute both a quotient and
1674 remainder into a structure, in which case we want to do the computation
1675 directly into the structure to avoid register-register copies.
1677 Note that this case handles both multiple sets in I2 and also
1678 cases where I2 has a number of CLOBBER or PARALLELs.
1680 We make very conservative checks below and only try to handle the
1681 most common cases of this. For example, we only handle the case
1682 where I2 and I3 are adjacent to avoid making difficult register
1685 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
1686 && REG_P (SET_SRC (PATTERN (i3
)))
1687 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1688 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1689 && GET_CODE (PATTERN (i2
)) == PARALLEL
1690 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1691 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1692 below would need to check what is inside (and reg_overlap_mentioned_p
1693 doesn't support those codes anyway). Don't allow those destinations;
1694 the resulting insn isn't likely to be recognized anyway. */
1695 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1696 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1697 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1698 SET_DEST (PATTERN (i3
)))
1699 && next_real_insn (i2
) == i3
)
1701 rtx p2
= PATTERN (i2
);
1703 /* Make sure that the destination of I3,
1704 which we are going to substitute into one output of I2,
1705 is not used within another output of I2. We must avoid making this:
1706 (parallel [(set (mem (reg 69)) ...)
1707 (set (reg 69) ...)])
1708 which is not well-defined as to order of actions.
1709 (Besides, reload can't handle output reloads for this.)
1711 The problem can also happen if the dest of I3 is a memory ref,
1712 if another dest in I2 is an indirect memory ref. */
1713 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1714 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1715 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1716 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1717 SET_DEST (XVECEXP (p2
, 0, i
))))
1720 if (i
== XVECLEN (p2
, 0))
1721 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1722 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1723 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1724 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1729 subst_low_cuid
= INSN_CUID (i2
);
1731 added_sets_2
= added_sets_1
= 0;
1732 i2dest
= SET_SRC (PATTERN (i3
));
1734 /* Replace the dest in I2 with our dest and make the resulting
1735 insn the new pattern for I3. Then skip to where we
1736 validate the pattern. Everything was set up above. */
1737 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1738 SET_DEST (PATTERN (i3
)));
1741 i3_subst_into_i2
= 1;
1742 goto validate_replacement
;
1746 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1747 one of those words to another constant, merge them by making a new
1750 && (temp
= single_set (i2
)) != 0
1751 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1752 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1753 && REG_P (SET_DEST (temp
))
1754 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1755 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1756 && GET_CODE (PATTERN (i3
)) == SET
1757 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1758 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1759 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1760 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1761 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1763 HOST_WIDE_INT lo
, hi
;
1765 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1766 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1769 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1770 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1773 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1775 /* We don't handle the case of the target word being wider
1776 than a host wide int. */
1777 gcc_assert (HOST_BITS_PER_WIDE_INT
>= BITS_PER_WORD
);
1779 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1780 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1781 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1783 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1784 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1785 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1787 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1788 >> (HOST_BITS_PER_WIDE_INT
- 1));
1790 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1791 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1792 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1793 (INTVAL (SET_SRC (PATTERN (i3
)))));
1795 hi
= lo
< 0 ? -1 : 0;
1798 /* We don't handle the case of the higher word not fitting
1799 entirely in either hi or lo. */
1804 subst_low_cuid
= INSN_CUID (i2
);
1805 added_sets_2
= added_sets_1
= 0;
1806 i2dest
= SET_DEST (temp
);
1808 SUBST (SET_SRC (temp
),
1809 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1811 newpat
= PATTERN (i2
);
1812 goto validate_replacement
;
1816 /* If we have no I1 and I2 looks like:
1817 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1819 make up a dummy I1 that is
1822 (set (reg:CC X) (compare:CC Y (const_int 0)))
1824 (We can ignore any trailing CLOBBERs.)
1826 This undoes a previous combination and allows us to match a branch-and-
1829 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1830 && XVECLEN (PATTERN (i2
), 0) >= 2
1831 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1832 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1834 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1835 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1836 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1837 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
1838 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1839 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1841 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1842 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1847 /* We make I1 with the same INSN_UID as I2. This gives it
1848 the same INSN_CUID for value tracking. Our fake I1 will
1849 never appear in the insn stream so giving it the same INSN_UID
1850 as I2 will not cause a problem. */
1852 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1853 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
1854 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1857 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1858 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1859 SET_DEST (PATTERN (i1
)));
1864 /* Verify that I2 and I1 are valid for combining. */
1865 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1866 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1872 /* Record whether I2DEST is used in I2SRC and similarly for the other
1873 cases. Knowing this will help in register status updating below. */
1874 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1875 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1876 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1878 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1880 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1882 /* Ensure that I3's pattern can be the destination of combines. */
1883 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1884 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1891 /* See if any of the insns is a MULT operation. Unless one is, we will
1892 reject a combination that is, since it must be slower. Be conservative
1894 if (GET_CODE (i2src
) == MULT
1895 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1896 || (GET_CODE (PATTERN (i3
)) == SET
1897 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1900 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1901 We used to do this EXCEPT in one case: I3 has a post-inc in an
1902 output operand. However, that exception can give rise to insns like
1904 which is a famous insn on the PDP-11 where the value of r3 used as the
1905 source was model-dependent. Avoid this sort of thing. */
1908 if (!(GET_CODE (PATTERN (i3
)) == SET
1909 && REG_P (SET_SRC (PATTERN (i3
)))
1910 && MEM_P (SET_DEST (PATTERN (i3
)))
1911 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1912 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1913 /* It's not the exception. */
1916 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1917 if (REG_NOTE_KIND (link
) == REG_INC
1918 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1920 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1927 /* See if the SETs in I1 or I2 need to be kept around in the merged
1928 instruction: whenever the value set there is still needed past I3.
1929 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1931 For the SET in I1, we have two cases: If I1 and I2 independently
1932 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1933 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1934 in I1 needs to be kept around unless I1DEST dies or is set in either
1935 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1936 I1DEST. If so, we know I1 feeds into I2. */
1938 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1941 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1942 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1944 /* If the set in I2 needs to be kept around, we must make a copy of
1945 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1946 PATTERN (I2), we are only substituting for the original I1DEST, not into
1947 an already-substituted copy. This also prevents making self-referential
1948 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1951 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1952 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1956 i2pat
= copy_rtx (i2pat
);
1960 /* Substitute in the latest insn for the regs set by the earlier ones. */
1962 maxreg
= max_reg_num ();
1966 /* It is possible that the source of I2 or I1 may be performing an
1967 unneeded operation, such as a ZERO_EXTEND of something that is known
1968 to have the high part zero. Handle that case by letting subst look at
1969 the innermost one of them.
1971 Another way to do this would be to have a function that tries to
1972 simplify a single insn instead of merging two or more insns. We don't
1973 do this because of the potential of infinite loops and because
1974 of the potential extra memory required. However, doing it the way
1975 we are is a bit of a kludge and doesn't catch all cases.
1977 But only do this if -fexpensive-optimizations since it slows things down
1978 and doesn't usually win. */
1980 if (flag_expensive_optimizations
)
1982 /* Pass pc_rtx so no substitutions are done, just simplifications. */
1985 subst_low_cuid
= INSN_CUID (i1
);
1986 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1990 subst_low_cuid
= INSN_CUID (i2
);
1991 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1996 /* Many machines that don't use CC0 have insns that can both perform an
1997 arithmetic operation and set the condition code. These operations will
1998 be represented as a PARALLEL with the first element of the vector
1999 being a COMPARE of an arithmetic operation with the constant zero.
2000 The second element of the vector will set some pseudo to the result
2001 of the same arithmetic operation. If we simplify the COMPARE, we won't
2002 match such a pattern and so will generate an extra insn. Here we test
2003 for this case, where both the comparison and the operation result are
2004 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2005 I2SRC. Later we will make the PARALLEL that contains I2. */
2007 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
2008 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
2009 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
2010 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2012 #ifdef SELECT_CC_MODE
2014 enum machine_mode compare_mode
;
2017 newpat
= PATTERN (i3
);
2018 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
2022 #ifdef SELECT_CC_MODE
2023 /* See if a COMPARE with the operand we substituted in should be done
2024 with the mode that is currently being used. If not, do the same
2025 processing we do in `subst' for a SET; namely, if the destination
2026 is used only once, try to replace it with a register of the proper
2027 mode and also replace the COMPARE. */
2028 if (undobuf
.other_insn
== 0
2029 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
2030 &undobuf
.other_insn
))
2031 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
2033 != GET_MODE (SET_DEST (newpat
))))
2035 unsigned int regno
= REGNO (SET_DEST (newpat
));
2036 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
2038 if (regno
< FIRST_PSEUDO_REGISTER
2039 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
2040 && ! REG_USERVAR_P (SET_DEST (newpat
))))
2042 if (regno
>= FIRST_PSEUDO_REGISTER
)
2043 SUBST (regno_reg_rtx
[regno
], new_dest
);
2045 SUBST (SET_DEST (newpat
), new_dest
);
2046 SUBST (XEXP (*cc_use
, 0), new_dest
);
2047 SUBST (SET_SRC (newpat
),
2048 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
2051 undobuf
.other_insn
= 0;
2058 n_occurrences
= 0; /* `subst' counts here */
2060 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2061 need to make a unique copy of I2SRC each time we substitute it
2062 to avoid self-referential rtl. */
2064 subst_low_cuid
= INSN_CUID (i2
);
2065 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
2066 ! i1_feeds_i3
&& i1dest_in_i1src
);
2069 /* Record whether i2's body now appears within i3's body. */
2070 i2_is_used
= n_occurrences
;
2073 /* If we already got a failure, don't try to do more. Otherwise,
2074 try to substitute in I1 if we have it. */
2076 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
2078 /* Before we can do this substitution, we must redo the test done
2079 above (see detailed comments there) that ensures that I1DEST
2080 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2082 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
2090 subst_low_cuid
= INSN_CUID (i1
);
2091 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
2095 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2096 to count all the ways that I2SRC and I1SRC can be used. */
2097 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
2098 && i2_is_used
+ added_sets_2
> 1)
2099 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
2100 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
2102 /* Fail if we tried to make a new register. */
2103 || max_reg_num () != maxreg
2104 /* Fail if we couldn't do something and have a CLOBBER. */
2105 || GET_CODE (newpat
) == CLOBBER
2106 /* Fail if this new pattern is a MULT and we didn't have one before
2107 at the outer level. */
2108 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
2115 /* If the actions of the earlier insns must be kept
2116 in addition to substituting them into the latest one,
2117 we must make a new PARALLEL for the latest insn
2118 to hold additional the SETs. */
2120 if (added_sets_1
|| added_sets_2
)
2124 if (GET_CODE (newpat
) == PARALLEL
)
2126 rtvec old
= XVEC (newpat
, 0);
2127 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2128 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2129 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2130 sizeof (old
->elem
[0]) * old
->num_elem
);
2135 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2136 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2137 XVECEXP (newpat
, 0, 0) = old
;
2141 XVECEXP (newpat
, 0, --total_sets
)
2142 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2143 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2147 /* If there is no I1, use I2's body as is. We used to also not do
2148 the subst call below if I2 was substituted into I3,
2149 but that could lose a simplification. */
2151 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2153 /* See comment where i2pat is assigned. */
2154 XVECEXP (newpat
, 0, --total_sets
)
2155 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2159 /* We come here when we are replacing a destination in I2 with the
2160 destination of I3. */
2161 validate_replacement
:
2163 /* Note which hard regs this insn has as inputs. */
2164 mark_used_regs_combine (newpat
);
2166 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2167 consider splitting this pattern, we might need these clobbers. */
2168 if (i1
&& GET_CODE (newpat
) == PARALLEL
2169 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
2171 int len
= XVECLEN (newpat
, 0);
2173 newpat_vec_with_clobbers
= rtvec_alloc (len
);
2174 for (i
= 0; i
< len
; i
++)
2175 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
2178 /* Is the result of combination a valid instruction? */
2179 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2181 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2182 the second SET's destination is a register that is unused and isn't
2183 marked as an instruction that might trap in an EH region. In that case,
2184 we just need the first SET. This can occur when simplifying a divmod
2185 insn. We *must* test for this case here because the code below that
2186 splits two independent SETs doesn't handle this case correctly when it
2187 updates the register status.
2189 It's pointless doing this if we originally had two sets, one from
2190 i3, and one from i2. Combining then splitting the parallel results
2191 in the original i2 again plus an invalid insn (which we delete).
2192 The net effect is only to move instructions around, which makes
2193 debug info less accurate.
2195 Also check the case where the first SET's destination is unused.
2196 That would not cause incorrect code, but does cause an unneeded
2199 if (insn_code_number
< 0
2200 && !(added_sets_2
&& i1
== 0)
2201 && GET_CODE (newpat
) == PARALLEL
2202 && XVECLEN (newpat
, 0) == 2
2203 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2204 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2205 && asm_noperands (newpat
) < 0)
2207 rtx set0
= XVECEXP (newpat
, 0, 0);
2208 rtx set1
= XVECEXP (newpat
, 0, 1);
2211 if (((REG_P (SET_DEST (set1
))
2212 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
2213 || (GET_CODE (SET_DEST (set1
)) == SUBREG
2214 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
2215 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2216 || INTVAL (XEXP (note
, 0)) <= 0)
2217 && ! side_effects_p (SET_SRC (set1
)))
2220 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2223 else if (((REG_P (SET_DEST (set0
))
2224 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
2225 || (GET_CODE (SET_DEST (set0
)) == SUBREG
2226 && find_reg_note (i3
, REG_UNUSED
,
2227 SUBREG_REG (SET_DEST (set0
)))))
2228 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2229 || INTVAL (XEXP (note
, 0)) <= 0)
2230 && ! side_effects_p (SET_SRC (set0
)))
2233 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2235 if (insn_code_number
>= 0)
2237 /* If we will be able to accept this, we have made a
2238 change to the destination of I3. This requires us to
2239 do a few adjustments. */
2241 PATTERN (i3
) = newpat
;
2242 adjust_for_new_dest (i3
);
2247 /* If we were combining three insns and the result is a simple SET
2248 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2249 insns. There are two ways to do this. It can be split using a
2250 machine-specific method (like when you have an addition of a large
2251 constant) or by combine in the function find_split_point. */
2253 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2254 && asm_noperands (newpat
) < 0)
2256 rtx m_split
, *split
;
2257 rtx ni2dest
= i2dest
;
2259 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2260 use I2DEST as a scratch register will help. In the latter case,
2261 convert I2DEST to the mode of the source of NEWPAT if we can. */
2263 m_split
= split_insns (newpat
, i3
);
2265 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2266 inputs of NEWPAT. */
2268 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2269 possible to try that as a scratch reg. This would require adding
2270 more code to make it work though. */
2272 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2274 /* If I2DEST is a hard register or the only use of a pseudo,
2275 we can change its mode. */
2276 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2277 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2279 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2280 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2281 && ! REG_USERVAR_P (i2dest
))))
2282 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2285 m_split
= split_insns (gen_rtx_PARALLEL
2287 gen_rtvec (2, newpat
,
2288 gen_rtx_CLOBBER (VOIDmode
,
2291 /* If the split with the mode-changed register didn't work, try
2292 the original register. */
2293 if (! m_split
&& ni2dest
!= i2dest
)
2296 m_split
= split_insns (gen_rtx_PARALLEL
2298 gen_rtvec (2, newpat
,
2299 gen_rtx_CLOBBER (VOIDmode
,
2305 /* If recog_for_combine has discarded clobbers, try to use them
2306 again for the split. */
2307 if (m_split
== 0 && newpat_vec_with_clobbers
)
2309 = split_insns (gen_rtx_PARALLEL (VOIDmode
,
2310 newpat_vec_with_clobbers
), i3
);
2312 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2314 m_split
= PATTERN (m_split
);
2315 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2316 if (insn_code_number
>= 0)
2319 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2320 && (next_real_insn (i2
) == i3
2321 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2324 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2325 newi2pat
= PATTERN (m_split
);
2327 i3set
= single_set (NEXT_INSN (m_split
));
2328 i2set
= single_set (m_split
);
2330 /* In case we changed the mode of I2DEST, replace it in the
2331 pseudo-register table here. We can't do it above in case this
2332 code doesn't get executed and we do a split the other way. */
2334 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2335 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2337 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2339 /* If I2 or I3 has multiple SETs, we won't know how to track
2340 register status, so don't use these insns. If I2's destination
2341 is used between I2 and I3, we also can't use these insns. */
2343 if (i2_code_number
>= 0 && i2set
&& i3set
2344 && (next_real_insn (i2
) == i3
2345 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2346 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2348 if (insn_code_number
>= 0)
2351 /* It is possible that both insns now set the destination of I3.
2352 If so, we must show an extra use of it. */
2354 if (insn_code_number
>= 0)
2356 rtx new_i3_dest
= SET_DEST (i3set
);
2357 rtx new_i2_dest
= SET_DEST (i2set
);
2359 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2360 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2361 || GET_CODE (new_i3_dest
) == SUBREG
)
2362 new_i3_dest
= XEXP (new_i3_dest
, 0);
2364 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2365 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2366 || GET_CODE (new_i2_dest
) == SUBREG
)
2367 new_i2_dest
= XEXP (new_i2_dest
, 0);
2369 if (REG_P (new_i3_dest
)
2370 && REG_P (new_i2_dest
)
2371 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2372 REG_N_SETS (REGNO (new_i2_dest
))++;
2376 /* If we can split it and use I2DEST, go ahead and see if that
2377 helps things be recognized. Verify that none of the registers
2378 are set between I2 and I3. */
2379 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2383 /* We need I2DEST in the proper mode. If it is a hard register
2384 or the only use of a pseudo, we can change its mode.
2385 Make sure we don't change a hard register to have a mode that
2386 isn't valid for it, or change the number of registers. */
2387 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2388 || GET_MODE (*split
) == VOIDmode
2389 || (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2390 && HARD_REGNO_MODE_OK (REGNO (i2dest
), GET_MODE (*split
))
2391 && (hard_regno_nregs
[REGNO (i2dest
)][GET_MODE (i2dest
)]
2392 == hard_regno_nregs
[REGNO (i2dest
)][GET_MODE (*split
)]))
2393 || (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
2394 && REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2395 && ! REG_USERVAR_P (i2dest
)))
2396 && (next_real_insn (i2
) == i3
2397 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2398 /* We can't overwrite I2DEST if its value is still used by
2400 && ! reg_referenced_p (i2dest
, newpat
))
2402 rtx newdest
= i2dest
;
2403 enum rtx_code split_code
= GET_CODE (*split
);
2404 enum machine_mode split_mode
= GET_MODE (*split
);
2406 /* Get NEWDEST as a register in the proper mode. We have already
2407 validated that we can do this. */
2408 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2410 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2412 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2413 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2416 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2417 an ASHIFT. This can occur if it was inside a PLUS and hence
2418 appeared to be a memory address. This is a kludge. */
2419 if (split_code
== MULT
2420 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2421 && INTVAL (XEXP (*split
, 1)) > 0
2422 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2424 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2425 XEXP (*split
, 0), GEN_INT (i
)));
2426 /* Update split_code because we may not have a multiply
2428 split_code
= GET_CODE (*split
);
2431 #ifdef INSN_SCHEDULING
2432 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2433 be written as a ZERO_EXTEND. */
2434 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
2436 #ifdef LOAD_EXTEND_OP
2437 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2438 what it really is. */
2439 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2441 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2442 SUBREG_REG (*split
)));
2445 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2446 SUBREG_REG (*split
)));
2450 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2451 SUBST (*split
, newdest
);
2452 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2454 /* recog_for_combine might have added CLOBBERs to newi2pat.
2455 Make sure NEWPAT does not depend on the clobbered regs. */
2456 if (GET_CODE (newi2pat
) == PARALLEL
)
2457 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
2458 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
2460 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
2461 if (reg_overlap_mentioned_p (reg
, newpat
))
2468 /* If the split point was a MULT and we didn't have one before,
2469 don't use one now. */
2470 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2471 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2475 /* Check for a case where we loaded from memory in a narrow mode and
2476 then sign extended it, but we need both registers. In that case,
2477 we have a PARALLEL with both loads from the same memory location.
2478 We can split this into a load from memory followed by a register-register
2479 copy. This saves at least one insn, more if register allocation can
2482 We cannot do this if the destination of the first assignment is a
2483 condition code register or cc0. We eliminate this case by making sure
2484 the SET_DEST and SET_SRC have the same mode.
2486 We cannot do this if the destination of the second assignment is
2487 a register that we have already assumed is zero-extended. Similarly
2488 for a SUBREG of such a register. */
2490 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2491 && GET_CODE (newpat
) == PARALLEL
2492 && XVECLEN (newpat
, 0) == 2
2493 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2494 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2495 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2496 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2497 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2498 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2499 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2500 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2502 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2503 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2504 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2506 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
2507 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2508 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2509 && (reg_stat
[REGNO (temp
)].nonzero_bits
2510 != GET_MODE_MASK (word_mode
))))
2511 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2512 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2514 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
2515 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2516 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2517 && (reg_stat
[REGNO (temp
)].nonzero_bits
2518 != GET_MODE_MASK (word_mode
)))))
2519 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2520 SET_SRC (XVECEXP (newpat
, 0, 1)))
2521 && ! find_reg_note (i3
, REG_UNUSED
,
2522 SET_DEST (XVECEXP (newpat
, 0, 0))))
2526 newi2pat
= XVECEXP (newpat
, 0, 0);
2527 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2528 newpat
= XVECEXP (newpat
, 0, 1);
2529 SUBST (SET_SRC (newpat
),
2530 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2531 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2533 if (i2_code_number
>= 0)
2534 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2536 if (insn_code_number
>= 0)
2540 /* Similarly, check for a case where we have a PARALLEL of two independent
2541 SETs but we started with three insns. In this case, we can do the sets
2542 as two separate insns. This case occurs when some SET allows two
2543 other insns to combine, but the destination of that SET is still live. */
2545 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2546 && GET_CODE (newpat
) == PARALLEL
2547 && XVECLEN (newpat
, 0) == 2
2548 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2549 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2550 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2551 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2552 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2553 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2554 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2556 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2557 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2558 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2559 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2560 XVECEXP (newpat
, 0, 0))
2561 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2562 XVECEXP (newpat
, 0, 1))
2563 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2564 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2566 /* Normally, it doesn't matter which of the two is done first,
2567 but it does if one references cc0. In that case, it has to
2570 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2572 newi2pat
= XVECEXP (newpat
, 0, 0);
2573 newpat
= XVECEXP (newpat
, 0, 1);
2578 newi2pat
= XVECEXP (newpat
, 0, 1);
2579 newpat
= XVECEXP (newpat
, 0, 0);
2582 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2584 if (i2_code_number
>= 0)
2585 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2588 /* If it still isn't recognized, fail and change things back the way they
2590 if ((insn_code_number
< 0
2591 /* Is the result a reasonable ASM_OPERANDS? */
2592 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2598 /* If we had to change another insn, make sure it is valid also. */
2599 if (undobuf
.other_insn
)
2601 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2602 rtx new_other_notes
;
2605 CLEAR_HARD_REG_SET (newpat_used_regs
);
2607 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2610 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2616 PATTERN (undobuf
.other_insn
) = other_pat
;
2618 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2619 are still valid. Then add any non-duplicate notes added by
2620 recog_for_combine. */
2621 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2623 next
= XEXP (note
, 1);
2625 if (REG_NOTE_KIND (note
) == REG_UNUSED
2626 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2628 if (REG_P (XEXP (note
, 0)))
2629 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2631 remove_note (undobuf
.other_insn
, note
);
2635 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2636 if (REG_P (XEXP (note
, 0)))
2637 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2639 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2640 undobuf
.other_insn
, NULL_RTX
);
2643 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2644 they are adjacent to each other or not. */
2646 rtx p
= prev_nonnote_insn (i3
);
2647 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
2648 && sets_cc0_p (newi2pat
))
2656 /* Only allow this combination if insn_rtx_costs reports that the
2657 replacement instructions are cheaper than the originals. */
2658 if (!combine_validate_cost (i1
, i2
, i3
, newpat
, newi2pat
))
2664 /* We now know that we can do this combination. Merge the insns and
2665 update the status of registers and LOG_LINKS. */
2673 /* I3 now uses what used to be its destination and which is now
2674 I2's destination. This requires us to do a few adjustments. */
2675 PATTERN (i3
) = newpat
;
2676 adjust_for_new_dest (i3
);
2678 /* We need a LOG_LINK from I3 to I2. But we used to have one,
2681 However, some later insn might be using I2's dest and have
2682 a LOG_LINK pointing at I3. We must remove this link.
2683 The simplest way to remove the link is to point it at I1,
2684 which we know will be a NOTE. */
2686 /* newi2pat is usually a SET here; however, recog_for_combine might
2687 have added some clobbers. */
2688 if (GET_CODE (newi2pat
) == PARALLEL
)
2689 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
2691 ni2dest
= SET_DEST (newi2pat
);
2693 for (insn
= NEXT_INSN (i3
);
2694 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2695 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
2696 insn
= NEXT_INSN (insn
))
2698 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2700 for (link
= LOG_LINKS (insn
); link
;
2701 link
= XEXP (link
, 1))
2702 if (XEXP (link
, 0) == i3
)
2703 XEXP (link
, 0) = i1
;
2711 rtx i3notes
, i2notes
, i1notes
= 0;
2712 rtx i3links
, i2links
, i1links
= 0;
2716 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2718 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2719 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2721 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2723 /* Ensure that we do not have something that should not be shared but
2724 occurs multiple times in the new insns. Check this by first
2725 resetting all the `used' flags and then copying anything is shared. */
2727 reset_used_flags (i3notes
);
2728 reset_used_flags (i2notes
);
2729 reset_used_flags (i1notes
);
2730 reset_used_flags (newpat
);
2731 reset_used_flags (newi2pat
);
2732 if (undobuf
.other_insn
)
2733 reset_used_flags (PATTERN (undobuf
.other_insn
));
2735 i3notes
= copy_rtx_if_shared (i3notes
);
2736 i2notes
= copy_rtx_if_shared (i2notes
);
2737 i1notes
= copy_rtx_if_shared (i1notes
);
2738 newpat
= copy_rtx_if_shared (newpat
);
2739 newi2pat
= copy_rtx_if_shared (newi2pat
);
2740 if (undobuf
.other_insn
)
2741 reset_used_flags (PATTERN (undobuf
.other_insn
));
2743 INSN_CODE (i3
) = insn_code_number
;
2744 PATTERN (i3
) = newpat
;
2746 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
2748 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2750 reset_used_flags (call_usage
);
2751 call_usage
= copy_rtx (call_usage
);
2754 replace_rtx (call_usage
, i2dest
, i2src
);
2757 replace_rtx (call_usage
, i1dest
, i1src
);
2759 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2762 if (undobuf
.other_insn
)
2763 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2765 /* We had one special case above where I2 had more than one set and
2766 we replaced a destination of one of those sets with the destination
2767 of I3. In that case, we have to update LOG_LINKS of insns later
2768 in this basic block. Note that this (expensive) case is rare.
2770 Also, in this case, we must pretend that all REG_NOTEs for I2
2771 actually came from I3, so that REG_UNUSED notes from I2 will be
2772 properly handled. */
2774 if (i3_subst_into_i2
)
2776 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2777 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2778 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
2779 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2780 && ! find_reg_note (i2
, REG_UNUSED
,
2781 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2782 for (temp
= NEXT_INSN (i2
);
2783 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2784 || BB_HEAD (this_basic_block
) != temp
);
2785 temp
= NEXT_INSN (temp
))
2786 if (temp
!= i3
&& INSN_P (temp
))
2787 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2788 if (XEXP (link
, 0) == i2
)
2789 XEXP (link
, 0) = i3
;
2794 while (XEXP (link
, 1))
2795 link
= XEXP (link
, 1);
2796 XEXP (link
, 1) = i2notes
;
2810 INSN_CODE (i2
) = i2_code_number
;
2811 PATTERN (i2
) = newi2pat
;
2814 SET_INSN_DELETED (i2
);
2820 SET_INSN_DELETED (i1
);
2823 /* Get death notes for everything that is now used in either I3 or
2824 I2 and used to die in a previous insn. If we built two new
2825 patterns, move from I1 to I2 then I2 to I3 so that we get the
2826 proper movement on registers that I2 modifies. */
2830 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2831 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2834 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2837 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2839 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
);
2841 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
);
2843 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
);
2845 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2847 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2848 know these are REG_UNUSED and want them to go to the desired insn,
2849 so we always pass it as i3. We have not counted the notes in
2850 reg_n_deaths yet, so we need to do so now. */
2852 if (newi2pat
&& new_i2_notes
)
2854 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2855 if (REG_P (XEXP (temp
, 0)))
2856 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2858 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
);
2863 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2864 if (REG_P (XEXP (temp
, 0)))
2865 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2867 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
);
2870 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2871 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2872 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2873 in that case, it might delete I2. Similarly for I2 and I1.
2874 Show an additional death due to the REG_DEAD note we make here. If
2875 we discard it in distribute_notes, we will decrement it again. */
2879 if (REG_P (i3dest_killed
))
2880 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2882 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2883 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2885 NULL_RTX
, i2
, NULL_RTX
);
2887 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2889 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2892 if (i2dest_in_i2src
)
2895 REG_N_DEATHS (REGNO (i2dest
))++;
2897 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2898 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2899 NULL_RTX
, i2
, NULL_RTX
);
2901 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2902 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2905 if (i1dest_in_i1src
)
2908 REG_N_DEATHS (REGNO (i1dest
))++;
2910 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2911 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2912 NULL_RTX
, i2
, NULL_RTX
);
2914 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2915 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2918 distribute_links (i3links
);
2919 distribute_links (i2links
);
2920 distribute_links (i1links
);
2925 rtx i2_insn
= 0, i2_val
= 0, set
;
2927 /* The insn that used to set this register doesn't exist, and
2928 this life of the register may not exist either. See if one of
2929 I3's links points to an insn that sets I2DEST. If it does,
2930 that is now the last known value for I2DEST. If we don't update
2931 this and I2 set the register to a value that depended on its old
2932 contents, we will get confused. If this insn is used, thing
2933 will be set correctly in combine_instructions. */
2935 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2936 if ((set
= single_set (XEXP (link
, 0))) != 0
2937 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2938 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2940 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2942 /* If the reg formerly set in I2 died only once and that was in I3,
2943 zero its use count so it won't make `reload' do any work. */
2945 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2946 && ! i2dest_in_i2src
)
2948 regno
= REGNO (i2dest
);
2949 REG_N_SETS (regno
)--;
2953 if (i1
&& REG_P (i1dest
))
2956 rtx i1_insn
= 0, i1_val
= 0, set
;
2958 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2959 if ((set
= single_set (XEXP (link
, 0))) != 0
2960 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2961 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2963 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2965 regno
= REGNO (i1dest
);
2966 if (! added_sets_1
&& ! i1dest_in_i1src
)
2967 REG_N_SETS (regno
)--;
2970 /* Update reg_stat[].nonzero_bits et al for any changes that may have
2971 been made to this insn. The order of
2972 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
2973 can affect nonzero_bits of newpat */
2975 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2976 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2978 /* Set new_direct_jump_p if a new return or simple jump instruction
2981 If I3 is now an unconditional jump, ensure that it has a
2982 BARRIER following it since it may have initially been a
2983 conditional jump. It may also be the last nonnote insn. */
2985 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2987 *new_direct_jump_p
= 1;
2988 mark_jump_label (PATTERN (i3
), i3
, 0);
2990 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2991 || !BARRIER_P (temp
))
2992 emit_barrier_after (i3
);
2995 if (undobuf
.other_insn
!= NULL_RTX
2996 && (returnjump_p (undobuf
.other_insn
)
2997 || any_uncondjump_p (undobuf
.other_insn
)))
2999 *new_direct_jump_p
= 1;
3001 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
3002 || !BARRIER_P (temp
))
3003 emit_barrier_after (undobuf
.other_insn
);
3006 /* An NOOP jump does not need barrier, but it does need cleaning up
3008 if (GET_CODE (newpat
) == SET
3009 && SET_SRC (newpat
) == pc_rtx
3010 && SET_DEST (newpat
) == pc_rtx
)
3011 *new_direct_jump_p
= 1;
3014 combine_successes
++;
3017 if (added_links_insn
3018 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
3019 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
3020 return added_links_insn
;
3022 return newi2pat
? i2
: i3
;
3025 /* Undo all the modifications recorded in undobuf. */
3030 struct undo
*undo
, *next
;
3032 for (undo
= undobuf
.undos
; undo
; undo
= next
)
3036 *undo
->where
.i
= undo
->old_contents
.i
;
3038 *undo
->where
.r
= undo
->old_contents
.r
;
3040 undo
->next
= undobuf
.frees
;
3041 undobuf
.frees
= undo
;
3047 /* We've committed to accepting the changes we made. Move all
3048 of the undos to the free list. */
3053 struct undo
*undo
, *next
;
3055 for (undo
= undobuf
.undos
; undo
; undo
= next
)
3058 undo
->next
= undobuf
.frees
;
3059 undobuf
.frees
= undo
;
3065 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3066 where we have an arithmetic expression and return that point. LOC will
3069 try_combine will call this function to see if an insn can be split into
3073 find_split_point (rtx
*loc
, rtx insn
)
3076 enum rtx_code code
= GET_CODE (x
);
3078 unsigned HOST_WIDE_INT len
= 0;
3079 HOST_WIDE_INT pos
= 0;
3081 rtx inner
= NULL_RTX
;
3083 /* First special-case some codes. */
3087 #ifdef INSN_SCHEDULING
3088 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3090 if (MEM_P (SUBREG_REG (x
)))
3093 return find_split_point (&SUBREG_REG (x
), insn
);
3097 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3098 using LO_SUM and HIGH. */
3099 if (GET_CODE (XEXP (x
, 0)) == CONST
3100 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
3103 gen_rtx_LO_SUM (Pmode
,
3104 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
3106 return &XEXP (XEXP (x
, 0), 0);
3110 /* If we have a PLUS whose second operand is a constant and the
3111 address is not valid, perhaps will can split it up using
3112 the machine-specific way to split large constants. We use
3113 the first pseudo-reg (one of the virtual regs) as a placeholder;
3114 it will not remain in the result. */
3115 if (GET_CODE (XEXP (x
, 0)) == PLUS
3116 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3117 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
3119 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
3120 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
3123 /* This should have produced two insns, each of which sets our
3124 placeholder. If the source of the second is a valid address,
3125 we can make put both sources together and make a split point
3129 && NEXT_INSN (seq
) != NULL_RTX
3130 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
3131 && NONJUMP_INSN_P (seq
)
3132 && GET_CODE (PATTERN (seq
)) == SET
3133 && SET_DEST (PATTERN (seq
)) == reg
3134 && ! reg_mentioned_p (reg
,
3135 SET_SRC (PATTERN (seq
)))
3136 && NONJUMP_INSN_P (NEXT_INSN (seq
))
3137 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
3138 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
3139 && memory_address_p (GET_MODE (x
),
3140 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
3142 rtx src1
= SET_SRC (PATTERN (seq
));
3143 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
3145 /* Replace the placeholder in SRC2 with SRC1. If we can
3146 find where in SRC2 it was placed, that can become our
3147 split point and we can replace this address with SRC2.
3148 Just try two obvious places. */
3150 src2
= replace_rtx (src2
, reg
, src1
);
3152 if (XEXP (src2
, 0) == src1
)
3153 split
= &XEXP (src2
, 0);
3154 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
3155 && XEXP (XEXP (src2
, 0), 0) == src1
)
3156 split
= &XEXP (XEXP (src2
, 0), 0);
3160 SUBST (XEXP (x
, 0), src2
);
3165 /* If that didn't work, perhaps the first operand is complex and
3166 needs to be computed separately, so make a split point there.
3167 This will occur on machines that just support REG + CONST
3168 and have a constant moved through some previous computation. */
3170 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
3171 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
3172 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
3173 return &XEXP (XEXP (x
, 0), 0);
3179 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3180 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3181 we need to put the operand into a register. So split at that
3184 if (SET_DEST (x
) == cc0_rtx
3185 && GET_CODE (SET_SRC (x
)) != COMPARE
3186 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
3187 && !OBJECT_P (SET_SRC (x
))
3188 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
3189 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
3190 return &SET_SRC (x
);
3193 /* See if we can split SET_SRC as it stands. */
3194 split
= find_split_point (&SET_SRC (x
), insn
);
3195 if (split
&& split
!= &SET_SRC (x
))
3198 /* See if we can split SET_DEST as it stands. */
3199 split
= find_split_point (&SET_DEST (x
), insn
);
3200 if (split
&& split
!= &SET_DEST (x
))
3203 /* See if this is a bitfield assignment with everything constant. If
3204 so, this is an IOR of an AND, so split it into that. */
3205 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
3206 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
3207 <= HOST_BITS_PER_WIDE_INT
)
3208 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
3209 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
3210 && GET_CODE (SET_SRC (x
)) == CONST_INT
3211 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3212 + INTVAL (XEXP (SET_DEST (x
), 2)))
3213 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3214 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3216 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3217 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3218 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3219 rtx dest
= XEXP (SET_DEST (x
), 0);
3220 enum machine_mode mode
= GET_MODE (dest
);
3221 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3223 if (BITS_BIG_ENDIAN
)
3224 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3228 simplify_gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3231 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
3233 simplify_gen_binary (IOR
, mode
,
3234 simplify_gen_binary (AND
, mode
,
3236 GEN_INT (src
<< pos
)));
3239 SUBST (SET_DEST (x
), dest
);
3241 split
= find_split_point (&SET_SRC (x
), insn
);
3242 if (split
&& split
!= &SET_SRC (x
))
3246 /* Otherwise, see if this is an operation that we can split into two.
3247 If so, try to split that. */
3248 code
= GET_CODE (SET_SRC (x
));
3253 /* If we are AND'ing with a large constant that is only a single
3254 bit and the result is only being used in a context where we
3255 need to know if it is zero or nonzero, replace it with a bit
3256 extraction. This will avoid the large constant, which might
3257 have taken more than one insn to make. If the constant were
3258 not a valid argument to the AND but took only one insn to make,
3259 this is no worse, but if it took more than one insn, it will
3262 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3263 && REG_P (XEXP (SET_SRC (x
), 0))
3264 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3265 && REG_P (SET_DEST (x
))
3266 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3267 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3268 && XEXP (*split
, 0) == SET_DEST (x
)
3269 && XEXP (*split
, 1) == const0_rtx
)
3271 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3272 XEXP (SET_SRC (x
), 0),
3273 pos
, NULL_RTX
, 1, 1, 0, 0);
3274 if (extraction
!= 0)
3276 SUBST (SET_SRC (x
), extraction
);
3277 return find_split_point (loc
, insn
);
3283 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3284 is known to be on, this can be converted into a NEG of a shift. */
3285 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3286 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3287 && 1 <= (pos
= exact_log2
3288 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3289 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3291 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3295 gen_rtx_LSHIFTRT (mode
,
3296 XEXP (SET_SRC (x
), 0),
3299 split
= find_split_point (&SET_SRC (x
), insn
);
3300 if (split
&& split
!= &SET_SRC (x
))
3306 inner
= XEXP (SET_SRC (x
), 0);
3308 /* We can't optimize if either mode is a partial integer
3309 mode as we don't know how many bits are significant
3311 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3312 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3316 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3322 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3323 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3325 inner
= XEXP (SET_SRC (x
), 0);
3326 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3327 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3329 if (BITS_BIG_ENDIAN
)
3330 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3331 unsignedp
= (code
== ZERO_EXTRACT
);
3339 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3341 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3343 /* For unsigned, we have a choice of a shift followed by an
3344 AND or two shifts. Use two shifts for field sizes where the
3345 constant might be too large. We assume here that we can
3346 always at least get 8-bit constants in an AND insn, which is
3347 true for every current RISC. */
3349 if (unsignedp
&& len
<= 8)
3354 (mode
, gen_lowpart (mode
, inner
),
3356 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3358 split
= find_split_point (&SET_SRC (x
), insn
);
3359 if (split
&& split
!= &SET_SRC (x
))
3366 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3367 gen_rtx_ASHIFT (mode
,
3368 gen_lowpart (mode
, inner
),
3369 GEN_INT (GET_MODE_BITSIZE (mode
)
3371 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3373 split
= find_split_point (&SET_SRC (x
), insn
);
3374 if (split
&& split
!= &SET_SRC (x
))
3379 /* See if this is a simple operation with a constant as the second
3380 operand. It might be that this constant is out of range and hence
3381 could be used as a split point. */
3382 if (BINARY_P (SET_SRC (x
))
3383 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3384 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
3385 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3386 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
3387 return &XEXP (SET_SRC (x
), 1);
3389 /* Finally, see if this is a simple operation with its first operand
3390 not in a register. The operation might require this operand in a
3391 register, so return it as a split point. We can always do this
3392 because if the first operand were another operation, we would have
3393 already found it as a split point. */
3394 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
3395 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3396 return &XEXP (SET_SRC (x
), 0);
3402 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3403 it is better to write this as (not (ior A B)) so we can split it.
3404 Similarly for IOR. */
3405 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3408 gen_rtx_NOT (GET_MODE (x
),
3409 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3411 XEXP (XEXP (x
, 0), 0),
3412 XEXP (XEXP (x
, 1), 0))));
3413 return find_split_point (loc
, insn
);
3416 /* Many RISC machines have a large set of logical insns. If the
3417 second operand is a NOT, put it first so we will try to split the
3418 other operand first. */
3419 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3421 rtx tem
= XEXP (x
, 0);
3422 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3423 SUBST (XEXP (x
, 1), tem
);
3431 /* Otherwise, select our actions depending on our rtx class. */
3432 switch (GET_RTX_CLASS (code
))
3434 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3436 split
= find_split_point (&XEXP (x
, 2), insn
);
3439 /* ... fall through ... */
3441 case RTX_COMM_ARITH
:
3443 case RTX_COMM_COMPARE
:
3444 split
= find_split_point (&XEXP (x
, 1), insn
);
3447 /* ... fall through ... */
3449 /* Some machines have (and (shift ...) ...) insns. If X is not
3450 an AND, but XEXP (X, 0) is, use it as our split point. */
3451 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3452 return &XEXP (x
, 0);
3454 split
= find_split_point (&XEXP (x
, 0), insn
);
3460 /* Otherwise, we don't have a split point. */
3465 /* Throughout X, replace FROM with TO, and return the result.
3466 The result is TO if X is FROM;
3467 otherwise the result is X, but its contents may have been modified.
3468 If they were modified, a record was made in undobuf so that
3469 undo_all will (among other things) return X to its original state.
3471 If the number of changes necessary is too much to record to undo,
3472 the excess changes are not made, so the result is invalid.
3473 The changes already made can still be undone.
3474 undobuf.num_undo is incremented for such changes, so by testing that
3475 the caller can tell whether the result is valid.
3477 `n_occurrences' is incremented each time FROM is replaced.
3479 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3481 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3482 by copying if `n_occurrences' is nonzero. */
3485 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3487 enum rtx_code code
= GET_CODE (x
);
3488 enum machine_mode op0_mode
= VOIDmode
;
3493 /* Two expressions are equal if they are identical copies of a shared
3494 RTX or if they are both registers with the same register number
3497 #define COMBINE_RTX_EQUAL_P(X,Y) \
3499 || (REG_P (X) && REG_P (Y) \
3500 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3502 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3505 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3508 /* If X and FROM are the same register but different modes, they will
3509 not have been seen as equal above. However, flow.c will make a
3510 LOG_LINKS entry for that case. If we do nothing, we will try to
3511 rerecognize our original insn and, when it succeeds, we will
3512 delete the feeding insn, which is incorrect.
3514 So force this insn not to match in this (rare) case. */
3515 if (! in_dest
&& code
== REG
&& REG_P (from
)
3516 && REGNO (x
) == REGNO (from
))
3517 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3519 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3520 of which may contain things that can be combined. */
3521 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
3524 /* It is possible to have a subexpression appear twice in the insn.
3525 Suppose that FROM is a register that appears within TO.
3526 Then, after that subexpression has been scanned once by `subst',
3527 the second time it is scanned, TO may be found. If we were
3528 to scan TO here, we would find FROM within it and create a
3529 self-referent rtl structure which is completely wrong. */
3530 if (COMBINE_RTX_EQUAL_P (x
, to
))
3533 /* Parallel asm_operands need special attention because all of the
3534 inputs are shared across the arms. Furthermore, unsharing the
3535 rtl results in recognition failures. Failure to handle this case
3536 specially can result in circular rtl.
3538 Solve this by doing a normal pass across the first entry of the
3539 parallel, and only processing the SET_DESTs of the subsequent
3542 if (code
== PARALLEL
3543 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3544 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3546 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3548 /* If this substitution failed, this whole thing fails. */
3549 if (GET_CODE (new) == CLOBBER
3550 && XEXP (new, 0) == const0_rtx
)
3553 SUBST (XVECEXP (x
, 0, 0), new);
3555 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3557 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3560 && GET_CODE (dest
) != CC0
3561 && GET_CODE (dest
) != PC
)
3563 new = subst (dest
, from
, to
, 0, unique_copy
);
3565 /* If this substitution failed, this whole thing fails. */
3566 if (GET_CODE (new) == CLOBBER
3567 && XEXP (new, 0) == const0_rtx
)
3570 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3576 len
= GET_RTX_LENGTH (code
);
3577 fmt
= GET_RTX_FORMAT (code
);
3579 /* We don't need to process a SET_DEST that is a register, CC0,
3580 or PC, so set up to skip this common case. All other cases
3581 where we want to suppress replacing something inside a
3582 SET_SRC are handled via the IN_DEST operand. */
3584 && (REG_P (SET_DEST (x
))
3585 || GET_CODE (SET_DEST (x
)) == CC0
3586 || GET_CODE (SET_DEST (x
)) == PC
))
3589 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3592 op0_mode
= GET_MODE (XEXP (x
, 0));
3594 for (i
= 0; i
< len
; i
++)
3599 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3601 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3603 new = (unique_copy
&& n_occurrences
3604 ? copy_rtx (to
) : to
);
3609 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3612 /* If this substitution failed, this whole thing
3614 if (GET_CODE (new) == CLOBBER
3615 && XEXP (new, 0) == const0_rtx
)
3619 SUBST (XVECEXP (x
, i
, j
), new);
3622 else if (fmt
[i
] == 'e')
3624 /* If this is a register being set, ignore it. */
3628 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
3630 || code
== STRICT_LOW_PART
))
3633 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3635 /* In general, don't install a subreg involving two
3636 modes not tieable. It can worsen register
3637 allocation, and can even make invalid reload
3638 insns, since the reg inside may need to be copied
3639 from in the outside mode, and that may be invalid
3640 if it is an fp reg copied in integer mode.
3642 We allow two exceptions to this: It is valid if
3643 it is inside another SUBREG and the mode of that
3644 SUBREG and the mode of the inside of TO is
3645 tieable and it is valid if X is a SET that copies
3648 if (GET_CODE (to
) == SUBREG
3649 && ! MODES_TIEABLE_P (GET_MODE (to
),
3650 GET_MODE (SUBREG_REG (to
)))
3651 && ! (code
== SUBREG
3652 && MODES_TIEABLE_P (GET_MODE (x
),
3653 GET_MODE (SUBREG_REG (to
))))
3655 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3658 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3660 #ifdef CANNOT_CHANGE_MODE_CLASS
3663 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3664 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3667 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3670 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3674 /* If we are in a SET_DEST, suppress most cases unless we
3675 have gone inside a MEM, in which case we want to
3676 simplify the address. We assume here that things that
3677 are actually part of the destination have their inner
3678 parts in the first expression. This is true for SUBREG,
3679 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3680 things aside from REG and MEM that should appear in a
3682 new = subst (XEXP (x
, i
), from
, to
,
3684 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3685 || code
== ZERO_EXTRACT
))
3687 && i
== 0), unique_copy
);
3689 /* If we found that we will have to reject this combination,
3690 indicate that by returning the CLOBBER ourselves, rather than
3691 an expression containing it. This will speed things up as
3692 well as prevent accidents where two CLOBBERs are considered
3693 to be equal, thus producing an incorrect simplification. */
3695 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3698 if (GET_CODE (x
) == SUBREG
3699 && (GET_CODE (new) == CONST_INT
3700 || GET_CODE (new) == CONST_DOUBLE
))
3702 enum machine_mode mode
= GET_MODE (x
);
3704 x
= simplify_subreg (GET_MODE (x
), new,
3705 GET_MODE (SUBREG_REG (x
)),
3708 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3710 else if (GET_CODE (new) == CONST_INT
3711 && GET_CODE (x
) == ZERO_EXTEND
)
3713 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3714 new, GET_MODE (XEXP (x
, 0)));
3718 SUBST (XEXP (x
, i
), new);
3723 /* Try to simplify X. If the simplification changed the code, it is likely
3724 that further simplification will help, so loop, but limit the number
3725 of repetitions that will be performed. */
3727 for (i
= 0; i
< 4; i
++)
3729 /* If X is sufficiently simple, don't bother trying to do anything
3731 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3732 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
);
3734 if (GET_CODE (x
) == code
)
3737 code
= GET_CODE (x
);
3739 /* We no longer know the original mode of operand 0 since we
3740 have changed the form of X) */
3741 op0_mode
= VOIDmode
;
3747 /* Simplify X, a piece of RTL. We just operate on the expression at the
3748 outer level; call `subst' to simplify recursively. Return the new
3751 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3752 if we are inside a SET_DEST. */
3755 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
)
3757 enum rtx_code code
= GET_CODE (x
);
3758 enum machine_mode mode
= GET_MODE (x
);
3763 /* If this is a commutative operation, put a constant last and a complex
3764 expression first. We don't need to do this for comparisons here. */
3765 if (COMMUTATIVE_ARITH_P (x
)
3766 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3769 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3770 SUBST (XEXP (x
, 1), temp
);
3773 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3774 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3775 things. Check for cases where both arms are testing the same
3778 Don't do anything if all operands are very simple. */
3781 && ((!OBJECT_P (XEXP (x
, 0))
3782 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3783 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
3784 || (!OBJECT_P (XEXP (x
, 1))
3785 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3786 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
3788 && (!OBJECT_P (XEXP (x
, 0))
3789 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3790 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
3792 rtx cond
, true_rtx
, false_rtx
;
3794 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3796 /* If everything is a comparison, what we have is highly unlikely
3797 to be simpler, so don't use it. */
3798 && ! (COMPARISON_P (x
)
3799 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
3801 rtx cop1
= const0_rtx
;
3802 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3804 if (cond_code
== NE
&& COMPARISON_P (cond
))
3807 /* Simplify the alternative arms; this may collapse the true and
3808 false arms to store-flag values. Be careful to use copy_rtx
3809 here since true_rtx or false_rtx might share RTL with x as a
3810 result of the if_then_else_cond call above. */
3811 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3812 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3814 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3815 is unlikely to be simpler. */
3816 if (general_operand (true_rtx
, VOIDmode
)
3817 && general_operand (false_rtx
, VOIDmode
))
3819 enum rtx_code reversed
;
3821 /* Restarting if we generate a store-flag expression will cause
3822 us to loop. Just drop through in this case. */
3824 /* If the result values are STORE_FLAG_VALUE and zero, we can
3825 just make the comparison operation. */
3826 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3827 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
3829 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3830 && ((reversed
= reversed_comparison_code_parts
3831 (cond_code
, cond
, cop1
, NULL
))
3833 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
3836 /* Likewise, we can make the negate of a comparison operation
3837 if the result values are - STORE_FLAG_VALUE and zero. */
3838 else if (GET_CODE (true_rtx
) == CONST_INT
3839 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3840 && false_rtx
== const0_rtx
)
3841 x
= simplify_gen_unary (NEG
, mode
,
3842 simplify_gen_relational (cond_code
,
3846 else if (GET_CODE (false_rtx
) == CONST_INT
3847 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3848 && true_rtx
== const0_rtx
3849 && ((reversed
= reversed_comparison_code_parts
3850 (cond_code
, cond
, cop1
, NULL
))
3852 x
= simplify_gen_unary (NEG
, mode
,
3853 simplify_gen_relational (reversed
,
3858 return gen_rtx_IF_THEN_ELSE (mode
,
3859 simplify_gen_relational (cond_code
,
3864 true_rtx
, false_rtx
);
3866 code
= GET_CODE (x
);
3867 op0_mode
= VOIDmode
;
3872 /* Try to fold this expression in case we have constants that weren't
3875 switch (GET_RTX_CLASS (code
))
3878 if (op0_mode
== VOIDmode
)
3879 op0_mode
= GET_MODE (XEXP (x
, 0));
3880 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3883 case RTX_COMM_COMPARE
:
3885 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3886 if (cmp_mode
== VOIDmode
)
3888 cmp_mode
= GET_MODE (XEXP (x
, 1));
3889 if (cmp_mode
== VOIDmode
)
3890 cmp_mode
= op0_mode
;
3892 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
3893 XEXP (x
, 0), XEXP (x
, 1));
3896 case RTX_COMM_ARITH
:
3898 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3900 case RTX_BITFIELD_OPS
:
3902 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3903 XEXP (x
, 1), XEXP (x
, 2));
3912 code
= GET_CODE (temp
);
3913 op0_mode
= VOIDmode
;
3914 mode
= GET_MODE (temp
);
3917 /* First see if we can apply the inverse distributive law. */
3918 if (code
== PLUS
|| code
== MINUS
3919 || code
== AND
|| code
== IOR
|| code
== XOR
)
3921 x
= apply_distributive_law (x
);
3922 code
= GET_CODE (x
);
3923 op0_mode
= VOIDmode
;
3926 /* If CODE is an associative operation not otherwise handled, see if we
3927 can associate some operands. This can win if they are constants or
3928 if they are logically related (i.e. (a & b) & a). */
3929 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3930 || code
== AND
|| code
== IOR
|| code
== XOR
3931 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3932 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3933 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3935 if (GET_CODE (XEXP (x
, 0)) == code
)
3937 rtx other
= XEXP (XEXP (x
, 0), 0);
3938 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3939 rtx inner_op1
= XEXP (x
, 1);
3942 /* Make sure we pass the constant operand if any as the second
3943 one if this is a commutative operation. */
3944 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
3946 rtx tem
= inner_op0
;
3947 inner_op0
= inner_op1
;
3950 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3951 : code
== DIV
? MULT
3953 mode
, inner_op0
, inner_op1
);
3955 /* For commutative operations, try the other pair if that one
3957 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
3959 other
= XEXP (XEXP (x
, 0), 1);
3960 inner
= simplify_binary_operation (code
, mode
,
3961 XEXP (XEXP (x
, 0), 0),
3966 return simplify_gen_binary (code
, mode
, other
, inner
);
3970 /* A little bit of algebraic simplification here. */
3974 /* Ensure that our address has any ASHIFTs converted to MULT in case
3975 address-recognizing predicates are called later. */
3976 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3977 SUBST (XEXP (x
, 0), temp
);
3981 if (op0_mode
== VOIDmode
)
3982 op0_mode
= GET_MODE (SUBREG_REG (x
));
3984 /* See if this can be moved to simplify_subreg. */
3985 if (CONSTANT_P (SUBREG_REG (x
))
3986 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3987 /* Don't call gen_lowpart if the inner mode
3988 is VOIDmode and we cannot simplify it, as SUBREG without
3989 inner mode is invalid. */
3990 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3991 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3992 return gen_lowpart (mode
, SUBREG_REG (x
));
3994 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3998 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
4004 /* Don't change the mode of the MEM if that would change the meaning
4006 if (MEM_P (SUBREG_REG (x
))
4007 && (MEM_VOLATILE_P (SUBREG_REG (x
))
4008 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
4009 return gen_rtx_CLOBBER (mode
, const0_rtx
);
4011 /* Note that we cannot do any narrowing for non-constants since
4012 we might have been counting on using the fact that some bits were
4013 zero. We now do this in the SET. */
4018 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4019 && subreg_lowpart_p (XEXP (x
, 0))
4020 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
4021 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
4022 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
4023 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
4025 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
4027 x
= gen_rtx_ROTATE (inner_mode
,
4028 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
4030 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
4031 return gen_lowpart (mode
, x
);
4034 /* Apply De Morgan's laws to reduce number of patterns for machines
4035 with negating logical insns (and-not, nand, etc.). If result has
4036 only one NOT, put it first, since that is how the patterns are
4039 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
4041 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
4042 enum machine_mode op_mode
;
4044 op_mode
= GET_MODE (in1
);
4045 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
4047 op_mode
= GET_MODE (in2
);
4048 if (op_mode
== VOIDmode
)
4050 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
4052 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
4055 in2
= in1
; in1
= tem
;
4058 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
4064 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4065 if (GET_CODE (XEXP (x
, 0)) == XOR
4066 && XEXP (XEXP (x
, 0), 1) == const1_rtx
4067 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
4068 return simplify_gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4071 temp
= expand_compound_operation (XEXP (x
, 0));
4073 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4074 replaced by (lshiftrt X C). This will convert
4075 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4077 if (GET_CODE (temp
) == ASHIFTRT
4078 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
4079 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4080 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4081 INTVAL (XEXP (temp
, 1)));
4083 /* If X has only a single bit that might be nonzero, say, bit I, convert
4084 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4085 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4086 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4087 or a SUBREG of one since we'd be making the expression more
4088 complex if it was just a register. */
4091 && ! (GET_CODE (temp
) == SUBREG
4092 && REG_P (SUBREG_REG (temp
)))
4093 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4095 rtx temp1
= simplify_shift_const
4096 (NULL_RTX
, ASHIFTRT
, mode
,
4097 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4098 GET_MODE_BITSIZE (mode
) - 1 - i
),
4099 GET_MODE_BITSIZE (mode
) - 1 - i
);
4101 /* If all we did was surround TEMP with the two shifts, we
4102 haven't improved anything, so don't use it. Otherwise,
4103 we are better off with TEMP1. */
4104 if (GET_CODE (temp1
) != ASHIFTRT
4105 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4106 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4112 /* We can't handle truncation to a partial integer mode here
4113 because we don't know the real bitsize of the partial
4115 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4118 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4119 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4120 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4122 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4123 GET_MODE_MASK (mode
), NULL_RTX
, 0));
4125 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4126 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4127 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4128 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4129 return XEXP (XEXP (x
, 0), 0);
4131 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4132 (OP:SI foo:SI) if OP is NEG or ABS. */
4133 if ((GET_CODE (XEXP (x
, 0)) == ABS
4134 || GET_CODE (XEXP (x
, 0)) == NEG
)
4135 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4136 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4137 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4138 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4139 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4141 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4143 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4144 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4145 && subreg_lowpart_p (XEXP (x
, 0)))
4146 return SUBREG_REG (XEXP (x
, 0));
4148 /* If we know that the value is already truncated, we can
4149 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4150 is nonzero for the corresponding modes. But don't do this
4151 for an (LSHIFTRT (MULT ...)) since this will cause problems
4152 with the umulXi3_highpart patterns. */
4153 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4154 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4155 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4156 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
4157 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4158 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4159 return gen_lowpart (mode
, XEXP (x
, 0));
4161 /* A truncate of a comparison can be replaced with a subreg if
4162 STORE_FLAG_VALUE permits. This is like the previous test,
4163 but it works even if the comparison is done in a mode larger
4164 than HOST_BITS_PER_WIDE_INT. */
4165 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4166 && COMPARISON_P (XEXP (x
, 0))
4167 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4168 return gen_lowpart (mode
, XEXP (x
, 0));
4170 /* Similarly, a truncate of a register whose value is a
4171 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4173 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4174 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4175 && (temp
= get_last_value (XEXP (x
, 0)))
4176 && COMPARISON_P (temp
))
4177 return gen_lowpart (mode
, XEXP (x
, 0));
4181 case FLOAT_TRUNCATE
:
4182 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4183 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4184 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4185 return XEXP (XEXP (x
, 0), 0);
4187 /* (float_truncate:SF (float_truncate:DF foo:XF))
4188 = (float_truncate:SF foo:XF).
4189 This may eliminate double rounding, so it is unsafe.
4191 (float_truncate:SF (float_extend:XF foo:DF))
4192 = (float_truncate:SF foo:DF).
4194 (float_truncate:DF (float_extend:XF foo:SF))
4195 = (float_extend:SF foo:DF). */
4196 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4197 && flag_unsafe_math_optimizations
)
4198 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4199 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4201 > GET_MODE_SIZE (mode
)
4202 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4204 XEXP (XEXP (x
, 0), 0), mode
);
4206 /* (float_truncate (float x)) is (float x) */
4207 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4208 && (flag_unsafe_math_optimizations
4209 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4210 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4211 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4212 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4213 return simplify_gen_unary (FLOAT
, mode
,
4214 XEXP (XEXP (x
, 0), 0),
4215 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4217 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4218 (OP:SF foo:SF) if OP is NEG or ABS. */
4219 if ((GET_CODE (XEXP (x
, 0)) == ABS
4220 || GET_CODE (XEXP (x
, 0)) == NEG
)
4221 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4222 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4223 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4224 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4226 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4227 is (float_truncate:SF x). */
4228 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4229 && subreg_lowpart_p (XEXP (x
, 0))
4230 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4231 return SUBREG_REG (XEXP (x
, 0));
4234 /* (float_extend (float_extend x)) is (float_extend x)
4236 (float_extend (float x)) is (float x) assuming that double
4237 rounding can't happen.
4239 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4240 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4241 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4242 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4243 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4244 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4245 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4246 XEXP (XEXP (x
, 0), 0),
4247 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4252 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4253 using cc0, in which case we want to leave it as a COMPARE
4254 so we can distinguish it from a register-register-copy. */
4255 if (XEXP (x
, 1) == const0_rtx
)
4258 /* x - 0 is the same as x unless x's mode has signed zeros and
4259 allows rounding towards -infinity. Under those conditions,
4261 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4262 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4263 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4269 /* (const (const X)) can become (const X). Do it this way rather than
4270 returning the inner CONST since CONST can be shared with a
4272 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4273 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4278 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4279 can add in an offset. find_split_point will split this address up
4280 again if it doesn't match. */
4281 if (GET_CODE (XEXP (x
, 0)) == HIGH
4282 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4288 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4290 if (GET_CODE (XEXP (x
, 0)) == MULT
4291 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4295 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4296 in2
= XEXP (XEXP (x
, 0), 1);
4297 return simplify_gen_binary (MINUS
, mode
, XEXP (x
, 1),
4298 simplify_gen_binary (MULT
, mode
,
4302 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4303 outermost. That's because that's the way indexed addresses are
4304 supposed to appear. This code used to check many more cases, but
4305 they are now checked elsewhere. */
4306 if (GET_CODE (XEXP (x
, 0)) == PLUS
4307 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4308 return simplify_gen_binary (PLUS
, mode
,
4309 simplify_gen_binary (PLUS
, mode
,
4310 XEXP (XEXP (x
, 0), 0),
4312 XEXP (XEXP (x
, 0), 1));
4314 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4315 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4316 bit-field and can be replaced by either a sign_extend or a
4317 sign_extract. The `and' may be a zero_extend and the two
4318 <c>, -<c> constants may be reversed. */
4319 if (GET_CODE (XEXP (x
, 0)) == XOR
4320 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4321 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4322 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4323 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4324 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4325 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4326 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4327 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4328 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4329 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4330 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4331 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4332 == (unsigned int) i
+ 1))))
4333 return simplify_shift_const
4334 (NULL_RTX
, ASHIFTRT
, mode
,
4335 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4336 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4337 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4338 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4340 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4341 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4342 is 1. This produces better code than the alternative immediately
4344 if (COMPARISON_P (XEXP (x
, 0))
4345 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4346 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4347 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
)))
4349 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4351 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4352 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4353 the bitsize of the mode - 1. This allows simplification of
4354 "a = (b & 8) == 0;" */
4355 if (XEXP (x
, 1) == constm1_rtx
4356 && !REG_P (XEXP (x
, 0))
4357 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4358 && REG_P (SUBREG_REG (XEXP (x
, 0))))
4359 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4360 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4361 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4362 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4363 GET_MODE_BITSIZE (mode
) - 1),
4364 GET_MODE_BITSIZE (mode
) - 1);
4366 /* If we are adding two things that have no bits in common, convert
4367 the addition into an IOR. This will often be further simplified,
4368 for example in cases like ((a & 1) + (a & 2)), which can
4371 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4372 && (nonzero_bits (XEXP (x
, 0), mode
)
4373 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4375 /* Try to simplify the expression further. */
4376 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4377 temp
= combine_simplify_rtx (tor
, mode
, in_dest
);
4379 /* If we could, great. If not, do not go ahead with the IOR
4380 replacement, since PLUS appears in many special purpose
4381 address arithmetic instructions. */
4382 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4388 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4389 by reversing the comparison code if valid. */
4390 if (STORE_FLAG_VALUE
== 1
4391 && XEXP (x
, 0) == const1_rtx
4392 && COMPARISON_P (XEXP (x
, 1))
4393 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
)))
4396 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4397 (and <foo> (const_int pow2-1)) */
4398 if (GET_CODE (XEXP (x
, 1)) == AND
4399 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4400 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4401 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4402 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4403 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4405 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4407 if (GET_CODE (XEXP (x
, 1)) == MULT
4408 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4412 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4413 in2
= XEXP (XEXP (x
, 1), 1);
4414 return simplify_gen_binary (PLUS
, mode
,
4415 simplify_gen_binary (MULT
, mode
,
4420 /* Canonicalize (minus (neg A) (mult B C)) to
4421 (minus (mult (neg B) C) A). */
4422 if (GET_CODE (XEXP (x
, 1)) == MULT
4423 && GET_CODE (XEXP (x
, 0)) == NEG
)
4427 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4428 in2
= XEXP (XEXP (x
, 1), 1);
4429 return simplify_gen_binary (MINUS
, mode
,
4430 simplify_gen_binary (MULT
, mode
,
4432 XEXP (XEXP (x
, 0), 0));
4435 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4437 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4438 return simplify_gen_binary (MINUS
, mode
,
4439 simplify_gen_binary (MINUS
, mode
,
4441 XEXP (XEXP (x
, 1), 0)),
4442 XEXP (XEXP (x
, 1), 1));
4446 /* If we have (mult (plus A B) C), apply the distributive law and then
4447 the inverse distributive law to see if things simplify. This
4448 occurs mostly in addresses, often when unrolling loops. */
4450 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4452 rtx result
= distribute_and_simplify_rtx (x
, 0);
4457 /* Try simplify a*(b/c) as (a*b)/c. */
4458 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4459 && GET_CODE (XEXP (x
, 0)) == DIV
)
4461 rtx tem
= simplify_binary_operation (MULT
, mode
,
4462 XEXP (XEXP (x
, 0), 0),
4465 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4470 /* If this is a divide by a power of two, treat it as a shift if
4471 its first operand is a shift. */
4472 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4473 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4474 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4475 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4476 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4477 || GET_CODE (XEXP (x
, 0)) == ROTATE
4478 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4479 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4483 case GT
: case GTU
: case GE
: case GEU
:
4484 case LT
: case LTU
: case LE
: case LEU
:
4485 case UNEQ
: case LTGT
:
4486 case UNGT
: case UNGE
:
4487 case UNLT
: case UNLE
:
4488 case UNORDERED
: case ORDERED
:
4489 /* If the first operand is a condition code, we can't do anything
4491 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4492 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4493 && ! CC0_P (XEXP (x
, 0))))
4495 rtx op0
= XEXP (x
, 0);
4496 rtx op1
= XEXP (x
, 1);
4497 enum rtx_code new_code
;
4499 if (GET_CODE (op0
) == COMPARE
)
4500 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4502 /* Simplify our comparison, if possible. */
4503 new_code
= simplify_comparison (code
, &op0
, &op1
);
4505 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4506 if only the low-order bit is possibly nonzero in X (such as when
4507 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4508 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4509 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4512 Remove any ZERO_EXTRACT we made when thinking this was a
4513 comparison. It may now be simpler to use, e.g., an AND. If a
4514 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4515 the call to make_compound_operation in the SET case. */
4517 if (STORE_FLAG_VALUE
== 1
4518 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4519 && op1
== const0_rtx
4520 && mode
== GET_MODE (op0
)
4521 && nonzero_bits (op0
, mode
) == 1)
4522 return gen_lowpart (mode
,
4523 expand_compound_operation (op0
));
4525 else if (STORE_FLAG_VALUE
== 1
4526 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4527 && op1
== const0_rtx
4528 && mode
== GET_MODE (op0
)
4529 && (num_sign_bit_copies (op0
, mode
)
4530 == GET_MODE_BITSIZE (mode
)))
4532 op0
= expand_compound_operation (op0
);
4533 return simplify_gen_unary (NEG
, mode
,
4534 gen_lowpart (mode
, op0
),
4538 else if (STORE_FLAG_VALUE
== 1
4539 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4540 && op1
== const0_rtx
4541 && mode
== GET_MODE (op0
)
4542 && nonzero_bits (op0
, mode
) == 1)
4544 op0
= expand_compound_operation (op0
);
4545 return simplify_gen_binary (XOR
, mode
,
4546 gen_lowpart (mode
, op0
),
4550 else if (STORE_FLAG_VALUE
== 1
4551 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4552 && op1
== const0_rtx
4553 && mode
== GET_MODE (op0
)
4554 && (num_sign_bit_copies (op0
, mode
)
4555 == GET_MODE_BITSIZE (mode
)))
4557 op0
= expand_compound_operation (op0
);
4558 return plus_constant (gen_lowpart (mode
, op0
), 1);
4561 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4563 if (STORE_FLAG_VALUE
== -1
4564 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4565 && op1
== const0_rtx
4566 && (num_sign_bit_copies (op0
, mode
)
4567 == GET_MODE_BITSIZE (mode
)))
4568 return gen_lowpart (mode
,
4569 expand_compound_operation (op0
));
4571 else if (STORE_FLAG_VALUE
== -1
4572 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4573 && op1
== const0_rtx
4574 && mode
== GET_MODE (op0
)
4575 && nonzero_bits (op0
, mode
) == 1)
4577 op0
= expand_compound_operation (op0
);
4578 return simplify_gen_unary (NEG
, mode
,
4579 gen_lowpart (mode
, op0
),
4583 else if (STORE_FLAG_VALUE
== -1
4584 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4585 && op1
== const0_rtx
4586 && mode
== GET_MODE (op0
)
4587 && (num_sign_bit_copies (op0
, mode
)
4588 == GET_MODE_BITSIZE (mode
)))
4590 op0
= expand_compound_operation (op0
);
4591 return simplify_gen_unary (NOT
, mode
,
4592 gen_lowpart (mode
, op0
),
4596 /* If X is 0/1, (eq X 0) is X-1. */
4597 else if (STORE_FLAG_VALUE
== -1
4598 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4599 && op1
== const0_rtx
4600 && mode
== GET_MODE (op0
)
4601 && nonzero_bits (op0
, mode
) == 1)
4603 op0
= expand_compound_operation (op0
);
4604 return plus_constant (gen_lowpart (mode
, op0
), -1);
4607 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4608 one bit that might be nonzero, we can convert (ne x 0) to
4609 (ashift x c) where C puts the bit in the sign bit. Remove any
4610 AND with STORE_FLAG_VALUE when we are done, since we are only
4611 going to test the sign bit. */
4612 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4613 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4614 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4615 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4616 && op1
== const0_rtx
4617 && mode
== GET_MODE (op0
)
4618 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4620 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4621 expand_compound_operation (op0
),
4622 GET_MODE_BITSIZE (mode
) - 1 - i
);
4623 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4629 /* If the code changed, return a whole new comparison. */
4630 if (new_code
!= code
)
4631 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4633 /* Otherwise, keep this operation, but maybe change its operands.
4634 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4635 SUBST (XEXP (x
, 0), op0
);
4636 SUBST (XEXP (x
, 1), op1
);
4641 return simplify_if_then_else (x
);
4647 /* If we are processing SET_DEST, we are done. */
4651 return expand_compound_operation (x
);
4654 return simplify_set (x
);
4659 return simplify_logical (x
);
4662 /* (abs (neg <foo>)) -> (abs <foo>) */
4663 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4664 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4666 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4668 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4671 /* If operand is something known to be positive, ignore the ABS. */
4672 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4673 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4674 <= HOST_BITS_PER_WIDE_INT
)
4675 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4676 & ((HOST_WIDE_INT
) 1
4677 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4681 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4682 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4683 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4688 /* (ffs (*_extend <X>)) = (ffs <X>) */
4689 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4690 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4691 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4696 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4697 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4698 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4702 /* (float (sign_extend <X>)) = (float <X>). */
4703 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4704 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4712 /* If this is a shift by a constant amount, simplify it. */
4713 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4714 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4715 INTVAL (XEXP (x
, 1)));
4717 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
4719 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4721 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4728 rtx op0
= XEXP (x
, 0);
4729 rtx op1
= XEXP (x
, 1);
4732 gcc_assert (GET_CODE (op1
) == PARALLEL
);
4733 len
= XVECLEN (op1
, 0);
4735 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4736 && GET_CODE (op0
) == VEC_CONCAT
)
4738 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4740 /* Try to find the element in the VEC_CONCAT. */
4743 if (GET_MODE (op0
) == GET_MODE (x
))
4745 if (GET_CODE (op0
) == VEC_CONCAT
)
4747 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4748 if (offset
< op0_size
)
4749 op0
= XEXP (op0
, 0);
4753 op0
= XEXP (op0
, 1);
4771 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4774 simplify_if_then_else (rtx x
)
4776 enum machine_mode mode
= GET_MODE (x
);
4777 rtx cond
= XEXP (x
, 0);
4778 rtx true_rtx
= XEXP (x
, 1);
4779 rtx false_rtx
= XEXP (x
, 2);
4780 enum rtx_code true_code
= GET_CODE (cond
);
4781 int comparison_p
= COMPARISON_P (cond
);
4784 enum rtx_code false_code
;
4787 /* Simplify storing of the truth value. */
4788 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4789 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
4790 XEXP (cond
, 0), XEXP (cond
, 1));
4792 /* Also when the truth value has to be reversed. */
4794 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4795 && (reversed
= reversed_comparison (cond
, mode
)))
4798 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4799 in it is being compared against certain values. Get the true and false
4800 comparisons and see if that says anything about the value of each arm. */
4803 && ((false_code
= reversed_comparison_code (cond
, NULL
))
4805 && REG_P (XEXP (cond
, 0)))
4808 rtx from
= XEXP (cond
, 0);
4809 rtx true_val
= XEXP (cond
, 1);
4810 rtx false_val
= true_val
;
4813 /* If FALSE_CODE is EQ, swap the codes and arms. */
4815 if (false_code
== EQ
)
4817 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4818 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4821 /* If we are comparing against zero and the expression being tested has
4822 only a single bit that might be nonzero, that is its value when it is
4823 not equal to zero. Similarly if it is known to be -1 or 0. */
4825 if (true_code
== EQ
&& true_val
== const0_rtx
4826 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4827 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4828 else if (true_code
== EQ
&& true_val
== const0_rtx
4829 && (num_sign_bit_copies (from
, GET_MODE (from
))
4830 == GET_MODE_BITSIZE (GET_MODE (from
))))
4831 false_code
= EQ
, false_val
= constm1_rtx
;
4833 /* Now simplify an arm if we know the value of the register in the
4834 branch and it is used in the arm. Be careful due to the potential
4835 of locally-shared RTL. */
4837 if (reg_mentioned_p (from
, true_rtx
))
4838 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4840 pc_rtx
, pc_rtx
, 0, 0);
4841 if (reg_mentioned_p (from
, false_rtx
))
4842 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4844 pc_rtx
, pc_rtx
, 0, 0);
4846 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4847 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4849 true_rtx
= XEXP (x
, 1);
4850 false_rtx
= XEXP (x
, 2);
4851 true_code
= GET_CODE (cond
);
4854 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4855 reversed, do so to avoid needing two sets of patterns for
4856 subtract-and-branch insns. Similarly if we have a constant in the true
4857 arm, the false arm is the same as the first operand of the comparison, or
4858 the false arm is more complicated than the true arm. */
4861 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
4862 && (true_rtx
== pc_rtx
4863 || (CONSTANT_P (true_rtx
)
4864 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4865 || true_rtx
== const0_rtx
4866 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
4867 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
4868 && !OBJECT_P (false_rtx
))
4869 || reg_mentioned_p (true_rtx
, false_rtx
)
4870 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4872 true_code
= reversed_comparison_code (cond
, NULL
);
4873 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
4874 SUBST (XEXP (x
, 1), false_rtx
);
4875 SUBST (XEXP (x
, 2), true_rtx
);
4877 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4880 /* It is possible that the conditional has been simplified out. */
4881 true_code
= GET_CODE (cond
);
4882 comparison_p
= COMPARISON_P (cond
);
4885 /* If the two arms are identical, we don't need the comparison. */
4887 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4890 /* Convert a == b ? b : a to "a". */
4891 if (true_code
== EQ
&& ! side_effects_p (cond
)
4892 && !HONOR_NANS (mode
)
4893 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4894 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4896 else if (true_code
== NE
&& ! side_effects_p (cond
)
4897 && !HONOR_NANS (mode
)
4898 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4899 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4902 /* Look for cases where we have (abs x) or (neg (abs X)). */
4904 if (GET_MODE_CLASS (mode
) == MODE_INT
4905 && GET_CODE (false_rtx
) == NEG
4906 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4908 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4909 && ! side_effects_p (true_rtx
))
4914 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4918 simplify_gen_unary (NEG
, mode
,
4919 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4925 /* Look for MIN or MAX. */
4927 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4929 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4930 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4931 && ! side_effects_p (cond
))
4936 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4939 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4942 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4945 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4950 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4951 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4952 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4953 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4954 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4955 neither 1 or -1, but it isn't worth checking for. */
4957 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4959 && GET_MODE_CLASS (mode
) == MODE_INT
4960 && ! side_effects_p (x
))
4962 rtx t
= make_compound_operation (true_rtx
, SET
);
4963 rtx f
= make_compound_operation (false_rtx
, SET
);
4964 rtx cond_op0
= XEXP (cond
, 0);
4965 rtx cond_op1
= XEXP (cond
, 1);
4966 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
4967 enum machine_mode m
= mode
;
4968 rtx z
= 0, c1
= NULL_RTX
;
4970 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4971 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4972 || GET_CODE (t
) == ASHIFT
4973 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4974 && rtx_equal_p (XEXP (t
, 0), f
))
4975 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4977 /* If an identity-zero op is commutative, check whether there
4978 would be a match if we swapped the operands. */
4979 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4980 || GET_CODE (t
) == XOR
)
4981 && rtx_equal_p (XEXP (t
, 1), f
))
4982 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4983 else if (GET_CODE (t
) == SIGN_EXTEND
4984 && (GET_CODE (XEXP (t
, 0)) == PLUS
4985 || GET_CODE (XEXP (t
, 0)) == MINUS
4986 || GET_CODE (XEXP (t
, 0)) == IOR
4987 || GET_CODE (XEXP (t
, 0)) == XOR
4988 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4989 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4990 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4991 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4992 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4993 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4994 && (num_sign_bit_copies (f
, GET_MODE (f
))
4996 (GET_MODE_BITSIZE (mode
)
4997 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4999 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5000 extend_op
= SIGN_EXTEND
;
5001 m
= GET_MODE (XEXP (t
, 0));
5003 else if (GET_CODE (t
) == SIGN_EXTEND
5004 && (GET_CODE (XEXP (t
, 0)) == PLUS
5005 || GET_CODE (XEXP (t
, 0)) == IOR
5006 || GET_CODE (XEXP (t
, 0)) == XOR
)
5007 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5008 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5009 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5010 && (num_sign_bit_copies (f
, GET_MODE (f
))
5012 (GET_MODE_BITSIZE (mode
)
5013 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
5015 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5016 extend_op
= SIGN_EXTEND
;
5017 m
= GET_MODE (XEXP (t
, 0));
5019 else if (GET_CODE (t
) == ZERO_EXTEND
5020 && (GET_CODE (XEXP (t
, 0)) == PLUS
5021 || GET_CODE (XEXP (t
, 0)) == MINUS
5022 || GET_CODE (XEXP (t
, 0)) == IOR
5023 || GET_CODE (XEXP (t
, 0)) == XOR
5024 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5025 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5026 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5027 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5028 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5029 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5030 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5031 && ((nonzero_bits (f
, GET_MODE (f
))
5032 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
5035 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5036 extend_op
= ZERO_EXTEND
;
5037 m
= GET_MODE (XEXP (t
, 0));
5039 else if (GET_CODE (t
) == ZERO_EXTEND
5040 && (GET_CODE (XEXP (t
, 0)) == PLUS
5041 || GET_CODE (XEXP (t
, 0)) == IOR
5042 || GET_CODE (XEXP (t
, 0)) == XOR
)
5043 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5044 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5045 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5046 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5047 && ((nonzero_bits (f
, GET_MODE (f
))
5048 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
5051 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5052 extend_op
= ZERO_EXTEND
;
5053 m
= GET_MODE (XEXP (t
, 0));
5058 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
5059 cond_op0
, cond_op1
),
5060 pc_rtx
, pc_rtx
, 0, 0);
5061 temp
= simplify_gen_binary (MULT
, m
, temp
,
5062 simplify_gen_binary (MULT
, m
, c1
,
5064 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
5065 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
5067 if (extend_op
!= UNKNOWN
)
5068 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
5074 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5075 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5076 negation of a single bit, we can convert this operation to a shift. We
5077 can actually do this more generally, but it doesn't seem worth it. */
5079 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5080 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5081 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
5082 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
5083 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
5084 == GET_MODE_BITSIZE (mode
))
5085 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
5087 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5088 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
5090 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5091 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5092 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5093 && GET_MODE (XEXP (cond
, 0)) == mode
5094 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
5095 == nonzero_bits (XEXP (cond
, 0), mode
)
5096 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
5097 return XEXP (cond
, 0);
5102 /* Simplify X, a SET expression. Return the new expression. */
5105 simplify_set (rtx x
)
5107 rtx src
= SET_SRC (x
);
5108 rtx dest
= SET_DEST (x
);
5109 enum machine_mode mode
5110 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
5114 /* (set (pc) (return)) gets written as (return). */
5115 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
5118 /* Now that we know for sure which bits of SRC we are using, see if we can
5119 simplify the expression for the object knowing that we only need the
5122 if (GET_MODE_CLASS (mode
) == MODE_INT
5123 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5125 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
5126 SUBST (SET_SRC (x
), src
);
5129 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5130 the comparison result and try to simplify it unless we already have used
5131 undobuf.other_insn. */
5132 if ((GET_MODE_CLASS (mode
) == MODE_CC
5133 || GET_CODE (src
) == COMPARE
5135 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5136 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5137 && COMPARISON_P (*cc_use
)
5138 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5140 enum rtx_code old_code
= GET_CODE (*cc_use
);
5141 enum rtx_code new_code
;
5143 int other_changed
= 0;
5144 enum machine_mode compare_mode
= GET_MODE (dest
);
5146 if (GET_CODE (src
) == COMPARE
)
5147 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5149 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
5151 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
5154 new_code
= old_code
;
5155 else if (!CONSTANT_P (tmp
))
5157 new_code
= GET_CODE (tmp
);
5158 op0
= XEXP (tmp
, 0);
5159 op1
= XEXP (tmp
, 1);
5163 rtx pat
= PATTERN (other_insn
);
5164 undobuf
.other_insn
= other_insn
;
5165 SUBST (*cc_use
, tmp
);
5167 /* Attempt to simplify CC user. */
5168 if (GET_CODE (pat
) == SET
)
5170 rtx
new = simplify_rtx (SET_SRC (pat
));
5171 if (new != NULL_RTX
)
5172 SUBST (SET_SRC (pat
), new);
5175 /* Convert X into a no-op move. */
5176 SUBST (SET_DEST (x
), pc_rtx
);
5177 SUBST (SET_SRC (x
), pc_rtx
);
5181 /* Simplify our comparison, if possible. */
5182 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
5184 #ifdef SELECT_CC_MODE
5185 /* If this machine has CC modes other than CCmode, check to see if we
5186 need to use a different CC mode here. */
5187 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5188 compare_mode
= GET_MODE (op0
);
5190 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5193 /* If the mode changed, we have to change SET_DEST, the mode in the
5194 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5195 a hard register, just build new versions with the proper mode. If it
5196 is a pseudo, we lose unless it is only time we set the pseudo, in
5197 which case we can safely change its mode. */
5198 if (compare_mode
!= GET_MODE (dest
))
5200 unsigned int regno
= REGNO (dest
);
5201 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5203 if (regno
< FIRST_PSEUDO_REGISTER
5204 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5206 if (regno
>= FIRST_PSEUDO_REGISTER
)
5207 SUBST (regno_reg_rtx
[regno
], new_dest
);
5209 SUBST (SET_DEST (x
), new_dest
);
5210 SUBST (XEXP (*cc_use
, 0), new_dest
);
5217 #endif /* SELECT_CC_MODE */
5219 /* If the code changed, we have to build a new comparison in
5220 undobuf.other_insn. */
5221 if (new_code
!= old_code
)
5223 int other_changed_previously
= other_changed
;
5224 unsigned HOST_WIDE_INT mask
;
5226 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5230 /* If the only change we made was to change an EQ into an NE or
5231 vice versa, OP0 has only one bit that might be nonzero, and OP1
5232 is zero, check if changing the user of the condition code will
5233 produce a valid insn. If it won't, we can keep the original code
5234 in that insn by surrounding our operation with an XOR. */
5236 if (((old_code
== NE
&& new_code
== EQ
)
5237 || (old_code
== EQ
&& new_code
== NE
))
5238 && ! other_changed_previously
&& op1
== const0_rtx
5239 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5240 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5242 rtx pat
= PATTERN (other_insn
), note
= 0;
5244 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5245 && ! check_asm_operands (pat
)))
5247 PUT_CODE (*cc_use
, old_code
);
5250 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
),
5251 op0
, GEN_INT (mask
));
5257 undobuf
.other_insn
= other_insn
;
5260 /* If we are now comparing against zero, change our source if
5261 needed. If we do not use cc0, we always have a COMPARE. */
5262 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5264 SUBST (SET_SRC (x
), op0
);
5270 /* Otherwise, if we didn't previously have a COMPARE in the
5271 correct mode, we need one. */
5272 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5274 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5277 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
5279 SUBST(SET_SRC (x
), op0
);
5284 /* Otherwise, update the COMPARE if needed. */
5285 SUBST (XEXP (src
, 0), op0
);
5286 SUBST (XEXP (src
, 1), op1
);
5291 /* Get SET_SRC in a form where we have placed back any
5292 compound expressions. Then do the checks below. */
5293 src
= make_compound_operation (src
, SET
);
5294 SUBST (SET_SRC (x
), src
);
5297 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5298 and X being a REG or (subreg (reg)), we may be able to convert this to
5299 (set (subreg:m2 x) (op)).
5301 We can always do this if M1 is narrower than M2 because that means that
5302 we only care about the low bits of the result.
5304 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5305 perform a narrower operation than requested since the high-order bits will
5306 be undefined. On machine where it is defined, this transformation is safe
5307 as long as M1 and M2 have the same number of words. */
5309 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5310 && !OBJECT_P (SUBREG_REG (src
))
5311 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5313 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5314 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5315 #ifndef WORD_REGISTER_OPERATIONS
5316 && (GET_MODE_SIZE (GET_MODE (src
))
5317 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5319 #ifdef CANNOT_CHANGE_MODE_CLASS
5320 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
5321 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5322 GET_MODE (SUBREG_REG (src
)),
5326 || (GET_CODE (dest
) == SUBREG
5327 && REG_P (SUBREG_REG (dest
)))))
5329 SUBST (SET_DEST (x
),
5330 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
5332 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5334 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5338 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5341 && GET_CODE (src
) == SUBREG
5342 && subreg_lowpart_p (src
)
5343 && (GET_MODE_BITSIZE (GET_MODE (src
))
5344 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5346 rtx inner
= SUBREG_REG (src
);
5347 enum machine_mode inner_mode
= GET_MODE (inner
);
5349 /* Here we make sure that we don't have a sign bit on. */
5350 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5351 && (nonzero_bits (inner
, inner_mode
)
5352 < ((unsigned HOST_WIDE_INT
) 1
5353 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5355 SUBST (SET_SRC (x
), inner
);
5361 #ifdef LOAD_EXTEND_OP
5362 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5363 would require a paradoxical subreg. Replace the subreg with a
5364 zero_extend to avoid the reload that would otherwise be required. */
5366 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5367 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
5368 && SUBREG_BYTE (src
) == 0
5369 && (GET_MODE_SIZE (GET_MODE (src
))
5370 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5371 && MEM_P (SUBREG_REG (src
)))
5374 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5375 GET_MODE (src
), SUBREG_REG (src
)));
5381 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5382 are comparing an item known to be 0 or -1 against 0, use a logical
5383 operation instead. Check for one of the arms being an IOR of the other
5384 arm with some value. We compute three terms to be IOR'ed together. In
5385 practice, at most two will be nonzero. Then we do the IOR's. */
5387 if (GET_CODE (dest
) != PC
5388 && GET_CODE (src
) == IF_THEN_ELSE
5389 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5390 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5391 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5392 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5393 #ifdef HAVE_conditional_move
5394 && ! can_conditionally_move_p (GET_MODE (src
))
5396 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5397 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5398 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5399 && ! side_effects_p (src
))
5401 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5402 ? XEXP (src
, 1) : XEXP (src
, 2));
5403 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5404 ? XEXP (src
, 2) : XEXP (src
, 1));
5405 rtx term1
= const0_rtx
, term2
, term3
;
5407 if (GET_CODE (true_rtx
) == IOR
5408 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5409 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5410 else if (GET_CODE (true_rtx
) == IOR
5411 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5412 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5413 else if (GET_CODE (false_rtx
) == IOR
5414 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5415 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5416 else if (GET_CODE (false_rtx
) == IOR
5417 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5418 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5420 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
5421 XEXP (XEXP (src
, 0), 0), true_rtx
);
5422 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
5423 simplify_gen_unary (NOT
, GET_MODE (src
),
5424 XEXP (XEXP (src
, 0), 0),
5429 simplify_gen_binary (IOR
, GET_MODE (src
),
5430 simplify_gen_binary (IOR
, GET_MODE (src
),
5437 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5438 whole thing fail. */
5439 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5441 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5444 /* Convert this into a field assignment operation, if possible. */
5445 return make_field_assignment (x
);
5448 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5452 simplify_logical (rtx x
)
5454 enum machine_mode mode
= GET_MODE (x
);
5455 rtx op0
= XEXP (x
, 0);
5456 rtx op1
= XEXP (x
, 1);
5459 switch (GET_CODE (x
))
5462 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5463 insn (and may simplify more). */
5464 if (GET_CODE (op0
) == XOR
5465 && rtx_equal_p (XEXP (op0
, 0), op1
)
5466 && ! side_effects_p (op1
))
5467 x
= simplify_gen_binary (AND
, mode
,
5468 simplify_gen_unary (NOT
, mode
,
5469 XEXP (op0
, 1), mode
),
5472 if (GET_CODE (op0
) == XOR
5473 && rtx_equal_p (XEXP (op0
, 1), op1
)
5474 && ! side_effects_p (op1
))
5475 x
= simplify_gen_binary (AND
, mode
,
5476 simplify_gen_unary (NOT
, mode
,
5477 XEXP (op0
, 0), mode
),
5480 /* Similarly for (~(A ^ B)) & A. */
5481 if (GET_CODE (op0
) == NOT
5482 && GET_CODE (XEXP (op0
, 0)) == XOR
5483 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5484 && ! side_effects_p (op1
))
5485 x
= simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5487 if (GET_CODE (op0
) == NOT
5488 && GET_CODE (XEXP (op0
, 0)) == XOR
5489 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5490 && ! side_effects_p (op1
))
5491 x
= simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5493 /* We can call simplify_and_const_int only if we don't lose
5494 any (sign) bits when converting INTVAL (op1) to
5495 "unsigned HOST_WIDE_INT". */
5496 if (GET_CODE (op1
) == CONST_INT
5497 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5498 || INTVAL (op1
) > 0))
5500 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5502 /* If we have (ior (and (X C1) C2)) and the next restart would be
5503 the last, simplify this by making C1 as small as possible
5504 and then exit. Only do this if C1 actually changes: for now
5505 this only saves memory but, should this transformation be
5506 moved to simplify-rtx.c, we'd risk unbounded recursion there. */
5507 if (GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5508 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5509 && GET_CODE (op1
) == CONST_INT
5510 && (INTVAL (XEXP (op0
, 1)) & INTVAL (op1
)) != 0)
5511 return simplify_gen_binary (IOR
, mode
,
5513 (AND
, mode
, XEXP (op0
, 0),
5514 GEN_INT (INTVAL (XEXP (op0
, 1))
5515 & ~INTVAL (op1
))), op1
);
5517 if (GET_CODE (x
) != AND
)
5524 /* Convert (A | B) & A to A. */
5525 if (GET_CODE (op0
) == IOR
5526 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5527 || rtx_equal_p (XEXP (op0
, 1), op1
))
5528 && ! side_effects_p (XEXP (op0
, 0))
5529 && ! side_effects_p (XEXP (op0
, 1)))
5532 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5533 apply the distributive law and then the inverse distributive
5534 law to see if things simplify. */
5535 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5537 rtx result
= distribute_and_simplify_rtx (x
, 0);
5541 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5543 rtx result
= distribute_and_simplify_rtx (x
, 1);
5550 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5551 if (GET_CODE (op1
) == CONST_INT
5552 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5553 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5556 /* Convert (A & B) | A to A. */
5557 if (GET_CODE (op0
) == AND
5558 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5559 || rtx_equal_p (XEXP (op0
, 1), op1
))
5560 && ! side_effects_p (XEXP (op0
, 0))
5561 && ! side_effects_p (XEXP (op0
, 1)))
5564 /* If we have (ior (and A B) C), apply the distributive law and then
5565 the inverse distributive law to see if things simplify. */
5567 if (GET_CODE (op0
) == AND
)
5569 rtx result
= distribute_and_simplify_rtx (x
, 0);
5574 if (GET_CODE (op1
) == AND
)
5576 rtx result
= distribute_and_simplify_rtx (x
, 1);
5581 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5582 mode size to (rotate A CX). */
5584 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5585 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5586 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5587 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5588 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5589 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5590 == GET_MODE_BITSIZE (mode
)))
5591 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5592 (GET_CODE (op0
) == ASHIFT
5593 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5595 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5596 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5597 does not affect any of the bits in OP1, it can really be done
5598 as a PLUS and we can associate. We do this by seeing if OP1
5599 can be safely shifted left C bits. */
5600 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5601 && GET_CODE (XEXP (op0
, 0)) == PLUS
5602 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5603 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5604 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5606 int count
= INTVAL (XEXP (op0
, 1));
5607 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5609 if (mask
>> count
== INTVAL (op1
)
5610 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5612 SUBST (XEXP (XEXP (op0
, 0), 1),
5613 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5620 /* If we are XORing two things that have no bits in common,
5621 convert them into an IOR. This helps to detect rotation encoded
5622 using those methods and possibly other simplifications. */
5624 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5625 && (nonzero_bits (op0
, mode
)
5626 & nonzero_bits (op1
, mode
)) == 0)
5627 return (simplify_gen_binary (IOR
, mode
, op0
, op1
));
5629 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5630 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5633 int num_negated
= 0;
5635 if (GET_CODE (op0
) == NOT
)
5636 num_negated
++, op0
= XEXP (op0
, 0);
5637 if (GET_CODE (op1
) == NOT
)
5638 num_negated
++, op1
= XEXP (op1
, 0);
5640 if (num_negated
== 2)
5642 SUBST (XEXP (x
, 0), op0
);
5643 SUBST (XEXP (x
, 1), op1
);
5645 else if (num_negated
== 1)
5647 simplify_gen_unary (NOT
, mode
,
5648 simplify_gen_binary (XOR
, mode
, op0
, op1
),
5652 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5653 correspond to a machine insn or result in further simplifications
5654 if B is a constant. */
5656 if (GET_CODE (op0
) == AND
5657 && rtx_equal_p (XEXP (op0
, 1), op1
)
5658 && ! side_effects_p (op1
))
5659 return simplify_gen_binary (AND
, mode
,
5660 simplify_gen_unary (NOT
, mode
,
5661 XEXP (op0
, 0), mode
),
5664 else if (GET_CODE (op0
) == AND
5665 && rtx_equal_p (XEXP (op0
, 0), op1
)
5666 && ! side_effects_p (op1
))
5667 return simplify_gen_binary (AND
, mode
,
5668 simplify_gen_unary (NOT
, mode
,
5669 XEXP (op0
, 1), mode
),
5672 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5673 comparison if STORE_FLAG_VALUE is 1. */
5674 if (STORE_FLAG_VALUE
== 1
5675 && op1
== const1_rtx
5676 && COMPARISON_P (op0
)
5677 && (reversed
= reversed_comparison (op0
, mode
)))
5680 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5681 is (lt foo (const_int 0)), so we can perform the above
5682 simplification if STORE_FLAG_VALUE is 1. */
5684 if (STORE_FLAG_VALUE
== 1
5685 && op1
== const1_rtx
5686 && GET_CODE (op0
) == LSHIFTRT
5687 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5688 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5689 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5691 /* (xor (comparison foo bar) (const_int sign-bit))
5692 when STORE_FLAG_VALUE is the sign bit. */
5693 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5694 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5695 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5696 && op1
== const_true_rtx
5697 && COMPARISON_P (op0
)
5698 && (reversed
= reversed_comparison (op0
, mode
)))
5710 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5711 operations" because they can be replaced with two more basic operations.
5712 ZERO_EXTEND is also considered "compound" because it can be replaced with
5713 an AND operation, which is simpler, though only one operation.
5715 The function expand_compound_operation is called with an rtx expression
5716 and will convert it to the appropriate shifts and AND operations,
5717 simplifying at each stage.
5719 The function make_compound_operation is called to convert an expression
5720 consisting of shifts and ANDs into the equivalent compound expression.
5721 It is the inverse of this function, loosely speaking. */
5724 expand_compound_operation (rtx x
)
5726 unsigned HOST_WIDE_INT pos
= 0, len
;
5728 unsigned int modewidth
;
5731 switch (GET_CODE (x
))
5736 /* We can't necessarily use a const_int for a multiword mode;
5737 it depends on implicitly extending the value.
5738 Since we don't know the right way to extend it,
5739 we can't tell whether the implicit way is right.
5741 Even for a mode that is no wider than a const_int,
5742 we can't win, because we need to sign extend one of its bits through
5743 the rest of it, and we don't know which bit. */
5744 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5747 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5748 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5749 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5750 reloaded. If not for that, MEM's would very rarely be safe.
5752 Reject MODEs bigger than a word, because we might not be able
5753 to reference a two-register group starting with an arbitrary register
5754 (and currently gen_lowpart might crash for a SUBREG). */
5756 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5759 /* Reject MODEs that aren't scalar integers because turning vector
5760 or complex modes into shifts causes problems. */
5762 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5765 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5766 /* If the inner object has VOIDmode (the only way this can happen
5767 is if it is an ASM_OPERANDS), we can't do anything since we don't
5768 know how much masking to do. */
5777 /* ... fall through ... */
5780 /* If the operand is a CLOBBER, just return it. */
5781 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5784 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5785 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5786 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5789 /* Reject MODEs that aren't scalar integers because turning vector
5790 or complex modes into shifts causes problems. */
5792 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5795 len
= INTVAL (XEXP (x
, 1));
5796 pos
= INTVAL (XEXP (x
, 2));
5798 /* If this goes outside the object being extracted, replace the object
5799 with a (use (mem ...)) construct that only combine understands
5800 and is used only for this purpose. */
5801 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5802 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5804 if (BITS_BIG_ENDIAN
)
5805 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5812 /* Convert sign extension to zero extension, if we know that the high
5813 bit is not set, as this is easier to optimize. It will be converted
5814 back to cheaper alternative in make_extraction. */
5815 if (GET_CODE (x
) == SIGN_EXTEND
5816 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5817 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5818 & ~(((unsigned HOST_WIDE_INT
)
5819 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5823 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5824 rtx temp2
= expand_compound_operation (temp
);
5826 /* Make sure this is a profitable operation. */
5827 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5829 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5835 /* We can optimize some special cases of ZERO_EXTEND. */
5836 if (GET_CODE (x
) == ZERO_EXTEND
)
5838 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5839 know that the last value didn't have any inappropriate bits
5841 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5842 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5843 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5844 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5845 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5846 return XEXP (XEXP (x
, 0), 0);
5848 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5849 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5850 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5851 && subreg_lowpart_p (XEXP (x
, 0))
5852 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5853 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5854 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5855 return SUBREG_REG (XEXP (x
, 0));
5857 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5858 is a comparison and STORE_FLAG_VALUE permits. This is like
5859 the first case, but it works even when GET_MODE (x) is larger
5860 than HOST_WIDE_INT. */
5861 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5862 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5863 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
5864 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5865 <= HOST_BITS_PER_WIDE_INT
)
5866 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5867 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5868 return XEXP (XEXP (x
, 0), 0);
5870 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5871 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5872 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5873 && subreg_lowpart_p (XEXP (x
, 0))
5874 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
5875 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5876 <= HOST_BITS_PER_WIDE_INT
)
5877 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5878 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5879 return SUBREG_REG (XEXP (x
, 0));
5883 /* If we reach here, we want to return a pair of shifts. The inner
5884 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5885 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5886 logical depending on the value of UNSIGNEDP.
5888 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5889 converted into an AND of a shift.
5891 We must check for the case where the left shift would have a negative
5892 count. This can happen in a case like (x >> 31) & 255 on machines
5893 that can't shift by a constant. On those machines, we would first
5894 combine the shift with the AND to produce a variable-position
5895 extraction. Then the constant of 31 would be substituted in to produce
5896 a such a position. */
5898 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5899 if (modewidth
+ len
>= pos
)
5900 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5902 simplify_shift_const (NULL_RTX
, ASHIFT
,
5905 modewidth
- pos
- len
),
5908 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5909 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5910 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5913 ((HOST_WIDE_INT
) 1 << len
) - 1);
5915 /* Any other cases we can't handle. */
5918 /* If we couldn't do this for some reason, return the original
5920 if (GET_CODE (tem
) == CLOBBER
)
5926 /* X is a SET which contains an assignment of one object into
5927 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5928 or certain SUBREGS). If possible, convert it into a series of
5931 We half-heartedly support variable positions, but do not at all
5932 support variable lengths. */
5935 expand_field_assignment (rtx x
)
5938 rtx pos
; /* Always counts from low bit. */
5940 rtx mask
, cleared
, masked
;
5941 enum machine_mode compute_mode
;
5943 /* Loop until we find something we can't simplify. */
5946 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5947 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5949 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5950 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5951 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5953 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5954 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5956 inner
= XEXP (SET_DEST (x
), 0);
5957 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5958 pos
= XEXP (SET_DEST (x
), 2);
5960 /* If the position is constant and spans the width of INNER,
5961 surround INNER with a USE to indicate this. */
5962 if (GET_CODE (pos
) == CONST_INT
5963 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5964 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5966 if (BITS_BIG_ENDIAN
)
5968 if (GET_CODE (pos
) == CONST_INT
)
5969 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5971 else if (GET_CODE (pos
) == MINUS
5972 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5973 && (INTVAL (XEXP (pos
, 1))
5974 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5975 /* If position is ADJUST - X, new position is X. */
5976 pos
= XEXP (pos
, 0);
5978 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
5979 GEN_INT (GET_MODE_BITSIZE (
5986 /* A SUBREG between two modes that occupy the same numbers of words
5987 can be done by moving the SUBREG to the source. */
5988 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5989 /* We need SUBREGs to compute nonzero_bits properly. */
5990 && nonzero_sign_valid
5991 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5992 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5993 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5994 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5996 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5998 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6005 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6006 inner
= SUBREG_REG (inner
);
6008 compute_mode
= GET_MODE (inner
);
6010 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6011 if (! SCALAR_INT_MODE_P (compute_mode
))
6013 enum machine_mode imode
;
6015 /* Don't do anything for vector or complex integral types. */
6016 if (! FLOAT_MODE_P (compute_mode
))
6019 /* Try to find an integral mode to pun with. */
6020 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6021 if (imode
== BLKmode
)
6024 compute_mode
= imode
;
6025 inner
= gen_lowpart (imode
, inner
);
6028 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6029 if (len
>= HOST_BITS_PER_WIDE_INT
)
6032 /* Now compute the equivalent expression. Make a copy of INNER
6033 for the SET_DEST in case it is a MEM into which we will substitute;
6034 we don't want shared RTL in that case. */
6035 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
6036 cleared
= simplify_gen_binary (AND
, compute_mode
,
6037 simplify_gen_unary (NOT
, compute_mode
,
6038 simplify_gen_binary (ASHIFT
,
6043 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
6044 simplify_gen_binary (
6046 gen_lowpart (compute_mode
, SET_SRC (x
)),
6050 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
6051 simplify_gen_binary (IOR
, compute_mode
,
6058 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6059 it is an RTX that represents a variable starting position; otherwise,
6060 POS is the (constant) starting bit position (counted from the LSB).
6062 INNER may be a USE. This will occur when we started with a bitfield
6063 that went outside the boundary of the object in memory, which is
6064 allowed on most machines. To isolate this case, we produce a USE
6065 whose mode is wide enough and surround the MEM with it. The only
6066 code that understands the USE is this routine. If it is not removed,
6067 it will cause the resulting insn not to match.
6069 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6072 IN_DEST is nonzero if this is a reference in the destination of a
6073 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6074 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6077 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6078 ZERO_EXTRACT should be built even for bits starting at bit 0.
6080 MODE is the desired mode of the result (if IN_DEST == 0).
6082 The result is an RTX for the extraction or NULL_RTX if the target
6086 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
6087 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
6088 int in_dest
, int in_compare
)
6090 /* This mode describes the size of the storage area
6091 to fetch the overall value from. Within that, we
6092 ignore the POS lowest bits, etc. */
6093 enum machine_mode is_mode
= GET_MODE (inner
);
6094 enum machine_mode inner_mode
;
6095 enum machine_mode wanted_inner_mode
= byte_mode
;
6096 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6097 enum machine_mode pos_mode
= word_mode
;
6098 enum machine_mode extraction_mode
= word_mode
;
6099 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6102 rtx orig_pos_rtx
= pos_rtx
;
6103 HOST_WIDE_INT orig_pos
;
6105 /* Get some information about INNER and get the innermost object. */
6106 if (GET_CODE (inner
) == USE
)
6107 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6108 /* We don't need to adjust the position because we set up the USE
6109 to pretend that it was a full-word object. */
6110 spans_byte
= 1, inner
= XEXP (inner
, 0);
6111 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6113 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6114 consider just the QI as the memory to extract from.
6115 The subreg adds or removes high bits; its mode is
6116 irrelevant to the meaning of this extraction,
6117 since POS and LEN count from the lsb. */
6118 if (MEM_P (SUBREG_REG (inner
)))
6119 is_mode
= GET_MODE (SUBREG_REG (inner
));
6120 inner
= SUBREG_REG (inner
);
6122 else if (GET_CODE (inner
) == ASHIFT
6123 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
6124 && pos_rtx
== 0 && pos
== 0
6125 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6127 /* We're extracting the least significant bits of an rtx
6128 (ashift X (const_int C)), where LEN > C. Extract the
6129 least significant (LEN - C) bits of X, giving an rtx
6130 whose mode is MODE, then shift it left C times. */
6131 new = make_extraction (mode
, XEXP (inner
, 0),
6132 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6133 unsignedp
, in_dest
, in_compare
);
6135 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
6138 inner_mode
= GET_MODE (inner
);
6140 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6141 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6143 /* See if this can be done without an extraction. We never can if the
6144 width of the field is not the same as that of some integer mode. For
6145 registers, we can only avoid the extraction if the position is at the
6146 low-order bit and this is either not in the destination or we have the
6147 appropriate STRICT_LOW_PART operation available.
6149 For MEM, we can avoid an extract if the field starts on an appropriate
6150 boundary and we can change the mode of the memory reference. However,
6151 we cannot directly access the MEM if we have a USE and the underlying
6152 MEM is not TMODE. This combination means that MEM was being used in a
6153 context where bits outside its mode were being referenced; that is only
6154 valid in bit-field insns. */
6156 if (tmode
!= BLKmode
6157 && ! (spans_byte
&& inner_mode
!= tmode
)
6158 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6162 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6163 || (MEM_P (inner
) && pos_rtx
== 0
6165 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6166 : BITS_PER_UNIT
)) == 0
6167 /* We can't do this if we are widening INNER_MODE (it
6168 may not be aligned, for one thing). */
6169 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6170 && (inner_mode
== tmode
6171 || (! mode_dependent_address_p (XEXP (inner
, 0))
6172 && ! MEM_VOLATILE_P (inner
))))))
6174 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6175 field. If the original and current mode are the same, we need not
6176 adjust the offset. Otherwise, we do if bytes big endian.
6178 If INNER is not a MEM, get a piece consisting of just the field
6179 of interest (in this case POS % BITS_PER_WORD must be 0). */
6183 HOST_WIDE_INT offset
;
6185 /* POS counts from lsb, but make OFFSET count in memory order. */
6186 if (BYTES_BIG_ENDIAN
)
6187 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6189 offset
= pos
/ BITS_PER_UNIT
;
6191 new = adjust_address_nv (inner
, tmode
, offset
);
6193 else if (REG_P (inner
))
6195 if (tmode
!= inner_mode
)
6197 /* We can't call gen_lowpart in a DEST since we
6198 always want a SUBREG (see below) and it would sometimes
6199 return a new hard register. */
6202 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6204 if (WORDS_BIG_ENDIAN
6205 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6206 final_word
= ((GET_MODE_SIZE (inner_mode
)
6207 - GET_MODE_SIZE (tmode
))
6208 / UNITS_PER_WORD
) - final_word
;
6210 final_word
*= UNITS_PER_WORD
;
6211 if (BYTES_BIG_ENDIAN
&&
6212 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6213 final_word
+= (GET_MODE_SIZE (inner_mode
)
6214 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6216 /* Avoid creating invalid subregs, for example when
6217 simplifying (x>>32)&255. */
6218 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6221 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6224 new = gen_lowpart (tmode
, inner
);
6230 new = force_to_mode (inner
, tmode
,
6231 len
>= HOST_BITS_PER_WIDE_INT
6232 ? ~(unsigned HOST_WIDE_INT
) 0
6233 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6236 /* If this extraction is going into the destination of a SET,
6237 make a STRICT_LOW_PART unless we made a MEM. */
6240 return (MEM_P (new) ? new
6241 : (GET_CODE (new) != SUBREG
6242 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6243 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6248 if (GET_CODE (new) == CONST_INT
)
6249 return gen_int_mode (INTVAL (new), mode
);
6251 /* If we know that no extraneous bits are set, and that the high
6252 bit is not set, convert the extraction to the cheaper of
6253 sign and zero extension, that are equivalent in these cases. */
6254 if (flag_expensive_optimizations
6255 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6256 && ((nonzero_bits (new, tmode
)
6257 & ~(((unsigned HOST_WIDE_INT
)
6258 GET_MODE_MASK (tmode
))
6262 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6263 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6265 /* Prefer ZERO_EXTENSION, since it gives more information to
6267 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6272 /* Otherwise, sign- or zero-extend unless we already are in the
6275 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6279 /* Unless this is a COMPARE or we have a funny memory reference,
6280 don't do anything with zero-extending field extracts starting at
6281 the low-order bit since they are simple AND operations. */
6282 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6283 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6286 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6287 we would be spanning bytes or if the position is not a constant and the
6288 length is not 1. In all other cases, we would only be going outside
6289 our object in cases when an original shift would have been
6291 if (! spans_byte
&& MEM_P (inner
)
6292 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6293 || (pos_rtx
!= 0 && len
!= 1)))
6296 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6297 and the mode for the result. */
6298 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6300 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6301 pos_mode
= mode_for_extraction (EP_insv
, 2);
6302 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6305 if (! in_dest
&& unsignedp
6306 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6308 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6309 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6310 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6313 if (! in_dest
&& ! unsignedp
6314 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6316 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6317 pos_mode
= mode_for_extraction (EP_extv
, 3);
6318 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6321 /* Never narrow an object, since that might not be safe. */
6323 if (mode
!= VOIDmode
6324 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6325 extraction_mode
= mode
;
6327 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6328 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6329 pos_mode
= GET_MODE (pos_rtx
);
6331 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6332 if we have to change the mode of memory and cannot, the desired mode is
6335 wanted_inner_mode
= wanted_inner_reg_mode
;
6336 else if (inner_mode
!= wanted_inner_mode
6337 && (mode_dependent_address_p (XEXP (inner
, 0))
6338 || MEM_VOLATILE_P (inner
)))
6339 wanted_inner_mode
= extraction_mode
;
6343 if (BITS_BIG_ENDIAN
)
6345 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6346 BITS_BIG_ENDIAN style. If position is constant, compute new
6347 position. Otherwise, build subtraction.
6348 Note that POS is relative to the mode of the original argument.
6349 If it's a MEM we need to recompute POS relative to that.
6350 However, if we're extracting from (or inserting into) a register,
6351 we want to recompute POS relative to wanted_inner_mode. */
6352 int width
= (MEM_P (inner
)
6353 ? GET_MODE_BITSIZE (is_mode
)
6354 : GET_MODE_BITSIZE (wanted_inner_mode
));
6357 pos
= width
- len
- pos
;
6360 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6361 /* POS may be less than 0 now, but we check for that below.
6362 Note that it can only be less than 0 if !MEM_P (inner). */
6365 /* If INNER has a wider mode, make it smaller. If this is a constant
6366 extract, try to adjust the byte to point to the byte containing
6368 if (wanted_inner_mode
!= VOIDmode
6369 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6371 && (inner_mode
== wanted_inner_mode
6372 || (! mode_dependent_address_p (XEXP (inner
, 0))
6373 && ! MEM_VOLATILE_P (inner
))))))
6377 /* The computations below will be correct if the machine is big
6378 endian in both bits and bytes or little endian in bits and bytes.
6379 If it is mixed, we must adjust. */
6381 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6382 adjust OFFSET to compensate. */
6383 if (BYTES_BIG_ENDIAN
6385 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6386 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6388 /* If this is a constant position, we can move to the desired byte. */
6391 offset
+= pos
/ BITS_PER_UNIT
;
6392 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6395 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6397 && is_mode
!= wanted_inner_mode
)
6398 offset
= (GET_MODE_SIZE (is_mode
)
6399 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6401 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6402 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6405 /* If INNER is not memory, we can always get it into the proper mode. If we
6406 are changing its mode, POS must be a constant and smaller than the size
6408 else if (!MEM_P (inner
))
6410 if (GET_MODE (inner
) != wanted_inner_mode
6412 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6415 inner
= force_to_mode (inner
, wanted_inner_mode
,
6417 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6418 ? ~(unsigned HOST_WIDE_INT
) 0
6419 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6424 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6425 have to zero extend. Otherwise, we can just use a SUBREG. */
6427 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6429 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6431 /* If we know that no extraneous bits are set, and that the high
6432 bit is not set, convert extraction to cheaper one - either
6433 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6435 if (flag_expensive_optimizations
6436 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6437 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6438 & ~(((unsigned HOST_WIDE_INT
)
6439 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6443 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6445 /* Prefer ZERO_EXTENSION, since it gives more information to
6447 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6452 else if (pos_rtx
!= 0
6453 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6454 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
6456 /* Make POS_RTX unless we already have it and it is correct. If we don't
6457 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6459 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6460 pos_rtx
= orig_pos_rtx
;
6462 else if (pos_rtx
== 0)
6463 pos_rtx
= GEN_INT (pos
);
6465 /* Make the required operation. See if we can use existing rtx. */
6466 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6467 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6469 new = gen_lowpart (mode
, new);
6474 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6475 with any other operations in X. Return X without that shift if so. */
6478 extract_left_shift (rtx x
, int count
)
6480 enum rtx_code code
= GET_CODE (x
);
6481 enum machine_mode mode
= GET_MODE (x
);
6487 /* This is the shift itself. If it is wide enough, we will return
6488 either the value being shifted if the shift count is equal to
6489 COUNT or a shift for the difference. */
6490 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6491 && INTVAL (XEXP (x
, 1)) >= count
)
6492 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6493 INTVAL (XEXP (x
, 1)) - count
);
6497 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6498 return simplify_gen_unary (code
, mode
, tem
, mode
);
6502 case PLUS
: case IOR
: case XOR
: case AND
:
6503 /* If we can safely shift this constant and we find the inner shift,
6504 make a new operation. */
6505 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6506 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6507 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6508 return simplify_gen_binary (code
, mode
, tem
,
6509 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6520 /* Look at the expression rooted at X. Look for expressions
6521 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6522 Form these expressions.
6524 Return the new rtx, usually just X.
6526 Also, for machines like the VAX that don't have logical shift insns,
6527 try to convert logical to arithmetic shift operations in cases where
6528 they are equivalent. This undoes the canonicalizations to logical
6529 shifts done elsewhere.
6531 We try, as much as possible, to re-use rtl expressions to save memory.
6533 IN_CODE says what kind of expression we are processing. Normally, it is
6534 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6535 being kludges), it is MEM. When processing the arguments of a comparison
6536 or a COMPARE against zero, it is COMPARE. */
6539 make_compound_operation (rtx x
, enum rtx_code in_code
)
6541 enum rtx_code code
= GET_CODE (x
);
6542 enum machine_mode mode
= GET_MODE (x
);
6543 int mode_width
= GET_MODE_BITSIZE (mode
);
6545 enum rtx_code next_code
;
6551 /* Select the code to be used in recursive calls. Once we are inside an
6552 address, we stay there. If we have a comparison, set to COMPARE,
6553 but once inside, go back to our default of SET. */
6555 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6556 : ((code
== COMPARE
|| COMPARISON_P (x
))
6557 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6558 : in_code
== COMPARE
? SET
: in_code
);
6560 /* Process depending on the code of this operation. If NEW is set
6561 nonzero, it will be returned. */
6566 /* Convert shifts by constants into multiplications if inside
6568 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6569 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6570 && INTVAL (XEXP (x
, 1)) >= 0)
6572 new = make_compound_operation (XEXP (x
, 0), next_code
);
6573 new = gen_rtx_MULT (mode
, new,
6574 GEN_INT ((HOST_WIDE_INT
) 1
6575 << INTVAL (XEXP (x
, 1))));
6580 /* If the second operand is not a constant, we can't do anything
6582 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6585 /* If the constant is a power of two minus one and the first operand
6586 is a logical right shift, make an extraction. */
6587 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6588 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6590 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6591 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6592 0, in_code
== COMPARE
);
6595 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6596 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6597 && subreg_lowpart_p (XEXP (x
, 0))
6598 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6599 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6601 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6603 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6604 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6605 0, in_code
== COMPARE
);
6607 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6608 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6609 || GET_CODE (XEXP (x
, 0)) == IOR
)
6610 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6611 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6612 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6614 /* Apply the distributive law, and then try to make extractions. */
6615 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6616 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6618 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6620 new = make_compound_operation (new, in_code
);
6623 /* If we are have (and (rotate X C) M) and C is larger than the number
6624 of bits in M, this is an extraction. */
6626 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6627 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6628 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6629 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6631 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6632 new = make_extraction (mode
, new,
6633 (GET_MODE_BITSIZE (mode
)
6634 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6635 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6638 /* On machines without logical shifts, if the operand of the AND is
6639 a logical shift and our mask turns off all the propagated sign
6640 bits, we can replace the logical shift with an arithmetic shift. */
6641 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6642 && !have_insn_for (LSHIFTRT
, mode
)
6643 && have_insn_for (ASHIFTRT
, mode
)
6644 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6645 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6646 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6647 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6649 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6651 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6652 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6654 gen_rtx_ASHIFTRT (mode
,
6655 make_compound_operation
6656 (XEXP (XEXP (x
, 0), 0), next_code
),
6657 XEXP (XEXP (x
, 0), 1)));
6660 /* If the constant is one less than a power of two, this might be
6661 representable by an extraction even if no shift is present.
6662 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6663 we are in a COMPARE. */
6664 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6665 new = make_extraction (mode
,
6666 make_compound_operation (XEXP (x
, 0),
6668 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6670 /* If we are in a comparison and this is an AND with a power of two,
6671 convert this into the appropriate bit extract. */
6672 else if (in_code
== COMPARE
6673 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6674 new = make_extraction (mode
,
6675 make_compound_operation (XEXP (x
, 0),
6677 i
, NULL_RTX
, 1, 1, 0, 1);
6682 /* If the sign bit is known to be zero, replace this with an
6683 arithmetic shift. */
6684 if (have_insn_for (ASHIFTRT
, mode
)
6685 && ! have_insn_for (LSHIFTRT
, mode
)
6686 && mode_width
<= HOST_BITS_PER_WIDE_INT
6687 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6689 new = gen_rtx_ASHIFTRT (mode
,
6690 make_compound_operation (XEXP (x
, 0),
6696 /* ... fall through ... */
6702 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6703 this is a SIGN_EXTRACT. */
6704 if (GET_CODE (rhs
) == CONST_INT
6705 && GET_CODE (lhs
) == ASHIFT
6706 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6707 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6709 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6710 new = make_extraction (mode
, new,
6711 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6712 NULL_RTX
, mode_width
- INTVAL (rhs
),
6713 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6717 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6718 If so, try to merge the shifts into a SIGN_EXTEND. We could
6719 also do this for some cases of SIGN_EXTRACT, but it doesn't
6720 seem worth the effort; the case checked for occurs on Alpha. */
6723 && ! (GET_CODE (lhs
) == SUBREG
6724 && (OBJECT_P (SUBREG_REG (lhs
))))
6725 && GET_CODE (rhs
) == CONST_INT
6726 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6727 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6728 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6729 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6730 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6735 /* Call ourselves recursively on the inner expression. If we are
6736 narrowing the object and it has a different RTL code from
6737 what it originally did, do this SUBREG as a force_to_mode. */
6739 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6743 simplified
= simplify_subreg (GET_MODE (x
), tem
, GET_MODE (tem
),
6749 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6750 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6751 && subreg_lowpart_p (x
))
6753 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6756 /* If we have something other than a SUBREG, we might have
6757 done an expansion, so rerun ourselves. */
6758 if (GET_CODE (newer
) != SUBREG
)
6759 newer
= make_compound_operation (newer
, in_code
);
6775 x
= gen_lowpart (mode
, new);
6776 code
= GET_CODE (x
);
6779 /* Now recursively process each operand of this operation. */
6780 fmt
= GET_RTX_FORMAT (code
);
6781 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6784 new = make_compound_operation (XEXP (x
, i
), next_code
);
6785 SUBST (XEXP (x
, i
), new);
6791 /* Given M see if it is a value that would select a field of bits
6792 within an item, but not the entire word. Return -1 if not.
6793 Otherwise, return the starting position of the field, where 0 is the
6796 *PLEN is set to the length of the field. */
6799 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6801 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6802 int pos
= exact_log2 (m
& -m
);
6806 /* Now shift off the low-order zero bits and see if we have a
6807 power of two minus 1. */
6808 len
= exact_log2 ((m
>> pos
) + 1);
6817 /* See if X can be simplified knowing that we will only refer to it in
6818 MODE and will only refer to those bits that are nonzero in MASK.
6819 If other bits are being computed or if masking operations are done
6820 that select a superset of the bits in MASK, they can sometimes be
6823 Return a possibly simplified expression, but always convert X to
6824 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6826 Also, if REG is nonzero and X is a register equal in value to REG,
6829 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6830 are all off in X. This is used when X will be complemented, by either
6831 NOT, NEG, or XOR. */
6834 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6835 rtx reg
, int just_select
)
6837 enum rtx_code code
= GET_CODE (x
);
6838 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6839 enum machine_mode op_mode
;
6840 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6843 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6844 code below will do the wrong thing since the mode of such an
6845 expression is VOIDmode.
6847 Also do nothing if X is a CLOBBER; this can happen if X was
6848 the return value from a call to gen_lowpart. */
6849 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6852 /* We want to perform the operation is its present mode unless we know
6853 that the operation is valid in MODE, in which case we do the operation
6855 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6856 && have_insn_for (code
, mode
))
6857 ? mode
: GET_MODE (x
));
6859 /* It is not valid to do a right-shift in a narrower mode
6860 than the one it came in with. */
6861 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6862 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6863 op_mode
= GET_MODE (x
);
6865 /* Truncate MASK to fit OP_MODE. */
6867 mask
&= GET_MODE_MASK (op_mode
);
6869 /* When we have an arithmetic operation, or a shift whose count we
6870 do not know, we need to assume that all bits up to the highest-order
6871 bit in MASK will be needed. This is how we form such a mask. */
6872 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
6873 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
6875 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6878 /* Determine what bits of X are guaranteed to be (non)zero. */
6879 nonzero
= nonzero_bits (x
, mode
);
6881 /* If none of the bits in X are needed, return a zero. */
6882 if (! just_select
&& (nonzero
& mask
) == 0)
6885 /* If X is a CONST_INT, return a new one. Do this here since the
6886 test below will fail. */
6887 if (GET_CODE (x
) == CONST_INT
)
6889 if (SCALAR_INT_MODE_P (mode
))
6890 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6893 x
= GEN_INT (INTVAL (x
) & mask
);
6894 return gen_lowpart_common (mode
, x
);
6898 /* If X is narrower than MODE and we want all the bits in X's mode, just
6899 get X in the proper mode. */
6900 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6901 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6902 return gen_lowpart (mode
, x
);
6907 /* If X is a (clobber (const_int)), return it since we know we are
6908 generating something that won't match. */
6912 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6913 spanned the boundary of the MEM. If we are now masking so it is
6914 within that boundary, we don't need the USE any more. */
6915 if (! BITS_BIG_ENDIAN
6916 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6917 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6924 x
= expand_compound_operation (x
);
6925 if (GET_CODE (x
) != code
)
6926 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6930 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6931 || rtx_equal_p (reg
, get_last_value (x
))))
6936 if (subreg_lowpart_p (x
)
6937 /* We can ignore the effect of this SUBREG if it narrows the mode or
6938 if the constant masks to zero all the bits the mode doesn't
6940 && ((GET_MODE_SIZE (GET_MODE (x
))
6941 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6943 & GET_MODE_MASK (GET_MODE (x
))
6944 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6945 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6949 /* If this is an AND with a constant, convert it into an AND
6950 whose constant is the AND of that constant with MASK. If it
6951 remains an AND of MASK, delete it since it is redundant. */
6953 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6955 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6956 mask
& INTVAL (XEXP (x
, 1)));
6958 /* If X is still an AND, see if it is an AND with a mask that
6959 is just some low-order bits. If so, and it is MASK, we don't
6962 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6963 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6967 /* If it remains an AND, try making another AND with the bits
6968 in the mode mask that aren't in MASK turned on. If the
6969 constant in the AND is wide enough, this might make a
6970 cheaper constant. */
6972 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6973 && GET_MODE_MASK (GET_MODE (x
)) != mask
6974 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6976 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6977 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6978 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6981 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6982 number, sign extend it. */
6983 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6984 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6985 cval
|= (HOST_WIDE_INT
) -1 << width
;
6987 y
= simplify_gen_binary (AND
, GET_MODE (x
),
6988 XEXP (x
, 0), GEN_INT (cval
));
6989 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6999 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7000 low-order bits (as in an alignment operation) and FOO is already
7001 aligned to that boundary, mask C1 to that boundary as well.
7002 This may eliminate that PLUS and, later, the AND. */
7005 unsigned int width
= GET_MODE_BITSIZE (mode
);
7006 unsigned HOST_WIDE_INT smask
= mask
;
7008 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7009 number, sign extend it. */
7011 if (width
< HOST_BITS_PER_WIDE_INT
7012 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7013 smask
|= (HOST_WIDE_INT
) -1 << width
;
7015 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7016 && exact_log2 (- smask
) >= 0
7017 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
7018 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
7019 return force_to_mode (plus_constant (XEXP (x
, 0),
7020 (INTVAL (XEXP (x
, 1)) & smask
)),
7021 mode
, smask
, reg
, next_select
);
7024 /* ... fall through ... */
7027 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7028 most significant bit in MASK since carries from those bits will
7029 affect the bits we are interested in. */
7034 /* If X is (minus C Y) where C's least set bit is larger than any bit
7035 in the mask, then we may replace with (neg Y). */
7036 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7037 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
7038 & -INTVAL (XEXP (x
, 0))))
7041 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
7043 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7046 /* Similarly, if C contains every bit in the fuller_mask, then we may
7047 replace with (not Y). */
7048 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7049 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
7050 == INTVAL (XEXP (x
, 0))))
7052 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
7053 XEXP (x
, 1), GET_MODE (x
));
7054 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7062 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7063 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7064 operation which may be a bitfield extraction. Ensure that the
7065 constant we form is not wider than the mode of X. */
7067 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7068 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7069 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7070 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7071 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7072 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
7073 + floor_log2 (INTVAL (XEXP (x
, 1))))
7074 < GET_MODE_BITSIZE (GET_MODE (x
)))
7075 && (INTVAL (XEXP (x
, 1))
7076 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
7078 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
7079 << INTVAL (XEXP (XEXP (x
, 0), 1)));
7080 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
7081 XEXP (XEXP (x
, 0), 0), temp
);
7082 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
7083 XEXP (XEXP (x
, 0), 1));
7084 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7088 /* For most binary operations, just propagate into the operation and
7089 change the mode if we have an operation of that mode. */
7091 op0
= gen_lowpart (op_mode
,
7092 force_to_mode (XEXP (x
, 0), mode
, mask
,
7094 op1
= gen_lowpart (op_mode
,
7095 force_to_mode (XEXP (x
, 1), mode
, mask
,
7098 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7099 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
7103 /* For left shifts, do the same, but just for the first operand.
7104 However, we cannot do anything with shifts where we cannot
7105 guarantee that the counts are smaller than the size of the mode
7106 because such a count will have a different meaning in a
7109 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7110 && INTVAL (XEXP (x
, 1)) >= 0
7111 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7112 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7113 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7114 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7117 /* If the shift count is a constant and we can do arithmetic in
7118 the mode of the shift, refine which bits we need. Otherwise, use the
7119 conservative form of the mask. */
7120 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7121 && INTVAL (XEXP (x
, 1)) >= 0
7122 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7123 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7124 mask
>>= INTVAL (XEXP (x
, 1));
7128 op0
= gen_lowpart (op_mode
,
7129 force_to_mode (XEXP (x
, 0), op_mode
,
7130 mask
, reg
, next_select
));
7132 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7133 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7137 /* Here we can only do something if the shift count is a constant,
7138 this shift constant is valid for the host, and we can do arithmetic
7141 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7142 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7143 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7145 rtx inner
= XEXP (x
, 0);
7146 unsigned HOST_WIDE_INT inner_mask
;
7148 /* Select the mask of the bits we need for the shift operand. */
7149 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7151 /* We can only change the mode of the shift if we can do arithmetic
7152 in the mode of the shift and INNER_MASK is no wider than the
7153 width of X's mode. */
7154 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
7155 op_mode
= GET_MODE (x
);
7157 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7159 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7160 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7163 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7164 shift and AND produces only copies of the sign bit (C2 is one less
7165 than a power of two), we can do this with just a shift. */
7167 if (GET_CODE (x
) == LSHIFTRT
7168 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7169 /* The shift puts one of the sign bit copies in the least significant
7171 && ((INTVAL (XEXP (x
, 1))
7172 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7173 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7174 && exact_log2 (mask
+ 1) >= 0
7175 /* Number of bits left after the shift must be more than the mask
7177 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7178 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7179 /* Must be more sign bit copies than the mask needs. */
7180 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7181 >= exact_log2 (mask
+ 1)))
7182 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7183 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7184 - exact_log2 (mask
+ 1)));
7189 /* If we are just looking for the sign bit, we don't need this shift at
7190 all, even if it has a variable count. */
7191 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7192 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7193 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7194 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7196 /* If this is a shift by a constant, get a mask that contains those bits
7197 that are not copies of the sign bit. We then have two cases: If
7198 MASK only includes those bits, this can be a logical shift, which may
7199 allow simplifications. If MASK is a single-bit field not within
7200 those bits, we are requesting a copy of the sign bit and hence can
7201 shift the sign bit to the appropriate location. */
7203 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7204 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7208 /* If the considered data is wider than HOST_WIDE_INT, we can't
7209 represent a mask for all its bits in a single scalar.
7210 But we only care about the lower bits, so calculate these. */
7212 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7214 nonzero
= ~(HOST_WIDE_INT
) 0;
7216 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7217 is the number of bits a full-width mask would have set.
7218 We need only shift if these are fewer than nonzero can
7219 hold. If not, we must keep all bits set in nonzero. */
7221 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7222 < HOST_BITS_PER_WIDE_INT
)
7223 nonzero
>>= INTVAL (XEXP (x
, 1))
7224 + HOST_BITS_PER_WIDE_INT
7225 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7229 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7230 nonzero
>>= INTVAL (XEXP (x
, 1));
7233 if ((mask
& ~nonzero
) == 0
7234 || (i
= exact_log2 (mask
)) >= 0)
7236 x
= simplify_shift_const
7237 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7238 i
< 0 ? INTVAL (XEXP (x
, 1))
7239 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7241 if (GET_CODE (x
) != ASHIFTRT
)
7242 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7246 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7247 even if the shift count isn't a constant. */
7249 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
7250 XEXP (x
, 0), XEXP (x
, 1));
7254 /* If this is a zero- or sign-extension operation that just affects bits
7255 we don't care about, remove it. Be sure the call above returned
7256 something that is still a shift. */
7258 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7259 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7260 && INTVAL (XEXP (x
, 1)) >= 0
7261 && (INTVAL (XEXP (x
, 1))
7262 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7263 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7264 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7265 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7272 /* If the shift count is constant and we can do computations
7273 in the mode of X, compute where the bits we care about are.
7274 Otherwise, we can't do anything. Don't change the mode of
7275 the shift or propagate MODE into the shift, though. */
7276 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7277 && INTVAL (XEXP (x
, 1)) >= 0)
7279 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7280 GET_MODE (x
), GEN_INT (mask
),
7282 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7284 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7285 INTVAL (temp
), reg
, next_select
));
7290 /* If we just want the low-order bit, the NEG isn't needed since it
7291 won't change the low-order bit. */
7293 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7295 /* We need any bits less significant than the most significant bit in
7296 MASK since carries from those bits will affect the bits we are
7302 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7303 same as the XOR case above. Ensure that the constant we form is not
7304 wider than the mode of X. */
7306 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7307 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7308 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7309 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7310 < GET_MODE_BITSIZE (GET_MODE (x
)))
7311 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7313 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7315 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
7316 XEXP (XEXP (x
, 0), 0), temp
);
7317 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
7318 temp
, XEXP (XEXP (x
, 0), 1));
7320 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7323 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7324 use the full mask inside the NOT. */
7328 op0
= gen_lowpart (op_mode
,
7329 force_to_mode (XEXP (x
, 0), mode
, mask
,
7331 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7332 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7336 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7337 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7338 which is equal to STORE_FLAG_VALUE. */
7339 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7340 && GET_MODE (XEXP (x
, 0)) == mode
7341 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7342 && (nonzero_bits (XEXP (x
, 0), mode
)
7343 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7344 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7349 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7350 written in a narrower mode. We play it safe and do not do so. */
7353 gen_lowpart (GET_MODE (x
),
7354 force_to_mode (XEXP (x
, 1), mode
,
7355 mask
, reg
, next_select
)));
7357 gen_lowpart (GET_MODE (x
),
7358 force_to_mode (XEXP (x
, 2), mode
,
7359 mask
, reg
, next_select
)));
7366 /* Ensure we return a value of the proper mode. */
7367 return gen_lowpart (mode
, x
);
7370 /* Return nonzero if X is an expression that has one of two values depending on
7371 whether some other value is zero or nonzero. In that case, we return the
7372 value that is being tested, *PTRUE is set to the value if the rtx being
7373 returned has a nonzero value, and *PFALSE is set to the other alternative.
7375 If we return zero, we set *PTRUE and *PFALSE to X. */
7378 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7380 enum machine_mode mode
= GET_MODE (x
);
7381 enum rtx_code code
= GET_CODE (x
);
7382 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7383 unsigned HOST_WIDE_INT nz
;
7385 /* If we are comparing a value against zero, we are done. */
7386 if ((code
== NE
|| code
== EQ
)
7387 && XEXP (x
, 1) == const0_rtx
)
7389 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7390 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7394 /* If this is a unary operation whose operand has one of two values, apply
7395 our opcode to compute those values. */
7396 else if (UNARY_P (x
)
7397 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7399 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7400 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7401 GET_MODE (XEXP (x
, 0)));
7405 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7406 make can't possibly match and would suppress other optimizations. */
7407 else if (code
== COMPARE
)
7410 /* If this is a binary operation, see if either side has only one of two
7411 values. If either one does or if both do and they are conditional on
7412 the same value, compute the new true and false values. */
7413 else if (BINARY_P (x
))
7415 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7416 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7418 if ((cond0
!= 0 || cond1
!= 0)
7419 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7421 /* If if_then_else_cond returned zero, then true/false are the
7422 same rtl. We must copy one of them to prevent invalid rtl
7425 true0
= copy_rtx (true0
);
7426 else if (cond1
== 0)
7427 true1
= copy_rtx (true1
);
7429 if (COMPARISON_P (x
))
7431 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
7433 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
7438 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
7439 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
7442 return cond0
? cond0
: cond1
;
7445 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7446 operands is zero when the other is nonzero, and vice-versa,
7447 and STORE_FLAG_VALUE is 1 or -1. */
7449 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7450 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7452 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7454 rtx op0
= XEXP (XEXP (x
, 0), 1);
7455 rtx op1
= XEXP (XEXP (x
, 1), 1);
7457 cond0
= XEXP (XEXP (x
, 0), 0);
7458 cond1
= XEXP (XEXP (x
, 1), 0);
7460 if (COMPARISON_P (cond0
)
7461 && COMPARISON_P (cond1
)
7462 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
7463 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7464 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7465 || ((swap_condition (GET_CODE (cond0
))
7466 == reversed_comparison_code (cond1
, NULL
))
7467 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7468 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7469 && ! side_effects_p (x
))
7471 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7472 *pfalse
= simplify_gen_binary (MULT
, mode
,
7474 ? simplify_gen_unary (NEG
, mode
,
7482 /* Similarly for MULT, AND and UMIN, except that for these the result
7484 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7485 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7486 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7488 cond0
= XEXP (XEXP (x
, 0), 0);
7489 cond1
= XEXP (XEXP (x
, 1), 0);
7491 if (COMPARISON_P (cond0
)
7492 && COMPARISON_P (cond1
)
7493 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
7494 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7495 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7496 || ((swap_condition (GET_CODE (cond0
))
7497 == reversed_comparison_code (cond1
, NULL
))
7498 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7499 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7500 && ! side_effects_p (x
))
7502 *ptrue
= *pfalse
= const0_rtx
;
7508 else if (code
== IF_THEN_ELSE
)
7510 /* If we have IF_THEN_ELSE already, extract the condition and
7511 canonicalize it if it is NE or EQ. */
7512 cond0
= XEXP (x
, 0);
7513 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7514 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7515 return XEXP (cond0
, 0);
7516 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7518 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7519 return XEXP (cond0
, 0);
7525 /* If X is a SUBREG, we can narrow both the true and false values
7526 if the inner expression, if there is a condition. */
7527 else if (code
== SUBREG
7528 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7531 true0
= simplify_gen_subreg (mode
, true0
,
7532 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7533 false0
= simplify_gen_subreg (mode
, false0
,
7534 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7535 if (true0
&& false0
)
7543 /* If X is a constant, this isn't special and will cause confusions
7544 if we treat it as such. Likewise if it is equivalent to a constant. */
7545 else if (CONSTANT_P (x
)
7546 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7549 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7550 will be least confusing to the rest of the compiler. */
7551 else if (mode
== BImode
)
7553 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7557 /* If X is known to be either 0 or -1, those are the true and
7558 false values when testing X. */
7559 else if (x
== constm1_rtx
|| x
== const0_rtx
7560 || (mode
!= VOIDmode
7561 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7563 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7567 /* Likewise for 0 or a single bit. */
7568 else if (SCALAR_INT_MODE_P (mode
)
7569 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7570 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7572 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7576 /* Otherwise fail; show no condition with true and false values the same. */
7577 *ptrue
= *pfalse
= x
;
7581 /* Return the value of expression X given the fact that condition COND
7582 is known to be true when applied to REG as its first operand and VAL
7583 as its second. X is known to not be shared and so can be modified in
7586 We only handle the simplest cases, and specifically those cases that
7587 arise with IF_THEN_ELSE expressions. */
7590 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7592 enum rtx_code code
= GET_CODE (x
);
7597 if (side_effects_p (x
))
7600 /* If either operand of the condition is a floating point value,
7601 then we have to avoid collapsing an EQ comparison. */
7603 && rtx_equal_p (x
, reg
)
7604 && ! FLOAT_MODE_P (GET_MODE (x
))
7605 && ! FLOAT_MODE_P (GET_MODE (val
)))
7608 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7611 /* If X is (abs REG) and we know something about REG's relationship
7612 with zero, we may be able to simplify this. */
7614 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7617 case GE
: case GT
: case EQ
:
7620 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7622 GET_MODE (XEXP (x
, 0)));
7627 /* The only other cases we handle are MIN, MAX, and comparisons if the
7628 operands are the same as REG and VAL. */
7630 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
7632 if (rtx_equal_p (XEXP (x
, 0), val
))
7633 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7635 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7637 if (COMPARISON_P (x
))
7639 if (comparison_dominates_p (cond
, code
))
7640 return const_true_rtx
;
7642 code
= reversed_comparison_code (x
, NULL
);
7644 && comparison_dominates_p (cond
, code
))
7649 else if (code
== SMAX
|| code
== SMIN
7650 || code
== UMIN
|| code
== UMAX
)
7652 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7654 /* Do not reverse the condition when it is NE or EQ.
7655 This is because we cannot conclude anything about
7656 the value of 'SMAX (x, y)' when x is not equal to y,
7657 but we can when x equals y. */
7658 if ((code
== SMAX
|| code
== UMAX
)
7659 && ! (cond
== EQ
|| cond
== NE
))
7660 cond
= reverse_condition (cond
);
7665 return unsignedp
? x
: XEXP (x
, 1);
7667 return unsignedp
? x
: XEXP (x
, 0);
7669 return unsignedp
? XEXP (x
, 1) : x
;
7671 return unsignedp
? XEXP (x
, 0) : x
;
7678 else if (code
== SUBREG
)
7680 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7681 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7683 if (SUBREG_REG (x
) != r
)
7685 /* We must simplify subreg here, before we lose track of the
7686 original inner_mode. */
7687 new = simplify_subreg (GET_MODE (x
), r
,
7688 inner_mode
, SUBREG_BYTE (x
));
7692 SUBST (SUBREG_REG (x
), r
);
7697 /* We don't have to handle SIGN_EXTEND here, because even in the
7698 case of replacing something with a modeless CONST_INT, a
7699 CONST_INT is already (supposed to be) a valid sign extension for
7700 its narrower mode, which implies it's already properly
7701 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7702 story is different. */
7703 else if (code
== ZERO_EXTEND
)
7705 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7706 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7708 if (XEXP (x
, 0) != r
)
7710 /* We must simplify the zero_extend here, before we lose
7711 track of the original inner_mode. */
7712 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7717 SUBST (XEXP (x
, 0), r
);
7723 fmt
= GET_RTX_FORMAT (code
);
7724 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7727 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7728 else if (fmt
[i
] == 'E')
7729 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7730 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7737 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7738 assignment as a field assignment. */
7741 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7743 if (x
== y
|| rtx_equal_p (x
, y
))
7746 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7749 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7750 Note that all SUBREGs of MEM are paradoxical; otherwise they
7751 would have been rewritten. */
7752 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
7753 && MEM_P (SUBREG_REG (y
))
7754 && rtx_equal_p (SUBREG_REG (y
),
7755 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
7758 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
7759 && MEM_P (SUBREG_REG (x
))
7760 && rtx_equal_p (SUBREG_REG (x
),
7761 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
7764 /* We used to see if get_last_value of X and Y were the same but that's
7765 not correct. In one direction, we'll cause the assignment to have
7766 the wrong destination and in the case, we'll import a register into this
7767 insn that might have already have been dead. So fail if none of the
7768 above cases are true. */
7772 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7773 Return that assignment if so.
7775 We only handle the most common cases. */
7778 make_field_assignment (rtx x
)
7780 rtx dest
= SET_DEST (x
);
7781 rtx src
= SET_SRC (x
);
7786 unsigned HOST_WIDE_INT len
;
7788 enum machine_mode mode
;
7790 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7791 a clear of a one-bit field. We will have changed it to
7792 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7795 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7796 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7797 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7798 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7800 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7803 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7807 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7808 && subreg_lowpart_p (XEXP (src
, 0))
7809 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7810 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7811 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7812 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
7813 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7814 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7816 assign
= make_extraction (VOIDmode
, dest
, 0,
7817 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7820 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7824 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7826 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7827 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7828 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7830 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7833 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7837 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7838 SRC is an AND with all bits of that field set, then we can discard
7840 if (GET_CODE (dest
) == ZERO_EXTRACT
7841 && GET_CODE (XEXP (dest
, 1)) == CONST_INT
7842 && GET_CODE (src
) == AND
7843 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
7845 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
7846 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
7847 unsigned HOST_WIDE_INT ze_mask
;
7849 if (width
>= HOST_BITS_PER_WIDE_INT
)
7852 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
7854 /* Complete overlap. We can remove the source AND. */
7855 if ((and_mask
& ze_mask
) == ze_mask
)
7856 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
7858 /* Partial overlap. We can reduce the source AND. */
7859 if ((and_mask
& ze_mask
) != and_mask
)
7861 mode
= GET_MODE (src
);
7862 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
7863 gen_int_mode (and_mask
& ze_mask
, mode
));
7864 return gen_rtx_SET (VOIDmode
, dest
, src
);
7868 /* The other case we handle is assignments into a constant-position
7869 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7870 a mask that has all one bits except for a group of zero bits and
7871 OTHER is known to have zeros where C1 has ones, this is such an
7872 assignment. Compute the position and length from C1. Shift OTHER
7873 to the appropriate position, force it to the required mode, and
7874 make the extraction. Check for the AND in both operands. */
7876 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7879 rhs
= expand_compound_operation (XEXP (src
, 0));
7880 lhs
= expand_compound_operation (XEXP (src
, 1));
7882 if (GET_CODE (rhs
) == AND
7883 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7884 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7885 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7886 else if (GET_CODE (lhs
) == AND
7887 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7888 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7889 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7893 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7894 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7895 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7896 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7899 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7903 /* The mode to use for the source is the mode of the assignment, or of
7904 what is inside a possible STRICT_LOW_PART. */
7905 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7906 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7908 /* Shift OTHER right POS places and make it the source, restricting it
7909 to the proper length and mode. */
7911 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7912 GET_MODE (src
), other
, pos
),
7914 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7915 ? ~(unsigned HOST_WIDE_INT
) 0
7916 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7919 /* If SRC is masked by an AND that does not make a difference in
7920 the value being stored, strip it. */
7921 if (GET_CODE (assign
) == ZERO_EXTRACT
7922 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
7923 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
7924 && GET_CODE (src
) == AND
7925 && GET_CODE (XEXP (src
, 1)) == CONST_INT
7926 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
7927 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
7928 src
= XEXP (src
, 0);
7930 return gen_rtx_SET (VOIDmode
, assign
, src
);
7933 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7937 apply_distributive_law (rtx x
)
7939 enum rtx_code code
= GET_CODE (x
);
7940 enum rtx_code inner_code
;
7941 rtx lhs
, rhs
, other
;
7944 /* Distributivity is not true for floating point as it can change the
7945 value. So we don't do it unless -funsafe-math-optimizations. */
7946 if (FLOAT_MODE_P (GET_MODE (x
))
7947 && ! flag_unsafe_math_optimizations
)
7950 /* The outer operation can only be one of the following: */
7951 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7952 && code
!= PLUS
&& code
!= MINUS
)
7958 /* If either operand is a primitive we can't do anything, so get out
7960 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
7963 lhs
= expand_compound_operation (lhs
);
7964 rhs
= expand_compound_operation (rhs
);
7965 inner_code
= GET_CODE (lhs
);
7966 if (inner_code
!= GET_CODE (rhs
))
7969 /* See if the inner and outer operations distribute. */
7976 /* These all distribute except over PLUS. */
7977 if (code
== PLUS
|| code
== MINUS
)
7982 if (code
!= PLUS
&& code
!= MINUS
)
7987 /* This is also a multiply, so it distributes over everything. */
7991 /* Non-paradoxical SUBREGs distributes over all operations, provided
7992 the inner modes and byte offsets are the same, this is an extraction
7993 of a low-order part, we don't convert an fp operation to int or
7994 vice versa, and we would not be converting a single-word
7995 operation into a multi-word operation. The latter test is not
7996 required, but it prevents generating unneeded multi-word operations.
7997 Some of the previous tests are redundant given the latter test, but
7998 are retained because they are required for correctness.
8000 We produce the result slightly differently in this case. */
8002 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
8003 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
8004 || ! subreg_lowpart_p (lhs
)
8005 || (GET_MODE_CLASS (GET_MODE (lhs
))
8006 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
8007 || (GET_MODE_SIZE (GET_MODE (lhs
))
8008 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
8009 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
8012 tem
= simplify_gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
8013 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
8014 return gen_lowpart (GET_MODE (x
), tem
);
8020 /* Set LHS and RHS to the inner operands (A and B in the example
8021 above) and set OTHER to the common operand (C in the example).
8022 There is only one way to do this unless the inner operation is
8024 if (COMMUTATIVE_ARITH_P (lhs
)
8025 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
8026 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
8027 else if (COMMUTATIVE_ARITH_P (lhs
)
8028 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
8029 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
8030 else if (COMMUTATIVE_ARITH_P (lhs
)
8031 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
8032 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
8033 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
8034 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
8038 /* Form the new inner operation, seeing if it simplifies first. */
8039 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
8041 /* There is one exception to the general way of distributing:
8042 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8043 if (code
== XOR
&& inner_code
== IOR
)
8046 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
8049 /* We may be able to continuing distributing the result, so call
8050 ourselves recursively on the inner operation before forming the
8051 outer operation, which we return. */
8052 return simplify_gen_binary (inner_code
, GET_MODE (x
),
8053 apply_distributive_law (tem
), other
);
8056 /* See if X is of the form (* (+ A B) C), and if so convert to
8057 (+ (* A C) (* B C)) and try to simplify.
8059 Most of the time, this results in no change. However, if some of
8060 the operands are the same or inverses of each other, simplifications
8063 For example, (and (ior A B) (not B)) can occur as the result of
8064 expanding a bit field assignment. When we apply the distributive
8065 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8066 which then simplifies to (and (A (not B))).
8068 Note that no checks happen on the validity of applying the inverse
8069 distributive law. This is pointless since we can do it in the
8070 few places where this routine is called.
8072 N is the index of the term that is decomposed (the arithmetic operation,
8073 i.e. (+ A B) in the first example above). !N is the index of the term that
8074 is distributed, i.e. of C in the first example above. */
8076 distribute_and_simplify_rtx (rtx x
, int n
)
8078 enum machine_mode mode
;
8079 enum rtx_code outer_code
, inner_code
;
8080 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
8082 decomposed
= XEXP (x
, n
);
8083 if (!ARITHMETIC_P (decomposed
))
8086 mode
= GET_MODE (x
);
8087 outer_code
= GET_CODE (x
);
8088 distributed
= XEXP (x
, !n
);
8090 inner_code
= GET_CODE (decomposed
);
8091 inner_op0
= XEXP (decomposed
, 0);
8092 inner_op1
= XEXP (decomposed
, 1);
8094 /* Special case (and (xor B C) (not A)), which is equivalent to
8095 (xor (ior A B) (ior A C)) */
8096 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
8098 distributed
= XEXP (distributed
, 0);
8104 /* Distribute the second term. */
8105 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
8106 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
8110 /* Distribute the first term. */
8111 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
8112 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
8115 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
8117 if (GET_CODE (tmp
) != outer_code
8118 && rtx_cost (tmp
, SET
) < rtx_cost (x
, SET
))
8124 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8127 Return an equivalent form, if different from X. Otherwise, return X. If
8128 X is zero, we are to always construct the equivalent form. */
8131 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
8132 unsigned HOST_WIDE_INT constop
)
8134 unsigned HOST_WIDE_INT nonzero
;
8137 /* Simplify VAROP knowing that we will be only looking at some of the
8140 Note by passing in CONSTOP, we guarantee that the bits not set in
8141 CONSTOP are not significant and will never be examined. We must
8142 ensure that is the case by explicitly masking out those bits
8143 before returning. */
8144 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
8146 /* If VAROP is a CLOBBER, we will fail so return it. */
8147 if (GET_CODE (varop
) == CLOBBER
)
8150 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8151 to VAROP and return the new constant. */
8152 if (GET_CODE (varop
) == CONST_INT
)
8153 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
8155 /* See what bits may be nonzero in VAROP. Unlike the general case of
8156 a call to nonzero_bits, here we don't care about bits outside
8159 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
8161 /* Turn off all bits in the constant that are known to already be zero.
8162 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8163 which is tested below. */
8167 /* If we don't have any bits left, return zero. */
8171 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8172 a power of two, we can replace this with an ASHIFT. */
8173 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
8174 && (i
= exact_log2 (constop
)) >= 0)
8175 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
8177 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8178 or XOR, then try to apply the distributive law. This may eliminate
8179 operations if either branch can be simplified because of the AND.
8180 It may also make some cases more complex, but those cases probably
8181 won't match a pattern either with or without this. */
8183 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
8187 apply_distributive_law
8188 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
8189 simplify_and_const_int (NULL_RTX
,
8193 simplify_and_const_int (NULL_RTX
,
8198 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8199 the AND and see if one of the operands simplifies to zero. If so, we
8200 may eliminate it. */
8202 if (GET_CODE (varop
) == PLUS
8203 && exact_log2 (constop
+ 1) >= 0)
8207 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
8208 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
8209 if (o0
== const0_rtx
)
8211 if (o1
== const0_rtx
)
8215 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8216 if we already had one (just check for the simplest cases). */
8217 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
8218 && GET_MODE (XEXP (x
, 0)) == mode
8219 && SUBREG_REG (XEXP (x
, 0)) == varop
)
8220 varop
= XEXP (x
, 0);
8222 varop
= gen_lowpart (mode
, varop
);
8224 /* If we can't make the SUBREG, try to return what we were given. */
8225 if (GET_CODE (varop
) == CLOBBER
)
8226 return x
? x
: varop
;
8228 /* If we are only masking insignificant bits, return VAROP. */
8229 if (constop
== nonzero
)
8233 /* Otherwise, return an AND. */
8234 constop
= trunc_int_for_mode (constop
, mode
);
8235 /* See how much, if any, of X we can use. */
8236 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
8237 x
= simplify_gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
8241 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8242 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
8243 SUBST (XEXP (x
, 1), GEN_INT (constop
));
8245 SUBST (XEXP (x
, 0), varop
);
8252 /* Given a REG, X, compute which bits in X can be nonzero.
8253 We don't care about bits outside of those defined in MODE.
8255 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8256 a shift, AND, or zero_extract, we can do better. */
8259 reg_nonzero_bits_for_combine (rtx x
, enum machine_mode mode
,
8260 rtx known_x ATTRIBUTE_UNUSED
,
8261 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
8262 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
8263 unsigned HOST_WIDE_INT
*nonzero
)
8267 /* If X is a register whose nonzero bits value is current, use it.
8268 Otherwise, if X is a register whose value we can find, use that
8269 value. Otherwise, use the previously-computed global nonzero bits
8270 for this register. */
8272 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8273 && (reg_stat
[REGNO (x
)].last_set_mode
== mode
8274 || (GET_MODE_CLASS (reg_stat
[REGNO (x
)].last_set_mode
) == MODE_INT
8275 && GET_MODE_CLASS (mode
) == MODE_INT
))
8276 && (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8277 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8278 && REG_N_SETS (REGNO (x
)) == 1
8279 && ! REGNO_REG_SET_P
8280 (ENTRY_BLOCK_PTR
->next_bb
->il
.rtl
->global_live_at_start
,
8282 && INSN_CUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_cuid
)
8284 *nonzero
&= reg_stat
[REGNO (x
)].last_set_nonzero_bits
;
8288 tem
= get_last_value (x
);
8292 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8293 /* If X is narrower than MODE and TEM is a non-negative
8294 constant that would appear negative in the mode of X,
8295 sign-extend it for use in reg_nonzero_bits because some
8296 machines (maybe most) will actually do the sign-extension
8297 and this is the conservative approach.
8299 ??? For 2.5, try to tighten up the MD files in this regard
8300 instead of this kludge. */
8302 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
)
8303 && GET_CODE (tem
) == CONST_INT
8305 && 0 != (INTVAL (tem
)
8306 & ((HOST_WIDE_INT
) 1
8307 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8308 tem
= GEN_INT (INTVAL (tem
)
8309 | ((HOST_WIDE_INT
) (-1)
8310 << GET_MODE_BITSIZE (GET_MODE (x
))));
8314 else if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].nonzero_bits
)
8316 unsigned HOST_WIDE_INT mask
= reg_stat
[REGNO (x
)].nonzero_bits
;
8318 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
))
8319 /* We don't know anything about the upper bits. */
8320 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8327 /* Return the number of bits at the high-order end of X that are known to
8328 be equal to the sign bit. X will be used in mode MODE; if MODE is
8329 VOIDmode, X will be used in its own mode. The returned value will always
8330 be between 1 and the number of bits in MODE. */
8333 reg_num_sign_bit_copies_for_combine (rtx x
, enum machine_mode mode
,
8334 rtx known_x ATTRIBUTE_UNUSED
,
8335 enum machine_mode known_mode
8337 unsigned int known_ret ATTRIBUTE_UNUSED
,
8338 unsigned int *result
)
8342 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8343 && reg_stat
[REGNO (x
)].last_set_mode
== mode
8344 && (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8345 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8346 && REG_N_SETS (REGNO (x
)) == 1
8347 && ! REGNO_REG_SET_P
8348 (ENTRY_BLOCK_PTR
->next_bb
->il
.rtl
->global_live_at_start
,
8350 && INSN_CUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_cuid
)
8352 *result
= reg_stat
[REGNO (x
)].last_set_sign_bit_copies
;
8356 tem
= get_last_value (x
);
8360 if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].sign_bit_copies
!= 0
8361 && GET_MODE_BITSIZE (GET_MODE (x
)) == GET_MODE_BITSIZE (mode
))
8362 *result
= reg_stat
[REGNO (x
)].sign_bit_copies
;
8367 /* Return the number of "extended" bits there are in X, when interpreted
8368 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8369 unsigned quantities, this is the number of high-order zero bits.
8370 For signed quantities, this is the number of copies of the sign bit
8371 minus 1. In both case, this function returns the number of "spare"
8372 bits. For example, if two quantities for which this function returns
8373 at least 1 are added, the addition is known not to overflow.
8375 This function will always return 0 unless called during combine, which
8376 implies that it must be called from a define_split. */
8379 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
8381 if (nonzero_sign_valid
== 0)
8385 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8386 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8387 - floor_log2 (nonzero_bits (x
, mode
)))
8389 : num_sign_bit_copies (x
, mode
) - 1);
8392 /* This function is called from `simplify_shift_const' to merge two
8393 outer operations. Specifically, we have already found that we need
8394 to perform operation *POP0 with constant *PCONST0 at the outermost
8395 position. We would now like to also perform OP1 with constant CONST1
8396 (with *POP0 being done last).
8398 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8399 the resulting operation. *PCOMP_P is set to 1 if we would need to
8400 complement the innermost operand, otherwise it is unchanged.
8402 MODE is the mode in which the operation will be done. No bits outside
8403 the width of this mode matter. It is assumed that the width of this mode
8404 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8406 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8407 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8408 result is simply *PCONST0.
8410 If the resulting operation cannot be expressed as one operation, we
8411 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8414 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
8416 enum rtx_code op0
= *pop0
;
8417 HOST_WIDE_INT const0
= *pconst0
;
8419 const0
&= GET_MODE_MASK (mode
);
8420 const1
&= GET_MODE_MASK (mode
);
8422 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8426 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8429 if (op1
== UNKNOWN
|| op0
== SET
)
8432 else if (op0
== UNKNOWN
)
8433 op0
= op1
, const0
= const1
;
8435 else if (op0
== op1
)
8459 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8460 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8463 /* If the two constants aren't the same, we can't do anything. The
8464 remaining six cases can all be done. */
8465 else if (const0
!= const1
)
8473 /* (a & b) | b == b */
8475 else /* op1 == XOR */
8476 /* (a ^ b) | b == a | b */
8482 /* (a & b) ^ b == (~a) & b */
8483 op0
= AND
, *pcomp_p
= 1;
8484 else /* op1 == IOR */
8485 /* (a | b) ^ b == a & ~b */
8486 op0
= AND
, const0
= ~const0
;
8491 /* (a | b) & b == b */
8493 else /* op1 == XOR */
8494 /* (a ^ b) & b) == (~a) & b */
8501 /* Check for NO-OP cases. */
8502 const0
&= GET_MODE_MASK (mode
);
8504 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8506 else if (const0
== 0 && op0
== AND
)
8508 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8512 /* ??? Slightly redundant with the above mask, but not entirely.
8513 Moving this above means we'd have to sign-extend the mode mask
8514 for the final test. */
8515 const0
= trunc_int_for_mode (const0
, mode
);
8523 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8524 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
8525 that we started with.
8527 The shift is normally computed in the widest mode we find in VAROP, as
8528 long as it isn't a different number of words than RESULT_MODE. Exceptions
8529 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8532 simplify_shift_const (rtx x
, enum rtx_code code
,
8533 enum machine_mode result_mode
, rtx varop
,
8536 enum rtx_code orig_code
= code
;
8539 enum machine_mode mode
= result_mode
;
8540 enum machine_mode shift_mode
, tmode
;
8541 unsigned int mode_words
8542 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8543 /* We form (outer_op (code varop count) (outer_const)). */
8544 enum rtx_code outer_op
= UNKNOWN
;
8545 HOST_WIDE_INT outer_const
= 0;
8547 int complement_p
= 0;
8550 /* Make sure and truncate the "natural" shift on the way in. We don't
8551 want to do this inside the loop as it makes it more difficult to
8553 if (SHIFT_COUNT_TRUNCATED
)
8554 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
8556 /* If we were given an invalid count, don't do anything except exactly
8557 what was requested. */
8559 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
8564 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
8569 /* Unless one of the branches of the `if' in this loop does a `continue',
8570 we will `break' the loop after the `if'. */
8574 /* If we have an operand of (clobber (const_int 0)), just return that
8576 if (GET_CODE (varop
) == CLOBBER
)
8579 /* If we discovered we had to complement VAROP, leave. Making a NOT
8580 here would cause an infinite loop. */
8584 /* Convert ROTATERT to ROTATE. */
8585 if (code
== ROTATERT
)
8587 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
8589 if (VECTOR_MODE_P (result_mode
))
8590 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
8592 count
= bitsize
- count
;
8595 /* We need to determine what mode we will do the shift in. If the
8596 shift is a right shift or a ROTATE, we must always do it in the mode
8597 it was originally done in. Otherwise, we can do it in MODE, the
8598 widest mode encountered. */
8600 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8601 ? result_mode
: mode
);
8603 /* Handle cases where the count is greater than the size of the mode
8604 minus 1. For ASHIFT, use the size minus one as the count (this can
8605 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8606 take the count modulo the size. For other shifts, the result is
8609 Since these shifts are being produced by the compiler by combining
8610 multiple operations, each of which are defined, we know what the
8611 result is supposed to be. */
8613 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
8615 if (code
== ASHIFTRT
)
8616 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8617 else if (code
== ROTATE
|| code
== ROTATERT
)
8618 count
%= GET_MODE_BITSIZE (shift_mode
);
8621 /* We can't simply return zero because there may be an
8629 /* An arithmetic right shift of a quantity known to be -1 or 0
8631 if (code
== ASHIFTRT
8632 && (num_sign_bit_copies (varop
, shift_mode
)
8633 == GET_MODE_BITSIZE (shift_mode
)))
8639 /* If we are doing an arithmetic right shift and discarding all but
8640 the sign bit copies, this is equivalent to doing a shift by the
8641 bitsize minus one. Convert it into that shift because it will often
8642 allow other simplifications. */
8644 if (code
== ASHIFTRT
8645 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
8646 >= GET_MODE_BITSIZE (shift_mode
)))
8647 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8649 /* We simplify the tests below and elsewhere by converting
8650 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8651 `make_compound_operation' will convert it to an ASHIFTRT for
8652 those machines (such as VAX) that don't have an LSHIFTRT. */
8653 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8655 && ((nonzero_bits (varop
, shift_mode
)
8656 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
8660 if (code
== LSHIFTRT
8661 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8662 && !(nonzero_bits (varop
, shift_mode
) >> count
))
8665 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8666 && !((nonzero_bits (varop
, shift_mode
) << count
)
8667 & GET_MODE_MASK (shift_mode
)))
8670 switch (GET_CODE (varop
))
8676 new = expand_compound_operation (varop
);
8685 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8686 minus the width of a smaller mode, we can do this with a
8687 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8688 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8689 && ! mode_dependent_address_p (XEXP (varop
, 0))
8690 && ! MEM_VOLATILE_P (varop
)
8691 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8692 MODE_INT
, 1)) != BLKmode
)
8694 new = adjust_address_nv (varop
, tmode
,
8695 BYTES_BIG_ENDIAN
? 0
8696 : count
/ BITS_PER_UNIT
);
8698 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8699 : ZERO_EXTEND
, mode
, new);
8706 /* Similar to the case above, except that we can only do this if
8707 the resulting mode is the same as that of the underlying
8708 MEM and adjust the address depending on the *bits* endianness
8709 because of the way that bit-field extract insns are defined. */
8710 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8711 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8712 MODE_INT
, 1)) != BLKmode
8713 && tmode
== GET_MODE (XEXP (varop
, 0)))
8715 if (BITS_BIG_ENDIAN
)
8716 new = XEXP (varop
, 0);
8719 new = copy_rtx (XEXP (varop
, 0));
8720 SUBST (XEXP (new, 0),
8721 plus_constant (XEXP (new, 0),
8722 count
/ BITS_PER_UNIT
));
8725 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8726 : ZERO_EXTEND
, mode
, new);
8733 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8734 the same number of words as what we've seen so far. Then store
8735 the widest mode in MODE. */
8736 if (subreg_lowpart_p (varop
)
8737 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8738 > GET_MODE_SIZE (GET_MODE (varop
)))
8739 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8740 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
8743 varop
= SUBREG_REG (varop
);
8744 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
8745 mode
= GET_MODE (varop
);
8751 /* Some machines use MULT instead of ASHIFT because MULT
8752 is cheaper. But it is still better on those machines to
8753 merge two shifts into one. */
8754 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8755 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8758 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
8760 GEN_INT (exact_log2 (
8761 INTVAL (XEXP (varop
, 1)))));
8767 /* Similar, for when divides are cheaper. */
8768 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8769 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8772 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
8774 GEN_INT (exact_log2 (
8775 INTVAL (XEXP (varop
, 1)))));
8781 /* If we are extracting just the sign bit of an arithmetic
8782 right shift, that shift is not needed. However, the sign
8783 bit of a wider mode may be different from what would be
8784 interpreted as the sign bit in a narrower mode, so, if
8785 the result is narrower, don't discard the shift. */
8786 if (code
== LSHIFTRT
8787 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
8788 && (GET_MODE_BITSIZE (result_mode
)
8789 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
8791 varop
= XEXP (varop
, 0);
8795 /* ... fall through ... */
8800 /* Here we have two nested shifts. The result is usually the
8801 AND of a new shift with a mask. We compute the result below. */
8802 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8803 && INTVAL (XEXP (varop
, 1)) >= 0
8804 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
8805 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8806 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8808 enum rtx_code first_code
= GET_CODE (varop
);
8809 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
8810 unsigned HOST_WIDE_INT mask
;
8813 /* We have one common special case. We can't do any merging if
8814 the inner code is an ASHIFTRT of a smaller mode. However, if
8815 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8816 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8817 we can convert it to
8818 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8819 This simplifies certain SIGN_EXTEND operations. */
8820 if (code
== ASHIFT
&& first_code
== ASHIFTRT
8821 && count
== (unsigned int)
8822 (GET_MODE_BITSIZE (result_mode
)
8823 - GET_MODE_BITSIZE (GET_MODE (varop
))))
8825 /* C3 has the low-order C1 bits zero. */
8827 mask
= (GET_MODE_MASK (mode
)
8828 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
8830 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
8831 XEXP (varop
, 0), mask
);
8832 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
8834 count
= first_count
;
8839 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8840 than C1 high-order bits equal to the sign bit, we can convert
8841 this to either an ASHIFT or an ASHIFTRT depending on the
8844 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8846 if (code
== ASHIFTRT
&& first_code
== ASHIFT
8847 && GET_MODE (varop
) == shift_mode
8848 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
8851 varop
= XEXP (varop
, 0);
8853 signed_count
= count
- first_count
;
8854 if (signed_count
< 0)
8855 count
= -signed_count
, code
= ASHIFT
;
8857 count
= signed_count
;
8862 /* There are some cases we can't do. If CODE is ASHIFTRT,
8863 we can only do this if FIRST_CODE is also ASHIFTRT.
8865 We can't do the case when CODE is ROTATE and FIRST_CODE is
8868 If the mode of this shift is not the mode of the outer shift,
8869 we can't do this if either shift is a right shift or ROTATE.
8871 Finally, we can't do any of these if the mode is too wide
8872 unless the codes are the same.
8874 Handle the case where the shift codes are the same
8877 if (code
== first_code
)
8879 if (GET_MODE (varop
) != result_mode
8880 && (code
== ASHIFTRT
|| code
== LSHIFTRT
8884 count
+= first_count
;
8885 varop
= XEXP (varop
, 0);
8889 if (code
== ASHIFTRT
8890 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
8891 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
8892 || (GET_MODE (varop
) != result_mode
8893 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
8894 || first_code
== ROTATE
8895 || code
== ROTATE
)))
8898 /* To compute the mask to apply after the shift, shift the
8899 nonzero bits of the inner shift the same way the
8900 outer shift will. */
8902 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
8905 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
8908 /* Give up if we can't compute an outer operation to use. */
8910 || GET_CODE (mask_rtx
) != CONST_INT
8911 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
8913 result_mode
, &complement_p
))
8916 /* If the shifts are in the same direction, we add the
8917 counts. Otherwise, we subtract them. */
8918 signed_count
= count
;
8919 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8920 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
8921 signed_count
+= first_count
;
8923 signed_count
-= first_count
;
8925 /* If COUNT is positive, the new shift is usually CODE,
8926 except for the two exceptions below, in which case it is
8927 FIRST_CODE. If the count is negative, FIRST_CODE should
8929 if (signed_count
> 0
8930 && ((first_code
== ROTATE
&& code
== ASHIFT
)
8931 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
8932 code
= first_code
, count
= signed_count
;
8933 else if (signed_count
< 0)
8934 code
= first_code
, count
= -signed_count
;
8936 count
= signed_count
;
8938 varop
= XEXP (varop
, 0);
8942 /* If we have (A << B << C) for any shift, we can convert this to
8943 (A << C << B). This wins if A is a constant. Only try this if
8944 B is not a constant. */
8946 else if (GET_CODE (varop
) == code
8947 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
8949 = simplify_binary_operation (code
, mode
,
8953 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
8960 /* Make this fit the case below. */
8961 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
8962 GEN_INT (GET_MODE_MASK (mode
)));
8968 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8969 with C the size of VAROP - 1 and the shift is logical if
8970 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8971 we have an (le X 0) operation. If we have an arithmetic shift
8972 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8973 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8975 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
8976 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
8977 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8978 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
8979 && count
== (unsigned int)
8980 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
8981 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
8984 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
8987 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
8988 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
8993 /* If we have (shift (logical)), move the logical to the outside
8994 to allow it to possibly combine with another logical and the
8995 shift to combine with another shift. This also canonicalizes to
8996 what a ZERO_EXTRACT looks like. Also, some machines have
8997 (and (shift)) insns. */
8999 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9000 /* We can't do this if we have (ashiftrt (xor)) and the
9001 constant has its sign bit set in shift_mode. */
9002 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9003 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9005 && (new = simplify_binary_operation (code
, result_mode
,
9007 GEN_INT (count
))) != 0
9008 && GET_CODE (new) == CONST_INT
9009 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9010 INTVAL (new), result_mode
, &complement_p
))
9012 varop
= XEXP (varop
, 0);
9016 /* If we can't do that, try to simplify the shift in each arm of the
9017 logical expression, make a new logical expression, and apply
9018 the inverse distributive law. This also can't be done
9019 for some (ashiftrt (xor)). */
9020 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9021 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9022 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9025 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9026 XEXP (varop
, 0), count
);
9027 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9028 XEXP (varop
, 1), count
);
9030 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
9032 varop
= apply_distributive_law (varop
);
9040 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9041 says that the sign bit can be tested, FOO has mode MODE, C is
9042 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9043 that may be nonzero. */
9044 if (code
== LSHIFTRT
9045 && XEXP (varop
, 1) == const0_rtx
9046 && GET_MODE (XEXP (varop
, 0)) == result_mode
9047 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9048 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9049 && ((STORE_FLAG_VALUE
9050 & ((HOST_WIDE_INT
) 1
9051 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9052 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9053 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9054 (HOST_WIDE_INT
) 1, result_mode
,
9057 varop
= XEXP (varop
, 0);
9064 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9065 than the number of bits in the mode is equivalent to A. */
9066 if (code
== LSHIFTRT
9067 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9068 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9070 varop
= XEXP (varop
, 0);
9075 /* NEG commutes with ASHIFT since it is multiplication. Move the
9076 NEG outside to allow shifts to combine. */
9078 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9079 (HOST_WIDE_INT
) 0, result_mode
,
9082 varop
= XEXP (varop
, 0);
9088 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9089 is one less than the number of bits in the mode is
9090 equivalent to (xor A 1). */
9091 if (code
== LSHIFTRT
9092 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9093 && XEXP (varop
, 1) == constm1_rtx
9094 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9095 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9096 (HOST_WIDE_INT
) 1, result_mode
,
9100 varop
= XEXP (varop
, 0);
9104 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9105 that might be nonzero in BAR are those being shifted out and those
9106 bits are known zero in FOO, we can replace the PLUS with FOO.
9107 Similarly in the other operand order. This code occurs when
9108 we are computing the size of a variable-size array. */
9110 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9111 && count
< HOST_BITS_PER_WIDE_INT
9112 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9113 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9114 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9116 varop
= XEXP (varop
, 0);
9119 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9120 && count
< HOST_BITS_PER_WIDE_INT
9121 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9122 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9124 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9125 & nonzero_bits (XEXP (varop
, 1),
9128 varop
= XEXP (varop
, 1);
9132 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9134 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9135 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9137 GEN_INT (count
))) != 0
9138 && GET_CODE (new) == CONST_INT
9139 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9140 INTVAL (new), result_mode
, &complement_p
))
9142 varop
= XEXP (varop
, 0);
9146 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9147 signbit', and attempt to change the PLUS to an XOR and move it to
9148 the outer operation as is done above in the AND/IOR/XOR case
9149 leg for shift(logical). See details in logical handling above
9150 for reasoning in doing so. */
9151 if (code
== LSHIFTRT
9152 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9153 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
9154 && (new = simplify_binary_operation (code
, result_mode
,
9156 GEN_INT (count
))) != 0
9157 && GET_CODE (new) == CONST_INT
9158 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9159 INTVAL (new), result_mode
, &complement_p
))
9161 varop
= XEXP (varop
, 0);
9168 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9169 with C the size of VAROP - 1 and the shift is logical if
9170 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9171 we have a (gt X 0) operation. If the shift is arithmetic with
9172 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9173 we have a (neg (gt X 0)) operation. */
9175 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9176 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9177 && count
== (unsigned int)
9178 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9179 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9180 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9181 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9183 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9186 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9189 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9190 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9197 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9198 if the truncate does not affect the value. */
9199 if (code
== LSHIFTRT
9200 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9201 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9202 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9203 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9204 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9206 rtx varop_inner
= XEXP (varop
, 0);
9209 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9210 XEXP (varop_inner
, 0),
9212 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9213 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9226 /* We need to determine what mode to do the shift in. If the shift is
9227 a right shift or ROTATE, we must always do it in the mode it was
9228 originally done in. Otherwise, we can do it in MODE, the widest mode
9229 encountered. The code we care about is that of the shift that will
9230 actually be done, not the shift that was originally requested. */
9232 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9233 ? result_mode
: mode
);
9235 /* We have now finished analyzing the shift. The result should be
9236 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9237 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9238 to the result of the shift. OUTER_CONST is the relevant constant,
9239 but we must turn off all bits turned off in the shift.
9241 If we were passed a value for X, see if we can use any pieces of
9242 it. If not, make new rtx. */
9244 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == RTX_BIN_ARITH
9245 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9246 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9247 const_rtx
= XEXP (x
, 1);
9249 const_rtx
= GEN_INT (count
);
9251 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9252 && GET_MODE (XEXP (x
, 0)) == shift_mode
9253 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9254 varop
= XEXP (x
, 0);
9255 else if (GET_MODE (varop
) != shift_mode
)
9256 varop
= gen_lowpart (shift_mode
, varop
);
9258 /* If we can't make the SUBREG, try to return what we were given. */
9259 if (GET_CODE (varop
) == CLOBBER
)
9260 return x
? x
: varop
;
9262 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9266 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9268 /* If we have an outer operation and we just made a shift, it is
9269 possible that we could have simplified the shift were it not
9270 for the outer operation. So try to do the simplification
9273 if (outer_op
!= UNKNOWN
&& GET_CODE (x
) == code
9274 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9275 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9276 INTVAL (XEXP (x
, 1)));
9278 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9279 turn off all the bits that the shift would have turned off. */
9280 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9281 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9282 GET_MODE_MASK (result_mode
) >> orig_count
);
9284 /* Do the remainder of the processing in RESULT_MODE. */
9285 x
= gen_lowpart (result_mode
, x
);
9287 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9290 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9292 if (outer_op
!= UNKNOWN
)
9294 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9295 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9297 if (outer_op
== AND
)
9298 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9299 else if (outer_op
== SET
)
9300 /* This means that we have determined that the result is
9301 equivalent to a constant. This should be rare. */
9302 x
= GEN_INT (outer_const
);
9303 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
9304 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9306 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
9307 GEN_INT (outer_const
));
9313 /* Like recog, but we receive the address of a pointer to a new pattern.
9314 We try to match the rtx that the pointer points to.
9315 If that fails, we may try to modify or replace the pattern,
9316 storing the replacement into the same pointer object.
9318 Modifications include deletion or addition of CLOBBERs.
9320 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9321 the CLOBBERs are placed.
9323 The value is the final insn code from the pattern ultimately matched,
9327 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9330 int insn_code_number
;
9331 int num_clobbers_to_add
= 0;
9334 rtx old_notes
, old_pat
;
9336 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9337 we use to indicate that something didn't match. If we find such a
9338 thing, force rejection. */
9339 if (GET_CODE (pat
) == PARALLEL
)
9340 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9341 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9342 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9345 old_pat
= PATTERN (insn
);
9346 old_notes
= REG_NOTES (insn
);
9347 PATTERN (insn
) = pat
;
9348 REG_NOTES (insn
) = 0;
9350 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9352 /* If it isn't, there is the possibility that we previously had an insn
9353 that clobbered some register as a side effect, but the combined
9354 insn doesn't need to do that. So try once more without the clobbers
9355 unless this represents an ASM insn. */
9357 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9358 && GET_CODE (pat
) == PARALLEL
)
9362 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9363 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9366 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9370 SUBST_INT (XVECLEN (pat
, 0), pos
);
9373 pat
= XVECEXP (pat
, 0, 0);
9375 PATTERN (insn
) = pat
;
9376 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9378 PATTERN (insn
) = old_pat
;
9379 REG_NOTES (insn
) = old_notes
;
9381 /* Recognize all noop sets, these will be killed by followup pass. */
9382 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9383 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9385 /* If we had any clobbers to add, make a new pattern than contains
9386 them. Then check to make sure that all of them are dead. */
9387 if (num_clobbers_to_add
)
9389 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9390 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9392 + num_clobbers_to_add
)
9393 : num_clobbers_to_add
+ 1));
9395 if (GET_CODE (pat
) == PARALLEL
)
9396 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9397 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9399 XVECEXP (newpat
, 0, 0) = pat
;
9401 add_clobbers (newpat
, insn_code_number
);
9403 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9404 i
< XVECLEN (newpat
, 0); i
++)
9406 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
9407 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9409 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9410 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9418 return insn_code_number
;
9421 /* Like gen_lowpart_general but for use by combine. In combine it
9422 is not possible to create any new pseudoregs. However, it is
9423 safe to create invalid memory addresses, because combine will
9424 try to recognize them and all they will do is make the combine
9427 If for some reason this cannot do its job, an rtx
9428 (clobber (const_int 0)) is returned.
9429 An insn containing that will not be recognized. */
9432 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
9434 enum machine_mode imode
= GET_MODE (x
);
9435 unsigned int osize
= GET_MODE_SIZE (omode
);
9436 unsigned int isize
= GET_MODE_SIZE (imode
);
9442 /* Return identity if this is a CONST or symbolic reference. */
9444 && (GET_CODE (x
) == CONST
9445 || GET_CODE (x
) == SYMBOL_REF
9446 || GET_CODE (x
) == LABEL_REF
))
9449 /* We can only support MODE being wider than a word if X is a
9450 constant integer or has a mode the same size. */
9451 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
9452 && ! ((imode
== VOIDmode
9453 && (GET_CODE (x
) == CONST_INT
9454 || GET_CODE (x
) == CONST_DOUBLE
))
9458 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9459 won't know what to do. So we will strip off the SUBREG here and
9460 process normally. */
9461 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
9465 /* For use in case we fall down into the address adjustments
9466 further below, we need to adjust the known mode and size of
9467 x; imode and isize, since we just adjusted x. */
9468 imode
= GET_MODE (x
);
9473 isize
= GET_MODE_SIZE (imode
);
9476 result
= gen_lowpart_common (omode
, x
);
9478 #ifdef CANNOT_CHANGE_MODE_CLASS
9479 if (result
!= 0 && GET_CODE (result
) == SUBREG
)
9480 record_subregs_of_mode (result
);
9490 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9492 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9495 /* If we want to refer to something bigger than the original memref,
9496 generate a paradoxical subreg instead. That will force a reload
9497 of the original memref X. */
9499 return gen_rtx_SUBREG (omode
, x
, 0);
9501 if (WORDS_BIG_ENDIAN
)
9502 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
9504 /* Adjust the address so that the address-after-the-data is
9506 if (BYTES_BIG_ENDIAN
)
9507 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
9509 return adjust_address_nv (x
, omode
, offset
);
9512 /* If X is a comparison operator, rewrite it in a new mode. This
9513 probably won't match, but may allow further simplifications. */
9514 else if (COMPARISON_P (x
))
9515 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
9517 /* If we couldn't simplify X any other way, just enclose it in a
9518 SUBREG. Normally, this SUBREG won't match, but some patterns may
9519 include an explicit SUBREG or we may simplify it further in combine. */
9525 offset
= subreg_lowpart_offset (omode
, imode
);
9526 if (imode
== VOIDmode
)
9528 imode
= int_mode_for_mode (omode
);
9529 x
= gen_lowpart_common (imode
, x
);
9533 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
9539 return gen_rtx_CLOBBER (imode
, const0_rtx
);
9542 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9543 comparison code that will be tested.
9545 The result is a possibly different comparison code to use. *POP0 and
9546 *POP1 may be updated.
9548 It is possible that we might detect that a comparison is either always
9549 true or always false. However, we do not perform general constant
9550 folding in combine, so this knowledge isn't useful. Such tautologies
9551 should have been detected earlier. Hence we ignore all such cases. */
9553 static enum rtx_code
9554 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
9560 enum machine_mode mode
, tmode
;
9562 /* Try a few ways of applying the same transformation to both operands. */
9565 #ifndef WORD_REGISTER_OPERATIONS
9566 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9567 so check specially. */
9568 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
9569 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
9570 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9571 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
9572 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
9573 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
9574 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
9575 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
9576 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9577 && XEXP (op0
, 1) == XEXP (op1
, 1)
9578 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
9579 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
9580 && (INTVAL (XEXP (op0
, 1))
9581 == (GET_MODE_BITSIZE (GET_MODE (op0
))
9583 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
9585 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
9586 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
9590 /* If both operands are the same constant shift, see if we can ignore the
9591 shift. We can if the shift is a rotate or if the bits shifted out of
9592 this shift are known to be zero for both inputs and if the type of
9593 comparison is compatible with the shift. */
9594 if (GET_CODE (op0
) == GET_CODE (op1
)
9595 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9596 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
9597 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
9598 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
9599 || (GET_CODE (op0
) == ASHIFTRT
9600 && (code
!= GTU
&& code
!= LTU
9601 && code
!= GEU
&& code
!= LEU
)))
9602 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9603 && INTVAL (XEXP (op0
, 1)) >= 0
9604 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9605 && XEXP (op0
, 1) == XEXP (op1
, 1))
9607 enum machine_mode mode
= GET_MODE (op0
);
9608 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9609 int shift_count
= INTVAL (XEXP (op0
, 1));
9611 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
9612 mask
&= (mask
>> shift_count
) << shift_count
;
9613 else if (GET_CODE (op0
) == ASHIFT
)
9614 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
9616 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
9617 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
9618 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
9623 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9624 SUBREGs are of the same mode, and, in both cases, the AND would
9625 be redundant if the comparison was done in the narrower mode,
9626 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9627 and the operand's possibly nonzero bits are 0xffffff01; in that case
9628 if we only care about QImode, we don't need the AND). This case
9629 occurs if the output mode of an scc insn is not SImode and
9630 STORE_FLAG_VALUE == 1 (e.g., the 386).
9632 Similarly, check for a case where the AND's are ZERO_EXTEND
9633 operations from some narrower mode even though a SUBREG is not
9636 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
9637 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9638 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
9640 rtx inner_op0
= XEXP (op0
, 0);
9641 rtx inner_op1
= XEXP (op1
, 0);
9642 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
9643 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
9646 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
9647 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
9648 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
9649 && (GET_MODE (SUBREG_REG (inner_op0
))
9650 == GET_MODE (SUBREG_REG (inner_op1
)))
9651 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
9652 <= HOST_BITS_PER_WIDE_INT
)
9653 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
9654 GET_MODE (SUBREG_REG (inner_op0
)))))
9655 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
9656 GET_MODE (SUBREG_REG (inner_op1
))))))
9658 op0
= SUBREG_REG (inner_op0
);
9659 op1
= SUBREG_REG (inner_op1
);
9661 /* The resulting comparison is always unsigned since we masked
9662 off the original sign bit. */
9663 code
= unsigned_condition (code
);
9669 for (tmode
= GET_CLASS_NARROWEST_MODE
9670 (GET_MODE_CLASS (GET_MODE (op0
)));
9671 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
9672 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
9674 op0
= gen_lowpart (tmode
, inner_op0
);
9675 op1
= gen_lowpart (tmode
, inner_op1
);
9676 code
= unsigned_condition (code
);
9685 /* If both operands are NOT, we can strip off the outer operation
9686 and adjust the comparison code for swapped operands; similarly for
9687 NEG, except that this must be an equality comparison. */
9688 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
9689 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
9690 && (code
== EQ
|| code
== NE
)))
9691 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
9697 /* If the first operand is a constant, swap the operands and adjust the
9698 comparison code appropriately, but don't do this if the second operand
9699 is already a constant integer. */
9700 if (swap_commutative_operands_p (op0
, op1
))
9702 tem
= op0
, op0
= op1
, op1
= tem
;
9703 code
= swap_condition (code
);
9706 /* We now enter a loop during which we will try to simplify the comparison.
9707 For the most part, we only are concerned with comparisons with zero,
9708 but some things may really be comparisons with zero but not start
9709 out looking that way. */
9711 while (GET_CODE (op1
) == CONST_INT
)
9713 enum machine_mode mode
= GET_MODE (op0
);
9714 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
9715 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9716 int equality_comparison_p
;
9717 int sign_bit_comparison_p
;
9718 int unsigned_comparison_p
;
9719 HOST_WIDE_INT const_op
;
9721 /* We only want to handle integral modes. This catches VOIDmode,
9722 CCmode, and the floating-point modes. An exception is that we
9723 can handle VOIDmode if OP0 is a COMPARE or a comparison
9726 if (GET_MODE_CLASS (mode
) != MODE_INT
9727 && ! (mode
== VOIDmode
9728 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
9731 /* Get the constant we are comparing against and turn off all bits
9732 not on in our mode. */
9733 const_op
= INTVAL (op1
);
9734 if (mode
!= VOIDmode
)
9735 const_op
= trunc_int_for_mode (const_op
, mode
);
9736 op1
= GEN_INT (const_op
);
9738 /* If we are comparing against a constant power of two and the value
9739 being compared can only have that single bit nonzero (e.g., it was
9740 `and'ed with that bit), we can replace this with a comparison
9743 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
9744 || code
== LT
|| code
== LTU
)
9745 && mode_width
<= HOST_BITS_PER_WIDE_INT
9746 && exact_log2 (const_op
) >= 0
9747 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
9749 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
9750 op1
= const0_rtx
, const_op
= 0;
9753 /* Similarly, if we are comparing a value known to be either -1 or
9754 0 with -1, change it to the opposite comparison against zero. */
9757 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
9758 || code
== GEU
|| code
== LTU
)
9759 && num_sign_bit_copies (op0
, mode
) == mode_width
)
9761 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
9762 op1
= const0_rtx
, const_op
= 0;
9765 /* Do some canonicalizations based on the comparison code. We prefer
9766 comparisons against zero and then prefer equality comparisons.
9767 If we can reduce the size of a constant, we will do that too. */
9772 /* < C is equivalent to <= (C - 1) */
9776 op1
= GEN_INT (const_op
);
9778 /* ... fall through to LE case below. */
9784 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9788 op1
= GEN_INT (const_op
);
9792 /* If we are doing a <= 0 comparison on a value known to have
9793 a zero sign bit, we can replace this with == 0. */
9794 else if (const_op
== 0
9795 && mode_width
<= HOST_BITS_PER_WIDE_INT
9796 && (nonzero_bits (op0
, mode
)
9797 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9802 /* >= C is equivalent to > (C - 1). */
9806 op1
= GEN_INT (const_op
);
9808 /* ... fall through to GT below. */
9814 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9818 op1
= GEN_INT (const_op
);
9822 /* If we are doing a > 0 comparison on a value known to have
9823 a zero sign bit, we can replace this with != 0. */
9824 else if (const_op
== 0
9825 && mode_width
<= HOST_BITS_PER_WIDE_INT
9826 && (nonzero_bits (op0
, mode
)
9827 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9832 /* < C is equivalent to <= (C - 1). */
9836 op1
= GEN_INT (const_op
);
9838 /* ... fall through ... */
9841 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9842 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9843 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9845 const_op
= 0, op1
= const0_rtx
;
9853 /* unsigned <= 0 is equivalent to == 0 */
9857 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9858 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9859 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9861 const_op
= 0, op1
= const0_rtx
;
9867 /* >= C is equivalent to > (C - 1). */
9871 op1
= GEN_INT (const_op
);
9873 /* ... fall through ... */
9876 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9877 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9878 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9880 const_op
= 0, op1
= const0_rtx
;
9888 /* unsigned > 0 is equivalent to != 0 */
9892 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9893 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9894 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9896 const_op
= 0, op1
= const0_rtx
;
9905 /* Compute some predicates to simplify code below. */
9907 equality_comparison_p
= (code
== EQ
|| code
== NE
);
9908 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
9909 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
9912 /* If this is a sign bit comparison and we can do arithmetic in
9913 MODE, say that we will only be needing the sign bit of OP0. */
9914 if (sign_bit_comparison_p
9915 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9916 op0
= force_to_mode (op0
, mode
,
9918 << (GET_MODE_BITSIZE (mode
) - 1)),
9921 /* Now try cases based on the opcode of OP0. If none of the cases
9922 does a "continue", we exit this loop immediately after the
9925 switch (GET_CODE (op0
))
9928 /* If we are extracting a single bit from a variable position in
9929 a constant that has only a single bit set and are comparing it
9930 with zero, we can convert this into an equality comparison
9931 between the position and the location of the single bit. */
9932 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9933 have already reduced the shift count modulo the word size. */
9934 if (!SHIFT_COUNT_TRUNCATED
9935 && GET_CODE (XEXP (op0
, 0)) == CONST_INT
9936 && XEXP (op0
, 1) == const1_rtx
9937 && equality_comparison_p
&& const_op
== 0
9938 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
9940 if (BITS_BIG_ENDIAN
)
9942 enum machine_mode new_mode
9943 = mode_for_extraction (EP_extzv
, 1);
9944 if (new_mode
== MAX_MACHINE_MODE
)
9945 i
= BITS_PER_WORD
- 1 - i
;
9949 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
9953 op0
= XEXP (op0
, 2);
9957 /* Result is nonzero iff shift count is equal to I. */
9958 code
= reverse_condition (code
);
9962 /* ... fall through ... */
9965 tem
= expand_compound_operation (op0
);
9974 /* If testing for equality, we can take the NOT of the constant. */
9975 if (equality_comparison_p
9976 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
9978 op0
= XEXP (op0
, 0);
9983 /* If just looking at the sign bit, reverse the sense of the
9985 if (sign_bit_comparison_p
)
9987 op0
= XEXP (op0
, 0);
9988 code
= (code
== GE
? LT
: GE
);
9994 /* If testing for equality, we can take the NEG of the constant. */
9995 if (equality_comparison_p
9996 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
9998 op0
= XEXP (op0
, 0);
10003 /* The remaining cases only apply to comparisons with zero. */
10007 /* When X is ABS or is known positive,
10008 (neg X) is < 0 if and only if X != 0. */
10010 if (sign_bit_comparison_p
10011 && (GET_CODE (XEXP (op0
, 0)) == ABS
10012 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10013 && (nonzero_bits (XEXP (op0
, 0), mode
)
10014 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10016 op0
= XEXP (op0
, 0);
10017 code
= (code
== LT
? NE
: EQ
);
10021 /* If we have NEG of something whose two high-order bits are the
10022 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10023 if (num_sign_bit_copies (op0
, mode
) >= 2)
10025 op0
= XEXP (op0
, 0);
10026 code
= swap_condition (code
);
10032 /* If we are testing equality and our count is a constant, we
10033 can perform the inverse operation on our RHS. */
10034 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10035 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10036 op1
, XEXP (op0
, 1))) != 0)
10038 op0
= XEXP (op0
, 0);
10043 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10044 a particular bit. Convert it to an AND of a constant of that
10045 bit. This will be converted into a ZERO_EXTRACT. */
10046 if (const_op
== 0 && sign_bit_comparison_p
10047 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10048 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10050 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10053 - INTVAL (XEXP (op0
, 1)))));
10054 code
= (code
== LT
? NE
: EQ
);
10058 /* Fall through. */
10061 /* ABS is ignorable inside an equality comparison with zero. */
10062 if (const_op
== 0 && equality_comparison_p
)
10064 op0
= XEXP (op0
, 0);
10070 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10071 (compare FOO CONST) if CONST fits in FOO's mode and we
10072 are either testing inequality or have an unsigned
10073 comparison with ZERO_EXTEND or a signed comparison with
10074 SIGN_EXTEND. But don't do it if we don't have a compare
10075 insn of the given mode, since we'd have to revert it
10076 later on, and then we wouldn't know whether to sign- or
10078 mode
= GET_MODE (XEXP (op0
, 0));
10079 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10080 && ! unsigned_comparison_p
10081 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10082 && ((unsigned HOST_WIDE_INT
) const_op
10083 < (((unsigned HOST_WIDE_INT
) 1
10084 << (GET_MODE_BITSIZE (mode
) - 1))))
10085 && cmp_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
10087 op0
= XEXP (op0
, 0);
10093 /* Check for the case where we are comparing A - C1 with C2, that is
10095 (subreg:MODE (plus (A) (-C1))) op (C2)
10097 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10098 comparison in the wider mode. One of the following two conditions
10099 must be true in order for this to be valid:
10101 1. The mode extension results in the same bit pattern being added
10102 on both sides and the comparison is equality or unsigned. As
10103 C2 has been truncated to fit in MODE, the pattern can only be
10106 2. The mode extension results in the sign bit being copied on
10109 The difficulty here is that we have predicates for A but not for
10110 (A - C1) so we need to check that C1 is within proper bounds so
10111 as to perturbate A as little as possible. */
10113 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10114 && subreg_lowpart_p (op0
)
10115 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) > mode_width
10116 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10117 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
)
10119 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
10120 rtx a
= XEXP (SUBREG_REG (op0
), 0);
10121 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
10124 && (unsigned HOST_WIDE_INT
) c1
10125 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
10126 && (equality_comparison_p
|| unsigned_comparison_p
)
10127 /* (A - C1) zero-extends if it is positive and sign-extends
10128 if it is negative, C2 both zero- and sign-extends. */
10129 && ((0 == (nonzero_bits (a
, inner_mode
)
10130 & ~GET_MODE_MASK (mode
))
10132 /* (A - C1) sign-extends if it is positive and 1-extends
10133 if it is negative, C2 both sign- and 1-extends. */
10134 || (num_sign_bit_copies (a
, inner_mode
)
10135 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10138 || ((unsigned HOST_WIDE_INT
) c1
10139 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
10140 /* (A - C1) always sign-extends, like C2. */
10141 && num_sign_bit_copies (a
, inner_mode
)
10142 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10143 - mode_width
- 1)))
10145 op0
= SUBREG_REG (op0
);
10150 /* If the inner mode is narrower and we are extracting the low part,
10151 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10152 if (subreg_lowpart_p (op0
)
10153 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10154 /* Fall through */ ;
10158 /* ... fall through ... */
10161 mode
= GET_MODE (XEXP (op0
, 0));
10162 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10163 && (unsigned_comparison_p
|| equality_comparison_p
)
10164 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10165 && ((unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
))
10166 && cmp_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
10168 op0
= XEXP (op0
, 0);
10174 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10175 this for equality comparisons due to pathological cases involving
10177 if (equality_comparison_p
10178 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10179 op1
, XEXP (op0
, 1))))
10181 op0
= XEXP (op0
, 0);
10186 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10187 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10188 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10190 op0
= XEXP (XEXP (op0
, 0), 0);
10191 code
= (code
== LT
? EQ
: NE
);
10197 /* We used to optimize signed comparisons against zero, but that
10198 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10199 arrive here as equality comparisons, or (GEU, LTU) are
10200 optimized away. No need to special-case them. */
10202 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10203 (eq B (minus A C)), whichever simplifies. We can only do
10204 this for equality comparisons due to pathological cases involving
10206 if (equality_comparison_p
10207 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10208 XEXP (op0
, 1), op1
)))
10210 op0
= XEXP (op0
, 0);
10215 if (equality_comparison_p
10216 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10217 XEXP (op0
, 0), op1
)))
10219 op0
= XEXP (op0
, 1);
10224 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10225 of bits in X minus 1, is one iff X > 0. */
10226 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10227 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10228 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10230 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10232 op0
= XEXP (op0
, 1);
10233 code
= (code
== GE
? LE
: GT
);
10239 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10240 if C is zero or B is a constant. */
10241 if (equality_comparison_p
10242 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10243 XEXP (op0
, 1), op1
)))
10245 op0
= XEXP (op0
, 0);
10252 case UNEQ
: case LTGT
:
10253 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10254 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10255 case UNORDERED
: case ORDERED
:
10256 /* We can't do anything if OP0 is a condition code value, rather
10257 than an actual data value. */
10259 || CC0_P (XEXP (op0
, 0))
10260 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10263 /* Get the two operands being compared. */
10264 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10265 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10267 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10269 /* Check for the cases where we simply want the result of the
10270 earlier test or the opposite of that result. */
10271 if (code
== NE
|| code
== EQ
10272 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10273 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10274 && (STORE_FLAG_VALUE
10275 & (((HOST_WIDE_INT
) 1
10276 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10277 && (code
== LT
|| code
== GE
)))
10279 enum rtx_code new_code
;
10280 if (code
== LT
|| code
== NE
)
10281 new_code
= GET_CODE (op0
);
10283 new_code
= reversed_comparison_code (op0
, NULL
);
10285 if (new_code
!= UNKNOWN
)
10296 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10298 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10299 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10300 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10302 op0
= XEXP (op0
, 1);
10303 code
= (code
== GE
? GT
: LE
);
10309 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10310 will be converted to a ZERO_EXTRACT later. */
10311 if (const_op
== 0 && equality_comparison_p
10312 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10313 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10315 op0
= simplify_and_const_int
10316 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10318 XEXP (XEXP (op0
, 0), 1)),
10319 (HOST_WIDE_INT
) 1);
10323 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10324 zero and X is a comparison and C1 and C2 describe only bits set
10325 in STORE_FLAG_VALUE, we can compare with X. */
10326 if (const_op
== 0 && equality_comparison_p
10327 && mode_width
<= HOST_BITS_PER_WIDE_INT
10328 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10329 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10330 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10331 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10332 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10334 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10335 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10336 if ((~STORE_FLAG_VALUE
& mask
) == 0
10337 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
10338 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10339 && COMPARISON_P (tem
))))
10341 op0
= XEXP (XEXP (op0
, 0), 0);
10346 /* If we are doing an equality comparison of an AND of a bit equal
10347 to the sign bit, replace this with a LT or GE comparison of
10348 the underlying value. */
10349 if (equality_comparison_p
10351 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10352 && mode_width
<= HOST_BITS_PER_WIDE_INT
10353 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10354 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10356 op0
= XEXP (op0
, 0);
10357 code
= (code
== EQ
? GE
: LT
);
10361 /* If this AND operation is really a ZERO_EXTEND from a narrower
10362 mode, the constant fits within that mode, and this is either an
10363 equality or unsigned comparison, try to do this comparison in
10364 the narrower mode. */
10365 if ((equality_comparison_p
|| unsigned_comparison_p
)
10366 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10367 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10368 & GET_MODE_MASK (mode
))
10370 && const_op
>> i
== 0
10371 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10373 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
10377 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10378 fits in both M1 and M2 and the SUBREG is either paradoxical
10379 or represents the low part, permute the SUBREG and the AND
10381 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10383 unsigned HOST_WIDE_INT c1
;
10384 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10385 /* Require an integral mode, to avoid creating something like
10387 if (SCALAR_INT_MODE_P (tmode
)
10388 /* It is unsafe to commute the AND into the SUBREG if the
10389 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10390 not defined. As originally written the upper bits
10391 have a defined value due to the AND operation.
10392 However, if we commute the AND inside the SUBREG then
10393 they no longer have defined values and the meaning of
10394 the code has been changed. */
10396 #ifdef WORD_REGISTER_OPERATIONS
10397 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10398 && mode_width
<= BITS_PER_WORD
)
10400 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10401 && subreg_lowpart_p (XEXP (op0
, 0))))
10402 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10403 && mode_width
<= HOST_BITS_PER_WIDE_INT
10404 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10405 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10406 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10408 && c1
!= GET_MODE_MASK (tmode
))
10410 op0
= simplify_gen_binary (AND
, tmode
,
10411 SUBREG_REG (XEXP (op0
, 0)),
10412 gen_int_mode (c1
, tmode
));
10413 op0
= gen_lowpart (mode
, op0
);
10418 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10419 if (const_op
== 0 && equality_comparison_p
10420 && XEXP (op0
, 1) == const1_rtx
10421 && GET_CODE (XEXP (op0
, 0)) == NOT
)
10423 op0
= simplify_and_const_int
10424 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
10425 code
= (code
== NE
? EQ
: NE
);
10429 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10430 (eq (and (lshiftrt X) 1) 0).
10431 Also handle the case where (not X) is expressed using xor. */
10432 if (const_op
== 0 && equality_comparison_p
10433 && XEXP (op0
, 1) == const1_rtx
10434 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
10436 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
10437 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
10439 if (GET_CODE (shift_op
) == NOT
10440 || (GET_CODE (shift_op
) == XOR
10441 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
10442 && GET_CODE (shift_count
) == CONST_INT
10443 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10444 && (INTVAL (XEXP (shift_op
, 1))
10445 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
10447 op0
= simplify_and_const_int
10449 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
10450 (HOST_WIDE_INT
) 1);
10451 code
= (code
== NE
? EQ
: NE
);
10458 /* If we have (compare (ashift FOO N) (const_int C)) and
10459 the high order N bits of FOO (N+1 if an inequality comparison)
10460 are known to be zero, we can do this by comparing FOO with C
10461 shifted right N bits so long as the low-order N bits of C are
10463 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10464 && INTVAL (XEXP (op0
, 1)) >= 0
10465 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10466 < HOST_BITS_PER_WIDE_INT
)
10468 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10469 && mode_width
<= HOST_BITS_PER_WIDE_INT
10470 && (nonzero_bits (XEXP (op0
, 0), mode
)
10471 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10472 + ! equality_comparison_p
))) == 0)
10474 /* We must perform a logical shift, not an arithmetic one,
10475 as we want the top N bits of C to be zero. */
10476 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10478 temp
>>= INTVAL (XEXP (op0
, 1));
10479 op1
= gen_int_mode (temp
, mode
);
10480 op0
= XEXP (op0
, 0);
10484 /* If we are doing a sign bit comparison, it means we are testing
10485 a particular bit. Convert it to the appropriate AND. */
10486 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10487 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10489 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10492 - INTVAL (XEXP (op0
, 1)))));
10493 code
= (code
== LT
? NE
: EQ
);
10497 /* If this an equality comparison with zero and we are shifting
10498 the low bit to the sign bit, we can convert this to an AND of the
10500 if (const_op
== 0 && equality_comparison_p
10501 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10502 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10505 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10506 (HOST_WIDE_INT
) 1);
10512 /* If this is an equality comparison with zero, we can do this
10513 as a logical shift, which might be much simpler. */
10514 if (equality_comparison_p
&& const_op
== 0
10515 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10517 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10519 INTVAL (XEXP (op0
, 1)));
10523 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10524 do the comparison in a narrower mode. */
10525 if (! unsigned_comparison_p
10526 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10527 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10528 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10529 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10530 MODE_INT
, 1)) != BLKmode
10531 && (((unsigned HOST_WIDE_INT
) const_op
10532 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10533 <= GET_MODE_MASK (tmode
)))
10535 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
10539 /* Likewise if OP0 is a PLUS of a sign extension with a
10540 constant, which is usually represented with the PLUS
10541 between the shifts. */
10542 if (! unsigned_comparison_p
10543 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10544 && GET_CODE (XEXP (op0
, 0)) == PLUS
10545 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10546 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10547 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10548 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10549 MODE_INT
, 1)) != BLKmode
10550 && (((unsigned HOST_WIDE_INT
) const_op
10551 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10552 <= GET_MODE_MASK (tmode
)))
10554 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10555 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10556 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
10557 add_const
, XEXP (op0
, 1));
10559 op0
= simplify_gen_binary (PLUS
, tmode
,
10560 gen_lowpart (tmode
, inner
),
10565 /* ... fall through ... */
10567 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10568 the low order N bits of FOO are known to be zero, we can do this
10569 by comparing FOO with C shifted left N bits so long as no
10570 overflow occurs. */
10571 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10572 && INTVAL (XEXP (op0
, 1)) >= 0
10573 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10574 && mode_width
<= HOST_BITS_PER_WIDE_INT
10575 && (nonzero_bits (XEXP (op0
, 0), mode
)
10576 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10577 && (((unsigned HOST_WIDE_INT
) const_op
10578 + (GET_CODE (op0
) != LSHIFTRT
10579 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
10582 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
10584 /* If the shift was logical, then we must make the condition
10586 if (GET_CODE (op0
) == LSHIFTRT
)
10587 code
= unsigned_condition (code
);
10589 const_op
<<= INTVAL (XEXP (op0
, 1));
10590 op1
= GEN_INT (const_op
);
10591 op0
= XEXP (op0
, 0);
10595 /* If we are using this shift to extract just the sign bit, we
10596 can replace this with an LT or GE comparison. */
10598 && (equality_comparison_p
|| sign_bit_comparison_p
)
10599 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10600 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10603 op0
= XEXP (op0
, 0);
10604 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10616 /* Now make any compound operations involved in this comparison. Then,
10617 check for an outmost SUBREG on OP0 that is not doing anything or is
10618 paradoxical. The latter transformation must only be performed when
10619 it is known that the "extra" bits will be the same in op0 and op1 or
10620 that they don't matter. There are three cases to consider:
10622 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10623 care bits and we can assume they have any convenient value. So
10624 making the transformation is safe.
10626 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10627 In this case the upper bits of op0 are undefined. We should not make
10628 the simplification in that case as we do not know the contents of
10631 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10632 UNKNOWN. In that case we know those bits are zeros or ones. We must
10633 also be sure that they are the same as the upper bits of op1.
10635 We can never remove a SUBREG for a non-equality comparison because
10636 the sign bit is in a different place in the underlying object. */
10638 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
10639 op1
= make_compound_operation (op1
, SET
);
10641 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10642 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10643 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
10644 && (code
== NE
|| code
== EQ
))
10646 if (GET_MODE_SIZE (GET_MODE (op0
))
10647 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
10649 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10651 if (REG_P (SUBREG_REG (op0
)))
10653 op0
= SUBREG_REG (op0
);
10654 op1
= gen_lowpart (GET_MODE (op0
), op1
);
10657 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10658 <= HOST_BITS_PER_WIDE_INT
)
10659 && (nonzero_bits (SUBREG_REG (op0
),
10660 GET_MODE (SUBREG_REG (op0
)))
10661 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
10663 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
10665 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
10666 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
10667 op0
= SUBREG_REG (op0
), op1
= tem
;
10671 /* We now do the opposite procedure: Some machines don't have compare
10672 insns in all modes. If OP0's mode is an integer mode smaller than a
10673 word and we can't do a compare in that mode, see if there is a larger
10674 mode for which we can do the compare. There are a number of cases in
10675 which we can use the wider mode. */
10677 mode
= GET_MODE (op0
);
10678 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10679 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
10680 && ! have_insn_for (COMPARE
, mode
))
10681 for (tmode
= GET_MODE_WIDER_MODE (mode
);
10683 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
10684 tmode
= GET_MODE_WIDER_MODE (tmode
))
10685 if (have_insn_for (COMPARE
, tmode
))
10689 /* If the only nonzero bits in OP0 and OP1 are those in the
10690 narrower mode and this is an equality or unsigned comparison,
10691 we can use the wider mode. Similarly for sign-extended
10692 values, in which case it is true for all comparisons. */
10693 zero_extended
= ((code
== EQ
|| code
== NE
10694 || code
== GEU
|| code
== GTU
10695 || code
== LEU
|| code
== LTU
)
10696 && (nonzero_bits (op0
, tmode
)
10697 & ~GET_MODE_MASK (mode
)) == 0
10698 && ((GET_CODE (op1
) == CONST_INT
10699 || (nonzero_bits (op1
, tmode
)
10700 & ~GET_MODE_MASK (mode
)) == 0)));
10703 || ((num_sign_bit_copies (op0
, tmode
)
10704 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
10705 - GET_MODE_BITSIZE (mode
)))
10706 && (num_sign_bit_copies (op1
, tmode
)
10707 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
10708 - GET_MODE_BITSIZE (mode
)))))
10710 /* If OP0 is an AND and we don't have an AND in MODE either,
10711 make a new AND in the proper mode. */
10712 if (GET_CODE (op0
) == AND
10713 && !have_insn_for (AND
, mode
))
10714 op0
= simplify_gen_binary (AND
, tmode
,
10715 gen_lowpart (tmode
,
10717 gen_lowpart (tmode
,
10720 op0
= gen_lowpart (tmode
, op0
);
10721 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
10722 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
10723 op1
= gen_lowpart (tmode
, op1
);
10727 /* If this is a test for negative, we can make an explicit
10728 test of the sign bit. */
10730 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
10731 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10733 op0
= simplify_gen_binary (AND
, tmode
,
10734 gen_lowpart (tmode
, op0
),
10735 GEN_INT ((HOST_WIDE_INT
) 1
10736 << (GET_MODE_BITSIZE (mode
)
10738 code
= (code
== LT
) ? NE
: EQ
;
10743 #ifdef CANONICALIZE_COMPARISON
10744 /* If this machine only supports a subset of valid comparisons, see if we
10745 can convert an unsupported one into a supported one. */
10746 CANONICALIZE_COMPARISON (code
, op0
, op1
);
10755 /* Utility function for record_value_for_reg. Count number of
10760 enum rtx_code code
= GET_CODE (x
);
10764 if (GET_RTX_CLASS (code
) == '2'
10765 || GET_RTX_CLASS (code
) == 'c')
10767 rtx x0
= XEXP (x
, 0);
10768 rtx x1
= XEXP (x
, 1);
10771 return 1 + 2 * count_rtxs (x0
);
10773 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
10774 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
10775 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
10776 return 2 + 2 * count_rtxs (x0
)
10777 + count_rtxs (x
== XEXP (x1
, 0)
10778 ? XEXP (x1
, 1) : XEXP (x1
, 0));
10780 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
10781 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
10782 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
10783 return 2 + 2 * count_rtxs (x1
)
10784 + count_rtxs (x
== XEXP (x0
, 0)
10785 ? XEXP (x0
, 1) : XEXP (x0
, 0));
10788 fmt
= GET_RTX_FORMAT (code
);
10789 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10791 ret
+= count_rtxs (XEXP (x
, i
));
10796 /* Utility function for following routine. Called when X is part of a value
10797 being stored into last_set_value. Sets last_set_table_tick
10798 for each register mentioned. Similar to mention_regs in cse.c */
10801 update_table_tick (rtx x
)
10803 enum rtx_code code
= GET_CODE (x
);
10804 const char *fmt
= GET_RTX_FORMAT (code
);
10809 unsigned int regno
= REGNO (x
);
10810 unsigned int endregno
10811 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10812 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
10815 for (r
= regno
; r
< endregno
; r
++)
10816 reg_stat
[r
].last_set_table_tick
= label_tick
;
10821 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10822 /* Note that we can't have an "E" in values stored; see
10823 get_last_value_validate. */
10826 /* Check for identical subexpressions. If x contains
10827 identical subexpression we only have to traverse one of
10829 if (i
== 0 && ARITHMETIC_P (x
))
10831 /* Note that at this point x1 has already been
10833 rtx x0
= XEXP (x
, 0);
10834 rtx x1
= XEXP (x
, 1);
10836 /* If x0 and x1 are identical then there is no need to
10841 /* If x0 is identical to a subexpression of x1 then while
10842 processing x1, x0 has already been processed. Thus we
10843 are done with x. */
10844 if (ARITHMETIC_P (x1
)
10845 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
10848 /* If x1 is identical to a subexpression of x0 then we
10849 still have to process the rest of x0. */
10850 if (ARITHMETIC_P (x0
)
10851 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
10853 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
10858 update_table_tick (XEXP (x
, i
));
10862 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10863 are saying that the register is clobbered and we no longer know its
10864 value. If INSN is zero, don't update reg_stat[].last_set; this is
10865 only permitted with VALUE also zero and is used to invalidate the
10869 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
10871 unsigned int regno
= REGNO (reg
);
10872 unsigned int endregno
10873 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10874 ? hard_regno_nregs
[regno
][GET_MODE (reg
)] : 1);
10877 /* If VALUE contains REG and we have a previous value for REG, substitute
10878 the previous value. */
10879 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
10883 /* Set things up so get_last_value is allowed to see anything set up to
10885 subst_low_cuid
= INSN_CUID (insn
);
10886 tem
= get_last_value (reg
);
10888 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10889 it isn't going to be useful and will take a lot of time to process,
10890 so just use the CLOBBER. */
10894 if (ARITHMETIC_P (tem
)
10895 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
10896 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
10897 tem
= XEXP (tem
, 0);
10898 else if (count_occurrences (value
, reg
, 1) >= 2)
10900 /* If there are two or more occurrences of REG in VALUE,
10901 prevent the value from growing too much. */
10902 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
10903 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
10906 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
10910 /* For each register modified, show we don't know its value, that
10911 we don't know about its bitwise content, that its value has been
10912 updated, and that we don't know the location of the death of the
10914 for (i
= regno
; i
< endregno
; i
++)
10917 reg_stat
[i
].last_set
= insn
;
10919 reg_stat
[i
].last_set_value
= 0;
10920 reg_stat
[i
].last_set_mode
= 0;
10921 reg_stat
[i
].last_set_nonzero_bits
= 0;
10922 reg_stat
[i
].last_set_sign_bit_copies
= 0;
10923 reg_stat
[i
].last_death
= 0;
10926 /* Mark registers that are being referenced in this value. */
10928 update_table_tick (value
);
10930 /* Now update the status of each register being set.
10931 If someone is using this register in this block, set this register
10932 to invalid since we will get confused between the two lives in this
10933 basic block. This makes using this register always invalid. In cse, we
10934 scan the table to invalidate all entries using this register, but this
10935 is too much work for us. */
10937 for (i
= regno
; i
< endregno
; i
++)
10939 reg_stat
[i
].last_set_label
= label_tick
;
10940 if (value
&& reg_stat
[i
].last_set_table_tick
== label_tick
)
10941 reg_stat
[i
].last_set_invalid
= 1;
10943 reg_stat
[i
].last_set_invalid
= 0;
10946 /* The value being assigned might refer to X (like in "x++;"). In that
10947 case, we must replace it with (clobber (const_int 0)) to prevent
10949 if (value
&& ! get_last_value_validate (&value
, insn
,
10950 reg_stat
[regno
].last_set_label
, 0))
10952 value
= copy_rtx (value
);
10953 if (! get_last_value_validate (&value
, insn
,
10954 reg_stat
[regno
].last_set_label
, 1))
10958 /* For the main register being modified, update the value, the mode, the
10959 nonzero bits, and the number of sign bit copies. */
10961 reg_stat
[regno
].last_set_value
= value
;
10965 enum machine_mode mode
= GET_MODE (reg
);
10966 subst_low_cuid
= INSN_CUID (insn
);
10967 reg_stat
[regno
].last_set_mode
= mode
;
10968 if (GET_MODE_CLASS (mode
) == MODE_INT
10969 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10970 mode
= nonzero_bits_mode
;
10971 reg_stat
[regno
].last_set_nonzero_bits
= nonzero_bits (value
, mode
);
10972 reg_stat
[regno
].last_set_sign_bit_copies
10973 = num_sign_bit_copies (value
, GET_MODE (reg
));
10977 /* Called via note_stores from record_dead_and_set_regs to handle one
10978 SET or CLOBBER in an insn. DATA is the instruction in which the
10979 set is occurring. */
10982 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
10984 rtx record_dead_insn
= (rtx
) data
;
10986 if (GET_CODE (dest
) == SUBREG
)
10987 dest
= SUBREG_REG (dest
);
10991 /* If we are setting the whole register, we know its value. Otherwise
10992 show that we don't know the value. We can handle SUBREG in
10994 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
10995 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
10996 else if (GET_CODE (setter
) == SET
10997 && GET_CODE (SET_DEST (setter
)) == SUBREG
10998 && SUBREG_REG (SET_DEST (setter
)) == dest
10999 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11000 && subreg_lowpart_p (SET_DEST (setter
)))
11001 record_value_for_reg (dest
, record_dead_insn
,
11002 gen_lowpart (GET_MODE (dest
),
11003 SET_SRC (setter
)));
11005 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11007 else if (MEM_P (dest
)
11008 /* Ignore pushes, they clobber nothing. */
11009 && ! push_operand (dest
, GET_MODE (dest
)))
11010 mem_last_set
= INSN_CUID (record_dead_insn
);
11013 /* Update the records of when each REG was most recently set or killed
11014 for the things done by INSN. This is the last thing done in processing
11015 INSN in the combiner loop.
11017 We update reg_stat[], in particular fields last_set, last_set_value,
11018 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11019 last_death, and also the similar information mem_last_set (which insn
11020 most recently modified memory) and last_call_cuid (which insn was the
11021 most recent subroutine call). */
11024 record_dead_and_set_regs (rtx insn
)
11029 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11031 if (REG_NOTE_KIND (link
) == REG_DEAD
11032 && REG_P (XEXP (link
, 0)))
11034 unsigned int regno
= REGNO (XEXP (link
, 0));
11035 unsigned int endregno
11036 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11037 ? hard_regno_nregs
[regno
][GET_MODE (XEXP (link
, 0))]
11040 for (i
= regno
; i
< endregno
; i
++)
11041 reg_stat
[i
].last_death
= insn
;
11043 else if (REG_NOTE_KIND (link
) == REG_INC
)
11044 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11049 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11050 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11052 reg_stat
[i
].last_set_value
= 0;
11053 reg_stat
[i
].last_set_mode
= 0;
11054 reg_stat
[i
].last_set_nonzero_bits
= 0;
11055 reg_stat
[i
].last_set_sign_bit_copies
= 0;
11056 reg_stat
[i
].last_death
= 0;
11059 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11061 /* Don't bother recording what this insn does. It might set the
11062 return value register, but we can't combine into a call
11063 pattern anyway, so there's no point trying (and it may cause
11064 a crash, if e.g. we wind up asking for last_set_value of a
11065 SUBREG of the return value register). */
11069 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11072 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11073 register present in the SUBREG, so for each such SUBREG go back and
11074 adjust nonzero and sign bit information of the registers that are
11075 known to have some zero/sign bits set.
11077 This is needed because when combine blows the SUBREGs away, the
11078 information on zero/sign bits is lost and further combines can be
11079 missed because of that. */
11082 record_promoted_value (rtx insn
, rtx subreg
)
11085 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11086 enum machine_mode mode
= GET_MODE (subreg
);
11088 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11091 for (links
= LOG_LINKS (insn
); links
;)
11093 insn
= XEXP (links
, 0);
11094 set
= single_set (insn
);
11096 if (! set
|| !REG_P (SET_DEST (set
))
11097 || REGNO (SET_DEST (set
)) != regno
11098 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11100 links
= XEXP (links
, 1);
11104 if (reg_stat
[regno
].last_set
== insn
)
11106 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11107 reg_stat
[regno
].last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
11110 if (REG_P (SET_SRC (set
)))
11112 regno
= REGNO (SET_SRC (set
));
11113 links
= LOG_LINKS (insn
);
11120 /* Scan X for promoted SUBREGs. For each one found,
11121 note what it implies to the registers used in it. */
11124 check_promoted_subreg (rtx insn
, rtx x
)
11126 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11127 && REG_P (SUBREG_REG (x
)))
11128 record_promoted_value (insn
, x
);
11131 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11134 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11138 check_promoted_subreg (insn
, XEXP (x
, i
));
11142 if (XVEC (x
, i
) != 0)
11143 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11144 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11150 /* Utility routine for the following function. Verify that all the registers
11151 mentioned in *LOC are valid when *LOC was part of a value set when
11152 label_tick == TICK. Return 0 if some are not.
11154 If REPLACE is nonzero, replace the invalid reference with
11155 (clobber (const_int 0)) and return 1. This replacement is useful because
11156 we often can get useful information about the form of a value (e.g., if
11157 it was produced by a shift that always produces -1 or 0) even though
11158 we don't know exactly what registers it was produced from. */
11161 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11164 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11165 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11170 unsigned int regno
= REGNO (x
);
11171 unsigned int endregno
11172 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11173 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11176 for (j
= regno
; j
< endregno
; j
++)
11177 if (reg_stat
[j
].last_set_invalid
11178 /* If this is a pseudo-register that was only set once and not
11179 live at the beginning of the function, it is always valid. */
11180 || (! (regno
>= FIRST_PSEUDO_REGISTER
11181 && REG_N_SETS (regno
) == 1
11182 && (! REGNO_REG_SET_P
11183 (ENTRY_BLOCK_PTR
->next_bb
->il
.rtl
->global_live_at_start
,
11185 && reg_stat
[j
].last_set_label
> tick
))
11188 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11194 /* If this is a memory reference, make sure that there were
11195 no stores after it that might have clobbered the value. We don't
11196 have alias info, so we assume any store invalidates it. */
11197 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
11198 && INSN_CUID (insn
) <= mem_last_set
)
11201 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11205 for (i
= 0; i
< len
; i
++)
11209 /* Check for identical subexpressions. If x contains
11210 identical subexpression we only have to traverse one of
11212 if (i
== 1 && ARITHMETIC_P (x
))
11214 /* Note that at this point x0 has already been checked
11215 and found valid. */
11216 rtx x0
= XEXP (x
, 0);
11217 rtx x1
= XEXP (x
, 1);
11219 /* If x0 and x1 are identical then x is also valid. */
11223 /* If x1 is identical to a subexpression of x0 then
11224 while checking x0, x1 has already been checked. Thus
11225 it is valid and so as x. */
11226 if (ARITHMETIC_P (x0
)
11227 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11230 /* If x0 is identical to a subexpression of x1 then x is
11231 valid iff the rest of x1 is valid. */
11232 if (ARITHMETIC_P (x1
)
11233 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11235 get_last_value_validate (&XEXP (x1
,
11236 x0
== XEXP (x1
, 0) ? 1 : 0),
11237 insn
, tick
, replace
);
11240 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11244 /* Don't bother with these. They shouldn't occur anyway. */
11245 else if (fmt
[i
] == 'E')
11249 /* If we haven't found a reason for it to be invalid, it is valid. */
11253 /* Get the last value assigned to X, if known. Some registers
11254 in the value may be replaced with (clobber (const_int 0)) if their value
11255 is known longer known reliably. */
11258 get_last_value (rtx x
)
11260 unsigned int regno
;
11263 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11264 then convert it to the desired mode. If this is a paradoxical SUBREG,
11265 we cannot predict what values the "extra" bits might have. */
11266 if (GET_CODE (x
) == SUBREG
11267 && subreg_lowpart_p (x
)
11268 && (GET_MODE_SIZE (GET_MODE (x
))
11269 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11270 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11271 return gen_lowpart (GET_MODE (x
), value
);
11277 value
= reg_stat
[regno
].last_set_value
;
11279 /* If we don't have a value, or if it isn't for this basic block and
11280 it's either a hard register, set more than once, or it's a live
11281 at the beginning of the function, return 0.
11283 Because if it's not live at the beginning of the function then the reg
11284 is always set before being used (is never used without being set).
11285 And, if it's set only once, and it's always set before use, then all
11286 uses must have the same last value, even if it's not from this basic
11290 || (reg_stat
[regno
].last_set_label
!= label_tick
11291 && (regno
< FIRST_PSEUDO_REGISTER
11292 || REG_N_SETS (regno
) != 1
11293 || (REGNO_REG_SET_P
11294 (ENTRY_BLOCK_PTR
->next_bb
->il
.rtl
->global_live_at_start
,
11298 /* If the value was set in a later insn than the ones we are processing,
11299 we can't use it even if the register was only set once. */
11300 if (INSN_CUID (reg_stat
[regno
].last_set
) >= subst_low_cuid
)
11303 /* If the value has all its registers valid, return it. */
11304 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11305 reg_stat
[regno
].last_set_label
, 0))
11308 /* Otherwise, make a copy and replace any invalid register with
11309 (clobber (const_int 0)). If that fails for some reason, return 0. */
11311 value
= copy_rtx (value
);
11312 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11313 reg_stat
[regno
].last_set_label
, 1))
11319 /* Return nonzero if expression X refers to a REG or to memory
11320 that is set in an instruction more recent than FROM_CUID. */
11323 use_crosses_set_p (rtx x
, int from_cuid
)
11327 enum rtx_code code
= GET_CODE (x
);
11331 unsigned int regno
= REGNO (x
);
11332 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11333 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11335 #ifdef PUSH_ROUNDING
11336 /* Don't allow uses of the stack pointer to be moved,
11337 because we don't know whether the move crosses a push insn. */
11338 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11341 for (; regno
< endreg
; regno
++)
11342 if (reg_stat
[regno
].last_set
11343 && INSN_CUID (reg_stat
[regno
].last_set
) > from_cuid
)
11348 if (code
== MEM
&& mem_last_set
> from_cuid
)
11351 fmt
= GET_RTX_FORMAT (code
);
11353 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11358 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11359 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11362 else if (fmt
[i
] == 'e'
11363 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11369 /* Define three variables used for communication between the following
11372 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11373 static int reg_dead_flag
;
11375 /* Function called via note_stores from reg_dead_at_p.
11377 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11378 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11381 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
11383 unsigned int regno
, endregno
;
11388 regno
= REGNO (dest
);
11389 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11390 ? hard_regno_nregs
[regno
][GET_MODE (dest
)] : 1);
11392 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11393 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11396 /* Return nonzero if REG is known to be dead at INSN.
11398 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11399 referencing REG, it is dead. If we hit a SET referencing REG, it is
11400 live. Otherwise, see if it is live or dead at the start of the basic
11401 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11402 must be assumed to be always live. */
11405 reg_dead_at_p (rtx reg
, rtx insn
)
11410 /* Set variables for reg_dead_at_p_1. */
11411 reg_dead_regno
= REGNO (reg
);
11412 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11413 ? hard_regno_nregs
[reg_dead_regno
]
11419 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11420 we allow the machine description to decide whether use-and-clobber
11421 patterns are OK. */
11422 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11424 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11425 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11429 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11430 beginning of function. */
11431 for (; insn
&& !LABEL_P (insn
) && !BARRIER_P (insn
);
11432 insn
= prev_nonnote_insn (insn
))
11434 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11436 return reg_dead_flag
== 1 ? 1 : 0;
11438 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11442 /* Get the basic block that we were in. */
11444 block
= ENTRY_BLOCK_PTR
->next_bb
;
11447 FOR_EACH_BB (block
)
11448 if (insn
== BB_HEAD (block
))
11451 if (block
== EXIT_BLOCK_PTR
)
11455 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11456 if (REGNO_REG_SET_P (block
->il
.rtl
->global_live_at_start
, i
))
11462 /* Note hard registers in X that are used. This code is similar to
11463 that in flow.c, but much simpler since we don't care about pseudos. */
11466 mark_used_regs_combine (rtx x
)
11468 RTX_CODE code
= GET_CODE (x
);
11469 unsigned int regno
;
11482 case ADDR_DIFF_VEC
:
11485 /* CC0 must die in the insn after it is set, so we don't need to take
11486 special note of it here. */
11492 /* If we are clobbering a MEM, mark any hard registers inside the
11493 address as used. */
11494 if (MEM_P (XEXP (x
, 0)))
11495 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11500 /* A hard reg in a wide mode may really be multiple registers.
11501 If so, mark all of them just like the first. */
11502 if (regno
< FIRST_PSEUDO_REGISTER
)
11504 unsigned int endregno
, r
;
11506 /* None of this applies to the stack, frame or arg pointers. */
11507 if (regno
== STACK_POINTER_REGNUM
11508 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11509 || regno
== HARD_FRAME_POINTER_REGNUM
11511 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11512 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11514 || regno
== FRAME_POINTER_REGNUM
)
11517 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11518 for (r
= regno
; r
< endregno
; r
++)
11519 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11525 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11527 rtx testreg
= SET_DEST (x
);
11529 while (GET_CODE (testreg
) == SUBREG
11530 || GET_CODE (testreg
) == ZERO_EXTRACT
11531 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11532 testreg
= XEXP (testreg
, 0);
11534 if (MEM_P (testreg
))
11535 mark_used_regs_combine (XEXP (testreg
, 0));
11537 mark_used_regs_combine (SET_SRC (x
));
11545 /* Recursively scan the operands of this expression. */
11548 const char *fmt
= GET_RTX_FORMAT (code
);
11550 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11553 mark_used_regs_combine (XEXP (x
, i
));
11554 else if (fmt
[i
] == 'E')
11558 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11559 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11565 /* Remove register number REGNO from the dead registers list of INSN.
11567 Return the note used to record the death, if there was one. */
11570 remove_death (unsigned int regno
, rtx insn
)
11572 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11576 REG_N_DEATHS (regno
)--;
11577 remove_note (insn
, note
);
11583 /* For each register (hardware or pseudo) used within expression X, if its
11584 death is in an instruction with cuid between FROM_CUID (inclusive) and
11585 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11586 list headed by PNOTES.
11588 That said, don't move registers killed by maybe_kill_insn.
11590 This is done when X is being merged by combination into TO_INSN. These
11591 notes will then be distributed as needed. */
11594 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
11599 enum rtx_code code
= GET_CODE (x
);
11603 unsigned int regno
= REGNO (x
);
11604 rtx where_dead
= reg_stat
[regno
].last_death
;
11605 rtx before_dead
, after_dead
;
11607 /* Don't move the register if it gets killed in between from and to. */
11608 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11609 && ! reg_referenced_p (x
, maybe_kill_insn
))
11612 /* WHERE_DEAD could be a USE insn made by combine, so first we
11613 make sure that we have insns with valid INSN_CUID values. */
11614 before_dead
= where_dead
;
11615 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11616 before_dead
= PREV_INSN (before_dead
);
11618 after_dead
= where_dead
;
11619 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11620 after_dead
= NEXT_INSN (after_dead
);
11622 if (before_dead
&& after_dead
11623 && INSN_CUID (before_dead
) >= from_cuid
11624 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11625 || (where_dead
!= after_dead
11626 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11628 rtx note
= remove_death (regno
, where_dead
);
11630 /* It is possible for the call above to return 0. This can occur
11631 when last_death points to I2 or I1 that we combined with.
11632 In that case make a new note.
11634 We must also check for the case where X is a hard register
11635 and NOTE is a death note for a range of hard registers
11636 including X. In that case, we must put REG_DEAD notes for
11637 the remaining registers in place of NOTE. */
11639 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11640 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11641 > GET_MODE_SIZE (GET_MODE (x
))))
11643 unsigned int deadregno
= REGNO (XEXP (note
, 0));
11644 unsigned int deadend
11645 = (deadregno
+ hard_regno_nregs
[deadregno
]
11646 [GET_MODE (XEXP (note
, 0))]);
11647 unsigned int ourend
11648 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11651 for (i
= deadregno
; i
< deadend
; i
++)
11652 if (i
< regno
|| i
>= ourend
)
11653 REG_NOTES (where_dead
)
11654 = gen_rtx_EXPR_LIST (REG_DEAD
,
11656 REG_NOTES (where_dead
));
11659 /* If we didn't find any note, or if we found a REG_DEAD note that
11660 covers only part of the given reg, and we have a multi-reg hard
11661 register, then to be safe we must check for REG_DEAD notes
11662 for each register other than the first. They could have
11663 their own REG_DEAD notes lying around. */
11664 else if ((note
== 0
11666 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11667 < GET_MODE_SIZE (GET_MODE (x
)))))
11668 && regno
< FIRST_PSEUDO_REGISTER
11669 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
11671 unsigned int ourend
11672 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11673 unsigned int i
, offset
;
11677 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
11681 for (i
= regno
+ offset
; i
< ourend
; i
++)
11682 move_deaths (regno_reg_rtx
[i
],
11683 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11686 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11688 XEXP (note
, 1) = *pnotes
;
11692 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
11694 REG_N_DEATHS (regno
)++;
11700 else if (GET_CODE (x
) == SET
)
11702 rtx dest
= SET_DEST (x
);
11704 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11706 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11707 that accesses one word of a multi-word item, some
11708 piece of everything register in the expression is used by
11709 this insn, so remove any old death. */
11710 /* ??? So why do we test for equality of the sizes? */
11712 if (GET_CODE (dest
) == ZERO_EXTRACT
11713 || GET_CODE (dest
) == STRICT_LOW_PART
11714 || (GET_CODE (dest
) == SUBREG
11715 && (((GET_MODE_SIZE (GET_MODE (dest
))
11716 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
11717 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
11718 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
11720 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11724 /* If this is some other SUBREG, we know it replaces the entire
11725 value, so use that as the destination. */
11726 if (GET_CODE (dest
) == SUBREG
)
11727 dest
= SUBREG_REG (dest
);
11729 /* If this is a MEM, adjust deaths of anything used in the address.
11730 For a REG (the only other possibility), the entire value is
11731 being replaced so the old value is not used in this insn. */
11734 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
11739 else if (GET_CODE (x
) == CLOBBER
)
11742 len
= GET_RTX_LENGTH (code
);
11743 fmt
= GET_RTX_FORMAT (code
);
11745 for (i
= 0; i
< len
; i
++)
11750 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11751 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
11754 else if (fmt
[i
] == 'e')
11755 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11759 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11760 pattern of an insn. X must be a REG. */
11763 reg_bitfield_target_p (rtx x
, rtx body
)
11767 if (GET_CODE (body
) == SET
)
11769 rtx dest
= SET_DEST (body
);
11771 unsigned int regno
, tregno
, endregno
, endtregno
;
11773 if (GET_CODE (dest
) == ZERO_EXTRACT
)
11774 target
= XEXP (dest
, 0);
11775 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
11776 target
= SUBREG_REG (XEXP (dest
, 0));
11780 if (GET_CODE (target
) == SUBREG
)
11781 target
= SUBREG_REG (target
);
11783 if (!REG_P (target
))
11786 tregno
= REGNO (target
), regno
= REGNO (x
);
11787 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
11788 return target
== x
;
11790 endtregno
= tregno
+ hard_regno_nregs
[tregno
][GET_MODE (target
)];
11791 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11793 return endregno
> tregno
&& regno
< endtregno
;
11796 else if (GET_CODE (body
) == PARALLEL
)
11797 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
11798 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
11804 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11805 as appropriate. I3 and I2 are the insns resulting from the combination
11806 insns including FROM (I2 may be zero).
11808 Each note in the list is either ignored or placed on some insns, depending
11809 on the type of note. */
11812 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
)
11814 rtx note
, next_note
;
11817 for (note
= notes
; note
; note
= next_note
)
11819 rtx place
= 0, place2
= 0;
11821 /* If this NOTE references a pseudo register, ensure it references
11822 the latest copy of that register. */
11823 if (XEXP (note
, 0) && REG_P (XEXP (note
, 0))
11824 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
11825 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
11827 next_note
= XEXP (note
, 1);
11828 switch (REG_NOTE_KIND (note
))
11832 /* Doesn't matter much where we put this, as long as it's somewhere.
11833 It is preferable to keep these notes on branches, which is most
11834 likely to be i3. */
11838 case REG_VALUE_PROFILE
:
11839 /* Just get rid of this note, as it is unused later anyway. */
11842 case REG_NON_LOCAL_GOTO
:
11847 gcc_assert (i2
&& JUMP_P (i2
));
11852 case REG_EH_REGION
:
11853 /* These notes must remain with the call or trapping instruction. */
11856 else if (i2
&& CALL_P (i2
))
11860 gcc_assert (flag_non_call_exceptions
);
11861 if (may_trap_p (i3
))
11863 else if (i2
&& may_trap_p (i2
))
11865 /* ??? Otherwise assume we've combined things such that we
11866 can now prove that the instructions can't trap. Drop the
11867 note in this case. */
11873 /* These notes must remain with the call. It should not be
11874 possible for both I2 and I3 to be a call. */
11879 gcc_assert (i2
&& CALL_P (i2
));
11885 /* Any clobbers for i3 may still exist, and so we must process
11886 REG_UNUSED notes from that insn.
11888 Any clobbers from i2 or i1 can only exist if they were added by
11889 recog_for_combine. In that case, recog_for_combine created the
11890 necessary REG_UNUSED notes. Trying to keep any original
11891 REG_UNUSED notes from these insns can cause incorrect output
11892 if it is for the same register as the original i3 dest.
11893 In that case, we will notice that the register is set in i3,
11894 and then add a REG_UNUSED note for the destination of i3, which
11895 is wrong. However, it is possible to have REG_UNUSED notes from
11896 i2 or i1 for register which were both used and clobbered, so
11897 we keep notes from i2 or i1 if they will turn into REG_DEAD
11900 /* If this register is set or clobbered in I3, put the note there
11901 unless there is one already. */
11902 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
11904 if (from_insn
!= i3
)
11907 if (! (REG_P (XEXP (note
, 0))
11908 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
11909 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
11912 /* Otherwise, if this register is used by I3, then this register
11913 now dies here, so we must put a REG_DEAD note here unless there
11915 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
11916 && ! (REG_P (XEXP (note
, 0))
11917 ? find_regno_note (i3
, REG_DEAD
,
11918 REGNO (XEXP (note
, 0)))
11919 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
11921 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
11929 /* These notes say something about results of an insn. We can
11930 only support them if they used to be on I3 in which case they
11931 remain on I3. Otherwise they are ignored.
11933 If the note refers to an expression that is not a constant, we
11934 must also ignore the note since we cannot tell whether the
11935 equivalence is still true. It might be possible to do
11936 slightly better than this (we only have a problem if I2DEST
11937 or I1DEST is present in the expression), but it doesn't
11938 seem worth the trouble. */
11940 if (from_insn
== i3
11941 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
11946 case REG_NO_CONFLICT
:
11947 /* These notes say something about how a register is used. They must
11948 be present on any use of the register in I2 or I3. */
11949 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
11952 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
11962 /* This can show up in several ways -- either directly in the
11963 pattern, or hidden off in the constant pool with (or without?)
11964 a REG_EQUAL note. */
11965 /* ??? Ignore the without-reg_equal-note problem for now. */
11966 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
11967 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
11968 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
11969 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
11973 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
11974 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
11975 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
11976 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
11984 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
11985 a JUMP_LABEL instead or decrement LABEL_NUSES. */
11986 if (place
&& JUMP_P (place
))
11988 rtx label
= JUMP_LABEL (place
);
11991 JUMP_LABEL (place
) = XEXP (note
, 0);
11994 gcc_assert (label
== XEXP (note
, 0));
11995 if (LABEL_P (label
))
11996 LABEL_NUSES (label
)--;
12000 if (place2
&& JUMP_P (place2
))
12002 rtx label
= JUMP_LABEL (place2
);
12005 JUMP_LABEL (place2
) = XEXP (note
, 0);
12008 gcc_assert (label
== XEXP (note
, 0));
12009 if (LABEL_P (label
))
12010 LABEL_NUSES (label
)--;
12017 /* This note says something about the value of a register prior
12018 to the execution of an insn. It is too much trouble to see
12019 if the note is still correct in all situations. It is better
12020 to simply delete it. */
12024 /* If the insn previously containing this note still exists,
12025 put it back where it was. Otherwise move it to the previous
12026 insn. Adjust the corresponding REG_LIBCALL note. */
12027 if (!NOTE_P (from_insn
))
12031 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12032 place
= prev_real_insn (from_insn
);
12034 XEXP (tem
, 0) = place
;
12035 /* If we're deleting the last remaining instruction of a
12036 libcall sequence, don't add the notes. */
12037 else if (XEXP (note
, 0) == from_insn
)
12039 /* Don't add the dangling REG_RETVAL note. */
12046 /* This is handled similarly to REG_RETVAL. */
12047 if (!NOTE_P (from_insn
))
12051 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12052 place
= next_real_insn (from_insn
);
12054 XEXP (tem
, 0) = place
;
12055 /* If we're deleting the last remaining instruction of a
12056 libcall sequence, don't add the notes. */
12057 else if (XEXP (note
, 0) == from_insn
)
12059 /* Don't add the dangling REG_LIBCALL note. */
12066 /* If the register is used as an input in I3, it dies there.
12067 Similarly for I2, if it is nonzero and adjacent to I3.
12069 If the register is not used as an input in either I3 or I2
12070 and it is not one of the registers we were supposed to eliminate,
12071 there are two possibilities. We might have a non-adjacent I2
12072 or we might have somehow eliminated an additional register
12073 from a computation. For example, we might have had A & B where
12074 we discover that B will always be zero. In this case we will
12075 eliminate the reference to A.
12077 In both cases, we must search to see if we can find a previous
12078 use of A and put the death note there. */
12081 && CALL_P (from_insn
)
12082 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12084 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12086 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12087 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12092 basic_block bb
= this_basic_block
;
12094 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12096 if (! INSN_P (tem
))
12098 if (tem
== BB_HEAD (bb
))
12103 /* If the register is being set at TEM, see if that is all
12104 TEM is doing. If so, delete TEM. Otherwise, make this
12105 into a REG_UNUSED note instead. Don't delete sets to
12106 global register vars. */
12107 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
12108 || !global_regs
[REGNO (XEXP (note
, 0))])
12109 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12111 rtx set
= single_set (tem
);
12112 rtx inner_dest
= 0;
12114 rtx cc0_setter
= NULL_RTX
;
12118 for (inner_dest
= SET_DEST (set
);
12119 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12120 || GET_CODE (inner_dest
) == SUBREG
12121 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12122 inner_dest
= XEXP (inner_dest
, 0))
12125 /* Verify that it was the set, and not a clobber that
12126 modified the register.
12128 CC0 targets must be careful to maintain setter/user
12129 pairs. If we cannot delete the setter due to side
12130 effects, mark the user with an UNUSED note instead
12133 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12134 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12136 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12137 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12138 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12142 /* Move the notes and links of TEM elsewhere.
12143 This might delete other dead insns recursively.
12144 First set the pattern to something that won't use
12146 rtx old_notes
= REG_NOTES (tem
);
12148 PATTERN (tem
) = pc_rtx
;
12149 REG_NOTES (tem
) = NULL
;
12151 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
);
12152 distribute_links (LOG_LINKS (tem
));
12154 SET_INSN_DELETED (tem
);
12157 /* Delete the setter too. */
12160 PATTERN (cc0_setter
) = pc_rtx
;
12161 old_notes
= REG_NOTES (cc0_setter
);
12162 REG_NOTES (cc0_setter
) = NULL
;
12164 distribute_notes (old_notes
, cc0_setter
,
12165 cc0_setter
, NULL_RTX
);
12166 distribute_links (LOG_LINKS (cc0_setter
));
12168 SET_INSN_DELETED (cc0_setter
);
12174 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12176 /* If there isn't already a REG_UNUSED note, put one
12177 here. Do not place a REG_DEAD note, even if
12178 the register is also used here; that would not
12179 match the algorithm used in lifetime analysis
12180 and can cause the consistency check in the
12181 scheduler to fail. */
12182 if (! find_regno_note (tem
, REG_UNUSED
,
12183 REGNO (XEXP (note
, 0))))
12188 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12190 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12194 /* If we are doing a 3->2 combination, and we have a
12195 register which formerly died in i3 and was not used
12196 by i2, which now no longer dies in i3 and is used in
12197 i2 but does not die in i2, and place is between i2
12198 and i3, then we may need to move a link from place to
12200 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12201 && INSN_CUID (place
) > INSN_CUID (i2
)
12203 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12204 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12206 rtx links
= LOG_LINKS (place
);
12207 LOG_LINKS (place
) = 0;
12208 distribute_links (links
);
12213 if (tem
== BB_HEAD (bb
))
12217 /* We haven't found an insn for the death note and it
12218 is still a REG_DEAD note, but we have hit the beginning
12219 of the block. If the existing life info says the reg
12220 was dead, there's nothing left to do. Otherwise, we'll
12221 need to do a global life update after combine. */
12222 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12223 && REGNO_REG_SET_P (bb
->il
.rtl
->global_live_at_start
,
12224 REGNO (XEXP (note
, 0))))
12225 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12228 /* If the register is set or already dead at PLACE, we needn't do
12229 anything with this note if it is still a REG_DEAD note.
12230 We check here if it is set at all, not if is it totally replaced,
12231 which is what `dead_or_set_p' checks, so also check for it being
12234 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12236 unsigned int regno
= REGNO (XEXP (note
, 0));
12238 /* Similarly, if the instruction on which we want to place
12239 the note is a noop, we'll need do a global live update
12240 after we remove them in delete_noop_moves. */
12241 if (noop_move_p (place
))
12242 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12244 if (dead_or_set_p (place
, XEXP (note
, 0))
12245 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12247 /* Unless the register previously died in PLACE, clear
12248 last_death. [I no longer understand why this is
12250 if (reg_stat
[regno
].last_death
!= place
)
12251 reg_stat
[regno
].last_death
= 0;
12255 reg_stat
[regno
].last_death
= place
;
12257 /* If this is a death note for a hard reg that is occupying
12258 multiple registers, ensure that we are still using all
12259 parts of the object. If we find a piece of the object
12260 that is unused, we must arrange for an appropriate REG_DEAD
12261 note to be added for it. However, we can't just emit a USE
12262 and tag the note to it, since the register might actually
12263 be dead; so we recourse, and the recursive call then finds
12264 the previous insn that used this register. */
12266 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12267 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
12269 unsigned int endregno
12270 = regno
+ hard_regno_nregs
[regno
]
12271 [GET_MODE (XEXP (note
, 0))];
12275 for (i
= regno
; i
< endregno
; i
++)
12276 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12277 && ! find_regno_fusage (place
, USE
, i
))
12278 || dead_or_set_regno_p (place
, i
))
12283 /* Put only REG_DEAD notes for pieces that are
12284 not already dead or set. */
12286 for (i
= regno
; i
< endregno
;
12287 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
12289 rtx piece
= regno_reg_rtx
[i
];
12290 basic_block bb
= this_basic_block
;
12292 if (! dead_or_set_p (place
, piece
)
12293 && ! reg_bitfield_target_p (piece
,
12297 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12299 distribute_notes (new_note
, place
, place
,
12302 else if (! refers_to_regno_p (i
, i
+ 1,
12303 PATTERN (place
), 0)
12304 && ! find_regno_fusage (place
, USE
, i
))
12305 for (tem
= PREV_INSN (place
); ;
12306 tem
= PREV_INSN (tem
))
12308 if (! INSN_P (tem
))
12310 if (tem
== BB_HEAD (bb
))
12312 SET_BIT (refresh_blocks
,
12313 this_basic_block
->index
);
12318 if (dead_or_set_p (tem
, piece
)
12319 || reg_bitfield_target_p (piece
,
12323 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12338 /* Any other notes should not be present at this point in the
12340 gcc_unreachable ();
12345 XEXP (note
, 1) = REG_NOTES (place
);
12346 REG_NOTES (place
) = note
;
12348 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12349 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12350 && REG_P (XEXP (note
, 0)))
12351 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12355 if ((REG_NOTE_KIND (note
) == REG_DEAD
12356 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12357 && REG_P (XEXP (note
, 0)))
12358 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12360 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12361 REG_NOTE_KIND (note
),
12363 REG_NOTES (place2
));
12368 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12369 I3, I2, and I1 to new locations. This is also called to add a link
12370 pointing at I3 when I3's destination is changed. */
12373 distribute_links (rtx links
)
12375 rtx link
, next_link
;
12377 for (link
= links
; link
; link
= next_link
)
12383 next_link
= XEXP (link
, 1);
12385 /* If the insn that this link points to is a NOTE or isn't a single
12386 set, ignore it. In the latter case, it isn't clear what we
12387 can do other than ignore the link, since we can't tell which
12388 register it was for. Such links wouldn't be used by combine
12391 It is not possible for the destination of the target of the link to
12392 have been changed by combine. The only potential of this is if we
12393 replace I3, I2, and I1 by I3 and I2. But in that case the
12394 destination of I2 also remains unchanged. */
12396 if (NOTE_P (XEXP (link
, 0))
12397 || (set
= single_set (XEXP (link
, 0))) == 0)
12400 reg
= SET_DEST (set
);
12401 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12402 || GET_CODE (reg
) == STRICT_LOW_PART
)
12403 reg
= XEXP (reg
, 0);
12405 /* A LOG_LINK is defined as being placed on the first insn that uses
12406 a register and points to the insn that sets the register. Start
12407 searching at the next insn after the target of the link and stop
12408 when we reach a set of the register or the end of the basic block.
12410 Note that this correctly handles the link that used to point from
12411 I3 to I2. Also note that not much searching is typically done here
12412 since most links don't point very far away. */
12414 for (insn
= NEXT_INSN (XEXP (link
, 0));
12415 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12416 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12417 insn
= NEXT_INSN (insn
))
12418 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12420 if (reg_referenced_p (reg
, PATTERN (insn
)))
12424 else if (CALL_P (insn
)
12425 && find_reg_fusage (insn
, USE
, reg
))
12430 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
12433 /* If we found a place to put the link, place it there unless there
12434 is already a link to the same insn as LINK at that point. */
12440 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12441 if (XEXP (link2
, 0) == XEXP (link
, 0))
12446 XEXP (link
, 1) = LOG_LINKS (place
);
12447 LOG_LINKS (place
) = link
;
12449 /* Set added_links_insn to the earliest insn we added a
12451 if (added_links_insn
== 0
12452 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12453 added_links_insn
= place
;
12459 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12460 Check whether the expression pointer to by LOC is a register or
12461 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12462 Otherwise return zero. */
12465 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
12470 && (REG_P (x
) || MEM_P (x
))
12471 && ! reg_mentioned_p (x
, (rtx
) expr
))
12476 /* Check for any register or memory mentioned in EQUIV that is not
12477 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12478 of EXPR where some registers may have been replaced by constants. */
12481 unmentioned_reg_p (rtx equiv
, rtx expr
)
12483 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
12486 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12489 insn_cuid (rtx insn
)
12491 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12492 && NONJUMP_INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
)
12493 insn
= NEXT_INSN (insn
);
12495 gcc_assert (INSN_UID (insn
) <= max_uid_cuid
);
12497 return INSN_CUID (insn
);
12501 dump_combine_stats (FILE *file
)
12505 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12506 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12510 dump_combine_total_stats (FILE *file
)
12514 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12515 total_attempts
, total_merges
, total_extras
, total_successes
);