1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
86 #include "stor-layout.h"
90 #include "hard-reg-set.h"
93 #include "dominance.h"
96 #include "cfgcleanup.h"
97 #include "basic-block.h"
98 #include "insn-config.h"
99 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
104 #include "emit-rtl.h"
108 #include "insn-attr.h"
110 #include "diagnostic-core.h"
112 #include "insn-codes.h"
114 #include "rtlhooks-def.h"
116 #include "tree-pass.h"
118 #include "valtrack.h"
121 #include "rtl-iter.h"
123 /* Number of attempts to combine instructions in this function. */
125 static int combine_attempts
;
127 /* Number of attempts that got as far as substitution in this function. */
129 static int combine_merges
;
131 /* Number of instructions combined with added SETs in this function. */
133 static int combine_extras
;
135 /* Number of instructions combined in this function. */
137 static int combine_successes
;
139 /* Totals over entire compilation. */
141 static int total_attempts
, total_merges
, total_extras
, total_successes
;
143 /* combine_instructions may try to replace the right hand side of the
144 second instruction with the value of an associated REG_EQUAL note
145 before throwing it at try_combine. That is problematic when there
146 is a REG_DEAD note for a register used in the old right hand side
147 and can cause distribute_notes to do wrong things. This is the
148 second instruction if it has been so modified, null otherwise. */
150 static rtx_insn
*i2mod
;
152 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
154 static rtx i2mod_old_rhs
;
156 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
158 static rtx i2mod_new_rhs
;
160 typedef struct reg_stat_struct
{
161 /* Record last point of death of (hard or pseudo) register n. */
162 rtx_insn
*last_death
;
164 /* Record last point of modification of (hard or pseudo) register n. */
167 /* The next group of fields allows the recording of the last value assigned
168 to (hard or pseudo) register n. We use this information to see if an
169 operation being processed is redundant given a prior operation performed
170 on the register. For example, an `and' with a constant is redundant if
171 all the zero bits are already known to be turned off.
173 We use an approach similar to that used by cse, but change it in the
176 (1) We do not want to reinitialize at each label.
177 (2) It is useful, but not critical, to know the actual value assigned
178 to a register. Often just its form is helpful.
180 Therefore, we maintain the following fields:
182 last_set_value the last value assigned
183 last_set_label records the value of label_tick when the
184 register was assigned
185 last_set_table_tick records the value of label_tick when a
186 value using the register is assigned
187 last_set_invalid set to nonzero when it is not valid
188 to use the value of this register in some
191 To understand the usage of these tables, it is important to understand
192 the distinction between the value in last_set_value being valid and
193 the register being validly contained in some other expression in the
196 (The next two parameters are out of date).
198 reg_stat[i].last_set_value is valid if it is nonzero, and either
199 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
201 Register I may validly appear in any expression returned for the value
202 of another register if reg_n_sets[i] is 1. It may also appear in the
203 value for register J if reg_stat[j].last_set_invalid is zero, or
204 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
206 If an expression is found in the table containing a register which may
207 not validly appear in an expression, the register is replaced by
208 something that won't match, (clobber (const_int 0)). */
210 /* Record last value assigned to (hard or pseudo) register n. */
214 /* Record the value of label_tick when an expression involving register n
215 is placed in last_set_value. */
217 int last_set_table_tick
;
219 /* Record the value of label_tick when the value for register n is placed in
224 /* These fields are maintained in parallel with last_set_value and are
225 used to store the mode in which the register was last set, the bits
226 that were known to be zero when it was last set, and the number of
227 sign bits copies it was known to have when it was last set. */
229 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
230 char last_set_sign_bit_copies
;
231 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
233 /* Set nonzero if references to register n in expressions should not be
234 used. last_set_invalid is set nonzero when this register is being
235 assigned to and last_set_table_tick == label_tick. */
237 char last_set_invalid
;
239 /* Some registers that are set more than once and used in more than one
240 basic block are nevertheless always set in similar ways. For example,
241 a QImode register may be loaded from memory in two places on a machine
242 where byte loads zero extend.
244 We record in the following fields if a register has some leading bits
245 that are always equal to the sign bit, and what we know about the
246 nonzero bits of a register, specifically which bits are known to be
249 If an entry is zero, it means that we don't know anything special. */
251 unsigned char sign_bit_copies
;
253 unsigned HOST_WIDE_INT nonzero_bits
;
255 /* Record the value of the label_tick when the last truncation
256 happened. The field truncated_to_mode is only valid if
257 truncation_label == label_tick. */
259 int truncation_label
;
261 /* Record the last truncation seen for this register. If truncation
262 is not a nop to this mode we might be able to save an explicit
263 truncation if we know that value already contains a truncated
266 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
270 static vec
<reg_stat_type
> reg_stat
;
272 /* One plus the highest pseudo for which we track REG_N_SETS.
273 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
274 but during combine_split_insns new pseudos can be created. As we don't have
275 updated DF information in that case, it is hard to initialize the array
276 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
277 so instead of growing the arrays, just assume all newly created pseudos
278 during combine might be set multiple times. */
280 static unsigned int reg_n_sets_max
;
282 /* Record the luid of the last insn that invalidated memory
283 (anything that writes memory, and subroutine calls, but not pushes). */
285 static int mem_last_set
;
287 /* Record the luid of the last CALL_INSN
288 so we can tell whether a potential combination crosses any calls. */
290 static int last_call_luid
;
292 /* When `subst' is called, this is the insn that is being modified
293 (by combining in a previous insn). The PATTERN of this insn
294 is still the old pattern partially modified and it should not be
295 looked at, but this may be used to examine the successors of the insn
296 to judge whether a simplification is valid. */
298 static rtx_insn
*subst_insn
;
300 /* This is the lowest LUID that `subst' is currently dealing with.
301 get_last_value will not return a value if the register was set at or
302 after this LUID. If not for this mechanism, we could get confused if
303 I2 or I1 in try_combine were an insn that used the old value of a register
304 to obtain a new value. In that case, we might erroneously get the
305 new value of the register when we wanted the old one. */
307 static int subst_low_luid
;
309 /* This contains any hard registers that are used in newpat; reg_dead_at_p
310 must consider all these registers to be always live. */
312 static HARD_REG_SET newpat_used_regs
;
314 /* This is an insn to which a LOG_LINKS entry has been added. If this
315 insn is the earlier than I2 or I3, combine should rescan starting at
318 static rtx_insn
*added_links_insn
;
320 /* Basic block in which we are performing combines. */
321 static basic_block this_basic_block
;
322 static bool optimize_this_for_speed_p
;
325 /* Length of the currently allocated uid_insn_cost array. */
327 static int max_uid_known
;
329 /* The following array records the insn_rtx_cost for every insn
330 in the instruction stream. */
332 static int *uid_insn_cost
;
334 /* The following array records the LOG_LINKS for every insn in the
335 instruction stream as struct insn_link pointers. */
340 struct insn_link
*next
;
343 static struct insn_link
**uid_log_links
;
345 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
346 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
348 #define FOR_EACH_LOG_LINK(L, INSN) \
349 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
351 /* Links for LOG_LINKS are allocated from this obstack. */
353 static struct obstack insn_link_obstack
;
355 /* Allocate a link. */
357 static inline struct insn_link
*
358 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
361 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
362 sizeof (struct insn_link
));
369 /* Incremented for each basic block. */
371 static int label_tick
;
373 /* Reset to label_tick for each extended basic block in scanning order. */
375 static int label_tick_ebb_start
;
377 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
378 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
380 static machine_mode nonzero_bits_mode
;
382 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
383 be safely used. It is zero while computing them and after combine has
384 completed. This former test prevents propagating values based on
385 previously set values, which can be incorrect if a variable is modified
388 static int nonzero_sign_valid
;
391 /* Record one modification to rtl structure
392 to be undone by storing old_contents into *where. */
394 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
400 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
401 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
404 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
405 num_undo says how many are currently recorded.
407 other_insn is nonzero if we have modified some other insn in the process
408 of working on subst_insn. It must be verified too. */
414 rtx_insn
*other_insn
;
417 static struct undobuf undobuf
;
419 /* Number of times the pseudo being substituted for
420 was found and replaced. */
422 static int n_occurrences
;
424 static rtx
reg_nonzero_bits_for_combine (const_rtx
, machine_mode
, const_rtx
,
426 unsigned HOST_WIDE_INT
,
427 unsigned HOST_WIDE_INT
*);
428 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, machine_mode
, const_rtx
,
430 unsigned int, unsigned int *);
431 static void do_SUBST (rtx
*, rtx
);
432 static void do_SUBST_INT (int *, int);
433 static void init_reg_last (void);
434 static void setup_incoming_promotions (rtx_insn
*);
435 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
436 static int cant_combine_insn_p (rtx_insn
*);
437 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
438 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
439 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
440 static int contains_muldiv (rtx
);
441 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
443 static void undo_all (void);
444 static void undo_commit (void);
445 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
446 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
447 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
448 static rtx
simplify_if_then_else (rtx
);
449 static rtx
simplify_set (rtx
);
450 static rtx
simplify_logical (rtx
);
451 static rtx
expand_compound_operation (rtx
);
452 static const_rtx
expand_field_assignment (const_rtx
);
453 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
454 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
455 static rtx
extract_left_shift (rtx
, int);
456 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
457 unsigned HOST_WIDE_INT
*);
458 static rtx
canon_reg_for_combine (rtx
, rtx
);
459 static rtx
force_to_mode (rtx
, machine_mode
,
460 unsigned HOST_WIDE_INT
, int);
461 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
462 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
463 static int rtx_equal_for_field_assignment_p (rtx
, rtx
, bool = false);
464 static rtx
make_field_assignment (rtx
);
465 static rtx
apply_distributive_law (rtx
);
466 static rtx
distribute_and_simplify_rtx (rtx
, int);
467 static rtx
simplify_and_const_int_1 (machine_mode
, rtx
,
468 unsigned HOST_WIDE_INT
);
469 static rtx
simplify_and_const_int (rtx
, machine_mode
, rtx
,
470 unsigned HOST_WIDE_INT
);
471 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
472 HOST_WIDE_INT
, machine_mode
, int *);
473 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
474 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
476 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
477 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
478 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
480 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
481 static void update_table_tick (rtx
);
482 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
483 static void check_promoted_subreg (rtx_insn
*, rtx
);
484 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
485 static void record_dead_and_set_regs (rtx_insn
*);
486 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
487 static rtx
get_last_value (const_rtx
);
488 static int use_crosses_set_p (const_rtx
, int);
489 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
490 static int reg_dead_at_p (rtx
, rtx_insn
*);
491 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
492 static int reg_bitfield_target_p (rtx
, rtx
);
493 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
494 static void distribute_links (struct insn_link
*);
495 static void mark_used_regs_combine (rtx
);
496 static void record_promoted_value (rtx_insn
*, rtx
);
497 static bool unmentioned_reg_p (rtx
, rtx
);
498 static void record_truncated_values (rtx
*, void *);
499 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
500 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
503 /* It is not safe to use ordinary gen_lowpart in combine.
504 See comments in gen_lowpart_for_combine. */
505 #undef RTL_HOOKS_GEN_LOWPART
506 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
508 /* Our implementation of gen_lowpart never emits a new pseudo. */
509 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
510 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
512 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
513 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
515 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
516 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
518 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
519 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
521 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
524 /* Convenience wrapper for the canonicalize_comparison target hook.
525 Target hooks cannot use enum rtx_code. */
527 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
528 bool op0_preserve_value
)
530 int code_int
= (int)*code
;
531 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
532 *code
= (enum rtx_code
)code_int
;
535 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
536 PATTERN can not be split. Otherwise, it returns an insn sequence.
537 This is a wrapper around split_insns which ensures that the
538 reg_stat vector is made larger if the splitter creates a new
542 combine_split_insns (rtx pattern
, rtx_insn
*insn
)
547 ret
= split_insns (pattern
, insn
);
548 nregs
= max_reg_num ();
549 if (nregs
> reg_stat
.length ())
550 reg_stat
.safe_grow_cleared (nregs
);
554 /* This is used by find_single_use to locate an rtx in LOC that
555 contains exactly one use of DEST, which is typically either a REG
556 or CC0. It returns a pointer to the innermost rtx expression
557 containing DEST. Appearances of DEST that are being used to
558 totally replace it are not counted. */
561 find_single_use_1 (rtx dest
, rtx
*loc
)
564 enum rtx_code code
= GET_CODE (x
);
580 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
581 of a REG that occupies all of the REG, the insn uses DEST if
582 it is mentioned in the destination or the source. Otherwise, we
583 need just check the source. */
584 if (GET_CODE (SET_DEST (x
)) != CC0
585 && GET_CODE (SET_DEST (x
)) != PC
586 && !REG_P (SET_DEST (x
))
587 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
588 && REG_P (SUBREG_REG (SET_DEST (x
)))
589 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
590 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
591 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
592 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
595 return find_single_use_1 (dest
, &SET_SRC (x
));
599 return find_single_use_1 (dest
, &XEXP (x
, 0));
605 /* If it wasn't one of the common cases above, check each expression and
606 vector of this code. Look for a unique usage of DEST. */
608 fmt
= GET_RTX_FORMAT (code
);
609 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
613 if (dest
== XEXP (x
, i
)
614 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
615 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
618 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
621 result
= this_result
;
622 else if (this_result
)
623 /* Duplicate usage. */
626 else if (fmt
[i
] == 'E')
630 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
632 if (XVECEXP (x
, i
, j
) == dest
634 && REG_P (XVECEXP (x
, i
, j
))
635 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
638 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
641 result
= this_result
;
642 else if (this_result
)
652 /* See if DEST, produced in INSN, is used only a single time in the
653 sequel. If so, return a pointer to the innermost rtx expression in which
656 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
658 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
659 care about REG_DEAD notes or LOG_LINKS.
661 Otherwise, we find the single use by finding an insn that has a
662 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
663 only referenced once in that insn, we know that it must be the first
664 and last insn referencing DEST. */
667 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
672 struct insn_link
*link
;
676 next
= NEXT_INSN (insn
);
678 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
681 result
= find_single_use_1 (dest
, &PATTERN (next
));
690 bb
= BLOCK_FOR_INSN (insn
);
691 for (next
= NEXT_INSN (insn
);
692 next
&& BLOCK_FOR_INSN (next
) == bb
;
693 next
= NEXT_INSN (next
))
694 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
696 FOR_EACH_LOG_LINK (link
, next
)
697 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
702 result
= find_single_use_1 (dest
, &PATTERN (next
));
712 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
713 insn. The substitution can be undone by undo_all. If INTO is already
714 set to NEWVAL, do not record this change. Because computing NEWVAL might
715 also call SUBST, we have to compute it before we put anything into
719 do_SUBST (rtx
*into
, rtx newval
)
724 if (oldval
== newval
)
727 /* We'd like to catch as many invalid transformations here as
728 possible. Unfortunately, there are way too many mode changes
729 that are perfectly valid, so we'd waste too much effort for
730 little gain doing the checks here. Focus on catching invalid
731 transformations involving integer constants. */
732 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
733 && CONST_INT_P (newval
))
735 /* Sanity check that we're replacing oldval with a CONST_INT
736 that is a valid sign-extension for the original mode. */
737 gcc_assert (INTVAL (newval
)
738 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
740 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
741 CONST_INT is not valid, because after the replacement, the
742 original mode would be gone. Unfortunately, we can't tell
743 when do_SUBST is called to replace the operand thereof, so we
744 perform this test on oldval instead, checking whether an
745 invalid replacement took place before we got here. */
746 gcc_assert (!(GET_CODE (oldval
) == SUBREG
747 && CONST_INT_P (SUBREG_REG (oldval
))));
748 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
749 && CONST_INT_P (XEXP (oldval
, 0))));
753 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
755 buf
= XNEW (struct undo
);
757 buf
->kind
= UNDO_RTX
;
759 buf
->old_contents
.r
= oldval
;
762 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
765 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
767 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
768 for the value of a HOST_WIDE_INT value (including CONST_INT) is
772 do_SUBST_INT (int *into
, int newval
)
777 if (oldval
== newval
)
781 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
783 buf
= XNEW (struct undo
);
785 buf
->kind
= UNDO_INT
;
787 buf
->old_contents
.i
= oldval
;
790 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
793 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
795 /* Similar to SUBST, but just substitute the mode. This is used when
796 changing the mode of a pseudo-register, so that any other
797 references to the entry in the regno_reg_rtx array will change as
801 do_SUBST_MODE (rtx
*into
, machine_mode newval
)
804 machine_mode oldval
= GET_MODE (*into
);
806 if (oldval
== newval
)
810 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
812 buf
= XNEW (struct undo
);
814 buf
->kind
= UNDO_MODE
;
816 buf
->old_contents
.m
= oldval
;
817 adjust_reg_mode (*into
, newval
);
819 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
822 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
825 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
828 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
831 struct insn_link
* oldval
= *into
;
833 if (oldval
== newval
)
837 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
839 buf
= XNEW (struct undo
);
841 buf
->kind
= UNDO_LINKS
;
843 buf
->old_contents
.l
= oldval
;
846 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
849 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
852 /* Subroutine of try_combine. Determine whether the replacement patterns
853 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
854 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
855 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
856 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
857 of all the instructions can be estimated and the replacements are more
858 expensive than the original sequence. */
861 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
862 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
864 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
865 int new_i2_cost
, new_i3_cost
;
866 int old_cost
, new_cost
;
868 /* Lookup the original insn_rtx_costs. */
869 i2_cost
= INSN_COST (i2
);
870 i3_cost
= INSN_COST (i3
);
874 i1_cost
= INSN_COST (i1
);
877 i0_cost
= INSN_COST (i0
);
878 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
879 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
883 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
884 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
890 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
891 i1_cost
= i0_cost
= 0;
894 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
896 if (old_cost
&& i1
&& INSN_UID (i1
) == INSN_UID (i2
))
900 /* Calculate the replacement insn_rtx_costs. */
901 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
904 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
905 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
906 ? new_i2_cost
+ new_i3_cost
: 0;
910 new_cost
= new_i3_cost
;
914 if (undobuf
.other_insn
)
916 int old_other_cost
, new_other_cost
;
918 old_other_cost
= INSN_COST (undobuf
.other_insn
);
919 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
920 if (old_other_cost
> 0 && new_other_cost
> 0)
922 old_cost
+= old_other_cost
;
923 new_cost
+= new_other_cost
;
929 /* Disallow this combination if both new_cost and old_cost are greater than
930 zero, and new_cost is greater than old cost. */
931 int reject
= old_cost
> 0 && new_cost
> old_cost
;
935 fprintf (dump_file
, "%s combination of insns ",
936 reject
? "rejecting" : "allowing");
938 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
939 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
940 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
941 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
943 fprintf (dump_file
, "original costs ");
945 fprintf (dump_file
, "%d + ", i0_cost
);
946 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
947 fprintf (dump_file
, "%d + ", i1_cost
);
948 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
951 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
952 new_i2_cost
, new_i3_cost
, new_cost
);
954 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
960 /* Update the uid_insn_cost array with the replacement costs. */
961 INSN_COST (i2
) = new_i2_cost
;
962 INSN_COST (i3
) = new_i3_cost
;
974 /* Delete any insns that copy a register to itself. */
977 delete_noop_moves (void)
979 rtx_insn
*insn
, *next
;
982 FOR_EACH_BB_FN (bb
, cfun
)
984 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
986 next
= NEXT_INSN (insn
);
987 if (INSN_P (insn
) && noop_move_p (insn
))
990 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
992 delete_insn_and_edges (insn
);
999 /* Return false if we do not want to (or cannot) combine DEF. */
1001 can_combine_def_p (df_ref def
)
1003 /* Do not consider if it is pre/post modification in MEM. */
1004 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
1007 unsigned int regno
= DF_REF_REGNO (def
);
1009 /* Do not combine frame pointer adjustments. */
1010 if ((regno
== FRAME_POINTER_REGNUM
1011 && (!reload_completed
|| frame_pointer_needed
))
1012 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1013 || (regno
== HARD_FRAME_POINTER_REGNUM
1014 && (!reload_completed
|| frame_pointer_needed
))
1016 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1017 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
]))
1023 /* Return false if we do not want to (or cannot) combine USE. */
1025 can_combine_use_p (df_ref use
)
1027 /* Do not consider the usage of the stack pointer by function call. */
1028 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1034 /* Fill in log links field for all insns. */
1037 create_log_links (void)
1040 rtx_insn
**next_use
;
1044 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1046 /* Pass through each block from the end, recording the uses of each
1047 register and establishing log links when def is encountered.
1048 Note that we do not clear next_use array in order to save time,
1049 so we have to test whether the use is in the same basic block as def.
1051 There are a few cases below when we do not consider the definition or
1052 usage -- these are taken from original flow.c did. Don't ask me why it is
1053 done this way; I don't know and if it works, I don't want to know. */
1055 FOR_EACH_BB_FN (bb
, cfun
)
1057 FOR_BB_INSNS_REVERSE (bb
, insn
)
1059 if (!NONDEBUG_INSN_P (insn
))
1062 /* Log links are created only once. */
1063 gcc_assert (!LOG_LINKS (insn
));
1065 FOR_EACH_INSN_DEF (def
, insn
)
1067 unsigned int regno
= DF_REF_REGNO (def
);
1070 if (!next_use
[regno
])
1073 if (!can_combine_def_p (def
))
1076 use_insn
= next_use
[regno
];
1077 next_use
[regno
] = NULL
;
1079 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1084 We don't build a LOG_LINK for hard registers contained
1085 in ASM_OPERANDs. If these registers get replaced,
1086 we might wind up changing the semantics of the insn,
1087 even if reload can make what appear to be valid
1088 assignments later. */
1089 if (regno
< FIRST_PSEUDO_REGISTER
1090 && asm_noperands (PATTERN (use_insn
)) >= 0)
1093 /* Don't add duplicate links between instructions. */
1094 struct insn_link
*links
;
1095 FOR_EACH_LOG_LINK (links
, use_insn
)
1096 if (insn
== links
->insn
&& regno
== links
->regno
)
1100 LOG_LINKS (use_insn
)
1101 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1104 FOR_EACH_INSN_USE (use
, insn
)
1105 if (can_combine_use_p (use
))
1106 next_use
[DF_REF_REGNO (use
)] = insn
;
1113 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1114 true if we found a LOG_LINK that proves that A feeds B. This only works
1115 if there are no instructions between A and B which could have a link
1116 depending on A, since in that case we would not record a link for B.
1117 We also check the implicit dependency created by a cc0 setter/user
1121 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1123 struct insn_link
*links
;
1124 FOR_EACH_LOG_LINK (links
, b
)
1125 if (links
->insn
== a
)
1127 if (HAVE_cc0
&& sets_cc0_p (a
))
1132 /* Main entry point for combiner. F is the first insn of the function.
1133 NREGS is the first unused pseudo-reg number.
1135 Return nonzero if the combiner has turned an indirect jump
1136 instruction into a direct jump. */
1138 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1140 rtx_insn
*insn
, *next
;
1144 struct insn_link
*links
, *nextlinks
;
1146 basic_block last_bb
;
1148 int new_direct_jump_p
= 0;
1150 for (first
= f
; first
&& !INSN_P (first
); )
1151 first
= NEXT_INSN (first
);
1155 combine_attempts
= 0;
1158 combine_successes
= 0;
1160 rtl_hooks
= combine_rtl_hooks
;
1162 reg_stat
.safe_grow_cleared (nregs
);
1164 init_recog_no_volatile ();
1166 /* Allocate array for insn info. */
1167 max_uid_known
= get_max_uid ();
1168 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1169 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1170 gcc_obstack_init (&insn_link_obstack
);
1172 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1174 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1175 problems when, for example, we have j <<= 1 in a loop. */
1177 nonzero_sign_valid
= 0;
1178 label_tick
= label_tick_ebb_start
= 1;
1180 /* Scan all SETs and see if we can deduce anything about what
1181 bits are known to be zero for some registers and how many copies
1182 of the sign bit are known to exist for those registers.
1184 Also set any known values so that we can use it while searching
1185 for what bits are known to be set. */
1187 setup_incoming_promotions (first
);
1188 /* Allow the entry block and the first block to fall into the same EBB.
1189 Conceptually the incoming promotions are assigned to the entry block. */
1190 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1192 create_log_links ();
1193 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1195 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1200 if (!single_pred_p (this_basic_block
)
1201 || single_pred (this_basic_block
) != last_bb
)
1202 label_tick_ebb_start
= label_tick
;
1203 last_bb
= this_basic_block
;
1205 FOR_BB_INSNS (this_basic_block
, insn
)
1206 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1212 subst_low_luid
= DF_INSN_LUID (insn
);
1215 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1217 record_dead_and_set_regs (insn
);
1220 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1221 if (REG_NOTE_KIND (links
) == REG_INC
)
1222 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1226 /* Record the current insn_rtx_cost of this instruction. */
1227 if (NONJUMP_INSN_P (insn
))
1228 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1229 optimize_this_for_speed_p
);
1231 fprintf (dump_file
, "insn_cost %d: %d\n",
1232 INSN_UID (insn
), INSN_COST (insn
));
1236 nonzero_sign_valid
= 1;
1238 /* Now scan all the insns in forward order. */
1239 label_tick
= label_tick_ebb_start
= 1;
1241 setup_incoming_promotions (first
);
1242 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1243 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1245 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1247 rtx_insn
*last_combined_insn
= NULL
;
1248 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1253 if (!single_pred_p (this_basic_block
)
1254 || single_pred (this_basic_block
) != last_bb
)
1255 label_tick_ebb_start
= label_tick
;
1256 last_bb
= this_basic_block
;
1258 rtl_profile_for_bb (this_basic_block
);
1259 for (insn
= BB_HEAD (this_basic_block
);
1260 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1261 insn
= next
? next
: NEXT_INSN (insn
))
1264 if (!NONDEBUG_INSN_P (insn
))
1267 while (last_combined_insn
1268 && last_combined_insn
->deleted ())
1269 last_combined_insn
= PREV_INSN (last_combined_insn
);
1270 if (last_combined_insn
== NULL_RTX
1271 || BARRIER_P (last_combined_insn
)
1272 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1273 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1274 last_combined_insn
= insn
;
1276 /* See if we know about function return values before this
1277 insn based upon SUBREG flags. */
1278 check_promoted_subreg (insn
, PATTERN (insn
));
1280 /* See if we can find hardregs and subreg of pseudos in
1281 narrower modes. This could help turning TRUNCATEs
1283 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1285 /* Try this insn with each insn it links back to. */
1287 FOR_EACH_LOG_LINK (links
, insn
)
1288 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1289 NULL
, &new_direct_jump_p
,
1290 last_combined_insn
)) != 0)
1292 statistics_counter_event (cfun
, "two-insn combine", 1);
1296 /* Try each sequence of three linked insns ending with this one. */
1298 if (max_combine
>= 3)
1299 FOR_EACH_LOG_LINK (links
, insn
)
1301 rtx_insn
*link
= links
->insn
;
1303 /* If the linked insn has been replaced by a note, then there
1304 is no point in pursuing this chain any further. */
1308 FOR_EACH_LOG_LINK (nextlinks
, link
)
1309 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1310 NULL
, &new_direct_jump_p
,
1311 last_combined_insn
)) != 0)
1313 statistics_counter_event (cfun
, "three-insn combine", 1);
1319 /* Try to combine a jump insn that uses CC0
1320 with a preceding insn that sets CC0, and maybe with its
1321 logical predecessor as well.
1322 This is how we make decrement-and-branch insns.
1323 We need this special code because data flow connections
1324 via CC0 do not get entered in LOG_LINKS. */
1327 && (prev
= prev_nonnote_insn (insn
)) != 0
1328 && NONJUMP_INSN_P (prev
)
1329 && sets_cc0_p (PATTERN (prev
)))
1331 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1333 last_combined_insn
)) != 0)
1336 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1337 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1338 NULL
, &new_direct_jump_p
,
1339 last_combined_insn
)) != 0)
1343 /* Do the same for an insn that explicitly references CC0. */
1344 if (NONJUMP_INSN_P (insn
)
1345 && (prev
= prev_nonnote_insn (insn
)) != 0
1346 && NONJUMP_INSN_P (prev
)
1347 && sets_cc0_p (PATTERN (prev
))
1348 && GET_CODE (PATTERN (insn
)) == SET
1349 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1351 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1353 last_combined_insn
)) != 0)
1356 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1357 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1358 NULL
, &new_direct_jump_p
,
1359 last_combined_insn
)) != 0)
1363 /* Finally, see if any of the insns that this insn links to
1364 explicitly references CC0. If so, try this insn, that insn,
1365 and its predecessor if it sets CC0. */
1366 FOR_EACH_LOG_LINK (links
, insn
)
1367 if (NONJUMP_INSN_P (links
->insn
)
1368 && GET_CODE (PATTERN (links
->insn
)) == SET
1369 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1370 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1371 && NONJUMP_INSN_P (prev
)
1372 && sets_cc0_p (PATTERN (prev
))
1373 && (next
= try_combine (insn
, links
->insn
,
1374 prev
, NULL
, &new_direct_jump_p
,
1375 last_combined_insn
)) != 0)
1379 /* Try combining an insn with two different insns whose results it
1381 if (max_combine
>= 3)
1382 FOR_EACH_LOG_LINK (links
, insn
)
1383 for (nextlinks
= links
->next
; nextlinks
;
1384 nextlinks
= nextlinks
->next
)
1385 if ((next
= try_combine (insn
, links
->insn
,
1386 nextlinks
->insn
, NULL
,
1388 last_combined_insn
)) != 0)
1391 statistics_counter_event (cfun
, "three-insn combine", 1);
1395 /* Try four-instruction combinations. */
1396 if (max_combine
>= 4)
1397 FOR_EACH_LOG_LINK (links
, insn
)
1399 struct insn_link
*next1
;
1400 rtx_insn
*link
= links
->insn
;
1402 /* If the linked insn has been replaced by a note, then there
1403 is no point in pursuing this chain any further. */
1407 FOR_EACH_LOG_LINK (next1
, link
)
1409 rtx_insn
*link1
= next1
->insn
;
1412 /* I0 -> I1 -> I2 -> I3. */
1413 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1414 if ((next
= try_combine (insn
, link
, link1
,
1417 last_combined_insn
)) != 0)
1419 statistics_counter_event (cfun
, "four-insn combine", 1);
1422 /* I0, I1 -> I2, I2 -> I3. */
1423 for (nextlinks
= next1
->next
; nextlinks
;
1424 nextlinks
= nextlinks
->next
)
1425 if ((next
= try_combine (insn
, link
, link1
,
1428 last_combined_insn
)) != 0)
1430 statistics_counter_event (cfun
, "four-insn combine", 1);
1435 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1437 rtx_insn
*link1
= next1
->insn
;
1440 /* I0 -> I2; I1, I2 -> I3. */
1441 FOR_EACH_LOG_LINK (nextlinks
, link
)
1442 if ((next
= try_combine (insn
, link
, link1
,
1445 last_combined_insn
)) != 0)
1447 statistics_counter_event (cfun
, "four-insn combine", 1);
1450 /* I0 -> I1; I1, I2 -> I3. */
1451 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1452 if ((next
= try_combine (insn
, link
, link1
,
1455 last_combined_insn
)) != 0)
1457 statistics_counter_event (cfun
, "four-insn combine", 1);
1463 /* Try this insn with each REG_EQUAL note it links back to. */
1464 FOR_EACH_LOG_LINK (links
, insn
)
1467 rtx_insn
*temp
= links
->insn
;
1468 if ((set
= single_set (temp
)) != 0
1469 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1470 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1471 /* Avoid using a register that may already been marked
1472 dead by an earlier instruction. */
1473 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1474 && (GET_MODE (note
) == VOIDmode
1475 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1476 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1478 /* Temporarily replace the set's source with the
1479 contents of the REG_EQUAL note. The insn will
1480 be deleted or recognized by try_combine. */
1481 rtx orig
= SET_SRC (set
);
1482 SET_SRC (set
) = note
;
1484 i2mod_old_rhs
= copy_rtx (orig
);
1485 i2mod_new_rhs
= copy_rtx (note
);
1486 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1488 last_combined_insn
);
1492 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1495 SET_SRC (set
) = orig
;
1500 record_dead_and_set_regs (insn
);
1507 default_rtl_profile ();
1509 new_direct_jump_p
|= purge_all_dead_edges ();
1510 delete_noop_moves ();
1513 obstack_free (&insn_link_obstack
, NULL
);
1514 free (uid_log_links
);
1515 free (uid_insn_cost
);
1516 reg_stat
.release ();
1519 struct undo
*undo
, *next
;
1520 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1528 total_attempts
+= combine_attempts
;
1529 total_merges
+= combine_merges
;
1530 total_extras
+= combine_extras
;
1531 total_successes
+= combine_successes
;
1533 nonzero_sign_valid
= 0;
1534 rtl_hooks
= general_rtl_hooks
;
1536 /* Make recognizer allow volatile MEMs again. */
1539 return new_direct_jump_p
;
1542 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1545 init_reg_last (void)
1550 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1551 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1554 /* Set up any promoted values for incoming argument registers. */
1557 setup_incoming_promotions (rtx_insn
*first
)
1560 bool strictly_local
= false;
1562 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1563 arg
= DECL_CHAIN (arg
))
1565 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1567 machine_mode mode1
, mode2
, mode3
, mode4
;
1569 /* Only continue if the incoming argument is in a register. */
1573 /* Determine, if possible, whether all call sites of the current
1574 function lie within the current compilation unit. (This does
1575 take into account the exporting of a function via taking its
1576 address, and so forth.) */
1577 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1579 /* The mode and signedness of the argument before any promotions happen
1580 (equal to the mode of the pseudo holding it at that stage). */
1581 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1582 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1584 /* The mode and signedness of the argument after any source language and
1585 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1586 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1587 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1589 /* The mode and signedness of the argument as it is actually passed,
1590 see assign_parm_setup_reg in function.c. */
1591 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns3
,
1592 TREE_TYPE (cfun
->decl
), 0);
1594 /* The mode of the register in which the argument is being passed. */
1595 mode4
= GET_MODE (reg
);
1597 /* Eliminate sign extensions in the callee when:
1598 (a) A mode promotion has occurred; */
1601 /* (b) The mode of the register is the same as the mode of
1602 the argument as it is passed; */
1605 /* (c) There's no language level extension; */
1608 /* (c.1) All callers are from the current compilation unit. If that's
1609 the case we don't have to rely on an ABI, we only have to know
1610 what we're generating right now, and we know that we will do the
1611 mode1 to mode2 promotion with the given sign. */
1612 else if (!strictly_local
)
1614 /* (c.2) The combination of the two promotions is useful. This is
1615 true when the signs match, or if the first promotion is unsigned.
1616 In the later case, (sign_extend (zero_extend x)) is the same as
1617 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1623 /* Record that the value was promoted from mode1 to mode3,
1624 so that any sign extension at the head of the current
1625 function may be eliminated. */
1626 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1627 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1628 record_value_for_reg (reg
, first
, x
);
1632 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1633 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1634 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1635 because some machines (maybe most) will actually do the sign-extension and
1636 this is the conservative approach.
1638 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1642 sign_extend_short_imm (rtx src
, machine_mode mode
, unsigned int prec
)
1644 if (GET_MODE_PRECISION (mode
) < prec
1645 && CONST_INT_P (src
)
1647 && val_signbit_known_set_p (mode
, INTVAL (src
)))
1648 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (mode
));
1654 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1658 update_rsp_from_reg_equal (reg_stat_type
*rsp
, rtx_insn
*insn
, const_rtx set
,
1661 rtx reg_equal_note
= insn
? find_reg_equal_equiv_note (insn
) : NULL_RTX
;
1662 unsigned HOST_WIDE_INT bits
= 0;
1663 rtx reg_equal
= NULL
, src
= SET_SRC (set
);
1664 unsigned int num
= 0;
1667 reg_equal
= XEXP (reg_equal_note
, 0);
1669 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1670 src
= sign_extend_short_imm (src
, GET_MODE (x
), BITS_PER_WORD
);
1672 reg_equal
= sign_extend_short_imm (reg_equal
, GET_MODE (x
), BITS_PER_WORD
);
1675 /* Don't call nonzero_bits if it cannot change anything. */
1676 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1678 bits
= nonzero_bits (src
, nonzero_bits_mode
);
1679 if (reg_equal
&& bits
)
1680 bits
&= nonzero_bits (reg_equal
, nonzero_bits_mode
);
1681 rsp
->nonzero_bits
|= bits
;
1684 /* Don't call num_sign_bit_copies if it cannot change anything. */
1685 if (rsp
->sign_bit_copies
!= 1)
1687 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1688 if (reg_equal
&& num
!= GET_MODE_PRECISION (GET_MODE (x
)))
1690 unsigned int numeq
= num_sign_bit_copies (reg_equal
, GET_MODE (x
));
1691 if (num
== 0 || numeq
> num
)
1694 if (rsp
->sign_bit_copies
== 0 || num
< rsp
->sign_bit_copies
)
1695 rsp
->sign_bit_copies
= num
;
1699 /* Called via note_stores. If X is a pseudo that is narrower than
1700 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1702 If we are setting only a portion of X and we can't figure out what
1703 portion, assume all bits will be used since we don't know what will
1706 Similarly, set how many bits of X are known to be copies of the sign bit
1707 at all locations in the function. This is the smallest number implied
1711 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1713 rtx_insn
*insn
= (rtx_insn
*) data
;
1716 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1717 /* If this register is undefined at the start of the file, we can't
1718 say what its contents were. */
1719 && ! REGNO_REG_SET_P
1720 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1721 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1723 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1725 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1727 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1728 rsp
->sign_bit_copies
= 1;
1732 /* If this register is being initialized using itself, and the
1733 register is uninitialized in this basic block, and there are
1734 no LOG_LINKS which set the register, then part of the
1735 register is uninitialized. In that case we can't assume
1736 anything about the number of nonzero bits.
1738 ??? We could do better if we checked this in
1739 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1740 could avoid making assumptions about the insn which initially
1741 sets the register, while still using the information in other
1742 insns. We would have to be careful to check every insn
1743 involved in the combination. */
1746 && reg_referenced_p (x
, PATTERN (insn
))
1747 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1750 struct insn_link
*link
;
1752 FOR_EACH_LOG_LINK (link
, insn
)
1753 if (dead_or_set_p (link
->insn
, x
))
1757 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1758 rsp
->sign_bit_copies
= 1;
1763 /* If this is a complex assignment, see if we can convert it into a
1764 simple assignment. */
1765 set
= expand_field_assignment (set
);
1767 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1768 set what we know about X. */
1770 if (SET_DEST (set
) == x
1771 || (paradoxical_subreg_p (SET_DEST (set
))
1772 && SUBREG_REG (SET_DEST (set
)) == x
))
1773 update_rsp_from_reg_equal (rsp
, insn
, set
, x
);
1776 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1777 rsp
->sign_bit_copies
= 1;
1782 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1783 optionally insns that were previously combined into I3 or that will be
1784 combined into the merger of INSN and I3. The order is PRED, PRED2,
1785 INSN, SUCC, SUCC2, I3.
1787 Return 0 if the combination is not allowed for any reason.
1789 If the combination is allowed, *PDEST will be set to the single
1790 destination of INSN and *PSRC to the single source, and this function
1794 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1795 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1796 rtx
*pdest
, rtx
*psrc
)
1805 bool all_adjacent
= true;
1806 int (*is_volatile_p
) (const_rtx
);
1812 if (next_active_insn (succ2
) != i3
)
1813 all_adjacent
= false;
1814 if (next_active_insn (succ
) != succ2
)
1815 all_adjacent
= false;
1817 else if (next_active_insn (succ
) != i3
)
1818 all_adjacent
= false;
1819 if (next_active_insn (insn
) != succ
)
1820 all_adjacent
= false;
1822 else if (next_active_insn (insn
) != i3
)
1823 all_adjacent
= false;
1825 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1826 or a PARALLEL consisting of such a SET and CLOBBERs.
1828 If INSN has CLOBBER parallel parts, ignore them for our processing.
1829 By definition, these happen during the execution of the insn. When it
1830 is merged with another insn, all bets are off. If they are, in fact,
1831 needed and aren't also supplied in I3, they may be added by
1832 recog_for_combine. Otherwise, it won't match.
1834 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1837 Get the source and destination of INSN. If more than one, can't
1840 if (GET_CODE (PATTERN (insn
)) == SET
)
1841 set
= PATTERN (insn
);
1842 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1843 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1845 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1847 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1849 switch (GET_CODE (elt
))
1851 /* This is important to combine floating point insns
1852 for the SH4 port. */
1854 /* Combining an isolated USE doesn't make sense.
1855 We depend here on combinable_i3pat to reject them. */
1856 /* The code below this loop only verifies that the inputs of
1857 the SET in INSN do not change. We call reg_set_between_p
1858 to verify that the REG in the USE does not change between
1860 If the USE in INSN was for a pseudo register, the matching
1861 insn pattern will likely match any register; combining this
1862 with any other USE would only be safe if we knew that the
1863 used registers have identical values, or if there was
1864 something to tell them apart, e.g. different modes. For
1865 now, we forgo such complicated tests and simply disallow
1866 combining of USES of pseudo registers with any other USE. */
1867 if (REG_P (XEXP (elt
, 0))
1868 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1870 rtx i3pat
= PATTERN (i3
);
1871 int i
= XVECLEN (i3pat
, 0) - 1;
1872 unsigned int regno
= REGNO (XEXP (elt
, 0));
1876 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1878 if (GET_CODE (i3elt
) == USE
1879 && REG_P (XEXP (i3elt
, 0))
1880 && (REGNO (XEXP (i3elt
, 0)) == regno
1881 ? reg_set_between_p (XEXP (elt
, 0),
1882 PREV_INSN (insn
), i3
)
1883 : regno
>= FIRST_PSEUDO_REGISTER
))
1890 /* We can ignore CLOBBERs. */
1895 /* Ignore SETs whose result isn't used but not those that
1896 have side-effects. */
1897 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1898 && insn_nothrow_p (insn
)
1899 && !side_effects_p (elt
))
1902 /* If we have already found a SET, this is a second one and
1903 so we cannot combine with this insn. */
1911 /* Anything else means we can't combine. */
1917 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1918 so don't do anything with it. */
1919 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1928 /* The simplification in expand_field_assignment may call back to
1929 get_last_value, so set safe guard here. */
1930 subst_low_luid
= DF_INSN_LUID (insn
);
1932 set
= expand_field_assignment (set
);
1933 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1935 /* Do not eliminate user-specified register if it is in an
1936 asm input because we may break the register asm usage defined
1937 in GCC manual if allow to do so.
1938 Be aware that this may cover more cases than we expect but this
1939 should be harmless. */
1940 if (REG_P (dest
) && REG_USERVAR_P (dest
) && HARD_REGISTER_P (dest
)
1941 && extract_asm_operands (PATTERN (i3
)))
1944 /* Don't eliminate a store in the stack pointer. */
1945 if (dest
== stack_pointer_rtx
1946 /* Don't combine with an insn that sets a register to itself if it has
1947 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1948 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1949 /* Can't merge an ASM_OPERANDS. */
1950 || GET_CODE (src
) == ASM_OPERANDS
1951 /* Can't merge a function call. */
1952 || GET_CODE (src
) == CALL
1953 /* Don't eliminate a function call argument. */
1955 && (find_reg_fusage (i3
, USE
, dest
)
1957 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1958 && global_regs
[REGNO (dest
)])))
1959 /* Don't substitute into an incremented register. */
1960 || FIND_REG_INC_NOTE (i3
, dest
)
1961 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1962 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1963 /* Don't substitute into a non-local goto, this confuses CFG. */
1964 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1965 /* Make sure that DEST is not used after SUCC but before I3. */
1968 && (reg_used_between_p (dest
, succ2
, i3
)
1969 || reg_used_between_p (dest
, succ
, succ2
)))
1970 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1971 /* Make sure that the value that is to be substituted for the register
1972 does not use any registers whose values alter in between. However,
1973 If the insns are adjacent, a use can't cross a set even though we
1974 think it might (this can happen for a sequence of insns each setting
1975 the same destination; last_set of that register might point to
1976 a NOTE). If INSN has a REG_EQUIV note, the register is always
1977 equivalent to the memory so the substitution is valid even if there
1978 are intervening stores. Also, don't move a volatile asm or
1979 UNSPEC_VOLATILE across any other insns. */
1982 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1983 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1984 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1985 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1986 /* Don't combine across a CALL_INSN, because that would possibly
1987 change whether the life span of some REGs crosses calls or not,
1988 and it is a pain to update that information.
1989 Exception: if source is a constant, moving it later can't hurt.
1990 Accept that as a special case. */
1991 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1994 /* DEST must either be a REG or CC0. */
1997 /* If register alignment is being enforced for multi-word items in all
1998 cases except for parameters, it is possible to have a register copy
1999 insn referencing a hard register that is not allowed to contain the
2000 mode being copied and which would not be valid as an operand of most
2001 insns. Eliminate this problem by not combining with such an insn.
2003 Also, on some machines we don't want to extend the life of a hard
2007 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
2008 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
2009 /* Don't extend the life of a hard register unless it is
2010 user variable (if we have few registers) or it can't
2011 fit into the desired register (meaning something special
2013 Also avoid substituting a return register into I3, because
2014 reload can't handle a conflict with constraints of other
2016 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
2017 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
2020 else if (GET_CODE (dest
) != CC0
)
2024 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
2025 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
2026 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
2028 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
2030 /* If the clobber represents an earlyclobber operand, we must not
2031 substitute an expression containing the clobbered register.
2032 As we do not analyze the constraint strings here, we have to
2033 make the conservative assumption. However, if the register is
2034 a fixed hard reg, the clobber cannot represent any operand;
2035 we leave it up to the machine description to either accept or
2036 reject use-and-clobber patterns. */
2038 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2039 || !fixed_regs
[REGNO (reg
)])
2040 if (reg_overlap_mentioned_p (reg
, src
))
2044 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2045 or not), reject, unless nothing volatile comes between it and I3 */
2047 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
2049 /* Make sure neither succ nor succ2 contains a volatile reference. */
2050 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
2052 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
2054 /* We'll check insns between INSN and I3 below. */
2057 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2058 to be an explicit register variable, and was chosen for a reason. */
2060 if (GET_CODE (src
) == ASM_OPERANDS
2061 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2064 /* If INSN contains volatile references (specifically volatile MEMs),
2065 we cannot combine across any other volatile references.
2066 Even if INSN doesn't contain volatile references, any intervening
2067 volatile insn might affect machine state. */
2069 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2073 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2074 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2077 /* If INSN contains an autoincrement or autodecrement, make sure that
2078 register is not used between there and I3, and not already used in
2079 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2080 Also insist that I3 not be a jump; if it were one
2081 and the incremented register were spilled, we would lose. */
2084 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2085 if (REG_NOTE_KIND (link
) == REG_INC
2087 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2088 || (pred
!= NULL_RTX
2089 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2090 || (pred2
!= NULL_RTX
2091 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2092 || (succ
!= NULL_RTX
2093 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2094 || (succ2
!= NULL_RTX
2095 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2096 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2100 /* Don't combine an insn that follows a CC0-setting insn.
2101 An insn that uses CC0 must not be separated from the one that sets it.
2102 We do, however, allow I2 to follow a CC0-setting insn if that insn
2103 is passed as I1; in that case it will be deleted also.
2104 We also allow combining in this case if all the insns are adjacent
2105 because that would leave the two CC0 insns adjacent as well.
2106 It would be more logical to test whether CC0 occurs inside I1 or I2,
2107 but that would be much slower, and this ought to be equivalent. */
2111 p
= prev_nonnote_insn (insn
);
2112 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2117 /* If we get here, we have passed all the tests and the combination is
2126 /* LOC is the location within I3 that contains its pattern or the component
2127 of a PARALLEL of the pattern. We validate that it is valid for combining.
2129 One problem is if I3 modifies its output, as opposed to replacing it
2130 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2131 doing so would produce an insn that is not equivalent to the original insns.
2135 (set (reg:DI 101) (reg:DI 100))
2136 (set (subreg:SI (reg:DI 101) 0) <foo>)
2138 This is NOT equivalent to:
2140 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2141 (set (reg:DI 101) (reg:DI 100))])
2143 Not only does this modify 100 (in which case it might still be valid
2144 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2146 We can also run into a problem if I2 sets a register that I1
2147 uses and I1 gets directly substituted into I3 (not via I2). In that
2148 case, we would be getting the wrong value of I2DEST into I3, so we
2149 must reject the combination. This case occurs when I2 and I1 both
2150 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2151 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2152 of a SET must prevent combination from occurring. The same situation
2153 can occur for I0, in which case I0_NOT_IN_SRC is set.
2155 Before doing the above check, we first try to expand a field assignment
2156 into a set of logical operations.
2158 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2159 we place a register that is both set and used within I3. If more than one
2160 such register is detected, we fail.
2162 Return 1 if the combination is valid, zero otherwise. */
2165 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2166 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2170 if (GET_CODE (x
) == SET
)
2173 rtx dest
= SET_DEST (set
);
2174 rtx src
= SET_SRC (set
);
2175 rtx inner_dest
= dest
;
2178 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2179 || GET_CODE (inner_dest
) == SUBREG
2180 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2181 inner_dest
= XEXP (inner_dest
, 0);
2183 /* Check for the case where I3 modifies its output, as discussed
2184 above. We don't want to prevent pseudos from being combined
2185 into the address of a MEM, so only prevent the combination if
2186 i1 or i2 set the same MEM. */
2187 if ((inner_dest
!= dest
&&
2188 (!MEM_P (inner_dest
)
2189 || rtx_equal_p (i2dest
, inner_dest
)
2190 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2191 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2192 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2193 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2194 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2196 /* This is the same test done in can_combine_p except we can't test
2197 all_adjacent; we don't have to, since this instruction will stay
2198 in place, thus we are not considering increasing the lifetime of
2201 Also, if this insn sets a function argument, combining it with
2202 something that might need a spill could clobber a previous
2203 function argument; the all_adjacent test in can_combine_p also
2204 checks this; here, we do a more specific test for this case. */
2206 || (REG_P (inner_dest
)
2207 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2208 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2209 GET_MODE (inner_dest
))))
2210 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2211 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2214 /* If DEST is used in I3, it is being killed in this insn, so
2215 record that for later. We have to consider paradoxical
2216 subregs here, since they kill the whole register, but we
2217 ignore partial subregs, STRICT_LOW_PART, etc.
2218 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2219 STACK_POINTER_REGNUM, since these are always considered to be
2220 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2222 if (GET_CODE (subdest
) == SUBREG
2223 && (GET_MODE_SIZE (GET_MODE (subdest
))
2224 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2225 subdest
= SUBREG_REG (subdest
);
2228 && reg_referenced_p (subdest
, PATTERN (i3
))
2229 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2230 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2231 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2233 && (FRAME_POINTER_REGNUM
== ARG_POINTER_REGNUM
2234 || (REGNO (subdest
) != ARG_POINTER_REGNUM
2235 || ! fixed_regs
[REGNO (subdest
)]))
2236 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2238 if (*pi3dest_killed
)
2241 *pi3dest_killed
= subdest
;
2245 else if (GET_CODE (x
) == PARALLEL
)
2249 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2250 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2251 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2258 /* Return 1 if X is an arithmetic expression that contains a multiplication
2259 and division. We don't count multiplications by powers of two here. */
2262 contains_muldiv (rtx x
)
2264 switch (GET_CODE (x
))
2266 case MOD
: case DIV
: case UMOD
: case UDIV
:
2270 return ! (CONST_INT_P (XEXP (x
, 1))
2271 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2274 return contains_muldiv (XEXP (x
, 0))
2275 || contains_muldiv (XEXP (x
, 1));
2278 return contains_muldiv (XEXP (x
, 0));
2284 /* Determine whether INSN can be used in a combination. Return nonzero if
2285 not. This is used in try_combine to detect early some cases where we
2286 can't perform combinations. */
2289 cant_combine_insn_p (rtx_insn
*insn
)
2294 /* If this isn't really an insn, we can't do anything.
2295 This can occur when flow deletes an insn that it has merged into an
2296 auto-increment address. */
2297 if (! INSN_P (insn
))
2300 /* Never combine loads and stores involving hard regs that are likely
2301 to be spilled. The register allocator can usually handle such
2302 reg-reg moves by tying. If we allow the combiner to make
2303 substitutions of likely-spilled regs, reload might die.
2304 As an exception, we allow combinations involving fixed regs; these are
2305 not available to the register allocator so there's no risk involved. */
2307 set
= single_set (insn
);
2310 src
= SET_SRC (set
);
2311 dest
= SET_DEST (set
);
2312 if (GET_CODE (src
) == SUBREG
)
2313 src
= SUBREG_REG (src
);
2314 if (GET_CODE (dest
) == SUBREG
)
2315 dest
= SUBREG_REG (dest
);
2316 if (REG_P (src
) && REG_P (dest
)
2317 && ((HARD_REGISTER_P (src
)
2318 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2319 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2320 || (HARD_REGISTER_P (dest
)
2321 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2322 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2328 struct likely_spilled_retval_info
2330 unsigned regno
, nregs
;
2334 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2335 hard registers that are known to be written to / clobbered in full. */
2337 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2339 struct likely_spilled_retval_info
*const info
=
2340 (struct likely_spilled_retval_info
*) data
;
2341 unsigned regno
, nregs
;
2344 if (!REG_P (XEXP (set
, 0)))
2347 if (regno
>= info
->regno
+ info
->nregs
)
2349 nregs
= REG_NREGS (x
);
2350 if (regno
+ nregs
<= info
->regno
)
2352 new_mask
= (2U << (nregs
- 1)) - 1;
2353 if (regno
< info
->regno
)
2354 new_mask
>>= info
->regno
- regno
;
2356 new_mask
<<= regno
- info
->regno
;
2357 info
->mask
&= ~new_mask
;
2360 /* Return nonzero iff part of the return value is live during INSN, and
2361 it is likely spilled. This can happen when more than one insn is needed
2362 to copy the return value, e.g. when we consider to combine into the
2363 second copy insn for a complex value. */
2366 likely_spilled_retval_p (rtx_insn
*insn
)
2368 rtx_insn
*use
= BB_END (this_basic_block
);
2371 unsigned regno
, nregs
;
2372 /* We assume here that no machine mode needs more than
2373 32 hard registers when the value overlaps with a register
2374 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2376 struct likely_spilled_retval_info info
;
2378 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2380 reg
= XEXP (PATTERN (use
), 0);
2381 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2383 regno
= REGNO (reg
);
2384 nregs
= REG_NREGS (reg
);
2387 mask
= (2U << (nregs
- 1)) - 1;
2389 /* Disregard parts of the return value that are set later. */
2393 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2395 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2398 /* Check if any of the (probably) live return value registers is
2403 if ((mask
& 1 << nregs
)
2404 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2410 /* Adjust INSN after we made a change to its destination.
2412 Changing the destination can invalidate notes that say something about
2413 the results of the insn and a LOG_LINK pointing to the insn. */
2416 adjust_for_new_dest (rtx_insn
*insn
)
2418 /* For notes, be conservative and simply remove them. */
2419 remove_reg_equal_equiv_notes (insn
);
2421 /* The new insn will have a destination that was previously the destination
2422 of an insn just above it. Call distribute_links to make a LOG_LINK from
2423 the next use of that destination. */
2425 rtx set
= single_set (insn
);
2428 rtx reg
= SET_DEST (set
);
2430 while (GET_CODE (reg
) == ZERO_EXTRACT
2431 || GET_CODE (reg
) == STRICT_LOW_PART
2432 || GET_CODE (reg
) == SUBREG
)
2433 reg
= XEXP (reg
, 0);
2434 gcc_assert (REG_P (reg
));
2436 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2438 df_insn_rescan (insn
);
2441 /* Return TRUE if combine can reuse reg X in mode MODE.
2442 ADDED_SETS is nonzero if the original set is still required. */
2444 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2452 /* Allow hard registers if the new mode is legal, and occupies no more
2453 registers than the old mode. */
2454 if (regno
< FIRST_PSEUDO_REGISTER
)
2455 return (HARD_REGNO_MODE_OK (regno
, mode
)
2456 && REG_NREGS (x
) >= hard_regno_nregs
[regno
][mode
]);
2458 /* Or a pseudo that is only used once. */
2459 return (regno
< reg_n_sets_max
2460 && REG_N_SETS (regno
) == 1
2462 && !REG_USERVAR_P (x
));
2466 /* Check whether X, the destination of a set, refers to part of
2467 the register specified by REG. */
2470 reg_subword_p (rtx x
, rtx reg
)
2472 /* Check that reg is an integer mode register. */
2473 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2476 if (GET_CODE (x
) == STRICT_LOW_PART
2477 || GET_CODE (x
) == ZERO_EXTRACT
)
2480 return GET_CODE (x
) == SUBREG
2481 && SUBREG_REG (x
) == reg
2482 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2485 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2486 Note that the INSN should be deleted *after* removing dead edges, so
2487 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2488 but not for a (set (pc) (label_ref FOO)). */
2491 update_cfg_for_uncondjump (rtx_insn
*insn
)
2493 basic_block bb
= BLOCK_FOR_INSN (insn
);
2494 gcc_assert (BB_END (bb
) == insn
);
2496 purge_dead_edges (bb
);
2499 if (EDGE_COUNT (bb
->succs
) == 1)
2503 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2505 /* Remove barriers from the footer if there are any. */
2506 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2507 if (BARRIER_P (insn
))
2509 if (PREV_INSN (insn
))
2510 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2512 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2513 if (NEXT_INSN (insn
))
2514 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2516 else if (LABEL_P (insn
))
2521 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2522 by an arbitrary number of CLOBBERs. */
2524 is_parallel_of_n_reg_sets (rtx pat
, int n
)
2526 if (GET_CODE (pat
) != PARALLEL
)
2529 int len
= XVECLEN (pat
, 0);
2534 for (i
= 0; i
< n
; i
++)
2535 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2536 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2538 for ( ; i
< len
; i
++)
2539 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
2546 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2547 CLOBBERs), can be split into individual SETs in that order, without
2548 changing semantics. */
2550 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2552 if (!insn_nothrow_p (insn
))
2555 rtx pat
= PATTERN (insn
);
2558 for (i
= 0; i
< n
; i
++)
2560 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2563 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2565 for (j
= i
+ 1; j
< n
; j
++)
2566 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2574 /* Try to combine the insns I0, I1 and I2 into I3.
2575 Here I0, I1 and I2 appear earlier than I3.
2576 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2579 If we are combining more than two insns and the resulting insn is not
2580 recognized, try splitting it into two insns. If that happens, I2 and I3
2581 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2582 Otherwise, I0, I1 and I2 are pseudo-deleted.
2584 Return 0 if the combination does not work. Then nothing is changed.
2585 If we did the combination, return the insn at which combine should
2588 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2589 new direct jump instruction.
2591 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2592 been I3 passed to an earlier try_combine within the same basic
2596 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2597 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2599 /* New patterns for I3 and I2, respectively. */
2600 rtx newpat
, newi2pat
= 0;
2601 rtvec newpat_vec_with_clobbers
= 0;
2602 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2603 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2605 int added_sets_0
, added_sets_1
, added_sets_2
;
2606 /* Total number of SETs to put into I3. */
2608 /* Nonzero if I2's or I1's body now appears in I3. */
2609 int i2_is_used
= 0, i1_is_used
= 0;
2610 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2611 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2612 /* Contains I3 if the destination of I3 is used in its source, which means
2613 that the old life of I3 is being killed. If that usage is placed into
2614 I2 and not in I3, a REG_DEAD note must be made. */
2615 rtx i3dest_killed
= 0;
2616 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2617 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2618 /* Copy of SET_SRC of I1 and I0, if needed. */
2619 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2620 /* Set if I2DEST was reused as a scratch register. */
2621 bool i2scratch
= false;
2622 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2623 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2624 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2625 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2626 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2627 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2628 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2629 /* Notes that must be added to REG_NOTES in I3 and I2. */
2630 rtx new_i3_notes
, new_i2_notes
;
2631 /* Notes that we substituted I3 into I2 instead of the normal case. */
2632 int i3_subst_into_i2
= 0;
2633 /* Notes that I1, I2 or I3 is a MULT operation. */
2636 int changed_i3_dest
= 0;
2639 rtx_insn
*temp_insn
;
2641 struct insn_link
*link
;
2643 rtx new_other_notes
;
2646 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2648 if (i1
== i2
|| i0
== i2
|| (i0
&& i0
== i1
))
2651 /* Only try four-insn combinations when there's high likelihood of
2652 success. Look for simple insns, such as loads of constants or
2653 binary operations involving a constant. */
2661 if (!flag_expensive_optimizations
)
2664 for (i
= 0; i
< 4; i
++)
2666 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2667 rtx set
= single_set (insn
);
2671 src
= SET_SRC (set
);
2672 if (CONSTANT_P (src
))
2677 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2679 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2680 || GET_CODE (src
) == LSHIFTRT
)
2684 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2685 are likely manipulating its value. Ideally we'll be able to combine
2686 all four insns into a bitfield insertion of some kind.
2688 Note the source in I0 might be inside a sign/zero extension and the
2689 memory modes in I0 and I3 might be different. So extract the address
2690 from the destination of I3 and search for it in the source of I0.
2692 In the event that there's a match but the source/dest do not actually
2693 refer to the same memory, the worst that happens is we try some
2694 combinations that we wouldn't have otherwise. */
2695 if ((set0
= single_set (i0
))
2696 /* Ensure the source of SET0 is a MEM, possibly buried inside
2698 && (GET_CODE (SET_SRC (set0
)) == MEM
2699 || ((GET_CODE (SET_SRC (set0
)) == ZERO_EXTEND
2700 || GET_CODE (SET_SRC (set0
)) == SIGN_EXTEND
)
2701 && GET_CODE (XEXP (SET_SRC (set0
), 0)) == MEM
))
2702 && (set3
= single_set (i3
))
2703 /* Ensure the destination of SET3 is a MEM. */
2704 && GET_CODE (SET_DEST (set3
)) == MEM
2705 /* Would it be better to extract the base address for the MEM
2706 in SET3 and look for that? I don't have cases where it matters
2707 but I could envision such cases. */
2708 && rtx_referenced_p (XEXP (SET_DEST (set3
), 0), SET_SRC (set0
)))
2711 if (ngood
< 2 && nshift
< 2)
2715 /* Exit early if one of the insns involved can't be used for
2718 || (i1
&& CALL_P (i1
))
2719 || (i0
&& CALL_P (i0
))
2720 || cant_combine_insn_p (i3
)
2721 || cant_combine_insn_p (i2
)
2722 || (i1
&& cant_combine_insn_p (i1
))
2723 || (i0
&& cant_combine_insn_p (i0
))
2724 || likely_spilled_retval_p (i3
))
2728 undobuf
.other_insn
= 0;
2730 /* Reset the hard register usage information. */
2731 CLEAR_HARD_REG_SET (newpat_used_regs
);
2733 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2736 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2737 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2739 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2740 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2742 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2743 INSN_UID (i2
), INSN_UID (i3
));
2746 /* If multiple insns feed into one of I2 or I3, they can be in any
2747 order. To simplify the code below, reorder them in sequence. */
2748 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2749 temp_insn
= i2
, i2
= i0
, i0
= temp_insn
;
2750 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2751 temp_insn
= i1
, i1
= i0
, i0
= temp_insn
;
2752 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2753 temp_insn
= i1
, i1
= i2
, i2
= temp_insn
;
2755 added_links_insn
= 0;
2757 /* First check for one important special case that the code below will
2758 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2759 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2760 we may be able to replace that destination with the destination of I3.
2761 This occurs in the common code where we compute both a quotient and
2762 remainder into a structure, in which case we want to do the computation
2763 directly into the structure to avoid register-register copies.
2765 Note that this case handles both multiple sets in I2 and also cases
2766 where I2 has a number of CLOBBERs inside the PARALLEL.
2768 We make very conservative checks below and only try to handle the
2769 most common cases of this. For example, we only handle the case
2770 where I2 and I3 are adjacent to avoid making difficult register
2773 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2774 && REG_P (SET_SRC (PATTERN (i3
)))
2775 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2776 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2777 && GET_CODE (PATTERN (i2
)) == PARALLEL
2778 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2779 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2780 below would need to check what is inside (and reg_overlap_mentioned_p
2781 doesn't support those codes anyway). Don't allow those destinations;
2782 the resulting insn isn't likely to be recognized anyway. */
2783 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2784 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2785 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2786 SET_DEST (PATTERN (i3
)))
2787 && next_active_insn (i2
) == i3
)
2789 rtx p2
= PATTERN (i2
);
2791 /* Make sure that the destination of I3,
2792 which we are going to substitute into one output of I2,
2793 is not used within another output of I2. We must avoid making this:
2794 (parallel [(set (mem (reg 69)) ...)
2795 (set (reg 69) ...)])
2796 which is not well-defined as to order of actions.
2797 (Besides, reload can't handle output reloads for this.)
2799 The problem can also happen if the dest of I3 is a memory ref,
2800 if another dest in I2 is an indirect memory ref. */
2801 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2802 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2803 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2804 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2805 SET_DEST (XVECEXP (p2
, 0, i
))))
2808 /* Make sure this PARALLEL is not an asm. We do not allow combining
2809 that usually (see can_combine_p), so do not here either. */
2810 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2811 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2812 && GET_CODE (SET_SRC (XVECEXP (p2
, 0, i
))) == ASM_OPERANDS
)
2815 if (i
== XVECLEN (p2
, 0))
2816 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2817 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2818 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2823 subst_low_luid
= DF_INSN_LUID (i2
);
2825 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2826 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2827 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2828 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2830 /* Replace the dest in I2 with our dest and make the resulting
2831 insn the new pattern for I3. Then skip to where we validate
2832 the pattern. Everything was set up above. */
2833 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2835 i3_subst_into_i2
= 1;
2836 goto validate_replacement
;
2840 /* If I2 is setting a pseudo to a constant and I3 is setting some
2841 sub-part of it to another constant, merge them by making a new
2844 && (temp_expr
= single_set (i2
)) != 0
2845 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2846 && GET_CODE (PATTERN (i3
)) == SET
2847 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2848 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2850 rtx dest
= SET_DEST (PATTERN (i3
));
2854 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2856 if (CONST_INT_P (XEXP (dest
, 1))
2857 && CONST_INT_P (XEXP (dest
, 2)))
2859 width
= INTVAL (XEXP (dest
, 1));
2860 offset
= INTVAL (XEXP (dest
, 2));
2861 dest
= XEXP (dest
, 0);
2862 if (BITS_BIG_ENDIAN
)
2863 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2868 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2869 dest
= XEXP (dest
, 0);
2870 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2876 /* If this is the low part, we're done. */
2877 if (subreg_lowpart_p (dest
))
2879 /* Handle the case where inner is twice the size of outer. */
2880 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr
)))
2881 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2882 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2883 /* Otherwise give up for now. */
2890 rtx inner
= SET_SRC (PATTERN (i3
));
2891 rtx outer
= SET_SRC (temp_expr
);
2894 = wi::insert (std::make_pair (outer
, GET_MODE (SET_DEST (temp_expr
))),
2895 std::make_pair (inner
, GET_MODE (dest
)),
2900 subst_low_luid
= DF_INSN_LUID (i2
);
2901 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2902 i2dest
= SET_DEST (temp_expr
);
2903 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2905 /* Replace the source in I2 with the new constant and make the
2906 resulting insn the new pattern for I3. Then skip to where we
2907 validate the pattern. Everything was set up above. */
2908 SUBST (SET_SRC (temp_expr
),
2909 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp_expr
))));
2911 newpat
= PATTERN (i2
);
2913 /* The dest of I3 has been replaced with the dest of I2. */
2914 changed_i3_dest
= 1;
2915 goto validate_replacement
;
2920 /* If we have no I1 and I2 looks like:
2921 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2923 make up a dummy I1 that is
2926 (set (reg:CC X) (compare:CC Y (const_int 0)))
2928 (We can ignore any trailing CLOBBERs.)
2930 This undoes a previous combination and allows us to match a branch-and-
2934 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2935 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2937 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2938 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2939 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2940 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
2941 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2942 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2944 /* We make I1 with the same INSN_UID as I2. This gives it
2945 the same DF_INSN_LUID for value tracking. Our fake I1 will
2946 never appear in the insn stream so giving it the same INSN_UID
2947 as I2 will not cause a problem. */
2949 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2950 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
2952 INSN_UID (i1
) = INSN_UID (i2
);
2954 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2955 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2956 SET_DEST (PATTERN (i1
)));
2957 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
2958 SUBST_LINK (LOG_LINKS (i2
),
2959 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
2962 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2963 make those two SETs separate I1 and I2 insns, and make an I0 that is
2966 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2967 && can_split_parallel_of_n_reg_sets (i2
, 2)
2968 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2969 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2971 /* If there is no I1, there is no I0 either. */
2974 /* We make I1 with the same INSN_UID as I2. This gives it
2975 the same DF_INSN_LUID for value tracking. Our fake I1 will
2976 never appear in the insn stream so giving it the same INSN_UID
2977 as I2 will not cause a problem. */
2979 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2980 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
2982 INSN_UID (i1
) = INSN_UID (i2
);
2984 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
2988 /* Verify that I2 and I1 are valid for combining. */
2989 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
)
2990 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
,
2992 || (i0
&& ! can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
,
2999 /* Record whether I2DEST is used in I2SRC and similarly for the other
3000 cases. Knowing this will help in register status updating below. */
3001 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
3002 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
3003 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
3004 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
3005 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
3006 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
3007 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
3008 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
3009 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
3011 /* For the earlier insns, determine which of the subsequent ones they
3013 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
3014 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
3015 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
3016 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
3017 && reg_overlap_mentioned_p (i0dest
, i2src
))));
3019 /* Ensure that I3's pattern can be the destination of combines. */
3020 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
3021 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
3022 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
3023 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
3030 /* See if any of the insns is a MULT operation. Unless one is, we will
3031 reject a combination that is, since it must be slower. Be conservative
3033 if (GET_CODE (i2src
) == MULT
3034 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
3035 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
3036 || (GET_CODE (PATTERN (i3
)) == SET
3037 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
3040 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3041 We used to do this EXCEPT in one case: I3 has a post-inc in an
3042 output operand. However, that exception can give rise to insns like
3044 which is a famous insn on the PDP-11 where the value of r3 used as the
3045 source was model-dependent. Avoid this sort of thing. */
3048 if (!(GET_CODE (PATTERN (i3
)) == SET
3049 && REG_P (SET_SRC (PATTERN (i3
)))
3050 && MEM_P (SET_DEST (PATTERN (i3
)))
3051 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
3052 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
3053 /* It's not the exception. */
3058 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
3059 if (REG_NOTE_KIND (link
) == REG_INC
3060 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
3062 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
3070 /* See if the SETs in I1 or I2 need to be kept around in the merged
3071 instruction: whenever the value set there is still needed past I3.
3072 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3074 For the SET in I1, we have two cases: if I1 and I2 independently feed
3075 into I3, the set in I1 needs to be kept around unless I1DEST dies
3076 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3077 in I1 needs to be kept around unless I1DEST dies or is set in either
3078 I2 or I3. The same considerations apply to I0. */
3080 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3083 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3084 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3089 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3090 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
3091 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3092 && dead_or_set_p (i2
, i0dest
)));
3096 /* We are about to copy insns for the case where they need to be kept
3097 around. Check that they can be copied in the merged instruction. */
3099 if (targetm
.cannot_copy_insn_p
3100 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3101 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3102 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3108 /* If the set in I2 needs to be kept around, we must make a copy of
3109 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3110 PATTERN (I2), we are only substituting for the original I1DEST, not into
3111 an already-substituted copy. This also prevents making self-referential
3112 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3117 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3118 i2pat
= gen_rtx_SET (i2dest
, copy_rtx (i2src
));
3120 i2pat
= copy_rtx (PATTERN (i2
));
3125 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3126 i1pat
= gen_rtx_SET (i1dest
, copy_rtx (i1src
));
3128 i1pat
= copy_rtx (PATTERN (i1
));
3133 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3134 i0pat
= gen_rtx_SET (i0dest
, copy_rtx (i0src
));
3136 i0pat
= copy_rtx (PATTERN (i0
));
3141 /* Substitute in the latest insn for the regs set by the earlier ones. */
3143 maxreg
= max_reg_num ();
3147 /* Many machines that don't use CC0 have insns that can both perform an
3148 arithmetic operation and set the condition code. These operations will
3149 be represented as a PARALLEL with the first element of the vector
3150 being a COMPARE of an arithmetic operation with the constant zero.
3151 The second element of the vector will set some pseudo to the result
3152 of the same arithmetic operation. If we simplify the COMPARE, we won't
3153 match such a pattern and so will generate an extra insn. Here we test
3154 for this case, where both the comparison and the operation result are
3155 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3156 I2SRC. Later we will make the PARALLEL that contains I2. */
3158 if (!HAVE_cc0
&& i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3159 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3160 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3161 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3164 rtx
*cc_use_loc
= NULL
;
3165 rtx_insn
*cc_use_insn
= NULL
;
3166 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3167 machine_mode compare_mode
, orig_compare_mode
;
3168 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3170 newpat
= PATTERN (i3
);
3171 newpat_dest
= SET_DEST (newpat
);
3172 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3174 if (undobuf
.other_insn
== 0
3175 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3178 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3179 compare_code
= simplify_compare_const (compare_code
,
3180 GET_MODE (i2dest
), op0
, &op1
);
3181 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3184 /* Do the rest only if op1 is const0_rtx, which may be the
3185 result of simplification. */
3186 if (op1
== const0_rtx
)
3188 /* If a single use of the CC is found, prepare to modify it
3189 when SELECT_CC_MODE returns a new CC-class mode, or when
3190 the above simplify_compare_const() returned a new comparison
3191 operator. undobuf.other_insn is assigned the CC use insn
3192 when modifying it. */
3195 #ifdef SELECT_CC_MODE
3196 machine_mode new_mode
3197 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3198 if (new_mode
!= orig_compare_mode
3199 && can_change_dest_mode (SET_DEST (newpat
),
3200 added_sets_2
, new_mode
))
3202 unsigned int regno
= REGNO (newpat_dest
);
3203 compare_mode
= new_mode
;
3204 if (regno
< FIRST_PSEUDO_REGISTER
)
3205 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3208 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3209 newpat_dest
= regno_reg_rtx
[regno
];
3213 /* Cases for modifying the CC-using comparison. */
3214 if (compare_code
!= orig_compare_code
3215 /* ??? Do we need to verify the zero rtx? */
3216 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3218 /* Replace cc_use_loc with entire new RTX. */
3220 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3221 newpat_dest
, const0_rtx
));
3222 undobuf
.other_insn
= cc_use_insn
;
3224 else if (compare_mode
!= orig_compare_mode
)
3226 /* Just replace the CC reg with a new mode. */
3227 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3228 undobuf
.other_insn
= cc_use_insn
;
3232 /* Now we modify the current newpat:
3233 First, SET_DEST(newpat) is updated if the CC mode has been
3234 altered. For targets without SELECT_CC_MODE, this should be
3236 if (compare_mode
!= orig_compare_mode
)
3237 SUBST (SET_DEST (newpat
), newpat_dest
);
3238 /* This is always done to propagate i2src into newpat. */
3239 SUBST (SET_SRC (newpat
),
3240 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3241 /* Create new version of i2pat if needed; the below PARALLEL
3242 creation needs this to work correctly. */
3243 if (! rtx_equal_p (i2src
, op0
))
3244 i2pat
= gen_rtx_SET (i2dest
, op0
);
3249 if (i2_is_used
== 0)
3251 /* It is possible that the source of I2 or I1 may be performing
3252 an unneeded operation, such as a ZERO_EXTEND of something
3253 that is known to have the high part zero. Handle that case
3254 by letting subst look at the inner insns.
3256 Another way to do this would be to have a function that tries
3257 to simplify a single insn instead of merging two or more
3258 insns. We don't do this because of the potential of infinite
3259 loops and because of the potential extra memory required.
3260 However, doing it the way we are is a bit of a kludge and
3261 doesn't catch all cases.
3263 But only do this if -fexpensive-optimizations since it slows
3264 things down and doesn't usually win.
3266 This is not done in the COMPARE case above because the
3267 unmodified I2PAT is used in the PARALLEL and so a pattern
3268 with a modified I2SRC would not match. */
3270 if (flag_expensive_optimizations
)
3272 /* Pass pc_rtx so no substitutions are done, just
3276 subst_low_luid
= DF_INSN_LUID (i1
);
3277 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3280 subst_low_luid
= DF_INSN_LUID (i2
);
3281 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3284 n_occurrences
= 0; /* `subst' counts here */
3285 subst_low_luid
= DF_INSN_LUID (i2
);
3287 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3288 copy of I2SRC each time we substitute it, in order to avoid creating
3289 self-referential RTL when we will be substituting I1SRC for I1DEST
3290 later. Likewise if I0 feeds into I2, either directly or indirectly
3291 through I1, and I0DEST is in I0SRC. */
3292 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3293 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3294 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3295 && i0dest_in_i0src
));
3298 /* Record whether I2's body now appears within I3's body. */
3299 i2_is_used
= n_occurrences
;
3302 /* If we already got a failure, don't try to do more. Otherwise, try to
3303 substitute I1 if we have it. */
3305 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3307 /* Check that an autoincrement side-effect on I1 has not been lost.
3308 This happens if I1DEST is mentioned in I2 and dies there, and
3309 has disappeared from the new pattern. */
3310 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3312 && dead_or_set_p (i2
, i1dest
)
3313 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3314 /* Before we can do this substitution, we must redo the test done
3315 above (see detailed comments there) that ensures I1DEST isn't
3316 mentioned in any SETs in NEWPAT that are field assignments. */
3317 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3325 subst_low_luid
= DF_INSN_LUID (i1
);
3327 /* If the following substitution will modify I1SRC, make a copy of it
3328 for the case where it is substituted for I1DEST in I2PAT later. */
3329 if (added_sets_2
&& i1_feeds_i2_n
)
3330 i1src_copy
= copy_rtx (i1src
);
3332 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3333 copy of I1SRC each time we substitute it, in order to avoid creating
3334 self-referential RTL when we will be substituting I0SRC for I0DEST
3336 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3337 i0_feeds_i1_n
&& i0dest_in_i0src
);
3340 /* Record whether I1's body now appears within I3's body. */
3341 i1_is_used
= n_occurrences
;
3344 /* Likewise for I0 if we have it. */
3346 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3348 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3349 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3350 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3351 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3352 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3359 /* If the following substitution will modify I0SRC, make a copy of it
3360 for the case where it is substituted for I0DEST in I1PAT later. */
3361 if (added_sets_1
&& i0_feeds_i1_n
)
3362 i0src_copy
= copy_rtx (i0src
);
3363 /* And a copy for I0DEST in I2PAT substitution. */
3364 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3365 || (i0_feeds_i2_n
)))
3366 i0src_copy2
= copy_rtx (i0src
);
3369 subst_low_luid
= DF_INSN_LUID (i0
);
3370 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3374 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3375 to count all the ways that I2SRC and I1SRC can be used. */
3376 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3377 && i2_is_used
+ added_sets_2
> 1)
3378 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3379 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3381 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3382 && (n_occurrences
+ added_sets_0
3383 + (added_sets_1
&& i0_feeds_i1_n
)
3384 + (added_sets_2
&& i0_feeds_i2_n
)
3386 /* Fail if we tried to make a new register. */
3387 || max_reg_num () != maxreg
3388 /* Fail if we couldn't do something and have a CLOBBER. */
3389 || GET_CODE (newpat
) == CLOBBER
3390 /* Fail if this new pattern is a MULT and we didn't have one before
3391 at the outer level. */
3392 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3399 /* If the actions of the earlier insns must be kept
3400 in addition to substituting them into the latest one,
3401 we must make a new PARALLEL for the latest insn
3402 to hold additional the SETs. */
3404 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3406 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3409 if (GET_CODE (newpat
) == PARALLEL
)
3411 rtvec old
= XVEC (newpat
, 0);
3412 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3413 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3414 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3415 sizeof (old
->elem
[0]) * old
->num_elem
);
3420 total_sets
= 1 + extra_sets
;
3421 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3422 XVECEXP (newpat
, 0, 0) = old
;
3426 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3432 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3434 XVECEXP (newpat
, 0, --total_sets
) = t
;
3440 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3441 i0_feeds_i1_n
&& i0dest_in_i0src
);
3442 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3443 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3445 XVECEXP (newpat
, 0, --total_sets
) = t
;
3449 validate_replacement
:
3451 /* Note which hard regs this insn has as inputs. */
3452 mark_used_regs_combine (newpat
);
3454 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3455 consider splitting this pattern, we might need these clobbers. */
3456 if (i1
&& GET_CODE (newpat
) == PARALLEL
3457 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3459 int len
= XVECLEN (newpat
, 0);
3461 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3462 for (i
= 0; i
< len
; i
++)
3463 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3466 /* We have recognized nothing yet. */
3467 insn_code_number
= -1;
3469 /* See if this is a PARALLEL of two SETs where one SET's destination is
3470 a register that is unused and this isn't marked as an instruction that
3471 might trap in an EH region. In that case, we just need the other SET.
3472 We prefer this over the PARALLEL.
3474 This can occur when simplifying a divmod insn. We *must* test for this
3475 case here because the code below that splits two independent SETs doesn't
3476 handle this case correctly when it updates the register status.
3478 It's pointless doing this if we originally had two sets, one from
3479 i3, and one from i2. Combining then splitting the parallel results
3480 in the original i2 again plus an invalid insn (which we delete).
3481 The net effect is only to move instructions around, which makes
3482 debug info less accurate. */
3484 if (!(added_sets_2
&& i1
== 0)
3485 && is_parallel_of_n_reg_sets (newpat
, 2)
3486 && asm_noperands (newpat
) < 0)
3488 rtx set0
= XVECEXP (newpat
, 0, 0);
3489 rtx set1
= XVECEXP (newpat
, 0, 1);
3490 rtx oldpat
= newpat
;
3492 if (((REG_P (SET_DEST (set1
))
3493 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3494 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3495 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3496 && insn_nothrow_p (i3
)
3497 && !side_effects_p (SET_SRC (set1
)))
3500 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3503 else if (((REG_P (SET_DEST (set0
))
3504 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3505 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3506 && find_reg_note (i3
, REG_UNUSED
,
3507 SUBREG_REG (SET_DEST (set0
)))))
3508 && insn_nothrow_p (i3
)
3509 && !side_effects_p (SET_SRC (set0
)))
3512 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3514 if (insn_code_number
>= 0)
3515 changed_i3_dest
= 1;
3518 if (insn_code_number
< 0)
3522 /* Is the result of combination a valid instruction? */
3523 if (insn_code_number
< 0)
3524 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3526 /* If we were combining three insns and the result is a simple SET
3527 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3528 insns. There are two ways to do this. It can be split using a
3529 machine-specific method (like when you have an addition of a large
3530 constant) or by combine in the function find_split_point. */
3532 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3533 && asm_noperands (newpat
) < 0)
3535 rtx parallel
, *split
;
3536 rtx_insn
*m_split_insn
;
3538 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3539 use I2DEST as a scratch register will help. In the latter case,
3540 convert I2DEST to the mode of the source of NEWPAT if we can. */
3542 m_split_insn
= combine_split_insns (newpat
, i3
);
3544 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3545 inputs of NEWPAT. */
3547 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3548 possible to try that as a scratch reg. This would require adding
3549 more code to make it work though. */
3551 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3553 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3555 /* First try to split using the original register as a
3556 scratch register. */
3557 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3558 gen_rtvec (2, newpat
,
3559 gen_rtx_CLOBBER (VOIDmode
,
3561 m_split_insn
= combine_split_insns (parallel
, i3
);
3563 /* If that didn't work, try changing the mode of I2DEST if
3565 if (m_split_insn
== 0
3566 && new_mode
!= GET_MODE (i2dest
)
3567 && new_mode
!= VOIDmode
3568 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3570 machine_mode old_mode
= GET_MODE (i2dest
);
3573 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3574 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3577 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3578 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3581 parallel
= (gen_rtx_PARALLEL
3583 gen_rtvec (2, newpat
,
3584 gen_rtx_CLOBBER (VOIDmode
,
3586 m_split_insn
= combine_split_insns (parallel
, i3
);
3588 if (m_split_insn
== 0
3589 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3593 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3594 buf
= undobuf
.undos
;
3595 undobuf
.undos
= buf
->next
;
3596 buf
->next
= undobuf
.frees
;
3597 undobuf
.frees
= buf
;
3601 i2scratch
= m_split_insn
!= 0;
3604 /* If recog_for_combine has discarded clobbers, try to use them
3605 again for the split. */
3606 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3608 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3609 m_split_insn
= combine_split_insns (parallel
, i3
);
3612 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3614 rtx m_split_pat
= PATTERN (m_split_insn
);
3615 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3616 if (insn_code_number
>= 0)
3617 newpat
= m_split_pat
;
3619 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3620 && (next_nonnote_nondebug_insn (i2
) == i3
3621 || ! use_crosses_set_p (PATTERN (m_split_insn
), DF_INSN_LUID (i2
))))
3624 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3625 newi2pat
= PATTERN (m_split_insn
);
3627 i3set
= single_set (NEXT_INSN (m_split_insn
));
3628 i2set
= single_set (m_split_insn
);
3630 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3632 /* If I2 or I3 has multiple SETs, we won't know how to track
3633 register status, so don't use these insns. If I2's destination
3634 is used between I2 and I3, we also can't use these insns. */
3636 if (i2_code_number
>= 0 && i2set
&& i3set
3637 && (next_nonnote_nondebug_insn (i2
) == i3
3638 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3639 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3641 if (insn_code_number
>= 0)
3644 /* It is possible that both insns now set the destination of I3.
3645 If so, we must show an extra use of it. */
3647 if (insn_code_number
>= 0)
3649 rtx new_i3_dest
= SET_DEST (i3set
);
3650 rtx new_i2_dest
= SET_DEST (i2set
);
3652 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3653 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3654 || GET_CODE (new_i3_dest
) == SUBREG
)
3655 new_i3_dest
= XEXP (new_i3_dest
, 0);
3657 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3658 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3659 || GET_CODE (new_i2_dest
) == SUBREG
)
3660 new_i2_dest
= XEXP (new_i2_dest
, 0);
3662 if (REG_P (new_i3_dest
)
3663 && REG_P (new_i2_dest
)
3664 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
)
3665 && REGNO (new_i2_dest
) < reg_n_sets_max
)
3666 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3670 /* If we can split it and use I2DEST, go ahead and see if that
3671 helps things be recognized. Verify that none of the registers
3672 are set between I2 and I3. */
3673 if (insn_code_number
< 0
3674 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3675 && (!HAVE_cc0
|| REG_P (i2dest
))
3676 /* We need I2DEST in the proper mode. If it is a hard register
3677 or the only use of a pseudo, we can change its mode.
3678 Make sure we don't change a hard register to have a mode that
3679 isn't valid for it, or change the number of registers. */
3680 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3681 || GET_MODE (*split
) == VOIDmode
3682 || can_change_dest_mode (i2dest
, added_sets_2
,
3684 && (next_nonnote_nondebug_insn (i2
) == i3
3685 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3686 /* We can't overwrite I2DEST if its value is still used by
3688 && ! reg_referenced_p (i2dest
, newpat
))
3690 rtx newdest
= i2dest
;
3691 enum rtx_code split_code
= GET_CODE (*split
);
3692 machine_mode split_mode
= GET_MODE (*split
);
3693 bool subst_done
= false;
3694 newi2pat
= NULL_RTX
;
3698 /* *SPLIT may be part of I2SRC, so make sure we have the
3699 original expression around for later debug processing.
3700 We should not need I2SRC any more in other cases. */
3701 if (MAY_HAVE_DEBUG_INSNS
)
3702 i2src
= copy_rtx (i2src
);
3706 /* Get NEWDEST as a register in the proper mode. We have already
3707 validated that we can do this. */
3708 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3710 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3711 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3714 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3715 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3719 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3720 an ASHIFT. This can occur if it was inside a PLUS and hence
3721 appeared to be a memory address. This is a kludge. */
3722 if (split_code
== MULT
3723 && CONST_INT_P (XEXP (*split
, 1))
3724 && INTVAL (XEXP (*split
, 1)) > 0
3725 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3727 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3728 XEXP (*split
, 0), GEN_INT (i
)));
3729 /* Update split_code because we may not have a multiply
3731 split_code
= GET_CODE (*split
);
3734 /* Similarly for (plus (mult FOO (const_int pow2))). */
3735 if (split_code
== PLUS
3736 && GET_CODE (XEXP (*split
, 0)) == MULT
3737 && CONST_INT_P (XEXP (XEXP (*split
, 0), 1))
3738 && INTVAL (XEXP (XEXP (*split
, 0), 1)) > 0
3739 && (i
= exact_log2 (UINTVAL (XEXP (XEXP (*split
, 0), 1)))) >= 0)
3741 rtx nsplit
= XEXP (*split
, 0);
3742 SUBST (XEXP (*split
, 0), gen_rtx_ASHIFT (GET_MODE (nsplit
),
3743 XEXP (nsplit
, 0), GEN_INT (i
)));
3744 /* Update split_code because we may not have a multiply
3746 split_code
= GET_CODE (*split
);
3749 #ifdef INSN_SCHEDULING
3750 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3751 be written as a ZERO_EXTEND. */
3752 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3754 #ifdef LOAD_EXTEND_OP
3755 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3756 what it really is. */
3757 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3759 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3760 SUBREG_REG (*split
)));
3763 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3764 SUBREG_REG (*split
)));
3768 /* Attempt to split binary operators using arithmetic identities. */
3769 if (BINARY_P (SET_SRC (newpat
))
3770 && split_mode
== GET_MODE (SET_SRC (newpat
))
3771 && ! side_effects_p (SET_SRC (newpat
)))
3773 rtx setsrc
= SET_SRC (newpat
);
3774 machine_mode mode
= GET_MODE (setsrc
);
3775 enum rtx_code code
= GET_CODE (setsrc
);
3776 rtx src_op0
= XEXP (setsrc
, 0);
3777 rtx src_op1
= XEXP (setsrc
, 1);
3779 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3780 if (rtx_equal_p (src_op0
, src_op1
))
3782 newi2pat
= gen_rtx_SET (newdest
, src_op0
);
3783 SUBST (XEXP (setsrc
, 0), newdest
);
3784 SUBST (XEXP (setsrc
, 1), newdest
);
3787 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3788 else if ((code
== PLUS
|| code
== MULT
)
3789 && GET_CODE (src_op0
) == code
3790 && GET_CODE (XEXP (src_op0
, 0)) == code
3791 && (INTEGRAL_MODE_P (mode
)
3792 || (FLOAT_MODE_P (mode
)
3793 && flag_unsafe_math_optimizations
)))
3795 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3796 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3797 rtx r
= XEXP (src_op0
, 1);
3800 /* Split both "((X op Y) op X) op Y" and
3801 "((X op Y) op Y) op X" as "T op T" where T is
3803 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3804 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3806 newi2pat
= gen_rtx_SET (newdest
, XEXP (src_op0
, 0));
3807 SUBST (XEXP (setsrc
, 0), newdest
);
3808 SUBST (XEXP (setsrc
, 1), newdest
);
3811 /* Split "((X op X) op Y) op Y)" as "T op T" where
3813 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3815 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3816 newi2pat
= gen_rtx_SET (newdest
, tmp
);
3817 SUBST (XEXP (setsrc
, 0), newdest
);
3818 SUBST (XEXP (setsrc
, 1), newdest
);
3826 newi2pat
= gen_rtx_SET (newdest
, *split
);
3827 SUBST (*split
, newdest
);
3830 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3832 /* recog_for_combine might have added CLOBBERs to newi2pat.
3833 Make sure NEWPAT does not depend on the clobbered regs. */
3834 if (GET_CODE (newi2pat
) == PARALLEL
)
3835 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3836 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3838 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3839 if (reg_overlap_mentioned_p (reg
, newpat
))
3846 /* If the split point was a MULT and we didn't have one before,
3847 don't use one now. */
3848 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3849 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3853 /* Check for a case where we loaded from memory in a narrow mode and
3854 then sign extended it, but we need both registers. In that case,
3855 we have a PARALLEL with both loads from the same memory location.
3856 We can split this into a load from memory followed by a register-register
3857 copy. This saves at least one insn, more if register allocation can
3860 We cannot do this if the destination of the first assignment is a
3861 condition code register or cc0. We eliminate this case by making sure
3862 the SET_DEST and SET_SRC have the same mode.
3864 We cannot do this if the destination of the second assignment is
3865 a register that we have already assumed is zero-extended. Similarly
3866 for a SUBREG of such a register. */
3868 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3869 && GET_CODE (newpat
) == PARALLEL
3870 && XVECLEN (newpat
, 0) == 2
3871 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3872 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3873 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3874 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3875 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3876 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3877 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3878 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3880 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3881 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3882 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3884 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3885 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3886 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3887 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3888 != GET_MODE_MASK (word_mode
))))
3889 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3890 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3892 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3893 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3894 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3895 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3896 != GET_MODE_MASK (word_mode
)))))
3897 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3898 SET_SRC (XVECEXP (newpat
, 0, 1)))
3899 && ! find_reg_note (i3
, REG_UNUSED
,
3900 SET_DEST (XVECEXP (newpat
, 0, 0))))
3904 newi2pat
= XVECEXP (newpat
, 0, 0);
3905 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3906 newpat
= XVECEXP (newpat
, 0, 1);
3907 SUBST (SET_SRC (newpat
),
3908 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3909 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3911 if (i2_code_number
>= 0)
3912 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3914 if (insn_code_number
>= 0)
3918 /* Similarly, check for a case where we have a PARALLEL of two independent
3919 SETs but we started with three insns. In this case, we can do the sets
3920 as two separate insns. This case occurs when some SET allows two
3921 other insns to combine, but the destination of that SET is still live.
3923 Also do this if we started with two insns and (at least) one of the
3924 resulting sets is a noop; this noop will be deleted later. */
3926 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
3927 && GET_CODE (newpat
) == PARALLEL
3928 && XVECLEN (newpat
, 0) == 2
3929 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3930 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3931 && (i1
|| set_noop_p (XVECEXP (newpat
, 0, 0))
3932 || set_noop_p (XVECEXP (newpat
, 0, 1)))
3933 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3934 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3935 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3936 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3937 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3938 XVECEXP (newpat
, 0, 0))
3939 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3940 XVECEXP (newpat
, 0, 1))
3941 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3942 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3944 rtx set0
= XVECEXP (newpat
, 0, 0);
3945 rtx set1
= XVECEXP (newpat
, 0, 1);
3947 /* Normally, it doesn't matter which of the two is done first,
3948 but the one that references cc0 can't be the second, and
3949 one which uses any regs/memory set in between i2 and i3 can't
3950 be first. The PARALLEL might also have been pre-existing in i3,
3951 so we need to make sure that we won't wrongly hoist a SET to i2
3952 that would conflict with a death note present in there. */
3953 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
3954 && !(REG_P (SET_DEST (set1
))
3955 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
3956 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
3957 && find_reg_note (i2
, REG_DEAD
,
3958 SUBREG_REG (SET_DEST (set1
))))
3959 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set0
))
3960 /* If I3 is a jump, ensure that set0 is a jump so that
3961 we do not create invalid RTL. */
3962 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
3968 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
3969 && !(REG_P (SET_DEST (set0
))
3970 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
3971 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
3972 && find_reg_note (i2
, REG_DEAD
,
3973 SUBREG_REG (SET_DEST (set0
))))
3974 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set1
))
3975 /* If I3 is a jump, ensure that set1 is a jump so that
3976 we do not create invalid RTL. */
3977 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
3989 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3991 if (i2_code_number
>= 0)
3993 /* recog_for_combine might have added CLOBBERs to newi2pat.
3994 Make sure NEWPAT does not depend on the clobbered regs. */
3995 if (GET_CODE (newi2pat
) == PARALLEL
)
3997 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3998 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
4000 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
4001 if (reg_overlap_mentioned_p (reg
, newpat
))
4009 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
4013 /* If it still isn't recognized, fail and change things back the way they
4015 if ((insn_code_number
< 0
4016 /* Is the result a reasonable ASM_OPERANDS? */
4017 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
4023 /* If we had to change another insn, make sure it is valid also. */
4024 if (undobuf
.other_insn
)
4026 CLEAR_HARD_REG_SET (newpat_used_regs
);
4028 other_pat
= PATTERN (undobuf
.other_insn
);
4029 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
4032 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
4039 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4040 they are adjacent to each other or not. */
4043 rtx_insn
*p
= prev_nonnote_insn (i3
);
4044 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
4045 && sets_cc0_p (newi2pat
))
4052 /* Only allow this combination if insn_rtx_costs reports that the
4053 replacement instructions are cheaper than the originals. */
4054 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
4060 if (MAY_HAVE_DEBUG_INSNS
)
4064 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
4065 if (undo
->kind
== UNDO_MODE
)
4067 rtx reg
= *undo
->where
.r
;
4068 machine_mode new_mode
= GET_MODE (reg
);
4069 machine_mode old_mode
= undo
->old_contents
.m
;
4071 /* Temporarily revert mode back. */
4072 adjust_reg_mode (reg
, old_mode
);
4074 if (reg
== i2dest
&& i2scratch
)
4076 /* If we used i2dest as a scratch register with a
4077 different mode, substitute it for the original
4078 i2src while its original mode is temporarily
4079 restored, and then clear i2scratch so that we don't
4080 do it again later. */
4081 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
4084 /* Put back the new mode. */
4085 adjust_reg_mode (reg
, new_mode
);
4089 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
4090 rtx_insn
*first
, *last
;
4095 last
= last_combined_insn
;
4100 last
= undobuf
.other_insn
;
4102 if (DF_INSN_LUID (last
)
4103 < DF_INSN_LUID (last_combined_insn
))
4104 last
= last_combined_insn
;
4107 /* We're dealing with a reg that changed mode but not
4108 meaning, so we want to turn it into a subreg for
4109 the new mode. However, because of REG sharing and
4110 because its mode had already changed, we have to do
4111 it in two steps. First, replace any debug uses of
4112 reg, with its original mode temporarily restored,
4113 with this copy we have created; then, replace the
4114 copy with the SUBREG of the original shared reg,
4115 once again changed to the new mode. */
4116 propagate_for_debug (first
, last
, reg
, tempreg
,
4118 adjust_reg_mode (reg
, new_mode
);
4119 propagate_for_debug (first
, last
, tempreg
,
4120 lowpart_subreg (old_mode
, reg
, new_mode
),
4126 /* If we will be able to accept this, we have made a
4127 change to the destination of I3. This requires us to
4128 do a few adjustments. */
4130 if (changed_i3_dest
)
4132 PATTERN (i3
) = newpat
;
4133 adjust_for_new_dest (i3
);
4136 /* We now know that we can do this combination. Merge the insns and
4137 update the status of registers and LOG_LINKS. */
4139 if (undobuf
.other_insn
)
4143 PATTERN (undobuf
.other_insn
) = other_pat
;
4145 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4146 ensure that they are still valid. Then add any non-duplicate
4147 notes added by recog_for_combine. */
4148 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4150 next
= XEXP (note
, 1);
4152 if ((REG_NOTE_KIND (note
) == REG_DEAD
4153 && !reg_referenced_p (XEXP (note
, 0),
4154 PATTERN (undobuf
.other_insn
)))
4155 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4156 && !reg_set_p (XEXP (note
, 0),
4157 PATTERN (undobuf
.other_insn
))))
4158 remove_note (undobuf
.other_insn
, note
);
4161 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4162 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4169 struct insn_link
*link
;
4172 /* I3 now uses what used to be its destination and which is now
4173 I2's destination. This requires us to do a few adjustments. */
4174 PATTERN (i3
) = newpat
;
4175 adjust_for_new_dest (i3
);
4177 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4180 However, some later insn might be using I2's dest and have
4181 a LOG_LINK pointing at I3. We must remove this link.
4182 The simplest way to remove the link is to point it at I1,
4183 which we know will be a NOTE. */
4185 /* newi2pat is usually a SET here; however, recog_for_combine might
4186 have added some clobbers. */
4187 if (GET_CODE (newi2pat
) == PARALLEL
)
4188 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
4190 ni2dest
= SET_DEST (newi2pat
);
4192 for (insn
= NEXT_INSN (i3
);
4193 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4194 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
4195 insn
= NEXT_INSN (insn
))
4197 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
4199 FOR_EACH_LOG_LINK (link
, insn
)
4200 if (link
->insn
== i3
)
4209 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4210 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4213 /* Compute which registers we expect to eliminate. newi2pat may be setting
4214 either i3dest or i2dest, so we must check it. */
4215 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4216 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4219 /* For i1, we need to compute both local elimination and global
4220 elimination information with respect to newi2pat because i1dest
4221 may be the same as i3dest, in which case newi2pat may be setting
4222 i1dest. Global information is used when distributing REG_DEAD
4223 note for i2 and i3, in which case it does matter if newi2pat sets
4226 Local information is used when distributing REG_DEAD note for i1,
4227 in which case it doesn't matter if newi2pat sets i1dest or not.
4228 See PR62151, if we have four insns combination:
4230 i1: r1 <- i1src (using r0)
4232 i2: r0 <- i2src (using r1)
4233 i3: r3 <- i3src (using r0)
4235 From i1's point of view, r0 is eliminated, no matter if it is set
4236 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4237 should be discarded.
4239 Note local information only affects cases in forms like "I1->I2->I3",
4240 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4241 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4243 rtx local_elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4246 rtx elim_i1
= (local_elim_i1
== 0
4247 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4249 /* Same case as i1. */
4250 rtx local_elim_i0
= (i0
== 0 || i0dest_in_i0src
|| !i0dest_killed
4252 rtx elim_i0
= (local_elim_i0
== 0
4253 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4256 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4258 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4259 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4261 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4263 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4265 /* Ensure that we do not have something that should not be shared but
4266 occurs multiple times in the new insns. Check this by first
4267 resetting all the `used' flags and then copying anything is shared. */
4269 reset_used_flags (i3notes
);
4270 reset_used_flags (i2notes
);
4271 reset_used_flags (i1notes
);
4272 reset_used_flags (i0notes
);
4273 reset_used_flags (newpat
);
4274 reset_used_flags (newi2pat
);
4275 if (undobuf
.other_insn
)
4276 reset_used_flags (PATTERN (undobuf
.other_insn
));
4278 i3notes
= copy_rtx_if_shared (i3notes
);
4279 i2notes
= copy_rtx_if_shared (i2notes
);
4280 i1notes
= copy_rtx_if_shared (i1notes
);
4281 i0notes
= copy_rtx_if_shared (i0notes
);
4282 newpat
= copy_rtx_if_shared (newpat
);
4283 newi2pat
= copy_rtx_if_shared (newi2pat
);
4284 if (undobuf
.other_insn
)
4285 reset_used_flags (PATTERN (undobuf
.other_insn
));
4287 INSN_CODE (i3
) = insn_code_number
;
4288 PATTERN (i3
) = newpat
;
4290 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4292 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4294 reset_used_flags (call_usage
);
4295 call_usage
= copy_rtx (call_usage
);
4299 /* I2SRC must still be meaningful at this point. Some splitting
4300 operations can invalidate I2SRC, but those operations do not
4303 replace_rtx (call_usage
, i2dest
, i2src
);
4307 replace_rtx (call_usage
, i1dest
, i1src
);
4309 replace_rtx (call_usage
, i0dest
, i0src
);
4311 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4314 if (undobuf
.other_insn
)
4315 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4317 /* We had one special case above where I2 had more than one set and
4318 we replaced a destination of one of those sets with the destination
4319 of I3. In that case, we have to update LOG_LINKS of insns later
4320 in this basic block. Note that this (expensive) case is rare.
4322 Also, in this case, we must pretend that all REG_NOTEs for I2
4323 actually came from I3, so that REG_UNUSED notes from I2 will be
4324 properly handled. */
4326 if (i3_subst_into_i2
)
4328 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4329 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4330 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4331 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4332 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4333 && ! find_reg_note (i2
, REG_UNUSED
,
4334 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4335 for (temp_insn
= NEXT_INSN (i2
);
4337 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4338 || BB_HEAD (this_basic_block
) != temp_insn
);
4339 temp_insn
= NEXT_INSN (temp_insn
))
4340 if (temp_insn
!= i3
&& INSN_P (temp_insn
))
4341 FOR_EACH_LOG_LINK (link
, temp_insn
)
4342 if (link
->insn
== i2
)
4348 while (XEXP (link
, 1))
4349 link
= XEXP (link
, 1);
4350 XEXP (link
, 1) = i2notes
;
4357 LOG_LINKS (i3
) = NULL
;
4359 LOG_LINKS (i2
) = NULL
;
4364 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4365 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4367 INSN_CODE (i2
) = i2_code_number
;
4368 PATTERN (i2
) = newi2pat
;
4372 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4373 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4375 SET_INSN_DELETED (i2
);
4380 LOG_LINKS (i1
) = NULL
;
4382 if (MAY_HAVE_DEBUG_INSNS
)
4383 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4385 SET_INSN_DELETED (i1
);
4390 LOG_LINKS (i0
) = NULL
;
4392 if (MAY_HAVE_DEBUG_INSNS
)
4393 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4395 SET_INSN_DELETED (i0
);
4398 /* Get death notes for everything that is now used in either I3 or
4399 I2 and used to die in a previous insn. If we built two new
4400 patterns, move from I1 to I2 then I2 to I3 so that we get the
4401 proper movement on registers that I2 modifies. */
4404 from_luid
= DF_INSN_LUID (i0
);
4406 from_luid
= DF_INSN_LUID (i1
);
4408 from_luid
= DF_INSN_LUID (i2
);
4410 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4411 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4413 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4415 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4416 elim_i2
, elim_i1
, elim_i0
);
4418 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4419 elim_i2
, elim_i1
, elim_i0
);
4421 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4422 elim_i2
, local_elim_i1
, local_elim_i0
);
4424 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4425 elim_i2
, elim_i1
, local_elim_i0
);
4427 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4428 elim_i2
, elim_i1
, elim_i0
);
4430 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4431 know these are REG_UNUSED and want them to go to the desired insn,
4432 so we always pass it as i3. */
4434 if (newi2pat
&& new_i2_notes
)
4435 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4439 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4442 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4443 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4444 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4445 in that case, it might delete I2. Similarly for I2 and I1.
4446 Show an additional death due to the REG_DEAD note we make here. If
4447 we discard it in distribute_notes, we will decrement it again. */
4451 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4452 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4453 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4456 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4457 elim_i2
, elim_i1
, elim_i0
);
4460 if (i2dest_in_i2src
)
4462 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4463 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4464 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4465 NULL_RTX
, NULL_RTX
);
4467 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4468 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4471 if (i1dest_in_i1src
)
4473 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4474 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4475 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4476 NULL_RTX
, NULL_RTX
);
4478 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4479 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4482 if (i0dest_in_i0src
)
4484 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4485 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4486 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4487 NULL_RTX
, NULL_RTX
);
4489 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4490 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4493 distribute_links (i3links
);
4494 distribute_links (i2links
);
4495 distribute_links (i1links
);
4496 distribute_links (i0links
);
4500 struct insn_link
*link
;
4501 rtx_insn
*i2_insn
= 0;
4502 rtx i2_val
= 0, set
;
4504 /* The insn that used to set this register doesn't exist, and
4505 this life of the register may not exist either. See if one of
4506 I3's links points to an insn that sets I2DEST. If it does,
4507 that is now the last known value for I2DEST. If we don't update
4508 this and I2 set the register to a value that depended on its old
4509 contents, we will get confused. If this insn is used, thing
4510 will be set correctly in combine_instructions. */
4511 FOR_EACH_LOG_LINK (link
, i3
)
4512 if ((set
= single_set (link
->insn
)) != 0
4513 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4514 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4516 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4518 /* If the reg formerly set in I2 died only once and that was in I3,
4519 zero its use count so it won't make `reload' do any work. */
4521 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4522 && ! i2dest_in_i2src
4523 && REGNO (i2dest
) < reg_n_sets_max
)
4524 INC_REG_N_SETS (REGNO (i2dest
), -1);
4527 if (i1
&& REG_P (i1dest
))
4529 struct insn_link
*link
;
4530 rtx_insn
*i1_insn
= 0;
4531 rtx i1_val
= 0, set
;
4533 FOR_EACH_LOG_LINK (link
, i3
)
4534 if ((set
= single_set (link
->insn
)) != 0
4535 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4536 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4538 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4541 && ! i1dest_in_i1src
4542 && REGNO (i1dest
) < reg_n_sets_max
)
4543 INC_REG_N_SETS (REGNO (i1dest
), -1);
4546 if (i0
&& REG_P (i0dest
))
4548 struct insn_link
*link
;
4549 rtx_insn
*i0_insn
= 0;
4550 rtx i0_val
= 0, set
;
4552 FOR_EACH_LOG_LINK (link
, i3
)
4553 if ((set
= single_set (link
->insn
)) != 0
4554 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4555 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4557 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4560 && ! i0dest_in_i0src
4561 && REGNO (i0dest
) < reg_n_sets_max
)
4562 INC_REG_N_SETS (REGNO (i0dest
), -1);
4565 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4566 been made to this insn. The order is important, because newi2pat
4567 can affect nonzero_bits of newpat. */
4569 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4570 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4573 if (undobuf
.other_insn
!= NULL_RTX
)
4577 fprintf (dump_file
, "modifying other_insn ");
4578 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4580 df_insn_rescan (undobuf
.other_insn
);
4583 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4587 fprintf (dump_file
, "modifying insn i0 ");
4588 dump_insn_slim (dump_file
, i0
);
4590 df_insn_rescan (i0
);
4593 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4597 fprintf (dump_file
, "modifying insn i1 ");
4598 dump_insn_slim (dump_file
, i1
);
4600 df_insn_rescan (i1
);
4603 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4607 fprintf (dump_file
, "modifying insn i2 ");
4608 dump_insn_slim (dump_file
, i2
);
4610 df_insn_rescan (i2
);
4613 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4617 fprintf (dump_file
, "modifying insn i3 ");
4618 dump_insn_slim (dump_file
, i3
);
4620 df_insn_rescan (i3
);
4623 /* Set new_direct_jump_p if a new return or simple jump instruction
4624 has been created. Adjust the CFG accordingly. */
4625 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4627 *new_direct_jump_p
= 1;
4628 mark_jump_label (PATTERN (i3
), i3
, 0);
4629 update_cfg_for_uncondjump (i3
);
4632 if (undobuf
.other_insn
!= NULL_RTX
4633 && (returnjump_p (undobuf
.other_insn
)
4634 || any_uncondjump_p (undobuf
.other_insn
)))
4636 *new_direct_jump_p
= 1;
4637 update_cfg_for_uncondjump (undobuf
.other_insn
);
4640 /* A noop might also need cleaning up of CFG, if it comes from the
4641 simplification of a jump. */
4643 && GET_CODE (newpat
) == SET
4644 && SET_SRC (newpat
) == pc_rtx
4645 && SET_DEST (newpat
) == pc_rtx
)
4647 *new_direct_jump_p
= 1;
4648 update_cfg_for_uncondjump (i3
);
4651 if (undobuf
.other_insn
!= NULL_RTX
4652 && JUMP_P (undobuf
.other_insn
)
4653 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4654 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4655 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4657 *new_direct_jump_p
= 1;
4658 update_cfg_for_uncondjump (undobuf
.other_insn
);
4661 combine_successes
++;
4664 if (added_links_insn
4665 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4666 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4667 return added_links_insn
;
4669 return newi2pat
? i2
: i3
;
4672 /* Get a marker for undoing to the current state. */
4675 get_undo_marker (void)
4677 return undobuf
.undos
;
4680 /* Undo the modifications up to the marker. */
4683 undo_to_marker (void *marker
)
4685 struct undo
*undo
, *next
;
4687 for (undo
= undobuf
.undos
; undo
!= marker
; undo
= next
)
4695 *undo
->where
.r
= undo
->old_contents
.r
;
4698 *undo
->where
.i
= undo
->old_contents
.i
;
4701 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4704 *undo
->where
.l
= undo
->old_contents
.l
;
4710 undo
->next
= undobuf
.frees
;
4711 undobuf
.frees
= undo
;
4714 undobuf
.undos
= (struct undo
*) marker
;
4717 /* Undo all the modifications recorded in undobuf. */
4725 /* We've committed to accepting the changes we made. Move all
4726 of the undos to the free list. */
4731 struct undo
*undo
, *next
;
4733 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4736 undo
->next
= undobuf
.frees
;
4737 undobuf
.frees
= undo
;
4742 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4743 where we have an arithmetic expression and return that point. LOC will
4746 try_combine will call this function to see if an insn can be split into
4750 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4753 enum rtx_code code
= GET_CODE (x
);
4755 unsigned HOST_WIDE_INT len
= 0;
4756 HOST_WIDE_INT pos
= 0;
4758 rtx inner
= NULL_RTX
;
4760 /* First special-case some codes. */
4764 #ifdef INSN_SCHEDULING
4765 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4767 if (MEM_P (SUBREG_REG (x
)))
4770 return find_split_point (&SUBREG_REG (x
), insn
, false);
4773 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4774 using LO_SUM and HIGH. */
4775 if (HAVE_lo_sum
&& (GET_CODE (XEXP (x
, 0)) == CONST
4776 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
))
4778 machine_mode address_mode
= get_address_mode (x
);
4781 gen_rtx_LO_SUM (address_mode
,
4782 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4784 return &XEXP (XEXP (x
, 0), 0);
4787 /* If we have a PLUS whose second operand is a constant and the
4788 address is not valid, perhaps will can split it up using
4789 the machine-specific way to split large constants. We use
4790 the first pseudo-reg (one of the virtual regs) as a placeholder;
4791 it will not remain in the result. */
4792 if (GET_CODE (XEXP (x
, 0)) == PLUS
4793 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4794 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4795 MEM_ADDR_SPACE (x
)))
4797 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4798 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (reg
, XEXP (x
, 0)),
4801 /* This should have produced two insns, each of which sets our
4802 placeholder. If the source of the second is a valid address,
4803 we can make put both sources together and make a split point
4807 && NEXT_INSN (seq
) != NULL_RTX
4808 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4809 && NONJUMP_INSN_P (seq
)
4810 && GET_CODE (PATTERN (seq
)) == SET
4811 && SET_DEST (PATTERN (seq
)) == reg
4812 && ! reg_mentioned_p (reg
,
4813 SET_SRC (PATTERN (seq
)))
4814 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4815 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4816 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4817 && memory_address_addr_space_p
4818 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4819 MEM_ADDR_SPACE (x
)))
4821 rtx src1
= SET_SRC (PATTERN (seq
));
4822 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4824 /* Replace the placeholder in SRC2 with SRC1. If we can
4825 find where in SRC2 it was placed, that can become our
4826 split point and we can replace this address with SRC2.
4827 Just try two obvious places. */
4829 src2
= replace_rtx (src2
, reg
, src1
);
4831 if (XEXP (src2
, 0) == src1
)
4832 split
= &XEXP (src2
, 0);
4833 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4834 && XEXP (XEXP (src2
, 0), 0) == src1
)
4835 split
= &XEXP (XEXP (src2
, 0), 0);
4839 SUBST (XEXP (x
, 0), src2
);
4844 /* If that didn't work, perhaps the first operand is complex and
4845 needs to be computed separately, so make a split point there.
4846 This will occur on machines that just support REG + CONST
4847 and have a constant moved through some previous computation. */
4849 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4850 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4851 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4852 return &XEXP (XEXP (x
, 0), 0);
4855 /* If we have a PLUS whose first operand is complex, try computing it
4856 separately by making a split there. */
4857 if (GET_CODE (XEXP (x
, 0)) == PLUS
4858 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4860 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4861 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4862 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4863 return &XEXP (XEXP (x
, 0), 0);
4867 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4868 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4869 we need to put the operand into a register. So split at that
4872 if (SET_DEST (x
) == cc0_rtx
4873 && GET_CODE (SET_SRC (x
)) != COMPARE
4874 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4875 && !OBJECT_P (SET_SRC (x
))
4876 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4877 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4878 return &SET_SRC (x
);
4880 /* See if we can split SET_SRC as it stands. */
4881 split
= find_split_point (&SET_SRC (x
), insn
, true);
4882 if (split
&& split
!= &SET_SRC (x
))
4885 /* See if we can split SET_DEST as it stands. */
4886 split
= find_split_point (&SET_DEST (x
), insn
, false);
4887 if (split
&& split
!= &SET_DEST (x
))
4890 /* See if this is a bitfield assignment with everything constant. If
4891 so, this is an IOR of an AND, so split it into that. */
4892 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4893 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4894 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4895 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4896 && CONST_INT_P (SET_SRC (x
))
4897 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4898 + INTVAL (XEXP (SET_DEST (x
), 2)))
4899 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4900 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4902 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4903 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4904 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4905 rtx dest
= XEXP (SET_DEST (x
), 0);
4906 machine_mode mode
= GET_MODE (dest
);
4907 unsigned HOST_WIDE_INT mask
4908 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4911 if (BITS_BIG_ENDIAN
)
4912 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4914 or_mask
= gen_int_mode (src
<< pos
, mode
);
4917 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4920 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4922 simplify_gen_binary (IOR
, mode
,
4923 simplify_gen_binary (AND
, mode
,
4928 SUBST (SET_DEST (x
), dest
);
4930 split
= find_split_point (&SET_SRC (x
), insn
, true);
4931 if (split
&& split
!= &SET_SRC (x
))
4935 /* Otherwise, see if this is an operation that we can split into two.
4936 If so, try to split that. */
4937 code
= GET_CODE (SET_SRC (x
));
4942 /* If we are AND'ing with a large constant that is only a single
4943 bit and the result is only being used in a context where we
4944 need to know if it is zero or nonzero, replace it with a bit
4945 extraction. This will avoid the large constant, which might
4946 have taken more than one insn to make. If the constant were
4947 not a valid argument to the AND but took only one insn to make,
4948 this is no worse, but if it took more than one insn, it will
4951 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4952 && REG_P (XEXP (SET_SRC (x
), 0))
4953 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4954 && REG_P (SET_DEST (x
))
4955 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
4956 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4957 && XEXP (*split
, 0) == SET_DEST (x
)
4958 && XEXP (*split
, 1) == const0_rtx
)
4960 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4961 XEXP (SET_SRC (x
), 0),
4962 pos
, NULL_RTX
, 1, 1, 0, 0);
4963 if (extraction
!= 0)
4965 SUBST (SET_SRC (x
), extraction
);
4966 return find_split_point (loc
, insn
, false);
4972 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4973 is known to be on, this can be converted into a NEG of a shift. */
4974 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4975 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4976 && 1 <= (pos
= exact_log2
4977 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4978 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4980 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4984 gen_rtx_LSHIFTRT (mode
,
4985 XEXP (SET_SRC (x
), 0),
4988 split
= find_split_point (&SET_SRC (x
), insn
, true);
4989 if (split
&& split
!= &SET_SRC (x
))
4995 inner
= XEXP (SET_SRC (x
), 0);
4997 /* We can't optimize if either mode is a partial integer
4998 mode as we don't know how many bits are significant
5000 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
5001 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
5005 len
= GET_MODE_PRECISION (GET_MODE (inner
));
5011 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
5012 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
5014 inner
= XEXP (SET_SRC (x
), 0);
5015 len
= INTVAL (XEXP (SET_SRC (x
), 1));
5016 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
5018 if (BITS_BIG_ENDIAN
)
5019 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
5020 unsignedp
= (code
== ZERO_EXTRACT
);
5029 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
5031 machine_mode mode
= GET_MODE (SET_SRC (x
));
5033 /* For unsigned, we have a choice of a shift followed by an
5034 AND or two shifts. Use two shifts for field sizes where the
5035 constant might be too large. We assume here that we can
5036 always at least get 8-bit constants in an AND insn, which is
5037 true for every current RISC. */
5039 if (unsignedp
&& len
<= 8)
5041 unsigned HOST_WIDE_INT mask
5042 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
5046 (mode
, gen_lowpart (mode
, inner
),
5048 gen_int_mode (mask
, mode
)));
5050 split
= find_split_point (&SET_SRC (x
), insn
, true);
5051 if (split
&& split
!= &SET_SRC (x
))
5058 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
5059 gen_rtx_ASHIFT (mode
,
5060 gen_lowpart (mode
, inner
),
5061 GEN_INT (GET_MODE_PRECISION (mode
)
5063 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
5065 split
= find_split_point (&SET_SRC (x
), insn
, true);
5066 if (split
&& split
!= &SET_SRC (x
))
5071 /* See if this is a simple operation with a constant as the second
5072 operand. It might be that this constant is out of range and hence
5073 could be used as a split point. */
5074 if (BINARY_P (SET_SRC (x
))
5075 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
5076 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
5077 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
5078 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
5079 return &XEXP (SET_SRC (x
), 1);
5081 /* Finally, see if this is a simple operation with its first operand
5082 not in a register. The operation might require this operand in a
5083 register, so return it as a split point. We can always do this
5084 because if the first operand were another operation, we would have
5085 already found it as a split point. */
5086 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
5087 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
5088 return &XEXP (SET_SRC (x
), 0);
5094 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5095 it is better to write this as (not (ior A B)) so we can split it.
5096 Similarly for IOR. */
5097 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
5100 gen_rtx_NOT (GET_MODE (x
),
5101 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
5103 XEXP (XEXP (x
, 0), 0),
5104 XEXP (XEXP (x
, 1), 0))));
5105 return find_split_point (loc
, insn
, set_src
);
5108 /* Many RISC machines have a large set of logical insns. If the
5109 second operand is a NOT, put it first so we will try to split the
5110 other operand first. */
5111 if (GET_CODE (XEXP (x
, 1)) == NOT
)
5113 rtx tem
= XEXP (x
, 0);
5114 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5115 SUBST (XEXP (x
, 1), tem
);
5121 /* Canonicalization can produce (minus A (mult B C)), where C is a
5122 constant. It may be better to try splitting (plus (mult B -C) A)
5123 instead if this isn't a multiply by a power of two. */
5124 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
5125 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5126 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
5128 machine_mode mode
= GET_MODE (x
);
5129 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
5130 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
5131 SUBST (*loc
, gen_rtx_PLUS (mode
,
5133 XEXP (XEXP (x
, 1), 0),
5134 gen_int_mode (other_int
,
5137 return find_split_point (loc
, insn
, set_src
);
5140 /* Split at a multiply-accumulate instruction. However if this is
5141 the SET_SRC, we likely do not have such an instruction and it's
5142 worthless to try this split. */
5144 && (GET_CODE (XEXP (x
, 0)) == MULT
5145 || (GET_CODE (XEXP (x
, 0)) == ASHIFT
5146 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5153 /* Otherwise, select our actions depending on our rtx class. */
5154 switch (GET_RTX_CLASS (code
))
5156 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5158 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5161 /* ... fall through ... */
5163 case RTX_COMM_ARITH
:
5165 case RTX_COMM_COMPARE
:
5166 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5169 /* ... fall through ... */
5171 /* Some machines have (and (shift ...) ...) insns. If X is not
5172 an AND, but XEXP (X, 0) is, use it as our split point. */
5173 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5174 return &XEXP (x
, 0);
5176 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5182 /* Otherwise, we don't have a split point. */
5187 /* Throughout X, replace FROM with TO, and return the result.
5188 The result is TO if X is FROM;
5189 otherwise the result is X, but its contents may have been modified.
5190 If they were modified, a record was made in undobuf so that
5191 undo_all will (among other things) return X to its original state.
5193 If the number of changes necessary is too much to record to undo,
5194 the excess changes are not made, so the result is invalid.
5195 The changes already made can still be undone.
5196 undobuf.num_undo is incremented for such changes, so by testing that
5197 the caller can tell whether the result is valid.
5199 `n_occurrences' is incremented each time FROM is replaced.
5201 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5203 IN_COND is nonzero if we are at the top level of a condition.
5205 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5206 by copying if `n_occurrences' is nonzero. */
5209 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5211 enum rtx_code code
= GET_CODE (x
);
5212 machine_mode op0_mode
= VOIDmode
;
5217 /* Two expressions are equal if they are identical copies of a shared
5218 RTX or if they are both registers with the same register number
5221 #define COMBINE_RTX_EQUAL_P(X,Y) \
5223 || (REG_P (X) && REG_P (Y) \
5224 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5226 /* Do not substitute into clobbers of regs -- this will never result in
5228 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5231 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5234 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5237 /* If X and FROM are the same register but different modes, they
5238 will not have been seen as equal above. However, the log links code
5239 will make a LOG_LINKS entry for that case. If we do nothing, we
5240 will try to rerecognize our original insn and, when it succeeds,
5241 we will delete the feeding insn, which is incorrect.
5243 So force this insn not to match in this (rare) case. */
5244 if (! in_dest
&& code
== REG
&& REG_P (from
)
5245 && reg_overlap_mentioned_p (x
, from
))
5246 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5248 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5249 of which may contain things that can be combined. */
5250 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5253 /* It is possible to have a subexpression appear twice in the insn.
5254 Suppose that FROM is a register that appears within TO.
5255 Then, after that subexpression has been scanned once by `subst',
5256 the second time it is scanned, TO may be found. If we were
5257 to scan TO here, we would find FROM within it and create a
5258 self-referent rtl structure which is completely wrong. */
5259 if (COMBINE_RTX_EQUAL_P (x
, to
))
5262 /* Parallel asm_operands need special attention because all of the
5263 inputs are shared across the arms. Furthermore, unsharing the
5264 rtl results in recognition failures. Failure to handle this case
5265 specially can result in circular rtl.
5267 Solve this by doing a normal pass across the first entry of the
5268 parallel, and only processing the SET_DESTs of the subsequent
5271 if (code
== PARALLEL
5272 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5273 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5275 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5277 /* If this substitution failed, this whole thing fails. */
5278 if (GET_CODE (new_rtx
) == CLOBBER
5279 && XEXP (new_rtx
, 0) == const0_rtx
)
5282 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5284 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5286 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5289 && GET_CODE (dest
) != CC0
5290 && GET_CODE (dest
) != PC
)
5292 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5294 /* If this substitution failed, this whole thing fails. */
5295 if (GET_CODE (new_rtx
) == CLOBBER
5296 && XEXP (new_rtx
, 0) == const0_rtx
)
5299 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5305 len
= GET_RTX_LENGTH (code
);
5306 fmt
= GET_RTX_FORMAT (code
);
5308 /* We don't need to process a SET_DEST that is a register, CC0,
5309 or PC, so set up to skip this common case. All other cases
5310 where we want to suppress replacing something inside a
5311 SET_SRC are handled via the IN_DEST operand. */
5313 && (REG_P (SET_DEST (x
))
5314 || GET_CODE (SET_DEST (x
)) == CC0
5315 || GET_CODE (SET_DEST (x
)) == PC
))
5318 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5321 op0_mode
= GET_MODE (XEXP (x
, 0));
5323 for (i
= 0; i
< len
; i
++)
5328 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5330 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5332 new_rtx
= (unique_copy
&& n_occurrences
5333 ? copy_rtx (to
) : to
);
5338 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5341 /* If this substitution failed, this whole thing
5343 if (GET_CODE (new_rtx
) == CLOBBER
5344 && XEXP (new_rtx
, 0) == const0_rtx
)
5348 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5351 else if (fmt
[i
] == 'e')
5353 /* If this is a register being set, ignore it. */
5354 new_rtx
= XEXP (x
, i
);
5357 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5359 || code
== STRICT_LOW_PART
))
5362 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5364 /* In general, don't install a subreg involving two
5365 modes not tieable. It can worsen register
5366 allocation, and can even make invalid reload
5367 insns, since the reg inside may need to be copied
5368 from in the outside mode, and that may be invalid
5369 if it is an fp reg copied in integer mode.
5371 We allow two exceptions to this: It is valid if
5372 it is inside another SUBREG and the mode of that
5373 SUBREG and the mode of the inside of TO is
5374 tieable and it is valid if X is a SET that copies
5377 if (GET_CODE (to
) == SUBREG
5378 && ! MODES_TIEABLE_P (GET_MODE (to
),
5379 GET_MODE (SUBREG_REG (to
)))
5380 && ! (code
== SUBREG
5381 && MODES_TIEABLE_P (GET_MODE (x
),
5382 GET_MODE (SUBREG_REG (to
))))
5384 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5387 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5391 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5392 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5395 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5397 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5401 /* If we are in a SET_DEST, suppress most cases unless we
5402 have gone inside a MEM, in which case we want to
5403 simplify the address. We assume here that things that
5404 are actually part of the destination have their inner
5405 parts in the first expression. This is true for SUBREG,
5406 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5407 things aside from REG and MEM that should appear in a
5409 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5411 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5412 || code
== ZERO_EXTRACT
))
5415 code
== IF_THEN_ELSE
&& i
== 0,
5418 /* If we found that we will have to reject this combination,
5419 indicate that by returning the CLOBBER ourselves, rather than
5420 an expression containing it. This will speed things up as
5421 well as prevent accidents where two CLOBBERs are considered
5422 to be equal, thus producing an incorrect simplification. */
5424 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5427 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5429 machine_mode mode
= GET_MODE (x
);
5431 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5432 GET_MODE (SUBREG_REG (x
)),
5435 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5437 else if (CONST_SCALAR_INT_P (new_rtx
)
5438 && GET_CODE (x
) == ZERO_EXTEND
)
5440 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5441 new_rtx
, GET_MODE (XEXP (x
, 0)));
5445 SUBST (XEXP (x
, i
), new_rtx
);
5450 /* Check if we are loading something from the constant pool via float
5451 extension; in this case we would undo compress_float_constant
5452 optimization and degenerate constant load to an immediate value. */
5453 if (GET_CODE (x
) == FLOAT_EXTEND
5454 && MEM_P (XEXP (x
, 0))
5455 && MEM_READONLY_P (XEXP (x
, 0)))
5457 rtx tmp
= avoid_constant_pool_reference (x
);
5462 /* Try to simplify X. If the simplification changed the code, it is likely
5463 that further simplification will help, so loop, but limit the number
5464 of repetitions that will be performed. */
5466 for (i
= 0; i
< 4; i
++)
5468 /* If X is sufficiently simple, don't bother trying to do anything
5470 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5471 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5473 if (GET_CODE (x
) == code
)
5476 code
= GET_CODE (x
);
5478 /* We no longer know the original mode of operand 0 since we
5479 have changed the form of X) */
5480 op0_mode
= VOIDmode
;
5486 /* Simplify X, a piece of RTL. We just operate on the expression at the
5487 outer level; call `subst' to simplify recursively. Return the new
5490 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5491 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5495 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5498 enum rtx_code code
= GET_CODE (x
);
5499 machine_mode mode
= GET_MODE (x
);
5503 /* If this is a commutative operation, put a constant last and a complex
5504 expression first. We don't need to do this for comparisons here. */
5505 if (COMMUTATIVE_ARITH_P (x
)
5506 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5509 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5510 SUBST (XEXP (x
, 1), temp
);
5513 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5514 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5515 things. Check for cases where both arms are testing the same
5518 Don't do anything if all operands are very simple. */
5521 && ((!OBJECT_P (XEXP (x
, 0))
5522 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5523 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5524 || (!OBJECT_P (XEXP (x
, 1))
5525 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5526 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5528 && (!OBJECT_P (XEXP (x
, 0))
5529 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5530 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5532 rtx cond
, true_rtx
, false_rtx
;
5534 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5536 /* If everything is a comparison, what we have is highly unlikely
5537 to be simpler, so don't use it. */
5538 && ! (COMPARISON_P (x
)
5539 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5541 rtx cop1
= const0_rtx
;
5542 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5544 if (cond_code
== NE
&& COMPARISON_P (cond
))
5547 /* Simplify the alternative arms; this may collapse the true and
5548 false arms to store-flag values. Be careful to use copy_rtx
5549 here since true_rtx or false_rtx might share RTL with x as a
5550 result of the if_then_else_cond call above. */
5551 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5552 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5554 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5555 is unlikely to be simpler. */
5556 if (general_operand (true_rtx
, VOIDmode
)
5557 && general_operand (false_rtx
, VOIDmode
))
5559 enum rtx_code reversed
;
5561 /* Restarting if we generate a store-flag expression will cause
5562 us to loop. Just drop through in this case. */
5564 /* If the result values are STORE_FLAG_VALUE and zero, we can
5565 just make the comparison operation. */
5566 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5567 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5569 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5570 && ((reversed
= reversed_comparison_code_parts
5571 (cond_code
, cond
, cop1
, NULL
))
5573 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5576 /* Likewise, we can make the negate of a comparison operation
5577 if the result values are - STORE_FLAG_VALUE and zero. */
5578 else if (CONST_INT_P (true_rtx
)
5579 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5580 && false_rtx
== const0_rtx
)
5581 x
= simplify_gen_unary (NEG
, mode
,
5582 simplify_gen_relational (cond_code
,
5586 else if (CONST_INT_P (false_rtx
)
5587 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5588 && true_rtx
== const0_rtx
5589 && ((reversed
= reversed_comparison_code_parts
5590 (cond_code
, cond
, cop1
, NULL
))
5592 x
= simplify_gen_unary (NEG
, mode
,
5593 simplify_gen_relational (reversed
,
5598 return gen_rtx_IF_THEN_ELSE (mode
,
5599 simplify_gen_relational (cond_code
,
5604 true_rtx
, false_rtx
);
5606 code
= GET_CODE (x
);
5607 op0_mode
= VOIDmode
;
5612 /* Try to fold this expression in case we have constants that weren't
5615 switch (GET_RTX_CLASS (code
))
5618 if (op0_mode
== VOIDmode
)
5619 op0_mode
= GET_MODE (XEXP (x
, 0));
5620 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5623 case RTX_COMM_COMPARE
:
5625 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5626 if (cmp_mode
== VOIDmode
)
5628 cmp_mode
= GET_MODE (XEXP (x
, 1));
5629 if (cmp_mode
== VOIDmode
)
5630 cmp_mode
= op0_mode
;
5632 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5633 XEXP (x
, 0), XEXP (x
, 1));
5636 case RTX_COMM_ARITH
:
5638 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5640 case RTX_BITFIELD_OPS
:
5642 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5643 XEXP (x
, 1), XEXP (x
, 2));
5652 code
= GET_CODE (temp
);
5653 op0_mode
= VOIDmode
;
5654 mode
= GET_MODE (temp
);
5657 /* First see if we can apply the inverse distributive law. */
5658 if (code
== PLUS
|| code
== MINUS
5659 || code
== AND
|| code
== IOR
|| code
== XOR
)
5661 x
= apply_distributive_law (x
);
5662 code
= GET_CODE (x
);
5663 op0_mode
= VOIDmode
;
5666 /* If CODE is an associative operation not otherwise handled, see if we
5667 can associate some operands. This can win if they are constants or
5668 if they are logically related (i.e. (a & b) & a). */
5669 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5670 || code
== AND
|| code
== IOR
|| code
== XOR
5671 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5672 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5673 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5675 if (GET_CODE (XEXP (x
, 0)) == code
)
5677 rtx other
= XEXP (XEXP (x
, 0), 0);
5678 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5679 rtx inner_op1
= XEXP (x
, 1);
5682 /* Make sure we pass the constant operand if any as the second
5683 one if this is a commutative operation. */
5684 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5685 std::swap (inner_op0
, inner_op1
);
5686 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5687 : code
== DIV
? MULT
5689 mode
, inner_op0
, inner_op1
);
5691 /* For commutative operations, try the other pair if that one
5693 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5695 other
= XEXP (XEXP (x
, 0), 1);
5696 inner
= simplify_binary_operation (code
, mode
,
5697 XEXP (XEXP (x
, 0), 0),
5702 return simplify_gen_binary (code
, mode
, other
, inner
);
5706 /* A little bit of algebraic simplification here. */
5710 /* Ensure that our address has any ASHIFTs converted to MULT in case
5711 address-recognizing predicates are called later. */
5712 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5713 SUBST (XEXP (x
, 0), temp
);
5717 if (op0_mode
== VOIDmode
)
5718 op0_mode
= GET_MODE (SUBREG_REG (x
));
5720 /* See if this can be moved to simplify_subreg. */
5721 if (CONSTANT_P (SUBREG_REG (x
))
5722 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5723 /* Don't call gen_lowpart if the inner mode
5724 is VOIDmode and we cannot simplify it, as SUBREG without
5725 inner mode is invalid. */
5726 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5727 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5728 return gen_lowpart (mode
, SUBREG_REG (x
));
5730 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5734 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5739 /* If op is known to have all lower bits zero, the result is zero. */
5741 && SCALAR_INT_MODE_P (mode
)
5742 && SCALAR_INT_MODE_P (op0_mode
)
5743 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5744 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5745 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5746 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5747 & GET_MODE_MASK (mode
)) == 0)
5748 return CONST0_RTX (mode
);
5751 /* Don't change the mode of the MEM if that would change the meaning
5753 if (MEM_P (SUBREG_REG (x
))
5754 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5755 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5756 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5757 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5759 /* Note that we cannot do any narrowing for non-constants since
5760 we might have been counting on using the fact that some bits were
5761 zero. We now do this in the SET. */
5766 temp
= expand_compound_operation (XEXP (x
, 0));
5768 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5769 replaced by (lshiftrt X C). This will convert
5770 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5772 if (GET_CODE (temp
) == ASHIFTRT
5773 && CONST_INT_P (XEXP (temp
, 1))
5774 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5775 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5776 INTVAL (XEXP (temp
, 1)));
5778 /* If X has only a single bit that might be nonzero, say, bit I, convert
5779 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5780 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5781 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5782 or a SUBREG of one since we'd be making the expression more
5783 complex if it was just a register. */
5786 && ! (GET_CODE (temp
) == SUBREG
5787 && REG_P (SUBREG_REG (temp
)))
5788 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5790 rtx temp1
= simplify_shift_const
5791 (NULL_RTX
, ASHIFTRT
, mode
,
5792 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5793 GET_MODE_PRECISION (mode
) - 1 - i
),
5794 GET_MODE_PRECISION (mode
) - 1 - i
);
5796 /* If all we did was surround TEMP with the two shifts, we
5797 haven't improved anything, so don't use it. Otherwise,
5798 we are better off with TEMP1. */
5799 if (GET_CODE (temp1
) != ASHIFTRT
5800 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5801 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5807 /* We can't handle truncation to a partial integer mode here
5808 because we don't know the real bitsize of the partial
5810 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5813 if (HWI_COMPUTABLE_MODE_P (mode
))
5815 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5816 GET_MODE_MASK (mode
), 0));
5818 /* We can truncate a constant value and return it. */
5819 if (CONST_INT_P (XEXP (x
, 0)))
5820 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5822 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5823 whose value is a comparison can be replaced with a subreg if
5824 STORE_FLAG_VALUE permits. */
5825 if (HWI_COMPUTABLE_MODE_P (mode
)
5826 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5827 && (temp
= get_last_value (XEXP (x
, 0)))
5828 && COMPARISON_P (temp
))
5829 return gen_lowpart (mode
, XEXP (x
, 0));
5833 /* (const (const X)) can become (const X). Do it this way rather than
5834 returning the inner CONST since CONST can be shared with a
5836 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5837 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5841 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5842 can add in an offset. find_split_point will split this address up
5843 again if it doesn't match. */
5844 if (HAVE_lo_sum
&& GET_CODE (XEXP (x
, 0)) == HIGH
5845 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5850 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5851 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5852 bit-field and can be replaced by either a sign_extend or a
5853 sign_extract. The `and' may be a zero_extend and the two
5854 <c>, -<c> constants may be reversed. */
5855 if (GET_CODE (XEXP (x
, 0)) == XOR
5856 && CONST_INT_P (XEXP (x
, 1))
5857 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5858 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5859 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5860 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5861 && HWI_COMPUTABLE_MODE_P (mode
)
5862 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5863 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5864 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5865 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5866 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5867 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5868 == (unsigned int) i
+ 1))))
5869 return simplify_shift_const
5870 (NULL_RTX
, ASHIFTRT
, mode
,
5871 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5872 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5873 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5874 GET_MODE_PRECISION (mode
) - (i
+ 1));
5876 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5877 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5878 the bitsize of the mode - 1. This allows simplification of
5879 "a = (b & 8) == 0;" */
5880 if (XEXP (x
, 1) == constm1_rtx
5881 && !REG_P (XEXP (x
, 0))
5882 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5883 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5884 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5885 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5886 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5887 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5888 GET_MODE_PRECISION (mode
) - 1),
5889 GET_MODE_PRECISION (mode
) - 1);
5891 /* If we are adding two things that have no bits in common, convert
5892 the addition into an IOR. This will often be further simplified,
5893 for example in cases like ((a & 1) + (a & 2)), which can
5896 if (HWI_COMPUTABLE_MODE_P (mode
)
5897 && (nonzero_bits (XEXP (x
, 0), mode
)
5898 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5900 /* Try to simplify the expression further. */
5901 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5902 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5904 /* If we could, great. If not, do not go ahead with the IOR
5905 replacement, since PLUS appears in many special purpose
5906 address arithmetic instructions. */
5907 if (GET_CODE (temp
) != CLOBBER
5908 && (GET_CODE (temp
) != IOR
5909 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5910 || XEXP (temp
, 1) != XEXP (x
, 1))
5911 && (XEXP (temp
, 0) != XEXP (x
, 1)
5912 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5918 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5919 (and <foo> (const_int pow2-1)) */
5920 if (GET_CODE (XEXP (x
, 1)) == AND
5921 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5922 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5923 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5924 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5925 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5929 /* If we have (mult (plus A B) C), apply the distributive law and then
5930 the inverse distributive law to see if things simplify. This
5931 occurs mostly in addresses, often when unrolling loops. */
5933 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5935 rtx result
= distribute_and_simplify_rtx (x
, 0);
5940 /* Try simplify a*(b/c) as (a*b)/c. */
5941 if (FLOAT_MODE_P (mode
) && flag_associative_math
5942 && GET_CODE (XEXP (x
, 0)) == DIV
)
5944 rtx tem
= simplify_binary_operation (MULT
, mode
,
5945 XEXP (XEXP (x
, 0), 0),
5948 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5953 /* If this is a divide by a power of two, treat it as a shift if
5954 its first operand is a shift. */
5955 if (CONST_INT_P (XEXP (x
, 1))
5956 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5957 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5958 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5959 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5960 || GET_CODE (XEXP (x
, 0)) == ROTATE
5961 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5962 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5966 case GT
: case GTU
: case GE
: case GEU
:
5967 case LT
: case LTU
: case LE
: case LEU
:
5968 case UNEQ
: case LTGT
:
5969 case UNGT
: case UNGE
:
5970 case UNLT
: case UNLE
:
5971 case UNORDERED
: case ORDERED
:
5972 /* If the first operand is a condition code, we can't do anything
5974 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5975 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5976 && ! CC0_P (XEXP (x
, 0))))
5978 rtx op0
= XEXP (x
, 0);
5979 rtx op1
= XEXP (x
, 1);
5980 enum rtx_code new_code
;
5982 if (GET_CODE (op0
) == COMPARE
)
5983 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5985 /* Simplify our comparison, if possible. */
5986 new_code
= simplify_comparison (code
, &op0
, &op1
);
5988 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5989 if only the low-order bit is possibly nonzero in X (such as when
5990 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5991 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5992 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5995 Remove any ZERO_EXTRACT we made when thinking this was a
5996 comparison. It may now be simpler to use, e.g., an AND. If a
5997 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5998 the call to make_compound_operation in the SET case.
6000 Don't apply these optimizations if the caller would
6001 prefer a comparison rather than a value.
6002 E.g., for the condition in an IF_THEN_ELSE most targets need
6003 an explicit comparison. */
6008 else if (STORE_FLAG_VALUE
== 1
6009 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6010 && op1
== const0_rtx
6011 && mode
== GET_MODE (op0
)
6012 && nonzero_bits (op0
, mode
) == 1)
6013 return gen_lowpart (mode
,
6014 expand_compound_operation (op0
));
6016 else if (STORE_FLAG_VALUE
== 1
6017 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6018 && op1
== const0_rtx
6019 && mode
== GET_MODE (op0
)
6020 && (num_sign_bit_copies (op0
, mode
)
6021 == GET_MODE_PRECISION (mode
)))
6023 op0
= expand_compound_operation (op0
);
6024 return simplify_gen_unary (NEG
, mode
,
6025 gen_lowpart (mode
, op0
),
6029 else if (STORE_FLAG_VALUE
== 1
6030 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6031 && op1
== const0_rtx
6032 && mode
== GET_MODE (op0
)
6033 && nonzero_bits (op0
, mode
) == 1)
6035 op0
= expand_compound_operation (op0
);
6036 return simplify_gen_binary (XOR
, mode
,
6037 gen_lowpart (mode
, op0
),
6041 else if (STORE_FLAG_VALUE
== 1
6042 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6043 && op1
== const0_rtx
6044 && mode
== GET_MODE (op0
)
6045 && (num_sign_bit_copies (op0
, mode
)
6046 == GET_MODE_PRECISION (mode
)))
6048 op0
= expand_compound_operation (op0
);
6049 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
6052 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6057 else if (STORE_FLAG_VALUE
== -1
6058 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6059 && op1
== const0_rtx
6060 && mode
== GET_MODE (op0
)
6061 && (num_sign_bit_copies (op0
, mode
)
6062 == GET_MODE_PRECISION (mode
)))
6063 return gen_lowpart (mode
,
6064 expand_compound_operation (op0
));
6066 else if (STORE_FLAG_VALUE
== -1
6067 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6068 && op1
== const0_rtx
6069 && mode
== GET_MODE (op0
)
6070 && nonzero_bits (op0
, mode
) == 1)
6072 op0
= expand_compound_operation (op0
);
6073 return simplify_gen_unary (NEG
, mode
,
6074 gen_lowpart (mode
, op0
),
6078 else if (STORE_FLAG_VALUE
== -1
6079 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6080 && op1
== const0_rtx
6081 && mode
== GET_MODE (op0
)
6082 && (num_sign_bit_copies (op0
, mode
)
6083 == GET_MODE_PRECISION (mode
)))
6085 op0
= expand_compound_operation (op0
);
6086 return simplify_gen_unary (NOT
, mode
,
6087 gen_lowpart (mode
, op0
),
6091 /* If X is 0/1, (eq X 0) is X-1. */
6092 else if (STORE_FLAG_VALUE
== -1
6093 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6094 && op1
== const0_rtx
6095 && mode
== GET_MODE (op0
)
6096 && nonzero_bits (op0
, mode
) == 1)
6098 op0
= expand_compound_operation (op0
);
6099 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
6102 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6103 one bit that might be nonzero, we can convert (ne x 0) to
6104 (ashift x c) where C puts the bit in the sign bit. Remove any
6105 AND with STORE_FLAG_VALUE when we are done, since we are only
6106 going to test the sign bit. */
6107 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6108 && HWI_COMPUTABLE_MODE_P (mode
)
6109 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
6110 && op1
== const0_rtx
6111 && mode
== GET_MODE (op0
)
6112 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
6114 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6115 expand_compound_operation (op0
),
6116 GET_MODE_PRECISION (mode
) - 1 - i
);
6117 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
6123 /* If the code changed, return a whole new comparison.
6124 We also need to avoid using SUBST in cases where
6125 simplify_comparison has widened a comparison with a CONST_INT,
6126 since in that case the wider CONST_INT may fail the sanity
6127 checks in do_SUBST. */
6128 if (new_code
!= code
6129 || (CONST_INT_P (op1
)
6130 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
6131 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
6132 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
6134 /* Otherwise, keep this operation, but maybe change its operands.
6135 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6136 SUBST (XEXP (x
, 0), op0
);
6137 SUBST (XEXP (x
, 1), op1
);
6142 return simplify_if_then_else (x
);
6148 /* If we are processing SET_DEST, we are done. */
6152 return expand_compound_operation (x
);
6155 return simplify_set (x
);
6159 return simplify_logical (x
);
6166 /* If this is a shift by a constant amount, simplify it. */
6167 if (CONST_INT_P (XEXP (x
, 1)))
6168 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6169 INTVAL (XEXP (x
, 1)));
6171 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6173 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6174 ((unsigned HOST_WIDE_INT
) 1
6175 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
6187 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6190 simplify_if_then_else (rtx x
)
6192 machine_mode mode
= GET_MODE (x
);
6193 rtx cond
= XEXP (x
, 0);
6194 rtx true_rtx
= XEXP (x
, 1);
6195 rtx false_rtx
= XEXP (x
, 2);
6196 enum rtx_code true_code
= GET_CODE (cond
);
6197 int comparison_p
= COMPARISON_P (cond
);
6200 enum rtx_code false_code
;
6203 /* Simplify storing of the truth value. */
6204 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6205 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6206 XEXP (cond
, 0), XEXP (cond
, 1));
6208 /* Also when the truth value has to be reversed. */
6210 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6211 && (reversed
= reversed_comparison (cond
, mode
)))
6214 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6215 in it is being compared against certain values. Get the true and false
6216 comparisons and see if that says anything about the value of each arm. */
6219 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6221 && REG_P (XEXP (cond
, 0)))
6224 rtx from
= XEXP (cond
, 0);
6225 rtx true_val
= XEXP (cond
, 1);
6226 rtx false_val
= true_val
;
6229 /* If FALSE_CODE is EQ, swap the codes and arms. */
6231 if (false_code
== EQ
)
6233 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6234 std::swap (true_rtx
, false_rtx
);
6237 /* If we are comparing against zero and the expression being tested has
6238 only a single bit that might be nonzero, that is its value when it is
6239 not equal to zero. Similarly if it is known to be -1 or 0. */
6241 if (true_code
== EQ
&& true_val
== const0_rtx
6242 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
6245 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
6247 else if (true_code
== EQ
&& true_val
== const0_rtx
6248 && (num_sign_bit_copies (from
, GET_MODE (from
))
6249 == GET_MODE_PRECISION (GET_MODE (from
))))
6252 false_val
= constm1_rtx
;
6255 /* Now simplify an arm if we know the value of the register in the
6256 branch and it is used in the arm. Be careful due to the potential
6257 of locally-shared RTL. */
6259 if (reg_mentioned_p (from
, true_rtx
))
6260 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6262 pc_rtx
, pc_rtx
, 0, 0, 0);
6263 if (reg_mentioned_p (from
, false_rtx
))
6264 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6266 pc_rtx
, pc_rtx
, 0, 0, 0);
6268 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6269 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6271 true_rtx
= XEXP (x
, 1);
6272 false_rtx
= XEXP (x
, 2);
6273 true_code
= GET_CODE (cond
);
6276 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6277 reversed, do so to avoid needing two sets of patterns for
6278 subtract-and-branch insns. Similarly if we have a constant in the true
6279 arm, the false arm is the same as the first operand of the comparison, or
6280 the false arm is more complicated than the true arm. */
6283 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6284 && (true_rtx
== pc_rtx
6285 || (CONSTANT_P (true_rtx
)
6286 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6287 || true_rtx
== const0_rtx
6288 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6289 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6290 && !OBJECT_P (false_rtx
))
6291 || reg_mentioned_p (true_rtx
, false_rtx
)
6292 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6294 true_code
= reversed_comparison_code (cond
, NULL
);
6295 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6296 SUBST (XEXP (x
, 1), false_rtx
);
6297 SUBST (XEXP (x
, 2), true_rtx
);
6299 std::swap (true_rtx
, false_rtx
);
6302 /* It is possible that the conditional has been simplified out. */
6303 true_code
= GET_CODE (cond
);
6304 comparison_p
= COMPARISON_P (cond
);
6307 /* If the two arms are identical, we don't need the comparison. */
6309 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6312 /* Convert a == b ? b : a to "a". */
6313 if (true_code
== EQ
&& ! side_effects_p (cond
)
6314 && !HONOR_NANS (mode
)
6315 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6316 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6318 else if (true_code
== NE
&& ! side_effects_p (cond
)
6319 && !HONOR_NANS (mode
)
6320 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6321 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6324 /* Look for cases where we have (abs x) or (neg (abs X)). */
6326 if (GET_MODE_CLASS (mode
) == MODE_INT
6328 && XEXP (cond
, 1) == const0_rtx
6329 && GET_CODE (false_rtx
) == NEG
6330 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6331 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6332 && ! side_effects_p (true_rtx
))
6337 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6341 simplify_gen_unary (NEG
, mode
,
6342 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6348 /* Look for MIN or MAX. */
6350 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6352 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6353 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6354 && ! side_effects_p (cond
))
6359 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6362 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6365 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6368 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6373 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6374 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6375 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6376 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6377 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6378 neither 1 or -1, but it isn't worth checking for. */
6380 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6382 && GET_MODE_CLASS (mode
) == MODE_INT
6383 && ! side_effects_p (x
))
6385 rtx t
= make_compound_operation (true_rtx
, SET
);
6386 rtx f
= make_compound_operation (false_rtx
, SET
);
6387 rtx cond_op0
= XEXP (cond
, 0);
6388 rtx cond_op1
= XEXP (cond
, 1);
6389 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6390 machine_mode m
= mode
;
6391 rtx z
= 0, c1
= NULL_RTX
;
6393 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6394 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6395 || GET_CODE (t
) == ASHIFT
6396 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6397 && rtx_equal_p (XEXP (t
, 0), f
))
6398 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6400 /* If an identity-zero op is commutative, check whether there
6401 would be a match if we swapped the operands. */
6402 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6403 || GET_CODE (t
) == XOR
)
6404 && rtx_equal_p (XEXP (t
, 1), f
))
6405 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6406 else if (GET_CODE (t
) == SIGN_EXTEND
6407 && (GET_CODE (XEXP (t
, 0)) == PLUS
6408 || GET_CODE (XEXP (t
, 0)) == MINUS
6409 || GET_CODE (XEXP (t
, 0)) == IOR
6410 || GET_CODE (XEXP (t
, 0)) == XOR
6411 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6412 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6413 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6414 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6415 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6416 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6417 && (num_sign_bit_copies (f
, GET_MODE (f
))
6419 (GET_MODE_PRECISION (mode
)
6420 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6422 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6423 extend_op
= SIGN_EXTEND
;
6424 m
= GET_MODE (XEXP (t
, 0));
6426 else if (GET_CODE (t
) == SIGN_EXTEND
6427 && (GET_CODE (XEXP (t
, 0)) == PLUS
6428 || GET_CODE (XEXP (t
, 0)) == IOR
6429 || GET_CODE (XEXP (t
, 0)) == XOR
)
6430 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6431 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6432 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6433 && (num_sign_bit_copies (f
, GET_MODE (f
))
6435 (GET_MODE_PRECISION (mode
)
6436 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6438 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6439 extend_op
= SIGN_EXTEND
;
6440 m
= GET_MODE (XEXP (t
, 0));
6442 else if (GET_CODE (t
) == ZERO_EXTEND
6443 && (GET_CODE (XEXP (t
, 0)) == PLUS
6444 || GET_CODE (XEXP (t
, 0)) == MINUS
6445 || GET_CODE (XEXP (t
, 0)) == IOR
6446 || GET_CODE (XEXP (t
, 0)) == XOR
6447 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6448 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6449 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6450 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6451 && HWI_COMPUTABLE_MODE_P (mode
)
6452 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6453 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6454 && ((nonzero_bits (f
, GET_MODE (f
))
6455 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6458 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6459 extend_op
= ZERO_EXTEND
;
6460 m
= GET_MODE (XEXP (t
, 0));
6462 else if (GET_CODE (t
) == ZERO_EXTEND
6463 && (GET_CODE (XEXP (t
, 0)) == PLUS
6464 || GET_CODE (XEXP (t
, 0)) == IOR
6465 || GET_CODE (XEXP (t
, 0)) == XOR
)
6466 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6467 && HWI_COMPUTABLE_MODE_P (mode
)
6468 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6469 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6470 && ((nonzero_bits (f
, GET_MODE (f
))
6471 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6474 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6475 extend_op
= ZERO_EXTEND
;
6476 m
= GET_MODE (XEXP (t
, 0));
6481 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6482 cond_op0
, cond_op1
),
6483 pc_rtx
, pc_rtx
, 0, 0, 0);
6484 temp
= simplify_gen_binary (MULT
, m
, temp
,
6485 simplify_gen_binary (MULT
, m
, c1
,
6487 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6488 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6490 if (extend_op
!= UNKNOWN
)
6491 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6497 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6498 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6499 negation of a single bit, we can convert this operation to a shift. We
6500 can actually do this more generally, but it doesn't seem worth it. */
6502 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6503 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6504 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6505 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6506 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6507 == GET_MODE_PRECISION (mode
))
6508 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6510 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6511 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6513 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6514 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6515 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6516 && GET_MODE (XEXP (cond
, 0)) == mode
6517 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6518 == nonzero_bits (XEXP (cond
, 0), mode
)
6519 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6520 return XEXP (cond
, 0);
6525 /* Simplify X, a SET expression. Return the new expression. */
6528 simplify_set (rtx x
)
6530 rtx src
= SET_SRC (x
);
6531 rtx dest
= SET_DEST (x
);
6533 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6534 rtx_insn
*other_insn
;
6537 /* (set (pc) (return)) gets written as (return). */
6538 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6541 /* Now that we know for sure which bits of SRC we are using, see if we can
6542 simplify the expression for the object knowing that we only need the
6545 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6547 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6548 SUBST (SET_SRC (x
), src
);
6551 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6552 the comparison result and try to simplify it unless we already have used
6553 undobuf.other_insn. */
6554 if ((GET_MODE_CLASS (mode
) == MODE_CC
6555 || GET_CODE (src
) == COMPARE
6557 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6558 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6559 && COMPARISON_P (*cc_use
)
6560 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6562 enum rtx_code old_code
= GET_CODE (*cc_use
);
6563 enum rtx_code new_code
;
6565 int other_changed
= 0;
6566 rtx inner_compare
= NULL_RTX
;
6567 machine_mode compare_mode
= GET_MODE (dest
);
6569 if (GET_CODE (src
) == COMPARE
)
6571 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6572 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6574 inner_compare
= op0
;
6575 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6579 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6581 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6584 new_code
= old_code
;
6585 else if (!CONSTANT_P (tmp
))
6587 new_code
= GET_CODE (tmp
);
6588 op0
= XEXP (tmp
, 0);
6589 op1
= XEXP (tmp
, 1);
6593 rtx pat
= PATTERN (other_insn
);
6594 undobuf
.other_insn
= other_insn
;
6595 SUBST (*cc_use
, tmp
);
6597 /* Attempt to simplify CC user. */
6598 if (GET_CODE (pat
) == SET
)
6600 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6601 if (new_rtx
!= NULL_RTX
)
6602 SUBST (SET_SRC (pat
), new_rtx
);
6605 /* Convert X into a no-op move. */
6606 SUBST (SET_DEST (x
), pc_rtx
);
6607 SUBST (SET_SRC (x
), pc_rtx
);
6611 /* Simplify our comparison, if possible. */
6612 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6614 #ifdef SELECT_CC_MODE
6615 /* If this machine has CC modes other than CCmode, check to see if we
6616 need to use a different CC mode here. */
6617 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6618 compare_mode
= GET_MODE (op0
);
6619 else if (inner_compare
6620 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6621 && new_code
== old_code
6622 && op0
== XEXP (inner_compare
, 0)
6623 && op1
== XEXP (inner_compare
, 1))
6624 compare_mode
= GET_MODE (inner_compare
);
6626 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6628 /* If the mode changed, we have to change SET_DEST, the mode in the
6629 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6630 a hard register, just build new versions with the proper mode. If it
6631 is a pseudo, we lose unless it is only time we set the pseudo, in
6632 which case we can safely change its mode. */
6633 if (!HAVE_cc0
&& compare_mode
!= GET_MODE (dest
))
6635 if (can_change_dest_mode (dest
, 0, compare_mode
))
6637 unsigned int regno
= REGNO (dest
);
6640 if (regno
< FIRST_PSEUDO_REGISTER
)
6641 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6644 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6645 new_dest
= regno_reg_rtx
[regno
];
6648 SUBST (SET_DEST (x
), new_dest
);
6649 SUBST (XEXP (*cc_use
, 0), new_dest
);
6655 #endif /* SELECT_CC_MODE */
6657 /* If the code changed, we have to build a new comparison in
6658 undobuf.other_insn. */
6659 if (new_code
!= old_code
)
6661 int other_changed_previously
= other_changed
;
6662 unsigned HOST_WIDE_INT mask
;
6663 rtx old_cc_use
= *cc_use
;
6665 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6669 /* If the only change we made was to change an EQ into an NE or
6670 vice versa, OP0 has only one bit that might be nonzero, and OP1
6671 is zero, check if changing the user of the condition code will
6672 produce a valid insn. If it won't, we can keep the original code
6673 in that insn by surrounding our operation with an XOR. */
6675 if (((old_code
== NE
&& new_code
== EQ
)
6676 || (old_code
== EQ
&& new_code
== NE
))
6677 && ! other_changed_previously
&& op1
== const0_rtx
6678 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6679 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6681 rtx pat
= PATTERN (other_insn
), note
= 0;
6683 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6684 && ! check_asm_operands (pat
)))
6686 *cc_use
= old_cc_use
;
6689 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6697 undobuf
.other_insn
= other_insn
;
6699 /* Don't generate a compare of a CC with 0, just use that CC. */
6700 if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6702 SUBST (SET_SRC (x
), op0
);
6705 /* Otherwise, if we didn't previously have the same COMPARE we
6706 want, create it from scratch. */
6707 else if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
6708 || XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6710 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6716 /* Get SET_SRC in a form where we have placed back any
6717 compound expressions. Then do the checks below. */
6718 src
= make_compound_operation (src
, SET
);
6719 SUBST (SET_SRC (x
), src
);
6722 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6723 and X being a REG or (subreg (reg)), we may be able to convert this to
6724 (set (subreg:m2 x) (op)).
6726 We can always do this if M1 is narrower than M2 because that means that
6727 we only care about the low bits of the result.
6729 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6730 perform a narrower operation than requested since the high-order bits will
6731 be undefined. On machine where it is defined, this transformation is safe
6732 as long as M1 and M2 have the same number of words. */
6734 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6735 && !OBJECT_P (SUBREG_REG (src
))
6736 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6738 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6739 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6740 #ifndef WORD_REGISTER_OPERATIONS
6741 && (GET_MODE_SIZE (GET_MODE (src
))
6742 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6744 #ifdef CANNOT_CHANGE_MODE_CLASS
6745 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6746 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6747 GET_MODE (SUBREG_REG (src
)),
6751 || (GET_CODE (dest
) == SUBREG
6752 && REG_P (SUBREG_REG (dest
)))))
6754 SUBST (SET_DEST (x
),
6755 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6757 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6759 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6762 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6765 && GET_CODE (src
) == SUBREG
6766 && subreg_lowpart_p (src
)
6767 && (GET_MODE_PRECISION (GET_MODE (src
))
6768 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6770 rtx inner
= SUBREG_REG (src
);
6771 machine_mode inner_mode
= GET_MODE (inner
);
6773 /* Here we make sure that we don't have a sign bit on. */
6774 if (val_signbit_known_clear_p (GET_MODE (src
),
6775 nonzero_bits (inner
, inner_mode
)))
6777 SUBST (SET_SRC (x
), inner
);
6782 #ifdef LOAD_EXTEND_OP
6783 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6784 would require a paradoxical subreg. Replace the subreg with a
6785 zero_extend to avoid the reload that would otherwise be required. */
6787 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6788 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6789 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6790 && SUBREG_BYTE (src
) == 0
6791 && paradoxical_subreg_p (src
)
6792 && MEM_P (SUBREG_REG (src
)))
6795 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6796 GET_MODE (src
), SUBREG_REG (src
)));
6802 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6803 are comparing an item known to be 0 or -1 against 0, use a logical
6804 operation instead. Check for one of the arms being an IOR of the other
6805 arm with some value. We compute three terms to be IOR'ed together. In
6806 practice, at most two will be nonzero. Then we do the IOR's. */
6808 if (GET_CODE (dest
) != PC
6809 && GET_CODE (src
) == IF_THEN_ELSE
6810 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6811 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6812 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6813 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6814 && (!HAVE_conditional_move
6815 || ! can_conditionally_move_p (GET_MODE (src
)))
6816 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6817 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6818 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6819 && ! side_effects_p (src
))
6821 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6822 ? XEXP (src
, 1) : XEXP (src
, 2));
6823 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6824 ? XEXP (src
, 2) : XEXP (src
, 1));
6825 rtx term1
= const0_rtx
, term2
, term3
;
6827 if (GET_CODE (true_rtx
) == IOR
6828 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6829 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6830 else if (GET_CODE (true_rtx
) == IOR
6831 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6832 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6833 else if (GET_CODE (false_rtx
) == IOR
6834 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6835 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6836 else if (GET_CODE (false_rtx
) == IOR
6837 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6838 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6840 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6841 XEXP (XEXP (src
, 0), 0), true_rtx
);
6842 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6843 simplify_gen_unary (NOT
, GET_MODE (src
),
6844 XEXP (XEXP (src
, 0), 0),
6849 simplify_gen_binary (IOR
, GET_MODE (src
),
6850 simplify_gen_binary (IOR
, GET_MODE (src
),
6857 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6858 whole thing fail. */
6859 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6861 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6864 /* Convert this into a field assignment operation, if possible. */
6865 return make_field_assignment (x
);
6868 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6872 simplify_logical (rtx x
)
6874 machine_mode mode
= GET_MODE (x
);
6875 rtx op0
= XEXP (x
, 0);
6876 rtx op1
= XEXP (x
, 1);
6878 switch (GET_CODE (x
))
6881 /* We can call simplify_and_const_int only if we don't lose
6882 any (sign) bits when converting INTVAL (op1) to
6883 "unsigned HOST_WIDE_INT". */
6884 if (CONST_INT_P (op1
)
6885 && (HWI_COMPUTABLE_MODE_P (mode
)
6886 || INTVAL (op1
) > 0))
6888 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6889 if (GET_CODE (x
) != AND
)
6896 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6897 apply the distributive law and then the inverse distributive
6898 law to see if things simplify. */
6899 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6901 rtx result
= distribute_and_simplify_rtx (x
, 0);
6905 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6907 rtx result
= distribute_and_simplify_rtx (x
, 1);
6914 /* If we have (ior (and A B) C), apply the distributive law and then
6915 the inverse distributive law to see if things simplify. */
6917 if (GET_CODE (op0
) == AND
)
6919 rtx result
= distribute_and_simplify_rtx (x
, 0);
6924 if (GET_CODE (op1
) == AND
)
6926 rtx result
= distribute_and_simplify_rtx (x
, 1);
6939 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6940 operations" because they can be replaced with two more basic operations.
6941 ZERO_EXTEND is also considered "compound" because it can be replaced with
6942 an AND operation, which is simpler, though only one operation.
6944 The function expand_compound_operation is called with an rtx expression
6945 and will convert it to the appropriate shifts and AND operations,
6946 simplifying at each stage.
6948 The function make_compound_operation is called to convert an expression
6949 consisting of shifts and ANDs into the equivalent compound expression.
6950 It is the inverse of this function, loosely speaking. */
6953 expand_compound_operation (rtx x
)
6955 unsigned HOST_WIDE_INT pos
= 0, len
;
6957 unsigned int modewidth
;
6960 switch (GET_CODE (x
))
6965 /* We can't necessarily use a const_int for a multiword mode;
6966 it depends on implicitly extending the value.
6967 Since we don't know the right way to extend it,
6968 we can't tell whether the implicit way is right.
6970 Even for a mode that is no wider than a const_int,
6971 we can't win, because we need to sign extend one of its bits through
6972 the rest of it, and we don't know which bit. */
6973 if (CONST_INT_P (XEXP (x
, 0)))
6976 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6977 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6978 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6979 reloaded. If not for that, MEM's would very rarely be safe.
6981 Reject MODEs bigger than a word, because we might not be able
6982 to reference a two-register group starting with an arbitrary register
6983 (and currently gen_lowpart might crash for a SUBREG). */
6985 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6988 /* Reject MODEs that aren't scalar integers because turning vector
6989 or complex modes into shifts causes problems. */
6991 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6994 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
6995 /* If the inner object has VOIDmode (the only way this can happen
6996 is if it is an ASM_OPERANDS), we can't do anything since we don't
6997 know how much masking to do. */
7006 /* ... fall through ... */
7009 /* If the operand is a CLOBBER, just return it. */
7010 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
7013 if (!CONST_INT_P (XEXP (x
, 1))
7014 || !CONST_INT_P (XEXP (x
, 2))
7015 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
7018 /* Reject MODEs that aren't scalar integers because turning vector
7019 or complex modes into shifts causes problems. */
7021 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
7024 len
= INTVAL (XEXP (x
, 1));
7025 pos
= INTVAL (XEXP (x
, 2));
7027 /* This should stay within the object being extracted, fail otherwise. */
7028 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
7031 if (BITS_BIG_ENDIAN
)
7032 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
7039 /* Convert sign extension to zero extension, if we know that the high
7040 bit is not set, as this is easier to optimize. It will be converted
7041 back to cheaper alternative in make_extraction. */
7042 if (GET_CODE (x
) == SIGN_EXTEND
7043 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7044 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7045 & ~(((unsigned HOST_WIDE_INT
)
7046 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
7050 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
7051 rtx temp2
= expand_compound_operation (temp
);
7053 /* Make sure this is a profitable operation. */
7054 if (set_src_cost (x
, optimize_this_for_speed_p
)
7055 > set_src_cost (temp2
, optimize_this_for_speed_p
))
7057 else if (set_src_cost (x
, optimize_this_for_speed_p
)
7058 > set_src_cost (temp
, optimize_this_for_speed_p
))
7064 /* We can optimize some special cases of ZERO_EXTEND. */
7065 if (GET_CODE (x
) == ZERO_EXTEND
)
7067 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7068 know that the last value didn't have any inappropriate bits
7070 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7071 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7072 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7073 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
7074 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7075 return XEXP (XEXP (x
, 0), 0);
7077 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7078 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7079 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7080 && subreg_lowpart_p (XEXP (x
, 0))
7081 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7082 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
7083 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7084 return SUBREG_REG (XEXP (x
, 0));
7086 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7087 is a comparison and STORE_FLAG_VALUE permits. This is like
7088 the first case, but it works even when GET_MODE (x) is larger
7089 than HOST_WIDE_INT. */
7090 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7091 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7092 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
7093 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7094 <= HOST_BITS_PER_WIDE_INT
)
7095 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7096 return XEXP (XEXP (x
, 0), 0);
7098 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7099 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7100 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7101 && subreg_lowpart_p (XEXP (x
, 0))
7102 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
7103 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7104 <= HOST_BITS_PER_WIDE_INT
)
7105 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7106 return SUBREG_REG (XEXP (x
, 0));
7110 /* If we reach here, we want to return a pair of shifts. The inner
7111 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7112 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7113 logical depending on the value of UNSIGNEDP.
7115 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7116 converted into an AND of a shift.
7118 We must check for the case where the left shift would have a negative
7119 count. This can happen in a case like (x >> 31) & 255 on machines
7120 that can't shift by a constant. On those machines, we would first
7121 combine the shift with the AND to produce a variable-position
7122 extraction. Then the constant of 31 would be substituted in
7123 to produce such a position. */
7125 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
7126 if (modewidth
>= pos
+ len
)
7128 machine_mode mode
= GET_MODE (x
);
7129 tem
= gen_lowpart (mode
, XEXP (x
, 0));
7130 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7132 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
7133 tem
, modewidth
- pos
- len
);
7134 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7135 mode
, tem
, modewidth
- len
);
7137 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7138 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
7139 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7142 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
7144 /* Any other cases we can't handle. */
7147 /* If we couldn't do this for some reason, return the original
7149 if (GET_CODE (tem
) == CLOBBER
)
7155 /* X is a SET which contains an assignment of one object into
7156 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7157 or certain SUBREGS). If possible, convert it into a series of
7160 We half-heartedly support variable positions, but do not at all
7161 support variable lengths. */
7164 expand_field_assignment (const_rtx x
)
7167 rtx pos
; /* Always counts from low bit. */
7169 rtx mask
, cleared
, masked
;
7170 machine_mode compute_mode
;
7172 /* Loop until we find something we can't simplify. */
7175 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7176 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7178 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7179 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
7180 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
7182 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7183 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7185 inner
= XEXP (SET_DEST (x
), 0);
7186 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7187 pos
= XEXP (SET_DEST (x
), 2);
7189 /* A constant position should stay within the width of INNER. */
7190 if (CONST_INT_P (pos
)
7191 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
7194 if (BITS_BIG_ENDIAN
)
7196 if (CONST_INT_P (pos
))
7197 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
7199 else if (GET_CODE (pos
) == MINUS
7200 && CONST_INT_P (XEXP (pos
, 1))
7201 && (INTVAL (XEXP (pos
, 1))
7202 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
7203 /* If position is ADJUST - X, new position is X. */
7204 pos
= XEXP (pos
, 0);
7207 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
7208 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7209 gen_int_mode (prec
- len
,
7216 /* A SUBREG between two modes that occupy the same numbers of words
7217 can be done by moving the SUBREG to the source. */
7218 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7219 /* We need SUBREGs to compute nonzero_bits properly. */
7220 && nonzero_sign_valid
7221 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
7222 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
7223 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
7224 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
7226 x
= gen_rtx_SET (SUBREG_REG (SET_DEST (x
)),
7228 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7235 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7236 inner
= SUBREG_REG (inner
);
7238 compute_mode
= GET_MODE (inner
);
7240 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7241 if (! SCALAR_INT_MODE_P (compute_mode
))
7245 /* Don't do anything for vector or complex integral types. */
7246 if (! FLOAT_MODE_P (compute_mode
))
7249 /* Try to find an integral mode to pun with. */
7250 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
7251 if (imode
== BLKmode
)
7254 compute_mode
= imode
;
7255 inner
= gen_lowpart (imode
, inner
);
7258 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7259 if (len
>= HOST_BITS_PER_WIDE_INT
)
7262 /* Now compute the equivalent expression. Make a copy of INNER
7263 for the SET_DEST in case it is a MEM into which we will substitute;
7264 we don't want shared RTL in that case. */
7265 mask
= gen_int_mode (((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7267 cleared
= simplify_gen_binary (AND
, compute_mode
,
7268 simplify_gen_unary (NOT
, compute_mode
,
7269 simplify_gen_binary (ASHIFT
,
7274 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7275 simplify_gen_binary (
7277 gen_lowpart (compute_mode
, SET_SRC (x
)),
7281 x
= gen_rtx_SET (copy_rtx (inner
),
7282 simplify_gen_binary (IOR
, compute_mode
,
7289 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7290 it is an RTX that represents the (variable) starting position; otherwise,
7291 POS is the (constant) starting bit position. Both are counted from the LSB.
7293 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7295 IN_DEST is nonzero if this is a reference in the destination of a SET.
7296 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7297 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7300 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7301 ZERO_EXTRACT should be built even for bits starting at bit 0.
7303 MODE is the desired mode of the result (if IN_DEST == 0).
7305 The result is an RTX for the extraction or NULL_RTX if the target
7309 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7310 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7311 int in_dest
, int in_compare
)
7313 /* This mode describes the size of the storage area
7314 to fetch the overall value from. Within that, we
7315 ignore the POS lowest bits, etc. */
7316 machine_mode is_mode
= GET_MODE (inner
);
7317 machine_mode inner_mode
;
7318 machine_mode wanted_inner_mode
;
7319 machine_mode wanted_inner_reg_mode
= word_mode
;
7320 machine_mode pos_mode
= word_mode
;
7321 machine_mode extraction_mode
= word_mode
;
7322 machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7324 rtx orig_pos_rtx
= pos_rtx
;
7325 HOST_WIDE_INT orig_pos
;
7327 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7328 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7330 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7332 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7333 consider just the QI as the memory to extract from.
7334 The subreg adds or removes high bits; its mode is
7335 irrelevant to the meaning of this extraction,
7336 since POS and LEN count from the lsb. */
7337 if (MEM_P (SUBREG_REG (inner
)))
7338 is_mode
= GET_MODE (SUBREG_REG (inner
));
7339 inner
= SUBREG_REG (inner
);
7341 else if (GET_CODE (inner
) == ASHIFT
7342 && CONST_INT_P (XEXP (inner
, 1))
7343 && pos_rtx
== 0 && pos
== 0
7344 && len
> UINTVAL (XEXP (inner
, 1)))
7346 /* We're extracting the least significant bits of an rtx
7347 (ashift X (const_int C)), where LEN > C. Extract the
7348 least significant (LEN - C) bits of X, giving an rtx
7349 whose mode is MODE, then shift it left C times. */
7350 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7351 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7352 unsignedp
, in_dest
, in_compare
);
7354 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7356 else if (GET_CODE (inner
) == TRUNCATE
)
7357 inner
= XEXP (inner
, 0);
7359 inner_mode
= GET_MODE (inner
);
7361 /* See if this can be done without an extraction. We never can if the
7362 width of the field is not the same as that of some integer mode. For
7363 registers, we can only avoid the extraction if the position is at the
7364 low-order bit and this is either not in the destination or we have the
7365 appropriate STRICT_LOW_PART operation available.
7367 For MEM, we can avoid an extract if the field starts on an appropriate
7368 boundary and we can change the mode of the memory reference. */
7370 if (tmode
!= BLKmode
7371 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7373 && (inner_mode
== tmode
7375 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7376 || reg_truncated_to_mode (tmode
, inner
))
7379 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7380 || (MEM_P (inner
) && pos_rtx
== 0
7382 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7383 : BITS_PER_UNIT
)) == 0
7384 /* We can't do this if we are widening INNER_MODE (it
7385 may not be aligned, for one thing). */
7386 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7387 && (inner_mode
== tmode
7388 || (! mode_dependent_address_p (XEXP (inner
, 0),
7389 MEM_ADDR_SPACE (inner
))
7390 && ! MEM_VOLATILE_P (inner
))))))
7392 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7393 field. If the original and current mode are the same, we need not
7394 adjust the offset. Otherwise, we do if bytes big endian.
7396 If INNER is not a MEM, get a piece consisting of just the field
7397 of interest (in this case POS % BITS_PER_WORD must be 0). */
7401 HOST_WIDE_INT offset
;
7403 /* POS counts from lsb, but make OFFSET count in memory order. */
7404 if (BYTES_BIG_ENDIAN
)
7405 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7407 offset
= pos
/ BITS_PER_UNIT
;
7409 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7411 else if (REG_P (inner
))
7413 if (tmode
!= inner_mode
)
7415 /* We can't call gen_lowpart in a DEST since we
7416 always want a SUBREG (see below) and it would sometimes
7417 return a new hard register. */
7420 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7422 if (WORDS_BIG_ENDIAN
7423 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7424 final_word
= ((GET_MODE_SIZE (inner_mode
)
7425 - GET_MODE_SIZE (tmode
))
7426 / UNITS_PER_WORD
) - final_word
;
7428 final_word
*= UNITS_PER_WORD
;
7429 if (BYTES_BIG_ENDIAN
&&
7430 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7431 final_word
+= (GET_MODE_SIZE (inner_mode
)
7432 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7434 /* Avoid creating invalid subregs, for example when
7435 simplifying (x>>32)&255. */
7436 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7439 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7442 new_rtx
= gen_lowpart (tmode
, inner
);
7448 new_rtx
= force_to_mode (inner
, tmode
,
7449 len
>= HOST_BITS_PER_WIDE_INT
7450 ? ~(unsigned HOST_WIDE_INT
) 0
7451 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7454 /* If this extraction is going into the destination of a SET,
7455 make a STRICT_LOW_PART unless we made a MEM. */
7458 return (MEM_P (new_rtx
) ? new_rtx
7459 : (GET_CODE (new_rtx
) != SUBREG
7460 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7461 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7466 if (CONST_SCALAR_INT_P (new_rtx
))
7467 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7468 mode
, new_rtx
, tmode
);
7470 /* If we know that no extraneous bits are set, and that the high
7471 bit is not set, convert the extraction to the cheaper of
7472 sign and zero extension, that are equivalent in these cases. */
7473 if (flag_expensive_optimizations
7474 && (HWI_COMPUTABLE_MODE_P (tmode
)
7475 && ((nonzero_bits (new_rtx
, tmode
)
7476 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7479 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7480 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7482 /* Prefer ZERO_EXTENSION, since it gives more information to
7484 if (set_src_cost (temp
, optimize_this_for_speed_p
)
7485 <= set_src_cost (temp1
, optimize_this_for_speed_p
))
7490 /* Otherwise, sign- or zero-extend unless we already are in the
7493 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7497 /* Unless this is a COMPARE or we have a funny memory reference,
7498 don't do anything with zero-extending field extracts starting at
7499 the low-order bit since they are simple AND operations. */
7500 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7501 && ! in_compare
&& unsignedp
)
7504 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7505 if the position is not a constant and the length is not 1. In all
7506 other cases, we would only be going outside our object in cases when
7507 an original shift would have been undefined. */
7509 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7510 || (pos_rtx
!= 0 && len
!= 1)))
7513 enum extraction_pattern pattern
= (in_dest
? EP_insv
7514 : unsignedp
? EP_extzv
: EP_extv
);
7516 /* If INNER is not from memory, we want it to have the mode of a register
7517 extraction pattern's structure operand, or word_mode if there is no
7518 such pattern. The same applies to extraction_mode and pos_mode
7519 and their respective operands.
7521 For memory, assume that the desired extraction_mode and pos_mode
7522 are the same as for a register operation, since at present we don't
7523 have named patterns for aligned memory structures. */
7524 struct extraction_insn insn
;
7525 if (get_best_reg_extraction_insn (&insn
, pattern
,
7526 GET_MODE_BITSIZE (inner_mode
), mode
))
7528 wanted_inner_reg_mode
= insn
.struct_mode
;
7529 pos_mode
= insn
.pos_mode
;
7530 extraction_mode
= insn
.field_mode
;
7533 /* Never narrow an object, since that might not be safe. */
7535 if (mode
!= VOIDmode
7536 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7537 extraction_mode
= mode
;
7540 wanted_inner_mode
= wanted_inner_reg_mode
;
7543 /* Be careful not to go beyond the extracted object and maintain the
7544 natural alignment of the memory. */
7545 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7546 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7547 > GET_MODE_BITSIZE (wanted_inner_mode
))
7549 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7550 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7556 if (BITS_BIG_ENDIAN
)
7558 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7559 BITS_BIG_ENDIAN style. If position is constant, compute new
7560 position. Otherwise, build subtraction.
7561 Note that POS is relative to the mode of the original argument.
7562 If it's a MEM we need to recompute POS relative to that.
7563 However, if we're extracting from (or inserting into) a register,
7564 we want to recompute POS relative to wanted_inner_mode. */
7565 int width
= (MEM_P (inner
)
7566 ? GET_MODE_BITSIZE (is_mode
)
7567 : GET_MODE_BITSIZE (wanted_inner_mode
));
7570 pos
= width
- len
- pos
;
7573 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7574 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7576 /* POS may be less than 0 now, but we check for that below.
7577 Note that it can only be less than 0 if !MEM_P (inner). */
7580 /* If INNER has a wider mode, and this is a constant extraction, try to
7581 make it smaller and adjust the byte to point to the byte containing
7583 if (wanted_inner_mode
!= VOIDmode
7584 && inner_mode
!= wanted_inner_mode
7586 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7588 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7589 && ! MEM_VOLATILE_P (inner
))
7593 /* The computations below will be correct if the machine is big
7594 endian in both bits and bytes or little endian in bits and bytes.
7595 If it is mixed, we must adjust. */
7597 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7598 adjust OFFSET to compensate. */
7599 if (BYTES_BIG_ENDIAN
7600 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7601 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7603 /* We can now move to the desired byte. */
7604 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7605 * GET_MODE_SIZE (wanted_inner_mode
);
7606 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7608 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7609 && is_mode
!= wanted_inner_mode
)
7610 offset
= (GET_MODE_SIZE (is_mode
)
7611 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7613 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7616 /* If INNER is not memory, get it into the proper mode. If we are changing
7617 its mode, POS must be a constant and smaller than the size of the new
7619 else if (!MEM_P (inner
))
7621 /* On the LHS, don't create paradoxical subregs implicitely truncating
7622 the register unless TRULY_NOOP_TRUNCATION. */
7624 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7628 if (GET_MODE (inner
) != wanted_inner_mode
7630 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7636 inner
= force_to_mode (inner
, wanted_inner_mode
,
7638 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7639 ? ~(unsigned HOST_WIDE_INT
) 0
7640 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7645 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7646 have to zero extend. Otherwise, we can just use a SUBREG. */
7648 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7650 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7651 GET_MODE (pos_rtx
));
7653 /* If we know that no extraneous bits are set, and that the high
7654 bit is not set, convert extraction to cheaper one - either
7655 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7657 if (flag_expensive_optimizations
7658 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7659 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7660 & ~(((unsigned HOST_WIDE_INT
)
7661 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7665 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7666 GET_MODE (pos_rtx
));
7668 /* Prefer ZERO_EXTENSION, since it gives more information to
7670 if (set_src_cost (temp1
, optimize_this_for_speed_p
)
7671 < set_src_cost (temp
, optimize_this_for_speed_p
))
7677 /* Make POS_RTX unless we already have it and it is correct. If we don't
7678 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7680 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7681 pos_rtx
= orig_pos_rtx
;
7683 else if (pos_rtx
== 0)
7684 pos_rtx
= GEN_INT (pos
);
7686 /* Make the required operation. See if we can use existing rtx. */
7687 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7688 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7690 new_rtx
= gen_lowpart (mode
, new_rtx
);
7695 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7696 with any other operations in X. Return X without that shift if so. */
7699 extract_left_shift (rtx x
, int count
)
7701 enum rtx_code code
= GET_CODE (x
);
7702 machine_mode mode
= GET_MODE (x
);
7708 /* This is the shift itself. If it is wide enough, we will return
7709 either the value being shifted if the shift count is equal to
7710 COUNT or a shift for the difference. */
7711 if (CONST_INT_P (XEXP (x
, 1))
7712 && INTVAL (XEXP (x
, 1)) >= count
)
7713 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7714 INTVAL (XEXP (x
, 1)) - count
);
7718 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7719 return simplify_gen_unary (code
, mode
, tem
, mode
);
7723 case PLUS
: case IOR
: case XOR
: case AND
:
7724 /* If we can safely shift this constant and we find the inner shift,
7725 make a new operation. */
7726 if (CONST_INT_P (XEXP (x
, 1))
7727 && (UINTVAL (XEXP (x
, 1))
7728 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7729 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7731 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7732 return simplify_gen_binary (code
, mode
, tem
,
7733 gen_int_mode (val
, mode
));
7744 /* Look at the expression rooted at X. Look for expressions
7745 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7746 Form these expressions.
7748 Return the new rtx, usually just X.
7750 Also, for machines like the VAX that don't have logical shift insns,
7751 try to convert logical to arithmetic shift operations in cases where
7752 they are equivalent. This undoes the canonicalizations to logical
7753 shifts done elsewhere.
7755 We try, as much as possible, to re-use rtl expressions to save memory.
7757 IN_CODE says what kind of expression we are processing. Normally, it is
7758 SET. In a memory address it is MEM. When processing the arguments of
7759 a comparison or a COMPARE against zero, it is COMPARE. */
7762 make_compound_operation (rtx x
, enum rtx_code in_code
)
7764 enum rtx_code code
= GET_CODE (x
);
7765 machine_mode mode
= GET_MODE (x
);
7766 int mode_width
= GET_MODE_PRECISION (mode
);
7768 enum rtx_code next_code
;
7774 /* Select the code to be used in recursive calls. Once we are inside an
7775 address, we stay there. If we have a comparison, set to COMPARE,
7776 but once inside, go back to our default of SET. */
7778 next_code
= (code
== MEM
? MEM
7779 : ((code
== COMPARE
|| COMPARISON_P (x
))
7780 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7781 : in_code
== COMPARE
? SET
: in_code
);
7783 /* Process depending on the code of this operation. If NEW is set
7784 nonzero, it will be returned. */
7789 /* Convert shifts by constants into multiplications if inside
7791 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7792 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7793 && INTVAL (XEXP (x
, 1)) >= 0
7794 && SCALAR_INT_MODE_P (mode
))
7796 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7797 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7799 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7800 if (GET_CODE (new_rtx
) == NEG
)
7802 new_rtx
= XEXP (new_rtx
, 0);
7805 multval
= trunc_int_for_mode (multval
, mode
);
7806 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7813 lhs
= make_compound_operation (lhs
, next_code
);
7814 rhs
= make_compound_operation (rhs
, next_code
);
7815 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7816 && SCALAR_INT_MODE_P (mode
))
7818 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7820 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7822 else if (GET_CODE (lhs
) == MULT
7823 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7825 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7826 simplify_gen_unary (NEG
, mode
,
7829 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7833 SUBST (XEXP (x
, 0), lhs
);
7834 SUBST (XEXP (x
, 1), rhs
);
7837 x
= gen_lowpart (mode
, new_rtx
);
7843 lhs
= make_compound_operation (lhs
, next_code
);
7844 rhs
= make_compound_operation (rhs
, next_code
);
7845 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7846 && SCALAR_INT_MODE_P (mode
))
7848 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7850 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7852 else if (GET_CODE (rhs
) == MULT
7853 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7855 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7856 simplify_gen_unary (NEG
, mode
,
7859 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7863 SUBST (XEXP (x
, 0), lhs
);
7864 SUBST (XEXP (x
, 1), rhs
);
7867 return gen_lowpart (mode
, new_rtx
);
7870 /* If the second operand is not a constant, we can't do anything
7872 if (!CONST_INT_P (XEXP (x
, 1)))
7875 /* If the constant is a power of two minus one and the first operand
7876 is a logical right shift, make an extraction. */
7877 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7878 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7880 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7881 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7882 0, in_code
== COMPARE
);
7885 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7886 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7887 && subreg_lowpart_p (XEXP (x
, 0))
7888 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7889 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7891 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7893 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7894 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7895 0, in_code
== COMPARE
);
7897 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7898 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7899 || GET_CODE (XEXP (x
, 0)) == IOR
)
7900 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7901 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7902 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7904 /* Apply the distributive law, and then try to make extractions. */
7905 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7906 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7908 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7910 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7913 /* If we are have (and (rotate X C) M) and C is larger than the number
7914 of bits in M, this is an extraction. */
7916 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7917 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7918 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7919 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7921 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7922 new_rtx
= make_extraction (mode
, new_rtx
,
7923 (GET_MODE_PRECISION (mode
)
7924 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7925 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7928 /* On machines without logical shifts, if the operand of the AND is
7929 a logical shift and our mask turns off all the propagated sign
7930 bits, we can replace the logical shift with an arithmetic shift. */
7931 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7932 && !have_insn_for (LSHIFTRT
, mode
)
7933 && have_insn_for (ASHIFTRT
, mode
)
7934 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7935 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7936 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7937 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7939 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7941 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7942 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7944 gen_rtx_ASHIFTRT (mode
,
7945 make_compound_operation
7946 (XEXP (XEXP (x
, 0), 0), next_code
),
7947 XEXP (XEXP (x
, 0), 1)));
7950 /* If the constant is one less than a power of two, this might be
7951 representable by an extraction even if no shift is present.
7952 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7953 we are in a COMPARE. */
7954 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7955 new_rtx
= make_extraction (mode
,
7956 make_compound_operation (XEXP (x
, 0),
7958 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7960 /* If we are in a comparison and this is an AND with a power of two,
7961 convert this into the appropriate bit extract. */
7962 else if (in_code
== COMPARE
7963 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7964 new_rtx
= make_extraction (mode
,
7965 make_compound_operation (XEXP (x
, 0),
7967 i
, NULL_RTX
, 1, 1, 0, 1);
7972 /* If the sign bit is known to be zero, replace this with an
7973 arithmetic shift. */
7974 if (have_insn_for (ASHIFTRT
, mode
)
7975 && ! have_insn_for (LSHIFTRT
, mode
)
7976 && mode_width
<= HOST_BITS_PER_WIDE_INT
7977 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7979 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7980 make_compound_operation (XEXP (x
, 0),
7986 /* ... fall through ... */
7992 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7993 this is a SIGN_EXTRACT. */
7994 if (CONST_INT_P (rhs
)
7995 && GET_CODE (lhs
) == ASHIFT
7996 && CONST_INT_P (XEXP (lhs
, 1))
7997 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7998 && INTVAL (XEXP (lhs
, 1)) >= 0
7999 && INTVAL (rhs
) < mode_width
)
8001 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
8002 new_rtx
= make_extraction (mode
, new_rtx
,
8003 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
8004 NULL_RTX
, mode_width
- INTVAL (rhs
),
8005 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8009 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8010 If so, try to merge the shifts into a SIGN_EXTEND. We could
8011 also do this for some cases of SIGN_EXTRACT, but it doesn't
8012 seem worth the effort; the case checked for occurs on Alpha. */
8015 && ! (GET_CODE (lhs
) == SUBREG
8016 && (OBJECT_P (SUBREG_REG (lhs
))))
8017 && CONST_INT_P (rhs
)
8018 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
8019 && INTVAL (rhs
) < mode_width
8020 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
8021 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
8022 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
8023 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8028 /* Call ourselves recursively on the inner expression. If we are
8029 narrowing the object and it has a different RTL code from
8030 what it originally did, do this SUBREG as a force_to_mode. */
8032 rtx inner
= SUBREG_REG (x
), simplified
;
8033 enum rtx_code subreg_code
= in_code
;
8035 /* If in_code is COMPARE, it isn't always safe to pass it through
8036 to the recursive make_compound_operation call. */
8037 if (subreg_code
== COMPARE
8038 && (!subreg_lowpart_p (x
)
8039 || GET_CODE (inner
) == SUBREG
8040 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8041 is (const_int 0), rather than
8042 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8043 || (GET_CODE (inner
) == AND
8044 && CONST_INT_P (XEXP (inner
, 1))
8045 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8046 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
8047 >= GET_MODE_BITSIZE (mode
))))
8050 tem
= make_compound_operation (inner
, subreg_code
);
8053 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
8057 if (GET_CODE (tem
) != GET_CODE (inner
)
8058 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8059 && subreg_lowpart_p (x
))
8062 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
8064 /* If we have something other than a SUBREG, we might have
8065 done an expansion, so rerun ourselves. */
8066 if (GET_CODE (newer
) != SUBREG
)
8067 newer
= make_compound_operation (newer
, in_code
);
8069 /* force_to_mode can expand compounds. If it just re-expanded the
8070 compound, use gen_lowpart to convert to the desired mode. */
8071 if (rtx_equal_p (newer
, x
)
8072 /* Likewise if it re-expanded the compound only partially.
8073 This happens for SUBREG of ZERO_EXTRACT if they extract
8074 the same number of bits. */
8075 || (GET_CODE (newer
) == SUBREG
8076 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
8077 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
8078 && GET_CODE (inner
) == AND
8079 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
8080 return gen_lowpart (GET_MODE (x
), tem
);
8096 x
= gen_lowpart (mode
, new_rtx
);
8097 code
= GET_CODE (x
);
8100 /* Now recursively process each operand of this operation. We need to
8101 handle ZERO_EXTEND specially so that we don't lose track of the
8103 if (GET_CODE (x
) == ZERO_EXTEND
)
8105 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8106 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8107 new_rtx
, GET_MODE (XEXP (x
, 0)));
8110 SUBST (XEXP (x
, 0), new_rtx
);
8114 fmt
= GET_RTX_FORMAT (code
);
8115 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8118 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
8119 SUBST (XEXP (x
, i
), new_rtx
);
8121 else if (fmt
[i
] == 'E')
8122 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8124 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
8125 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
8129 /* If this is a commutative operation, the changes to the operands
8130 may have made it noncanonical. */
8131 if (COMMUTATIVE_ARITH_P (x
)
8132 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
8135 SUBST (XEXP (x
, 0), XEXP (x
, 1));
8136 SUBST (XEXP (x
, 1), tem
);
8142 /* Given M see if it is a value that would select a field of bits
8143 within an item, but not the entire word. Return -1 if not.
8144 Otherwise, return the starting position of the field, where 0 is the
8147 *PLEN is set to the length of the field. */
8150 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8152 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8153 int pos
= m
? ctz_hwi (m
) : -1;
8157 /* Now shift off the low-order zero bits and see if we have a
8158 power of two minus 1. */
8159 len
= exact_log2 ((m
>> pos
) + 1);
8168 /* If X refers to a register that equals REG in value, replace these
8169 references with REG. */
8171 canon_reg_for_combine (rtx x
, rtx reg
)
8178 enum rtx_code code
= GET_CODE (x
);
8179 switch (GET_RTX_CLASS (code
))
8182 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8183 if (op0
!= XEXP (x
, 0))
8184 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8189 case RTX_COMM_ARITH
:
8190 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8191 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8192 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8193 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8197 case RTX_COMM_COMPARE
:
8198 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8199 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8200 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8201 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8202 GET_MODE (op0
), op0
, op1
);
8206 case RTX_BITFIELD_OPS
:
8207 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8208 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8209 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8210 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8211 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8212 GET_MODE (op0
), op0
, op1
, op2
);
8217 if (rtx_equal_p (get_last_value (reg
), x
)
8218 || rtx_equal_p (reg
, get_last_value (x
)))
8227 fmt
= GET_RTX_FORMAT (code
);
8229 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8232 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8233 if (op
!= XEXP (x
, i
))
8243 else if (fmt
[i
] == 'E')
8246 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8248 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8249 if (op
!= XVECEXP (x
, i
, j
))
8256 XVECEXP (x
, i
, j
) = op
;
8267 /* Return X converted to MODE. If the value is already truncated to
8268 MODE we can just return a subreg even though in the general case we
8269 would need an explicit truncation. */
8272 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8274 if (!CONST_INT_P (x
)
8275 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8276 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8277 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8279 /* Bit-cast X into an integer mode. */
8280 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8281 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
8282 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
8286 return gen_lowpart (mode
, x
);
8289 /* See if X can be simplified knowing that we will only refer to it in
8290 MODE and will only refer to those bits that are nonzero in MASK.
8291 If other bits are being computed or if masking operations are done
8292 that select a superset of the bits in MASK, they can sometimes be
8295 Return a possibly simplified expression, but always convert X to
8296 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8298 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8299 are all off in X. This is used when X will be complemented, by either
8300 NOT, NEG, or XOR. */
8303 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8306 enum rtx_code code
= GET_CODE (x
);
8307 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8308 machine_mode op_mode
;
8309 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8312 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8313 code below will do the wrong thing since the mode of such an
8314 expression is VOIDmode.
8316 Also do nothing if X is a CLOBBER; this can happen if X was
8317 the return value from a call to gen_lowpart. */
8318 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8321 /* We want to perform the operation in its present mode unless we know
8322 that the operation is valid in MODE, in which case we do the operation
8324 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8325 && have_insn_for (code
, mode
))
8326 ? mode
: GET_MODE (x
));
8328 /* It is not valid to do a right-shift in a narrower mode
8329 than the one it came in with. */
8330 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8331 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8332 op_mode
= GET_MODE (x
);
8334 /* Truncate MASK to fit OP_MODE. */
8336 mask
&= GET_MODE_MASK (op_mode
);
8338 /* When we have an arithmetic operation, or a shift whose count we
8339 do not know, we need to assume that all bits up to the highest-order
8340 bit in MASK will be needed. This is how we form such a mask. */
8341 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
8342 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8344 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
8347 /* Determine what bits of X are guaranteed to be (non)zero. */
8348 nonzero
= nonzero_bits (x
, mode
);
8350 /* If none of the bits in X are needed, return a zero. */
8351 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8354 /* If X is a CONST_INT, return a new one. Do this here since the
8355 test below will fail. */
8356 if (CONST_INT_P (x
))
8358 if (SCALAR_INT_MODE_P (mode
))
8359 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8362 x
= GEN_INT (INTVAL (x
) & mask
);
8363 return gen_lowpart_common (mode
, x
);
8367 /* If X is narrower than MODE and we want all the bits in X's mode, just
8368 get X in the proper mode. */
8369 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8370 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8371 return gen_lowpart (mode
, x
);
8373 /* We can ignore the effect of a SUBREG if it narrows the mode or
8374 if the constant masks to zero all the bits the mode doesn't have. */
8375 if (GET_CODE (x
) == SUBREG
8376 && subreg_lowpart_p (x
)
8377 && ((GET_MODE_SIZE (GET_MODE (x
))
8378 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8380 & GET_MODE_MASK (GET_MODE (x
))
8381 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8382 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8384 /* The arithmetic simplifications here only work for scalar integer modes. */
8385 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8386 return gen_lowpart_or_truncate (mode
, x
);
8391 /* If X is a (clobber (const_int)), return it since we know we are
8392 generating something that won't match. */
8399 x
= expand_compound_operation (x
);
8400 if (GET_CODE (x
) != code
)
8401 return force_to_mode (x
, mode
, mask
, next_select
);
8405 /* Similarly for a truncate. */
8406 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8409 /* If this is an AND with a constant, convert it into an AND
8410 whose constant is the AND of that constant with MASK. If it
8411 remains an AND of MASK, delete it since it is redundant. */
8413 if (CONST_INT_P (XEXP (x
, 1)))
8415 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8416 mask
& INTVAL (XEXP (x
, 1)));
8418 /* If X is still an AND, see if it is an AND with a mask that
8419 is just some low-order bits. If so, and it is MASK, we don't
8422 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8423 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8427 /* If it remains an AND, try making another AND with the bits
8428 in the mode mask that aren't in MASK turned on. If the
8429 constant in the AND is wide enough, this might make a
8430 cheaper constant. */
8432 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8433 && GET_MODE_MASK (GET_MODE (x
)) != mask
8434 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8436 unsigned HOST_WIDE_INT cval
8437 = UINTVAL (XEXP (x
, 1))
8438 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8441 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8442 gen_int_mode (cval
, GET_MODE (x
)));
8443 if (set_src_cost (y
, optimize_this_for_speed_p
)
8444 < set_src_cost (x
, optimize_this_for_speed_p
))
8454 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8455 low-order bits (as in an alignment operation) and FOO is already
8456 aligned to that boundary, mask C1 to that boundary as well.
8457 This may eliminate that PLUS and, later, the AND. */
8460 unsigned int width
= GET_MODE_PRECISION (mode
);
8461 unsigned HOST_WIDE_INT smask
= mask
;
8463 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8464 number, sign extend it. */
8466 if (width
< HOST_BITS_PER_WIDE_INT
8467 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8468 smask
|= HOST_WIDE_INT_M1U
<< width
;
8470 if (CONST_INT_P (XEXP (x
, 1))
8471 && exact_log2 (- smask
) >= 0
8472 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8473 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8474 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8475 (INTVAL (XEXP (x
, 1)) & smask
)),
8476 mode
, smask
, next_select
);
8479 /* ... fall through ... */
8482 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8483 most significant bit in MASK since carries from those bits will
8484 affect the bits we are interested in. */
8489 /* If X is (minus C Y) where C's least set bit is larger than any bit
8490 in the mask, then we may replace with (neg Y). */
8491 if (CONST_INT_P (XEXP (x
, 0))
8492 && ((UINTVAL (XEXP (x
, 0)) & -UINTVAL (XEXP (x
, 0))) > mask
))
8494 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8496 return force_to_mode (x
, mode
, mask
, next_select
);
8499 /* Similarly, if C contains every bit in the fuller_mask, then we may
8500 replace with (not Y). */
8501 if (CONST_INT_P (XEXP (x
, 0))
8502 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8504 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8505 XEXP (x
, 1), GET_MODE (x
));
8506 return force_to_mode (x
, mode
, mask
, next_select
);
8514 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8515 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8516 operation which may be a bitfield extraction. Ensure that the
8517 constant we form is not wider than the mode of X. */
8519 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8520 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8521 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8522 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8523 && CONST_INT_P (XEXP (x
, 1))
8524 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8525 + floor_log2 (INTVAL (XEXP (x
, 1))))
8526 < GET_MODE_PRECISION (GET_MODE (x
)))
8527 && (UINTVAL (XEXP (x
, 1))
8528 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8530 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8531 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8533 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8534 XEXP (XEXP (x
, 0), 0), temp
);
8535 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8536 XEXP (XEXP (x
, 0), 1));
8537 return force_to_mode (x
, mode
, mask
, next_select
);
8541 /* For most binary operations, just propagate into the operation and
8542 change the mode if we have an operation of that mode. */
8544 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8545 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8547 /* If we ended up truncating both operands, truncate the result of the
8548 operation instead. */
8549 if (GET_CODE (op0
) == TRUNCATE
8550 && GET_CODE (op1
) == TRUNCATE
)
8552 op0
= XEXP (op0
, 0);
8553 op1
= XEXP (op1
, 0);
8556 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8557 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8559 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8560 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8564 /* For left shifts, do the same, but just for the first operand.
8565 However, we cannot do anything with shifts where we cannot
8566 guarantee that the counts are smaller than the size of the mode
8567 because such a count will have a different meaning in a
8570 if (! (CONST_INT_P (XEXP (x
, 1))
8571 && INTVAL (XEXP (x
, 1)) >= 0
8572 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8573 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8574 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8575 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8578 /* If the shift count is a constant and we can do arithmetic in
8579 the mode of the shift, refine which bits we need. Otherwise, use the
8580 conservative form of the mask. */
8581 if (CONST_INT_P (XEXP (x
, 1))
8582 && INTVAL (XEXP (x
, 1)) >= 0
8583 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8584 && HWI_COMPUTABLE_MODE_P (op_mode
))
8585 mask
>>= INTVAL (XEXP (x
, 1));
8589 op0
= gen_lowpart_or_truncate (op_mode
,
8590 force_to_mode (XEXP (x
, 0), op_mode
,
8591 mask
, next_select
));
8593 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8594 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8598 /* Here we can only do something if the shift count is a constant,
8599 this shift constant is valid for the host, and we can do arithmetic
8602 if (CONST_INT_P (XEXP (x
, 1))
8603 && INTVAL (XEXP (x
, 1)) >= 0
8604 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8605 && HWI_COMPUTABLE_MODE_P (op_mode
))
8607 rtx inner
= XEXP (x
, 0);
8608 unsigned HOST_WIDE_INT inner_mask
;
8610 /* Select the mask of the bits we need for the shift operand. */
8611 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8613 /* We can only change the mode of the shift if we can do arithmetic
8614 in the mode of the shift and INNER_MASK is no wider than the
8615 width of X's mode. */
8616 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8617 op_mode
= GET_MODE (x
);
8619 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8621 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8622 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8625 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8626 shift and AND produces only copies of the sign bit (C2 is one less
8627 than a power of two), we can do this with just a shift. */
8629 if (GET_CODE (x
) == LSHIFTRT
8630 && CONST_INT_P (XEXP (x
, 1))
8631 /* The shift puts one of the sign bit copies in the least significant
8633 && ((INTVAL (XEXP (x
, 1))
8634 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8635 >= GET_MODE_PRECISION (GET_MODE (x
)))
8636 && exact_log2 (mask
+ 1) >= 0
8637 /* Number of bits left after the shift must be more than the mask
8639 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8640 <= GET_MODE_PRECISION (GET_MODE (x
)))
8641 /* Must be more sign bit copies than the mask needs. */
8642 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8643 >= exact_log2 (mask
+ 1)))
8644 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8645 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8646 - exact_log2 (mask
+ 1)));
8651 /* If we are just looking for the sign bit, we don't need this shift at
8652 all, even if it has a variable count. */
8653 if (val_signbit_p (GET_MODE (x
), mask
))
8654 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8656 /* If this is a shift by a constant, get a mask that contains those bits
8657 that are not copies of the sign bit. We then have two cases: If
8658 MASK only includes those bits, this can be a logical shift, which may
8659 allow simplifications. If MASK is a single-bit field not within
8660 those bits, we are requesting a copy of the sign bit and hence can
8661 shift the sign bit to the appropriate location. */
8663 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8664 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8668 /* If the considered data is wider than HOST_WIDE_INT, we can't
8669 represent a mask for all its bits in a single scalar.
8670 But we only care about the lower bits, so calculate these. */
8672 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8674 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8676 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8677 is the number of bits a full-width mask would have set.
8678 We need only shift if these are fewer than nonzero can
8679 hold. If not, we must keep all bits set in nonzero. */
8681 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8682 < HOST_BITS_PER_WIDE_INT
)
8683 nonzero
>>= INTVAL (XEXP (x
, 1))
8684 + HOST_BITS_PER_WIDE_INT
8685 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8689 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8690 nonzero
>>= INTVAL (XEXP (x
, 1));
8693 if ((mask
& ~nonzero
) == 0)
8695 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8696 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8697 if (GET_CODE (x
) != ASHIFTRT
)
8698 return force_to_mode (x
, mode
, mask
, next_select
);
8701 else if ((i
= exact_log2 (mask
)) >= 0)
8703 x
= simplify_shift_const
8704 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8705 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8707 if (GET_CODE (x
) != ASHIFTRT
)
8708 return force_to_mode (x
, mode
, mask
, next_select
);
8712 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8713 even if the shift count isn't a constant. */
8715 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8716 XEXP (x
, 0), XEXP (x
, 1));
8720 /* If this is a zero- or sign-extension operation that just affects bits
8721 we don't care about, remove it. Be sure the call above returned
8722 something that is still a shift. */
8724 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8725 && CONST_INT_P (XEXP (x
, 1))
8726 && INTVAL (XEXP (x
, 1)) >= 0
8727 && (INTVAL (XEXP (x
, 1))
8728 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8729 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8730 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8731 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8738 /* If the shift count is constant and we can do computations
8739 in the mode of X, compute where the bits we care about are.
8740 Otherwise, we can't do anything. Don't change the mode of
8741 the shift or propagate MODE into the shift, though. */
8742 if (CONST_INT_P (XEXP (x
, 1))
8743 && INTVAL (XEXP (x
, 1)) >= 0)
8745 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8747 gen_int_mode (mask
, GET_MODE (x
)),
8749 if (temp
&& CONST_INT_P (temp
))
8750 x
= simplify_gen_binary (code
, GET_MODE (x
),
8751 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8752 INTVAL (temp
), next_select
),
8758 /* If we just want the low-order bit, the NEG isn't needed since it
8759 won't change the low-order bit. */
8761 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8763 /* We need any bits less significant than the most significant bit in
8764 MASK since carries from those bits will affect the bits we are
8770 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8771 same as the XOR case above. Ensure that the constant we form is not
8772 wider than the mode of X. */
8774 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8775 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8776 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8777 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8778 < GET_MODE_PRECISION (GET_MODE (x
)))
8779 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8781 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8783 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8784 XEXP (XEXP (x
, 0), 0), temp
);
8785 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8786 temp
, XEXP (XEXP (x
, 0), 1));
8788 return force_to_mode (x
, mode
, mask
, next_select
);
8791 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8792 use the full mask inside the NOT. */
8796 op0
= gen_lowpart_or_truncate (op_mode
,
8797 force_to_mode (XEXP (x
, 0), mode
, mask
,
8799 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8800 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8804 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8805 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8806 which is equal to STORE_FLAG_VALUE. */
8807 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8808 && XEXP (x
, 1) == const0_rtx
8809 && GET_MODE (XEXP (x
, 0)) == mode
8810 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8811 && (nonzero_bits (XEXP (x
, 0), mode
)
8812 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8813 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8818 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8819 written in a narrower mode. We play it safe and do not do so. */
8821 op0
= gen_lowpart_or_truncate (GET_MODE (x
),
8822 force_to_mode (XEXP (x
, 1), mode
,
8823 mask
, next_select
));
8824 op1
= gen_lowpart_or_truncate (GET_MODE (x
),
8825 force_to_mode (XEXP (x
, 2), mode
,
8826 mask
, next_select
));
8827 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
8828 x
= simplify_gen_ternary (IF_THEN_ELSE
, GET_MODE (x
),
8829 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
8837 /* Ensure we return a value of the proper mode. */
8838 return gen_lowpart_or_truncate (mode
, x
);
8841 /* Return nonzero if X is an expression that has one of two values depending on
8842 whether some other value is zero or nonzero. In that case, we return the
8843 value that is being tested, *PTRUE is set to the value if the rtx being
8844 returned has a nonzero value, and *PFALSE is set to the other alternative.
8846 If we return zero, we set *PTRUE and *PFALSE to X. */
8849 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8851 machine_mode mode
= GET_MODE (x
);
8852 enum rtx_code code
= GET_CODE (x
);
8853 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8854 unsigned HOST_WIDE_INT nz
;
8856 /* If we are comparing a value against zero, we are done. */
8857 if ((code
== NE
|| code
== EQ
)
8858 && XEXP (x
, 1) == const0_rtx
)
8860 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8861 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8865 /* If this is a unary operation whose operand has one of two values, apply
8866 our opcode to compute those values. */
8867 else if (UNARY_P (x
)
8868 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8870 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8871 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8872 GET_MODE (XEXP (x
, 0)));
8876 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8877 make can't possibly match and would suppress other optimizations. */
8878 else if (code
== COMPARE
)
8881 /* If this is a binary operation, see if either side has only one of two
8882 values. If either one does or if both do and they are conditional on
8883 the same value, compute the new true and false values. */
8884 else if (BINARY_P (x
))
8886 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8887 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8889 if ((cond0
!= 0 || cond1
!= 0)
8890 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8892 /* If if_then_else_cond returned zero, then true/false are the
8893 same rtl. We must copy one of them to prevent invalid rtl
8896 true0
= copy_rtx (true0
);
8897 else if (cond1
== 0)
8898 true1
= copy_rtx (true1
);
8900 if (COMPARISON_P (x
))
8902 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8904 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8909 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8910 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8913 return cond0
? cond0
: cond1
;
8916 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8917 operands is zero when the other is nonzero, and vice-versa,
8918 and STORE_FLAG_VALUE is 1 or -1. */
8920 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8921 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8923 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8925 rtx op0
= XEXP (XEXP (x
, 0), 1);
8926 rtx op1
= XEXP (XEXP (x
, 1), 1);
8928 cond0
= XEXP (XEXP (x
, 0), 0);
8929 cond1
= XEXP (XEXP (x
, 1), 0);
8931 if (COMPARISON_P (cond0
)
8932 && COMPARISON_P (cond1
)
8933 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8934 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8935 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8936 || ((swap_condition (GET_CODE (cond0
))
8937 == reversed_comparison_code (cond1
, NULL
))
8938 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8939 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8940 && ! side_effects_p (x
))
8942 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8943 *pfalse
= simplify_gen_binary (MULT
, mode
,
8945 ? simplify_gen_unary (NEG
, mode
,
8953 /* Similarly for MULT, AND and UMIN, except that for these the result
8955 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8956 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8957 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8959 cond0
= XEXP (XEXP (x
, 0), 0);
8960 cond1
= XEXP (XEXP (x
, 1), 0);
8962 if (COMPARISON_P (cond0
)
8963 && COMPARISON_P (cond1
)
8964 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8965 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8966 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8967 || ((swap_condition (GET_CODE (cond0
))
8968 == reversed_comparison_code (cond1
, NULL
))
8969 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8970 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8971 && ! side_effects_p (x
))
8973 *ptrue
= *pfalse
= const0_rtx
;
8979 else if (code
== IF_THEN_ELSE
)
8981 /* If we have IF_THEN_ELSE already, extract the condition and
8982 canonicalize it if it is NE or EQ. */
8983 cond0
= XEXP (x
, 0);
8984 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8985 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8986 return XEXP (cond0
, 0);
8987 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8989 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8990 return XEXP (cond0
, 0);
8996 /* If X is a SUBREG, we can narrow both the true and false values
8997 if the inner expression, if there is a condition. */
8998 else if (code
== SUBREG
8999 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
9002 true0
= simplify_gen_subreg (mode
, true0
,
9003 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9004 false0
= simplify_gen_subreg (mode
, false0
,
9005 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9006 if (true0
&& false0
)
9014 /* If X is a constant, this isn't special and will cause confusions
9015 if we treat it as such. Likewise if it is equivalent to a constant. */
9016 else if (CONSTANT_P (x
)
9017 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
9020 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9021 will be least confusing to the rest of the compiler. */
9022 else if (mode
== BImode
)
9024 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
9028 /* If X is known to be either 0 or -1, those are the true and
9029 false values when testing X. */
9030 else if (x
== constm1_rtx
|| x
== const0_rtx
9031 || (mode
!= VOIDmode
9032 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
9034 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
9038 /* Likewise for 0 or a single bit. */
9039 else if (HWI_COMPUTABLE_MODE_P (mode
)
9040 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
9042 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
9046 /* Otherwise fail; show no condition with true and false values the same. */
9047 *ptrue
= *pfalse
= x
;
9051 /* Return the value of expression X given the fact that condition COND
9052 is known to be true when applied to REG as its first operand and VAL
9053 as its second. X is known to not be shared and so can be modified in
9056 We only handle the simplest cases, and specifically those cases that
9057 arise with IF_THEN_ELSE expressions. */
9060 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
9062 enum rtx_code code
= GET_CODE (x
);
9066 if (side_effects_p (x
))
9069 /* If either operand of the condition is a floating point value,
9070 then we have to avoid collapsing an EQ comparison. */
9072 && rtx_equal_p (x
, reg
)
9073 && ! FLOAT_MODE_P (GET_MODE (x
))
9074 && ! FLOAT_MODE_P (GET_MODE (val
)))
9077 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
9080 /* If X is (abs REG) and we know something about REG's relationship
9081 with zero, we may be able to simplify this. */
9083 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
9086 case GE
: case GT
: case EQ
:
9089 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
9091 GET_MODE (XEXP (x
, 0)));
9096 /* The only other cases we handle are MIN, MAX, and comparisons if the
9097 operands are the same as REG and VAL. */
9099 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
9101 if (rtx_equal_p (XEXP (x
, 0), val
))
9103 std::swap (val
, reg
);
9104 cond
= swap_condition (cond
);
9107 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
9109 if (COMPARISON_P (x
))
9111 if (comparison_dominates_p (cond
, code
))
9112 return const_true_rtx
;
9114 code
= reversed_comparison_code (x
, NULL
);
9116 && comparison_dominates_p (cond
, code
))
9121 else if (code
== SMAX
|| code
== SMIN
9122 || code
== UMIN
|| code
== UMAX
)
9124 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
9126 /* Do not reverse the condition when it is NE or EQ.
9127 This is because we cannot conclude anything about
9128 the value of 'SMAX (x, y)' when x is not equal to y,
9129 but we can when x equals y. */
9130 if ((code
== SMAX
|| code
== UMAX
)
9131 && ! (cond
== EQ
|| cond
== NE
))
9132 cond
= reverse_condition (cond
);
9137 return unsignedp
? x
: XEXP (x
, 1);
9139 return unsignedp
? x
: XEXP (x
, 0);
9141 return unsignedp
? XEXP (x
, 1) : x
;
9143 return unsignedp
? XEXP (x
, 0) : x
;
9150 else if (code
== SUBREG
)
9152 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9153 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9155 if (SUBREG_REG (x
) != r
)
9157 /* We must simplify subreg here, before we lose track of the
9158 original inner_mode. */
9159 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9160 inner_mode
, SUBREG_BYTE (x
));
9164 SUBST (SUBREG_REG (x
), r
);
9169 /* We don't have to handle SIGN_EXTEND here, because even in the
9170 case of replacing something with a modeless CONST_INT, a
9171 CONST_INT is already (supposed to be) a valid sign extension for
9172 its narrower mode, which implies it's already properly
9173 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9174 story is different. */
9175 else if (code
== ZERO_EXTEND
)
9177 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9178 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9180 if (XEXP (x
, 0) != r
)
9182 /* We must simplify the zero_extend here, before we lose
9183 track of the original inner_mode. */
9184 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9189 SUBST (XEXP (x
, 0), r
);
9195 fmt
= GET_RTX_FORMAT (code
);
9196 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9199 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9200 else if (fmt
[i
] == 'E')
9201 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9202 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9209 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9210 assignment as a field assignment. */
9213 rtx_equal_for_field_assignment_p (rtx x
, rtx y
, bool widen_x
)
9215 if (widen_x
&& GET_MODE (x
) != GET_MODE (y
))
9217 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (y
)))
9219 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
9221 /* For big endian, adjust the memory offset. */
9222 if (BYTES_BIG_ENDIAN
)
9223 x
= adjust_address_nv (x
, GET_MODE (y
),
9224 -subreg_lowpart_offset (GET_MODE (x
),
9227 x
= adjust_address_nv (x
, GET_MODE (y
), 0);
9230 if (x
== y
|| rtx_equal_p (x
, y
))
9233 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9236 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9237 Note that all SUBREGs of MEM are paradoxical; otherwise they
9238 would have been rewritten. */
9239 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9240 && MEM_P (SUBREG_REG (y
))
9241 && rtx_equal_p (SUBREG_REG (y
),
9242 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9245 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9246 && MEM_P (SUBREG_REG (x
))
9247 && rtx_equal_p (SUBREG_REG (x
),
9248 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9251 /* We used to see if get_last_value of X and Y were the same but that's
9252 not correct. In one direction, we'll cause the assignment to have
9253 the wrong destination and in the case, we'll import a register into this
9254 insn that might have already have been dead. So fail if none of the
9255 above cases are true. */
9259 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9260 Return that assignment if so.
9262 We only handle the most common cases. */
9265 make_field_assignment (rtx x
)
9267 rtx dest
= SET_DEST (x
);
9268 rtx src
= SET_SRC (x
);
9273 unsigned HOST_WIDE_INT len
;
9277 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9278 a clear of a one-bit field. We will have changed it to
9279 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9282 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9283 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9284 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9285 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9287 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9290 return gen_rtx_SET (assign
, const0_rtx
);
9294 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9295 && subreg_lowpart_p (XEXP (src
, 0))
9296 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
9297 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
9298 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9299 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9300 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9301 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9303 assign
= make_extraction (VOIDmode
, dest
, 0,
9304 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9307 return gen_rtx_SET (assign
, const0_rtx
);
9311 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9313 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9314 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9315 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9317 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9320 return gen_rtx_SET (assign
, const1_rtx
);
9324 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9325 SRC is an AND with all bits of that field set, then we can discard
9327 if (GET_CODE (dest
) == ZERO_EXTRACT
9328 && CONST_INT_P (XEXP (dest
, 1))
9329 && GET_CODE (src
) == AND
9330 && CONST_INT_P (XEXP (src
, 1)))
9332 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9333 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9334 unsigned HOST_WIDE_INT ze_mask
;
9336 if (width
>= HOST_BITS_PER_WIDE_INT
)
9339 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9341 /* Complete overlap. We can remove the source AND. */
9342 if ((and_mask
& ze_mask
) == ze_mask
)
9343 return gen_rtx_SET (dest
, XEXP (src
, 0));
9345 /* Partial overlap. We can reduce the source AND. */
9346 if ((and_mask
& ze_mask
) != and_mask
)
9348 mode
= GET_MODE (src
);
9349 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9350 gen_int_mode (and_mask
& ze_mask
, mode
));
9351 return gen_rtx_SET (dest
, src
);
9355 /* The other case we handle is assignments into a constant-position
9356 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9357 a mask that has all one bits except for a group of zero bits and
9358 OTHER is known to have zeros where C1 has ones, this is such an
9359 assignment. Compute the position and length from C1. Shift OTHER
9360 to the appropriate position, force it to the required mode, and
9361 make the extraction. Check for the AND in both operands. */
9363 /* One or more SUBREGs might obscure the constant-position field
9364 assignment. The first one we are likely to encounter is an outer
9365 narrowing SUBREG, which we can just strip for the purposes of
9366 identifying the constant-field assignment. */
9367 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
))
9368 src
= SUBREG_REG (src
);
9370 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9373 rhs
= expand_compound_operation (XEXP (src
, 0));
9374 lhs
= expand_compound_operation (XEXP (src
, 1));
9376 if (GET_CODE (rhs
) == AND
9377 && CONST_INT_P (XEXP (rhs
, 1))
9378 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9379 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9380 /* The second SUBREG that might get in the way is a paradoxical
9381 SUBREG around the first operand of the AND. We want to
9382 pretend the operand is as wide as the destination here. We
9383 do this by adjusting the MEM to wider mode for the sole
9384 purpose of the call to rtx_equal_for_field_assignment_p. Also
9385 note this trick only works for MEMs. */
9386 else if (GET_CODE (rhs
) == AND
9387 && paradoxical_subreg_p (XEXP (rhs
, 0))
9388 && MEM_P (SUBREG_REG (XEXP (rhs
, 0)))
9389 && CONST_INT_P (XEXP (rhs
, 1))
9390 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs
, 0)),
9392 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9393 else if (GET_CODE (lhs
) == AND
9394 && CONST_INT_P (XEXP (lhs
, 1))
9395 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9396 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9397 /* The second SUBREG that might get in the way is a paradoxical
9398 SUBREG around the first operand of the AND. We want to
9399 pretend the operand is as wide as the destination here. We
9400 do this by adjusting the MEM to wider mode for the sole
9401 purpose of the call to rtx_equal_for_field_assignment_p. Also
9402 note this trick only works for MEMs. */
9403 else if (GET_CODE (lhs
) == AND
9404 && paradoxical_subreg_p (XEXP (lhs
, 0))
9405 && MEM_P (SUBREG_REG (XEXP (lhs
, 0)))
9406 && CONST_INT_P (XEXP (lhs
, 1))
9407 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs
, 0)),
9409 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9413 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9414 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9415 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9416 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9419 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9423 /* The mode to use for the source is the mode of the assignment, or of
9424 what is inside a possible STRICT_LOW_PART. */
9425 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9426 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9428 /* Shift OTHER right POS places and make it the source, restricting it
9429 to the proper length and mode. */
9431 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9435 src
= force_to_mode (src
, mode
,
9436 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9437 ? ~(unsigned HOST_WIDE_INT
) 0
9438 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9441 /* If SRC is masked by an AND that does not make a difference in
9442 the value being stored, strip it. */
9443 if (GET_CODE (assign
) == ZERO_EXTRACT
9444 && CONST_INT_P (XEXP (assign
, 1))
9445 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9446 && GET_CODE (src
) == AND
9447 && CONST_INT_P (XEXP (src
, 1))
9448 && UINTVAL (XEXP (src
, 1))
9449 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9450 src
= XEXP (src
, 0);
9452 return gen_rtx_SET (assign
, src
);
9455 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9459 apply_distributive_law (rtx x
)
9461 enum rtx_code code
= GET_CODE (x
);
9462 enum rtx_code inner_code
;
9463 rtx lhs
, rhs
, other
;
9466 /* Distributivity is not true for floating point as it can change the
9467 value. So we don't do it unless -funsafe-math-optimizations. */
9468 if (FLOAT_MODE_P (GET_MODE (x
))
9469 && ! flag_unsafe_math_optimizations
)
9472 /* The outer operation can only be one of the following: */
9473 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9474 && code
!= PLUS
&& code
!= MINUS
)
9480 /* If either operand is a primitive we can't do anything, so get out
9482 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9485 lhs
= expand_compound_operation (lhs
);
9486 rhs
= expand_compound_operation (rhs
);
9487 inner_code
= GET_CODE (lhs
);
9488 if (inner_code
!= GET_CODE (rhs
))
9491 /* See if the inner and outer operations distribute. */
9498 /* These all distribute except over PLUS. */
9499 if (code
== PLUS
|| code
== MINUS
)
9504 if (code
!= PLUS
&& code
!= MINUS
)
9509 /* This is also a multiply, so it distributes over everything. */
9512 /* This used to handle SUBREG, but this turned out to be counter-
9513 productive, since (subreg (op ...)) usually is not handled by
9514 insn patterns, and this "optimization" therefore transformed
9515 recognizable patterns into unrecognizable ones. Therefore the
9516 SUBREG case was removed from here.
9518 It is possible that distributing SUBREG over arithmetic operations
9519 leads to an intermediate result than can then be optimized further,
9520 e.g. by moving the outer SUBREG to the other side of a SET as done
9521 in simplify_set. This seems to have been the original intent of
9522 handling SUBREGs here.
9524 However, with current GCC this does not appear to actually happen,
9525 at least on major platforms. If some case is found where removing
9526 the SUBREG case here prevents follow-on optimizations, distributing
9527 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9533 /* Set LHS and RHS to the inner operands (A and B in the example
9534 above) and set OTHER to the common operand (C in the example).
9535 There is only one way to do this unless the inner operation is
9537 if (COMMUTATIVE_ARITH_P (lhs
)
9538 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9539 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9540 else if (COMMUTATIVE_ARITH_P (lhs
)
9541 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9542 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9543 else if (COMMUTATIVE_ARITH_P (lhs
)
9544 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9545 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9546 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9547 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9551 /* Form the new inner operation, seeing if it simplifies first. */
9552 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9554 /* There is one exception to the general way of distributing:
9555 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9556 if (code
== XOR
&& inner_code
== IOR
)
9559 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9562 /* We may be able to continuing distributing the result, so call
9563 ourselves recursively on the inner operation before forming the
9564 outer operation, which we return. */
9565 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9566 apply_distributive_law (tem
), other
);
9569 /* See if X is of the form (* (+ A B) C), and if so convert to
9570 (+ (* A C) (* B C)) and try to simplify.
9572 Most of the time, this results in no change. However, if some of
9573 the operands are the same or inverses of each other, simplifications
9576 For example, (and (ior A B) (not B)) can occur as the result of
9577 expanding a bit field assignment. When we apply the distributive
9578 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9579 which then simplifies to (and (A (not B))).
9581 Note that no checks happen on the validity of applying the inverse
9582 distributive law. This is pointless since we can do it in the
9583 few places where this routine is called.
9585 N is the index of the term that is decomposed (the arithmetic operation,
9586 i.e. (+ A B) in the first example above). !N is the index of the term that
9587 is distributed, i.e. of C in the first example above. */
9589 distribute_and_simplify_rtx (rtx x
, int n
)
9592 enum rtx_code outer_code
, inner_code
;
9593 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9595 /* Distributivity is not true for floating point as it can change the
9596 value. So we don't do it unless -funsafe-math-optimizations. */
9597 if (FLOAT_MODE_P (GET_MODE (x
))
9598 && ! flag_unsafe_math_optimizations
)
9601 decomposed
= XEXP (x
, n
);
9602 if (!ARITHMETIC_P (decomposed
))
9605 mode
= GET_MODE (x
);
9606 outer_code
= GET_CODE (x
);
9607 distributed
= XEXP (x
, !n
);
9609 inner_code
= GET_CODE (decomposed
);
9610 inner_op0
= XEXP (decomposed
, 0);
9611 inner_op1
= XEXP (decomposed
, 1);
9613 /* Special case (and (xor B C) (not A)), which is equivalent to
9614 (xor (ior A B) (ior A C)) */
9615 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9617 distributed
= XEXP (distributed
, 0);
9623 /* Distribute the second term. */
9624 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9625 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9629 /* Distribute the first term. */
9630 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9631 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9634 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9636 if (GET_CODE (tmp
) != outer_code
9637 && (set_src_cost (tmp
, optimize_this_for_speed_p
)
9638 < set_src_cost (x
, optimize_this_for_speed_p
)))
9644 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9645 in MODE. Return an equivalent form, if different from (and VAROP
9646 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9649 simplify_and_const_int_1 (machine_mode mode
, rtx varop
,
9650 unsigned HOST_WIDE_INT constop
)
9652 unsigned HOST_WIDE_INT nonzero
;
9653 unsigned HOST_WIDE_INT orig_constop
;
9658 orig_constop
= constop
;
9659 if (GET_CODE (varop
) == CLOBBER
)
9662 /* Simplify VAROP knowing that we will be only looking at some of the
9665 Note by passing in CONSTOP, we guarantee that the bits not set in
9666 CONSTOP are not significant and will never be examined. We must
9667 ensure that is the case by explicitly masking out those bits
9668 before returning. */
9669 varop
= force_to_mode (varop
, mode
, constop
, 0);
9671 /* If VAROP is a CLOBBER, we will fail so return it. */
9672 if (GET_CODE (varop
) == CLOBBER
)
9675 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9676 to VAROP and return the new constant. */
9677 if (CONST_INT_P (varop
))
9678 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9680 /* See what bits may be nonzero in VAROP. Unlike the general case of
9681 a call to nonzero_bits, here we don't care about bits outside
9684 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9686 /* Turn off all bits in the constant that are known to already be zero.
9687 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9688 which is tested below. */
9692 /* If we don't have any bits left, return zero. */
9696 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9697 a power of two, we can replace this with an ASHIFT. */
9698 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9699 && (i
= exact_log2 (constop
)) >= 0)
9700 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9702 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9703 or XOR, then try to apply the distributive law. This may eliminate
9704 operations if either branch can be simplified because of the AND.
9705 It may also make some cases more complex, but those cases probably
9706 won't match a pattern either with or without this. */
9708 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9712 apply_distributive_law
9713 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9714 simplify_and_const_int (NULL_RTX
,
9718 simplify_and_const_int (NULL_RTX
,
9723 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9724 the AND and see if one of the operands simplifies to zero. If so, we
9725 may eliminate it. */
9727 if (GET_CODE (varop
) == PLUS
9728 && exact_log2 (constop
+ 1) >= 0)
9732 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9733 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9734 if (o0
== const0_rtx
)
9736 if (o1
== const0_rtx
)
9740 /* Make a SUBREG if necessary. If we can't make it, fail. */
9741 varop
= gen_lowpart (mode
, varop
);
9742 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9745 /* If we are only masking insignificant bits, return VAROP. */
9746 if (constop
== nonzero
)
9749 if (varop
== orig_varop
&& constop
== orig_constop
)
9752 /* Otherwise, return an AND. */
9753 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9757 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9760 Return an equivalent form, if different from X. Otherwise, return X. If
9761 X is zero, we are to always construct the equivalent form. */
9764 simplify_and_const_int (rtx x
, machine_mode mode
, rtx varop
,
9765 unsigned HOST_WIDE_INT constop
)
9767 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9772 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9773 gen_int_mode (constop
, mode
));
9774 if (GET_MODE (x
) != mode
)
9775 x
= gen_lowpart (mode
, x
);
9779 /* Given a REG, X, compute which bits in X can be nonzero.
9780 We don't care about bits outside of those defined in MODE.
9782 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9783 a shift, AND, or zero_extract, we can do better. */
9786 reg_nonzero_bits_for_combine (const_rtx x
, machine_mode mode
,
9787 const_rtx known_x ATTRIBUTE_UNUSED
,
9788 machine_mode known_mode ATTRIBUTE_UNUSED
,
9789 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9790 unsigned HOST_WIDE_INT
*nonzero
)
9795 /* If X is a register whose nonzero bits value is current, use it.
9796 Otherwise, if X is a register whose value we can find, use that
9797 value. Otherwise, use the previously-computed global nonzero bits
9798 for this register. */
9800 rsp
= ®_stat
[REGNO (x
)];
9801 if (rsp
->last_set_value
!= 0
9802 && (rsp
->last_set_mode
== mode
9803 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9804 && GET_MODE_CLASS (mode
) == MODE_INT
))
9805 && ((rsp
->last_set_label
>= label_tick_ebb_start
9806 && rsp
->last_set_label
< label_tick
)
9807 || (rsp
->last_set_label
== label_tick
9808 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9809 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9810 && REGNO (x
) < reg_n_sets_max
9811 && REG_N_SETS (REGNO (x
)) == 1
9813 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9816 unsigned HOST_WIDE_INT mask
= rsp
->last_set_nonzero_bits
;
9818 if (GET_MODE_PRECISION (rsp
->last_set_mode
) < GET_MODE_PRECISION (mode
))
9819 /* We don't know anything about the upper bits. */
9820 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (rsp
->last_set_mode
);
9826 tem
= get_last_value (x
);
9830 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9831 tem
= sign_extend_short_imm (tem
, GET_MODE (x
),
9832 GET_MODE_PRECISION (mode
));
9836 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9838 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9840 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
9841 /* We don't know anything about the upper bits. */
9842 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9850 /* Return the number of bits at the high-order end of X that are known to
9851 be equal to the sign bit. X will be used in mode MODE; if MODE is
9852 VOIDmode, X will be used in its own mode. The returned value will always
9853 be between 1 and the number of bits in MODE. */
9856 reg_num_sign_bit_copies_for_combine (const_rtx x
, machine_mode mode
,
9857 const_rtx known_x ATTRIBUTE_UNUSED
,
9858 machine_mode known_mode
9860 unsigned int known_ret ATTRIBUTE_UNUSED
,
9861 unsigned int *result
)
9866 rsp
= ®_stat
[REGNO (x
)];
9867 if (rsp
->last_set_value
!= 0
9868 && rsp
->last_set_mode
== mode
9869 && ((rsp
->last_set_label
>= label_tick_ebb_start
9870 && rsp
->last_set_label
< label_tick
)
9871 || (rsp
->last_set_label
== label_tick
9872 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9873 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9874 && REGNO (x
) < reg_n_sets_max
9875 && REG_N_SETS (REGNO (x
)) == 1
9877 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9880 *result
= rsp
->last_set_sign_bit_copies
;
9884 tem
= get_last_value (x
);
9888 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9889 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
9890 *result
= rsp
->sign_bit_copies
;
9895 /* Return the number of "extended" bits there are in X, when interpreted
9896 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9897 unsigned quantities, this is the number of high-order zero bits.
9898 For signed quantities, this is the number of copies of the sign bit
9899 minus 1. In both case, this function returns the number of "spare"
9900 bits. For example, if two quantities for which this function returns
9901 at least 1 are added, the addition is known not to overflow.
9903 This function will always return 0 unless called during combine, which
9904 implies that it must be called from a define_split. */
9907 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
9909 if (nonzero_sign_valid
== 0)
9913 ? (HWI_COMPUTABLE_MODE_P (mode
)
9914 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
9915 - floor_log2 (nonzero_bits (x
, mode
)))
9917 : num_sign_bit_copies (x
, mode
) - 1);
9920 /* This function is called from `simplify_shift_const' to merge two
9921 outer operations. Specifically, we have already found that we need
9922 to perform operation *POP0 with constant *PCONST0 at the outermost
9923 position. We would now like to also perform OP1 with constant CONST1
9924 (with *POP0 being done last).
9926 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9927 the resulting operation. *PCOMP_P is set to 1 if we would need to
9928 complement the innermost operand, otherwise it is unchanged.
9930 MODE is the mode in which the operation will be done. No bits outside
9931 the width of this mode matter. It is assumed that the width of this mode
9932 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9934 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9935 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9936 result is simply *PCONST0.
9938 If the resulting operation cannot be expressed as one operation, we
9939 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9942 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
9944 enum rtx_code op0
= *pop0
;
9945 HOST_WIDE_INT const0
= *pconst0
;
9947 const0
&= GET_MODE_MASK (mode
);
9948 const1
&= GET_MODE_MASK (mode
);
9950 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9954 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9957 if (op1
== UNKNOWN
|| op0
== SET
)
9960 else if (op0
== UNKNOWN
)
9961 op0
= op1
, const0
= const1
;
9963 else if (op0
== op1
)
9987 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9988 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9991 /* If the two constants aren't the same, we can't do anything. The
9992 remaining six cases can all be done. */
9993 else if (const0
!= const1
)
10001 /* (a & b) | b == b */
10003 else /* op1 == XOR */
10004 /* (a ^ b) | b == a | b */
10010 /* (a & b) ^ b == (~a) & b */
10011 op0
= AND
, *pcomp_p
= 1;
10012 else /* op1 == IOR */
10013 /* (a | b) ^ b == a & ~b */
10014 op0
= AND
, const0
= ~const0
;
10019 /* (a | b) & b == b */
10021 else /* op1 == XOR */
10022 /* (a ^ b) & b) == (~a) & b */
10029 /* Check for NO-OP cases. */
10030 const0
&= GET_MODE_MASK (mode
);
10032 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
10034 else if (const0
== 0 && op0
== AND
)
10036 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
10042 /* ??? Slightly redundant with the above mask, but not entirely.
10043 Moving this above means we'd have to sign-extend the mode mask
10044 for the final test. */
10045 if (op0
!= UNKNOWN
&& op0
!= NEG
)
10046 *pconst0
= trunc_int_for_mode (const0
, mode
);
10051 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10052 the shift in. The original shift operation CODE is performed on OP in
10053 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10054 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10055 result of the shift is subject to operation OUTER_CODE with operand
10058 static machine_mode
10059 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
10060 machine_mode orig_mode
, machine_mode mode
,
10061 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
10063 if (orig_mode
== mode
)
10065 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
10067 /* In general we can't perform in wider mode for right shift and rotate. */
10071 /* We can still widen if the bits brought in from the left are identical
10072 to the sign bit of ORIG_MODE. */
10073 if (num_sign_bit_copies (op
, mode
)
10074 > (unsigned) (GET_MODE_PRECISION (mode
)
10075 - GET_MODE_PRECISION (orig_mode
)))
10080 /* Similarly here but with zero bits. */
10081 if (HWI_COMPUTABLE_MODE_P (mode
)
10082 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
10085 /* We can also widen if the bits brought in will be masked off. This
10086 operation is performed in ORIG_MODE. */
10087 if (outer_code
== AND
)
10089 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
10092 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
10101 gcc_unreachable ();
10108 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10109 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10110 if we cannot simplify it. Otherwise, return a simplified value.
10112 The shift is normally computed in the widest mode we find in VAROP, as
10113 long as it isn't a different number of words than RESULT_MODE. Exceptions
10114 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10117 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
10118 rtx varop
, int orig_count
)
10120 enum rtx_code orig_code
= code
;
10121 rtx orig_varop
= varop
;
10123 machine_mode mode
= result_mode
;
10124 machine_mode shift_mode
, tmode
;
10125 unsigned int mode_words
10126 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
10127 /* We form (outer_op (code varop count) (outer_const)). */
10128 enum rtx_code outer_op
= UNKNOWN
;
10129 HOST_WIDE_INT outer_const
= 0;
10130 int complement_p
= 0;
10133 /* Make sure and truncate the "natural" shift on the way in. We don't
10134 want to do this inside the loop as it makes it more difficult to
10136 if (SHIFT_COUNT_TRUNCATED
)
10137 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
10139 /* If we were given an invalid count, don't do anything except exactly
10140 what was requested. */
10142 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_PRECISION (mode
))
10145 count
= orig_count
;
10147 /* Unless one of the branches of the `if' in this loop does a `continue',
10148 we will `break' the loop after the `if'. */
10152 /* If we have an operand of (clobber (const_int 0)), fail. */
10153 if (GET_CODE (varop
) == CLOBBER
)
10156 /* Convert ROTATERT to ROTATE. */
10157 if (code
== ROTATERT
)
10159 unsigned int bitsize
= GET_MODE_PRECISION (result_mode
);
10161 if (VECTOR_MODE_P (result_mode
))
10162 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
10164 count
= bitsize
- count
;
10167 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
10168 mode
, outer_op
, outer_const
);
10170 /* Handle cases where the count is greater than the size of the mode
10171 minus 1. For ASHIFT, use the size minus one as the count (this can
10172 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10173 take the count modulo the size. For other shifts, the result is
10176 Since these shifts are being produced by the compiler by combining
10177 multiple operations, each of which are defined, we know what the
10178 result is supposed to be. */
10180 if (count
> (GET_MODE_PRECISION (shift_mode
) - 1))
10182 if (code
== ASHIFTRT
)
10183 count
= GET_MODE_PRECISION (shift_mode
) - 1;
10184 else if (code
== ROTATE
|| code
== ROTATERT
)
10185 count
%= GET_MODE_PRECISION (shift_mode
);
10188 /* We can't simply return zero because there may be an
10190 varop
= const0_rtx
;
10196 /* If we discovered we had to complement VAROP, leave. Making a NOT
10197 here would cause an infinite loop. */
10201 /* An arithmetic right shift of a quantity known to be -1 or 0
10203 if (code
== ASHIFTRT
10204 && (num_sign_bit_copies (varop
, shift_mode
)
10205 == GET_MODE_PRECISION (shift_mode
)))
10211 /* If we are doing an arithmetic right shift and discarding all but
10212 the sign bit copies, this is equivalent to doing a shift by the
10213 bitsize minus one. Convert it into that shift because it will often
10214 allow other simplifications. */
10216 if (code
== ASHIFTRT
10217 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
10218 >= GET_MODE_PRECISION (shift_mode
)))
10219 count
= GET_MODE_PRECISION (shift_mode
) - 1;
10221 /* We simplify the tests below and elsewhere by converting
10222 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10223 `make_compound_operation' will convert it to an ASHIFTRT for
10224 those machines (such as VAX) that don't have an LSHIFTRT. */
10225 if (code
== ASHIFTRT
10226 && val_signbit_known_clear_p (shift_mode
,
10227 nonzero_bits (varop
, shift_mode
)))
10230 if (((code
== LSHIFTRT
10231 && HWI_COMPUTABLE_MODE_P (shift_mode
)
10232 && !(nonzero_bits (varop
, shift_mode
) >> count
))
10234 && HWI_COMPUTABLE_MODE_P (shift_mode
)
10235 && !((nonzero_bits (varop
, shift_mode
) << count
)
10236 & GET_MODE_MASK (shift_mode
))))
10237 && !side_effects_p (varop
))
10238 varop
= const0_rtx
;
10240 switch (GET_CODE (varop
))
10246 new_rtx
= expand_compound_operation (varop
);
10247 if (new_rtx
!= varop
)
10255 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10256 minus the width of a smaller mode, we can do this with a
10257 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10258 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10259 && ! mode_dependent_address_p (XEXP (varop
, 0),
10260 MEM_ADDR_SPACE (varop
))
10261 && ! MEM_VOLATILE_P (varop
)
10262 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
10263 MODE_INT
, 1)) != BLKmode
)
10265 new_rtx
= adjust_address_nv (varop
, tmode
,
10266 BYTES_BIG_ENDIAN
? 0
10267 : count
/ BITS_PER_UNIT
);
10269 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10270 : ZERO_EXTEND
, mode
, new_rtx
);
10277 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10278 the same number of words as what we've seen so far. Then store
10279 the widest mode in MODE. */
10280 if (subreg_lowpart_p (varop
)
10281 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10282 > GET_MODE_SIZE (GET_MODE (varop
)))
10283 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10284 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
10286 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
10287 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
10289 varop
= SUBREG_REG (varop
);
10290 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
10291 mode
= GET_MODE (varop
);
10297 /* Some machines use MULT instead of ASHIFT because MULT
10298 is cheaper. But it is still better on those machines to
10299 merge two shifts into one. */
10300 if (CONST_INT_P (XEXP (varop
, 1))
10301 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10304 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10306 GEN_INT (exact_log2 (
10307 UINTVAL (XEXP (varop
, 1)))));
10313 /* Similar, for when divides are cheaper. */
10314 if (CONST_INT_P (XEXP (varop
, 1))
10315 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10318 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10320 GEN_INT (exact_log2 (
10321 UINTVAL (XEXP (varop
, 1)))));
10327 /* If we are extracting just the sign bit of an arithmetic
10328 right shift, that shift is not needed. However, the sign
10329 bit of a wider mode may be different from what would be
10330 interpreted as the sign bit in a narrower mode, so, if
10331 the result is narrower, don't discard the shift. */
10332 if (code
== LSHIFTRT
10333 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10334 && (GET_MODE_BITSIZE (result_mode
)
10335 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
10337 varop
= XEXP (varop
, 0);
10341 /* ... fall through ... */
10346 /* Here we have two nested shifts. The result is usually the
10347 AND of a new shift with a mask. We compute the result below. */
10348 if (CONST_INT_P (XEXP (varop
, 1))
10349 && INTVAL (XEXP (varop
, 1)) >= 0
10350 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10351 && HWI_COMPUTABLE_MODE_P (result_mode
)
10352 && HWI_COMPUTABLE_MODE_P (mode
)
10353 && !VECTOR_MODE_P (result_mode
))
10355 enum rtx_code first_code
= GET_CODE (varop
);
10356 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10357 unsigned HOST_WIDE_INT mask
;
10360 /* We have one common special case. We can't do any merging if
10361 the inner code is an ASHIFTRT of a smaller mode. However, if
10362 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10363 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10364 we can convert it to
10365 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10366 This simplifies certain SIGN_EXTEND operations. */
10367 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10368 && count
== (GET_MODE_PRECISION (result_mode
)
10369 - GET_MODE_PRECISION (GET_MODE (varop
))))
10371 /* C3 has the low-order C1 bits zero. */
10373 mask
= GET_MODE_MASK (mode
)
10374 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
10376 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10377 XEXP (varop
, 0), mask
);
10378 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10380 count
= first_count
;
10385 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10386 than C1 high-order bits equal to the sign bit, we can convert
10387 this to either an ASHIFT or an ASHIFTRT depending on the
10390 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10392 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10393 && GET_MODE (varop
) == shift_mode
10394 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10397 varop
= XEXP (varop
, 0);
10398 count
-= first_count
;
10408 /* There are some cases we can't do. If CODE is ASHIFTRT,
10409 we can only do this if FIRST_CODE is also ASHIFTRT.
10411 We can't do the case when CODE is ROTATE and FIRST_CODE is
10414 If the mode of this shift is not the mode of the outer shift,
10415 we can't do this if either shift is a right shift or ROTATE.
10417 Finally, we can't do any of these if the mode is too wide
10418 unless the codes are the same.
10420 Handle the case where the shift codes are the same
10423 if (code
== first_code
)
10425 if (GET_MODE (varop
) != result_mode
10426 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10427 || code
== ROTATE
))
10430 count
+= first_count
;
10431 varop
= XEXP (varop
, 0);
10435 if (code
== ASHIFTRT
10436 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10437 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10438 || (GET_MODE (varop
) != result_mode
10439 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10440 || first_code
== ROTATE
10441 || code
== ROTATE
)))
10444 /* To compute the mask to apply after the shift, shift the
10445 nonzero bits of the inner shift the same way the
10446 outer shift will. */
10448 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10452 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10455 /* Give up if we can't compute an outer operation to use. */
10457 || !CONST_INT_P (mask_rtx
)
10458 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10460 result_mode
, &complement_p
))
10463 /* If the shifts are in the same direction, we add the
10464 counts. Otherwise, we subtract them. */
10465 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10466 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10467 count
+= first_count
;
10469 count
-= first_count
;
10471 /* If COUNT is positive, the new shift is usually CODE,
10472 except for the two exceptions below, in which case it is
10473 FIRST_CODE. If the count is negative, FIRST_CODE should
10476 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10477 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10479 else if (count
< 0)
10480 code
= first_code
, count
= -count
;
10482 varop
= XEXP (varop
, 0);
10486 /* If we have (A << B << C) for any shift, we can convert this to
10487 (A << C << B). This wins if A is a constant. Only try this if
10488 B is not a constant. */
10490 else if (GET_CODE (varop
) == code
10491 && CONST_INT_P (XEXP (varop
, 0))
10492 && !CONST_INT_P (XEXP (varop
, 1)))
10494 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10497 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10504 if (VECTOR_MODE_P (mode
))
10507 /* Make this fit the case below. */
10508 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10514 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10515 with C the size of VAROP - 1 and the shift is logical if
10516 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10517 we have an (le X 0) operation. If we have an arithmetic shift
10518 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10519 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10521 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10522 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10523 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10524 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10525 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10526 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10529 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10532 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10533 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10538 /* If we have (shift (logical)), move the logical to the outside
10539 to allow it to possibly combine with another logical and the
10540 shift to combine with another shift. This also canonicalizes to
10541 what a ZERO_EXTRACT looks like. Also, some machines have
10542 (and (shift)) insns. */
10544 if (CONST_INT_P (XEXP (varop
, 1))
10545 /* We can't do this if we have (ashiftrt (xor)) and the
10546 constant has its sign bit set in shift_mode with shift_mode
10547 wider than result_mode. */
10548 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10549 && result_mode
!= shift_mode
10550 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10552 && (new_rtx
= simplify_const_binary_operation
10553 (code
, result_mode
,
10554 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10555 GEN_INT (count
))) != 0
10556 && CONST_INT_P (new_rtx
)
10557 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10558 INTVAL (new_rtx
), result_mode
, &complement_p
))
10560 varop
= XEXP (varop
, 0);
10564 /* If we can't do that, try to simplify the shift in each arm of the
10565 logical expression, make a new logical expression, and apply
10566 the inverse distributive law. This also can't be done for
10567 (ashiftrt (xor)) where we've widened the shift and the constant
10568 changes the sign bit. */
10569 if (CONST_INT_P (XEXP (varop
, 1))
10570 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10571 && result_mode
!= shift_mode
10572 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10575 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10576 XEXP (varop
, 0), count
);
10577 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10578 XEXP (varop
, 1), count
);
10580 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10582 varop
= apply_distributive_law (varop
);
10590 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10591 says that the sign bit can be tested, FOO has mode MODE, C is
10592 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10593 that may be nonzero. */
10594 if (code
== LSHIFTRT
10595 && XEXP (varop
, 1) == const0_rtx
10596 && GET_MODE (XEXP (varop
, 0)) == result_mode
10597 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10598 && HWI_COMPUTABLE_MODE_P (result_mode
)
10599 && STORE_FLAG_VALUE
== -1
10600 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10601 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10604 varop
= XEXP (varop
, 0);
10611 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10612 than the number of bits in the mode is equivalent to A. */
10613 if (code
== LSHIFTRT
10614 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10615 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10617 varop
= XEXP (varop
, 0);
10622 /* NEG commutes with ASHIFT since it is multiplication. Move the
10623 NEG outside to allow shifts to combine. */
10625 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10628 varop
= XEXP (varop
, 0);
10634 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10635 is one less than the number of bits in the mode is
10636 equivalent to (xor A 1). */
10637 if (code
== LSHIFTRT
10638 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10639 && XEXP (varop
, 1) == constm1_rtx
10640 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10641 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10645 varop
= XEXP (varop
, 0);
10649 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10650 that might be nonzero in BAR are those being shifted out and those
10651 bits are known zero in FOO, we can replace the PLUS with FOO.
10652 Similarly in the other operand order. This code occurs when
10653 we are computing the size of a variable-size array. */
10655 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10656 && count
< HOST_BITS_PER_WIDE_INT
10657 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10658 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10659 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10661 varop
= XEXP (varop
, 0);
10664 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10665 && count
< HOST_BITS_PER_WIDE_INT
10666 && HWI_COMPUTABLE_MODE_P (result_mode
)
10667 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10669 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10670 & nonzero_bits (XEXP (varop
, 1),
10673 varop
= XEXP (varop
, 1);
10677 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10679 && CONST_INT_P (XEXP (varop
, 1))
10680 && (new_rtx
= simplify_const_binary_operation
10681 (ASHIFT
, result_mode
,
10682 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10683 GEN_INT (count
))) != 0
10684 && CONST_INT_P (new_rtx
)
10685 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10686 INTVAL (new_rtx
), result_mode
, &complement_p
))
10688 varop
= XEXP (varop
, 0);
10692 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10693 signbit', and attempt to change the PLUS to an XOR and move it to
10694 the outer operation as is done above in the AND/IOR/XOR case
10695 leg for shift(logical). See details in logical handling above
10696 for reasoning in doing so. */
10697 if (code
== LSHIFTRT
10698 && CONST_INT_P (XEXP (varop
, 1))
10699 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10700 && (new_rtx
= simplify_const_binary_operation
10701 (code
, result_mode
,
10702 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10703 GEN_INT (count
))) != 0
10704 && CONST_INT_P (new_rtx
)
10705 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10706 INTVAL (new_rtx
), result_mode
, &complement_p
))
10708 varop
= XEXP (varop
, 0);
10715 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10716 with C the size of VAROP - 1 and the shift is logical if
10717 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10718 we have a (gt X 0) operation. If the shift is arithmetic with
10719 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10720 we have a (neg (gt X 0)) operation. */
10722 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10723 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10724 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10725 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10726 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10727 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10728 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10731 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10734 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10735 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10742 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10743 if the truncate does not affect the value. */
10744 if (code
== LSHIFTRT
10745 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10746 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10747 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10748 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop
, 0)))
10749 - GET_MODE_PRECISION (GET_MODE (varop
)))))
10751 rtx varop_inner
= XEXP (varop
, 0);
10754 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10755 XEXP (varop_inner
, 0),
10757 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10758 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10771 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10772 outer_op
, outer_const
);
10774 /* We have now finished analyzing the shift. The result should be
10775 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10776 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10777 to the result of the shift. OUTER_CONST is the relevant constant,
10778 but we must turn off all bits turned off in the shift. */
10780 if (outer_op
== UNKNOWN
10781 && orig_code
== code
&& orig_count
== count
10782 && varop
== orig_varop
10783 && shift_mode
== GET_MODE (varop
))
10786 /* Make a SUBREG if necessary. If we can't make it, fail. */
10787 varop
= gen_lowpart (shift_mode
, varop
);
10788 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10791 /* If we have an outer operation and we just made a shift, it is
10792 possible that we could have simplified the shift were it not
10793 for the outer operation. So try to do the simplification
10796 if (outer_op
!= UNKNOWN
)
10797 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10802 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10804 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10805 turn off all the bits that the shift would have turned off. */
10806 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10807 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10808 GET_MODE_MASK (result_mode
) >> orig_count
);
10810 /* Do the remainder of the processing in RESULT_MODE. */
10811 x
= gen_lowpart_or_truncate (result_mode
, x
);
10813 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10816 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10818 if (outer_op
!= UNKNOWN
)
10820 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10821 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10822 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10824 if (outer_op
== AND
)
10825 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10826 else if (outer_op
== SET
)
10828 /* This means that we have determined that the result is
10829 equivalent to a constant. This should be rare. */
10830 if (!side_effects_p (x
))
10831 x
= GEN_INT (outer_const
);
10833 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10834 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10836 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10837 GEN_INT (outer_const
));
10843 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10844 The result of the shift is RESULT_MODE. If we cannot simplify it,
10845 return X or, if it is NULL, synthesize the expression with
10846 simplify_gen_binary. Otherwise, return a simplified value.
10848 The shift is normally computed in the widest mode we find in VAROP, as
10849 long as it isn't a different number of words than RESULT_MODE. Exceptions
10850 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10853 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
10854 rtx varop
, int count
)
10856 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10861 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10862 if (GET_MODE (x
) != result_mode
)
10863 x
= gen_lowpart (result_mode
, x
);
10868 /* A subroutine of recog_for_combine. See there for arguments and
10872 recog_for_combine_1 (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
10874 rtx pat
= *pnewpat
;
10875 rtx pat_without_clobbers
;
10876 int insn_code_number
;
10877 int num_clobbers_to_add
= 0;
10879 rtx notes
= NULL_RTX
;
10880 rtx old_notes
, old_pat
;
10883 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10884 we use to indicate that something didn't match. If we find such a
10885 thing, force rejection. */
10886 if (GET_CODE (pat
) == PARALLEL
)
10887 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10888 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10889 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10892 old_pat
= PATTERN (insn
);
10893 old_notes
= REG_NOTES (insn
);
10894 PATTERN (insn
) = pat
;
10895 REG_NOTES (insn
) = NULL_RTX
;
10897 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10898 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10900 if (insn_code_number
< 0)
10901 fputs ("Failed to match this instruction:\n", dump_file
);
10903 fputs ("Successfully matched this instruction:\n", dump_file
);
10904 print_rtl_single (dump_file
, pat
);
10907 /* If it isn't, there is the possibility that we previously had an insn
10908 that clobbered some register as a side effect, but the combined
10909 insn doesn't need to do that. So try once more without the clobbers
10910 unless this represents an ASM insn. */
10912 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10913 && GET_CODE (pat
) == PARALLEL
)
10917 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10918 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10921 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10925 SUBST_INT (XVECLEN (pat
, 0), pos
);
10928 pat
= XVECEXP (pat
, 0, 0);
10930 PATTERN (insn
) = pat
;
10931 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10932 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10934 if (insn_code_number
< 0)
10935 fputs ("Failed to match this instruction:\n", dump_file
);
10937 fputs ("Successfully matched this instruction:\n", dump_file
);
10938 print_rtl_single (dump_file
, pat
);
10942 pat_without_clobbers
= pat
;
10944 PATTERN (insn
) = old_pat
;
10945 REG_NOTES (insn
) = old_notes
;
10947 /* Recognize all noop sets, these will be killed by followup pass. */
10948 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10949 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10951 /* If we had any clobbers to add, make a new pattern than contains
10952 them. Then check to make sure that all of them are dead. */
10953 if (num_clobbers_to_add
)
10955 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10956 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10957 ? (XVECLEN (pat
, 0)
10958 + num_clobbers_to_add
)
10959 : num_clobbers_to_add
+ 1));
10961 if (GET_CODE (pat
) == PARALLEL
)
10962 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10963 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10965 XVECEXP (newpat
, 0, 0) = pat
;
10967 add_clobbers (newpat
, insn_code_number
);
10969 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10970 i
< XVECLEN (newpat
, 0); i
++)
10972 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10973 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10975 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10977 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10978 notes
= alloc_reg_note (REG_UNUSED
,
10979 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10985 if (insn_code_number
>= 0
10986 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
10988 old_pat
= PATTERN (insn
);
10989 old_notes
= REG_NOTES (insn
);
10990 old_icode
= INSN_CODE (insn
);
10991 PATTERN (insn
) = pat
;
10992 REG_NOTES (insn
) = notes
;
10994 /* Allow targets to reject combined insn. */
10995 if (!targetm
.legitimate_combined_insn (insn
))
10997 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10998 fputs ("Instruction not appropriate for target.",
11001 /* Callers expect recog_for_combine to strip
11002 clobbers from the pattern on failure. */
11003 pat
= pat_without_clobbers
;
11006 insn_code_number
= -1;
11009 PATTERN (insn
) = old_pat
;
11010 REG_NOTES (insn
) = old_notes
;
11011 INSN_CODE (insn
) = old_icode
;
11017 return insn_code_number
;
11020 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11021 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11022 Return whether anything was so changed. */
11025 change_zero_ext (rtx
*src
)
11027 bool changed
= false;
11029 subrtx_ptr_iterator::array_type array
;
11030 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11033 machine_mode mode
= GET_MODE (x
);
11036 if (GET_CODE (x
) == ZERO_EXTRACT
11037 && CONST_INT_P (XEXP (x
, 1))
11038 && CONST_INT_P (XEXP (x
, 2))
11039 && GET_MODE (XEXP (x
, 0)) == mode
)
11041 size
= INTVAL (XEXP (x
, 1));
11043 int start
= INTVAL (XEXP (x
, 2));
11044 if (BITS_BIG_ENDIAN
)
11045 start
= GET_MODE_PRECISION (mode
) - size
- start
;
11047 x
= gen_rtx_LSHIFTRT (mode
, XEXP (x
, 0), GEN_INT (start
));
11049 else if (GET_CODE (x
) == ZERO_EXTEND
11050 && GET_CODE (XEXP (x
, 0)) == SUBREG
11051 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == mode
11052 && subreg_lowpart_p (XEXP (x
, 0)))
11054 size
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
11055 x
= SUBREG_REG (XEXP (x
, 0));
11060 unsigned HOST_WIDE_INT mask
= 1;
11064 x
= gen_rtx_AND (mode
, x
, GEN_INT (mask
));
11073 /* Like recog, but we receive the address of a pointer to a new pattern.
11074 We try to match the rtx that the pointer points to.
11075 If that fails, we may try to modify or replace the pattern,
11076 storing the replacement into the same pointer object.
11078 Modifications include deletion or addition of CLOBBERs. If the
11079 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11080 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11081 (and undo if that fails).
11083 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11084 the CLOBBERs are placed.
11086 The value is the final insn code from the pattern ultimately matched,
11090 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11092 rtx pat
= PATTERN (insn
);
11093 int insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11094 if (insn_code_number
>= 0 || check_asm_operands (pat
))
11095 return insn_code_number
;
11097 void *marker
= get_undo_marker ();
11098 bool changed
= false;
11100 if (GET_CODE (pat
) == SET
)
11101 changed
= change_zero_ext (&SET_SRC (pat
));
11102 else if (GET_CODE (pat
) == PARALLEL
)
11105 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11107 rtx set
= XVECEXP (pat
, 0, i
);
11108 if (GET_CODE (set
) == SET
)
11109 changed
|= change_zero_ext (&SET_SRC (set
));
11115 insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11117 if (insn_code_number
< 0)
11118 undo_to_marker (marker
);
11121 return insn_code_number
;
11124 /* Like gen_lowpart_general but for use by combine. In combine it
11125 is not possible to create any new pseudoregs. However, it is
11126 safe to create invalid memory addresses, because combine will
11127 try to recognize them and all they will do is make the combine
11130 If for some reason this cannot do its job, an rtx
11131 (clobber (const_int 0)) is returned.
11132 An insn containing that will not be recognized. */
11135 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
11137 machine_mode imode
= GET_MODE (x
);
11138 unsigned int osize
= GET_MODE_SIZE (omode
);
11139 unsigned int isize
= GET_MODE_SIZE (imode
);
11142 if (omode
== imode
)
11145 /* We can only support MODE being wider than a word if X is a
11146 constant integer or has a mode the same size. */
11147 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
11148 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
11151 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11152 won't know what to do. So we will strip off the SUBREG here and
11153 process normally. */
11154 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
11156 x
= SUBREG_REG (x
);
11158 /* For use in case we fall down into the address adjustments
11159 further below, we need to adjust the known mode and size of
11160 x; imode and isize, since we just adjusted x. */
11161 imode
= GET_MODE (x
);
11163 if (imode
== omode
)
11166 isize
= GET_MODE_SIZE (imode
);
11169 result
= gen_lowpart_common (omode
, x
);
11178 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11180 if (MEM_VOLATILE_P (x
)
11181 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
11184 /* If we want to refer to something bigger than the original memref,
11185 generate a paradoxical subreg instead. That will force a reload
11186 of the original memref X. */
11188 return gen_rtx_SUBREG (omode
, x
, 0);
11190 if (WORDS_BIG_ENDIAN
)
11191 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
11193 /* Adjust the address so that the address-after-the-data is
11195 if (BYTES_BIG_ENDIAN
)
11196 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
11198 return adjust_address_nv (x
, omode
, offset
);
11201 /* If X is a comparison operator, rewrite it in a new mode. This
11202 probably won't match, but may allow further simplifications. */
11203 else if (COMPARISON_P (x
))
11204 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
11206 /* If we couldn't simplify X any other way, just enclose it in a
11207 SUBREG. Normally, this SUBREG won't match, but some patterns may
11208 include an explicit SUBREG or we may simplify it further in combine. */
11214 offset
= subreg_lowpart_offset (omode
, imode
);
11215 if (imode
== VOIDmode
)
11217 imode
= int_mode_for_mode (omode
);
11218 x
= gen_lowpart_common (imode
, x
);
11222 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
11228 return gen_rtx_CLOBBER (omode
, const0_rtx
);
11231 /* Try to simplify a comparison between OP0 and a constant OP1,
11232 where CODE is the comparison code that will be tested, into a
11233 (CODE OP0 const0_rtx) form.
11235 The result is a possibly different comparison code to use.
11236 *POP1 may be updated. */
11238 static enum rtx_code
11239 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
11240 rtx op0
, rtx
*pop1
)
11242 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11243 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
11245 /* Get the constant we are comparing against and turn off all bits
11246 not on in our mode. */
11247 if (mode
!= VOIDmode
)
11248 const_op
= trunc_int_for_mode (const_op
, mode
);
11250 /* If we are comparing against a constant power of two and the value
11251 being compared can only have that single bit nonzero (e.g., it was
11252 `and'ed with that bit), we can replace this with a comparison
11255 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
11256 || code
== LT
|| code
== LTU
)
11257 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11258 && exact_log2 (const_op
& GET_MODE_MASK (mode
)) >= 0
11259 && (nonzero_bits (op0
, mode
)
11260 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
11262 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11266 /* Similarly, if we are comparing a value known to be either -1 or
11267 0 with -1, change it to the opposite comparison against zero. */
11269 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11270 || code
== GEU
|| code
== LTU
)
11271 && num_sign_bit_copies (op0
, mode
) == mode_width
)
11273 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11277 /* Do some canonicalizations based on the comparison code. We prefer
11278 comparisons against zero and then prefer equality comparisons.
11279 If we can reduce the size of a constant, we will do that too. */
11283 /* < C is equivalent to <= (C - 1) */
11288 /* ... fall through to LE case below. */
11294 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11301 /* If we are doing a <= 0 comparison on a value known to have
11302 a zero sign bit, we can replace this with == 0. */
11303 else if (const_op
== 0
11304 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11305 && (nonzero_bits (op0
, mode
)
11306 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11312 /* >= C is equivalent to > (C - 1). */
11317 /* ... fall through to GT below. */
11323 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11330 /* If we are doing a > 0 comparison on a value known to have
11331 a zero sign bit, we can replace this with != 0. */
11332 else if (const_op
== 0
11333 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11334 && (nonzero_bits (op0
, mode
)
11335 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11341 /* < C is equivalent to <= (C - 1). */
11346 /* ... fall through ... */
11348 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11349 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11350 && (unsigned HOST_WIDE_INT
) const_op
11351 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11361 /* unsigned <= 0 is equivalent to == 0 */
11364 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11365 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11366 && (unsigned HOST_WIDE_INT
) const_op
11367 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11375 /* >= C is equivalent to > (C - 1). */
11380 /* ... fall through ... */
11383 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11384 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11385 && (unsigned HOST_WIDE_INT
) const_op
11386 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11396 /* unsigned > 0 is equivalent to != 0 */
11399 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11400 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11401 && (unsigned HOST_WIDE_INT
) const_op
11402 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11413 *pop1
= GEN_INT (const_op
);
11417 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11418 comparison code that will be tested.
11420 The result is a possibly different comparison code to use. *POP0 and
11421 *POP1 may be updated.
11423 It is possible that we might detect that a comparison is either always
11424 true or always false. However, we do not perform general constant
11425 folding in combine, so this knowledge isn't useful. Such tautologies
11426 should have been detected earlier. Hence we ignore all such cases. */
11428 static enum rtx_code
11429 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11435 machine_mode mode
, tmode
;
11437 /* Try a few ways of applying the same transformation to both operands. */
11440 #ifndef WORD_REGISTER_OPERATIONS
11441 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11442 so check specially. */
11443 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11444 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11445 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11446 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11447 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11448 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11449 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11450 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11451 && CONST_INT_P (XEXP (op0
, 1))
11452 && XEXP (op0
, 1) == XEXP (op1
, 1)
11453 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11454 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11455 && (INTVAL (XEXP (op0
, 1))
11456 == (GET_MODE_PRECISION (GET_MODE (op0
))
11457 - (GET_MODE_PRECISION
11458 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11460 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11461 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11465 /* If both operands are the same constant shift, see if we can ignore the
11466 shift. We can if the shift is a rotate or if the bits shifted out of
11467 this shift are known to be zero for both inputs and if the type of
11468 comparison is compatible with the shift. */
11469 if (GET_CODE (op0
) == GET_CODE (op1
)
11470 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11471 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11472 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11473 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11474 || (GET_CODE (op0
) == ASHIFTRT
11475 && (code
!= GTU
&& code
!= LTU
11476 && code
!= GEU
&& code
!= LEU
)))
11477 && CONST_INT_P (XEXP (op0
, 1))
11478 && INTVAL (XEXP (op0
, 1)) >= 0
11479 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11480 && XEXP (op0
, 1) == XEXP (op1
, 1))
11482 machine_mode mode
= GET_MODE (op0
);
11483 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11484 int shift_count
= INTVAL (XEXP (op0
, 1));
11486 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11487 mask
&= (mask
>> shift_count
) << shift_count
;
11488 else if (GET_CODE (op0
) == ASHIFT
)
11489 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11491 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11492 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11493 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11498 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11499 SUBREGs are of the same mode, and, in both cases, the AND would
11500 be redundant if the comparison was done in the narrower mode,
11501 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11502 and the operand's possibly nonzero bits are 0xffffff01; in that case
11503 if we only care about QImode, we don't need the AND). This case
11504 occurs if the output mode of an scc insn is not SImode and
11505 STORE_FLAG_VALUE == 1 (e.g., the 386).
11507 Similarly, check for a case where the AND's are ZERO_EXTEND
11508 operations from some narrower mode even though a SUBREG is not
11511 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11512 && CONST_INT_P (XEXP (op0
, 1))
11513 && CONST_INT_P (XEXP (op1
, 1)))
11515 rtx inner_op0
= XEXP (op0
, 0);
11516 rtx inner_op1
= XEXP (op1
, 0);
11517 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11518 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11521 if (paradoxical_subreg_p (inner_op0
)
11522 && GET_CODE (inner_op1
) == SUBREG
11523 && (GET_MODE (SUBREG_REG (inner_op0
))
11524 == GET_MODE (SUBREG_REG (inner_op1
)))
11525 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11526 <= HOST_BITS_PER_WIDE_INT
)
11527 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11528 GET_MODE (SUBREG_REG (inner_op0
)))))
11529 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11530 GET_MODE (SUBREG_REG (inner_op1
))))))
11532 op0
= SUBREG_REG (inner_op0
);
11533 op1
= SUBREG_REG (inner_op1
);
11535 /* The resulting comparison is always unsigned since we masked
11536 off the original sign bit. */
11537 code
= unsigned_condition (code
);
11543 for (tmode
= GET_CLASS_NARROWEST_MODE
11544 (GET_MODE_CLASS (GET_MODE (op0
)));
11545 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11546 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11548 op0
= gen_lowpart (tmode
, inner_op0
);
11549 op1
= gen_lowpart (tmode
, inner_op1
);
11550 code
= unsigned_condition (code
);
11559 /* If both operands are NOT, we can strip off the outer operation
11560 and adjust the comparison code for swapped operands; similarly for
11561 NEG, except that this must be an equality comparison. */
11562 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11563 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11564 && (code
== EQ
|| code
== NE
)))
11565 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11571 /* If the first operand is a constant, swap the operands and adjust the
11572 comparison code appropriately, but don't do this if the second operand
11573 is already a constant integer. */
11574 if (swap_commutative_operands_p (op0
, op1
))
11576 std::swap (op0
, op1
);
11577 code
= swap_condition (code
);
11580 /* We now enter a loop during which we will try to simplify the comparison.
11581 For the most part, we only are concerned with comparisons with zero,
11582 but some things may really be comparisons with zero but not start
11583 out looking that way. */
11585 while (CONST_INT_P (op1
))
11587 machine_mode mode
= GET_MODE (op0
);
11588 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11589 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11590 int equality_comparison_p
;
11591 int sign_bit_comparison_p
;
11592 int unsigned_comparison_p
;
11593 HOST_WIDE_INT const_op
;
11595 /* We only want to handle integral modes. This catches VOIDmode,
11596 CCmode, and the floating-point modes. An exception is that we
11597 can handle VOIDmode if OP0 is a COMPARE or a comparison
11600 if (GET_MODE_CLASS (mode
) != MODE_INT
11601 && ! (mode
== VOIDmode
11602 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11605 /* Try to simplify the compare to constant, possibly changing the
11606 comparison op, and/or changing op1 to zero. */
11607 code
= simplify_compare_const (code
, mode
, op0
, &op1
);
11608 const_op
= INTVAL (op1
);
11610 /* Compute some predicates to simplify code below. */
11612 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11613 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11614 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11617 /* If this is a sign bit comparison and we can do arithmetic in
11618 MODE, say that we will only be needing the sign bit of OP0. */
11619 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11620 op0
= force_to_mode (op0
, mode
,
11621 (unsigned HOST_WIDE_INT
) 1
11622 << (GET_MODE_PRECISION (mode
) - 1),
11625 /* Now try cases based on the opcode of OP0. If none of the cases
11626 does a "continue", we exit this loop immediately after the
11629 switch (GET_CODE (op0
))
11632 /* If we are extracting a single bit from a variable position in
11633 a constant that has only a single bit set and are comparing it
11634 with zero, we can convert this into an equality comparison
11635 between the position and the location of the single bit. */
11636 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11637 have already reduced the shift count modulo the word size. */
11638 if (!SHIFT_COUNT_TRUNCATED
11639 && CONST_INT_P (XEXP (op0
, 0))
11640 && XEXP (op0
, 1) == const1_rtx
11641 && equality_comparison_p
&& const_op
== 0
11642 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11644 if (BITS_BIG_ENDIAN
)
11645 i
= BITS_PER_WORD
- 1 - i
;
11647 op0
= XEXP (op0
, 2);
11651 /* Result is nonzero iff shift count is equal to I. */
11652 code
= reverse_condition (code
);
11656 /* ... fall through ... */
11659 tem
= expand_compound_operation (op0
);
11668 /* If testing for equality, we can take the NOT of the constant. */
11669 if (equality_comparison_p
11670 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11672 op0
= XEXP (op0
, 0);
11677 /* If just looking at the sign bit, reverse the sense of the
11679 if (sign_bit_comparison_p
)
11681 op0
= XEXP (op0
, 0);
11682 code
= (code
== GE
? LT
: GE
);
11688 /* If testing for equality, we can take the NEG of the constant. */
11689 if (equality_comparison_p
11690 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11692 op0
= XEXP (op0
, 0);
11697 /* The remaining cases only apply to comparisons with zero. */
11701 /* When X is ABS or is known positive,
11702 (neg X) is < 0 if and only if X != 0. */
11704 if (sign_bit_comparison_p
11705 && (GET_CODE (XEXP (op0
, 0)) == ABS
11706 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11707 && (nonzero_bits (XEXP (op0
, 0), mode
)
11708 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11711 op0
= XEXP (op0
, 0);
11712 code
= (code
== LT
? NE
: EQ
);
11716 /* If we have NEG of something whose two high-order bits are the
11717 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11718 if (num_sign_bit_copies (op0
, mode
) >= 2)
11720 op0
= XEXP (op0
, 0);
11721 code
= swap_condition (code
);
11727 /* If we are testing equality and our count is a constant, we
11728 can perform the inverse operation on our RHS. */
11729 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11730 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11731 op1
, XEXP (op0
, 1))) != 0)
11733 op0
= XEXP (op0
, 0);
11738 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11739 a particular bit. Convert it to an AND of a constant of that
11740 bit. This will be converted into a ZERO_EXTRACT. */
11741 if (const_op
== 0 && sign_bit_comparison_p
11742 && CONST_INT_P (XEXP (op0
, 1))
11743 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11745 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11746 ((unsigned HOST_WIDE_INT
) 1
11748 - INTVAL (XEXP (op0
, 1)))));
11749 code
= (code
== LT
? NE
: EQ
);
11753 /* Fall through. */
11756 /* ABS is ignorable inside an equality comparison with zero. */
11757 if (const_op
== 0 && equality_comparison_p
)
11759 op0
= XEXP (op0
, 0);
11765 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11766 (compare FOO CONST) if CONST fits in FOO's mode and we
11767 are either testing inequality or have an unsigned
11768 comparison with ZERO_EXTEND or a signed comparison with
11769 SIGN_EXTEND. But don't do it if we don't have a compare
11770 insn of the given mode, since we'd have to revert it
11771 later on, and then we wouldn't know whether to sign- or
11773 mode
= GET_MODE (XEXP (op0
, 0));
11774 if (GET_MODE_CLASS (mode
) == MODE_INT
11775 && ! unsigned_comparison_p
11776 && HWI_COMPUTABLE_MODE_P (mode
)
11777 && trunc_int_for_mode (const_op
, mode
) == const_op
11778 && have_insn_for (COMPARE
, mode
))
11780 op0
= XEXP (op0
, 0);
11786 /* Check for the case where we are comparing A - C1 with C2, that is
11788 (subreg:MODE (plus (A) (-C1))) op (C2)
11790 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11791 comparison in the wider mode. One of the following two conditions
11792 must be true in order for this to be valid:
11794 1. The mode extension results in the same bit pattern being added
11795 on both sides and the comparison is equality or unsigned. As
11796 C2 has been truncated to fit in MODE, the pattern can only be
11799 2. The mode extension results in the sign bit being copied on
11802 The difficulty here is that we have predicates for A but not for
11803 (A - C1) so we need to check that C1 is within proper bounds so
11804 as to perturbate A as little as possible. */
11806 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11807 && subreg_lowpart_p (op0
)
11808 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
11809 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11810 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11812 machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11813 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11814 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11817 && (unsigned HOST_WIDE_INT
) c1
11818 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11819 && (equality_comparison_p
|| unsigned_comparison_p
)
11820 /* (A - C1) zero-extends if it is positive and sign-extends
11821 if it is negative, C2 both zero- and sign-extends. */
11822 && ((0 == (nonzero_bits (a
, inner_mode
)
11823 & ~GET_MODE_MASK (mode
))
11825 /* (A - C1) sign-extends if it is positive and 1-extends
11826 if it is negative, C2 both sign- and 1-extends. */
11827 || (num_sign_bit_copies (a
, inner_mode
)
11828 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11831 || ((unsigned HOST_WIDE_INT
) c1
11832 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11833 /* (A - C1) always sign-extends, like C2. */
11834 && num_sign_bit_copies (a
, inner_mode
)
11835 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11836 - (mode_width
- 1))))
11838 op0
= SUBREG_REG (op0
);
11843 /* If the inner mode is narrower and we are extracting the low part,
11844 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11845 if (subreg_lowpart_p (op0
)
11846 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11847 /* Fall through */ ;
11851 /* ... fall through ... */
11854 mode
= GET_MODE (XEXP (op0
, 0));
11855 if (GET_MODE_CLASS (mode
) == MODE_INT
11856 && (unsigned_comparison_p
|| equality_comparison_p
)
11857 && HWI_COMPUTABLE_MODE_P (mode
)
11858 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
11860 && have_insn_for (COMPARE
, mode
))
11862 op0
= XEXP (op0
, 0);
11868 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11869 this for equality comparisons due to pathological cases involving
11871 if (equality_comparison_p
11872 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11873 op1
, XEXP (op0
, 1))))
11875 op0
= XEXP (op0
, 0);
11880 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11881 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11882 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11884 op0
= XEXP (XEXP (op0
, 0), 0);
11885 code
= (code
== LT
? EQ
: NE
);
11891 /* We used to optimize signed comparisons against zero, but that
11892 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11893 arrive here as equality comparisons, or (GEU, LTU) are
11894 optimized away. No need to special-case them. */
11896 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11897 (eq B (minus A C)), whichever simplifies. We can only do
11898 this for equality comparisons due to pathological cases involving
11900 if (equality_comparison_p
11901 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11902 XEXP (op0
, 1), op1
)))
11904 op0
= XEXP (op0
, 0);
11909 if (equality_comparison_p
11910 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11911 XEXP (op0
, 0), op1
)))
11913 op0
= XEXP (op0
, 1);
11918 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11919 of bits in X minus 1, is one iff X > 0. */
11920 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11921 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11922 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11923 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11925 op0
= XEXP (op0
, 1);
11926 code
= (code
== GE
? LE
: GT
);
11932 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11933 if C is zero or B is a constant. */
11934 if (equality_comparison_p
11935 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11936 XEXP (op0
, 1), op1
)))
11938 op0
= XEXP (op0
, 0);
11945 case UNEQ
: case LTGT
:
11946 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11947 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11948 case UNORDERED
: case ORDERED
:
11949 /* We can't do anything if OP0 is a condition code value, rather
11950 than an actual data value. */
11952 || CC0_P (XEXP (op0
, 0))
11953 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11956 /* Get the two operands being compared. */
11957 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11958 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11960 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11962 /* Check for the cases where we simply want the result of the
11963 earlier test or the opposite of that result. */
11964 if (code
== NE
|| code
== EQ
11965 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
11966 && (code
== LT
|| code
== GE
)))
11968 enum rtx_code new_code
;
11969 if (code
== LT
|| code
== NE
)
11970 new_code
= GET_CODE (op0
);
11972 new_code
= reversed_comparison_code (op0
, NULL
);
11974 if (new_code
!= UNKNOWN
)
11985 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11987 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11988 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11989 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11991 op0
= XEXP (op0
, 1);
11992 code
= (code
== GE
? GT
: LE
);
11998 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11999 will be converted to a ZERO_EXTRACT later. */
12000 if (const_op
== 0 && equality_comparison_p
12001 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12002 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
12004 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
12005 XEXP (XEXP (op0
, 0), 1));
12006 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12010 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12011 zero and X is a comparison and C1 and C2 describe only bits set
12012 in STORE_FLAG_VALUE, we can compare with X. */
12013 if (const_op
== 0 && equality_comparison_p
12014 && mode_width
<= HOST_BITS_PER_WIDE_INT
12015 && CONST_INT_P (XEXP (op0
, 1))
12016 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
12017 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12018 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
12019 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
12021 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12022 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
12023 if ((~STORE_FLAG_VALUE
& mask
) == 0
12024 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
12025 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
12026 && COMPARISON_P (tem
))))
12028 op0
= XEXP (XEXP (op0
, 0), 0);
12033 /* If we are doing an equality comparison of an AND of a bit equal
12034 to the sign bit, replace this with a LT or GE comparison of
12035 the underlying value. */
12036 if (equality_comparison_p
12038 && CONST_INT_P (XEXP (op0
, 1))
12039 && mode_width
<= HOST_BITS_PER_WIDE_INT
12040 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12041 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
12043 op0
= XEXP (op0
, 0);
12044 code
= (code
== EQ
? GE
: LT
);
12048 /* If this AND operation is really a ZERO_EXTEND from a narrower
12049 mode, the constant fits within that mode, and this is either an
12050 equality or unsigned comparison, try to do this comparison in
12055 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12056 -> (ne:DI (reg:SI 4) (const_int 0))
12058 unless TRULY_NOOP_TRUNCATION allows it or the register is
12059 known to hold a value of the required mode the
12060 transformation is invalid. */
12061 if ((equality_comparison_p
|| unsigned_comparison_p
)
12062 && CONST_INT_P (XEXP (op0
, 1))
12063 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
12064 & GET_MODE_MASK (mode
))
12066 && const_op
>> i
== 0
12067 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
12068 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode
, GET_MODE (op0
))
12069 || (REG_P (XEXP (op0
, 0))
12070 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
12072 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
12076 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
12077 fits in both M1 and M2 and the SUBREG is either paradoxical
12078 or represents the low part, permute the SUBREG and the AND
12080 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
12082 unsigned HOST_WIDE_INT c1
;
12083 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
12084 /* Require an integral mode, to avoid creating something like
12086 if (SCALAR_INT_MODE_P (tmode
)
12087 /* It is unsafe to commute the AND into the SUBREG if the
12088 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12089 not defined. As originally written the upper bits
12090 have a defined value due to the AND operation.
12091 However, if we commute the AND inside the SUBREG then
12092 they no longer have defined values and the meaning of
12093 the code has been changed. */
12095 #ifdef WORD_REGISTER_OPERATIONS
12096 || (mode_width
> GET_MODE_PRECISION (tmode
)
12097 && mode_width
<= BITS_PER_WORD
)
12099 || (mode_width
<= GET_MODE_PRECISION (tmode
)
12100 && subreg_lowpart_p (XEXP (op0
, 0))))
12101 && CONST_INT_P (XEXP (op0
, 1))
12102 && mode_width
<= HOST_BITS_PER_WIDE_INT
12103 && HWI_COMPUTABLE_MODE_P (tmode
)
12104 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
12105 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
12107 && c1
!= GET_MODE_MASK (tmode
))
12109 op0
= simplify_gen_binary (AND
, tmode
,
12110 SUBREG_REG (XEXP (op0
, 0)),
12111 gen_int_mode (c1
, tmode
));
12112 op0
= gen_lowpart (mode
, op0
);
12117 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12118 if (const_op
== 0 && equality_comparison_p
12119 && XEXP (op0
, 1) == const1_rtx
12120 && GET_CODE (XEXP (op0
, 0)) == NOT
)
12122 op0
= simplify_and_const_int (NULL_RTX
, mode
,
12123 XEXP (XEXP (op0
, 0), 0), 1);
12124 code
= (code
== NE
? EQ
: NE
);
12128 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12129 (eq (and (lshiftrt X) 1) 0).
12130 Also handle the case where (not X) is expressed using xor. */
12131 if (const_op
== 0 && equality_comparison_p
12132 && XEXP (op0
, 1) == const1_rtx
12133 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
12135 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
12136 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
12138 if (GET_CODE (shift_op
) == NOT
12139 || (GET_CODE (shift_op
) == XOR
12140 && CONST_INT_P (XEXP (shift_op
, 1))
12141 && CONST_INT_P (shift_count
)
12142 && HWI_COMPUTABLE_MODE_P (mode
)
12143 && (UINTVAL (XEXP (shift_op
, 1))
12144 == (unsigned HOST_WIDE_INT
) 1
12145 << INTVAL (shift_count
))))
12148 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
12149 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12150 code
= (code
== NE
? EQ
: NE
);
12157 /* If we have (compare (ashift FOO N) (const_int C)) and
12158 the high order N bits of FOO (N+1 if an inequality comparison)
12159 are known to be zero, we can do this by comparing FOO with C
12160 shifted right N bits so long as the low-order N bits of C are
12162 if (CONST_INT_P (XEXP (op0
, 1))
12163 && INTVAL (XEXP (op0
, 1)) >= 0
12164 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
12165 < HOST_BITS_PER_WIDE_INT
)
12166 && (((unsigned HOST_WIDE_INT
) const_op
12167 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
12169 && mode_width
<= HOST_BITS_PER_WIDE_INT
12170 && (nonzero_bits (XEXP (op0
, 0), mode
)
12171 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
12172 + ! equality_comparison_p
))) == 0)
12174 /* We must perform a logical shift, not an arithmetic one,
12175 as we want the top N bits of C to be zero. */
12176 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
12178 temp
>>= INTVAL (XEXP (op0
, 1));
12179 op1
= gen_int_mode (temp
, mode
);
12180 op0
= XEXP (op0
, 0);
12184 /* If we are doing a sign bit comparison, it means we are testing
12185 a particular bit. Convert it to the appropriate AND. */
12186 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12187 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12189 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12190 ((unsigned HOST_WIDE_INT
) 1
12192 - INTVAL (XEXP (op0
, 1)))));
12193 code
= (code
== LT
? NE
: EQ
);
12197 /* If this an equality comparison with zero and we are shifting
12198 the low bit to the sign bit, we can convert this to an AND of the
12200 if (const_op
== 0 && equality_comparison_p
12201 && CONST_INT_P (XEXP (op0
, 1))
12202 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12204 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
12210 /* If this is an equality comparison with zero, we can do this
12211 as a logical shift, which might be much simpler. */
12212 if (equality_comparison_p
&& const_op
== 0
12213 && CONST_INT_P (XEXP (op0
, 1)))
12215 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
12217 INTVAL (XEXP (op0
, 1)));
12221 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12222 do the comparison in a narrower mode. */
12223 if (! unsigned_comparison_p
12224 && CONST_INT_P (XEXP (op0
, 1))
12225 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12226 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12227 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12228 MODE_INT
, 1)) != BLKmode
12229 && (((unsigned HOST_WIDE_INT
) const_op
12230 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12231 <= GET_MODE_MASK (tmode
)))
12233 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
12237 /* Likewise if OP0 is a PLUS of a sign extension with a
12238 constant, which is usually represented with the PLUS
12239 between the shifts. */
12240 if (! unsigned_comparison_p
12241 && CONST_INT_P (XEXP (op0
, 1))
12242 && GET_CODE (XEXP (op0
, 0)) == PLUS
12243 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12244 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
12245 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
12246 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12247 MODE_INT
, 1)) != BLKmode
12248 && (((unsigned HOST_WIDE_INT
) const_op
12249 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12250 <= GET_MODE_MASK (tmode
)))
12252 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
12253 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
12254 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
12255 add_const
, XEXP (op0
, 1));
12257 op0
= simplify_gen_binary (PLUS
, tmode
,
12258 gen_lowpart (tmode
, inner
),
12263 /* ... fall through ... */
12265 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12266 the low order N bits of FOO are known to be zero, we can do this
12267 by comparing FOO with C shifted left N bits so long as no
12268 overflow occurs. Even if the low order N bits of FOO aren't known
12269 to be zero, if the comparison is >= or < we can use the same
12270 optimization and for > or <= by setting all the low
12271 order N bits in the comparison constant. */
12272 if (CONST_INT_P (XEXP (op0
, 1))
12273 && INTVAL (XEXP (op0
, 1)) > 0
12274 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12275 && mode_width
<= HOST_BITS_PER_WIDE_INT
12276 && (((unsigned HOST_WIDE_INT
) const_op
12277 + (GET_CODE (op0
) != LSHIFTRT
12278 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
12281 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
12283 unsigned HOST_WIDE_INT low_bits
12284 = (nonzero_bits (XEXP (op0
, 0), mode
)
12285 & (((unsigned HOST_WIDE_INT
) 1
12286 << INTVAL (XEXP (op0
, 1))) - 1));
12287 if (low_bits
== 0 || !equality_comparison_p
)
12289 /* If the shift was logical, then we must make the condition
12291 if (GET_CODE (op0
) == LSHIFTRT
)
12292 code
= unsigned_condition (code
);
12294 const_op
<<= INTVAL (XEXP (op0
, 1));
12296 && (code
== GT
|| code
== GTU
12297 || code
== LE
|| code
== LEU
))
12299 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
12300 op1
= GEN_INT (const_op
);
12301 op0
= XEXP (op0
, 0);
12306 /* If we are using this shift to extract just the sign bit, we
12307 can replace this with an LT or GE comparison. */
12309 && (equality_comparison_p
|| sign_bit_comparison_p
)
12310 && CONST_INT_P (XEXP (op0
, 1))
12311 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12313 op0
= XEXP (op0
, 0);
12314 code
= (code
== NE
|| code
== GT
? LT
: GE
);
12326 /* Now make any compound operations involved in this comparison. Then,
12327 check for an outmost SUBREG on OP0 that is not doing anything or is
12328 paradoxical. The latter transformation must only be performed when
12329 it is known that the "extra" bits will be the same in op0 and op1 or
12330 that they don't matter. There are three cases to consider:
12332 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12333 care bits and we can assume they have any convenient value. So
12334 making the transformation is safe.
12336 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12337 In this case the upper bits of op0 are undefined. We should not make
12338 the simplification in that case as we do not know the contents of
12341 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12342 UNKNOWN. In that case we know those bits are zeros or ones. We must
12343 also be sure that they are the same as the upper bits of op1.
12345 We can never remove a SUBREG for a non-equality comparison because
12346 the sign bit is in a different place in the underlying object. */
12348 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
12349 op1
= make_compound_operation (op1
, SET
);
12351 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
12352 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12353 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12354 && (code
== NE
|| code
== EQ
))
12356 if (paradoxical_subreg_p (op0
))
12358 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12360 if (REG_P (SUBREG_REG (op0
)))
12362 op0
= SUBREG_REG (op0
);
12363 op1
= gen_lowpart (GET_MODE (op0
), op1
);
12366 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12367 <= HOST_BITS_PER_WIDE_INT
)
12368 && (nonzero_bits (SUBREG_REG (op0
),
12369 GET_MODE (SUBREG_REG (op0
)))
12370 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12372 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12374 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12375 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12376 op0
= SUBREG_REG (op0
), op1
= tem
;
12380 /* We now do the opposite procedure: Some machines don't have compare
12381 insns in all modes. If OP0's mode is an integer mode smaller than a
12382 word and we can't do a compare in that mode, see if there is a larger
12383 mode for which we can do the compare. There are a number of cases in
12384 which we can use the wider mode. */
12386 mode
= GET_MODE (op0
);
12387 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
12388 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12389 && ! have_insn_for (COMPARE
, mode
))
12390 for (tmode
= GET_MODE_WIDER_MODE (mode
);
12391 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
12392 tmode
= GET_MODE_WIDER_MODE (tmode
))
12393 if (have_insn_for (COMPARE
, tmode
))
12397 /* If this is a test for negative, we can make an explicit
12398 test of the sign bit. Test this first so we can use
12399 a paradoxical subreg to extend OP0. */
12401 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12402 && HWI_COMPUTABLE_MODE_P (mode
))
12404 unsigned HOST_WIDE_INT sign
12405 = (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1);
12406 op0
= simplify_gen_binary (AND
, tmode
,
12407 gen_lowpart (tmode
, op0
),
12408 gen_int_mode (sign
, tmode
));
12409 code
= (code
== LT
) ? NE
: EQ
;
12413 /* If the only nonzero bits in OP0 and OP1 are those in the
12414 narrower mode and this is an equality or unsigned comparison,
12415 we can use the wider mode. Similarly for sign-extended
12416 values, in which case it is true for all comparisons. */
12417 zero_extended
= ((code
== EQ
|| code
== NE
12418 || code
== GEU
|| code
== GTU
12419 || code
== LEU
|| code
== LTU
)
12420 && (nonzero_bits (op0
, tmode
)
12421 & ~GET_MODE_MASK (mode
)) == 0
12422 && ((CONST_INT_P (op1
)
12423 || (nonzero_bits (op1
, tmode
)
12424 & ~GET_MODE_MASK (mode
)) == 0)));
12427 || ((num_sign_bit_copies (op0
, tmode
)
12428 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12429 - GET_MODE_PRECISION (mode
)))
12430 && (num_sign_bit_copies (op1
, tmode
)
12431 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12432 - GET_MODE_PRECISION (mode
)))))
12434 /* If OP0 is an AND and we don't have an AND in MODE either,
12435 make a new AND in the proper mode. */
12436 if (GET_CODE (op0
) == AND
12437 && !have_insn_for (AND
, mode
))
12438 op0
= simplify_gen_binary (AND
, tmode
,
12439 gen_lowpart (tmode
,
12441 gen_lowpart (tmode
,
12447 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12448 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12452 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12453 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12460 /* We may have changed the comparison operands. Re-canonicalize. */
12461 if (swap_commutative_operands_p (op0
, op1
))
12463 std::swap (op0
, op1
);
12464 code
= swap_condition (code
);
12467 /* If this machine only supports a subset of valid comparisons, see if we
12468 can convert an unsupported one into a supported one. */
12469 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12477 /* Utility function for record_value_for_reg. Count number of
12482 enum rtx_code code
= GET_CODE (x
);
12486 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12487 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12489 rtx x0
= XEXP (x
, 0);
12490 rtx x1
= XEXP (x
, 1);
12493 return 1 + 2 * count_rtxs (x0
);
12495 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12496 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12497 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12498 return 2 + 2 * count_rtxs (x0
)
12499 + count_rtxs (x
== XEXP (x1
, 0)
12500 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12502 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12503 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12504 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12505 return 2 + 2 * count_rtxs (x1
)
12506 + count_rtxs (x
== XEXP (x0
, 0)
12507 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12510 fmt
= GET_RTX_FORMAT (code
);
12511 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12513 ret
+= count_rtxs (XEXP (x
, i
));
12514 else if (fmt
[i
] == 'E')
12515 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12516 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12521 /* Utility function for following routine. Called when X is part of a value
12522 being stored into last_set_value. Sets last_set_table_tick
12523 for each register mentioned. Similar to mention_regs in cse.c */
12526 update_table_tick (rtx x
)
12528 enum rtx_code code
= GET_CODE (x
);
12529 const char *fmt
= GET_RTX_FORMAT (code
);
12534 unsigned int regno
= REGNO (x
);
12535 unsigned int endregno
= END_REGNO (x
);
12538 for (r
= regno
; r
< endregno
; r
++)
12540 reg_stat_type
*rsp
= ®_stat
[r
];
12541 rsp
->last_set_table_tick
= label_tick
;
12547 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12550 /* Check for identical subexpressions. If x contains
12551 identical subexpression we only have to traverse one of
12553 if (i
== 0 && ARITHMETIC_P (x
))
12555 /* Note that at this point x1 has already been
12557 rtx x0
= XEXP (x
, 0);
12558 rtx x1
= XEXP (x
, 1);
12560 /* If x0 and x1 are identical then there is no need to
12565 /* If x0 is identical to a subexpression of x1 then while
12566 processing x1, x0 has already been processed. Thus we
12567 are done with x. */
12568 if (ARITHMETIC_P (x1
)
12569 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12572 /* If x1 is identical to a subexpression of x0 then we
12573 still have to process the rest of x0. */
12574 if (ARITHMETIC_P (x0
)
12575 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12577 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12582 update_table_tick (XEXP (x
, i
));
12584 else if (fmt
[i
] == 'E')
12585 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12586 update_table_tick (XVECEXP (x
, i
, j
));
12589 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12590 are saying that the register is clobbered and we no longer know its
12591 value. If INSN is zero, don't update reg_stat[].last_set; this is
12592 only permitted with VALUE also zero and is used to invalidate the
12596 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
12598 unsigned int regno
= REGNO (reg
);
12599 unsigned int endregno
= END_REGNO (reg
);
12601 reg_stat_type
*rsp
;
12603 /* If VALUE contains REG and we have a previous value for REG, substitute
12604 the previous value. */
12605 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12609 /* Set things up so get_last_value is allowed to see anything set up to
12611 subst_low_luid
= DF_INSN_LUID (insn
);
12612 tem
= get_last_value (reg
);
12614 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12615 it isn't going to be useful and will take a lot of time to process,
12616 so just use the CLOBBER. */
12620 if (ARITHMETIC_P (tem
)
12621 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12622 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12623 tem
= XEXP (tem
, 0);
12624 else if (count_occurrences (value
, reg
, 1) >= 2)
12626 /* If there are two or more occurrences of REG in VALUE,
12627 prevent the value from growing too much. */
12628 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12629 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12632 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12636 /* For each register modified, show we don't know its value, that
12637 we don't know about its bitwise content, that its value has been
12638 updated, and that we don't know the location of the death of the
12640 for (i
= regno
; i
< endregno
; i
++)
12642 rsp
= ®_stat
[i
];
12645 rsp
->last_set
= insn
;
12647 rsp
->last_set_value
= 0;
12648 rsp
->last_set_mode
= VOIDmode
;
12649 rsp
->last_set_nonzero_bits
= 0;
12650 rsp
->last_set_sign_bit_copies
= 0;
12651 rsp
->last_death
= 0;
12652 rsp
->truncated_to_mode
= VOIDmode
;
12655 /* Mark registers that are being referenced in this value. */
12657 update_table_tick (value
);
12659 /* Now update the status of each register being set.
12660 If someone is using this register in this block, set this register
12661 to invalid since we will get confused between the two lives in this
12662 basic block. This makes using this register always invalid. In cse, we
12663 scan the table to invalidate all entries using this register, but this
12664 is too much work for us. */
12666 for (i
= regno
; i
< endregno
; i
++)
12668 rsp
= ®_stat
[i
];
12669 rsp
->last_set_label
= label_tick
;
12671 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12672 rsp
->last_set_invalid
= 1;
12674 rsp
->last_set_invalid
= 0;
12677 /* The value being assigned might refer to X (like in "x++;"). In that
12678 case, we must replace it with (clobber (const_int 0)) to prevent
12680 rsp
= ®_stat
[regno
];
12681 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12683 value
= copy_rtx (value
);
12684 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12688 /* For the main register being modified, update the value, the mode, the
12689 nonzero bits, and the number of sign bit copies. */
12691 rsp
->last_set_value
= value
;
12695 machine_mode mode
= GET_MODE (reg
);
12696 subst_low_luid
= DF_INSN_LUID (insn
);
12697 rsp
->last_set_mode
= mode
;
12698 if (GET_MODE_CLASS (mode
) == MODE_INT
12699 && HWI_COMPUTABLE_MODE_P (mode
))
12700 mode
= nonzero_bits_mode
;
12701 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12702 rsp
->last_set_sign_bit_copies
12703 = num_sign_bit_copies (value
, GET_MODE (reg
));
12707 /* Called via note_stores from record_dead_and_set_regs to handle one
12708 SET or CLOBBER in an insn. DATA is the instruction in which the
12709 set is occurring. */
12712 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12714 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
12716 if (GET_CODE (dest
) == SUBREG
)
12717 dest
= SUBREG_REG (dest
);
12719 if (!record_dead_insn
)
12722 record_value_for_reg (dest
, NULL
, NULL_RTX
);
12728 /* If we are setting the whole register, we know its value. Otherwise
12729 show that we don't know the value. We can handle SUBREG in
12731 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12732 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12733 else if (GET_CODE (setter
) == SET
12734 && GET_CODE (SET_DEST (setter
)) == SUBREG
12735 && SUBREG_REG (SET_DEST (setter
)) == dest
12736 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
12737 && subreg_lowpart_p (SET_DEST (setter
)))
12738 record_value_for_reg (dest
, record_dead_insn
,
12739 gen_lowpart (GET_MODE (dest
),
12740 SET_SRC (setter
)));
12742 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12744 else if (MEM_P (dest
)
12745 /* Ignore pushes, they clobber nothing. */
12746 && ! push_operand (dest
, GET_MODE (dest
)))
12747 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12750 /* Update the records of when each REG was most recently set or killed
12751 for the things done by INSN. This is the last thing done in processing
12752 INSN in the combiner loop.
12754 We update reg_stat[], in particular fields last_set, last_set_value,
12755 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12756 last_death, and also the similar information mem_last_set (which insn
12757 most recently modified memory) and last_call_luid (which insn was the
12758 most recent subroutine call). */
12761 record_dead_and_set_regs (rtx_insn
*insn
)
12766 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12768 if (REG_NOTE_KIND (link
) == REG_DEAD
12769 && REG_P (XEXP (link
, 0)))
12771 unsigned int regno
= REGNO (XEXP (link
, 0));
12772 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12774 for (i
= regno
; i
< endregno
; i
++)
12776 reg_stat_type
*rsp
;
12778 rsp
= ®_stat
[i
];
12779 rsp
->last_death
= insn
;
12782 else if (REG_NOTE_KIND (link
) == REG_INC
)
12783 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12788 hard_reg_set_iterator hrsi
;
12789 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
12791 reg_stat_type
*rsp
;
12793 rsp
= ®_stat
[i
];
12794 rsp
->last_set_invalid
= 1;
12795 rsp
->last_set
= insn
;
12796 rsp
->last_set_value
= 0;
12797 rsp
->last_set_mode
= VOIDmode
;
12798 rsp
->last_set_nonzero_bits
= 0;
12799 rsp
->last_set_sign_bit_copies
= 0;
12800 rsp
->last_death
= 0;
12801 rsp
->truncated_to_mode
= VOIDmode
;
12804 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12806 /* We can't combine into a call pattern. Remember, though, that
12807 the return value register is set at this LUID. We could
12808 still replace a register with the return value from the
12809 wrong subroutine call! */
12810 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12813 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12816 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12817 register present in the SUBREG, so for each such SUBREG go back and
12818 adjust nonzero and sign bit information of the registers that are
12819 known to have some zero/sign bits set.
12821 This is needed because when combine blows the SUBREGs away, the
12822 information on zero/sign bits is lost and further combines can be
12823 missed because of that. */
12826 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
12828 struct insn_link
*links
;
12830 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12831 machine_mode mode
= GET_MODE (subreg
);
12833 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
12836 for (links
= LOG_LINKS (insn
); links
;)
12838 reg_stat_type
*rsp
;
12840 insn
= links
->insn
;
12841 set
= single_set (insn
);
12843 if (! set
|| !REG_P (SET_DEST (set
))
12844 || REGNO (SET_DEST (set
)) != regno
12845 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12847 links
= links
->next
;
12851 rsp
= ®_stat
[regno
];
12852 if (rsp
->last_set
== insn
)
12854 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
12855 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12858 if (REG_P (SET_SRC (set
)))
12860 regno
= REGNO (SET_SRC (set
));
12861 links
= LOG_LINKS (insn
);
12868 /* Check if X, a register, is known to contain a value already
12869 truncated to MODE. In this case we can use a subreg to refer to
12870 the truncated value even though in the generic case we would need
12871 an explicit truncation. */
12874 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
12876 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
12877 machine_mode truncated
= rsp
->truncated_to_mode
;
12880 || rsp
->truncation_label
< label_tick_ebb_start
)
12882 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12884 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
12889 /* If X is a hard reg or a subreg record the mode that the register is
12890 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12891 to turn a truncate into a subreg using this information. Return true
12892 if traversing X is complete. */
12895 record_truncated_value (rtx x
)
12897 machine_mode truncated_mode
;
12898 reg_stat_type
*rsp
;
12900 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12902 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12903 truncated_mode
= GET_MODE (x
);
12905 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12908 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
12911 x
= SUBREG_REG (x
);
12913 /* ??? For hard-regs we now record everything. We might be able to
12914 optimize this using last_set_mode. */
12915 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12916 truncated_mode
= GET_MODE (x
);
12920 rsp
= ®_stat
[REGNO (x
)];
12921 if (rsp
->truncated_to_mode
== 0
12922 || rsp
->truncation_label
< label_tick_ebb_start
12923 || (GET_MODE_SIZE (truncated_mode
)
12924 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12926 rsp
->truncated_to_mode
= truncated_mode
;
12927 rsp
->truncation_label
= label_tick
;
12933 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12934 the modes they are used in. This can help truning TRUNCATEs into
12938 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
12940 subrtx_var_iterator::array_type array
;
12941 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
12942 if (record_truncated_value (*iter
))
12943 iter
.skip_subrtxes ();
12946 /* Scan X for promoted SUBREGs. For each one found,
12947 note what it implies to the registers used in it. */
12950 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
12952 if (GET_CODE (x
) == SUBREG
12953 && SUBREG_PROMOTED_VAR_P (x
)
12954 && REG_P (SUBREG_REG (x
)))
12955 record_promoted_value (insn
, x
);
12958 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12961 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12965 check_promoted_subreg (insn
, XEXP (x
, i
));
12969 if (XVEC (x
, i
) != 0)
12970 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12971 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12977 /* Verify that all the registers and memory references mentioned in *LOC are
12978 still valid. *LOC was part of a value set in INSN when label_tick was
12979 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12980 the invalid references with (clobber (const_int 0)) and return 1. This
12981 replacement is useful because we often can get useful information about
12982 the form of a value (e.g., if it was produced by a shift that always
12983 produces -1 or 0) even though we don't know exactly what registers it
12984 was produced from. */
12987 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
12990 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12991 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12996 unsigned int regno
= REGNO (x
);
12997 unsigned int endregno
= END_REGNO (x
);
13000 for (j
= regno
; j
< endregno
; j
++)
13002 reg_stat_type
*rsp
= ®_stat
[j
];
13003 if (rsp
->last_set_invalid
13004 /* If this is a pseudo-register that was only set once and not
13005 live at the beginning of the function, it is always valid. */
13006 || (! (regno
>= FIRST_PSEUDO_REGISTER
13007 && regno
< reg_n_sets_max
13008 && REG_N_SETS (regno
) == 1
13009 && (!REGNO_REG_SET_P
13010 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
13012 && rsp
->last_set_label
> tick
))
13015 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13022 /* If this is a memory reference, make sure that there were no stores after
13023 it that might have clobbered the value. We don't have alias info, so we
13024 assume any store invalidates it. Moreover, we only have local UIDs, so
13025 we also assume that there were stores in the intervening basic blocks. */
13026 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
13027 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
13030 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13034 for (i
= 0; i
< len
; i
++)
13038 /* Check for identical subexpressions. If x contains
13039 identical subexpression we only have to traverse one of
13041 if (i
== 1 && ARITHMETIC_P (x
))
13043 /* Note that at this point x0 has already been checked
13044 and found valid. */
13045 rtx x0
= XEXP (x
, 0);
13046 rtx x1
= XEXP (x
, 1);
13048 /* If x0 and x1 are identical then x is also valid. */
13052 /* If x1 is identical to a subexpression of x0 then
13053 while checking x0, x1 has already been checked. Thus
13054 it is valid and so as x. */
13055 if (ARITHMETIC_P (x0
)
13056 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13059 /* If x0 is identical to a subexpression of x1 then x is
13060 valid iff the rest of x1 is valid. */
13061 if (ARITHMETIC_P (x1
)
13062 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13064 get_last_value_validate (&XEXP (x1
,
13065 x0
== XEXP (x1
, 0) ? 1 : 0),
13066 insn
, tick
, replace
);
13069 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
13073 else if (fmt
[i
] == 'E')
13074 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13075 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
13076 insn
, tick
, replace
) == 0)
13080 /* If we haven't found a reason for it to be invalid, it is valid. */
13084 /* Get the last value assigned to X, if known. Some registers
13085 in the value may be replaced with (clobber (const_int 0)) if their value
13086 is known longer known reliably. */
13089 get_last_value (const_rtx x
)
13091 unsigned int regno
;
13093 reg_stat_type
*rsp
;
13095 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13096 then convert it to the desired mode. If this is a paradoxical SUBREG,
13097 we cannot predict what values the "extra" bits might have. */
13098 if (GET_CODE (x
) == SUBREG
13099 && subreg_lowpart_p (x
)
13100 && !paradoxical_subreg_p (x
)
13101 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
13102 return gen_lowpart (GET_MODE (x
), value
);
13108 rsp
= ®_stat
[regno
];
13109 value
= rsp
->last_set_value
;
13111 /* If we don't have a value, or if it isn't for this basic block and
13112 it's either a hard register, set more than once, or it's a live
13113 at the beginning of the function, return 0.
13115 Because if it's not live at the beginning of the function then the reg
13116 is always set before being used (is never used without being set).
13117 And, if it's set only once, and it's always set before use, then all
13118 uses must have the same last value, even if it's not from this basic
13122 || (rsp
->last_set_label
< label_tick_ebb_start
13123 && (regno
< FIRST_PSEUDO_REGISTER
13124 || regno
>= reg_n_sets_max
13125 || REG_N_SETS (regno
) != 1
13127 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
13130 /* If the value was set in a later insn than the ones we are processing,
13131 we can't use it even if the register was only set once. */
13132 if (rsp
->last_set_label
== label_tick
13133 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
13136 /* If the value has all its registers valid, return it. */
13137 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
13140 /* Otherwise, make a copy and replace any invalid register with
13141 (clobber (const_int 0)). If that fails for some reason, return 0. */
13143 value
= copy_rtx (value
);
13144 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
13150 /* Return nonzero if expression X refers to a REG or to memory
13151 that is set in an instruction more recent than FROM_LUID. */
13154 use_crosses_set_p (const_rtx x
, int from_luid
)
13158 enum rtx_code code
= GET_CODE (x
);
13162 unsigned int regno
= REGNO (x
);
13163 unsigned endreg
= END_REGNO (x
);
13165 #ifdef PUSH_ROUNDING
13166 /* Don't allow uses of the stack pointer to be moved,
13167 because we don't know whether the move crosses a push insn. */
13168 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
13171 for (; regno
< endreg
; regno
++)
13173 reg_stat_type
*rsp
= ®_stat
[regno
];
13175 && rsp
->last_set_label
== label_tick
13176 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
13182 if (code
== MEM
&& mem_last_set
> from_luid
)
13185 fmt
= GET_RTX_FORMAT (code
);
13187 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13192 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13193 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
13196 else if (fmt
[i
] == 'e'
13197 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
13203 /* Define three variables used for communication between the following
13206 static unsigned int reg_dead_regno
, reg_dead_endregno
;
13207 static int reg_dead_flag
;
13209 /* Function called via note_stores from reg_dead_at_p.
13211 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13212 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13215 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
13217 unsigned int regno
, endregno
;
13222 regno
= REGNO (dest
);
13223 endregno
= END_REGNO (dest
);
13224 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
13225 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
13228 /* Return nonzero if REG is known to be dead at INSN.
13230 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13231 referencing REG, it is dead. If we hit a SET referencing REG, it is
13232 live. Otherwise, see if it is live or dead at the start of the basic
13233 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13234 must be assumed to be always live. */
13237 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
13242 /* Set variables for reg_dead_at_p_1. */
13243 reg_dead_regno
= REGNO (reg
);
13244 reg_dead_endregno
= END_REGNO (reg
);
13248 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13249 we allow the machine description to decide whether use-and-clobber
13250 patterns are OK. */
13251 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
13253 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13254 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
13258 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13259 beginning of basic block. */
13260 block
= BLOCK_FOR_INSN (insn
);
13265 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13268 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
13270 return reg_dead_flag
== 1 ? 1 : 0;
13272 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13276 if (insn
== BB_HEAD (block
))
13279 insn
= PREV_INSN (insn
);
13282 /* Look at live-in sets for the basic block that we were in. */
13283 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13284 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
13290 /* Note hard registers in X that are used. */
13293 mark_used_regs_combine (rtx x
)
13295 RTX_CODE code
= GET_CODE (x
);
13296 unsigned int regno
;
13307 case ADDR_DIFF_VEC
:
13309 /* CC0 must die in the insn after it is set, so we don't need to take
13310 special note of it here. */
13315 /* If we are clobbering a MEM, mark any hard registers inside the
13316 address as used. */
13317 if (MEM_P (XEXP (x
, 0)))
13318 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
13323 /* A hard reg in a wide mode may really be multiple registers.
13324 If so, mark all of them just like the first. */
13325 if (regno
< FIRST_PSEUDO_REGISTER
)
13327 /* None of this applies to the stack, frame or arg pointers. */
13328 if (regno
== STACK_POINTER_REGNUM
13329 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
13330 || regno
== HARD_FRAME_POINTER_REGNUM
13332 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
13333 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
13334 || regno
== FRAME_POINTER_REGNUM
)
13337 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
13343 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13345 rtx testreg
= SET_DEST (x
);
13347 while (GET_CODE (testreg
) == SUBREG
13348 || GET_CODE (testreg
) == ZERO_EXTRACT
13349 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13350 testreg
= XEXP (testreg
, 0);
13352 if (MEM_P (testreg
))
13353 mark_used_regs_combine (XEXP (testreg
, 0));
13355 mark_used_regs_combine (SET_SRC (x
));
13363 /* Recursively scan the operands of this expression. */
13366 const char *fmt
= GET_RTX_FORMAT (code
);
13368 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13371 mark_used_regs_combine (XEXP (x
, i
));
13372 else if (fmt
[i
] == 'E')
13376 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13377 mark_used_regs_combine (XVECEXP (x
, i
, j
));
13383 /* Remove register number REGNO from the dead registers list of INSN.
13385 Return the note used to record the death, if there was one. */
13388 remove_death (unsigned int regno
, rtx_insn
*insn
)
13390 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13393 remove_note (insn
, note
);
13398 /* For each register (hardware or pseudo) used within expression X, if its
13399 death is in an instruction with luid between FROM_LUID (inclusive) and
13400 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13401 list headed by PNOTES.
13403 That said, don't move registers killed by maybe_kill_insn.
13405 This is done when X is being merged by combination into TO_INSN. These
13406 notes will then be distributed as needed. */
13409 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13414 enum rtx_code code
= GET_CODE (x
);
13418 unsigned int regno
= REGNO (x
);
13419 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13421 /* Don't move the register if it gets killed in between from and to. */
13422 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13423 && ! reg_referenced_p (x
, maybe_kill_insn
))
13427 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13428 && DF_INSN_LUID (where_dead
) >= from_luid
13429 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13431 rtx note
= remove_death (regno
, where_dead
);
13433 /* It is possible for the call above to return 0. This can occur
13434 when last_death points to I2 or I1 that we combined with.
13435 In that case make a new note.
13437 We must also check for the case where X is a hard register
13438 and NOTE is a death note for a range of hard registers
13439 including X. In that case, we must put REG_DEAD notes for
13440 the remaining registers in place of NOTE. */
13442 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13443 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13444 > GET_MODE_SIZE (GET_MODE (x
))))
13446 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13447 unsigned int deadend
= END_REGNO (XEXP (note
, 0));
13448 unsigned int ourend
= END_REGNO (x
);
13451 for (i
= deadregno
; i
< deadend
; i
++)
13452 if (i
< regno
|| i
>= ourend
)
13453 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13456 /* If we didn't find any note, or if we found a REG_DEAD note that
13457 covers only part of the given reg, and we have a multi-reg hard
13458 register, then to be safe we must check for REG_DEAD notes
13459 for each register other than the first. They could have
13460 their own REG_DEAD notes lying around. */
13461 else if ((note
== 0
13463 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13464 < GET_MODE_SIZE (GET_MODE (x
)))))
13465 && regno
< FIRST_PSEUDO_REGISTER
13466 && REG_NREGS (x
) > 1)
13468 unsigned int ourend
= END_REGNO (x
);
13469 unsigned int i
, offset
;
13473 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13477 for (i
= regno
+ offset
; i
< ourend
; i
++)
13478 move_deaths (regno_reg_rtx
[i
],
13479 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13482 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13484 XEXP (note
, 1) = *pnotes
;
13488 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13494 else if (GET_CODE (x
) == SET
)
13496 rtx dest
= SET_DEST (x
);
13498 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13500 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13501 that accesses one word of a multi-word item, some
13502 piece of everything register in the expression is used by
13503 this insn, so remove any old death. */
13504 /* ??? So why do we test for equality of the sizes? */
13506 if (GET_CODE (dest
) == ZERO_EXTRACT
13507 || GET_CODE (dest
) == STRICT_LOW_PART
13508 || (GET_CODE (dest
) == SUBREG
13509 && (((GET_MODE_SIZE (GET_MODE (dest
))
13510 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13511 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13512 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13514 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13518 /* If this is some other SUBREG, we know it replaces the entire
13519 value, so use that as the destination. */
13520 if (GET_CODE (dest
) == SUBREG
)
13521 dest
= SUBREG_REG (dest
);
13523 /* If this is a MEM, adjust deaths of anything used in the address.
13524 For a REG (the only other possibility), the entire value is
13525 being replaced so the old value is not used in this insn. */
13528 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13533 else if (GET_CODE (x
) == CLOBBER
)
13536 len
= GET_RTX_LENGTH (code
);
13537 fmt
= GET_RTX_FORMAT (code
);
13539 for (i
= 0; i
< len
; i
++)
13544 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13545 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13548 else if (fmt
[i
] == 'e')
13549 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13553 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13554 pattern of an insn. X must be a REG. */
13557 reg_bitfield_target_p (rtx x
, rtx body
)
13561 if (GET_CODE (body
) == SET
)
13563 rtx dest
= SET_DEST (body
);
13565 unsigned int regno
, tregno
, endregno
, endtregno
;
13567 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13568 target
= XEXP (dest
, 0);
13569 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13570 target
= SUBREG_REG (XEXP (dest
, 0));
13574 if (GET_CODE (target
) == SUBREG
)
13575 target
= SUBREG_REG (target
);
13577 if (!REG_P (target
))
13580 tregno
= REGNO (target
), regno
= REGNO (x
);
13581 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13582 return target
== x
;
13584 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13585 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13587 return endregno
> tregno
&& regno
< endtregno
;
13590 else if (GET_CODE (body
) == PARALLEL
)
13591 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13592 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13598 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13599 as appropriate. I3 and I2 are the insns resulting from the combination
13600 insns including FROM (I2 may be zero).
13602 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13603 not need REG_DEAD notes because they are being substituted for. This
13604 saves searching in the most common cases.
13606 Each note in the list is either ignored or placed on some insns, depending
13607 on the type of note. */
13610 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
13611 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
13613 rtx note
, next_note
;
13615 rtx_insn
*tem_insn
;
13617 for (note
= notes
; note
; note
= next_note
)
13619 rtx_insn
*place
= 0, *place2
= 0;
13621 next_note
= XEXP (note
, 1);
13622 switch (REG_NOTE_KIND (note
))
13626 /* Doesn't matter much where we put this, as long as it's somewhere.
13627 It is preferable to keep these notes on branches, which is most
13628 likely to be i3. */
13632 case REG_NON_LOCAL_GOTO
:
13637 gcc_assert (i2
&& JUMP_P (i2
));
13642 case REG_EH_REGION
:
13643 /* These notes must remain with the call or trapping instruction. */
13646 else if (i2
&& CALL_P (i2
))
13650 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13651 if (may_trap_p (i3
))
13653 else if (i2
&& may_trap_p (i2
))
13655 /* ??? Otherwise assume we've combined things such that we
13656 can now prove that the instructions can't trap. Drop the
13657 note in this case. */
13661 case REG_ARGS_SIZE
:
13662 /* ??? How to distribute between i3-i1. Assume i3 contains the
13663 entire adjustment. Assert i3 contains at least some adjust. */
13664 if (!noop_move_p (i3
))
13666 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
13667 /* fixup_args_size_notes looks at REG_NORETURN note,
13668 so ensure the note is placed there first. */
13672 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
13673 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
13677 XEXP (n
, 1) = REG_NOTES (i3
);
13678 REG_NOTES (i3
) = n
;
13682 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
13683 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13684 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13685 gcc_assert (old_size
!= args_size
13687 && !ACCUMULATE_OUTGOING_ARGS
13688 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
13695 case REG_CALL_DECL
:
13696 /* These notes must remain with the call. It should not be
13697 possible for both I2 and I3 to be a call. */
13702 gcc_assert (i2
&& CALL_P (i2
));
13708 /* Any clobbers for i3 may still exist, and so we must process
13709 REG_UNUSED notes from that insn.
13711 Any clobbers from i2 or i1 can only exist if they were added by
13712 recog_for_combine. In that case, recog_for_combine created the
13713 necessary REG_UNUSED notes. Trying to keep any original
13714 REG_UNUSED notes from these insns can cause incorrect output
13715 if it is for the same register as the original i3 dest.
13716 In that case, we will notice that the register is set in i3,
13717 and then add a REG_UNUSED note for the destination of i3, which
13718 is wrong. However, it is possible to have REG_UNUSED notes from
13719 i2 or i1 for register which were both used and clobbered, so
13720 we keep notes from i2 or i1 if they will turn into REG_DEAD
13723 /* If this register is set or clobbered in I3, put the note there
13724 unless there is one already. */
13725 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13727 if (from_insn
!= i3
)
13730 if (! (REG_P (XEXP (note
, 0))
13731 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13732 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13735 /* Otherwise, if this register is used by I3, then this register
13736 now dies here, so we must put a REG_DEAD note here unless there
13738 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13739 && ! (REG_P (XEXP (note
, 0))
13740 ? find_regno_note (i3
, REG_DEAD
,
13741 REGNO (XEXP (note
, 0)))
13742 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13744 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13752 /* These notes say something about results of an insn. We can
13753 only support them if they used to be on I3 in which case they
13754 remain on I3. Otherwise they are ignored.
13756 If the note refers to an expression that is not a constant, we
13757 must also ignore the note since we cannot tell whether the
13758 equivalence is still true. It might be possible to do
13759 slightly better than this (we only have a problem if I2DEST
13760 or I1DEST is present in the expression), but it doesn't
13761 seem worth the trouble. */
13763 if (from_insn
== i3
13764 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13769 /* These notes say something about how a register is used. They must
13770 be present on any use of the register in I2 or I3. */
13771 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13774 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13783 case REG_LABEL_TARGET
:
13784 case REG_LABEL_OPERAND
:
13785 /* This can show up in several ways -- either directly in the
13786 pattern, or hidden off in the constant pool with (or without?)
13787 a REG_EQUAL note. */
13788 /* ??? Ignore the without-reg_equal-note problem for now. */
13789 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13790 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13791 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13792 && LABEL_REF_LABEL (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
13796 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13797 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13798 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13799 && LABEL_REF_LABEL (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
13807 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13808 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13810 if (place
&& JUMP_P (place
)
13811 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13812 && (JUMP_LABEL (place
) == NULL
13813 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13815 rtx label
= JUMP_LABEL (place
);
13818 JUMP_LABEL (place
) = XEXP (note
, 0);
13819 else if (LABEL_P (label
))
13820 LABEL_NUSES (label
)--;
13823 if (place2
&& JUMP_P (place2
)
13824 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13825 && (JUMP_LABEL (place2
) == NULL
13826 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13828 rtx label
= JUMP_LABEL (place2
);
13831 JUMP_LABEL (place2
) = XEXP (note
, 0);
13832 else if (LABEL_P (label
))
13833 LABEL_NUSES (label
)--;
13839 /* This note says something about the value of a register prior
13840 to the execution of an insn. It is too much trouble to see
13841 if the note is still correct in all situations. It is better
13842 to simply delete it. */
13846 /* If we replaced the right hand side of FROM_INSN with a
13847 REG_EQUAL note, the original use of the dying register
13848 will not have been combined into I3 and I2. In such cases,
13849 FROM_INSN is guaranteed to be the first of the combined
13850 instructions, so we simply need to search back before
13851 FROM_INSN for the previous use or set of this register,
13852 then alter the notes there appropriately.
13854 If the register is used as an input in I3, it dies there.
13855 Similarly for I2, if it is nonzero and adjacent to I3.
13857 If the register is not used as an input in either I3 or I2
13858 and it is not one of the registers we were supposed to eliminate,
13859 there are two possibilities. We might have a non-adjacent I2
13860 or we might have somehow eliminated an additional register
13861 from a computation. For example, we might have had A & B where
13862 we discover that B will always be zero. In this case we will
13863 eliminate the reference to A.
13865 In both cases, we must search to see if we can find a previous
13866 use of A and put the death note there. */
13869 && from_insn
== i2mod
13870 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13871 tem_insn
= from_insn
;
13875 && CALL_P (from_insn
)
13876 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13878 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13880 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13881 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13883 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13885 && reg_overlap_mentioned_p (XEXP (note
, 0),
13887 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13888 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13891 /* If the new I2 sets the same register that is marked dead
13892 in the note, the note now should not be put on I2, as the
13893 note refers to a previous incarnation of the reg. */
13894 if (i2
!= 0 && reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
13900 basic_block bb
= this_basic_block
;
13902 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
13904 if (!NONDEBUG_INSN_P (tem_insn
))
13906 if (tem_insn
== BB_HEAD (bb
))
13911 /* If the register is being set at TEM_INSN, see if that is all
13912 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13913 into a REG_UNUSED note instead. Don't delete sets to
13914 global register vars. */
13915 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13916 || !global_regs
[REGNO (XEXP (note
, 0))])
13917 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
13919 rtx set
= single_set (tem_insn
);
13920 rtx inner_dest
= 0;
13921 rtx_insn
*cc0_setter
= NULL
;
13924 for (inner_dest
= SET_DEST (set
);
13925 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13926 || GET_CODE (inner_dest
) == SUBREG
13927 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13928 inner_dest
= XEXP (inner_dest
, 0))
13931 /* Verify that it was the set, and not a clobber that
13932 modified the register.
13934 CC0 targets must be careful to maintain setter/user
13935 pairs. If we cannot delete the setter due to side
13936 effects, mark the user with an UNUSED note instead
13939 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13940 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13942 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13943 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
13944 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13948 /* Move the notes and links of TEM_INSN elsewhere.
13949 This might delete other dead insns recursively.
13950 First set the pattern to something that won't use
13952 rtx old_notes
= REG_NOTES (tem_insn
);
13954 PATTERN (tem_insn
) = pc_rtx
;
13955 REG_NOTES (tem_insn
) = NULL
;
13957 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
13958 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13959 distribute_links (LOG_LINKS (tem_insn
));
13961 SET_INSN_DELETED (tem_insn
);
13962 if (tem_insn
== i2
)
13965 /* Delete the setter too. */
13968 PATTERN (cc0_setter
) = pc_rtx
;
13969 old_notes
= REG_NOTES (cc0_setter
);
13970 REG_NOTES (cc0_setter
) = NULL
;
13972 distribute_notes (old_notes
, cc0_setter
,
13974 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13975 distribute_links (LOG_LINKS (cc0_setter
));
13977 SET_INSN_DELETED (cc0_setter
);
13978 if (cc0_setter
== i2
)
13984 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13986 /* If there isn't already a REG_UNUSED note, put one
13987 here. Do not place a REG_DEAD note, even if
13988 the register is also used here; that would not
13989 match the algorithm used in lifetime analysis
13990 and can cause the consistency check in the
13991 scheduler to fail. */
13992 if (! find_regno_note (tem_insn
, REG_UNUSED
,
13993 REGNO (XEXP (note
, 0))))
13998 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
13999 || (CALL_P (tem_insn
)
14000 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
14004 /* If we are doing a 3->2 combination, and we have a
14005 register which formerly died in i3 and was not used
14006 by i2, which now no longer dies in i3 and is used in
14007 i2 but does not die in i2, and place is between i2
14008 and i3, then we may need to move a link from place to
14010 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
14012 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
14013 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14015 struct insn_link
*links
= LOG_LINKS (place
);
14016 LOG_LINKS (place
) = NULL
;
14017 distribute_links (links
);
14022 if (tem_insn
== BB_HEAD (bb
))
14028 /* If the register is set or already dead at PLACE, we needn't do
14029 anything with this note if it is still a REG_DEAD note.
14030 We check here if it is set at all, not if is it totally replaced,
14031 which is what `dead_or_set_p' checks, so also check for it being
14034 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
14036 unsigned int regno
= REGNO (XEXP (note
, 0));
14037 reg_stat_type
*rsp
= ®_stat
[regno
];
14039 if (dead_or_set_p (place
, XEXP (note
, 0))
14040 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
14042 /* Unless the register previously died in PLACE, clear
14043 last_death. [I no longer understand why this is
14045 if (rsp
->last_death
!= place
)
14046 rsp
->last_death
= 0;
14050 rsp
->last_death
= place
;
14052 /* If this is a death note for a hard reg that is occupying
14053 multiple registers, ensure that we are still using all
14054 parts of the object. If we find a piece of the object
14055 that is unused, we must arrange for an appropriate REG_DEAD
14056 note to be added for it. However, we can't just emit a USE
14057 and tag the note to it, since the register might actually
14058 be dead; so we recourse, and the recursive call then finds
14059 the previous insn that used this register. */
14061 if (place
&& REG_NREGS (XEXP (note
, 0)) > 1)
14063 unsigned int endregno
= END_REGNO (XEXP (note
, 0));
14064 bool all_used
= true;
14067 for (i
= regno
; i
< endregno
; i
++)
14068 if ((! refers_to_regno_p (i
, PATTERN (place
))
14069 && ! find_regno_fusage (place
, USE
, i
))
14070 || dead_or_set_regno_p (place
, i
))
14078 /* Put only REG_DEAD notes for pieces that are
14079 not already dead or set. */
14081 for (i
= regno
; i
< endregno
;
14082 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
14084 rtx piece
= regno_reg_rtx
[i
];
14085 basic_block bb
= this_basic_block
;
14087 if (! dead_or_set_p (place
, piece
)
14088 && ! reg_bitfield_target_p (piece
,
14091 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
14094 distribute_notes (new_note
, place
, place
,
14095 NULL
, NULL_RTX
, NULL_RTX
,
14098 else if (! refers_to_regno_p (i
, PATTERN (place
))
14099 && ! find_regno_fusage (place
, USE
, i
))
14100 for (tem_insn
= PREV_INSN (place
); ;
14101 tem_insn
= PREV_INSN (tem_insn
))
14103 if (!NONDEBUG_INSN_P (tem_insn
))
14105 if (tem_insn
== BB_HEAD (bb
))
14109 if (dead_or_set_p (tem_insn
, piece
)
14110 || reg_bitfield_target_p (piece
,
14111 PATTERN (tem_insn
)))
14113 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
14126 /* Any other notes should not be present at this point in the
14128 gcc_unreachable ();
14133 XEXP (note
, 1) = REG_NOTES (place
);
14134 REG_NOTES (place
) = note
;
14138 add_shallow_copy_of_reg_note (place2
, note
);
14142 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14143 I3, I2, and I1 to new locations. This is also called to add a link
14144 pointing at I3 when I3's destination is changed. */
14147 distribute_links (struct insn_link
*links
)
14149 struct insn_link
*link
, *next_link
;
14151 for (link
= links
; link
; link
= next_link
)
14153 rtx_insn
*place
= 0;
14157 next_link
= link
->next
;
14159 /* If the insn that this link points to is a NOTE, ignore it. */
14160 if (NOTE_P (link
->insn
))
14164 rtx pat
= PATTERN (link
->insn
);
14165 if (GET_CODE (pat
) == SET
)
14167 else if (GET_CODE (pat
) == PARALLEL
)
14170 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
14172 set
= XVECEXP (pat
, 0, i
);
14173 if (GET_CODE (set
) != SET
)
14176 reg
= SET_DEST (set
);
14177 while (GET_CODE (reg
) == ZERO_EXTRACT
14178 || GET_CODE (reg
) == STRICT_LOW_PART
14179 || GET_CODE (reg
) == SUBREG
)
14180 reg
= XEXP (reg
, 0);
14185 if (REGNO (reg
) == link
->regno
)
14188 if (i
== XVECLEN (pat
, 0))
14194 reg
= SET_DEST (set
);
14196 while (GET_CODE (reg
) == ZERO_EXTRACT
14197 || GET_CODE (reg
) == STRICT_LOW_PART
14198 || GET_CODE (reg
) == SUBREG
)
14199 reg
= XEXP (reg
, 0);
14201 /* A LOG_LINK is defined as being placed on the first insn that uses
14202 a register and points to the insn that sets the register. Start
14203 searching at the next insn after the target of the link and stop
14204 when we reach a set of the register or the end of the basic block.
14206 Note that this correctly handles the link that used to point from
14207 I3 to I2. Also note that not much searching is typically done here
14208 since most links don't point very far away. */
14210 for (insn
= NEXT_INSN (link
->insn
);
14211 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
14212 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
14213 insn
= NEXT_INSN (insn
))
14214 if (DEBUG_INSN_P (insn
))
14216 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
14218 if (reg_referenced_p (reg
, PATTERN (insn
)))
14222 else if (CALL_P (insn
)
14223 && find_reg_fusage (insn
, USE
, reg
))
14228 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
14231 /* If we found a place to put the link, place it there unless there
14232 is already a link to the same insn as LINK at that point. */
14236 struct insn_link
*link2
;
14238 FOR_EACH_LOG_LINK (link2
, place
)
14239 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
14244 link
->next
= LOG_LINKS (place
);
14245 LOG_LINKS (place
) = link
;
14247 /* Set added_links_insn to the earliest insn we added a
14249 if (added_links_insn
== 0
14250 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
14251 added_links_insn
= place
;
14257 /* Check for any register or memory mentioned in EQUIV that is not
14258 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14259 of EXPR where some registers may have been replaced by constants. */
14262 unmentioned_reg_p (rtx equiv
, rtx expr
)
14264 subrtx_iterator::array_type array
;
14265 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
14267 const_rtx x
= *iter
;
14268 if ((REG_P (x
) || MEM_P (x
))
14269 && !reg_mentioned_p (x
, expr
))
14275 DEBUG_FUNCTION
void
14276 dump_combine_stats (FILE *file
)
14280 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14281 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
14285 dump_combine_total_stats (FILE *file
)
14289 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14290 total_attempts
, total_merges
, total_extras
, total_successes
);
14293 /* Try combining insns through substitution. */
14294 static unsigned int
14295 rest_of_handle_combine (void)
14297 int rebuild_jump_labels_after_combine
;
14299 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
14300 df_note_add_problem ();
14303 regstat_init_n_sets_and_refs ();
14304 reg_n_sets_max
= max_reg_num ();
14306 rebuild_jump_labels_after_combine
14307 = combine_instructions (get_insns (), max_reg_num ());
14309 /* Combining insns may have turned an indirect jump into a
14310 direct jump. Rebuild the JUMP_LABEL fields of jumping
14312 if (rebuild_jump_labels_after_combine
)
14314 timevar_push (TV_JUMP
);
14315 rebuild_jump_labels (get_insns ());
14317 timevar_pop (TV_JUMP
);
14320 regstat_free_n_sets_and_refs ();
14326 const pass_data pass_data_combine
=
14328 RTL_PASS
, /* type */
14329 "combine", /* name */
14330 OPTGROUP_NONE
, /* optinfo_flags */
14331 TV_COMBINE
, /* tv_id */
14332 PROP_cfglayout
, /* properties_required */
14333 0, /* properties_provided */
14334 0, /* properties_destroyed */
14335 0, /* todo_flags_start */
14336 TODO_df_finish
, /* todo_flags_finish */
14339 class pass_combine
: public rtl_opt_pass
14342 pass_combine (gcc::context
*ctxt
)
14343 : rtl_opt_pass (pass_data_combine
, ctxt
)
14346 /* opt_pass methods: */
14347 virtual bool gate (function
*) { return (optimize
> 0); }
14348 virtual unsigned int execute (function
*)
14350 return rest_of_handle_combine ();
14353 }; // class pass_combine
14355 } // anon namespace
14358 make_pass_combine (gcc::context
*ctxt
)
14360 return new pass_combine (ctxt
);