1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by A. Lichnewsky, lich@inria.inria.fr.
7 Changes by Michael Meissner, meissner@osf.org.
8 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
9 Brendan Eich, brendan@microunity.com.
11 This file is part of GCC.
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GCC; see the file COPYING3. If not see
25 <http://www.gnu.org/licenses/>. */
29 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-attr.h"
52 #include "target-def.h"
53 #include "langhooks.h"
54 #include "sched-int.h"
57 #include "diagnostic.h"
58 #include "target-globals.h"
61 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75 /* The maximum distance between the top of the stack frame and the
76 value $sp has when we save and restore registers.
78 The value for normal-mode code must be a SMALL_OPERAND and must
79 preserve the maximum stack alignment. We therefore use a value
80 of 0x7ff0 in this case.
82 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
83 up to 0x7f8 bytes and can usually save or restore all the registers
84 that we need to save or restore. (Note that we can only use these
85 instructions for o32, for which the stack alignment is 8 bytes.)
87 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
88 RESTORE are not available. We can then use unextended instructions
89 to save and restore registers, and to allocate and deallocate the top
91 #define MIPS_MAX_FIRST_STACK_STEP \
92 (!TARGET_MIPS16 ? 0x7ff0 \
93 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
94 : TARGET_64BIT ? 0x100 : 0x400)
96 /* True if INSN is a mips.md pattern or asm statement. */
97 #define USEFUL_INSN_P(INSN) \
98 (NONDEBUG_INSN_P (INSN) \
99 && GET_CODE (PATTERN (INSN)) != USE \
100 && GET_CODE (PATTERN (INSN)) != CLOBBER \
101 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
102 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
104 /* If INSN is a delayed branch sequence, return the first instruction
105 in the sequence, otherwise return INSN itself. */
106 #define SEQ_BEGIN(INSN) \
107 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
108 ? XVECEXP (PATTERN (INSN), 0, 0) \
111 /* Likewise for the last instruction in a delayed branch sequence. */
112 #define SEQ_END(INSN) \
113 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
114 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
117 /* Execute the following loop body with SUBINSN set to each instruction
118 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
119 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
120 for ((SUBINSN) = SEQ_BEGIN (INSN); \
121 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
122 (SUBINSN) = NEXT_INSN (SUBINSN))
124 /* True if bit BIT is set in VALUE. */
125 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
127 /* Return the opcode for a ptr_mode load of the form:
129 l[wd] DEST, OFFSET(BASE). */
130 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
131 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
136 /* Return the opcode to move register SRC into register DEST. */
137 #define MIPS_MOVE(DEST, SRC) \
138 ((TARGET_64BIT ? 0x2d : 0x21) \
142 /* Return the opcode for:
145 #define MIPS_LUI(DEST, VALUE) \
146 ((0xf << 26) | ((DEST) << 16) | (VALUE))
148 /* Return the opcode to jump to register DEST. */
149 #define MIPS_JR(DEST) \
150 (((DEST) << 21) | 0x8)
152 /* Return the opcode for:
154 bal . + (1 + OFFSET) * 4. */
155 #define MIPS_BAL(OFFSET) \
156 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
158 /* Return the usual opcode for a nop. */
161 /* Classifies an address.
164 A natural register + offset address. The register satisfies
165 mips_valid_base_register_p and the offset is a const_arith_operand.
168 A LO_SUM rtx. The first operand is a valid base register and
169 the second operand is a symbolic address.
172 A signed 16-bit constant address.
175 A constant symbolic address. */
176 enum mips_address_type
{
183 /* Macros to create an enumeration identifier for a function prototype. */
184 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
185 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
186 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
187 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
189 /* Classifies the prototype of a built-in function. */
190 enum mips_function_type
{
191 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
192 #include "config/mips/mips-ftypes.def"
193 #undef DEF_MIPS_FTYPE
197 /* Specifies how a built-in function should be converted into rtl. */
198 enum mips_builtin_type
{
199 /* The function corresponds directly to an .md pattern. The return
200 value is mapped to operand 0 and the arguments are mapped to
201 operands 1 and above. */
204 /* The function corresponds directly to an .md pattern. There is no return
205 value and the arguments are mapped to operands 0 and above. */
206 MIPS_BUILTIN_DIRECT_NO_TARGET
,
208 /* The function corresponds to a comparison instruction followed by
209 a mips_cond_move_tf_ps pattern. The first two arguments are the
210 values to compare and the second two arguments are the vector
211 operands for the movt.ps or movf.ps instruction (in assembly order). */
215 /* The function corresponds to a V2SF comparison instruction. Operand 0
216 of this instruction is the result of the comparison, which has mode
217 CCV2 or CCV4. The function arguments are mapped to operands 1 and
218 above. The function's return value is an SImode boolean that is
219 true under the following conditions:
221 MIPS_BUILTIN_CMP_ANY: one of the registers is true
222 MIPS_BUILTIN_CMP_ALL: all of the registers are true
223 MIPS_BUILTIN_CMP_LOWER: the first register is true
224 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
225 MIPS_BUILTIN_CMP_ANY
,
226 MIPS_BUILTIN_CMP_ALL
,
227 MIPS_BUILTIN_CMP_UPPER
,
228 MIPS_BUILTIN_CMP_LOWER
,
230 /* As above, but the instruction only sets a single $fcc register. */
231 MIPS_BUILTIN_CMP_SINGLE
,
233 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
234 MIPS_BUILTIN_BPOSGE32
237 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
238 #define MIPS_FP_CONDITIONS(MACRO) \
256 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
257 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
258 enum mips_fp_condition
{
259 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
262 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
263 #define STRINGIFY(X) #X
264 static const char *const mips_fp_conditions
[] = {
265 MIPS_FP_CONDITIONS (STRINGIFY
)
268 /* Information about a function's frame layout. */
269 struct GTY(()) mips_frame_info
{
270 /* The size of the frame in bytes. */
271 HOST_WIDE_INT total_size
;
273 /* The number of bytes allocated to variables. */
274 HOST_WIDE_INT var_size
;
276 /* The number of bytes allocated to outgoing function arguments. */
277 HOST_WIDE_INT args_size
;
279 /* The number of bytes allocated to the .cprestore slot, or 0 if there
281 HOST_WIDE_INT cprestore_size
;
283 /* Bit X is set if the function saves or restores GPR X. */
286 /* Likewise FPR X. */
289 /* Likewise doubleword accumulator X ($acX). */
290 unsigned int acc_mask
;
292 /* The number of GPRs, FPRs, doubleword accumulators and COP0
296 unsigned int num_acc
;
297 unsigned int num_cop0_regs
;
299 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
300 save slots from the top of the frame, or zero if no such slots are
302 HOST_WIDE_INT gp_save_offset
;
303 HOST_WIDE_INT fp_save_offset
;
304 HOST_WIDE_INT acc_save_offset
;
305 HOST_WIDE_INT cop0_save_offset
;
307 /* Likewise, but giving offsets from the bottom of the frame. */
308 HOST_WIDE_INT gp_sp_offset
;
309 HOST_WIDE_INT fp_sp_offset
;
310 HOST_WIDE_INT acc_sp_offset
;
311 HOST_WIDE_INT cop0_sp_offset
;
313 /* Similar, but the value passed to _mcount. */
314 HOST_WIDE_INT ra_fp_offset
;
316 /* The offset of arg_pointer_rtx from the bottom of the frame. */
317 HOST_WIDE_INT arg_pointer_offset
;
319 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
320 HOST_WIDE_INT hard_frame_pointer_offset
;
323 struct GTY(()) machine_function
{
324 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
325 rtx mips16_gp_pseudo_rtx
;
327 /* The number of extra stack bytes taken up by register varargs.
328 This area is allocated by the callee at the very top of the frame. */
331 /* The current frame information, calculated by mips_compute_frame_info. */
332 struct mips_frame_info frame
;
334 /* The register to use as the function's global pointer, or INVALID_REGNUM
335 if the function doesn't need one. */
336 unsigned int global_pointer
;
338 /* How many instructions it takes to load a label into $AT, or 0 if
339 this property hasn't yet been calculated. */
340 unsigned int load_label_num_insns
;
342 /* True if mips_adjust_insn_length should ignore an instruction's
344 bool ignore_hazard_length_p
;
346 /* True if the whole function is suitable for .set noreorder and
348 bool all_noreorder_p
;
350 /* True if the function has "inflexible" and "flexible" references
351 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
352 and mips_cfun_has_flexible_gp_ref_p for details. */
353 bool has_inflexible_gp_insn_p
;
354 bool has_flexible_gp_insn_p
;
356 /* True if the function's prologue must load the global pointer
357 value into pic_offset_table_rtx and store the same value in
358 the function's cprestore slot (if any). Even if this value
359 is currently false, we may decide to set it to true later;
360 see mips_must_initialize_gp_p () for details. */
361 bool must_initialize_gp_p
;
363 /* True if the current function must restore $gp after any potential
364 clobber. This value is only meaningful during the first post-epilogue
365 split_insns pass; see mips_must_initialize_gp_p () for details. */
366 bool must_restore_gp_when_clobbered_p
;
368 /* True if this is an interrupt handler. */
369 bool interrupt_handler_p
;
371 /* True if this is an interrupt handler that uses shadow registers. */
372 bool use_shadow_register_set_p
;
374 /* True if this is an interrupt handler that should keep interrupts
376 bool keep_interrupts_masked_p
;
378 /* True if this is an interrupt handler that should use DERET
380 bool use_debug_exception_return_p
;
383 /* Information about a single argument. */
384 struct mips_arg_info
{
385 /* True if the argument is passed in a floating-point register, or
386 would have been if we hadn't run out of registers. */
389 /* The number of words passed in registers, rounded up. */
390 unsigned int reg_words
;
392 /* For EABI, the offset of the first register from GP_ARG_FIRST or
393 FP_ARG_FIRST. For other ABIs, the offset of the first register from
394 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
395 comment for details).
397 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
399 unsigned int reg_offset
;
401 /* The number of words that must be passed on the stack, rounded up. */
402 unsigned int stack_words
;
404 /* The offset from the start of the stack overflow area of the argument's
405 first stack word. Only meaningful when STACK_WORDS is nonzero. */
406 unsigned int stack_offset
;
409 /* Information about an address described by mips_address_type.
415 REG is the base register and OFFSET is the constant offset.
418 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
419 is the type of symbol it references.
422 SYMBOL_TYPE is the type of symbol that the address references. */
423 struct mips_address_info
{
424 enum mips_address_type type
;
427 enum mips_symbol_type symbol_type
;
430 /* One stage in a constant building sequence. These sequences have
434 A = A CODE[1] VALUE[1]
435 A = A CODE[2] VALUE[2]
438 where A is an accumulator, each CODE[i] is a binary rtl operation
439 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
440 struct mips_integer_op
{
442 unsigned HOST_WIDE_INT value
;
445 /* The largest number of operations needed to load an integer constant.
446 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
447 When the lowest bit is clear, we can try, but reject a sequence with
448 an extra SLL at the end. */
449 #define MIPS_MAX_INTEGER_OPS 7
451 /* Information about a MIPS16e SAVE or RESTORE instruction. */
452 struct mips16e_save_restore_info
{
453 /* The number of argument registers saved by a SAVE instruction.
454 0 for RESTORE instructions. */
457 /* Bit X is set if the instruction saves or restores GPR X. */
460 /* The total number of bytes to allocate. */
464 /* Costs of various operations on the different architectures. */
466 struct mips_rtx_cost_data
468 unsigned short fp_add
;
469 unsigned short fp_mult_sf
;
470 unsigned short fp_mult_df
;
471 unsigned short fp_div_sf
;
472 unsigned short fp_div_df
;
473 unsigned short int_mult_si
;
474 unsigned short int_mult_di
;
475 unsigned short int_div_si
;
476 unsigned short int_div_di
;
477 unsigned short branch_cost
;
478 unsigned short memory_latency
;
481 /* Global variables for machine-dependent things. */
483 /* The -G setting, or the configuration's default small-data limit if
484 no -G option is given. */
485 static unsigned int mips_small_data_threshold
;
487 /* The number of file directives written by mips_output_filename. */
488 int num_source_filenames
;
490 /* The name that appeared in the last .file directive written by
491 mips_output_filename, or "" if mips_output_filename hasn't
492 written anything yet. */
493 const char *current_function_file
= "";
495 /* Arrays that map GCC register numbers to debugger register numbers. */
496 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
497 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
499 /* Information about the current function's epilogue, used only while
502 /* A list of queued REG_CFA_RESTORE notes. */
505 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
507 HOST_WIDE_INT cfa_offset
;
509 /* The offset of the CFA from the stack pointer while restoring
511 HOST_WIDE_INT cfa_restore_sp_offset
;
514 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
515 struct mips_asm_switch mips_noreorder
= { "reorder", 0 };
516 struct mips_asm_switch mips_nomacro
= { "macro", 0 };
517 struct mips_asm_switch mips_noat
= { "at", 0 };
519 /* True if we're writing out a branch-likely instruction rather than a
521 static bool mips_branch_likely
;
523 /* The current instruction-set architecture. */
524 enum processor mips_arch
;
525 const struct mips_cpu_info
*mips_arch_info
;
527 /* The processor that we should tune the code for. */
528 enum processor mips_tune
;
529 const struct mips_cpu_info
*mips_tune_info
;
531 /* The ISA level associated with mips_arch. */
534 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
535 static const struct mips_cpu_info
*mips_isa_option_info
;
537 /* Which cost information to use. */
538 static const struct mips_rtx_cost_data
*mips_cost
;
540 /* The ambient target flags, excluding MASK_MIPS16. */
541 static int mips_base_target_flags
;
543 /* True if MIPS16 is the default mode. */
544 bool mips_base_mips16
;
546 /* The ambient values of other global variables. */
547 static int mips_base_schedule_insns
; /* flag_schedule_insns */
548 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
549 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
550 static int mips_base_align_loops
; /* align_loops */
551 static int mips_base_align_jumps
; /* align_jumps */
552 static int mips_base_align_functions
; /* align_functions */
554 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
555 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
557 /* Index C is true if character C is a valid PRINT_OPERAND punctation
559 static bool mips_print_operand_punct
[256];
561 static GTY (()) int mips_output_filename_first_time
= 1;
563 /* mips_split_p[X] is true if symbols of type X can be split by
564 mips_split_symbol. */
565 bool mips_split_p
[NUM_SYMBOL_TYPES
];
567 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
568 can be split by mips_split_symbol. */
569 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
571 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
572 forced into a PC-relative constant pool. */
573 bool mips_use_pcrel_pool_p
[NUM_SYMBOL_TYPES
];
575 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
576 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
577 if they are matched by a special .md file pattern. */
578 const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
580 /* Likewise for HIGHs. */
581 const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
583 /* Target state for MIPS16. */
584 struct target_globals
*mips16_globals
;
586 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
587 and returned from mips_sched_reorder2. */
588 static int cached_can_issue_more
;
590 /* True if the output uses __mips16_rdhwr. */
591 static bool mips_need_mips16_rdhwr_p
;
593 /* Index R is the smallest register class that contains register R. */
594 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
595 LEA_REGS
, LEA_REGS
, M16_REGS
, V1_REG
,
596 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
597 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
598 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
599 M16_REGS
, M16_REGS
, LEA_REGS
, LEA_REGS
,
600 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
601 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
602 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
603 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
604 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
605 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
606 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
607 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
608 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
609 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
610 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
611 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
612 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
613 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
614 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
615 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
616 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
617 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
618 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
619 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
620 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
621 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
622 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
623 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
624 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
625 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
626 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
627 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
628 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
629 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
630 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
631 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
632 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
633 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
634 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
635 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
636 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
637 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
638 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
639 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
640 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
641 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
644 /* The value of TARGET_ATTRIBUTE_TABLE. */
645 static const struct attribute_spec mips_attribute_table
[] = {
646 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
648 { "long_call", 0, 0, false, true, true, NULL
, false },
649 { "far", 0, 0, false, true, true, NULL
, false },
650 { "near", 0, 0, false, true, true, NULL
, false },
651 /* We would really like to treat "mips16" and "nomips16" as type
652 attributes, but GCC doesn't provide the hooks we need to support
653 the right conversion rules. As declaration attributes, they affect
654 code generation but don't carry other semantics. */
655 { "mips16", 0, 0, true, false, false, NULL
, false },
656 { "nomips16", 0, 0, true, false, false, NULL
, false },
657 /* Allow functions to be specified as interrupt handlers */
658 { "interrupt", 0, 0, false, true, true, NULL
, false },
659 { "use_shadow_register_set", 0, 0, false, true, true, NULL
, false },
660 { "keep_interrupts_masked", 0, 0, false, true, true, NULL
, false },
661 { "use_debug_exception_return", 0, 0, false, true, true, NULL
, false },
662 { NULL
, 0, 0, false, false, false, NULL
, false }
665 /* A table describing all the processors GCC knows about; see
666 mips-cpus.def for details. */
667 static const struct mips_cpu_info mips_cpu_info_table
[] = {
668 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
669 { NAME, CPU, ISA, FLAGS },
670 #include "mips-cpus.def"
674 /* Default costs. If these are used for a processor we should look
675 up the actual costs. */
676 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
677 COSTS_N_INSNS (7), /* fp_mult_sf */ \
678 COSTS_N_INSNS (8), /* fp_mult_df */ \
679 COSTS_N_INSNS (23), /* fp_div_sf */ \
680 COSTS_N_INSNS (36), /* fp_div_df */ \
681 COSTS_N_INSNS (10), /* int_mult_si */ \
682 COSTS_N_INSNS (10), /* int_mult_di */ \
683 COSTS_N_INSNS (69), /* int_div_si */ \
684 COSTS_N_INSNS (69), /* int_div_di */ \
685 2, /* branch_cost */ \
686 4 /* memory_latency */
688 /* Floating-point costs for processors without an FPU. Just assume that
689 all floating-point libcalls are very expensive. */
690 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
691 COSTS_N_INSNS (256), /* fp_mult_sf */ \
692 COSTS_N_INSNS (256), /* fp_mult_df */ \
693 COSTS_N_INSNS (256), /* fp_div_sf */ \
694 COSTS_N_INSNS (256) /* fp_div_df */
696 /* Costs to use when optimizing for size. */
697 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
698 COSTS_N_INSNS (1), /* fp_add */
699 COSTS_N_INSNS (1), /* fp_mult_sf */
700 COSTS_N_INSNS (1), /* fp_mult_df */
701 COSTS_N_INSNS (1), /* fp_div_sf */
702 COSTS_N_INSNS (1), /* fp_div_df */
703 COSTS_N_INSNS (1), /* int_mult_si */
704 COSTS_N_INSNS (1), /* int_mult_di */
705 COSTS_N_INSNS (1), /* int_div_si */
706 COSTS_N_INSNS (1), /* int_div_di */
708 4 /* memory_latency */
711 /* Costs to use when optimizing for speed, indexed by processor. */
712 static const struct mips_rtx_cost_data
713 mips_rtx_cost_data
[NUM_PROCESSOR_VALUES
] = {
715 COSTS_N_INSNS (2), /* fp_add */
716 COSTS_N_INSNS (4), /* fp_mult_sf */
717 COSTS_N_INSNS (5), /* fp_mult_df */
718 COSTS_N_INSNS (12), /* fp_div_sf */
719 COSTS_N_INSNS (19), /* fp_div_df */
720 COSTS_N_INSNS (12), /* int_mult_si */
721 COSTS_N_INSNS (12), /* int_mult_di */
722 COSTS_N_INSNS (35), /* int_div_si */
723 COSTS_N_INSNS (35), /* int_div_di */
725 4 /* memory_latency */
729 COSTS_N_INSNS (6), /* int_mult_si */
730 COSTS_N_INSNS (6), /* int_mult_di */
731 COSTS_N_INSNS (36), /* int_div_si */
732 COSTS_N_INSNS (36), /* int_div_di */
734 4 /* memory_latency */
738 COSTS_N_INSNS (36), /* int_mult_si */
739 COSTS_N_INSNS (36), /* int_mult_di */
740 COSTS_N_INSNS (37), /* int_div_si */
741 COSTS_N_INSNS (37), /* int_div_di */
743 4 /* memory_latency */
747 COSTS_N_INSNS (4), /* int_mult_si */
748 COSTS_N_INSNS (11), /* int_mult_di */
749 COSTS_N_INSNS (36), /* int_div_si */
750 COSTS_N_INSNS (68), /* int_div_di */
752 4 /* memory_latency */
755 COSTS_N_INSNS (4), /* fp_add */
756 COSTS_N_INSNS (4), /* fp_mult_sf */
757 COSTS_N_INSNS (5), /* fp_mult_df */
758 COSTS_N_INSNS (17), /* fp_div_sf */
759 COSTS_N_INSNS (32), /* fp_div_df */
760 COSTS_N_INSNS (4), /* int_mult_si */
761 COSTS_N_INSNS (11), /* int_mult_di */
762 COSTS_N_INSNS (36), /* int_div_si */
763 COSTS_N_INSNS (68), /* int_div_di */
765 4 /* memory_latency */
768 COSTS_N_INSNS (4), /* fp_add */
769 COSTS_N_INSNS (4), /* fp_mult_sf */
770 COSTS_N_INSNS (5), /* fp_mult_df */
771 COSTS_N_INSNS (17), /* fp_div_sf */
772 COSTS_N_INSNS (32), /* fp_div_df */
773 COSTS_N_INSNS (4), /* int_mult_si */
774 COSTS_N_INSNS (7), /* int_mult_di */
775 COSTS_N_INSNS (42), /* int_div_si */
776 COSTS_N_INSNS (72), /* int_div_di */
778 4 /* memory_latency */
782 COSTS_N_INSNS (5), /* int_mult_si */
783 COSTS_N_INSNS (5), /* int_mult_di */
784 COSTS_N_INSNS (41), /* int_div_si */
785 COSTS_N_INSNS (41), /* int_div_di */
787 4 /* memory_latency */
790 COSTS_N_INSNS (8), /* fp_add */
791 COSTS_N_INSNS (8), /* fp_mult_sf */
792 COSTS_N_INSNS (10), /* fp_mult_df */
793 COSTS_N_INSNS (34), /* fp_div_sf */
794 COSTS_N_INSNS (64), /* fp_div_df */
795 COSTS_N_INSNS (5), /* int_mult_si */
796 COSTS_N_INSNS (5), /* int_mult_di */
797 COSTS_N_INSNS (41), /* int_div_si */
798 COSTS_N_INSNS (41), /* int_div_di */
800 4 /* memory_latency */
803 COSTS_N_INSNS (4), /* fp_add */
804 COSTS_N_INSNS (4), /* fp_mult_sf */
805 COSTS_N_INSNS (5), /* fp_mult_df */
806 COSTS_N_INSNS (17), /* fp_div_sf */
807 COSTS_N_INSNS (32), /* fp_div_df */
808 COSTS_N_INSNS (5), /* int_mult_si */
809 COSTS_N_INSNS (5), /* int_mult_di */
810 COSTS_N_INSNS (41), /* int_div_si */
811 COSTS_N_INSNS (41), /* int_div_di */
813 4 /* memory_latency */
817 COSTS_N_INSNS (5), /* int_mult_si */
818 COSTS_N_INSNS (5), /* int_mult_di */
819 COSTS_N_INSNS (41), /* int_div_si */
820 COSTS_N_INSNS (41), /* int_div_di */
822 4 /* memory_latency */
825 COSTS_N_INSNS (8), /* fp_add */
826 COSTS_N_INSNS (8), /* fp_mult_sf */
827 COSTS_N_INSNS (10), /* fp_mult_df */
828 COSTS_N_INSNS (34), /* fp_div_sf */
829 COSTS_N_INSNS (64), /* fp_div_df */
830 COSTS_N_INSNS (5), /* int_mult_si */
831 COSTS_N_INSNS (5), /* int_mult_di */
832 COSTS_N_INSNS (41), /* int_div_si */
833 COSTS_N_INSNS (41), /* int_div_di */
835 4 /* memory_latency */
838 COSTS_N_INSNS (4), /* fp_add */
839 COSTS_N_INSNS (4), /* fp_mult_sf */
840 COSTS_N_INSNS (5), /* fp_mult_df */
841 COSTS_N_INSNS (17), /* fp_div_sf */
842 COSTS_N_INSNS (32), /* fp_div_df */
843 COSTS_N_INSNS (5), /* int_mult_si */
844 COSTS_N_INSNS (5), /* int_mult_di */
845 COSTS_N_INSNS (41), /* int_div_si */
846 COSTS_N_INSNS (41), /* int_div_di */
848 4 /* memory_latency */
851 COSTS_N_INSNS (6), /* fp_add */
852 COSTS_N_INSNS (6), /* fp_mult_sf */
853 COSTS_N_INSNS (7), /* fp_mult_df */
854 COSTS_N_INSNS (25), /* fp_div_sf */
855 COSTS_N_INSNS (48), /* fp_div_df */
856 COSTS_N_INSNS (5), /* int_mult_si */
857 COSTS_N_INSNS (5), /* int_mult_di */
858 COSTS_N_INSNS (41), /* int_div_si */
859 COSTS_N_INSNS (41), /* int_div_di */
861 4 /* memory_latency */
878 COSTS_N_INSNS (5), /* int_mult_si */
879 COSTS_N_INSNS (5), /* int_mult_di */
880 COSTS_N_INSNS (72), /* int_div_si */
881 COSTS_N_INSNS (72), /* int_div_di */
883 4 /* memory_latency */
888 COSTS_N_INSNS (6), /* int_mult_si */
889 COSTS_N_INSNS (6), /* int_mult_di */
890 COSTS_N_INSNS (18), /* int_div_si */
891 COSTS_N_INSNS (35), /* int_div_di */
893 4 /* memory_latency */
896 COSTS_N_INSNS (2), /* fp_add */
897 COSTS_N_INSNS (4), /* fp_mult_sf */
898 COSTS_N_INSNS (5), /* fp_mult_df */
899 COSTS_N_INSNS (12), /* fp_div_sf */
900 COSTS_N_INSNS (19), /* fp_div_df */
901 COSTS_N_INSNS (2), /* int_mult_si */
902 COSTS_N_INSNS (2), /* int_mult_di */
903 COSTS_N_INSNS (35), /* int_div_si */
904 COSTS_N_INSNS (35), /* int_div_di */
906 4 /* memory_latency */
909 COSTS_N_INSNS (3), /* fp_add */
910 COSTS_N_INSNS (5), /* fp_mult_sf */
911 COSTS_N_INSNS (6), /* fp_mult_df */
912 COSTS_N_INSNS (15), /* fp_div_sf */
913 COSTS_N_INSNS (16), /* fp_div_df */
914 COSTS_N_INSNS (17), /* int_mult_si */
915 COSTS_N_INSNS (17), /* int_mult_di */
916 COSTS_N_INSNS (38), /* int_div_si */
917 COSTS_N_INSNS (38), /* int_div_di */
919 6 /* memory_latency */
922 COSTS_N_INSNS (6), /* fp_add */
923 COSTS_N_INSNS (7), /* fp_mult_sf */
924 COSTS_N_INSNS (8), /* fp_mult_df */
925 COSTS_N_INSNS (23), /* fp_div_sf */
926 COSTS_N_INSNS (36), /* fp_div_df */
927 COSTS_N_INSNS (10), /* int_mult_si */
928 COSTS_N_INSNS (10), /* int_mult_di */
929 COSTS_N_INSNS (69), /* int_div_si */
930 COSTS_N_INSNS (69), /* int_div_di */
932 6 /* memory_latency */
944 /* The only costs that appear to be updated here are
945 integer multiplication. */
947 COSTS_N_INSNS (4), /* int_mult_si */
948 COSTS_N_INSNS (6), /* int_mult_di */
949 COSTS_N_INSNS (69), /* int_div_si */
950 COSTS_N_INSNS (69), /* int_div_di */
952 4 /* memory_latency */
967 COSTS_N_INSNS (6), /* fp_add */
968 COSTS_N_INSNS (4), /* fp_mult_sf */
969 COSTS_N_INSNS (5), /* fp_mult_df */
970 COSTS_N_INSNS (23), /* fp_div_sf */
971 COSTS_N_INSNS (36), /* fp_div_df */
972 COSTS_N_INSNS (5), /* int_mult_si */
973 COSTS_N_INSNS (5), /* int_mult_di */
974 COSTS_N_INSNS (36), /* int_div_si */
975 COSTS_N_INSNS (36), /* int_div_di */
977 4 /* memory_latency */
980 COSTS_N_INSNS (6), /* fp_add */
981 COSTS_N_INSNS (5), /* fp_mult_sf */
982 COSTS_N_INSNS (6), /* fp_mult_df */
983 COSTS_N_INSNS (30), /* fp_div_sf */
984 COSTS_N_INSNS (59), /* fp_div_df */
985 COSTS_N_INSNS (3), /* int_mult_si */
986 COSTS_N_INSNS (4), /* int_mult_di */
987 COSTS_N_INSNS (42), /* int_div_si */
988 COSTS_N_INSNS (74), /* int_div_di */
990 4 /* memory_latency */
993 COSTS_N_INSNS (6), /* fp_add */
994 COSTS_N_INSNS (5), /* fp_mult_sf */
995 COSTS_N_INSNS (6), /* fp_mult_df */
996 COSTS_N_INSNS (30), /* fp_div_sf */
997 COSTS_N_INSNS (59), /* fp_div_df */
998 COSTS_N_INSNS (5), /* int_mult_si */
999 COSTS_N_INSNS (9), /* int_mult_di */
1000 COSTS_N_INSNS (42), /* int_div_si */
1001 COSTS_N_INSNS (74), /* int_div_di */
1002 1, /* branch_cost */
1003 4 /* memory_latency */
1006 /* The only costs that are changed here are
1007 integer multiplication. */
1008 COSTS_N_INSNS (6), /* fp_add */
1009 COSTS_N_INSNS (7), /* fp_mult_sf */
1010 COSTS_N_INSNS (8), /* fp_mult_df */
1011 COSTS_N_INSNS (23), /* fp_div_sf */
1012 COSTS_N_INSNS (36), /* fp_div_df */
1013 COSTS_N_INSNS (5), /* int_mult_si */
1014 COSTS_N_INSNS (9), /* int_mult_di */
1015 COSTS_N_INSNS (69), /* int_div_si */
1016 COSTS_N_INSNS (69), /* int_div_di */
1017 1, /* branch_cost */
1018 4 /* memory_latency */
1024 /* The only costs that are changed here are
1025 integer multiplication. */
1026 COSTS_N_INSNS (6), /* fp_add */
1027 COSTS_N_INSNS (7), /* fp_mult_sf */
1028 COSTS_N_INSNS (8), /* fp_mult_df */
1029 COSTS_N_INSNS (23), /* fp_div_sf */
1030 COSTS_N_INSNS (36), /* fp_div_df */
1031 COSTS_N_INSNS (3), /* int_mult_si */
1032 COSTS_N_INSNS (8), /* int_mult_di */
1033 COSTS_N_INSNS (69), /* int_div_si */
1034 COSTS_N_INSNS (69), /* int_div_di */
1035 1, /* branch_cost */
1036 4 /* memory_latency */
1039 COSTS_N_INSNS (2), /* fp_add */
1040 COSTS_N_INSNS (2), /* fp_mult_sf */
1041 COSTS_N_INSNS (2), /* fp_mult_df */
1042 COSTS_N_INSNS (12), /* fp_div_sf */
1043 COSTS_N_INSNS (19), /* fp_div_df */
1044 COSTS_N_INSNS (5), /* int_mult_si */
1045 COSTS_N_INSNS (9), /* int_mult_di */
1046 COSTS_N_INSNS (34), /* int_div_si */
1047 COSTS_N_INSNS (66), /* int_div_di */
1048 1, /* branch_cost */
1049 4 /* memory_latency */
1052 /* These costs are the same as the SB-1A below. */
1053 COSTS_N_INSNS (4), /* fp_add */
1054 COSTS_N_INSNS (4), /* fp_mult_sf */
1055 COSTS_N_INSNS (4), /* fp_mult_df */
1056 COSTS_N_INSNS (24), /* fp_div_sf */
1057 COSTS_N_INSNS (32), /* fp_div_df */
1058 COSTS_N_INSNS (3), /* int_mult_si */
1059 COSTS_N_INSNS (4), /* int_mult_di */
1060 COSTS_N_INSNS (36), /* int_div_si */
1061 COSTS_N_INSNS (68), /* int_div_di */
1062 1, /* branch_cost */
1063 4 /* memory_latency */
1066 /* These costs are the same as the SB-1 above. */
1067 COSTS_N_INSNS (4), /* fp_add */
1068 COSTS_N_INSNS (4), /* fp_mult_sf */
1069 COSTS_N_INSNS (4), /* fp_mult_df */
1070 COSTS_N_INSNS (24), /* fp_div_sf */
1071 COSTS_N_INSNS (32), /* fp_div_df */
1072 COSTS_N_INSNS (3), /* int_mult_si */
1073 COSTS_N_INSNS (4), /* int_mult_di */
1074 COSTS_N_INSNS (36), /* int_div_si */
1075 COSTS_N_INSNS (68), /* int_div_di */
1076 1, /* branch_cost */
1077 4 /* memory_latency */
1084 COSTS_N_INSNS (8), /* int_mult_si */
1085 COSTS_N_INSNS (8), /* int_mult_di */
1086 COSTS_N_INSNS (72), /* int_div_si */
1087 COSTS_N_INSNS (72), /* int_div_di */
1088 1, /* branch_cost */
1089 4 /* memory_latency */
1092 /* These costs are the same as 5KF above. */
1093 COSTS_N_INSNS (4), /* fp_add */
1094 COSTS_N_INSNS (4), /* fp_mult_sf */
1095 COSTS_N_INSNS (5), /* fp_mult_df */
1096 COSTS_N_INSNS (17), /* fp_div_sf */
1097 COSTS_N_INSNS (32), /* fp_div_df */
1098 COSTS_N_INSNS (4), /* int_mult_si */
1099 COSTS_N_INSNS (11), /* int_mult_di */
1100 COSTS_N_INSNS (36), /* int_div_si */
1101 COSTS_N_INSNS (68), /* int_div_di */
1102 1, /* branch_cost */
1103 4 /* memory_latency */
1107 static rtx
mips_find_pic_call_symbol (rtx
, rtx
, bool);
1108 static int mips_register_move_cost (enum machine_mode
, reg_class_t
,
1110 static unsigned int mips_function_arg_boundary (enum machine_mode
, const_tree
);
1112 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1113 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1114 struct GTY (()) mflip_mips16_entry
{
1118 static GTY ((param_is (struct mflip_mips16_entry
))) htab_t mflip_mips16_htab
;
1120 /* Hash table callbacks for mflip_mips16_htab. */
1123 mflip_mips16_htab_hash (const void *entry
)
1125 return htab_hash_string (((const struct mflip_mips16_entry
*) entry
)->name
);
1129 mflip_mips16_htab_eq (const void *entry
, const void *name
)
1131 return strcmp (((const struct mflip_mips16_entry
*) entry
)->name
,
1132 (const char *) name
) == 0;
1135 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1136 mode, false if it should next add an attribute for the opposite mode. */
1137 static GTY(()) bool mips16_flipper
;
1139 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1140 for -mflip-mips16. Return true if it should use "mips16" and false if
1141 it should use "nomips16". */
1144 mflip_mips16_use_mips16_p (tree decl
)
1146 struct mflip_mips16_entry
*entry
;
1151 /* Use the opposite of the command-line setting for anonymous decls. */
1152 if (!DECL_NAME (decl
))
1153 return !mips_base_mips16
;
1155 if (!mflip_mips16_htab
)
1156 mflip_mips16_htab
= htab_create_ggc (37, mflip_mips16_htab_hash
,
1157 mflip_mips16_htab_eq
, NULL
);
1159 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1160 hash
= htab_hash_string (name
);
1161 slot
= htab_find_slot_with_hash (mflip_mips16_htab
, name
, hash
, INSERT
);
1162 entry
= (struct mflip_mips16_entry
*) *slot
;
1165 mips16_flipper
= !mips16_flipper
;
1166 entry
= ggc_alloc_mflip_mips16_entry ();
1168 entry
->mips16_p
= mips16_flipper
? !mips_base_mips16
: mips_base_mips16
;
1171 return entry
->mips16_p
;
1174 /* Predicates to test for presence of "near" and "far"/"long_call"
1175 attributes on the given TYPE. */
1178 mips_near_type_p (const_tree type
)
1180 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1184 mips_far_type_p (const_tree type
)
1186 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1187 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1190 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1193 mips_mips16_decl_p (const_tree decl
)
1195 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl
)) != NULL
;
1199 mips_nomips16_decl_p (const_tree decl
)
1201 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl
)) != NULL
;
1204 /* Check if the interrupt attribute is set for a function. */
1207 mips_interrupt_type_p (tree type
)
1209 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1212 /* Check if the attribute to use shadow register set is set for a function. */
1215 mips_use_shadow_register_set_p (tree type
)
1217 return lookup_attribute ("use_shadow_register_set",
1218 TYPE_ATTRIBUTES (type
)) != NULL
;
1221 /* Check if the attribute to keep interrupts masked is set for a function. */
1224 mips_keep_interrupts_masked_p (tree type
)
1226 return lookup_attribute ("keep_interrupts_masked",
1227 TYPE_ATTRIBUTES (type
)) != NULL
;
1230 /* Check if the attribute to use debug exception return is set for
1234 mips_use_debug_exception_return_p (tree type
)
1236 return lookup_attribute ("use_debug_exception_return",
1237 TYPE_ATTRIBUTES (type
)) != NULL
;
1240 /* Return true if function DECL is a MIPS16 function. Return the ambient
1241 setting if DECL is null. */
1244 mips_use_mips16_mode_p (tree decl
)
1248 /* Nested functions must use the same frame pointer as their
1249 parent and must therefore use the same ISA mode. */
1250 tree parent
= decl_function_context (decl
);
1253 if (mips_mips16_decl_p (decl
))
1255 if (mips_nomips16_decl_p (decl
))
1258 return mips_base_mips16
;
1261 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1264 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1266 /* Disallow mixed near/far attributes. */
1267 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1269 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1274 /* Implement TARGET_INSERT_ATTRIBUTES. */
1277 mips_insert_attributes (tree decl
, tree
*attributes
)
1280 bool mips16_p
, nomips16_p
;
1282 /* Check for "mips16" and "nomips16" attributes. */
1283 mips16_p
= lookup_attribute ("mips16", *attributes
) != NULL
;
1284 nomips16_p
= lookup_attribute ("nomips16", *attributes
) != NULL
;
1285 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1288 error ("%qs attribute only applies to functions", "mips16");
1290 error ("%qs attribute only applies to functions", "nomips16");
1294 mips16_p
|= mips_mips16_decl_p (decl
);
1295 nomips16_p
|= mips_nomips16_decl_p (decl
);
1296 if (mips16_p
|| nomips16_p
)
1298 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1299 if (mips16_p
&& nomips16_p
)
1300 error ("%qE cannot have both %<mips16%> and "
1301 "%<nomips16%> attributes",
1304 else if (TARGET_FLIP_MIPS16
&& !DECL_ARTIFICIAL (decl
))
1306 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1307 "mips16" attribute, arbitrarily pick one. We must pick the same
1308 setting for duplicate declarations of a function. */
1309 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1310 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1315 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1318 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1320 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1321 if (mips_mips16_decl_p (olddecl
) != mips_mips16_decl_p (newdecl
))
1322 error ("%qE redeclared with conflicting %qs attributes",
1323 DECL_NAME (newdecl
), "mips16");
1324 if (mips_nomips16_decl_p (olddecl
) != mips_nomips16_decl_p (newdecl
))
1325 error ("%qE redeclared with conflicting %qs attributes",
1326 DECL_NAME (newdecl
), "nomips16");
1328 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1329 DECL_ATTRIBUTES (newdecl
));
1332 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1333 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1336 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1338 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
1340 *base_ptr
= XEXP (x
, 0);
1341 *offset_ptr
= INTVAL (XEXP (x
, 1));
1350 static unsigned int mips_build_integer (struct mips_integer_op
*,
1351 unsigned HOST_WIDE_INT
);
1353 /* A subroutine of mips_build_integer, with the same interface.
1354 Assume that the final action in the sequence should be a left shift. */
1357 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1359 unsigned int i
, shift
;
1361 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1362 since signed numbers are easier to load than unsigned ones. */
1364 while ((value
& 1) == 0)
1365 value
/= 2, shift
++;
1367 i
= mips_build_integer (codes
, value
);
1368 codes
[i
].code
= ASHIFT
;
1369 codes
[i
].value
= shift
;
1373 /* As for mips_build_shift, but assume that the final action will be
1374 an IOR or PLUS operation. */
1377 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1379 unsigned HOST_WIDE_INT high
;
1382 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1383 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1385 /* The constant is too complex to load with a simple LUI/ORI pair,
1386 so we want to give the recursive call as many trailing zeros as
1387 possible. In this case, we know bit 16 is set and that the
1388 low 16 bits form a negative number. If we subtract that number
1389 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1390 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1391 codes
[i
].code
= PLUS
;
1392 codes
[i
].value
= CONST_LOW_PART (value
);
1396 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1397 bits gives a value with at least 17 trailing zeros. */
1398 i
= mips_build_integer (codes
, high
);
1399 codes
[i
].code
= IOR
;
1400 codes
[i
].value
= value
& 0xffff;
1405 /* Fill CODES with a sequence of rtl operations to load VALUE.
1406 Return the number of operations needed. */
1409 mips_build_integer (struct mips_integer_op
*codes
,
1410 unsigned HOST_WIDE_INT value
)
1412 if (SMALL_OPERAND (value
)
1413 || SMALL_OPERAND_UNSIGNED (value
)
1414 || LUI_OPERAND (value
))
1416 /* The value can be loaded with a single instruction. */
1417 codes
[0].code
= UNKNOWN
;
1418 codes
[0].value
= value
;
1421 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1423 /* Either the constant is a simple LUI/ORI combination or its
1424 lowest bit is set. We don't want to shift in this case. */
1425 return mips_build_lower (codes
, value
);
1427 else if ((value
& 0xffff) == 0)
1429 /* The constant will need at least three actions. The lowest
1430 16 bits are clear, so the final action will be a shift. */
1431 return mips_build_shift (codes
, value
);
1435 /* The final action could be a shift, add or inclusive OR.
1436 Rather than use a complex condition to select the best
1437 approach, try both mips_build_shift and mips_build_lower
1438 and pick the one that gives the shortest sequence.
1439 Note that this case is only used once per constant. */
1440 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1441 unsigned int cost
, alt_cost
;
1443 cost
= mips_build_shift (codes
, value
);
1444 alt_cost
= mips_build_lower (alt_codes
, value
);
1445 if (alt_cost
< cost
)
1447 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1454 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1457 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1459 return mips_const_insns (x
) > 0;
1462 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1465 mips16_stub_function (const char *name
)
1469 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
1470 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
1474 /* Return true if symbols of type TYPE require a GOT access. */
1477 mips_got_symbol_type_p (enum mips_symbol_type type
)
1481 case SYMBOL_GOT_PAGE_OFST
:
1482 case SYMBOL_GOT_DISP
:
1490 /* Return true if X is a thread-local symbol. */
1493 mips_tls_symbol_p (rtx x
)
1495 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1498 /* Return true if SYMBOL_REF X is associated with a global symbol
1499 (in the STB_GLOBAL sense). */
1502 mips_global_symbol_p (const_rtx x
)
1504 const_tree decl
= SYMBOL_REF_DECL (x
);
1507 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1509 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1510 or weak symbols. Relocations in the object file will be against
1511 the target symbol, so it's that symbol's binding that matters here. */
1512 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1515 /* Return true if function X is a libgcc MIPS16 stub function. */
1518 mips16_stub_function_p (const_rtx x
)
1520 return (GET_CODE (x
) == SYMBOL_REF
1521 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1524 /* Return true if function X is a locally-defined and locally-binding
1528 mips16_local_function_p (const_rtx x
)
1530 return (GET_CODE (x
) == SYMBOL_REF
1531 && SYMBOL_REF_LOCAL_P (x
)
1532 && !SYMBOL_REF_EXTERNAL_P (x
)
1533 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x
)));
1536 /* Return true if SYMBOL_REF X binds locally. */
1539 mips_symbol_binds_local_p (const_rtx x
)
1541 return (SYMBOL_REF_DECL (x
)
1542 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1543 : SYMBOL_REF_LOCAL_P (x
));
1546 /* Return true if rtx constants of mode MODE should be put into a small
1550 mips_rtx_constant_in_small_data_p (enum machine_mode mode
)
1552 return (!TARGET_EMBEDDED_DATA
1553 && TARGET_LOCAL_SDATA
1554 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1557 /* Return true if X should not be moved directly into register $25.
1558 We need this because many versions of GAS will treat "la $25,foo" as
1559 part of a call sequence and so allow a global "foo" to be lazily bound. */
1562 mips_dangerous_for_la25_p (rtx x
)
1564 return (!TARGET_EXPLICIT_RELOCS
1566 && GET_CODE (x
) == SYMBOL_REF
1567 && mips_global_symbol_p (x
));
1570 /* Return true if calls to X might need $25 to be valid on entry. */
1573 mips_use_pic_fn_addr_reg_p (const_rtx x
)
1575 if (!TARGET_USE_PIC_FN_ADDR_REG
)
1578 /* MIPS16 stub functions are guaranteed not to use $25. */
1579 if (mips16_stub_function_p (x
))
1582 if (GET_CODE (x
) == SYMBOL_REF
)
1584 /* If PLTs and copy relocations are available, the static linker
1585 will make sure that $25 is valid on entry to the target function. */
1586 if (TARGET_ABICALLS_PIC0
)
1589 /* Locally-defined functions use absolute accesses to set up
1590 the global pointer. */
1591 if (TARGET_ABSOLUTE_ABICALLS
1592 && mips_symbol_binds_local_p (x
)
1593 && !SYMBOL_REF_EXTERNAL_P (x
))
1600 /* Return the method that should be used to access SYMBOL_REF or
1601 LABEL_REF X in context CONTEXT. */
1603 static enum mips_symbol_type
1604 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1607 return SYMBOL_GOT_DISP
;
1609 if (GET_CODE (x
) == LABEL_REF
)
1611 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1612 code and if we know that the label is in the current function's
1613 text section. LABEL_REFs are used for jump tables as well as
1614 text labels, so we must check whether jump tables live in the
1616 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1617 && !LABEL_REF_NONLOCAL_P (x
))
1618 return SYMBOL_PC_RELATIVE
;
1620 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1621 return SYMBOL_GOT_PAGE_OFST
;
1623 return SYMBOL_ABSOLUTE
;
1626 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1628 if (SYMBOL_REF_TLS_MODEL (x
))
1631 if (CONSTANT_POOL_ADDRESS_P (x
))
1633 if (TARGET_MIPS16_TEXT_LOADS
)
1634 return SYMBOL_PC_RELATIVE
;
1636 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1637 return SYMBOL_PC_RELATIVE
;
1639 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1640 return SYMBOL_GP_RELATIVE
;
1643 /* Do not use small-data accesses for weak symbols; they may end up
1645 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
1646 return SYMBOL_GP_RELATIVE
;
1648 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1650 if (TARGET_ABICALLS_PIC2
1651 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1653 /* There are three cases to consider:
1655 - o32 PIC (either with or without explicit relocs)
1656 - n32/n64 PIC without explicit relocs
1657 - n32/n64 PIC with explicit relocs
1659 In the first case, both local and global accesses will use an
1660 R_MIPS_GOT16 relocation. We must correctly predict which of
1661 the two semantics (local or global) the assembler and linker
1662 will apply. The choice depends on the symbol's binding rather
1663 than its visibility.
1665 In the second case, the assembler will not use R_MIPS_GOT16
1666 relocations, but it chooses between local and global accesses
1667 in the same way as for o32 PIC.
1669 In the third case we have more freedom since both forms of
1670 access will work for any kind of symbol. However, there seems
1671 little point in doing things differently. */
1672 if (mips_global_symbol_p (x
))
1673 return SYMBOL_GOT_DISP
;
1675 return SYMBOL_GOT_PAGE_OFST
;
1678 return SYMBOL_ABSOLUTE
;
1681 /* Classify the base of symbolic expression X, given that X appears in
1684 static enum mips_symbol_type
1685 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
1689 split_const (x
, &x
, &offset
);
1690 if (UNSPEC_ADDRESS_P (x
))
1691 return UNSPEC_ADDRESS_TYPE (x
);
1693 return mips_classify_symbol (x
, context
);
1696 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1697 is the alignment in bytes of SYMBOL_REF X. */
1700 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
1702 HOST_WIDE_INT align
;
1704 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
1705 return IN_RANGE (offset
, 0, align
- 1);
1708 /* Return true if X is a symbolic constant that can be used in context
1709 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1712 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
1713 enum mips_symbol_type
*symbol_type
)
1717 split_const (x
, &x
, &offset
);
1718 if (UNSPEC_ADDRESS_P (x
))
1720 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
1721 x
= UNSPEC_ADDRESS (x
);
1723 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1725 *symbol_type
= mips_classify_symbol (x
, context
);
1726 if (*symbol_type
== SYMBOL_TLS
)
1732 if (offset
== const0_rtx
)
1735 /* Check whether a nonzero offset is valid for the underlying
1737 switch (*symbol_type
)
1739 case SYMBOL_ABSOLUTE
:
1740 case SYMBOL_64_HIGH
:
1743 /* If the target has 64-bit pointers and the object file only
1744 supports 32-bit symbols, the values of those symbols will be
1745 sign-extended. In this case we can't allow an arbitrary offset
1746 in case the 32-bit value X + OFFSET has a different sign from X. */
1747 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
1748 return offset_within_block_p (x
, INTVAL (offset
));
1750 /* In other cases the relocations can handle any offset. */
1753 case SYMBOL_PC_RELATIVE
:
1754 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1755 In this case, we no longer have access to the underlying constant,
1756 but the original symbol-based access was known to be valid. */
1757 if (GET_CODE (x
) == LABEL_REF
)
1762 case SYMBOL_GP_RELATIVE
:
1763 /* Make sure that the offset refers to something within the
1764 same object block. This should guarantee that the final
1765 PC- or GP-relative offset is within the 16-bit limit. */
1766 return offset_within_block_p (x
, INTVAL (offset
));
1768 case SYMBOL_GOT_PAGE_OFST
:
1769 case SYMBOL_GOTOFF_PAGE
:
1770 /* If the symbol is global, the GOT entry will contain the symbol's
1771 address, and we will apply a 16-bit offset after loading it.
1772 If the symbol is local, the linker should provide enough local
1773 GOT entries for a 16-bit offset, but larger offsets may lead
1775 return SMALL_INT (offset
);
1779 /* There is no carry between the HI and LO REL relocations, so the
1780 offset is only valid if we know it won't lead to such a carry. */
1781 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
1783 case SYMBOL_GOT_DISP
:
1784 case SYMBOL_GOTOFF_DISP
:
1785 case SYMBOL_GOTOFF_CALL
:
1786 case SYMBOL_GOTOFF_LOADGP
:
1789 case SYMBOL_GOTTPREL
:
1797 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1798 single instruction. We rely on the fact that, in the worst case,
1799 all instructions involved in a MIPS16 address calculation are usually
1803 mips_symbol_insns_1 (enum mips_symbol_type type
, enum machine_mode mode
)
1805 if (mips_use_pcrel_pool_p
[(int) type
])
1807 if (mode
== MAX_MACHINE_MODE
)
1808 /* LEAs will be converted into constant-pool references by
1810 type
= SYMBOL_PC_RELATIVE
;
1812 /* The constant must be loaded and then dereferenced. */
1818 case SYMBOL_ABSOLUTE
:
1819 /* When using 64-bit symbols, we need 5 preparatory instructions,
1822 lui $at,%highest(symbol)
1823 daddiu $at,$at,%higher(symbol)
1825 daddiu $at,$at,%hi(symbol)
1828 The final address is then $at + %lo(symbol). With 32-bit
1829 symbols we just need a preparatory LUI for normal mode and
1830 a preparatory LI and SLL for MIPS16. */
1831 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
1833 case SYMBOL_GP_RELATIVE
:
1834 /* Treat GP-relative accesses as taking a single instruction on
1835 MIPS16 too; the copy of $gp can often be shared. */
1838 case SYMBOL_PC_RELATIVE
:
1839 /* PC-relative constants can be only be used with ADDIUPC,
1840 DADDIUPC, LWPC and LDPC. */
1841 if (mode
== MAX_MACHINE_MODE
1842 || GET_MODE_SIZE (mode
) == 4
1843 || GET_MODE_SIZE (mode
) == 8)
1846 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1849 case SYMBOL_GOT_DISP
:
1850 /* The constant will have to be loaded from the GOT before it
1851 is used in an address. */
1852 if (mode
!= MAX_MACHINE_MODE
)
1857 case SYMBOL_GOT_PAGE_OFST
:
1858 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1859 local/global classification is accurate. The worst cases are:
1861 (1) For local symbols when generating o32 or o64 code. The assembler
1867 ...and the final address will be $at + %lo(symbol).
1869 (2) For global symbols when -mxgot. The assembler will use:
1871 lui $at,%got_hi(symbol)
1874 ...and the final address will be $at + %got_lo(symbol). */
1877 case SYMBOL_GOTOFF_PAGE
:
1878 case SYMBOL_GOTOFF_DISP
:
1879 case SYMBOL_GOTOFF_CALL
:
1880 case SYMBOL_GOTOFF_LOADGP
:
1881 case SYMBOL_64_HIGH
:
1887 case SYMBOL_GOTTPREL
:
1890 /* A 16-bit constant formed by a single relocation, or a 32-bit
1891 constant formed from a high 16-bit relocation and a low 16-bit
1892 relocation. Use mips_split_p to determine which. 32-bit
1893 constants need an "lui; addiu" sequence for normal mode and
1894 an "li; sll; addiu" sequence for MIPS16 mode. */
1895 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
1898 /* We don't treat a bare TLS symbol as a constant. */
1904 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1905 to load symbols of type TYPE into a register. Return 0 if the given
1906 type of symbol cannot be used as an immediate operand.
1908 Otherwise, return the number of instructions needed to load or store
1909 values of mode MODE to or from addresses of type TYPE. Return 0 if
1910 the given type of symbol is not valid in addresses.
1912 In both cases, treat extended MIPS16 instructions as two instructions. */
1915 mips_symbol_insns (enum mips_symbol_type type
, enum machine_mode mode
)
1917 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
1920 /* A for_each_rtx callback. Stop the search if *X references a
1921 thread-local symbol. */
1924 mips_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
1926 return mips_tls_symbol_p (*x
);
1929 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1932 mips_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
1934 enum mips_symbol_type type
;
1937 /* There is no assembler syntax for expressing an address-sized
1939 if (GET_CODE (x
) == HIGH
)
1942 /* As an optimization, reject constants that mips_legitimize_move
1945 Suppose we have a multi-instruction sequence that loads constant C
1946 into register R. If R does not get allocated a hard register, and
1947 R is used in an operand that allows both registers and memory
1948 references, reload will consider forcing C into memory and using
1949 one of the instruction's memory alternatives. Returning false
1950 here will force it to use an input reload instead. */
1951 if (CONST_INT_P (x
) && mips_legitimate_constant_p (mode
, x
))
1954 split_const (x
, &base
, &offset
);
1955 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
))
1957 /* See whether we explicitly want these symbols in the pool. */
1958 if (mips_use_pcrel_pool_p
[(int) type
])
1961 /* The same optimization as for CONST_INT. */
1962 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
1965 /* If MIPS16 constant pools live in the text section, they should
1966 not refer to anything that might need run-time relocation. */
1967 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
1971 /* TLS symbols must be computed by mips_legitimize_move. */
1972 if (for_each_rtx (&x
, &mips_tls_symbol_ref_1
, NULL
))
1978 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1979 constants when we're using a per-function constant pool. */
1982 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
1983 const_rtx x ATTRIBUTE_UNUSED
)
1985 return !TARGET_MIPS16_PCREL_LOADS
;
1988 /* Return true if register REGNO is a valid base register for mode MODE.
1989 STRICT_P is true if REG_OK_STRICT is in effect. */
1992 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
,
1995 if (!HARD_REGISTER_NUM_P (regno
))
1999 regno
= reg_renumber
[regno
];
2002 /* These fake registers will be eliminated to either the stack or
2003 hard frame pointer, both of which are usually valid base registers.
2004 Reload deals with the cases where the eliminated form isn't valid. */
2005 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
2008 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2009 values, nothing smaller. There are two problems here:
2011 (a) Instantiating virtual registers can introduce new uses of the
2012 stack pointer. If these virtual registers are valid addresses,
2013 the stack pointer should be too.
2015 (b) Most uses of the stack pointer are not made explicit until
2016 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2017 We don't know until that stage whether we'll be eliminating to the
2018 stack pointer (which needs the restriction) or the hard frame
2019 pointer (which doesn't).
2021 All in all, it seems more consistent to only enforce this restriction
2022 during and after reload. */
2023 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
2024 return !strict_p
|| GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
2026 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
2029 /* Return true if X is a valid base register for mode MODE.
2030 STRICT_P is true if REG_OK_STRICT is in effect. */
2033 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, bool strict_p
)
2035 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2039 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
2042 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2043 can address a value of mode MODE. */
2046 mips_valid_offset_p (rtx x
, enum machine_mode mode
)
2048 /* Check that X is a signed 16-bit number. */
2049 if (!const_arith_operand (x
, Pmode
))
2052 /* We may need to split multiword moves, so make sure that every word
2054 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2055 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2061 /* Return true if a LO_SUM can address a value of mode MODE when the
2062 LO_SUM symbol has type SYMBOL_TYPE. */
2065 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, enum machine_mode mode
)
2067 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2069 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2072 /* Check that there is a known low-part relocation. */
2073 if (mips_lo_relocs
[symbol_type
] == NULL
)
2076 /* We may need to split multiword moves, so make sure that each word
2077 can be accessed without inducing a carry. This is mainly needed
2078 for o64, which has historically only guaranteed 64-bit alignment
2079 for 128-bit types. */
2080 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2081 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2087 /* Return true if X is a valid address for machine mode MODE. If it is,
2088 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2092 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2093 enum machine_mode mode
, bool strict_p
)
2095 switch (GET_CODE (x
))
2099 info
->type
= ADDRESS_REG
;
2101 info
->offset
= const0_rtx
;
2102 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2105 info
->type
= ADDRESS_REG
;
2106 info
->reg
= XEXP (x
, 0);
2107 info
->offset
= XEXP (x
, 1);
2108 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2109 && mips_valid_offset_p (info
->offset
, mode
));
2112 info
->type
= ADDRESS_LO_SUM
;
2113 info
->reg
= XEXP (x
, 0);
2114 info
->offset
= XEXP (x
, 1);
2115 /* We have to trust the creator of the LO_SUM to do something vaguely
2116 sane. Target-independent code that creates a LO_SUM should also
2117 create and verify the matching HIGH. Target-independent code that
2118 adds an offset to a LO_SUM must prove that the offset will not
2119 induce a carry. Failure to do either of these things would be
2120 a bug, and we are not required to check for it here. The MIPS
2121 backend itself should only create LO_SUMs for valid symbolic
2122 constants, with the high part being either a HIGH or a copy
2125 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2126 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2127 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2130 /* Small-integer addresses don't occur very often, but they
2131 are legitimate if $0 is a valid base register. */
2132 info
->type
= ADDRESS_CONST_INT
;
2133 return !TARGET_MIPS16
&& SMALL_INT (x
);
2138 info
->type
= ADDRESS_SYMBOLIC
;
2139 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2141 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2142 && !mips_split_p
[info
->symbol_type
]);
2149 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2152 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2154 struct mips_address_info addr
;
2156 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2159 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2162 mips_stack_address_p (rtx x
, enum machine_mode mode
)
2164 struct mips_address_info addr
;
2166 return (mips_classify_address (&addr
, x
, mode
, false)
2167 && addr
.type
== ADDRESS_REG
2168 && addr
.reg
== stack_pointer_rtx
);
2171 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2172 address instruction. Note that such addresses are not considered
2173 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2174 is so restricted. */
2177 mips_lwxs_address_p (rtx addr
)
2180 && GET_CODE (addr
) == PLUS
2181 && REG_P (XEXP (addr
, 1)))
2183 rtx offset
= XEXP (addr
, 0);
2184 if (GET_CODE (offset
) == MULT
2185 && REG_P (XEXP (offset
, 0))
2186 && CONST_INT_P (XEXP (offset
, 1))
2187 && INTVAL (XEXP (offset
, 1)) == 4)
2193 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2194 indexed address instruction. Note that such addresses are
2195 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2196 sense, because their use is so restricted. */
2199 mips_lx_address_p (rtx addr
, enum machine_mode mode
)
2201 if (GET_CODE (addr
) != PLUS
2202 || !REG_P (XEXP (addr
, 0))
2203 || !REG_P (XEXP (addr
, 1)))
2205 if (ISA_HAS_LBX
&& mode
== QImode
)
2207 if (ISA_HAS_LHX
&& mode
== HImode
)
2209 if (ISA_HAS_LWX
&& mode
== SImode
)
2211 if (ISA_HAS_LDX
&& mode
== DImode
)
2216 /* Return true if a value at OFFSET bytes from base register BASE can be
2217 accessed using an unextended MIPS16 instruction. MODE is the mode of
2220 Usually the offset in an unextended instruction is a 5-bit field.
2221 The offset is unsigned and shifted left once for LH and SH, twice
2222 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2223 an 8-bit immediate field that's shifted left twice. */
2226 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
,
2227 unsigned HOST_WIDE_INT offset
)
2229 if (mode
!= BLKmode
&& offset
% GET_MODE_SIZE (mode
) == 0)
2231 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2232 return offset
< 256U * GET_MODE_SIZE (mode
);
2233 return offset
< 32U * GET_MODE_SIZE (mode
);
2238 /* Return the number of instructions needed to load or store a value
2239 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2240 Assume that multiword moves may need to be split into word moves
2241 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2244 For MIPS16 code, count extended instructions as two instructions. */
2247 mips_address_insns (rtx x
, enum machine_mode mode
, bool might_split_p
)
2249 struct mips_address_info addr
;
2252 /* BLKmode is used for single unaligned loads and stores and should
2253 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2254 meaningless, so we have to single it out as a special case one way
2256 if (mode
!= BLKmode
&& might_split_p
)
2257 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2261 if (mips_classify_address (&addr
, x
, mode
, false))
2266 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2267 UINTVAL (addr
.offset
)))
2271 case ADDRESS_LO_SUM
:
2272 return TARGET_MIPS16
? factor
* 2 : factor
;
2274 case ADDRESS_CONST_INT
:
2277 case ADDRESS_SYMBOLIC
:
2278 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2283 /* Return the number of instructions needed to load constant X.
2284 Return 0 if X isn't a valid constant. */
2287 mips_const_insns (rtx x
)
2289 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2290 enum mips_symbol_type symbol_type
;
2293 switch (GET_CODE (x
))
2296 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2298 || !mips_split_p
[symbol_type
])
2301 /* This is simply an LUI for normal mode. It is an extended
2302 LI followed by an extended SLL for MIPS16. */
2303 return TARGET_MIPS16
? 4 : 1;
2307 /* Unsigned 8-bit constants can be loaded using an unextended
2308 LI instruction. Unsigned 16-bit constants can be loaded
2309 using an extended LI. Negative constants must be loaded
2310 using LI and then negated. */
2311 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2312 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2313 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2314 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2317 return mips_build_integer (codes
, INTVAL (x
));
2321 /* Allow zeros for normal mode, where we can use $0. */
2322 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2328 /* See if we can refer to X directly. */
2329 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2330 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2332 /* Otherwise try splitting the constant into a base and offset.
2333 If the offset is a 16-bit value, we can load the base address
2334 into a register and then use (D)ADDIU to add in the offset.
2335 If the offset is larger, we can load the base and offset
2336 into separate registers and add them together with (D)ADDU.
2337 However, the latter is only possible before reload; during
2338 and after reload, we must have the option of forcing the
2339 constant into the pool instead. */
2340 split_const (x
, &x
, &offset
);
2343 int n
= mips_const_insns (x
);
2346 if (SMALL_INT (offset
))
2348 else if (!targetm
.cannot_force_const_mem (GET_MODE (x
), x
))
2349 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2356 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2364 /* X is a doubleword constant that can be handled by splitting it into
2365 two words and loading each word separately. Return the number of
2366 instructions required to do this. */
2369 mips_split_const_insns (rtx x
)
2371 unsigned int low
, high
;
2373 low
= mips_const_insns (mips_subword (x
, false));
2374 high
= mips_const_insns (mips_subword (x
, true));
2375 gcc_assert (low
> 0 && high
> 0);
2379 /* Return the number of instructions needed to implement INSN,
2380 given that it loads from or stores to MEM. Count extended
2381 MIPS16 instructions as two instructions. */
2384 mips_load_store_insns (rtx mem
, rtx insn
)
2386 enum machine_mode mode
;
2390 gcc_assert (MEM_P (mem
));
2391 mode
= GET_MODE (mem
);
2393 /* Try to prove that INSN does not need to be split. */
2394 might_split_p
= true;
2395 if (GET_MODE_BITSIZE (mode
) == 64)
2397 set
= single_set (insn
);
2398 if (set
&& !mips_split_64bit_move_p (SET_DEST (set
), SET_SRC (set
)))
2399 might_split_p
= false;
2402 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2405 /* Return the number of instructions needed for an integer division. */
2408 mips_idiv_insns (void)
2413 if (TARGET_CHECK_ZERO_DIV
)
2415 if (GENERATE_DIVIDE_TRAPS
)
2421 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2426 /* Emit a move from SRC to DEST. Assume that the move expanders can
2427 handle all moves if !can_create_pseudo_p (). The distinction is
2428 important because, unlike emit_move_insn, the move expanders know
2429 how to force Pmode objects into the constant pool even when the
2430 constant pool address is not itself legitimate. */
2433 mips_emit_move (rtx dest
, rtx src
)
2435 return (can_create_pseudo_p ()
2436 ? emit_move_insn (dest
, src
)
2437 : emit_move_insn_1 (dest
, src
));
2440 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2443 mips_emit_unary (enum rtx_code code
, rtx target
, rtx op0
)
2445 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2446 gen_rtx_fmt_e (code
, GET_MODE (op0
), op0
)));
2449 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2450 Return that new register. */
2453 mips_force_unary (enum machine_mode mode
, enum rtx_code code
, rtx op0
)
2457 reg
= gen_reg_rtx (mode
);
2458 mips_emit_unary (code
, reg
, op0
);
2462 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2465 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2467 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2468 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
2471 /* Compute (CODE OP0 OP1) and store the result in a new register
2472 of mode MODE. Return that new register. */
2475 mips_force_binary (enum machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
2479 reg
= gen_reg_rtx (mode
);
2480 mips_emit_binary (code
, reg
, op0
, op1
);
2484 /* Copy VALUE to a register and return that register. If new pseudos
2485 are allowed, copy it into a new register, otherwise use DEST. */
2488 mips_force_temporary (rtx dest
, rtx value
)
2490 if (can_create_pseudo_p ())
2491 return force_reg (Pmode
, value
);
2494 mips_emit_move (dest
, value
);
2499 /* Emit a call sequence with call pattern PATTERN and return the call
2500 instruction itself (which is not necessarily the last instruction
2501 emitted). ORIG_ADDR is the original, unlegitimized address,
2502 ADDR is the legitimized form, and LAZY_P is true if the call
2503 address is lazily-bound. */
2506 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
2510 insn
= emit_call_insn (pattern
);
2512 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
2514 /* MIPS16 JALRs only take MIPS16 registers. If the target
2515 function requires $25 to be valid on entry, we must copy it
2516 there separately. The move instruction can be put in the
2517 call's delay slot. */
2518 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
2519 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
2520 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
2524 /* Lazy-binding stubs require $gp to be valid on entry. */
2525 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2529 /* See the comment above load_call<mode> for details. */
2530 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2531 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
2532 emit_insn (gen_update_got_version ());
2537 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2538 then add CONST_INT OFFSET to the result. */
2541 mips_unspec_address_offset (rtx base
, rtx offset
,
2542 enum mips_symbol_type symbol_type
)
2544 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2545 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2546 if (offset
!= const0_rtx
)
2547 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2548 return gen_rtx_CONST (Pmode
, base
);
2551 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2552 type SYMBOL_TYPE. */
2555 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2559 split_const (address
, &base
, &offset
);
2560 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2563 /* If OP is an UNSPEC address, return the address to which it refers,
2564 otherwise return OP itself. */
2567 mips_strip_unspec_address (rtx op
)
2571 split_const (op
, &base
, &offset
);
2572 if (UNSPEC_ADDRESS_P (base
))
2573 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
2577 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2578 high part to BASE and return the result. Just return BASE otherwise.
2579 TEMP is as for mips_force_temporary.
2581 The returned expression can be used as the first operand to a LO_SUM. */
2584 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2585 enum mips_symbol_type symbol_type
)
2587 if (mips_split_p
[symbol_type
])
2589 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2590 addr
= mips_force_temporary (temp
, addr
);
2591 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2596 /* Return an instruction that copies $gp into register REG. We want
2597 GCC to treat the register's value as constant, so that its value
2598 can be rematerialized on demand. */
2601 gen_load_const_gp (rtx reg
)
2603 return PMODE_INSN (gen_load_const_gp
, (reg
));
2606 /* Return a pseudo register that contains the value of $gp throughout
2607 the current function. Such registers are needed by MIPS16 functions,
2608 for which $gp itself is not a valid base register or addition operand. */
2611 mips16_gp_pseudo_reg (void)
2613 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
2617 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
2619 push_topmost_sequence ();
2621 scan
= get_insns ();
2622 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
2623 scan
= NEXT_INSN (scan
);
2625 insn
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
2626 insn
= emit_insn_after (insn
, scan
);
2627 INSN_LOCATOR (insn
) = 0;
2629 pop_topmost_sequence ();
2632 return cfun
->machine
->mips16_gp_pseudo_rtx
;
2635 /* Return a base register that holds pic_offset_table_rtx.
2636 TEMP, if nonnull, is a scratch Pmode base register. */
2639 mips_pic_base_register (rtx temp
)
2642 return pic_offset_table_rtx
;
2644 if (currently_expanding_to_rtl
)
2645 return mips16_gp_pseudo_reg ();
2647 if (can_create_pseudo_p ())
2648 temp
= gen_reg_rtx (Pmode
);
2651 /* The first post-reload split exposes all references to $gp
2652 (both uses and definitions). All references must remain
2653 explicit after that point.
2655 It is safe to introduce uses of $gp at any time, so for
2656 simplicity, we do that before the split too. */
2657 mips_emit_move (temp
, pic_offset_table_rtx
);
2659 emit_insn (gen_load_const_gp (temp
));
2663 /* Return the RHS of a load_call<mode> insn. */
2666 mips_unspec_call (rtx reg
, rtx symbol
)
2670 vec
= gen_rtvec (3, reg
, symbol
, gen_rtx_REG (SImode
, GOT_VERSION_REGNUM
));
2671 return gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_LOAD_CALL
);
2674 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2675 reference. Return NULL_RTX otherwise. */
2678 mips_strip_unspec_call (rtx src
)
2680 if (GET_CODE (src
) == UNSPEC
&& XINT (src
, 1) == UNSPEC_LOAD_CALL
)
2681 return mips_strip_unspec_address (XVECEXP (src
, 0, 1));
2685 /* Create and return a GOT reference of type TYPE for address ADDR.
2686 TEMP, if nonnull, is a scratch Pmode base register. */
2689 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
2691 rtx base
, high
, lo_sum_symbol
;
2693 base
= mips_pic_base_register (temp
);
2695 /* If we used the temporary register to load $gp, we can't use
2696 it for the high part as well. */
2697 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
2700 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
2701 lo_sum_symbol
= mips_unspec_address (addr
, type
);
2703 if (type
== SYMBOL_GOTOFF_CALL
)
2704 return mips_unspec_call (high
, lo_sum_symbol
);
2706 return PMODE_INSN (gen_unspec_got
, (high
, lo_sum_symbol
));
2709 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2710 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2711 constant in that context and can be split into high and low parts.
2712 If so, and if LOW_OUT is nonnull, emit the high part and store the
2713 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2715 TEMP is as for mips_force_temporary and is used to load the high
2716 part into a register.
2718 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2719 a legitimize SET_SRC for an .md pattern, otherwise the low part
2720 is guaranteed to be a legitimate address for mode MODE. */
2723 mips_split_symbol (rtx temp
, rtx addr
, enum machine_mode mode
, rtx
*low_out
)
2725 enum mips_symbol_context context
;
2726 enum mips_symbol_type symbol_type
;
2729 context
= (mode
== MAX_MACHINE_MODE
2730 ? SYMBOL_CONTEXT_LEA
2731 : SYMBOL_CONTEXT_MEM
);
2732 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
2734 addr
= XEXP (addr
, 0);
2735 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2736 && mips_symbol_insns (symbol_type
, mode
) > 0
2737 && mips_split_hi_p
[symbol_type
])
2740 switch (symbol_type
)
2742 case SYMBOL_GOT_PAGE_OFST
:
2743 /* The high part of a page/ofst pair is loaded from the GOT. */
2744 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
2755 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2756 && mips_symbol_insns (symbol_type
, mode
) > 0
2757 && mips_split_p
[symbol_type
])
2760 switch (symbol_type
)
2762 case SYMBOL_GOT_DISP
:
2763 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2764 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
2767 case SYMBOL_GP_RELATIVE
:
2768 high
= mips_pic_base_register (temp
);
2769 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2773 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
2774 high
= mips_force_temporary (temp
, high
);
2775 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2784 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2785 mips_force_temporary; it is only needed when OFFSET is not a
2789 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
2791 if (!SMALL_OPERAND (offset
))
2797 /* Load the full offset into a register so that we can use
2798 an unextended instruction for the address itself. */
2799 high
= GEN_INT (offset
);
2804 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2805 The addition inside the macro CONST_HIGH_PART may cause an
2806 overflow, so we need to force a sign-extension check. */
2807 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
2808 offset
= CONST_LOW_PART (offset
);
2810 high
= mips_force_temporary (temp
, high
);
2811 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
2813 return plus_constant (Pmode
, reg
, offset
);
2816 /* The __tls_get_attr symbol. */
2817 static GTY(()) rtx mips_tls_symbol
;
2819 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2820 the TLS symbol we are referencing and TYPE is the symbol type to use
2821 (either global dynamic or local dynamic). V0 is an RTX for the
2822 return value location. */
2825 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
2829 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
2831 if (!mips_tls_symbol
)
2832 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
2834 loc
= mips_unspec_address (sym
, type
);
2838 emit_insn (gen_rtx_SET (Pmode
, a0
,
2839 gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, loc
)));
2840 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
2841 const0_rtx
, NULL_RTX
, false);
2842 RTL_CONST_CALL_P (insn
) = 1;
2843 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
2844 insn
= get_insns ();
2851 /* Return a pseudo register that contains the current thread pointer. */
2858 tp
= gen_reg_rtx (Pmode
);
2861 mips_need_mips16_rdhwr_p
= true;
2862 fn
= mips16_stub_function ("__mips16_rdhwr");
2863 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_LOCAL
;
2864 if (!call_insn_operand (fn
, VOIDmode
))
2865 fn
= force_reg (Pmode
, fn
);
2866 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16
, (tp
, fn
)));
2869 emit_insn (PMODE_INSN (gen_tls_get_tp
, (tp
)));
2873 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2874 its address. The return value will be both a valid address and a valid
2875 SET_SRC (either a REG or a LO_SUM). */
2878 mips_legitimize_tls_address (rtx loc
)
2880 rtx dest
, insn
, v0
, tp
, tmp1
, tmp2
, eqv
, offset
;
2881 enum tls_model model
;
2883 model
= SYMBOL_REF_TLS_MODEL (loc
);
2884 /* Only TARGET_ABICALLS code can have more than one module; other
2885 code must be be static and should not use a GOT. All TLS models
2886 reduce to local exec in this situation. */
2887 if (!TARGET_ABICALLS
)
2888 model
= TLS_MODEL_LOCAL_EXEC
;
2892 case TLS_MODEL_GLOBAL_DYNAMIC
:
2893 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
2894 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
2895 dest
= gen_reg_rtx (Pmode
);
2896 emit_libcall_block (insn
, dest
, v0
, loc
);
2899 case TLS_MODEL_LOCAL_DYNAMIC
:
2900 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
2901 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
2902 tmp1
= gen_reg_rtx (Pmode
);
2904 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2905 share the LDM result with other LD model accesses. */
2906 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2908 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
2910 offset
= mips_unspec_address (loc
, SYMBOL_DTPREL
);
2911 if (mips_split_p
[SYMBOL_DTPREL
])
2913 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
2914 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
2917 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
2918 0, 0, OPTAB_DIRECT
);
2921 case TLS_MODEL_INITIAL_EXEC
:
2922 tp
= mips_get_tp ();
2923 tmp1
= gen_reg_rtx (Pmode
);
2924 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
2925 if (Pmode
== DImode
)
2926 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
2928 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
2929 dest
= gen_reg_rtx (Pmode
);
2930 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
2933 case TLS_MODEL_LOCAL_EXEC
:
2934 tmp1
= mips_get_tp ();
2935 offset
= mips_unspec_address (loc
, SYMBOL_TPREL
);
2936 if (mips_split_p
[SYMBOL_TPREL
])
2938 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_TPREL
);
2939 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
2942 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
2943 0, 0, OPTAB_DIRECT
);
2952 /* If X is not a valid address for mode MODE, force it into a register. */
2955 mips_force_address (rtx x
, enum machine_mode mode
)
2957 if (!mips_legitimate_address_p (mode
, x
, false))
2958 x
= force_reg (Pmode
, x
);
2962 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2963 be legitimized in a way that the generic machinery might not expect,
2964 return a new address, otherwise return NULL. MODE is the mode of
2965 the memory being accessed. */
2968 mips_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
2969 enum machine_mode mode
)
2972 HOST_WIDE_INT offset
;
2974 if (mips_tls_symbol_p (x
))
2975 return mips_legitimize_tls_address (x
);
2977 /* See if the address can split into a high part and a LO_SUM. */
2978 if (mips_split_symbol (NULL
, x
, mode
, &addr
))
2979 return mips_force_address (addr
, mode
);
2981 /* Handle BASE + OFFSET using mips_add_offset. */
2982 mips_split_plus (x
, &base
, &offset
);
2985 if (!mips_valid_base_register_p (base
, mode
, false))
2986 base
= copy_to_mode_reg (Pmode
, base
);
2987 addr
= mips_add_offset (NULL
, base
, offset
);
2988 return mips_force_address (addr
, mode
);
2994 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2997 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
2999 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
3000 enum machine_mode mode
;
3001 unsigned int i
, num_ops
;
3004 mode
= GET_MODE (dest
);
3005 num_ops
= mips_build_integer (codes
, value
);
3007 /* Apply each binary operation to X. Invariant: X is a legitimate
3008 source operand for a SET pattern. */
3009 x
= GEN_INT (codes
[0].value
);
3010 for (i
= 1; i
< num_ops
; i
++)
3012 if (!can_create_pseudo_p ())
3014 emit_insn (gen_rtx_SET (VOIDmode
, temp
, x
));
3018 x
= force_reg (mode
, x
);
3019 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
3022 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
3025 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3026 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3030 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
3034 /* Split moves of big integers into smaller pieces. */
3035 if (splittable_const_int_operand (src
, mode
))
3037 mips_move_integer (dest
, dest
, INTVAL (src
));
3041 /* Split moves of symbolic constants into high/low pairs. */
3042 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
3044 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
3048 /* Generate the appropriate access sequences for TLS symbols. */
3049 if (mips_tls_symbol_p (src
))
3051 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
3055 /* If we have (const (plus symbol offset)), and that expression cannot
3056 be forced into memory, load the symbol first and add in the offset.
3057 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3058 forced into memory, as it usually produces better code. */
3059 split_const (src
, &base
, &offset
);
3060 if (offset
!= const0_rtx
3061 && (targetm
.cannot_force_const_mem (mode
, src
)
3062 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
3064 base
= mips_force_temporary (dest
, base
);
3065 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
3069 src
= force_const_mem (mode
, src
);
3071 /* When using explicit relocs, constant pool references are sometimes
3072 not legitimate addresses. */
3073 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
3074 mips_emit_move (dest
, src
);
3077 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3078 sequence that is valid. */
3081 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
3083 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
3085 mips_emit_move (dest
, force_reg (mode
, src
));
3089 /* We need to deal with constants that would be legitimate
3090 immediate_operands but aren't legitimate move_operands. */
3091 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
3093 mips_legitimize_const_move (mode
, dest
, src
);
3094 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
3100 /* Return true if value X in context CONTEXT is a small-data address
3101 that can be rewritten as a LO_SUM. */
3104 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3106 enum mips_symbol_type symbol_type
;
3108 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3109 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3110 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3111 && symbol_type
== SYMBOL_GP_RELATIVE
);
3114 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3115 containing MEM, or null if none. */
3118 mips_small_data_pattern_1 (rtx
*loc
, void *data
)
3120 enum mips_symbol_context context
;
3122 /* Ignore things like "g" constraints in asms. We make no particular
3123 guarantee about which symbolic constants are acceptable as asm operands
3124 versus which must be forced into a GPR. */
3125 if (GET_CODE (*loc
) == LO_SUM
|| GET_CODE (*loc
) == ASM_OPERANDS
)
3130 if (for_each_rtx (&XEXP (*loc
, 0), mips_small_data_pattern_1
, *loc
))
3135 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3136 return mips_rewrite_small_data_p (*loc
, context
);
3139 /* Return true if OP refers to small data symbols directly, not through
3143 mips_small_data_pattern_p (rtx op
)
3145 return for_each_rtx (&op
, mips_small_data_pattern_1
, NULL
);
3148 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3149 DATA is the containing MEM, or null if none. */
3152 mips_rewrite_small_data_1 (rtx
*loc
, void *data
)
3154 enum mips_symbol_context context
;
3158 for_each_rtx (&XEXP (*loc
, 0), mips_rewrite_small_data_1
, *loc
);
3162 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3163 if (mips_rewrite_small_data_p (*loc
, context
))
3164 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3166 if (GET_CODE (*loc
) == LO_SUM
)
3172 /* Rewrite instruction pattern PATTERN so that it refers to small data
3173 using explicit relocations. */
3176 mips_rewrite_small_data (rtx pattern
)
3178 pattern
= copy_insn (pattern
);
3179 for_each_rtx (&pattern
, mips_rewrite_small_data_1
, NULL
);
3183 /* We need a lot of little routines to check the range of MIPS16 immediate
3187 m16_check_op (rtx op
, int low
, int high
, int mask
)
3189 return (CONST_INT_P (op
)
3190 && IN_RANGE (INTVAL (op
), low
, high
)
3191 && (INTVAL (op
) & mask
) == 0);
3195 m16_uimm3_b (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3197 return m16_check_op (op
, 0x1, 0x8, 0);
3201 m16_simm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3203 return m16_check_op (op
, -0x8, 0x7, 0);
3207 m16_nsimm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3209 return m16_check_op (op
, -0x7, 0x8, 0);
3213 m16_simm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3215 return m16_check_op (op
, -0x10, 0xf, 0);
3219 m16_nsimm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3221 return m16_check_op (op
, -0xf, 0x10, 0);
3225 m16_uimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3227 return m16_check_op (op
, -0x10 << 2, 0xf << 2, 3);
3231 m16_nuimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3233 return m16_check_op (op
, -0xf << 2, 0x10 << 2, 3);
3237 m16_simm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3239 return m16_check_op (op
, -0x80, 0x7f, 0);
3243 m16_nsimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3245 return m16_check_op (op
, -0x7f, 0x80, 0);
3249 m16_uimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3251 return m16_check_op (op
, 0x0, 0xff, 0);
3255 m16_nuimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3257 return m16_check_op (op
, -0xff, 0x0, 0);
3261 m16_uimm8_m1_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3263 return m16_check_op (op
, -0x1, 0xfe, 0);
3267 m16_uimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3269 return m16_check_op (op
, 0x0, 0xff << 2, 3);
3273 m16_nuimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3275 return m16_check_op (op
, -0xff << 2, 0x0, 3);
3279 m16_simm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3281 return m16_check_op (op
, -0x80 << 3, 0x7f << 3, 7);
3285 m16_nsimm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3287 return m16_check_op (op
, -0x7f << 3, 0x80 << 3, 7);
3290 /* The cost of loading values from the constant pool. It should be
3291 larger than the cost of any constant we want to synthesize inline. */
3292 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3294 /* Return the cost of X when used as an operand to the MIPS16 instruction
3295 that implements CODE. Return -1 if there is no such instruction, or if
3296 X is not a valid immediate operand for it. */
3299 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3306 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3307 other shifts are extended. The shift patterns truncate the shift
3308 count to the right size, so there are no out-of-range values. */
3309 if (IN_RANGE (x
, 1, 8))
3311 return COSTS_N_INSNS (1);
3314 if (IN_RANGE (x
, -128, 127))
3316 if (SMALL_OPERAND (x
))
3317 return COSTS_N_INSNS (1);
3321 /* Like LE, but reject the always-true case. */
3325 /* We add 1 to the immediate and use SLT. */
3328 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3331 if (IN_RANGE (x
, 0, 255))
3333 if (SMALL_OPERAND_UNSIGNED (x
))
3334 return COSTS_N_INSNS (1);
3339 /* Equality comparisons with 0 are cheap. */
3349 /* Return true if there is a non-MIPS16 instruction that implements CODE
3350 and if that instruction accepts X as an immediate operand. */
3353 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3360 /* All shift counts are truncated to a valid constant. */
3365 /* Likewise rotates, if the target supports rotates at all. */
3371 /* These instructions take 16-bit unsigned immediates. */
3372 return SMALL_OPERAND_UNSIGNED (x
);
3377 /* These instructions take 16-bit signed immediates. */
3378 return SMALL_OPERAND (x
);
3384 /* The "immediate" forms of these instructions are really
3385 implemented as comparisons with register 0. */
3390 /* Likewise, meaning that the only valid immediate operand is 1. */
3394 /* We add 1 to the immediate and use SLT. */
3395 return SMALL_OPERAND (x
+ 1);
3398 /* Likewise SLTU, but reject the always-true case. */
3399 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3403 /* The bit position and size are immediate operands. */
3404 return ISA_HAS_EXT_INS
;
3407 /* By default assume that $0 can be used for 0. */
3412 /* Return the cost of binary operation X, given that the instruction
3413 sequence for a word-sized or smaller operation has cost SINGLE_COST
3414 and that the sequence of a double-word operation has cost DOUBLE_COST.
3415 If SPEED is true, optimize for speed otherwise optimize for size. */
3418 mips_binary_cost (rtx x
, int single_cost
, int double_cost
, bool speed
)
3422 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3427 + set_src_cost (XEXP (x
, 0), speed
)
3428 + rtx_cost (XEXP (x
, 1), GET_CODE (x
), 1, speed
));
3431 /* Return the cost of floating-point multiplications of mode MODE. */
3434 mips_fp_mult_cost (enum machine_mode mode
)
3436 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3439 /* Return the cost of floating-point divisions of mode MODE. */
3442 mips_fp_div_cost (enum machine_mode mode
)
3444 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3447 /* Return the cost of sign-extending OP to mode MODE, not including the
3448 cost of OP itself. */
3451 mips_sign_extend_cost (enum machine_mode mode
, rtx op
)
3454 /* Extended loads are as cheap as unextended ones. */
3457 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3458 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3461 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3462 /* We can use SEB or SEH. */
3463 return COSTS_N_INSNS (1);
3465 /* We need to use a shift left and a shift right. */
3466 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3469 /* Return the cost of zero-extending OP to mode MODE, not including the
3470 cost of OP itself. */
3473 mips_zero_extend_cost (enum machine_mode mode
, rtx op
)
3476 /* Extended loads are as cheap as unextended ones. */
3479 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3480 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3481 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3483 if (GENERATE_MIPS16E
)
3484 /* We can use ZEB or ZEH. */
3485 return COSTS_N_INSNS (1);
3488 /* We need to load 0xff or 0xffff into a register and use AND. */
3489 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
3491 /* We can use ANDI. */
3492 return COSTS_N_INSNS (1);
3495 /* Return the cost of moving between two registers of mode MODE,
3496 assuming that the move will be in pieces of at most UNITS bytes. */
3499 mips_set_reg_reg_piece_cost (enum machine_mode mode
, unsigned int units
)
3501 return COSTS_N_INSNS ((GET_MODE_SIZE (mode
) + units
- 1) / units
);
3504 /* Return the cost of moving between two registers of mode MODE. */
3507 mips_set_reg_reg_cost (enum machine_mode mode
)
3509 switch (GET_MODE_CLASS (mode
))
3512 return mips_set_reg_reg_piece_cost (mode
, GET_MODE_SIZE (CCmode
));
3515 case MODE_COMPLEX_FLOAT
:
3516 case MODE_VECTOR_FLOAT
:
3517 if (TARGET_HARD_FLOAT
)
3518 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_HWFPVALUE
);
3522 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_WORD
);
3526 /* Implement TARGET_RTX_COSTS. */
3529 mips_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
3530 int *total
, bool speed
)
3532 enum machine_mode mode
= GET_MODE (x
);
3533 bool float_mode_p
= FLOAT_MODE_P (mode
);
3537 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3538 appear in the instruction stream, and the cost of a comparison is
3539 really the cost of the branch or scc condition. At the time of
3540 writing, GCC only uses an explicit outer COMPARE code when optabs
3541 is testing whether a constant is expensive enough to force into a
3542 register. We want optabs to pass such constants through the MIPS
3543 expanders instead, so make all constants very cheap here. */
3544 if (outer_code
== COMPARE
)
3546 gcc_assert (CONSTANT_P (x
));
3554 /* Treat *clear_upper32-style ANDs as having zero cost in the
3555 second operand. The cost is entirely in the first operand.
3557 ??? This is needed because we would otherwise try to CSE
3558 the constant operand. Although that's the right thing for
3559 instructions that continue to be a register operation throughout
3560 compilation, it is disastrous for instructions that could
3561 later be converted into a memory operation. */
3563 && outer_code
== AND
3564 && UINTVAL (x
) == 0xffffffff)
3572 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3581 /* When not optimizing for size, we care more about the cost
3582 of hot code, and hot code is often in a loop. If a constant
3583 operand needs to be forced into a register, we will often be
3584 able to hoist the constant load out of the loop, so the load
3585 should not contribute to the cost. */
3586 if (speed
|| mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3598 if (force_to_mem_operand (x
, VOIDmode
))
3600 *total
= COSTS_N_INSNS (1);
3603 cost
= mips_const_insns (x
);
3606 /* If the constant is likely to be stored in a GPR, SETs of
3607 single-insn constants are as cheap as register sets; we
3608 never want to CSE them.
3610 Don't reduce the cost of storing a floating-point zero in
3611 FPRs. If we have a zero in an FPR for other reasons, we
3612 can get better cfg-cleanup and delayed-branch results by
3613 using it consistently, rather than using $0 sometimes and
3614 an FPR at other times. Also, moves between floating-point
3615 registers are sometimes cheaper than (D)MTC1 $0. */
3617 && outer_code
== SET
3618 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3620 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3621 want to CSE the constant itself. It is usually better to
3622 have N copies of the last operation in the sequence and one
3623 shared copy of the other operations. (Note that this is
3624 not true for MIPS16 code, where the final operation in the
3625 sequence is often an extended instruction.)
3627 Also, if we have a CONST_INT, we don't know whether it is
3628 for a word or doubleword operation, so we cannot rely on
3629 the result of mips_build_integer. */
3630 else if (!TARGET_MIPS16
3631 && (outer_code
== SET
|| mode
== VOIDmode
))
3633 *total
= COSTS_N_INSNS (cost
);
3636 /* The value will need to be fetched from the constant pool. */
3637 *total
= CONSTANT_POOL_COST
;
3641 /* If the address is legitimate, return the number of
3642 instructions it needs. */
3644 cost
= mips_address_insns (addr
, mode
, true);
3647 *total
= COSTS_N_INSNS (cost
+ 1);
3650 /* Check for a scaled indexed address. */
3651 if (mips_lwxs_address_p (addr
)
3652 || mips_lx_address_p (addr
, mode
))
3654 *total
= COSTS_N_INSNS (2);
3657 /* Otherwise use the default handling. */
3661 *total
= COSTS_N_INSNS (6);
3665 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3669 /* Check for a *clear_upper32 pattern and treat it like a zero
3670 extension. See the pattern's comment for details. */
3673 && CONST_INT_P (XEXP (x
, 1))
3674 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3676 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3677 + set_src_cost (XEXP (x
, 0), speed
));
3680 if (ISA_HAS_CINS
&& CONST_INT_P (XEXP (x
, 1)))
3682 rtx op
= XEXP (x
, 0);
3683 if (GET_CODE (op
) == ASHIFT
3684 && CONST_INT_P (XEXP (op
, 1))
3685 && mask_low_and_shift_p (mode
, XEXP (x
, 1), XEXP (op
, 1), 32))
3687 *total
= COSTS_N_INSNS (1) + set_src_cost (XEXP (op
, 0), speed
);
3696 /* Double-word operations use two single-word operations. */
3697 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3706 if (CONSTANT_P (XEXP (x
, 1)))
3707 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3710 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3716 *total
= mips_cost
->fp_add
;
3718 *total
= COSTS_N_INSNS (4);
3722 /* Low-part immediates need an extended MIPS16 instruction. */
3723 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
3724 + set_src_cost (XEXP (x
, 0), speed
));
3739 /* Branch comparisons have VOIDmode, so use the first operand's
3741 mode
= GET_MODE (XEXP (x
, 0));
3742 if (FLOAT_MODE_P (mode
))
3744 *total
= mips_cost
->fp_add
;
3747 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3753 && (ISA_HAS_NMADD4_NMSUB4 (mode
) || ISA_HAS_NMADD3_NMSUB3 (mode
))
3754 && TARGET_FUSED_MADD
3755 && !HONOR_NANS (mode
)
3756 && !HONOR_SIGNED_ZEROS (mode
))
3758 /* See if we can use NMADD or NMSUB. See mips.md for the
3759 associated patterns. */
3760 rtx op0
= XEXP (x
, 0);
3761 rtx op1
= XEXP (x
, 1);
3762 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
3764 *total
= (mips_fp_mult_cost (mode
)
3765 + set_src_cost (XEXP (XEXP (op0
, 0), 0), speed
)
3766 + set_src_cost (XEXP (op0
, 1), speed
)
3767 + set_src_cost (op1
, speed
));
3770 if (GET_CODE (op1
) == MULT
)
3772 *total
= (mips_fp_mult_cost (mode
)
3773 + set_src_cost (op0
, speed
)
3774 + set_src_cost (XEXP (op1
, 0), speed
)
3775 + set_src_cost (XEXP (op1
, 1), speed
));
3784 /* If this is part of a MADD or MSUB, treat the PLUS as
3787 && TARGET_FUSED_MADD
3788 && GET_CODE (XEXP (x
, 0)) == MULT
)
3791 *total
= mips_cost
->fp_add
;
3795 /* Double-word operations require three single-word operations and
3796 an SLTU. The MIPS16 version then needs to move the result of
3797 the SLTU from $24 to a MIPS16 register. */
3798 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
3799 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4),
3805 && (ISA_HAS_NMADD4_NMSUB4 (mode
) || ISA_HAS_NMADD3_NMSUB3 (mode
))
3806 && TARGET_FUSED_MADD
3807 && !HONOR_NANS (mode
)
3808 && HONOR_SIGNED_ZEROS (mode
))
3810 /* See if we can use NMADD or NMSUB. See mips.md for the
3811 associated patterns. */
3812 rtx op
= XEXP (x
, 0);
3813 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3814 && GET_CODE (XEXP (op
, 0)) == MULT
)
3816 *total
= (mips_fp_mult_cost (mode
)
3817 + set_src_cost (XEXP (XEXP (op
, 0), 0), speed
)
3818 + set_src_cost (XEXP (XEXP (op
, 0), 1), speed
)
3819 + set_src_cost (XEXP (op
, 1), speed
));
3825 *total
= mips_cost
->fp_add
;
3827 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
3832 *total
= mips_fp_mult_cost (mode
);
3833 else if (mode
== DImode
&& !TARGET_64BIT
)
3834 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3835 where the mulsidi3 always includes an MFHI and an MFLO. */
3837 ? mips_cost
->int_mult_si
* 3 + 6
3838 : COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9));
3840 *total
= COSTS_N_INSNS (ISA_HAS_MUL3
? 1 : 2);
3841 else if (mode
== DImode
)
3842 *total
= mips_cost
->int_mult_di
;
3844 *total
= mips_cost
->int_mult_si
;
3848 /* Check for a reciprocal. */
3851 && flag_unsafe_math_optimizations
3852 && XEXP (x
, 0) == CONST1_RTX (mode
))
3854 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
3855 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3856 division as being free. */
3857 *total
= set_src_cost (XEXP (x
, 1), speed
);
3859 *total
= (mips_fp_div_cost (mode
)
3860 + set_src_cost (XEXP (x
, 1), speed
));
3869 *total
= mips_fp_div_cost (mode
);
3878 /* It is our responsibility to make division by a power of 2
3879 as cheap as 2 register additions if we want the division
3880 expanders to be used for such operations; see the setting
3881 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3882 should always produce shorter code than using
3883 expand_sdiv2_pow2. */
3885 && CONST_INT_P (XEXP (x
, 1))
3886 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
3888 *total
= COSTS_N_INSNS (2) + set_src_cost (XEXP (x
, 0), speed
);
3891 *total
= COSTS_N_INSNS (mips_idiv_insns ());
3893 else if (mode
== DImode
)
3894 *total
= mips_cost
->int_div_di
;
3896 *total
= mips_cost
->int_div_si
;
3900 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
3904 if (outer_code
== SET
3906 && (GET_CODE (XEXP (x
, 0)) == TRUNCATE
3907 || GET_CODE (XEXP (x
, 0)) == SUBREG
)
3908 && GET_MODE (XEXP (x
, 0)) == QImode
3909 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
3911 *total
= set_src_cost (XEXP (XEXP (x
, 0), 0), speed
);
3914 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
3918 case UNSIGNED_FLOAT
:
3921 case FLOAT_TRUNCATE
:
3922 *total
= mips_cost
->fp_add
;
3926 if (register_operand (SET_DEST (x
), VOIDmode
)
3927 && reg_or_0_operand (SET_SRC (x
), VOIDmode
))
3929 *total
= mips_set_reg_reg_cost (GET_MODE (SET_DEST (x
)));
3939 /* Implement TARGET_ADDRESS_COST. */
3942 mips_address_cost (rtx addr
, bool speed ATTRIBUTE_UNUSED
)
3944 return mips_address_insns (addr
, SImode
, false);
3947 /* Information about a single instruction in a multi-instruction
3949 struct mips_multi_member
{
3950 /* True if this is a label, false if it is code. */
3953 /* The output_asm_insn format of the instruction. */
3956 /* The operands to the instruction. */
3957 rtx operands
[MAX_RECOG_OPERANDS
];
3959 typedef struct mips_multi_member mips_multi_member
;
3961 /* Vector definitions for the above. */
3962 DEF_VEC_O(mips_multi_member
);
3963 DEF_VEC_ALLOC_O(mips_multi_member
, heap
);
3965 /* The instructions that make up the current multi-insn sequence. */
3966 static VEC (mips_multi_member
, heap
) *mips_multi_members
;
3968 /* How many instructions (as opposed to labels) are in the current
3969 multi-insn sequence. */
3970 static unsigned int mips_multi_num_insns
;
3972 /* Start a new multi-insn sequence. */
3975 mips_multi_start (void)
3977 VEC_truncate (mips_multi_member
, mips_multi_members
, 0);
3978 mips_multi_num_insns
= 0;
3981 /* Add a new, uninitialized member to the current multi-insn sequence. */
3983 static struct mips_multi_member
*
3984 mips_multi_add (void)
3986 return VEC_safe_push (mips_multi_member
, heap
, mips_multi_members
,
3987 (struct mips_multi_member
*) 0);
3990 /* Add a normal insn with the given asm format to the current multi-insn
3991 sequence. The other arguments are a null-terminated list of operands. */
3994 mips_multi_add_insn (const char *format
, ...)
3996 struct mips_multi_member
*member
;
4001 member
= mips_multi_add ();
4002 member
->is_label_p
= false;
4003 member
->format
= format
;
4004 va_start (ap
, format
);
4006 while ((op
= va_arg (ap
, rtx
)))
4007 member
->operands
[i
++] = op
;
4009 mips_multi_num_insns
++;
4012 /* Add the given label definition to the current multi-insn sequence.
4013 The definition should include the colon. */
4016 mips_multi_add_label (const char *label
)
4018 struct mips_multi_member
*member
;
4020 member
= mips_multi_add ();
4021 member
->is_label_p
= true;
4022 member
->format
= label
;
4025 /* Return the index of the last member of the current multi-insn sequence. */
4028 mips_multi_last_index (void)
4030 return VEC_length (mips_multi_member
, mips_multi_members
) - 1;
4033 /* Add a copy of an existing instruction to the current multi-insn
4034 sequence. I is the index of the instruction that should be copied. */
4037 mips_multi_copy_insn (unsigned int i
)
4039 struct mips_multi_member
*member
;
4041 member
= mips_multi_add ();
4042 memcpy (member
, &VEC_index (mips_multi_member
, mips_multi_members
, i
),
4044 gcc_assert (!member
->is_label_p
);
4047 /* Change the operand of an existing instruction in the current
4048 multi-insn sequence. I is the index of the instruction,
4049 OP is the index of the operand, and X is the new value. */
4052 mips_multi_set_operand (unsigned int i
, unsigned int op
, rtx x
)
4054 VEC_index (mips_multi_member
, mips_multi_members
, i
).operands
[op
] = x
;
4057 /* Write out the asm code for the current multi-insn sequence. */
4060 mips_multi_write (void)
4062 struct mips_multi_member
*member
;
4065 FOR_EACH_VEC_ELT (mips_multi_member
, mips_multi_members
, i
, member
)
4066 if (member
->is_label_p
)
4067 fprintf (asm_out_file
, "%s\n", member
->format
);
4069 output_asm_insn (member
->format
, member
->operands
);
4072 /* Return one word of double-word value OP, taking into account the fixed
4073 endianness of certain registers. HIGH_P is true to select the high part,
4074 false to select the low part. */
4077 mips_subword (rtx op
, bool high_p
)
4079 unsigned int byte
, offset
;
4080 enum machine_mode mode
;
4082 mode
= GET_MODE (op
);
4083 if (mode
== VOIDmode
)
4084 mode
= TARGET_64BIT
? TImode
: DImode
;
4086 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
4087 byte
= UNITS_PER_WORD
;
4091 if (FP_REG_RTX_P (op
))
4093 /* Paired FPRs are always ordered little-endian. */
4094 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
4095 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
4099 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
4101 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
4104 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
4107 mips_split_64bit_move_p (rtx dest
, rtx src
)
4112 /* FPR-to-FPR moves can be done in a single instruction, if they're
4114 if (FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4117 /* Check for floating-point loads and stores. */
4118 if (ISA_HAS_LDC1_SDC1
)
4120 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4122 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4128 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
4129 this function handles 64-bit moves for which mips_split_64bit_move_p
4130 holds. For 64-bit targets, this function handles 128-bit moves. */
4133 mips_split_doubleword_move (rtx dest
, rtx src
)
4137 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
4139 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
4140 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
4141 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
4142 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
4143 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
4144 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
4145 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
4146 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
4147 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
4148 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
4149 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
4150 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
4151 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
4152 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
4156 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
4158 low_dest
= mips_subword (dest
, false);
4159 mips_emit_move (low_dest
, mips_subword (src
, false));
4161 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
4163 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
4165 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
4167 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
4169 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
4171 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
4175 /* The operation can be split into two normal moves. Decide in
4176 which order to do them. */
4177 low_dest
= mips_subword (dest
, false);
4178 if (REG_P (low_dest
)
4179 && reg_overlap_mentioned_p (low_dest
, src
))
4181 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4182 mips_emit_move (low_dest
, mips_subword (src
, false));
4186 mips_emit_move (low_dest
, mips_subword (src
, false));
4187 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4192 /* Return the appropriate instructions to move SRC into DEST. Assume
4193 that SRC is operand 1 and DEST is operand 0. */
4196 mips_output_move (rtx dest
, rtx src
)
4198 enum rtx_code dest_code
, src_code
;
4199 enum machine_mode mode
;
4200 enum mips_symbol_type symbol_type
;
4203 dest_code
= GET_CODE (dest
);
4204 src_code
= GET_CODE (src
);
4205 mode
= GET_MODE (dest
);
4206 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
4208 if (dbl_p
&& mips_split_64bit_move_p (dest
, src
))
4211 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
4212 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
4214 if (dest_code
== REG
)
4216 if (GP_REG_P (REGNO (dest
)))
4217 return "move\t%0,%z1";
4219 /* Moves to HI are handled by special .md insns. */
4220 if (REGNO (dest
) == LO_REGNUM
)
4223 if (DSP_ACC_REG_P (REGNO (dest
)))
4225 static char retval
[] = "mt__\t%z1,%q0";
4227 retval
[2] = reg_names
[REGNO (dest
)][4];
4228 retval
[3] = reg_names
[REGNO (dest
)][5];
4232 if (FP_REG_P (REGNO (dest
)))
4233 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4235 if (ALL_COP_REG_P (REGNO (dest
)))
4237 static char retval
[] = "dmtc_\t%z1,%0";
4239 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4240 return dbl_p
? retval
: retval
+ 1;
4243 if (dest_code
== MEM
)
4244 switch (GET_MODE_SIZE (mode
))
4246 case 1: return "sb\t%z1,%0";
4247 case 2: return "sh\t%z1,%0";
4248 case 4: return "sw\t%z1,%0";
4249 case 8: return "sd\t%z1,%0";
4252 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
4254 if (src_code
== REG
)
4256 /* Moves from HI are handled by special .md insns. */
4257 if (REGNO (src
) == LO_REGNUM
)
4259 /* When generating VR4120 or VR4130 code, we use MACC and
4260 DMACC instead of MFLO. This avoids both the normal
4261 MIPS III HI/LO hazards and the errata related to
4264 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4268 if (DSP_ACC_REG_P (REGNO (src
)))
4270 static char retval
[] = "mf__\t%0,%q1";
4272 retval
[2] = reg_names
[REGNO (src
)][4];
4273 retval
[3] = reg_names
[REGNO (src
)][5];
4277 if (FP_REG_P (REGNO (src
)))
4278 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4280 if (ALL_COP_REG_P (REGNO (src
)))
4282 static char retval
[] = "dmfc_\t%0,%1";
4284 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4285 return dbl_p
? retval
: retval
+ 1;
4288 if (ST_REG_P (REGNO (src
)) && ISA_HAS_8CC
)
4289 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
4292 if (src_code
== MEM
)
4293 switch (GET_MODE_SIZE (mode
))
4295 case 1: return "lbu\t%0,%1";
4296 case 2: return "lhu\t%0,%1";
4297 case 4: return "lw\t%0,%1";
4298 case 8: return "ld\t%0,%1";
4301 if (src_code
== CONST_INT
)
4303 /* Don't use the X format for the operand itself, because that
4304 will give out-of-range numbers for 64-bit hosts and 32-bit
4307 return "li\t%0,%1\t\t\t# %X1";
4309 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
4312 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
4316 if (src_code
== HIGH
)
4317 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
4319 if (CONST_GP_P (src
))
4320 return "move\t%0,%1";
4322 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
4323 && mips_lo_relocs
[symbol_type
] != 0)
4325 /* A signed 16-bit constant formed by applying a relocation
4326 operator to a symbolic address. */
4327 gcc_assert (!mips_split_p
[symbol_type
]);
4328 return "li\t%0,%R1";
4331 if (symbolic_operand (src
, VOIDmode
))
4333 gcc_assert (TARGET_MIPS16
4334 ? TARGET_MIPS16_TEXT_LOADS
4335 : !TARGET_EXPLICIT_RELOCS
);
4336 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
4339 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
4341 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4343 if (GET_MODE (dest
) == V2SFmode
)
4344 return "mov.ps\t%0,%1";
4346 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4349 if (dest_code
== MEM
)
4350 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
4352 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4354 if (src_code
== MEM
)
4355 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4357 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
4359 static char retval
[] = "l_c_\t%0,%1";
4361 retval
[1] = (dbl_p
? 'd' : 'w');
4362 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4365 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
4367 static char retval
[] = "s_c_\t%1,%0";
4369 retval
[1] = (dbl_p
? 'd' : 'w');
4370 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4376 /* Return true if CMP1 is a suitable second operand for integer ordering
4377 test CODE. See also the *sCC patterns in mips.md. */
4380 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
4386 return reg_or_0_operand (cmp1
, VOIDmode
);
4390 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
4394 return arith_operand (cmp1
, VOIDmode
);
4397 return sle_operand (cmp1
, VOIDmode
);
4400 return sleu_operand (cmp1
, VOIDmode
);
4407 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4408 integer ordering test *CODE, or if an equivalent combination can
4409 be formed by adjusting *CODE and *CMP1. When returning true, update
4410 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4414 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
4415 enum machine_mode mode
)
4417 HOST_WIDE_INT plus_one
;
4419 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
4422 if (CONST_INT_P (*cmp1
))
4426 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4427 if (INTVAL (*cmp1
) < plus_one
)
4430 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4436 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4440 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4451 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4452 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4453 is nonnull, it's OK to set TARGET to the inverse of the result and
4454 flip *INVERT_PTR instead. */
4457 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
4458 rtx target
, rtx cmp0
, rtx cmp1
)
4460 enum machine_mode mode
;
4462 /* First see if there is a MIPS instruction that can do this operation.
4463 If not, try doing the same for the inverse operation. If that also
4464 fails, force CMP1 into a register and try again. */
4465 mode
= GET_MODE (cmp0
);
4466 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
4467 mips_emit_binary (code
, target
, cmp0
, cmp1
);
4470 enum rtx_code inv_code
= reverse_condition (code
);
4471 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
4473 cmp1
= force_reg (mode
, cmp1
);
4474 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
4476 else if (invert_ptr
== 0)
4480 inv_target
= mips_force_binary (GET_MODE (target
),
4481 inv_code
, cmp0
, cmp1
);
4482 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
4486 *invert_ptr
= !*invert_ptr
;
4487 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
4492 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4493 The register will have the same mode as CMP0. */
4496 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
4498 if (cmp1
== const0_rtx
)
4501 if (uns_arith_operand (cmp1
, VOIDmode
))
4502 return expand_binop (GET_MODE (cmp0
), xor_optab
,
4503 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4505 return expand_binop (GET_MODE (cmp0
), sub_optab
,
4506 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4509 /* Convert *CODE into a code that can be used in a floating-point
4510 scc instruction (C.cond.fmt). Return true if the values of
4511 the condition code registers will be inverted, with 0 indicating
4512 that the condition holds. */
4515 mips_reversed_fp_cond (enum rtx_code
*code
)
4522 *code
= reverse_condition_maybe_unordered (*code
);
4530 /* Convert a comparison into something that can be used in a branch or
4531 conditional move. On entry, *OP0 and *OP1 are the values being
4532 compared and *CODE is the code used to compare them.
4534 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4535 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4536 otherwise any standard branch condition can be used. The standard branch
4539 - EQ or NE between two registers.
4540 - any comparison between a register and zero. */
4543 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
4548 if (GET_MODE_CLASS (GET_MODE (*op0
)) == MODE_INT
)
4550 if (!need_eq_ne_p
&& *op1
== const0_rtx
)
4552 else if (*code
== EQ
|| *code
== NE
)
4556 *op0
= mips_zero_if_equal (cmp_op0
, cmp_op1
);
4560 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
4564 /* The comparison needs a separate scc instruction. Store the
4565 result of the scc in *OP0 and compare it against zero. */
4566 bool invert
= false;
4567 *op0
= gen_reg_rtx (GET_MODE (cmp_op0
));
4568 mips_emit_int_order_test (*code
, &invert
, *op0
, cmp_op0
, cmp_op1
);
4569 *code
= (invert
? EQ
: NE
);
4573 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0
)))
4575 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
4576 mips_emit_binary (*code
, *op0
, cmp_op0
, cmp_op1
);
4582 enum rtx_code cmp_code
;
4584 /* Floating-point tests use a separate C.cond.fmt comparison to
4585 set a condition code register. The branch or conditional move
4586 will then compare that register against zero.
4588 Set CMP_CODE to the code of the comparison instruction and
4589 *CODE to the code that the branch or move should use. */
4591 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
4593 ? gen_reg_rtx (CCmode
)
4594 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
4596 mips_emit_binary (cmp_code
, *op0
, cmp_op0
, cmp_op1
);
4600 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4601 and OPERAND[3]. Store the result in OPERANDS[0].
4603 On 64-bit targets, the mode of the comparison and target will always be
4604 SImode, thus possibly narrower than that of the comparison's operands. */
4607 mips_expand_scc (rtx operands
[])
4609 rtx target
= operands
[0];
4610 enum rtx_code code
= GET_CODE (operands
[1]);
4611 rtx op0
= operands
[2];
4612 rtx op1
= operands
[3];
4614 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
);
4616 if (code
== EQ
|| code
== NE
)
4619 && reg_imm10_operand (op1
, GET_MODE (op1
)))
4620 mips_emit_binary (code
, target
, op0
, op1
);
4623 rtx zie
= mips_zero_if_equal (op0
, op1
);
4624 mips_emit_binary (code
, target
, zie
, const0_rtx
);
4628 mips_emit_int_order_test (code
, 0, target
, op0
, op1
);
4631 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4632 CODE and jump to OPERANDS[3] if the condition holds. */
4635 mips_expand_conditional_branch (rtx
*operands
)
4637 enum rtx_code code
= GET_CODE (operands
[0]);
4638 rtx op0
= operands
[1];
4639 rtx op1
= operands
[2];
4642 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
4643 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
4644 emit_jump_insn (gen_condjump (condition
, operands
[3]));
4649 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4650 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4653 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
4654 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
4659 reversed_p
= mips_reversed_fp_cond (&cond
);
4660 cmp_result
= gen_reg_rtx (CCV2mode
);
4661 emit_insn (gen_scc_ps (cmp_result
,
4662 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
4664 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
4667 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
4671 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4672 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4675 mips_expand_conditional_move (rtx
*operands
)
4678 enum rtx_code code
= GET_CODE (operands
[1]);
4679 rtx op0
= XEXP (operands
[1], 0);
4680 rtx op1
= XEXP (operands
[1], 1);
4682 mips_emit_compare (&code
, &op0
, &op1
, true);
4683 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
4684 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
4685 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
4686 operands
[2], operands
[3])));
4689 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4692 mips_expand_conditional_trap (rtx comparison
)
4695 enum machine_mode mode
;
4698 /* MIPS conditional trap instructions don't have GT or LE flavors,
4699 so we must swap the operands and convert to LT and GE respectively. */
4700 code
= GET_CODE (comparison
);
4707 code
= swap_condition (code
);
4708 op0
= XEXP (comparison
, 1);
4709 op1
= XEXP (comparison
, 0);
4713 op0
= XEXP (comparison
, 0);
4714 op1
= XEXP (comparison
, 1);
4718 mode
= GET_MODE (XEXP (comparison
, 0));
4719 op0
= force_reg (mode
, op0
);
4720 if (!arith_operand (op1
, mode
))
4721 op1
= force_reg (mode
, op1
);
4723 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
4724 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
4728 /* Initialize *CUM for a call to a function of type FNTYPE. */
4731 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
4733 memset (cum
, 0, sizeof (*cum
));
4734 cum
->prototype
= (fntype
&& prototype_p (fntype
));
4735 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
4738 /* Fill INFO with information about a single argument. CUM is the
4739 cumulative state for earlier arguments. MODE is the mode of this
4740 argument and TYPE is its type (if known). NAMED is true if this
4741 is a named (fixed) argument rather than a variable one. */
4744 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
4745 enum machine_mode mode
, const_tree type
, bool named
)
4747 bool doubleword_aligned_p
;
4748 unsigned int num_bytes
, num_words
, max_regs
;
4750 /* Work out the size of the argument. */
4751 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
4752 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4754 /* Decide whether it should go in a floating-point register, assuming
4755 one is free. Later code checks for availability.
4757 The checks against UNITS_PER_FPVALUE handle the soft-float and
4758 single-float cases. */
4762 /* The EABI conventions have traditionally been defined in terms
4763 of TYPE_MODE, regardless of the actual type. */
4764 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4765 || mode
== V2SFmode
)
4766 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4771 /* Only leading floating-point scalars are passed in
4772 floating-point registers. We also handle vector floats the same
4773 say, which is OK because they are not covered by the standard ABI. */
4774 info
->fpr_p
= (!cum
->gp_reg_found
4775 && cum
->arg_number
< 2
4777 || SCALAR_FLOAT_TYPE_P (type
)
4778 || VECTOR_FLOAT_TYPE_P (type
))
4779 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4780 || mode
== V2SFmode
)
4781 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4786 /* Scalar, complex and vector floating-point types are passed in
4787 floating-point registers, as long as this is a named rather
4788 than a variable argument. */
4789 info
->fpr_p
= (named
4790 && (type
== 0 || FLOAT_TYPE_P (type
))
4791 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4792 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4793 || mode
== V2SFmode
)
4794 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4796 /* ??? According to the ABI documentation, the real and imaginary
4797 parts of complex floats should be passed in individual registers.
4798 The real and imaginary parts of stack arguments are supposed
4799 to be contiguous and there should be an extra word of padding
4802 This has two problems. First, it makes it impossible to use a
4803 single "void *" va_list type, since register and stack arguments
4804 are passed differently. (At the time of writing, MIPSpro cannot
4805 handle complex float varargs correctly.) Second, it's unclear
4806 what should happen when there is only one register free.
4808 For now, we assume that named complex floats should go into FPRs
4809 if there are two FPRs free, otherwise they should be passed in the
4810 same way as a struct containing two floats. */
4812 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4813 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
4815 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
4816 info
->fpr_p
= false;
4826 /* See whether the argument has doubleword alignment. */
4827 doubleword_aligned_p
= (mips_function_arg_boundary (mode
, type
)
4830 /* Set REG_OFFSET to the register count we're interested in.
4831 The EABI allocates the floating-point registers separately,
4832 but the other ABIs allocate them like integer registers. */
4833 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
4837 /* Advance to an even register if the argument is doubleword-aligned. */
4838 if (doubleword_aligned_p
)
4839 info
->reg_offset
+= info
->reg_offset
& 1;
4841 /* Work out the offset of a stack argument. */
4842 info
->stack_offset
= cum
->stack_words
;
4843 if (doubleword_aligned_p
)
4844 info
->stack_offset
+= info
->stack_offset
& 1;
4846 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
4848 /* Partition the argument between registers and stack. */
4849 info
->reg_words
= MIN (num_words
, max_regs
);
4850 info
->stack_words
= num_words
- info
->reg_words
;
4853 /* INFO describes a register argument that has the normal format for the
4854 argument's mode. Return the register it uses, assuming that FPRs are
4855 available if HARD_FLOAT_P. */
4858 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
4860 if (!info
->fpr_p
|| !hard_float_p
)
4861 return GP_ARG_FIRST
+ info
->reg_offset
;
4862 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
4863 /* In o32, the second argument is always passed in $f14
4864 for TARGET_DOUBLE_FLOAT, regardless of whether the
4865 first argument was a word or doubleword. */
4866 return FP_ARG_FIRST
+ 2;
4868 return FP_ARG_FIRST
+ info
->reg_offset
;
4871 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4874 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
4876 return !TARGET_OLDABI
;
4879 /* Implement TARGET_FUNCTION_ARG. */
4882 mips_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
4883 const_tree type
, bool named
)
4885 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
4886 struct mips_arg_info info
;
4888 /* We will be called with a mode of VOIDmode after the last argument
4889 has been seen. Whatever we return will be passed to the call expander.
4890 If we need a MIPS16 fp_code, return a REG with the code stored as
4892 if (mode
== VOIDmode
)
4894 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
4895 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
4900 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
4902 /* Return straight away if the whole argument is passed on the stack. */
4903 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
4906 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4907 contains a double in its entirety, then that 64-bit chunk is passed
4908 in a floating-point register. */
4910 && TARGET_HARD_FLOAT
4913 && TREE_CODE (type
) == RECORD_TYPE
4914 && TYPE_SIZE_UNIT (type
)
4915 && host_integerp (TYPE_SIZE_UNIT (type
), 1))
4919 /* First check to see if there is any such field. */
4920 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
4921 if (TREE_CODE (field
) == FIELD_DECL
4922 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
4923 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
4924 && host_integerp (bit_position (field
), 0)
4925 && int_bit_position (field
) % BITS_PER_WORD
== 0)
4930 /* Now handle the special case by returning a PARALLEL
4931 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4932 chunks are passed in registers. */
4934 HOST_WIDE_INT bitpos
;
4937 /* assign_parms checks the mode of ENTRY_PARM, so we must
4938 use the actual mode here. */
4939 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
4942 field
= TYPE_FIELDS (type
);
4943 for (i
= 0; i
< info
.reg_words
; i
++)
4947 for (; field
; field
= DECL_CHAIN (field
))
4948 if (TREE_CODE (field
) == FIELD_DECL
4949 && int_bit_position (field
) >= bitpos
)
4953 && int_bit_position (field
) == bitpos
4954 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
4955 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
4956 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
4958 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
4961 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4962 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4964 bitpos
+= BITS_PER_WORD
;
4970 /* Handle the n32/n64 conventions for passing complex floating-point
4971 arguments in FPR pairs. The real part goes in the lower register
4972 and the imaginary part goes in the upper register. */
4975 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4978 enum machine_mode inner
;
4981 inner
= GET_MODE_INNER (mode
);
4982 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
4983 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
4985 /* Real part in registers, imaginary part on stack. */
4986 gcc_assert (info
.stack_words
== info
.reg_words
);
4987 return gen_rtx_REG (inner
, regno
);
4991 gcc_assert (info
.stack_words
== 0);
4992 real
= gen_rtx_EXPR_LIST (VOIDmode
,
4993 gen_rtx_REG (inner
, regno
),
4995 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
4997 regno
+ info
.reg_words
/ 2),
4998 GEN_INT (GET_MODE_SIZE (inner
)));
4999 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
5003 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
5006 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5009 mips_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
5010 const_tree type
, bool named
)
5012 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5013 struct mips_arg_info info
;
5015 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5018 cum
->gp_reg_found
= true;
5020 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5021 an explanation of what this code does. It assumes that we're using
5022 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5024 if (cum
->arg_number
< 2 && info
.fpr_p
)
5025 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
5027 /* Advance the register count. This has the effect of setting
5028 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5029 argument required us to skip the final GPR and pass the whole
5030 argument on the stack. */
5031 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
5032 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
5033 else if (info
.reg_words
> 0)
5034 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
5036 /* Advance the stack word count. */
5037 if (info
.stack_words
> 0)
5038 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
5043 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5046 mips_arg_partial_bytes (cumulative_args_t cum
,
5047 enum machine_mode mode
, tree type
, bool named
)
5049 struct mips_arg_info info
;
5051 mips_get_arg_info (&info
, get_cumulative_args (cum
), mode
, type
, named
);
5052 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
5055 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5056 least PARM_BOUNDARY bits of alignment, but will be given anything up
5057 to STACK_BOUNDARY bits if the type requires it. */
5060 mips_function_arg_boundary (enum machine_mode mode
, const_tree type
)
5062 unsigned int alignment
;
5064 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
5065 if (alignment
< PARM_BOUNDARY
)
5066 alignment
= PARM_BOUNDARY
;
5067 if (alignment
> STACK_BOUNDARY
)
5068 alignment
= STACK_BOUNDARY
;
5072 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5073 upward rather than downward. In other words, return true if the
5074 first byte of the stack slot has useful data, false if the last
5078 mips_pad_arg_upward (enum machine_mode mode
, const_tree type
)
5080 /* On little-endian targets, the first byte of every stack argument
5081 is passed in the first byte of the stack slot. */
5082 if (!BYTES_BIG_ENDIAN
)
5085 /* Otherwise, integral types are padded downward: the last byte of a
5086 stack argument is passed in the last byte of the stack slot. */
5088 ? (INTEGRAL_TYPE_P (type
)
5089 || POINTER_TYPE_P (type
)
5090 || FIXED_POINT_TYPE_P (type
))
5091 : (SCALAR_INT_MODE_P (mode
)
5092 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
5095 /* Big-endian o64 pads floating-point arguments downward. */
5096 if (mips_abi
== ABI_O64
)
5097 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5100 /* Other types are padded upward for o32, o64, n32 and n64. */
5101 if (mips_abi
!= ABI_EABI
)
5104 /* Arguments smaller than a stack slot are padded downward. */
5105 if (mode
!= BLKmode
)
5106 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
5108 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
5111 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5112 if the least significant byte of the register has useful data. Return
5113 the opposite if the most significant byte does. */
5116 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
5118 /* No shifting is required for floating-point arguments. */
5119 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5120 return !BYTES_BIG_ENDIAN
;
5122 /* Otherwise, apply the same padding to register arguments as we do
5123 to stack arguments. */
5124 return mips_pad_arg_upward (mode
, type
);
5127 /* Return nonzero when an argument must be passed by reference. */
5130 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5131 enum machine_mode mode
, const_tree type
,
5132 bool named ATTRIBUTE_UNUSED
)
5134 if (mips_abi
== ABI_EABI
)
5138 /* ??? How should SCmode be handled? */
5139 if (mode
== DImode
|| mode
== DFmode
5140 || mode
== DQmode
|| mode
== UDQmode
5141 || mode
== DAmode
|| mode
== UDAmode
)
5144 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5145 return size
== -1 || size
> UNITS_PER_WORD
;
5149 /* If we have a variable-sized parameter, we have no choice. */
5150 return targetm
.calls
.must_pass_in_stack (mode
, type
);
5154 /* Implement TARGET_CALLEE_COPIES. */
5157 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5158 enum machine_mode mode ATTRIBUTE_UNUSED
,
5159 const_tree type ATTRIBUTE_UNUSED
, bool named
)
5161 return mips_abi
== ABI_EABI
&& named
;
5164 /* See whether VALTYPE is a record whose fields should be returned in
5165 floating-point registers. If so, return the number of fields and
5166 list them in FIELDS (which should have two elements). Return 0
5169 For n32 & n64, a structure with one or two fields is returned in
5170 floating-point registers as long as every field has a floating-point
5174 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
5182 if (TREE_CODE (valtype
) != RECORD_TYPE
)
5186 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= DECL_CHAIN (field
))
5188 if (TREE_CODE (field
) != FIELD_DECL
)
5191 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
5197 fields
[i
++] = field
;
5202 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5203 a value in the most significant part of $2/$3 if:
5205 - the target is big-endian;
5207 - the value has a structure or union type (we generalize this to
5208 cover aggregates from other languages too); and
5210 - the structure is not returned in floating-point registers. */
5213 mips_return_in_msb (const_tree valtype
)
5217 return (TARGET_NEWABI
5218 && TARGET_BIG_ENDIAN
5219 && AGGREGATE_TYPE_P (valtype
)
5220 && mips_fpr_return_fields (valtype
, fields
) == 0);
5223 /* Return true if the function return value MODE will get returned in a
5224 floating-point register. */
5227 mips_return_mode_in_fpr_p (enum machine_mode mode
)
5229 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5231 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5232 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
5235 /* Return the representation of an FPR return register when the
5236 value being returned in FP_RETURN has mode VALUE_MODE and the
5237 return type itself has mode TYPE_MODE. On NewABI targets,
5238 the two modes may be different for structures like:
5240 struct __attribute__((packed)) foo { float f; }
5242 where we return the SFmode value of "f" in FP_RETURN, but where
5243 the structure itself has mode BLKmode. */
5246 mips_return_fpr_single (enum machine_mode type_mode
,
5247 enum machine_mode value_mode
)
5251 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
5252 if (type_mode
!= value_mode
)
5254 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
5255 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
5260 /* Return a composite value in a pair of floating-point registers.
5261 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5262 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5265 For n32 & n64, $f0 always holds the first value and $f2 the second.
5266 Otherwise the values are packed together as closely as possible. */
5269 mips_return_fpr_pair (enum machine_mode mode
,
5270 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
5271 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
5275 inc
= (TARGET_NEWABI
? 2 : MAX_FPRS_PER_FMT
);
5276 return gen_rtx_PARALLEL
5279 gen_rtx_EXPR_LIST (VOIDmode
,
5280 gen_rtx_REG (mode1
, FP_RETURN
),
5282 gen_rtx_EXPR_LIST (VOIDmode
,
5283 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
5284 GEN_INT (offset2
))));
5288 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5289 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5290 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5293 mips_function_value_1 (const_tree valtype
, const_tree fn_decl_or_type
,
5294 enum machine_mode mode
)
5302 if (fn_decl_or_type
&& DECL_P (fn_decl_or_type
))
5303 func
= fn_decl_or_type
;
5307 mode
= TYPE_MODE (valtype
);
5308 unsigned_p
= TYPE_UNSIGNED (valtype
);
5310 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5311 return values, promote the mode here too. */
5312 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
5314 /* Handle structures whose fields are returned in $f0/$f2. */
5315 switch (mips_fpr_return_fields (valtype
, fields
))
5318 return mips_return_fpr_single (mode
,
5319 TYPE_MODE (TREE_TYPE (fields
[0])));
5322 return mips_return_fpr_pair (mode
,
5323 TYPE_MODE (TREE_TYPE (fields
[0])),
5324 int_byte_position (fields
[0]),
5325 TYPE_MODE (TREE_TYPE (fields
[1])),
5326 int_byte_position (fields
[1]));
5329 /* If a value is passed in the most significant part of a register, see
5330 whether we have to round the mode up to a whole number of words. */
5331 if (mips_return_in_msb (valtype
))
5333 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
5334 if (size
% UNITS_PER_WORD
!= 0)
5336 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
5337 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5341 /* For EABI, the class of return register depends entirely on MODE.
5342 For example, "struct { some_type x; }" and "union { some_type x; }"
5343 are returned in the same way as a bare "some_type" would be.
5344 Other ABIs only use FPRs for scalar, complex or vector types. */
5345 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
5346 return gen_rtx_REG (mode
, GP_RETURN
);
5351 /* Handle long doubles for n32 & n64. */
5353 return mips_return_fpr_pair (mode
,
5355 DImode
, GET_MODE_SIZE (mode
) / 2);
5357 if (mips_return_mode_in_fpr_p (mode
))
5359 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5360 return mips_return_fpr_pair (mode
,
5361 GET_MODE_INNER (mode
), 0,
5362 GET_MODE_INNER (mode
),
5363 GET_MODE_SIZE (mode
) / 2);
5365 return gen_rtx_REG (mode
, FP_RETURN
);
5369 return gen_rtx_REG (mode
, GP_RETURN
);
5372 /* Implement TARGET_FUNCTION_VALUE. */
5375 mips_function_value (const_tree valtype
, const_tree fn_decl_or_type
,
5376 bool outgoing ATTRIBUTE_UNUSED
)
5378 return mips_function_value_1 (valtype
, fn_decl_or_type
, VOIDmode
);
5381 /* Implement TARGET_LIBCALL_VALUE. */
5384 mips_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5386 return mips_function_value_1 (NULL_TREE
, NULL_TREE
, mode
);
5389 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5391 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5392 Currently, R2 and F0 are only implemented here (C has no complex type). */
5395 mips_function_value_regno_p (const unsigned int regno
)
5397 if (regno
== GP_RETURN
5398 || regno
== FP_RETURN
5399 || (LONG_DOUBLE_TYPE_SIZE
== 128
5400 && FP_RETURN
!= GP_RETURN
5401 && regno
== FP_RETURN
+ 2))
5407 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5408 all BLKmode objects are returned in memory. Under the n32, n64
5409 and embedded ABIs, small structures are returned in a register.
5410 Objects with varying size must still be returned in memory, of
5414 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
5416 return (TARGET_OLDABI
5417 ? TYPE_MODE (type
) == BLKmode
5418 : !IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
5421 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5424 mips_setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
5425 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5428 CUMULATIVE_ARGS local_cum
;
5429 int gp_saved
, fp_saved
;
5431 /* The caller has advanced CUM up to, but not beyond, the last named
5432 argument. Advance a local copy of CUM past the last "real" named
5433 argument, to find out how many registers are left over. */
5434 local_cum
= *get_cumulative_args (cum
);
5435 mips_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
,
5438 /* Found out how many registers we need to save. */
5439 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
5440 fp_saved
= (EABI_FLOAT_VARARGS_P
5441 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
5450 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
5451 REG_PARM_STACK_SPACE (cfun
->decl
)
5452 - gp_saved
* UNITS_PER_WORD
);
5453 mem
= gen_frame_mem (BLKmode
, ptr
);
5454 set_mem_alias_set (mem
, get_varargs_alias_set ());
5456 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
5461 /* We can't use move_block_from_reg, because it will use
5463 enum machine_mode mode
;
5466 /* Set OFF to the offset from virtual_incoming_args_rtx of
5467 the first float register. The FP save area lies below
5468 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5469 off
= (-gp_saved
* UNITS_PER_WORD
) & -UNITS_PER_FPVALUE
;
5470 off
-= fp_saved
* UNITS_PER_FPREG
;
5472 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5474 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
5475 i
+= MAX_FPRS_PER_FMT
)
5479 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
, off
);
5480 mem
= gen_frame_mem (mode
, ptr
);
5481 set_mem_alias_set (mem
, get_varargs_alias_set ());
5482 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
5483 off
+= UNITS_PER_HWFPVALUE
;
5487 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
5488 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
5489 + fp_saved
* UNITS_PER_FPREG
);
5492 /* Implement TARGET_BUILTIN_VA_LIST. */
5495 mips_build_builtin_va_list (void)
5497 if (EABI_FLOAT_VARARGS_P
)
5499 /* We keep 3 pointers, and two offsets.
5501 Two pointers are to the overflow area, which starts at the CFA.
5502 One of these is constant, for addressing into the GPR save area
5503 below it. The other is advanced up the stack through the
5506 The third pointer is to the bottom of the GPR save area.
5507 Since the FPR save area is just below it, we can address
5508 FPR slots off this pointer.
5510 We also keep two one-byte offsets, which are to be subtracted
5511 from the constant pointers to yield addresses in the GPR and
5512 FPR save areas. These are downcounted as float or non-float
5513 arguments are used, and when they get to zero, the argument
5514 must be obtained from the overflow region. */
5515 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
5518 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
5520 f_ovfl
= build_decl (BUILTINS_LOCATION
,
5521 FIELD_DECL
, get_identifier ("__overflow_argptr"),
5523 f_gtop
= build_decl (BUILTINS_LOCATION
,
5524 FIELD_DECL
, get_identifier ("__gpr_top"),
5526 f_ftop
= build_decl (BUILTINS_LOCATION
,
5527 FIELD_DECL
, get_identifier ("__fpr_top"),
5529 f_goff
= build_decl (BUILTINS_LOCATION
,
5530 FIELD_DECL
, get_identifier ("__gpr_offset"),
5531 unsigned_char_type_node
);
5532 f_foff
= build_decl (BUILTINS_LOCATION
,
5533 FIELD_DECL
, get_identifier ("__fpr_offset"),
5534 unsigned_char_type_node
);
5535 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5536 warn on every user file. */
5537 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
5538 array
= build_array_type (unsigned_char_type_node
,
5539 build_index_type (index
));
5540 f_res
= build_decl (BUILTINS_LOCATION
,
5541 FIELD_DECL
, get_identifier ("__reserved"), array
);
5543 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
5544 DECL_FIELD_CONTEXT (f_gtop
) = record
;
5545 DECL_FIELD_CONTEXT (f_ftop
) = record
;
5546 DECL_FIELD_CONTEXT (f_goff
) = record
;
5547 DECL_FIELD_CONTEXT (f_foff
) = record
;
5548 DECL_FIELD_CONTEXT (f_res
) = record
;
5550 TYPE_FIELDS (record
) = f_ovfl
;
5551 DECL_CHAIN (f_ovfl
) = f_gtop
;
5552 DECL_CHAIN (f_gtop
) = f_ftop
;
5553 DECL_CHAIN (f_ftop
) = f_goff
;
5554 DECL_CHAIN (f_goff
) = f_foff
;
5555 DECL_CHAIN (f_foff
) = f_res
;
5557 layout_type (record
);
5561 /* Otherwise, we use 'void *'. */
5562 return ptr_type_node
;
5565 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5568 mips_va_start (tree valist
, rtx nextarg
)
5570 if (EABI_FLOAT_VARARGS_P
)
5572 const CUMULATIVE_ARGS
*cum
;
5573 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5574 tree ovfl
, gtop
, ftop
, goff
, foff
;
5576 int gpr_save_area_size
;
5577 int fpr_save_area_size
;
5580 cum
= &crtl
->args
.info
;
5582 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
5584 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
5586 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5587 f_gtop
= DECL_CHAIN (f_ovfl
);
5588 f_ftop
= DECL_CHAIN (f_gtop
);
5589 f_goff
= DECL_CHAIN (f_ftop
);
5590 f_foff
= DECL_CHAIN (f_goff
);
5592 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5594 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
5596 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
5598 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
5600 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
5603 /* Emit code to initialize OVFL, which points to the next varargs
5604 stack argument. CUM->STACK_WORDS gives the number of stack
5605 words used by named arguments. */
5606 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
5607 if (cum
->stack_words
> 0)
5608 t
= fold_build_pointer_plus_hwi (t
, cum
->stack_words
* UNITS_PER_WORD
);
5609 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
5610 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5612 /* Emit code to initialize GTOP, the top of the GPR save area. */
5613 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
5614 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
5615 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5617 /* Emit code to initialize FTOP, the top of the FPR save area.
5618 This address is gpr_save_area_bytes below GTOP, rounded
5619 down to the next fp-aligned boundary. */
5620 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
5621 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
5622 fpr_offset
&= -UNITS_PER_FPVALUE
;
5624 t
= fold_build_pointer_plus_hwi (t
, -fpr_offset
);
5625 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
5626 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5628 /* Emit code to initialize GOFF, the offset from GTOP of the
5629 next GPR argument. */
5630 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
5631 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
5632 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5634 /* Likewise emit code to initialize FOFF, the offset from FTOP
5635 of the next FPR argument. */
5636 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
5637 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
5638 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5642 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
5643 std_expand_builtin_va_start (valist
, nextarg
);
5647 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
5651 mips_std_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
5654 tree addr
, t
, type_size
, rounded_size
, valist_tmp
;
5655 unsigned HOST_WIDE_INT align
, boundary
;
5658 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
5660 type
= build_pointer_type (type
);
5662 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
5663 boundary
= targetm
.calls
.function_arg_boundary (TYPE_MODE (type
), type
);
5665 /* When we align parameter on stack for caller, if the parameter
5666 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
5667 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
5668 here with caller. */
5669 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
5670 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
5672 boundary
/= BITS_PER_UNIT
;
5674 /* Hoist the valist value into a temporary for the moment. */
5675 valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
5677 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
5678 requires greater alignment, we must perform dynamic alignment. */
5679 if (boundary
> align
)
5681 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
5682 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
5683 gimplify_and_add (t
, pre_p
);
5685 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
5686 fold_build2 (BIT_AND_EXPR
, TREE_TYPE (valist
),
5688 build_int_cst (TREE_TYPE (valist
), -boundary
)));
5689 gimplify_and_add (t
, pre_p
);
5694 /* If the actual alignment is less than the alignment of the type,
5695 adjust the type accordingly so that we don't assume strict alignment
5696 when dereferencing the pointer. */
5697 boundary
*= BITS_PER_UNIT
;
5698 if (boundary
< TYPE_ALIGN (type
))
5700 type
= build_variant_type_copy (type
);
5701 TYPE_ALIGN (type
) = boundary
;
5704 /* Compute the rounded size of the type. */
5705 type_size
= size_in_bytes (type
);
5706 rounded_size
= round_up (type_size
, align
);
5708 /* Reduce rounded_size so it's sharable with the postqueue. */
5709 gimplify_expr (&rounded_size
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
5713 if (PAD_VARARGS_DOWN
&& !integer_zerop (rounded_size
))
5715 /* Small args are padded downward. */
5716 t
= fold_build2_loc (input_location
, GT_EXPR
, sizetype
,
5717 rounded_size
, size_int (align
));
5718 t
= fold_build3 (COND_EXPR
, sizetype
, t
, size_zero_node
,
5719 size_binop (MINUS_EXPR
, rounded_size
, type_size
));
5720 addr
= fold_build_pointer_plus (addr
, t
);
5723 /* Compute new value for AP. */
5724 t
= fold_build_pointer_plus (valist_tmp
, rounded_size
);
5725 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
5726 gimplify_and_add (t
, pre_p
);
5728 addr
= fold_convert (build_pointer_type (type
), addr
);
5731 addr
= build_va_arg_indirect_ref (addr
);
5733 return build_va_arg_indirect_ref (addr
);
5736 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5739 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
5745 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
5747 type
= build_pointer_type (type
);
5749 if (!EABI_FLOAT_VARARGS_P
)
5750 addr
= mips_std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
5753 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5754 tree ovfl
, top
, off
, align
;
5755 HOST_WIDE_INT size
, rsize
, osize
;
5758 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5759 f_gtop
= DECL_CHAIN (f_ovfl
);
5760 f_ftop
= DECL_CHAIN (f_gtop
);
5761 f_goff
= DECL_CHAIN (f_ftop
);
5762 f_foff
= DECL_CHAIN (f_goff
);
5766 TOP be the top of the GPR or FPR save area;
5767 OFF be the offset from TOP of the next register;
5768 ADDR_RTX be the address of the argument;
5769 SIZE be the number of bytes in the argument type;
5770 RSIZE be the number of bytes used to store the argument
5771 when it's in the register save area; and
5772 OSIZE be the number of bytes used to store it when it's
5773 in the stack overflow area.
5775 The code we want is:
5777 1: off &= -rsize; // round down
5780 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5785 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5786 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5790 [1] and [9] can sometimes be optimized away. */
5792 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5794 size
= int_size_in_bytes (type
);
5796 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
5797 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
5799 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
5800 unshare_expr (valist
), f_ftop
, NULL_TREE
);
5801 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
5802 unshare_expr (valist
), f_foff
, NULL_TREE
);
5804 /* When va_start saves FPR arguments to the stack, each slot
5805 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5806 argument's precision. */
5807 rsize
= UNITS_PER_HWFPVALUE
;
5809 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5810 (= PARM_BOUNDARY bits). This can be different from RSIZE
5813 (1) On 32-bit targets when TYPE is a structure such as:
5815 struct s { float f; };
5817 Such structures are passed in paired FPRs, so RSIZE
5818 will be 8 bytes. However, the structure only takes
5819 up 4 bytes of memory, so OSIZE will only be 4.
5821 (2) In combinations such as -mgp64 -msingle-float
5822 -fshort-double. Doubles passed in registers will then take
5823 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5824 stack take up UNITS_PER_WORD bytes. */
5825 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
5829 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
5830 unshare_expr (valist
), f_gtop
, NULL_TREE
);
5831 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
5832 unshare_expr (valist
), f_goff
, NULL_TREE
);
5833 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
5834 if (rsize
> UNITS_PER_WORD
)
5836 /* [1] Emit code for: off &= -rsize. */
5837 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
5838 build_int_cst (TREE_TYPE (off
), -rsize
));
5839 gimplify_assign (unshare_expr (off
), t
, pre_p
);
5844 /* [2] Emit code to branch if off == 0. */
5845 t
= build2 (NE_EXPR
, boolean_type_node
, unshare_expr (off
),
5846 build_int_cst (TREE_TYPE (off
), 0));
5847 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
5849 /* [5] Emit code for: off -= rsize. We do this as a form of
5850 post-decrement not available to C. */
5851 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
5852 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
5854 /* [4] Emit code for:
5855 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5856 t
= fold_convert (sizetype
, t
);
5857 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
5858 t
= fold_build_pointer_plus (top
, t
);
5859 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
5860 t
= fold_build_pointer_plus_hwi (t
, rsize
- size
);
5861 COND_EXPR_THEN (addr
) = t
;
5863 if (osize
> UNITS_PER_WORD
)
5865 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5866 t
= fold_build_pointer_plus_hwi (unshare_expr (ovfl
), osize
- 1);
5867 u
= build_int_cst (TREE_TYPE (t
), -osize
);
5868 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
, u
);
5869 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
5870 unshare_expr (ovfl
), t
);
5875 /* [10, 11] Emit code for:
5876 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5878 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
5879 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
5880 if (BYTES_BIG_ENDIAN
&& osize
> size
)
5881 t
= fold_build_pointer_plus_hwi (t
, osize
- size
);
5883 /* String [9] and [10, 11] together. */
5885 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
5886 COND_EXPR_ELSE (addr
) = t
;
5888 addr
= fold_convert (build_pointer_type (type
), addr
);
5889 addr
= build_va_arg_indirect_ref (addr
);
5893 addr
= build_va_arg_indirect_ref (addr
);
5898 /* Declare a unique, locally-binding function called NAME, then start
5902 mips_start_unique_function (const char *name
)
5906 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
5907 get_identifier (name
),
5908 build_function_type_list (void_type_node
, NULL_TREE
));
5909 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
5910 NULL_TREE
, void_type_node
);
5911 TREE_PUBLIC (decl
) = 1;
5912 TREE_STATIC (decl
) = 1;
5914 DECL_COMDAT_GROUP (decl
) = DECL_ASSEMBLER_NAME (decl
);
5916 targetm
.asm_out
.unique_section (decl
, 0);
5917 switch_to_section (get_named_section (decl
, NULL
, 0));
5919 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
5920 fputs ("\t.hidden\t", asm_out_file
);
5921 assemble_name (asm_out_file
, name
);
5922 putc ('\n', asm_out_file
);
5925 /* Start a definition of function NAME. MIPS16_P indicates whether the
5926 function contains MIPS16 code. */
5929 mips_start_function_definition (const char *name
, bool mips16_p
)
5932 fprintf (asm_out_file
, "\t.set\tmips16\n");
5934 fprintf (asm_out_file
, "\t.set\tnomips16\n");
5936 if (!flag_inhibit_size_directive
)
5938 fputs ("\t.ent\t", asm_out_file
);
5939 assemble_name (asm_out_file
, name
);
5940 fputs ("\n", asm_out_file
);
5943 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
5945 /* Start the definition proper. */
5946 assemble_name (asm_out_file
, name
);
5947 fputs (":\n", asm_out_file
);
5950 /* End a function definition started by mips_start_function_definition. */
5953 mips_end_function_definition (const char *name
)
5955 if (!flag_inhibit_size_directive
)
5957 fputs ("\t.end\t", asm_out_file
);
5958 assemble_name (asm_out_file
, name
);
5959 fputs ("\n", asm_out_file
);
5963 /* Output a definition of the __mips16_rdhwr function. */
5966 mips_output_mips16_rdhwr (void)
5970 name
= "__mips16_rdhwr";
5971 mips_start_unique_function (name
);
5972 mips_start_function_definition (name
, false);
5973 fprintf (asm_out_file
,
5975 "\t.set\tmips32r2\n"
5976 "\t.set\tnoreorder\n"
5980 mips_end_function_definition (name
);
5983 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5986 mips_ok_for_lazy_binding_p (rtx x
)
5988 return (TARGET_USE_GOT
5989 && GET_CODE (x
) == SYMBOL_REF
5990 && !SYMBOL_REF_BIND_NOW_P (x
)
5991 && !mips_symbol_binds_local_p (x
));
5994 /* Load function address ADDR into register DEST. TYPE is as for
5995 mips_expand_call. Return true if we used an explicit lazy-binding
5999 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
6001 /* If we're generating PIC, and this call is to a global function,
6002 try to allow its address to be resolved lazily. This isn't
6003 possible for sibcalls when $gp is call-saved because the value
6004 of $gp on entry to the stub would be our caller's gp, not ours. */
6005 if (TARGET_EXPLICIT_RELOCS
6006 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
6007 && mips_ok_for_lazy_binding_p (addr
))
6009 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
6010 emit_insn (gen_rtx_SET (VOIDmode
, dest
, addr
));
6015 mips_emit_move (dest
, addr
);
6020 /* Each locally-defined hard-float MIPS16 function has a local symbol
6021 associated with it. This hash table maps the function symbol (FUNC)
6022 to the local symbol (LOCAL). */
6023 struct GTY(()) mips16_local_alias
{
6027 static GTY ((param_is (struct mips16_local_alias
))) htab_t mips16_local_aliases
;
6029 /* Hash table callbacks for mips16_local_aliases. */
6032 mips16_local_aliases_hash (const void *entry
)
6034 const struct mips16_local_alias
*alias
;
6036 alias
= (const struct mips16_local_alias
*) entry
;
6037 return htab_hash_string (XSTR (alias
->func
, 0));
6041 mips16_local_aliases_eq (const void *entry1
, const void *entry2
)
6043 const struct mips16_local_alias
*alias1
, *alias2
;
6045 alias1
= (const struct mips16_local_alias
*) entry1
;
6046 alias2
= (const struct mips16_local_alias
*) entry2
;
6047 return rtx_equal_p (alias1
->func
, alias2
->func
);
6050 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6051 Return a local alias for it, creating a new one if necessary. */
6054 mips16_local_alias (rtx func
)
6056 struct mips16_local_alias
*alias
, tmp_alias
;
6059 /* Create the hash table if this is the first call. */
6060 if (mips16_local_aliases
== NULL
)
6061 mips16_local_aliases
= htab_create_ggc (37, mips16_local_aliases_hash
,
6062 mips16_local_aliases_eq
, NULL
);
6064 /* Look up the function symbol, creating a new entry if need be. */
6065 tmp_alias
.func
= func
;
6066 slot
= htab_find_slot (mips16_local_aliases
, &tmp_alias
, INSERT
);
6067 gcc_assert (slot
!= NULL
);
6069 alias
= (struct mips16_local_alias
*) *slot
;
6072 const char *func_name
, *local_name
;
6075 /* Create a new SYMBOL_REF for the local symbol. The choice of
6076 __fn_local_* is based on the __fn_stub_* names that we've
6077 traditionally used for the non-MIPS16 stub. */
6078 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
6079 local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
6080 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
6081 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
6083 /* Create a new structure to represent the mapping. */
6084 alias
= ggc_alloc_mips16_local_alias ();
6086 alias
->local
= local
;
6089 return alias
->local
;
6092 /* A chained list of functions for which mips16_build_call_stub has already
6093 generated a stub. NAME is the name of the function and FP_RET_P is true
6094 if the function returns a value in floating-point registers. */
6095 struct mips16_stub
{
6096 struct mips16_stub
*next
;
6100 static struct mips16_stub
*mips16_stubs
;
6102 /* Return the two-character string that identifies floating-point
6103 return mode MODE in the name of a MIPS16 function stub. */
6106 mips16_call_stub_mode_suffix (enum machine_mode mode
)
6110 else if (mode
== DFmode
)
6112 else if (mode
== SCmode
)
6114 else if (mode
== DCmode
)
6116 else if (mode
== V2SFmode
)
6122 /* Write instructions to move a 32-bit value between general register
6123 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6124 from GPREG to FPREG and 'f' to move in the opposite direction. */
6127 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6129 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6130 reg_names
[gpreg
], reg_names
[fpreg
]);
6133 /* Likewise for 64-bit values. */
6136 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6139 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
6140 reg_names
[gpreg
], reg_names
[fpreg
]);
6141 else if (TARGET_FLOAT64
)
6143 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6144 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6145 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
6146 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
6150 /* Move the least-significant word. */
6151 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6152 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6153 /* ...then the most significant word. */
6154 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6155 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
6159 /* Write out code to move floating-point arguments into or out of
6160 general registers. FP_CODE is the code describing which arguments
6161 are present (see the comment above the definition of CUMULATIVE_ARGS
6162 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6165 mips_output_args_xfer (int fp_code
, char direction
)
6167 unsigned int gparg
, fparg
, f
;
6168 CUMULATIVE_ARGS cum
;
6170 /* This code only works for o32 and o64. */
6171 gcc_assert (TARGET_OLDABI
);
6173 mips_init_cumulative_args (&cum
, NULL
);
6175 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6177 enum machine_mode mode
;
6178 struct mips_arg_info info
;
6182 else if ((f
& 3) == 2)
6187 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
6188 gparg
= mips_arg_regno (&info
, false);
6189 fparg
= mips_arg_regno (&info
, true);
6192 mips_output_32bit_xfer (direction
, gparg
, fparg
);
6194 mips_output_64bit_xfer (direction
, gparg
, fparg
);
6196 mips_function_arg_advance (pack_cumulative_args (&cum
), mode
, NULL
, true);
6200 /* Write a MIPS16 stub for the current function. This stub is used
6201 for functions which take arguments in the floating-point registers.
6202 It is normal-mode code that moves the floating-point arguments
6203 into the general registers and then jumps to the MIPS16 code. */
6206 mips16_build_function_stub (void)
6208 const char *fnname
, *alias_name
, *separator
;
6209 char *secname
, *stubname
;
6214 /* Create the name of the stub, and its unique section. */
6215 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
6216 alias
= mips16_local_alias (symbol
);
6218 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
6219 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
6220 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
6221 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
6223 /* Build a decl for the stub. */
6224 stubdecl
= build_decl (BUILTINS_LOCATION
,
6225 FUNCTION_DECL
, get_identifier (stubname
),
6226 build_function_type_list (void_type_node
, NULL_TREE
));
6227 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6228 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6229 RESULT_DECL
, NULL_TREE
, void_type_node
);
6231 /* Output a comment. */
6232 fprintf (asm_out_file
, "\t# Stub function for %s (",
6233 current_function_name ());
6235 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
6237 fprintf (asm_out_file
, "%s%s", separator
,
6238 (f
& 3) == 1 ? "float" : "double");
6241 fprintf (asm_out_file
, ")\n");
6243 /* Start the function definition. */
6244 assemble_start_function (stubdecl
, stubname
);
6245 mips_start_function_definition (stubname
, false);
6247 /* If generating pic2 code, either set up the global pointer or
6249 if (TARGET_ABICALLS_PIC2
)
6251 if (TARGET_ABSOLUTE_ABICALLS
)
6252 fprintf (asm_out_file
, "\t.option\tpic0\n");
6255 output_asm_insn ("%(.cpload\t%^%)", NULL
);
6256 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6257 target function is. Use a local GOT access when loading the
6258 symbol, to cut down on the number of unnecessary GOT entries
6259 for stubs that aren't needed. */
6260 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
6265 /* Load the address of the MIPS16 function into $25. Do this first so
6266 that targets with coprocessor interlocks can use an MFC1 to fill the
6268 output_asm_insn ("la\t%^,%0", &symbol
);
6270 /* Move the arguments from floating-point registers to general registers. */
6271 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
6273 /* Jump to the MIPS16 function. */
6274 output_asm_insn ("jr\t%^", NULL
);
6276 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
6277 fprintf (asm_out_file
, "\t.option\tpic2\n");
6279 mips_end_function_definition (stubname
);
6281 /* If the linker needs to create a dynamic symbol for the target
6282 function, it will associate the symbol with the stub (which,
6283 unlike the target function, follows the proper calling conventions).
6284 It is therefore useful to have a local alias for the target function,
6285 so that it can still be identified as MIPS16 code. As an optimization,
6286 this symbol can also be used for indirect MIPS16 references from
6287 within this file. */
6288 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
6290 switch_to_section (function_section (current_function_decl
));
6293 /* The current function is a MIPS16 function that returns a value in an FPR.
6294 Copy the return value from its soft-float to its hard-float location.
6295 libgcc2 has special non-MIPS16 helper functions for each case. */
6298 mips16_copy_fpr_return_value (void)
6300 rtx fn
, insn
, retval
;
6302 enum machine_mode return_mode
;
6305 return_type
= DECL_RESULT (current_function_decl
);
6306 return_mode
= DECL_MODE (return_type
);
6308 name
= ACONCAT (("__mips16_ret_",
6309 mips16_call_stub_mode_suffix (return_mode
),
6311 fn
= mips16_stub_function (name
);
6313 /* The function takes arguments in $2 (and possibly $3), so calls
6314 to it cannot be lazily bound. */
6315 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
6317 /* Model the call as something that takes the GPR return value as
6318 argument and returns an "updated" value. */
6319 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
6320 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
6321 const0_rtx
, NULL_RTX
, false);
6322 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
6325 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6326 RETVAL is the location of the return value, or null if this is
6327 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6328 arguments and FP_CODE is the code built by mips_function_arg;
6329 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6331 There are three alternatives:
6333 - If a stub was needed, emit the call and return the call insn itself.
6335 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6336 to the new target and return null.
6338 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6341 A stub is needed for calls to functions that, in normal mode,
6342 receive arguments in FPRs or return values in FPRs. The stub
6343 copies the arguments from their soft-float positions to their
6344 hard-float positions, calls the real function, then copies the
6345 return value from its hard-float position to its soft-float
6348 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6349 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6350 automatically redirects the JAL to the stub, otherwise the JAL
6351 continues to call FN directly. */
6354 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
6358 struct mips16_stub
*l
;
6361 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6362 we were invoked with the -msoft-float option. */
6363 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
6366 /* Figure out whether the value might come back in a floating-point
6368 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
6370 /* We don't need to do anything if there were no floating-point
6371 arguments and the value will not be returned in a floating-point
6373 if (fp_code
== 0 && !fp_ret_p
)
6376 /* We don't need to do anything if this is a call to a special
6377 MIPS16 support function. */
6379 if (mips16_stub_function_p (fn
))
6382 /* If we're calling a locally-defined MIPS16 function, we know that
6383 it will return values in both the "soft-float" and "hard-float"
6384 registers. There is no need to use a stub to move the latter
6386 if (fp_code
== 0 && mips16_local_function_p (fn
))
6389 /* This code will only work for o32 and o64 abis. The other ABI's
6390 require more sophisticated support. */
6391 gcc_assert (TARGET_OLDABI
);
6393 /* If we're calling via a function pointer, use one of the magic
6394 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6395 Each stub expects the function address to arrive in register $2. */
6396 if (GET_CODE (fn
) != SYMBOL_REF
6397 || !call_insn_operand (fn
, VOIDmode
))
6400 rtx stub_fn
, insn
, addr
;
6403 /* If this is a locally-defined and locally-binding function,
6404 avoid the stub by calling the local alias directly. */
6405 if (mips16_local_function_p (fn
))
6407 *fn_ptr
= mips16_local_alias (fn
);
6411 /* Create a SYMBOL_REF for the libgcc.a function. */
6413 sprintf (buf
, "__mips16_call_stub_%s_%d",
6414 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
6417 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
6418 stub_fn
= mips16_stub_function (buf
);
6420 /* The function uses $2 as an argument, so calls to it
6421 cannot be lazily bound. */
6422 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
6424 /* Load the target function into $2. */
6425 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
6426 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
6428 /* Emit the call. */
6429 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
6430 args_size
, NULL_RTX
, lazy_p
);
6432 /* Tell GCC that this call does indeed use the value of $2. */
6433 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
6435 /* If we are handling a floating-point return value, we need to
6436 save $18 in the function prologue. Putting a note on the
6437 call will mean that df_regs_ever_live_p ($18) will be true if the
6438 call is not eliminated, and we can check that in the prologue
6441 CALL_INSN_FUNCTION_USAGE (insn
) =
6442 gen_rtx_EXPR_LIST (VOIDmode
,
6443 gen_rtx_CLOBBER (VOIDmode
,
6444 gen_rtx_REG (word_mode
, 18)),
6445 CALL_INSN_FUNCTION_USAGE (insn
));
6450 /* We know the function we are going to call. If we have already
6451 built a stub, we don't need to do anything further. */
6452 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
6453 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
6454 if (strcmp (l
->name
, fnname
) == 0)
6459 const char *separator
;
6460 char *secname
, *stubname
;
6461 tree stubid
, stubdecl
;
6464 /* If the function does not return in FPRs, the special stub
6468 If the function does return in FPRs, the stub section is named
6469 .mips16.call.fp.FNNAME
6471 Build a decl for the stub. */
6472 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
6474 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
6476 stubid
= get_identifier (stubname
);
6477 stubdecl
= build_decl (BUILTINS_LOCATION
,
6478 FUNCTION_DECL
, stubid
,
6479 build_function_type_list (void_type_node
,
6481 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6482 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6483 RESULT_DECL
, NULL_TREE
,
6486 /* Output a comment. */
6487 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
6489 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
6493 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6495 fprintf (asm_out_file
, "%s%s", separator
,
6496 (f
& 3) == 1 ? "float" : "double");
6499 fprintf (asm_out_file
, ")\n");
6501 /* Start the function definition. */
6502 assemble_start_function (stubdecl
, stubname
);
6503 mips_start_function_definition (stubname
, false);
6507 fprintf (asm_out_file
, "\t.cfi_startproc\n");
6509 /* Create a fake CFA 4 bytes below the stack pointer.
6510 This works around unwinders (like libgcc's) that expect
6511 the CFA for non-signal frames to be unique. */
6512 fprintf (asm_out_file
, "\t.cfi_def_cfa 29,-4\n");
6514 /* "Save" $sp in itself so we don't use the fake CFA.
6515 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6516 fprintf (asm_out_file
, "\t.cfi_escape 0x16,29,1,0x6d\n");
6520 /* Load the address of the MIPS16 function into $25. Do this
6521 first so that targets with coprocessor interlocks can use
6522 an MFC1 to fill the delay slot. */
6523 if (TARGET_EXPLICIT_RELOCS
)
6525 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
6526 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
6529 output_asm_insn ("la\t%^,%0", &fn
);
6532 /* Move the arguments from general registers to floating-point
6534 mips_output_args_xfer (fp_code
, 't');
6538 /* Save the return address in $18 and call the non-MIPS16 function.
6539 The stub's caller knows that $18 might be clobbered, even though
6540 $18 is usually a call-saved register. */
6541 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
6542 reg_names
[GP_REG_FIRST
+ 18], reg_names
[RETURN_ADDR_REGNUM
]);
6543 output_asm_insn (MIPS_CALL ("jal", &fn
, 0, -1), &fn
);
6544 fprintf (asm_out_file
, "\t.cfi_register 31,18\n");
6546 /* Move the result from floating-point registers to
6547 general registers. */
6548 switch (GET_MODE (retval
))
6551 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_BIG_ENDIAN
,
6553 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6555 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_LITTLE_ENDIAN
,
6556 TARGET_LITTLE_ENDIAN
6557 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6559 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
6561 /* On 64-bit targets, complex floats are returned in
6562 a single GPR, such that "sd" on a suitably-aligned
6563 target would store the value correctly. */
6564 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6565 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6566 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6567 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6568 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
6569 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
6570 fprintf (asm_out_file
, "\tdsrl\t%s,%s,32\n",
6571 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6572 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6573 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
6574 reg_names
[GP_RETURN
],
6575 reg_names
[GP_RETURN
],
6576 reg_names
[GP_RETURN
+ 1]);
6581 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6585 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
6586 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
6590 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6596 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
6597 fprintf (asm_out_file
, "\t.cfi_endproc\n");
6601 /* Jump to the previously-loaded address. */
6602 output_asm_insn ("jr\t%^", NULL
);
6605 #ifdef ASM_DECLARE_FUNCTION_SIZE
6606 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
6609 mips_end_function_definition (stubname
);
6611 /* Record this stub. */
6612 l
= XNEW (struct mips16_stub
);
6613 l
->name
= xstrdup (fnname
);
6614 l
->fp_ret_p
= fp_ret_p
;
6615 l
->next
= mips16_stubs
;
6619 /* If we expect a floating-point return value, but we've built a
6620 stub which does not expect one, then we're in trouble. We can't
6621 use the existing stub, because it won't handle the floating-point
6622 value. We can't build a new stub, because the linker won't know
6623 which stub to use for the various calls in this object file.
6624 Fortunately, this case is illegal, since it means that a function
6625 was declared in two different ways in a single compilation. */
6626 if (fp_ret_p
&& !l
->fp_ret_p
)
6627 error ("cannot handle inconsistent calls to %qs", fnname
);
6629 if (retval
== NULL_RTX
)
6630 insn
= gen_call_internal_direct (fn
, args_size
);
6632 insn
= gen_call_value_internal_direct (retval
, fn
, args_size
);
6633 insn
= mips_emit_call_insn (insn
, fn
, fn
, false);
6635 /* If we are calling a stub which handles a floating-point return
6636 value, we need to arrange to save $18 in the prologue. We do this
6637 by marking the function call as using the register. The prologue
6638 will later see that it is used, and emit code to save it. */
6640 CALL_INSN_FUNCTION_USAGE (insn
) =
6641 gen_rtx_EXPR_LIST (VOIDmode
,
6642 gen_rtx_CLOBBER (VOIDmode
,
6643 gen_rtx_REG (word_mode
, 18)),
6644 CALL_INSN_FUNCTION_USAGE (insn
));
6649 /* Expand a call of type TYPE. RESULT is where the result will go (null
6650 for "call"s and "sibcall"s), ADDR is the address of the function,
6651 ARGS_SIZE is the size of the arguments and AUX is the value passed
6652 to us by mips_function_arg. LAZY_P is true if this call already
6653 involves a lazily-bound function address (such as when calling
6654 functions through a MIPS16 hard-float stub).
6656 Return the call itself. */
6659 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
6660 rtx args_size
, rtx aux
, bool lazy_p
)
6662 rtx orig_addr
, pattern
, insn
;
6665 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
6666 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
6669 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
6674 if (!call_insn_operand (addr
, VOIDmode
))
6676 if (type
== MIPS_CALL_EPILOGUE
)
6677 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
6679 addr
= gen_reg_rtx (Pmode
);
6680 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
6685 rtx (*fn
) (rtx
, rtx
);
6687 if (type
== MIPS_CALL_SIBCALL
)
6688 fn
= gen_sibcall_internal
;
6690 fn
= gen_call_internal
;
6692 pattern
= fn (addr
, args_size
);
6694 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
6696 /* Handle return values created by mips_return_fpr_pair. */
6697 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
6700 if (type
== MIPS_CALL_SIBCALL
)
6701 fn
= gen_sibcall_value_multiple_internal
;
6703 fn
= gen_call_value_multiple_internal
;
6705 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
6706 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
6707 pattern
= fn (reg1
, addr
, args_size
, reg2
);
6711 rtx (*fn
) (rtx
, rtx
, rtx
);
6713 if (type
== MIPS_CALL_SIBCALL
)
6714 fn
= gen_sibcall_value_internal
;
6716 fn
= gen_call_value_internal
;
6718 /* Handle return values created by mips_return_fpr_single. */
6719 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
6720 result
= XEXP (XVECEXP (result
, 0, 0), 0);
6721 pattern
= fn (result
, addr
, args_size
);
6724 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
6727 /* Split call instruction INSN into a $gp-clobbering call and
6728 (where necessary) an instruction to restore $gp from its save slot.
6729 CALL_PATTERN is the pattern of the new call. */
6732 mips_split_call (rtx insn
, rtx call_pattern
)
6734 emit_call_insn (call_pattern
);
6735 if (!find_reg_note (insn
, REG_NORETURN
, 0))
6736 /* Pick a temporary register that is suitable for both MIPS16 and
6737 non-MIPS16 code. $4 and $5 are used for returning complex double
6738 values in soft-float code, so $6 is the first suitable candidate. */
6739 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 2));
6742 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6745 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
6747 if (!TARGET_SIBCALLS
)
6750 /* Interrupt handlers need special epilogue code and therefore can't
6752 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
6755 /* We can't do a sibcall if the called function is a MIPS16 function
6756 because there is no direct "jx" instruction equivalent to "jalx" to
6757 switch the ISA mode. We only care about cases where the sibling
6758 and normal calls would both be direct. */
6760 && mips_use_mips16_mode_p (decl
)
6761 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
))
6764 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6765 functions could be MIPS16 ones unless an attribute explicitly tells
6767 if (TARGET_INTERLINK_MIPS16
6769 && (DECL_EXTERNAL (decl
) || !targetm
.binds_local_p (decl
))
6770 && !mips_nomips16_decl_p (decl
)
6771 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
))
6778 /* Emit code to move general operand SRC into condition-code
6779 register DEST given that SCRATCH is a scratch TFmode FPR.
6786 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6789 mips_expand_fcc_reload (rtx dest
, rtx src
, rtx scratch
)
6793 /* Change the source to SFmode. */
6795 src
= adjust_address (src
, SFmode
, 0);
6796 else if (REG_P (src
) || GET_CODE (src
) == SUBREG
)
6797 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
6799 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
6800 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + MAX_FPRS_PER_FMT
);
6802 mips_emit_move (copy_rtx (fp1
), src
);
6803 mips_emit_move (copy_rtx (fp2
), CONST0_RTX (SFmode
));
6804 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
6807 /* Implement MOVE_BY_PIECES_P. */
6810 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
6814 /* movmemsi is meant to generate code that is at least as good as
6815 move_by_pieces. However, movmemsi effectively uses a by-pieces
6816 implementation both for moves smaller than a word and for
6817 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
6818 bytes. We should allow the tree-level optimisers to do such
6819 moves by pieces, as it often exposes other optimization
6820 opportunities. We might as well continue to use movmemsi at
6821 the rtl level though, as it produces better code when
6822 scheduling is disabled (such as at -O). */
6823 if (currently_expanding_to_rtl
)
6825 if (align
< BITS_PER_WORD
)
6826 return size
< UNITS_PER_WORD
;
6827 return size
<= MIPS_MAX_MOVE_BYTES_STRAIGHT
;
6829 /* The default value. If this becomes a target hook, we should
6830 call the default definition instead. */
6831 return (move_by_pieces_ninsns (size
, align
, MOVE_MAX_PIECES
+ 1)
6832 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
6835 /* Implement STORE_BY_PIECES_P. */
6838 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
6840 /* Storing by pieces involves moving constants into registers
6841 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
6842 We need to decide whether it is cheaper to load the address of
6843 constant data into a register and use a block move instead. */
6845 /* If the data is only byte aligned, then:
6847 (a1) A block move of less than 4 bytes would involve three 3 LBs and
6848 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
6851 (a2) A block move of 4 bytes from aligned source data can use an
6852 LW/SWL/SWR sequence. This is often better than the 4 LIs and
6853 4 SBs that we would generate when storing by pieces. */
6854 if (align
<= BITS_PER_UNIT
)
6857 /* If the data is 2-byte aligned, then:
6859 (b1) A block move of less than 4 bytes would use a combination of LBs,
6860 LHs, SBs and SHs. We get better code by using single-instruction
6861 LIs, SBs and SHs instead.
6863 (b2) A block move of 4 bytes from aligned source data would again use
6864 an LW/SWL/SWR sequence. In most cases, loading the address of
6865 the source data would require at least one extra instruction.
6866 It is often more efficient to use 2 single-instruction LIs and
6869 (b3) A block move of up to 3 additional bytes would be like (b1).
6871 (b4) A block move of 8 bytes from aligned source data can use two
6872 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
6873 sequences are better than the 4 LIs and 4 SHs that we'd generate
6874 when storing by pieces.
6876 The reasoning for higher alignments is similar:
6878 (c1) A block move of less than 4 bytes would be the same as (b1).
6880 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
6881 loading the address of the source data would typically require
6882 at least one extra instruction. It is generally better to use
6885 (c3) A block move of up to 3 additional bytes would be like (b1).
6887 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
6888 LD/SD sequence, and in these cases we've traditionally preferred
6889 the memory copy over the more bulky constant moves. */
6893 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6894 Assume that the areas do not overlap. */
6897 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
6899 HOST_WIDE_INT offset
, delta
;
6900 unsigned HOST_WIDE_INT bits
;
6902 enum machine_mode mode
;
6905 /* Work out how many bits to move at a time. If both operands have
6906 half-word alignment, it is usually better to move in half words.
6907 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6908 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6909 Otherwise move word-sized chunks. */
6910 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
6911 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
6912 bits
= BITS_PER_WORD
/ 2;
6914 bits
= BITS_PER_WORD
;
6916 mode
= mode_for_size (bits
, MODE_INT
, 0);
6917 delta
= bits
/ BITS_PER_UNIT
;
6919 /* Allocate a buffer for the temporary registers. */
6920 regs
= XALLOCAVEC (rtx
, length
/ delta
);
6922 /* Load as many BITS-sized chunks as possible. Use a normal load if
6923 the source has enough alignment, otherwise use left/right pairs. */
6924 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
6926 regs
[i
] = gen_reg_rtx (mode
);
6927 if (MEM_ALIGN (src
) >= bits
)
6928 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
6931 rtx part
= adjust_address (src
, BLKmode
, offset
);
6932 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0, 0))
6937 /* Copy the chunks to the destination. */
6938 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
6939 if (MEM_ALIGN (dest
) >= bits
)
6940 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
6943 rtx part
= adjust_address (dest
, BLKmode
, offset
);
6944 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
6948 /* Mop up any left-over bytes. */
6949 if (offset
< length
)
6951 src
= adjust_address (src
, BLKmode
, offset
);
6952 dest
= adjust_address (dest
, BLKmode
, offset
);
6953 move_by_pieces (dest
, src
, length
- offset
,
6954 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
6958 /* Helper function for doing a loop-based block operation on memory
6959 reference MEM. Each iteration of the loop will operate on LENGTH
6962 Create a new base register for use within the loop and point it to
6963 the start of MEM. Create a new memory reference that uses this
6964 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6967 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
6968 rtx
*loop_reg
, rtx
*loop_mem
)
6970 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
6972 /* Although the new mem does not refer to a known location,
6973 it does keep up to LENGTH bytes of alignment. */
6974 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
6975 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
6978 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6979 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6980 the memory regions do not overlap. */
6983 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
6984 HOST_WIDE_INT bytes_per_iter
)
6986 rtx label
, src_reg
, dest_reg
, final_src
, test
;
6987 HOST_WIDE_INT leftover
;
6989 leftover
= length
% bytes_per_iter
;
6992 /* Create registers and memory references for use within the loop. */
6993 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
6994 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
6996 /* Calculate the value that SRC_REG should have after the last iteration
6998 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
7001 /* Emit the start of the loop. */
7002 label
= gen_label_rtx ();
7005 /* Emit the loop body. */
7006 mips_block_move_straight (dest
, src
, bytes_per_iter
);
7008 /* Move on to the next block. */
7009 mips_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
7010 mips_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
7012 /* Emit the loop condition. */
7013 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
7014 if (Pmode
== DImode
)
7015 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
7017 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
7019 /* Mop up any left-over bytes. */
7021 mips_block_move_straight (dest
, src
, leftover
);
7024 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7025 memory reference SRC to memory reference DEST. */
7028 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
7030 if (CONST_INT_P (length
))
7032 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
7034 mips_block_move_straight (dest
, src
, INTVAL (length
));
7039 mips_block_move_loop (dest
, src
, INTVAL (length
),
7040 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
7047 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7050 mips_expand_synci_loop (rtx begin
, rtx end
)
7052 rtx inc
, label
, end_label
, cmp_result
, mask
, length
;
7054 /* Create end_label. */
7055 end_label
= gen_label_rtx ();
7057 /* Check if begin equals end. */
7058 cmp_result
= gen_rtx_EQ (VOIDmode
, begin
, end
);
7059 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7061 /* Load INC with the cache line size (rdhwr INC,$1). */
7062 inc
= gen_reg_rtx (Pmode
);
7063 emit_insn (PMODE_INSN (gen_rdhwr_synci_step
, (inc
)));
7065 /* Check if inc is 0. */
7066 cmp_result
= gen_rtx_EQ (VOIDmode
, inc
, const0_rtx
);
7067 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7069 /* Calculate mask. */
7070 mask
= mips_force_unary (Pmode
, NEG
, inc
);
7072 /* Mask out begin by mask. */
7073 begin
= mips_force_binary (Pmode
, AND
, begin
, mask
);
7075 /* Calculate length. */
7076 length
= mips_force_binary (Pmode
, MINUS
, end
, begin
);
7078 /* Loop back to here. */
7079 label
= gen_label_rtx ();
7082 emit_insn (gen_synci (begin
));
7084 /* Update length. */
7085 mips_emit_binary (MINUS
, length
, length
, inc
);
7088 mips_emit_binary (PLUS
, begin
, begin
, inc
);
7090 /* Check if length is greater than 0. */
7091 cmp_result
= gen_rtx_GT (VOIDmode
, length
, const0_rtx
);
7092 emit_jump_insn (gen_condjump (cmp_result
, label
));
7094 emit_label (end_label
);
7097 /* Expand a QI or HI mode atomic memory operation.
7099 GENERATOR contains a pointer to the gen_* function that generates
7100 the SI mode underlying atomic operation using masks that we
7103 RESULT is the return register for the operation. Its value is NULL
7106 MEM is the location of the atomic access.
7108 OLDVAL is the first operand for the operation.
7110 NEWVAL is the optional second operand for the operation. Its value
7111 is NULL if unused. */
7114 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
7115 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
7117 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
7118 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
7120 enum machine_mode mode
;
7122 mode
= GET_MODE (mem
);
7124 /* Compute the address of the containing SImode value. */
7125 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
7126 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
7127 force_reg (Pmode
, GEN_INT (-4)));
7129 /* Create a memory reference for it. */
7130 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
7131 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
7132 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
7134 /* Work out the byte offset of the QImode or HImode value,
7135 counting from the least significant byte. */
7136 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
7137 if (TARGET_BIG_ENDIAN
)
7138 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
7140 /* Multiply by eight to convert the shift value from bytes to bits. */
7141 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
7143 /* Make the final shift an SImode value, so that it can be used in
7144 SImode operations. */
7145 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
7147 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7148 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
7149 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
7150 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
7152 /* Compute the equivalent exclusive mask. */
7153 inverted_mask
= gen_reg_rtx (SImode
);
7154 emit_insn (gen_rtx_SET (VOIDmode
, inverted_mask
,
7155 gen_rtx_NOT (SImode
, mask
)));
7157 /* Shift the old value into place. */
7158 if (oldval
!= const0_rtx
)
7160 oldval
= convert_modes (SImode
, mode
, oldval
, true);
7161 oldval
= force_reg (SImode
, oldval
);
7162 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
7165 /* Do the same for the new value. */
7166 if (newval
&& newval
!= const0_rtx
)
7168 newval
= convert_modes (SImode
, mode
, newval
, true);
7169 newval
= force_reg (SImode
, newval
);
7170 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
7173 /* Do the SImode atomic access. */
7175 res
= gen_reg_rtx (SImode
);
7177 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
7179 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
7181 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
7187 /* Shift and convert the result. */
7188 mips_emit_binary (AND
, res
, res
, mask
);
7189 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
7190 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
7194 /* Return true if it is possible to use left/right accesses for a
7195 bitfield of WIDTH bits starting BITPOS bits into *OP. When
7196 returning true, update *OP, *LEFT and *RIGHT as follows:
7198 *OP is a BLKmode reference to the whole field.
7200 *LEFT is a QImode reference to the first byte if big endian or
7201 the last byte if little endian. This address can be used in the
7202 left-side instructions (LWL, SWL, LDL, SDL).
7204 *RIGHT is a QImode reference to the opposite end of the field and
7205 can be used in the patterning right-side instruction. */
7208 mips_get_unaligned_mem (rtx
*op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
7209 rtx
*left
, rtx
*right
)
7213 /* Check that the operand really is a MEM. Not all the extv and
7214 extzv predicates are checked. */
7218 /* Check that the size is valid. */
7219 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
7222 /* We can only access byte-aligned values. Since we are always passed
7223 a reference to the first byte of the field, it is not necessary to
7224 do anything with BITPOS after this check. */
7225 if (bitpos
% BITS_PER_UNIT
!= 0)
7228 /* Reject aligned bitfields: we want to use a normal load or store
7229 instead of a left/right pair. */
7230 if (MEM_ALIGN (*op
) >= width
)
7233 /* Create a copy of *OP that refers to the whole field. This also has
7234 the effect of legitimizing *OP's address for BLKmode, possibly
7236 *op
= copy_rtx (adjust_address (*op
, BLKmode
, 0));
7237 set_mem_size (*op
, width
/ BITS_PER_UNIT
);
7239 /* Get references to both ends of the field. We deliberately don't
7240 use the original QImode *OP for FIRST since the new BLKmode one
7241 might have a simpler address. */
7242 first
= adjust_address (*op
, QImode
, 0);
7243 last
= adjust_address (*op
, QImode
, width
/ BITS_PER_UNIT
- 1);
7245 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7246 correspond to the MSB and RIGHT to the LSB. */
7247 if (TARGET_BIG_ENDIAN
)
7248 *left
= first
, *right
= last
;
7250 *left
= last
, *right
= first
;
7255 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7256 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7257 the operation is the equivalent of:
7259 (set DEST (*_extract SRC WIDTH BITPOS))
7261 Return true on success. */
7264 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7265 HOST_WIDE_INT bitpos
, bool unsigned_p
)
7267 rtx left
, right
, temp
;
7268 rtx dest1
= NULL_RTX
;
7270 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7271 be a paradoxical word_mode subreg. This is the only case in which
7272 we allow the destination to be larger than the source. */
7273 if (GET_CODE (dest
) == SUBREG
7274 && GET_MODE (dest
) == DImode
7275 && GET_MODE (SUBREG_REG (dest
)) == SImode
)
7276 dest
= SUBREG_REG (dest
);
7278 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7279 be a DImode, create a new temp and emit a zero extend at the end. */
7280 if (GET_MODE (dest
) == DImode
7282 && GET_MODE_BITSIZE (SImode
) == width
)
7285 dest
= gen_reg_rtx (SImode
);
7288 /* After the above adjustment, the destination must be the same
7289 width as the source. */
7290 if (GET_MODE_BITSIZE (GET_MODE (dest
)) != width
)
7293 if (!mips_get_unaligned_mem (&src
, width
, bitpos
, &left
, &right
))
7296 temp
= gen_reg_rtx (GET_MODE (dest
));
7297 if (GET_MODE (dest
) == DImode
)
7299 emit_insn (gen_mov_ldl (temp
, src
, left
));
7300 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
7304 emit_insn (gen_mov_lwl (temp
, src
, left
));
7305 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
7308 /* If we were loading 32bits and the original register was DI then
7309 sign/zero extend into the orignal dest. */
7313 emit_insn (gen_zero_extendsidi2 (dest1
, dest
));
7315 emit_insn (gen_extendsidi2 (dest1
, dest
));
7320 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7321 BITPOS and SRC are the operands passed to the expander; the operation
7322 is the equivalent of:
7324 (set (zero_extract DEST WIDTH BITPOS) SRC)
7326 Return true on success. */
7329 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7330 HOST_WIDE_INT bitpos
)
7333 enum machine_mode mode
;
7335 if (!mips_get_unaligned_mem (&dest
, width
, bitpos
, &left
, &right
))
7338 mode
= mode_for_size (width
, MODE_INT
, 0);
7339 src
= gen_lowpart (mode
, src
);
7342 emit_insn (gen_mov_sdl (dest
, src
, left
));
7343 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
7347 emit_insn (gen_mov_swl (dest
, src
, left
));
7348 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
7353 /* Return true if X is a MEM with the same size as MODE. */
7356 mips_mem_fits_mode_p (enum machine_mode mode
, rtx x
)
7359 && MEM_SIZE_KNOWN_P (x
)
7360 && MEM_SIZE (x
) == GET_MODE_SIZE (mode
));
7363 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7364 source of an "ext" instruction or the destination of an "ins"
7365 instruction. OP must be a register operand and the following
7366 conditions must hold:
7368 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7369 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7370 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7372 Also reject lengths equal to a word as they are better handled
7373 by the move patterns. */
7376 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
7378 if (!ISA_HAS_EXT_INS
7379 || !register_operand (op
, VOIDmode
)
7380 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
7383 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
7386 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
7392 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7393 operation if MAXLEN is the maxium length of consecutive bits that
7394 can make up MASK. MODE is the mode of the operation. See
7395 mask_low_and_shift_len for the actual definition. */
7398 mask_low_and_shift_p (enum machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
7400 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
7403 /* Return true iff OP1 and OP2 are valid operands together for the
7404 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7405 see the table in the comment before the pattern. */
7408 and_operands_ok (enum machine_mode mode
, rtx op1
, rtx op2
)
7410 return (memory_operand (op1
, mode
)
7411 ? and_load_operand (op2
, mode
)
7412 : and_reg_operand (op2
, mode
));
7415 /* The canonical form of a mask-low-and-shift-left operation is
7416 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7417 cleared. Thus we need to shift MASK to the right before checking if it
7418 is a valid mask value. MODE is the mode of the operation. If true
7419 return the length of the mask, otherwise return -1. */
7422 mask_low_and_shift_len (enum machine_mode mode
, rtx mask
, rtx shift
)
7424 HOST_WIDE_INT shval
;
7426 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
7427 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
7430 /* Return true if -msplit-addresses is selected and should be honored.
7432 -msplit-addresses is a half-way house between explicit relocations
7433 and the traditional assembler macros. It can split absolute 32-bit
7434 symbolic constants into a high/lo_sum pair but uses macros for other
7437 Like explicit relocation support for REL targets, it relies
7438 on GNU extensions in the assembler and the linker.
7440 Although this code should work for -O0, it has traditionally
7441 been treated as an optimization. */
7444 mips_split_addresses_p (void)
7446 return (TARGET_SPLIT_ADDRESSES
7450 && !ABI_HAS_64BIT_SYMBOLS
);
7453 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7456 mips_init_relocs (void)
7458 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
7459 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
7460 memset (mips_use_pcrel_pool_p
, '\0', sizeof (mips_use_pcrel_pool_p
));
7461 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
7462 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
7464 if (TARGET_MIPS16_PCREL_LOADS
)
7465 mips_use_pcrel_pool_p
[SYMBOL_ABSOLUTE
] = true;
7468 if (ABI_HAS_64BIT_SYMBOLS
)
7470 if (TARGET_EXPLICIT_RELOCS
)
7472 mips_split_p
[SYMBOL_64_HIGH
] = true;
7473 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
7474 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
7476 mips_split_p
[SYMBOL_64_MID
] = true;
7477 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
7478 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
7480 mips_split_p
[SYMBOL_64_LOW
] = true;
7481 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
7482 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
7484 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7485 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7490 if (TARGET_EXPLICIT_RELOCS
7491 || mips_split_addresses_p ()
7494 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7495 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
7496 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7503 /* The high part is provided by a pseudo copy of $gp. */
7504 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
7505 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
7507 else if (TARGET_EXPLICIT_RELOCS
)
7508 /* Small data constants are kept whole until after reload,
7509 then lowered by mips_rewrite_small_data. */
7510 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
7512 if (TARGET_EXPLICIT_RELOCS
)
7514 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7517 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
7518 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
7522 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
7523 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
7526 /* Expose the use of $28 as soon as possible. */
7527 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7531 /* The HIGH and LO_SUM are matched by special .md patterns. */
7532 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7534 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
7535 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
7536 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
7538 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
7539 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
7540 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
7545 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
7547 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
7548 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
7550 /* Expose the use of $28 as soon as possible. */
7551 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7557 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
7558 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
7559 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
7562 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
7563 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
7565 if (TARGET_MIPS16_PCREL_LOADS
)
7567 mips_use_pcrel_pool_p
[SYMBOL_DTPREL
] = true;
7568 mips_use_pcrel_pool_p
[SYMBOL_TPREL
] = true;
7572 mips_split_p
[SYMBOL_DTPREL
] = true;
7573 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
7574 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
7576 mips_split_p
[SYMBOL_TPREL
] = true;
7577 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
7578 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
7581 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
7582 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
7585 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7586 in context CONTEXT. RELOCS is the array of relocations to use. */
7589 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
7590 const char **relocs
)
7592 enum mips_symbol_type symbol_type
;
7595 symbol_type
= mips_classify_symbolic_expression (op
, context
);
7596 gcc_assert (relocs
[symbol_type
]);
7598 fputs (relocs
[symbol_type
], file
);
7599 output_addr_const (file
, mips_strip_unspec_address (op
));
7600 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
7605 /* Start a new block with the given asm switch enabled. If we need
7606 to print a directive, emit PREFIX before it and SUFFIX after it. */
7609 mips_push_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7610 const char *prefix
, const char *suffix
)
7612 if (asm_switch
->nesting_level
== 0)
7613 fprintf (asm_out_file
, "%s.set\tno%s%s", prefix
, asm_switch
->name
, suffix
);
7614 asm_switch
->nesting_level
++;
7617 /* Likewise, but end a block. */
7620 mips_pop_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7621 const char *prefix
, const char *suffix
)
7623 gcc_assert (asm_switch
->nesting_level
);
7624 asm_switch
->nesting_level
--;
7625 if (asm_switch
->nesting_level
== 0)
7626 fprintf (asm_out_file
, "%s.set\t%s%s", prefix
, asm_switch
->name
, suffix
);
7629 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7630 that either print a complete line or print nothing. */
7633 mips_push_asm_switch (struct mips_asm_switch
*asm_switch
)
7635 mips_push_asm_switch_1 (asm_switch
, "\t", "\n");
7639 mips_pop_asm_switch (struct mips_asm_switch
*asm_switch
)
7641 mips_pop_asm_switch_1 (asm_switch
, "\t", "\n");
7644 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7645 The punctuation characters are:
7647 '(' Start a nested ".set noreorder" block.
7648 ')' End a nested ".set noreorder" block.
7649 '[' Start a nested ".set noat" block.
7650 ']' End a nested ".set noat" block.
7651 '<' Start a nested ".set nomacro" block.
7652 '>' End a nested ".set nomacro" block.
7653 '*' Behave like %(%< if generating a delayed-branch sequence.
7654 '#' Print a nop if in a ".set noreorder" block.
7655 '/' Like '#', but do nothing within a delayed-branch sequence.
7656 '?' Print "l" if mips_branch_likely is true
7657 '~' Print a nop if mips_branch_likely is true
7658 '.' Print the name of the register with a hard-wired zero (zero or $0).
7659 '@' Print the name of the assembler temporary register (at or $1).
7660 '^' Print the name of the pic call-through register (t9 or $25).
7661 '+' Print the name of the gp register (usually gp or $28).
7662 '$' Print the name of the stack pointer register (sp or $29).
7664 See also mips_init_print_operand_pucnt. */
7667 mips_print_operand_punctuation (FILE *file
, int ch
)
7672 mips_push_asm_switch_1 (&mips_noreorder
, "", "\n\t");
7676 mips_pop_asm_switch_1 (&mips_noreorder
, "\n\t", "");
7680 mips_push_asm_switch_1 (&mips_noat
, "", "\n\t");
7684 mips_pop_asm_switch_1 (&mips_noat
, "\n\t", "");
7688 mips_push_asm_switch_1 (&mips_nomacro
, "", "\n\t");
7692 mips_pop_asm_switch_1 (&mips_nomacro
, "\n\t", "");
7696 if (final_sequence
!= 0)
7698 mips_print_operand_punctuation (file
, '(');
7699 mips_print_operand_punctuation (file
, '<');
7704 if (mips_noreorder
.nesting_level
> 0)
7705 fputs ("\n\tnop", file
);
7709 /* Print an extra newline so that the delayed insn is separated
7710 from the following ones. This looks neater and is consistent
7711 with non-nop delayed sequences. */
7712 if (mips_noreorder
.nesting_level
> 0 && final_sequence
== 0)
7713 fputs ("\n\tnop\n", file
);
7717 if (mips_branch_likely
)
7722 if (mips_branch_likely
)
7723 fputs ("\n\tnop", file
);
7727 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
7731 fputs (reg_names
[AT_REGNUM
], file
);
7735 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
7739 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
7743 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
7752 /* Initialize mips_print_operand_punct. */
7755 mips_init_print_operand_punct (void)
7759 for (p
= "()[]<>*#/?~.@^+$"; *p
; p
++)
7760 mips_print_operand_punct
[(unsigned char) *p
] = true;
7763 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7764 associated with condition CODE. Print the condition part of the
7768 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
7782 /* Conveniently, the MIPS names for these conditions are the same
7783 as their RTL equivalents. */
7784 fputs (GET_RTX_NAME (code
), file
);
7788 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
7793 /* Likewise floating-point branches. */
7796 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
7801 fputs ("c1f", file
);
7805 fputs ("c1t", file
);
7809 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
7814 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7817 mips_print_operand_punct_valid_p (unsigned char code
)
7819 return mips_print_operand_punct
[code
];
7822 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
7824 'X' Print CONST_INT OP in hexadecimal format.
7825 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7826 'd' Print CONST_INT OP in decimal.
7827 'm' Print one less than CONST_INT OP in decimal.
7828 'h' Print the high-part relocation associated with OP, after stripping
7830 'R' Print the low-part relocation associated with OP.
7831 'C' Print the integer branch condition for comparison OP.
7832 'N' Print the inverse of the integer branch condition for comparison OP.
7833 'F' Print the FPU branch condition for comparison OP.
7834 'W' Print the inverse of the FPU branch condition for comparison OP.
7835 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7836 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7837 't' Like 'T', but with the EQ/NE cases reversed
7838 'Y' Print mips_fp_conditions[INTVAL (OP)]
7839 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7840 'q' Print a DSP accumulator register.
7841 'D' Print the second part of a double-word register or memory operand.
7842 'L' Print the low-order register in a double-word register operand.
7843 'M' Print high-order register in a double-word register operand.
7844 'z' Print $0 if OP is zero, otherwise print OP normally.
7845 'b' Print the address of a memory operand, without offset. */
7848 mips_print_operand (FILE *file
, rtx op
, int letter
)
7852 if (mips_print_operand_punct_valid_p (letter
))
7854 mips_print_operand_punctuation (file
, letter
);
7859 code
= GET_CODE (op
);
7864 if (CONST_INT_P (op
))
7865 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
7867 output_operand_lossage ("invalid use of '%%%c'", letter
);
7871 if (CONST_INT_P (op
))
7872 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
7874 output_operand_lossage ("invalid use of '%%%c'", letter
);
7878 if (CONST_INT_P (op
))
7879 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
7881 output_operand_lossage ("invalid use of '%%%c'", letter
);
7885 if (CONST_INT_P (op
))
7886 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
7888 output_operand_lossage ("invalid use of '%%%c'", letter
);
7894 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
7898 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
7902 mips_print_int_branch_condition (file
, code
, letter
);
7906 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
7910 mips_print_float_branch_condition (file
, code
, letter
);
7914 mips_print_float_branch_condition (file
, reverse_condition (code
),
7921 int truth
= (code
== NE
) == (letter
== 'T');
7922 fputc ("zfnt"[truth
* 2 + (GET_MODE (op
) == CCmode
)], file
);
7927 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
7928 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
7930 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7937 mips_print_operand (file
, op
, 0);
7943 if (code
== REG
&& MD_REG_P (REGNO (op
)))
7944 fprintf (file
, "$ac0");
7945 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
7946 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
7948 output_operand_lossage ("invalid use of '%%%c'", letter
);
7956 unsigned int regno
= REGNO (op
);
7957 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
7958 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
7961 else if (letter
&& letter
!= 'z' && letter
!= 'M' && letter
!= 'L')
7962 output_operand_lossage ("invalid use of '%%%c'", letter
);
7963 /* We need to print $0 .. $31 for COP0 registers. */
7964 if (COP0_REG_P (regno
))
7965 fprintf (file
, "$%s", ®_names
[regno
][4]);
7967 fprintf (file
, "%s", reg_names
[regno
]);
7973 output_address (plus_constant (Pmode
, XEXP (op
, 0), 4));
7974 else if (letter
== 'b')
7976 gcc_assert (REG_P (XEXP (op
, 0)));
7977 mips_print_operand (file
, XEXP (op
, 0), 0);
7979 else if (letter
&& letter
!= 'z')
7980 output_operand_lossage ("invalid use of '%%%c'", letter
);
7982 output_address (XEXP (op
, 0));
7986 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
7987 fputs (reg_names
[GP_REG_FIRST
], file
);
7988 else if (letter
&& letter
!= 'z')
7989 output_operand_lossage ("invalid use of '%%%c'", letter
);
7990 else if (CONST_GP_P (op
))
7991 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
7993 output_addr_const (file
, mips_strip_unspec_address (op
));
7999 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8002 mips_print_operand_address (FILE *file
, rtx x
)
8004 struct mips_address_info addr
;
8006 if (mips_classify_address (&addr
, x
, word_mode
, true))
8010 mips_print_operand (file
, addr
.offset
, 0);
8011 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8014 case ADDRESS_LO_SUM
:
8015 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
8017 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8020 case ADDRESS_CONST_INT
:
8021 output_addr_const (file
, x
);
8022 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
8025 case ADDRESS_SYMBOLIC
:
8026 output_addr_const (file
, mips_strip_unspec_address (x
));
8032 /* Implement TARGET_ENCODE_SECTION_INFO. */
8035 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
8037 default_encode_section_info (decl
, rtl
, first
);
8039 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8041 rtx symbol
= XEXP (rtl
, 0);
8042 tree type
= TREE_TYPE (decl
);
8044 /* Encode whether the symbol is short or long. */
8045 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
8046 || mips_far_type_p (type
))
8047 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
8051 /* Implement TARGET_SELECT_RTX_SECTION. */
8054 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
8055 unsigned HOST_WIDE_INT align
)
8057 /* ??? Consider using mergeable small data sections. */
8058 if (mips_rtx_constant_in_small_data_p (mode
))
8059 return get_named_section (NULL
, ".sdata", 0);
8061 return default_elf_select_rtx_section (mode
, x
, align
);
8064 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8066 The complication here is that, with the combination TARGET_ABICALLS
8067 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8068 absolute addresses, and should therefore not be included in the
8069 read-only part of a DSO. Handle such cases by selecting a normal
8070 data section instead of a read-only one. The logic apes that in
8071 default_function_rodata_section. */
8074 mips_function_rodata_section (tree decl
)
8076 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
8077 return default_function_rodata_section (decl
);
8079 if (decl
&& DECL_SECTION_NAME (decl
))
8081 const char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
8082 if (DECL_ONE_ONLY (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
8084 char *rname
= ASTRDUP (name
);
8086 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
8088 else if (flag_function_sections
8089 && flag_data_sections
8090 && strncmp (name
, ".text.", 6) == 0)
8092 char *rname
= ASTRDUP (name
);
8093 memcpy (rname
+ 1, "data", 4);
8094 return get_section (rname
, SECTION_WRITE
, decl
);
8097 return data_section
;
8100 /* Implement TARGET_IN_SMALL_DATA_P. */
8103 mips_in_small_data_p (const_tree decl
)
8105 unsigned HOST_WIDE_INT size
;
8107 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
8110 /* We don't yet generate small-data references for -mabicalls
8111 or VxWorks RTP code. See the related -G handling in
8112 mips_option_override. */
8113 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
8116 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
8120 /* Reject anything that isn't in a known small-data section. */
8121 name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
8122 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
8125 /* If a symbol is defined externally, the assembler will use the
8126 usual -G rules when deciding how to implement macros. */
8127 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
8130 else if (TARGET_EMBEDDED_DATA
)
8132 /* Don't put constants into the small data section: we want them
8133 to be in ROM rather than RAM. */
8134 if (TREE_CODE (decl
) != VAR_DECL
)
8137 if (TREE_READONLY (decl
)
8138 && !TREE_SIDE_EFFECTS (decl
)
8139 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
8143 /* Enforce -mlocal-sdata. */
8144 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
8147 /* Enforce -mextern-sdata. */
8148 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
8150 if (DECL_EXTERNAL (decl
))
8152 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
8156 /* We have traditionally not treated zero-sized objects as small data,
8157 so this is now effectively part of the ABI. */
8158 size
= int_size_in_bytes (TREE_TYPE (decl
));
8159 return size
> 0 && size
<= mips_small_data_threshold
;
8162 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8163 anchors for small data: the GP register acts as an anchor in that
8164 case. We also don't want to use them for PC-relative accesses,
8165 where the PC acts as an anchor. */
8168 mips_use_anchors_for_symbol_p (const_rtx symbol
)
8170 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
8172 case SYMBOL_PC_RELATIVE
:
8173 case SYMBOL_GP_RELATIVE
:
8177 return default_use_anchors_for_symbol_p (symbol
);
8181 /* The MIPS debug format wants all automatic variables and arguments
8182 to be in terms of the virtual frame pointer (stack pointer before
8183 any adjustment in the function), while the MIPS 3.0 linker wants
8184 the frame pointer to be the stack pointer after the initial
8185 adjustment. So, we do the adjustment here. The arg pointer (which
8186 is eliminated) points to the virtual frame pointer, while the frame
8187 pointer (which may be eliminated) points to the stack pointer after
8188 the initial adjustments. */
8191 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
8193 rtx offset2
= const0_rtx
;
8194 rtx reg
= eliminate_constant_term (addr
, &offset2
);
8197 offset
= INTVAL (offset2
);
8199 if (reg
== stack_pointer_rtx
8200 || reg
== frame_pointer_rtx
8201 || reg
== hard_frame_pointer_rtx
)
8203 offset
-= cfun
->machine
->frame
.total_size
;
8204 if (reg
== hard_frame_pointer_rtx
)
8205 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8211 /* Implement ASM_OUTPUT_EXTERNAL. */
8214 mips_output_external (FILE *file
, tree decl
, const char *name
)
8216 default_elf_asm_output_external (file
, decl
, name
);
8218 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8219 set in order to avoid putting out names that are never really
8221 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
8223 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
8225 /* When using assembler macros, emit .extern directives for
8226 all small-data externs so that the assembler knows how
8229 In most cases it would be safe (though pointless) to emit
8230 .externs for other symbols too. One exception is when an
8231 object is within the -G limit but declared by the user to
8232 be in a section other than .sbss or .sdata. */
8233 fputs ("\t.extern\t", file
);
8234 assemble_name (file
, name
);
8235 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
8236 int_size_in_bytes (TREE_TYPE (decl
)));
8241 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8244 mips_output_filename (FILE *stream
, const char *name
)
8246 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8248 if (write_symbols
== DWARF2_DEBUG
)
8250 else if (mips_output_filename_first_time
)
8252 mips_output_filename_first_time
= 0;
8253 num_source_filenames
+= 1;
8254 current_function_file
= name
;
8255 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8256 output_quoted_string (stream
, name
);
8257 putc ('\n', stream
);
8259 /* If we are emitting stabs, let dbxout.c handle this (except for
8260 the mips_output_filename_first_time case). */
8261 else if (write_symbols
== DBX_DEBUG
)
8263 else if (name
!= current_function_file
8264 && strcmp (name
, current_function_file
) != 0)
8266 num_source_filenames
+= 1;
8267 current_function_file
= name
;
8268 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8269 output_quoted_string (stream
, name
);
8270 putc ('\n', stream
);
8274 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8276 static void ATTRIBUTE_UNUSED
8277 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8282 fputs ("\t.dtprelword\t", file
);
8286 fputs ("\t.dtpreldword\t", file
);
8292 output_addr_const (file
, x
);
8293 fputs ("+0x8000", file
);
8296 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8299 mips_dwarf_register_span (rtx reg
)
8302 enum machine_mode mode
;
8304 /* By default, GCC maps increasing register numbers to increasing
8305 memory locations, but paired FPRs are always little-endian,
8306 regardless of the prevailing endianness. */
8307 mode
= GET_MODE (reg
);
8308 if (FP_REG_P (REGNO (reg
))
8309 && TARGET_BIG_ENDIAN
8310 && MAX_FPRS_PER_FMT
> 1
8311 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
8313 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
8314 high
= mips_subword (reg
, true);
8315 low
= mips_subword (reg
, false);
8316 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
8322 /* DSP ALU can bypass data with no delays for the following pairs. */
8323 enum insn_code dspalu_bypass_table
[][2] =
8325 {CODE_FOR_mips_addsc
, CODE_FOR_mips_addwc
},
8326 {CODE_FOR_mips_cmpu_eq_qb
, CODE_FOR_mips_pick_qb
},
8327 {CODE_FOR_mips_cmpu_lt_qb
, CODE_FOR_mips_pick_qb
},
8328 {CODE_FOR_mips_cmpu_le_qb
, CODE_FOR_mips_pick_qb
},
8329 {CODE_FOR_mips_cmp_eq_ph
, CODE_FOR_mips_pick_ph
},
8330 {CODE_FOR_mips_cmp_lt_ph
, CODE_FOR_mips_pick_ph
},
8331 {CODE_FOR_mips_cmp_le_ph
, CODE_FOR_mips_pick_ph
},
8332 {CODE_FOR_mips_wrdsp
, CODE_FOR_mips_insv
}
8336 mips_dspalu_bypass_p (rtx out_insn
, rtx in_insn
)
8339 int num_bypass
= ARRAY_SIZE (dspalu_bypass_table
);
8340 enum insn_code out_icode
= (enum insn_code
) INSN_CODE (out_insn
);
8341 enum insn_code in_icode
= (enum insn_code
) INSN_CODE (in_insn
);
8343 for (i
= 0; i
< num_bypass
; i
++)
8345 if (out_icode
== dspalu_bypass_table
[i
][0]
8346 && in_icode
== dspalu_bypass_table
[i
][1])
8352 /* Implement ASM_OUTPUT_ASCII. */
8355 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
8361 fprintf (stream
, "\t.ascii\t\"");
8362 for (i
= 0; i
< len
; i
++)
8366 c
= (unsigned char) string
[i
];
8369 if (c
== '\\' || c
== '\"')
8371 putc ('\\', stream
);
8379 fprintf (stream
, "\\%03o", c
);
8383 if (cur_pos
> 72 && i
+1 < len
)
8386 fprintf (stream
, "\"\n\t.ascii\t\"");
8389 fprintf (stream
, "\"\n");
8392 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8393 Update *ADDR with the operand that should be printed. */
8396 mips_output_tls_reloc_directive (rtx
*addr
)
8398 enum mips_symbol_type type
;
8400 type
= mips_classify_symbolic_expression (*addr
, SYMBOL_CONTEXT_LEA
);
8401 *addr
= mips_strip_unspec_address (*addr
);
8405 return Pmode
== SImode
? ".dtprelword\t%0" : ".dtpreldword\t%0";
8408 return Pmode
== SImode
? ".tprelword\t%0" : ".tpreldword\t%0";
8415 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8416 macros, mark the symbol as written so that mips_asm_output_external
8417 won't emit an .extern for it. STREAM is the output file, NAME is the
8418 name of the symbol, INIT_STRING is the string that should be written
8419 before the symbol and FINAL_STRING is the string that should be
8420 written after it. FINAL_STRING is a printf format that consumes the
8421 remaining arguments. */
8424 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
8425 const char *final_string
, ...)
8429 fputs (init_string
, stream
);
8430 assemble_name (stream
, name
);
8431 va_start (ap
, final_string
);
8432 vfprintf (stream
, final_string
, ap
);
8435 if (!TARGET_EXPLICIT_RELOCS
)
8437 tree name_tree
= get_identifier (name
);
8438 TREE_ASM_WRITTEN (name_tree
) = 1;
8442 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8443 NAME is the name of the object and ALIGN is the required alignment
8444 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8445 alignment argument. */
8448 mips_declare_common_object (FILE *stream
, const char *name
,
8449 const char *init_string
,
8450 unsigned HOST_WIDE_INT size
,
8451 unsigned int align
, bool takes_alignment_p
)
8453 if (!takes_alignment_p
)
8455 size
+= (align
/ BITS_PER_UNIT
) - 1;
8456 size
-= size
% (align
/ BITS_PER_UNIT
);
8457 mips_declare_object (stream
, name
, init_string
,
8458 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
8461 mips_declare_object (stream
, name
, init_string
,
8462 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
8463 size
, align
/ BITS_PER_UNIT
);
8466 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8467 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8470 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
8471 unsigned HOST_WIDE_INT size
,
8474 /* If the target wants uninitialized const declarations in
8475 .rdata then don't put them in .comm. */
8476 if (TARGET_EMBEDDED_DATA
8477 && TARGET_UNINIT_CONST_IN_RODATA
8478 && TREE_CODE (decl
) == VAR_DECL
8479 && TREE_READONLY (decl
)
8480 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
8482 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
8483 targetm
.asm_out
.globalize_label (stream
, name
);
8485 switch_to_section (readonly_data_section
);
8486 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
8487 mips_declare_object (stream
, name
, "",
8488 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
8492 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
8496 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8497 extern int size_directive_output
;
8499 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8500 definitions except that it uses mips_declare_object to emit the label. */
8503 mips_declare_object_name (FILE *stream
, const char *name
,
8504 tree decl ATTRIBUTE_UNUSED
)
8506 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8507 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
8510 size_directive_output
= 0;
8511 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
8515 size_directive_output
= 1;
8516 size
= int_size_in_bytes (TREE_TYPE (decl
));
8517 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8520 mips_declare_object (stream
, name
, "", ":\n");
8523 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8526 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
8530 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
8531 if (!flag_inhibit_size_directive
8532 && DECL_SIZE (decl
) != 0
8535 && DECL_INITIAL (decl
) == error_mark_node
8536 && !size_directive_output
)
8540 size_directive_output
= 1;
8541 size
= int_size_in_bytes (TREE_TYPE (decl
));
8542 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8547 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8548 with the current ABI. */
8551 mips_mdebug_abi_name (void)
8564 return TARGET_64BIT
? "eabi64" : "eabi32";
8570 /* Implement TARGET_ASM_FILE_START. */
8573 mips_file_start (void)
8575 default_file_start ();
8577 /* Generate a special section to describe the ABI switches used to
8578 produce the resultant binary. */
8580 /* Record the ABI itself. Modern versions of binutils encode
8581 this information in the ELF header flags, but GDB needs the
8582 information in order to correctly debug binaries produced by
8583 older binutils. See the function mips_gdbarch_init in
8585 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
8586 mips_mdebug_abi_name ());
8588 /* There is no ELF header flag to distinguish long32 forms of the
8589 EABI from long64 forms. Emit a special section to help tools
8590 such as GDB. Do the same for o64, which is sometimes used with
8592 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
8593 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
8594 "\t.previous\n", TARGET_LONG64
? 64 : 32);
8596 #ifdef HAVE_AS_GNU_ATTRIBUTE
8600 /* No floating-point operations, -mno-float. */
8601 if (TARGET_NO_FLOAT
)
8603 /* Soft-float code, -msoft-float. */
8604 else if (!TARGET_HARD_FLOAT_ABI
)
8606 /* Single-float code, -msingle-float. */
8607 else if (!TARGET_DOUBLE_FLOAT
)
8609 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8610 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
8612 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8616 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", attr
);
8620 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8621 if (TARGET_ABICALLS
)
8623 fprintf (asm_out_file
, "\t.abicalls\n");
8624 if (TARGET_ABICALLS_PIC0
)
8625 fprintf (asm_out_file
, "\t.option\tpic0\n");
8628 if (flag_verbose_asm
)
8629 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8631 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
8634 /* Implement TARGET_ASM_CODE_END. */
8637 mips_code_end (void)
8639 if (mips_need_mips16_rdhwr_p
)
8640 mips_output_mips16_rdhwr ();
8643 /* Make the last instruction frame-related and note that it performs
8644 the operation described by FRAME_PATTERN. */
8647 mips_set_frame_expr (rtx frame_pattern
)
8651 insn
= get_last_insn ();
8652 RTX_FRAME_RELATED_P (insn
) = 1;
8653 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
8658 /* Return a frame-related rtx that stores REG at MEM.
8659 REG must be a single register. */
8662 mips_frame_set (rtx mem
, rtx reg
)
8666 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
8667 RTX_FRAME_RELATED_P (set
) = 1;
8672 /* Record that the epilogue has restored call-saved register REG. */
8675 mips_add_cfa_restore (rtx reg
)
8677 mips_epilogue
.cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
8678 mips_epilogue
.cfa_restores
);
8681 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8682 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8683 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8684 static const unsigned char mips16e_s2_s8_regs
[] = {
8685 30, 23, 22, 21, 20, 19, 18
8687 static const unsigned char mips16e_a0_a3_regs
[] = {
8691 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8692 ordered from the uppermost in memory to the lowest in memory. */
8693 static const unsigned char mips16e_save_restore_regs
[] = {
8694 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8697 /* Return the index of the lowest X in the range [0, SIZE) for which
8698 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8701 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
8706 for (i
= 0; i
< size
; i
++)
8707 if (BITSET_P (mask
, regs
[i
]))
8713 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8714 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8715 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8716 is true for all indexes (X, SIZE). */
8719 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
8720 unsigned int size
, unsigned int *num_regs_ptr
)
8724 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
8725 for (i
++; i
< size
; i
++)
8726 if (!BITSET_P (*mask_ptr
, regs
[i
]))
8729 *mask_ptr
|= 1 << regs
[i
];
8733 /* Return a simplified form of X using the register values in REG_VALUES.
8734 REG_VALUES[R] is the last value assigned to hard register R, or null
8735 if R has not been modified.
8737 This function is rather limited, but is good enough for our purposes. */
8740 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
8742 x
= avoid_constant_pool_reference (x
);
8746 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
8747 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
8748 x0
, GET_MODE (XEXP (x
, 0)));
8751 if (ARITHMETIC_P (x
))
8753 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
8754 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
8755 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
8759 && reg_values
[REGNO (x
)]
8760 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
8761 return reg_values
[REGNO (x
)];
8766 /* Return true if (set DEST SRC) stores an argument register into its
8767 caller-allocated save slot, storing the number of that argument
8768 register in *REGNO_PTR if so. REG_VALUES is as for
8769 mips16e_collect_propagate_value. */
8772 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
8773 unsigned int *regno_ptr
)
8775 unsigned int argno
, regno
;
8776 HOST_WIDE_INT offset
, required_offset
;
8779 /* Check that this is a word-mode store. */
8780 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
8783 /* Check that the register being saved is an unmodified argument
8785 regno
= REGNO (src
);
8786 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
8788 argno
= regno
- GP_ARG_FIRST
;
8790 /* Check whether the address is an appropriate stack-pointer or
8791 frame-pointer access. */
8792 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
8793 mips_split_plus (addr
, &base
, &offset
);
8794 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
8795 if (base
== hard_frame_pointer_rtx
)
8796 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8797 else if (base
!= stack_pointer_rtx
)
8799 if (offset
!= required_offset
)
8806 /* A subroutine of mips_expand_prologue, called only when generating
8807 MIPS16e SAVE instructions. Search the start of the function for any
8808 instructions that save argument registers into their caller-allocated
8809 save slots. Delete such instructions and return a value N such that
8810 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8811 instructions redundant. */
8814 mips16e_collect_argument_saves (void)
8816 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
8817 rtx insn
, next
, set
, dest
, src
;
8818 unsigned int nargs
, regno
;
8820 push_topmost_sequence ();
8822 memset (reg_values
, 0, sizeof (reg_values
));
8823 for (insn
= get_insns (); insn
; insn
= next
)
8825 next
= NEXT_INSN (insn
);
8826 if (NOTE_P (insn
) || DEBUG_INSN_P (insn
))
8832 set
= PATTERN (insn
);
8833 if (GET_CODE (set
) != SET
)
8836 dest
= SET_DEST (set
);
8837 src
= SET_SRC (set
);
8838 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
8840 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
8843 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
8846 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
8847 reg_values
[REGNO (dest
)]
8848 = mips16e_collect_propagate_value (src
, reg_values
);
8852 pop_topmost_sequence ();
8857 /* Return a move between register REGNO and memory location SP + OFFSET.
8858 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
8859 Make the move a load if RESTORE_P, otherwise make it a store. */
8862 mips16e_save_restore_reg (bool restore_p
, bool reg_parm_p
,
8863 HOST_WIDE_INT offset
, unsigned int regno
)
8867 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, stack_pointer_rtx
,
8869 reg
= gen_rtx_REG (SImode
, regno
);
8872 mips_add_cfa_restore (reg
);
8873 return gen_rtx_SET (VOIDmode
, reg
, mem
);
8876 return gen_rtx_SET (VOIDmode
, mem
, reg
);
8877 return mips_frame_set (mem
, reg
);
8880 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8881 The instruction must:
8883 - Allocate or deallocate SIZE bytes in total; SIZE is known
8886 - Save or restore as many registers in *MASK_PTR as possible.
8887 The instruction saves the first registers at the top of the
8888 allocated area, with the other registers below it.
8890 - Save NARGS argument registers above the allocated area.
8892 (NARGS is always zero if RESTORE_P.)
8894 The SAVE and RESTORE instructions cannot save and restore all general
8895 registers, so there may be some registers left over for the caller to
8896 handle. Destructively modify *MASK_PTR so that it contains the registers
8897 that still need to be saved or restored. The caller can save these
8898 registers in the memory immediately below *OFFSET_PTR, which is a
8899 byte offset from the bottom of the allocated stack area. */
8902 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
8903 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
8907 HOST_WIDE_INT offset
, top_offset
;
8908 unsigned int i
, regno
;
8911 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
8913 /* Calculate the number of elements in the PARALLEL. We need one element
8914 for the stack adjustment, one for each argument register save, and one
8915 for each additional register move. */
8917 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
8918 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
8921 /* Create the final PARALLEL. */
8922 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
8925 /* Add the stack pointer adjustment. */
8926 set
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8927 plus_constant (Pmode
, stack_pointer_rtx
,
8928 restore_p
? size
: -size
));
8929 RTX_FRAME_RELATED_P (set
) = 1;
8930 XVECEXP (pattern
, 0, n
++) = set
;
8932 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8933 top_offset
= restore_p
? size
: 0;
8935 /* Save the arguments. */
8936 for (i
= 0; i
< nargs
; i
++)
8938 offset
= top_offset
+ i
* UNITS_PER_WORD
;
8939 set
= mips16e_save_restore_reg (restore_p
, true, offset
,
8941 XVECEXP (pattern
, 0, n
++) = set
;
8944 /* Then fill in the other register moves. */
8945 offset
= top_offset
;
8946 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
8948 regno
= mips16e_save_restore_regs
[i
];
8949 if (BITSET_P (*mask_ptr
, regno
))
8951 offset
-= UNITS_PER_WORD
;
8952 set
= mips16e_save_restore_reg (restore_p
, false, offset
, regno
);
8953 XVECEXP (pattern
, 0, n
++) = set
;
8954 *mask_ptr
&= ~(1 << regno
);
8958 /* Tell the caller what offset it should use for the remaining registers. */
8959 *offset_ptr
= size
+ (offset
- top_offset
);
8961 gcc_assert (n
== XVECLEN (pattern
, 0));
8966 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8967 pointer. Return true if PATTERN matches the kind of instruction
8968 generated by mips16e_build_save_restore. If INFO is nonnull,
8969 initialize it when returning true. */
8972 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
8973 struct mips16e_save_restore_info
*info
)
8975 unsigned int i
, nargs
, mask
, extra
;
8976 HOST_WIDE_INT top_offset
, save_offset
, offset
;
8977 rtx set
, reg
, mem
, base
;
8980 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
8983 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8984 top_offset
= adjust
> 0 ? adjust
: 0;
8986 /* Interpret all other members of the PARALLEL. */
8987 save_offset
= top_offset
- UNITS_PER_WORD
;
8991 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
8993 /* Check that we have a SET. */
8994 set
= XVECEXP (pattern
, 0, n
);
8995 if (GET_CODE (set
) != SET
)
8998 /* Check that the SET is a load (if restoring) or a store
9000 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
9004 /* Check that the address is the sum of the stack pointer and a
9005 possibly-zero constant offset. */
9006 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
9007 if (base
!= stack_pointer_rtx
)
9010 /* Check that SET's other operand is a register. */
9011 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
9015 /* Check for argument saves. */
9016 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
9017 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
9019 else if (offset
== save_offset
)
9021 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
9022 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
9025 mask
|= 1 << REGNO (reg
);
9026 save_offset
-= UNITS_PER_WORD
;
9032 /* Check that the restrictions on register ranges are met. */
9034 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
9035 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
9036 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
9037 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
9041 /* Make sure that the topmost argument register is not saved twice.
9042 The checks above ensure that the same is then true for the other
9043 argument registers. */
9044 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
9047 /* Pass back information, if requested. */
9050 info
->nargs
= nargs
;
9052 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
9058 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9059 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9060 the null terminator. */
9063 mips16e_add_register_range (char *s
, unsigned int min_reg
,
9064 unsigned int max_reg
)
9066 if (min_reg
!= max_reg
)
9067 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
9069 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
9073 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9074 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9077 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
9079 static char buffer
[300];
9081 struct mips16e_save_restore_info info
;
9082 unsigned int i
, end
;
9085 /* Parse the pattern. */
9086 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
9089 /* Add the mnemonic. */
9090 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
9093 /* Save the arguments. */
9095 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
9096 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
9097 else if (info
.nargs
== 1)
9098 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
9100 /* Emit the amount of stack space to allocate or deallocate. */
9101 s
+= sprintf (s
, "%d", (int) info
.size
);
9103 /* Save or restore $16. */
9104 if (BITSET_P (info
.mask
, 16))
9105 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
9107 /* Save or restore $17. */
9108 if (BITSET_P (info
.mask
, 17))
9109 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
9111 /* Save or restore registers in the range $s2...$s8, which
9112 mips16e_s2_s8_regs lists in decreasing order. Note that this
9113 is a software register range; the hardware registers are not
9114 numbered consecutively. */
9115 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
9116 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
9118 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
9119 mips16e_s2_s8_regs
[i
]);
9121 /* Save or restore registers in the range $a0...$a3. */
9122 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
9123 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
9125 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
9126 mips16e_a0_a3_regs
[end
- 1]);
9128 /* Save or restore $31. */
9129 if (BITSET_P (info
.mask
, RETURN_ADDR_REGNUM
))
9130 s
+= sprintf (s
, ",%s", reg_names
[RETURN_ADDR_REGNUM
]);
9135 /* Return true if the current function returns its value in a floating-point
9136 register in MIPS16 mode. */
9139 mips16_cfun_returns_in_fpr_p (void)
9141 tree return_type
= DECL_RESULT (current_function_decl
);
9142 return (TARGET_MIPS16
9143 && TARGET_HARD_FLOAT_ABI
9144 && !aggregate_value_p (return_type
, current_function_decl
)
9145 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
9148 /* Return true if predicate PRED is true for at least one instruction.
9149 Cache the result in *CACHE, and assume that the result is true
9150 if *CACHE is already true. */
9153 mips_find_gp_ref (bool *cache
, bool (*pred
) (rtx
))
9159 push_topmost_sequence ();
9160 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9161 if (USEFUL_INSN_P (insn
) && pred (insn
))
9166 pop_topmost_sequence ();
9171 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9172 See mips_cfun_has_inflexible_gp_ref_p for details. */
9175 mips_insn_has_inflexible_gp_ref_p (rtx insn
)
9177 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9178 indicate that the target could be a traditional MIPS
9179 lazily-binding stub. */
9180 return find_reg_fusage (insn
, USE
, pic_offset_table_rtx
);
9183 /* Return true if the current function refers to the global pointer
9184 in a way that forces $28 to be valid. This means that we can't
9185 change the choice of global pointer, even for NewABI code.
9187 One example of this (and one which needs several checks) is that
9188 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9189 (This restriction does not apply to PLTs.) */
9192 mips_cfun_has_inflexible_gp_ref_p (void)
9194 /* If the function has a nonlocal goto, $28 must hold the correct
9195 global pointer for the target function. That is, the target
9196 of the goto implicitly uses $28. */
9197 if (crtl
->has_nonlocal_goto
)
9200 if (TARGET_ABICALLS_PIC2
)
9202 /* Symbolic accesses implicitly use the global pointer unless
9203 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9204 might go to traditional MIPS lazy-binding stubs. */
9205 if (!TARGET_EXPLICIT_RELOCS
)
9208 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9209 can be lazily-bound. */
9213 /* MIPS16 functions that return in FPRs need to call an
9214 external libgcc routine. This call is only made explict
9215 during mips_expand_epilogue, and it too might be lazily bound. */
9216 if (mips16_cfun_returns_in_fpr_p ())
9220 return mips_find_gp_ref (&cfun
->machine
->has_inflexible_gp_insn_p
,
9221 mips_insn_has_inflexible_gp_ref_p
);
9224 /* Return true if INSN refers to the global pointer in a "flexible" way.
9225 See mips_cfun_has_flexible_gp_ref_p for details. */
9228 mips_insn_has_flexible_gp_ref_p (rtx insn
)
9230 return (get_attr_got (insn
) != GOT_UNSET
9231 || mips_small_data_pattern_p (PATTERN (insn
))
9232 || reg_overlap_mentioned_p (pic_offset_table_rtx
, PATTERN (insn
)));
9235 /* Return true if the current function references the global pointer,
9236 but if those references do not inherently require the global pointer
9237 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9240 mips_cfun_has_flexible_gp_ref_p (void)
9242 /* Reload can sometimes introduce constant pool references
9243 into a function that otherwise didn't need them. For example,
9244 suppose we have an instruction like:
9246 (set (reg:DF R1) (float:DF (reg:SI R2)))
9248 If R2 turns out to be a constant such as 1, the instruction may
9249 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9250 the option of using this constant if R2 doesn't get allocated
9253 In cases like these, reload will have added the constant to the
9254 pool but no instruction will yet refer to it. */
9255 if (TARGET_ABICALLS_PIC2
&& !reload_completed
&& crtl
->uses_const_pool
)
9258 return mips_find_gp_ref (&cfun
->machine
->has_flexible_gp_insn_p
,
9259 mips_insn_has_flexible_gp_ref_p
);
9262 /* Return the register that should be used as the global pointer
9263 within this function. Return INVALID_REGNUM if the function
9264 doesn't need a global pointer. */
9267 mips_global_pointer (void)
9271 /* $gp is always available unless we're using a GOT. */
9272 if (!TARGET_USE_GOT
)
9273 return GLOBAL_POINTER_REGNUM
;
9275 /* If there are inflexible references to $gp, we must use the
9276 standard register. */
9277 if (mips_cfun_has_inflexible_gp_ref_p ())
9278 return GLOBAL_POINTER_REGNUM
;
9280 /* If there are no current references to $gp, then the only uses
9281 we can introduce later are those involved in long branches. */
9282 if (TARGET_ABSOLUTE_JUMPS
&& !mips_cfun_has_flexible_gp_ref_p ())
9283 return INVALID_REGNUM
;
9285 /* If the global pointer is call-saved, try to use a call-clobbered
9287 if (TARGET_CALL_SAVED_GP
&& crtl
->is_leaf
)
9288 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9289 if (!df_regs_ever_live_p (regno
)
9290 && call_really_used_regs
[regno
]
9291 && !fixed_regs
[regno
]
9292 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
9295 return GLOBAL_POINTER_REGNUM
;
9298 /* Return true if the current function's prologue must load the global
9299 pointer value into pic_offset_table_rtx and store the same value in
9300 the function's cprestore slot (if any).
9302 One problem we have to deal with is that, when emitting GOT-based
9303 position independent code, long-branch sequences will need to load
9304 the address of the branch target from the GOT. We don't know until
9305 the very end of compilation whether (and where) the function needs
9306 long branches, so we must ensure that _any_ branch can access the
9307 global pointer in some form. However, we do not want to pessimize
9308 the usual case in which all branches are short.
9310 We handle this as follows:
9312 (1) During reload, we set cfun->machine->global_pointer to
9313 INVALID_REGNUM if we _know_ that the current function
9314 doesn't need a global pointer. This is only valid if
9315 long branches don't need the GOT.
9317 Otherwise, we assume that we might need a global pointer
9318 and pick an appropriate register.
9320 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9321 we ensure that the global pointer is available at every
9322 block boundary bar entry and exit. We do this in one of two ways:
9324 - If the function has a cprestore slot, we ensure that this
9325 slot is valid at every branch. However, as explained in
9326 point (6) below, there is no guarantee that pic_offset_table_rtx
9327 itself is valid if new uses of the global pointer are introduced
9328 after the first post-epilogue split.
9330 We guarantee that the cprestore slot is valid by loading it
9331 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9332 this register live at every block boundary bar function entry
9333 and exit. It is then invalid to move the load (and thus the
9334 preceding store) across a block boundary.
9336 - If the function has no cprestore slot, we guarantee that
9337 pic_offset_table_rtx itself is valid at every branch.
9339 See mips_eh_uses for the handling of the register liveness.
9341 (3) During prologue and epilogue generation, we emit "ghost"
9342 placeholder instructions to manipulate the global pointer.
9344 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9345 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9346 that the function needs a global pointer. (There is no need to set
9347 them earlier than this, and doing it as late as possible leads to
9348 fewer false positives.)
9350 (5) If cfun->machine->must_initialize_gp_p is true during a
9351 split_insns pass, we split the ghost instructions into real
9352 instructions. These split instructions can then be optimized in
9353 the usual way. Otherwise, we keep the ghost instructions intact,
9354 and optimize for the case where they aren't needed. We still
9355 have the option of splitting them later, if we need to introduce
9356 new uses of the global pointer.
9358 For example, the scheduler ignores a ghost instruction that
9359 stores $28 to the stack, but it handles the split form of
9360 the ghost instruction as an ordinary store.
9362 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9363 is true during the first post-epilogue split_insns pass, we split
9364 calls and restore_gp patterns into instructions that explicitly
9365 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9366 we split these patterns into instructions that _don't_ load from
9369 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9370 time of the split, then any instructions that exist at that time
9371 can make free use of pic_offset_table_rtx. However, if we want
9372 to introduce new uses of the global pointer after the split,
9373 we must explicitly load the value from the cprestore slot, since
9374 pic_offset_table_rtx itself might not be valid at a given point
9377 The idea is that we want to be able to delete redundant
9378 loads from the cprestore slot in the usual case where no
9379 long branches are needed.
9381 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9382 of md_reorg, we decide whether the global pointer is needed for
9383 long branches. If so, we set cfun->machine->must_initialize_gp_p
9384 to true and split the ghost instructions into real instructions
9387 Note that the ghost instructions must have a zero length for three reasons:
9389 - Giving the length of the underlying $gp sequence might cause
9390 us to use long branches in cases where they aren't really needed.
9392 - They would perturb things like alignment calculations.
9394 - More importantly, the hazard detection in md_reorg relies on
9395 empty instructions having a zero length.
9397 If we find a long branch and split the ghost instructions at the
9398 end of md_reorg, the split could introduce more long branches.
9399 That isn't a problem though, because we still do the split before
9400 the final shorten_branches pass.
9402 This is extremely ugly, but it seems like the best compromise between
9403 correctness and efficiency. */
9406 mips_must_initialize_gp_p (void)
9408 return cfun
->machine
->must_initialize_gp_p
;
9411 /* Return true if REGNO is a register that is ordinarily call-clobbered
9412 but must nevertheless be preserved by an interrupt handler. */
9415 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
9417 if (MD_REG_P (regno
))
9420 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
9423 if (GP_REG_P (regno
) && !cfun
->machine
->use_shadow_register_set_p
)
9425 /* $0 is hard-wired. */
9426 if (regno
== GP_REG_FIRST
)
9429 /* The interrupt handler can treat kernel registers as
9430 scratch registers. */
9431 if (KERNEL_REG_P (regno
))
9434 /* The function will return the stack pointer to its original value
9436 if (regno
== STACK_POINTER_REGNUM
)
9439 /* Otherwise, return true for registers that aren't ordinarily
9441 return call_really_used_regs
[regno
];
9447 /* Return true if the current function should treat register REGNO
9451 mips_cfun_call_saved_reg_p (unsigned int regno
)
9453 /* If the user makes an ordinarily-call-saved register global,
9454 that register is no longer call-saved. */
9455 if (global_regs
[regno
])
9458 /* Interrupt handlers need to save extra registers. */
9459 if (cfun
->machine
->interrupt_handler_p
9460 && mips_interrupt_extra_call_saved_reg_p (regno
))
9463 /* call_insns preserve $28 unless they explicitly say otherwise,
9464 so call_really_used_regs[] treats $28 as call-saved. However,
9465 we want the ABI property rather than the default call_insn
9467 return (regno
== GLOBAL_POINTER_REGNUM
9468 ? TARGET_CALL_SAVED_GP
9469 : !call_really_used_regs
[regno
]);
9472 /* Return true if the function body might clobber register REGNO.
9473 We know that REGNO is call-saved. */
9476 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
9478 /* Some functions should be treated as clobbering all call-saved
9480 if (crtl
->saves_all_registers
)
9483 /* DF handles cases where a register is explicitly referenced in
9484 the rtl. Incoming values are passed in call-clobbered registers,
9485 so we can assume that any live call-saved register is set within
9487 if (df_regs_ever_live_p (regno
))
9490 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9491 These clobbers are not explicit in the rtl. */
9492 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
9495 /* If we're using a call-saved global pointer, the function's
9496 prologue will need to set it up. */
9497 if (cfun
->machine
->global_pointer
== regno
)
9500 /* The function's prologue will need to set the frame pointer if
9501 frame_pointer_needed. */
9502 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
9505 /* If a MIPS16 function returns a value in FPRs, its epilogue
9506 will need to call an external libgcc routine. This yet-to-be
9507 generated call_insn will clobber $31. */
9508 if (regno
== RETURN_ADDR_REGNUM
&& mips16_cfun_returns_in_fpr_p ())
9511 /* If REGNO is ordinarily call-clobbered, we must assume that any
9512 called function could modify it. */
9513 if (cfun
->machine
->interrupt_handler_p
9515 && mips_interrupt_extra_call_saved_reg_p (regno
))
9521 /* Return true if the current function must save register REGNO. */
9524 mips_save_reg_p (unsigned int regno
)
9526 if (mips_cfun_call_saved_reg_p (regno
))
9528 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
9531 /* Save both registers in an FPR pair if either one is used. This is
9532 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9533 register to be used without the even register. */
9534 if (FP_REG_P (regno
)
9535 && MAX_FPRS_PER_FMT
== 2
9536 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
9540 /* We need to save the incoming return address if __builtin_eh_return
9541 is being used to set a different return address. */
9542 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
9548 /* Populate the current function's mips_frame_info structure.
9550 MIPS stack frames look like:
9552 +-------------------------------+
9554 | incoming stack arguments |
9556 +-------------------------------+
9558 | caller-allocated save area |
9559 A | for register arguments |
9561 +-------------------------------+ <-- incoming stack pointer
9563 | callee-allocated save area |
9564 B | for arguments that are |
9565 | split between registers and |
9568 +-------------------------------+ <-- arg_pointer_rtx
9570 C | callee-allocated save area |
9571 | for register varargs |
9573 +-------------------------------+ <-- frame_pointer_rtx
9574 | | + cop0_sp_offset
9575 | COP0 reg save area | + UNITS_PER_WORD
9577 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9578 | | + UNITS_PER_WORD
9579 | accumulator save area |
9581 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9582 | | + UNITS_PER_HWFPVALUE
9585 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9586 | | + UNITS_PER_WORD
9589 +-------------------------------+ <-- frame_pointer_rtx with
9590 | | \ -fstack-protector
9591 | local variables | | var_size
9593 +-------------------------------+
9595 | $gp save area | | cprestore_size
9597 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9599 | outgoing stack arguments | |
9601 +-------------------------------+ | args_size
9603 | caller-allocated save area | |
9604 | for register arguments | |
9606 +-------------------------------+ <-- stack_pointer_rtx
9607 frame_pointer_rtx without
9609 hard_frame_pointer_rtx for
9612 At least two of A, B and C will be empty.
9614 Dynamic stack allocations such as alloca insert data at point P.
9615 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9616 hard_frame_pointer_rtx unchanged. */
9619 mips_compute_frame_info (void)
9621 struct mips_frame_info
*frame
;
9622 HOST_WIDE_INT offset
, size
;
9623 unsigned int regno
, i
;
9625 /* Set this function's interrupt properties. */
9626 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
9629 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9630 else if (TARGET_HARD_FLOAT
)
9631 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9632 else if (TARGET_MIPS16
)
9633 error ("interrupt handlers cannot be MIPS16 functions");
9636 cfun
->machine
->interrupt_handler_p
= true;
9637 cfun
->machine
->use_shadow_register_set_p
=
9638 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl
));
9639 cfun
->machine
->keep_interrupts_masked_p
=
9640 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
9641 cfun
->machine
->use_debug_exception_return_p
=
9642 mips_use_debug_exception_return_p (TREE_TYPE
9643 (current_function_decl
));
9647 frame
= &cfun
->machine
->frame
;
9648 memset (frame
, 0, sizeof (*frame
));
9649 size
= get_frame_size ();
9651 cfun
->machine
->global_pointer
= mips_global_pointer ();
9653 /* The first two blocks contain the outgoing argument area and the $gp save
9654 slot. This area isn't needed in leaf functions, but if the
9655 target-independent frame size is nonzero, we have already committed to
9656 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9657 if ((size
== 0 || FRAME_GROWS_DOWNWARD
) && crtl
->is_leaf
)
9659 /* The MIPS 3.0 linker does not like functions that dynamically
9660 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9661 looks like we are trying to create a second frame pointer to the
9662 function, so allocate some stack space to make it happy. */
9663 if (cfun
->calls_alloca
)
9664 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
9666 frame
->args_size
= 0;
9667 frame
->cprestore_size
= 0;
9671 frame
->args_size
= crtl
->outgoing_args_size
;
9672 frame
->cprestore_size
= MIPS_GP_SAVE_AREA_SIZE
;
9674 offset
= frame
->args_size
+ frame
->cprestore_size
;
9676 /* Move above the local variables. */
9677 frame
->var_size
= MIPS_STACK_ALIGN (size
);
9678 offset
+= frame
->var_size
;
9680 /* Find out which GPRs we need to save. */
9681 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9682 if (mips_save_reg_p (regno
))
9685 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
9688 /* If this function calls eh_return, we must also save and restore the
9689 EH data registers. */
9690 if (crtl
->calls_eh_return
)
9691 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
9694 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
9697 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9698 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9699 save all later registers too. */
9700 if (GENERATE_MIPS16E_SAVE_RESTORE
)
9702 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
9703 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
9704 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
9705 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
9708 /* Move above the GPR save area. */
9709 if (frame
->num_gp
> 0)
9711 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
9712 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
9715 /* Find out which FPRs we need to save. This loop must iterate over
9716 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9717 if (TARGET_HARD_FLOAT
)
9718 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
9719 if (mips_save_reg_p (regno
))
9721 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
9722 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
9725 /* Move above the FPR save area. */
9726 if (frame
->num_fp
> 0)
9728 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
9729 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
9732 /* Add in space for the interrupt context information. */
9733 if (cfun
->machine
->interrupt_handler_p
)
9736 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
9739 frame
->acc_mask
|= (1 << 0);
9742 /* Check accumulators 1, 2, 3. */
9743 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
9744 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
9747 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
9750 /* All interrupt context functions need space to preserve STATUS. */
9751 frame
->num_cop0_regs
++;
9753 /* If we don't keep interrupts masked, we need to save EPC. */
9754 if (!cfun
->machine
->keep_interrupts_masked_p
)
9755 frame
->num_cop0_regs
++;
9758 /* Move above the accumulator save area. */
9759 if (frame
->num_acc
> 0)
9761 /* Each accumulator needs 2 words. */
9762 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
9763 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
9766 /* Move above the COP0 register save area. */
9767 if (frame
->num_cop0_regs
> 0)
9769 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
9770 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
9773 /* Move above the callee-allocated varargs save area. */
9774 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
9775 frame
->arg_pointer_offset
= offset
;
9777 /* Move above the callee-allocated area for pretend stack arguments. */
9778 offset
+= crtl
->args
.pretend_args_size
;
9779 frame
->total_size
= offset
;
9781 /* Work out the offsets of the save areas from the top of the frame. */
9782 if (frame
->gp_sp_offset
> 0)
9783 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
9784 if (frame
->fp_sp_offset
> 0)
9785 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
9786 if (frame
->acc_sp_offset
> 0)
9787 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
9788 if (frame
->num_cop0_regs
> 0)
9789 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
9791 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9792 arguments. This tends to increase the chances of using unextended
9793 instructions for local variables and incoming arguments. */
9795 frame
->hard_frame_pointer_offset
= frame
->args_size
;
9798 /* Return the style of GP load sequence that is being used for the
9799 current function. */
9801 enum mips_loadgp_style
9802 mips_current_loadgp_style (void)
9804 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
9810 if (TARGET_ABSOLUTE_ABICALLS
)
9811 return LOADGP_ABSOLUTE
;
9813 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
9816 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9819 mips_frame_pointer_required (void)
9821 /* If the function contains dynamic stack allocations, we need to
9822 use the frame pointer to access the static parts of the frame. */
9823 if (cfun
->calls_alloca
)
9826 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9827 reload may be unable to compute the address of a local variable,
9828 since there is no way to add a large constant to the stack pointer
9829 without using a second temporary register. */
9832 mips_compute_frame_info ();
9833 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
9840 /* Make sure that we're not trying to eliminate to the wrong hard frame
9844 mips_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
9846 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
9849 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9850 or argument pointer. TO is either the stack pointer or hard frame
9854 mips_initial_elimination_offset (int from
, int to
)
9856 HOST_WIDE_INT offset
;
9858 mips_compute_frame_info ();
9860 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
9863 case FRAME_POINTER_REGNUM
:
9864 if (FRAME_GROWS_DOWNWARD
)
9865 offset
= (cfun
->machine
->frame
.args_size
9866 + cfun
->machine
->frame
.cprestore_size
9867 + cfun
->machine
->frame
.var_size
);
9872 case ARG_POINTER_REGNUM
:
9873 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
9880 if (to
== HARD_FRAME_POINTER_REGNUM
)
9881 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
9886 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9889 mips_extra_live_on_entry (bitmap regs
)
9893 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
9894 the global pointer. */
9895 if (!TARGET_ABSOLUTE_ABICALLS
)
9896 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
9898 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9899 the global pointer. */
9901 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
9903 /* See the comment above load_call<mode> for details. */
9904 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
9908 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9912 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
9917 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
9920 /* Emit code to change the current function's return address to
9921 ADDRESS. SCRATCH is available as a scratch register, if needed.
9922 ADDRESS and SCRATCH are both word-mode GPRs. */
9925 mips_set_return_address (rtx address
, rtx scratch
)
9929 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
9930 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
9931 cfun
->machine
->frame
.gp_sp_offset
);
9932 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
9935 /* Return true if the current function has a cprestore slot. */
9938 mips_cfun_has_cprestore_slot_p (void)
9940 return (cfun
->machine
->global_pointer
!= INVALID_REGNUM
9941 && cfun
->machine
->frame
.cprestore_size
> 0);
9944 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
9945 cprestore slot. LOAD_P is true if the caller wants to load from
9946 the cprestore slot; it is false if the caller wants to store to
9950 mips_get_cprestore_base_and_offset (rtx
*base
, HOST_WIDE_INT
*offset
,
9953 const struct mips_frame_info
*frame
;
9955 frame
= &cfun
->machine
->frame
;
9956 /* .cprestore always uses the stack pointer instead of the frame pointer.
9957 We have a free choice for direct stores for non-MIPS16 functions,
9958 and for MIPS16 functions whose cprestore slot is in range of the
9959 stack pointer. Using the stack pointer would sometimes give more
9960 (early) scheduling freedom, but using the frame pointer would
9961 sometimes give more (late) scheduling freedom. It's hard to
9962 predict which applies to a given function, so let's keep things
9965 Loads must always use the frame pointer in functions that call
9966 alloca, and there's little benefit to using the stack pointer
9968 if (frame_pointer_needed
&& !(TARGET_CPRESTORE_DIRECTIVE
&& !load_p
))
9970 *base
= hard_frame_pointer_rtx
;
9971 *offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
9975 *base
= stack_pointer_rtx
;
9976 *offset
= frame
->args_size
;
9980 /* Return true if X is the load or store address of the cprestore slot;
9981 LOAD_P says which. */
9984 mips_cprestore_address_p (rtx x
, bool load_p
)
9986 rtx given_base
, required_base
;
9987 HOST_WIDE_INT given_offset
, required_offset
;
9989 mips_split_plus (x
, &given_base
, &given_offset
);
9990 mips_get_cprestore_base_and_offset (&required_base
, &required_offset
, load_p
);
9991 return given_base
== required_base
&& given_offset
== required_offset
;
9994 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
9995 going to load from it, false if we are going to store to it.
9996 Use TEMP as a temporary register if need be. */
9999 mips_cprestore_slot (rtx temp
, bool load_p
)
10002 HOST_WIDE_INT offset
;
10004 mips_get_cprestore_base_and_offset (&base
, &offset
, load_p
);
10005 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
10008 /* Emit instructions to save global pointer value GP into cprestore
10009 slot MEM. OFFSET is the offset that MEM applies to the base register.
10011 MEM may not be a legitimate address. If it isn't, TEMP is a
10012 temporary register that can be used, otherwise it is a SCRATCH. */
10015 mips_save_gp_to_cprestore_slot (rtx mem
, rtx offset
, rtx gp
, rtx temp
)
10017 if (TARGET_CPRESTORE_DIRECTIVE
)
10019 gcc_assert (gp
== pic_offset_table_rtx
);
10020 emit_insn (PMODE_INSN (gen_cprestore
, (mem
, offset
)));
10023 mips_emit_move (mips_cprestore_slot (temp
, false), gp
);
10026 /* Restore $gp from its save slot, using TEMP as a temporary base register
10027 if need be. This function is for o32 and o64 abicalls only.
10029 See mips_must_initialize_gp_p for details about how we manage the
10033 mips_restore_gp_from_cprestore_slot (rtx temp
)
10035 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
&& epilogue_completed
);
10037 if (!cfun
->machine
->must_restore_gp_when_clobbered_p
)
10039 emit_note (NOTE_INSN_DELETED
);
10045 mips_emit_move (temp
, mips_cprestore_slot (temp
, true));
10046 mips_emit_move (pic_offset_table_rtx
, temp
);
10049 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
, true));
10050 if (!TARGET_EXPLICIT_RELOCS
)
10051 emit_insn (gen_blockage ());
10054 /* A function to save or store a register. The first argument is the
10055 register and the second is the stack slot. */
10056 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
10058 /* Use FN to save or restore register REGNO. MODE is the register's
10059 mode and OFFSET is the offset of its save slot from the current
10063 mips_save_restore_reg (enum machine_mode mode
, int regno
,
10064 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
10068 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
,
10070 fn (gen_rtx_REG (mode
, regno
), mem
);
10073 /* Call FN for each accumlator that is saved by the current function.
10074 SP_OFFSET is the offset of the current stack pointer from the start
10078 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
10080 HOST_WIDE_INT offset
;
10083 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
10084 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
10086 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
10087 offset
-= UNITS_PER_WORD
;
10088 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
10089 offset
-= UNITS_PER_WORD
;
10092 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
10093 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
10094 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
10096 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10097 offset
-= UNITS_PER_WORD
;
10101 /* Call FN for each register that is saved by the current function.
10102 SP_OFFSET is the offset of the current stack pointer from the start
10106 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
10107 mips_save_restore_fn fn
)
10109 enum machine_mode fpr_mode
;
10110 HOST_WIDE_INT offset
;
10113 /* Save registers starting from high to low. The debuggers prefer at least
10114 the return register be stored at func+4, and also it allows us not to
10115 need a nop in the epilogue if at least one register is reloaded in
10116 addition to return address. */
10117 offset
= cfun
->machine
->frame
.gp_sp_offset
- sp_offset
;
10118 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
10119 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
10121 /* Record the ra offset for use by mips_function_profiler. */
10122 if (regno
== RETURN_ADDR_REGNUM
)
10123 cfun
->machine
->frame
.ra_fp_offset
= offset
+ sp_offset
;
10124 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10125 offset
-= UNITS_PER_WORD
;
10128 /* This loop must iterate over the same space as its companion in
10129 mips_compute_frame_info. */
10130 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
10131 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
10132 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
10133 regno
>= FP_REG_FIRST
;
10134 regno
-= MAX_FPRS_PER_FMT
)
10135 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
10137 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
10138 offset
-= GET_MODE_SIZE (fpr_mode
);
10142 /* Return true if a move between register REGNO and its save slot (MEM)
10143 can be done in a single move. LOAD_P is true if we are loading
10144 from the slot, false if we are storing to it. */
10147 mips_direct_save_slot_move_p (unsigned int regno
, rtx mem
, bool load_p
)
10149 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10150 if (TARGET_MIPS16
&& !load_p
&& regno
== RETURN_ADDR_REGNUM
)
10153 return mips_secondary_reload_class (REGNO_REG_CLASS (regno
),
10154 GET_MODE (mem
), mem
, load_p
) == NO_REGS
;
10157 /* Emit a move from SRC to DEST, given that one of them is a register
10158 save slot and that the other is a register. TEMP is a temporary
10159 GPR of the same mode that is available if need be. */
10162 mips_emit_save_slot_move (rtx dest
, rtx src
, rtx temp
)
10164 unsigned int regno
;
10169 regno
= REGNO (src
);
10174 regno
= REGNO (dest
);
10178 if (regno
== cfun
->machine
->global_pointer
&& !mips_must_initialize_gp_p ())
10180 /* We don't yet know whether we'll need this instruction or not.
10181 Postpone the decision by emitting a ghost move. This move
10182 is specifically not frame-related; only the split version is. */
10184 emit_insn (gen_move_gpdi (dest
, src
));
10186 emit_insn (gen_move_gpsi (dest
, src
));
10190 if (regno
== HI_REGNUM
)
10194 mips_emit_move (temp
, src
);
10196 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode
, MD_REG_FIRST
),
10197 temp
, gen_rtx_REG (DImode
, LO_REGNUM
)));
10199 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
10200 temp
, gen_rtx_REG (SImode
, LO_REGNUM
)));
10205 emit_insn (gen_mfhidi_ti (temp
,
10206 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
10208 emit_insn (gen_mfhisi_di (temp
,
10209 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
10210 mips_emit_move (dest
, temp
);
10213 else if (mips_direct_save_slot_move_p (regno
, mem
, mem
== src
))
10214 mips_emit_move (dest
, src
);
10217 gcc_assert (!reg_overlap_mentioned_p (dest
, temp
));
10218 mips_emit_move (temp
, src
);
10219 mips_emit_move (dest
, temp
);
10222 mips_set_frame_expr (mips_frame_set (dest
, src
));
10225 /* If we're generating n32 or n64 abicalls, and the current function
10226 does not use $28 as its global pointer, emit a cplocal directive.
10227 Use pic_offset_table_rtx as the argument to the directive. */
10230 mips_output_cplocal (void)
10232 if (!TARGET_EXPLICIT_RELOCS
10233 && mips_must_initialize_gp_p ()
10234 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
10235 output_asm_insn (".cplocal %+", 0);
10238 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10241 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10243 const char *fnname
;
10245 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10246 floating-point arguments. */
10248 && TARGET_HARD_FLOAT_ABI
10249 && crtl
->args
.info
.fp_code
!= 0)
10250 mips16_build_function_stub ();
10252 /* Get the function name the same way that toplev.c does before calling
10253 assemble_start_function. This is needed so that the name used here
10254 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10255 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10256 mips_start_function_definition (fnname
, TARGET_MIPS16
);
10258 /* Output MIPS-specific frame information. */
10259 if (!flag_inhibit_size_directive
)
10261 const struct mips_frame_info
*frame
;
10263 frame
= &cfun
->machine
->frame
;
10265 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10267 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
10268 "# vars= " HOST_WIDE_INT_PRINT_DEC
10270 ", args= " HOST_WIDE_INT_PRINT_DEC
10271 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
10272 reg_names
[frame_pointer_needed
10273 ? HARD_FRAME_POINTER_REGNUM
10274 : STACK_POINTER_REGNUM
],
10275 (frame_pointer_needed
10276 ? frame
->total_size
- frame
->hard_frame_pointer_offset
10277 : frame
->total_size
),
10278 reg_names
[RETURN_ADDR_REGNUM
],
10280 frame
->num_gp
, frame
->num_fp
,
10282 frame
->cprestore_size
);
10284 /* .mask MASK, OFFSET. */
10285 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10286 frame
->mask
, frame
->gp_save_offset
);
10288 /* .fmask MASK, OFFSET. */
10289 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10290 frame
->fmask
, frame
->fp_save_offset
);
10293 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10294 Also emit the ".set noreorder; .set nomacro" sequence for functions
10296 if (mips_must_initialize_gp_p ()
10297 && mips_current_loadgp_style () == LOADGP_OLDABI
)
10301 /* This is a fixed-form sequence. The position of the
10302 first two instructions is important because of the
10303 way _gp_disp is defined. */
10304 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10305 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10306 output_asm_insn ("sll\t$2,16", 0);
10307 output_asm_insn ("addu\t$2,$3", 0);
10311 /* .cpload must be in a .set noreorder but not a
10312 .set nomacro block. */
10313 mips_push_asm_switch (&mips_noreorder
);
10314 output_asm_insn (".cpload\t%^", 0);
10315 if (!cfun
->machine
->all_noreorder_p
)
10316 mips_pop_asm_switch (&mips_noreorder
);
10318 mips_push_asm_switch (&mips_nomacro
);
10321 else if (cfun
->machine
->all_noreorder_p
)
10323 mips_push_asm_switch (&mips_noreorder
);
10324 mips_push_asm_switch (&mips_nomacro
);
10327 /* Tell the assembler which register we're using as the global
10328 pointer. This is needed for thunks, since they can use either
10329 explicit relocs or assembler macros. */
10330 mips_output_cplocal ();
10333 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10336 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
10337 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10339 const char *fnname
;
10341 /* Reinstate the normal $gp. */
10342 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
10343 mips_output_cplocal ();
10345 if (cfun
->machine
->all_noreorder_p
)
10347 mips_pop_asm_switch (&mips_nomacro
);
10348 mips_pop_asm_switch (&mips_noreorder
);
10351 /* Get the function name the same way that toplev.c does before calling
10352 assemble_start_function. This is needed so that the name used here
10353 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10354 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10355 mips_end_function_definition (fnname
);
10358 /* Emit an optimisation barrier for accesses to the current frame. */
10361 mips_frame_barrier (void)
10363 emit_clobber (gen_frame_mem (BLKmode
, stack_pointer_rtx
));
10366 /* Save register REG to MEM. Make the instruction frame-related. */
10369 mips_save_reg (rtx reg
, rtx mem
)
10371 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
10375 if (mips_split_64bit_move_p (mem
, reg
))
10376 mips_split_doubleword_move (mem
, reg
);
10378 mips_emit_move (mem
, reg
);
10380 x1
= mips_frame_set (mips_subword (mem
, false),
10381 mips_subword (reg
, false));
10382 x2
= mips_frame_set (mips_subword (mem
, true),
10383 mips_subword (reg
, true));
10384 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
10387 mips_emit_save_slot_move (mem
, reg
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
10390 /* The __gnu_local_gp symbol. */
10392 static GTY(()) rtx mips_gnu_local_gp
;
10394 /* If we're generating n32 or n64 abicalls, emit instructions
10395 to set up the global pointer. */
10398 mips_emit_loadgp (void)
10400 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
10402 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
10403 switch (mips_current_loadgp_style ())
10405 case LOADGP_ABSOLUTE
:
10406 if (mips_gnu_local_gp
== NULL
)
10408 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
10409 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
10411 emit_insn (PMODE_INSN (gen_loadgp_absolute
,
10412 (pic_reg
, mips_gnu_local_gp
)));
10415 case LOADGP_OLDABI
:
10416 /* Added by mips_output_function_prologue. */
10419 case LOADGP_NEWABI
:
10420 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
10421 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
10422 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
10423 emit_insn (PMODE_INSN (gen_loadgp_newabi
,
10424 (pic_reg
, offset
, incoming_address
)));
10428 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
10429 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
10430 emit_insn (PMODE_INSN (gen_loadgp_rtp
, (pic_reg
, base
, index
)));
10438 emit_insn (PMODE_INSN (gen_copygp_mips16
,
10439 (pic_offset_table_rtx
, pic_reg
)));
10441 /* Emit a blockage if there are implicit uses of the GP register.
10442 This includes profiled functions, because FUNCTION_PROFILE uses
10444 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
10445 emit_insn (gen_loadgp_blockage ());
10448 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10451 mips_kernel_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
10453 return REG_P (*x
) && KERNEL_REG_P (REGNO (*x
));
10456 /* Expand the "prologue" pattern. */
10459 mips_expand_prologue (void)
10461 const struct mips_frame_info
*frame
;
10462 HOST_WIDE_INT size
;
10463 unsigned int nargs
;
10466 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
10468 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10469 or implicitly. If so, we can commit to using a global pointer
10470 straight away, otherwise we need to defer the decision. */
10471 if (mips_cfun_has_inflexible_gp_ref_p ()
10472 || mips_cfun_has_flexible_gp_ref_p ())
10474 cfun
->machine
->must_initialize_gp_p
= true;
10475 cfun
->machine
->must_restore_gp_when_clobbered_p
= true;
10478 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
10481 frame
= &cfun
->machine
->frame
;
10482 size
= frame
->total_size
;
10484 if (flag_stack_usage_info
)
10485 current_function_static_stack_size
= size
;
10487 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10488 bytes beforehand; this is enough to cover the register save area
10489 without going out of range. */
10490 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
10491 || frame
->num_cop0_regs
> 0)
10493 HOST_WIDE_INT step1
;
10495 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
10496 if (GENERATE_MIPS16E_SAVE_RESTORE
)
10498 HOST_WIDE_INT offset
;
10499 unsigned int mask
, regno
;
10501 /* Try to merge argument stores into the save instruction. */
10502 nargs
= mips16e_collect_argument_saves ();
10504 /* Build the save instruction. */
10505 mask
= frame
->mask
;
10506 insn
= mips16e_build_save_restore (false, &mask
, &offset
,
10508 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10509 mips_frame_barrier ();
10512 /* Check if we need to save other registers. */
10513 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
10514 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10516 offset
-= UNITS_PER_WORD
;
10517 mips_save_restore_reg (word_mode
, regno
,
10518 offset
, mips_save_reg
);
10523 if (cfun
->machine
->interrupt_handler_p
)
10525 HOST_WIDE_INT offset
;
10528 /* If this interrupt is using a shadow register set, we need to
10529 get the stack pointer from the previous register set. */
10530 if (cfun
->machine
->use_shadow_register_set_p
)
10531 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx
,
10532 stack_pointer_rtx
));
10534 if (!cfun
->machine
->keep_interrupts_masked_p
)
10536 /* Move from COP0 Cause to K0. */
10537 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
10538 gen_rtx_REG (SImode
,
10539 COP0_CAUSE_REG_NUM
)));
10540 /* Move from COP0 EPC to K1. */
10541 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
10542 gen_rtx_REG (SImode
,
10543 COP0_EPC_REG_NUM
)));
10546 /* Allocate the first part of the frame. */
10547 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
10549 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10550 mips_frame_barrier ();
10553 /* Start at the uppermost location for saving. */
10554 offset
= frame
->cop0_sp_offset
- size
;
10555 if (!cfun
->machine
->keep_interrupts_masked_p
)
10557 /* Push EPC into its stack slot. */
10558 mem
= gen_frame_mem (word_mode
,
10559 plus_constant (Pmode
, stack_pointer_rtx
,
10561 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
10562 offset
-= UNITS_PER_WORD
;
10565 /* Move from COP0 Status to K1. */
10566 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
10567 gen_rtx_REG (SImode
,
10568 COP0_STATUS_REG_NUM
)));
10570 /* Right justify the RIPL in k0. */
10571 if (!cfun
->machine
->keep_interrupts_masked_p
)
10572 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
10573 gen_rtx_REG (SImode
, K0_REG_NUM
),
10574 GEN_INT (CAUSE_IPL
)));
10576 /* Push Status into its stack slot. */
10577 mem
= gen_frame_mem (word_mode
,
10578 plus_constant (Pmode
, stack_pointer_rtx
,
10580 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
10581 offset
-= UNITS_PER_WORD
;
10583 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10584 if (!cfun
->machine
->keep_interrupts_masked_p
)
10585 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
10588 gen_rtx_REG (SImode
, K0_REG_NUM
)));
10590 if (!cfun
->machine
->keep_interrupts_masked_p
)
10591 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10592 IE is already the correct value, so we don't have to do
10593 anything explicit. */
10594 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
10597 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
10599 /* Disable interrupts by clearing the KSU, ERL, EXL,
10601 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
10604 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
10608 insn
= gen_add3_insn (stack_pointer_rtx
,
10611 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10612 mips_frame_barrier ();
10615 mips_for_each_saved_acc (size
, mips_save_reg
);
10616 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
10620 /* Allocate the rest of the frame. */
10623 if (SMALL_OPERAND (-size
))
10624 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
10626 GEN_INT (-size
)))) = 1;
10629 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
10632 /* There are no instructions to add or subtract registers
10633 from the stack pointer, so use the frame pointer as a
10634 temporary. We should always be using a frame pointer
10635 in this case anyway. */
10636 gcc_assert (frame_pointer_needed
);
10637 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
10638 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
10639 hard_frame_pointer_rtx
,
10640 MIPS_PROLOGUE_TEMP (Pmode
)));
10641 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
10644 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
10646 MIPS_PROLOGUE_TEMP (Pmode
)));
10648 /* Describe the combined effect of the previous instructions. */
10649 mips_set_frame_expr
10650 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
10651 plus_constant (Pmode
, stack_pointer_rtx
, -size
)));
10653 mips_frame_barrier ();
10656 /* Set up the frame pointer, if we're using one. */
10657 if (frame_pointer_needed
)
10659 HOST_WIDE_INT offset
;
10661 offset
= frame
->hard_frame_pointer_offset
;
10664 insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
10665 RTX_FRAME_RELATED_P (insn
) = 1;
10667 else if (SMALL_OPERAND (offset
))
10669 insn
= gen_add3_insn (hard_frame_pointer_rtx
,
10670 stack_pointer_rtx
, GEN_INT (offset
));
10671 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10675 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
10676 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
10677 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
10678 hard_frame_pointer_rtx
,
10679 MIPS_PROLOGUE_TEMP (Pmode
)));
10680 mips_set_frame_expr
10681 (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
10682 plus_constant (Pmode
, stack_pointer_rtx
, offset
)));
10686 mips_emit_loadgp ();
10688 /* Initialize the $gp save slot. */
10689 if (mips_cfun_has_cprestore_slot_p ())
10691 rtx base
, mem
, gp
, temp
;
10692 HOST_WIDE_INT offset
;
10694 mips_get_cprestore_base_and_offset (&base
, &offset
, false);
10695 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
10696 gp
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
10697 temp
= (SMALL_OPERAND (offset
)
10698 ? gen_rtx_SCRATCH (Pmode
)
10699 : MIPS_PROLOGUE_TEMP (Pmode
));
10700 emit_insn (PMODE_INSN (gen_potential_cprestore
,
10701 (mem
, GEN_INT (offset
), gp
, temp
)));
10703 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
10704 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
10705 emit_insn (PMODE_INSN (gen_use_cprestore
, (mem
)));
10708 /* We need to search back to the last use of K0 or K1. */
10709 if (cfun
->machine
->interrupt_handler_p
)
10711 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
10713 && for_each_rtx (&PATTERN (insn
), mips_kernel_reg_p
, NULL
))
10715 /* Emit a move from K1 to COP0 Status after insn. */
10716 gcc_assert (insn
!= NULL_RTX
);
10717 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
10718 gen_rtx_REG (SImode
, K1_REG_NUM
)),
10722 /* If we are profiling, make sure no instructions are scheduled before
10723 the call to mcount. */
10725 emit_insn (gen_blockage ());
10728 /* Attach all pending register saves to the previous instruction.
10729 Return that instruction. */
10732 mips_epilogue_emit_cfa_restores (void)
10736 insn
= get_last_insn ();
10737 gcc_assert (insn
&& !REG_NOTES (insn
));
10738 if (mips_epilogue
.cfa_restores
)
10740 RTX_FRAME_RELATED_P (insn
) = 1;
10741 REG_NOTES (insn
) = mips_epilogue
.cfa_restores
;
10742 mips_epilogue
.cfa_restores
= 0;
10747 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
10748 now at REG + OFFSET. */
10751 mips_epilogue_set_cfa (rtx reg
, HOST_WIDE_INT offset
)
10755 insn
= mips_epilogue_emit_cfa_restores ();
10756 if (reg
!= mips_epilogue
.cfa_reg
|| offset
!= mips_epilogue
.cfa_offset
)
10758 RTX_FRAME_RELATED_P (insn
) = 1;
10759 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_DEF_CFA
,
10760 plus_constant (Pmode
, reg
, offset
),
10762 mips_epilogue
.cfa_reg
= reg
;
10763 mips_epilogue
.cfa_offset
= offset
;
10767 /* Emit instructions to restore register REG from slot MEM. Also update
10768 the cfa_restores list. */
10771 mips_restore_reg (rtx reg
, rtx mem
)
10773 /* There's no MIPS16 instruction to load $31 directly. Load into
10774 $7 instead and adjust the return insn appropriately. */
10775 if (TARGET_MIPS16
&& REGNO (reg
) == RETURN_ADDR_REGNUM
)
10776 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
10777 else if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
10779 mips_add_cfa_restore (mips_subword (reg
, true));
10780 mips_add_cfa_restore (mips_subword (reg
, false));
10783 mips_add_cfa_restore (reg
);
10785 mips_emit_save_slot_move (reg
, mem
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
10786 if (REGNO (reg
) == REGNO (mips_epilogue
.cfa_reg
))
10787 /* The CFA is currently defined in terms of the register whose
10788 value we have just restored. Redefine the CFA in terms of
10789 the stack pointer. */
10790 mips_epilogue_set_cfa (stack_pointer_rtx
,
10791 mips_epilogue
.cfa_restore_sp_offset
);
10794 /* Emit code to set the stack pointer to BASE + OFFSET, given that
10795 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
10796 BASE, if not the stack pointer, is available as a temporary. */
10799 mips_deallocate_stack (rtx base
, rtx offset
, HOST_WIDE_INT new_frame_size
)
10801 if (base
== stack_pointer_rtx
&& offset
== const0_rtx
)
10804 mips_frame_barrier ();
10805 if (offset
== const0_rtx
)
10807 emit_move_insn (stack_pointer_rtx
, base
);
10808 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
10810 else if (TARGET_MIPS16
&& base
!= stack_pointer_rtx
)
10812 emit_insn (gen_add3_insn (base
, base
, offset
));
10813 mips_epilogue_set_cfa (base
, new_frame_size
);
10814 emit_move_insn (stack_pointer_rtx
, base
);
10818 emit_insn (gen_add3_insn (stack_pointer_rtx
, base
, offset
));
10819 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
10823 /* Emit any instructions needed before a return. */
10826 mips_expand_before_return (void)
10828 /* When using a call-clobbered gp, we start out with unified call
10829 insns that include instructions to restore the gp. We then split
10830 these unified calls after reload. These split calls explicitly
10831 clobber gp, so there is no need to define
10832 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
10834 For consistency, we should also insert an explicit clobber of $28
10835 before return insns, so that the post-reload optimizers know that
10836 the register is not live on exit. */
10837 if (TARGET_CALL_CLOBBERED_GP
)
10838 emit_clobber (pic_offset_table_rtx
);
10841 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
10845 mips_expand_epilogue (bool sibcall_p
)
10847 const struct mips_frame_info
*frame
;
10848 HOST_WIDE_INT step1
, step2
;
10849 rtx base
, adjust
, insn
;
10851 if (!sibcall_p
&& mips_can_use_return_insn ())
10853 emit_jump_insn (gen_return ());
10857 /* In MIPS16 mode, if the return value should go into a floating-point
10858 register, we need to call a helper routine to copy it over. */
10859 if (mips16_cfun_returns_in_fpr_p ())
10860 mips16_copy_fpr_return_value ();
10862 /* Split the frame into two. STEP1 is the amount of stack we should
10863 deallocate before restoring the registers. STEP2 is the amount we
10864 should deallocate afterwards.
10866 Start off by assuming that no registers need to be restored. */
10867 frame
= &cfun
->machine
->frame
;
10868 step1
= frame
->total_size
;
10871 /* Work out which register holds the frame address. */
10872 if (!frame_pointer_needed
)
10873 base
= stack_pointer_rtx
;
10876 base
= hard_frame_pointer_rtx
;
10877 step1
-= frame
->hard_frame_pointer_offset
;
10879 mips_epilogue
.cfa_reg
= base
;
10880 mips_epilogue
.cfa_offset
= step1
;
10881 mips_epilogue
.cfa_restores
= NULL_RTX
;
10883 /* If we need to restore registers, deallocate as much stack as
10884 possible in the second step without going out of range. */
10885 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
10886 || frame
->num_cop0_regs
> 0)
10888 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
10892 /* Get an rtx for STEP1 that we can add to BASE. */
10893 adjust
= GEN_INT (step1
);
10894 if (!SMALL_OPERAND (step1
))
10896 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
10897 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
10899 mips_deallocate_stack (base
, adjust
, step2
);
10901 /* If we're using addressing macros, $gp is implicitly used by all
10902 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
10904 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
10905 emit_insn (gen_blockage ());
10907 mips_epilogue
.cfa_restore_sp_offset
= step2
;
10908 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
10910 unsigned int regno
, mask
;
10911 HOST_WIDE_INT offset
;
10914 /* Generate the restore instruction. */
10915 mask
= frame
->mask
;
10916 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
10918 /* Restore any other registers manually. */
10919 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
10920 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10922 offset
-= UNITS_PER_WORD
;
10923 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
10926 /* Restore the remaining registers and deallocate the final bit
10928 mips_frame_barrier ();
10929 emit_insn (restore
);
10930 mips_epilogue_set_cfa (stack_pointer_rtx
, 0);
10934 /* Restore the registers. */
10935 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
10936 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
10939 if (cfun
->machine
->interrupt_handler_p
)
10941 HOST_WIDE_INT offset
;
10944 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
10945 if (!cfun
->machine
->keep_interrupts_masked_p
)
10947 /* Restore the original EPC. */
10948 mem
= gen_frame_mem (word_mode
,
10949 plus_constant (Pmode
, stack_pointer_rtx
,
10951 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
10952 offset
-= UNITS_PER_WORD
;
10954 /* Move to COP0 EPC. */
10955 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
10956 gen_rtx_REG (SImode
, K0_REG_NUM
)));
10959 /* Restore the original Status. */
10960 mem
= gen_frame_mem (word_mode
,
10961 plus_constant (Pmode
, stack_pointer_rtx
,
10963 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
10964 offset
-= UNITS_PER_WORD
;
10966 /* If we don't use shoadow register set, we need to update SP. */
10967 if (!cfun
->machine
->use_shadow_register_set_p
)
10968 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
10970 /* The choice of position is somewhat arbitrary in this case. */
10971 mips_epilogue_emit_cfa_restores ();
10973 /* Move to COP0 Status. */
10974 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
10975 gen_rtx_REG (SImode
, K0_REG_NUM
)));
10978 /* Deallocate the final bit of the frame. */
10979 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
10981 gcc_assert (!mips_epilogue
.cfa_restores
);
10983 /* Add in the __builtin_eh_return stack adjustment. We need to
10984 use a temporary in MIPS16 code. */
10985 if (crtl
->calls_eh_return
)
10989 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
10990 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
10991 MIPS_EPILOGUE_TEMP (Pmode
),
10992 EH_RETURN_STACKADJ_RTX
));
10993 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
10996 emit_insn (gen_add3_insn (stack_pointer_rtx
,
10998 EH_RETURN_STACKADJ_RTX
));
11003 mips_expand_before_return ();
11004 if (cfun
->machine
->interrupt_handler_p
)
11006 /* Interrupt handlers generate eret or deret. */
11007 if (cfun
->machine
->use_debug_exception_return_p
)
11008 emit_jump_insn (gen_mips_deret ());
11010 emit_jump_insn (gen_mips_eret ());
11016 /* When generating MIPS16 code, the normal
11017 mips_for_each_saved_gpr_and_fpr path will restore the return
11018 address into $7 rather than $31. */
11020 && !GENERATE_MIPS16E_SAVE_RESTORE
11021 && BITSET_P (frame
->mask
, RETURN_ADDR_REGNUM
))
11023 /* simple_returns cannot rely on values that are only available
11024 on paths through the epilogue (because return paths that do
11025 not pass through the epilogue may nevertheless reuse a
11026 simple_return that occurs at the end of the epilogue).
11027 Use a normal return here instead. */
11028 rtx reg
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 7);
11029 pat
= gen_return_internal (reg
);
11033 rtx reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
11034 pat
= gen_simple_return_internal (reg
);
11036 emit_jump_insn (pat
);
11040 /* Search from the beginning to the first use of K0 or K1. */
11041 if (cfun
->machine
->interrupt_handler_p
11042 && !cfun
->machine
->keep_interrupts_masked_p
)
11044 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
11046 && for_each_rtx (&PATTERN(insn
), mips_kernel_reg_p
, NULL
))
11048 gcc_assert (insn
!= NULL_RTX
);
11049 /* Insert disable interrupts before the first use of K0 or K1. */
11050 emit_insn_before (gen_mips_di (), insn
);
11051 emit_insn_before (gen_mips_ehb (), insn
);
11055 /* Return nonzero if this function is known to have a null epilogue.
11056 This allows the optimizer to omit jumps to jumps if no stack
11060 mips_can_use_return_insn (void)
11062 /* Interrupt handlers need to go through the epilogue. */
11063 if (cfun
->machine
->interrupt_handler_p
)
11066 if (!reload_completed
)
11072 /* In MIPS16 mode, a function that returns a floating-point value
11073 needs to arrange to copy the return value into the floating-point
11075 if (mips16_cfun_returns_in_fpr_p ())
11078 return cfun
->machine
->frame
.total_size
== 0;
11081 /* Return true if register REGNO can store a value of mode MODE.
11082 The result of this function is cached in mips_hard_regno_mode_ok. */
11085 mips_hard_regno_mode_ok_p (unsigned int regno
, enum machine_mode mode
)
11088 enum mode_class mclass
;
11090 if (mode
== CCV2mode
)
11091 return (ISA_HAS_8CC
11092 && ST_REG_P (regno
)
11093 && (regno
- ST_REG_FIRST
) % 2 == 0);
11095 if (mode
== CCV4mode
)
11096 return (ISA_HAS_8CC
11097 && ST_REG_P (regno
)
11098 && (regno
- ST_REG_FIRST
) % 4 == 0);
11100 if (mode
== CCmode
)
11103 return regno
== FPSW_REGNUM
;
11105 return (ST_REG_P (regno
)
11106 || GP_REG_P (regno
)
11107 || FP_REG_P (regno
));
11110 size
= GET_MODE_SIZE (mode
);
11111 mclass
= GET_MODE_CLASS (mode
);
11113 if (GP_REG_P (regno
))
11114 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
11116 if (FP_REG_P (regno
)
11117 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
11118 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
11120 /* Allow TFmode for CCmode reloads. */
11121 if (mode
== TFmode
&& ISA_HAS_8CC
)
11124 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11125 if (TARGET_LOONGSON_VECTORS
11126 && (mode
== V2SImode
11127 || mode
== V4HImode
11128 || mode
== V8QImode
11129 || mode
== DImode
))
11132 if (mclass
== MODE_FLOAT
11133 || mclass
== MODE_COMPLEX_FLOAT
11134 || mclass
== MODE_VECTOR_FLOAT
)
11135 return size
<= UNITS_PER_FPVALUE
;
11137 /* Allow integer modes that fit into a single register. We need
11138 to put integers into FPRs when using instructions like CVT
11139 and TRUNC. There's no point allowing sizes smaller than a word,
11140 because the FPU has no appropriate load/store instructions. */
11141 if (mclass
== MODE_INT
)
11142 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
11145 if (ACC_REG_P (regno
)
11146 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
11148 if (MD_REG_P (regno
))
11150 /* After a multiplication or division, clobbering HI makes
11151 the value of LO unpredictable, and vice versa. This means
11152 that, for all interesting cases, HI and LO are effectively
11155 We model this by requiring that any value that uses HI
11157 if (size
<= UNITS_PER_WORD
* 2)
11158 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
11162 /* DSP accumulators do not have the same restrictions as
11163 HI and LO, so we can treat them as normal doubleword
11165 if (size
<= UNITS_PER_WORD
)
11168 if (size
<= UNITS_PER_WORD
* 2
11169 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
11174 if (ALL_COP_REG_P (regno
))
11175 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
11177 if (regno
== GOT_VERSION_REGNUM
)
11178 return mode
== SImode
;
11183 /* Implement HARD_REGNO_NREGS. */
11186 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
11188 if (ST_REG_P (regno
))
11189 /* The size of FP status registers is always 4, because they only hold
11190 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11191 return (GET_MODE_SIZE (mode
) + 3) / 4;
11193 if (FP_REG_P (regno
))
11194 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
11196 /* All other registers are word-sized. */
11197 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
11200 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11201 in mips_hard_regno_nregs. */
11204 mips_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
11210 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
11211 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
11213 if (HARD_REGNO_MODE_OK (ST_REG_FIRST
, mode
))
11214 size
= MIN (size
, 4);
11215 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
11217 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
11219 if (HARD_REGNO_MODE_OK (FP_REG_FIRST
, mode
))
11220 size
= MIN (size
, UNITS_PER_FPREG
);
11221 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
11223 if (!hard_reg_set_empty_p (left
))
11224 size
= MIN (size
, UNITS_PER_WORD
);
11225 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
11228 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11231 mips_cannot_change_mode_class (enum machine_mode from
,
11232 enum machine_mode to
,
11233 enum reg_class rclass
)
11235 /* Allow conversions between different Loongson integer vectors,
11236 and between those vectors and DImode. */
11237 if (GET_MODE_SIZE (from
) == 8 && GET_MODE_SIZE (to
) == 8
11238 && INTEGRAL_MODE_P (from
) && INTEGRAL_MODE_P (to
))
11241 /* Otherwise, there are several problems with changing the modes of
11242 values in floating-point registers:
11244 - When a multi-word value is stored in paired floating-point
11245 registers, the first register always holds the low word. We
11246 therefore can't allow FPRs to change between single-word and
11247 multi-word modes on big-endian targets.
11249 - GCC assumes that each word of a multiword register can be
11250 accessed individually using SUBREGs. This is not true for
11251 floating-point registers if they are bigger than a word.
11253 - Loading a 32-bit value into a 64-bit floating-point register
11254 will not sign-extend the value, despite what LOAD_EXTEND_OP
11255 says. We can't allow FPRs to change from SImode to a wider
11256 mode on 64-bit targets.
11258 - If the FPU has already interpreted a value in one format, we
11259 must not ask it to treat the value as having a different
11262 We therefore disallow all mode changes involving FPRs. */
11264 return reg_classes_intersect_p (FP_REGS
, rclass
);
11267 /* Implement target hook small_register_classes_for_mode_p. */
11270 mips_small_register_classes_for_mode_p (enum machine_mode mode
11273 return TARGET_MIPS16
;
11276 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11279 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode
)
11284 return TARGET_HARD_FLOAT
;
11287 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
11290 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
11297 /* Implement MODES_TIEABLE_P. */
11300 mips_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
11302 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11303 prefer to put one of them in FPRs. */
11304 return (mode1
== mode2
11305 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
11306 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
11309 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11312 mips_preferred_reload_class (rtx x
, reg_class_t rclass
)
11314 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
11317 if (reg_class_subset_p (FP_REGS
, rclass
)
11318 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
11321 if (reg_class_subset_p (GR_REGS
, rclass
))
11324 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
11330 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11331 Return a "canonical" class to represent it in later calculations. */
11334 mips_canonicalize_move_class (reg_class_t rclass
)
11336 /* All moves involving accumulator registers have the same cost. */
11337 if (reg_class_subset_p (rclass
, ACC_REGS
))
11340 /* Likewise promote subclasses of general registers to the most
11341 interesting containing class. */
11342 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
11344 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
11345 rclass
= GENERAL_REGS
;
11350 /* Return the cost of moving a value of mode MODE from a register of
11351 class FROM to a GPR. Return 0 for classes that are unions of other
11352 classes handled by this function. */
11355 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
11361 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11365 /* MFLO and MFHI. */
11373 /* LUI followed by MOVF. */
11379 /* This choice of value is historical. */
11387 /* Return the cost of moving a value of mode MODE from a GPR to a
11388 register of class TO. Return 0 for classes that are unions of
11389 other classes handled by this function. */
11392 mips_move_from_gpr_cost (enum machine_mode mode
, reg_class_t to
)
11397 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11401 /* MTLO and MTHI. */
11409 /* A secondary reload through an FPR scratch. */
11410 return (mips_register_move_cost (mode
, GENERAL_REGS
, FP_REGS
)
11411 + mips_register_move_cost (mode
, FP_REGS
, ST_REGS
));
11416 /* This choice of value is historical. */
11424 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
11425 maximum of the move costs for subclasses; regclass will work out
11426 the maximum for us. */
11429 mips_register_move_cost (enum machine_mode mode
,
11430 reg_class_t from
, reg_class_t to
)
11435 from
= mips_canonicalize_move_class (from
);
11436 to
= mips_canonicalize_move_class (to
);
11438 /* Handle moves that can be done without using general-purpose registers. */
11439 if (from
== FP_REGS
)
11441 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
11445 /* The sequence generated by mips_expand_fcc_reload. */
11449 /* Handle cases in which only one class deviates from the ideal. */
11450 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
11452 return mips_move_from_gpr_cost (mode
, to
);
11454 return mips_move_to_gpr_cost (mode
, from
);
11456 /* Handles cases that require a GPR temporary. */
11457 cost1
= mips_move_to_gpr_cost (mode
, from
);
11460 cost2
= mips_move_from_gpr_cost (mode
, to
);
11462 return cost1
+ cost2
;
11468 /* Implement TARGET_MEMORY_MOVE_COST. */
11471 mips_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
, bool in
)
11473 return (mips_cost
->memory_latency
11474 + memory_move_secondary_cost (mode
, rclass
, in
));
11477 /* Return the register class required for a secondary register when
11478 copying between one of the registers in RCLASS and value X, which
11479 has mode MODE. X is the source of the move if IN_P, otherwise it
11480 is the destination. Return NO_REGS if no secondary register is
11484 mips_secondary_reload_class (enum reg_class rclass
,
11485 enum machine_mode mode
, rtx x
, bool in_p
)
11489 /* If X is a constant that cannot be loaded into $25, it must be loaded
11490 into some other GPR. No other register class allows a direct move. */
11491 if (mips_dangerous_for_la25_p (x
))
11492 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
11494 regno
= true_regnum (x
);
11497 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
11498 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
11504 /* Copying from accumulator registers to anywhere other than a general
11505 register requires a temporary general register. */
11506 if (reg_class_subset_p (rclass
, ACC_REGS
))
11507 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
11508 if (ACC_REG_P (regno
))
11509 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
11511 /* We can only copy a value to a condition code register from a
11512 floating-point register, and even then we require a scratch
11513 floating-point register. We can only copy a value out of a
11514 condition-code register into a general register. */
11515 if (reg_class_subset_p (rclass
, ST_REGS
))
11519 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
11521 if (ST_REG_P (regno
))
11525 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
11528 if (reg_class_subset_p (rclass
, FP_REGS
))
11531 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8))
11532 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
11533 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
11536 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
11537 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
11540 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (mode
, x
))
11541 /* We can force the constant to memory and use lwc1
11542 and ldc1. As above, we will use pairs of lwc1s if
11543 ldc1 is not supported. */
11546 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
11547 /* In this case we can use mov.fmt. */
11550 /* Otherwise, we need to reload through an integer register. */
11553 if (FP_REG_P (regno
))
11554 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
11559 /* Implement TARGET_MODE_REP_EXTENDED. */
11562 mips_mode_rep_extended (enum machine_mode mode
, enum machine_mode mode_rep
)
11564 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
11565 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
11566 return SIGN_EXTEND
;
11571 /* Implement TARGET_VALID_POINTER_MODE. */
11574 mips_valid_pointer_mode (enum machine_mode mode
)
11576 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
11579 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
11582 mips_vector_mode_supported_p (enum machine_mode mode
)
11587 return TARGET_PAIRED_SINGLE_FLOAT
;
11602 return TARGET_LOONGSON_VECTORS
;
11609 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11612 mips_scalar_mode_supported_p (enum machine_mode mode
)
11614 if (ALL_FIXED_POINT_MODE_P (mode
)
11615 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
11618 return default_scalar_mode_supported_p (mode
);
11621 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
11623 static enum machine_mode
11624 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED
)
11626 if (TARGET_PAIRED_SINGLE_FLOAT
11632 /* Implement TARGET_INIT_LIBFUNCS. */
11635 mips_init_libfuncs (void)
11637 if (TARGET_FIX_VR4120
)
11639 /* Register the special divsi3 and modsi3 functions needed to work
11640 around VR4120 division errata. */
11641 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
11642 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
11645 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
11647 /* Register the MIPS16 -mhard-float stubs. */
11648 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
11649 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
11650 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
11651 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
11653 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
11654 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
11655 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
11656 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
11657 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
11658 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
11659 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
11661 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
11662 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
11663 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
11665 if (TARGET_DOUBLE_FLOAT
)
11667 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
11668 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
11669 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
11670 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
11672 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
11673 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
11674 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
11675 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
11676 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
11677 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
11678 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
11680 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
11681 "__mips16_extendsfdf2");
11682 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
11683 "__mips16_truncdfsf2");
11684 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
11685 "__mips16_fix_truncdfsi");
11686 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
11687 "__mips16_floatsidf");
11688 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
11689 "__mips16_floatunsidf");
11693 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11694 on an external non-MIPS16 routine to implement __sync_synchronize.
11695 Similarly for the rest of the ll/sc libfuncs. */
11698 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
11699 init_sync_libfuncs (UNITS_PER_WORD
);
11703 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11706 mips_process_load_label (rtx target
)
11708 rtx base
, gp
, intop
;
11709 HOST_WIDE_INT offset
;
11711 mips_multi_start ();
11715 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target
, 0);
11716 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target
, 0);
11720 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target
, 0);
11721 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target
, 0);
11725 gp
= pic_offset_table_rtx
;
11726 if (mips_cfun_has_cprestore_slot_p ())
11728 gp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
11729 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
11730 if (!SMALL_OPERAND (offset
))
11732 intop
= GEN_INT (CONST_HIGH_PART (offset
));
11733 mips_multi_add_insn ("lui\t%0,%1", gp
, intop
, 0);
11734 mips_multi_add_insn ("addu\t%0,%0,%1", gp
, base
, 0);
11737 offset
= CONST_LOW_PART (offset
);
11739 intop
= GEN_INT (offset
);
11740 if (ISA_HAS_LOAD_DELAY
)
11741 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp
, intop
, base
, 0);
11743 mips_multi_add_insn ("lw\t%0,%1(%2)", gp
, intop
, base
, 0);
11745 if (ISA_HAS_LOAD_DELAY
)
11746 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target
, gp
, 0);
11748 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target
, gp
, 0);
11749 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target
, 0);
11754 /* Return the number of instructions needed to load a label into $AT. */
11756 static unsigned int
11757 mips_load_label_num_insns (void)
11759 if (cfun
->machine
->load_label_num_insns
== 0)
11761 mips_process_load_label (pc_rtx
);
11762 cfun
->machine
->load_label_num_insns
= mips_multi_num_insns
;
11764 return cfun
->machine
->load_label_num_insns
;
11767 /* Emit an asm sequence to start a noat block and load the address
11768 of a label into $1. */
11771 mips_output_load_label (rtx target
)
11773 mips_push_asm_switch (&mips_noat
);
11774 if (TARGET_EXPLICIT_RELOCS
)
11776 mips_process_load_label (target
);
11777 mips_multi_write ();
11781 if (Pmode
== DImode
)
11782 output_asm_insn ("dla\t%@,%0", &target
);
11784 output_asm_insn ("la\t%@,%0", &target
);
11788 /* Return the length of INSN. LENGTH is the initial length computed by
11789 attributes in the machine-description file. */
11792 mips_adjust_insn_length (rtx insn
, int length
)
11794 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
11795 of a PIC long-branch sequence. Substitute the correct value. */
11796 if (length
== MAX_PIC_BRANCH_LENGTH
11797 && INSN_CODE (insn
) >= 0
11798 && get_attr_type (insn
) == TYPE_BRANCH
)
11800 /* Add the branch-over instruction and its delay slot, if this
11801 is a conditional branch. */
11802 length
= simplejump_p (insn
) ? 0 : 8;
11804 /* Load the label into $AT and jump to it. Ignore the delay
11805 slot of the jump. */
11806 length
+= 4 * mips_load_label_num_insns() + 4;
11809 /* A unconditional jump has an unfilled delay slot if it is not part
11810 of a sequence. A conditional jump normally has a delay slot, but
11811 does not on MIPS16. */
11812 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
11815 /* See how many nops might be needed to avoid hardware hazards. */
11816 if (!cfun
->machine
->ignore_hazard_length_p
&& INSN_CODE (insn
) >= 0)
11817 switch (get_attr_hazard (insn
))
11831 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
11832 the .md file length attributes are 4-based for both modes.
11833 Adjust the MIPS16 ones here. */
11840 /* Return the assembly code for INSN, which has the operands given by
11841 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
11842 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
11843 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
11844 version of BRANCH_IF_TRUE. */
11847 mips_output_conditional_branch (rtx insn
, rtx
*operands
,
11848 const char *branch_if_true
,
11849 const char *branch_if_false
)
11851 unsigned int length
;
11852 rtx taken
, not_taken
;
11854 gcc_assert (LABEL_P (operands
[0]));
11856 length
= get_attr_length (insn
);
11859 /* Just a simple conditional branch. */
11860 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
11861 return branch_if_true
;
11864 /* Generate a reversed branch around a direct jump. This fallback does
11865 not use branch-likely instructions. */
11866 mips_branch_likely
= false;
11867 not_taken
= gen_label_rtx ();
11868 taken
= operands
[0];
11870 /* Generate the reversed branch to NOT_TAKEN. */
11871 operands
[0] = not_taken
;
11872 output_asm_insn (branch_if_false
, operands
);
11874 /* If INSN has a delay slot, we must provide delay slots for both the
11875 branch to NOT_TAKEN and the conditional jump. We must also ensure
11876 that INSN's delay slot is executed in the appropriate cases. */
11877 if (final_sequence
)
11879 /* This first delay slot will always be executed, so use INSN's
11880 delay slot if is not annulled. */
11881 if (!INSN_ANNULLED_BRANCH_P (insn
))
11883 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
11884 asm_out_file
, optimize
, 1, NULL
);
11885 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
11888 output_asm_insn ("nop", 0);
11889 fprintf (asm_out_file
, "\n");
11892 /* Output the unconditional branch to TAKEN. */
11893 if (TARGET_ABSOLUTE_JUMPS
)
11894 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken
);
11897 mips_output_load_label (taken
);
11898 output_asm_insn ("jr\t%@%]%/", 0);
11901 /* Now deal with its delay slot; see above. */
11902 if (final_sequence
)
11904 /* This delay slot will only be executed if the branch is taken.
11905 Use INSN's delay slot if is annulled. */
11906 if (INSN_ANNULLED_BRANCH_P (insn
))
11908 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
11909 asm_out_file
, optimize
, 1, NULL
);
11910 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
11913 output_asm_insn ("nop", 0);
11914 fprintf (asm_out_file
, "\n");
11917 /* Output NOT_TAKEN. */
11918 targetm
.asm_out
.internal_label (asm_out_file
, "L",
11919 CODE_LABEL_NUMBER (not_taken
));
11923 /* Return the assembly code for INSN, which branches to OPERANDS[0]
11924 if some ordering condition is true. The condition is given by
11925 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
11926 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
11927 its second is always zero. */
11930 mips_output_order_conditional_branch (rtx insn
, rtx
*operands
, bool inverted_p
)
11932 const char *branch
[2];
11934 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
11935 Make BRANCH[0] branch on the inverse condition. */
11936 switch (GET_CODE (operands
[1]))
11938 /* These cases are equivalent to comparisons against zero. */
11940 inverted_p
= !inverted_p
;
11941 /* Fall through. */
11943 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%0");
11944 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%0");
11947 /* These cases are always true or always false. */
11949 inverted_p
= !inverted_p
;
11950 /* Fall through. */
11952 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%0");
11953 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%0");
11957 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1z", "%2,%0");
11958 branch
[inverted_p
] = MIPS_BRANCH ("b%N1z", "%2,%0");
11961 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
11964 /* Start a block of code that needs access to the LL, SC and SYNC
11968 mips_start_ll_sc_sync_block (void)
11970 if (!ISA_HAS_LL_SC
)
11972 output_asm_insn (".set\tpush", 0);
11973 output_asm_insn (".set\tmips2", 0);
11977 /* End a block started by mips_start_ll_sc_sync_block. */
11980 mips_end_ll_sc_sync_block (void)
11982 if (!ISA_HAS_LL_SC
)
11983 output_asm_insn (".set\tpop", 0);
11986 /* Output and/or return the asm template for a sync instruction. */
11989 mips_output_sync (void)
11991 mips_start_ll_sc_sync_block ();
11992 output_asm_insn ("sync", 0);
11993 mips_end_ll_sc_sync_block ();
11997 /* Return the asm template associated with sync_insn1 value TYPE.
11998 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12000 static const char *
12001 mips_sync_insn1_template (enum attr_sync_insn1 type
, bool is_64bit_p
)
12005 case SYNC_INSN1_MOVE
:
12006 return "move\t%0,%z2";
12007 case SYNC_INSN1_LI
:
12008 return "li\t%0,%2";
12009 case SYNC_INSN1_ADDU
:
12010 return is_64bit_p
? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12011 case SYNC_INSN1_ADDIU
:
12012 return is_64bit_p
? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12013 case SYNC_INSN1_SUBU
:
12014 return is_64bit_p
? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12015 case SYNC_INSN1_AND
:
12016 return "and\t%0,%1,%z2";
12017 case SYNC_INSN1_ANDI
:
12018 return "andi\t%0,%1,%2";
12019 case SYNC_INSN1_OR
:
12020 return "or\t%0,%1,%z2";
12021 case SYNC_INSN1_ORI
:
12022 return "ori\t%0,%1,%2";
12023 case SYNC_INSN1_XOR
:
12024 return "xor\t%0,%1,%z2";
12025 case SYNC_INSN1_XORI
:
12026 return "xori\t%0,%1,%2";
12028 gcc_unreachable ();
12031 /* Return the asm template associated with sync_insn2 value TYPE. */
12033 static const char *
12034 mips_sync_insn2_template (enum attr_sync_insn2 type
)
12038 case SYNC_INSN2_NOP
:
12039 gcc_unreachable ();
12040 case SYNC_INSN2_AND
:
12041 return "and\t%0,%1,%z2";
12042 case SYNC_INSN2_XOR
:
12043 return "xor\t%0,%1,%z2";
12044 case SYNC_INSN2_NOT
:
12045 return "nor\t%0,%1,%.";
12047 gcc_unreachable ();
12050 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12051 the value of the one of the sync_* attributes. Return the operand
12052 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12053 have the associated attribute. */
12056 mips_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
12059 default_value
= operands
[index
- 1];
12060 return default_value
;
12063 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12064 sequence for it. */
12067 mips_process_sync_loop (rtx insn
, rtx
*operands
)
12069 rtx at
, mem
, oldval
, newval
, inclusive_mask
, exclusive_mask
;
12070 rtx required_oldval
, insn1_op2
, tmp1
, tmp2
, tmp3
, cmp
;
12071 unsigned int tmp3_insn
;
12072 enum attr_sync_insn1 insn1
;
12073 enum attr_sync_insn2 insn2
;
12076 enum memmodel model
;
12078 /* Read an operand from the sync_WHAT attribute and store it in
12079 variable WHAT. DEFAULT is the default value if no attribute
12081 #define READ_OPERAND(WHAT, DEFAULT) \
12082 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12085 /* Read the memory. */
12086 READ_OPERAND (mem
, 0);
12088 is_64bit_p
= (GET_MODE_BITSIZE (GET_MODE (mem
)) == 64);
12090 /* Read the other attributes. */
12091 at
= gen_rtx_REG (GET_MODE (mem
), AT_REGNUM
);
12092 READ_OPERAND (oldval
, at
);
12093 READ_OPERAND (cmp
, 0);
12094 READ_OPERAND (newval
, at
);
12095 READ_OPERAND (inclusive_mask
, 0);
12096 READ_OPERAND (exclusive_mask
, 0);
12097 READ_OPERAND (required_oldval
, 0);
12098 READ_OPERAND (insn1_op2
, 0);
12099 insn1
= get_attr_sync_insn1 (insn
);
12100 insn2
= get_attr_sync_insn2 (insn
);
12102 /* Don't bother setting CMP result that is never used. */
12103 if (cmp
&& find_reg_note (insn
, REG_UNUSED
, cmp
))
12106 memmodel_attr
= get_attr_sync_memmodel (insn
);
12107 switch (memmodel_attr
)
12110 model
= MEMMODEL_ACQ_REL
;
12113 model
= MEMMODEL_ACQUIRE
;
12116 model
= (enum memmodel
) INTVAL (operands
[memmodel_attr
]);
12119 mips_multi_start ();
12121 /* Output the release side of the memory barrier. */
12122 if (need_atomic_barrier_p (model
, true))
12124 if (required_oldval
== 0 && TARGET_OCTEON
)
12126 /* Octeon doesn't reorder reads, so a full barrier can be
12127 created by using SYNCW to order writes combined with the
12128 write from the following SC. When the SC successfully
12129 completes, we know that all preceding writes are also
12130 committed to the coherent memory system. It is possible
12131 for a single SYNCW to fail, but a pair of them will never
12132 fail, so we use two. */
12133 mips_multi_add_insn ("syncw", NULL
);
12134 mips_multi_add_insn ("syncw", NULL
);
12137 mips_multi_add_insn ("sync", NULL
);
12140 /* Output the branch-back label. */
12141 mips_multi_add_label ("1:");
12143 /* OLDVAL = *MEM. */
12144 mips_multi_add_insn (is_64bit_p
? "lld\t%0,%1" : "ll\t%0,%1",
12145 oldval
, mem
, NULL
);
12147 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12148 if (required_oldval
)
12150 if (inclusive_mask
== 0)
12154 gcc_assert (oldval
!= at
);
12155 mips_multi_add_insn ("and\t%0,%1,%2",
12156 at
, oldval
, inclusive_mask
, NULL
);
12159 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1
, required_oldval
, NULL
);
12161 /* CMP = 0 [delay slot]. */
12163 mips_multi_add_insn ("li\t%0,0", cmp
, NULL
);
12166 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12167 if (exclusive_mask
== 0)
12171 gcc_assert (oldval
!= at
);
12172 mips_multi_add_insn ("and\t%0,%1,%z2",
12173 at
, oldval
, exclusive_mask
, NULL
);
12177 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12179 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12180 at least one instruction in that case. */
12181 if (insn1
== SYNC_INSN1_MOVE
12182 && (tmp1
!= const0_rtx
|| insn2
!= SYNC_INSN2_NOP
))
12186 mips_multi_add_insn (mips_sync_insn1_template (insn1
, is_64bit_p
),
12187 newval
, oldval
, insn1_op2
, NULL
);
12191 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12192 if (insn2
== SYNC_INSN2_NOP
)
12196 mips_multi_add_insn (mips_sync_insn2_template (insn2
),
12197 newval
, tmp2
, inclusive_mask
, NULL
);
12200 tmp3_insn
= mips_multi_last_index ();
12202 /* $AT = $TMP1 | $TMP3. */
12203 if (tmp1
== const0_rtx
|| tmp3
== const0_rtx
)
12205 mips_multi_set_operand (tmp3_insn
, 0, at
);
12210 gcc_assert (tmp1
!= tmp3
);
12211 mips_multi_add_insn ("or\t%0,%1,%2", at
, tmp1
, tmp3
, NULL
);
12214 /* if (!commit (*MEM = $AT)) goto 1.
12216 This will sometimes be a delayed branch; see the write code below
12218 mips_multi_add_insn (is_64bit_p
? "scd\t%0,%1" : "sc\t%0,%1", at
, mem
, NULL
);
12219 mips_multi_add_insn ("beq%?\t%0,%.,1b", at
, NULL
);
12221 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12222 if (insn1
!= SYNC_INSN1_MOVE
&& insn1
!= SYNC_INSN1_LI
&& tmp3
!= newval
)
12224 mips_multi_copy_insn (tmp3_insn
);
12225 mips_multi_set_operand (mips_multi_last_index (), 0, newval
);
12227 else if (!(required_oldval
&& cmp
))
12228 mips_multi_add_insn ("nop", NULL
);
12230 /* CMP = 1 -- either standalone or in a delay slot. */
12231 if (required_oldval
&& cmp
)
12232 mips_multi_add_insn ("li\t%0,1", cmp
, NULL
);
12234 /* Output the acquire side of the memory barrier. */
12235 if (TARGET_SYNC_AFTER_SC
&& need_atomic_barrier_p (model
, false))
12236 mips_multi_add_insn ("sync", NULL
);
12238 /* Output the exit label, if needed. */
12239 if (required_oldval
)
12240 mips_multi_add_label ("2:");
12242 #undef READ_OPERAND
12245 /* Output and/or return the asm template for sync loop INSN, which has
12246 the operands given by OPERANDS. */
12249 mips_output_sync_loop (rtx insn
, rtx
*operands
)
12251 mips_process_sync_loop (insn
, operands
);
12253 /* Use branch-likely instructions to work around the LL/SC R10000
12255 mips_branch_likely
= TARGET_FIX_R10000
;
12257 mips_push_asm_switch (&mips_noreorder
);
12258 mips_push_asm_switch (&mips_nomacro
);
12259 mips_push_asm_switch (&mips_noat
);
12260 mips_start_ll_sc_sync_block ();
12262 mips_multi_write ();
12264 mips_end_ll_sc_sync_block ();
12265 mips_pop_asm_switch (&mips_noat
);
12266 mips_pop_asm_switch (&mips_nomacro
);
12267 mips_pop_asm_switch (&mips_noreorder
);
12272 /* Return the number of individual instructions in sync loop INSN,
12273 which has the operands given by OPERANDS. */
12276 mips_sync_loop_insns (rtx insn
, rtx
*operands
)
12278 mips_process_sync_loop (insn
, operands
);
12279 return mips_multi_num_insns
;
12282 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12283 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12285 When working around R4000 and R4400 errata, we need to make sure that
12286 the division is not immediately followed by a shift[1][2]. We also
12287 need to stop the division from being put into a branch delay slot[3].
12288 The easiest way to avoid both problems is to add a nop after the
12289 division. When a divide-by-zero check is needed, this nop can be
12290 used to fill the branch delay slot.
12292 [1] If a double-word or a variable shift executes immediately
12293 after starting an integer division, the shift may give an
12294 incorrect result. See quotations of errata #16 and #28 from
12295 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12296 in mips.md for details.
12298 [2] A similar bug to [1] exists for all revisions of the
12299 R4000 and the R4400 when run in an MC configuration.
12300 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12302 "19. In this following sequence:
12304 ddiv (or ddivu or div or divu)
12305 dsll32 (or dsrl32, dsra32)
12307 if an MPT stall occurs, while the divide is slipping the cpu
12308 pipeline, then the following double shift would end up with an
12311 Workaround: The compiler needs to avoid generating any
12312 sequence with divide followed by extended double shift."
12314 This erratum is also present in "MIPS R4400MC Errata, Processor
12315 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12316 & 3.0" as errata #10 and #4, respectively.
12318 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12319 (also valid for MIPS R4000MC processors):
12321 "52. R4000SC: This bug does not apply for the R4000PC.
12323 There are two flavors of this bug:
12325 1) If the instruction just after divide takes an RF exception
12326 (tlb-refill, tlb-invalid) and gets an instruction cache
12327 miss (both primary and secondary) and the line which is
12328 currently in secondary cache at this index had the first
12329 data word, where the bits 5..2 are set, then R4000 would
12330 get a wrong result for the div.
12335 ------------------- # end-of page. -tlb-refill
12340 ------------------- # end-of page. -tlb-invalid
12343 2) If the divide is in the taken branch delay slot, where the
12344 target takes RF exception and gets an I-cache miss for the
12345 exception vector or where I-cache miss occurs for the
12346 target address, under the above mentioned scenarios, the
12347 div would get wrong results.
12350 j r2 # to next page mapped or unmapped
12351 div r8,r9 # this bug would be there as long
12352 # as there is an ICache miss and
12353 nop # the "data pattern" is present
12356 beq r0, r0, NextPage # to Next page
12360 This bug is present for div, divu, ddiv, and ddivu
12363 Workaround: For item 1), OS could make sure that the next page
12364 after the divide instruction is also mapped. For item 2), the
12365 compiler could make sure that the divide instruction is not in
12366 the branch delay slot."
12368 These processors have PRId values of 0x00004220 and 0x00004300 for
12369 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12372 mips_output_division (const char *division
, rtx
*operands
)
12377 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
12379 output_asm_insn (s
, operands
);
12382 if (TARGET_CHECK_ZERO_DIV
)
12386 output_asm_insn (s
, operands
);
12387 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
12389 else if (GENERATE_DIVIDE_TRAPS
)
12391 /* Avoid long replay penalty on load miss by putting the trap before
12394 output_asm_insn ("teq\t%2,%.,7", operands
);
12397 output_asm_insn (s
, operands
);
12398 s
= "teq\t%2,%.,7";
12403 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
12404 output_asm_insn (s
, operands
);
12405 s
= "break\t7%)\n1:";
12411 /* Return true if IN_INSN is a multiply-add or multiply-subtract
12412 instruction and if OUT_INSN assigns to the accumulator operand. */
12415 mips_linked_madd_p (rtx out_insn
, rtx in_insn
)
12417 enum attr_accum_in accum_in
;
12418 int accum_in_opnum
;
12421 if (recog_memoized (in_insn
) < 0)
12424 accum_in
= get_attr_accum_in (in_insn
);
12425 if (accum_in
== ACCUM_IN_NONE
)
12428 accum_in_opnum
= accum_in
- ACCUM_IN_0
;
12430 extract_insn (in_insn
);
12431 gcc_assert (accum_in_opnum
< recog_data
.n_operands
);
12432 accum_in_op
= recog_data
.operand
[accum_in_opnum
];
12434 return reg_set_p (accum_in_op
, out_insn
);
12437 /* True if the dependency between OUT_INSN and IN_INSN is on the store
12438 data rather than the address. We need this because the cprestore
12439 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
12440 which causes the default routine to abort. We just return false
12444 mips_store_data_bypass_p (rtx out_insn
, rtx in_insn
)
12446 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
12449 return !store_data_bypass_p (out_insn
, in_insn
);
12453 /* Variables and flags used in scheduler hooks when tuning for
12457 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
12460 /* If true, then next ALU1/2 instruction will go to ALU1. */
12463 /* If true, then next FALU1/2 unstruction will go to FALU1. */
12466 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
12467 int alu1_core_unit_code
;
12468 int alu2_core_unit_code
;
12469 int falu1_core_unit_code
;
12470 int falu2_core_unit_code
;
12472 /* True if current cycle has a multi instruction.
12473 This flag is used in mips_ls2_dfa_post_advance_cycle. */
12474 bool cycle_has_multi_p
;
12476 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
12477 These are used in mips_ls2_dfa_post_advance_cycle to initialize
12479 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
12480 instruction to go ALU1. */
12481 rtx alu1_turn_enabled_insn
;
12482 rtx alu2_turn_enabled_insn
;
12483 rtx falu1_turn_enabled_insn
;
12484 rtx falu2_turn_enabled_insn
;
12487 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
12488 dependencies have no cost, except on the 20Kc where output-dependence
12489 is treated like input-dependence. */
12492 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED
, rtx link
,
12493 rtx dep ATTRIBUTE_UNUSED
, int cost
)
12495 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
12498 if (REG_NOTE_KIND (link
) != 0)
12503 /* Return the number of instructions that can be issued per cycle. */
12506 mips_issue_rate (void)
12510 case PROCESSOR_74KC
:
12511 case PROCESSOR_74KF2_1
:
12512 case PROCESSOR_74KF1_1
:
12513 case PROCESSOR_74KF3_2
:
12514 /* The 74k is not strictly quad-issue cpu, but can be seen as one
12515 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
12516 but in reality only a maximum of 3 insns can be issued as
12517 floating-point loads and stores also require a slot in the
12519 case PROCESSOR_R10000
:
12520 /* All R10K Processors are quad-issue (being the first MIPS
12521 processors to support this feature). */
12524 case PROCESSOR_20KC
:
12525 case PROCESSOR_R4130
:
12526 case PROCESSOR_R5400
:
12527 case PROCESSOR_R5500
:
12528 case PROCESSOR_R7000
:
12529 case PROCESSOR_R9000
:
12530 case PROCESSOR_OCTEON
:
12531 case PROCESSOR_OCTEON2
:
12534 case PROCESSOR_SB1
:
12535 case PROCESSOR_SB1A
:
12536 /* This is actually 4, but we get better performance if we claim 3.
12537 This is partly because of unwanted speculative code motion with the
12538 larger number, and partly because in most common cases we can't
12539 reach the theoretical max of 4. */
12542 case PROCESSOR_LOONGSON_2E
:
12543 case PROCESSOR_LOONGSON_2F
:
12544 case PROCESSOR_LOONGSON_3A
:
12547 case PROCESSOR_XLP
:
12548 return (reload_completed
? 4 : 3);
12555 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
12558 mips_ls2_init_dfa_post_cycle_insn (void)
12561 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
12562 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
12566 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
12567 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
12571 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
12572 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
12576 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
12577 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
12580 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
12581 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
12582 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
12583 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
12586 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
12587 Init data used in mips_dfa_post_advance_cycle. */
12590 mips_init_dfa_post_cycle_insn (void)
12592 if (TUNE_LOONGSON_2EF
)
12593 mips_ls2_init_dfa_post_cycle_insn ();
12596 /* Initialize STATE when scheduling for Loongson 2E/2F.
12597 Support round-robin dispatch scheme by enabling only one of
12598 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
12602 mips_ls2_dfa_post_advance_cycle (state_t state
)
12604 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
12606 /* Though there are no non-pipelined ALU1 insns,
12607 we can get an instruction of type 'multi' before reload. */
12608 gcc_assert (mips_ls2
.cycle_has_multi_p
);
12609 mips_ls2
.alu1_turn_p
= false;
12612 mips_ls2
.cycle_has_multi_p
= false;
12614 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
12615 /* We have a non-pipelined alu instruction in the core,
12616 adjust round-robin counter. */
12617 mips_ls2
.alu1_turn_p
= true;
12619 if (mips_ls2
.alu1_turn_p
)
12621 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
12622 gcc_unreachable ();
12626 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
12627 gcc_unreachable ();
12630 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
12632 /* There are no non-pipelined FALU1 insns. */
12633 gcc_unreachable ();
12634 mips_ls2
.falu1_turn_p
= false;
12637 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
12638 /* We have a non-pipelined falu instruction in the core,
12639 adjust round-robin counter. */
12640 mips_ls2
.falu1_turn_p
= true;
12642 if (mips_ls2
.falu1_turn_p
)
12644 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
12645 gcc_unreachable ();
12649 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
12650 gcc_unreachable ();
12654 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12655 This hook is being called at the start of each cycle. */
12658 mips_dfa_post_advance_cycle (void)
12660 if (TUNE_LOONGSON_2EF
)
12661 mips_ls2_dfa_post_advance_cycle (curr_state
);
12664 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12665 be as wide as the scheduling freedom in the DFA. */
12668 mips_multipass_dfa_lookahead (void)
12670 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12674 if (TUNE_LOONGSON_2EF
|| TUNE_LOONGSON_3A
)
12683 /* Remove the instruction at index LOWER from ready queue READY and
12684 reinsert it in front of the instruction at index HIGHER. LOWER must
12688 mips_promote_ready (rtx
*ready
, int lower
, int higher
)
12693 new_head
= ready
[lower
];
12694 for (i
= lower
; i
< higher
; i
++)
12695 ready
[i
] = ready
[i
+ 1];
12696 ready
[i
] = new_head
;
12699 /* If the priority of the instruction at POS2 in the ready queue READY
12700 is within LIMIT units of that of the instruction at POS1, swap the
12701 instructions if POS2 is not already less than POS1. */
12704 mips_maybe_swap_ready (rtx
*ready
, int pos1
, int pos2
, int limit
)
12707 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
12711 temp
= ready
[pos1
];
12712 ready
[pos1
] = ready
[pos2
];
12713 ready
[pos2
] = temp
;
12717 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12718 that may clobber hi or lo. */
12719 static rtx mips_macc_chains_last_hilo
;
12721 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12722 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12725 mips_macc_chains_record (rtx insn
)
12727 if (get_attr_may_clobber_hilo (insn
))
12728 mips_macc_chains_last_hilo
= insn
;
12731 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
12732 has NREADY elements, looking for a multiply-add or multiply-subtract
12733 instruction that is cumulative with mips_macc_chains_last_hilo.
12734 If there is one, promote it ahead of anything else that might
12735 clobber hi or lo. */
12738 mips_macc_chains_reorder (rtx
*ready
, int nready
)
12742 if (mips_macc_chains_last_hilo
!= 0)
12743 for (i
= nready
- 1; i
>= 0; i
--)
12744 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
12746 for (j
= nready
- 1; j
> i
; j
--)
12747 if (recog_memoized (ready
[j
]) >= 0
12748 && get_attr_may_clobber_hilo (ready
[j
]))
12750 mips_promote_ready (ready
, i
, j
);
12757 /* The last instruction to be scheduled. */
12758 static rtx vr4130_last_insn
;
12760 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
12761 points to an rtx that is initially an instruction. Nullify the rtx
12762 if the instruction uses the value of register X. */
12765 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
12770 insn_ptr
= (rtx
*) data
;
12773 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
12777 /* Return true if there is true register dependence between vr4130_last_insn
12781 vr4130_true_reg_dependence_p (rtx insn
)
12783 note_stores (PATTERN (vr4130_last_insn
),
12784 vr4130_true_reg_dependence_p_1
, &insn
);
12788 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
12789 the ready queue and that INSN2 is the instruction after it, return
12790 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
12791 in which INSN1 and INSN2 can probably issue in parallel, but for
12792 which (INSN2, INSN1) should be less sensitive to instruction
12793 alignment than (INSN1, INSN2). See 4130.md for more details. */
12796 vr4130_swap_insns_p (rtx insn1
, rtx insn2
)
12798 sd_iterator_def sd_it
;
12801 /* Check for the following case:
12803 1) there is some other instruction X with an anti dependence on INSN1;
12804 2) X has a higher priority than INSN2; and
12805 3) X is an arithmetic instruction (and thus has no unit restrictions).
12807 If INSN1 is the last instruction blocking X, it would better to
12808 choose (INSN1, X) over (INSN2, INSN1). */
12809 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
12810 if (DEP_TYPE (dep
) == REG_DEP_ANTI
12811 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
12812 && recog_memoized (DEP_CON (dep
)) >= 0
12813 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
12816 if (vr4130_last_insn
!= 0
12817 && recog_memoized (insn1
) >= 0
12818 && recog_memoized (insn2
) >= 0)
12820 /* See whether INSN1 and INSN2 use different execution units,
12821 or if they are both ALU-type instructions. If so, they can
12822 probably execute in parallel. */
12823 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
12824 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
12825 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
12827 /* If only one of the instructions has a dependence on
12828 vr4130_last_insn, prefer to schedule the other one first. */
12829 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
12830 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
12831 if (dep1_p
!= dep2_p
)
12834 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
12835 is not an ALU-type instruction and if INSN1 uses the same
12836 execution unit. (Note that if this condition holds, we already
12837 know that INSN2 uses a different execution unit.) */
12838 if (class1
!= VR4130_CLASS_ALU
12839 && recog_memoized (vr4130_last_insn
) >= 0
12840 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
12847 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
12848 queue with at least two instructions. Swap the first two if
12849 vr4130_swap_insns_p says that it could be worthwhile. */
12852 vr4130_reorder (rtx
*ready
, int nready
)
12854 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
12855 mips_promote_ready (ready
, nready
- 2, nready
- 1);
12858 /* Record whether last 74k AGEN instruction was a load or store. */
12859 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
12861 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
12862 resets to TYPE_UNKNOWN state. */
12865 mips_74k_agen_init (rtx insn
)
12867 if (!insn
|| CALL_P (insn
) || JUMP_P (insn
))
12868 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
12871 enum attr_type type
= get_attr_type (insn
);
12872 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
12873 mips_last_74k_agen_insn
= type
;
12877 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
12878 loads to be grouped together, and multiple stores to be grouped
12879 together. Swap things around in the ready queue to make this happen. */
12882 mips_74k_agen_reorder (rtx
*ready
, int nready
)
12885 int store_pos
, load_pos
;
12890 for (i
= nready
- 1; i
>= 0; i
--)
12892 rtx insn
= ready
[i
];
12893 if (USEFUL_INSN_P (insn
))
12894 switch (get_attr_type (insn
))
12897 if (store_pos
== -1)
12902 if (load_pos
== -1)
12911 if (load_pos
== -1 || store_pos
== -1)
12914 switch (mips_last_74k_agen_insn
)
12917 /* Prefer to schedule loads since they have a higher latency. */
12919 /* Swap loads to the front of the queue. */
12920 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
12923 /* Swap stores to the front of the queue. */
12924 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
12931 /* Implement TARGET_SCHED_INIT. */
12934 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12935 int max_ready ATTRIBUTE_UNUSED
)
12937 mips_macc_chains_last_hilo
= 0;
12938 vr4130_last_insn
= 0;
12939 mips_74k_agen_init (NULL_RTX
);
12941 /* When scheduling for Loongson2, branch instructions go to ALU1,
12942 therefore basic block is most likely to start with round-robin counter
12943 pointed to ALU2. */
12944 mips_ls2
.alu1_turn_p
= false;
12945 mips_ls2
.falu1_turn_p
= true;
12948 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
12951 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12952 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
12954 if (!reload_completed
12955 && TUNE_MACC_CHAINS
12957 mips_macc_chains_reorder (ready
, *nreadyp
);
12959 if (reload_completed
12961 && !TARGET_VR4130_ALIGN
12963 vr4130_reorder (ready
, *nreadyp
);
12966 mips_74k_agen_reorder (ready
, *nreadyp
);
12969 /* Implement TARGET_SCHED_REORDER. */
12972 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12973 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
12975 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
12976 return mips_issue_rate ();
12979 /* Implement TARGET_SCHED_REORDER2. */
12982 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12983 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
12985 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
12986 return cached_can_issue_more
;
12989 /* Update round-robin counters for ALU1/2 and FALU1/2. */
12992 mips_ls2_variable_issue (rtx insn
)
12994 if (mips_ls2
.alu1_turn_p
)
12996 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
12997 mips_ls2
.alu1_turn_p
= false;
13001 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
13002 mips_ls2
.alu1_turn_p
= true;
13005 if (mips_ls2
.falu1_turn_p
)
13007 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
13008 mips_ls2
.falu1_turn_p
= false;
13012 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
13013 mips_ls2
.falu1_turn_p
= true;
13016 if (recog_memoized (insn
) >= 0)
13017 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
13020 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13023 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13024 rtx insn
, int more
)
13026 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13027 if (USEFUL_INSN_P (insn
))
13029 if (get_attr_type (insn
) != TYPE_GHOST
)
13031 if (!reload_completed
&& TUNE_MACC_CHAINS
)
13032 mips_macc_chains_record (insn
);
13033 vr4130_last_insn
= insn
;
13035 mips_74k_agen_init (insn
);
13036 else if (TUNE_LOONGSON_2EF
)
13037 mips_ls2_variable_issue (insn
);
13040 /* Instructions of type 'multi' should all be split before
13041 the second scheduling pass. */
13042 gcc_assert (!reload_completed
13043 || recog_memoized (insn
) < 0
13044 || get_attr_type (insn
) != TYPE_MULTI
);
13046 cached_can_issue_more
= more
;
13050 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13051 return the first operand of the associated PREF or PREFX insn. */
13054 mips_prefetch_cookie (rtx write
, rtx locality
)
13056 /* store_streamed / load_streamed. */
13057 if (INTVAL (locality
) <= 0)
13058 return GEN_INT (INTVAL (write
) + 4);
13060 /* store / load. */
13061 if (INTVAL (locality
) <= 2)
13064 /* store_retained / load_retained. */
13065 return GEN_INT (INTVAL (write
) + 6);
13068 /* Flags that indicate when a built-in function is available.
13070 BUILTIN_AVAIL_NON_MIPS16
13071 The function is available on the current target, but only
13072 in non-MIPS16 mode. */
13073 #define BUILTIN_AVAIL_NON_MIPS16 1
13075 /* Declare an availability predicate for built-in functions that
13076 require non-MIPS16 mode and also require COND to be true.
13077 NAME is the main part of the predicate's name. */
13078 #define AVAIL_NON_MIPS16(NAME, COND) \
13079 static unsigned int \
13080 mips_builtin_avail_##NAME (void) \
13082 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13085 /* This structure describes a single built-in function. */
13086 struct mips_builtin_description
{
13087 /* The code of the main .md file instruction. See mips_builtin_type
13088 for more information. */
13089 enum insn_code icode
;
13091 /* The floating-point comparison code to use with ICODE, if any. */
13092 enum mips_fp_condition cond
;
13094 /* The name of the built-in function. */
13097 /* Specifies how the function should be expanded. */
13098 enum mips_builtin_type builtin_type
;
13100 /* The function's prototype. */
13101 enum mips_function_type function_type
;
13103 /* Whether the function is available. */
13104 unsigned int (*avail
) (void);
13107 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
13108 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
13109 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
13110 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
13111 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
13112 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
13113 AVAIL_NON_MIPS16 (dsp_64
, TARGET_64BIT
&& TARGET_DSP
)
13114 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
13115 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_VECTORS
)
13116 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
13118 /* Construct a mips_builtin_description from the given arguments.
13120 INSN is the name of the associated instruction pattern, without the
13121 leading CODE_FOR_mips_.
13123 CODE is the floating-point condition code associated with the
13124 function. It can be 'f' if the field is not applicable.
13126 NAME is the name of the function itself, without the leading
13129 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13131 AVAIL is the name of the availability predicate, without the leading
13132 mips_builtin_avail_. */
13133 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13134 FUNCTION_TYPE, AVAIL) \
13135 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13136 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13137 mips_builtin_avail_ ## AVAIL }
13139 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13140 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13141 are as for MIPS_BUILTIN. */
13142 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13143 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13145 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13146 are subject to mips_builtin_avail_<AVAIL>. */
13147 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13148 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13149 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13150 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13151 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13153 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13154 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13155 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13156 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13157 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13158 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13160 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13161 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13163 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13164 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13166 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13167 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13170 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13171 are subject to mips_builtin_avail_mips3d. */
13172 #define CMP_4S_BUILTINS(INSN, COND) \
13173 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13174 MIPS_BUILTIN_CMP_ANY, \
13175 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13176 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13177 MIPS_BUILTIN_CMP_ALL, \
13178 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13180 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13181 instruction requires mips_builtin_avail_<AVAIL>. */
13182 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13183 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13184 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13186 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13187 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13190 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13191 #define CMP_BUILTINS(COND) \
13192 MOVTF_BUILTINS (c, COND, paired_single), \
13193 MOVTF_BUILTINS (cabs, COND, mips3d), \
13194 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13195 CMP_PS_BUILTINS (c, COND, paired_single), \
13196 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13197 CMP_4S_BUILTINS (c, COND), \
13198 CMP_4S_BUILTINS (cabs, COND)
13200 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13201 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13202 and AVAIL are as for MIPS_BUILTIN. */
13203 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13204 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13205 FUNCTION_TYPE, AVAIL)
13207 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13208 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13209 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13210 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13211 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13213 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13214 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13215 builtin_description field. */
13216 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13217 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13218 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13219 FUNCTION_TYPE, mips_builtin_avail_loongson }
13221 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13222 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13223 builtin_description field. */
13224 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13225 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13227 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13228 We use functions of this form when the same insn can be usefully applied
13229 to more than one datatype. */
13230 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13231 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13233 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13234 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13235 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13236 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13237 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13238 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13239 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13240 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13242 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13243 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13244 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13245 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13246 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13247 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13248 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13249 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13250 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13251 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13252 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13253 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13254 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13255 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13256 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13257 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13258 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13259 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13260 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13261 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13262 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13263 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13264 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13265 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13266 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13267 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13268 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13269 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13270 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13271 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13273 static const struct mips_builtin_description mips_builtins
[] = {
13274 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13275 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13276 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13277 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13278 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
13279 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
13280 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
13281 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
13283 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
13284 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13285 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13286 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13287 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13289 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
13290 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
13291 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13292 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
13293 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
13294 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13296 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
13297 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
13298 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13299 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
13300 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
13301 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13303 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
13305 /* Built-in functions for the SB-1 processor. */
13306 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
13308 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13309 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13310 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13311 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13312 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13313 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13314 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13315 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13316 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13317 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13318 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13319 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13320 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13321 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13322 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
13323 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
13324 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
13325 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
13326 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
13327 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
13328 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
13329 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
13330 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
13331 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13332 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13333 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13334 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13335 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13336 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13337 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13338 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13339 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
13340 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13341 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13342 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13343 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
13344 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13345 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13346 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13347 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
13348 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
13349 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13350 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
13351 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
13352 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
13353 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13354 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
13355 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
13356 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13357 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13358 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13359 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13360 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13361 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13362 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13363 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13364 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13365 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13366 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13367 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13368 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
13369 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
13370 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13371 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13372 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13373 BPOSGE_BUILTIN (32, dsp
),
13375 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
13376 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
13377 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13378 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13379 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13380 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13381 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13382 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13383 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13384 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13385 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13386 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13387 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13388 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13389 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13390 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13391 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
13392 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
13393 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
13394 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13395 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
13396 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
13397 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
13398 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13399 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13400 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13401 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13402 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13403 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13404 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13405 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13406 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13407 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13408 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13409 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13411 /* Built-in functions for the DSP ASE (32-bit only). */
13412 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13413 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13414 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13415 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13416 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13417 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13418 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13419 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13420 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13421 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13422 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13423 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13424 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13425 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13426 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13427 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13428 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13429 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13430 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13431 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
13432 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
13433 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13434 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
13435 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13436 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
13437 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dsp_32
),
13438 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dsp_32
),
13440 /* Built-in functions for the DSP ASE (64-bit only). */
13441 DIRECT_BUILTIN (ldx
, MIPS_DI_FTYPE_POINTER_SI
, dsp_64
),
13443 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
13444 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13445 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13446 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13447 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13448 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13449 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13450 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13451 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13452 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13454 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
13455 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
13456 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
13457 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
13458 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13459 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13460 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13461 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13462 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13463 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13464 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
13465 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
13466 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13467 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13468 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13469 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13470 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
13471 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13472 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13473 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13474 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
13475 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13476 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13477 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13478 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13479 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13480 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13481 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13482 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13483 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13484 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13485 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13486 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13487 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13488 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13489 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13490 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13491 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13492 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
13493 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
13494 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13495 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13496 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13497 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13498 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13499 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13500 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13501 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13502 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
13503 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13504 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13505 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13506 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13507 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
13508 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
13509 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13510 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13511 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13512 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
13513 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13514 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
13515 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
13516 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
13517 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
13518 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
13519 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
13520 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
13521 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
13522 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
13523 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
13524 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
13525 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
13526 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
13527 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
13528 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
13529 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
13530 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13531 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13532 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13533 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13534 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13535 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13536 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
13537 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
13538 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13539 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13540 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13541 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13542 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13543 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13544 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13545 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13546 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13547 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13548 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13549 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13550 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13551 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13552 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13553 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13555 /* Sundry other built-in functions. */
13556 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
)
13559 /* Index I is the function declaration for mips_builtins[I], or null if the
13560 function isn't defined on this target. */
13561 static GTY(()) tree mips_builtin_decls
[ARRAY_SIZE (mips_builtins
)];
13563 /* MODE is a vector mode whose elements have type TYPE. Return the type
13564 of the vector itself. */
13567 mips_builtin_vector_type (tree type
, enum machine_mode mode
)
13569 static tree types
[2 * (int) MAX_MACHINE_MODE
];
13572 mode_index
= (int) mode
;
13574 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
13575 mode_index
+= MAX_MACHINE_MODE
;
13577 if (types
[mode_index
] == NULL_TREE
)
13578 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
13579 return types
[mode_index
];
13582 /* Return a type for 'const volatile void *'. */
13585 mips_build_cvpointer_type (void)
13589 if (cache
== NULL_TREE
)
13590 cache
= build_pointer_type (build_qualified_type
13592 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
13596 /* Source-level argument types. */
13597 #define MIPS_ATYPE_VOID void_type_node
13598 #define MIPS_ATYPE_INT integer_type_node
13599 #define MIPS_ATYPE_POINTER ptr_type_node
13600 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
13602 /* Standard mode-based argument types. */
13603 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
13604 #define MIPS_ATYPE_SI intSI_type_node
13605 #define MIPS_ATYPE_USI unsigned_intSI_type_node
13606 #define MIPS_ATYPE_DI intDI_type_node
13607 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
13608 #define MIPS_ATYPE_SF float_type_node
13609 #define MIPS_ATYPE_DF double_type_node
13611 /* Vector argument types. */
13612 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
13613 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
13614 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
13615 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
13616 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
13617 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
13618 #define MIPS_ATYPE_UV2SI \
13619 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
13620 #define MIPS_ATYPE_UV4HI \
13621 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
13622 #define MIPS_ATYPE_UV8QI \
13623 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
13625 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
13626 their associated MIPS_ATYPEs. */
13627 #define MIPS_FTYPE_ATYPES1(A, B) \
13628 MIPS_ATYPE_##A, MIPS_ATYPE_##B
13630 #define MIPS_FTYPE_ATYPES2(A, B, C) \
13631 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
13633 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
13634 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
13636 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
13637 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
13640 /* Return the function type associated with function prototype TYPE. */
13643 mips_build_function_type (enum mips_function_type type
)
13645 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
13647 if (types
[(int) type
] == NULL_TREE
)
13650 #define DEF_MIPS_FTYPE(NUM, ARGS) \
13651 case MIPS_FTYPE_NAME##NUM ARGS: \
13652 types[(int) type] \
13653 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
13656 #include "config/mips/mips-ftypes.def"
13657 #undef DEF_MIPS_FTYPE
13659 gcc_unreachable ();
13662 return types
[(int) type
];
13665 /* Implement TARGET_INIT_BUILTINS. */
13668 mips_init_builtins (void)
13670 const struct mips_builtin_description
*d
;
13673 /* Iterate through all of the bdesc arrays, initializing all of the
13674 builtin functions. */
13675 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
13677 d
= &mips_builtins
[i
];
13679 mips_builtin_decls
[i
]
13680 = add_builtin_function (d
->name
,
13681 mips_build_function_type (d
->function_type
),
13682 i
, BUILT_IN_MD
, NULL
, NULL
);
13686 /* Implement TARGET_BUILTIN_DECL. */
13689 mips_builtin_decl (unsigned int code
, bool initialize_p ATTRIBUTE_UNUSED
)
13691 if (code
>= ARRAY_SIZE (mips_builtins
))
13692 return error_mark_node
;
13693 return mips_builtin_decls
[code
];
13696 /* Take argument ARGNO from EXP's argument list and convert it into
13697 an expand operand. Store the operand in *OP. */
13700 mips_prepare_builtin_arg (struct expand_operand
*op
, tree exp
,
13701 unsigned int argno
)
13706 arg
= CALL_EXPR_ARG (exp
, argno
);
13707 value
= expand_normal (arg
);
13708 create_input_operand (op
, value
, TYPE_MODE (TREE_TYPE (arg
)));
13711 /* Expand instruction ICODE as part of a built-in function sequence.
13712 Use the first NOPS elements of OPS as the instruction's operands.
13713 HAS_TARGET_P is true if operand 0 is a target; it is false if the
13714 instruction has no target.
13716 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
13719 mips_expand_builtin_insn (enum insn_code icode
, unsigned int nops
,
13720 struct expand_operand
*ops
, bool has_target_p
)
13722 if (!maybe_expand_insn (icode
, nops
, ops
))
13724 error ("invalid argument to built-in function");
13725 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
13727 return has_target_p
? ops
[0].value
: const0_rtx
;
13730 /* Expand a floating-point comparison for built-in function call EXP.
13731 The first NARGS arguments are the values to be compared. ICODE is
13732 the .md pattern that does the comparison and COND is the condition
13733 that is being tested. Return an rtx for the result. */
13736 mips_expand_builtin_compare_1 (enum insn_code icode
,
13737 enum mips_fp_condition cond
,
13738 tree exp
, int nargs
)
13740 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
13743 /* The instruction should have a target operand, an operand for each
13744 argument, and an operand for COND. */
13745 gcc_assert (nargs
+ 2 == insn_data
[(int) icode
].n_generator_args
);
13748 create_output_operand (&ops
[opno
++], NULL_RTX
,
13749 insn_data
[(int) icode
].operand
[0].mode
);
13750 for (argno
= 0; argno
< nargs
; argno
++)
13751 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
13752 create_integer_operand (&ops
[opno
++], (int) cond
);
13753 return mips_expand_builtin_insn (icode
, opno
, ops
, true);
13756 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
13757 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
13758 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
13759 suggests a good place to put the result. */
13762 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
13765 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
13768 /* Map any target to operand 0. */
13771 create_output_operand (&ops
[opno
++], target
, TYPE_MODE (TREE_TYPE (exp
)));
13773 /* Map the arguments to the other operands. */
13774 gcc_assert (opno
+ call_expr_nargs (exp
)
13775 == insn_data
[icode
].n_generator_args
);
13776 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
13777 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
13779 return mips_expand_builtin_insn (icode
, opno
, ops
, has_target_p
);
13782 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
13783 function; TYPE says which. EXP is the CALL_EXPR that calls the
13784 function, ICODE is the instruction that should be used to compare
13785 the first two arguments, and COND is the condition it should test.
13786 TARGET, if nonnull, suggests a good place to put the result. */
13789 mips_expand_builtin_movtf (enum mips_builtin_type type
,
13790 enum insn_code icode
, enum mips_fp_condition cond
,
13791 rtx target
, tree exp
)
13793 struct expand_operand ops
[4];
13796 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
, 2);
13797 create_output_operand (&ops
[0], target
, TYPE_MODE (TREE_TYPE (exp
)));
13798 if (type
== MIPS_BUILTIN_MOVT
)
13800 mips_prepare_builtin_arg (&ops
[2], exp
, 2);
13801 mips_prepare_builtin_arg (&ops
[1], exp
, 3);
13805 mips_prepare_builtin_arg (&ops
[1], exp
, 2);
13806 mips_prepare_builtin_arg (&ops
[2], exp
, 3);
13808 create_fixed_operand (&ops
[3], cmp_result
);
13809 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps
,
13813 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
13814 into TARGET otherwise. Return TARGET. */
13817 mips_builtin_branch_and_move (rtx condition
, rtx target
,
13818 rtx value_if_true
, rtx value_if_false
)
13820 rtx true_label
, done_label
;
13822 true_label
= gen_label_rtx ();
13823 done_label
= gen_label_rtx ();
13825 /* First assume that CONDITION is false. */
13826 mips_emit_move (target
, value_if_false
);
13828 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
13829 emit_jump_insn (gen_condjump (condition
, true_label
));
13830 emit_jump_insn (gen_jump (done_label
));
13833 /* Fix TARGET if CONDITION is true. */
13834 emit_label (true_label
);
13835 mips_emit_move (target
, value_if_true
);
13837 emit_label (done_label
);
13841 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
13842 the CALL_EXPR that calls the function, ICODE is the code of the
13843 comparison instruction, and COND is the condition it should test.
13844 TARGET, if nonnull, suggests a good place to put the boolean result. */
13847 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
13848 enum insn_code icode
, enum mips_fp_condition cond
,
13849 rtx target
, tree exp
)
13851 rtx offset
, condition
, cmp_result
;
13853 if (target
== 0 || GET_MODE (target
) != SImode
)
13854 target
= gen_reg_rtx (SImode
);
13855 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
,
13856 call_expr_nargs (exp
));
13858 /* If the comparison sets more than one register, we define the result
13859 to be 0 if all registers are false and -1 if all registers are true.
13860 The value of the complete result is indeterminate otherwise. */
13861 switch (builtin_type
)
13863 case MIPS_BUILTIN_CMP_ALL
:
13864 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
13865 return mips_builtin_branch_and_move (condition
, target
,
13866 const0_rtx
, const1_rtx
);
13868 case MIPS_BUILTIN_CMP_UPPER
:
13869 case MIPS_BUILTIN_CMP_LOWER
:
13870 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
13871 condition
= gen_single_cc (cmp_result
, offset
);
13872 return mips_builtin_branch_and_move (condition
, target
,
13873 const1_rtx
, const0_rtx
);
13876 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
13877 return mips_builtin_branch_and_move (condition
, target
,
13878 const1_rtx
, const0_rtx
);
13882 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
13883 if nonnull, suggests a good place to put the boolean result. */
13886 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
13888 rtx condition
, cmp_result
;
13891 if (target
== 0 || GET_MODE (target
) != SImode
)
13892 target
= gen_reg_rtx (SImode
);
13894 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
13896 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
13901 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
13902 return mips_builtin_branch_and_move (condition
, target
,
13903 const1_rtx
, const0_rtx
);
13906 /* Implement TARGET_EXPAND_BUILTIN. */
13909 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
13910 enum machine_mode mode
, int ignore
)
13913 unsigned int fcode
, avail
;
13914 const struct mips_builtin_description
*d
;
13916 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13917 fcode
= DECL_FUNCTION_CODE (fndecl
);
13918 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
13919 d
= &mips_builtins
[fcode
];
13920 avail
= d
->avail ();
13921 gcc_assert (avail
!= 0);
13924 error ("built-in function %qE not supported for MIPS16",
13925 DECL_NAME (fndecl
));
13926 return ignore
? const0_rtx
: CONST0_RTX (mode
);
13928 switch (d
->builtin_type
)
13930 case MIPS_BUILTIN_DIRECT
:
13931 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
13933 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
13934 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
13936 case MIPS_BUILTIN_MOVT
:
13937 case MIPS_BUILTIN_MOVF
:
13938 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
13939 d
->cond
, target
, exp
);
13941 case MIPS_BUILTIN_CMP_ANY
:
13942 case MIPS_BUILTIN_CMP_ALL
:
13943 case MIPS_BUILTIN_CMP_UPPER
:
13944 case MIPS_BUILTIN_CMP_LOWER
:
13945 case MIPS_BUILTIN_CMP_SINGLE
:
13946 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
13947 d
->cond
, target
, exp
);
13949 case MIPS_BUILTIN_BPOSGE32
:
13950 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
13952 gcc_unreachable ();
13955 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
13956 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
13957 struct mips16_constant
{
13958 struct mips16_constant
*next
;
13961 enum machine_mode mode
;
13964 /* Information about an incomplete MIPS16 constant pool. FIRST is the
13965 first constant, HIGHEST_ADDRESS is the highest address that the first
13966 byte of the pool can have, and INSN_ADDRESS is the current instruction
13968 struct mips16_constant_pool
{
13969 struct mips16_constant
*first
;
13970 int highest_address
;
13974 /* Add constant VALUE to POOL and return its label. MODE is the
13975 value's mode (used for CONST_INTs, etc.). */
13978 mips16_add_constant (struct mips16_constant_pool
*pool
,
13979 rtx value
, enum machine_mode mode
)
13981 struct mips16_constant
**p
, *c
;
13982 bool first_of_size_p
;
13984 /* See whether the constant is already in the pool. If so, return the
13985 existing label, otherwise leave P pointing to the place where the
13986 constant should be added.
13988 Keep the pool sorted in increasing order of mode size so that we can
13989 reduce the number of alignments needed. */
13990 first_of_size_p
= true;
13991 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
13993 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
13994 return (*p
)->label
;
13995 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
13997 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
13998 first_of_size_p
= false;
14001 /* In the worst case, the constant needed by the earliest instruction
14002 will end up at the end of the pool. The entire pool must then be
14003 accessible from that instruction.
14005 When adding the first constant, set the pool's highest address to
14006 the address of the first out-of-range byte. Adjust this address
14007 downwards each time a new constant is added. */
14008 if (pool
->first
== 0)
14009 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14010 of the instruction with the lowest two bits clear. The base PC
14011 value for LDPC has the lowest three bits clear. Assume the worst
14012 case here; namely that the PC-relative instruction occupies the
14013 last 2 bytes in an aligned word. */
14014 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
14015 pool
->highest_address
-= GET_MODE_SIZE (mode
);
14016 if (first_of_size_p
)
14017 /* Take into account the worst possible padding due to alignment. */
14018 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
14020 /* Create a new entry. */
14021 c
= XNEW (struct mips16_constant
);
14024 c
->label
= gen_label_rtx ();
14031 /* Output constant VALUE after instruction INSN and return the last
14032 instruction emitted. MODE is the mode of the constant. */
14035 mips16_emit_constants_1 (enum machine_mode mode
, rtx value
, rtx insn
)
14037 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
14039 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
14040 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
14043 if (SCALAR_FLOAT_MODE_P (mode
))
14044 return emit_insn_after (gen_consttable_float (value
), insn
);
14046 if (VECTOR_MODE_P (mode
))
14050 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
14051 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
14052 CONST_VECTOR_ELT (value
, i
), insn
);
14056 gcc_unreachable ();
14059 /* Dump out the constants in CONSTANTS after INSN. */
14062 mips16_emit_constants (struct mips16_constant
*constants
, rtx insn
)
14064 struct mips16_constant
*c
, *next
;
14068 for (c
= constants
; c
!= NULL
; c
= next
)
14070 /* If necessary, increase the alignment of PC. */
14071 if (align
< GET_MODE_SIZE (c
->mode
))
14073 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
14074 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
14076 align
= GET_MODE_SIZE (c
->mode
);
14078 insn
= emit_label_after (c
->label
, insn
);
14079 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
14085 emit_barrier_after (insn
);
14088 /* Return the length of instruction INSN. */
14091 mips16_insn_length (rtx insn
)
14095 rtx body
= PATTERN (insn
);
14096 if (GET_CODE (body
) == ADDR_VEC
)
14097 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
14098 if (GET_CODE (body
) == ADDR_DIFF_VEC
)
14099 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
14101 return get_attr_length (insn
);
14104 /* If *X is a symbolic constant that refers to the constant pool, add
14105 the constant to POOL and rewrite *X to use the constant's label. */
14108 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
14110 rtx base
, offset
, label
;
14112 split_const (*x
, &base
, &offset
);
14113 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
14115 label
= mips16_add_constant (pool
, copy_rtx (get_pool_constant (base
)),
14116 get_pool_mode (base
));
14117 base
= gen_rtx_LABEL_REF (Pmode
, label
);
14118 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
14122 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14123 INSN is the instruction we're rewriting and POOL points to the current
14125 struct mips16_rewrite_pool_refs_info
{
14127 struct mips16_constant_pool
*pool
;
14130 /* Rewrite *X so that constant pool references refer to the constant's
14131 label instead. DATA points to a mips16_rewrite_pool_refs_info
14135 mips16_rewrite_pool_refs (rtx
*x
, void *data
)
14137 struct mips16_rewrite_pool_refs_info
*info
=
14138 (struct mips16_rewrite_pool_refs_info
*) data
;
14140 if (force_to_mem_operand (*x
, Pmode
))
14142 rtx mem
= force_const_mem (GET_MODE (*x
), *x
);
14143 validate_change (info
->insn
, x
, mem
, false);
14148 mips16_rewrite_pool_constant (info
->pool
, &XEXP (*x
, 0));
14152 /* Don't rewrite the __mips16_rdwr symbol. */
14153 if (GET_CODE (*x
) == UNSPEC
&& XINT (*x
, 1) == UNSPEC_TLS_GET_TP
)
14156 if (TARGET_MIPS16_TEXT_LOADS
)
14157 mips16_rewrite_pool_constant (info
->pool
, x
);
14159 return GET_CODE (*x
) == CONST
? -1 : 0;
14162 /* Return whether CFG is used in mips_reorg. */
14165 mips_cfg_in_reorg (void)
14167 return (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
14168 || TARGET_RELAX_PIC_CALLS
);
14171 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14172 otherwise assume that they are already split. */
14175 mips16_lay_out_constants (bool split_p
)
14177 struct mips16_constant_pool pool
;
14178 struct mips16_rewrite_pool_refs_info info
;
14181 if (!TARGET_MIPS16_PCREL_LOADS
)
14186 if (mips_cfg_in_reorg ())
14187 split_all_insns ();
14189 split_all_insns_noflow ();
14192 memset (&pool
, 0, sizeof (pool
));
14193 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14195 /* Rewrite constant pool references in INSN. */
14196 if (USEFUL_INSN_P (insn
))
14200 for_each_rtx (&PATTERN (insn
), mips16_rewrite_pool_refs
, &info
);
14203 pool
.insn_address
+= mips16_insn_length (insn
);
14205 if (pool
.first
!= NULL
)
14207 /* If there are no natural barriers between the first user of
14208 the pool and the highest acceptable address, we'll need to
14209 create a new instruction to jump around the constant pool.
14210 In the worst case, this instruction will be 4 bytes long.
14212 If it's too late to do this transformation after INSN,
14213 do it immediately before INSN. */
14214 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
14218 label
= gen_label_rtx ();
14220 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
14221 JUMP_LABEL (jump
) = label
;
14222 LABEL_NUSES (label
) = 1;
14223 barrier
= emit_barrier_after (jump
);
14225 emit_label_after (label
, barrier
);
14226 pool
.insn_address
+= 4;
14229 /* See whether the constant pool is now out of range of the first
14230 user. If so, output the constants after the previous barrier.
14231 Note that any instructions between BARRIER and INSN (inclusive)
14232 will use negative offsets to refer to the pool. */
14233 if (pool
.insn_address
> pool
.highest_address
)
14235 mips16_emit_constants (pool
.first
, barrier
);
14239 else if (BARRIER_P (insn
))
14243 mips16_emit_constants (pool
.first
, get_last_insn ());
14246 /* Return true if it is worth r10k_simplify_address's while replacing
14247 an address with X. We are looking for constants, and for addresses
14248 at a known offset from the incoming stack pointer. */
14251 r10k_simplified_address_p (rtx x
)
14253 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
14255 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
14258 /* X is an expression that appears in INSN. Try to use the UD chains
14259 to simplify it, returning the simplified form on success and the
14260 original form otherwise. Replace the incoming value of $sp with
14261 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14264 r10k_simplify_address (rtx x
, rtx insn
)
14266 rtx newx
, op0
, op1
, set
, def_insn
, note
;
14268 struct df_link
*defs
;
14273 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14274 if (op0
!= XEXP (x
, 0))
14275 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
14276 op0
, GET_MODE (XEXP (x
, 0)));
14278 else if (BINARY_P (x
))
14280 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14281 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
14282 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
14283 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
14285 else if (GET_CODE (x
) == LO_SUM
)
14287 /* LO_SUMs can be offset from HIGHs, if we know they won't
14288 overflow. See mips_classify_address for the rationale behind
14290 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14291 if (GET_CODE (op0
) == HIGH
)
14292 newx
= XEXP (x
, 1);
14294 else if (REG_P (x
))
14296 /* Uses are recorded by regno_reg_rtx, not X itself. */
14297 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
14299 defs
= DF_REF_CHAIN (use
);
14301 /* Require a single definition. */
14302 if (defs
&& defs
->next
== NULL
)
14305 if (DF_REF_IS_ARTIFICIAL (def
))
14307 /* Replace the incoming value of $sp with
14308 virtual_incoming_args_rtx. */
14309 if (x
== stack_pointer_rtx
14310 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR
)
14311 newx
= virtual_incoming_args_rtx
;
14313 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
14316 /* Make sure that DEF_INSN is a single set of REG. */
14317 def_insn
= DF_REF_INSN (def
);
14318 if (NONJUMP_INSN_P (def_insn
))
14320 set
= single_set (def_insn
);
14321 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
14323 /* Prefer to use notes, since the def-use chains
14324 are often shorter. */
14325 note
= find_reg_equal_equiv_note (def_insn
);
14327 newx
= XEXP (note
, 0);
14329 newx
= SET_SRC (set
);
14330 newx
= r10k_simplify_address (newx
, def_insn
);
14336 if (newx
&& r10k_simplified_address_p (newx
))
14341 /* Return true if ADDRESS is known to be an uncached address
14342 on R10K systems. */
14345 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
14347 unsigned HOST_WIDE_INT upper
;
14349 /* Check for KSEG1. */
14350 if (address
+ 0x60000000 < 0x20000000)
14353 /* Check for uncached XKPHYS addresses. */
14354 if (Pmode
== DImode
)
14356 upper
= (address
>> 40) & 0xf9ffff;
14357 if (upper
== 0x900000 || upper
== 0xb80000)
14363 /* Return true if we can prove that an access to address X in instruction
14364 INSN would be safe from R10K speculation. This X is a general
14365 expression; it might not be a legitimate address. */
14368 r10k_safe_address_p (rtx x
, rtx insn
)
14371 HOST_WIDE_INT offset_val
;
14373 x
= r10k_simplify_address (x
, insn
);
14375 /* Check for references to the stack frame. It doesn't really matter
14376 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
14377 allows us to assume that accesses to any part of the eventual frame
14378 is safe from speculation at any point in the function. */
14379 mips_split_plus (x
, &base
, &offset_val
);
14380 if (base
== virtual_incoming_args_rtx
14381 && offset_val
>= -cfun
->machine
->frame
.total_size
14382 && offset_val
< cfun
->machine
->frame
.args_size
)
14385 /* Check for uncached addresses. */
14386 if (CONST_INT_P (x
))
14387 return r10k_uncached_address_p (INTVAL (x
));
14389 /* Check for accesses to a static object. */
14390 split_const (x
, &base
, &offset
);
14391 return offset_within_block_p (base
, INTVAL (offset
));
14394 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
14395 an in-range access to an automatic variable, or to an object with
14396 a link-time-constant address. */
14399 r10k_safe_mem_expr_p (tree expr
, HOST_WIDE_INT offset
)
14401 HOST_WIDE_INT bitoffset
, bitsize
;
14402 tree inner
, var_offset
;
14403 enum machine_mode mode
;
14404 int unsigned_p
, volatile_p
;
14406 inner
= get_inner_reference (expr
, &bitsize
, &bitoffset
, &var_offset
, &mode
,
14407 &unsigned_p
, &volatile_p
, false);
14408 if (!DECL_P (inner
) || !DECL_SIZE_UNIT (inner
) || var_offset
)
14411 offset
+= bitoffset
/ BITS_PER_UNIT
;
14412 return offset
>= 0 && offset
< tree_low_cst (DECL_SIZE_UNIT (inner
), 1);
14415 /* A for_each_rtx callback for which DATA points to the instruction
14416 containing *X. Stop the search if we find a MEM that is not safe
14417 from R10K speculation. */
14420 r10k_needs_protection_p_1 (rtx
*loc
, void *data
)
14429 && MEM_OFFSET_KNOWN_P (mem
)
14430 && r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
14433 if (r10k_safe_address_p (XEXP (mem
, 0), (rtx
) data
))
14439 /* A note_stores callback for which DATA points to an instruction pointer.
14440 If *DATA is nonnull, make it null if it X contains a MEM that is not
14441 safe from R10K speculation. */
14444 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
14449 insn_ptr
= (rtx
*) data
;
14450 if (*insn_ptr
&& for_each_rtx (&x
, r10k_needs_protection_p_1
, *insn_ptr
))
14451 *insn_ptr
= NULL_RTX
;
14454 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
14455 Return nonzero if the call is not to a declared function. */
14458 r10k_needs_protection_p_call (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
14467 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_DECL (x
))
14473 /* Return true if instruction INSN needs to be protected by an R10K
14477 r10k_needs_protection_p (rtx insn
)
14480 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_call
, NULL
);
14482 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
14484 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
14485 return insn
== NULL_RTX
;
14488 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_1
, insn
);
14491 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
14492 edge is unconditional. */
14495 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
14500 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
14501 if (!single_succ_p (e
->src
)
14502 || !TEST_BIT (protected_bbs
, e
->src
->index
)
14503 || (e
->flags
& EDGE_COMPLEX
) != 0)
14508 /* Implement -mr10k-cache-barrier= for the current function. */
14511 r10k_insert_cache_barriers (void)
14513 int *rev_post_order
;
14516 sbitmap protected_bbs
;
14517 rtx insn
, end
, unprotected_region
;
14521 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
14525 /* Calculate dominators. */
14526 calculate_dominance_info (CDI_DOMINATORS
);
14528 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
14529 X is protected by a cache barrier. */
14530 protected_bbs
= sbitmap_alloc (last_basic_block
);
14531 sbitmap_zero (protected_bbs
);
14533 /* Iterate over the basic blocks in reverse post-order. */
14534 rev_post_order
= XNEWVEC (int, last_basic_block
);
14535 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
14536 for (i
= 0; i
< n
; i
++)
14538 bb
= BASIC_BLOCK (rev_post_order
[i
]);
14540 /* If this block is only reached by unconditional edges, and if the
14541 source of every edge is protected, the beginning of the block is
14543 if (r10k_protected_bb_p (bb
, protected_bbs
))
14544 unprotected_region
= NULL_RTX
;
14546 unprotected_region
= pc_rtx
;
14547 end
= NEXT_INSN (BB_END (bb
));
14549 /* UNPROTECTED_REGION is:
14551 - null if we are processing a protected region,
14552 - pc_rtx if we are processing an unprotected region but have
14553 not yet found the first instruction in it
14554 - the first instruction in an unprotected region otherwise. */
14555 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
14557 if (unprotected_region
&& USEFUL_INSN_P (insn
))
14559 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
14560 /* This CACHE instruction protects the following code. */
14561 unprotected_region
= NULL_RTX
;
14564 /* See if INSN is the first instruction in this
14565 unprotected region. */
14566 if (unprotected_region
== pc_rtx
)
14567 unprotected_region
= insn
;
14569 /* See if INSN needs to be protected. If so,
14570 we must insert a cache barrier somewhere between
14571 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
14572 clear which position is better performance-wise,
14573 but as a tie-breaker, we assume that it is better
14574 to allow delay slots to be back-filled where
14575 possible, and that it is better not to insert
14576 barriers in the middle of already-scheduled code.
14577 We therefore insert the barrier at the beginning
14579 if (r10k_needs_protection_p (insn
))
14581 emit_insn_before (gen_r10k_cache_barrier (),
14582 unprotected_region
);
14583 unprotected_region
= NULL_RTX
;
14589 /* The called function is not required to protect the exit path.
14590 The code that follows a call is therefore unprotected. */
14591 unprotected_region
= pc_rtx
;
14594 /* Record whether the end of this block is protected. */
14595 if (unprotected_region
== NULL_RTX
)
14596 SET_BIT (protected_bbs
, bb
->index
);
14598 XDELETEVEC (rev_post_order
);
14600 sbitmap_free (protected_bbs
);
14602 free_dominance_info (CDI_DOMINATORS
);
14605 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
14606 otherwise. If INSN has two call rtx, then store the second one in
14610 mips_call_expr_from_insn (rtx insn
, rtx
*second_call
)
14615 if (!CALL_P (insn
))
14618 x
= PATTERN (insn
);
14619 if (GET_CODE (x
) == PARALLEL
)
14621 /* Calls returning complex values have two CALL rtx. Look for the second
14622 one here, and return it via the SECOND_CALL arg. */
14623 x2
= XVECEXP (x
, 0, 1);
14624 if (GET_CODE (x2
) == SET
)
14626 if (GET_CODE (x2
) == CALL
)
14629 x
= XVECEXP (x
, 0, 0);
14631 if (GET_CODE (x
) == SET
)
14633 gcc_assert (GET_CODE (x
) == CALL
);
14638 /* REG is set in DEF. See if the definition is one of the ways we load a
14639 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
14640 If it is, return the symbol reference of the function, otherwise return
14643 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
14644 the values of source registers, otherwise treat such registers as
14645 having an unknown value. */
14648 mips_pic_call_symbol_from_set (df_ref def
, rtx reg
, bool recurse_p
)
14652 if (DF_REF_IS_ARTIFICIAL (def
))
14655 def_insn
= DF_REF_INSN (def
);
14656 set
= single_set (def_insn
);
14657 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
14659 rtx note
, src
, symbol
;
14661 /* First, look at REG_EQUAL/EQUIV notes. */
14662 note
= find_reg_equal_equiv_note (def_insn
);
14663 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
14664 return XEXP (note
, 0);
14666 /* For %call16 references we don't have REG_EQUAL. */
14667 src
= SET_SRC (set
);
14668 symbol
= mips_strip_unspec_call (src
);
14671 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
14675 /* Follow at most one simple register copy. Such copies are
14676 interesting in cases like:
14680 locally_binding_fn (...);
14685 locally_binding_fn (...);
14687 locally_binding_fn (...);
14689 where the load of locally_binding_fn can legitimately be
14690 hoisted or shared. However, we do not expect to see complex
14691 chains of copies, so a full worklist solution to the problem
14692 would probably be overkill. */
14693 if (recurse_p
&& REG_P (src
))
14694 return mips_find_pic_call_symbol (def_insn
, src
, false);
14700 /* Find the definition of the use of REG in INSN. See if the definition
14701 is one of the ways we load a register with a symbol address for a
14702 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
14703 of the function, otherwise return NULL_RTX. RECURSE_P is as for
14704 mips_pic_call_symbol_from_set. */
14707 mips_find_pic_call_symbol (rtx insn
, rtx reg
, bool recurse_p
)
14710 struct df_link
*defs
;
14713 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (reg
)]);
14716 defs
= DF_REF_CHAIN (use
);
14719 symbol
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
14723 /* If we have more than one definition, they need to be identical. */
14724 for (defs
= defs
->next
; defs
; defs
= defs
->next
)
14728 other
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
14729 if (!rtx_equal_p (symbol
, other
))
14736 /* Replace the args_size operand of the call expression CALL with the
14737 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
14740 mips_annotate_pic_call_expr (rtx call
, rtx symbol
)
14744 args_size
= XEXP (call
, 1);
14745 XEXP (call
, 1) = gen_rtx_UNSPEC (GET_MODE (args_size
),
14746 gen_rtvec (2, args_size
, symbol
),
14750 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
14751 if instead of the arg_size argument it contains the call attributes. If
14752 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
14753 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
14757 mips_get_pic_call_symbol (rtx
*operands
, int args_size_opno
)
14759 rtx args_size
, symbol
;
14761 if (!TARGET_RELAX_PIC_CALLS
|| args_size_opno
== -1)
14764 args_size
= operands
[args_size_opno
];
14765 if (GET_CODE (args_size
) != UNSPEC
)
14767 gcc_assert (XINT (args_size
, 1) == UNSPEC_CALL_ATTR
);
14769 symbol
= XVECEXP (args_size
, 0, 1);
14770 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
14772 operands
[args_size_opno
] = symbol
;
14776 /* Use DF to annotate PIC indirect calls with the function symbol they
14780 mips_annotate_pic_calls (void)
14786 FOR_BB_INSNS (bb
, insn
)
14788 rtx call
, reg
, symbol
, second_call
;
14791 call
= mips_call_expr_from_insn (insn
, &second_call
);
14794 gcc_assert (MEM_P (XEXP (call
, 0)));
14795 reg
= XEXP (XEXP (call
, 0), 0);
14799 symbol
= mips_find_pic_call_symbol (insn
, reg
, true);
14802 mips_annotate_pic_call_expr (call
, symbol
);
14804 mips_annotate_pic_call_expr (second_call
, symbol
);
14809 /* A temporary variable used by for_each_rtx callbacks, etc. */
14810 static rtx mips_sim_insn
;
14812 /* A structure representing the state of the processor pipeline.
14813 Used by the mips_sim_* family of functions. */
14815 /* The maximum number of instructions that can be issued in a cycle.
14816 (Caches mips_issue_rate.) */
14817 unsigned int issue_rate
;
14819 /* The current simulation time. */
14822 /* How many more instructions can be issued in the current cycle. */
14823 unsigned int insns_left
;
14825 /* LAST_SET[X].INSN is the last instruction to set register X.
14826 LAST_SET[X].TIME is the time at which that instruction was issued.
14827 INSN is null if no instruction has yet set register X. */
14831 } last_set
[FIRST_PSEUDO_REGISTER
];
14833 /* The pipeline's current DFA state. */
14837 /* Reset STATE to the initial simulation state. */
14840 mips_sim_reset (struct mips_sim
*state
)
14843 state
->insns_left
= state
->issue_rate
;
14844 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
14845 state_reset (state
->dfa_state
);
14848 /* Initialize STATE before its first use. DFA_STATE points to an
14849 allocated but uninitialized DFA state. */
14852 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
14854 state
->issue_rate
= mips_issue_rate ();
14855 state
->dfa_state
= dfa_state
;
14856 mips_sim_reset (state
);
14859 /* Advance STATE by one clock cycle. */
14862 mips_sim_next_cycle (struct mips_sim
*state
)
14865 state
->insns_left
= state
->issue_rate
;
14866 state_transition (state
->dfa_state
, 0);
14869 /* Advance simulation state STATE until instruction INSN can read
14873 mips_sim_wait_reg (struct mips_sim
*state
, rtx insn
, rtx reg
)
14875 unsigned int regno
, end_regno
;
14877 end_regno
= END_REGNO (reg
);
14878 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
14879 if (state
->last_set
[regno
].insn
!= 0)
14883 t
= (state
->last_set
[regno
].time
14884 + insn_latency (state
->last_set
[regno
].insn
, insn
));
14885 while (state
->time
< t
)
14886 mips_sim_next_cycle (state
);
14890 /* A for_each_rtx callback. If *X is a register, advance simulation state
14891 DATA until mips_sim_insn can read the register's value. */
14894 mips_sim_wait_regs_2 (rtx
*x
, void *data
)
14897 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *x
);
14901 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
14904 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
14906 for_each_rtx (x
, mips_sim_wait_regs_2
, data
);
14909 /* Advance simulation state STATE until all of INSN's register
14910 dependencies are satisfied. */
14913 mips_sim_wait_regs (struct mips_sim
*state
, rtx insn
)
14915 mips_sim_insn
= insn
;
14916 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
14919 /* Advance simulation state STATE until the units required by
14920 instruction INSN are available. */
14923 mips_sim_wait_units (struct mips_sim
*state
, rtx insn
)
14927 tmp_state
= alloca (state_size ());
14928 while (state
->insns_left
== 0
14929 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
14930 state_transition (tmp_state
, insn
) >= 0))
14931 mips_sim_next_cycle (state
);
14934 /* Advance simulation state STATE until INSN is ready to issue. */
14937 mips_sim_wait_insn (struct mips_sim
*state
, rtx insn
)
14939 mips_sim_wait_regs (state
, insn
);
14940 mips_sim_wait_units (state
, insn
);
14943 /* mips_sim_insn has just set X. Update the LAST_SET array
14944 in simulation state DATA. */
14947 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
14949 struct mips_sim
*state
;
14951 state
= (struct mips_sim
*) data
;
14954 unsigned int regno
, end_regno
;
14956 end_regno
= END_REGNO (x
);
14957 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
14959 state
->last_set
[regno
].insn
= mips_sim_insn
;
14960 state
->last_set
[regno
].time
= state
->time
;
14965 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
14966 can issue immediately (i.e., that mips_sim_wait_insn has already
14970 mips_sim_issue_insn (struct mips_sim
*state
, rtx insn
)
14972 state_transition (state
->dfa_state
, insn
);
14973 state
->insns_left
--;
14975 mips_sim_insn
= insn
;
14976 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
14979 /* Simulate issuing a NOP in state STATE. */
14982 mips_sim_issue_nop (struct mips_sim
*state
)
14984 if (state
->insns_left
== 0)
14985 mips_sim_next_cycle (state
);
14986 state
->insns_left
--;
14989 /* Update simulation state STATE so that it's ready to accept the instruction
14990 after INSN. INSN should be part of the main rtl chain, not a member of a
14994 mips_sim_finish_insn (struct mips_sim
*state
, rtx insn
)
14996 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
14998 mips_sim_issue_nop (state
);
15000 switch (GET_CODE (SEQ_BEGIN (insn
)))
15004 /* We can't predict the processor state after a call or label. */
15005 mips_sim_reset (state
);
15009 /* The delay slots of branch likely instructions are only executed
15010 when the branch is taken. Therefore, if the caller has simulated
15011 the delay slot instruction, STATE does not really reflect the state
15012 of the pipeline for the instruction after the delay slot. Also,
15013 branch likely instructions tend to incur a penalty when not taken,
15014 so there will probably be an extra delay between the branch and
15015 the instruction after the delay slot. */
15016 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
15017 mips_sim_reset (state
);
15025 /* The VR4130 pipeline issues aligned pairs of instructions together,
15026 but it stalls the second instruction if it depends on the first.
15027 In order to cut down the amount of logic required, this dependence
15028 check is not based on a full instruction decode. Instead, any non-SPECIAL
15029 instruction is assumed to modify the register specified by bits 20-16
15030 (which is usually the "rt" field).
15032 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15033 input, so we can end up with a false dependence between the branch
15034 and its delay slot. If this situation occurs in instruction INSN,
15035 try to avoid it by swapping rs and rt. */
15038 vr4130_avoid_branch_rt_conflict (rtx insn
)
15042 first
= SEQ_BEGIN (insn
);
15043 second
= SEQ_END (insn
);
15045 && NONJUMP_INSN_P (second
)
15046 && GET_CODE (PATTERN (first
)) == SET
15047 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
15048 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
15050 /* Check for the right kind of condition. */
15051 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
15052 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
15053 && REG_P (XEXP (cond
, 0))
15054 && REG_P (XEXP (cond
, 1))
15055 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
15056 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
15058 /* SECOND mentions the rt register but not the rs register. */
15059 rtx tmp
= XEXP (cond
, 0);
15060 XEXP (cond
, 0) = XEXP (cond
, 1);
15061 XEXP (cond
, 1) = tmp
;
15066 /* Implement -mvr4130-align. Go through each basic block and simulate the
15067 processor pipeline. If we find that a pair of instructions could execute
15068 in parallel, and the first of those instructions is not 8-byte aligned,
15069 insert a nop to make it aligned. */
15072 vr4130_align_insns (void)
15074 struct mips_sim state
;
15075 rtx insn
, subinsn
, last
, last2
, next
;
15080 /* LAST is the last instruction before INSN to have a nonzero length.
15081 LAST2 is the last such instruction before LAST. */
15085 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15088 mips_sim_init (&state
, alloca (state_size ()));
15089 for (insn
= get_insns (); insn
!= 0; insn
= next
)
15091 unsigned int length
;
15093 next
= NEXT_INSN (insn
);
15095 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15096 This isn't really related to the alignment pass, but we do it on
15097 the fly to avoid a separate instruction walk. */
15098 vr4130_avoid_branch_rt_conflict (insn
);
15100 if (USEFUL_INSN_P (insn
))
15101 FOR_EACH_SUBINSN (subinsn
, insn
)
15103 mips_sim_wait_insn (&state
, subinsn
);
15105 /* If we want this instruction to issue in parallel with the
15106 previous one, make sure that the previous instruction is
15107 aligned. There are several reasons why this isn't worthwhile
15108 when the second instruction is a call:
15110 - Calls are less likely to be performance critical,
15111 - There's a good chance that the delay slot can execute
15112 in parallel with the call.
15113 - The return address would then be unaligned.
15115 In general, if we're going to insert a nop between instructions
15116 X and Y, it's better to insert it immediately after X. That
15117 way, if the nop makes Y aligned, it will also align any labels
15118 between X and Y. */
15119 if (state
.insns_left
!= state
.issue_rate
15120 && !CALL_P (subinsn
))
15122 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
15124 /* SUBINSN is the first instruction in INSN and INSN is
15125 aligned. We want to align the previous instruction
15126 instead, so insert a nop between LAST2 and LAST.
15128 Note that LAST could be either a single instruction
15129 or a branch with a delay slot. In the latter case,
15130 LAST, like INSN, is already aligned, but the delay
15131 slot must have some extra delay that stops it from
15132 issuing at the same time as the branch. We therefore
15133 insert a nop before the branch in order to align its
15135 emit_insn_after (gen_nop (), last2
);
15138 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
15140 /* SUBINSN is the delay slot of INSN, but INSN is
15141 currently unaligned. Insert a nop between
15142 LAST and INSN to align it. */
15143 emit_insn_after (gen_nop (), last
);
15147 mips_sim_issue_insn (&state
, subinsn
);
15149 mips_sim_finish_insn (&state
, insn
);
15151 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15152 length
= get_attr_length (insn
);
15155 /* If the instruction is an asm statement or multi-instruction
15156 mips.md patern, the length is only an estimate. Insert an
15157 8 byte alignment after it so that the following instructions
15158 can be handled correctly. */
15159 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
15160 && (recog_memoized (insn
) < 0 || length
>= 8))
15162 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
15163 next
= NEXT_INSN (next
);
15164 mips_sim_next_cycle (&state
);
15167 else if (length
& 4)
15168 aligned_p
= !aligned_p
;
15173 /* See whether INSN is an aligned label. */
15174 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
15180 /* This structure records that the current function has a LO_SUM
15181 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15182 the largest offset applied to BASE by all such LO_SUMs. */
15183 struct mips_lo_sum_offset
{
15185 HOST_WIDE_INT offset
;
15188 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15191 mips_hash_base (rtx base
)
15193 int do_not_record_p
;
15195 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
15198 /* Hash-table callbacks for mips_lo_sum_offsets. */
15201 mips_lo_sum_offset_hash (const void *entry
)
15203 return mips_hash_base (((const struct mips_lo_sum_offset
*) entry
)->base
);
15207 mips_lo_sum_offset_eq (const void *entry
, const void *value
)
15209 return rtx_equal_p (((const struct mips_lo_sum_offset
*) entry
)->base
,
15210 (const_rtx
) value
);
15213 /* Look up symbolic constant X in HTAB, which is a hash table of
15214 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
15215 paired with a recorded LO_SUM, otherwise record X in the table. */
15218 mips_lo_sum_offset_lookup (htab_t htab
, rtx x
, enum insert_option option
)
15222 struct mips_lo_sum_offset
*entry
;
15224 /* Split X into a base and offset. */
15225 split_const (x
, &base
, &offset
);
15226 if (UNSPEC_ADDRESS_P (base
))
15227 base
= UNSPEC_ADDRESS (base
);
15229 /* Look up the base in the hash table. */
15230 slot
= htab_find_slot_with_hash (htab
, base
, mips_hash_base (base
), option
);
15234 entry
= (struct mips_lo_sum_offset
*) *slot
;
15235 if (option
== INSERT
)
15239 entry
= XNEW (struct mips_lo_sum_offset
);
15240 entry
->base
= base
;
15241 entry
->offset
= INTVAL (offset
);
15246 if (INTVAL (offset
) > entry
->offset
)
15247 entry
->offset
= INTVAL (offset
);
15250 return INTVAL (offset
) <= entry
->offset
;
15253 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
15254 Record every LO_SUM in *LOC. */
15257 mips_record_lo_sum (rtx
*loc
, void *data
)
15259 if (GET_CODE (*loc
) == LO_SUM
)
15260 mips_lo_sum_offset_lookup ((htab_t
) data
, XEXP (*loc
, 1), INSERT
);
15264 /* Return true if INSN is a SET of an orphaned high-part relocation.
15265 HTAB is a hash table of mips_lo_sum_offsets that describes all the
15266 LO_SUMs in the current function. */
15269 mips_orphaned_high_part_p (htab_t htab
, rtx insn
)
15271 enum mips_symbol_type type
;
15274 set
= single_set (insn
);
15277 /* Check for %his. */
15279 if (GET_CODE (x
) == HIGH
15280 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
15281 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
15283 /* Check for local %gots (and %got_pages, which is redundant but OK). */
15284 if (GET_CODE (x
) == UNSPEC
15285 && XINT (x
, 1) == UNSPEC_LOAD_GOT
15286 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
15287 SYMBOL_CONTEXT_LEA
, &type
)
15288 && type
== SYMBOL_GOTOFF_PAGE
)
15289 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
15294 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
15295 INSN and a previous instruction, avoid it by inserting nops after
15298 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
15299 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
15300 before using the value of that register. *HILO_DELAY counts the
15301 number of instructions since the last hilo hazard (that is,
15302 the number of instructions since the last MFLO or MFHI).
15304 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
15305 for the next instruction.
15307 LO_REG is an rtx for the LO register, used in dependence checking. */
15310 mips_avoid_hazard (rtx after
, rtx insn
, int *hilo_delay
,
15311 rtx
*delayed_reg
, rtx lo_reg
)
15316 pattern
= PATTERN (insn
);
15318 /* Do not put the whole function in .set noreorder if it contains
15319 an asm statement. We don't know whether there will be hazards
15320 between the asm statement and the gcc-generated code. */
15321 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
15322 cfun
->machine
->all_noreorder_p
= false;
15324 /* Ignore zero-length instructions (barriers and the like). */
15325 ninsns
= get_attr_length (insn
) / 4;
15329 /* Work out how many nops are needed. Note that we only care about
15330 registers that are explicitly mentioned in the instruction's pattern.
15331 It doesn't matter that calls use the argument registers or that they
15332 clobber hi and lo. */
15333 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
15334 nops
= 2 - *hilo_delay
;
15335 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
15340 /* Insert the nops between this instruction and the previous one.
15341 Each new nop takes us further from the last hilo hazard. */
15342 *hilo_delay
+= nops
;
15344 emit_insn_after (gen_hazard_nop (), after
);
15346 /* Set up the state for the next instruction. */
15347 *hilo_delay
+= ninsns
;
15349 if (INSN_CODE (insn
) >= 0)
15350 switch (get_attr_hazard (insn
))
15360 set
= single_set (insn
);
15362 *delayed_reg
= SET_DEST (set
);
15367 /* Go through the instruction stream and insert nops where necessary.
15368 Also delete any high-part relocations whose partnering low parts
15369 are now all dead. See if the whole function can then be put into
15370 .set noreorder and .set nomacro. */
15373 mips_reorg_process_insns (void)
15375 rtx insn
, last_insn
, subinsn
, next_insn
, lo_reg
, delayed_reg
;
15379 /* Force all instructions to be split into their final form. */
15380 split_all_insns_noflow ();
15382 /* Recalculate instruction lengths without taking nops into account. */
15383 cfun
->machine
->ignore_hazard_length_p
= true;
15384 shorten_branches (get_insns ());
15386 cfun
->machine
->all_noreorder_p
= true;
15388 /* We don't track MIPS16 PC-relative offsets closely enough to make
15389 a good job of "set .noreorder" code in MIPS16 mode. */
15391 cfun
->machine
->all_noreorder_p
= false;
15393 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
15394 if (!TARGET_EXPLICIT_RELOCS
)
15395 cfun
->machine
->all_noreorder_p
= false;
15397 /* Profiled functions can't be all noreorder because the profiler
15398 support uses assembler macros. */
15400 cfun
->machine
->all_noreorder_p
= false;
15402 /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
15403 because we rely on the assembler to work around some errata. */
15404 if (TARGET_FIX_VR4120
|| TARGET_FIX_24K
)
15405 cfun
->machine
->all_noreorder_p
= false;
15407 /* The same is true for -mfix-vr4130 if we might generate MFLO or
15408 MFHI instructions. Note that we avoid using MFLO and MFHI if
15409 the VR4130 MACC and DMACC instructions are available instead;
15410 see the *mfhilo_{si,di}_macc patterns. */
15411 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
15412 cfun
->machine
->all_noreorder_p
= false;
15414 htab
= htab_create (37, mips_lo_sum_offset_hash
,
15415 mips_lo_sum_offset_eq
, free
);
15417 /* Make a first pass over the instructions, recording all the LO_SUMs. */
15418 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
15419 FOR_EACH_SUBINSN (subinsn
, insn
)
15420 if (USEFUL_INSN_P (subinsn
))
15421 for_each_rtx (&PATTERN (subinsn
), mips_record_lo_sum
, htab
);
15426 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
15428 /* Make a second pass over the instructions. Delete orphaned
15429 high-part relocations or turn them into NOPs. Avoid hazards
15430 by inserting NOPs. */
15431 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
15433 next_insn
= NEXT_INSN (insn
);
15434 if (USEFUL_INSN_P (insn
))
15436 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
15438 /* If we find an orphaned high-part relocation in a delay
15439 slot, it's easier to turn that instruction into a NOP than
15440 to delete it. The delay slot will be a NOP either way. */
15441 FOR_EACH_SUBINSN (subinsn
, insn
)
15442 if (INSN_P (subinsn
))
15444 if (mips_orphaned_high_part_p (htab
, subinsn
))
15446 PATTERN (subinsn
) = gen_nop ();
15447 INSN_CODE (subinsn
) = CODE_FOR_nop
;
15449 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
15450 &delayed_reg
, lo_reg
);
15456 /* INSN is a single instruction. Delete it if it's an
15457 orphaned high-part relocation. */
15458 if (mips_orphaned_high_part_p (htab
, insn
))
15459 delete_insn (insn
);
15460 /* Also delete cache barriers if the last instruction
15461 was an annulled branch. INSN will not be speculatively
15463 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
15465 && JUMP_P (SEQ_BEGIN (last_insn
))
15466 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
15467 delete_insn (insn
);
15470 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
15471 &delayed_reg
, lo_reg
);
15478 htab_delete (htab
);
15481 /* Return true if the function has a long branch instruction. */
15484 mips_has_long_branch_p (void)
15489 /* We need up-to-date instruction lengths. */
15490 shorten_branches (get_insns ());
15492 /* Look for a branch that is longer than normal. The normal length for
15493 non-MIPS16 branches is 8, because the length includes the delay slot.
15494 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
15495 but they have no delay slot. */
15496 normal_length
= (TARGET_MIPS16
? 4 : 8);
15497 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
15498 FOR_EACH_SUBINSN (subinsn
, insn
)
15499 if (JUMP_P (subinsn
)
15500 && USEFUL_INSN_P (subinsn
)
15501 && get_attr_length (subinsn
) > normal_length
15502 && (any_condjump_p (subinsn
) || any_uncondjump_p (subinsn
)))
15508 /* If we are using a GOT, but have not decided to use a global pointer yet,
15509 see whether we need one to implement long branches. Convert the ghost
15510 global-pointer instructions into real ones if so. */
15513 mips_expand_ghost_gp_insns (void)
15515 /* Quick exit if we already know that we will or won't need a
15517 if (!TARGET_USE_GOT
15518 || cfun
->machine
->global_pointer
== INVALID_REGNUM
15519 || mips_must_initialize_gp_p ())
15522 /* Run a full check for long branches. */
15523 if (!mips_has_long_branch_p ())
15526 /* We've now established that we need $gp. */
15527 cfun
->machine
->must_initialize_gp_p
= true;
15528 split_all_insns_noflow ();
15533 /* Subroutine of mips_reorg to manage passes that require DF. */
15536 mips_df_reorg (void)
15538 /* Create def-use chains. */
15539 df_set_flags (DF_EQ_NOTES
);
15540 df_chain_add_problem (DF_UD_CHAIN
);
15543 if (TARGET_RELAX_PIC_CALLS
)
15544 mips_annotate_pic_calls ();
15546 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
15547 r10k_insert_cache_barriers ();
15549 df_finish_pass (false);
15552 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
15553 called very late in mips_reorg, but the caller is required to run
15554 mips16_lay_out_constants on the result. */
15557 mips16_load_branch_target (rtx dest
, rtx src
)
15559 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
15563 if (mips_cfun_has_cprestore_slot_p ())
15564 mips_emit_move (dest
, mips_cprestore_slot (dest
, true));
15566 mips_emit_move (dest
, pic_offset_table_rtx
);
15567 page
= mips_unspec_address (src
, SYMBOL_GOTOFF_PAGE
);
15568 low
= mips_unspec_address (src
, SYMBOL_GOT_PAGE_OFST
);
15569 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
15570 PMODE_INSN (gen_unspec_got
, (dest
, page
))));
15571 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
15572 gen_rtx_LO_SUM (Pmode
, dest
, low
)));
15576 src
= mips_unspec_address (src
, SYMBOL_ABSOLUTE
);
15577 mips_emit_move (dest
, src
);
15581 /* If we're compiling a MIPS16 function, look for and split any long branches.
15582 This must be called after all other instruction modifications in
15586 mips16_split_long_branches (void)
15588 bool something_changed
;
15590 if (!TARGET_MIPS16
)
15593 /* Loop until the alignments for all targets are sufficient. */
15598 shorten_branches (get_insns ());
15599 something_changed
= false;
15600 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
15602 && USEFUL_INSN_P (insn
)
15603 && get_attr_length (insn
) > 8
15604 && (any_condjump_p (insn
) || any_uncondjump_p (insn
)))
15606 rtx old_label
, new_label
, temp
, saved_temp
;
15607 rtx target
, jump
, jump_sequence
;
15611 /* Free up a MIPS16 register by saving it in $1. */
15612 saved_temp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
15613 temp
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
15614 emit_move_insn (saved_temp
, temp
);
15616 /* Load the branch target into TEMP. */
15617 old_label
= JUMP_LABEL (insn
);
15618 target
= gen_rtx_LABEL_REF (Pmode
, old_label
);
15619 mips16_load_branch_target (temp
, target
);
15621 /* Jump to the target and restore the register's
15623 jump
= emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore
,
15624 (temp
, temp
, saved_temp
)));
15625 JUMP_LABEL (jump
) = old_label
;
15626 LABEL_NUSES (old_label
)++;
15628 /* Rewrite any symbolic references that are supposed to use
15629 a PC-relative constant pool. */
15630 mips16_lay_out_constants (false);
15632 if (simplejump_p (insn
))
15633 /* We're going to replace INSN with a longer form. */
15634 new_label
= NULL_RTX
;
15637 /* Create a branch-around label for the original
15639 new_label
= gen_label_rtx ();
15640 emit_label (new_label
);
15643 jump_sequence
= get_insns ();
15646 emit_insn_after (jump_sequence
, insn
);
15648 invert_jump (insn
, new_label
, false);
15650 delete_insn (insn
);
15651 something_changed
= true;
15654 while (something_changed
);
15657 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
15662 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
15663 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
15664 to date if the CFG is available. */
15665 if (mips_cfg_in_reorg ())
15666 compute_bb_for_insn ();
15667 mips16_lay_out_constants (true);
15668 if (mips_cfg_in_reorg ())
15671 free_bb_for_insn ();
15674 if (optimize
> 0 && flag_delayed_branch
)
15675 dbr_schedule (get_insns ());
15676 mips_reorg_process_insns ();
15678 && TARGET_EXPLICIT_RELOCS
15680 && TARGET_VR4130_ALIGN
)
15681 vr4130_align_insns ();
15682 if (mips_expand_ghost_gp_insns ())
15683 /* The expansion could invalidate some of the VR4130 alignment
15684 optimizations, but this should be an extremely rare case anyhow. */
15685 mips_reorg_process_insns ();
15686 mips16_split_long_branches ();
15689 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
15690 in order to avoid duplicating too much logic from elsewhere. */
15693 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
15694 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
15697 rtx this_rtx
, temp1
, temp2
, insn
, fnaddr
;
15698 bool use_sibcall_p
;
15700 /* Pretend to be a post-reload pass while generating rtl. */
15701 reload_completed
= 1;
15703 /* Mark the end of the (empty) prologue. */
15704 emit_note (NOTE_INSN_PROLOGUE_END
);
15706 /* Determine if we can use a sibcall to call FUNCTION directly. */
15707 fnaddr
= XEXP (DECL_RTL (function
), 0);
15708 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
15709 && const_call_insn_operand (fnaddr
, Pmode
));
15711 /* Determine if we need to load FNADDR from the GOT. */
15713 && (mips_got_symbol_type_p
15714 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
15716 /* Pick a global pointer. Use a call-clobbered register if
15717 TARGET_CALL_SAVED_GP. */
15718 cfun
->machine
->global_pointer
15719 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
15720 cfun
->machine
->must_initialize_gp_p
= true;
15721 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
15723 /* Set up the global pointer for n32 or n64 abicalls. */
15724 mips_emit_loadgp ();
15727 /* We need two temporary registers in some cases. */
15728 temp1
= gen_rtx_REG (Pmode
, 2);
15729 temp2
= gen_rtx_REG (Pmode
, 3);
15731 /* Find out which register contains the "this" pointer. */
15732 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
15733 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
15735 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
15737 /* Add DELTA to THIS_RTX. */
15740 rtx offset
= GEN_INT (delta
);
15741 if (!SMALL_OPERAND (delta
))
15743 mips_emit_move (temp1
, offset
);
15746 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
15749 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
15750 if (vcall_offset
!= 0)
15754 /* Set TEMP1 to *THIS_RTX. */
15755 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
15757 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
15758 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
15760 /* Load the offset and add it to THIS_RTX. */
15761 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
15762 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
15765 /* Jump to the target function. Use a sibcall if direct jumps are
15766 allowed, otherwise load the address into a register first. */
15769 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
15770 SIBLING_CALL_P (insn
) = 1;
15774 /* This is messy. GAS treats "la $25,foo" as part of a call
15775 sequence and may allow a global "foo" to be lazily bound.
15776 The general move patterns therefore reject this combination.
15778 In this context, lazy binding would actually be OK
15779 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
15780 TARGET_CALL_SAVED_GP; see mips_load_call_address.
15781 We must therefore load the address via a temporary
15782 register if mips_dangerous_for_la25_p.
15784 If we jump to the temporary register rather than $25,
15785 the assembler can use the move insn to fill the jump's
15788 We can use the same technique for MIPS16 code, where $25
15789 is not a valid JR register. */
15790 if (TARGET_USE_PIC_FN_ADDR_REG
15792 && !mips_dangerous_for_la25_p (fnaddr
))
15793 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
15794 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
15796 if (TARGET_USE_PIC_FN_ADDR_REG
15797 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
15798 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
15799 emit_jump_insn (gen_indirect_jump (temp1
));
15802 /* Run just enough of rest_of_compilation. This sequence was
15803 "borrowed" from alpha.c. */
15804 insn
= get_insns ();
15805 insn_locators_alloc ();
15806 split_all_insns_noflow ();
15807 mips16_lay_out_constants (true);
15808 shorten_branches (insn
);
15809 final_start_function (insn
, file
, 1);
15810 final (insn
, file
, 1);
15811 final_end_function ();
15813 /* Clean up the vars set above. Note that final_end_function resets
15814 the global pointer for us. */
15815 reload_completed
= 0;
15818 /* The last argument passed to mips_set_mips16_mode, or negative if the
15819 function hasn't been called yet. */
15820 static int was_mips16_p
= -1;
15822 /* Set up the target-dependent global state so that it matches the
15823 current function's ISA mode. */
15826 mips_set_mips16_mode (int mips16_p
)
15828 if (mips16_p
== was_mips16_p
)
15831 /* Restore base settings of various flags. */
15832 target_flags
= mips_base_target_flags
;
15833 flag_schedule_insns
= mips_base_schedule_insns
;
15834 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
15835 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
15836 align_loops
= mips_base_align_loops
;
15837 align_jumps
= mips_base_align_jumps
;
15838 align_functions
= mips_base_align_functions
;
15842 /* Switch to MIPS16 mode. */
15843 target_flags
|= MASK_MIPS16
;
15845 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
15846 target_flags
&= ~MASK_SYNCI
;
15848 /* Don't run the scheduler before reload, since it tends to
15849 increase register pressure. */
15850 flag_schedule_insns
= 0;
15852 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
15853 the whole function to be in a single section. */
15854 flag_reorder_blocks_and_partition
= 0;
15856 /* Don't move loop invariants, because it tends to increase
15857 register pressure. It also introduces an extra move in cases
15858 where the constant is the first operand in a two-operand binary
15859 instruction, or when it forms a register argument to a functon
15861 flag_move_loop_invariants
= 0;
15863 target_flags
|= MASK_EXPLICIT_RELOCS
;
15865 /* Experiments suggest we get the best overall section-anchor
15866 results from using the range of an unextended LW or SW. Code
15867 that makes heavy use of byte or short accesses can do better
15868 with ranges of 0...31 and 0...63 respectively, but most code is
15869 sensitive to the range of LW and SW instead. */
15870 targetm
.min_anchor_offset
= 0;
15871 targetm
.max_anchor_offset
= 127;
15873 targetm
.const_anchor
= 0;
15875 /* MIPS16 has no BAL instruction. */
15876 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
15878 /* The R4000 errata don't apply to any known MIPS16 cores.
15879 It's simpler to make the R4000 fixes and MIPS16 mode
15880 mutually exclusive. */
15881 target_flags
&= ~MASK_FIX_R4000
;
15883 if (flag_pic
&& !TARGET_OLDABI
)
15884 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
15887 sorry ("MIPS16 -mxgot code");
15889 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
15890 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
15894 /* Switch to normal (non-MIPS16) mode. */
15895 target_flags
&= ~MASK_MIPS16
;
15897 /* Provide default values for align_* for 64-bit targets. */
15900 if (align_loops
== 0)
15902 if (align_jumps
== 0)
15904 if (align_functions
== 0)
15905 align_functions
= 8;
15908 targetm
.min_anchor_offset
= -32768;
15909 targetm
.max_anchor_offset
= 32767;
15911 targetm
.const_anchor
= 0x8000;
15914 /* (Re)initialize MIPS target internals for new ISA. */
15915 mips_init_relocs ();
15919 if (!mips16_globals
)
15920 mips16_globals
= save_target_globals ();
15922 restore_target_globals (mips16_globals
);
15925 restore_target_globals (&default_target_globals
);
15927 was_mips16_p
= mips16_p
;
15930 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
15931 function should use the MIPS16 ISA and switch modes accordingly. */
15934 mips_set_current_function (tree fndecl
)
15936 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl
));
15939 /* Allocate a chunk of memory for per-function machine-dependent data. */
15941 static struct machine_function
*
15942 mips_init_machine_status (void)
15944 return ggc_alloc_cleared_machine_function ();
15947 /* Return the processor associated with the given ISA level, or null
15948 if the ISA isn't valid. */
15950 static const struct mips_cpu_info
*
15951 mips_cpu_info_from_isa (int isa
)
15955 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
15956 if (mips_cpu_info_table
[i
].isa
== isa
)
15957 return mips_cpu_info_table
+ i
;
15962 /* Return a mips_cpu_info entry determined by an option valued
15965 static const struct mips_cpu_info
*
15966 mips_cpu_info_from_opt (int opt
)
15970 case MIPS_ARCH_OPTION_FROM_ABI
:
15971 /* 'from-abi' selects the most compatible architecture for the
15972 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
15973 ABIs. For the EABIs, we have to decide whether we're using
15974 the 32-bit or 64-bit version. */
15975 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
15976 : ABI_NEEDS_64BIT_REGS
? 3
15977 : (TARGET_64BIT
? 3 : 1));
15979 case MIPS_ARCH_OPTION_NATIVE
:
15980 gcc_unreachable ();
15983 return &mips_cpu_info_table
[opt
];
15987 /* Return a default mips_cpu_info entry, given that no -march= option
15988 was explicitly specified. */
15990 static const struct mips_cpu_info
*
15991 mips_default_arch (void)
15993 #if defined (MIPS_CPU_STRING_DEFAULT)
15995 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
15996 if (strcmp (mips_cpu_info_table
[i
].name
, MIPS_CPU_STRING_DEFAULT
) == 0)
15997 return mips_cpu_info_table
+ i
;
15998 gcc_unreachable ();
15999 #elif defined (MIPS_ISA_DEFAULT)
16000 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
);
16002 /* 'from-abi' makes a good default: you get whatever the ABI
16004 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI
);
16008 /* Set up globals to generate code for the ISA or processor
16009 described by INFO. */
16012 mips_set_architecture (const struct mips_cpu_info
*info
)
16016 mips_arch_info
= info
;
16017 mips_arch
= info
->cpu
;
16018 mips_isa
= info
->isa
;
16022 /* Likewise for tuning. */
16025 mips_set_tune (const struct mips_cpu_info
*info
)
16029 mips_tune_info
= info
;
16030 mips_tune
= info
->cpu
;
16034 /* Implement TARGET_OPTION_OVERRIDE. */
16037 mips_option_override (void)
16039 int i
, start
, regno
, mode
;
16041 if (global_options_set
.x_mips_isa_option
)
16042 mips_isa_option_info
= &mips_cpu_info_table
[mips_isa_option
];
16044 /* Process flags as though we were generating non-MIPS16 code. */
16045 mips_base_mips16
= TARGET_MIPS16
;
16046 target_flags
&= ~MASK_MIPS16
;
16048 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16049 SUBTARGET_OVERRIDE_OPTIONS
;
16052 /* -mno-float overrides -mhard-float and -msoft-float. */
16053 if (TARGET_NO_FLOAT
)
16055 target_flags
|= MASK_SOFT_FLOAT_ABI
;
16056 target_flags_explicit
|= MASK_SOFT_FLOAT_ABI
;
16059 if (TARGET_FLIP_MIPS16
)
16060 TARGET_INTERLINK_MIPS16
= 1;
16062 /* Set the small data limit. */
16063 mips_small_data_threshold
= (global_options_set
.x_g_switch_value
16065 : MIPS_DEFAULT_GVALUE
);
16067 /* The following code determines the architecture and register size.
16068 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
16069 The GAS and GCC code should be kept in sync as much as possible. */
16071 if (global_options_set
.x_mips_arch_option
)
16072 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option
));
16074 if (mips_isa_option_info
!= 0)
16076 if (mips_arch_info
== 0)
16077 mips_set_architecture (mips_isa_option_info
);
16078 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
16079 error ("%<-%s%> conflicts with the other architecture options, "
16080 "which specify a %s processor",
16081 mips_isa_option_info
->name
,
16082 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
16085 if (mips_arch_info
== 0)
16086 mips_set_architecture (mips_default_arch ());
16088 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
16089 error ("%<-march=%s%> is not compatible with the selected ABI",
16090 mips_arch_info
->name
);
16092 /* Optimize for mips_arch, unless -mtune selects a different processor. */
16093 if (global_options_set
.x_mips_tune_option
)
16094 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option
));
16096 if (mips_tune_info
== 0)
16097 mips_set_tune (mips_arch_info
);
16099 if ((target_flags_explicit
& MASK_64BIT
) != 0)
16101 /* The user specified the size of the integer registers. Make sure
16102 it agrees with the ABI and ISA. */
16103 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
16104 error ("%<-mgp64%> used with a 32-bit processor");
16105 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
16106 error ("%<-mgp32%> used with a 64-bit ABI");
16107 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
16108 error ("%<-mgp64%> used with a 32-bit ABI");
16112 /* Infer the integer register size from the ABI and processor.
16113 Restrict ourselves to 32-bit registers if that's all the
16114 processor has, or if the ABI cannot handle 64-bit registers. */
16115 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
16116 target_flags
&= ~MASK_64BIT
;
16118 target_flags
|= MASK_64BIT
;
16121 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
16123 if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
16124 error ("unsupported combination: %s", "-mfp64 -msingle-float");
16125 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
16126 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
16127 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
16129 if (!ISA_HAS_MXHC1
)
16130 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
16131 " the target supports the mfhc1 and mthc1 instructions");
16132 else if (mips_abi
!= ABI_32
)
16133 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
16139 /* -msingle-float selects 32-bit float registers. Otherwise the
16140 float registers should be the same size as the integer ones. */
16141 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
16142 target_flags
|= MASK_FLOAT64
;
16144 target_flags
&= ~MASK_FLOAT64
;
16147 /* End of code shared with GAS. */
16149 /* If a -mlong* option was given, check that it matches the ABI,
16150 otherwise infer the -mlong* setting from the other options. */
16151 if ((target_flags_explicit
& MASK_LONG64
) != 0)
16155 if (mips_abi
== ABI_N32
)
16156 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
16157 else if (mips_abi
== ABI_32
)
16158 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
16159 else if (mips_abi
== ABI_O64
&& TARGET_ABICALLS
)
16160 /* We have traditionally allowed non-abicalls code to use
16161 an LP64 form of o64. However, it would take a bit more
16162 effort to support the combination of 32-bit GOT entries
16163 and 64-bit pointers, so we treat the abicalls case as
16165 error ("the combination of %qs and %qs is incompatible with %qs",
16166 "-mabi=o64", "-mabicalls", "-mlong64");
16170 if (mips_abi
== ABI_64
)
16171 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
16176 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
16177 target_flags
|= MASK_LONG64
;
16179 target_flags
&= ~MASK_LONG64
;
16182 if (!TARGET_OLDABI
)
16183 flag_pcc_struct_return
= 0;
16185 /* Decide which rtx_costs structure to use. */
16187 mips_cost
= &mips_rtx_cost_optimize_size
;
16189 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
16191 /* If the user hasn't specified a branch cost, use the processor's
16193 if (mips_branch_cost
== 0)
16194 mips_branch_cost
= mips_cost
->branch_cost
;
16196 /* If neither -mbranch-likely nor -mno-branch-likely was given
16197 on the command line, set MASK_BRANCHLIKELY based on the target
16198 architecture and tuning flags. Annulled delay slots are a
16199 size win, so we only consider the processor-specific tuning
16200 for !optimize_size. */
16201 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
16203 if (ISA_HAS_BRANCHLIKELY
16205 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
16206 target_flags
|= MASK_BRANCHLIKELY
;
16208 target_flags
&= ~MASK_BRANCHLIKELY
;
16210 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
16211 warning (0, "the %qs architecture does not support branch-likely"
16212 " instructions", mips_arch_info
->name
);
16214 /* The effect of -mabicalls isn't defined for the EABI. */
16215 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
16217 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
16218 target_flags
&= ~MASK_ABICALLS
;
16221 /* PIC requires -mabicalls. */
16224 if (mips_abi
== ABI_EABI
)
16225 error ("cannot generate position-independent code for %qs",
16227 else if (!TARGET_ABICALLS
)
16228 error ("position-independent code requires %qs", "-mabicalls");
16231 if (TARGET_ABICALLS_PIC2
)
16232 /* We need to set flag_pic for executables as well as DSOs
16233 because we may reference symbols that are not defined in
16234 the final executable. (MIPS does not use things like
16235 copy relocs, for example.)
16237 There is a body of code that uses __PIC__ to distinguish
16238 between -mabicalls and -mno-abicalls code. The non-__PIC__
16239 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
16240 long as any indirect jumps use $25. */
16243 /* -mvr4130-align is a "speed over size" optimization: it usually produces
16244 faster code, but at the expense of more nops. Enable it at -O3 and
16246 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
16247 target_flags
|= MASK_VR4130_ALIGN
;
16249 /* Prefer a call to memcpy over inline code when optimizing for size,
16250 though see MOVE_RATIO in mips.h. */
16251 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
16252 target_flags
|= MASK_MEMCPY
;
16254 /* If we have a nonzero small-data limit, check that the -mgpopt
16255 setting is consistent with the other target flags. */
16256 if (mips_small_data_threshold
> 0)
16260 if (!TARGET_EXPLICIT_RELOCS
)
16261 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
16263 TARGET_LOCAL_SDATA
= false;
16264 TARGET_EXTERN_SDATA
= false;
16268 if (TARGET_VXWORKS_RTP
)
16269 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
16271 if (TARGET_ABICALLS
)
16272 warning (0, "cannot use small-data accesses for %qs",
16277 /* Make sure that the user didn't turn off paired single support when
16278 MIPS-3D support is requested. */
16280 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
16281 && !TARGET_PAIRED_SINGLE_FLOAT
)
16282 error ("%<-mips3d%> requires %<-mpaired-single%>");
16284 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
16286 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
16288 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
16289 and TARGET_HARD_FLOAT_ABI are both true. */
16290 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
16291 error ("%qs must be used with %qs",
16292 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
16293 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
16295 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
16297 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
16298 warning (0, "the %qs architecture does not support paired-single"
16299 " instructions", mips_arch_info
->name
);
16301 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
16302 && !TARGET_CACHE_BUILTIN
)
16304 error ("%qs requires a target that provides the %qs instruction",
16305 "-mr10k-cache-barrier", "cache");
16306 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
16309 /* If TARGET_DSPR2, enable MASK_DSP. */
16311 target_flags
|= MASK_DSP
;
16313 /* .eh_frame addresses should be the same width as a C pointer.
16314 Most MIPS ABIs support only one pointer size, so the assembler
16315 will usually know exactly how big an .eh_frame address is.
16317 Unfortunately, this is not true of the 64-bit EABI. The ABI was
16318 originally defined to use 64-bit pointers (i.e. it is LP64), and
16319 this is still the default mode. However, we also support an n32-like
16320 ILP32 mode, which is selected by -mlong32. The problem is that the
16321 assembler has traditionally not had an -mlong option, so it has
16322 traditionally not known whether we're using the ILP32 or LP64 form.
16324 As it happens, gas versions up to and including 2.19 use _32-bit_
16325 addresses for EABI64 .cfi_* directives. This is wrong for the
16326 default LP64 mode, so we can't use the directives by default.
16327 Moreover, since gas's current behavior is at odds with gcc's
16328 default behavior, it seems unwise to rely on future versions
16329 of gas behaving the same way. We therefore avoid using .cfi
16330 directives for -mlong32 as well. */
16331 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
16332 flag_dwarf2_cfi_asm
= 0;
16334 /* .cfi_* directives generate a read-only section, so fall back on
16335 manual .eh_frame creation if we need the section to be writable. */
16336 if (TARGET_WRITABLE_EH_FRAME
)
16337 flag_dwarf2_cfi_asm
= 0;
16339 mips_init_print_operand_punct ();
16341 /* Set up array to map GCC register number to debug register number.
16342 Ignore the special purpose register numbers. */
16344 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
16346 mips_dbx_regno
[i
] = INVALID_REGNUM
;
16347 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
16348 mips_dwarf_regno
[i
] = i
;
16350 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
16353 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
16354 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
16355 mips_dbx_regno
[i
] = i
+ start
;
16357 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
16358 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
16359 mips_dbx_regno
[i
] = i
+ start
;
16361 /* Accumulator debug registers use big-endian ordering. */
16362 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
16363 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
16364 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
16365 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
16366 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
16368 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
16369 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
16372 /* Set up mips_hard_regno_mode_ok. */
16373 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
16374 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
16375 mips_hard_regno_mode_ok
[mode
][regno
]
16376 = mips_hard_regno_mode_ok_p (regno
, (enum machine_mode
) mode
);
16378 /* Function to allocate machine-dependent function status. */
16379 init_machine_status
= &mips_init_machine_status
;
16381 /* Default to working around R4000 errata only if the processor
16382 was selected explicitly. */
16383 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
16384 && strcmp (mips_arch_info
->name
, "r4000") == 0)
16385 target_flags
|= MASK_FIX_R4000
;
16387 /* Default to working around R4400 errata only if the processor
16388 was selected explicitly. */
16389 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
16390 && strcmp (mips_arch_info
->name
, "r4400") == 0)
16391 target_flags
|= MASK_FIX_R4400
;
16393 /* Default to working around R10000 errata only if the processor
16394 was selected explicitly. */
16395 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
16396 && strcmp (mips_arch_info
->name
, "r10000") == 0)
16397 target_flags
|= MASK_FIX_R10000
;
16399 /* Make sure that branch-likely instructions available when using
16400 -mfix-r10000. The instructions are not available if either:
16402 1. -mno-branch-likely was passed.
16403 2. The selected ISA does not support branch-likely and
16404 the command line does not include -mbranch-likely. */
16405 if (TARGET_FIX_R10000
16406 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
16407 ? !ISA_HAS_BRANCHLIKELY
16408 : !TARGET_BRANCHLIKELY
))
16409 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
16411 if (TARGET_SYNCI
&& !ISA_HAS_SYNCI
)
16413 warning (0, "the %qs architecture does not support the synci "
16414 "instruction", mips_arch_info
->name
);
16415 target_flags
&= ~MASK_SYNCI
;
16418 /* Only optimize PIC indirect calls if they are actually required. */
16419 if (!TARGET_USE_GOT
|| !TARGET_EXPLICIT_RELOCS
)
16420 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
16422 /* Save base state of options. */
16423 mips_base_target_flags
= target_flags
;
16424 mips_base_schedule_insns
= flag_schedule_insns
;
16425 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
16426 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
16427 mips_base_align_loops
= align_loops
;
16428 mips_base_align_jumps
= align_jumps
;
16429 mips_base_align_functions
= align_functions
;
16431 /* Now select the ISA mode.
16433 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
16434 MIPS16 mode afterwards if need be. */
16435 mips_set_mips16_mode (false);
16438 /* Swap the register information for registers I and I + 1, which
16439 currently have the wrong endianness. Note that the registers'
16440 fixedness and call-clobberedness might have been set on the
16444 mips_swap_registers (unsigned int i
)
16449 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
16450 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
16452 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
16453 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
16454 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
16455 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
16461 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
16464 mips_conditional_register_usage (void)
16469 /* These DSP control register fields are global. */
16470 global_regs
[CCDSP_PO_REGNUM
] = 1;
16471 global_regs
[CCDSP_SC_REGNUM
] = 1;
16474 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
16475 reg_class_contents
[(int) DSP_ACC_REGS
]);
16477 if (!TARGET_HARD_FLOAT
)
16479 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
16480 reg_class_contents
[(int) FP_REGS
]);
16481 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
16482 reg_class_contents
[(int) ST_REGS
]);
16484 else if (!ISA_HAS_8CC
)
16486 /* We only have a single condition-code register. We implement
16487 this by fixing all the condition-code registers and generating
16488 RTL that refers directly to ST_REG_FIRST. */
16489 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
16490 reg_class_contents
[(int) ST_REGS
]);
16491 SET_HARD_REG_BIT (accessible_reg_set
, FPSW_REGNUM
);
16492 fixed_regs
[FPSW_REGNUM
] = call_used_regs
[FPSW_REGNUM
] = 1;
16496 /* In MIPS16 mode, we permit the $t temporary registers to be used
16497 for reload. We prohibit the unused $s registers, since they
16498 are call-saved, and saving them via a MIPS16 register would
16499 probably waste more time than just reloading the value. */
16500 fixed_regs
[18] = call_used_regs
[18] = 1;
16501 fixed_regs
[19] = call_used_regs
[19] = 1;
16502 fixed_regs
[20] = call_used_regs
[20] = 1;
16503 fixed_regs
[21] = call_used_regs
[21] = 1;
16504 fixed_regs
[22] = call_used_regs
[22] = 1;
16505 fixed_regs
[23] = call_used_regs
[23] = 1;
16506 fixed_regs
[26] = call_used_regs
[26] = 1;
16507 fixed_regs
[27] = call_used_regs
[27] = 1;
16508 fixed_regs
[30] = call_used_regs
[30] = 1;
16510 /* Do not allow HI and LO to be treated as register operands.
16511 There are no MTHI or MTLO instructions (or any real need
16512 for them) and one-way registers cannot easily be reloaded. */
16513 AND_COMPL_HARD_REG_SET (operand_reg_set
,
16514 reg_class_contents
[(int) MD_REGS
]);
16516 /* $f20-$f23 are call-clobbered for n64. */
16517 if (mips_abi
== ABI_64
)
16520 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
16521 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
16523 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
16525 if (mips_abi
== ABI_N32
)
16528 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
16529 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
16531 /* Make sure that double-register accumulator values are correctly
16532 ordered for the current endianness. */
16533 if (TARGET_LITTLE_ENDIAN
)
16535 unsigned int regno
;
16537 mips_swap_registers (MD_REG_FIRST
);
16538 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
16539 mips_swap_registers (regno
);
16543 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
16544 other registers for instructions for which it is possible. This
16545 encourages the compiler to use CMP in cases where an XOR would
16546 require some register shuffling. */
16549 mips_order_regs_for_local_alloc (void)
16553 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
16554 reg_alloc_order
[i
] = i
;
16558 /* It really doesn't matter where we put register 0, since it is
16559 a fixed register anyhow. */
16560 reg_alloc_order
[0] = 24;
16561 reg_alloc_order
[24] = 0;
16565 /* Implement EH_USES. */
16568 mips_eh_uses (unsigned int regno
)
16570 if (reload_completed
&& !TARGET_ABSOLUTE_JUMPS
)
16572 /* We need to force certain registers to be live in order to handle
16573 PIC long branches correctly. See mips_must_initialize_gp_p for
16575 if (mips_cfun_has_cprestore_slot_p ())
16577 if (regno
== CPRESTORE_SLOT_REGNUM
)
16582 if (cfun
->machine
->global_pointer
== regno
)
16590 /* Implement EPILOGUE_USES. */
16593 mips_epilogue_uses (unsigned int regno
)
16595 /* Say that the epilogue uses the return address register. Note that
16596 in the case of sibcalls, the values "used by the epilogue" are
16597 considered live at the start of the called function. */
16598 if (regno
== RETURN_ADDR_REGNUM
)
16601 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
16602 See the comment above load_call<mode> for details. */
16603 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
16606 /* An interrupt handler must preserve some registers that are
16607 ordinarily call-clobbered. */
16608 if (cfun
->machine
->interrupt_handler_p
16609 && mips_interrupt_extra_call_saved_reg_p (regno
))
16615 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
16618 mips_at_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
16620 return REG_P (*x
) && REGNO (*x
) == AT_REGNUM
;
16623 /* Return true if INSN needs to be wrapped in ".set noat".
16624 INSN has NOPERANDS operands, stored in OPVEC. */
16627 mips_need_noat_wrapper_p (rtx insn
, rtx
*opvec
, int noperands
)
16631 if (recog_memoized (insn
) >= 0)
16632 for (i
= 0; i
< noperands
; i
++)
16633 if (for_each_rtx (&opvec
[i
], mips_at_reg_p
, NULL
))
16638 /* Implement FINAL_PRESCAN_INSN. */
16641 mips_final_prescan_insn (rtx insn
, rtx
*opvec
, int noperands
)
16643 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
16644 mips_push_asm_switch (&mips_noat
);
16647 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
16650 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED
, rtx insn
,
16651 rtx
*opvec
, int noperands
)
16653 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
16654 mips_pop_asm_switch (&mips_noat
);
16657 /* Return the function that is used to expand the <u>mulsidi3 pattern.
16658 EXT_CODE is the code of the extension used. Return NULL if widening
16659 multiplication shouldn't be used. */
16662 mips_mulsidi3_gen_fn (enum rtx_code ext_code
)
16666 signed_p
= ext_code
== SIGN_EXTEND
;
16669 /* Don't use widening multiplication with MULT when we have DMUL. Even
16670 with the extension of its input operands DMUL is faster. Note that
16671 the extension is not needed for signed multiplication. In order to
16672 ensure that we always remove the redundant sign-extension in this
16673 case we still expand mulsidi3 for DMUL. */
16675 return signed_p
? gen_mulsidi3_64bit_dmul
: NULL
;
16678 ? gen_mulsidi3_64bit_mips16
16679 : gen_umulsidi3_64bit_mips16
);
16680 if (TARGET_FIX_R4000
)
16682 return signed_p
? gen_mulsidi3_64bit
: gen_umulsidi3_64bit
;
16688 ? gen_mulsidi3_32bit_mips16
16689 : gen_umulsidi3_32bit_mips16
);
16690 if (TARGET_FIX_R4000
&& !ISA_HAS_DSP
)
16691 return signed_p
? gen_mulsidi3_32bit_r4000
: gen_umulsidi3_32bit_r4000
;
16692 return signed_p
? gen_mulsidi3_32bit
: gen_umulsidi3_32bit
;
16696 /* Return the size in bytes of the trampoline code, padded to
16697 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
16698 function address immediately follow. */
16701 mips_trampoline_code_size (void)
16703 if (TARGET_USE_PIC_FN_ADDR_REG
)
16705 else if (ptr_mode
== DImode
)
16707 else if (ISA_HAS_LOAD_DELAY
)
16713 /* Implement TARGET_TRAMPOLINE_INIT. */
16716 mips_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
16718 rtx addr
, end_addr
, high
, low
, opcode
, mem
;
16721 HOST_WIDE_INT end_addr_offset
, static_chain_offset
, target_function_offset
;
16723 /* Work out the offsets of the pointers from the start of the
16724 trampoline code. */
16725 end_addr_offset
= mips_trampoline_code_size ();
16726 static_chain_offset
= end_addr_offset
;
16727 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
16729 /* Get pointers to the beginning and end of the code block. */
16730 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
16731 end_addr
= mips_force_binary (Pmode
, PLUS
, addr
, GEN_INT (end_addr_offset
));
16733 #define OP(X) gen_int_mode (X, SImode)
16735 /* Build up the code in TRAMPOLINE. */
16737 if (TARGET_USE_PIC_FN_ADDR_REG
)
16739 /* $25 contains the address of the trampoline. Emit code of the form:
16741 l[wd] $1, target_function_offset($25)
16742 l[wd] $static_chain, static_chain_offset($25)
16745 trampoline
[i
++] = OP (MIPS_LOAD_PTR (AT_REGNUM
,
16746 target_function_offset
,
16747 PIC_FUNCTION_ADDR_REGNUM
));
16748 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
16749 static_chain_offset
,
16750 PIC_FUNCTION_ADDR_REGNUM
));
16751 trampoline
[i
++] = OP (MIPS_JR (AT_REGNUM
));
16752 trampoline
[i
++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM
, AT_REGNUM
));
16754 else if (ptr_mode
== DImode
)
16756 /* It's too cumbersome to create the full 64-bit address, so let's
16762 1: l[wd] $25, target_function_offset - 12($31)
16763 l[wd] $static_chain, static_chain_offset - 12($31)
16767 where 12 is the offset of "1:" from the start of the code block. */
16768 trampoline
[i
++] = OP (MIPS_MOVE (AT_REGNUM
, RETURN_ADDR_REGNUM
));
16769 trampoline
[i
++] = OP (MIPS_BAL (1));
16770 trampoline
[i
++] = OP (MIPS_NOP
);
16771 trampoline
[i
++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
16772 target_function_offset
- 12,
16773 RETURN_ADDR_REGNUM
));
16774 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
16775 static_chain_offset
- 12,
16776 RETURN_ADDR_REGNUM
));
16777 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
16778 trampoline
[i
++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM
, AT_REGNUM
));
16782 /* If the target has load delays, emit:
16784 lui $1, %hi(end_addr)
16785 lw $25, %lo(end_addr + ...)($1)
16786 lw $static_chain, %lo(end_addr + ...)($1)
16792 lui $1, %hi(end_addr)
16793 lw $25, %lo(end_addr + ...)($1)
16795 lw $static_chain, %lo(end_addr + ...)($1). */
16797 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
16798 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
16799 high
= expand_simple_binop (SImode
, PLUS
, end_addr
, GEN_INT (0x8000),
16800 NULL
, false, OPTAB_WIDEN
);
16801 high
= expand_simple_binop (SImode
, LSHIFTRT
, high
, GEN_INT (16),
16802 NULL
, false, OPTAB_WIDEN
);
16803 low
= convert_to_mode (SImode
, gen_lowpart (HImode
, end_addr
), true);
16805 /* Emit the LUI. */
16806 opcode
= OP (MIPS_LUI (AT_REGNUM
, 0));
16807 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, high
,
16808 NULL
, false, OPTAB_WIDEN
);
16810 /* Emit the load of the target function. */
16811 opcode
= OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
16812 target_function_offset
- end_addr_offset
,
16814 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
16815 NULL
, false, OPTAB_WIDEN
);
16817 /* Emit the JR here, if we can. */
16818 if (!ISA_HAS_LOAD_DELAY
)
16819 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
16821 /* Emit the load of the static chain register. */
16822 opcode
= OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
16823 static_chain_offset
- end_addr_offset
,
16825 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
16826 NULL
, false, OPTAB_WIDEN
);
16828 /* Emit the JR, if we couldn't above. */
16829 if (ISA_HAS_LOAD_DELAY
)
16831 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
16832 trampoline
[i
++] = OP (MIPS_NOP
);
16838 /* Copy the trampoline code. Leave any padding uninitialized. */
16839 for (j
= 0; j
< i
; j
++)
16841 mem
= adjust_address (m_tramp
, SImode
, j
* GET_MODE_SIZE (SImode
));
16842 mips_emit_move (mem
, trampoline
[j
]);
16845 /* Set up the static chain pointer field. */
16846 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
16847 mips_emit_move (mem
, chain_value
);
16849 /* Set up the target function field. */
16850 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
16851 mips_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
16853 /* Flush the code part of the trampoline. */
16854 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
16855 emit_insn (gen_clear_cache (addr
, end_addr
));
16858 /* Implement FUNCTION_PROFILER. */
16860 void mips_function_profiler (FILE *file
)
16863 sorry ("mips16 function profiling");
16864 if (TARGET_LONG_CALLS
)
16866 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
16867 if (Pmode
== DImode
)
16868 fprintf (file
, "\tdla\t%s,_mcount\n", reg_names
[3]);
16870 fprintf (file
, "\tla\t%s,_mcount\n", reg_names
[3]);
16872 mips_push_asm_switch (&mips_noat
);
16873 fprintf (file
, "\tmove\t%s,%s\t\t# save current return address\n",
16874 reg_names
[AT_REGNUM
], reg_names
[RETURN_ADDR_REGNUM
]);
16875 /* _mcount treats $2 as the static chain register. */
16876 if (cfun
->static_chain_decl
!= NULL
)
16877 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[2],
16878 reg_names
[STATIC_CHAIN_REGNUM
]);
16879 if (TARGET_MCOUNT_RA_ADDRESS
)
16881 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
16882 ra save location. */
16883 if (cfun
->machine
->frame
.ra_fp_offset
== 0)
16884 /* ra not saved, pass zero. */
16885 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[12], reg_names
[0]);
16887 fprintf (file
, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC
"(%s)\n",
16888 Pmode
== DImode
? "dla" : "la", reg_names
[12],
16889 cfun
->machine
->frame
.ra_fp_offset
,
16890 reg_names
[STACK_POINTER_REGNUM
]);
16892 if (!TARGET_NEWABI
)
16894 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
16895 TARGET_64BIT
? "dsubu" : "subu",
16896 reg_names
[STACK_POINTER_REGNUM
],
16897 reg_names
[STACK_POINTER_REGNUM
],
16898 Pmode
== DImode
? 16 : 8);
16900 if (TARGET_LONG_CALLS
)
16901 fprintf (file
, "\tjalr\t%s\n", reg_names
[3]);
16903 fprintf (file
, "\tjal\t_mcount\n");
16904 mips_pop_asm_switch (&mips_noat
);
16905 /* _mcount treats $2 as the static chain register. */
16906 if (cfun
->static_chain_decl
!= NULL
)
16907 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[STATIC_CHAIN_REGNUM
],
16911 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
16912 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
16913 when TARGET_LOONGSON_VECTORS is true. */
16915 static unsigned HOST_WIDE_INT
16916 mips_shift_truncation_mask (enum machine_mode mode
)
16918 if (TARGET_LOONGSON_VECTORS
&& VECTOR_MODE_P (mode
))
16921 return GET_MODE_BITSIZE (mode
) - 1;
16924 /* Implement TARGET_PREPARE_PCH_SAVE. */
16927 mips_prepare_pch_save (void)
16929 /* We are called in a context where the current MIPS16 vs. non-MIPS16
16930 setting should be irrelevant. The question then is: which setting
16931 makes most sense at load time?
16933 The PCH is loaded before the first token is read. We should never
16934 have switched into MIPS16 mode by that point, and thus should not
16935 have populated mips16_globals. Nor can we load the entire contents
16936 of mips16_globals from the PCH file, because mips16_globals contains
16937 a combination of GGC and non-GGC data.
16939 There is therefore no point in trying save the GGC part of
16940 mips16_globals to the PCH file, or to preserve MIPS16ness across
16941 the PCH save and load. The loading compiler would not have access
16942 to the non-GGC parts of mips16_globals (either from the PCH file,
16943 or from a copy that the loading compiler generated itself) and would
16944 have to call target_reinit anyway.
16946 It therefore seems best to switch back to non-MIPS16 mode at
16947 save time, and to ensure that mips16_globals remains null after
16949 mips_set_mips16_mode (false);
16950 mips16_globals
= 0;
16953 /* Generate or test for an insn that supports a constant permutation. */
16955 #define MAX_VECT_LEN 8
16957 struct expand_vec_perm_d
16959 rtx target
, op0
, op1
;
16960 unsigned char perm
[MAX_VECT_LEN
];
16961 enum machine_mode vmode
;
16962 unsigned char nelt
;
16967 /* Construct (set target (vec_select op0 (parallel perm))) and
16968 return true if that's a valid instruction in the active ISA. */
16971 mips_expand_vselect (rtx target
, rtx op0
,
16972 const unsigned char *perm
, unsigned nelt
)
16974 rtx rperm
[MAX_VECT_LEN
], x
;
16977 for (i
= 0; i
< nelt
; ++i
)
16978 rperm
[i
] = GEN_INT (perm
[i
]);
16980 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nelt
, rperm
));
16981 x
= gen_rtx_VEC_SELECT (GET_MODE (target
), op0
, x
);
16982 x
= gen_rtx_SET (VOIDmode
, target
, x
);
16985 if (recog_memoized (x
) < 0)
16993 /* Similar, but generate a vec_concat from op0 and op1 as well. */
16996 mips_expand_vselect_vconcat (rtx target
, rtx op0
, rtx op1
,
16997 const unsigned char *perm
, unsigned nelt
)
16999 enum machine_mode v2mode
;
17002 v2mode
= GET_MODE_2XWIDER_MODE (GET_MODE (op0
));
17003 x
= gen_rtx_VEC_CONCAT (v2mode
, op0
, op1
);
17004 return mips_expand_vselect (target
, x
, perm
, nelt
);
17007 /* Recognize patterns for even-odd extraction. */
17010 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d
*d
)
17012 unsigned i
, odd
, nelt
= d
->nelt
;
17013 rtx t0
, t1
, t2
, t3
;
17015 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
17017 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
17024 for (i
= 1; i
< nelt
; ++i
)
17025 if (d
->perm
[i
] != i
* 2 + odd
)
17031 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
17032 t0
= gen_reg_rtx (d
->vmode
);
17033 t1
= gen_reg_rtx (d
->vmode
);
17037 emit_insn (gen_loongson_punpckhhw (t0
, d
->op0
, d
->op1
));
17038 emit_insn (gen_loongson_punpcklhw (t1
, d
->op0
, d
->op1
));
17040 emit_insn (gen_loongson_punpckhhw (d
->target
, t1
, t0
));
17042 emit_insn (gen_loongson_punpcklhw (d
->target
, t1
, t0
));
17046 t2
= gen_reg_rtx (d
->vmode
);
17047 t3
= gen_reg_rtx (d
->vmode
);
17048 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op1
));
17049 emit_insn (gen_loongson_punpcklbh (t1
, d
->op0
, d
->op1
));
17050 emit_insn (gen_loongson_punpckhbh (t2
, t1
, t0
));
17051 emit_insn (gen_loongson_punpcklbh (t3
, t1
, t0
));
17053 emit_insn (gen_loongson_punpckhbh (d
->target
, t3
, t2
));
17055 emit_insn (gen_loongson_punpcklbh (d
->target
, t3
, t2
));
17059 gcc_unreachable ();
17064 /* Recognize patterns for the Loongson PSHUFH instruction. */
17067 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d
*d
)
17072 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
17074 if (d
->vmode
!= V4HImode
)
17079 /* Convert the selector into the packed 8-bit form for pshufh. */
17080 /* Recall that loongson is little-endian only. No big-endian
17081 adjustment required. */
17082 for (i
= mask
= 0; i
< 4; i
++)
17083 mask
|= (d
->perm
[i
] & 3) << (i
* 2);
17084 rmask
= force_reg (SImode
, GEN_INT (mask
));
17086 if (d
->one_vector_p
)
17087 emit_insn (gen_loongson_pshufh (d
->target
, d
->op0
, rmask
));
17090 rtx t0
, t1
, x
, merge
, rmerge
[4];
17092 t0
= gen_reg_rtx (V4HImode
);
17093 t1
= gen_reg_rtx (V4HImode
);
17094 emit_insn (gen_loongson_pshufh (t1
, d
->op1
, rmask
));
17095 emit_insn (gen_loongson_pshufh (t0
, d
->op0
, rmask
));
17097 for (i
= 0; i
< 4; ++i
)
17098 rmerge
[i
] = (d
->perm
[i
] & 4 ? constm1_rtx
: const0_rtx
);
17099 merge
= gen_rtx_CONST_VECTOR (V4HImode
, gen_rtvec_v (4, rmerge
));
17100 merge
= force_reg (V4HImode
, merge
);
17102 x
= gen_rtx_AND (V4HImode
, merge
, t1
);
17103 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
17105 x
= gen_rtx_NOT (V4HImode
, merge
);
17106 x
= gen_rtx_AND (V4HImode
, x
, t0
);
17107 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
17109 x
= gen_rtx_IOR (V4HImode
, t0
, t1
);
17110 emit_insn (gen_rtx_SET (VOIDmode
, d
->target
, x
));
17116 /* Recognize broadcast patterns for the Loongson. */
17119 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d
*d
)
17124 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
17126 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
17127 if (d
->vmode
!= V8QImode
)
17129 if (!d
->one_vector_p
)
17133 for (i
= 1; i
< 8; ++i
)
17134 if (d
->perm
[i
] != elt
)
17140 /* With one interleave we put two of the desired element adjacent. */
17141 t0
= gen_reg_rtx (V8QImode
);
17143 emit_insn (gen_loongson_punpcklbh (t0
, d
->op0
, d
->op0
));
17145 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op0
));
17147 /* Shuffle that one HImode element into all locations. */
17150 t1
= gen_reg_rtx (V4HImode
);
17151 emit_insn (gen_loongson_pshufh (t1
, gen_lowpart (V4HImode
, t0
),
17152 force_reg (SImode
, GEN_INT (elt
))));
17154 emit_move_insn (d
->target
, gen_lowpart (V8QImode
, t1
));
17159 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
17161 unsigned int i
, nelt
= d
->nelt
;
17162 unsigned char perm2
[MAX_VECT_LEN
];
17164 if (d
->one_vector_p
)
17166 /* Try interleave with alternating operands. */
17167 memcpy (perm2
, d
->perm
, sizeof(perm2
));
17168 for (i
= 1; i
< nelt
; i
+= 2)
17170 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
, perm2
, nelt
))
17175 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
,
17179 /* Try again with swapped operands. */
17180 for (i
= 0; i
< nelt
; ++i
)
17181 perm2
[i
] = (d
->perm
[i
] + nelt
) & (2 * nelt
- 1);
17182 if (mips_expand_vselect_vconcat (d
->target
, d
->op1
, d
->op0
, perm2
, nelt
))
17186 if (mips_expand_vpc_loongson_even_odd (d
))
17188 if (mips_expand_vpc_loongson_pshufh (d
))
17190 if (mips_expand_vpc_loongson_bcast (d
))
17195 /* Expand a vec_perm_const pattern. */
17198 mips_expand_vec_perm_const (rtx operands
[4])
17200 struct expand_vec_perm_d d
;
17201 int i
, nelt
, which
;
17202 unsigned char orig_perm
[MAX_VECT_LEN
];
17206 d
.target
= operands
[0];
17207 d
.op0
= operands
[1];
17208 d
.op1
= operands
[2];
17211 d
.vmode
= GET_MODE (d
.target
);
17212 gcc_assert (VECTOR_MODE_P (d
.vmode
));
17213 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
17214 d
.testing_p
= false;
17216 for (i
= which
= 0; i
< nelt
; ++i
)
17218 rtx e
= XVECEXP (sel
, 0, i
);
17219 int ei
= INTVAL (e
) & (2 * nelt
- 1);
17220 which
|= (ei
< nelt
? 1 : 2);
17223 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
17231 d
.one_vector_p
= false;
17232 if (!rtx_equal_p (d
.op0
, d
.op1
))
17237 for (i
= 0; i
< nelt
; ++i
)
17238 d
.perm
[i
] &= nelt
- 1;
17240 d
.one_vector_p
= true;
17245 d
.one_vector_p
= true;
17249 ok
= mips_expand_vec_perm_const_1 (&d
);
17251 /* If we were given a two-vector permutation which just happened to
17252 have both input vectors equal, we folded this into a one-vector
17253 permutation. There are several loongson patterns that are matched
17254 via direct vec_select+vec_concat expansion, but we do not have
17255 support in mips_expand_vec_perm_const_1 to guess the adjustment
17256 that should be made for a single operand. Just try again with
17257 the original permutation. */
17258 if (!ok
&& which
== 3)
17260 d
.op0
= operands
[1];
17261 d
.op1
= operands
[2];
17262 d
.one_vector_p
= false;
17263 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
17264 ok
= mips_expand_vec_perm_const_1 (&d
);
17270 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
17273 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
17274 const unsigned char *sel
)
17276 struct expand_vec_perm_d d
;
17277 unsigned int i
, nelt
, which
;
17281 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
17282 d
.testing_p
= true;
17283 memcpy (d
.perm
, sel
, nelt
);
17285 /* Categorize the set of elements in the selector. */
17286 for (i
= which
= 0; i
< nelt
; ++i
)
17288 unsigned char e
= d
.perm
[i
];
17289 gcc_assert (e
< 2 * nelt
);
17290 which
|= (e
< nelt
? 1 : 2);
17293 /* For all elements from second vector, fold the elements to first. */
17295 for (i
= 0; i
< nelt
; ++i
)
17298 /* Check whether the mask can be applied to the vector type. */
17299 d
.one_vector_p
= (which
!= 3);
17301 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
17302 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
17303 if (!d
.one_vector_p
)
17304 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
17307 ret
= mips_expand_vec_perm_const_1 (&d
);
17313 /* Expand an integral vector unpack operation. */
17316 mips_expand_vec_unpack (rtx operands
[2], bool unsigned_p
, bool high_p
)
17318 enum machine_mode imode
= GET_MODE (operands
[1]);
17319 rtx (*unpack
) (rtx
, rtx
, rtx
);
17320 rtx (*cmpgt
) (rtx
, rtx
, rtx
);
17321 rtx tmp
, dest
, zero
;
17327 unpack
= gen_loongson_punpckhbh
;
17329 unpack
= gen_loongson_punpcklbh
;
17330 cmpgt
= gen_loongson_pcmpgtb
;
17334 unpack
= gen_loongson_punpckhhw
;
17336 unpack
= gen_loongson_punpcklhw
;
17337 cmpgt
= gen_loongson_pcmpgth
;
17340 gcc_unreachable ();
17343 zero
= force_reg (imode
, CONST0_RTX (imode
));
17348 tmp
= gen_reg_rtx (imode
);
17349 emit_insn (cmpgt (tmp
, zero
, operands
[1]));
17352 dest
= gen_reg_rtx (imode
);
17353 emit_insn (unpack (dest
, operands
[1], tmp
));
17355 emit_move_insn (operands
[0], gen_lowpart (GET_MODE (operands
[0]), dest
));
17358 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
17361 mips_constant_elt_p (rtx x
)
17363 return CONST_INT_P (x
) || GET_CODE (x
) == CONST_DOUBLE
;
17366 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
17369 mips_expand_vi_broadcast (enum machine_mode vmode
, rtx target
, rtx elt
)
17371 struct expand_vec_perm_d d
;
17375 if (elt
!= const0_rtx
)
17376 elt
= force_reg (GET_MODE_INNER (vmode
), elt
);
17378 elt
= gen_lowpart (DImode
, elt
);
17380 t1
= gen_reg_rtx (vmode
);
17384 emit_insn (gen_loongson_vec_init1_v8qi (t1
, elt
));
17387 emit_insn (gen_loongson_vec_init1_v4hi (t1
, elt
));
17390 gcc_unreachable ();
17393 memset (&d
, 0, sizeof (d
));
17398 d
.nelt
= GET_MODE_NUNITS (vmode
);
17399 d
.one_vector_p
= true;
17401 ok
= mips_expand_vec_perm_const_1 (&d
);
17405 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
17406 elements of VALS with zeros, copy the constant vector to TARGET. */
17409 mips_expand_vi_constant (enum machine_mode vmode
, unsigned nelt
,
17410 rtx target
, rtx vals
)
17412 rtvec vec
= shallow_copy_rtvec (XVEC (vals
, 0));
17415 for (i
= 0; i
< nelt
; ++i
)
17417 if (!mips_constant_elt_p (RTVEC_ELT (vec
, i
)))
17418 RTVEC_ELT (vec
, i
) = const0_rtx
;
17421 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, vec
));
17425 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
17428 mips_expand_vi_loongson_one_pinsrh (rtx target
, rtx vals
, unsigned one_var
)
17430 mips_expand_vi_constant (V4HImode
, 4, target
, vals
);
17432 emit_insn (gen_vec_setv4hi (target
, target
, XVECEXP (vals
, 0, one_var
),
17433 GEN_INT (one_var
)));
17436 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
17439 mips_expand_vi_general (enum machine_mode vmode
, enum machine_mode imode
,
17440 unsigned nelt
, unsigned nvar
, rtx target
, rtx vals
)
17442 rtx mem
= assign_stack_temp (vmode
, GET_MODE_SIZE (vmode
));
17443 unsigned int i
, isize
= GET_MODE_SIZE (imode
);
17446 mips_expand_vi_constant (vmode
, nelt
, mem
, vals
);
17448 for (i
= 0; i
< nelt
; ++i
)
17450 rtx x
= XVECEXP (vals
, 0, i
);
17451 if (!mips_constant_elt_p (x
))
17452 emit_move_insn (adjust_address (mem
, imode
, i
* isize
), x
);
17455 emit_move_insn (target
, mem
);
17458 /* Expand a vector initialization. */
17461 mips_expand_vector_init (rtx target
, rtx vals
)
17463 enum machine_mode vmode
= GET_MODE (target
);
17464 enum machine_mode imode
= GET_MODE_INNER (vmode
);
17465 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
17466 unsigned nvar
= 0, one_var
= -1u;
17467 bool all_same
= true;
17470 for (i
= 0; i
< nelt
; ++i
)
17472 x
= XVECEXP (vals
, 0, i
);
17473 if (!mips_constant_elt_p (x
))
17474 nvar
++, one_var
= i
;
17475 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
17479 /* Load constants from the pool, or whatever's handy. */
17482 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, XVEC (vals
, 0)));
17486 /* For two-part initialization, always use CONCAT. */
17489 rtx op0
= force_reg (imode
, XVECEXP (vals
, 0, 0));
17490 rtx op1
= force_reg (imode
, XVECEXP (vals
, 0, 1));
17491 x
= gen_rtx_VEC_CONCAT (vmode
, op0
, op1
);
17492 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
17496 /* Loongson is the only cpu with vectors with more elements. */
17497 gcc_assert (TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
);
17499 /* If all values are identical, broadcast the value. */
17502 mips_expand_vi_broadcast (vmode
, target
, XVECEXP (vals
, 0, 0));
17506 /* If we've only got one non-variable V4HImode, use PINSRH. */
17507 if (nvar
== 1 && vmode
== V4HImode
)
17509 mips_expand_vi_loongson_one_pinsrh (target
, vals
, one_var
);
17513 mips_expand_vi_general (vmode
, imode
, nelt
, nvar
, target
, vals
);
17516 /* Expand a vector reduction. */
17519 mips_expand_vec_reduc (rtx target
, rtx in
, rtx (*gen
)(rtx
, rtx
, rtx
))
17521 enum machine_mode vmode
= GET_MODE (in
);
17522 unsigned char perm2
[2];
17523 rtx last
, next
, fold
, x
;
17527 fold
= gen_reg_rtx (vmode
);
17531 /* Use PUL/PLU to produce { L, H } op { H, L }.
17532 By reversing the pair order, rather than a pure interleave high,
17533 we avoid erroneous exceptional conditions that we might otherwise
17534 produce from the computation of H op H. */
17537 ok
= mips_expand_vselect_vconcat (fold
, last
, last
, perm2
, 2);
17542 /* Use interleave to produce { H, L } op { H, H }. */
17543 emit_insn (gen_loongson_punpckhwd (fold
, last
, last
));
17547 /* Perform the first reduction with interleave,
17548 and subsequent reductions with shifts. */
17549 emit_insn (gen_loongson_punpckhwd_hi (fold
, last
, last
));
17551 next
= gen_reg_rtx (vmode
);
17552 emit_insn (gen (next
, last
, fold
));
17555 fold
= gen_reg_rtx (vmode
);
17556 x
= force_reg (SImode
, GEN_INT (16));
17557 emit_insn (gen_vec_shr_v4hi (fold
, last
, x
));
17561 emit_insn (gen_loongson_punpckhwd_qi (fold
, last
, last
));
17563 next
= gen_reg_rtx (vmode
);
17564 emit_insn (gen (next
, last
, fold
));
17567 fold
= gen_reg_rtx (vmode
);
17568 x
= force_reg (SImode
, GEN_INT (16));
17569 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
17571 next
= gen_reg_rtx (vmode
);
17572 emit_insn (gen (next
, last
, fold
));
17575 fold
= gen_reg_rtx (vmode
);
17576 x
= force_reg (SImode
, GEN_INT (8));
17577 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
17581 gcc_unreachable ();
17584 emit_insn (gen (target
, last
, fold
));
17587 /* Expand a vector minimum/maximum. */
17590 mips_expand_vec_minmax (rtx target
, rtx op0
, rtx op1
,
17591 rtx (*cmp
) (rtx
, rtx
, rtx
), bool min_p
)
17593 enum machine_mode vmode
= GET_MODE (target
);
17596 tc
= gen_reg_rtx (vmode
);
17597 t0
= gen_reg_rtx (vmode
);
17598 t1
= gen_reg_rtx (vmode
);
17601 emit_insn (cmp (tc
, op0
, op1
));
17603 x
= gen_rtx_AND (vmode
, tc
, (min_p
? op1
: op0
));
17604 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
17606 x
= gen_rtx_NOT (vmode
, tc
);
17607 x
= gen_rtx_AND (vmode
, x
, (min_p
? op0
: op1
));
17608 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
17610 x
= gen_rtx_IOR (vmode
, t0
, t1
);
17611 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
17614 /* Initialize the GCC target structure. */
17615 #undef TARGET_ASM_ALIGNED_HI_OP
17616 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
17617 #undef TARGET_ASM_ALIGNED_SI_OP
17618 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
17619 #undef TARGET_ASM_ALIGNED_DI_OP
17620 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
17622 #undef TARGET_OPTION_OVERRIDE
17623 #define TARGET_OPTION_OVERRIDE mips_option_override
17625 #undef TARGET_LEGITIMIZE_ADDRESS
17626 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
17628 #undef TARGET_ASM_FUNCTION_PROLOGUE
17629 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
17630 #undef TARGET_ASM_FUNCTION_EPILOGUE
17631 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
17632 #undef TARGET_ASM_SELECT_RTX_SECTION
17633 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
17634 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
17635 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
17637 #undef TARGET_SCHED_INIT
17638 #define TARGET_SCHED_INIT mips_sched_init
17639 #undef TARGET_SCHED_REORDER
17640 #define TARGET_SCHED_REORDER mips_sched_reorder
17641 #undef TARGET_SCHED_REORDER2
17642 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
17643 #undef TARGET_SCHED_VARIABLE_ISSUE
17644 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
17645 #undef TARGET_SCHED_ADJUST_COST
17646 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
17647 #undef TARGET_SCHED_ISSUE_RATE
17648 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
17649 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
17650 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
17651 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
17652 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
17653 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
17654 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
17655 mips_multipass_dfa_lookahead
17656 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
17657 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
17658 mips_small_register_classes_for_mode_p
17660 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
17661 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
17663 #undef TARGET_INSERT_ATTRIBUTES
17664 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
17665 #undef TARGET_MERGE_DECL_ATTRIBUTES
17666 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
17667 #undef TARGET_SET_CURRENT_FUNCTION
17668 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
17670 #undef TARGET_VALID_POINTER_MODE
17671 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
17672 #undef TARGET_REGISTER_MOVE_COST
17673 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
17674 #undef TARGET_MEMORY_MOVE_COST
17675 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
17676 #undef TARGET_RTX_COSTS
17677 #define TARGET_RTX_COSTS mips_rtx_costs
17678 #undef TARGET_ADDRESS_COST
17679 #define TARGET_ADDRESS_COST mips_address_cost
17681 #undef TARGET_IN_SMALL_DATA_P
17682 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
17684 #undef TARGET_MACHINE_DEPENDENT_REORG
17685 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
17687 #undef TARGET_PREFERRED_RELOAD_CLASS
17688 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
17690 #undef TARGET_ASM_FILE_START
17691 #define TARGET_ASM_FILE_START mips_file_start
17692 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
17693 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
17694 #undef TARGET_ASM_CODE_END
17695 #define TARGET_ASM_CODE_END mips_code_end
17697 #undef TARGET_INIT_LIBFUNCS
17698 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
17700 #undef TARGET_BUILD_BUILTIN_VA_LIST
17701 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
17702 #undef TARGET_EXPAND_BUILTIN_VA_START
17703 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
17704 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
17705 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
17707 #undef TARGET_PROMOTE_FUNCTION_MODE
17708 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
17709 #undef TARGET_PROMOTE_PROTOTYPES
17710 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
17712 #undef TARGET_FUNCTION_VALUE
17713 #define TARGET_FUNCTION_VALUE mips_function_value
17714 #undef TARGET_LIBCALL_VALUE
17715 #define TARGET_LIBCALL_VALUE mips_libcall_value
17716 #undef TARGET_FUNCTION_VALUE_REGNO_P
17717 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
17718 #undef TARGET_RETURN_IN_MEMORY
17719 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
17720 #undef TARGET_RETURN_IN_MSB
17721 #define TARGET_RETURN_IN_MSB mips_return_in_msb
17723 #undef TARGET_ASM_OUTPUT_MI_THUNK
17724 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
17725 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
17726 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
17728 #undef TARGET_PRINT_OPERAND
17729 #define TARGET_PRINT_OPERAND mips_print_operand
17730 #undef TARGET_PRINT_OPERAND_ADDRESS
17731 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
17732 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
17733 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
17735 #undef TARGET_SETUP_INCOMING_VARARGS
17736 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
17737 #undef TARGET_STRICT_ARGUMENT_NAMING
17738 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
17739 #undef TARGET_MUST_PASS_IN_STACK
17740 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
17741 #undef TARGET_PASS_BY_REFERENCE
17742 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
17743 #undef TARGET_CALLEE_COPIES
17744 #define TARGET_CALLEE_COPIES mips_callee_copies
17745 #undef TARGET_ARG_PARTIAL_BYTES
17746 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
17747 #undef TARGET_FUNCTION_ARG
17748 #define TARGET_FUNCTION_ARG mips_function_arg
17749 #undef TARGET_FUNCTION_ARG_ADVANCE
17750 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
17751 #undef TARGET_FUNCTION_ARG_BOUNDARY
17752 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
17754 #undef TARGET_MODE_REP_EXTENDED
17755 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
17757 #undef TARGET_VECTOR_MODE_SUPPORTED_P
17758 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
17760 #undef TARGET_SCALAR_MODE_SUPPORTED_P
17761 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
17763 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
17764 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
17766 #undef TARGET_INIT_BUILTINS
17767 #define TARGET_INIT_BUILTINS mips_init_builtins
17768 #undef TARGET_BUILTIN_DECL
17769 #define TARGET_BUILTIN_DECL mips_builtin_decl
17770 #undef TARGET_EXPAND_BUILTIN
17771 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
17773 #undef TARGET_HAVE_TLS
17774 #define TARGET_HAVE_TLS HAVE_AS_TLS
17776 #undef TARGET_CANNOT_FORCE_CONST_MEM
17777 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
17779 #undef TARGET_LEGITIMATE_CONSTANT_P
17780 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
17782 #undef TARGET_ENCODE_SECTION_INFO
17783 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
17785 #undef TARGET_ATTRIBUTE_TABLE
17786 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
17787 /* All our function attributes are related to how out-of-line copies should
17788 be compiled or called. They don't in themselves prevent inlining. */
17789 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
17790 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
17792 #undef TARGET_EXTRA_LIVE_ON_ENTRY
17793 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
17795 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
17796 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
17797 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
17798 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
17800 #undef TARGET_COMP_TYPE_ATTRIBUTES
17801 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
17803 #ifdef HAVE_AS_DTPRELWORD
17804 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
17805 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
17807 #undef TARGET_DWARF_REGISTER_SPAN
17808 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
17810 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
17811 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
17813 #undef TARGET_LEGITIMATE_ADDRESS_P
17814 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
17816 #undef TARGET_FRAME_POINTER_REQUIRED
17817 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
17819 #undef TARGET_CAN_ELIMINATE
17820 #define TARGET_CAN_ELIMINATE mips_can_eliminate
17822 #undef TARGET_CONDITIONAL_REGISTER_USAGE
17823 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
17825 #undef TARGET_TRAMPOLINE_INIT
17826 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
17828 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
17829 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
17831 #undef TARGET_SHIFT_TRUNCATION_MASK
17832 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
17834 #undef TARGET_PREPARE_PCH_SAVE
17835 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
17837 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
17838 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
17840 struct gcc_target targetm
= TARGET_INITIALIZER
;
17842 #include "gt-mips.h"