1 /* Subroutines for insn-output.c for VAX.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
25 #include "dominance.h"
31 #include "cfgcleanup.h"
33 #include "basic-block.h"
38 #include "double-int.h"
48 #include "hard-reg-set.h"
49 #include "insn-config.h"
50 #include "conditions.h"
53 #include "insn-attr.h"
57 #include "statistics.h"
59 #include "fixed-value.h"
66 #include "insn-codes.h"
69 #include "diagnostic-core.h"
72 #include "tm-constrs.h"
75 #include "target-def.h"
78 static void vax_option_override (void);
79 static bool vax_legitimate_address_p (machine_mode
, rtx
, bool);
80 static void vax_file_start (void);
81 static void vax_init_libfuncs (void);
82 static void vax_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
84 static int vax_address_cost_1 (rtx
);
85 static int vax_address_cost (rtx
, machine_mode
, addr_space_t
, bool);
86 static bool vax_rtx_costs (rtx
, int, int, int, int *, bool);
87 static rtx
vax_function_arg (cumulative_args_t
, machine_mode
,
89 static void vax_function_arg_advance (cumulative_args_t
, machine_mode
,
91 static rtx
vax_struct_value_rtx (tree
, int);
92 static rtx
vax_builtin_setjmp_frame_value (void);
93 static void vax_asm_trampoline_template (FILE *);
94 static void vax_trampoline_init (rtx
, tree
, rtx
);
95 static int vax_return_pops_args (tree
, tree
, int);
96 static bool vax_mode_dependent_address_p (const_rtx
, addr_space_t
);
98 /* Initialize the GCC target structure. */
99 #undef TARGET_ASM_ALIGNED_HI_OP
100 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
102 #undef TARGET_ASM_FILE_START
103 #define TARGET_ASM_FILE_START vax_file_start
104 #undef TARGET_ASM_FILE_START_APP_OFF
105 #define TARGET_ASM_FILE_START_APP_OFF true
107 #undef TARGET_INIT_LIBFUNCS
108 #define TARGET_INIT_LIBFUNCS vax_init_libfuncs
110 #undef TARGET_ASM_OUTPUT_MI_THUNK
111 #define TARGET_ASM_OUTPUT_MI_THUNK vax_output_mi_thunk
112 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
113 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
115 #undef TARGET_RTX_COSTS
116 #define TARGET_RTX_COSTS vax_rtx_costs
117 #undef TARGET_ADDRESS_COST
118 #define TARGET_ADDRESS_COST vax_address_cost
120 #undef TARGET_PROMOTE_PROTOTYPES
121 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
123 #undef TARGET_FUNCTION_ARG
124 #define TARGET_FUNCTION_ARG vax_function_arg
125 #undef TARGET_FUNCTION_ARG_ADVANCE
126 #define TARGET_FUNCTION_ARG_ADVANCE vax_function_arg_advance
128 #undef TARGET_STRUCT_VALUE_RTX
129 #define TARGET_STRUCT_VALUE_RTX vax_struct_value_rtx
131 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
132 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE vax_builtin_setjmp_frame_value
134 #undef TARGET_LEGITIMATE_ADDRESS_P
135 #define TARGET_LEGITIMATE_ADDRESS_P vax_legitimate_address_p
136 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
137 #define TARGET_MODE_DEPENDENT_ADDRESS_P vax_mode_dependent_address_p
139 #undef TARGET_FRAME_POINTER_REQUIRED
140 #define TARGET_FRAME_POINTER_REQUIRED hook_bool_void_true
142 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
143 #define TARGET_ASM_TRAMPOLINE_TEMPLATE vax_asm_trampoline_template
144 #undef TARGET_TRAMPOLINE_INIT
145 #define TARGET_TRAMPOLINE_INIT vax_trampoline_init
146 #undef TARGET_RETURN_POPS_ARGS
147 #define TARGET_RETURN_POPS_ARGS vax_return_pops_args
149 #undef TARGET_OPTION_OVERRIDE
150 #define TARGET_OPTION_OVERRIDE vax_option_override
152 struct gcc_target targetm
= TARGET_INITIALIZER
;
154 /* Set global variables as needed for the options enabled. */
157 vax_option_override (void)
159 /* We're VAX floating point, not IEEE floating point. */
161 REAL_MODE_FORMAT (DFmode
) = &vax_g_format
;
163 #ifdef SUBTARGET_OVERRIDE_OPTIONS
164 SUBTARGET_OVERRIDE_OPTIONS
;
169 vax_add_reg_cfa_offset (rtx insn
, int offset
, rtx src
)
173 x
= plus_constant (Pmode
, frame_pointer_rtx
, offset
);
174 x
= gen_rtx_MEM (SImode
, x
);
175 x
= gen_rtx_SET (x
, src
);
176 add_reg_note (insn
, REG_CFA_OFFSET
, x
);
179 /* Generate the assembly code for function entry. FILE is a stdio
180 stream to output the code to. SIZE is an int: how many units of
181 temporary storage to allocate.
183 Refer to the array `regs_ever_live' to determine which registers to
184 save; `regs_ever_live[I]' is nonzero if register number I is ever
185 used in the function. This function is responsible for knowing
186 which registers should not be saved even if used. */
189 vax_expand_prologue (void)
196 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
197 if (df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
200 insn
= emit_insn (gen_procedure_entry_mask (GEN_INT (mask
)));
201 RTX_FRAME_RELATED_P (insn
) = 1;
203 /* The layout of the CALLG/S stack frame is follows:
208 ... Registers saved as specified by MASK
218 The rest of the prologue will adjust the SP for the local frame. */
220 vax_add_reg_cfa_offset (insn
, 4, arg_pointer_rtx
);
221 vax_add_reg_cfa_offset (insn
, 8, frame_pointer_rtx
);
222 vax_add_reg_cfa_offset (insn
, 12, pc_rtx
);
225 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
226 if (mask
& (1 << regno
))
228 vax_add_reg_cfa_offset (insn
, offset
, gen_rtx_REG (SImode
, regno
));
232 /* Because add_reg_note pushes the notes, adding this last means that
233 it will be processed first. This is required to allow the other
234 notes be interpreted properly. */
235 add_reg_note (insn
, REG_CFA_DEF_CFA
,
236 plus_constant (Pmode
, frame_pointer_rtx
, offset
));
238 /* Allocate the local stack frame. */
239 size
= get_frame_size ();
240 size
-= STARTING_FRAME_OFFSET
;
241 emit_insn (gen_addsi3 (stack_pointer_rtx
,
242 stack_pointer_rtx
, GEN_INT (-size
)));
244 /* Do not allow instructions referencing local stack memory to be
245 scheduled before the frame is allocated. This is more pedantic
246 than anything else, given that VAX does not currently have a
247 scheduling description. */
248 emit_insn (gen_blockage ());
251 /* When debugging with stabs, we want to output an extra dummy label
252 so that gas can distinguish between D_float and G_float prior to
253 processing the .stabs directive identifying type double. */
255 vax_file_start (void)
257 default_file_start ();
259 if (write_symbols
== DBX_DEBUG
)
260 fprintf (asm_out_file
, "___vax_%c_doubles:\n", ASM_DOUBLE_CHAR
);
263 /* We can use the BSD C library routines for the libgcc calls that are
264 still generated, since that's what they boil down to anyways. When
265 ELF, avoid the user's namespace. */
268 vax_init_libfuncs (void)
270 if (TARGET_BSD_DIVMOD
)
272 set_optab_libfunc (udiv_optab
, SImode
, TARGET_ELF
? "*__udiv" : "*udiv");
273 set_optab_libfunc (umod_optab
, SImode
, TARGET_ELF
? "*__urem" : "*urem");
277 /* This is like nonimmediate_operand with a restriction on the type of MEM. */
280 split_quadword_operands (rtx insn
, enum rtx_code code
, rtx
* operands
,
285 for (i
= 0; i
< n
; i
++)
288 for (i
= 0; i
< n
; i
++)
290 if (MEM_P (operands
[i
])
291 && (GET_CODE (XEXP (operands
[i
], 0)) == PRE_DEC
292 || GET_CODE (XEXP (operands
[i
], 0)) == POST_INC
))
294 rtx addr
= XEXP (operands
[i
], 0);
295 operands
[i
] = low
[i
] = gen_rtx_MEM (SImode
, addr
);
297 else if (optimize_size
&& MEM_P (operands
[i
])
298 && REG_P (XEXP (operands
[i
], 0))
299 && (code
!= MINUS
|| operands
[1] != const0_rtx
)
300 && find_regno_note (insn
, REG_DEAD
,
301 REGNO (XEXP (operands
[i
], 0))))
303 low
[i
] = gen_rtx_MEM (SImode
,
304 gen_rtx_POST_INC (Pmode
,
305 XEXP (operands
[i
], 0)));
306 operands
[i
] = gen_rtx_MEM (SImode
, XEXP (operands
[i
], 0));
310 low
[i
] = operand_subword (operands
[i
], 0, 0, DImode
);
311 operands
[i
] = operand_subword (operands
[i
], 1, 0, DImode
);
317 print_operand_address (FILE * file
, rtx addr
)
320 rtx reg1
, breg
, ireg
;
324 switch (GET_CODE (addr
))
328 addr
= XEXP (addr
, 0);
332 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
336 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
340 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
344 /* There can be either two or three things added here. One must be a
345 REG. One can be either a REG or a MULT of a REG and an appropriate
346 constant, and the third can only be a constant or a MEM.
348 We get these two or three things and put the constant or MEM in
349 OFFSET, the MULT or REG in IREG, and the REG in BREG. If we have
350 a register and can't tell yet if it is a base or index register,
353 reg1
= 0; ireg
= 0; breg
= 0; offset
= 0;
355 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0))
356 || MEM_P (XEXP (addr
, 0)))
358 offset
= XEXP (addr
, 0);
359 addr
= XEXP (addr
, 1);
361 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1))
362 || MEM_P (XEXP (addr
, 1)))
364 offset
= XEXP (addr
, 1);
365 addr
= XEXP (addr
, 0);
367 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
369 ireg
= XEXP (addr
, 1);
370 addr
= XEXP (addr
, 0);
372 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
374 ireg
= XEXP (addr
, 0);
375 addr
= XEXP (addr
, 1);
377 else if (REG_P (XEXP (addr
, 1)))
379 reg1
= XEXP (addr
, 1);
380 addr
= XEXP (addr
, 0);
382 else if (REG_P (XEXP (addr
, 0)))
384 reg1
= XEXP (addr
, 0);
385 addr
= XEXP (addr
, 1);
397 else if (GET_CODE (addr
) == MULT
)
401 gcc_assert (GET_CODE (addr
) == PLUS
);
402 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0))
403 || MEM_P (XEXP (addr
, 0)))
407 if (CONST_INT_P (offset
))
408 offset
= plus_constant (Pmode
, XEXP (addr
, 0),
412 gcc_assert (CONST_INT_P (XEXP (addr
, 0)));
413 offset
= plus_constant (Pmode
, offset
,
414 INTVAL (XEXP (addr
, 0)));
417 offset
= XEXP (addr
, 0);
419 else if (REG_P (XEXP (addr
, 0)))
422 ireg
= reg1
, breg
= XEXP (addr
, 0), reg1
= 0;
424 reg1
= XEXP (addr
, 0);
428 gcc_assert (GET_CODE (XEXP (addr
, 0)) == MULT
);
430 ireg
= XEXP (addr
, 0);
433 if (CONSTANT_ADDRESS_P (XEXP (addr
, 1))
434 || MEM_P (XEXP (addr
, 1)))
438 if (CONST_INT_P (offset
))
439 offset
= plus_constant (Pmode
, XEXP (addr
, 1),
443 gcc_assert (CONST_INT_P (XEXP (addr
, 1)));
444 offset
= plus_constant (Pmode
, offset
,
445 INTVAL (XEXP (addr
, 1)));
448 offset
= XEXP (addr
, 1);
450 else if (REG_P (XEXP (addr
, 1)))
453 ireg
= reg1
, breg
= XEXP (addr
, 1), reg1
= 0;
455 reg1
= XEXP (addr
, 1);
459 gcc_assert (GET_CODE (XEXP (addr
, 1)) == MULT
);
461 ireg
= XEXP (addr
, 1);
465 /* If REG1 is nonzero, figure out if it is a base or index register. */
469 || (flag_pic
&& GET_CODE (addr
) == SYMBOL_REF
)
472 || (flag_pic
&& symbolic_operand (offset
, SImode
)))))
483 if (flag_pic
&& symbolic_operand (offset
, SImode
))
488 output_operand_lossage ("symbol used with both base and indexed registers");
491 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS
492 if (flag_pic
> 1 && GET_CODE (offset
) == CONST
493 && GET_CODE (XEXP (XEXP (offset
, 0), 0)) == SYMBOL_REF
494 && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (offset
, 0), 0)))
497 output_operand_lossage ("symbol with offset used in PIC mode");
501 /* symbol(reg) isn't PIC, but symbol[reg] is. */
510 output_address (offset
);
514 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
518 if (GET_CODE (ireg
) == MULT
)
519 ireg
= XEXP (ireg
, 0);
520 gcc_assert (REG_P (ireg
));
521 fprintf (file
, "[%s]", reg_names
[REGNO (ireg
)]);
526 output_addr_const (file
, addr
);
531 print_operand (FILE *file
, rtx x
, int code
)
534 fputc (ASM_DOUBLE_CHAR
, file
);
535 else if (code
== '|')
536 fputs (REGISTER_PREFIX
, file
);
537 else if (code
== 'c')
538 fputs (cond_name (x
), file
);
539 else if (code
== 'C')
540 fputs (rev_cond_name (x
), file
);
541 else if (code
== 'D' && CONST_INT_P (x
) && INTVAL (x
) < 0)
542 fprintf (file
, "$" NEG_HWI_PRINT_HEX16
, INTVAL (x
));
543 else if (code
== 'P' && CONST_INT_P (x
))
544 fprintf (file
, "$" HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) + 1);
545 else if (code
== 'N' && CONST_INT_P (x
))
546 fprintf (file
, "$" HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
547 /* rotl instruction cannot deal with negative arguments. */
548 else if (code
== 'R' && CONST_INT_P (x
))
549 fprintf (file
, "$" HOST_WIDE_INT_PRINT_DEC
, 32 - INTVAL (x
));
550 else if (code
== 'H' && CONST_INT_P (x
))
551 fprintf (file
, "$%d", (int) (0xffff & ~ INTVAL (x
)));
552 else if (code
== 'h' && CONST_INT_P (x
))
553 fprintf (file
, "$%d", (short) - INTVAL (x
));
554 else if (code
== 'B' && CONST_INT_P (x
))
555 fprintf (file
, "$%d", (int) (0xff & ~ INTVAL (x
)));
556 else if (code
== 'b' && CONST_INT_P (x
))
557 fprintf (file
, "$%d", (int) (0xff & - INTVAL (x
)));
558 else if (code
== 'M' && CONST_INT_P (x
))
559 fprintf (file
, "$%d", ~((1 << INTVAL (x
)) - 1));
560 else if (code
== 'x' && CONST_INT_P (x
))
561 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
563 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
565 output_address (XEXP (x
, 0));
566 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == SFmode
)
569 real_to_decimal (dstr
, CONST_DOUBLE_REAL_VALUE (x
),
570 sizeof (dstr
), 0, 1);
571 fprintf (file
, "$0f%s", dstr
);
573 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == DFmode
)
576 real_to_decimal (dstr
, CONST_DOUBLE_REAL_VALUE (x
),
577 sizeof (dstr
), 0, 1);
578 fprintf (file
, "$0%c%s", ASM_DOUBLE_CHAR
, dstr
);
582 if (flag_pic
> 1 && symbolic_operand (x
, SImode
))
585 output_operand_lossage ("symbol used as immediate operand");
588 output_addr_const (file
, x
);
595 switch (GET_CODE (op
))
624 rev_cond_name (rtx op
)
626 switch (GET_CODE (op
))
655 vax_float_literal (rtx c
)
658 REAL_VALUE_TYPE r
, s
;
661 if (GET_CODE (c
) != CONST_DOUBLE
)
666 if (c
== const_tiny_rtx
[(int) mode
][0]
667 || c
== const_tiny_rtx
[(int) mode
][1]
668 || c
== const_tiny_rtx
[(int) mode
][2])
671 REAL_VALUE_FROM_CONST_DOUBLE (r
, c
);
673 for (i
= 0; i
< 7; i
++)
677 real_from_integer (&s
, mode
, x
, SIGNED
);
679 if (REAL_VALUES_EQUAL (r
, s
))
681 ok
= exact_real_inverse (mode
, &s
);
683 if (REAL_VALUES_EQUAL (r
, s
))
690 /* Return the cost in cycles of a memory address, relative to register
693 Each of the following adds the indicated number of cycles:
697 1 - indexing and/or offset(register)
702 vax_address_cost_1 (rtx addr
)
704 int reg
= 0, indexed
= 0, indir
= 0, offset
= 0, predec
= 0;
705 rtx plus_op0
= 0, plus_op1
= 0;
707 switch (GET_CODE (addr
))
717 indexed
= 1; /* 2 on VAX 2 */
720 /* byte offsets cost nothing (on a VAX 2, they cost 1 cycle) */
722 offset
= (unsigned HOST_WIDE_INT
)(INTVAL(addr
)+128) > 256;
726 offset
= 1; /* 2 on VAX 2 */
728 case LABEL_REF
: /* this is probably a byte offset from the pc */
734 plus_op1
= XEXP (addr
, 0);
736 plus_op0
= XEXP (addr
, 0);
737 addr
= XEXP (addr
, 1);
740 indir
= 2; /* 3 on VAX 2 */
741 addr
= XEXP (addr
, 0);
747 /* Up to 3 things can be added in an address. They are stored in
748 plus_op0, plus_op1, and addr. */
762 /* Indexing and register+offset can both be used (except on a VAX 2)
763 without increasing execution time over either one alone. */
764 if (reg
&& indexed
&& offset
)
765 return reg
+ indir
+ offset
+ predec
;
766 return reg
+ indexed
+ indir
+ offset
+ predec
;
770 vax_address_cost (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
,
771 addr_space_t as ATTRIBUTE_UNUSED
,
772 bool speed ATTRIBUTE_UNUSED
)
774 return (1 + (REG_P (x
) ? 0 : vax_address_cost_1 (x
)));
777 /* Cost of an expression on a VAX. This version has costs tuned for the
778 CVAX chip (found in the VAX 3 series) with comments for variations on
781 FIXME: The costs need review, particularly for TRUNCATE, FLOAT_EXTEND
782 and FLOAT_TRUNCATE. We need a -mcpu option to allow provision of
783 costs on a per cpu basis. */
786 vax_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
787 int *total
, bool speed ATTRIBUTE_UNUSED
)
789 machine_mode mode
= GET_MODE (x
);
790 int i
= 0; /* may be modified in switch */
791 const char *fmt
= GET_RTX_FORMAT (code
); /* may be modified in switch */
795 /* On a VAX, constants from 0..63 are cheap because they can use the
796 1 byte literal constant format. Compare to -1 should be made cheap
797 so that decrement-and-branch insns can be formed more easily (if
798 the value -1 is copied to a register some decrement-and-branch
799 patterns will not match). */
806 if (outer_code
== AND
)
808 *total
= ((unsigned HOST_WIDE_INT
) ~INTVAL (x
) <= 077) ? 1 : 2;
811 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) <= 077
812 || (outer_code
== COMPARE
814 || ((outer_code
== PLUS
|| outer_code
== MINUS
)
815 && (unsigned HOST_WIDE_INT
) -INTVAL (x
) <= 077))
829 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
830 *total
= vax_float_literal (x
) ? 5 : 8;
832 *total
= ((CONST_DOUBLE_HIGH (x
) == 0
833 && (unsigned HOST_WIDE_INT
) CONST_DOUBLE_LOW (x
) < 64)
834 || (outer_code
== PLUS
835 && CONST_DOUBLE_HIGH (x
) == -1
836 && (unsigned HOST_WIDE_INT
)-CONST_DOUBLE_LOW (x
) < 64))
842 return true; /* Implies register operand. */
846 return true; /* Implies register operand. */
852 *total
= 16; /* 4 on VAX 9000 */
855 *total
= 9; /* 4 on VAX 9000, 12 on VAX 2 */
858 *total
= 16; /* 6 on VAX 9000, 28 on VAX 2 */
863 *total
= 10; /* 3-4 on VAX 9000, 20-28 on VAX 2 */
866 *total
= MAX_COST
; /* Mode is not supported. */
874 *total
= MAX_COST
; /* Mode is not supported. */
882 *total
= 30; /* Highly variable. */
883 else if (mode
== DFmode
)
884 /* divide takes 28 cycles if the result is not zero, 13 otherwise */
887 *total
= 11; /* 25 on VAX 2 */
897 *total
= MAX_COST
; /* Mode is not supported. */
904 *total
= (6 /* 4 on VAX 9000 */
905 + (mode
== DFmode
) + (GET_MODE (XEXP (x
, 0)) != SImode
));
909 *total
= 7; /* 17 on VAX 2 */
918 *total
= 10; /* 6 on VAX 9000 */
923 *total
= 6; /* 5 on VAX 2, 4 on VAX 9000 */
924 if (CONST_INT_P (XEXP (x
, 1)))
925 fmt
= "e"; /* all constant rotate counts are short */
930 *total
= (mode
== DFmode
) ? 13 : 8; /* 6/8 on VAX 9000, 16/15 on VAX 2 */
931 /* Small integer operands can use subl2 and addl2. */
932 if ((CONST_INT_P (XEXP (x
, 1)))
933 && (unsigned HOST_WIDE_INT
)(INTVAL (XEXP (x
, 1)) + 63) < 127)
943 /* AND is special because the first operand is complemented. */
945 if (CONST_INT_P (XEXP (x
, 0)))
947 if ((unsigned HOST_WIDE_INT
)~INTVAL (XEXP (x
, 0)) > 63)
957 else if (mode
== SFmode
)
959 else if (mode
== DImode
)
975 if (mode
== DImode
|| mode
== DFmode
)
976 *total
= 5; /* 7 on VAX 2 */
978 *total
= 3; /* 4 on VAX 2 */
980 if (!REG_P (x
) && GET_CODE (x
) != POST_INC
)
981 *total
+= vax_address_cost_1 (x
);
987 *total
= 3; /* FIXME: Costs need to be checked */
994 /* Now look inside the expression. Operands which are not registers or
995 short constants add to the cost.
997 FMT and I may have been adjusted in the switch above for instructions
998 which require special handling. */
1000 while (*fmt
++ == 'e')
1002 rtx op
= XEXP (x
, i
);
1005 code
= GET_CODE (op
);
1007 /* A NOT is likely to be found as the first operand of an AND
1008 (in which case the relevant cost is of the operand inside
1009 the not) and not likely to be found anywhere else. */
1011 op
= XEXP (op
, 0), code
= GET_CODE (op
);
1016 if ((unsigned HOST_WIDE_INT
)INTVAL (op
) > 63
1017 && GET_MODE (x
) != QImode
)
1018 *total
+= 1; /* 2 on VAX 2 */
1023 *total
+= 1; /* 2 on VAX 2 */
1026 if (GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
1028 /* Registers are faster than floating point constants -- even
1029 those constants which can be encoded in a single byte. */
1030 if (vax_float_literal (op
))
1033 *total
+= (GET_MODE (x
) == DFmode
) ? 3 : 2;
1037 if (CONST_DOUBLE_HIGH (op
) != 0
1038 || (unsigned HOST_WIDE_INT
)CONST_DOUBLE_LOW (op
) > 63)
1043 *total
+= 1; /* 2 on VAX 2 */
1044 if (!REG_P (XEXP (op
, 0)))
1045 *total
+= vax_address_cost_1 (XEXP (op
, 0));
1058 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
1059 Used for C++ multiple inheritance.
1060 .mask ^m<r2,r3,r4,r5,r6,r7,r8,r9,r10,r11> #conservative entry mask
1061 addl2 $DELTA, 4(ap) #adjust first argument
1062 jmp FUNCTION+2 #jump beyond FUNCTION's entry mask
1066 vax_output_mi_thunk (FILE * file
,
1067 tree thunk ATTRIBUTE_UNUSED
,
1068 HOST_WIDE_INT delta
,
1069 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
1072 fprintf (file
, "\t.word 0x0ffc\n\taddl2 $" HOST_WIDE_INT_PRINT_DEC
, delta
);
1073 asm_fprintf (file
, ",4(%Rap)\n");
1074 fprintf (file
, "\tjmp ");
1075 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
1076 fprintf (file
, "+2\n");
1080 vax_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
1081 int incoming ATTRIBUTE_UNUSED
)
1083 return gen_rtx_REG (Pmode
, VAX_STRUCT_VALUE_REGNUM
);
1087 vax_builtin_setjmp_frame_value (void)
1089 return hard_frame_pointer_rtx
;
1092 /* Worker function for NOTICE_UPDATE_CC. */
1095 vax_notice_update_cc (rtx exp
, rtx insn ATTRIBUTE_UNUSED
)
1097 if (GET_CODE (exp
) == SET
)
1099 if (GET_CODE (SET_SRC (exp
)) == CALL
)
1101 else if (GET_CODE (SET_DEST (exp
)) != ZERO_EXTRACT
1102 && GET_CODE (SET_DEST (exp
)) != PC
)
1104 cc_status
.flags
= 0;
1105 /* The integer operations below don't set carry or
1106 set it in an incompatible way. That's ok though
1107 as the Z bit is all we need when doing unsigned
1108 comparisons on the result of these insns (since
1109 they're always with 0). Set CC_NO_OVERFLOW to
1110 generate the correct unsigned branches. */
1111 switch (GET_CODE (SET_SRC (exp
)))
1114 if (GET_MODE_CLASS (GET_MODE (exp
)) == MODE_FLOAT
)
1122 cc_status
.flags
= CC_NO_OVERFLOW
;
1127 cc_status
.value1
= SET_DEST (exp
);
1128 cc_status
.value2
= SET_SRC (exp
);
1131 else if (GET_CODE (exp
) == PARALLEL
1132 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
1134 if (GET_CODE (SET_SRC (XVECEXP (exp
, 0, 0))) == CALL
)
1136 else if (GET_CODE (SET_DEST (XVECEXP (exp
, 0, 0))) != PC
)
1138 cc_status
.flags
= 0;
1139 cc_status
.value1
= SET_DEST (XVECEXP (exp
, 0, 0));
1140 cc_status
.value2
= SET_SRC (XVECEXP (exp
, 0, 0));
1143 /* PARALLELs whose first element sets the PC are aob,
1144 sob insns. They do change the cc's. */
1149 if (cc_status
.value1
&& REG_P (cc_status
.value1
)
1151 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
1152 cc_status
.value2
= 0;
1153 if (cc_status
.value1
&& MEM_P (cc_status
.value1
)
1155 && MEM_P (cc_status
.value2
))
1156 cc_status
.value2
= 0;
1157 /* Actual condition, one line up, should be that value2's address
1158 depends on value1, but that is too much of a pain. */
1161 /* Output integer move instructions. */
1164 vax_output_int_move (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
,
1168 const char *pattern_hi
, *pattern_lo
;
1173 if (operands
[1] == const0_rtx
)
1175 if (TARGET_QMATH
&& optimize_size
1176 && (CONST_INT_P (operands
[1])
1177 || GET_CODE (operands
[1]) == CONST_DOUBLE
))
1179 unsigned HOST_WIDE_INT hval
, lval
;
1182 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1184 gcc_assert (HOST_BITS_PER_WIDE_INT
!= 64);
1186 /* Make sure only the low 32 bits are valid. */
1187 lval
= CONST_DOUBLE_LOW (operands
[1]) & 0xffffffff;
1188 hval
= CONST_DOUBLE_HIGH (operands
[1]) & 0xffffffff;
1192 lval
= INTVAL (operands
[1]);
1196 /* Here we see if we are trying to see if the 64bit value is really
1197 a 6bit shifted some arbitrary amount. If so, we can use ashq to
1198 shift it to the correct value saving 7 bytes (1 addr-mode-byte +
1199 8 bytes - 1 shift byte - 1 short literal byte. */
1201 && (n
= exact_log2 (lval
& (- lval
))) != -1
1202 && (lval
>> n
) < 64)
1206 /* On 32bit platforms, if the 6bits didn't overflow into the
1207 upper 32bit value that value better be 0. If we have
1208 overflowed, make sure it wasn't too much. */
1209 if (HOST_BITS_PER_WIDE_INT
== 32 && hval
!= 0)
1211 if (n
<= 26 || hval
>= ((unsigned)1 << (n
- 26)))
1212 n
= 0; /* failure */
1214 lval
|= hval
<< (32 - n
);
1216 /* If n is 0, then ashq is not the best way to emit this. */
1219 operands
[1] = GEN_INT (lval
);
1220 operands
[2] = GEN_INT (n
);
1221 return "ashq %2,%D1,%0";
1223 #if HOST_BITS_PER_WIDE_INT == 32
1225 /* On 32bit platforms, if the low 32bit value is 0, checkout the
1226 upper 32bit value. */
1228 && (n
= exact_log2 (hval
& (- hval
)) - 1) != -1
1229 && (hval
>> n
) < 64)
1231 operands
[1] = GEN_INT (hval
>> n
);
1232 operands
[2] = GEN_INT (n
+ 32);
1233 return "ashq %2,%D1,%0";
1239 && (!MEM_P (operands
[0])
1240 || GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1241 || GET_CODE (XEXP (operands
[0], 0)) == POST_INC
1242 || !illegal_addsub_di_memory_operand (operands
[0], DImode
))
1243 && ((CONST_INT_P (operands
[1])
1244 && (unsigned HOST_WIDE_INT
) INTVAL (operands
[1]) >= 64)
1245 || GET_CODE (operands
[1]) == CONST_DOUBLE
))
1247 hi
[0] = operands
[0];
1248 hi
[1] = operands
[1];
1250 split_quadword_operands (insn
, SET
, hi
, lo
, 2);
1252 pattern_lo
= vax_output_int_move (NULL
, lo
, SImode
);
1253 pattern_hi
= vax_output_int_move (NULL
, hi
, SImode
);
1255 /* The patterns are just movl/movl or pushl/pushl then a movq will
1256 be shorter (1 opcode byte + 1 addrmode byte + 8 immediate value
1257 bytes .vs. 2 opcode bytes + 2 addrmode bytes + 8 immediate value
1259 if ((!strncmp (pattern_lo
, "movl", 4)
1260 && !strncmp (pattern_hi
, "movl", 4))
1261 || (!strncmp (pattern_lo
, "pushl", 5)
1262 && !strncmp (pattern_hi
, "pushl", 5)))
1263 return "movq %1,%0";
1265 if (MEM_P (operands
[0])
1266 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1268 output_asm_insn (pattern_hi
, hi
);
1269 operands
[0] = lo
[0];
1270 operands
[1] = lo
[1];
1271 operands
[2] = lo
[2];
1276 output_asm_insn (pattern_lo
, lo
);
1277 operands
[0] = hi
[0];
1278 operands
[1] = hi
[1];
1279 operands
[2] = hi
[2];
1283 return "movq %1,%0";
1286 if (symbolic_operand (operands
[1], SImode
))
1288 if (push_operand (operands
[0], SImode
))
1289 return "pushab %a1";
1290 return "movab %a1,%0";
1293 if (operands
[1] == const0_rtx
)
1295 if (push_operand (operands
[1], SImode
))
1300 if (CONST_INT_P (operands
[1])
1301 && (unsigned HOST_WIDE_INT
) INTVAL (operands
[1]) >= 64)
1303 HOST_WIDE_INT i
= INTVAL (operands
[1]);
1305 if ((unsigned HOST_WIDE_INT
)(~i
) < 64)
1306 return "mcoml %N1,%0";
1307 if ((unsigned HOST_WIDE_INT
)i
< 0x100)
1308 return "movzbl %1,%0";
1309 if (i
>= -0x80 && i
< 0)
1310 return "cvtbl %1,%0";
1312 && (n
= exact_log2 (i
& (-i
))) != -1
1313 && ((unsigned HOST_WIDE_INT
)i
>> n
) < 64)
1315 operands
[1] = GEN_INT ((unsigned HOST_WIDE_INT
)i
>> n
);
1316 operands
[2] = GEN_INT (n
);
1317 return "ashl %2,%1,%0";
1319 if ((unsigned HOST_WIDE_INT
)i
< 0x10000)
1320 return "movzwl %1,%0";
1321 if (i
>= -0x8000 && i
< 0)
1322 return "cvtwl %1,%0";
1324 if (push_operand (operands
[0], SImode
))
1326 return "movl %1,%0";
1329 if (CONST_INT_P (operands
[1]))
1331 HOST_WIDE_INT i
= INTVAL (operands
[1]);
1334 else if ((unsigned HOST_WIDE_INT
)i
< 64)
1335 return "movw %1,%0";
1336 else if ((unsigned HOST_WIDE_INT
)~i
< 64)
1337 return "mcomw %H1,%0";
1338 else if ((unsigned HOST_WIDE_INT
)i
< 256)
1339 return "movzbw %1,%0";
1340 else if (i
>= -0x80 && i
< 0)
1341 return "cvtbw %1,%0";
1343 return "movw %1,%0";
1346 if (CONST_INT_P (operands
[1]))
1348 HOST_WIDE_INT i
= INTVAL (operands
[1]);
1351 else if ((unsigned HOST_WIDE_INT
)~i
< 64)
1352 return "mcomb %B1,%0";
1354 return "movb %1,%0";
1361 /* Output integer add instructions.
1363 The space-time-opcode tradeoffs for addition vary by model of VAX.
1365 On a VAX 3 "movab (r1)[r2],r3" is faster than "addl3 r1,r2,r3",
1366 but it not faster on other models.
1368 "movab #(r1),r2" is usually shorter than "addl3 #,r1,r2", and is
1369 faster on a VAX 3, but some VAXen (e.g. VAX 9000) will stall if
1370 a register is used in an address too soon after it is set.
1371 Compromise by using movab only when it is shorter than the add
1372 or the base register in the address is one of sp, ap, and fp,
1373 which are not modified very often. */
1376 vax_output_int_add (rtx insn
, rtx
*operands
, machine_mode mode
)
1383 const char *pattern
;
1387 if (TARGET_QMATH
&& 0)
1390 split_quadword_operands (insn
, PLUS
, operands
, low
, 3);
1394 gcc_assert (rtx_equal_p (operands
[0], operands
[1]));
1395 #ifdef NO_EXTERNAL_INDIRECT_ADDRESSS
1396 gcc_assert (!flag_pic
|| !external_memory_operand (low
[2], SImode
));
1397 gcc_assert (!flag_pic
|| !external_memory_operand (low
[0], SImode
));
1400 /* No reason to add a 0 to the low part and thus no carry, so just
1401 emit the appropriate add/sub instruction. */
1402 if (low
[2] == const0_rtx
)
1403 return vax_output_int_add (NULL
, operands
, SImode
);
1405 /* Are we doing addition or subtraction? */
1406 sub
= CONST_INT_P (operands
[2]) && INTVAL (operands
[2]) < 0;
1408 /* We can't use vax_output_int_add since some the patterns don't
1409 modify the carry bit. */
1412 if (low
[2] == constm1_rtx
)
1413 pattern
= "decl %0";
1415 pattern
= "subl2 $%n2,%0";
1419 if (low
[2] == const1_rtx
)
1420 pattern
= "incl %0";
1422 pattern
= "addl2 %2,%0";
1424 output_asm_insn (pattern
, low
);
1426 /* In 2's complement, -n = ~n + 1. Since we are dealing with
1427 two 32bit parts, we complement each and then add one to
1428 low part. We know that the low part can't overflow since
1429 it's value can never be 0. */
1431 return "sbwc %N2,%0";
1432 return "adwc %2,%0";
1435 /* Add low parts. */
1436 if (rtx_equal_p (operands
[0], operands
[1]))
1438 if (low
[2] == const0_rtx
)
1439 /* Should examine operand, punt if not POST_INC. */
1440 pattern
= "tstl %0", carry
= 0;
1441 else if (low
[2] == const1_rtx
)
1442 pattern
= "incl %0";
1444 pattern
= "addl2 %2,%0";
1448 if (low
[2] == const0_rtx
)
1449 pattern
= "movl %1,%0", carry
= 0;
1451 pattern
= "addl3 %2,%1,%0";
1454 output_asm_insn (pattern
, low
);
1456 /* If CARRY is 0, we don't have any carry value to worry about. */
1457 return get_insn_template (CODE_FOR_addsi3
, insn
);
1458 /* %0 = C + %1 + %2 */
1459 if (!rtx_equal_p (operands
[0], operands
[1]))
1460 output_asm_insn ((operands
[1] == const0_rtx
1462 : "movl %1,%0"), operands
);
1463 return "adwc %2,%0";
1467 if (rtx_equal_p (operands
[0], operands
[1]))
1469 if (operands
[2] == const1_rtx
)
1471 if (operands
[2] == constm1_rtx
)
1473 if (CONST_INT_P (operands
[2])
1474 && (unsigned HOST_WIDE_INT
) (- INTVAL (operands
[2])) < 64)
1475 return "subl2 $%n2,%0";
1476 if (CONST_INT_P (operands
[2])
1477 && (unsigned HOST_WIDE_INT
) INTVAL (operands
[2]) >= 64
1478 && REG_P (operands
[1])
1479 && ((INTVAL (operands
[2]) < 32767 && INTVAL (operands
[2]) > -32768)
1480 || REGNO (operands
[1]) > 11))
1481 return "movab %c2(%1),%0";
1482 if (REG_P (operands
[0]) && symbolic_operand (operands
[2], SImode
))
1483 return "movab %a2[%0],%0";
1484 return "addl2 %2,%0";
1487 if (rtx_equal_p (operands
[0], operands
[2]))
1489 if (REG_P (operands
[0]) && symbolic_operand (operands
[1], SImode
))
1490 return "movab %a1[%0],%0";
1491 return "addl2 %1,%0";
1494 if (CONST_INT_P (operands
[2])
1495 && INTVAL (operands
[2]) < 32767
1496 && INTVAL (operands
[2]) > -32768
1497 && REG_P (operands
[1])
1498 && push_operand (operands
[0], SImode
))
1499 return "pushab %c2(%1)";
1501 if (CONST_INT_P (operands
[2])
1502 && (unsigned HOST_WIDE_INT
) (- INTVAL (operands
[2])) < 64)
1503 return "subl3 $%n2,%1,%0";
1505 if (CONST_INT_P (operands
[2])
1506 && (unsigned HOST_WIDE_INT
) INTVAL (operands
[2]) >= 64
1507 && REG_P (operands
[1])
1508 && ((INTVAL (operands
[2]) < 32767 && INTVAL (operands
[2]) > -32768)
1509 || REGNO (operands
[1]) > 11))
1510 return "movab %c2(%1),%0";
1512 /* Add this if using gcc on a VAX 3xxx:
1513 if (REG_P (operands[1]) && REG_P (operands[2]))
1514 return "movab (%1)[%2],%0";
1517 if (REG_P (operands
[1]) && symbolic_operand (operands
[2], SImode
))
1519 if (push_operand (operands
[0], SImode
))
1520 return "pushab %a2[%1]";
1521 return "movab %a2[%1],%0";
1524 if (REG_P (operands
[2]) && symbolic_operand (operands
[1], SImode
))
1526 if (push_operand (operands
[0], SImode
))
1527 return "pushab %a1[%2]";
1528 return "movab %a1[%2],%0";
1531 if (flag_pic
&& REG_P (operands
[0])
1532 && symbolic_operand (operands
[2], SImode
))
1533 return "movab %a2,%0;addl2 %1,%0";
1536 && (symbolic_operand (operands
[1], SImode
)
1537 || symbolic_operand (operands
[1], SImode
)))
1540 return "addl3 %1,%2,%0";
1543 if (rtx_equal_p (operands
[0], operands
[1]))
1545 if (operands
[2] == const1_rtx
)
1547 if (operands
[2] == constm1_rtx
)
1549 if (CONST_INT_P (operands
[2])
1550 && (unsigned HOST_WIDE_INT
) (- INTVAL (operands
[2])) < 64)
1551 return "subw2 $%n2,%0";
1552 return "addw2 %2,%0";
1554 if (rtx_equal_p (operands
[0], operands
[2]))
1555 return "addw2 %1,%0";
1556 if (CONST_INT_P (operands
[2])
1557 && (unsigned HOST_WIDE_INT
) (- INTVAL (operands
[2])) < 64)
1558 return "subw3 $%n2,%1,%0";
1559 return "addw3 %1,%2,%0";
1562 if (rtx_equal_p (operands
[0], operands
[1]))
1564 if (operands
[2] == const1_rtx
)
1566 if (operands
[2] == constm1_rtx
)
1568 if (CONST_INT_P (operands
[2])
1569 && (unsigned HOST_WIDE_INT
) (- INTVAL (operands
[2])) < 64)
1570 return "subb2 $%n2,%0";
1571 return "addb2 %2,%0";
1573 if (rtx_equal_p (operands
[0], operands
[2]))
1574 return "addb2 %1,%0";
1575 if (CONST_INT_P (operands
[2])
1576 && (unsigned HOST_WIDE_INT
) (- INTVAL (operands
[2])) < 64)
1577 return "subb3 $%n2,%1,%0";
1578 return "addb3 %1,%2,%0";
1586 vax_output_int_subtract (rtx insn
, rtx
*operands
, machine_mode mode
)
1593 const char *pattern
;
1596 if (TARGET_QMATH
&& 0)
1599 split_quadword_operands (insn
, MINUS
, operands
, low
, 3);
1603 if (operands
[1] == const0_rtx
&& low
[1] == const0_rtx
)
1605 /* Negation is tricky. It's basically complement and increment.
1606 Negate hi, then lo, and subtract the carry back. */
1607 if ((MEM_P (low
[0]) && GET_CODE (XEXP (low
[0], 0)) == POST_INC
)
1608 || (MEM_P (operands
[0])
1609 && GET_CODE (XEXP (operands
[0], 0)) == POST_INC
))
1610 fatal_insn ("illegal operand detected", insn
);
1611 output_asm_insn ("mnegl %2,%0", operands
);
1612 output_asm_insn ("mnegl %2,%0", low
);
1613 return "sbwc $0,%0";
1615 gcc_assert (rtx_equal_p (operands
[0], operands
[1]));
1616 gcc_assert (rtx_equal_p (low
[0], low
[1]));
1617 if (low
[2] == const1_rtx
)
1618 output_asm_insn ("decl %0", low
);
1620 output_asm_insn ("subl2 %2,%0", low
);
1621 return "sbwc %2,%0";
1624 /* Subtract low parts. */
1625 if (rtx_equal_p (operands
[0], operands
[1]))
1627 if (low
[2] == const0_rtx
)
1628 pattern
= 0, carry
= 0;
1629 else if (low
[2] == constm1_rtx
)
1630 pattern
= "decl %0";
1632 pattern
= "subl2 %2,%0";
1636 if (low
[2] == constm1_rtx
)
1637 pattern
= "decl %0";
1638 else if (low
[2] == const0_rtx
)
1639 pattern
= get_insn_template (CODE_FOR_movsi
, insn
), carry
= 0;
1641 pattern
= "subl3 %2,%1,%0";
1644 output_asm_insn (pattern
, low
);
1647 if (!rtx_equal_p (operands
[0], operands
[1]))
1648 return "movl %1,%0;sbwc %2,%0";
1649 return "sbwc %2,%0";
1650 /* %0 = %2 - %1 - C */
1652 return get_insn_template (CODE_FOR_subsi3
, insn
);
1660 /* True if X is an rtx for a constant that is a valid address. */
1663 legitimate_constant_address_p (rtx x
)
1665 if (GET_CODE (x
) == LABEL_REF
|| GET_CODE (x
) == SYMBOL_REF
1666 || CONST_INT_P (x
) || GET_CODE (x
) == HIGH
)
1668 if (GET_CODE (x
) != CONST
)
1670 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS
1672 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1673 && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (x
, 0), 0)))
1679 /* The other macros defined here are used only in legitimate_address_p (). */
1681 /* Nonzero if X is a hard reg that can be used as an index
1682 or, if not strict, if it is a pseudo reg. */
1683 #define INDEX_REGISTER_P(X, STRICT) \
1684 (REG_P (X) && (!(STRICT) || REGNO_OK_FOR_INDEX_P (REGNO (X))))
1686 /* Nonzero if X is a hard reg that can be used as a base reg
1687 or, if not strict, if it is a pseudo reg. */
1688 #define BASE_REGISTER_P(X, STRICT) \
1689 (REG_P (X) && (!(STRICT) || REGNO_OK_FOR_BASE_P (REGNO (X))))
1691 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS
1693 /* Re-definition of CONSTANT_ADDRESS_P, which is true only when there
1694 are no SYMBOL_REFs for external symbols present. */
1697 indirectable_constant_address_p (rtx x
, bool indirect
)
1699 if (GET_CODE (x
) == SYMBOL_REF
)
1700 return !flag_pic
|| SYMBOL_REF_LOCAL_P (x
) || !indirect
;
1702 if (GET_CODE (x
) == CONST
)
1704 || GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
1705 || SYMBOL_REF_LOCAL_P (XEXP (XEXP (x
, 0), 0));
1707 return CONSTANT_ADDRESS_P (x
);
1710 #else /* not NO_EXTERNAL_INDIRECT_ADDRESS */
1713 indirectable_constant_address_p (rtx x
, bool indirect ATTRIBUTE_UNUSED
)
1715 return CONSTANT_ADDRESS_P (x
);
1718 #endif /* not NO_EXTERNAL_INDIRECT_ADDRESS */
1720 /* True if X is an address which can be indirected. External symbols
1721 could be in a sharable image library, so we disallow those. */
1724 indirectable_address_p (rtx x
, bool strict
, bool indirect
)
1726 if (indirectable_constant_address_p (x
, indirect
)
1727 || BASE_REGISTER_P (x
, strict
))
1729 if (GET_CODE (x
) != PLUS
1730 || !BASE_REGISTER_P (XEXP (x
, 0), strict
)
1731 || (flag_pic
&& !CONST_INT_P (XEXP (x
, 1))))
1733 return indirectable_constant_address_p (XEXP (x
, 1), indirect
);
1736 /* Return true if x is a valid address not using indexing.
1737 (This much is the easy part.) */
1739 nonindexed_address_p (rtx x
, bool strict
)
1744 if (! reload_in_progress
1745 || reg_equiv_mem (REGNO (x
)) == 0
1746 || indirectable_address_p (reg_equiv_mem (REGNO (x
)), strict
, false))
1749 if (indirectable_constant_address_p (x
, false))
1751 if (indirectable_address_p (x
, strict
, false))
1753 xfoo0
= XEXP (x
, 0);
1754 if (MEM_P (x
) && indirectable_address_p (xfoo0
, strict
, true))
1756 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1757 && BASE_REGISTER_P (xfoo0
, strict
))
1762 /* True if PROD is either a reg times size of mode MODE and MODE is less
1763 than or equal 8 bytes, or just a reg if MODE is one byte. */
1766 index_term_p (rtx prod
, machine_mode mode
, bool strict
)
1770 if (GET_MODE_SIZE (mode
) == 1)
1771 return BASE_REGISTER_P (prod
, strict
);
1773 if (GET_CODE (prod
) != MULT
|| GET_MODE_SIZE (mode
) > 8)
1776 xfoo0
= XEXP (prod
, 0);
1777 xfoo1
= XEXP (prod
, 1);
1779 if (CONST_INT_P (xfoo0
)
1780 && INTVAL (xfoo0
) == (int)GET_MODE_SIZE (mode
)
1781 && INDEX_REGISTER_P (xfoo1
, strict
))
1784 if (CONST_INT_P (xfoo1
)
1785 && INTVAL (xfoo1
) == (int)GET_MODE_SIZE (mode
)
1786 && INDEX_REGISTER_P (xfoo0
, strict
))
1792 /* Return true if X is the sum of a register
1793 and a valid index term for mode MODE. */
1795 reg_plus_index_p (rtx x
, machine_mode mode
, bool strict
)
1799 if (GET_CODE (x
) != PLUS
)
1802 xfoo0
= XEXP (x
, 0);
1803 xfoo1
= XEXP (x
, 1);
1805 if (BASE_REGISTER_P (xfoo0
, strict
) && index_term_p (xfoo1
, mode
, strict
))
1808 if (BASE_REGISTER_P (xfoo1
, strict
) && index_term_p (xfoo0
, mode
, strict
))
1814 /* Return true if xfoo0 and xfoo1 constitute a valid indexed address. */
1816 indexable_address_p (rtx xfoo0
, rtx xfoo1
, machine_mode mode
, bool strict
)
1818 if (!CONSTANT_ADDRESS_P (xfoo0
))
1820 if (BASE_REGISTER_P (xfoo1
, strict
))
1821 return !flag_pic
|| mode
== QImode
;
1822 if (flag_pic
&& symbolic_operand (xfoo0
, SImode
))
1824 return reg_plus_index_p (xfoo1
, mode
, strict
);
1827 /* legitimate_address_p returns true if it recognizes an RTL expression "x"
1828 that is a valid memory address for an instruction.
1829 The MODE argument is the machine mode for the MEM expression
1830 that wants to use this address. */
1832 vax_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
1836 if (nonindexed_address_p (x
, strict
))
1839 if (GET_CODE (x
) != PLUS
)
1842 /* Handle <address>[index] represented with index-sum outermost */
1844 xfoo0
= XEXP (x
, 0);
1845 xfoo1
= XEXP (x
, 1);
1847 if (index_term_p (xfoo0
, mode
, strict
)
1848 && nonindexed_address_p (xfoo1
, strict
))
1851 if (index_term_p (xfoo1
, mode
, strict
)
1852 && nonindexed_address_p (xfoo0
, strict
))
1855 /* Handle offset(reg)[index] with offset added outermost */
1857 if (indexable_address_p (xfoo0
, xfoo1
, mode
, strict
)
1858 || indexable_address_p (xfoo1
, xfoo0
, mode
, strict
))
1864 /* Return true if x (a legitimate address expression) has an effect that
1865 depends on the machine mode it is used for. On the VAX, the predecrement
1866 and postincrement address depend thus (the amount of decrement or
1867 increment being the length of the operand) and all indexed address depend
1868 thus (because the index scale factor is the length of the operand). */
1871 vax_mode_dependent_address_p (const_rtx x
, addr_space_t as ATTRIBUTE_UNUSED
)
1875 /* Auto-increment cases are now dealt with generically in recog.c. */
1876 if (GET_CODE (x
) != PLUS
)
1879 xfoo0
= XEXP (x
, 0);
1880 xfoo1
= XEXP (x
, 1);
1882 if (CONST_INT_P (xfoo0
) && REG_P (xfoo1
))
1884 if (CONST_INT_P (xfoo1
) && REG_P (xfoo0
))
1886 if (!flag_pic
&& CONSTANT_ADDRESS_P (xfoo0
) && REG_P (xfoo1
))
1888 if (!flag_pic
&& CONSTANT_ADDRESS_P (xfoo1
) && REG_P (xfoo0
))
1895 fixup_mathdi_operand (rtx x
, machine_mode mode
)
1897 if (illegal_addsub_di_memory_operand (x
, mode
))
1899 rtx addr
= XEXP (x
, 0);
1900 rtx temp
= gen_reg_rtx (Pmode
);
1902 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS
1903 if (GET_CODE (addr
) == CONST
&& flag_pic
)
1905 offset
= XEXP (XEXP (addr
, 0), 1);
1906 addr
= XEXP (XEXP (addr
, 0), 0);
1909 emit_move_insn (temp
, addr
);
1911 temp
= gen_rtx_PLUS (Pmode
, temp
, offset
);
1912 x
= gen_rtx_MEM (DImode
, temp
);
1918 vax_expand_addsub_di_operands (rtx
* operands
, enum rtx_code code
)
1920 int hi_only
= operand_subword (operands
[2], 0, 0, DImode
) == const0_rtx
;
1923 rtx (*gen_old_insn
)(rtx
, rtx
, rtx
);
1924 rtx (*gen_si_insn
)(rtx
, rtx
, rtx
);
1925 rtx (*gen_insn
)(rtx
, rtx
, rtx
);
1929 gen_old_insn
= gen_adddi3_old
;
1930 gen_si_insn
= gen_addsi3
;
1931 gen_insn
= gen_adcdi3
;
1933 else if (code
== MINUS
)
1935 gen_old_insn
= gen_subdi3_old
;
1936 gen_si_insn
= gen_subsi3
;
1937 gen_insn
= gen_sbcdi3
;
1942 /* If this is addition (thus operands are commutative) and if there is one
1943 addend that duplicates the desination, we want that addend to be the
1946 && rtx_equal_p (operands
[0], operands
[2])
1947 && !rtx_equal_p (operands
[1], operands
[2]))
1950 operands
[2] = operands
[1];
1956 emit_insn ((*gen_old_insn
) (operands
[0], operands
[1], operands
[2]));
1960 if (!rtx_equal_p (operands
[0], operands
[1])
1961 && (REG_P (operands
[0]) && MEM_P (operands
[1])))
1963 emit_move_insn (operands
[0], operands
[1]);
1964 operands
[1] = operands
[0];
1967 operands
[0] = fixup_mathdi_operand (operands
[0], DImode
);
1968 operands
[1] = fixup_mathdi_operand (operands
[1], DImode
);
1969 operands
[2] = fixup_mathdi_operand (operands
[2], DImode
);
1971 if (!rtx_equal_p (operands
[0], operands
[1]))
1972 emit_move_insn (operand_subword (operands
[0], 0, 0, DImode
),
1973 operand_subword (operands
[1], 0, 0, DImode
));
1975 emit_insn ((*gen_si_insn
) (operand_subword (operands
[0], 1, 0, DImode
),
1976 operand_subword (operands
[1], 1, 0, DImode
),
1977 operand_subword (operands
[2], 1, 0, DImode
)));
1981 /* If are adding the same value together, that's really a multiply by 2,
1982 and that's just a left shift of 1. */
1983 if (rtx_equal_p (operands
[1], operands
[2]))
1985 gcc_assert (code
!= MINUS
);
1986 emit_insn (gen_ashldi3 (operands
[0], operands
[1], const1_rtx
));
1990 operands
[0] = fixup_mathdi_operand (operands
[0], DImode
);
1992 /* If an operand is the same as operand[0], use the operand[0] rtx
1993 because fixup will an equivalent rtx but not an equal one. */
1995 if (rtx_equal_p (operands
[0], operands
[1]))
1996 operands
[1] = operands
[0];
1998 operands
[1] = fixup_mathdi_operand (operands
[1], DImode
);
2000 if (rtx_equal_p (operands
[0], operands
[2]))
2001 operands
[2] = operands
[0];
2003 operands
[2] = fixup_mathdi_operand (operands
[2], DImode
);
2005 /* If we are subtracting not from ourselves [d = a - b], and because the
2006 carry ops are two operand only, we would need to do a move prior to
2007 the subtract. And if d == b, we would need a temp otherwise
2008 [d = a, d -= d] and we end up with 0. Instead we rewrite d = a - b
2009 into d = -b, d += a. Since -b can never overflow, even if b == d,
2012 If we are doing addition, since the carry ops are two operand, if
2013 we aren't adding to ourselves, move the first addend to the
2014 destination first. */
2016 gcc_assert (operands
[1] != const0_rtx
|| code
== MINUS
);
2017 if (!rtx_equal_p (operands
[0], operands
[1]) && operands
[1] != const0_rtx
)
2019 if (code
== MINUS
&& CONSTANT_P (operands
[1]))
2021 temp
= gen_reg_rtx (DImode
);
2022 emit_insn (gen_sbcdi3 (operands
[0], const0_rtx
, operands
[2]));
2024 gen_insn
= gen_adcdi3
;
2025 operands
[2] = operands
[1];
2026 operands
[1] = operands
[0];
2029 emit_move_insn (operands
[0], operands
[1]);
2032 /* Subtracting a constant will have been rewritten to an addition of the
2033 negative of that constant before we get here. */
2034 gcc_assert (!CONSTANT_P (operands
[2]) || code
== PLUS
);
2035 emit_insn ((*gen_insn
) (operands
[0], operands
[1], operands
[2]));
2040 adjacent_operands_p (rtx lo
, rtx hi
, machine_mode mode
)
2042 HOST_WIDE_INT lo_offset
;
2043 HOST_WIDE_INT hi_offset
;
2045 if (GET_CODE (lo
) != GET_CODE (hi
))
2049 return mode
== SImode
&& REGNO (lo
) + 1 == REGNO (hi
);
2050 if (CONST_INT_P (lo
))
2051 return INTVAL (hi
) == 0 && 0 <= INTVAL (lo
) && INTVAL (lo
) < 64;
2052 if (CONST_INT_P (lo
))
2053 return mode
!= SImode
;
2058 if (MEM_VOLATILE_P (lo
) || MEM_VOLATILE_P (hi
))
2064 if (GET_CODE (lo
) == POST_INC
/* || GET_CODE (lo) == PRE_DEC */)
2065 return rtx_equal_p (lo
, hi
);
2067 switch (GET_CODE (lo
))
2077 if (!CONST_INT_P (XEXP (lo
, 1)))
2079 lo_offset
= INTVAL (XEXP (lo
, 1));
2086 switch (GET_CODE (hi
))
2096 if (!CONST_INT_P (XEXP (hi
, 1)))
2098 hi_offset
= INTVAL (XEXP (hi
, 1));
2105 if (GET_CODE (lo
) == MULT
|| GET_CODE (lo
) == PLUS
)
2108 return rtx_equal_p (lo
, hi
)
2109 && hi_offset
- lo_offset
== GET_MODE_SIZE (mode
);
2112 /* Output assembler code for a block containing the constant parts
2113 of a trampoline, leaving space for the variable parts. */
2115 /* On the VAX, the trampoline contains an entry mask and two instructions:
2117 movl $STATIC,r0 (store the functions static chain)
2118 jmp *$FUNCTION (jump to function code at address FUNCTION) */
2121 vax_asm_trampoline_template (FILE *f ATTRIBUTE_UNUSED
)
2123 assemble_aligned_integer (2, const0_rtx
);
2124 assemble_aligned_integer (2, GEN_INT (0x8fd0));
2125 assemble_aligned_integer (4, const0_rtx
);
2126 assemble_aligned_integer (1, GEN_INT (0x50 + STATIC_CHAIN_REGNUM
));
2127 assemble_aligned_integer (2, GEN_INT (0x9f17));
2128 assemble_aligned_integer (4, const0_rtx
);
2131 /* We copy the register-mask from the function's pure code
2132 to the start of the trampoline. */
2135 vax_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
2137 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
2140 emit_block_move (m_tramp
, assemble_trampoline_template (),
2141 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
2143 mem
= adjust_address (m_tramp
, HImode
, 0);
2144 emit_move_insn (mem
, gen_const_mem (HImode
, fnaddr
));
2146 mem
= adjust_address (m_tramp
, SImode
, 4);
2147 emit_move_insn (mem
, cxt
);
2148 mem
= adjust_address (m_tramp
, SImode
, 11);
2149 emit_move_insn (mem
, plus_constant (Pmode
, fnaddr
, 2));
2150 emit_insn (gen_sync_istream ());
2153 /* Value is the number of bytes of arguments automatically
2154 popped when returning from a subroutine call.
2155 FUNDECL is the declaration node of the function (as a tree),
2156 FUNTYPE is the data type of the function (as a tree),
2157 or for a library call it is an identifier node for the subroutine name.
2158 SIZE is the number of bytes of arguments passed on the stack.
2160 On the VAX, the RET insn pops a maximum of 255 args for any function. */
2163 vax_return_pops_args (tree fundecl ATTRIBUTE_UNUSED
,
2164 tree funtype ATTRIBUTE_UNUSED
, int size
)
2166 return size
> 255 * 4 ? 0 : size
;
2169 /* Define where to put the arguments to a function.
2170 Value is zero to push the argument on the stack,
2171 or a hard register in which to store the argument.
2173 MODE is the argument's machine mode.
2174 TYPE is the data type of the argument (as a tree).
2175 This is null for libcalls where that information may
2177 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2178 the preceding args and about the function being called.
2179 NAMED is nonzero if this argument is a named parameter
2180 (otherwise it is an extra parameter matching an ellipsis). */
2182 /* On the VAX all args are pushed. */
2185 vax_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED
,
2186 machine_mode mode ATTRIBUTE_UNUSED
,
2187 const_tree type ATTRIBUTE_UNUSED
,
2188 bool named ATTRIBUTE_UNUSED
)
2193 /* Update the data in CUM to advance over an argument of mode MODE and
2194 data type TYPE. (TYPE is null for libcalls where that information
2195 may not be available.) */
2198 vax_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
2199 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2201 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2203 *cum
+= (mode
!= BLKmode
2204 ? (GET_MODE_SIZE (mode
) + 3) & ~3
2205 : (int_size_in_bytes (type
) + 3) & ~3);