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1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999-2015 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com) and
5 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 3, or (at your option) any later
12 ;; version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 ;; for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;
24 ;; See constraints.md for a description of constraints specific to s390.
25 ;;
27 ;; Special formats used for outputting 390 instructions.
28 ;;
29 ;; %C: print opcode suffix for branch condition.
30 ;; %D: print opcode suffix for inverse branch condition.
31 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
32 ;; %G: print the size of the operand in bytes.
33 ;; %O: print only the displacement of a memory reference.
34 ;; %R: print only the base register of a memory reference.
35 ;; %S: print S-type memory reference (base+displacement).
36 ;; %N: print the second word of a DImode operand.
37 ;; %M: print the second word of a TImode operand.
38 ;; %Y: print shift count operand.
39 ;;
40 ;; %b: print integer X as if it's an unsigned byte.
41 ;; %c: print integer X as if it's an signed byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
49 ;;
50 ;; We have a special constraint for pattern matching.
51 ;;
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
53 ;;
55 ;;
56 ;; UNSPEC usage
57 ;;
59 (define_c_enum "unspec" [
60 ; Miscellaneous
61 UNSPEC_ROUND
62 UNSPEC_ICM
63 UNSPEC_TIE
65 ; Convert CC into a str comparison result and copy it into an
66 ; integer register
67 ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
68 UNSPEC_STRCMPCC_TO_INT
70 ; Copy CC as is into the lower 2 bits of an integer register
71 UNSPEC_CC_TO_INT
73 ; GOT/PLT and lt-relative accesses
74 UNSPEC_LTREL_OFFSET
75 UNSPEC_LTREL_BASE
76 UNSPEC_POOL_OFFSET
77 UNSPEC_GOTENT
78 UNSPEC_GOT
79 UNSPEC_GOTOFF
80 UNSPEC_PLT
81 UNSPEC_PLTOFF
83 ; Literal pool
84 UNSPEC_RELOAD_BASE
85 UNSPEC_MAIN_BASE
86 UNSPEC_LTREF
87 UNSPEC_INSN
88 UNSPEC_EXECUTE
90 ; Atomic Support
91 UNSPEC_MB
92 UNSPEC_MOVA
94 ; TLS relocation specifiers
95 UNSPEC_TLSGD
96 UNSPEC_TLSLDM
97 UNSPEC_NTPOFF
98 UNSPEC_DTPOFF
99 UNSPEC_GOTNTPOFF
100 UNSPEC_INDNTPOFF
102 ; TLS support
103 UNSPEC_TLSLDM_NTPOFF
104 UNSPEC_TLS_LOAD
106 ; String Functions
107 UNSPEC_SRST
108 UNSPEC_MVST
110 ; Stack Smashing Protector
111 UNSPEC_SP_SET
112 UNSPEC_SP_TEST
114 ; Test Data Class (TDC)
115 UNSPEC_TDC_INSN
117 ; Population Count
118 UNSPEC_POPCNT
119 UNSPEC_COPYSIGN
121 ; Load FP Integer
122 UNSPEC_FPINT_FLOOR
123 UNSPEC_FPINT_BTRUNC
124 UNSPEC_FPINT_ROUND
125 UNSPEC_FPINT_CEIL
126 UNSPEC_FPINT_NEARBYINT
127 UNSPEC_FPINT_RINT
128 ])
130 ;;
131 ;; UNSPEC_VOLATILE usage
132 ;;
134 (define_c_enum "unspecv" [
135 ; Blockage
136 UNSPECV_BLOCKAGE
138 ; TPF Support
139 UNSPECV_TPF_PROLOGUE
140 UNSPECV_TPF_EPILOGUE
142 ; Literal pool
143 UNSPECV_POOL
144 UNSPECV_POOL_SECTION
145 UNSPECV_POOL_ALIGN
146 UNSPECV_POOL_ENTRY
147 UNSPECV_MAIN_POOL
149 ; TLS support
150 UNSPECV_SET_TP
152 ; Atomic Support
153 UNSPECV_CAS
154 UNSPECV_ATOMIC_OP
156 ; Hotpatching (unremovable NOPs)
157 UNSPECV_NOP_2_BYTE
158 UNSPECV_NOP_4_BYTE
159 UNSPECV_NOP_6_BYTE
161 ; Transactional Execution support
162 UNSPECV_TBEGIN
163 UNSPECV_TBEGIN_TDB
164 UNSPECV_TBEGINC
165 UNSPECV_TEND
166 UNSPECV_TABORT
167 UNSPECV_ETND
168 UNSPECV_NTSTG
169 UNSPECV_PPA
171 ; Set and get floating point control register
172 UNSPECV_SFPC
173 UNSPECV_EFPC
174 ])
176 ;;
177 ;; Registers
178 ;;
180 ; Registers with special meaning
182 (define_constants
183 [
184 ; Sibling call register.
185 (SIBCALL_REGNUM 1)
186 ; Literal pool base register.
187 (BASE_REGNUM 13)
188 ; Return address register.
189 (RETURN_REGNUM 14)
190 ; Condition code register.
191 (CC_REGNUM 33)
192 ; Thread local storage pointer register.
193 (TP_REGNUM 36)
194 ])
196 ; Hardware register names
198 (define_constants
199 [
200 ; General purpose registers
201 (GPR0_REGNUM 0)
202 ; Floating point registers.
203 (FPR0_REGNUM 16)
204 (FPR1_REGNUM 20)
205 (FPR2_REGNUM 17)
206 (FPR3_REGNUM 21)
207 (FPR4_REGNUM 18)
208 (FPR5_REGNUM 22)
209 (FPR6_REGNUM 19)
210 (FPR7_REGNUM 23)
211 (FPR8_REGNUM 24)
212 (FPR9_REGNUM 28)
213 (FPR10_REGNUM 25)
214 (FPR11_REGNUM 29)
215 (FPR12_REGNUM 26)
216 (FPR13_REGNUM 30)
217 (FPR14_REGNUM 27)
218 (FPR15_REGNUM 31)
219 ])
221 ;;
222 ;; PFPO GPR0 argument format
223 ;;
225 (define_constants
226 [
227 ; PFPO operation type
228 (PFPO_CONVERT 0x1000000)
229 ; PFPO operand types
230 (PFPO_OP_TYPE_SF 0x5)
231 (PFPO_OP_TYPE_DF 0x6)
232 (PFPO_OP_TYPE_TF 0x7)
233 (PFPO_OP_TYPE_SD 0x8)
234 (PFPO_OP_TYPE_DD 0x9)
235 (PFPO_OP_TYPE_TD 0xa)
236 ; Bitposition of operand types
237 (PFPO_OP0_TYPE_SHIFT 16)
238 (PFPO_OP1_TYPE_SHIFT 8)
239 ])
241 ; Immediate operands for tbegin and tbeginc
242 (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c
243 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
245 ;; Instruction operand type as used in the Principles of Operation.
246 ;; Used to determine defaults for length and other attribute values.
248 (define_attr "op_type"
249 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
250 (const_string "NN"))
252 ;; Instruction type attribute used for scheduling.
254 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
255 cs,vs,store,sem,idiv,
256 imulhi,imulsi,imuldi,
257 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
258 floadtf,floaddf,floadsf,fstoredf,fstoresf,
259 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
260 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
261 fmadddf,fmaddsf,
262 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
263 itoftf, itofdf, itofsf, itofdd, itoftd,
264 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
265 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
266 ftoidfp, other"
267 (cond [(eq_attr "op_type" "NN") (const_string "other")
268 (eq_attr "op_type" "SS") (const_string "cs")]
269 (const_string "integer")))
271 ;; Another attribute used for scheduling purposes:
272 ;; agen: Instruction uses the address generation unit
273 ;; reg: Instruction does not use the agen unit
275 (define_attr "atype" "agen,reg"
276 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
277 (const_string "reg")
278 (const_string "agen")))
280 ;; Properties concerning Z10 execution grouping and value forwarding.
281 ;; z10_super: instruction is superscalar.
282 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
283 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
284 ;; target register. It can forward this value to a second instruction that reads
285 ;; the same register if that second instruction is issued in the same group.
286 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
287 ;; instruction in the S pipe writes to the register, then the T instruction
288 ;; can immediately read the new value.
289 ;; z10_fr: union of Z10_fwd and z10_rec.
290 ;; z10_c: second operand of instruction is a register and read with complemented bits.
291 ;;
292 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
295 (define_attr "z10prop" "none,
296 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
297 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
298 z10_rec,
299 z10_fr, z10_fr_A3, z10_fr_E1,
300 z10_c"
301 (const_string "none"))
303 ;; Properties concerning Z196 decoding
304 ;; z196_alone: must group alone
305 ;; z196_end: ends a group
306 ;; z196_cracked: instruction is cracked or expanded
307 (define_attr "z196prop" "none,
308 z196_alone, z196_ends,
309 z196_cracked"
310 (const_string "none"))
312 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
314 ;; Length in bytes.
316 (define_attr "length" ""
317 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
318 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
319 (const_int 6)))
322 ;; Processor type. This attribute must exactly match the processor_type
323 ;; enumeration in s390.h. The current machine description does not
324 ;; distinguish between g5 and g6, but there are differences between the two
325 ;; CPUs could in theory be modeled.
327 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12"
328 (const (symbol_ref "s390_tune_attr")))
330 (define_attr "cpu_facility"
331 "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12"
332 (const_string "standard"))
334 (define_attr "enabled" ""
335 (cond [(eq_attr "cpu_facility" "standard")
336 (const_int 1)
338 (and (eq_attr "cpu_facility" "ieee")
339 (match_test "TARGET_CPU_IEEE_FLOAT"))
340 (const_int 1)
342 (and (eq_attr "cpu_facility" "zarch")
343 (match_test "TARGET_ZARCH"))
344 (const_int 1)
346 (and (eq_attr "cpu_facility" "longdisp")
347 (match_test "TARGET_LONG_DISPLACEMENT"))
348 (const_int 1)
350 (and (eq_attr "cpu_facility" "extimm")
351 (match_test "TARGET_EXTIMM"))
352 (const_int 1)
354 (and (eq_attr "cpu_facility" "dfp")
355 (match_test "TARGET_DFP"))
356 (const_int 1)
358 (and (eq_attr "cpu_facility" "cpu_zarch")
359 (match_test "TARGET_CPU_ZARCH"))
360 (const_int 1)
362 (and (eq_attr "cpu_facility" "z10")
363 (match_test "TARGET_Z10"))
364 (const_int 1)
366 (and (eq_attr "cpu_facility" "z196")
367 (match_test "TARGET_Z196"))
368 (const_int 1)
370 (and (eq_attr "cpu_facility" "zEC12")
371 (match_test "TARGET_ZEC12"))
372 (const_int 1)]
373 (const_int 0)))
375 ;; Pipeline description for z900. For lack of anything better,
376 ;; this description is also used for the g5 and g6.
377 (include "2064.md")
379 ;; Pipeline description for z990, z9-109 and z9-ec.
380 (include "2084.md")
382 ;; Pipeline description for z10
383 (include "2097.md")
385 ;; Pipeline description for z196
386 (include "2817.md")
388 ;; Pipeline description for zEC12
389 (include "2827.md")
391 ;; Predicates
392 (include "predicates.md")
394 ;; Constraint definitions
395 (include "constraints.md")
397 ;; Other includes
398 (include "tpf.md")
400 ;; Iterators
402 ;; These mode iterators allow floating point patterns to be generated from the
403 ;; same template.
404 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
405 (SD "TARGET_HARD_DFP")])
406 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
407 (define_mode_iterator FPALL [TF DF SF TD DD SD])
408 (define_mode_iterator BFP [TF DF SF])
409 (define_mode_iterator DFP [TD DD])
410 (define_mode_iterator DFP_ALL [TD DD SD])
411 (define_mode_iterator DSF [DF SF])
412 (define_mode_iterator SD_SF [SF SD])
413 (define_mode_iterator DD_DF [DF DD])
414 (define_mode_iterator TD_TF [TF TD])
416 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
417 ;; from the same template.
418 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
419 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
420 (define_mode_iterator DSI [DI SI])
421 (define_mode_iterator TDI [TI DI])
423 ;; These mode iterators allow :P to be used for patterns that operate on
424 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
425 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
427 ;; These macros refer to the actual word_mode of the configuration.
428 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
429 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
430 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
432 ;; Used by the umul pattern to express modes having half the size.
433 (define_mode_attr DWH [(TI "DI") (DI "SI")])
434 (define_mode_attr dwh [(TI "di") (DI "si")])
436 ;; This mode iterator allows the QI and HI patterns to be defined from
437 ;; the same template.
438 (define_mode_iterator HQI [HI QI])
440 ;; This mode iterator allows the integer patterns to be defined from the
441 ;; same template.
442 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
443 (define_mode_iterator INTALL [TI DI SI HI QI])
444 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
446 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
447 ;; the same template.
448 (define_code_iterator SHIFT [ashift lshiftrt])
450 ;; This iterator allows r[ox]sbg to be defined with the same template
451 (define_code_iterator IXOR [ior xor])
453 ;; This iterator is used to expand the patterns for the nearest
454 ;; integer functions.
455 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
456 UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
457 UNSPEC_FPINT_NEARBYINT])
458 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
459 (UNSPEC_FPINT_BTRUNC "btrunc")
460 (UNSPEC_FPINT_ROUND "round")
461 (UNSPEC_FPINT_CEIL "ceil")
462 (UNSPEC_FPINT_NEARBYINT "nearbyint")])
463 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
464 (UNSPEC_FPINT_BTRUNC "5")
465 (UNSPEC_FPINT_ROUND "1")
466 (UNSPEC_FPINT_CEIL "6")
467 (UNSPEC_FPINT_NEARBYINT "0")])
469 ;; This iterator and attribute allow to combine most atomic operations.
470 (define_code_iterator ATOMIC [and ior xor plus minus mult])
471 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
472 (define_code_attr atomic [(and "and") (ior "or") (xor "xor")
473 (plus "add") (minus "sub") (mult "nand")])
474 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
476 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
477 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
478 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
480 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
481 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
482 ;; SDmode.
483 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
485 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
486 ;; Likewise for "<RXe>".
487 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
488 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
490 ;; The decimal floating point variants of add, sub, div and mul support 3
491 ;; fp register operands. The following attributes allow to merge the bfp and
492 ;; dfp variants in a single insn definition.
494 ;; This attribute is used to set op_type accordingly.
495 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
496 (DD "RRR") (SD "RRR")])
498 ;; This attribute is used in the operand constraint list in order to have the
499 ;; first and the second operand match for bfp modes.
500 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
502 ;; This attribute is used in the operand list of the instruction to have an
503 ;; additional operand for the dfp instructions.
504 (define_mode_attr op1 [(TF "") (DF "") (SF "")
505 (TD "%1,") (DD "%1,") (SD "%1,")])
508 ;; This attribute is used in the operand constraint list
509 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
510 ;; TFmode values are represented by a fp register pair. Since the
511 ;; sign bit instructions only handle single source and target fp registers
512 ;; these instructions can only be used for TFmode values if the source and
513 ;; target operand uses the same fp register.
514 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
516 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
517 ;; This is used to disable the memory alternative in TFmode patterns.
518 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
520 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
521 ;; within instruction mnemonics.
522 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
524 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
525 ;; modes and to an empty string for bfp modes.
526 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
528 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
529 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
530 ;; version only operates on one register.
531 (define_mode_attr d0 [(DI "d") (SI "0")])
533 ;; In combination with d0 this allows to combine instructions of which the 31bit
534 ;; version only operates on one register. The DImode version needs an additional
535 ;; register for the assembler output.
536 (define_mode_attr 1 [(DI "%1,") (SI "")])
538 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
539 ;; 'ashift' and "srdl" in 'lshiftrt'.
540 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
542 ;; In SHIFT templates, this attribute holds the correct standard name for the
543 ;; pattern itself and the corresponding function calls.
544 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
546 ;; This attribute handles differences in the instruction 'type' and will result
547 ;; in "RRE" for DImode and "RR" for SImode.
548 (define_mode_attr E [(DI "E") (SI "")])
550 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
551 ;; to result in "RXY" for DImode and "RX" for SImode.
552 (define_mode_attr Y [(DI "Y") (SI "")])
554 ;; This attribute handles differences in the instruction 'type' and will result
555 ;; in "RSE" for TImode and "RS" for DImode.
556 (define_mode_attr TE [(TI "E") (DI "")])
558 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
559 ;; and "lcr" in SImode.
560 (define_mode_attr g [(DI "g") (SI "")])
562 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
563 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
564 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
565 ;; variant for long displacements.
566 (define_mode_attr y [(DI "g") (SI "y")])
568 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
569 ;; and "cds" in DImode.
570 (define_mode_attr tg [(TI "g") (DI "")])
572 ;; In TDI templates, a string like "c<d>sg".
573 (define_mode_attr td [(TI "d") (DI "")])
575 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
576 ;; and "cfdbr" in SImode.
577 (define_mode_attr gf [(DI "g") (SI "f")])
579 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
580 ;; and sllk for SI. This way it is possible to merge the new z196 SI
581 ;; 3 operands shift instructions into the existing patterns.
582 (define_mode_attr gk [(DI "g") (SI "k")])
584 ;; ICM mask required to load MODE value into the lowest subreg
585 ;; of a SImode register.
586 (define_mode_attr icm_lo [(HI "3") (QI "1")])
588 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
589 ;; HImode and "llgc" in QImode.
590 (define_mode_attr hc [(HI "h") (QI "c")])
592 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
593 ;; in SImode.
594 (define_mode_attr DBL [(DI "TI") (SI "DI")])
596 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
597 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
598 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
600 ;; Maximum unsigned integer that fits in MODE.
601 (define_mode_attr max_uint [(HI "65535") (QI "255")])
603 ;; Start and end field computations for RISBG et al.
604 (define_mode_attr bfstart [(DI "s") (SI "t")])
605 (define_mode_attr bfend [(DI "e") (SI "f")])
607 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
608 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
610 ;; Allow return and simple_return to be defined from a single template.
611 (define_code_iterator ANY_RETURN [return simple_return])
613 ;;
614 ;;- Compare instructions.
615 ;;
617 ; Test-under-Mask instructions
619 (define_insn "*tmqi_mem"
620 [(set (reg CC_REGNUM)
621 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
622 (match_operand:QI 1 "immediate_operand" "n,n"))
623 (match_operand:QI 2 "immediate_operand" "n,n")))]
624 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
625 "@
626 tm\t%S0,%b1
627 tmy\t%S0,%b1"
628 [(set_attr "op_type" "SI,SIY")
629 (set_attr "z10prop" "z10_super,z10_super")])
631 (define_insn "*tmdi_reg"
632 [(set (reg CC_REGNUM)
633 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
634 (match_operand:DI 1 "immediate_operand"
635 "N0HD0,N1HD0,N2HD0,N3HD0"))
636 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
637 "TARGET_ZARCH
638 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
639 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
640 "@
641 tmhh\t%0,%i1
642 tmhl\t%0,%i1
643 tmlh\t%0,%i1
644 tmll\t%0,%i1"
645 [(set_attr "op_type" "RI")
646 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
648 (define_insn "*tmsi_reg"
649 [(set (reg CC_REGNUM)
650 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
651 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
652 (match_operand:SI 2 "immediate_operand" "n,n")))]
653 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
654 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
655 "@
656 tmh\t%0,%i1
657 tml\t%0,%i1"
658 [(set_attr "op_type" "RI")
659 (set_attr "z10prop" "z10_super,z10_super")])
661 (define_insn "*tm<mode>_full"
662 [(set (reg CC_REGNUM)
663 (compare (match_operand:HQI 0 "register_operand" "d")
664 (match_operand:HQI 1 "immediate_operand" "n")))]
665 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
666 "tml\t%0,<max_uint>"
667 [(set_attr "op_type" "RI")
668 (set_attr "z10prop" "z10_super")])
671 ;
672 ; Load-and-Test instructions
673 ;
675 ; tst(di|si) instruction pattern(s).
677 (define_insn "*tstdi_sign"
678 [(set (reg CC_REGNUM)
679 (compare
680 (ashiftrt:DI
681 (ashift:DI
682 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
683 (const_int 32)) (const_int 32))
684 (match_operand:DI 1 "const0_operand" "")))
685 (set (match_operand:DI 2 "register_operand" "=d,d")
686 (sign_extend:DI (match_dup 0)))]
687 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
688 "ltgfr\t%2,%0
689 ltgf\t%2,%0"
690 [(set_attr "op_type" "RRE,RXY")
691 (set_attr "cpu_facility" "*,z10")
692 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
694 ; ltr, lt, ltgr, ltg
695 (define_insn "*tst<mode>_extimm"
696 [(set (reg CC_REGNUM)
697 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
698 (match_operand:GPR 1 "const0_operand" "")))
699 (set (match_operand:GPR 2 "register_operand" "=d,d")
700 (match_dup 0))]
701 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
702 "@
703 lt<g>r\t%2,%0
704 lt<g>\t%2,%0"
705 [(set_attr "op_type" "RR<E>,RXY")
706 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
708 ; ltr, lt, ltgr, ltg
709 (define_insn "*tst<mode>_cconly_extimm"
710 [(set (reg CC_REGNUM)
711 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
712 (match_operand:GPR 1 "const0_operand" "")))
713 (clobber (match_scratch:GPR 2 "=X,d"))]
714 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
715 "@
716 lt<g>r\t%0,%0
717 lt<g>\t%2,%0"
718 [(set_attr "op_type" "RR<E>,RXY")
719 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
721 (define_insn "*tstdi"
722 [(set (reg CC_REGNUM)
723 (compare (match_operand:DI 0 "register_operand" "d")
724 (match_operand:DI 1 "const0_operand" "")))
725 (set (match_operand:DI 2 "register_operand" "=d")
726 (match_dup 0))]
727 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
728 "ltgr\t%2,%0"
729 [(set_attr "op_type" "RRE")
730 (set_attr "z10prop" "z10_fr_E1")])
732 (define_insn "*tstsi"
733 [(set (reg CC_REGNUM)
734 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
735 (match_operand:SI 1 "const0_operand" "")))
736 (set (match_operand:SI 2 "register_operand" "=d,d,d")
737 (match_dup 0))]
738 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
739 "@
740 ltr\t%2,%0
741 icm\t%2,15,%S0
742 icmy\t%2,15,%S0"
743 [(set_attr "op_type" "RR,RS,RSY")
744 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
746 (define_insn "*tstsi_cconly"
747 [(set (reg CC_REGNUM)
748 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
749 (match_operand:SI 1 "const0_operand" "")))
750 (clobber (match_scratch:SI 2 "=X,d,d"))]
751 "s390_match_ccmode(insn, CCSmode)"
752 "@
753 ltr\t%0,%0
754 icm\t%2,15,%S0
755 icmy\t%2,15,%S0"
756 [(set_attr "op_type" "RR,RS,RSY")
757 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
759 (define_insn "*tstdi_cconly_31"
760 [(set (reg CC_REGNUM)
761 (compare (match_operand:DI 0 "register_operand" "d")
762 (match_operand:DI 1 "const0_operand" "")))]
763 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
764 "srda\t%0,0"
765 [(set_attr "op_type" "RS")
766 (set_attr "atype" "reg")])
768 ; ltr, ltgr
769 (define_insn "*tst<mode>_cconly2"
770 [(set (reg CC_REGNUM)
771 (compare (match_operand:GPR 0 "register_operand" "d")
772 (match_operand:GPR 1 "const0_operand" "")))]
773 "s390_match_ccmode(insn, CCSmode)"
774 "lt<g>r\t%0,%0"
775 [(set_attr "op_type" "RR<E>")
776 (set_attr "z10prop" "z10_fr_E1")])
778 ; tst(hi|qi) instruction pattern(s).
780 (define_insn "*tst<mode>CCT"
781 [(set (reg CC_REGNUM)
782 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
783 (match_operand:HQI 1 "const0_operand" "")))
784 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
785 (match_dup 0))]
786 "s390_match_ccmode(insn, CCTmode)"
787 "@
788 icm\t%2,<icm_lo>,%S0
789 icmy\t%2,<icm_lo>,%S0
790 tml\t%0,<max_uint>"
791 [(set_attr "op_type" "RS,RSY,RI")
792 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
794 (define_insn "*tsthiCCT_cconly"
795 [(set (reg CC_REGNUM)
796 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
797 (match_operand:HI 1 "const0_operand" "")))
798 (clobber (match_scratch:HI 2 "=d,d,X"))]
799 "s390_match_ccmode(insn, CCTmode)"
800 "@
801 icm\t%2,3,%S0
802 icmy\t%2,3,%S0
803 tml\t%0,65535"
804 [(set_attr "op_type" "RS,RSY,RI")
805 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
807 (define_insn "*tstqiCCT_cconly"
808 [(set (reg CC_REGNUM)
809 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
810 (match_operand:QI 1 "const0_operand" "")))]
811 "s390_match_ccmode(insn, CCTmode)"
812 "@
813 cli\t%S0,0
814 cliy\t%S0,0
815 tml\t%0,255"
816 [(set_attr "op_type" "SI,SIY,RI")
817 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
819 (define_insn "*tst<mode>"
820 [(set (reg CC_REGNUM)
821 (compare (match_operand:HQI 0 "s_operand" "Q,S")
822 (match_operand:HQI 1 "const0_operand" "")))
823 (set (match_operand:HQI 2 "register_operand" "=d,d")
824 (match_dup 0))]
825 "s390_match_ccmode(insn, CCSmode)"
826 "@
827 icm\t%2,<icm_lo>,%S0
828 icmy\t%2,<icm_lo>,%S0"
829 [(set_attr "op_type" "RS,RSY")
830 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
832 (define_insn "*tst<mode>_cconly"
833 [(set (reg CC_REGNUM)
834 (compare (match_operand:HQI 0 "s_operand" "Q,S")
835 (match_operand:HQI 1 "const0_operand" "")))
836 (clobber (match_scratch:HQI 2 "=d,d"))]
837 "s390_match_ccmode(insn, CCSmode)"
838 "@
839 icm\t%2,<icm_lo>,%S0
840 icmy\t%2,<icm_lo>,%S0"
841 [(set_attr "op_type" "RS,RSY")
842 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
845 ; Compare (equality) instructions
847 (define_insn "*cmpdi_cct"
848 [(set (reg CC_REGNUM)
849 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
850 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
851 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
852 "@
853 cgr\t%0,%1
854 cghi\t%0,%h1
855 cgfi\t%0,%1
856 cg\t%0,%1
857 #"
858 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
859 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
861 (define_insn "*cmpsi_cct"
862 [(set (reg CC_REGNUM)
863 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
864 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
865 "s390_match_ccmode (insn, CCTmode)"
866 "@
867 cr\t%0,%1
868 chi\t%0,%h1
869 cfi\t%0,%1
870 c\t%0,%1
871 cy\t%0,%1
872 #"
873 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
874 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
876 ; Compare (signed) instructions
878 (define_insn "*cmpdi_ccs_sign"
879 [(set (reg CC_REGNUM)
880 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
881 "d,RT,b"))
882 (match_operand:DI 0 "register_operand" "d, d,d")))]
883 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
884 "@
885 cgfr\t%0,%1
886 cgf\t%0,%1
887 cgfrl\t%0,%1"
888 [(set_attr "op_type" "RRE,RXY,RIL")
889 (set_attr "z10prop" "z10_c,*,*")
890 (set_attr "type" "*,*,larl")])
894 (define_insn "*cmpsi_ccs_sign"
895 [(set (reg CC_REGNUM)
896 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
897 (match_operand:SI 0 "register_operand" "d,d,d")))]
898 "s390_match_ccmode(insn, CCSRmode)"
899 "@
900 ch\t%0,%1
901 chy\t%0,%1
902 chrl\t%0,%1"
903 [(set_attr "op_type" "RX,RXY,RIL")
904 (set_attr "cpu_facility" "*,*,z10")
905 (set_attr "type" "*,*,larl")
906 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
908 (define_insn "*cmphi_ccs_z10"
909 [(set (reg CC_REGNUM)
910 (compare (match_operand:HI 0 "s_operand" "Q")
911 (match_operand:HI 1 "immediate_operand" "K")))]
912 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
913 "chhsi\t%0,%1"
914 [(set_attr "op_type" "SIL")
915 (set_attr "z196prop" "z196_cracked")])
917 (define_insn "*cmpdi_ccs_signhi_rl"
918 [(set (reg CC_REGNUM)
919 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
920 (match_operand:GPR 0 "register_operand" "d,d")))]
921 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
922 "@
923 cgh\t%0,%1
924 cghrl\t%0,%1"
925 [(set_attr "op_type" "RXY,RIL")
926 (set_attr "type" "*,larl")])
928 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
929 (define_insn "*cmp<mode>_ccs"
930 [(set (reg CC_REGNUM)
931 (compare (match_operand:GPR 0 "nonimmediate_operand"
932 "d,d,Q, d,d,d,d")
933 (match_operand:GPR 1 "general_operand"
934 "d,K,K,Os,R,T,b")))]
935 "s390_match_ccmode(insn, CCSmode)"
936 "@
937 c<g>r\t%0,%1
938 c<g>hi\t%0,%h1
939 c<g>hsi\t%0,%h1
940 c<g>fi\t%0,%1
941 c<g>\t%0,%1
942 c<y>\t%0,%1
943 c<g>rl\t%0,%1"
944 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
945 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
946 (set_attr "type" "*,*,*,*,*,*,larl")
947 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
950 ; Compare (unsigned) instructions
952 (define_insn "*cmpsi_ccu_zerohi_rlsi"
953 [(set (reg CC_REGNUM)
954 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
955 "larl_operand" "X")))
956 (match_operand:SI 0 "register_operand" "d")))]
957 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
958 "clhrl\t%0,%1"
959 [(set_attr "op_type" "RIL")
960 (set_attr "type" "larl")
961 (set_attr "z10prop" "z10_super")])
963 ; clhrl, clghrl
964 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
965 [(set (reg CC_REGNUM)
966 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
967 "larl_operand" "X")))
968 (match_operand:GPR 0 "register_operand" "d")))]
969 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
970 "cl<g>hrl\t%0,%1"
971 [(set_attr "op_type" "RIL")
972 (set_attr "type" "larl")
973 (set_attr "z10prop" "z10_super")])
975 (define_insn "*cmpdi_ccu_zero"
976 [(set (reg CC_REGNUM)
977 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
978 "d,RT,b"))
979 (match_operand:DI 0 "register_operand" "d, d,d")))]
980 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
981 "@
982 clgfr\t%0,%1
983 clgf\t%0,%1
984 clgfrl\t%0,%1"
985 [(set_attr "op_type" "RRE,RXY,RIL")
986 (set_attr "cpu_facility" "*,*,z10")
987 (set_attr "type" "*,*,larl")
988 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
990 (define_insn "*cmpdi_ccu"
991 [(set (reg CC_REGNUM)
992 (compare (match_operand:DI 0 "nonimmediate_operand"
993 "d, d,d,Q, d, Q,BQ")
994 (match_operand:DI 1 "general_operand"
995 "d,Op,b,D,RT,BQ,Q")))]
996 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
997 "@
998 clgr\t%0,%1
999 clgfi\t%0,%1
1000 clgrl\t%0,%1
1001 clghsi\t%0,%x1
1002 clg\t%0,%1
1003 #
1004 #"
1005 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
1006 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
1007 (set_attr "type" "*,*,larl,*,*,*,*")
1008 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
1010 (define_insn "*cmpsi_ccu"
1011 [(set (reg CC_REGNUM)
1012 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1013 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
1014 "s390_match_ccmode (insn, CCUmode)"
1015 "@
1016 clr\t%0,%1
1017 clfi\t%0,%o1
1018 clrl\t%0,%1
1019 clfhsi\t%0,%x1
1020 cl\t%0,%1
1021 cly\t%0,%1
1022 #
1023 #"
1024 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1025 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
1026 (set_attr "type" "*,*,larl,*,*,*,*,*")
1027 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1029 (define_insn "*cmphi_ccu"
1030 [(set (reg CC_REGNUM)
1031 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1032 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
1033 "s390_match_ccmode (insn, CCUmode)
1034 && !register_operand (operands[1], HImode)"
1035 "@
1036 clm\t%0,3,%S1
1037 clmy\t%0,3,%S1
1038 clhhsi\t%0,%1
1039 #
1040 #"
1041 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1042 (set_attr "cpu_facility" "*,*,z10,*,*")
1043 (set_attr "z10prop" "*,*,z10_super,*,*")])
1045 (define_insn "*cmpqi_ccu"
1046 [(set (reg CC_REGNUM)
1047 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1048 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1049 "s390_match_ccmode (insn, CCUmode)
1050 && !register_operand (operands[1], QImode)"
1051 "@
1052 clm\t%0,1,%S1
1053 clmy\t%0,1,%S1
1054 cli\t%S0,%b1
1055 cliy\t%S0,%b1
1056 #
1057 #"
1058 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1059 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1062 ; Block compare (CLC) instruction patterns.
1064 (define_insn "*clc"
1065 [(set (reg CC_REGNUM)
1066 (compare (match_operand:BLK 0 "memory_operand" "Q")
1067 (match_operand:BLK 1 "memory_operand" "Q")))
1068 (use (match_operand 2 "const_int_operand" "n"))]
1069 "s390_match_ccmode (insn, CCUmode)
1070 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1071 "clc\t%O0(%2,%R0),%S1"
1072 [(set_attr "op_type" "SS")])
1074 (define_split
1075 [(set (reg CC_REGNUM)
1076 (compare (match_operand 0 "memory_operand" "")
1077 (match_operand 1 "memory_operand" "")))]
1078 "reload_completed
1079 && s390_match_ccmode (insn, CCUmode)
1080 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1081 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1082 [(parallel
1083 [(set (match_dup 0) (match_dup 1))
1084 (use (match_dup 2))])]
1085 {
1086 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1087 operands[0] = adjust_address (operands[0], BLKmode, 0);
1088 operands[1] = adjust_address (operands[1], BLKmode, 0);
1090 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1091 operands[0], operands[1]);
1092 operands[0] = SET_DEST (PATTERN (curr_insn));
1093 })
1096 ; (TF|DF|SF|TD|DD|SD) instructions
1098 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1099 (define_insn "*cmp<mode>_ccs_0"
1100 [(set (reg CC_REGNUM)
1101 (compare (match_operand:FP 0 "register_operand" "f")
1102 (match_operand:FP 1 "const0_operand" "")))]
1103 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1104 "lt<xde><bt>r\t%0,%0"
1105 [(set_attr "op_type" "RRE")
1106 (set_attr "type" "fsimp<mode>")])
1108 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1109 (define_insn "*cmp<mode>_ccs"
1110 [(set (reg CC_REGNUM)
1111 (compare (match_operand:FP 0 "register_operand" "f,f")
1112 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1113 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1114 "@
1115 c<xde><bt>r\t%0,%1
1116 c<xde>b\t%0,%1"
1117 [(set_attr "op_type" "RRE,RXE")
1118 (set_attr "type" "fsimp<mode>")])
1121 ; Compare and Branch instructions
1123 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1124 ; The following instructions do a complementary access of their second
1125 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1126 (define_insn "*cmp_and_br_signed_<mode>"
1127 [(set (pc)
1128 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1129 [(match_operand:GPR 1 "register_operand" "d,d")
1130 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1131 (label_ref (match_operand 3 "" ""))
1132 (pc)))
1133 (clobber (reg:CC CC_REGNUM))]
1134 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1135 {
1136 if (get_attr_length (insn) == 6)
1137 return which_alternative ?
1138 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1139 else
1140 return which_alternative ?
1141 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1142 }
1143 [(set_attr "op_type" "RIE")
1144 (set_attr "type" "branch")
1145 (set_attr "z10prop" "z10_super_c,z10_super")
1146 (set (attr "length")
1147 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1148 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1149 ; 10 byte for cgr/jg
1151 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1152 ; The following instructions do a complementary access of their second
1153 ; operand (z10 only): clrj, clgrj, clr, clgr
1154 (define_insn "*cmp_and_br_unsigned_<mode>"
1155 [(set (pc)
1156 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1157 [(match_operand:GPR 1 "register_operand" "d,d")
1158 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1159 (label_ref (match_operand 3 "" ""))
1160 (pc)))
1161 (clobber (reg:CC CC_REGNUM))]
1162 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1163 {
1164 if (get_attr_length (insn) == 6)
1165 return which_alternative ?
1166 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1167 else
1168 return which_alternative ?
1169 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1170 }
1171 [(set_attr "op_type" "RIE")
1172 (set_attr "type" "branch")
1173 (set_attr "z10prop" "z10_super_c,z10_super")
1174 (set (attr "length")
1175 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1176 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1177 ; 10 byte for clgr/jg
1179 ; And now the same two patterns as above but with a negated CC mask.
1181 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1182 ; The following instructions do a complementary access of their second
1183 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1184 (define_insn "*icmp_and_br_signed_<mode>"
1185 [(set (pc)
1186 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1187 [(match_operand:GPR 1 "register_operand" "d,d")
1188 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1189 (pc)
1190 (label_ref (match_operand 3 "" ""))))
1191 (clobber (reg:CC CC_REGNUM))]
1192 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1193 {
1194 if (get_attr_length (insn) == 6)
1195 return which_alternative ?
1196 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1197 else
1198 return which_alternative ?
1199 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1200 }
1201 [(set_attr "op_type" "RIE")
1202 (set_attr "type" "branch")
1203 (set_attr "z10prop" "z10_super_c,z10_super")
1204 (set (attr "length")
1205 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1206 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1207 ; 10 byte for cgr/jg
1209 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1210 ; The following instructions do a complementary access of their second
1211 ; operand (z10 only): clrj, clgrj, clr, clgr
1212 (define_insn "*icmp_and_br_unsigned_<mode>"
1213 [(set (pc)
1214 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1215 [(match_operand:GPR 1 "register_operand" "d,d")
1216 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1217 (pc)
1218 (label_ref (match_operand 3 "" ""))))
1219 (clobber (reg:CC CC_REGNUM))]
1220 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1221 {
1222 if (get_attr_length (insn) == 6)
1223 return which_alternative ?
1224 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1225 else
1226 return which_alternative ?
1227 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1228 }
1229 [(set_attr "op_type" "RIE")
1230 (set_attr "type" "branch")
1231 (set_attr "z10prop" "z10_super_c,z10_super")
1232 (set (attr "length")
1233 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1234 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1235 ; 10 byte for clgr/jg
1237 ;;
1238 ;;- Move instructions.
1239 ;;
1241 ;
1242 ; movti instruction pattern(s).
1243 ;
1245 (define_insn "movti"
1246 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1247 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1248 "TARGET_ZARCH"
1249 "@
1250 lmg\t%0,%N0,%S1
1251 stmg\t%1,%N1,%S0
1252 #
1253 #"
1254 [(set_attr "op_type" "RSY,RSY,*,*")
1255 (set_attr "type" "lm,stm,*,*")])
1257 (define_split
1258 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1259 (match_operand:TI 1 "general_operand" ""))]
1260 "TARGET_ZARCH && reload_completed
1261 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1262 [(set (match_dup 2) (match_dup 4))
1263 (set (match_dup 3) (match_dup 5))]
1264 {
1265 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1266 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1267 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1268 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1269 })
1271 (define_split
1272 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1273 (match_operand:TI 1 "general_operand" ""))]
1274 "TARGET_ZARCH && reload_completed
1275 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1276 [(set (match_dup 2) (match_dup 4))
1277 (set (match_dup 3) (match_dup 5))]
1278 {
1279 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1280 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1281 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1282 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1283 })
1285 (define_split
1286 [(set (match_operand:TI 0 "register_operand" "")
1287 (match_operand:TI 1 "memory_operand" ""))]
1288 "TARGET_ZARCH && reload_completed
1289 && !s_operand (operands[1], VOIDmode)"
1290 [(set (match_dup 0) (match_dup 1))]
1291 {
1292 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1293 addr = gen_lowpart (Pmode, addr);
1294 s390_load_address (addr, XEXP (operands[1], 0));
1295 operands[1] = replace_equiv_address (operands[1], addr);
1296 })
1299 ;
1300 ; Patterns used for secondary reloads
1301 ;
1303 ; z10 provides move instructions accepting larl memory operands.
1304 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1305 ; These patterns are also used for unaligned SI and DI accesses.
1307 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1308 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1309 (match_operand:INTALL 1 "register_operand" "=d")
1310 (match_operand:P 2 "register_operand" "=&a")])]
1311 "TARGET_Z10"
1312 {
1313 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1314 DONE;
1315 })
1317 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1318 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1319 (match_operand:INTALL 1 "memory_operand" "")
1320 (match_operand:P 2 "register_operand" "=a")])]
1321 "TARGET_Z10"
1322 {
1323 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1324 DONE;
1325 })
1327 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1328 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1329 (match_operand:FPALL 1 "register_operand" "=d")
1330 (match_operand:P 2 "register_operand" "=&a")])]
1331 "TARGET_Z10"
1332 {
1333 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1334 DONE;
1335 })
1337 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1338 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1339 (match_operand:FPALL 1 "memory_operand" "")
1340 (match_operand:P 2 "register_operand" "=a")])]
1341 "TARGET_Z10"
1342 {
1343 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1344 DONE;
1345 })
1347 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1348 [(parallel [(match_operand:P 0 "register_operand" "=d")
1349 (match_operand:P 1 "larl_operand" "")
1350 (match_operand:P 2 "register_operand" "=a")])]
1351 "TARGET_Z10"
1352 {
1353 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1354 DONE;
1355 })
1357 ; Handles loading a PLUS (load address) expression
1359 (define_expand "reload<mode>_plus"
1360 [(parallel [(match_operand:P 0 "register_operand" "=a")
1361 (match_operand:P 1 "s390_plus_operand" "")
1362 (match_operand:P 2 "register_operand" "=&a")])]
1363 ""
1364 {
1365 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1366 DONE;
1367 })
1369 ; Handles assessing a non-offsetable memory address
1371 (define_expand "reload<mode>_nonoffmem_in"
1372 [(parallel [(match_operand 0 "register_operand" "")
1373 (match_operand 1 "" "")
1374 (match_operand:P 2 "register_operand" "=&a")])]
1375 ""
1376 {
1377 gcc_assert (MEM_P (operands[1]));
1378 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1379 operands[1] = replace_equiv_address (operands[1], operands[2]);
1380 emit_move_insn (operands[0], operands[1]);
1381 DONE;
1382 })
1384 (define_expand "reload<mode>_nonoffmem_out"
1385 [(parallel [(match_operand 0 "" "")
1386 (match_operand 1 "register_operand" "")
1387 (match_operand:P 2 "register_operand" "=&a")])]
1388 ""
1389 {
1390 gcc_assert (MEM_P (operands[0]));
1391 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1392 operands[0] = replace_equiv_address (operands[0], operands[2]);
1393 emit_move_insn (operands[0], operands[1]);
1394 DONE;
1395 })
1397 (define_expand "reload<mode>_PIC_addr"
1398 [(parallel [(match_operand 0 "register_operand" "=d")
1399 (match_operand 1 "larl_operand" "")
1400 (match_operand:P 2 "register_operand" "=a")])]
1401 ""
1402 {
1403 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1404 emit_move_insn (operands[0], new_rtx);
1405 })
1407 ;
1408 ; movdi instruction pattern(s).
1409 ;
1411 (define_expand "movdi"
1412 [(set (match_operand:DI 0 "general_operand" "")
1413 (match_operand:DI 1 "general_operand" ""))]
1414 ""
1415 {
1416 /* Handle symbolic constants. */
1417 if (TARGET_64BIT
1418 && (SYMBOLIC_CONST (operands[1])
1419 || (GET_CODE (operands[1]) == PLUS
1420 && XEXP (operands[1], 0) == pic_offset_table_rtx
1421 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1422 emit_symbolic_move (operands);
1423 })
1425 (define_insn "*movdi_larl"
1426 [(set (match_operand:DI 0 "register_operand" "=d")
1427 (match_operand:DI 1 "larl_operand" "X"))]
1428 "TARGET_64BIT
1429 && !FP_REG_P (operands[0])"
1430 "larl\t%0,%1"
1431 [(set_attr "op_type" "RIL")
1432 (set_attr "type" "larl")
1433 (set_attr "z10prop" "z10_super_A1")])
1435 (define_insn "*movdi_64"
1436 [(set (match_operand:DI 0 "nonimmediate_operand"
1437 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1438 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1439 (match_operand:DI 1 "general_operand"
1440 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1441 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1442 "TARGET_ZARCH"
1443 "@
1444 lghi\t%0,%h1
1445 llihh\t%0,%i1
1446 llihl\t%0,%i1
1447 llilh\t%0,%i1
1448 llill\t%0,%i1
1449 lgfi\t%0,%1
1450 llihf\t%0,%k1
1451 llilf\t%0,%k1
1452 ldgr\t%0,%1
1453 lgdr\t%0,%1
1454 lay\t%0,%a1
1455 lgrl\t%0,%1
1456 lgr\t%0,%1
1457 lg\t%0,%1
1458 stg\t%1,%0
1459 ldr\t%0,%1
1460 ld\t%0,%1
1461 ldy\t%0,%1
1462 std\t%1,%0
1463 stdy\t%1,%0
1464 stgrl\t%1,%0
1465 mvghi\t%0,%1
1466 #
1467 #
1468 stam\t%1,%N1,%S0
1469 lam\t%0,%N0,%S1"
1470 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1471 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1472 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1473 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1474 *,*")
1475 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1476 z10,*,*,*,*,*,longdisp,*,longdisp,
1477 z10,z10,*,*,*,*")
1478 (set_attr "z10prop" "z10_fwd_A1,
1479 z10_fwd_E1,
1480 z10_fwd_E1,
1481 z10_fwd_E1,
1482 z10_fwd_E1,
1483 z10_fwd_A1,
1484 z10_fwd_E1,
1485 z10_fwd_E1,
1486 *,
1487 *,
1488 z10_fwd_A1,
1489 z10_fwd_A3,
1490 z10_fr_E1,
1491 z10_fwd_A3,
1492 z10_rec,
1493 *,
1494 *,
1495 *,
1496 *,
1497 *,
1498 z10_rec,
1499 z10_super,
1500 *,
1501 *,
1502 *,
1503 *")
1504 ])
1506 (define_split
1507 [(set (match_operand:DI 0 "register_operand" "")
1508 (match_operand:DI 1 "register_operand" ""))]
1509 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1510 [(set (match_dup 2) (match_dup 3))
1511 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1512 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1513 "operands[2] = gen_lowpart (SImode, operands[0]);
1514 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1516 (define_split
1517 [(set (match_operand:DI 0 "register_operand" "")
1518 (match_operand:DI 1 "register_operand" ""))]
1519 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1520 && dead_or_set_p (insn, operands[1])"
1521 [(set (match_dup 3) (match_dup 2))
1522 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1523 (set (match_dup 4) (match_dup 2))]
1524 "operands[2] = gen_lowpart (SImode, operands[1]);
1525 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1527 (define_split
1528 [(set (match_operand:DI 0 "register_operand" "")
1529 (match_operand:DI 1 "register_operand" ""))]
1530 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1531 && !dead_or_set_p (insn, operands[1])"
1532 [(set (match_dup 3) (match_dup 2))
1533 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1534 (set (match_dup 4) (match_dup 2))
1535 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1536 "operands[2] = gen_lowpart (SImode, operands[1]);
1537 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1539 (define_insn "*movdi_31"
1540 [(set (match_operand:DI 0 "nonimmediate_operand"
1541 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1542 (match_operand:DI 1 "general_operand"
1543 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1544 "!TARGET_ZARCH"
1545 "@
1546 lm\t%0,%N0,%S1
1547 lmy\t%0,%N0,%S1
1548 stm\t%1,%N1,%S0
1549 stmy\t%1,%N1,%S0
1550 #
1551 #
1552 ldr\t%0,%1
1553 ld\t%0,%1
1554 ldy\t%0,%1
1555 std\t%1,%0
1556 stdy\t%1,%0
1557 #"
1558 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1559 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1560 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1562 ; For a load from a symbol ref we can use one of the target registers
1563 ; together with larl to load the address.
1564 (define_split
1565 [(set (match_operand:DI 0 "register_operand" "")
1566 (match_operand:DI 1 "memory_operand" ""))]
1567 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1568 && larl_operand (XEXP (operands[1], 0), SImode)"
1569 [(set (match_dup 2) (match_dup 3))
1570 (set (match_dup 0) (match_dup 1))]
1571 {
1572 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1573 operands[3] = XEXP (operands[1], 0);
1574 operands[1] = replace_equiv_address (operands[1], operands[2]);
1575 })
1577 (define_split
1578 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1579 (match_operand:DI 1 "general_operand" ""))]
1580 "!TARGET_ZARCH && reload_completed
1581 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1582 [(set (match_dup 2) (match_dup 4))
1583 (set (match_dup 3) (match_dup 5))]
1584 {
1585 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1586 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1587 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1588 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1589 })
1591 (define_split
1592 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1593 (match_operand:DI 1 "general_operand" ""))]
1594 "!TARGET_ZARCH && reload_completed
1595 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1596 [(set (match_dup 2) (match_dup 4))
1597 (set (match_dup 3) (match_dup 5))]
1598 {
1599 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1600 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1601 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1602 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1603 })
1605 (define_split
1606 [(set (match_operand:DI 0 "register_operand" "")
1607 (match_operand:DI 1 "memory_operand" ""))]
1608 "!TARGET_ZARCH && reload_completed
1609 && !FP_REG_P (operands[0])
1610 && !s_operand (operands[1], VOIDmode)"
1611 [(set (match_dup 0) (match_dup 1))]
1612 {
1613 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1614 s390_load_address (addr, XEXP (operands[1], 0));
1615 operands[1] = replace_equiv_address (operands[1], addr);
1616 })
1618 (define_peephole2
1619 [(set (match_operand:DI 0 "register_operand" "")
1620 (mem:DI (match_operand 1 "address_operand" "")))]
1621 "TARGET_ZARCH
1622 && !FP_REG_P (operands[0])
1623 && GET_CODE (operands[1]) == SYMBOL_REF
1624 && CONSTANT_POOL_ADDRESS_P (operands[1])
1625 && get_pool_mode (operands[1]) == DImode
1626 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1627 [(set (match_dup 0) (match_dup 2))]
1628 "operands[2] = get_pool_constant (operands[1]);")
1630 (define_insn "*la_64"
1631 [(set (match_operand:DI 0 "register_operand" "=d,d")
1632 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1633 "TARGET_64BIT"
1634 "@
1635 la\t%0,%a1
1636 lay\t%0,%a1"
1637 [(set_attr "op_type" "RX,RXY")
1638 (set_attr "type" "la")
1639 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1641 (define_peephole2
1642 [(parallel
1643 [(set (match_operand:DI 0 "register_operand" "")
1644 (match_operand:QI 1 "address_operand" ""))
1645 (clobber (reg:CC CC_REGNUM))])]
1646 "TARGET_64BIT
1647 && preferred_la_operand_p (operands[1], const0_rtx)"
1648 [(set (match_dup 0) (match_dup 1))]
1649 "")
1651 (define_peephole2
1652 [(set (match_operand:DI 0 "register_operand" "")
1653 (match_operand:DI 1 "register_operand" ""))
1654 (parallel
1655 [(set (match_dup 0)
1656 (plus:DI (match_dup 0)
1657 (match_operand:DI 2 "nonmemory_operand" "")))
1658 (clobber (reg:CC CC_REGNUM))])]
1659 "TARGET_64BIT
1660 && !reg_overlap_mentioned_p (operands[0], operands[2])
1661 && preferred_la_operand_p (operands[1], operands[2])"
1662 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1663 "")
1665 ;
1666 ; movsi instruction pattern(s).
1667 ;
1669 (define_expand "movsi"
1670 [(set (match_operand:SI 0 "general_operand" "")
1671 (match_operand:SI 1 "general_operand" ""))]
1672 ""
1673 {
1674 /* Handle symbolic constants. */
1675 if (!TARGET_64BIT
1676 && (SYMBOLIC_CONST (operands[1])
1677 || (GET_CODE (operands[1]) == PLUS
1678 && XEXP (operands[1], 0) == pic_offset_table_rtx
1679 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1680 emit_symbolic_move (operands);
1681 })
1683 (define_insn "*movsi_larl"
1684 [(set (match_operand:SI 0 "register_operand" "=d")
1685 (match_operand:SI 1 "larl_operand" "X"))]
1686 "!TARGET_64BIT && TARGET_CPU_ZARCH
1687 && !FP_REG_P (operands[0])"
1688 "larl\t%0,%1"
1689 [(set_attr "op_type" "RIL")
1690 (set_attr "type" "larl")
1691 (set_attr "z10prop" "z10_fwd_A1")])
1693 (define_insn "*movsi_zarch"
1694 [(set (match_operand:SI 0 "nonimmediate_operand"
1695 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1696 (match_operand:SI 1 "general_operand"
1697 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1698 "TARGET_ZARCH"
1699 "@
1700 lhi\t%0,%h1
1701 llilh\t%0,%i1
1702 llill\t%0,%i1
1703 iilf\t%0,%o1
1704 lay\t%0,%a1
1705 lrl\t%0,%1
1706 lr\t%0,%1
1707 l\t%0,%1
1708 ly\t%0,%1
1709 st\t%1,%0
1710 sty\t%1,%0
1711 ler\t%0,%1
1712 le\t%0,%1
1713 ley\t%0,%1
1714 ste\t%1,%0
1715 stey\t%1,%0
1716 ear\t%0,%1
1717 sar\t%0,%1
1718 stam\t%1,%1,%S0
1719 strl\t%1,%0
1720 mvhi\t%0,%1
1721 lam\t%0,%0,%S1"
1722 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1723 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1724 (set_attr "type" "*,
1725 *,
1726 *,
1727 *,
1728 la,
1729 larl,
1730 lr,
1731 load,
1732 load,
1733 store,
1734 store,
1735 floadsf,
1736 floadsf,
1737 floadsf,
1738 fstoresf,
1739 fstoresf,
1740 *,
1741 *,
1742 *,
1743 larl,
1744 *,
1745 *")
1746 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1747 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1748 (set_attr "z10prop" "z10_fwd_A1,
1749 z10_fwd_E1,
1750 z10_fwd_E1,
1751 z10_fwd_A1,
1752 z10_fwd_A1,
1753 z10_fwd_A3,
1754 z10_fr_E1,
1755 z10_fwd_A3,
1756 z10_fwd_A3,
1757 z10_rec,
1758 z10_rec,
1759 *,
1760 *,
1761 *,
1762 *,
1763 *,
1764 z10_super_E1,
1765 z10_super,
1766 *,
1767 z10_rec,
1768 z10_super,
1769 *")])
1771 (define_insn "*movsi_esa"
1772 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1773 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1774 "!TARGET_ZARCH"
1775 "@
1776 lhi\t%0,%h1
1777 lr\t%0,%1
1778 l\t%0,%1
1779 st\t%1,%0
1780 ler\t%0,%1
1781 le\t%0,%1
1782 ste\t%1,%0
1783 ear\t%0,%1
1784 sar\t%0,%1
1785 stam\t%1,%1,%S0
1786 lam\t%0,%0,%S1"
1787 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1788 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1789 (set_attr "z10prop" "z10_fwd_A1,
1790 z10_fr_E1,
1791 z10_fwd_A3,
1792 z10_rec,
1793 *,
1794 *,
1795 *,
1796 z10_super_E1,
1797 z10_super,
1798 *,
1799 *")
1800 ])
1802 (define_peephole2
1803 [(set (match_operand:SI 0 "register_operand" "")
1804 (mem:SI (match_operand 1 "address_operand" "")))]
1805 "!FP_REG_P (operands[0])
1806 && GET_CODE (operands[1]) == SYMBOL_REF
1807 && CONSTANT_POOL_ADDRESS_P (operands[1])
1808 && get_pool_mode (operands[1]) == SImode
1809 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1810 [(set (match_dup 0) (match_dup 2))]
1811 "operands[2] = get_pool_constant (operands[1]);")
1813 (define_insn "*la_31"
1814 [(set (match_operand:SI 0 "register_operand" "=d,d")
1815 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1816 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1817 "@
1818 la\t%0,%a1
1819 lay\t%0,%a1"
1820 [(set_attr "op_type" "RX,RXY")
1821 (set_attr "type" "la")
1822 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1824 (define_peephole2
1825 [(parallel
1826 [(set (match_operand:SI 0 "register_operand" "")
1827 (match_operand:QI 1 "address_operand" ""))
1828 (clobber (reg:CC CC_REGNUM))])]
1829 "!TARGET_64BIT
1830 && preferred_la_operand_p (operands[1], const0_rtx)"
1831 [(set (match_dup 0) (match_dup 1))]
1832 "")
1834 (define_peephole2
1835 [(set (match_operand:SI 0 "register_operand" "")
1836 (match_operand:SI 1 "register_operand" ""))
1837 (parallel
1838 [(set (match_dup 0)
1839 (plus:SI (match_dup 0)
1840 (match_operand:SI 2 "nonmemory_operand" "")))
1841 (clobber (reg:CC CC_REGNUM))])]
1842 "!TARGET_64BIT
1843 && !reg_overlap_mentioned_p (operands[0], operands[2])
1844 && preferred_la_operand_p (operands[1], operands[2])"
1845 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1846 "")
1848 (define_insn "*la_31_and"
1849 [(set (match_operand:SI 0 "register_operand" "=d,d")
1850 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1851 (const_int 2147483647)))]
1852 "!TARGET_64BIT"
1853 "@
1854 la\t%0,%a1
1855 lay\t%0,%a1"
1856 [(set_attr "op_type" "RX,RXY")
1857 (set_attr "type" "la")
1858 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1860 (define_insn_and_split "*la_31_and_cc"
1861 [(set (match_operand:SI 0 "register_operand" "=d")
1862 (and:SI (match_operand:QI 1 "address_operand" "p")
1863 (const_int 2147483647)))
1864 (clobber (reg:CC CC_REGNUM))]
1865 "!TARGET_64BIT"
1866 "#"
1867 "&& reload_completed"
1868 [(set (match_dup 0)
1869 (and:SI (match_dup 1) (const_int 2147483647)))]
1870 ""
1871 [(set_attr "op_type" "RX")
1872 (set_attr "type" "la")])
1874 (define_insn "force_la_31"
1875 [(set (match_operand:SI 0 "register_operand" "=d,d")
1876 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1877 (use (const_int 0))]
1878 "!TARGET_64BIT"
1879 "@
1880 la\t%0,%a1
1881 lay\t%0,%a1"
1882 [(set_attr "op_type" "RX")
1883 (set_attr "type" "la")
1884 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1886 ;
1887 ; movhi instruction pattern(s).
1888 ;
1890 (define_expand "movhi"
1891 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1892 (match_operand:HI 1 "general_operand" ""))]
1893 ""
1894 {
1895 /* Make it explicit that loading a register from memory
1896 always sign-extends (at least) to SImode. */
1897 if (optimize && can_create_pseudo_p ()
1898 && register_operand (operands[0], VOIDmode)
1899 && GET_CODE (operands[1]) == MEM)
1900 {
1901 rtx tmp = gen_reg_rtx (SImode);
1902 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1903 emit_insn (gen_rtx_SET (tmp, ext));
1904 operands[1] = gen_lowpart (HImode, tmp);
1905 }
1906 })
1908 (define_insn "*movhi"
1909 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1910 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1911 ""
1912 "@
1913 lr\t%0,%1
1914 lhi\t%0,%h1
1915 lh\t%0,%1
1916 lhy\t%0,%1
1917 lhrl\t%0,%1
1918 sth\t%1,%0
1919 sthy\t%1,%0
1920 sthrl\t%1,%0
1921 mvhhi\t%0,%1"
1922 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1923 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1924 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1925 (set_attr "z10prop" "z10_fr_E1,
1926 z10_fwd_A1,
1927 z10_super_E1,
1928 z10_super_E1,
1929 z10_super_E1,
1930 z10_rec,
1931 z10_rec,
1932 z10_rec,
1933 z10_super")])
1935 (define_peephole2
1936 [(set (match_operand:HI 0 "register_operand" "")
1937 (mem:HI (match_operand 1 "address_operand" "")))]
1938 "GET_CODE (operands[1]) == SYMBOL_REF
1939 && CONSTANT_POOL_ADDRESS_P (operands[1])
1940 && get_pool_mode (operands[1]) == HImode
1941 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1942 [(set (match_dup 0) (match_dup 2))]
1943 "operands[2] = get_pool_constant (operands[1]);")
1945 ;
1946 ; movqi instruction pattern(s).
1947 ;
1949 (define_expand "movqi"
1950 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1951 (match_operand:QI 1 "general_operand" ""))]
1952 ""
1953 {
1954 /* On z/Architecture, zero-extending from memory to register
1955 is just as fast as a QImode load. */
1956 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1957 && register_operand (operands[0], VOIDmode)
1958 && GET_CODE (operands[1]) == MEM)
1959 {
1960 rtx tmp = gen_reg_rtx (DImode);
1961 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
1962 emit_insn (gen_rtx_SET (tmp, ext));
1963 operands[1] = gen_lowpart (QImode, tmp);
1964 }
1965 })
1967 (define_insn "*movqi"
1968 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1969 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
1970 ""
1971 "@
1972 lr\t%0,%1
1973 lhi\t%0,%b1
1974 ic\t%0,%1
1975 icy\t%0,%1
1976 stc\t%1,%0
1977 stcy\t%1,%0
1978 mvi\t%S0,%b1
1979 mviy\t%S0,%b1
1980 #"
1981 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1982 (set_attr "type" "lr,*,*,*,store,store,store,store,*")
1983 (set_attr "z10prop" "z10_fr_E1,
1984 z10_fwd_A1,
1985 z10_super_E1,
1986 z10_super_E1,
1987 z10_rec,
1988 z10_rec,
1989 z10_super,
1990 z10_super,
1991 *")])
1993 (define_peephole2
1994 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1995 (mem:QI (match_operand 1 "address_operand" "")))]
1996 "GET_CODE (operands[1]) == SYMBOL_REF
1997 && CONSTANT_POOL_ADDRESS_P (operands[1])
1998 && get_pool_mode (operands[1]) == QImode
1999 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2000 [(set (match_dup 0) (match_dup 2))]
2001 "operands[2] = get_pool_constant (operands[1]);")
2003 ;
2004 ; movstrictqi instruction pattern(s).
2005 ;
2007 (define_insn "*movstrictqi"
2008 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
2009 (match_operand:QI 1 "memory_operand" "R,T"))]
2010 ""
2011 "@
2012 ic\t%0,%1
2013 icy\t%0,%1"
2014 [(set_attr "op_type" "RX,RXY")
2015 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2017 ;
2018 ; movstricthi instruction pattern(s).
2019 ;
2021 (define_insn "*movstricthi"
2022 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2023 (match_operand:HI 1 "memory_operand" "Q,S"))
2024 (clobber (reg:CC CC_REGNUM))]
2025 ""
2026 "@
2027 icm\t%0,3,%S1
2028 icmy\t%0,3,%S1"
2029 [(set_attr "op_type" "RS,RSY")
2030 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2032 ;
2033 ; movstrictsi instruction pattern(s).
2034 ;
2036 (define_insn "movstrictsi"
2037 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2038 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2039 "TARGET_ZARCH"
2040 "@
2041 lr\t%0,%1
2042 l\t%0,%1
2043 ly\t%0,%1
2044 ear\t%0,%1"
2045 [(set_attr "op_type" "RR,RX,RXY,RRE")
2046 (set_attr "type" "lr,load,load,*")
2047 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2049 ;
2050 ; mov(tf|td) instruction pattern(s).
2051 ;
2053 (define_expand "mov<mode>"
2054 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2055 (match_operand:TD_TF 1 "general_operand" ""))]
2056 ""
2057 "")
2059 (define_insn "*mov<mode>_64"
2060 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
2061 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
2062 "TARGET_ZARCH"
2063 "@
2064 lzxr\t%0
2065 lxr\t%0,%1
2066 #
2067 #
2068 lmg\t%0,%N0,%S1
2069 stmg\t%1,%N1,%S0
2070 #
2071 #"
2072 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
2073 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
2074 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2076 (define_insn "*mov<mode>_31"
2077 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2078 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2079 "!TARGET_ZARCH"
2080 "@
2081 lzxr\t%0
2082 lxr\t%0,%1
2083 #
2084 #"
2085 [(set_attr "op_type" "RRE,RRE,*,*")
2086 (set_attr "type" "fsimptf,fsimptf,*,*")
2087 (set_attr "cpu_facility" "z196,*,*,*")])
2089 ; TFmode in GPRs splitters
2091 (define_split
2092 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2093 (match_operand:TD_TF 1 "general_operand" ""))]
2094 "TARGET_ZARCH && reload_completed
2095 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2096 [(set (match_dup 2) (match_dup 4))
2097 (set (match_dup 3) (match_dup 5))]
2098 {
2099 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2100 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2101 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2102 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2103 })
2105 (define_split
2106 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2107 (match_operand:TD_TF 1 "general_operand" ""))]
2108 "TARGET_ZARCH && reload_completed
2109 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2110 [(set (match_dup 2) (match_dup 4))
2111 (set (match_dup 3) (match_dup 5))]
2112 {
2113 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2114 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2115 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2116 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2117 })
2119 (define_split
2120 [(set (match_operand:TD_TF 0 "register_operand" "")
2121 (match_operand:TD_TF 1 "memory_operand" ""))]
2122 "TARGET_ZARCH && reload_completed
2123 && !FP_REG_P (operands[0])
2124 && !s_operand (operands[1], VOIDmode)"
2125 [(set (match_dup 0) (match_dup 1))]
2126 {
2127 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2128 addr = gen_lowpart (Pmode, addr);
2129 s390_load_address (addr, XEXP (operands[1], 0));
2130 operands[1] = replace_equiv_address (operands[1], addr);
2131 })
2133 ; TFmode in BFPs splitters
2135 (define_split
2136 [(set (match_operand:TD_TF 0 "register_operand" "")
2137 (match_operand:TD_TF 1 "memory_operand" ""))]
2138 "reload_completed && offsettable_memref_p (operands[1])
2139 && FP_REG_P (operands[0])"
2140 [(set (match_dup 2) (match_dup 4))
2141 (set (match_dup 3) (match_dup 5))]
2142 {
2143 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2144 <MODE>mode, 0);
2145 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2146 <MODE>mode, 8);
2147 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2148 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2149 })
2151 (define_split
2152 [(set (match_operand:TD_TF 0 "memory_operand" "")
2153 (match_operand:TD_TF 1 "register_operand" ""))]
2154 "reload_completed && offsettable_memref_p (operands[0])
2155 && FP_REG_P (operands[1])"
2156 [(set (match_dup 2) (match_dup 4))
2157 (set (match_dup 3) (match_dup 5))]
2158 {
2159 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2160 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2161 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2162 <MODE>mode, 0);
2163 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2164 <MODE>mode, 8);
2165 })
2167 ;
2168 ; mov(df|dd) instruction pattern(s).
2169 ;
2171 (define_expand "mov<mode>"
2172 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2173 (match_operand:DD_DF 1 "general_operand" ""))]
2174 ""
2175 "")
2177 (define_insn "*mov<mode>_64dfp"
2178 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2179 "=f,f,f,d,f,f,R,T,d,d, d,RT")
2180 (match_operand:DD_DF 1 "general_operand"
2181 " G,f,d,f,R,T,f,f,G,d,RT, d"))]
2182 "TARGET_DFP"
2183 "@
2184 lzdr\t%0
2185 ldr\t%0,%1
2186 ldgr\t%0,%1
2187 lgdr\t%0,%1
2188 ld\t%0,%1
2189 ldy\t%0,%1
2190 std\t%1,%0
2191 stdy\t%1,%0
2192 lghi\t%0,0
2193 lgr\t%0,%1
2194 lg\t%0,%1
2195 stg\t%1,%0"
2196 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2197 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2198 fstoredf,fstoredf,*,lr,load,store")
2199 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2200 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2202 (define_insn "*mov<mode>_64"
2203 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT")
2204 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))]
2205 "TARGET_ZARCH"
2206 "@
2207 lzdr\t%0
2208 ldr\t%0,%1
2209 ld\t%0,%1
2210 ldy\t%0,%1
2211 std\t%1,%0
2212 stdy\t%1,%0
2213 lghi\t%0,0
2214 lgr\t%0,%1
2215 lg\t%0,%1
2216 stg\t%1,%0"
2217 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2218 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2219 fstore<mode>,fstore<mode>,*,lr,load,store")
2220 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2221 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")])
2223 (define_insn "*mov<mode>_31"
2224 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2225 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2226 (match_operand:DD_DF 1 "general_operand"
2227 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2228 "!TARGET_ZARCH"
2229 "@
2230 lzdr\t%0
2231 ldr\t%0,%1
2232 ld\t%0,%1
2233 ldy\t%0,%1
2234 std\t%1,%0
2235 stdy\t%1,%0
2236 lm\t%0,%N0,%S1
2237 lmy\t%0,%N0,%S1
2238 stm\t%1,%N1,%S0
2239 stmy\t%1,%N1,%S0
2240 #
2241 #"
2242 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2243 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2244 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2245 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2247 (define_split
2248 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2249 (match_operand:DD_DF 1 "general_operand" ""))]
2250 "!TARGET_ZARCH && reload_completed
2251 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2252 [(set (match_dup 2) (match_dup 4))
2253 (set (match_dup 3) (match_dup 5))]
2254 {
2255 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2256 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2257 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2258 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2259 })
2261 (define_split
2262 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2263 (match_operand:DD_DF 1 "general_operand" ""))]
2264 "!TARGET_ZARCH && reload_completed
2265 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2266 [(set (match_dup 2) (match_dup 4))
2267 (set (match_dup 3) (match_dup 5))]
2268 {
2269 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2270 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2271 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2272 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2273 })
2275 (define_split
2276 [(set (match_operand:DD_DF 0 "register_operand" "")
2277 (match_operand:DD_DF 1 "memory_operand" ""))]
2278 "!TARGET_ZARCH && reload_completed
2279 && !FP_REG_P (operands[0])
2280 && !s_operand (operands[1], VOIDmode)"
2281 [(set (match_dup 0) (match_dup 1))]
2282 {
2283 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2284 s390_load_address (addr, XEXP (operands[1], 0));
2285 operands[1] = replace_equiv_address (operands[1], addr);
2286 })
2288 ;
2289 ; mov(sf|sd) instruction pattern(s).
2290 ;
2292 (define_insn "mov<mode>"
2293 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2294 "=f,f,f,f,R,T,d,d,d,d,R,T")
2295 (match_operand:SD_SF 1 "general_operand"
2296 " G,f,R,T,f,f,G,d,R,T,d,d"))]
2297 ""
2298 "@
2299 lzer\t%0
2300 ler\t%0,%1
2301 le\t%0,%1
2302 ley\t%0,%1
2303 ste\t%1,%0
2304 stey\t%1,%0
2305 lhi\t%0,0
2306 lr\t%0,%1
2307 l\t%0,%1
2308 ly\t%0,%1
2309 st\t%1,%0
2310 sty\t%1,%0"
2311 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
2312 (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>,
2313 fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
2314 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2315 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2317 ;
2318 ; movcc instruction pattern
2319 ;
2321 (define_insn "movcc"
2322 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2323 (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2324 ""
2325 "@
2326 lr\t%0,%1
2327 tmh\t%1,12288
2328 ipm\t%0
2329 l\t%0,%1
2330 ly\t%0,%1
2331 st\t%1,%0
2332 sty\t%1,%0"
2333 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2334 (set_attr "type" "lr,*,*,load,load,store,store")
2335 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2336 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2338 ;
2339 ; Block move (MVC) patterns.
2340 ;
2342 (define_insn "*mvc"
2343 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2344 (match_operand:BLK 1 "memory_operand" "Q"))
2345 (use (match_operand 2 "const_int_operand" "n"))]
2346 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2347 "mvc\t%O0(%2,%R0),%S1"
2348 [(set_attr "op_type" "SS")])
2350 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2351 ; order to have it implemented with mvc.
2353 (define_split
2354 [(set (match_operand:QI 0 "memory_operand" "")
2355 (match_operand:QI 1 "memory_operand" ""))]
2356 "reload_completed"
2357 [(parallel
2358 [(set (match_dup 0) (match_dup 1))
2359 (use (const_int 1))])]
2360 {
2361 operands[0] = adjust_address (operands[0], BLKmode, 0);
2362 operands[1] = adjust_address (operands[1], BLKmode, 0);
2363 })
2366 (define_peephole2
2367 [(parallel
2368 [(set (match_operand:BLK 0 "memory_operand" "")
2369 (match_operand:BLK 1 "memory_operand" ""))
2370 (use (match_operand 2 "const_int_operand" ""))])
2371 (parallel
2372 [(set (match_operand:BLK 3 "memory_operand" "")
2373 (match_operand:BLK 4 "memory_operand" ""))
2374 (use (match_operand 5 "const_int_operand" ""))])]
2375 "s390_offset_p (operands[0], operands[3], operands[2])
2376 && s390_offset_p (operands[1], operands[4], operands[2])
2377 && !s390_overlap_p (operands[0], operands[1],
2378 INTVAL (operands[2]) + INTVAL (operands[5]))
2379 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2380 [(parallel
2381 [(set (match_dup 6) (match_dup 7))
2382 (use (match_dup 8))])]
2383 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2384 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2385 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2388 ;
2389 ; load_multiple pattern(s).
2390 ;
2391 ; ??? Due to reload problems with replacing registers inside match_parallel
2392 ; we currently support load_multiple/store_multiple only after reload.
2393 ;
2395 (define_expand "load_multiple"
2396 [(match_par_dup 3 [(set (match_operand 0 "" "")
2397 (match_operand 1 "" ""))
2398 (use (match_operand 2 "" ""))])]
2399 "reload_completed"
2400 {
2401 machine_mode mode;
2402 int regno;
2403 int count;
2404 rtx from;
2405 int i, off;
2407 /* Support only loading a constant number of fixed-point registers from
2408 memory and only bother with this if more than two */
2409 if (GET_CODE (operands[2]) != CONST_INT
2410 || INTVAL (operands[2]) < 2
2411 || INTVAL (operands[2]) > 16
2412 || GET_CODE (operands[1]) != MEM
2413 || GET_CODE (operands[0]) != REG
2414 || REGNO (operands[0]) >= 16)
2415 FAIL;
2417 count = INTVAL (operands[2]);
2418 regno = REGNO (operands[0]);
2419 mode = GET_MODE (operands[0]);
2420 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2421 FAIL;
2423 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2424 if (!can_create_pseudo_p ())
2425 {
2426 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2427 {
2428 from = XEXP (operands[1], 0);
2429 off = 0;
2430 }
2431 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2432 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2433 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2434 {
2435 from = XEXP (XEXP (operands[1], 0), 0);
2436 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2437 }
2438 else
2439 FAIL;
2440 }
2441 else
2442 {
2443 from = force_reg (Pmode, XEXP (operands[1], 0));
2444 off = 0;
2445 }
2447 for (i = 0; i < count; i++)
2448 XVECEXP (operands[3], 0, i)
2449 = gen_rtx_SET (gen_rtx_REG (mode, regno + i),
2450 change_address (operands[1], mode,
2451 plus_constant (Pmode, from,
2452 off + i * GET_MODE_SIZE (mode))));
2453 })
2455 (define_insn "*load_multiple_di"
2456 [(match_parallel 0 "load_multiple_operation"
2457 [(set (match_operand:DI 1 "register_operand" "=r")
2458 (match_operand:DI 2 "s_operand" "QS"))])]
2459 "reload_completed && TARGET_ZARCH"
2460 {
2461 int words = XVECLEN (operands[0], 0);
2462 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2463 return "lmg\t%1,%0,%S2";
2464 }
2465 [(set_attr "op_type" "RSY")
2466 (set_attr "type" "lm")])
2468 (define_insn "*load_multiple_si"
2469 [(match_parallel 0 "load_multiple_operation"
2470 [(set (match_operand:SI 1 "register_operand" "=r,r")
2471 (match_operand:SI 2 "s_operand" "Q,S"))])]
2472 "reload_completed"
2473 {
2474 int words = XVECLEN (operands[0], 0);
2475 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2476 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2477 }
2478 [(set_attr "op_type" "RS,RSY")
2479 (set_attr "type" "lm")])
2481 ;
2482 ; store multiple pattern(s).
2483 ;
2485 (define_expand "store_multiple"
2486 [(match_par_dup 3 [(set (match_operand 0 "" "")
2487 (match_operand 1 "" ""))
2488 (use (match_operand 2 "" ""))])]
2489 "reload_completed"
2490 {
2491 machine_mode mode;
2492 int regno;
2493 int count;
2494 rtx to;
2495 int i, off;
2497 /* Support only storing a constant number of fixed-point registers to
2498 memory and only bother with this if more than two. */
2499 if (GET_CODE (operands[2]) != CONST_INT
2500 || INTVAL (operands[2]) < 2
2501 || INTVAL (operands[2]) > 16
2502 || GET_CODE (operands[0]) != MEM
2503 || GET_CODE (operands[1]) != REG
2504 || REGNO (operands[1]) >= 16)
2505 FAIL;
2507 count = INTVAL (operands[2]);
2508 regno = REGNO (operands[1]);
2509 mode = GET_MODE (operands[1]);
2510 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2511 FAIL;
2513 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2515 if (!can_create_pseudo_p ())
2516 {
2517 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2518 {
2519 to = XEXP (operands[0], 0);
2520 off = 0;
2521 }
2522 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2523 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2524 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2525 {
2526 to = XEXP (XEXP (operands[0], 0), 0);
2527 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2528 }
2529 else
2530 FAIL;
2531 }
2532 else
2533 {
2534 to = force_reg (Pmode, XEXP (operands[0], 0));
2535 off = 0;
2536 }
2538 for (i = 0; i < count; i++)
2539 XVECEXP (operands[3], 0, i)
2540 = gen_rtx_SET (change_address (operands[0], mode,
2541 plus_constant (Pmode, to,
2542 off + i * GET_MODE_SIZE (mode))),
2543 gen_rtx_REG (mode, regno + i));
2544 })
2546 (define_insn "*store_multiple_di"
2547 [(match_parallel 0 "store_multiple_operation"
2548 [(set (match_operand:DI 1 "s_operand" "=QS")
2549 (match_operand:DI 2 "register_operand" "r"))])]
2550 "reload_completed && TARGET_ZARCH"
2551 {
2552 int words = XVECLEN (operands[0], 0);
2553 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2554 return "stmg\t%2,%0,%S1";
2555 }
2556 [(set_attr "op_type" "RSY")
2557 (set_attr "type" "stm")])
2560 (define_insn "*store_multiple_si"
2561 [(match_parallel 0 "store_multiple_operation"
2562 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2563 (match_operand:SI 2 "register_operand" "r,r"))])]
2564 "reload_completed"
2565 {
2566 int words = XVECLEN (operands[0], 0);
2567 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2568 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2569 }
2570 [(set_attr "op_type" "RS,RSY")
2571 (set_attr "type" "stm")])
2573 ;;
2574 ;; String instructions.
2575 ;;
2577 (define_insn "*execute_rl"
2578 [(match_parallel 0 "execute_operation"
2579 [(unspec [(match_operand 1 "register_operand" "a")
2580 (match_operand 2 "" "")
2581 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2582 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2583 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2584 "exrl\t%1,%3"
2585 [(set_attr "op_type" "RIL")
2586 (set_attr "type" "cs")])
2588 (define_insn "*execute"
2589 [(match_parallel 0 "execute_operation"
2590 [(unspec [(match_operand 1 "register_operand" "a")
2591 (match_operand:BLK 2 "memory_operand" "R")
2592 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2593 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2594 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2595 "ex\t%1,%2"
2596 [(set_attr "op_type" "RX")
2597 (set_attr "type" "cs")])
2600 ;
2601 ; strlenM instruction pattern(s).
2602 ;
2604 (define_expand "strlen<mode>"
2605 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2606 (parallel
2607 [(set (match_dup 4)
2608 (unspec:P [(const_int 0)
2609 (match_operand:BLK 1 "memory_operand" "")
2610 (reg:SI 0)
2611 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2612 (clobber (scratch:P))
2613 (clobber (reg:CC CC_REGNUM))])
2614 (parallel
2615 [(set (match_operand:P 0 "register_operand" "")
2616 (minus:P (match_dup 4) (match_dup 5)))
2617 (clobber (reg:CC CC_REGNUM))])]
2618 ""
2619 {
2620 operands[4] = gen_reg_rtx (Pmode);
2621 operands[5] = gen_reg_rtx (Pmode);
2622 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2623 operands[1] = replace_equiv_address (operands[1], operands[5]);
2624 })
2626 (define_insn "*strlen<mode>"
2627 [(set (match_operand:P 0 "register_operand" "=a")
2628 (unspec:P [(match_operand:P 2 "general_operand" "0")
2629 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2630 (reg:SI 0)
2631 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2632 (clobber (match_scratch:P 1 "=a"))
2633 (clobber (reg:CC CC_REGNUM))]
2634 ""
2635 "srst\t%0,%1\;jo\t.-4"
2636 [(set_attr "length" "8")
2637 (set_attr "type" "vs")])
2639 ;
2640 ; cmpstrM instruction pattern(s).
2641 ;
2643 (define_expand "cmpstrsi"
2644 [(set (reg:SI 0) (const_int 0))
2645 (parallel
2646 [(clobber (match_operand 3 "" ""))
2647 (clobber (match_dup 4))
2648 (set (reg:CCU CC_REGNUM)
2649 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2650 (match_operand:BLK 2 "memory_operand" "")))
2651 (use (reg:SI 0))])
2652 (parallel
2653 [(set (match_operand:SI 0 "register_operand" "=d")
2654 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
2655 (clobber (reg:CC CC_REGNUM))])]
2656 ""
2657 {
2658 /* As the result of CMPINT is inverted compared to what we need,
2659 we have to swap the operands. */
2660 rtx op1 = operands[2];
2661 rtx op2 = operands[1];
2662 rtx addr1 = gen_reg_rtx (Pmode);
2663 rtx addr2 = gen_reg_rtx (Pmode);
2665 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2666 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2667 operands[1] = replace_equiv_address_nv (op1, addr1);
2668 operands[2] = replace_equiv_address_nv (op2, addr2);
2669 operands[3] = addr1;
2670 operands[4] = addr2;
2671 })
2673 (define_insn "*cmpstr<mode>"
2674 [(clobber (match_operand:P 0 "register_operand" "=d"))
2675 (clobber (match_operand:P 1 "register_operand" "=d"))
2676 (set (reg:CCU CC_REGNUM)
2677 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2678 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2679 (use (reg:SI 0))]
2680 ""
2681 "clst\t%0,%1\;jo\t.-4"
2682 [(set_attr "length" "8")
2683 (set_attr "type" "vs")])
2685 ;
2686 ; movstr instruction pattern.
2687 ;
2689 (define_expand "movstr"
2690 [(set (reg:SI 0) (const_int 0))
2691 (parallel
2692 [(clobber (match_dup 3))
2693 (set (match_operand:BLK 1 "memory_operand" "")
2694 (match_operand:BLK 2 "memory_operand" ""))
2695 (set (match_operand 0 "register_operand" "")
2696 (unspec [(match_dup 1)
2697 (match_dup 2)
2698 (reg:SI 0)] UNSPEC_MVST))
2699 (clobber (reg:CC CC_REGNUM))])]
2700 ""
2701 {
2702 rtx addr1 = gen_reg_rtx (Pmode);
2703 rtx addr2 = gen_reg_rtx (Pmode);
2705 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2706 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2707 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2708 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2709 operands[3] = addr2;
2710 })
2712 (define_insn "*movstr"
2713 [(clobber (match_operand:P 2 "register_operand" "=d"))
2714 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2715 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2716 (set (match_operand:P 0 "register_operand" "=d")
2717 (unspec [(mem:BLK (match_dup 1))
2718 (mem:BLK (match_dup 3))
2719 (reg:SI 0)] UNSPEC_MVST))
2720 (clobber (reg:CC CC_REGNUM))]
2721 ""
2722 "mvst\t%1,%2\;jo\t.-4"
2723 [(set_attr "length" "8")
2724 (set_attr "type" "vs")])
2727 ;
2728 ; movmemM instruction pattern(s).
2729 ;
2731 (define_expand "movmem<mode>"
2732 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2733 (match_operand:BLK 1 "memory_operand" "")) ; source
2734 (use (match_operand:GPR 2 "general_operand" "")) ; count
2735 (match_operand 3 "" "")]
2736 ""
2737 {
2738 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2739 DONE;
2740 else
2741 FAIL;
2742 })
2744 ; Move a block that is up to 256 bytes in length.
2745 ; The block length is taken as (operands[2] % 256) + 1.
2747 (define_expand "movmem_short"
2748 [(parallel
2749 [(set (match_operand:BLK 0 "memory_operand" "")
2750 (match_operand:BLK 1 "memory_operand" ""))
2751 (use (match_operand 2 "nonmemory_operand" ""))
2752 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2753 (clobber (match_dup 3))])]
2754 ""
2755 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2757 (define_insn "*movmem_short"
2758 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2759 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2760 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2761 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2762 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
2763 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
2764 "#"
2765 [(set_attr "type" "cs")
2766 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
2768 (define_split
2769 [(set (match_operand:BLK 0 "memory_operand" "")
2770 (match_operand:BLK 1 "memory_operand" ""))
2771 (use (match_operand 2 "const_int_operand" ""))
2772 (use (match_operand 3 "immediate_operand" ""))
2773 (clobber (scratch))]
2774 "reload_completed"
2775 [(parallel
2776 [(set (match_dup 0) (match_dup 1))
2777 (use (match_dup 2))])]
2778 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2780 (define_split
2781 [(set (match_operand:BLK 0 "memory_operand" "")
2782 (match_operand:BLK 1 "memory_operand" ""))
2783 (use (match_operand 2 "register_operand" ""))
2784 (use (match_operand 3 "memory_operand" ""))
2785 (clobber (scratch))]
2786 "reload_completed"
2787 [(parallel
2788 [(unspec [(match_dup 2) (match_dup 3)
2789 (const_int 0)] UNSPEC_EXECUTE)
2790 (set (match_dup 0) (match_dup 1))
2791 (use (const_int 1))])]
2792 "")
2794 (define_split
2795 [(set (match_operand:BLK 0 "memory_operand" "")
2796 (match_operand:BLK 1 "memory_operand" ""))
2797 (use (match_operand 2 "register_operand" ""))
2798 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2799 (clobber (scratch))]
2800 "TARGET_Z10 && reload_completed"
2801 [(parallel
2802 [(unspec [(match_dup 2) (const_int 0)
2803 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2804 (set (match_dup 0) (match_dup 1))
2805 (use (const_int 1))])]
2806 "operands[3] = gen_label_rtx ();")
2808 (define_split
2809 [(set (match_operand:BLK 0 "memory_operand" "")
2810 (match_operand:BLK 1 "memory_operand" ""))
2811 (use (match_operand 2 "register_operand" ""))
2812 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2813 (clobber (match_operand 3 "register_operand" ""))]
2814 "reload_completed && TARGET_CPU_ZARCH"
2815 [(set (match_dup 3) (label_ref (match_dup 4)))
2816 (parallel
2817 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2818 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2819 (set (match_dup 0) (match_dup 1))
2820 (use (const_int 1))])]
2821 "operands[4] = gen_label_rtx ();")
2823 ; Move a block of arbitrary length.
2825 (define_expand "movmem_long"
2826 [(parallel
2827 [(clobber (match_dup 2))
2828 (clobber (match_dup 3))
2829 (set (match_operand:BLK 0 "memory_operand" "")
2830 (match_operand:BLK 1 "memory_operand" ""))
2831 (use (match_operand 2 "general_operand" ""))
2832 (use (match_dup 3))
2833 (clobber (reg:CC CC_REGNUM))])]
2834 ""
2835 {
2836 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2837 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2838 rtx reg0 = gen_reg_rtx (dreg_mode);
2839 rtx reg1 = gen_reg_rtx (dreg_mode);
2840 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2841 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2842 rtx len0 = gen_lowpart (Pmode, reg0);
2843 rtx len1 = gen_lowpart (Pmode, reg1);
2845 emit_clobber (reg0);
2846 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2847 emit_move_insn (len0, operands[2]);
2849 emit_clobber (reg1);
2850 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2851 emit_move_insn (len1, operands[2]);
2853 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2854 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2855 operands[2] = reg0;
2856 operands[3] = reg1;
2857 })
2859 (define_insn "*movmem_long"
2860 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2861 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2862 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2863 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2864 (use (match_dup 2))
2865 (use (match_dup 3))
2866 (clobber (reg:CC CC_REGNUM))]
2867 "TARGET_64BIT || !TARGET_ZARCH"
2868 "mvcle\t%0,%1,0\;jo\t.-4"
2869 [(set_attr "length" "8")
2870 (set_attr "type" "vs")])
2872 (define_insn "*movmem_long_31z"
2873 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2874 (clobber (match_operand:TI 1 "register_operand" "=d"))
2875 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2876 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2877 (use (match_dup 2))
2878 (use (match_dup 3))
2879 (clobber (reg:CC CC_REGNUM))]
2880 "!TARGET_64BIT && TARGET_ZARCH"
2881 "mvcle\t%0,%1,0\;jo\t.-4"
2882 [(set_attr "length" "8")
2883 (set_attr "type" "vs")])
2886 ;
2887 ; Test data class.
2888 ;
2890 (define_expand "signbit<mode>2"
2891 [(set (reg:CCZ CC_REGNUM)
2892 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2893 (match_dup 2)]
2894 UNSPEC_TDC_INSN))
2895 (set (match_operand:SI 0 "register_operand" "=d")
2896 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
2897 "TARGET_HARD_FLOAT"
2898 {
2899 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2900 })
2902 (define_expand "isinf<mode>2"
2903 [(set (reg:CCZ CC_REGNUM)
2904 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2905 (match_dup 2)]
2906 UNSPEC_TDC_INSN))
2907 (set (match_operand:SI 0 "register_operand" "=d")
2908 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
2909 "TARGET_HARD_FLOAT"
2910 {
2911 operands[2] = GEN_INT (S390_TDC_INFINITY);
2912 })
2914 (define_insn_and_split "*cc_to_int"
2915 [(set (match_operand:SI 0 "register_operand" "=d")
2916 (unspec:SI [(match_operand 1 "register_operand" "0")]
2917 UNSPEC_CC_TO_INT))]
2918 "operands != NULL"
2919 "#"
2920 "reload_completed"
2921 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2923 ; This insn is used to generate all variants of the Test Data Class
2924 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2925 ; is the register to be tested and the second one is the bit mask
2926 ; specifying the required test(s).
2927 ;
2928 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
2929 (define_insn "*TDC_insn_<mode>"
2930 [(set (reg:CCZ CC_REGNUM)
2931 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2932 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2933 "TARGET_HARD_FLOAT"
2934 "t<_d>c<xde><bt>\t%0,%1"
2935 [(set_attr "op_type" "RXE")
2936 (set_attr "type" "fsimp<mode>")])
2940 ;
2941 ; setmemM instruction pattern(s).
2942 ;
2944 (define_expand "setmem<mode>"
2945 [(set (match_operand:BLK 0 "memory_operand" "")
2946 (match_operand:QI 2 "general_operand" ""))
2947 (use (match_operand:GPR 1 "general_operand" ""))
2948 (match_operand 3 "" "")]
2949 ""
2950 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2952 ; Clear a block that is up to 256 bytes in length.
2953 ; The block length is taken as (operands[1] % 256) + 1.
2955 (define_expand "clrmem_short"
2956 [(parallel
2957 [(set (match_operand:BLK 0 "memory_operand" "")
2958 (const_int 0))
2959 (use (match_operand 1 "nonmemory_operand" ""))
2960 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2961 (clobber (match_dup 2))
2962 (clobber (reg:CC CC_REGNUM))])]
2963 ""
2964 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2966 (define_insn "*clrmem_short"
2967 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2968 (const_int 0))
2969 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2970 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2971 (clobber (match_scratch:P 3 "=X,X,X,&a"))
2972 (clobber (reg:CC CC_REGNUM))]
2973 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
2974 "#"
2975 [(set_attr "type" "cs")
2976 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
2978 (define_split
2979 [(set (match_operand:BLK 0 "memory_operand" "")
2980 (const_int 0))
2981 (use (match_operand 1 "const_int_operand" ""))
2982 (use (match_operand 2 "immediate_operand" ""))
2983 (clobber (scratch))
2984 (clobber (reg:CC CC_REGNUM))]
2985 "reload_completed"
2986 [(parallel
2987 [(set (match_dup 0) (const_int 0))
2988 (use (match_dup 1))
2989 (clobber (reg:CC CC_REGNUM))])]
2990 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2992 (define_split
2993 [(set (match_operand:BLK 0 "memory_operand" "")
2994 (const_int 0))
2995 (use (match_operand 1 "register_operand" ""))
2996 (use (match_operand 2 "memory_operand" ""))
2997 (clobber (scratch))
2998 (clobber (reg:CC CC_REGNUM))]
2999 "reload_completed"
3000 [(parallel
3001 [(unspec [(match_dup 1) (match_dup 2)
3002 (const_int 0)] UNSPEC_EXECUTE)
3003 (set (match_dup 0) (const_int 0))
3004 (use (const_int 1))
3005 (clobber (reg:CC CC_REGNUM))])]
3006 "")
3008 (define_split
3009 [(set (match_operand:BLK 0 "memory_operand" "")
3010 (const_int 0))
3011 (use (match_operand 1 "register_operand" ""))
3012 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3013 (clobber (scratch))
3014 (clobber (reg:CC CC_REGNUM))]
3015 "TARGET_Z10 && reload_completed"
3016 [(parallel
3017 [(unspec [(match_dup 1) (const_int 0)
3018 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3019 (set (match_dup 0) (const_int 0))
3020 (use (const_int 1))
3021 (clobber (reg:CC CC_REGNUM))])]
3022 "operands[3] = gen_label_rtx ();")
3024 (define_split
3025 [(set (match_operand:BLK 0 "memory_operand" "")
3026 (const_int 0))
3027 (use (match_operand 1 "register_operand" ""))
3028 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3029 (clobber (match_operand 2 "register_operand" ""))
3030 (clobber (reg:CC CC_REGNUM))]
3031 "reload_completed && TARGET_CPU_ZARCH"
3032 [(set (match_dup 2) (label_ref (match_dup 3)))
3033 (parallel
3034 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3035 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3036 (set (match_dup 0) (const_int 0))
3037 (use (const_int 1))
3038 (clobber (reg:CC CC_REGNUM))])]
3039 "operands[3] = gen_label_rtx ();")
3041 ; Initialize a block of arbitrary length with (operands[2] % 256).
3043 (define_expand "setmem_long"
3044 [(parallel
3045 [(clobber (match_dup 1))
3046 (set (match_operand:BLK 0 "memory_operand" "")
3047 (match_operand 2 "shift_count_or_setmem_operand" ""))
3048 (use (match_operand 1 "general_operand" ""))
3049 (use (match_dup 3))
3050 (clobber (reg:CC CC_REGNUM))])]
3051 ""
3052 {
3053 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3054 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3055 rtx reg0 = gen_reg_rtx (dreg_mode);
3056 rtx reg1 = gen_reg_rtx (dreg_mode);
3057 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3058 rtx len0 = gen_lowpart (Pmode, reg0);
3060 emit_clobber (reg0);
3061 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3062 emit_move_insn (len0, operands[1]);
3064 emit_move_insn (reg1, const0_rtx);
3066 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3067 operands[1] = reg0;
3068 operands[3] = reg1;
3069 })
3071 (define_insn "*setmem_long"
3072 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3073 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3074 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3075 (use (match_dup 3))
3076 (use (match_operand:<DBL> 1 "register_operand" "d"))
3077 (clobber (reg:CC CC_REGNUM))]
3078 "TARGET_64BIT || !TARGET_ZARCH"
3079 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3080 [(set_attr "length" "8")
3081 (set_attr "type" "vs")])
3083 (define_insn "*setmem_long_and"
3084 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3085 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3086 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
3087 (match_operand 4 "const_int_operand" "n")))
3088 (use (match_dup 3))
3089 (use (match_operand:<DBL> 1 "register_operand" "d"))
3090 (clobber (reg:CC CC_REGNUM))]
3091 "(TARGET_64BIT || !TARGET_ZARCH) &&
3092 (INTVAL (operands[4]) & 255) == 255"
3093 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3094 [(set_attr "length" "8")
3095 (set_attr "type" "vs")])
3097 (define_insn "*setmem_long_31z"
3098 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3099 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3100 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3101 (use (match_dup 3))
3102 (use (match_operand:TI 1 "register_operand" "d"))
3103 (clobber (reg:CC CC_REGNUM))]
3104 "!TARGET_64BIT && TARGET_ZARCH"
3105 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3106 [(set_attr "length" "8")
3107 (set_attr "type" "vs")])
3109 ;
3110 ; cmpmemM instruction pattern(s).
3111 ;
3113 (define_expand "cmpmemsi"
3114 [(set (match_operand:SI 0 "register_operand" "")
3115 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3116 (match_operand:BLK 2 "memory_operand" "") ) )
3117 (use (match_operand:SI 3 "general_operand" ""))
3118 (use (match_operand:SI 4 "" ""))]
3119 ""
3120 {
3121 if (s390_expand_cmpmem (operands[0], operands[1],
3122 operands[2], operands[3]))
3123 DONE;
3124 else
3125 FAIL;
3126 })
3128 ; Compare a block that is up to 256 bytes in length.
3129 ; The block length is taken as (operands[2] % 256) + 1.
3131 (define_expand "cmpmem_short"
3132 [(parallel
3133 [(set (reg:CCU CC_REGNUM)
3134 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3135 (match_operand:BLK 1 "memory_operand" "")))
3136 (use (match_operand 2 "nonmemory_operand" ""))
3137 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3138 (clobber (match_dup 3))])]
3139 ""
3140 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3142 (define_insn "*cmpmem_short"
3143 [(set (reg:CCU CC_REGNUM)
3144 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3145 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3146 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3147 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3148 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3149 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3150 "#"
3151 [(set_attr "type" "cs")
3152 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3154 (define_split
3155 [(set (reg:CCU CC_REGNUM)
3156 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3157 (match_operand:BLK 1 "memory_operand" "")))
3158 (use (match_operand 2 "const_int_operand" ""))
3159 (use (match_operand 3 "immediate_operand" ""))
3160 (clobber (scratch))]
3161 "reload_completed"
3162 [(parallel
3163 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3164 (use (match_dup 2))])]
3165 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3167 (define_split
3168 [(set (reg:CCU CC_REGNUM)
3169 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3170 (match_operand:BLK 1 "memory_operand" "")))
3171 (use (match_operand 2 "register_operand" ""))
3172 (use (match_operand 3 "memory_operand" ""))
3173 (clobber (scratch))]
3174 "reload_completed"
3175 [(parallel
3176 [(unspec [(match_dup 2) (match_dup 3)
3177 (const_int 0)] UNSPEC_EXECUTE)
3178 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3179 (use (const_int 1))])]
3180 "")
3182 (define_split
3183 [(set (reg:CCU CC_REGNUM)
3184 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3185 (match_operand:BLK 1 "memory_operand" "")))
3186 (use (match_operand 2 "register_operand" ""))
3187 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3188 (clobber (scratch))]
3189 "TARGET_Z10 && reload_completed"
3190 [(parallel
3191 [(unspec [(match_dup 2) (const_int 0)
3192 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3193 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3194 (use (const_int 1))])]
3195 "operands[4] = gen_label_rtx ();")
3197 (define_split
3198 [(set (reg:CCU CC_REGNUM)
3199 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3200 (match_operand:BLK 1 "memory_operand" "")))
3201 (use (match_operand 2 "register_operand" ""))
3202 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3203 (clobber (match_operand 3 "register_operand" ""))]
3204 "reload_completed && TARGET_CPU_ZARCH"
3205 [(set (match_dup 3) (label_ref (match_dup 4)))
3206 (parallel
3207 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3208 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3209 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3210 (use (const_int 1))])]
3211 "operands[4] = gen_label_rtx ();")
3213 ; Compare a block of arbitrary length.
3215 (define_expand "cmpmem_long"
3216 [(parallel
3217 [(clobber (match_dup 2))
3218 (clobber (match_dup 3))
3219 (set (reg:CCU CC_REGNUM)
3220 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3221 (match_operand:BLK 1 "memory_operand" "")))
3222 (use (match_operand 2 "general_operand" ""))
3223 (use (match_dup 3))])]
3224 ""
3225 {
3226 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3227 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3228 rtx reg0 = gen_reg_rtx (dreg_mode);
3229 rtx reg1 = gen_reg_rtx (dreg_mode);
3230 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3231 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3232 rtx len0 = gen_lowpart (Pmode, reg0);
3233 rtx len1 = gen_lowpart (Pmode, reg1);
3235 emit_clobber (reg0);
3236 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3237 emit_move_insn (len0, operands[2]);
3239 emit_clobber (reg1);
3240 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3241 emit_move_insn (len1, operands[2]);
3243 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3244 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3245 operands[2] = reg0;
3246 operands[3] = reg1;
3247 })
3249 (define_insn "*cmpmem_long"
3250 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3251 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3252 (set (reg:CCU CC_REGNUM)
3253 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3254 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3255 (use (match_dup 2))
3256 (use (match_dup 3))]
3257 "TARGET_64BIT || !TARGET_ZARCH"
3258 "clcle\t%0,%1,0\;jo\t.-4"
3259 [(set_attr "length" "8")
3260 (set_attr "type" "vs")])
3262 (define_insn "*cmpmem_long_31z"
3263 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3264 (clobber (match_operand:TI 1 "register_operand" "=d"))
3265 (set (reg:CCU CC_REGNUM)
3266 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3267 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3268 (use (match_dup 2))
3269 (use (match_dup 3))]
3270 "!TARGET_64BIT && TARGET_ZARCH"
3271 "clcle\t%0,%1,0\;jo\t.-4"
3272 [(set_attr "op_type" "NN")
3273 (set_attr "type" "vs")
3274 (set_attr "length" "8")])
3276 ; Convert CCUmode condition code to integer.
3277 ; Result is zero if EQ, positive if LTU, negative if GTU.
3279 (define_insn_and_split "cmpint"
3280 [(set (match_operand:SI 0 "register_operand" "=d")
3281 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3282 UNSPEC_STRCMPCC_TO_INT))
3283 (clobber (reg:CC CC_REGNUM))]
3284 ""
3285 "#"
3286 "reload_completed"
3287 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3288 (parallel
3289 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3290 (clobber (reg:CC CC_REGNUM))])])
3292 (define_insn_and_split "*cmpint_cc"
3293 [(set (reg CC_REGNUM)
3294 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3295 UNSPEC_STRCMPCC_TO_INT)
3296 (const_int 0)))
3297 (set (match_operand:SI 0 "register_operand" "=d")
3298 (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3299 "s390_match_ccmode (insn, CCSmode)"
3300 "#"
3301 "&& reload_completed"
3302 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3303 (parallel
3304 [(set (match_dup 2) (match_dup 3))
3305 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3306 {
3307 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3308 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3309 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3310 })
3312 (define_insn_and_split "*cmpint_sign"
3313 [(set (match_operand:DI 0 "register_operand" "=d")
3314 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3315 UNSPEC_STRCMPCC_TO_INT)))
3316 (clobber (reg:CC CC_REGNUM))]
3317 "TARGET_ZARCH"
3318 "#"
3319 "&& reload_completed"
3320 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3321 (parallel
3322 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3323 (clobber (reg:CC CC_REGNUM))])])
3325 (define_insn_and_split "*cmpint_sign_cc"
3326 [(set (reg CC_REGNUM)
3327 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3328 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3329 UNSPEC_STRCMPCC_TO_INT) 0)
3330 (const_int 32)) (const_int 32))
3331 (const_int 0)))
3332 (set (match_operand:DI 0 "register_operand" "=d")
3333 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3334 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3335 "#"
3336 "&& reload_completed"
3337 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3338 (parallel
3339 [(set (match_dup 2) (match_dup 3))
3340 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3341 {
3342 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3343 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3344 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3345 })
3348 ;;
3349 ;;- Conversion instructions.
3350 ;;
3352 (define_insn "*sethighpartsi"
3353 [(set (match_operand:SI 0 "register_operand" "=d,d")
3354 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3355 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3356 (clobber (reg:CC CC_REGNUM))]
3357 ""
3358 "@
3359 icm\t%0,%2,%S1
3360 icmy\t%0,%2,%S1"
3361 [(set_attr "op_type" "RS,RSY")
3362 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3364 (define_insn "*sethighpartdi_64"
3365 [(set (match_operand:DI 0 "register_operand" "=d")
3366 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3367 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3368 (clobber (reg:CC CC_REGNUM))]
3369 "TARGET_ZARCH"
3370 "icmh\t%0,%2,%S1"
3371 [(set_attr "op_type" "RSY")
3372 (set_attr "z10prop" "z10_super")])
3374 (define_insn "*sethighpartdi_31"
3375 [(set (match_operand:DI 0 "register_operand" "=d,d")
3376 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3377 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3378 (clobber (reg:CC CC_REGNUM))]
3379 "!TARGET_ZARCH"
3380 "@
3381 icm\t%0,%2,%S1
3382 icmy\t%0,%2,%S1"
3383 [(set_attr "op_type" "RS,RSY")
3384 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3386 ;
3387 ; extv instruction patterns
3388 ;
3390 ; FIXME: This expander needs to be converted from DI to GPR as well
3391 ; after resolving some issues with it.
3393 (define_expand "extzv"
3394 [(parallel
3395 [(set (match_operand:DI 0 "register_operand" "=d")
3396 (zero_extract:DI
3397 (match_operand:DI 1 "register_operand" "d")
3398 (match_operand 2 "const_int_operand" "") ; size
3399 (match_operand 3 "const_int_operand" ""))) ; start
3400 (clobber (reg:CC CC_REGNUM))])]
3401 "TARGET_Z10"
3402 {
3403 /* Starting with zEC12 there is risbgn not clobbering CC. */
3404 if (TARGET_ZEC12)
3405 {
3406 emit_move_insn (operands[0],
3407 gen_rtx_ZERO_EXTRACT (DImode,
3408 operands[1],
3409 operands[2],
3410 operands[3]));
3411 DONE;
3412 }
3413 })
3415 (define_insn "*extzv<mode>_zEC12"
3416 [(set (match_operand:GPR 0 "register_operand" "=d")
3417 (zero_extract:GPR
3418 (match_operand:GPR 1 "register_operand" "d")
3419 (match_operand 2 "const_int_operand" "") ; size
3420 (match_operand 3 "const_int_operand" "")))] ; start]
3421 "TARGET_ZEC12"
3422 "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3423 [(set_attr "op_type" "RIE")])
3425 (define_insn "*extzv<mode>_z10"
3426 [(set (match_operand:GPR 0 "register_operand" "=d")
3427 (zero_extract:GPR
3428 (match_operand:GPR 1 "register_operand" "d")
3429 (match_operand 2 "const_int_operand" "") ; size
3430 (match_operand 3 "const_int_operand" ""))) ; start
3431 (clobber (reg:CC CC_REGNUM))]
3432 "TARGET_Z10"
3433 "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3434 [(set_attr "op_type" "RIE")
3435 (set_attr "z10prop" "z10_super_E1")])
3437 (define_insn_and_split "*pre_z10_extzv<mode>"
3438 [(set (match_operand:GPR 0 "register_operand" "=d")
3439 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3440 (match_operand 2 "nonzero_shift_count_operand" "")
3441 (const_int 0)))
3442 (clobber (reg:CC CC_REGNUM))]
3443 "!TARGET_Z10"
3444 "#"
3445 "&& reload_completed"
3446 [(parallel
3447 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3448 (clobber (reg:CC CC_REGNUM))])
3449 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3450 {
3451 int bitsize = INTVAL (operands[2]);
3452 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3453 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3455 operands[1] = adjust_address (operands[1], BLKmode, 0);
3456 set_mem_size (operands[1], size);
3457 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3458 operands[3] = GEN_INT (mask);
3459 })
3461 (define_insn_and_split "*pre_z10_extv<mode>"
3462 [(set (match_operand:GPR 0 "register_operand" "=d")
3463 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3464 (match_operand 2 "nonzero_shift_count_operand" "")
3465 (const_int 0)))
3466 (clobber (reg:CC CC_REGNUM))]
3467 ""
3468 "#"
3469 "&& reload_completed"
3470 [(parallel
3471 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3472 (clobber (reg:CC CC_REGNUM))])
3473 (parallel
3474 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3475 (clobber (reg:CC CC_REGNUM))])]
3476 {
3477 int bitsize = INTVAL (operands[2]);
3478 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3479 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3481 operands[1] = adjust_address (operands[1], BLKmode, 0);
3482 set_mem_size (operands[1], size);
3483 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3484 operands[3] = GEN_INT (mask);
3485 })
3487 ;
3488 ; insv instruction patterns
3489 ;
3491 (define_expand "insv"
3492 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3493 (match_operand 1 "const_int_operand" "")
3494 (match_operand 2 "const_int_operand" ""))
3495 (match_operand 3 "general_operand" ""))]
3496 ""
3497 {
3498 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3499 DONE;
3500 FAIL;
3501 })
3504 ; The normal RTL expansion will never generate a zero_extract where
3505 ; the location operand isn't word mode. However, we do this in the
3506 ; back-end when generating atomic operations. See s390_two_part_insv.
3507 (define_insn "*insv<mode>_zEC12"
3508 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3509 (match_operand 1 "const_int_operand" "I") ; size
3510 (match_operand 2 "const_int_operand" "I")) ; pos
3511 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3512 "TARGET_ZEC12
3513 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3514 "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3515 [(set_attr "op_type" "RIE")])
3517 (define_insn "*insv<mode>_z10"
3518 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3519 (match_operand 1 "const_int_operand" "I") ; size
3520 (match_operand 2 "const_int_operand" "I")) ; pos
3521 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3522 (clobber (reg:CC CC_REGNUM))]
3523 "TARGET_Z10
3524 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3525 "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3526 [(set_attr "op_type" "RIE")
3527 (set_attr "z10prop" "z10_super_E1")])
3529 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3530 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3531 (define_insn "*insv<mode>_zEC12_noshift"
3532 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3533 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3534 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3535 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3536 (match_operand:GPR 4 "const_int_operand" ""))))]
3537 "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3538 "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3539 [(set_attr "op_type" "RIE")])
3541 (define_insn "*insv<mode>_z10_noshift"
3542 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3543 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3544 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3545 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3546 (match_operand:GPR 4 "const_int_operand" ""))))
3547 (clobber (reg:CC CC_REGNUM))]
3548 "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3549 "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3550 [(set_attr "op_type" "RIE")
3551 (set_attr "z10prop" "z10_super_E1")])
3553 (define_insn "*r<noxa>sbg_<mode>_noshift"
3554 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3555 (IXOR:GPR
3556 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3557 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3558 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3559 (clobber (reg:CC CC_REGNUM))]
3560 "TARGET_Z10"
3561 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3562 [(set_attr "op_type" "RIE")])
3564 (define_insn "*r<noxa>sbg_di_rotl"
3565 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3566 (IXOR:DI
3567 (and:DI
3568 (rotate:DI
3569 (match_operand:DI 1 "nonimmediate_operand" "d")
3570 (match_operand:DI 3 "const_int_operand" ""))
3571 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3572 (match_operand:DI 4 "nonimmediate_operand" "0")))
3573 (clobber (reg:CC CC_REGNUM))]
3574 "TARGET_Z10"
3575 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3576 [(set_attr "op_type" "RIE")])
3578 (define_insn "*r<noxa>sbg_<mode>_srl"
3579 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3580 (IXOR:GPR
3581 (and:GPR
3582 (lshiftrt:GPR
3583 (match_operand:GPR 1 "nonimmediate_operand" "d")
3584 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3585 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3586 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3587 (clobber (reg:CC CC_REGNUM))]
3588 "TARGET_Z10
3589 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
3590 INTVAL (operands[2]))"
3591 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
3592 [(set_attr "op_type" "RIE")])
3594 (define_insn "*r<noxa>sbg_<mode>_sll"
3595 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3596 (IXOR:GPR
3597 (and:GPR
3598 (ashift:GPR
3599 (match_operand:GPR 1 "nonimmediate_operand" "d")
3600 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3601 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3602 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3603 (clobber (reg:CC CC_REGNUM))]
3604 "TARGET_Z10
3605 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
3606 INTVAL (operands[2]))"
3607 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
3608 [(set_attr "op_type" "RIE")])
3610 ;; These two are generated by combine for s.bf &= val.
3611 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
3612 ;; shifts and ands, which results in some truly awful patterns
3613 ;; including subregs of operations. Rather unnecessisarily, IMO.
3614 ;; Instead of
3615 ;;
3616 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3617 ;; (const_int 24 [0x18])
3618 ;; (const_int 0 [0]))
3619 ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
3620 ;; (const_int 40 [0x28])) 4)
3621 ;; (reg:SI 4 %r4 [ y+4 ])) 0))
3622 ;;
3623 ;; we should instead generate
3624 ;;
3625 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3626 ;; (const_int 24 [0x18])
3627 ;; (const_int 0 [0]))
3628 ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
3629 ;; (const_int 40 [0x28]))
3630 ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
3631 ;;
3632 ;; by noticing that we can push down the outer paradoxical subreg
3633 ;; into the operation.
3635 (define_insn "*insv_rnsbg_noshift"
3636 [(set (zero_extract:DI
3637 (match_operand:DI 0 "nonimmediate_operand" "+d")
3638 (match_operand 1 "const_int_operand" "")
3639 (match_operand 2 "const_int_operand" ""))
3640 (and:DI
3641 (match_dup 0)
3642 (match_operand:DI 3 "nonimmediate_operand" "d")))
3643 (clobber (reg:CC CC_REGNUM))]
3644 "TARGET_Z10
3645 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
3646 "rnsbg\t%0,%3,%2,63,0"
3647 [(set_attr "op_type" "RIE")])
3649 (define_insn "*insv_rnsbg_srl"
3650 [(set (zero_extract:DI
3651 (match_operand:DI 0 "nonimmediate_operand" "+d")
3652 (match_operand 1 "const_int_operand" "")
3653 (match_operand 2 "const_int_operand" ""))
3654 (and:DI
3655 (lshiftrt:DI
3656 (match_dup 0)
3657 (match_operand 3 "const_int_operand" ""))
3658 (match_operand:DI 4 "nonimmediate_operand" "d")))
3659 (clobber (reg:CC CC_REGNUM))]
3660 "TARGET_Z10
3661 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
3662 "rnsbg\t%0,%4,%2,%2+%1-1,%3"
3663 [(set_attr "op_type" "RIE")])
3665 (define_insn "*insv<mode>_mem_reg"
3666 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3667 (match_operand 1 "const_int_operand" "n,n")
3668 (const_int 0))
3669 (match_operand:W 2 "register_operand" "d,d"))]
3670 "INTVAL (operands[1]) > 0
3671 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3672 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3673 {
3674 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3676 operands[1] = GEN_INT ((1ul << size) - 1);
3677 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3678 : "stcmy\t%2,%1,%S0";
3679 }
3680 [(set_attr "op_type" "RS,RSY")
3681 (set_attr "z10prop" "z10_super,z10_super")])
3683 (define_insn "*insvdi_mem_reghigh"
3684 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3685 (match_operand 1 "const_int_operand" "n")
3686 (const_int 0))
3687 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3688 (const_int 32)))]
3689 "TARGET_ZARCH
3690 && INTVAL (operands[1]) > 0
3691 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3692 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3693 {
3694 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3696 operands[1] = GEN_INT ((1ul << size) - 1);
3697 return "stcmh\t%2,%1,%S0";
3698 }
3699 [(set_attr "op_type" "RSY")
3700 (set_attr "z10prop" "z10_super")])
3702 (define_insn "*insvdi_reg_imm"
3703 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3704 (const_int 16)
3705 (match_operand 1 "const_int_operand" "n"))
3706 (match_operand:DI 2 "const_int_operand" "n"))]
3707 "TARGET_ZARCH
3708 && INTVAL (operands[1]) >= 0
3709 && INTVAL (operands[1]) < BITS_PER_WORD
3710 && INTVAL (operands[1]) % 16 == 0"
3711 {
3712 switch (BITS_PER_WORD - INTVAL (operands[1]))
3713 {
3714 case 64: return "iihh\t%0,%x2"; break;
3715 case 48: return "iihl\t%0,%x2"; break;
3716 case 32: return "iilh\t%0,%x2"; break;
3717 case 16: return "iill\t%0,%x2"; break;
3718 default: gcc_unreachable();
3719 }
3720 }
3721 [(set_attr "op_type" "RI")
3722 (set_attr "z10prop" "z10_super_E1")])
3724 ; Update the left-most 32 bit of a DI.
3725 (define_insn "*insv_h_di_reg_extimm"
3726 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3727 (const_int 32)
3728 (const_int 0))
3729 (match_operand:DI 1 "const_int_operand" "n"))]
3730 "TARGET_EXTIMM"
3731 "iihf\t%0,%o1"
3732 [(set_attr "op_type" "RIL")
3733 (set_attr "z10prop" "z10_fwd_E1")])
3735 ; Update the right-most 32 bit of a DI.
3736 (define_insn "*insv_l_di_reg_extimm"
3737 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3738 (const_int 32)
3739 (const_int 32))
3740 (match_operand:DI 1 "const_int_operand" "n"))]
3741 "TARGET_EXTIMM"
3742 "iilf\t%0,%o1"
3743 [(set_attr "op_type" "RIL")
3744 (set_attr "z10prop" "z10_fwd_A1")])
3746 ;
3747 ; extendsidi2 instruction pattern(s).
3748 ;
3750 (define_expand "extendsidi2"
3751 [(set (match_operand:DI 0 "register_operand" "")
3752 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3753 ""
3754 {
3755 if (!TARGET_ZARCH)
3756 {
3757 emit_clobber (operands[0]);
3758 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3759 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3760 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3761 DONE;
3762 }
3763 })
3765 (define_insn "*extendsidi2"
3766 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3767 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3768 "TARGET_ZARCH"
3769 "@
3770 lgfr\t%0,%1
3771 lgf\t%0,%1
3772 lgfrl\t%0,%1"
3773 [(set_attr "op_type" "RRE,RXY,RIL")
3774 (set_attr "type" "*,*,larl")
3775 (set_attr "cpu_facility" "*,*,z10")
3776 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3778 ;
3779 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3780 ;
3782 (define_expand "extend<HQI:mode><DSI:mode>2"
3783 [(set (match_operand:DSI 0 "register_operand" "")
3784 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3785 ""
3786 {
3787 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3788 {
3789 rtx tmp = gen_reg_rtx (SImode);
3790 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3791 emit_insn (gen_extendsidi2 (operands[0], tmp));
3792 DONE;
3793 }
3794 else if (!TARGET_EXTIMM)
3795 {
3796 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
3798 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3799 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3800 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3801 DONE;
3802 }
3803 })
3805 ;
3806 ; extendhidi2 instruction pattern(s).
3807 ;
3809 (define_insn "*extendhidi2_extimm"
3810 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3811 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3812 "TARGET_ZARCH && TARGET_EXTIMM"
3813 "@
3814 lghr\t%0,%1
3815 lgh\t%0,%1
3816 lghrl\t%0,%1"
3817 [(set_attr "op_type" "RRE,RXY,RIL")
3818 (set_attr "type" "*,*,larl")
3819 (set_attr "cpu_facility" "extimm,extimm,z10")
3820 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3822 (define_insn "*extendhidi2"
3823 [(set (match_operand:DI 0 "register_operand" "=d")
3824 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3825 "TARGET_ZARCH"
3826 "lgh\t%0,%1"
3827 [(set_attr "op_type" "RXY")
3828 (set_attr "z10prop" "z10_super_E1")])
3830 ;
3831 ; extendhisi2 instruction pattern(s).
3832 ;
3834 (define_insn "*extendhisi2_extimm"
3835 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3836 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3837 "TARGET_EXTIMM"
3838 "@
3839 lhr\t%0,%1
3840 lh\t%0,%1
3841 lhy\t%0,%1
3842 lhrl\t%0,%1"
3843 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3844 (set_attr "type" "*,*,*,larl")
3845 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3846 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3848 (define_insn "*extendhisi2"
3849 [(set (match_operand:SI 0 "register_operand" "=d,d")
3850 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3851 "!TARGET_EXTIMM"
3852 "@
3853 lh\t%0,%1
3854 lhy\t%0,%1"
3855 [(set_attr "op_type" "RX,RXY")
3856 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3858 ;
3859 ; extendqi(si|di)2 instruction pattern(s).
3860 ;
3862 ; lbr, lgbr, lb, lgb
3863 (define_insn "*extendqi<mode>2_extimm"
3864 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3865 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3866 "TARGET_EXTIMM"
3867 "@
3868 l<g>br\t%0,%1
3869 l<g>b\t%0,%1"
3870 [(set_attr "op_type" "RRE,RXY")
3871 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3873 ; lb, lgb
3874 (define_insn "*extendqi<mode>2"
3875 [(set (match_operand:GPR 0 "register_operand" "=d")
3876 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3877 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3878 "l<g>b\t%0,%1"
3879 [(set_attr "op_type" "RXY")
3880 (set_attr "z10prop" "z10_super_E1")])
3882 (define_insn_and_split "*extendqi<mode>2_short_displ"
3883 [(set (match_operand:GPR 0 "register_operand" "=d")
3884 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3885 (clobber (reg:CC CC_REGNUM))]
3886 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3887 "#"
3888 "&& reload_completed"
3889 [(parallel
3890 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3891 (clobber (reg:CC CC_REGNUM))])
3892 (parallel
3893 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3894 (clobber (reg:CC CC_REGNUM))])]
3895 {
3896 operands[1] = adjust_address (operands[1], BLKmode, 0);
3897 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
3898 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
3899 })
3901 ;
3902 ; zero_extendsidi2 instruction pattern(s).
3903 ;
3905 (define_expand "zero_extendsidi2"
3906 [(set (match_operand:DI 0 "register_operand" "")
3907 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3908 ""
3909 {
3910 if (!TARGET_ZARCH)
3911 {
3912 emit_clobber (operands[0]);
3913 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3914 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3915 DONE;
3916 }
3917 })
3919 (define_insn "*zero_extendsidi2"
3920 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3921 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3922 "TARGET_ZARCH"
3923 "@
3924 llgfr\t%0,%1
3925 llgf\t%0,%1
3926 llgfrl\t%0,%1"
3927 [(set_attr "op_type" "RRE,RXY,RIL")
3928 (set_attr "type" "*,*,larl")
3929 (set_attr "cpu_facility" "*,*,z10")
3930 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3932 ;
3933 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3934 ;
3936 (define_insn "*llgt_sidi"
3937 [(set (match_operand:DI 0 "register_operand" "=d")
3938 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3939 (const_int 2147483647)))]
3940 "TARGET_ZARCH"
3941 "llgt\t%0,%1"
3942 [(set_attr "op_type" "RXE")
3943 (set_attr "z10prop" "z10_super_E1")])
3945 (define_insn_and_split "*llgt_sidi_split"
3946 [(set (match_operand:DI 0 "register_operand" "=d")
3947 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3948 (const_int 2147483647)))
3949 (clobber (reg:CC CC_REGNUM))]
3950 "TARGET_ZARCH"
3951 "#"
3952 "&& reload_completed"
3953 [(set (match_dup 0)
3954 (and:DI (subreg:DI (match_dup 1) 0)
3955 (const_int 2147483647)))]
3956 "")
3958 (define_insn "*llgt_sisi"
3959 [(set (match_operand:SI 0 "register_operand" "=d,d")
3960 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3961 (const_int 2147483647)))]
3962 "TARGET_ZARCH"
3963 "@
3964 llgtr\t%0,%1
3965 llgt\t%0,%1"
3966 [(set_attr "op_type" "RRE,RXE")
3967 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3969 (define_insn "*llgt_didi"
3970 [(set (match_operand:DI 0 "register_operand" "=d,d")
3971 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3972 (const_int 2147483647)))]
3973 "TARGET_ZARCH"
3974 "@
3975 llgtr\t%0,%1
3976 llgt\t%0,%N1"
3977 [(set_attr "op_type" "RRE,RXE")
3978 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3980 (define_split
3981 [(set (match_operand:DSI 0 "register_operand" "")
3982 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
3983 (const_int 2147483647)))
3984 (clobber (reg:CC CC_REGNUM))]
3985 "TARGET_ZARCH && reload_completed"
3986 [(set (match_dup 0)
3987 (and:DSI (match_dup 1)
3988 (const_int 2147483647)))]
3989 "")
3991 ;
3992 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3993 ;
3995 (define_expand "zero_extend<mode>di2"
3996 [(set (match_operand:DI 0 "register_operand" "")
3997 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3998 ""
3999 {
4000 if (!TARGET_ZARCH)
4001 {
4002 rtx tmp = gen_reg_rtx (SImode);
4003 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
4004 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
4005 DONE;
4006 }
4007 else if (!TARGET_EXTIMM)
4008 {
4009 rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
4010 operands[1] = gen_lowpart (DImode, operands[1]);
4011 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4012 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4013 DONE;
4014 }
4015 })
4017 (define_expand "zero_extend<mode>si2"
4018 [(set (match_operand:SI 0 "register_operand" "")
4019 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4020 ""
4021 {
4022 if (!TARGET_EXTIMM)
4023 {
4024 operands[1] = gen_lowpart (SImode, operands[1]);
4025 emit_insn (gen_andsi3 (operands[0], operands[1],
4026 GEN_INT ((1 << <HQI:bitsize>) - 1)));
4027 DONE;
4028 }
4029 })
4031 ; llhrl, llghrl
4032 (define_insn "*zero_extendhi<mode>2_z10"
4033 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4034 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
4035 "TARGET_Z10"
4036 "@
4037 ll<g>hr\t%0,%1
4038 ll<g>h\t%0,%1
4039 ll<g>hrl\t%0,%1"
4040 [(set_attr "op_type" "RXY,RRE,RIL")
4041 (set_attr "type" "*,*,larl")
4042 (set_attr "cpu_facility" "*,*,z10")
4043 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4045 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4046 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4047 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4048 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
4049 "TARGET_EXTIMM"
4050 "@
4051 ll<g><hc>r\t%0,%1
4052 ll<g><hc>\t%0,%1"
4053 [(set_attr "op_type" "RRE,RXY")
4054 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4056 ; llgh, llgc
4057 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4058 [(set (match_operand:GPR 0 "register_operand" "=d")
4059 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
4060 "TARGET_ZARCH && !TARGET_EXTIMM"
4061 "llg<hc>\t%0,%1"
4062 [(set_attr "op_type" "RXY")
4063 (set_attr "z10prop" "z10_fwd_A3")])
4065 (define_insn_and_split "*zero_extendhisi2_31"
4066 [(set (match_operand:SI 0 "register_operand" "=&d")
4067 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
4068 (clobber (reg:CC CC_REGNUM))]
4069 "!TARGET_ZARCH"
4070 "#"
4071 "&& reload_completed"
4072 [(set (match_dup 0) (const_int 0))
4073 (parallel
4074 [(set (strict_low_part (match_dup 2)) (match_dup 1))
4075 (clobber (reg:CC CC_REGNUM))])]
4076 "operands[2] = gen_lowpart (HImode, operands[0]);")
4078 (define_insn_and_split "*zero_extendqisi2_31"
4079 [(set (match_operand:SI 0 "register_operand" "=&d")
4080 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
4081 "!TARGET_ZARCH"
4082 "#"
4083 "&& reload_completed"
4084 [(set (match_dup 0) (const_int 0))
4085 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4086 "operands[2] = gen_lowpart (QImode, operands[0]);")
4088 ;
4089 ; zero_extendqihi2 instruction pattern(s).
4090 ;
4092 (define_expand "zero_extendqihi2"
4093 [(set (match_operand:HI 0 "register_operand" "")
4094 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4095 "TARGET_ZARCH && !TARGET_EXTIMM"
4096 {
4097 operands[1] = gen_lowpart (HImode, operands[1]);
4098 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4099 DONE;
4100 })
4102 (define_insn "*zero_extendqihi2_64"
4103 [(set (match_operand:HI 0 "register_operand" "=d")
4104 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4105 "TARGET_ZARCH && !TARGET_EXTIMM"
4106 "llgc\t%0,%1"
4107 [(set_attr "op_type" "RXY")
4108 (set_attr "z10prop" "z10_fwd_A3")])
4110 (define_insn_and_split "*zero_extendqihi2_31"
4111 [(set (match_operand:HI 0 "register_operand" "=&d")
4112 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4113 "!TARGET_ZARCH"
4114 "#"
4115 "&& reload_completed"
4116 [(set (match_dup 0) (const_int 0))
4117 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4118 "operands[2] = gen_lowpart (QImode, operands[0]);")
4120 ;
4121 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4122 ;
4124 (define_expand "fixuns_truncdddi2"
4125 [(parallel
4126 [(set (match_operand:DI 0 "register_operand" "")
4127 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4128 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4129 (clobber (reg:CC CC_REGNUM))])]
4131 "TARGET_HARD_DFP"
4132 {
4133 if (!TARGET_Z196)
4134 {
4135 rtx_code_label *label1 = gen_label_rtx ();
4136 rtx_code_label *label2 = gen_label_rtx ();
4137 rtx temp = gen_reg_rtx (TDmode);
4138 REAL_VALUE_TYPE cmp, sub;
4140 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4141 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4143 /* 2^63 can't be represented as 64bit DFP number with full precision. The
4144 solution is doing the check and the subtraction in TD mode and using a
4145 TD -> DI convert afterwards. */
4146 emit_insn (gen_extendddtd2 (temp, operands[1]));
4147 temp = force_reg (TDmode, temp);
4148 emit_cmp_and_jump_insns (temp,
4149 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4150 LT, NULL_RTX, VOIDmode, 0, label1);
4151 emit_insn (gen_subtd3 (temp, temp,
4152 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4153 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4154 emit_jump (label2);
4156 emit_label (label1);
4157 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4158 emit_label (label2);
4159 DONE;
4160 }
4161 })
4163 (define_expand "fixuns_trunctddi2"
4164 [(parallel
4165 [(set (match_operand:DI 0 "register_operand" "")
4166 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4167 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4168 (clobber (reg:CC CC_REGNUM))])]
4170 "TARGET_HARD_DFP"
4171 {
4172 if (!TARGET_Z196)
4173 {
4174 rtx_code_label *label1 = gen_label_rtx ();
4175 rtx_code_label *label2 = gen_label_rtx ();
4176 rtx temp = gen_reg_rtx (TDmode);
4177 REAL_VALUE_TYPE cmp, sub;
4179 operands[1] = force_reg (TDmode, operands[1]);
4180 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4181 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4183 emit_cmp_and_jump_insns (operands[1],
4184 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4185 LT, NULL_RTX, VOIDmode, 0, label1);
4186 emit_insn (gen_subtd3 (temp, operands[1],
4187 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4188 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4189 emit_jump (label2);
4191 emit_label (label1);
4192 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4193 emit_label (label2);
4194 DONE;
4195 }
4196 })
4198 ;
4199 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4200 ; instruction pattern(s).
4201 ;
4203 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4204 [(parallel
4205 [(set (match_operand:GPR 0 "register_operand" "")
4206 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4207 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4208 (clobber (reg:CC CC_REGNUM))])]
4209 "TARGET_HARD_FLOAT"
4210 {
4211 if (!TARGET_Z196)
4212 {
4213 rtx_code_label *label1 = gen_label_rtx ();
4214 rtx_code_label *label2 = gen_label_rtx ();
4215 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4216 REAL_VALUE_TYPE cmp, sub;
4218 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4219 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4220 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4222 emit_cmp_and_jump_insns (operands[1],
4223 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
4224 LT, NULL_RTX, VOIDmode, 0, label1);
4225 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4226 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
4227 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4228 GEN_INT (7)));
4229 emit_jump (label2);
4231 emit_label (label1);
4232 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4233 operands[1], GEN_INT (5)));
4234 emit_label (label2);
4235 DONE;
4236 }
4237 })
4239 ; fixuns_trunc(td|dd)si2 expander
4240 (define_expand "fixuns_trunc<mode>si2"
4241 [(parallel
4242 [(set (match_operand:SI 0 "register_operand" "")
4243 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4244 (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4245 (clobber (reg:CC CC_REGNUM))])]
4246 "TARGET_Z196 && TARGET_HARD_DFP"
4247 "")
4249 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4251 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4252 ; clfdtr, clfxtr, clgdtr, clgxtr
4253 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4254 [(set (match_operand:GPR 0 "register_operand" "=r")
4255 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4256 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4257 (clobber (reg:CC CC_REGNUM))]
4258 "TARGET_Z196"
4259 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4260 [(set_attr "op_type" "RRF")
4261 (set_attr "type" "ftoi")])
4263 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4264 [(set (match_operand:GPR 0 "register_operand" "")
4265 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4266 "TARGET_HARD_FLOAT"
4267 {
4268 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4269 GEN_INT (5)));
4270 DONE;
4271 })
4273 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4274 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4275 [(set (match_operand:GPR 0 "register_operand" "=d")
4276 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4277 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4278 (clobber (reg:CC CC_REGNUM))]
4279 "TARGET_HARD_FLOAT"
4280 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4281 [(set_attr "op_type" "RRE")
4282 (set_attr "type" "ftoi")])
4285 ;
4286 ; fix_trunc(td|dd)di2 instruction pattern(s).
4287 ;
4289 (define_expand "fix_trunc<mode>di2"
4290 [(set (match_operand:DI 0 "register_operand" "")
4291 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4292 "TARGET_ZARCH && TARGET_HARD_DFP"
4293 {
4294 operands[1] = force_reg (<MODE>mode, operands[1]);
4295 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4296 GEN_INT (9)));
4297 DONE;
4298 })
4300 ; cgxtr, cgdtr
4301 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4302 [(set (match_operand:DI 0 "register_operand" "=d")
4303 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4304 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4305 (clobber (reg:CC CC_REGNUM))]
4306 "TARGET_ZARCH && TARGET_HARD_DFP"
4307 "cg<DFP:xde>tr\t%0,%h2,%1"
4308 [(set_attr "op_type" "RRF")
4309 (set_attr "type" "ftoidfp")])
4312 ;
4313 ; fix_trunctf(si|di)2 instruction pattern(s).
4314 ;
4316 (define_expand "fix_trunctf<mode>2"
4317 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4318 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4319 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4320 (clobber (reg:CC CC_REGNUM))])]
4321 "TARGET_HARD_FLOAT"
4322 "")
4325 ;
4326 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4327 ;
4329 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4330 (define_insn "floatdi<mode>2"
4331 [(set (match_operand:FP 0 "register_operand" "=f")
4332 (float:FP (match_operand:DI 1 "register_operand" "d")))]
4333 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4334 "c<xde>g<bt>r\t%0,%1"
4335 [(set_attr "op_type" "RRE")
4336 (set_attr "type" "itof<mode>" )])
4338 ; cxfbr, cdfbr, cefbr
4339 (define_insn "floatsi<mode>2"
4340 [(set (match_operand:BFP 0 "register_operand" "=f")
4341 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4342 "TARGET_HARD_FLOAT"
4343 "c<xde>fbr\t%0,%1"
4344 [(set_attr "op_type" "RRE")
4345 (set_attr "type" "itof<mode>" )])
4347 ; cxftr, cdftr
4348 (define_insn "floatsi<mode>2"
4349 [(set (match_operand:DFP 0 "register_operand" "=f")
4350 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4351 "TARGET_Z196 && TARGET_HARD_FLOAT"
4352 "c<xde>ftr\t%0,0,%1,0"
4353 [(set_attr "op_type" "RRE")
4354 (set_attr "type" "itof<mode>" )])
4356 ;
4357 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4358 ;
4360 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4361 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4362 (define_insn "floatuns<GPR:mode><FP:mode>2"
4363 [(set (match_operand:FP 0 "register_operand" "=f")
4364 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4365 "TARGET_Z196 && TARGET_HARD_FLOAT"
4366 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4367 [(set_attr "op_type" "RRE")
4368 (set_attr "type" "itof<FP:mode>" )])
4370 ;
4371 ; truncdfsf2 instruction pattern(s).
4372 ;
4374 (define_insn "truncdfsf2"
4375 [(set (match_operand:SF 0 "register_operand" "=f")
4376 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4377 "TARGET_HARD_FLOAT"
4378 "ledbr\t%0,%1"
4379 [(set_attr "op_type" "RRE")
4380 (set_attr "type" "ftruncdf")])
4382 ;
4383 ; trunctf(df|sf)2 instruction pattern(s).
4384 ;
4386 ; ldxbr, lexbr
4387 (define_insn "trunctf<mode>2"
4388 [(set (match_operand:DSF 0 "register_operand" "=f")
4389 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4390 (clobber (match_scratch:TF 2 "=f"))]
4391 "TARGET_HARD_FLOAT"
4392 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4393 [(set_attr "length" "6")
4394 (set_attr "type" "ftrunctf")])
4396 ;
4397 ; trunctddd2 and truncddsd2 instruction pattern(s).
4398 ;
4400 (define_insn "trunctddd2"
4401 [(set (match_operand:DD 0 "register_operand" "=f")
4402 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4403 (clobber (match_scratch:TD 2 "=f"))]
4404 "TARGET_HARD_DFP"
4405 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4406 [(set_attr "length" "6")
4407 (set_attr "type" "ftruncdd")])
4409 (define_insn "truncddsd2"
4410 [(set (match_operand:SD 0 "register_operand" "=f")
4411 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4412 "TARGET_HARD_DFP"
4413 "ledtr\t%0,0,%1,0"
4414 [(set_attr "op_type" "RRF")
4415 (set_attr "type" "ftruncsd")])
4417 (define_expand "trunctdsd2"
4418 [(parallel
4419 [(set (match_dup 3)
4420 (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
4421 (clobber (match_scratch:TD 2 ""))])
4422 (set (match_operand:SD 0 "register_operand" "")
4423 (float_truncate:SD (match_dup 3)))]
4424 "TARGET_HARD_DFP"
4425 {
4426 operands[3] = gen_reg_rtx (DDmode);
4427 })
4429 ;
4430 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4431 ;
4433 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4434 (define_insn "extend<DSF:mode><BFP:mode>2"
4435 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4436 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4437 "TARGET_HARD_FLOAT
4438 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4439 "@
4440 l<BFP:xde><DSF:xde>br\t%0,%1
4441 l<BFP:xde><DSF:xde>b\t%0,%1"
4442 [(set_attr "op_type" "RRE,RXE")
4443 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4445 ;
4446 ; extendddtd2 and extendsddd2 instruction pattern(s).
4447 ;
4449 (define_insn "extendddtd2"
4450 [(set (match_operand:TD 0 "register_operand" "=f")
4451 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4452 "TARGET_HARD_DFP"
4453 "lxdtr\t%0,%1,0"
4454 [(set_attr "op_type" "RRF")
4455 (set_attr "type" "fsimptf")])
4457 (define_insn "extendsddd2"
4458 [(set (match_operand:DD 0 "register_operand" "=f")
4459 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4460 "TARGET_HARD_DFP"
4461 "ldetr\t%0,%1,0"
4462 [(set_attr "op_type" "RRF")
4463 (set_attr "type" "fsimptf")])
4465 (define_expand "extendsdtd2"
4466 [(set (match_dup 2)
4467 (float_extend:DD (match_operand:SD 1 "register_operand" "")))
4468 (set (match_operand:TD 0 "register_operand" "")
4469 (float_extend:TD (match_dup 2)))]
4470 "TARGET_HARD_DFP"
4471 {
4472 operands[2] = gen_reg_rtx (DDmode);
4473 })
4475 ; Binary Floating Point - load fp integer
4477 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
4478 ; For all of them the inexact exceptions are suppressed.
4480 ; fiebra, fidbra, fixbra
4481 (define_insn "<FPINT:fpint_name><BFP:mode>2"
4482 [(set (match_operand:BFP 0 "register_operand" "=f")
4483 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4484 FPINT))]
4485 "TARGET_Z196"
4486 "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
4487 [(set_attr "op_type" "RRF")
4488 (set_attr "type" "fsimp<BFP:mode>")])
4490 ; rint is supposed to raise an inexact exception so we can use the
4491 ; older instructions.
4493 ; fiebr, fidbr, fixbr
4494 (define_insn "rint<BFP:mode>2"
4495 [(set (match_operand:BFP 0 "register_operand" "=f")
4496 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4497 UNSPEC_FPINT_RINT))]
4498 ""
4499 "fi<BFP:xde>br\t%0,0,%1"
4500 [(set_attr "op_type" "RRF")
4501 (set_attr "type" "fsimp<BFP:mode>")])
4504 ; Decimal Floating Point - load fp integer
4506 ; fidtr, fixtr
4507 (define_insn "<FPINT:fpint_name><DFP:mode>2"
4508 [(set (match_operand:DFP 0 "register_operand" "=f")
4509 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4510 FPINT))]
4511 "TARGET_HARD_DFP"
4512 "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
4513 [(set_attr "op_type" "RRF")
4514 (set_attr "type" "fsimp<DFP:mode>")])
4516 ; fidtr, fixtr
4517 (define_insn "rint<DFP:mode>2"
4518 [(set (match_operand:DFP 0 "register_operand" "=f")
4519 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4520 UNSPEC_FPINT_RINT))]
4521 "TARGET_HARD_DFP"
4522 "fi<DFP:xde>tr\t%0,0,%1,0"
4523 [(set_attr "op_type" "RRF")
4524 (set_attr "type" "fsimp<DFP:mode>")])
4526 ;
4527 ; Binary <-> Decimal floating point trunc patterns
4528 ;
4530 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4531 [(set (reg:DFP_ALL FPR0_REGNUM)
4532 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4533 (use (reg:SI GPR0_REGNUM))
4534 (clobber (reg:CC CC_REGNUM))]
4535 "TARGET_HARD_DFP"
4536 "pfpo")
4538 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4539 [(set (reg:BFP FPR0_REGNUM)
4540 (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4541 (use (reg:SI GPR0_REGNUM))
4542 (clobber (reg:CC CC_REGNUM))]
4543 "TARGET_HARD_DFP"
4544 "pfpo")
4546 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4547 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4548 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4549 (parallel
4550 [(set (reg:DFP_ALL FPR0_REGNUM)
4551 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4552 (use (reg:SI GPR0_REGNUM))
4553 (clobber (reg:CC CC_REGNUM))])
4554 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4555 (reg:DFP_ALL FPR0_REGNUM))]
4556 "TARGET_HARD_DFP
4557 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4558 {
4559 HOST_WIDE_INT flags;
4561 flags = (PFPO_CONVERT |
4562 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4563 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4565 operands[2] = GEN_INT (flags);
4566 })
4568 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4569 [(set (reg:DFP_ALL FPR4_REGNUM)
4570 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4571 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4572 (parallel
4573 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4574 (use (reg:SI GPR0_REGNUM))
4575 (clobber (reg:CC CC_REGNUM))])
4576 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4577 "TARGET_HARD_DFP
4578 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4579 {
4580 HOST_WIDE_INT flags;
4582 flags = (PFPO_CONVERT |
4583 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4584 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4586 operands[2] = GEN_INT (flags);
4587 })
4589 ;
4590 ; Binary <-> Decimal floating point extend patterns
4591 ;
4593 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4594 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4595 (use (reg:SI GPR0_REGNUM))
4596 (clobber (reg:CC CC_REGNUM))]
4597 "TARGET_HARD_DFP"
4598 "pfpo")
4600 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4601 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
4602 (use (reg:SI GPR0_REGNUM))
4603 (clobber (reg:CC CC_REGNUM))]
4604 "TARGET_HARD_DFP"
4605 "pfpo")
4607 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4608 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4609 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4610 (parallel
4611 [(set (reg:DFP_ALL FPR0_REGNUM)
4612 (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4613 (use (reg:SI GPR0_REGNUM))
4614 (clobber (reg:CC CC_REGNUM))])
4615 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4616 (reg:DFP_ALL FPR0_REGNUM))]
4617 "TARGET_HARD_DFP
4618 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4619 {
4620 HOST_WIDE_INT flags;
4622 flags = (PFPO_CONVERT |
4623 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4624 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4626 operands[2] = GEN_INT (flags);
4627 })
4629 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4630 [(set (reg:DFP_ALL FPR4_REGNUM)
4631 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4632 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4633 (parallel
4634 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
4635 (use (reg:SI GPR0_REGNUM))
4636 (clobber (reg:CC CC_REGNUM))])
4637 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4638 "TARGET_HARD_DFP
4639 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4640 {
4641 HOST_WIDE_INT flags;
4643 flags = (PFPO_CONVERT |
4644 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4645 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4647 operands[2] = GEN_INT (flags);
4648 })
4651 ;;
4652 ;; ARITHMETIC OPERATIONS
4653 ;;
4654 ; arithmetic operations set the ConditionCode,
4655 ; because of unpredictable Bits in Register for Halfword and Byte
4656 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4658 ;;
4659 ;;- Add instructions.
4660 ;;
4662 ;
4663 ; addti3 instruction pattern(s).
4664 ;
4666 (define_insn_and_split "addti3"
4667 [(set (match_operand:TI 0 "register_operand" "=&d")
4668 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4669 (match_operand:TI 2 "general_operand" "do") ) )
4670 (clobber (reg:CC CC_REGNUM))]
4671 "TARGET_ZARCH"
4672 "#"
4673 "&& reload_completed"
4674 [(parallel
4675 [(set (reg:CCL1 CC_REGNUM)
4676 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4677 (match_dup 7)))
4678 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4679 (parallel
4680 [(set (match_dup 3) (plus:DI
4681 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4682 (match_dup 4)) (match_dup 5)))
4683 (clobber (reg:CC CC_REGNUM))])]
4684 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4685 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4686 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4687 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4688 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4689 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4691 ;
4692 ; adddi3 instruction pattern(s).
4693 ;
4695 (define_expand "adddi3"
4696 [(parallel
4697 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4698 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4699 (match_operand:DI 2 "general_operand" "")))
4700 (clobber (reg:CC CC_REGNUM))])]
4701 ""
4702 "")
4704 (define_insn "*adddi3_sign"
4705 [(set (match_operand:DI 0 "register_operand" "=d,d")
4706 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4707 (match_operand:DI 1 "register_operand" "0,0")))
4708 (clobber (reg:CC CC_REGNUM))]
4709 "TARGET_ZARCH"
4710 "@
4711 agfr\t%0,%2
4712 agf\t%0,%2"
4713 [(set_attr "op_type" "RRE,RXY")
4714 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4716 (define_insn "*adddi3_zero_cc"
4717 [(set (reg CC_REGNUM)
4718 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4719 (match_operand:DI 1 "register_operand" "0,0"))
4720 (const_int 0)))
4721 (set (match_operand:DI 0 "register_operand" "=d,d")
4722 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4723 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4724 "@
4725 algfr\t%0,%2
4726 algf\t%0,%2"
4727 [(set_attr "op_type" "RRE,RXY")
4728 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4730 (define_insn "*adddi3_zero_cconly"
4731 [(set (reg CC_REGNUM)
4732 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4733 (match_operand:DI 1 "register_operand" "0,0"))
4734 (const_int 0)))
4735 (clobber (match_scratch:DI 0 "=d,d"))]
4736 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4737 "@
4738 algfr\t%0,%2
4739 algf\t%0,%2"
4740 [(set_attr "op_type" "RRE,RXY")
4741 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4743 (define_insn "*adddi3_zero"
4744 [(set (match_operand:DI 0 "register_operand" "=d,d")
4745 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4746 (match_operand:DI 1 "register_operand" "0,0")))
4747 (clobber (reg:CC CC_REGNUM))]
4748 "TARGET_ZARCH"
4749 "@
4750 algfr\t%0,%2
4751 algf\t%0,%2"
4752 [(set_attr "op_type" "RRE,RXY")
4753 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4755 (define_insn_and_split "*adddi3_31z"
4756 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4757 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4758 (match_operand:DI 2 "general_operand" "do") ) )
4759 (clobber (reg:CC CC_REGNUM))]
4760 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4761 "#"
4762 "&& reload_completed"
4763 [(parallel
4764 [(set (reg:CCL1 CC_REGNUM)
4765 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4766 (match_dup 7)))
4767 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4768 (parallel
4769 [(set (match_dup 3) (plus:SI
4770 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4771 (match_dup 4)) (match_dup 5)))
4772 (clobber (reg:CC CC_REGNUM))])]
4773 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4774 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4775 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4776 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4777 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4778 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4780 (define_insn_and_split "*adddi3_31"
4781 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4782 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4783 (match_operand:DI 2 "general_operand" "do") ) )
4784 (clobber (reg:CC CC_REGNUM))]
4785 "!TARGET_CPU_ZARCH"
4786 "#"
4787 "&& reload_completed"
4788 [(parallel
4789 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4790 (clobber (reg:CC CC_REGNUM))])
4791 (parallel
4792 [(set (reg:CCL1 CC_REGNUM)
4793 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4794 (match_dup 7)))
4795 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4796 (set (pc)
4797 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4798 (pc)
4799 (label_ref (match_dup 9))))
4800 (parallel
4801 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4802 (clobber (reg:CC CC_REGNUM))])
4803 (match_dup 9)]
4804 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4805 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4806 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4807 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4808 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4809 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4810 operands[9] = gen_label_rtx ();")
4812 ;
4813 ; addsi3 instruction pattern(s).
4814 ;
4816 (define_expand "addsi3"
4817 [(parallel
4818 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4819 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4820 (match_operand:SI 2 "general_operand" "")))
4821 (clobber (reg:CC CC_REGNUM))])]
4822 ""
4823 "")
4825 (define_insn "*addsi3_sign"
4826 [(set (match_operand:SI 0 "register_operand" "=d,d")
4827 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4828 (match_operand:SI 1 "register_operand" "0,0")))
4829 (clobber (reg:CC CC_REGNUM))]
4830 ""
4831 "@
4832 ah\t%0,%2
4833 ahy\t%0,%2"
4834 [(set_attr "op_type" "RX,RXY")
4835 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4837 ;
4838 ; add(di|si)3 instruction pattern(s).
4839 ;
4841 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4842 (define_insn "*add<mode>3"
4843 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
4844 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
4845 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
4846 (clobber (reg:CC CC_REGNUM))]
4847 ""
4848 "@
4849 a<g>r\t%0,%2
4850 a<g>rk\t%0,%1,%2
4851 a<g>hi\t%0,%h2
4852 a<g>hik\t%0,%1,%h2
4853 al<g>fi\t%0,%2
4854 sl<g>fi\t%0,%n2
4855 a<g>\t%0,%2
4856 a<y>\t%0,%2
4857 a<g>si\t%0,%c2"
4858 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
4859 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
4860 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
4861 z10_super_E1,z10_super_E1,z10_super_E1")])
4863 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
4864 (define_insn "*add<mode>3_carry1_cc"
4865 [(set (reg CC_REGNUM)
4866 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
4867 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
4868 (match_dup 1)))
4869 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
4870 (plus:GPR (match_dup 1) (match_dup 2)))]
4871 "s390_match_ccmode (insn, CCL1mode)"
4872 "@
4873 al<g>r\t%0,%2
4874 al<g>rk\t%0,%1,%2
4875 al<g>fi\t%0,%2
4876 sl<g>fi\t%0,%n2
4877 al<g>hsik\t%0,%1,%h2
4878 al<g>\t%0,%2
4879 al<y>\t%0,%2
4880 al<g>si\t%0,%c2"
4881 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4882 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4883 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4884 z10_super_E1,z10_super_E1,z10_super_E1")])
4886 ; alr, al, aly, algr, alg, alrk, algrk
4887 (define_insn "*add<mode>3_carry1_cconly"
4888 [(set (reg CC_REGNUM)
4889 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4890 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4891 (match_dup 1)))
4892 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4893 "s390_match_ccmode (insn, CCL1mode)"
4894 "@
4895 al<g>r\t%0,%2
4896 al<g>rk\t%0,%1,%2
4897 al<g>\t%0,%2
4898 al<y>\t%0,%2"
4899 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4900 (set_attr "cpu_facility" "*,z196,*,*")
4901 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4903 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4904 (define_insn "*add<mode>3_carry2_cc"
4905 [(set (reg CC_REGNUM)
4906 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4907 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4908 (match_dup 2)))
4909 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4910 (plus:GPR (match_dup 1) (match_dup 2)))]
4911 "s390_match_ccmode (insn, CCL1mode)"
4912 "@
4913 al<g>r\t%0,%2
4914 al<g>rk\t%0,%1,%2
4915 al<g>fi\t%0,%2
4916 sl<g>fi\t%0,%n2
4917 al<g>hsik\t%0,%1,%h2
4918 al<g>\t%0,%2
4919 al<y>\t%0,%2
4920 al<g>si\t%0,%c2"
4921 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4922 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4923 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4924 z10_super_E1,z10_super_E1,z10_super_E1")])
4926 ; alr, al, aly, algr, alg, alrk, algrk
4927 (define_insn "*add<mode>3_carry2_cconly"
4928 [(set (reg CC_REGNUM)
4929 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4930 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4931 (match_dup 2)))
4932 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4933 "s390_match_ccmode (insn, CCL1mode)"
4934 "@
4935 al<g>r\t%0,%2
4936 al<g>rk\t%0,%1,%2
4937 al<g>\t%0,%2
4938 al<y>\t%0,%2"
4939 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4940 (set_attr "cpu_facility" "*,z196,*,*")
4941 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4943 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4944 (define_insn "*add<mode>3_cc"
4945 [(set (reg CC_REGNUM)
4946 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4947 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4948 (const_int 0)))
4949 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4950 (plus:GPR (match_dup 1) (match_dup 2)))]
4951 "s390_match_ccmode (insn, CCLmode)"
4952 "@
4953 al<g>r\t%0,%2
4954 al<g>rk\t%0,%1,%2
4955 al<g>fi\t%0,%2
4956 sl<g>fi\t%0,%n2
4957 al<g>hsik\t%0,%1,%h2
4958 al<g>\t%0,%2
4959 al<y>\t%0,%2
4960 al<g>si\t%0,%c2"
4961 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4962 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4963 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
4964 *,z10_super_E1,z10_super_E1,z10_super_E1")])
4966 ; alr, al, aly, algr, alg, alrk, algrk
4967 (define_insn "*add<mode>3_cconly"
4968 [(set (reg CC_REGNUM)
4969 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4970 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4971 (const_int 0)))
4972 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4973 "s390_match_ccmode (insn, CCLmode)"
4974 "@
4975 al<g>r\t%0,%2
4976 al<g>rk\t%0,%1,%2
4977 al<g>\t%0,%2
4978 al<y>\t%0,%2"
4979 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4980 (set_attr "cpu_facility" "*,z196,*,*")
4981 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4983 ; alr, al, aly, algr, alg, alrk, algrk
4984 (define_insn "*add<mode>3_cconly2"
4985 [(set (reg CC_REGNUM)
4986 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4987 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
4988 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4989 "s390_match_ccmode(insn, CCLmode)"
4990 "@
4991 al<g>r\t%0,%2
4992 al<g>rk\t%0,%1,%2
4993 al<g>\t%0,%2
4994 al<y>\t%0,%2"
4995 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4996 (set_attr "cpu_facility" "*,z196,*,*")
4997 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4999 ; ahi, afi, aghi, agfi, asi, agsi
5000 (define_insn "*add<mode>3_imm_cc"
5001 [(set (reg CC_REGNUM)
5002 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
5003 (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
5004 (const_int 0)))
5005 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
5006 (plus:GPR (match_dup 1) (match_dup 2)))]
5007 "s390_match_ccmode (insn, CCAmode)
5008 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
5009 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
5010 /* Avoid INT32_MIN on 32 bit. */
5011 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
5012 "@
5013 a<g>hi\t%0,%h2
5014 a<g>hik\t%0,%1,%h2
5015 a<g>fi\t%0,%2
5016 a<g>si\t%0,%c2"
5017 [(set_attr "op_type" "RI,RIE,RIL,SIY")
5018 (set_attr "cpu_facility" "*,z196,extimm,z10")
5019 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5021 ;
5022 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
5023 ;
5025 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5026 (define_insn "add<mode>3"
5027 [(set (match_operand:FP 0 "register_operand" "=f, f")
5028 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5029 (match_operand:FP 2 "general_operand" " f,<Rf>")))
5030 (clobber (reg:CC CC_REGNUM))]
5031 "TARGET_HARD_FLOAT"
5032 "@
5033 a<xde><bt>r\t%0,<op1>%2
5034 a<xde>b\t%0,%2"
5035 [(set_attr "op_type" "<RRer>,RXE")
5036 (set_attr "type" "fsimp<mode>")])
5038 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5039 (define_insn "*add<mode>3_cc"
5040 [(set (reg CC_REGNUM)
5041 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5042 (match_operand:FP 2 "general_operand" " f,<Rf>"))
5043 (match_operand:FP 3 "const0_operand" "")))
5044 (set (match_operand:FP 0 "register_operand" "=f,f")
5045 (plus:FP (match_dup 1) (match_dup 2)))]
5046 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5047 "@
5048 a<xde><bt>r\t%0,<op1>%2
5049 a<xde>b\t%0,%2"
5050 [(set_attr "op_type" "<RRer>,RXE")
5051 (set_attr "type" "fsimp<mode>")])
5053 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5054 (define_insn "*add<mode>3_cconly"
5055 [(set (reg CC_REGNUM)
5056 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5057 (match_operand:FP 2 "general_operand" " f,<Rf>"))
5058 (match_operand:FP 3 "const0_operand" "")))
5059 (clobber (match_scratch:FP 0 "=f,f"))]
5060 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5061 "@
5062 a<xde><bt>r\t%0,<op1>%2
5063 a<xde>b\t%0,%2"
5064 [(set_attr "op_type" "<RRer>,RXE")
5065 (set_attr "type" "fsimp<mode>")])
5067 ;
5068 ; Pointer add instruction patterns
5069 ;
5071 ; This will match "*la_64"
5072 (define_expand "addptrdi3"
5073 [(set (match_operand:DI 0 "register_operand" "")
5074 (plus:DI (match_operand:DI 1 "register_operand" "")
5075 (match_operand:DI 2 "nonmemory_operand" "")))]
5076 "TARGET_64BIT"
5077 {
5078 if (GET_CODE (operands[2]) == CONST_INT)
5079 {
5080 HOST_WIDE_INT c = INTVAL (operands[2]);
5082 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5083 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5084 {
5085 operands[2] = force_const_mem (DImode, operands[2]);
5086 operands[2] = force_reg (DImode, operands[2]);
5087 }
5088 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5089 operands[2] = force_reg (DImode, operands[2]);
5090 }
5091 })
5093 ; For 31 bit we have to prevent the generated pattern from matching
5094 ; normal ADDs since la only does a 31 bit add. This is supposed to
5095 ; match "force_la_31".
5096 (define_expand "addptrsi3"
5097 [(parallel
5098 [(set (match_operand:SI 0 "register_operand" "")
5099 (plus:SI (match_operand:SI 1 "register_operand" "")
5100 (match_operand:SI 2 "nonmemory_operand" "")))
5101 (use (const_int 0))])]
5102 "!TARGET_64BIT"
5103 {
5104 if (GET_CODE (operands[2]) == CONST_INT)
5105 {
5106 HOST_WIDE_INT c = INTVAL (operands[2]);
5108 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5109 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5110 {
5111 operands[2] = force_const_mem (SImode, operands[2]);
5112 operands[2] = force_reg (SImode, operands[2]);
5113 }
5114 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5115 operands[2] = force_reg (SImode, operands[2]);
5116 }
5117 })
5119 ;;
5120 ;;- Subtract instructions.
5121 ;;
5123 ;
5124 ; subti3 instruction pattern(s).
5125 ;
5127 (define_insn_and_split "subti3"
5128 [(set (match_operand:TI 0 "register_operand" "=&d")
5129 (minus:TI (match_operand:TI 1 "register_operand" "0")
5130 (match_operand:TI 2 "general_operand" "do") ) )
5131 (clobber (reg:CC CC_REGNUM))]
5132 "TARGET_ZARCH"
5133 "#"
5134 "&& reload_completed"
5135 [(parallel
5136 [(set (reg:CCL2 CC_REGNUM)
5137 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
5138 (match_dup 7)))
5139 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
5140 (parallel
5141 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
5142 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
5143 (clobber (reg:CC CC_REGNUM))])]
5144 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5145 operands[4] = operand_subword (operands[1], 0, 0, TImode);
5146 operands[5] = operand_subword (operands[2], 0, 0, TImode);
5147 operands[6] = operand_subword (operands[0], 1, 0, TImode);
5148 operands[7] = operand_subword (operands[1], 1, 0, TImode);
5149 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
5151 ;
5152 ; subdi3 instruction pattern(s).
5153 ;
5155 (define_expand "subdi3"
5156 [(parallel
5157 [(set (match_operand:DI 0 "register_operand" "")
5158 (minus:DI (match_operand:DI 1 "register_operand" "")
5159 (match_operand:DI 2 "general_operand" "")))
5160 (clobber (reg:CC CC_REGNUM))])]
5161 ""
5162 "")
5164 (define_insn "*subdi3_sign"
5165 [(set (match_operand:DI 0 "register_operand" "=d,d")
5166 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5167 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5168 (clobber (reg:CC CC_REGNUM))]
5169 "TARGET_ZARCH"
5170 "@
5171 sgfr\t%0,%2
5172 sgf\t%0,%2"
5173 [(set_attr "op_type" "RRE,RXY")
5174 (set_attr "z10prop" "z10_c,*")
5175 (set_attr "z196prop" "z196_cracked")])
5177 (define_insn "*subdi3_zero_cc"
5178 [(set (reg CC_REGNUM)
5179 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5180 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5181 (const_int 0)))
5182 (set (match_operand:DI 0 "register_operand" "=d,d")
5183 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
5184 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5185 "@
5186 slgfr\t%0,%2
5187 slgf\t%0,%2"
5188 [(set_attr "op_type" "RRE,RXY")
5189 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5191 (define_insn "*subdi3_zero_cconly"
5192 [(set (reg CC_REGNUM)
5193 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5194 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5195 (const_int 0)))
5196 (clobber (match_scratch:DI 0 "=d,d"))]
5197 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5198 "@
5199 slgfr\t%0,%2
5200 slgf\t%0,%2"
5201 [(set_attr "op_type" "RRE,RXY")
5202 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5204 (define_insn "*subdi3_zero"
5205 [(set (match_operand:DI 0 "register_operand" "=d,d")
5206 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5207 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5208 (clobber (reg:CC CC_REGNUM))]
5209 "TARGET_ZARCH"
5210 "@
5211 slgfr\t%0,%2
5212 slgf\t%0,%2"
5213 [(set_attr "op_type" "RRE,RXY")
5214 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5216 (define_insn_and_split "*subdi3_31z"
5217 [(set (match_operand:DI 0 "register_operand" "=&d")
5218 (minus:DI (match_operand:DI 1 "register_operand" "0")
5219 (match_operand:DI 2 "general_operand" "do") ) )
5220 (clobber (reg:CC CC_REGNUM))]
5221 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5222 "#"
5223 "&& reload_completed"
5224 [(parallel
5225 [(set (reg:CCL2 CC_REGNUM)
5226 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5227 (match_dup 7)))
5228 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5229 (parallel
5230 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5231 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5232 (clobber (reg:CC CC_REGNUM))])]
5233 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5234 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5235 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5236 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5237 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5238 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5240 (define_insn_and_split "*subdi3_31"
5241 [(set (match_operand:DI 0 "register_operand" "=&d")
5242 (minus:DI (match_operand:DI 1 "register_operand" "0")
5243 (match_operand:DI 2 "general_operand" "do") ) )
5244 (clobber (reg:CC CC_REGNUM))]
5245 "!TARGET_CPU_ZARCH"
5246 "#"
5247 "&& reload_completed"
5248 [(parallel
5249 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5250 (clobber (reg:CC CC_REGNUM))])
5251 (parallel
5252 [(set (reg:CCL2 CC_REGNUM)
5253 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5254 (match_dup 7)))
5255 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5256 (set (pc)
5257 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5258 (pc)
5259 (label_ref (match_dup 9))))
5260 (parallel
5261 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5262 (clobber (reg:CC CC_REGNUM))])
5263 (match_dup 9)]
5264 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5265 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5266 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5267 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5268 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5269 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5270 operands[9] = gen_label_rtx ();")
5272 ;
5273 ; subsi3 instruction pattern(s).
5274 ;
5276 (define_expand "subsi3"
5277 [(parallel
5278 [(set (match_operand:SI 0 "register_operand" "")
5279 (minus:SI (match_operand:SI 1 "register_operand" "")
5280 (match_operand:SI 2 "general_operand" "")))
5281 (clobber (reg:CC CC_REGNUM))])]
5282 ""
5283 "")
5285 (define_insn "*subsi3_sign"
5286 [(set (match_operand:SI 0 "register_operand" "=d,d")
5287 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5288 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5289 (clobber (reg:CC CC_REGNUM))]
5290 ""
5291 "@
5292 sh\t%0,%2
5293 shy\t%0,%2"
5294 [(set_attr "op_type" "RX,RXY")
5295 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5297 ;
5298 ; sub(di|si)3 instruction pattern(s).
5299 ;
5301 ; sr, s, sy, sgr, sg, srk, sgrk
5302 (define_insn "*sub<mode>3"
5303 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5304 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5305 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
5306 (clobber (reg:CC CC_REGNUM))]
5307 ""
5308 "@
5309 s<g>r\t%0,%2
5310 s<g>rk\t%0,%1,%2
5311 s<g>\t%0,%2
5312 s<y>\t%0,%2"
5313 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5314 (set_attr "cpu_facility" "*,z196,*,*")
5315 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5317 ; slr, sl, sly, slgr, slg, slrk, slgrk
5318 (define_insn "*sub<mode>3_borrow_cc"
5319 [(set (reg CC_REGNUM)
5320 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5321 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5322 (match_dup 1)))
5323 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5324 (minus:GPR (match_dup 1) (match_dup 2)))]
5325 "s390_match_ccmode (insn, CCL2mode)"
5326 "@
5327 sl<g>r\t%0,%2
5328 sl<g>rk\t%0,%1,%2
5329 sl<g>\t%0,%2
5330 sl<y>\t%0,%2"
5331 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5332 (set_attr "cpu_facility" "*,z196,*,*")
5333 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5335 ; slr, sl, sly, slgr, slg, slrk, slgrk
5336 (define_insn "*sub<mode>3_borrow_cconly"
5337 [(set (reg CC_REGNUM)
5338 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5339 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5340 (match_dup 1)))
5341 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5342 "s390_match_ccmode (insn, CCL2mode)"
5343 "@
5344 sl<g>r\t%0,%2
5345 sl<g>rk\t%0,%1,%2
5346 sl<g>\t%0,%2
5347 sl<y>\t%0,%2"
5348 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5349 (set_attr "cpu_facility" "*,z196,*,*")
5350 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5352 ; slr, sl, sly, slgr, slg, slrk, slgrk
5353 (define_insn "*sub<mode>3_cc"
5354 [(set (reg CC_REGNUM)
5355 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5356 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5357 (const_int 0)))
5358 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5359 (minus:GPR (match_dup 1) (match_dup 2)))]
5360 "s390_match_ccmode (insn, CCLmode)"
5361 "@
5362 sl<g>r\t%0,%2
5363 sl<g>rk\t%0,%1,%2
5364 sl<g>\t%0,%2
5365 sl<y>\t%0,%2"
5366 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5367 (set_attr "cpu_facility" "*,z196,*,*")
5368 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5370 ; slr, sl, sly, slgr, slg, slrk, slgrk
5371 (define_insn "*sub<mode>3_cc2"
5372 [(set (reg CC_REGNUM)
5373 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5374 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5375 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5376 (minus:GPR (match_dup 1) (match_dup 2)))]
5377 "s390_match_ccmode (insn, CCL3mode)"
5378 "@
5379 sl<g>r\t%0,%2
5380 sl<g>rk\t%0,%1,%2
5381 sl<g>\t%0,%2
5382 sl<y>\t%0,%2"
5383 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5384 (set_attr "cpu_facility" "*,z196,*,*")
5385 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5387 ; slr, sl, sly, slgr, slg, slrk, slgrk
5388 (define_insn "*sub<mode>3_cconly"
5389 [(set (reg CC_REGNUM)
5390 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5391 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5392 (const_int 0)))
5393 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5394 "s390_match_ccmode (insn, CCLmode)"
5395 "@
5396 sl<g>r\t%0,%2
5397 sl<g>rk\t%0,%1,%2
5398 sl<g>\t%0,%2
5399 sl<y>\t%0,%2"
5400 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5401 (set_attr "cpu_facility" "*,z196,*,*")
5402 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5405 ; slr, sl, sly, slgr, slg, slrk, slgrk
5406 (define_insn "*sub<mode>3_cconly2"
5407 [(set (reg CC_REGNUM)
5408 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5409 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5410 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5411 "s390_match_ccmode (insn, CCL3mode)"
5412 "@
5413 sl<g>r\t%0,%2
5414 sl<g>rk\t%0,%1,%2
5415 sl<g>\t%0,%2
5416 sl<y>\t%0,%2"
5417 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5418 (set_attr "cpu_facility" "*,z196,*,*")
5419 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5422 ;
5423 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5424 ;
5426 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5427 (define_insn "sub<mode>3"
5428 [(set (match_operand:FP 0 "register_operand" "=f, f")
5429 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5430 (match_operand:FP 2 "general_operand" "f,<Rf>")))
5431 (clobber (reg:CC CC_REGNUM))]
5432 "TARGET_HARD_FLOAT"
5433 "@
5434 s<xde><bt>r\t%0,<op1>%2
5435 s<xde>b\t%0,%2"
5436 [(set_attr "op_type" "<RRer>,RXE")
5437 (set_attr "type" "fsimp<mode>")])
5439 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5440 (define_insn "*sub<mode>3_cc"
5441 [(set (reg CC_REGNUM)
5442 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5443 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5444 (match_operand:FP 3 "const0_operand" "")))
5445 (set (match_operand:FP 0 "register_operand" "=f,f")
5446 (minus:FP (match_dup 1) (match_dup 2)))]
5447 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5448 "@
5449 s<xde><bt>r\t%0,<op1>%2
5450 s<xde>b\t%0,%2"
5451 [(set_attr "op_type" "<RRer>,RXE")
5452 (set_attr "type" "fsimp<mode>")])
5454 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5455 (define_insn "*sub<mode>3_cconly"
5456 [(set (reg CC_REGNUM)
5457 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5458 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5459 (match_operand:FP 3 "const0_operand" "")))
5460 (clobber (match_scratch:FP 0 "=f,f"))]
5461 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5462 "@
5463 s<xde><bt>r\t%0,<op1>%2
5464 s<xde>b\t%0,%2"
5465 [(set_attr "op_type" "<RRer>,RXE")
5466 (set_attr "type" "fsimp<mode>")])
5469 ;;
5470 ;;- Conditional add/subtract instructions.
5471 ;;
5473 ;
5474 ; add(di|si)cc instruction pattern(s).
5475 ;
5477 ; the following 4 patterns are used when the result of an add with
5478 ; carry is checked for an overflow condition
5480 ; op1 + op2 + c < op1
5482 ; alcr, alc, alcgr, alcg
5483 (define_insn "*add<mode>3_alc_carry1_cc"
5484 [(set (reg CC_REGNUM)
5485 (compare
5486 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5487 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5488 (match_operand:GPR 2 "general_operand" "d,RT"))
5489 (match_dup 1)))
5490 (set (match_operand:GPR 0 "register_operand" "=d,d")
5491 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5492 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5493 "@
5494 alc<g>r\t%0,%2
5495 alc<g>\t%0,%2"
5496 [(set_attr "op_type" "RRE,RXY")
5497 (set_attr "z196prop" "z196_alone,z196_alone")])
5499 ; alcr, alc, alcgr, alcg
5500 (define_insn "*add<mode>3_alc_carry1_cconly"
5501 [(set (reg CC_REGNUM)
5502 (compare
5503 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5504 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5505 (match_operand:GPR 2 "general_operand" "d,RT"))
5506 (match_dup 1)))
5507 (clobber (match_scratch:GPR 0 "=d,d"))]
5508 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5509 "@
5510 alc<g>r\t%0,%2
5511 alc<g>\t%0,%2"
5512 [(set_attr "op_type" "RRE,RXY")
5513 (set_attr "z196prop" "z196_alone,z196_alone")])
5515 ; op1 + op2 + c < op2
5517 ; alcr, alc, alcgr, alcg
5518 (define_insn "*add<mode>3_alc_carry2_cc"
5519 [(set (reg CC_REGNUM)
5520 (compare
5521 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5522 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5523 (match_operand:GPR 2 "general_operand" "d,RT"))
5524 (match_dup 2)))
5525 (set (match_operand:GPR 0 "register_operand" "=d,d")
5526 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5527 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5528 "@
5529 alc<g>r\t%0,%2
5530 alc<g>\t%0,%2"
5531 [(set_attr "op_type" "RRE,RXY")])
5533 ; alcr, alc, alcgr, alcg
5534 (define_insn "*add<mode>3_alc_carry2_cconly"
5535 [(set (reg CC_REGNUM)
5536 (compare
5537 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5538 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5539 (match_operand:GPR 2 "general_operand" "d,RT"))
5540 (match_dup 2)))
5541 (clobber (match_scratch:GPR 0 "=d,d"))]
5542 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5543 "@
5544 alc<g>r\t%0,%2
5545 alc<g>\t%0,%2"
5546 [(set_attr "op_type" "RRE,RXY")])
5548 ; alcr, alc, alcgr, alcg
5549 (define_insn "*add<mode>3_alc_cc"
5550 [(set (reg CC_REGNUM)
5551 (compare
5552 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5553 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5554 (match_operand:GPR 2 "general_operand" "d,RT"))
5555 (const_int 0)))
5556 (set (match_operand:GPR 0 "register_operand" "=d,d")
5557 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5558 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5559 "@
5560 alc<g>r\t%0,%2
5561 alc<g>\t%0,%2"
5562 [(set_attr "op_type" "RRE,RXY")])
5564 ; alcr, alc, alcgr, alcg
5565 (define_insn "*add<mode>3_alc"
5566 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5567 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5568 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5569 (match_operand:GPR 2 "general_operand" "d,RT")))
5570 (clobber (reg:CC CC_REGNUM))]
5571 "TARGET_CPU_ZARCH"
5572 "@
5573 alc<g>r\t%0,%2
5574 alc<g>\t%0,%2"
5575 [(set_attr "op_type" "RRE,RXY")])
5577 ; slbr, slb, slbgr, slbg
5578 (define_insn "*sub<mode>3_slb_cc"
5579 [(set (reg CC_REGNUM)
5580 (compare
5581 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5582 (match_operand:GPR 2 "general_operand" "d,RT"))
5583 (match_operand:GPR 3 "s390_slb_comparison" ""))
5584 (const_int 0)))
5585 (set (match_operand:GPR 0 "register_operand" "=d,d")
5586 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5587 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5588 "@
5589 slb<g>r\t%0,%2
5590 slb<g>\t%0,%2"
5591 [(set_attr "op_type" "RRE,RXY")
5592 (set_attr "z10prop" "z10_c,*")])
5594 ; slbr, slb, slbgr, slbg
5595 (define_insn "*sub<mode>3_slb"
5596 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5597 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5598 (match_operand:GPR 2 "general_operand" "d,RT"))
5599 (match_operand:GPR 3 "s390_slb_comparison" "")))
5600 (clobber (reg:CC CC_REGNUM))]
5601 "TARGET_CPU_ZARCH"
5602 "@
5603 slb<g>r\t%0,%2
5604 slb<g>\t%0,%2"
5605 [(set_attr "op_type" "RRE,RXY")
5606 (set_attr "z10prop" "z10_c,*")])
5608 (define_expand "add<mode>cc"
5609 [(match_operand:GPR 0 "register_operand" "")
5610 (match_operand 1 "comparison_operator" "")
5611 (match_operand:GPR 2 "register_operand" "")
5612 (match_operand:GPR 3 "const_int_operand" "")]
5613 "TARGET_CPU_ZARCH"
5614 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5615 XEXP (operands[1], 0), XEXP (operands[1], 1),
5616 operands[0], operands[2],
5617 operands[3])) FAIL; DONE;")
5619 ;
5620 ; scond instruction pattern(s).
5621 ;
5623 (define_insn_and_split "*scond<mode>"
5624 [(set (match_operand:GPR 0 "register_operand" "=&d")
5625 (match_operand:GPR 1 "s390_alc_comparison" ""))
5626 (clobber (reg:CC CC_REGNUM))]
5627 "TARGET_CPU_ZARCH"
5628 "#"
5629 "&& reload_completed"
5630 [(set (match_dup 0) (const_int 0))
5631 (parallel
5632 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5633 (match_dup 0)))
5634 (clobber (reg:CC CC_REGNUM))])]
5635 "")
5637 (define_insn_and_split "*scond<mode>_neg"
5638 [(set (match_operand:GPR 0 "register_operand" "=&d")
5639 (match_operand:GPR 1 "s390_slb_comparison" ""))
5640 (clobber (reg:CC CC_REGNUM))]
5641 "TARGET_CPU_ZARCH"
5642 "#"
5643 "&& reload_completed"
5644 [(set (match_dup 0) (const_int 0))
5645 (parallel
5646 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5647 (match_dup 1)))
5648 (clobber (reg:CC CC_REGNUM))])
5649 (parallel
5650 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5651 (clobber (reg:CC CC_REGNUM))])]
5652 "")
5655 (define_expand "cstore<mode>4"
5656 [(set (match_operand:SI 0 "register_operand" "")
5657 (match_operator:SI 1 "s390_scond_operator"
5658 [(match_operand:GPR 2 "register_operand" "")
5659 (match_operand:GPR 3 "general_operand" "")]))]
5660 "TARGET_CPU_ZARCH"
5661 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5662 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5664 (define_expand "cstorecc4"
5665 [(parallel
5666 [(set (match_operand:SI 0 "register_operand" "")
5667 (match_operator:SI 1 "s390_eqne_operator"
5668 [(match_operand:CCZ1 2 "register_operand")
5669 (match_operand 3 "const0_operand")]))
5670 (clobber (reg:CC CC_REGNUM))])]
5671 ""
5672 "emit_insn (gen_sne (operands[0], operands[2]));
5673 if (GET_CODE (operands[1]) == EQ)
5674 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5675 DONE;")
5677 (define_insn_and_split "sne"
5678 [(set (match_operand:SI 0 "register_operand" "=d")
5679 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5680 (const_int 0)))
5681 (clobber (reg:CC CC_REGNUM))]
5682 ""
5683 "#"
5684 "reload_completed"
5685 [(parallel
5686 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5687 (clobber (reg:CC CC_REGNUM))])])
5690 ;;
5691 ;; - Conditional move instructions (introduced with z196)
5692 ;;
5694 (define_expand "mov<mode>cc"
5695 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
5696 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5697 (match_operand:GPR 2 "nonimmediate_operand" "")
5698 (match_operand:GPR 3 "nonimmediate_operand" "")))]
5699 "TARGET_Z196"
5700 "operands[1] = s390_emit_compare (GET_CODE (operands[1]),
5701 XEXP (operands[1], 0), XEXP (operands[1], 1));")
5703 ; locr, loc, stoc, locgr, locg, stocg
5704 (define_insn_and_split "*mov<mode>cc"
5705 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
5706 (if_then_else:GPR
5707 (match_operator 1 "s390_comparison"
5708 [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
5709 (match_operand 5 "const_int_operand" "")])
5710 (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
5711 (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
5712 "TARGET_Z196"
5713 "@
5714 loc<g>r%C1\t%0,%3
5715 loc<g>r%D1\t%0,%4
5716 loc<g>%C1\t%0,%3
5717 loc<g>%D1\t%0,%4
5718 stoc<g>%C1\t%3,%0
5719 stoc<g>%D1\t%4,%0
5720 #"
5721 "&& reload_completed
5722 && MEM_P (operands[3]) && MEM_P (operands[4])"
5723 [(set (match_dup 0)
5724 (if_then_else:GPR
5725 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5726 (match_dup 3)
5727 (match_dup 0)))
5728 (set (match_dup 0)
5729 (if_then_else:GPR
5730 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5731 (match_dup 0)
5732 (match_dup 4)))]
5733 ""
5734 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
5736 ;;
5737 ;;- Multiply instructions.
5738 ;;
5740 ;
5741 ; muldi3 instruction pattern(s).
5742 ;
5744 (define_insn "*muldi3_sign"
5745 [(set (match_operand:DI 0 "register_operand" "=d,d")
5746 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5747 (match_operand:DI 1 "register_operand" "0,0")))]
5748 "TARGET_ZARCH"
5749 "@
5750 msgfr\t%0,%2
5751 msgf\t%0,%2"
5752 [(set_attr "op_type" "RRE,RXY")
5753 (set_attr "type" "imuldi")])
5755 (define_insn "muldi3"
5756 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5757 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5758 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5759 "TARGET_ZARCH"
5760 "@
5761 msgr\t%0,%2
5762 mghi\t%0,%h2
5763 msg\t%0,%2
5764 msgfi\t%0,%2"
5765 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5766 (set_attr "type" "imuldi")
5767 (set_attr "cpu_facility" "*,*,*,z10")])
5769 ;
5770 ; mulsi3 instruction pattern(s).
5771 ;
5773 (define_insn "*mulsi3_sign"
5774 [(set (match_operand:SI 0 "register_operand" "=d,d")
5775 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5776 (match_operand:SI 1 "register_operand" "0,0")))]
5777 ""
5778 "@
5779 mh\t%0,%2
5780 mhy\t%0,%2"
5781 [(set_attr "op_type" "RX,RXY")
5782 (set_attr "type" "imulhi")
5783 (set_attr "cpu_facility" "*,z10")])
5785 (define_insn "mulsi3"
5786 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5787 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5788 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5789 ""
5790 "@
5791 msr\t%0,%2
5792 mhi\t%0,%h2
5793 ms\t%0,%2
5794 msy\t%0,%2
5795 msfi\t%0,%2"
5796 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5797 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5798 (set_attr "cpu_facility" "*,*,*,*,z10")])
5800 ;
5801 ; mulsidi3 instruction pattern(s).
5802 ;
5804 (define_insn "mulsidi3"
5805 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5806 (mult:DI (sign_extend:DI
5807 (match_operand:SI 1 "register_operand" "%0,0,0"))
5808 (sign_extend:DI
5809 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5810 "!TARGET_ZARCH"
5811 "@
5812 mr\t%0,%2
5813 m\t%0,%2
5814 mfy\t%0,%2"
5815 [(set_attr "op_type" "RR,RX,RXY")
5816 (set_attr "type" "imulsi")
5817 (set_attr "cpu_facility" "*,*,z10")])
5819 ;
5820 ; umul instruction pattern(s).
5821 ;
5823 ; mlr, ml, mlgr, mlg
5824 (define_insn "umul<dwh><mode>3"
5825 [(set (match_operand:DW 0 "register_operand" "=d, d")
5826 (mult:DW (zero_extend:DW
5827 (match_operand:<DWH> 1 "register_operand" "%0, 0"))
5828 (zero_extend:DW
5829 (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
5830 "TARGET_CPU_ZARCH"
5831 "@
5832 ml<tg>r\t%0,%2
5833 ml<tg>\t%0,%2"
5834 [(set_attr "op_type" "RRE,RXY")
5835 (set_attr "type" "imul<dwh>")])
5837 ;
5838 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5839 ;
5841 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5842 (define_insn "mul<mode>3"
5843 [(set (match_operand:FP 0 "register_operand" "=f,f")
5844 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5845 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5846 "TARGET_HARD_FLOAT"
5847 "@
5848 m<xdee><bt>r\t%0,<op1>%2
5849 m<xdee>b\t%0,%2"
5850 [(set_attr "op_type" "<RRer>,RXE")
5851 (set_attr "type" "fmul<mode>")])
5853 ; madbr, maebr, maxb, madb, maeb
5854 (define_insn "fma<mode>4"
5855 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5856 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5857 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5858 (match_operand:DSF 3 "register_operand" "0,0")))]
5859 "TARGET_HARD_FLOAT"
5860 "@
5861 ma<xde>br\t%0,%1,%2
5862 ma<xde>b\t%0,%1,%2"
5863 [(set_attr "op_type" "RRE,RXE")
5864 (set_attr "type" "fmadd<mode>")])
5866 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5867 (define_insn "fms<mode>4"
5868 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5869 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5870 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5871 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))]
5872 "TARGET_HARD_FLOAT"
5873 "@
5874 ms<xde>br\t%0,%1,%2
5875 ms<xde>b\t%0,%1,%2"
5876 [(set_attr "op_type" "RRE,RXE")
5877 (set_attr "type" "fmadd<mode>")])
5879 ;;
5880 ;;- Divide and modulo instructions.
5881 ;;
5883 ;
5884 ; divmoddi4 instruction pattern(s).
5885 ;
5887 (define_expand "divmoddi4"
5888 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5889 (div:DI (match_operand:DI 1 "register_operand" "")
5890 (match_operand:DI 2 "general_operand" "")))
5891 (set (match_operand:DI 3 "general_operand" "")
5892 (mod:DI (match_dup 1) (match_dup 2)))])
5893 (clobber (match_dup 4))]
5894 "TARGET_ZARCH"
5895 {
5896 rtx insn, div_equal, mod_equal;
5898 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5899 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5901 operands[4] = gen_reg_rtx(TImode);
5902 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5904 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5905 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5907 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5908 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5910 DONE;
5911 })
5913 (define_insn "divmodtidi3"
5914 [(set (match_operand:TI 0 "register_operand" "=d,d")
5915 (ior:TI
5916 (ashift:TI
5917 (zero_extend:TI
5918 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5919 (match_operand:DI 2 "general_operand" "d,RT")))
5920 (const_int 64))
5921 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5922 "TARGET_ZARCH"
5923 "@
5924 dsgr\t%0,%2
5925 dsg\t%0,%2"
5926 [(set_attr "op_type" "RRE,RXY")
5927 (set_attr "type" "idiv")])
5929 (define_insn "divmodtisi3"
5930 [(set (match_operand:TI 0 "register_operand" "=d,d")
5931 (ior:TI
5932 (ashift:TI
5933 (zero_extend:TI
5934 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5935 (sign_extend:DI
5936 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5937 (const_int 64))
5938 (zero_extend:TI
5939 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5940 "TARGET_ZARCH"
5941 "@
5942 dsgfr\t%0,%2
5943 dsgf\t%0,%2"
5944 [(set_attr "op_type" "RRE,RXY")
5945 (set_attr "type" "idiv")])
5947 ;
5948 ; udivmoddi4 instruction pattern(s).
5949 ;
5951 (define_expand "udivmoddi4"
5952 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5953 (udiv:DI (match_operand:DI 1 "general_operand" "")
5954 (match_operand:DI 2 "nonimmediate_operand" "")))
5955 (set (match_operand:DI 3 "general_operand" "")
5956 (umod:DI (match_dup 1) (match_dup 2)))])
5957 (clobber (match_dup 4))]
5958 "TARGET_ZARCH"
5959 {
5960 rtx insn, div_equal, mod_equal, equal;
5962 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5963 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5964 equal = gen_rtx_IOR (TImode,
5965 gen_rtx_ASHIFT (TImode,
5966 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5967 GEN_INT (64)),
5968 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5970 operands[4] = gen_reg_rtx(TImode);
5971 emit_clobber (operands[4]);
5972 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5973 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5975 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5976 set_unique_reg_note (insn, REG_EQUAL, equal);
5978 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5979 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5981 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5982 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5984 DONE;
5985 })
5987 (define_insn "udivmodtidi3"
5988 [(set (match_operand:TI 0 "register_operand" "=d,d")
5989 (ior:TI
5990 (ashift:TI
5991 (zero_extend:TI
5992 (truncate:DI
5993 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5994 (zero_extend:TI
5995 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5996 (const_int 64))
5997 (zero_extend:TI
5998 (truncate:DI
5999 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
6000 "TARGET_ZARCH"
6001 "@
6002 dlgr\t%0,%2
6003 dlg\t%0,%2"
6004 [(set_attr "op_type" "RRE,RXY")
6005 (set_attr "type" "idiv")])
6007 ;
6008 ; divmodsi4 instruction pattern(s).
6009 ;
6011 (define_expand "divmodsi4"
6012 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6013 (div:SI (match_operand:SI 1 "general_operand" "")
6014 (match_operand:SI 2 "nonimmediate_operand" "")))
6015 (set (match_operand:SI 3 "general_operand" "")
6016 (mod:SI (match_dup 1) (match_dup 2)))])
6017 (clobber (match_dup 4))]
6018 "!TARGET_ZARCH"
6019 {
6020 rtx insn, div_equal, mod_equal, equal;
6022 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
6023 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
6024 equal = gen_rtx_IOR (DImode,
6025 gen_rtx_ASHIFT (DImode,
6026 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6027 GEN_INT (32)),
6028 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6030 operands[4] = gen_reg_rtx(DImode);
6031 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
6033 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
6034 set_unique_reg_note (insn, REG_EQUAL, equal);
6036 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6037 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6039 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6040 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6042 DONE;
6043 })
6045 (define_insn "divmoddisi3"
6046 [(set (match_operand:DI 0 "register_operand" "=d,d")
6047 (ior:DI
6048 (ashift:DI
6049 (zero_extend:DI
6050 (truncate:SI
6051 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6052 (sign_extend:DI
6053 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
6054 (const_int 32))
6055 (zero_extend:DI
6056 (truncate:SI
6057 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
6058 "!TARGET_ZARCH"
6059 "@
6060 dr\t%0,%2
6061 d\t%0,%2"
6062 [(set_attr "op_type" "RR,RX")
6063 (set_attr "type" "idiv")])
6065 ;
6066 ; udivsi3 and umodsi3 instruction pattern(s).
6067 ;
6069 (define_expand "udivmodsi4"
6070 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6071 (udiv:SI (match_operand:SI 1 "general_operand" "")
6072 (match_operand:SI 2 "nonimmediate_operand" "")))
6073 (set (match_operand:SI 3 "general_operand" "")
6074 (umod:SI (match_dup 1) (match_dup 2)))])
6075 (clobber (match_dup 4))]
6076 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6077 {
6078 rtx insn, div_equal, mod_equal, equal;
6080 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6081 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6082 equal = gen_rtx_IOR (DImode,
6083 gen_rtx_ASHIFT (DImode,
6084 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6085 GEN_INT (32)),
6086 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6088 operands[4] = gen_reg_rtx(DImode);
6089 emit_clobber (operands[4]);
6090 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
6091 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
6093 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
6094 set_unique_reg_note (insn, REG_EQUAL, equal);
6096 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6097 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6099 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6100 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6102 DONE;
6103 })
6105 (define_insn "udivmoddisi3"
6106 [(set (match_operand:DI 0 "register_operand" "=d,d")
6107 (ior:DI
6108 (ashift:DI
6109 (zero_extend:DI
6110 (truncate:SI
6111 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
6112 (zero_extend:DI
6113 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
6114 (const_int 32))
6115 (zero_extend:DI
6116 (truncate:SI
6117 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
6118 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6119 "@
6120 dlr\t%0,%2
6121 dl\t%0,%2"
6122 [(set_attr "op_type" "RRE,RXY")
6123 (set_attr "type" "idiv")])
6125 (define_expand "udivsi3"
6126 [(set (match_operand:SI 0 "register_operand" "=d")
6127 (udiv:SI (match_operand:SI 1 "general_operand" "")
6128 (match_operand:SI 2 "general_operand" "")))
6129 (clobber (match_dup 3))]
6130 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6131 {
6132 rtx insn, udiv_equal, umod_equal, equal;
6134 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6135 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6136 equal = gen_rtx_IOR (DImode,
6137 gen_rtx_ASHIFT (DImode,
6138 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6139 GEN_INT (32)),
6140 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6142 operands[3] = gen_reg_rtx (DImode);
6144 if (CONSTANT_P (operands[2]))
6145 {
6146 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6147 {
6148 rtx_code_label *label1 = gen_label_rtx ();
6150 operands[1] = make_safe_from (operands[1], operands[0]);
6151 emit_move_insn (operands[0], const0_rtx);
6152 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
6153 SImode, 1, label1);
6154 emit_move_insn (operands[0], const1_rtx);
6155 emit_label (label1);
6156 }
6157 else
6158 {
6159 operands[2] = force_reg (SImode, operands[2]);
6160 operands[2] = make_safe_from (operands[2], operands[0]);
6162 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6163 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6164 operands[2]));
6165 set_unique_reg_note (insn, REG_EQUAL, equal);
6167 insn = emit_move_insn (operands[0],
6168 gen_lowpart (SImode, operands[3]));
6169 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6170 }
6171 }
6172 else
6173 {
6174 rtx_code_label *label1 = gen_label_rtx ();
6175 rtx_code_label *label2 = gen_label_rtx ();
6176 rtx_code_label *label3 = gen_label_rtx ();
6178 operands[1] = force_reg (SImode, operands[1]);
6179 operands[1] = make_safe_from (operands[1], operands[0]);
6180 operands[2] = force_reg (SImode, operands[2]);
6181 operands[2] = make_safe_from (operands[2], operands[0]);
6183 emit_move_insn (operands[0], const0_rtx);
6184 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6185 SImode, 1, label3);
6186 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6187 SImode, 0, label2);
6188 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6189 SImode, 0, label1);
6190 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6191 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6192 operands[2]));
6193 set_unique_reg_note (insn, REG_EQUAL, equal);
6195 insn = emit_move_insn (operands[0],
6196 gen_lowpart (SImode, operands[3]));
6197 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6199 emit_jump (label3);
6200 emit_label (label1);
6201 emit_move_insn (operands[0], operands[1]);
6202 emit_jump (label3);
6203 emit_label (label2);
6204 emit_move_insn (operands[0], const1_rtx);
6205 emit_label (label3);
6206 }
6207 emit_move_insn (operands[0], operands[0]);
6208 DONE;
6209 })
6211 (define_expand "umodsi3"
6212 [(set (match_operand:SI 0 "register_operand" "=d")
6213 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6214 (match_operand:SI 2 "nonimmediate_operand" "")))
6215 (clobber (match_dup 3))]
6216 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6217 {
6218 rtx insn, udiv_equal, umod_equal, equal;
6220 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6221 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6222 equal = gen_rtx_IOR (DImode,
6223 gen_rtx_ASHIFT (DImode,
6224 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6225 GEN_INT (32)),
6226 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6228 operands[3] = gen_reg_rtx (DImode);
6230 if (CONSTANT_P (operands[2]))
6231 {
6232 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6233 {
6234 rtx_code_label *label1 = gen_label_rtx ();
6236 operands[1] = make_safe_from (operands[1], operands[0]);
6237 emit_move_insn (operands[0], operands[1]);
6238 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6239 SImode, 1, label1);
6240 emit_insn (gen_abssi2 (operands[0], operands[2]));
6241 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6242 emit_label (label1);
6243 }
6244 else
6245 {
6246 operands[2] = force_reg (SImode, operands[2]);
6247 operands[2] = make_safe_from (operands[2], operands[0]);
6249 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6250 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6251 operands[2]));
6252 set_unique_reg_note (insn, REG_EQUAL, equal);
6254 insn = emit_move_insn (operands[0],
6255 gen_highpart (SImode, operands[3]));
6256 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6257 }
6258 }
6259 else
6260 {
6261 rtx_code_label *label1 = gen_label_rtx ();
6262 rtx_code_label *label2 = gen_label_rtx ();
6263 rtx_code_label *label3 = gen_label_rtx ();
6265 operands[1] = force_reg (SImode, operands[1]);
6266 operands[1] = make_safe_from (operands[1], operands[0]);
6267 operands[2] = force_reg (SImode, operands[2]);
6268 operands[2] = make_safe_from (operands[2], operands[0]);
6270 emit_move_insn(operands[0], operands[1]);
6271 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6272 SImode, 1, label3);
6273 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6274 SImode, 0, label2);
6275 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6276 SImode, 0, label1);
6277 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6278 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6279 operands[2]));
6280 set_unique_reg_note (insn, REG_EQUAL, equal);
6282 insn = emit_move_insn (operands[0],
6283 gen_highpart (SImode, operands[3]));
6284 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6286 emit_jump (label3);
6287 emit_label (label1);
6288 emit_move_insn (operands[0], const0_rtx);
6289 emit_jump (label3);
6290 emit_label (label2);
6291 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6292 emit_label (label3);
6293 }
6294 DONE;
6295 })
6297 ;
6298 ; div(df|sf)3 instruction pattern(s).
6299 ;
6301 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6302 (define_insn "div<mode>3"
6303 [(set (match_operand:FP 0 "register_operand" "=f,f")
6304 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
6305 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
6306 "TARGET_HARD_FLOAT"
6307 "@
6308 d<xde><bt>r\t%0,<op1>%2
6309 d<xde>b\t%0,%2"
6310 [(set_attr "op_type" "<RRer>,RXE")
6311 (set_attr "type" "fdiv<mode>")])
6314 ;;
6315 ;;- And instructions.
6316 ;;
6318 (define_expand "and<mode>3"
6319 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6320 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6321 (match_operand:INT 2 "general_operand" "")))
6322 (clobber (reg:CC CC_REGNUM))]
6323 ""
6324 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6326 ;
6327 ; anddi3 instruction pattern(s).
6328 ;
6330 (define_insn "*anddi3_cc"
6331 [(set (reg CC_REGNUM)
6332 (compare
6333 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6334 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6335 (const_int 0)))
6336 (set (match_operand:DI 0 "register_operand" "=d,d, d, d")
6337 (and:DI (match_dup 1) (match_dup 2)))]
6338 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6339 "@
6340 ngr\t%0,%2
6341 ngrk\t%0,%1,%2
6342 ng\t%0,%2
6343 risbg\t%0,%1,%s2,128+%e2,0"
6344 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6345 (set_attr "cpu_facility" "*,z196,*,z10")
6346 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6348 (define_insn "*anddi3_cconly"
6349 [(set (reg CC_REGNUM)
6350 (compare
6351 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6352 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6353 (const_int 0)))
6354 (clobber (match_scratch:DI 0 "=d,d, d, d"))]
6355 "TARGET_ZARCH
6356 && s390_match_ccmode(insn, CCTmode)
6357 /* Do not steal TM patterns. */
6358 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6359 "@
6360 ngr\t%0,%2
6361 ngrk\t%0,%1,%2
6362 ng\t%0,%2
6363 risbg\t%0,%1,%s2,128+%e2,0"
6364 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6365 (set_attr "cpu_facility" "*,z196,*,z10")
6366 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6368 (define_insn "*anddi3"
6369 [(set (match_operand:DI 0 "nonimmediate_operand"
6370 "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q")
6371 (and:DI
6372 (match_operand:DI 1 "nonimmediate_operand"
6373 "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0")
6374 (match_operand:DI 2 "general_operand"
6375 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
6376 (clobber (reg:CC CC_REGNUM))]
6377 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6378 "@
6379 #
6380 #
6381 nihh\t%0,%j2
6382 nihl\t%0,%j2
6383 nilh\t%0,%j2
6384 nill\t%0,%j2
6385 nihf\t%0,%m2
6386 nilf\t%0,%m2
6387 ngr\t%0,%2
6388 ngrk\t%0,%1,%2
6389 ng\t%0,%2
6390 risbg\t%0,%1,%s2,128+%e2,0
6391 #
6392 #"
6393 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
6394 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
6395 (set_attr "z10prop" "*,
6396 *,
6397 z10_super_E1,
6398 z10_super_E1,
6399 z10_super_E1,
6400 z10_super_E1,
6401 z10_super_E1,
6402 z10_super_E1,
6403 z10_super_E1,
6404 *,
6405 z10_super_E1,
6406 z10_super_E1,
6407 *,
6408 *")])
6410 (define_split
6411 [(set (match_operand:DI 0 "s_operand" "")
6412 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6413 (clobber (reg:CC CC_REGNUM))]
6414 "reload_completed"
6415 [(parallel
6416 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6417 (clobber (reg:CC CC_REGNUM))])]
6418 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6420 ;; These two are what combine generates for (ashift (zero_extract)).
6421 (define_insn "*extzv_<mode>_srl"
6422 [(set (match_operand:GPR 0 "register_operand" "=d")
6423 (and:GPR (lshiftrt:GPR
6424 (match_operand:GPR 1 "register_operand" "d")
6425 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6426 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6427 (clobber (reg:CC CC_REGNUM))]
6428 "TARGET_Z10
6429 /* Note that even for the SImode pattern, the rotate is always DImode. */
6430 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
6431 INTVAL (operands[3]))"
6432 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
6433 [(set_attr "op_type" "RIE")
6434 (set_attr "z10prop" "z10_super_E1")])
6436 (define_insn "*extzv_<mode>_sll"
6437 [(set (match_operand:GPR 0 "register_operand" "=d")
6438 (and:GPR (ashift:GPR
6439 (match_operand:GPR 1 "register_operand" "d")
6440 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6441 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6442 (clobber (reg:CC CC_REGNUM))]
6443 "TARGET_Z10
6444 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
6445 INTVAL (operands[3]))"
6446 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
6447 [(set_attr "op_type" "RIE")
6448 (set_attr "z10prop" "z10_super_E1")])
6451 ;
6452 ; andsi3 instruction pattern(s).
6453 ;
6455 (define_insn "*andsi3_cc"
6456 [(set (reg CC_REGNUM)
6457 (compare
6458 (and:SI
6459 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6460 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6461 (const_int 0)))
6462 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
6463 (and:SI (match_dup 1) (match_dup 2)))]
6464 "s390_match_ccmode(insn, CCTmode)"
6465 "@
6466 nilf\t%0,%o2
6467 nr\t%0,%2
6468 nrk\t%0,%1,%2
6469 n\t%0,%2
6470 ny\t%0,%2
6471 risbg\t%0,%1,%t2,128+%f2,0"
6472 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6473 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6474 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6475 z10_super_E1,z10_super_E1,z10_super_E1")])
6477 (define_insn "*andsi3_cconly"
6478 [(set (reg CC_REGNUM)
6479 (compare
6480 (and:SI
6481 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6482 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6483 (const_int 0)))
6484 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
6485 "s390_match_ccmode(insn, CCTmode)
6486 /* Do not steal TM patterns. */
6487 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6488 "@
6489 nilf\t%0,%o2
6490 nr\t%0,%2
6491 nrk\t%0,%1,%2
6492 n\t%0,%2
6493 ny\t%0,%2
6494 risbg\t%0,%1,%t2,128+%f2,0"
6495 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6496 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6497 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6498 z10_super_E1,z10_super_E1,z10_super_E1")])
6500 (define_insn "*andsi3_zarch"
6501 [(set (match_operand:SI 0 "nonimmediate_operand"
6502 "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
6503 (and:SI (match_operand:SI 1 "nonimmediate_operand"
6504 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
6505 (match_operand:SI 2 "general_operand"
6506 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
6507 (clobber (reg:CC CC_REGNUM))]
6508 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6509 "@
6510 #
6511 #
6512 nilh\t%0,%j2
6513 nill\t%0,%j2
6514 nilf\t%0,%o2
6515 nr\t%0,%2
6516 nrk\t%0,%1,%2
6517 n\t%0,%2
6518 ny\t%0,%2
6519 risbg\t%0,%1,%t2,128+%f2,0
6520 #
6521 #"
6522 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
6523 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
6524 (set_attr "z10prop" "*,
6525 *,
6526 z10_super_E1,
6527 z10_super_E1,
6528 z10_super_E1,
6529 z10_super_E1,
6530 *,
6531 z10_super_E1,
6532 z10_super_E1,
6533 z10_super_E1,
6534 *,
6535 *")])
6537 (define_insn "*andsi3_esa"
6538 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
6539 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
6540 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
6541 (clobber (reg:CC CC_REGNUM))]
6542 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6543 "@
6544 nr\t%0,%2
6545 n\t%0,%2
6546 #
6547 #"
6548 [(set_attr "op_type" "RR,RX,SI,SS")
6549 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6552 (define_split
6553 [(set (match_operand:SI 0 "s_operand" "")
6554 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6555 (clobber (reg:CC CC_REGNUM))]
6556 "reload_completed"
6557 [(parallel
6558 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6559 (clobber (reg:CC CC_REGNUM))])]
6560 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6562 ;
6563 ; andhi3 instruction pattern(s).
6564 ;
6566 (define_insn "*andhi3_zarch"
6567 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6568 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6569 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
6570 (clobber (reg:CC CC_REGNUM))]
6571 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6572 "@
6573 nr\t%0,%2
6574 nrk\t%0,%1,%2
6575 nill\t%0,%x2
6576 #
6577 #"
6578 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6579 (set_attr "cpu_facility" "*,z196,*,*,*")
6580 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
6581 ])
6583 (define_insn "*andhi3_esa"
6584 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6585 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6586 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
6587 (clobber (reg:CC CC_REGNUM))]
6588 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6589 "@
6590 nr\t%0,%2
6591 #
6592 #"
6593 [(set_attr "op_type" "RR,SI,SS")
6594 (set_attr "z10prop" "z10_super_E1,*,*")
6595 ])
6597 (define_split
6598 [(set (match_operand:HI 0 "s_operand" "")
6599 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6600 (clobber (reg:CC CC_REGNUM))]
6601 "reload_completed"
6602 [(parallel
6603 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6604 (clobber (reg:CC CC_REGNUM))])]
6605 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6607 ;
6608 ; andqi3 instruction pattern(s).
6609 ;
6611 (define_insn "*andqi3_zarch"
6612 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6613 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6614 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6615 (clobber (reg:CC CC_REGNUM))]
6616 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6617 "@
6618 nr\t%0,%2
6619 nrk\t%0,%1,%2
6620 nill\t%0,%b2
6621 ni\t%S0,%b2
6622 niy\t%S0,%b2
6623 #"
6624 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6625 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6626 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
6628 (define_insn "*andqi3_esa"
6629 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6630 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6631 (match_operand:QI 2 "general_operand" "d,n,Q")))
6632 (clobber (reg:CC CC_REGNUM))]
6633 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6634 "@
6635 nr\t%0,%2
6636 ni\t%S0,%b2
6637 #"
6638 [(set_attr "op_type" "RR,SI,SS")
6639 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6641 ;
6642 ; Block and (NC) patterns.
6643 ;
6645 (define_insn "*nc"
6646 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6647 (and:BLK (match_dup 0)
6648 (match_operand:BLK 1 "memory_operand" "Q")))
6649 (use (match_operand 2 "const_int_operand" "n"))
6650 (clobber (reg:CC CC_REGNUM))]
6651 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6652 "nc\t%O0(%2,%R0),%S1"
6653 [(set_attr "op_type" "SS")
6654 (set_attr "z196prop" "z196_cracked")])
6656 (define_split
6657 [(set (match_operand 0 "memory_operand" "")
6658 (and (match_dup 0)
6659 (match_operand 1 "memory_operand" "")))
6660 (clobber (reg:CC CC_REGNUM))]
6661 "reload_completed
6662 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6663 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6664 [(parallel
6665 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6666 (use (match_dup 2))
6667 (clobber (reg:CC CC_REGNUM))])]
6668 {
6669 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6670 operands[0] = adjust_address (operands[0], BLKmode, 0);
6671 operands[1] = adjust_address (operands[1], BLKmode, 0);
6672 })
6674 (define_peephole2
6675 [(parallel
6676 [(set (match_operand:BLK 0 "memory_operand" "")
6677 (and:BLK (match_dup 0)
6678 (match_operand:BLK 1 "memory_operand" "")))
6679 (use (match_operand 2 "const_int_operand" ""))
6680 (clobber (reg:CC CC_REGNUM))])
6681 (parallel
6682 [(set (match_operand:BLK 3 "memory_operand" "")
6683 (and:BLK (match_dup 3)
6684 (match_operand:BLK 4 "memory_operand" "")))
6685 (use (match_operand 5 "const_int_operand" ""))
6686 (clobber (reg:CC CC_REGNUM))])]
6687 "s390_offset_p (operands[0], operands[3], operands[2])
6688 && s390_offset_p (operands[1], operands[4], operands[2])
6689 && !s390_overlap_p (operands[0], operands[1],
6690 INTVAL (operands[2]) + INTVAL (operands[5]))
6691 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6692 [(parallel
6693 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6694 (use (match_dup 8))
6695 (clobber (reg:CC CC_REGNUM))])]
6696 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6697 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6698 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6701 ;;
6702 ;;- Bit set (inclusive or) instructions.
6703 ;;
6705 (define_expand "ior<mode>3"
6706 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6707 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6708 (match_operand:INT 2 "general_operand" "")))
6709 (clobber (reg:CC CC_REGNUM))]
6710 ""
6711 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6713 ;
6714 ; iordi3 instruction pattern(s).
6715 ;
6717 (define_insn "*iordi3_cc"
6718 [(set (reg CC_REGNUM)
6719 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6720 (match_operand:DI 2 "general_operand" " d,d,RT"))
6721 (const_int 0)))
6722 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6723 (ior:DI (match_dup 1) (match_dup 2)))]
6724 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6725 "@
6726 ogr\t%0,%2
6727 ogrk\t%0,%1,%2
6728 og\t%0,%2"
6729 [(set_attr "op_type" "RRE,RRF,RXY")
6730 (set_attr "cpu_facility" "*,z196,*")
6731 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6733 (define_insn "*iordi3_cconly"
6734 [(set (reg CC_REGNUM)
6735 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
6736 (match_operand:DI 2 "general_operand" " d,d,RT"))
6737 (const_int 0)))
6738 (clobber (match_scratch:DI 0 "=d,d,d"))]
6739 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6740 "@
6741 ogr\t%0,%2
6742 ogrk\t%0,%1,%2
6743 og\t%0,%2"
6744 [(set_attr "op_type" "RRE,RRF,RXY")
6745 (set_attr "cpu_facility" "*,z196,*")
6746 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6748 (define_insn "*iordi3"
6749 [(set (match_operand:DI 0 "nonimmediate_operand"
6750 "=d, d, d, d, d, d,d,d, d, AQ,Q")
6751 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
6752 " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6753 (match_operand:DI 2 "general_operand"
6754 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6755 (clobber (reg:CC CC_REGNUM))]
6756 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6757 "@
6758 oihh\t%0,%i2
6759 oihl\t%0,%i2
6760 oilh\t%0,%i2
6761 oill\t%0,%i2
6762 oihf\t%0,%k2
6763 oilf\t%0,%k2
6764 ogr\t%0,%2
6765 ogrk\t%0,%1,%2
6766 og\t%0,%2
6767 #
6768 #"
6769 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6770 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
6771 (set_attr "z10prop" "z10_super_E1,
6772 z10_super_E1,
6773 z10_super_E1,
6774 z10_super_E1,
6775 z10_super_E1,
6776 z10_super_E1,
6777 z10_super_E1,
6778 *,
6779 z10_super_E1,
6780 *,
6781 *")])
6783 (define_split
6784 [(set (match_operand:DI 0 "s_operand" "")
6785 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6786 (clobber (reg:CC CC_REGNUM))]
6787 "reload_completed"
6788 [(parallel
6789 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6790 (clobber (reg:CC CC_REGNUM))])]
6791 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6793 ;
6794 ; iorsi3 instruction pattern(s).
6795 ;
6797 (define_insn "*iorsi3_cc"
6798 [(set (reg CC_REGNUM)
6799 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6800 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6801 (const_int 0)))
6802 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6803 (ior:SI (match_dup 1) (match_dup 2)))]
6804 "s390_match_ccmode(insn, CCTmode)"
6805 "@
6806 oilf\t%0,%o2
6807 or\t%0,%2
6808 ork\t%0,%1,%2
6809 o\t%0,%2
6810 oy\t%0,%2"
6811 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6812 (set_attr "cpu_facility" "*,*,z196,*,*")
6813 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6815 (define_insn "*iorsi3_cconly"
6816 [(set (reg CC_REGNUM)
6817 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6818 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6819 (const_int 0)))
6820 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6821 "s390_match_ccmode(insn, CCTmode)"
6822 "@
6823 oilf\t%0,%o2
6824 or\t%0,%2
6825 ork\t%0,%1,%2
6826 o\t%0,%2
6827 oy\t%0,%2"
6828 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6829 (set_attr "cpu_facility" "*,*,z196,*,*")
6830 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6832 (define_insn "*iorsi3_zarch"
6833 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
6834 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
6835 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
6836 (clobber (reg:CC CC_REGNUM))]
6837 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6838 "@
6839 oilh\t%0,%i2
6840 oill\t%0,%i2
6841 oilf\t%0,%o2
6842 or\t%0,%2
6843 ork\t%0,%1,%2
6844 o\t%0,%2
6845 oy\t%0,%2
6846 #
6847 #"
6848 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
6849 (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
6850 (set_attr "z10prop" "z10_super_E1,
6851 z10_super_E1,
6852 z10_super_E1,
6853 z10_super_E1,
6854 *,
6855 z10_super_E1,
6856 z10_super_E1,
6857 *,
6858 *")])
6860 (define_insn "*iorsi3_esa"
6861 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6862 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6863 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6864 (clobber (reg:CC CC_REGNUM))]
6865 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6866 "@
6867 or\t%0,%2
6868 o\t%0,%2
6869 #
6870 #"
6871 [(set_attr "op_type" "RR,RX,SI,SS")
6872 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6874 (define_split
6875 [(set (match_operand:SI 0 "s_operand" "")
6876 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6877 (clobber (reg:CC CC_REGNUM))]
6878 "reload_completed"
6879 [(parallel
6880 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6881 (clobber (reg:CC CC_REGNUM))])]
6882 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6884 ;
6885 ; iorhi3 instruction pattern(s).
6886 ;
6888 (define_insn "*iorhi3_zarch"
6889 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6890 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6891 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
6892 (clobber (reg:CC CC_REGNUM))]
6893 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6894 "@
6895 or\t%0,%2
6896 ork\t%0,%1,%2
6897 oill\t%0,%x2
6898 #
6899 #"
6900 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6901 (set_attr "cpu_facility" "*,z196,*,*,*")
6902 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
6904 (define_insn "*iorhi3_esa"
6905 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6906 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6907 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6908 (clobber (reg:CC CC_REGNUM))]
6909 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6910 "@
6911 or\t%0,%2
6912 #
6913 #"
6914 [(set_attr "op_type" "RR,SI,SS")
6915 (set_attr "z10prop" "z10_super_E1,*,*")])
6917 (define_split
6918 [(set (match_operand:HI 0 "s_operand" "")
6919 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6920 (clobber (reg:CC CC_REGNUM))]
6921 "reload_completed"
6922 [(parallel
6923 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6924 (clobber (reg:CC CC_REGNUM))])]
6925 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6927 ;
6928 ; iorqi3 instruction pattern(s).
6929 ;
6931 (define_insn "*iorqi3_zarch"
6932 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6933 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6934 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6935 (clobber (reg:CC CC_REGNUM))]
6936 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6937 "@
6938 or\t%0,%2
6939 ork\t%0,%1,%2
6940 oill\t%0,%b2
6941 oi\t%S0,%b2
6942 oiy\t%S0,%b2
6943 #"
6944 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6945 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6946 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
6947 z10_super,z10_super,*")])
6949 (define_insn "*iorqi3_esa"
6950 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6951 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6952 (match_operand:QI 2 "general_operand" "d,n,Q")))
6953 (clobber (reg:CC CC_REGNUM))]
6954 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6955 "@
6956 or\t%0,%2
6957 oi\t%S0,%b2
6958 #"
6959 [(set_attr "op_type" "RR,SI,SS")
6960 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6962 ;
6963 ; Block inclusive or (OC) patterns.
6964 ;
6966 (define_insn "*oc"
6967 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6968 (ior:BLK (match_dup 0)
6969 (match_operand:BLK 1 "memory_operand" "Q")))
6970 (use (match_operand 2 "const_int_operand" "n"))
6971 (clobber (reg:CC CC_REGNUM))]
6972 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6973 "oc\t%O0(%2,%R0),%S1"
6974 [(set_attr "op_type" "SS")
6975 (set_attr "z196prop" "z196_cracked")])
6977 (define_split
6978 [(set (match_operand 0 "memory_operand" "")
6979 (ior (match_dup 0)
6980 (match_operand 1 "memory_operand" "")))
6981 (clobber (reg:CC CC_REGNUM))]
6982 "reload_completed
6983 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6984 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6985 [(parallel
6986 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6987 (use (match_dup 2))
6988 (clobber (reg:CC CC_REGNUM))])]
6989 {
6990 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6991 operands[0] = adjust_address (operands[0], BLKmode, 0);
6992 operands[1] = adjust_address (operands[1], BLKmode, 0);
6993 })
6995 (define_peephole2
6996 [(parallel
6997 [(set (match_operand:BLK 0 "memory_operand" "")
6998 (ior:BLK (match_dup 0)
6999 (match_operand:BLK 1 "memory_operand" "")))
7000 (use (match_operand 2 "const_int_operand" ""))
7001 (clobber (reg:CC CC_REGNUM))])
7002 (parallel
7003 [(set (match_operand:BLK 3 "memory_operand" "")
7004 (ior:BLK (match_dup 3)
7005 (match_operand:BLK 4 "memory_operand" "")))
7006 (use (match_operand 5 "const_int_operand" ""))
7007 (clobber (reg:CC CC_REGNUM))])]
7008 "s390_offset_p (operands[0], operands[3], operands[2])
7009 && s390_offset_p (operands[1], operands[4], operands[2])
7010 && !s390_overlap_p (operands[0], operands[1],
7011 INTVAL (operands[2]) + INTVAL (operands[5]))
7012 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7013 [(parallel
7014 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
7015 (use (match_dup 8))
7016 (clobber (reg:CC CC_REGNUM))])]
7017 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7018 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7019 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7022 ;;
7023 ;;- Xor instructions.
7024 ;;
7026 (define_expand "xor<mode>3"
7027 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7028 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
7029 (match_operand:INT 2 "general_operand" "")))
7030 (clobber (reg:CC CC_REGNUM))]
7031 ""
7032 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
7034 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing
7035 ; simplifications. So its better to have something matching.
7036 (define_split
7037 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7038 (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))]
7039 ""
7040 [(parallel
7041 [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2)))
7042 (clobber (reg:CC CC_REGNUM))])]
7043 {
7044 operands[2] = constm1_rtx;
7045 if (!s390_logical_operator_ok_p (operands))
7046 FAIL;
7047 })
7049 ;
7050 ; xordi3 instruction pattern(s).
7051 ;
7053 (define_insn "*xordi3_cc"
7054 [(set (reg CC_REGNUM)
7055 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7056 (match_operand:DI 2 "general_operand" " d,d,RT"))
7057 (const_int 0)))
7058 (set (match_operand:DI 0 "register_operand" "=d,d, d")
7059 (xor:DI (match_dup 1) (match_dup 2)))]
7060 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7061 "@
7062 xgr\t%0,%2
7063 xgrk\t%0,%1,%2
7064 xg\t%0,%2"
7065 [(set_attr "op_type" "RRE,RRF,RXY")
7066 (set_attr "cpu_facility" "*,z196,*")
7067 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7069 (define_insn "*xordi3_cconly"
7070 [(set (reg CC_REGNUM)
7071 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7072 (match_operand:DI 2 "general_operand" " d,d,RT"))
7073 (const_int 0)))
7074 (clobber (match_scratch:DI 0 "=d,d, d"))]
7075 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7076 "@
7077 xgr\t%0,%2
7078 xgrk\t%0,%1,%2
7079 xg\t%0,%2"
7080 [(set_attr "op_type" "RRE,RRF,RXY")
7081 (set_attr "cpu_facility" "*,z196,*")
7082 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7084 (define_insn "*xordi3"
7085 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
7086 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
7087 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
7088 (clobber (reg:CC CC_REGNUM))]
7089 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7090 "@
7091 xihf\t%0,%k2
7092 xilf\t%0,%k2
7093 xgr\t%0,%2
7094 xgrk\t%0,%1,%2
7095 xg\t%0,%2
7096 #
7097 #"
7098 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
7099 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
7100 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
7101 *,z10_super_E1,*,*")])
7103 (define_split
7104 [(set (match_operand:DI 0 "s_operand" "")
7105 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7106 (clobber (reg:CC CC_REGNUM))]
7107 "reload_completed"
7108 [(parallel
7109 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7110 (clobber (reg:CC CC_REGNUM))])]
7111 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7113 ;
7114 ; xorsi3 instruction pattern(s).
7115 ;
7117 (define_insn "*xorsi3_cc"
7118 [(set (reg CC_REGNUM)
7119 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7120 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7121 (const_int 0)))
7122 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
7123 (xor:SI (match_dup 1) (match_dup 2)))]
7124 "s390_match_ccmode(insn, CCTmode)"
7125 "@
7126 xilf\t%0,%o2
7127 xr\t%0,%2
7128 xrk\t%0,%1,%2
7129 x\t%0,%2
7130 xy\t%0,%2"
7131 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7132 (set_attr "cpu_facility" "*,*,z196,*,*")
7133 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7134 z10_super_E1,z10_super_E1")])
7136 (define_insn "*xorsi3_cconly"
7137 [(set (reg CC_REGNUM)
7138 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7139 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7140 (const_int 0)))
7141 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
7142 "s390_match_ccmode(insn, CCTmode)"
7143 "@
7144 xilf\t%0,%o2
7145 xr\t%0,%2
7146 xrk\t%0,%1,%2
7147 x\t%0,%2
7148 xy\t%0,%2"
7149 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7150 (set_attr "cpu_facility" "*,*,z196,*,*")
7151 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7152 z10_super_E1,z10_super_E1")])
7154 (define_insn "*xorsi3"
7155 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
7156 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
7157 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
7158 (clobber (reg:CC CC_REGNUM))]
7159 "s390_logical_operator_ok_p (operands)"
7160 "@
7161 xilf\t%0,%o2
7162 xr\t%0,%2
7163 xrk\t%0,%1,%2
7164 x\t%0,%2
7165 xy\t%0,%2
7166 #
7167 #"
7168 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
7169 (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
7170 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7171 z10_super_E1,z10_super_E1,*,*")])
7173 (define_split
7174 [(set (match_operand:SI 0 "s_operand" "")
7175 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7176 (clobber (reg:CC CC_REGNUM))]
7177 "reload_completed"
7178 [(parallel
7179 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7180 (clobber (reg:CC CC_REGNUM))])]
7181 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7183 ;
7184 ; xorhi3 instruction pattern(s).
7185 ;
7187 (define_insn "*xorhi3"
7188 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7189 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
7190 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
7191 (clobber (reg:CC CC_REGNUM))]
7192 "s390_logical_operator_ok_p (operands)"
7193 "@
7194 xilf\t%0,%x2
7195 xr\t%0,%2
7196 xrk\t%0,%1,%2
7197 #
7198 #"
7199 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
7200 (set_attr "cpu_facility" "*,*,z196,*,*")
7201 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
7203 (define_split
7204 [(set (match_operand:HI 0 "s_operand" "")
7205 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7206 (clobber (reg:CC CC_REGNUM))]
7207 "reload_completed"
7208 [(parallel
7209 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7210 (clobber (reg:CC CC_REGNUM))])]
7211 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7213 ;
7214 ; xorqi3 instruction pattern(s).
7215 ;
7217 (define_insn "*xorqi3"
7218 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7219 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7220 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
7221 (clobber (reg:CC CC_REGNUM))]
7222 "s390_logical_operator_ok_p (operands)"
7223 "@
7224 xilf\t%0,%b2
7225 xr\t%0,%2
7226 xrk\t%0,%1,%2
7227 xi\t%S0,%b2
7228 xiy\t%S0,%b2
7229 #"
7230 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
7231 (set_attr "cpu_facility" "*,*,z196,*,*,*")
7232 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
7235 ;
7236 ; Block exclusive or (XC) patterns.
7237 ;
7239 (define_insn "*xc"
7240 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7241 (xor:BLK (match_dup 0)
7242 (match_operand:BLK 1 "memory_operand" "Q")))
7243 (use (match_operand 2 "const_int_operand" "n"))
7244 (clobber (reg:CC CC_REGNUM))]
7245 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7246 "xc\t%O0(%2,%R0),%S1"
7247 [(set_attr "op_type" "SS")])
7249 (define_split
7250 [(set (match_operand 0 "memory_operand" "")
7251 (xor (match_dup 0)
7252 (match_operand 1 "memory_operand" "")))
7253 (clobber (reg:CC CC_REGNUM))]
7254 "reload_completed
7255 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7256 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7257 [(parallel
7258 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
7259 (use (match_dup 2))
7260 (clobber (reg:CC CC_REGNUM))])]
7261 {
7262 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7263 operands[0] = adjust_address (operands[0], BLKmode, 0);
7264 operands[1] = adjust_address (operands[1], BLKmode, 0);
7265 })
7267 (define_peephole2
7268 [(parallel
7269 [(set (match_operand:BLK 0 "memory_operand" "")
7270 (xor:BLK (match_dup 0)
7271 (match_operand:BLK 1 "memory_operand" "")))
7272 (use (match_operand 2 "const_int_operand" ""))
7273 (clobber (reg:CC CC_REGNUM))])
7274 (parallel
7275 [(set (match_operand:BLK 3 "memory_operand" "")
7276 (xor:BLK (match_dup 3)
7277 (match_operand:BLK 4 "memory_operand" "")))
7278 (use (match_operand 5 "const_int_operand" ""))
7279 (clobber (reg:CC CC_REGNUM))])]
7280 "s390_offset_p (operands[0], operands[3], operands[2])
7281 && s390_offset_p (operands[1], operands[4], operands[2])
7282 && !s390_overlap_p (operands[0], operands[1],
7283 INTVAL (operands[2]) + INTVAL (operands[5]))
7284 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7285 [(parallel
7286 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7287 (use (match_dup 8))
7288 (clobber (reg:CC CC_REGNUM))])]
7289 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7290 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7291 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7293 ;
7294 ; Block xor (XC) patterns with src == dest.
7295 ;
7297 (define_insn "*xc_zero"
7298 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7299 (const_int 0))
7300 (use (match_operand 1 "const_int_operand" "n"))
7301 (clobber (reg:CC CC_REGNUM))]
7302 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7303 "xc\t%O0(%1,%R0),%S0"
7304 [(set_attr "op_type" "SS")
7305 (set_attr "z196prop" "z196_cracked")])
7307 (define_peephole2
7308 [(parallel
7309 [(set (match_operand:BLK 0 "memory_operand" "")
7310 (const_int 0))
7311 (use (match_operand 1 "const_int_operand" ""))
7312 (clobber (reg:CC CC_REGNUM))])
7313 (parallel
7314 [(set (match_operand:BLK 2 "memory_operand" "")
7315 (const_int 0))
7316 (use (match_operand 3 "const_int_operand" ""))
7317 (clobber (reg:CC CC_REGNUM))])]
7318 "s390_offset_p (operands[0], operands[2], operands[1])
7319 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7320 [(parallel
7321 [(set (match_dup 4) (const_int 0))
7322 (use (match_dup 5))
7323 (clobber (reg:CC CC_REGNUM))])]
7324 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7325 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7328 ;;
7329 ;;- Negate instructions.
7330 ;;
7332 ;
7333 ; neg(di|si)2 instruction pattern(s).
7334 ;
7336 (define_expand "neg<mode>2"
7337 [(parallel
7338 [(set (match_operand:DSI 0 "register_operand" "=d")
7339 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7340 (clobber (reg:CC CC_REGNUM))])]
7341 ""
7342 "")
7344 (define_insn "*negdi2_sign_cc"
7345 [(set (reg CC_REGNUM)
7346 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7347 (match_operand:SI 1 "register_operand" "d") 0)
7348 (const_int 32)) (const_int 32)))
7349 (const_int 0)))
7350 (set (match_operand:DI 0 "register_operand" "=d")
7351 (neg:DI (sign_extend:DI (match_dup 1))))]
7352 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7353 "lcgfr\t%0,%1"
7354 [(set_attr "op_type" "RRE")
7355 (set_attr "z10prop" "z10_c")])
7357 (define_insn "*negdi2_sign"
7358 [(set (match_operand:DI 0 "register_operand" "=d")
7359 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7360 (clobber (reg:CC CC_REGNUM))]
7361 "TARGET_ZARCH"
7362 "lcgfr\t%0,%1"
7363 [(set_attr "op_type" "RRE")
7364 (set_attr "z10prop" "z10_c")])
7366 ; lcr, lcgr
7367 (define_insn "*neg<mode>2_cc"
7368 [(set (reg CC_REGNUM)
7369 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7370 (const_int 0)))
7371 (set (match_operand:GPR 0 "register_operand" "=d")
7372 (neg:GPR (match_dup 1)))]
7373 "s390_match_ccmode (insn, CCAmode)"
7374 "lc<g>r\t%0,%1"
7375 [(set_attr "op_type" "RR<E>")
7376 (set_attr "z10prop" "z10_super_c_E1")])
7378 ; lcr, lcgr
7379 (define_insn "*neg<mode>2_cconly"
7380 [(set (reg CC_REGNUM)
7381 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7382 (const_int 0)))
7383 (clobber (match_scratch:GPR 0 "=d"))]
7384 "s390_match_ccmode (insn, CCAmode)"
7385 "lc<g>r\t%0,%1"
7386 [(set_attr "op_type" "RR<E>")
7387 (set_attr "z10prop" "z10_super_c_E1")])
7389 ; lcr, lcgr
7390 (define_insn "*neg<mode>2"
7391 [(set (match_operand:GPR 0 "register_operand" "=d")
7392 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7393 (clobber (reg:CC CC_REGNUM))]
7394 ""
7395 "lc<g>r\t%0,%1"
7396 [(set_attr "op_type" "RR<E>")
7397 (set_attr "z10prop" "z10_super_c_E1")])
7399 (define_insn "*negdi2_31"
7400 [(set (match_operand:DI 0 "register_operand" "=d")
7401 (neg:DI (match_operand:DI 1 "register_operand" "d")))
7402 (clobber (reg:CC CC_REGNUM))]
7403 "!TARGET_ZARCH"
7404 "#")
7406 ; Split a DImode NEG on 31bit into 2 SImode NEGs
7408 ; Doing the twos complement separately on the SImode parts does an
7409 ; unwanted +1 on the high part which needs to be subtracted afterwards
7410 ; ... unless the +1 on the low part created an overflow.
7412 (define_split
7413 [(set (match_operand:DI 0 "register_operand" "")
7414 (neg:DI (match_operand:DI 1 "register_operand" "")))
7415 (clobber (reg:CC CC_REGNUM))]
7416 "!TARGET_ZARCH
7417 && (REGNO (operands[0]) == REGNO (operands[1])
7418 || s390_split_ok_p (operands[0], operands[1], DImode, 0))
7419 && reload_completed"
7420 [(parallel
7421 [(set (match_dup 2) (neg:SI (match_dup 3)))
7422 (clobber (reg:CC CC_REGNUM))])
7423 (parallel
7424 [(set (reg:CCAP CC_REGNUM)
7425 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7426 (set (match_dup 4) (neg:SI (match_dup 5)))])
7427 (set (pc)
7428 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7429 (pc)
7430 (label_ref (match_dup 6))))
7431 (parallel
7432 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7433 (clobber (reg:CC CC_REGNUM))])
7434 (match_dup 6)]
7435 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7436 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7437 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7438 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7439 operands[6] = gen_label_rtx ();")
7441 ; Like above but first make a copy of the low part of the src operand
7442 ; since it might overlap with the high part of the destination.
7444 (define_split
7445 [(set (match_operand:DI 0 "register_operand" "")
7446 (neg:DI (match_operand:DI 1 "register_operand" "")))
7447 (clobber (reg:CC CC_REGNUM))]
7448 "!TARGET_ZARCH
7449 && s390_split_ok_p (operands[0], operands[1], DImode, 1)
7450 && reload_completed"
7451 [; Make a backup of op5 first
7452 (set (match_dup 4) (match_dup 5))
7453 ; Setting op2 here might clobber op5
7454 (parallel
7455 [(set (match_dup 2) (neg:SI (match_dup 3)))
7456 (clobber (reg:CC CC_REGNUM))])
7457 (parallel
7458 [(set (reg:CCAP CC_REGNUM)
7459 (compare:CCAP (neg:SI (match_dup 4)) (const_int 0)))
7460 (set (match_dup 4) (neg:SI (match_dup 4)))])
7461 (set (pc)
7462 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7463 (pc)
7464 (label_ref (match_dup 6))))
7465 (parallel
7466 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7467 (clobber (reg:CC CC_REGNUM))])
7468 (match_dup 6)]
7469 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7470 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7471 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7472 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7473 operands[6] = gen_label_rtx ();")
7475 ;
7476 ; neg(df|sf)2 instruction pattern(s).
7477 ;
7479 (define_expand "neg<mode>2"
7480 [(parallel
7481 [(set (match_operand:BFP 0 "register_operand" "=f")
7482 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7483 (clobber (reg:CC CC_REGNUM))])]
7484 "TARGET_HARD_FLOAT"
7485 "")
7487 ; lcxbr, lcdbr, lcebr
7488 (define_insn "*neg<mode>2_cc"
7489 [(set (reg CC_REGNUM)
7490 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7491 (match_operand:BFP 2 "const0_operand" "")))
7492 (set (match_operand:BFP 0 "register_operand" "=f")
7493 (neg:BFP (match_dup 1)))]
7494 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7495 "lc<xde>br\t%0,%1"
7496 [(set_attr "op_type" "RRE")
7497 (set_attr "type" "fsimp<mode>")])
7499 ; lcxbr, lcdbr, lcebr
7500 (define_insn "*neg<mode>2_cconly"
7501 [(set (reg CC_REGNUM)
7502 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7503 (match_operand:BFP 2 "const0_operand" "")))
7504 (clobber (match_scratch:BFP 0 "=f"))]
7505 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7506 "lc<xde>br\t%0,%1"
7507 [(set_attr "op_type" "RRE")
7508 (set_attr "type" "fsimp<mode>")])
7510 ; lcdfr
7511 (define_insn "*neg<mode>2_nocc"
7512 [(set (match_operand:FP 0 "register_operand" "=f")
7513 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7514 "TARGET_DFP"
7515 "lcdfr\t%0,%1"
7516 [(set_attr "op_type" "RRE")
7517 (set_attr "type" "fsimp<mode>")])
7519 ; lcxbr, lcdbr, lcebr
7520 (define_insn "*neg<mode>2"
7521 [(set (match_operand:BFP 0 "register_operand" "=f")
7522 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7523 (clobber (reg:CC CC_REGNUM))]
7524 "TARGET_HARD_FLOAT"
7525 "lc<xde>br\t%0,%1"
7526 [(set_attr "op_type" "RRE")
7527 (set_attr "type" "fsimp<mode>")])
7530 ;;
7531 ;;- Absolute value instructions.
7532 ;;
7534 ;
7535 ; abs(di|si)2 instruction pattern(s).
7536 ;
7538 (define_insn "*absdi2_sign_cc"
7539 [(set (reg CC_REGNUM)
7540 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7541 (match_operand:SI 1 "register_operand" "d") 0)
7542 (const_int 32)) (const_int 32)))
7543 (const_int 0)))
7544 (set (match_operand:DI 0 "register_operand" "=d")
7545 (abs:DI (sign_extend:DI (match_dup 1))))]
7546 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7547 "lpgfr\t%0,%1"
7548 [(set_attr "op_type" "RRE")
7549 (set_attr "z10prop" "z10_c")])
7551 (define_insn "*absdi2_sign"
7552 [(set (match_operand:DI 0 "register_operand" "=d")
7553 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7554 (clobber (reg:CC CC_REGNUM))]
7555 "TARGET_ZARCH"
7556 "lpgfr\t%0,%1"
7557 [(set_attr "op_type" "RRE")
7558 (set_attr "z10prop" "z10_c")])
7560 ; lpr, lpgr
7561 (define_insn "*abs<mode>2_cc"
7562 [(set (reg CC_REGNUM)
7563 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
7564 (const_int 0)))
7565 (set (match_operand:GPR 0 "register_operand" "=d")
7566 (abs:GPR (match_dup 1)))]
7567 "s390_match_ccmode (insn, CCAmode)"
7568 "lp<g>r\t%0,%1"
7569 [(set_attr "op_type" "RR<E>")
7570 (set_attr "z10prop" "z10_c")])
7572 ; lpr, lpgr
7573 (define_insn "*abs<mode>2_cconly"
7574 [(set (reg CC_REGNUM)
7575 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
7576 (const_int 0)))
7577 (clobber (match_scratch:GPR 0 "=d"))]
7578 "s390_match_ccmode (insn, CCAmode)"
7579 "lp<g>r\t%0,%1"
7580 [(set_attr "op_type" "RR<E>")
7581 (set_attr "z10prop" "z10_c")])
7583 ; lpr, lpgr
7584 (define_insn "abs<mode>2"
7585 [(set (match_operand:GPR 0 "register_operand" "=d")
7586 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7587 (clobber (reg:CC CC_REGNUM))]
7588 ""
7589 "lp<g>r\t%0,%1"
7590 [(set_attr "op_type" "RR<E>")
7591 (set_attr "z10prop" "z10_c")])
7593 ;
7594 ; abs(df|sf)2 instruction pattern(s).
7595 ;
7597 (define_expand "abs<mode>2"
7598 [(parallel
7599 [(set (match_operand:BFP 0 "register_operand" "=f")
7600 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7601 (clobber (reg:CC CC_REGNUM))])]
7602 "TARGET_HARD_FLOAT"
7603 "")
7605 ; lpxbr, lpdbr, lpebr
7606 (define_insn "*abs<mode>2_cc"
7607 [(set (reg CC_REGNUM)
7608 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7609 (match_operand:BFP 2 "const0_operand" "")))
7610 (set (match_operand:BFP 0 "register_operand" "=f")
7611 (abs:BFP (match_dup 1)))]
7612 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7613 "lp<xde>br\t%0,%1"
7614 [(set_attr "op_type" "RRE")
7615 (set_attr "type" "fsimp<mode>")])
7617 ; lpxbr, lpdbr, lpebr
7618 (define_insn "*abs<mode>2_cconly"
7619 [(set (reg CC_REGNUM)
7620 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7621 (match_operand:BFP 2 "const0_operand" "")))
7622 (clobber (match_scratch:BFP 0 "=f"))]
7623 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7624 "lp<xde>br\t%0,%1"
7625 [(set_attr "op_type" "RRE")
7626 (set_attr "type" "fsimp<mode>")])
7628 ; lpdfr
7629 (define_insn "*abs<mode>2_nocc"
7630 [(set (match_operand:FP 0 "register_operand" "=f")
7631 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7632 "TARGET_DFP"
7633 "lpdfr\t%0,%1"
7634 [(set_attr "op_type" "RRE")
7635 (set_attr "type" "fsimp<mode>")])
7637 ; lpxbr, lpdbr, lpebr
7638 (define_insn "*abs<mode>2"
7639 [(set (match_operand:BFP 0 "register_operand" "=f")
7640 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7641 (clobber (reg:CC CC_REGNUM))]
7642 "TARGET_HARD_FLOAT"
7643 "lp<xde>br\t%0,%1"
7644 [(set_attr "op_type" "RRE")
7645 (set_attr "type" "fsimp<mode>")])
7648 ;;
7649 ;;- Negated absolute value instructions
7650 ;;
7652 ;
7653 ; Integer
7654 ;
7656 (define_insn "*negabsdi2_sign_cc"
7657 [(set (reg CC_REGNUM)
7658 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7659 (match_operand:SI 1 "register_operand" "d") 0)
7660 (const_int 32)) (const_int 32))))
7661 (const_int 0)))
7662 (set (match_operand:DI 0 "register_operand" "=d")
7663 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
7664 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7665 "lngfr\t%0,%1"
7666 [(set_attr "op_type" "RRE")
7667 (set_attr "z10prop" "z10_c")])
7669 (define_insn "*negabsdi2_sign"
7670 [(set (match_operand:DI 0 "register_operand" "=d")
7671 (neg:DI (abs:DI (sign_extend:DI
7672 (match_operand:SI 1 "register_operand" "d")))))
7673 (clobber (reg:CC CC_REGNUM))]
7674 "TARGET_ZARCH"
7675 "lngfr\t%0,%1"
7676 [(set_attr "op_type" "RRE")
7677 (set_attr "z10prop" "z10_c")])
7679 ; lnr, lngr
7680 (define_insn "*negabs<mode>2_cc"
7681 [(set (reg CC_REGNUM)
7682 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7683 (const_int 0)))
7684 (set (match_operand:GPR 0 "register_operand" "=d")
7685 (neg:GPR (abs:GPR (match_dup 1))))]
7686 "s390_match_ccmode (insn, CCAmode)"
7687 "ln<g>r\t%0,%1"
7688 [(set_attr "op_type" "RR<E>")
7689 (set_attr "z10prop" "z10_c")])
7691 ; lnr, lngr
7692 (define_insn "*negabs<mode>2_cconly"
7693 [(set (reg CC_REGNUM)
7694 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7695 (const_int 0)))
7696 (clobber (match_scratch:GPR 0 "=d"))]
7697 "s390_match_ccmode (insn, CCAmode)"
7698 "ln<g>r\t%0,%1"
7699 [(set_attr "op_type" "RR<E>")
7700 (set_attr "z10prop" "z10_c")])
7702 ; lnr, lngr
7703 (define_insn "*negabs<mode>2"
7704 [(set (match_operand:GPR 0 "register_operand" "=d")
7705 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
7706 (clobber (reg:CC CC_REGNUM))]
7707 ""
7708 "ln<g>r\t%0,%1"
7709 [(set_attr "op_type" "RR<E>")
7710 (set_attr "z10prop" "z10_c")])
7712 ;
7713 ; Floating point
7714 ;
7716 ; lnxbr, lndbr, lnebr
7717 (define_insn "*negabs<mode>2_cc"
7718 [(set (reg CC_REGNUM)
7719 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7720 (match_operand:BFP 2 "const0_operand" "")))
7721 (set (match_operand:BFP 0 "register_operand" "=f")
7722 (neg:BFP (abs:BFP (match_dup 1))))]
7723 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7724 "ln<xde>br\t%0,%1"
7725 [(set_attr "op_type" "RRE")
7726 (set_attr "type" "fsimp<mode>")])
7728 ; lnxbr, lndbr, lnebr
7729 (define_insn "*negabs<mode>2_cconly"
7730 [(set (reg CC_REGNUM)
7731 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7732 (match_operand:BFP 2 "const0_operand" "")))
7733 (clobber (match_scratch:BFP 0 "=f"))]
7734 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7735 "ln<xde>br\t%0,%1"
7736 [(set_attr "op_type" "RRE")
7737 (set_attr "type" "fsimp<mode>")])
7739 ; lndfr
7740 (define_insn "*negabs<mode>2_nocc"
7741 [(set (match_operand:FP 0 "register_operand" "=f")
7742 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7743 "TARGET_DFP"
7744 "lndfr\t%0,%1"
7745 [(set_attr "op_type" "RRE")
7746 (set_attr "type" "fsimp<mode>")])
7748 ; lnxbr, lndbr, lnebr
7749 (define_insn "*negabs<mode>2"
7750 [(set (match_operand:BFP 0 "register_operand" "=f")
7751 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7752 (clobber (reg:CC CC_REGNUM))]
7753 "TARGET_HARD_FLOAT"
7754 "ln<xde>br\t%0,%1"
7755 [(set_attr "op_type" "RRE")
7756 (set_attr "type" "fsimp<mode>")])
7758 ;;
7759 ;;- Square root instructions.
7760 ;;
7762 ;
7763 ; sqrt(df|sf)2 instruction pattern(s).
7764 ;
7766 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7767 (define_insn "sqrt<mode>2"
7768 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7769 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7770 "TARGET_HARD_FLOAT"
7771 "@
7772 sq<xde>br\t%0,%1
7773 sq<xde>b\t%0,%1"
7774 [(set_attr "op_type" "RRE,RXE")
7775 (set_attr "type" "fsqrt<mode>")])
7778 ;;
7779 ;;- One complement instructions.
7780 ;;
7782 ;
7783 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7784 ;
7786 (define_expand "one_cmpl<mode>2"
7787 [(parallel
7788 [(set (match_operand:INT 0 "register_operand" "")
7789 (xor:INT (match_operand:INT 1 "register_operand" "")
7790 (const_int -1)))
7791 (clobber (reg:CC CC_REGNUM))])]
7792 ""
7793 "")
7796 ;;
7797 ;; Find leftmost bit instructions.
7798 ;;
7800 (define_expand "clzdi2"
7801 [(set (match_operand:DI 0 "register_operand" "=d")
7802 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7803 "TARGET_EXTIMM && TARGET_ZARCH"
7804 {
7805 rtx insn, clz_equal;
7806 rtx wide_reg = gen_reg_rtx (TImode);
7807 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7809 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7811 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7813 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7814 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7816 DONE;
7817 })
7819 (define_insn "clztidi2"
7820 [(set (match_operand:TI 0 "register_operand" "=d")
7821 (ior:TI
7822 (ashift:TI
7823 (zero_extend:TI
7824 (xor:DI (match_operand:DI 1 "register_operand" "d")
7825 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7826 (subreg:SI (clz:DI (match_dup 1)) 4))))
7828 (const_int 64))
7829 (zero_extend:TI (clz:DI (match_dup 1)))))
7830 (clobber (reg:CC CC_REGNUM))]
7831 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7832 == (unsigned HOST_WIDE_INT) 1 << 63
7833 && TARGET_EXTIMM && TARGET_ZARCH"
7834 "flogr\t%0,%1"
7835 [(set_attr "op_type" "RRE")])
7838 ;;
7839 ;;- Rotate instructions.
7840 ;;
7842 ;
7843 ; rotl(di|si)3 instruction pattern(s).
7844 ;
7846 ; rll, rllg
7847 (define_insn "rotl<mode>3"
7848 [(set (match_operand:GPR 0 "register_operand" "=d")
7849 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7850 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7851 "TARGET_CPU_ZARCH"
7852 "rll<g>\t%0,%1,%Y2"
7853 [(set_attr "op_type" "RSE")
7854 (set_attr "atype" "reg")
7855 (set_attr "z10prop" "z10_super_E1")])
7857 ; rll, rllg
7858 (define_insn "*rotl<mode>3_and"
7859 [(set (match_operand:GPR 0 "register_operand" "=d")
7860 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7861 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7862 (match_operand:SI 3 "const_int_operand" "n"))))]
7863 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7864 "rll<g>\t%0,%1,%Y2"
7865 [(set_attr "op_type" "RSE")
7866 (set_attr "atype" "reg")
7867 (set_attr "z10prop" "z10_super_E1")])
7870 ;;
7871 ;;- Shift instructions.
7872 ;;
7874 ;
7875 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7876 ; Left shifts and logical right shifts
7878 (define_expand "<shift><mode>3"
7879 [(set (match_operand:DSI 0 "register_operand" "")
7880 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7881 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7882 ""
7883 "")
7885 ; sldl, srdl
7886 (define_insn "*<shift>di3_31"
7887 [(set (match_operand:DI 0 "register_operand" "=d")
7888 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7889 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7890 "!TARGET_ZARCH"
7891 "s<lr>dl\t%0,%Y2"
7892 [(set_attr "op_type" "RS")
7893 (set_attr "atype" "reg")
7894 (set_attr "z196prop" "z196_cracked")])
7896 ; sll, srl, sllg, srlg, sllk, srlk
7897 (define_insn "*<shift><mode>3"
7898 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7899 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7900 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
7901 ""
7902 "@
7903 s<lr>l<g>\t%0,<1>%Y2
7904 s<lr>l<gk>\t%0,%1,%Y2"
7905 [(set_attr "op_type" "RS<E>,RSY")
7906 (set_attr "atype" "reg,reg")
7907 (set_attr "cpu_facility" "*,z196")
7908 (set_attr "z10prop" "z10_super_E1,*")])
7910 ; sldl, srdl
7911 (define_insn "*<shift>di3_31_and"
7912 [(set (match_operand:DI 0 "register_operand" "=d")
7913 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7914 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7915 (match_operand:SI 3 "const_int_operand" "n"))))]
7916 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7917 "s<lr>dl\t%0,%Y2"
7918 [(set_attr "op_type" "RS")
7919 (set_attr "atype" "reg")])
7921 ; sll, srl, sllg, srlg, sllk, srlk
7922 (define_insn "*<shift><mode>3_and"
7923 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7924 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7925 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7926 (match_operand:SI 3 "const_int_operand" "n,n"))))]
7927 "(INTVAL (operands[3]) & 63) == 63"
7928 "@
7929 s<lr>l<g>\t%0,<1>%Y2
7930 s<lr>l<gk>\t%0,%1,%Y2"
7931 [(set_attr "op_type" "RS<E>,RSY")
7932 (set_attr "atype" "reg,reg")
7933 (set_attr "cpu_facility" "*,z196")
7934 (set_attr "z10prop" "z10_super_E1,*")])
7936 ;
7937 ; ashr(di|si)3 instruction pattern(s).
7938 ; Arithmetic right shifts
7940 (define_expand "ashr<mode>3"
7941 [(parallel
7942 [(set (match_operand:DSI 0 "register_operand" "")
7943 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7944 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7945 (clobber (reg:CC CC_REGNUM))])]
7946 ""
7947 "")
7949 (define_insn "*ashrdi3_cc_31"
7950 [(set (reg CC_REGNUM)
7951 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7952 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7953 (const_int 0)))
7954 (set (match_operand:DI 0 "register_operand" "=d")
7955 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7956 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7957 "srda\t%0,%Y2"
7958 [(set_attr "op_type" "RS")
7959 (set_attr "atype" "reg")])
7961 (define_insn "*ashrdi3_cconly_31"
7962 [(set (reg CC_REGNUM)
7963 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7964 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7965 (const_int 0)))
7966 (clobber (match_scratch:DI 0 "=d"))]
7967 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7968 "srda\t%0,%Y2"
7969 [(set_attr "op_type" "RS")
7970 (set_attr "atype" "reg")])
7972 (define_insn "*ashrdi3_31"
7973 [(set (match_operand:DI 0 "register_operand" "=d")
7974 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7975 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7976 (clobber (reg:CC CC_REGNUM))]
7977 "!TARGET_ZARCH"
7978 "srda\t%0,%Y2"
7979 [(set_attr "op_type" "RS")
7980 (set_attr "atype" "reg")])
7982 ; sra, srag, srak
7983 (define_insn "*ashr<mode>3_cc"
7984 [(set (reg CC_REGNUM)
7985 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7986 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7987 (const_int 0)))
7988 (set (match_operand:GPR 0 "register_operand" "=d,d")
7989 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7990 "s390_match_ccmode(insn, CCSmode)"
7991 "@
7992 sra<g>\t%0,<1>%Y2
7993 sra<gk>\t%0,%1,%Y2"
7994 [(set_attr "op_type" "RS<E>,RSY")
7995 (set_attr "atype" "reg,reg")
7996 (set_attr "cpu_facility" "*,z196")
7997 (set_attr "z10prop" "z10_super_E1,*")])
7999 ; sra, srag, srak
8000 (define_insn "*ashr<mode>3_cconly"
8001 [(set (reg CC_REGNUM)
8002 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8003 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
8004 (const_int 0)))
8005 (clobber (match_scratch:GPR 0 "=d,d"))]
8006 "s390_match_ccmode(insn, CCSmode)"
8007 "@
8008 sra<g>\t%0,<1>%Y2
8009 sra<gk>\t%0,%1,%Y2"
8010 [(set_attr "op_type" "RS<E>,RSY")
8011 (set_attr "atype" "reg,reg")
8012 (set_attr "cpu_facility" "*,z196")
8013 (set_attr "z10prop" "z10_super_E1,*")])
8015 ; sra, srag
8016 (define_insn "*ashr<mode>3"
8017 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8018 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8019 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
8020 (clobber (reg:CC CC_REGNUM))]
8021 ""
8022 "@
8023 sra<g>\t%0,<1>%Y2
8024 sra<gk>\t%0,%1,%Y2"
8025 [(set_attr "op_type" "RS<E>,RSY")
8026 (set_attr "atype" "reg,reg")
8027 (set_attr "cpu_facility" "*,z196")
8028 (set_attr "z10prop" "z10_super_E1,*")])
8031 ; shift pattern with implicit ANDs
8033 (define_insn "*ashrdi3_cc_31_and"
8034 [(set (reg CC_REGNUM)
8035 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8036 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8037 (match_operand:SI 3 "const_int_operand" "n")))
8038 (const_int 0)))
8039 (set (match_operand:DI 0 "register_operand" "=d")
8040 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8041 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
8042 && (INTVAL (operands[3]) & 63) == 63"
8043 "srda\t%0,%Y2"
8044 [(set_attr "op_type" "RS")
8045 (set_attr "atype" "reg")])
8047 (define_insn "*ashrdi3_cconly_31_and"
8048 [(set (reg CC_REGNUM)
8049 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8050 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8051 (match_operand:SI 3 "const_int_operand" "n")))
8052 (const_int 0)))
8053 (clobber (match_scratch:DI 0 "=d"))]
8054 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
8055 && (INTVAL (operands[3]) & 63) == 63"
8056 "srda\t%0,%Y2"
8057 [(set_attr "op_type" "RS")
8058 (set_attr "atype" "reg")])
8060 (define_insn "*ashrdi3_31_and"
8061 [(set (match_operand:DI 0 "register_operand" "=d")
8062 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8063 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8064 (match_operand:SI 3 "const_int_operand" "n"))))
8065 (clobber (reg:CC CC_REGNUM))]
8066 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8067 "srda\t%0,%Y2"
8068 [(set_attr "op_type" "RS")
8069 (set_attr "atype" "reg")])
8071 ; sra, srag, srak
8072 (define_insn "*ashr<mode>3_cc_and"
8073 [(set (reg CC_REGNUM)
8074 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8075 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8076 (match_operand:SI 3 "const_int_operand" "n,n")))
8077 (const_int 0)))
8078 (set (match_operand:GPR 0 "register_operand" "=d,d")
8079 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8080 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8081 "@
8082 sra<g>\t%0,<1>%Y2
8083 sra<gk>\t%0,%1,%Y2"
8084 [(set_attr "op_type" "RS<E>,RSY")
8085 (set_attr "atype" "reg,reg")
8086 (set_attr "cpu_facility" "*,z196")
8087 (set_attr "z10prop" "z10_super_E1,*")])
8089 ; sra, srag, srak
8090 (define_insn "*ashr<mode>3_cconly_and"
8091 [(set (reg CC_REGNUM)
8092 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8093 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8094 (match_operand:SI 3 "const_int_operand" "n,n")))
8095 (const_int 0)))
8096 (clobber (match_scratch:GPR 0 "=d,d"))]
8097 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8098 "@
8099 sra<g>\t%0,<1>%Y2
8100 sra<gk>\t%0,%1,%Y2"
8101 [(set_attr "op_type" "RS<E>,RSY")
8102 (set_attr "atype" "reg,reg")
8103 (set_attr "cpu_facility" "*,z196")
8104 (set_attr "z10prop" "z10_super_E1,*")])
8106 ; sra, srag, srak
8107 (define_insn "*ashr<mode>3_and"
8108 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8109 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8110 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8111 (match_operand:SI 3 "const_int_operand" "n,n"))))
8112 (clobber (reg:CC CC_REGNUM))]
8113 "(INTVAL (operands[3]) & 63) == 63"
8114 "@
8115 sra<g>\t%0,<1>%Y2
8116 sra<gk>\t%0,%1,%Y2"
8117 [(set_attr "op_type" "RS<E>,RSY")
8118 (set_attr "atype" "reg,reg")
8119 (set_attr "cpu_facility" "*,z196")
8120 (set_attr "z10prop" "z10_super_E1,*")])
8123 ;;
8124 ;; Branch instruction patterns.
8125 ;;
8127 (define_expand "cbranch<mode>4"
8128 [(set (pc)
8129 (if_then_else (match_operator 0 "comparison_operator"
8130 [(match_operand:GPR 1 "register_operand" "")
8131 (match_operand:GPR 2 "general_operand" "")])
8132 (label_ref (match_operand 3 "" ""))
8133 (pc)))]
8134 ""
8135 "s390_emit_jump (operands[3],
8136 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8137 DONE;")
8139 (define_expand "cbranch<mode>4"
8140 [(set (pc)
8141 (if_then_else (match_operator 0 "comparison_operator"
8142 [(match_operand:FP 1 "register_operand" "")
8143 (match_operand:FP 2 "general_operand" "")])
8144 (label_ref (match_operand 3 "" ""))
8145 (pc)))]
8146 "TARGET_HARD_FLOAT"
8147 "s390_emit_jump (operands[3],
8148 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8149 DONE;")
8151 (define_expand "cbranchcc4"
8152 [(set (pc)
8153 (if_then_else (match_operator 0 "s390_comparison"
8154 [(match_operand 1 "cc_reg_operand" "")
8155 (match_operand 2 "const_int_operand" "")])
8156 (label_ref (match_operand 3 "" ""))
8157 (pc)))]
8158 ""
8159 "")
8162 ;;
8163 ;;- Conditional jump instructions.
8164 ;;
8166 (define_insn "*cjump_64"
8167 [(set (pc)
8168 (if_then_else
8169 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8170 (match_operand 2 "const_int_operand" "")])
8171 (label_ref (match_operand 0 "" ""))
8172 (pc)))]
8173 "TARGET_CPU_ZARCH"
8174 {
8175 if (get_attr_length (insn) == 4)
8176 return "j%C1\t%l0";
8177 else
8178 return "jg%C1\t%l0";
8179 }
8180 [(set_attr "op_type" "RI")
8181 (set_attr "type" "branch")
8182 (set (attr "length")
8183 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8184 (const_int 4) (const_int 6)))])
8186 (define_insn "*cjump_31"
8187 [(set (pc)
8188 (if_then_else
8189 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8190 (match_operand 2 "const_int_operand" "")])
8191 (label_ref (match_operand 0 "" ""))
8192 (pc)))]
8193 "!TARGET_CPU_ZARCH"
8194 {
8195 gcc_assert (get_attr_length (insn) == 4);
8196 return "j%C1\t%l0";
8197 }
8198 [(set_attr "op_type" "RI")
8199 (set_attr "type" "branch")
8200 (set (attr "length")
8201 (if_then_else (not (match_test "flag_pic"))
8202 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8203 (const_int 4) (const_int 6))
8204 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8205 (const_int 4) (const_int 8))))])
8207 (define_insn "*cjump_long"
8208 [(set (pc)
8209 (if_then_else
8210 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8211 (match_operand 0 "address_operand" "ZQZR")
8212 (pc)))]
8213 ""
8214 {
8215 if (get_attr_op_type (insn) == OP_TYPE_RR)
8216 return "b%C1r\t%0";
8217 else
8218 return "b%C1\t%a0";
8219 }
8220 [(set (attr "op_type")
8221 (if_then_else (match_operand 0 "register_operand" "")
8222 (const_string "RR") (const_string "RX")))
8223 (set_attr "type" "branch")
8224 (set_attr "atype" "agen")])
8226 ;; A conditional return instruction.
8227 (define_insn "*c<code>"
8228 [(set (pc)
8229 (if_then_else
8230 (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8231 (ANY_RETURN)
8232 (pc)))]
8233 "s390_can_use_<code>_insn ()"
8234 "b%C0r\t%%r14"
8235 [(set_attr "op_type" "RR")
8236 (set_attr "type" "jsr")
8237 (set_attr "atype" "agen")])
8239 ;;
8240 ;;- Negated conditional jump instructions.
8241 ;;
8243 (define_insn "*icjump_64"
8244 [(set (pc)
8245 (if_then_else
8246 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8247 (pc)
8248 (label_ref (match_operand 0 "" ""))))]
8249 "TARGET_CPU_ZARCH"
8250 {
8251 if (get_attr_length (insn) == 4)
8252 return "j%D1\t%l0";
8253 else
8254 return "jg%D1\t%l0";
8255 }
8256 [(set_attr "op_type" "RI")
8257 (set_attr "type" "branch")
8258 (set (attr "length")
8259 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8260 (const_int 4) (const_int 6)))])
8262 (define_insn "*icjump_31"
8263 [(set (pc)
8264 (if_then_else
8265 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8266 (pc)
8267 (label_ref (match_operand 0 "" ""))))]
8268 "!TARGET_CPU_ZARCH"
8269 {
8270 gcc_assert (get_attr_length (insn) == 4);
8271 return "j%D1\t%l0";
8272 }
8273 [(set_attr "op_type" "RI")
8274 (set_attr "type" "branch")
8275 (set (attr "length")
8276 (if_then_else (not (match_test "flag_pic"))
8277 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8278 (const_int 4) (const_int 6))
8279 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8280 (const_int 4) (const_int 8))))])
8282 (define_insn "*icjump_long"
8283 [(set (pc)
8284 (if_then_else
8285 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8286 (pc)
8287 (match_operand 0 "address_operand" "ZQZR")))]
8288 ""
8289 {
8290 if (get_attr_op_type (insn) == OP_TYPE_RR)
8291 return "b%D1r\t%0";
8292 else
8293 return "b%D1\t%a0";
8294 }
8295 [(set (attr "op_type")
8296 (if_then_else (match_operand 0 "register_operand" "")
8297 (const_string "RR") (const_string "RX")))
8298 (set_attr "type" "branch")
8299 (set_attr "atype" "agen")])
8301 ;;
8302 ;;- Trap instructions.
8303 ;;
8305 (define_insn "trap"
8306 [(trap_if (const_int 1) (const_int 0))]
8307 ""
8308 "j\t.+2"
8309 [(set_attr "op_type" "RI")
8310 (set_attr "type" "branch")])
8312 (define_expand "ctrap<mode>4"
8313 [(trap_if (match_operator 0 "comparison_operator"
8314 [(match_operand:GPR 1 "register_operand" "")
8315 (match_operand:GPR 2 "general_operand" "")])
8316 (match_operand 3 "const0_operand" ""))]
8317 ""
8318 {
8319 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8320 operands[1], operands[2]);
8321 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8322 DONE;
8323 })
8325 (define_expand "ctrap<mode>4"
8326 [(trap_if (match_operator 0 "comparison_operator"
8327 [(match_operand:FP 1 "register_operand" "")
8328 (match_operand:FP 2 "general_operand" "")])
8329 (match_operand 3 "const0_operand" ""))]
8330 ""
8331 {
8332 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8333 operands[1], operands[2]);
8334 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8335 DONE;
8336 })
8338 (define_insn "condtrap"
8339 [(trap_if (match_operator 0 "s390_comparison"
8340 [(match_operand 1 "cc_reg_operand" "c")
8341 (const_int 0)])
8342 (const_int 0))]
8343 ""
8344 "j%C0\t.+2";
8345 [(set_attr "op_type" "RI")
8346 (set_attr "type" "branch")])
8348 ; crt, cgrt, cit, cgit
8349 (define_insn "*cmp_and_trap_signed_int<mode>"
8350 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8351 [(match_operand:GPR 1 "register_operand" "d,d")
8352 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8353 (const_int 0))]
8354 "TARGET_Z10"
8355 "@
8356 c<g>rt%C0\t%1,%2
8357 c<g>it%C0\t%1,%h2"
8358 [(set_attr "op_type" "RRF,RIE")
8359 (set_attr "type" "branch")
8360 (set_attr "z10prop" "z10_super_c,z10_super")])
8362 ; clrt, clgrt, clfit, clgit, clt, clgt
8363 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8364 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8365 [(match_operand:GPR 1 "register_operand" "d,d, d")
8366 (match_operand:GPR 2 "general_operand" "d,D,RT")])
8367 (const_int 0))]
8368 "TARGET_Z10"
8369 "@
8370 cl<g>rt%C0\t%1,%2
8371 cl<gf>it%C0\t%1,%x2
8372 cl<g>t%C0\t%1,%2"
8373 [(set_attr "op_type" "RRF,RIE,RSY")
8374 (set_attr "type" "branch")
8375 (set_attr "z10prop" "z10_super_c,z10_super,*")
8376 (set_attr "cpu_facility" "z10,z10,zEC12")])
8378 ; lat, lgat
8379 (define_insn "*load_and_trap<mode>"
8380 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT")
8381 (const_int 0))
8382 (const_int 0))
8383 (set (match_operand:GPR 1 "register_operand" "=d")
8384 (match_dup 0))]
8385 "TARGET_ZEC12"
8386 "l<g>at\t%1,%0"
8387 [(set_attr "op_type" "RXY")])
8390 ;;
8391 ;;- Loop instructions.
8392 ;;
8393 ;; This is all complicated by the fact that since this is a jump insn
8394 ;; we must handle our own output reloads.
8396 ;; branch on index
8398 ; This splitter will be matched by combine and has to add the 2 moves
8399 ; necessary to load the compare and the increment values into a
8400 ; register pair as needed by brxle.
8402 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8403 [(set (pc)
8404 (if_then_else
8405 (match_operator 6 "s390_brx_operator"
8406 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8407 (match_operand:GPR 2 "general_operand" ""))
8408 (match_operand:GPR 3 "register_operand" "")])
8409 (label_ref (match_operand 0 "" ""))
8410 (pc)))
8411 (set (match_operand:GPR 4 "nonimmediate_operand" "")
8412 (plus:GPR (match_dup 1) (match_dup 2)))
8413 (clobber (match_scratch:GPR 5 ""))]
8414 "TARGET_CPU_ZARCH"
8415 "#"
8416 "!reload_completed && !reload_in_progress"
8417 [(set (match_dup 7) (match_dup 2)) ; the increment
8418 (set (match_dup 8) (match_dup 3)) ; the comparison value
8419 (parallel [(set (pc)
8420 (if_then_else
8421 (match_op_dup 6
8422 [(plus:GPR (match_dup 1) (match_dup 7))
8423 (match_dup 8)])
8424 (label_ref (match_dup 0))
8425 (pc)))
8426 (set (match_dup 4)
8427 (plus:GPR (match_dup 1) (match_dup 7)))
8428 (clobber (match_dup 5))
8429 (clobber (reg:CC CC_REGNUM))])]
8430 {
8431 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8432 operands[7] = gen_lowpart (<GPR:MODE>mode,
8433 gen_highpart (word_mode, dreg));
8434 operands[8] = gen_lowpart (<GPR:MODE>mode,
8435 gen_lowpart (word_mode, dreg));
8436 })
8438 ; brxlg, brxhg
8440 (define_insn_and_split "*brxg_64bit"
8441 [(set (pc)
8442 (if_then_else
8443 (match_operator 5 "s390_brx_operator"
8444 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8445 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8446 (subreg:DI (match_dup 2) 8)])
8447 (label_ref (match_operand 0 "" ""))
8448 (pc)))
8449 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8450 (plus:DI (match_dup 1)
8451 (subreg:DI (match_dup 2) 0)))
8452 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8453 (clobber (reg:CC CC_REGNUM))]
8454 "TARGET_ZARCH"
8455 {
8456 if (which_alternative != 0)
8457 return "#";
8458 else if (get_attr_length (insn) == 6)
8459 return "brx%E5g\t%1,%2,%l0";
8460 else
8461 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8462 }
8463 "&& reload_completed
8464 && (!REG_P (operands[3])
8465 || !rtx_equal_p (operands[1], operands[3]))"
8466 [(set (match_dup 4) (match_dup 1))
8467 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8468 (clobber (reg:CC CC_REGNUM))])
8469 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8470 (set (match_dup 3) (match_dup 4))
8471 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8472 (label_ref (match_dup 0))
8473 (pc)))]
8474 ""
8475 [(set_attr "op_type" "RIE")
8476 (set_attr "type" "branch")
8477 (set (attr "length")
8478 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8479 (const_int 6) (const_int 16)))])
8481 ; brxle, brxh
8483 (define_insn_and_split "*brx_64bit"
8484 [(set (pc)
8485 (if_then_else
8486 (match_operator 5 "s390_brx_operator"
8487 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8488 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8489 (subreg:SI (match_dup 2) 12)])
8490 (label_ref (match_operand 0 "" ""))
8491 (pc)))
8492 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8493 (plus:SI (match_dup 1)
8494 (subreg:SI (match_dup 2) 4)))
8495 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8496 (clobber (reg:CC CC_REGNUM))]
8497 "TARGET_ZARCH"
8498 {
8499 if (which_alternative != 0)
8500 return "#";
8501 else if (get_attr_length (insn) == 6)
8502 return "brx%C5\t%1,%2,%l0";
8503 else
8504 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8505 }
8506 "&& reload_completed
8507 && (!REG_P (operands[3])
8508 || !rtx_equal_p (operands[1], operands[3]))"
8509 [(set (match_dup 4) (match_dup 1))
8510 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8511 (clobber (reg:CC CC_REGNUM))])
8512 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8513 (set (match_dup 3) (match_dup 4))
8514 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8515 (label_ref (match_dup 0))
8516 (pc)))]
8517 ""
8518 [(set_attr "op_type" "RSI")
8519 (set_attr "type" "branch")
8520 (set (attr "length")
8521 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8522 (const_int 6) (const_int 14)))])
8524 ; brxle, brxh
8526 (define_insn_and_split "*brx_31bit"
8527 [(set (pc)
8528 (if_then_else
8529 (match_operator 5 "s390_brx_operator"
8530 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8531 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8532 (subreg:SI (match_dup 2) 4)])
8533 (label_ref (match_operand 0 "" ""))
8534 (pc)))
8535 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8536 (plus:SI (match_dup 1)
8537 (subreg:SI (match_dup 2) 0)))
8538 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8539 (clobber (reg:CC CC_REGNUM))]
8540 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8541 {
8542 if (which_alternative != 0)
8543 return "#";
8544 else if (get_attr_length (insn) == 6)
8545 return "brx%C5\t%1,%2,%l0";
8546 else
8547 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8548 }
8549 "&& reload_completed
8550 && (!REG_P (operands[3])
8551 || !rtx_equal_p (operands[1], operands[3]))"
8552 [(set (match_dup 4) (match_dup 1))
8553 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
8554 (clobber (reg:CC CC_REGNUM))])
8555 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
8556 (set (match_dup 3) (match_dup 4))
8557 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8558 (label_ref (match_dup 0))
8559 (pc)))]
8560 ""
8561 [(set_attr "op_type" "RSI")
8562 (set_attr "type" "branch")
8563 (set (attr "length")
8564 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8565 (const_int 6) (const_int 14)))])
8568 ;; branch on count
8570 (define_expand "doloop_end"
8571 [(use (match_operand 0 "" "")) ; loop pseudo
8572 (use (match_operand 1 "" ""))] ; label
8573 ""
8574 {
8575 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
8576 emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
8577 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
8578 emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
8579 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
8580 emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
8581 else
8582 FAIL;
8584 DONE;
8585 })
8587 (define_insn_and_split "doloop_si64"
8588 [(set (pc)
8589 (if_then_else
8590 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8591 (const_int 1))
8592 (label_ref (match_operand 0 "" ""))
8593 (pc)))
8594 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8595 (plus:SI (match_dup 1) (const_int -1)))
8596 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8597 (clobber (reg:CC CC_REGNUM))]
8598 "TARGET_CPU_ZARCH"
8599 {
8600 if (which_alternative != 0)
8601 return "#";
8602 else if (get_attr_length (insn) == 4)
8603 return "brct\t%1,%l0";
8604 else
8605 return "ahi\t%1,-1\;jgne\t%l0";
8606 }
8607 "&& reload_completed
8608 && (! REG_P (operands[2])
8609 || ! rtx_equal_p (operands[1], operands[2]))"
8610 [(set (match_dup 3) (match_dup 1))
8611 (parallel [(set (reg:CCAN CC_REGNUM)
8612 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8613 (const_int 0)))
8614 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8615 (set (match_dup 2) (match_dup 3))
8616 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8617 (label_ref (match_dup 0))
8618 (pc)))]
8619 ""
8620 [(set_attr "op_type" "RI")
8621 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8622 ; hurt us in the (rare) case of ahi.
8623 (set_attr "z10prop" "z10_super_E1")
8624 (set_attr "type" "branch")
8625 (set (attr "length")
8626 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8627 (const_int 4) (const_int 10)))])
8629 (define_insn_and_split "doloop_si31"
8630 [(set (pc)
8631 (if_then_else
8632 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8633 (const_int 1))
8634 (label_ref (match_operand 0 "" ""))
8635 (pc)))
8636 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8637 (plus:SI (match_dup 1) (const_int -1)))
8638 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8639 (clobber (reg:CC CC_REGNUM))]
8640 "!TARGET_CPU_ZARCH"
8641 {
8642 if (which_alternative != 0)
8643 return "#";
8644 else if (get_attr_length (insn) == 4)
8645 return "brct\t%1,%l0";
8646 else
8647 gcc_unreachable ();
8648 }
8649 "&& reload_completed
8650 && (! REG_P (operands[2])
8651 || ! rtx_equal_p (operands[1], operands[2]))"
8652 [(set (match_dup 3) (match_dup 1))
8653 (parallel [(set (reg:CCAN CC_REGNUM)
8654 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8655 (const_int 0)))
8656 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8657 (set (match_dup 2) (match_dup 3))
8658 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8659 (label_ref (match_dup 0))
8660 (pc)))]
8661 ""
8662 [(set_attr "op_type" "RI")
8663 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8664 ; hurt us in the (rare) case of ahi.
8665 (set_attr "z10prop" "z10_super_E1")
8666 (set_attr "type" "branch")
8667 (set (attr "length")
8668 (if_then_else (not (match_test "flag_pic"))
8669 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8670 (const_int 4) (const_int 6))
8671 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8672 (const_int 4) (const_int 8))))])
8674 (define_insn "*doloop_si_long"
8675 [(set (pc)
8676 (if_then_else
8677 (ne (match_operand:SI 1 "register_operand" "d")
8678 (const_int 1))
8679 (match_operand 0 "address_operand" "ZQZR")
8680 (pc)))
8681 (set (match_operand:SI 2 "register_operand" "=1")
8682 (plus:SI (match_dup 1) (const_int -1)))
8683 (clobber (match_scratch:SI 3 "=X"))
8684 (clobber (reg:CC CC_REGNUM))]
8685 "!TARGET_CPU_ZARCH"
8686 {
8687 if (get_attr_op_type (insn) == OP_TYPE_RR)
8688 return "bctr\t%1,%0";
8689 else
8690 return "bct\t%1,%a0";
8691 }
8692 [(set (attr "op_type")
8693 (if_then_else (match_operand 0 "register_operand" "")
8694 (const_string "RR") (const_string "RX")))
8695 (set_attr "type" "branch")
8696 (set_attr "atype" "agen")
8697 (set_attr "z10prop" "z10_c")
8698 (set_attr "z196prop" "z196_cracked")])
8700 (define_insn_and_split "doloop_di"
8701 [(set (pc)
8702 (if_then_else
8703 (ne (match_operand:DI 1 "register_operand" "d,d,d")
8704 (const_int 1))
8705 (label_ref (match_operand 0 "" ""))
8706 (pc)))
8707 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
8708 (plus:DI (match_dup 1) (const_int -1)))
8709 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
8710 (clobber (reg:CC CC_REGNUM))]
8711 "TARGET_ZARCH"
8712 {
8713 if (which_alternative != 0)
8714 return "#";
8715 else if (get_attr_length (insn) == 4)
8716 return "brctg\t%1,%l0";
8717 else
8718 return "aghi\t%1,-1\;jgne\t%l0";
8719 }
8720 "&& reload_completed
8721 && (! REG_P (operands[2])
8722 || ! rtx_equal_p (operands[1], operands[2]))"
8723 [(set (match_dup 3) (match_dup 1))
8724 (parallel [(set (reg:CCAN CC_REGNUM)
8725 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
8726 (const_int 0)))
8727 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
8728 (set (match_dup 2) (match_dup 3))
8729 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8730 (label_ref (match_dup 0))
8731 (pc)))]
8732 ""
8733 [(set_attr "op_type" "RI")
8734 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8735 ; hurt us in the (rare) case of ahi.
8736 (set_attr "z10prop" "z10_super_E1")
8737 (set_attr "type" "branch")
8738 (set (attr "length")
8739 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8740 (const_int 4) (const_int 10)))])
8742 ;;
8743 ;;- Unconditional jump instructions.
8744 ;;
8746 ;
8747 ; jump instruction pattern(s).
8748 ;
8750 (define_expand "jump"
8751 [(match_operand 0 "" "")]
8752 ""
8753 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
8755 (define_insn "*jump64"
8756 [(set (pc) (label_ref (match_operand 0 "" "")))]
8757 "TARGET_CPU_ZARCH"
8758 {
8759 if (get_attr_length (insn) == 4)
8760 return "j\t%l0";
8761 else
8762 return "jg\t%l0";
8763 }
8764 [(set_attr "op_type" "RI")
8765 (set_attr "type" "branch")
8766 (set (attr "length")
8767 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8768 (const_int 4) (const_int 6)))])
8770 (define_insn "*jump31"
8771 [(set (pc) (label_ref (match_operand 0 "" "")))]
8772 "!TARGET_CPU_ZARCH"
8773 {
8774 gcc_assert (get_attr_length (insn) == 4);
8775 return "j\t%l0";
8776 }
8777 [(set_attr "op_type" "RI")
8778 (set_attr "type" "branch")
8779 (set (attr "length")
8780 (if_then_else (not (match_test "flag_pic"))
8781 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8782 (const_int 4) (const_int 6))
8783 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8784 (const_int 4) (const_int 8))))])
8786 ;
8787 ; indirect-jump instruction pattern(s).
8788 ;
8790 (define_insn "indirect_jump"
8791 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8792 ""
8793 {
8794 if (get_attr_op_type (insn) == OP_TYPE_RR)
8795 return "br\t%0";
8796 else
8797 return "b\t%a0";
8798 }
8799 [(set (attr "op_type")
8800 (if_then_else (match_operand 0 "register_operand" "")
8801 (const_string "RR") (const_string "RX")))
8802 (set_attr "type" "branch")
8803 (set_attr "atype" "agen")])
8805 ;
8806 ; casesi instruction pattern(s).
8807 ;
8809 (define_insn "casesi_jump"
8810 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8811 (use (label_ref (match_operand 1 "" "")))]
8812 ""
8813 {
8814 if (get_attr_op_type (insn) == OP_TYPE_RR)
8815 return "br\t%0";
8816 else
8817 return "b\t%a0";
8818 }
8819 [(set (attr "op_type")
8820 (if_then_else (match_operand 0 "register_operand" "")
8821 (const_string "RR") (const_string "RX")))
8822 (set_attr "type" "branch")
8823 (set_attr "atype" "agen")])
8825 (define_expand "casesi"
8826 [(match_operand:SI 0 "general_operand" "")
8827 (match_operand:SI 1 "general_operand" "")
8828 (match_operand:SI 2 "general_operand" "")
8829 (label_ref (match_operand 3 "" ""))
8830 (label_ref (match_operand 4 "" ""))]
8831 ""
8832 {
8833 rtx index = gen_reg_rtx (SImode);
8834 rtx base = gen_reg_rtx (Pmode);
8835 rtx target = gen_reg_rtx (Pmode);
8837 emit_move_insn (index, operands[0]);
8838 emit_insn (gen_subsi3 (index, index, operands[1]));
8839 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8840 operands[4]);
8842 if (Pmode != SImode)
8843 index = convert_to_mode (Pmode, index, 1);
8844 if (GET_CODE (index) != REG)
8845 index = copy_to_mode_reg (Pmode, index);
8847 if (TARGET_64BIT)
8848 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
8849 else
8850 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
8852 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
8854 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
8855 emit_move_insn (target, index);
8857 if (flag_pic)
8858 target = gen_rtx_PLUS (Pmode, base, target);
8859 emit_jump_insn (gen_casesi_jump (target, operands[3]));
8861 DONE;
8862 })
8865 ;;
8866 ;;- Jump to subroutine.
8867 ;;
8868 ;;
8870 ;
8871 ; untyped call instruction pattern(s).
8872 ;
8874 ;; Call subroutine returning any type.
8875 (define_expand "untyped_call"
8876 [(parallel [(call (match_operand 0 "" "")
8877 (const_int 0))
8878 (match_operand 1 "" "")
8879 (match_operand 2 "" "")])]
8880 ""
8881 {
8882 int i;
8884 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8886 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8887 {
8888 rtx set = XVECEXP (operands[2], 0, i);
8889 emit_move_insn (SET_DEST (set), SET_SRC (set));
8890 }
8892 /* The optimizer does not know that the call sets the function value
8893 registers we stored in the result block. We avoid problems by
8894 claiming that all hard registers are used and clobbered at this
8895 point. */
8896 emit_insn (gen_blockage ());
8898 DONE;
8899 })
8901 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8902 ;; all of memory. This blocks insns from being moved across this point.
8904 (define_insn "blockage"
8905 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8906 ""
8907 ""
8908 [(set_attr "type" "none")
8909 (set_attr "length" "0")])
8911 ;
8912 ; sibcall patterns
8913 ;
8915 (define_expand "sibcall"
8916 [(call (match_operand 0 "" "")
8917 (match_operand 1 "" ""))]
8918 ""
8919 {
8920 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
8921 DONE;
8922 })
8924 (define_insn "*sibcall_br"
8925 [(call (mem:QI (reg SIBCALL_REGNUM))
8926 (match_operand 0 "const_int_operand" "n"))]
8927 "SIBLING_CALL_P (insn)
8928 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
8929 "br\t%%r1"
8930 [(set_attr "op_type" "RR")
8931 (set_attr "type" "branch")
8932 (set_attr "atype" "agen")])
8934 (define_insn "*sibcall_brc"
8935 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8936 (match_operand 1 "const_int_operand" "n"))]
8937 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8938 "j\t%0"
8939 [(set_attr "op_type" "RI")
8940 (set_attr "type" "branch")])
8942 (define_insn "*sibcall_brcl"
8943 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8944 (match_operand 1 "const_int_operand" "n"))]
8945 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8946 "jg\t%0"
8947 [(set_attr "op_type" "RIL")
8948 (set_attr "type" "branch")])
8950 ;
8951 ; sibcall_value patterns
8952 ;
8954 (define_expand "sibcall_value"
8955 [(set (match_operand 0 "" "")
8956 (call (match_operand 1 "" "")
8957 (match_operand 2 "" "")))]
8958 ""
8959 {
8960 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
8961 DONE;
8962 })
8964 (define_insn "*sibcall_value_br"
8965 [(set (match_operand 0 "" "")
8966 (call (mem:QI (reg SIBCALL_REGNUM))
8967 (match_operand 1 "const_int_operand" "n")))]
8968 "SIBLING_CALL_P (insn)
8969 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
8970 "br\t%%r1"
8971 [(set_attr "op_type" "RR")
8972 (set_attr "type" "branch")
8973 (set_attr "atype" "agen")])
8975 (define_insn "*sibcall_value_brc"
8976 [(set (match_operand 0 "" "")
8977 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8978 (match_operand 2 "const_int_operand" "n")))]
8979 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8980 "j\t%1"
8981 [(set_attr "op_type" "RI")
8982 (set_attr "type" "branch")])
8984 (define_insn "*sibcall_value_brcl"
8985 [(set (match_operand 0 "" "")
8986 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8987 (match_operand 2 "const_int_operand" "n")))]
8988 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8989 "jg\t%1"
8990 [(set_attr "op_type" "RIL")
8991 (set_attr "type" "branch")])
8994 ;
8995 ; call instruction pattern(s).
8996 ;
8998 (define_expand "call"
8999 [(call (match_operand 0 "" "")
9000 (match_operand 1 "" ""))
9001 (use (match_operand 2 "" ""))]
9002 ""
9003 {
9004 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
9005 gen_rtx_REG (Pmode, RETURN_REGNUM));
9006 DONE;
9007 })
9009 (define_insn "*bras"
9010 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9011 (match_operand 1 "const_int_operand" "n"))
9012 (clobber (match_operand 2 "register_operand" "=r"))]
9013 "!SIBLING_CALL_P (insn)
9014 && TARGET_SMALL_EXEC
9015 && GET_MODE (operands[2]) == Pmode"
9016 "bras\t%2,%0"
9017 [(set_attr "op_type" "RI")
9018 (set_attr "type" "jsr")
9019 (set_attr "z196prop" "z196_cracked")])
9021 (define_insn "*brasl"
9022 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9023 (match_operand 1 "const_int_operand" "n"))
9024 (clobber (match_operand 2 "register_operand" "=r"))]
9025 "!SIBLING_CALL_P (insn)
9026 && TARGET_CPU_ZARCH
9027 && GET_MODE (operands[2]) == Pmode"
9028 "brasl\t%2,%0"
9029 [(set_attr "op_type" "RIL")
9030 (set_attr "type" "jsr")
9031 (set_attr "z196prop" "z196_cracked")])
9033 (define_insn "*basr"
9034 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
9035 (match_operand 1 "const_int_operand" "n"))
9036 (clobber (match_operand 2 "register_operand" "=r"))]
9037 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
9038 {
9039 if (get_attr_op_type (insn) == OP_TYPE_RR)
9040 return "basr\t%2,%0";
9041 else
9042 return "bas\t%2,%a0";
9043 }
9044 [(set (attr "op_type")
9045 (if_then_else (match_operand 0 "register_operand" "")
9046 (const_string "RR") (const_string "RX")))
9047 (set_attr "type" "jsr")
9048 (set_attr "atype" "agen")
9049 (set_attr "z196prop" "z196_cracked")])
9051 ;
9052 ; call_value instruction pattern(s).
9053 ;
9055 (define_expand "call_value"
9056 [(set (match_operand 0 "" "")
9057 (call (match_operand 1 "" "")
9058 (match_operand 2 "" "")))
9059 (use (match_operand 3 "" ""))]
9060 ""
9061 {
9062 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
9063 gen_rtx_REG (Pmode, RETURN_REGNUM));
9064 DONE;
9065 })
9067 (define_insn "*bras_r"
9068 [(set (match_operand 0 "" "")
9069 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9070 (match_operand:SI 2 "const_int_operand" "n")))
9071 (clobber (match_operand 3 "register_operand" "=r"))]
9072 "!SIBLING_CALL_P (insn)
9073 && TARGET_SMALL_EXEC
9074 && GET_MODE (operands[3]) == Pmode"
9075 "bras\t%3,%1"
9076 [(set_attr "op_type" "RI")
9077 (set_attr "type" "jsr")
9078 (set_attr "z196prop" "z196_cracked")])
9080 (define_insn "*brasl_r"
9081 [(set (match_operand 0 "" "")
9082 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9083 (match_operand 2 "const_int_operand" "n")))
9084 (clobber (match_operand 3 "register_operand" "=r"))]
9085 "!SIBLING_CALL_P (insn)
9086 && TARGET_CPU_ZARCH
9087 && GET_MODE (operands[3]) == Pmode"
9088 "brasl\t%3,%1"
9089 [(set_attr "op_type" "RIL")
9090 (set_attr "type" "jsr")
9091 (set_attr "z196prop" "z196_cracked")])
9093 (define_insn "*basr_r"
9094 [(set (match_operand 0 "" "")
9095 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9096 (match_operand 2 "const_int_operand" "n")))
9097 (clobber (match_operand 3 "register_operand" "=r"))]
9098 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9099 {
9100 if (get_attr_op_type (insn) == OP_TYPE_RR)
9101 return "basr\t%3,%1";
9102 else
9103 return "bas\t%3,%a1";
9104 }
9105 [(set (attr "op_type")
9106 (if_then_else (match_operand 1 "register_operand" "")
9107 (const_string "RR") (const_string "RX")))
9108 (set_attr "type" "jsr")
9109 (set_attr "atype" "agen")
9110 (set_attr "z196prop" "z196_cracked")])
9112 ;;
9113 ;;- Thread-local storage support.
9114 ;;
9116 (define_expand "get_thread_pointer<mode>"
9117 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
9118 ""
9119 "")
9121 (define_expand "set_thread_pointer<mode>"
9122 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
9123 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
9124 ""
9125 "")
9127 (define_insn "*set_tp"
9128 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
9129 ""
9130 ""
9131 [(set_attr "type" "none")
9132 (set_attr "length" "0")])
9134 (define_insn "*tls_load_64"
9135 [(set (match_operand:DI 0 "register_operand" "=d")
9136 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
9137 (match_operand:DI 2 "" "")]
9138 UNSPEC_TLS_LOAD))]
9139 "TARGET_64BIT"
9140 "lg\t%0,%1%J2"
9141 [(set_attr "op_type" "RXE")
9142 (set_attr "z10prop" "z10_fwd_A3")])
9144 (define_insn "*tls_load_31"
9145 [(set (match_operand:SI 0 "register_operand" "=d,d")
9146 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
9147 (match_operand:SI 2 "" "")]
9148 UNSPEC_TLS_LOAD))]
9149 "!TARGET_64BIT"
9150 "@
9151 l\t%0,%1%J2
9152 ly\t%0,%1%J2"
9153 [(set_attr "op_type" "RX,RXY")
9154 (set_attr "type" "load")
9155 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
9157 (define_insn "*bras_tls"
9158 [(set (match_operand 0 "" "")
9159 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9160 (match_operand 2 "const_int_operand" "n")))
9161 (clobber (match_operand 3 "register_operand" "=r"))
9162 (use (match_operand 4 "" ""))]
9163 "!SIBLING_CALL_P (insn)
9164 && TARGET_SMALL_EXEC
9165 && GET_MODE (operands[3]) == Pmode"
9166 "bras\t%3,%1%J4"
9167 [(set_attr "op_type" "RI")
9168 (set_attr "type" "jsr")
9169 (set_attr "z196prop" "z196_cracked")])
9171 (define_insn "*brasl_tls"
9172 [(set (match_operand 0 "" "")
9173 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9174 (match_operand 2 "const_int_operand" "n")))
9175 (clobber (match_operand 3 "register_operand" "=r"))
9176 (use (match_operand 4 "" ""))]
9177 "!SIBLING_CALL_P (insn)
9178 && TARGET_CPU_ZARCH
9179 && GET_MODE (operands[3]) == Pmode"
9180 "brasl\t%3,%1%J4"
9181 [(set_attr "op_type" "RIL")
9182 (set_attr "type" "jsr")
9183 (set_attr "z196prop" "z196_cracked")])
9185 (define_insn "*basr_tls"
9186 [(set (match_operand 0 "" "")
9187 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9188 (match_operand 2 "const_int_operand" "n")))
9189 (clobber (match_operand 3 "register_operand" "=r"))
9190 (use (match_operand 4 "" ""))]
9191 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9192 {
9193 if (get_attr_op_type (insn) == OP_TYPE_RR)
9194 return "basr\t%3,%1%J4";
9195 else
9196 return "bas\t%3,%a1%J4";
9197 }
9198 [(set (attr "op_type")
9199 (if_then_else (match_operand 1 "register_operand" "")
9200 (const_string "RR") (const_string "RX")))
9201 (set_attr "type" "jsr")
9202 (set_attr "atype" "agen")
9203 (set_attr "z196prop" "z196_cracked")])
9205 ;;
9206 ;;- Atomic operations
9207 ;;
9209 ;
9210 ; memory barrier patterns.
9211 ;
9213 (define_expand "mem_signal_fence"
9214 [(match_operand:SI 0 "const_int_operand")] ;; model
9215 ""
9216 {
9217 /* The s390 memory model is strong enough not to require any
9218 barrier in order to synchronize a thread with itself. */
9219 DONE;
9220 })
9222 (define_expand "mem_thread_fence"
9223 [(match_operand:SI 0 "const_int_operand")] ;; model
9224 ""
9225 {
9226 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
9227 enough not to require barriers of any kind. */
9228 if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST)
9229 {
9230 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
9231 MEM_VOLATILE_P (mem) = 1;
9232 emit_insn (gen_mem_thread_fence_1 (mem));
9233 }
9234 DONE;
9235 })
9237 ; Although bcr is superscalar on Z10, this variant will never
9238 ; become part of an execution group.
9239 ; With z196 we can make use of the fast-BCR-serialization facility.
9240 ; This allows for a slightly faster sync which is sufficient for our
9241 ; purposes.
9242 (define_insn "mem_thread_fence_1"
9243 [(set (match_operand:BLK 0 "" "")
9244 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
9245 ""
9246 {
9247 if (TARGET_Z196)
9248 return "bcr\t14,0";
9249 else
9250 return "bcr\t15,0";
9251 }
9252 [(set_attr "op_type" "RR")
9253 (set_attr "mnemonic" "bcr_flush")
9254 (set_attr "z196prop" "z196_alone")])
9256 ;
9257 ; atomic load/store operations
9258 ;
9260 ; Atomic loads need not examine the memory model at all.
9261 (define_expand "atomic_load<mode>"
9262 [(match_operand:DINT 0 "register_operand") ;; output
9263 (match_operand:DINT 1 "memory_operand") ;; memory
9264 (match_operand:SI 2 "const_int_operand")] ;; model
9265 ""
9266 {
9267 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9268 FAIL;
9270 if (<MODE>mode == TImode)
9271 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
9272 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9273 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
9274 else
9275 emit_move_insn (operands[0], operands[1]);
9276 DONE;
9277 })
9279 ; Different from movdi_31 in that we want no splitters.
9280 (define_insn "atomic_loaddi_1"
9281 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9282 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9283 UNSPEC_MOVA))]
9284 "!TARGET_ZARCH"
9285 "@
9286 lm\t%0,%M0,%S1
9287 lmy\t%0,%M0,%S1
9288 ld\t%0,%1
9289 ldy\t%0,%1"
9290 [(set_attr "op_type" "RS,RSY,RS,RSY")
9291 (set_attr "type" "lm,lm,floaddf,floaddf")])
9293 (define_insn "atomic_loadti_1"
9294 [(set (match_operand:TI 0 "register_operand" "=r")
9295 (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
9296 UNSPEC_MOVA))]
9297 "TARGET_ZARCH"
9298 "lpq\t%0,%1"
9299 [(set_attr "op_type" "RXY")
9300 (set_attr "type" "other")])
9302 ; Atomic stores must(?) enforce sequential consistency.
9303 (define_expand "atomic_store<mode>"
9304 [(match_operand:DINT 0 "memory_operand") ;; memory
9305 (match_operand:DINT 1 "register_operand") ;; input
9306 (match_operand:SI 2 "const_int_operand")] ;; model
9307 ""
9308 {
9309 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
9311 if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0])))
9312 FAIL;
9314 if (<MODE>mode == TImode)
9315 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9316 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9317 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9318 else
9319 emit_move_insn (operands[0], operands[1]);
9320 if (model == MEMMODEL_SEQ_CST)
9321 emit_insn (gen_mem_thread_fence (operands[2]));
9322 DONE;
9323 })
9325 ; Different from movdi_31 in that we want no splitters.
9326 (define_insn "atomic_storedi_1"
9327 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9328 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9329 UNSPEC_MOVA))]
9330 "!TARGET_ZARCH"
9331 "@
9332 stm\t%1,%N1,%S0
9333 stmy\t%1,%N1,%S0
9334 std %1,%0
9335 stdy %1,%0"
9336 [(set_attr "op_type" "RS,RSY,RS,RSY")
9337 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9339 (define_insn "atomic_storeti_1"
9340 [(set (match_operand:TI 0 "memory_operand" "=RT")
9341 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9342 UNSPEC_MOVA))]
9343 "TARGET_ZARCH"
9344 "stpq\t%1,%0"
9345 [(set_attr "op_type" "RXY")
9346 (set_attr "type" "other")])
9348 ;
9349 ; compare and swap patterns.
9350 ;
9352 (define_expand "atomic_compare_and_swap<mode>"
9353 [(match_operand:SI 0 "register_operand") ;; bool success output
9354 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9355 (match_operand:DGPR 2 "memory_operand") ;; memory
9356 (match_operand:DGPR 3 "register_operand") ;; expected intput
9357 (match_operand:DGPR 4 "register_operand") ;; newval intput
9358 (match_operand:SI 5 "const_int_operand") ;; is_weak
9359 (match_operand:SI 6 "const_int_operand") ;; success model
9360 (match_operand:SI 7 "const_int_operand")] ;; failure model
9361 ""
9362 {
9363 rtx cc, cmp, output = operands[1];
9365 if (!register_operand (output, <MODE>mode))
9366 output = gen_reg_rtx (<MODE>mode);
9368 if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2])))
9369 FAIL;
9371 emit_insn (gen_atomic_compare_and_swap<mode>_internal
9372 (output, operands[2], operands[3], operands[4]));
9374 /* We deliberately accept non-register operands in the predicate
9375 to ensure the write back to the output operand happens *before*
9376 the store-flags code below. This makes it easier for combine
9377 to merge the store-flags code with a potential test-and-branch
9378 pattern following (immediately!) afterwards. */
9379 if (output != operands[1])
9380 emit_move_insn (operands[1], output);
9382 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9383 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9384 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9385 DONE;
9386 })
9388 (define_expand "atomic_compare_and_swap<mode>"
9389 [(match_operand:SI 0 "register_operand") ;; bool success output
9390 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9391 (match_operand:HQI 2 "memory_operand") ;; memory
9392 (match_operand:HQI 3 "general_operand") ;; expected intput
9393 (match_operand:HQI 4 "general_operand") ;; newval intput
9394 (match_operand:SI 5 "const_int_operand") ;; is_weak
9395 (match_operand:SI 6 "const_int_operand") ;; success model
9396 (match_operand:SI 7 "const_int_operand")] ;; failure model
9397 ""
9398 {
9399 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9400 operands[3], operands[4], INTVAL (operands[5]));
9401 DONE;
9402 })
9404 (define_expand "atomic_compare_and_swap<mode>_internal"
9405 [(parallel
9406 [(set (match_operand:DGPR 0 "register_operand")
9407 (match_operand:DGPR 1 "memory_operand"))
9408 (set (match_dup 1)
9409 (unspec_volatile:DGPR
9410 [(match_dup 1)
9411 (match_operand:DGPR 2 "register_operand")
9412 (match_operand:DGPR 3 "register_operand")]
9413 UNSPECV_CAS))
9414 (set (reg:CCZ1 CC_REGNUM)
9415 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9416 "")
9418 ; cdsg, csg
9419 (define_insn "*atomic_compare_and_swap<mode>_1"
9420 [(set (match_operand:TDI 0 "register_operand" "=r")
9421 (match_operand:TDI 1 "memory_operand" "+QS"))
9422 (set (match_dup 1)
9423 (unspec_volatile:TDI
9424 [(match_dup 1)
9425 (match_operand:TDI 2 "register_operand" "0")
9426 (match_operand:TDI 3 "register_operand" "r")]
9427 UNSPECV_CAS))
9428 (set (reg:CCZ1 CC_REGNUM)
9429 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9430 "TARGET_ZARCH"
9431 "c<td>sg\t%0,%3,%S1"
9432 [(set_attr "op_type" "RSY")
9433 (set_attr "type" "sem")])
9435 ; cds, cdsy
9436 (define_insn "*atomic_compare_and_swapdi_2"
9437 [(set (match_operand:DI 0 "register_operand" "=r,r")
9438 (match_operand:DI 1 "memory_operand" "+Q,S"))
9439 (set (match_dup 1)
9440 (unspec_volatile:DI
9441 [(match_dup 1)
9442 (match_operand:DI 2 "register_operand" "0,0")
9443 (match_operand:DI 3 "register_operand" "r,r")]
9444 UNSPECV_CAS))
9445 (set (reg:CCZ1 CC_REGNUM)
9446 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9447 "!TARGET_ZARCH"
9448 "@
9449 cds\t%0,%3,%S1
9450 cdsy\t%0,%3,%S1"
9451 [(set_attr "op_type" "RS,RSY")
9452 (set_attr "type" "sem")])
9454 ; cs, csy
9455 (define_insn "*atomic_compare_and_swapsi_3"
9456 [(set (match_operand:SI 0 "register_operand" "=r,r")
9457 (match_operand:SI 1 "memory_operand" "+Q,S"))
9458 (set (match_dup 1)
9459 (unspec_volatile:SI
9460 [(match_dup 1)
9461 (match_operand:SI 2 "register_operand" "0,0")
9462 (match_operand:SI 3 "register_operand" "r,r")]
9463 UNSPECV_CAS))
9464 (set (reg:CCZ1 CC_REGNUM)
9465 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9466 ""
9467 "@
9468 cs\t%0,%3,%S1
9469 csy\t%0,%3,%S1"
9470 [(set_attr "op_type" "RS,RSY")
9471 (set_attr "type" "sem")])
9473 ;
9474 ; Other atomic instruction patterns.
9475 ;
9477 ; z196 load and add, xor, or and and instructions
9479 (define_expand "atomic_fetch_<atomic><mode>"
9480 [(match_operand:GPR 0 "register_operand") ;; val out
9481 (ATOMIC_Z196:GPR
9482 (match_operand:GPR 1 "memory_operand") ;; memory
9483 (match_operand:GPR 2 "register_operand")) ;; val in
9484 (match_operand:SI 3 "const_int_operand")] ;; model
9485 "TARGET_Z196"
9486 {
9487 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9488 FAIL;
9490 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9491 (operands[0], operands[1], operands[2]));
9492 DONE;
9493 })
9495 ; lan, lang, lao, laog, lax, laxg, laa, laag
9496 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9497 [(set (match_operand:GPR 0 "register_operand" "=d")
9498 (match_operand:GPR 1 "memory_operand" "+QS"))
9499 (set (match_dup 1)
9500 (unspec_volatile:GPR
9501 [(ATOMIC_Z196:GPR (match_dup 1)
9502 (match_operand:GPR 2 "general_operand" "d"))]
9503 UNSPECV_ATOMIC_OP))
9504 (clobber (reg:CC CC_REGNUM))]
9505 "TARGET_Z196"
9506 "la<noxa><g>\t%0,%2,%1"
9507 [(set_attr "op_type" "RSY")
9508 (set_attr "type" "sem")])
9510 ;; For SImode and larger, the optabs.c code will do just fine in
9511 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
9512 ;; better by expanding our own loop.
9514 (define_expand "atomic_<atomic><mode>"
9515 [(ATOMIC:HQI
9516 (match_operand:HQI 0 "memory_operand") ;; memory
9517 (match_operand:HQI 1 "general_operand")) ;; val in
9518 (match_operand:SI 2 "const_int_operand")] ;; model
9519 ""
9520 {
9521 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9522 operands[1], false);
9523 DONE;
9524 })
9526 (define_expand "atomic_fetch_<atomic><mode>"
9527 [(match_operand:HQI 0 "register_operand") ;; val out
9528 (ATOMIC:HQI
9529 (match_operand:HQI 1 "memory_operand") ;; memory
9530 (match_operand:HQI 2 "general_operand")) ;; val in
9531 (match_operand:SI 3 "const_int_operand")] ;; model
9532 ""
9533 {
9534 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9535 operands[2], false);
9536 DONE;
9537 })
9539 (define_expand "atomic_<atomic>_fetch<mode>"
9540 [(match_operand:HQI 0 "register_operand") ;; val out
9541 (ATOMIC:HQI
9542 (match_operand:HQI 1 "memory_operand") ;; memory
9543 (match_operand:HQI 2 "general_operand")) ;; val in
9544 (match_operand:SI 3 "const_int_operand")] ;; model
9545 ""
9546 {
9547 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9548 operands[2], true);
9549 DONE;
9550 })
9552 (define_expand "atomic_exchange<mode>"
9553 [(match_operand:HQI 0 "register_operand") ;; val out
9554 (match_operand:HQI 1 "memory_operand") ;; memory
9555 (match_operand:HQI 2 "general_operand") ;; val in
9556 (match_operand:SI 3 "const_int_operand")] ;; model
9557 ""
9558 {
9559 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
9560 operands[2], false);
9561 DONE;
9562 })
9564 ;;
9565 ;;- Miscellaneous instructions.
9566 ;;
9568 ;
9569 ; allocate stack instruction pattern(s).
9570 ;
9572 (define_expand "allocate_stack"
9573 [(match_operand 0 "general_operand" "")
9574 (match_operand 1 "general_operand" "")]
9575 "TARGET_BACKCHAIN"
9576 {
9577 rtx temp = gen_reg_rtx (Pmode);
9579 emit_move_insn (temp, s390_back_chain_rtx ());
9580 anti_adjust_stack (operands[1]);
9581 emit_move_insn (s390_back_chain_rtx (), temp);
9583 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9584 DONE;
9585 })
9588 ;
9589 ; setjmp instruction pattern.
9590 ;
9592 (define_expand "builtin_setjmp_receiver"
9593 [(match_operand 0 "" "")]
9594 "flag_pic"
9595 {
9596 emit_insn (s390_load_got ());
9597 emit_use (pic_offset_table_rtx);
9598 DONE;
9599 })
9601 ;; These patterns say how to save and restore the stack pointer. We need not
9602 ;; save the stack pointer at function level since we are careful to
9603 ;; preserve the backchain. At block level, we have to restore the backchain
9604 ;; when we restore the stack pointer.
9605 ;;
9606 ;; For nonlocal gotos, we must save both the stack pointer and its
9607 ;; backchain and restore both. Note that in the nonlocal case, the
9608 ;; save area is a memory location.
9610 (define_expand "save_stack_function"
9611 [(match_operand 0 "general_operand" "")
9612 (match_operand 1 "general_operand" "")]
9613 ""
9614 "DONE;")
9616 (define_expand "restore_stack_function"
9617 [(match_operand 0 "general_operand" "")
9618 (match_operand 1 "general_operand" "")]
9619 ""
9620 "DONE;")
9622 (define_expand "restore_stack_block"
9623 [(match_operand 0 "register_operand" "")
9624 (match_operand 1 "register_operand" "")]
9625 "TARGET_BACKCHAIN"
9626 {
9627 rtx temp = gen_reg_rtx (Pmode);
9629 emit_move_insn (temp, s390_back_chain_rtx ());
9630 emit_move_insn (operands[0], operands[1]);
9631 emit_move_insn (s390_back_chain_rtx (), temp);
9633 DONE;
9634 })
9636 (define_expand "save_stack_nonlocal"
9637 [(match_operand 0 "memory_operand" "")
9638 (match_operand 1 "register_operand" "")]
9639 ""
9640 {
9641 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9643 /* Copy the backchain to the first word, sp to the second and the
9644 literal pool base to the third. */
9646 rtx save_bc = adjust_address (operands[0], Pmode, 0);
9647 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
9648 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
9650 if (TARGET_BACKCHAIN)
9651 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
9653 emit_move_insn (save_sp, operands[1]);
9654 emit_move_insn (save_bp, base);
9656 DONE;
9657 })
9659 (define_expand "restore_stack_nonlocal"
9660 [(match_operand 0 "register_operand" "")
9661 (match_operand 1 "memory_operand" "")]
9662 ""
9663 {
9664 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9665 rtx temp = NULL_RTX;
9667 /* Restore the backchain from the first word, sp from the second and the
9668 literal pool base from the third. */
9670 rtx save_bc = adjust_address (operands[1], Pmode, 0);
9671 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
9672 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
9674 if (TARGET_BACKCHAIN)
9675 temp = force_reg (Pmode, save_bc);
9677 emit_move_insn (base, save_bp);
9678 emit_move_insn (operands[0], save_sp);
9680 if (temp)
9681 emit_move_insn (s390_back_chain_rtx (), temp);
9683 emit_use (base);
9684 DONE;
9685 })
9687 (define_expand "exception_receiver"
9688 [(const_int 0)]
9689 ""
9690 {
9691 s390_set_has_landing_pad_p (true);
9692 DONE;
9693 })
9695 ;
9696 ; nop instruction pattern(s).
9697 ;
9699 (define_insn "nop"
9700 [(const_int 0)]
9701 ""
9702 "lr\t0,0"
9703 [(set_attr "op_type" "RR")
9704 (set_attr "z10prop" "z10_fr_E1")])
9706 (define_insn "nop1"
9707 [(const_int 1)]
9708 ""
9709 "lr\t1,1"
9710 [(set_attr "op_type" "RR")])
9712 ;;- Undeletable nops (used for hotpatching)
9714 (define_insn "nop_2_byte"
9715 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)]
9716 ""
9717 "nopr\t%%r7"
9718 [(set_attr "op_type" "RR")])
9720 (define_insn "nop_4_byte"
9721 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)]
9722 ""
9723 "nop\t0"
9724 [(set_attr "op_type" "RX")])
9726 (define_insn "nop_6_byte"
9727 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
9728 "TARGET_CPU_ZARCH"
9729 "brcl\t0, 0"
9730 [(set_attr "op_type" "RIL")])
9733 ;
9734 ; Special literal pool access instruction pattern(s).
9735 ;
9737 (define_insn "*pool_entry"
9738 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
9739 UNSPECV_POOL_ENTRY)]
9740 ""
9741 {
9742 machine_mode mode = GET_MODE (PATTERN (insn));
9743 unsigned int align = GET_MODE_BITSIZE (mode);
9744 s390_output_pool_entry (operands[0], mode, align);
9745 return "";
9746 }
9747 [(set (attr "length")
9748 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
9750 (define_insn "pool_align"
9751 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
9752 UNSPECV_POOL_ALIGN)]
9753 ""
9754 ".align\t%0"
9755 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9757 (define_insn "pool_section_start"
9758 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
9759 ""
9760 ".section\t.rodata"
9761 [(set_attr "length" "0")])
9763 (define_insn "pool_section_end"
9764 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
9765 ""
9766 ".previous"
9767 [(set_attr "length" "0")])
9769 (define_insn "main_base_31_small"
9770 [(set (match_operand 0 "register_operand" "=a")
9771 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9772 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9773 "basr\t%0,0"
9774 [(set_attr "op_type" "RR")
9775 (set_attr "type" "la")
9776 (set_attr "z196prop" "z196_cracked")])
9778 (define_insn "main_base_31_large"
9779 [(set (match_operand 0 "register_operand" "=a")
9780 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
9781 (set (pc) (label_ref (match_operand 2 "" "")))]
9782 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9783 "bras\t%0,%2"
9784 [(set_attr "op_type" "RI")
9785 (set_attr "z196prop" "z196_cracked")])
9787 (define_insn "main_base_64"
9788 [(set (match_operand 0 "register_operand" "=a")
9789 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9790 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9791 "larl\t%0,%1"
9792 [(set_attr "op_type" "RIL")
9793 (set_attr "type" "larl")
9794 (set_attr "z10prop" "z10_fwd_A1")])
9796 (define_insn "main_pool"
9797 [(set (match_operand 0 "register_operand" "=a")
9798 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
9799 "GET_MODE (operands[0]) == Pmode"
9800 {
9801 gcc_unreachable ();
9802 }
9803 [(set (attr "type")
9804 (if_then_else (match_test "TARGET_CPU_ZARCH")
9805 (const_string "larl") (const_string "la")))])
9807 (define_insn "reload_base_31"
9808 [(set (match_operand 0 "register_operand" "=a")
9809 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9810 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9811 "basr\t%0,0\;la\t%0,%1-.(%0)"
9812 [(set_attr "length" "6")
9813 (set_attr "type" "la")
9814 (set_attr "z196prop" "z196_cracked")])
9816 (define_insn "reload_base_64"
9817 [(set (match_operand 0 "register_operand" "=a")
9818 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9819 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9820 "larl\t%0,%1"
9821 [(set_attr "op_type" "RIL")
9822 (set_attr "type" "larl")
9823 (set_attr "z10prop" "z10_fwd_A1")])
9825 (define_insn "pool"
9826 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
9827 ""
9828 {
9829 gcc_unreachable ();
9830 }
9831 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9833 ;;
9834 ;; Insns related to generating the function prologue and epilogue.
9835 ;;
9838 (define_expand "prologue"
9839 [(use (const_int 0))]
9840 ""
9841 "s390_emit_prologue (); DONE;")
9843 (define_expand "epilogue"
9844 [(use (const_int 1))]
9845 ""
9846 "s390_emit_epilogue (false); DONE;")
9848 (define_expand "sibcall_epilogue"
9849 [(use (const_int 0))]
9850 ""
9851 "s390_emit_epilogue (true); DONE;")
9853 ;; A direct return instruction, without using an epilogue.
9854 (define_insn "<code>"
9855 [(ANY_RETURN)]
9856 "s390_can_use_<code>_insn ()"
9857 "br\t%%r14"
9858 [(set_attr "op_type" "RR")
9859 (set_attr "type" "jsr")
9860 (set_attr "atype" "agen")])
9862 (define_insn "*return"
9863 [(return)
9864 (use (match_operand 0 "register_operand" "a"))]
9865 "GET_MODE (operands[0]) == Pmode"
9866 "br\t%0"
9867 [(set_attr "op_type" "RR")
9868 (set_attr "type" "jsr")
9869 (set_attr "atype" "agen")])
9872 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
9873 ;; pointer. This is used for compatibility.
9875 (define_expand "ptr_extend"
9876 [(set (match_operand:DI 0 "register_operand" "=r")
9877 (match_operand:SI 1 "register_operand" "r"))]
9878 "TARGET_64BIT"
9879 {
9880 emit_insn (gen_anddi3 (operands[0],
9881 gen_lowpart (DImode, operands[1]),
9882 GEN_INT (0x7fffffff)));
9883 DONE;
9884 })
9886 ;; Instruction definition to expand eh_return macro to support
9887 ;; swapping in special linkage return addresses.
9889 (define_expand "eh_return"
9890 [(use (match_operand 0 "register_operand" ""))]
9891 "TARGET_TPF"
9892 {
9893 s390_emit_tpf_eh_return (operands[0]);
9894 DONE;
9895 })
9897 ;
9898 ; Stack Protector Patterns
9899 ;
9901 (define_expand "stack_protect_set"
9902 [(set (match_operand 0 "memory_operand" "")
9903 (match_operand 1 "memory_operand" ""))]
9904 ""
9905 {
9906 #ifdef TARGET_THREAD_SSP_OFFSET
9907 operands[1]
9908 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9909 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9910 #endif
9911 if (TARGET_64BIT)
9912 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
9913 else
9914 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
9916 DONE;
9917 })
9919 (define_insn "stack_protect_set<mode>"
9920 [(set (match_operand:DSI 0 "memory_operand" "=Q")
9921 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
9922 ""
9923 "mvc\t%O0(%G0,%R0),%S1"
9924 [(set_attr "op_type" "SS")])
9926 (define_expand "stack_protect_test"
9927 [(set (reg:CC CC_REGNUM)
9928 (compare (match_operand 0 "memory_operand" "")
9929 (match_operand 1 "memory_operand" "")))
9930 (match_operand 2 "" "")]
9931 ""
9932 {
9933 rtx cc_reg, test;
9934 #ifdef TARGET_THREAD_SSP_OFFSET
9935 operands[1]
9936 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9937 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9938 #endif
9939 if (TARGET_64BIT)
9940 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
9941 else
9942 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
9944 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
9945 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
9946 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
9947 DONE;
9948 })
9950 (define_insn "stack_protect_test<mode>"
9951 [(set (reg:CCZ CC_REGNUM)
9952 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
9953 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
9954 ""
9955 "clc\t%O0(%G0,%R0),%S1"
9956 [(set_attr "op_type" "SS")])
9958 ; This is used in s390_emit_prologue in order to prevent insns
9959 ; adjusting the stack pointer to be moved over insns writing stack
9960 ; slots using a copy of the stack pointer in a different register.
9961 (define_insn "stack_tie"
9962 [(set (match_operand:BLK 0 "memory_operand" "+m")
9963 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9964 ""
9965 ""
9966 [(set_attr "length" "0")])
9969 ;
9970 ; Data prefetch patterns
9971 ;
9973 (define_insn "prefetch"
9974 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
9975 (match_operand:SI 1 "const_int_operand" " n,n")
9976 (match_operand:SI 2 "const_int_operand" " n,n"))]
9977 "TARGET_Z10"
9978 {
9979 switch (which_alternative)
9980 {
9981 case 0:
9982 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
9983 case 1:
9984 if (larl_operand (operands[0], Pmode))
9985 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
9986 default:
9988 /* This might be reached for symbolic operands with an odd
9989 addend. We simply omit the prefetch for such rare cases. */
9991 return "";
9992 }
9993 }
9994 [(set_attr "type" "load,larl")
9995 (set_attr "op_type" "RXY,RIL")
9996 (set_attr "z10prop" "z10_super")
9997 (set_attr "z196prop" "z196_alone")])
10000 ;
10001 ; Byte swap instructions
10002 ;
10004 (define_insn "bswap<mode>2"
10005 [(set (match_operand:GPR 0 "register_operand" "=d, d")
10006 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
10007 "TARGET_CPU_ZARCH"
10008 "@
10009 lrv<g>r\t%0,%1
10010 lrv<g>\t%0,%1"
10011 [(set_attr "type" "*,load")
10012 (set_attr "op_type" "RRE,RXY")
10013 (set_attr "z10prop" "z10_super")])
10016 ;
10017 ; Population count instruction
10018 ;
10020 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
10021 ; portions and stores the result in the corresponding bytes in op0.
10022 (define_insn "*popcount<mode>"
10023 [(set (match_operand:INT 0 "register_operand" "=d")
10024 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
10025 (clobber (reg:CC CC_REGNUM))]
10026 "TARGET_Z196"
10027 "popcnt\t%0,%1"
10028 [(set_attr "op_type" "RRE")])
10030 (define_expand "popcountdi2"
10031 [; popcnt op0, op1
10032 (parallel [(set (match_operand:DI 0 "register_operand" "")
10033 (unspec:DI [(match_operand:DI 1 "register_operand")]
10034 UNSPEC_POPCNT))
10035 (clobber (reg:CC CC_REGNUM))])
10036 ; sllg op2, op0, 32
10037 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
10038 ; agr op0, op2
10039 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10040 (clobber (reg:CC CC_REGNUM))])
10041 ; sllg op2, op0, 16
10042 (set (match_dup 2)
10043 (ashift:DI (match_dup 0) (const_int 16)))
10044 ; agr op0, op2
10045 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10046 (clobber (reg:CC CC_REGNUM))])
10047 ; sllg op2, op0, 8
10048 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
10049 ; agr op0, op2
10050 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10051 (clobber (reg:CC CC_REGNUM))])
10052 ; srlg op0, op0, 56
10053 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
10054 "TARGET_Z196 && TARGET_64BIT"
10055 "operands[2] = gen_reg_rtx (DImode);")
10057 (define_expand "popcountsi2"
10058 [; popcnt op0, op1
10059 (parallel [(set (match_operand:SI 0 "register_operand" "")
10060 (unspec:SI [(match_operand:SI 1 "register_operand")]
10061 UNSPEC_POPCNT))
10062 (clobber (reg:CC CC_REGNUM))])
10063 ; sllk op2, op0, 16
10064 (set (match_dup 2)
10065 (ashift:SI (match_dup 0) (const_int 16)))
10066 ; ar op0, op2
10067 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10068 (clobber (reg:CC CC_REGNUM))])
10069 ; sllk op2, op0, 8
10070 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
10071 ; ar op0, op2
10072 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10073 (clobber (reg:CC CC_REGNUM))])
10074 ; srl op0, op0, 24
10075 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
10076 "TARGET_Z196"
10077 "operands[2] = gen_reg_rtx (SImode);")
10079 (define_expand "popcounthi2"
10080 [; popcnt op0, op1
10081 (parallel [(set (match_operand:HI 0 "register_operand" "")
10082 (unspec:HI [(match_operand:HI 1 "register_operand")]
10083 UNSPEC_POPCNT))
10084 (clobber (reg:CC CC_REGNUM))])
10085 ; sllk op2, op0, 8
10086 (set (match_dup 2)
10087 (ashift:SI (match_dup 0) (const_int 8)))
10088 ; ar op0, op2
10089 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10090 (clobber (reg:CC CC_REGNUM))])
10091 ; srl op0, op0, 8
10092 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
10093 "TARGET_Z196"
10094 "operands[2] = gen_reg_rtx (SImode);")
10096 (define_expand "popcountqi2"
10097 [; popcnt op0, op1
10098 (parallel [(set (match_operand:QI 0 "register_operand" "")
10099 (unspec:QI [(match_operand:QI 1 "register_operand")]
10100 UNSPEC_POPCNT))
10101 (clobber (reg:CC CC_REGNUM))])]
10102 "TARGET_Z196"
10103 "")
10105 ;;
10106 ;;- Copy sign instructions
10107 ;;
10109 (define_insn "copysign<mode>3"
10110 [(set (match_operand:FP 0 "register_operand" "=f")
10111 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
10112 (match_operand:FP 2 "register_operand" "f")]
10113 UNSPEC_COPYSIGN))]
10114 "TARGET_Z196"
10115 "cpsdr\t%0,%2,%1"
10116 [(set_attr "op_type" "RRF")
10117 (set_attr "type" "fsimp<mode>")])
10120 ;;
10121 ;;- Transactional execution instructions
10122 ;;
10124 ; This splitter helps combine to make use of CC directly when
10125 ; comparing the integer result of a tbegin builtin with a constant.
10126 ; The unspec is already removed by canonicalize_comparison. So this
10127 ; splitters only job is to turn the PARALLEL into separate insns
10128 ; again. Unfortunately this only works with the very first cc/int
10129 ; compare since combine is not able to deal with data flow across
10130 ; basic block boundaries.
10132 ; It needs to be an insn pattern as well since combine does not apply
10133 ; the splitter directly. Combine would only use it if it actually
10134 ; would reduce the number of instructions.
10135 (define_insn_and_split "*ccraw_to_int"
10136 [(set (pc)
10137 (if_then_else
10138 (match_operator 0 "s390_eqne_operator"
10139 [(reg:CCRAW CC_REGNUM)
10140 (match_operand 1 "const_int_operand" "")])
10141 (label_ref (match_operand 2 "" ""))
10142 (pc)))
10143 (set (match_operand:SI 3 "register_operand" "=d")
10144 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10145 ""
10146 "#"
10147 ""
10148 [(set (match_dup 3)
10149 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
10150 (set (pc)
10151 (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
10152 (label_ref (match_dup 2))
10153 (pc)))]
10154 "")
10156 ; Non-constrained transaction begin
10158 (define_expand "tbegin"
10159 [(match_operand:SI 0 "register_operand" "")
10160 (match_operand:BLK 1 "memory_operand" "")]
10161 "TARGET_HTM"
10162 {
10163 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
10164 DONE;
10165 })
10167 (define_expand "tbegin_nofloat"
10168 [(match_operand:SI 0 "register_operand" "")
10169 (match_operand:BLK 1 "memory_operand" "")]
10170 "TARGET_HTM"
10171 {
10172 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
10173 DONE;
10174 })
10176 (define_expand "tbegin_retry"
10177 [(match_operand:SI 0 "register_operand" "")
10178 (match_operand:BLK 1 "memory_operand" "")
10179 (match_operand:SI 2 "general_operand" "")]
10180 "TARGET_HTM"
10181 {
10182 s390_expand_tbegin (operands[0], operands[1], operands[2], true);
10183 DONE;
10184 })
10186 (define_expand "tbegin_retry_nofloat"
10187 [(match_operand:SI 0 "register_operand" "")
10188 (match_operand:BLK 1 "memory_operand" "")
10189 (match_operand:SI 2 "general_operand" "")]
10190 "TARGET_HTM"
10191 {
10192 s390_expand_tbegin (operands[0], operands[1], operands[2], false);
10193 DONE;
10194 })
10196 (define_insn "tbegin_1"
10197 [(set (reg:CCRAW CC_REGNUM)
10198 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10199 UNSPECV_TBEGIN))
10200 (set (match_operand:BLK 1 "memory_operand" "=Q")
10201 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10202 (clobber (reg:DF 16))
10203 (clobber (reg:DF 17))
10204 (clobber (reg:DF 18))
10205 (clobber (reg:DF 19))
10206 (clobber (reg:DF 20))
10207 (clobber (reg:DF 21))
10208 (clobber (reg:DF 22))
10209 (clobber (reg:DF 23))
10210 (clobber (reg:DF 24))
10211 (clobber (reg:DF 25))
10212 (clobber (reg:DF 26))
10213 (clobber (reg:DF 27))
10214 (clobber (reg:DF 28))
10215 (clobber (reg:DF 29))
10216 (clobber (reg:DF 30))
10217 (clobber (reg:DF 31))]
10218 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10219 ; not supposed to be used for immediates (see genpreds.c).
10220 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10221 "tbegin\t%1,%x0"
10222 [(set_attr "op_type" "SIL")])
10224 ; Same as above but without the FPR clobbers
10225 (define_insn "tbegin_nofloat_1"
10226 [(set (reg:CCRAW CC_REGNUM)
10227 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10228 UNSPECV_TBEGIN))
10229 (set (match_operand:BLK 1 "memory_operand" "=Q")
10230 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
10231 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10232 "tbegin\t%1,%x0"
10233 [(set_attr "op_type" "SIL")])
10236 ; Constrained transaction begin
10238 (define_expand "tbeginc"
10239 [(set (reg:CCRAW CC_REGNUM)
10240 (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
10241 UNSPECV_TBEGINC))]
10242 "TARGET_HTM"
10243 "")
10245 (define_insn "*tbeginc_1"
10246 [(set (reg:CCRAW CC_REGNUM)
10247 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
10248 UNSPECV_TBEGINC))]
10249 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10250 "tbeginc\t0,%x0"
10251 [(set_attr "op_type" "SIL")])
10253 ; Transaction end
10255 (define_expand "tend"
10256 [(set (reg:CCRAW CC_REGNUM)
10257 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
10258 (set (match_operand:SI 0 "register_operand" "")
10259 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10260 "TARGET_HTM"
10261 "")
10263 (define_insn "*tend_1"
10264 [(set (reg:CCRAW CC_REGNUM)
10265 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
10266 "TARGET_HTM"
10267 "tend"
10268 [(set_attr "op_type" "S")])
10270 ; Transaction abort
10272 (define_expand "tabort"
10273 [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "")]
10274 UNSPECV_TABORT)]
10275 "TARGET_HTM && operands != NULL"
10276 {
10277 if (CONST_INT_P (operands[0])
10278 && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
10279 {
10280 error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
10281 ". Values in range 0 through 255 are reserved.",
10282 INTVAL (operands[0]));
10283 FAIL;
10284 }
10285 })
10287 (define_insn "*tabort_1"
10288 [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "Y")]
10289 UNSPECV_TABORT)]
10290 "TARGET_HTM && operands != NULL"
10291 "tabort\t%Y0"
10292 [(set_attr "op_type" "S")])
10294 ; Transaction extract nesting depth
10296 (define_insn "etnd"
10297 [(set (match_operand:SI 0 "register_operand" "=d")
10298 (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
10299 "TARGET_HTM"
10300 "etnd\t%0"
10301 [(set_attr "op_type" "RRE")])
10303 ; Non-transactional store
10305 (define_insn "ntstg"
10306 [(set (match_operand:DI 0 "memory_operand" "=RT")
10307 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
10308 UNSPECV_NTSTG))]
10309 "TARGET_HTM"
10310 "ntstg\t%1,%0"
10311 [(set_attr "op_type" "RXY")])
10313 ; Transaction perform processor assist
10315 (define_expand "tx_assist"
10316 [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
10317 (reg:SI GPR0_REGNUM)
10318 (const_int 1)]
10319 UNSPECV_PPA)]
10320 "TARGET_HTM"
10321 "")
10323 (define_insn "*ppa"
10324 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
10325 (match_operand:SI 1 "register_operand" "d")
10326 (match_operand 2 "const_int_operand" "I")]
10327 UNSPECV_PPA)]
10328 "TARGET_HTM && INTVAL (operands[2]) < 16"
10329 "ppa\t%0,%1,%2"
10330 [(set_attr "op_type" "RRF")])
10333 ; Set and get floating point control register
10335 (define_insn "s390_sfpc"
10336 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
10337 UNSPECV_SFPC)]
10338 "TARGET_HARD_FLOAT"
10339 "sfpc\t%0")
10341 (define_insn "s390_efpc"
10342 [(set (match_operand:SI 0 "register_operand" "=d")
10343 (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))]
10344 "TARGET_HARD_FLOAT"
10345 "efpc\t%0")