1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992-2015 Free Software Foundation, Inc.
3 ;; Contributed by the Center for Software Science at the University
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; This machine description is inspired by sparc.md and to a lesser
25 ;; Possible improvements:
27 ;; * With PA1.1, most computational instructions can conditionally nullify
28 ;; the execution of the following instruction. A nullified instruction
29 ;; does not cause the instruction pipeline to stall, making it a very
30 ;; efficient alternative to e.g. branching or conditional moves.
32 ;; Nullification is performed conditionally based on the outcome of a
33 ;; test specified in the opcode. The test result is stored in PSW[N]
34 ;; and can only be used to nullify the instruction following immediately
35 ;; after the test. For example:
39 ;; sub,< %r26,%r25,%r28
40 ;; sub %r28,%r25,%r28 ; %r28 == 0
41 ;; sub,> %r26,%r25,%r29
42 ;; sub %r29,%r25,%r29 ; %r29 == 5
44 ;; This could be tricky to implement because the result of the test has
45 ;; to be propagated one instruction forward, which, in the worst case,
46 ;; would involve (1) adding a fake register for PSW[N]; (2) adding the
47 ;; variants of the computational instructions that set or consume this
48 ;; fake register. The cond_exec infrastructure is probably not helpful
51 ;; * PA-RISC includes a set of conventions for branch instruction usage
52 ;; to indicate whether a particular branch is more likely to be taken
53 ;; or not taken. For example, the prediction for CMPB instructions
54 ;; (CMPB,cond,n r1,r2,target) depends on the direction of the branch
55 ;; (forward or backward) and on the order of the operands:
57 ;; | branch | operand | branch |
58 ;; | direction | compare | prediction |
59 ;; +-----------+----------+------------+
60 ;; | backward | r1 < r2 | taken |
61 ;; | backward | r1 >= r2 | not taken |
62 ;; | forward | r1 < r2 | not taken |
63 ;; | forward | r1 >= r2 | taken |
65 ;; By choosing instructions and operand order carefully, the compiler
66 ;; could give the CPU branch predictor some help.
69 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
71 ;; Uses of UNSPEC in this file:
73 (define_c_enum "unspec"
74 [UNSPEC_CFFC ; canonicalize_funcptr_for_compare
75 UNSPEC_GOTO ; indirect_goto
91 (define_c_enum "unspecv"
92 [UNSPECV_BLOCKAGE ; blockage
93 UNSPECV_DCACHE ; dcacheflush
94 UNSPECV_ICACHE ; icacheflush
95 UNSPECV_OPC ; outline_prologue_call
96 UNSPECV_OEC ; outline_epilogue_call
97 UNSPECV_LONGJMP ; builtin_longjmp
100 ;; Maximum pc-relative branch offsets.
102 ;; These numbers are a bit smaller than the maximum allowable offsets
103 ;; so that a few instructions may be inserted before the actual branch.
106 [(MAX_12BIT_OFFSET 8184) ; 12-bit branch
107 (MAX_17BIT_OFFSET 262100) ; 17-bit branch
110 ;; Mode and code iterators
112 ;; This mode iterator allows :P to be used for patterns that operate on
113 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
114 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
116 ;; This attribute defines the condition prefix for word and double word
117 ;; add, compare, subtract and logical instructions.
118 (define_mode_attr dwc [(SI "") (DI "*")])
120 ;; Insn type. Used to default other attribute values.
122 ;; type "unary" insns have one input operand (1) and one output operand (0)
123 ;; type "binary" insns have two input operands (1,2) and one output (0)
126 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,sh_func_adrs,parallel_branch,fpstore_load,store_fpload,trap"
127 (const_string "binary"))
129 (define_attr "pa_combine_type"
130 "fmpy,faddsub,uncond_branch,addmove,none"
131 (const_string "none"))
133 ;; Processor type (for scheduling, not code generation) -- this attribute
134 ;; must exactly match the processor_type enumeration in pa.h.
136 ;; FIXME: Add 800 scheduling for completeness?
138 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
140 ;; Length (in # of bytes).
141 (define_attr "length" ""
142 (cond [(eq_attr "type" "load,fpload")
143 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
144 (const_int 8) (const_int 4))
146 (eq_attr "type" "store,fpstore")
147 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
148 (const_int 8) (const_int 4))
150 (eq_attr "type" "binary,shift,nullshift")
151 (if_then_else (match_operand 2 "arith14_operand" "")
152 (const_int 4) (const_int 12))
154 (eq_attr "type" "move,unary,shift,nullshift")
155 (if_then_else (match_operand 1 "arith14_operand" "")
156 (const_int 4) (const_int 8))]
160 (define_asm_attributes
161 [(set_attr "length" "4")
162 (set_attr "type" "multi")])
164 ;; Attributes for instruction and branch scheduling
166 ;; For conditional branches. Frame related instructions are not allowed
167 ;; because they confuse the unwind support.
168 (define_attr "in_branch_delay" "false,true"
169 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,trap")
170 (eq_attr "length" "4")
171 (not (match_test "RTX_FRAME_RELATED_P (insn)")))
172 (const_string "true")
173 (const_string "false")))
175 ;; Disallow instructions which use the FPU since they will tie up the FPU
176 ;; even if the instruction is nullified.
177 (define_attr "in_nullified_branch_delay" "false,true"
178 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch,trap")
179 (eq_attr "length" "4")
180 (not (match_test "RTX_FRAME_RELATED_P (insn)")))
181 (const_string "true")
182 (const_string "false")))
184 ;; For calls and millicode calls.
185 (define_attr "in_call_delay" "false,true"
186 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,trap")
187 (eq_attr "length" "4")
188 (not (match_test "RTX_FRAME_RELATED_P (insn)")))
189 (const_string "true")
190 (const_string "false")))
192 ;; Call delay slot description.
193 (define_delay (eq_attr "type" "call")
194 [(eq_attr "in_call_delay" "true") (nil) (nil)])
196 ;; Sibcall delay slot description.
197 (define_delay (eq_attr "type" "sibcall")
198 [(eq_attr "in_call_delay" "true") (nil) (nil)])
200 ;; Millicode call delay slot description.
201 (define_delay (eq_attr "type" "milli")
202 [(eq_attr "in_call_delay" "true") (nil) (nil)])
204 ;; Return and other similar instructions.
205 (define_delay (eq_attr "type" "branch,parallel_branch")
206 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
208 ;; Floating point conditional branch delay slot description.
209 (define_delay (eq_attr "type" "fbranch")
210 [(eq_attr "in_branch_delay" "true")
211 (eq_attr "in_nullified_branch_delay" "true")
214 ;; Integer conditional branch delay slot description.
215 ;; Nullification of conditional branches on the PA is dependent on the
216 ;; direction of the branch. Forward branches nullify true and
217 ;; backward branches nullify false. If the direction is unknown
218 ;; then nullification is not allowed.
219 (define_delay (eq_attr "type" "cbranch")
220 [(eq_attr "in_branch_delay" "true")
221 (and (eq_attr "in_nullified_branch_delay" "true")
222 (attr_flag "forward"))
223 (and (eq_attr "in_nullified_branch_delay" "true")
224 (attr_flag "backward"))])
226 (define_delay (eq_attr "type" "uncond_branch")
227 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
229 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
230 ;; load: 2, fpload: 3
231 ;; store, fpstore: 3, no D-cache operations should be scheduled.
233 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
235 ;; Instruction Time Unit Minimum Distance (unit contention)
242 ;; fmpyadd 3 ALU,MPY 2
243 ;; fmpysub 3 ALU,MPY 2
244 ;; fmpycfxt 3 ALU,MPY 2
247 ;; fdiv,sgl 10 MPY 10
248 ;; fdiv,dbl 12 MPY 12
249 ;; fsqrt,sgl 14 MPY 14
250 ;; fsqrt,dbl 18 MPY 18
252 ;; We don't model fmpyadd/fmpysub properly as those instructions
253 ;; keep both the FP ALU and MPY units busy. Given that these
254 ;; processors are obsolete, I'm not going to spend the time to
255 ;; model those instructions correctly.
257 (define_automaton "pa700")
258 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
260 (define_insn_reservation "W0" 4
261 (and (eq_attr "type" "fpcc")
262 (eq_attr "cpu" "700"))
265 (define_insn_reservation "W1" 3
266 (and (eq_attr "type" "fpalu")
267 (eq_attr "cpu" "700"))
270 (define_insn_reservation "W2" 3
271 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
272 (eq_attr "cpu" "700"))
275 (define_insn_reservation "W3" 10
276 (and (eq_attr "type" "fpdivsgl")
277 (eq_attr "cpu" "700"))
280 (define_insn_reservation "W4" 12
281 (and (eq_attr "type" "fpdivdbl")
282 (eq_attr "cpu" "700"))
285 (define_insn_reservation "W5" 14
286 (and (eq_attr "type" "fpsqrtsgl")
287 (eq_attr "cpu" "700"))
290 (define_insn_reservation "W6" 18
291 (and (eq_attr "type" "fpsqrtdbl")
292 (eq_attr "cpu" "700"))
295 (define_insn_reservation "W7" 2
296 (and (eq_attr "type" "load")
297 (eq_attr "cpu" "700"))
300 (define_insn_reservation "W8" 2
301 (and (eq_attr "type" "fpload")
302 (eq_attr "cpu" "700"))
305 (define_insn_reservation "W9" 3
306 (and (eq_attr "type" "store")
307 (eq_attr "cpu" "700"))
310 (define_insn_reservation "W10" 3
311 (and (eq_attr "type" "fpstore")
312 (eq_attr "cpu" "700"))
315 (define_insn_reservation "W11" 5
316 (and (eq_attr "type" "fpstore_load")
317 (eq_attr "cpu" "700"))
320 (define_insn_reservation "W12" 6
321 (and (eq_attr "type" "store_fpload")
322 (eq_attr "cpu" "700"))
325 (define_insn_reservation "W13" 1
326 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
327 (eq_attr "cpu" "700"))
330 ;; We have a bypass for all computations in the FP unit which feed an
331 ;; FP store as long as the sizes are the same.
332 (define_bypass 2 "W1,W2" "W10,W11" "pa_fpstore_bypass_p")
333 (define_bypass 9 "W3" "W10,W11" "pa_fpstore_bypass_p")
334 (define_bypass 11 "W4" "W10,W11" "pa_fpstore_bypass_p")
335 (define_bypass 13 "W5" "W10,W11" "pa_fpstore_bypass_p")
336 (define_bypass 17 "W6" "W10,W11" "pa_fpstore_bypass_p")
338 ;; We have an "anti-bypass" for FP loads which feed an FP store.
339 (define_bypass 4 "W8,W12" "W10,W11" "pa_fpstore_bypass_p")
341 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
342 ;; floating point computations with non-floating point computations (fp loads
343 ;; and stores are not fp computations).
345 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
346 ;; take two cycles, during which no Dcache operations should be scheduled.
347 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
348 ;; all have the same memory characteristics if one disregards cache misses.
350 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
351 ;; There's no value in modeling the ALU and MUL separately though
352 ;; since there can never be a functional unit conflict given the
353 ;; latency and issue rates for those units.
356 ;; Instruction Time Unit Minimum Distance (unit contention)
363 ;; fmpyadd 2 ALU,MPY 1
364 ;; fmpysub 2 ALU,MPY 1
365 ;; fmpycfxt 2 ALU,MPY 1
369 ;; fdiv,dbl 15 DIV 15
371 ;; fsqrt,dbl 15 DIV 15
373 (define_automaton "pa7100")
374 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
376 (define_insn_reservation "X0" 2
377 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
378 (eq_attr "cpu" "7100"))
381 (define_insn_reservation "X1" 8
382 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
383 (eq_attr "cpu" "7100"))
384 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
386 (define_insn_reservation "X2" 15
387 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
388 (eq_attr "cpu" "7100"))
389 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
391 (define_insn_reservation "X3" 2
392 (and (eq_attr "type" "load")
393 (eq_attr "cpu" "7100"))
396 (define_insn_reservation "X4" 2
397 (and (eq_attr "type" "fpload")
398 (eq_attr "cpu" "7100"))
401 (define_insn_reservation "X5" 2
402 (and (eq_attr "type" "store")
403 (eq_attr "cpu" "7100"))
404 "i_7100+mem_7100,mem_7100")
406 (define_insn_reservation "X6" 2
407 (and (eq_attr "type" "fpstore")
408 (eq_attr "cpu" "7100"))
409 "i_7100+mem_7100,mem_7100")
411 (define_insn_reservation "X7" 4
412 (and (eq_attr "type" "fpstore_load")
413 (eq_attr "cpu" "7100"))
414 "i_7100+mem_7100,mem_7100*3")
416 (define_insn_reservation "X8" 4
417 (and (eq_attr "type" "store_fpload")
418 (eq_attr "cpu" "7100"))
419 "i_7100+mem_7100,mem_7100*3")
421 (define_insn_reservation "X9" 1
422 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
423 (eq_attr "cpu" "7100"))
426 ;; We have a bypass for all computations in the FP unit which feed an
427 ;; FP store as long as the sizes are the same.
428 (define_bypass 1 "X0" "X6,X7" "pa_fpstore_bypass_p")
429 (define_bypass 7 "X1" "X6,X7" "pa_fpstore_bypass_p")
430 (define_bypass 14 "X2" "X6,X7" "pa_fpstore_bypass_p")
432 ;; We have an "anti-bypass" for FP loads which feed an FP store.
433 (define_bypass 3 "X4,X8" "X6,X7" "pa_fpstore_bypass_p")
435 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
436 ;; There's no value in modeling the ALU and MUL separately though
437 ;; since there can never be a functional unit conflict that
438 ;; can be avoided given the latency, issue rates and mandatory
439 ;; one cycle cpu-wide lock for a double precision fp multiply.
442 ;; Instruction Time Unit Minimum Distance (unit contention)
449 ;; fmpyadd,sgl 2 ALU,MPY 1
450 ;; fmpyadd,dbl 3 ALU,MPY 2
451 ;; fmpysub,sgl 2 ALU,MPY 1
452 ;; fmpysub,dbl 3 ALU,MPY 2
453 ;; fmpycfxt,sgl 2 ALU,MPY 1
454 ;; fmpycfxt,dbl 3 ALU,MPY 2
459 ;; fdiv,dbl 15 DIV 15
461 ;; fsqrt,dbl 15 DIV 15
463 ;; The PA7200 is just like the PA7100LC except that there is
464 ;; no store-store penalty.
466 ;; The PA7300 is just like the PA7200 except that there is
467 ;; no store-load penalty.
469 ;; Note there are some aspects of the 7100LC we are not modeling
470 ;; at the moment. I'll be reviewing the 7100LC scheduling info
471 ;; shortly and updating this description.
475 ;; other issue modeling
477 (define_automaton "pa7100lc")
478 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
479 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
480 (define_cpu_unit "mem_7100lc" "pa7100lc")
482 ;; Double precision multiplies lock the entire CPU for one
483 ;; cycle. There is no way to avoid this lock and trying to
484 ;; schedule around the lock is pointless and thus there is no
485 ;; value in trying to model this lock.
487 ;; Not modeling the lock allows us to treat fp multiplies just
488 ;; like any other FP alu instruction. It allows for a smaller
489 ;; DFA and may reduce register pressure.
490 (define_insn_reservation "Y0" 2
491 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
492 (eq_attr "cpu" "7100LC,7200,7300"))
493 "f_7100lc,fpmac_7100lc")
495 ;; fp division and sqrt instructions lock the entire CPU for
496 ;; 7 cycles (single precision) or 14 cycles (double precision).
497 ;; There is no way to avoid this lock and trying to schedule
498 ;; around the lock is pointless and thus there is no value in
499 ;; trying to model this lock. Not modeling the lock allows
500 ;; for a smaller DFA and may reduce register pressure.
501 (define_insn_reservation "Y1" 1
502 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
503 (eq_attr "cpu" "7100LC,7200,7300"))
506 (define_insn_reservation "Y2" 2
507 (and (eq_attr "type" "load")
508 (eq_attr "cpu" "7100LC,7200,7300"))
509 "i1_7100lc+mem_7100lc")
511 (define_insn_reservation "Y3" 2
512 (and (eq_attr "type" "fpload")
513 (eq_attr "cpu" "7100LC,7200,7300"))
514 "i1_7100lc+mem_7100lc")
516 (define_insn_reservation "Y4" 2
517 (and (eq_attr "type" "store")
518 (eq_attr "cpu" "7100LC"))
519 "i1_7100lc+mem_7100lc,mem_7100lc")
521 (define_insn_reservation "Y5" 2
522 (and (eq_attr "type" "fpstore")
523 (eq_attr "cpu" "7100LC"))
524 "i1_7100lc+mem_7100lc,mem_7100lc")
526 (define_insn_reservation "Y6" 4
527 (and (eq_attr "type" "fpstore_load")
528 (eq_attr "cpu" "7100LC"))
529 "i1_7100lc+mem_7100lc,mem_7100lc*3")
531 (define_insn_reservation "Y7" 4
532 (and (eq_attr "type" "store_fpload")
533 (eq_attr "cpu" "7100LC"))
534 "i1_7100lc+mem_7100lc,mem_7100lc*3")
536 (define_insn_reservation "Y8" 1
537 (and (eq_attr "type" "shift,nullshift")
538 (eq_attr "cpu" "7100LC,7200,7300"))
541 (define_insn_reservation "Y9" 1
542 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
543 (eq_attr "cpu" "7100LC,7200,7300"))
544 "(i0_7100lc|i1_7100lc)")
546 ;; The 7200 has a store-load penalty
547 (define_insn_reservation "Y10" 2
548 (and (eq_attr "type" "store")
549 (eq_attr "cpu" "7200"))
550 "i1_7100lc,mem_7100lc")
552 (define_insn_reservation "Y11" 2
553 (and (eq_attr "type" "fpstore")
554 (eq_attr "cpu" "7200"))
555 "i1_7100lc,mem_7100lc")
557 (define_insn_reservation "Y12" 4
558 (and (eq_attr "type" "fpstore_load")
559 (eq_attr "cpu" "7200"))
560 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
562 (define_insn_reservation "Y13" 4
563 (and (eq_attr "type" "store_fpload")
564 (eq_attr "cpu" "7200"))
565 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
567 ;; The 7300 has no penalty for store-store or store-load
568 (define_insn_reservation "Y14" 2
569 (and (eq_attr "type" "store")
570 (eq_attr "cpu" "7300"))
573 (define_insn_reservation "Y15" 2
574 (and (eq_attr "type" "fpstore")
575 (eq_attr "cpu" "7300"))
578 (define_insn_reservation "Y16" 4
579 (and (eq_attr "type" "fpstore_load")
580 (eq_attr "cpu" "7300"))
581 "i1_7100lc,i1_7100lc+mem_7100lc")
583 (define_insn_reservation "Y17" 4
584 (and (eq_attr "type" "store_fpload")
585 (eq_attr "cpu" "7300"))
586 "i1_7100lc,i1_7100lc+mem_7100lc")
588 ;; We have an "anti-bypass" for FP loads which feed an FP store.
589 (define_bypass 3 "Y3,Y7,Y13,Y17" "Y5,Y6,Y11,Y12,Y15,Y16" "pa_fpstore_bypass_p")
591 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
592 ;; traditional architecture.
594 ;; The PA8000 has a large (56) entry reorder buffer that is split between
595 ;; memory and non-memory operations.
597 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
598 ;; the function units, with the exception of branches and multi-output
599 ;; instructions. The PA8000 can retire two non-memory operations per cycle
600 ;; and two memory operations per cycle, only one of which may be a store.
602 ;; Given the large reorder buffer, the processor can hide most latencies.
603 ;; According to HP, they've got the best results by scheduling for retirement
604 ;; bandwidth with limited latency scheduling for floating point operations.
605 ;; Latency for integer operations and memory references is ignored.
608 ;; We claim floating point operations have a 2 cycle latency and are
609 ;; fully pipelined, except for div and sqrt which are not pipelined and
610 ;; take from 17 to 31 cycles to complete.
612 ;; It's worth noting that there is no way to saturate all the functional
613 ;; units on the PA8000 as there is not enough issue bandwidth.
615 (define_automaton "pa8000")
616 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
617 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
618 (define_cpu_unit "store_8000" "pa8000")
619 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
620 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
621 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
622 (define_reservation "im_8000" "im0_8000 | im1_8000")
623 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
624 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
625 (define_reservation "f_8000" "f0_8000 | f1_8000")
626 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
628 ;; We can issue any two memops per cycle, but we can only retire
629 ;; one memory store per cycle. We assume that the reorder buffer
630 ;; will hide any memory latencies per HP's recommendation.
631 (define_insn_reservation "Z0" 0
633 (eq_attr "type" "load,fpload")
634 (eq_attr "cpu" "8000"))
637 (define_insn_reservation "Z1" 0
639 (eq_attr "type" "store,fpstore")
640 (eq_attr "cpu" "8000"))
641 "im_8000,rm_8000+store_8000")
643 (define_insn_reservation "Z2" 0
644 (and (eq_attr "type" "fpstore_load,store_fpload")
645 (eq_attr "cpu" "8000"))
646 "im_8000,rm_8000+store_8000,im_8000,rm_8000")
648 ;; We can issue and retire two non-memory operations per cycle with
649 ;; a few exceptions (branches). This group catches those we want
650 ;; to assume have zero latency.
651 (define_insn_reservation "Z3" 0
653 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl,fpstore_load,store_fpload")
654 (eq_attr "cpu" "8000"))
657 ;; Branches use both slots in the non-memory issue and
659 (define_insn_reservation "Z4" 0
661 (eq_attr "type" "uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch")
662 (eq_attr "cpu" "8000"))
663 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
665 ;; We partial latency schedule the floating point units.
666 ;; They can issue/retire two at a time in the non-memory
667 ;; units. We fix their latency at 2 cycles and they
668 ;; are fully pipelined.
669 (define_insn_reservation "Z5" 1
671 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
672 (eq_attr "cpu" "8000"))
673 "inm_8000,f_8000,rnm_8000")
675 ;; The fdivsqrt units are not pipelined and have a very long latency.
676 ;; To keep the DFA from exploding, we do not show all the
677 ;; reservations for the divsqrt unit.
678 (define_insn_reservation "Z6" 17
680 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
681 (eq_attr "cpu" "8000"))
682 "inm_8000,fdivsqrt_8000*6,rnm_8000")
684 (define_insn_reservation "Z7" 31
686 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
687 (eq_attr "cpu" "8000"))
688 "inm_8000,fdivsqrt_8000*6,rnm_8000")
690 ;; Operand and operator predicates and constraints
692 (include "predicates.md")
693 (include "constraints.md")
695 ;; Atomic instructions
697 ;; All memory loads and stores access storage atomically except
698 ;; for one exception. The STORE BYTES, STORE DOUBLE BYTES, and
699 ;; doubleword loads and stores are not guaranteed to be atomic
700 ;; when referencing the I/O address space.
702 ;; Implement atomic DImode load using 64-bit floating point load and copy.
704 (define_expand "atomic_loaddi"
705 [(match_operand:DI 0 "register_operand") ;; val out
706 (match_operand:DI 1 "memory_operand") ;; memory
707 (match_operand:SI 2 "const_int_operand")] ;; model
708 "!TARGET_64BIT && !TARGET_SOFT_FLOAT"
710 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
711 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
712 operands[2] = gen_reg_rtx (DImode);
713 expand_mem_thread_fence (model);
714 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1], operands[2]));
715 if ((model & MEMMODEL_MASK) == MEMMODEL_SEQ_CST)
716 expand_mem_thread_fence (model);
720 (define_insn "atomic_loaddi_1"
721 [(set (match_operand:DI 0 "register_operand" "=r")
722 (mem:DI (match_operand:SI 1 "register_operand" "r")))
723 (clobber (match_operand:DI 2 "register_operand" "=&f"))]
724 "!TARGET_64BIT && !TARGET_SOFT_FLOAT"
725 "{fldds|fldd} 0(%1),%2\;{fstds|fstd} %2,-16(%%sp)\;{ldws|ldw} -16(%%sp),%0\;{ldws|ldw} -12(%%sp),%R0"
726 [(set_attr "type" "move")
727 (set_attr "length" "16")])
729 ;; Implement atomic DImode store using copy and 64-bit floating point store.
731 (define_expand "atomic_storedi"
732 [(match_operand:DI 0 "memory_operand") ;; memory
733 (match_operand:DI 1 "register_operand") ;; val out
734 (match_operand:SI 2 "const_int_operand")] ;; model
735 "!TARGET_64BIT && !TARGET_SOFT_FLOAT"
737 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
738 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
739 operands[2] = gen_reg_rtx (DImode);
740 expand_mem_thread_fence (model);
741 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1], operands[2]));
742 if ((model & MEMMODEL_MASK) == MEMMODEL_SEQ_CST)
743 expand_mem_thread_fence (model);
747 (define_insn "atomic_storedi_1"
748 [(set (mem:DI (match_operand:SI 0 "register_operand" "r"))
749 (match_operand:DI 1 "register_operand" "r"))
750 (clobber (match_operand:DI 2 "register_operand" "=&f"))]
751 "!TARGET_64BIT && !TARGET_SOFT_FLOAT"
752 "{stws|stw} %1,-16(%%sp)\;{stws|stw} %R1,-12(%%sp)\;{fldds|fldd} -16(%%sp),%2\;{fstds|fstd} %2,0(%0)"
753 [(set_attr "type" "move")
754 (set_attr "length" "16")])
756 ;; Compare instructions.
757 ;; This controls RTL generation and register allocation.
761 (match_operator:CCFP 2 "comparison_operator"
762 [(match_operand:SF 0 "reg_or_0_operand" "fG")
763 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
764 "! TARGET_SOFT_FLOAT"
765 "fcmp,sgl,%Y2 %f0,%f1"
766 [(set_attr "length" "4")
767 (set_attr "type" "fpcc")])
771 (match_operator:CCFP 2 "comparison_operator"
772 [(match_operand:DF 0 "reg_or_0_operand" "fG")
773 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
774 "! TARGET_SOFT_FLOAT"
775 "fcmp,dbl,%Y2 %f0,%f1"
776 [(set_attr "length" "4")
777 (set_attr "type" "fpcc")])
779 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
780 ;; placeholders. This is necessary in rare situations when a
781 ;; placeholder is re-emitted (see PR 8705).
783 (define_expand "movccfp"
785 (match_operand 0 "const_int_operand" ""))]
786 "! TARGET_SOFT_FLOAT"
789 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
793 ;; The following patterns are optimization placeholders. In almost
794 ;; all cases, the user of the condition code will be simplified and the
795 ;; original condition code setting insn should be eliminated.
797 (define_insn "*movccfp0"
800 "! TARGET_SOFT_FLOAT"
801 "fcmp,dbl,= %%fr0,%%fr0"
802 [(set_attr "length" "4")
803 (set_attr "type" "fpcc")])
805 (define_insn "*movccfp1"
808 "! TARGET_SOFT_FLOAT"
809 "fcmp,dbl,!= %%fr0,%%fr0"
810 [(set_attr "length" "4")
811 (set_attr "type" "fpcc")])
815 (define_expand "cstoresi4"
816 [(set (match_operand:SI 0 "register_operand")
817 (match_operator:SI 1 "ordered_comparison_operator"
818 [(match_operand:SI 2 "reg_or_0_operand" "")
819 (match_operand:SI 3 "arith5_operand" "")]))]
823 ;; Instruction canonicalization puts immediate operands second, which
824 ;; is the reverse of what we want.
827 [(set (match_operand:SI 0 "register_operand" "=r")
828 (match_operator:SI 3 "comparison_operator"
829 [(match_operand:SI 1 "reg_or_0_operand" "rM")
830 (match_operand:SI 2 "arith11_operand" "rI")]))]
832 "{com%I2clr|cmp%I2clr},%B3 %2,%r1,%0\;ldi 1,%0"
833 [(set_attr "type" "binary")
834 (set_attr "length" "8")])
837 [(set (match_operand:DI 0 "register_operand" "=r")
838 (match_operator:DI 3 "comparison_operator"
839 [(match_operand:DI 1 "reg_or_0_operand" "rM")
840 (match_operand:DI 2 "arith11_operand" "rI")]))]
842 "cmp%I2clr,*%B3 %2,%r1,%0\;ldi 1,%0"
843 [(set_attr "type" "binary")
844 (set_attr "length" "8")])
846 (define_insn "iorscc"
847 [(set (match_operand:SI 0 "register_operand" "=r")
848 (ior:SI (match_operator:SI 3 "comparison_operator"
849 [(match_operand:SI 1 "reg_or_0_operand" "rM")
850 (match_operand:SI 2 "arith11_operand" "rI")])
851 (match_operator:SI 6 "comparison_operator"
852 [(match_operand:SI 4 "reg_or_0_operand" "rM")
853 (match_operand:SI 5 "arith11_operand" "rI")])))]
855 "{com%I2clr|cmp%I2clr},%S3 %2,%r1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%r4,%0\;ldi 1,%0"
856 [(set_attr "type" "binary")
857 (set_attr "length" "12")])
860 [(set (match_operand:DI 0 "register_operand" "=r")
861 (ior:DI (match_operator:DI 3 "comparison_operator"
862 [(match_operand:DI 1 "reg_or_0_operand" "rM")
863 (match_operand:DI 2 "arith11_operand" "rI")])
864 (match_operator:DI 6 "comparison_operator"
865 [(match_operand:DI 4 "reg_or_0_operand" "rM")
866 (match_operand:DI 5 "arith11_operand" "rI")])))]
868 "cmp%I2clr,*%S3 %2,%r1,%%r0\;cmp%I5clr,*%B6 %5,%r4,%0\;ldi 1,%0"
869 [(set_attr "type" "binary")
870 (set_attr "length" "12")])
872 ;; Combiner patterns for common operations performed with the output
873 ;; from an scc insn (negscc and incscc).
874 (define_insn "negscc"
875 [(set (match_operand:SI 0 "register_operand" "=r")
876 (neg:SI (match_operator:SI 3 "comparison_operator"
877 [(match_operand:SI 1 "reg_or_0_operand" "rM")
878 (match_operand:SI 2 "arith11_operand" "rI")])))]
880 "{com%I2clr|cmp%I2clr},%B3 %2,%r1,%0\;ldi -1,%0"
881 [(set_attr "type" "binary")
882 (set_attr "length" "8")])
885 [(set (match_operand:DI 0 "register_operand" "=r")
886 (neg:DI (match_operator:DI 3 "comparison_operator"
887 [(match_operand:DI 1 "reg_or_0_operand" "rM")
888 (match_operand:DI 2 "arith11_operand" "rI")])))]
890 "cmp%I2clr,*%B3 %2,%r1,%0\;ldi -1,%0"
891 [(set_attr "type" "binary")
892 (set_attr "length" "8")])
894 ;; Patterns for adding/subtracting the result of a boolean expression from
895 ;; a register. First we have special patterns that make use of the carry
896 ;; bit, and output only two instructions. For the cases we can't in
897 ;; general do in two instructions, the incscc pattern at the end outputs
898 ;; two or three instructions.
901 [(set (match_operand:SI 0 "register_operand" "=r")
902 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
903 (match_operand:SI 3 "arith11_operand" "rI"))
904 (match_operand:SI 1 "register_operand" "r")))]
906 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
907 [(set_attr "type" "binary")
908 (set_attr "length" "8")])
911 [(set (match_operand:DI 0 "register_operand" "=r")
912 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
913 (match_operand:DI 3 "arith11_operand" "rI"))
914 (match_operand:DI 1 "register_operand" "r")))]
916 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
917 [(set_attr "type" "binary")
918 (set_attr "length" "8")])
920 ; This need only accept registers for op3, since canonicalization
921 ; replaces geu with gtu when op3 is an integer.
923 [(set (match_operand:SI 0 "register_operand" "=r")
924 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
925 (match_operand:SI 3 "register_operand" "r"))
926 (match_operand:SI 1 "register_operand" "r")))]
928 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
929 [(set_attr "type" "binary")
930 (set_attr "length" "8")])
933 [(set (match_operand:DI 0 "register_operand" "=r")
934 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
935 (match_operand:DI 3 "register_operand" "r"))
936 (match_operand:DI 1 "register_operand" "r")))]
938 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
939 [(set_attr "type" "binary")
940 (set_attr "length" "8")])
942 ; Match only integers for op3 here. This is used as canonical form of the
943 ; geu pattern when op3 is an integer. Don't match registers since we can't
944 ; make better code than the general incscc pattern.
946 [(set (match_operand:SI 0 "register_operand" "=r")
947 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
948 (match_operand:SI 3 "int11_operand" "I"))
949 (match_operand:SI 1 "register_operand" "r")))]
951 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
952 [(set_attr "type" "binary")
953 (set_attr "length" "8")])
956 [(set (match_operand:DI 0 "register_operand" "=r")
957 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
958 (match_operand:DI 3 "int11_operand" "I"))
959 (match_operand:DI 1 "register_operand" "r")))]
961 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
962 [(set_attr "type" "binary")
963 (set_attr "length" "8")])
965 (define_insn "incscc"
966 [(set (match_operand:SI 0 "register_operand" "=r,r")
967 (plus:SI (match_operator:SI 4 "comparison_operator"
968 [(match_operand:SI 2 "register_operand" "r,r")
969 (match_operand:SI 3 "arith11_operand" "rI,rI")])
970 (match_operand:SI 1 "register_operand" "0,?r")))]
973 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
974 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
975 [(set_attr "type" "binary,binary")
976 (set_attr "length" "8,12")])
979 [(set (match_operand:DI 0 "register_operand" "=r,r")
980 (plus:DI (match_operator:DI 4 "comparison_operator"
981 [(match_operand:DI 2 "register_operand" "r,r")
982 (match_operand:DI 3 "arith11_operand" "rI,rI")])
983 (match_operand:DI 1 "register_operand" "0,?r")))]
986 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
987 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
988 [(set_attr "type" "binary,binary")
989 (set_attr "length" "8,12")])
992 [(set (match_operand:SI 0 "register_operand" "=r")
993 (minus:SI (match_operand:SI 1 "register_operand" "r")
994 (gtu:SI (match_operand:SI 2 "register_operand" "r")
995 (match_operand:SI 3 "arith11_operand" "rI"))))]
997 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
998 [(set_attr "type" "binary")
999 (set_attr "length" "8")])
1002 [(set (match_operand:DI 0 "register_operand" "=r")
1003 (minus:DI (match_operand:DI 1 "register_operand" "r")
1004 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1005 (match_operand:DI 3 "arith11_operand" "rI"))))]
1007 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
1008 [(set_attr "type" "binary")
1009 (set_attr "length" "8")])
1012 [(set (match_operand:SI 0 "register_operand" "=r")
1013 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1014 (gtu:SI (match_operand:SI 2 "register_operand" "r")
1015 (match_operand:SI 3 "arith11_operand" "rI")))
1016 (match_operand:SI 4 "register_operand" "r")))]
1018 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1019 [(set_attr "type" "binary")
1020 (set_attr "length" "8")])
1023 [(set (match_operand:DI 0 "register_operand" "=r")
1024 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1025 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1026 (match_operand:DI 3 "arith11_operand" "rI")))
1027 (match_operand:DI 4 "register_operand" "r")))]
1029 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
1030 [(set_attr "type" "binary")
1031 (set_attr "length" "8")])
1033 ; This need only accept registers for op3, since canonicalization
1034 ; replaces ltu with leu when op3 is an integer.
1036 [(set (match_operand:SI 0 "register_operand" "=r")
1037 (minus:SI (match_operand:SI 1 "register_operand" "r")
1038 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1039 (match_operand:SI 3 "register_operand" "r"))))]
1041 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
1042 [(set_attr "type" "binary")
1043 (set_attr "length" "8")])
1046 [(set (match_operand:DI 0 "register_operand" "=r")
1047 (minus:DI (match_operand:DI 1 "register_operand" "r")
1048 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1049 (match_operand:DI 3 "register_operand" "r"))))]
1051 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
1052 [(set_attr "type" "binary")
1053 (set_attr "length" "8")])
1056 [(set (match_operand:SI 0 "register_operand" "=r")
1057 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1058 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1059 (match_operand:SI 3 "register_operand" "r")))
1060 (match_operand:SI 4 "register_operand" "r")))]
1062 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1063 [(set_attr "type" "binary")
1064 (set_attr "length" "8")])
1067 [(set (match_operand:DI 0 "register_operand" "=r")
1068 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1069 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1070 (match_operand:DI 3 "register_operand" "r")))
1071 (match_operand:DI 4 "register_operand" "r")))]
1073 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
1074 [(set_attr "type" "binary")
1075 (set_attr "length" "8")])
1077 ; Match only integers for op3 here. This is used as canonical form of the
1078 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1079 ; make better code than the general incscc pattern.
1081 [(set (match_operand:SI 0 "register_operand" "=r")
1082 (minus:SI (match_operand:SI 1 "register_operand" "r")
1083 (leu:SI (match_operand:SI 2 "register_operand" "r")
1084 (match_operand:SI 3 "int11_operand" "I"))))]
1086 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1087 [(set_attr "type" "binary")
1088 (set_attr "length" "8")])
1091 [(set (match_operand:DI 0 "register_operand" "=r")
1092 (minus:DI (match_operand:DI 1 "register_operand" "r")
1093 (leu:DI (match_operand:DI 2 "register_operand" "r")
1094 (match_operand:DI 3 "int11_operand" "I"))))]
1096 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1097 [(set_attr "type" "binary")
1098 (set_attr "length" "8")])
1101 [(set (match_operand:SI 0 "register_operand" "=r")
1102 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1103 (leu:SI (match_operand:SI 2 "register_operand" "r")
1104 (match_operand:SI 3 "int11_operand" "I")))
1105 (match_operand:SI 4 "register_operand" "r")))]
1107 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1108 [(set_attr "type" "binary")
1109 (set_attr "length" "8")])
1112 [(set (match_operand:DI 0 "register_operand" "=r")
1113 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1114 (leu:DI (match_operand:DI 2 "register_operand" "r")
1115 (match_operand:DI 3 "int11_operand" "I")))
1116 (match_operand:DI 4 "register_operand" "r")))]
1118 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1119 [(set_attr "type" "binary")
1120 (set_attr "length" "8")])
1122 (define_insn "decscc"
1123 [(set (match_operand:SI 0 "register_operand" "=r,r")
1124 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1125 (match_operator:SI 4 "comparison_operator"
1126 [(match_operand:SI 2 "register_operand" "r,r")
1127 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1130 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1131 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1132 [(set_attr "type" "binary,binary")
1133 (set_attr "length" "8,12")])
1136 [(set (match_operand:DI 0 "register_operand" "=r,r")
1137 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1138 (match_operator:DI 4 "comparison_operator"
1139 [(match_operand:DI 2 "register_operand" "r,r")
1140 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1143 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1144 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1145 [(set_attr "type" "binary,binary")
1146 (set_attr "length" "8,12")])
1148 ; Patterns for max and min. (There is no need for an earlyclobber in the
1149 ; last alternative since the middle alternative will match if op0 == op1.)
1151 (define_insn "sminsi3"
1152 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1153 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1154 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1157 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1158 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1159 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1160 [(set_attr "type" "multi,multi,multi")
1161 (set_attr "length" "8,8,8")])
1163 (define_insn "smindi3"
1164 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1165 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1166 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1169 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1170 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1171 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1172 [(set_attr "type" "multi,multi,multi")
1173 (set_attr "length" "8,8,8")])
1175 (define_insn "uminsi3"
1176 [(set (match_operand:SI 0 "register_operand" "=r,r")
1177 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1178 (match_operand:SI 2 "arith11_operand" "r,I")))]
1181 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1182 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1183 [(set_attr "type" "multi,multi")
1184 (set_attr "length" "8,8")])
1186 (define_insn "umindi3"
1187 [(set (match_operand:DI 0 "register_operand" "=r,r")
1188 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1189 (match_operand:DI 2 "arith11_operand" "r,I")))]
1192 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1193 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1194 [(set_attr "type" "multi,multi")
1195 (set_attr "length" "8,8")])
1197 (define_insn "smaxsi3"
1198 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1199 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1200 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1203 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1204 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1205 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1206 [(set_attr "type" "multi,multi,multi")
1207 (set_attr "length" "8,8,8")])
1209 (define_insn "smaxdi3"
1210 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1211 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1212 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1215 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1216 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1217 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1218 [(set_attr "type" "multi,multi,multi")
1219 (set_attr "length" "8,8,8")])
1221 (define_insn "umaxsi3"
1222 [(set (match_operand:SI 0 "register_operand" "=r,r")
1223 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1224 (match_operand:SI 2 "arith11_operand" "r,I")))]
1227 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1228 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1229 [(set_attr "type" "multi,multi")
1230 (set_attr "length" "8,8")])
1232 (define_insn "umaxdi3"
1233 [(set (match_operand:DI 0 "register_operand" "=r,r")
1234 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1235 (match_operand:DI 2 "arith11_operand" "r,I")))]
1238 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1239 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1240 [(set_attr "type" "multi,multi")
1241 (set_attr "length" "8,8")])
1243 (define_insn "abssi2"
1244 [(set (match_operand:SI 0 "register_operand" "=r")
1245 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1247 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1248 [(set_attr "type" "multi")
1249 (set_attr "length" "8")])
1251 (define_insn "absdi2"
1252 [(set (match_operand:DI 0 "register_operand" "=r")
1253 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1255 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1256 [(set_attr "type" "multi")
1257 (set_attr "length" "8")])
1259 ;;; Experimental conditional move patterns
1261 (define_expand "movsicc"
1262 [(set (match_operand:SI 0 "register_operand" "")
1264 (match_operand 1 "comparison_operator" "")
1265 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1266 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1270 if (GET_MODE (XEXP (operands[1], 0)) != SImode
1271 || GET_MODE (XEXP (operands[1], 0)) != GET_MODE (XEXP (operands[1], 1)))
1275 ;; We used to accept any register for op1.
1277 ;; However, it loses sometimes because the compiler will end up using
1278 ;; different registers for op0 and op1 in some critical cases. local-alloc
1279 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1281 ;; If/when global register allocation supports tying we should allow any
1282 ;; register for op1 again.
1284 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1286 (match_operator 2 "comparison_operator"
1287 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1288 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1289 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1293 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1294 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1295 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1296 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1297 [(set_attr "type" "multi,multi,multi,nullshift")
1298 (set_attr "length" "8,8,8,8")])
1301 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1303 (match_operator 5 "comparison_operator"
1304 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1305 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1306 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1307 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1310 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1311 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1312 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1313 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1314 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1315 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1316 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1317 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1318 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1319 (set_attr "length" "8,8,8,8,8,8,8,8")])
1321 (define_expand "movdicc"
1322 [(set (match_operand:DI 0 "register_operand" "")
1324 (match_operand 1 "comparison_operator" "")
1325 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1326 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1330 if (GET_MODE (XEXP (operands[1], 0)) != DImode
1331 || GET_MODE (XEXP (operands[1], 0)) != GET_MODE (XEXP (operands[1], 1)))
1335 ; We need the first constraint alternative in order to avoid
1336 ; earlyclobbers on all other alternatives.
1338 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1340 (match_operator 2 "comparison_operator"
1341 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1342 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1343 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1347 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1348 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1349 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1350 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1351 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1352 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1353 (set_attr "length" "8,8,8,8,8")])
1356 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1358 (match_operator 5 "comparison_operator"
1359 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1360 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1361 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1362 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1365 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1366 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1367 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1368 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1369 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1370 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1371 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1372 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1373 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1374 (set_attr "length" "8,8,8,8,8,8,8,8")])
1376 ;; Conditional Branches
1378 (define_expand "cbranchdi4"
1380 (if_then_else (match_operator 0 "ordered_comparison_operator"
1381 [(match_operand:DI 1 "reg_or_0_operand" "")
1382 (match_operand:DI 2 "register_operand" "")])
1383 (label_ref (match_operand 3 "" ""))
1388 (define_expand "cbranchsi4"
1390 (if_then_else (match_operator 0 "ordered_comparison_operator"
1391 [(match_operand:SI 1 "reg_or_0_operand" "")
1392 (match_operand:SI 2 "arith5_operand" "")])
1393 (label_ref (match_operand 3 "" ""))
1398 (define_expand "cbranchsf4"
1400 (if_then_else (match_operator 0 "comparison_operator"
1401 [(match_operand:SF 1 "reg_or_0_operand" "")
1402 (match_operand:SF 2 "reg_or_0_operand" "")])
1403 (label_ref (match_operand 3 "" ""))
1408 pa_emit_bcond_fp (operands);
1413 (define_expand "cbranchdf4"
1415 (if_then_else (match_operator 0 "comparison_operator"
1416 [(match_operand:DF 1 "reg_or_0_operand" "")
1417 (match_operand:DF 2 "reg_or_0_operand" "")])
1418 (label_ref (match_operand 3 "" ""))
1423 pa_emit_bcond_fp (operands);
1427 ;; Match the branch patterns.
1430 ;; Note a long backward conditional branch with an annulled delay slot
1431 ;; has a length of 12.
1435 (match_operator 3 "comparison_operator"
1436 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1437 (match_operand:SI 2 "arith5_operand" "rL")])
1438 (label_ref (match_operand 0 "" ""))
1443 return pa_output_cbranch (operands, 0, insn);
1445 [(set_attr "type" "cbranch")
1446 (set (attr "length")
1447 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1448 (const_int MAX_12BIT_OFFSET))
1450 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1451 (const_int MAX_17BIT_OFFSET))
1453 (match_test "TARGET_PORTABLE_RUNTIME")
1455 (not (match_test "flag_pic"))
1459 ;; Match the negated branch.
1464 (match_operator 3 "comparison_operator"
1465 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1466 (match_operand:SI 2 "arith5_operand" "rL")])
1468 (label_ref (match_operand 0 "" ""))))]
1472 return pa_output_cbranch (operands, 1, insn);
1474 [(set_attr "type" "cbranch")
1475 (set (attr "length")
1476 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1477 (const_int MAX_12BIT_OFFSET))
1479 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1480 (const_int MAX_17BIT_OFFSET))
1482 (match_test "TARGET_PORTABLE_RUNTIME")
1484 (not (match_test "flag_pic"))
1491 (match_operator 3 "comparison_operator"
1492 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1493 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1494 (label_ref (match_operand 0 "" ""))
1499 return pa_output_cbranch (operands, 0, insn);
1501 [(set_attr "type" "cbranch")
1502 (set (attr "length")
1503 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1504 (const_int MAX_12BIT_OFFSET))
1506 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1507 (const_int MAX_17BIT_OFFSET))
1509 (match_test "TARGET_PORTABLE_RUNTIME")
1511 (not (match_test "flag_pic"))
1515 ;; Match the negated branch.
1520 (match_operator 3 "comparison_operator"
1521 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1522 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1524 (label_ref (match_operand 0 "" ""))))]
1528 return pa_output_cbranch (operands, 1, insn);
1530 [(set_attr "type" "cbranch")
1531 (set (attr "length")
1532 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1533 (const_int MAX_12BIT_OFFSET))
1535 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1536 (const_int MAX_17BIT_OFFSET))
1538 (match_test "TARGET_PORTABLE_RUNTIME")
1540 (not (match_test "flag_pic"))
1546 (match_operator 3 "cmpib_comparison_operator"
1547 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1548 (match_operand:DI 2 "arith5_operand" "rL")])
1549 (label_ref (match_operand 0 "" ""))
1554 return pa_output_cbranch (operands, 0, insn);
1556 [(set_attr "type" "cbranch")
1557 (set (attr "length")
1558 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1559 (const_int MAX_12BIT_OFFSET))
1561 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1562 (const_int MAX_17BIT_OFFSET))
1564 (match_test "TARGET_PORTABLE_RUNTIME")
1566 (not (match_test "flag_pic"))
1570 ;; Match the negated branch.
1575 (match_operator 3 "cmpib_comparison_operator"
1576 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1577 (match_operand:DI 2 "arith5_operand" "rL")])
1579 (label_ref (match_operand 0 "" ""))))]
1583 return pa_output_cbranch (operands, 1, insn);
1585 [(set_attr "type" "cbranch")
1586 (set (attr "length")
1587 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1588 (const_int MAX_12BIT_OFFSET))
1590 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1591 (const_int MAX_17BIT_OFFSET))
1593 (match_test "TARGET_PORTABLE_RUNTIME")
1595 (not (match_test "flag_pic"))
1599 ;; Branch on Bit patterns.
1603 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1605 (match_operand:SI 1 "uint5_operand" ""))
1607 (label_ref (match_operand 2 "" ""))
1612 return pa_output_bb (operands, 0, insn, 0);
1614 [(set_attr "type" "cbranch")
1615 (set (attr "length")
1616 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1617 (const_int MAX_12BIT_OFFSET))
1619 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1620 (const_int MAX_17BIT_OFFSET))
1622 (match_test "TARGET_PORTABLE_RUNTIME")
1624 (not (match_test "flag_pic"))
1631 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1633 (match_operand:DI 1 "uint32_operand" ""))
1635 (label_ref (match_operand 2 "" ""))
1640 return pa_output_bb (operands, 0, insn, 0);
1642 [(set_attr "type" "cbranch")
1643 (set (attr "length")
1644 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1645 (const_int MAX_12BIT_OFFSET))
1647 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1648 (const_int MAX_17BIT_OFFSET))
1650 (match_test "TARGET_PORTABLE_RUNTIME")
1652 (not (match_test "flag_pic"))
1659 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1661 (match_operand:SI 1 "uint5_operand" ""))
1664 (label_ref (match_operand 2 "" ""))))]
1668 return pa_output_bb (operands, 1, insn, 0);
1670 [(set_attr "type" "cbranch")
1671 (set (attr "length")
1672 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1673 (const_int MAX_12BIT_OFFSET))
1675 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1676 (const_int MAX_17BIT_OFFSET))
1678 (match_test "TARGET_PORTABLE_RUNTIME")
1680 (not (match_test "flag_pic"))
1687 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1689 (match_operand:DI 1 "uint32_operand" ""))
1692 (label_ref (match_operand 2 "" ""))))]
1696 return pa_output_bb (operands, 1, insn, 0);
1698 [(set_attr "type" "cbranch")
1699 (set (attr "length")
1700 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1701 (const_int MAX_12BIT_OFFSET))
1703 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1704 (const_int MAX_17BIT_OFFSET))
1706 (match_test "TARGET_PORTABLE_RUNTIME")
1708 (not (match_test "flag_pic"))
1715 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1717 (match_operand:SI 1 "uint5_operand" ""))
1719 (label_ref (match_operand 2 "" ""))
1724 return pa_output_bb (operands, 0, insn, 1);
1726 [(set_attr "type" "cbranch")
1727 (set (attr "length")
1728 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1729 (const_int MAX_12BIT_OFFSET))
1731 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1732 (const_int MAX_17BIT_OFFSET))
1734 (match_test "TARGET_PORTABLE_RUNTIME")
1736 (not (match_test "flag_pic"))
1743 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1745 (match_operand:DI 1 "uint32_operand" ""))
1747 (label_ref (match_operand 2 "" ""))
1752 return pa_output_bb (operands, 0, insn, 1);
1754 [(set_attr "type" "cbranch")
1755 (set (attr "length")
1756 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1757 (const_int MAX_12BIT_OFFSET))
1759 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1760 (const_int MAX_17BIT_OFFSET))
1762 (match_test "TARGET_PORTABLE_RUNTIME")
1764 (not (match_test "flag_pic"))
1771 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1773 (match_operand:SI 1 "uint5_operand" ""))
1776 (label_ref (match_operand 2 "" ""))))]
1780 return pa_output_bb (operands, 1, insn, 1);
1782 [(set_attr "type" "cbranch")
1783 (set (attr "length")
1784 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1785 (const_int MAX_12BIT_OFFSET))
1787 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1788 (const_int MAX_17BIT_OFFSET))
1790 (match_test "TARGET_PORTABLE_RUNTIME")
1792 (not (match_test "flag_pic"))
1799 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1801 (match_operand:DI 1 "uint32_operand" ""))
1804 (label_ref (match_operand 2 "" ""))))]
1808 return pa_output_bb (operands, 1, insn, 1);
1810 [(set_attr "type" "cbranch")
1811 (set (attr "length")
1812 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1813 (const_int MAX_12BIT_OFFSET))
1815 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1816 (const_int MAX_17BIT_OFFSET))
1818 (match_test "TARGET_PORTABLE_RUNTIME")
1820 (not (match_test "flag_pic"))
1824 ;; Branch on Variable Bit patterns.
1828 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1830 (match_operand:SI 1 "register_operand" "q"))
1832 (label_ref (match_operand 2 "" ""))
1837 return pa_output_bvb (operands, 0, insn, 0);
1839 [(set_attr "type" "cbranch")
1840 (set (attr "length")
1841 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1842 (const_int MAX_12BIT_OFFSET))
1844 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1845 (const_int MAX_17BIT_OFFSET))
1847 (match_test "TARGET_PORTABLE_RUNTIME")
1849 (not (match_test "flag_pic"))
1856 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1858 (match_operand:DI 1 "register_operand" "q"))
1860 (label_ref (match_operand 2 "" ""))
1865 return pa_output_bvb (operands, 0, insn, 0);
1867 [(set_attr "type" "cbranch")
1868 (set (attr "length")
1869 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1870 (const_int MAX_12BIT_OFFSET))
1872 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1873 (const_int MAX_17BIT_OFFSET))
1875 (match_test "TARGET_PORTABLE_RUNTIME")
1877 (not (match_test "flag_pic"))
1884 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1886 (match_operand:SI 1 "register_operand" "q"))
1889 (label_ref (match_operand 2 "" ""))))]
1893 return pa_output_bvb (operands, 1, insn, 0);
1895 [(set_attr "type" "cbranch")
1896 (set (attr "length")
1897 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1898 (const_int MAX_12BIT_OFFSET))
1900 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1901 (const_int MAX_17BIT_OFFSET))
1903 (match_test "TARGET_PORTABLE_RUNTIME")
1905 (not (match_test "flag_pic"))
1912 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1914 (match_operand:DI 1 "register_operand" "q"))
1917 (label_ref (match_operand 2 "" ""))))]
1921 return pa_output_bvb (operands, 1, insn, 0);
1923 [(set_attr "type" "cbranch")
1924 (set (attr "length")
1925 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1926 (const_int MAX_12BIT_OFFSET))
1928 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1929 (const_int MAX_17BIT_OFFSET))
1931 (match_test "TARGET_PORTABLE_RUNTIME")
1933 (not (match_test "flag_pic"))
1940 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1942 (match_operand:SI 1 "register_operand" "q"))
1944 (label_ref (match_operand 2 "" ""))
1949 return pa_output_bvb (operands, 0, insn, 1);
1951 [(set_attr "type" "cbranch")
1952 (set (attr "length")
1953 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1954 (const_int MAX_12BIT_OFFSET))
1956 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1957 (const_int MAX_17BIT_OFFSET))
1959 (match_test "TARGET_PORTABLE_RUNTIME")
1961 (not (match_test "flag_pic"))
1968 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1970 (match_operand:DI 1 "register_operand" "q"))
1972 (label_ref (match_operand 2 "" ""))
1977 return pa_output_bvb (operands, 0, insn, 1);
1979 [(set_attr "type" "cbranch")
1980 (set (attr "length")
1981 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1982 (const_int MAX_12BIT_OFFSET))
1984 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1985 (const_int MAX_17BIT_OFFSET))
1987 (match_test "TARGET_PORTABLE_RUNTIME")
1989 (not (match_test "flag_pic"))
1996 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1998 (match_operand:SI 1 "register_operand" "q"))
2001 (label_ref (match_operand 2 "" ""))))]
2005 return pa_output_bvb (operands, 1, insn, 1);
2007 [(set_attr "type" "cbranch")
2008 (set (attr "length")
2009 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2010 (const_int MAX_12BIT_OFFSET))
2012 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2013 (const_int MAX_17BIT_OFFSET))
2015 (match_test "TARGET_PORTABLE_RUNTIME")
2017 (not (match_test "flag_pic"))
2024 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2026 (match_operand:DI 1 "register_operand" "q"))
2029 (label_ref (match_operand 2 "" ""))))]
2033 return pa_output_bvb (operands, 1, insn, 1);
2035 [(set_attr "type" "cbranch")
2036 (set (attr "length")
2037 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2038 (const_int MAX_12BIT_OFFSET))
2040 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2041 (const_int MAX_17BIT_OFFSET))
2043 (match_test "TARGET_PORTABLE_RUNTIME")
2045 (not (match_test "flag_pic"))
2049 ;; Floating point branches
2051 ;; ??? Nullification is handled differently from other branches.
2052 ;; If nullification is specified, the delay slot is nullified on any
2053 ;; taken branch regardless of branch direction.
2055 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2056 (label_ref (match_operand 0 "" ""))
2058 "!TARGET_SOFT_FLOAT"
2061 int length = get_attr_length (insn);
2063 int nullify, xdelay;
2066 return \"ftest\;b%* %l0\";
2068 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2072 xoperands[0] = GEN_INT (length - 8);
2078 xoperands[0] = GEN_INT (length - 4);
2082 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b,n .+%0\", xoperands);
2084 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b .+%0\", xoperands);
2085 return pa_output_lbranch (operands[0], insn, xdelay);
2087 [(set_attr "type" "fbranch")
2088 (set (attr "length")
2089 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2090 (const_int MAX_17BIT_OFFSET))
2092 (match_test "TARGET_PORTABLE_RUNTIME")
2094 (not (match_test "flag_pic"))
2099 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2101 (label_ref (match_operand 0 "" ""))))]
2102 "!TARGET_SOFT_FLOAT"
2105 int length = get_attr_length (insn);
2107 int nullify, xdelay;
2110 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2112 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2116 xoperands[0] = GEN_INT (length - 4);
2122 xoperands[0] = GEN_INT (length);
2126 output_asm_insn (\"ftest\;b,n .+%0\", xoperands);
2128 output_asm_insn (\"ftest\;b .+%0\", xoperands);
2129 return pa_output_lbranch (operands[0], insn, xdelay);
2131 [(set_attr "type" "fbranch")
2132 (set (attr "length")
2133 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2134 (const_int MAX_17BIT_OFFSET))
2136 (match_test "TARGET_PORTABLE_RUNTIME")
2138 (not (match_test "flag_pic"))
2142 ;; Move instructions
2144 (define_expand "movsi"
2145 [(set (match_operand:SI 0 "general_operand" "")
2146 (match_operand:SI 1 "general_operand" ""))]
2150 if (pa_emit_move_sequence (operands, SImode, 0))
2154 ;; Handle SImode input reloads requiring %r1 as a scratch register.
2155 (define_expand "reload_insi_r1"
2156 [(set (match_operand:SI 0 "register_operand" "=Z")
2157 (match_operand:SI 1 "non_hard_reg_operand" ""))
2158 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
2162 if (pa_emit_move_sequence (operands, SImode, operands[2]))
2165 /* We don't want the clobber emitted, so handle this ourselves. */
2166 emit_insn (gen_rtx_SET (operands[0], operands[1]));
2170 ;; Handle SImode input reloads requiring a general register as a
2171 ;; scratch register.
2172 (define_expand "reload_insi"
2173 [(set (match_operand:SI 0 "register_operand" "=Z")
2174 (match_operand:SI 1 "non_hard_reg_operand" ""))
2175 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2179 if (pa_emit_move_sequence (operands, SImode, operands[2]))
2182 /* We don't want the clobber emitted, so handle this ourselves. */
2183 emit_insn (gen_rtx_SET (operands[0], operands[1]));
2187 ;; Handle SImode output reloads requiring a general register as a
2188 ;; scratch register.
2189 (define_expand "reload_outsi"
2190 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2191 (match_operand:SI 1 "register_operand" "Z"))
2192 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2196 if (pa_emit_move_sequence (operands, SImode, operands[2]))
2199 /* We don't want the clobber emitted, so handle this ourselves. */
2200 emit_insn (gen_rtx_SET (operands[0], operands[1]));
2205 [(set (match_operand:SI 0 "move_dest_operand"
2206 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f")
2207 (match_operand:SI 1 "move_src_operand"
2208 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))]
2209 "(register_operand (operands[0], SImode)
2210 || reg_or_0_operand (operands[1], SImode))
2211 && !TARGET_SOFT_FLOAT
2218 {zdepi|depwi,z} %Z1,%0
2222 {mfctl|mfctl,w} %%sar,%0
2226 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
2227 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
2228 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,fpstore_load,store_fpload")
2229 (set_attr "pa_combine_type" "addmove")
2230 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")])
2233 [(set (match_operand:SI 0 "move_dest_operand"
2234 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
2235 (match_operand:SI 1 "move_src_operand"
2236 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
2237 "(register_operand (operands[0], SImode)
2238 || reg_or_0_operand (operands[1], SImode))
2239 && !TARGET_SOFT_FLOAT
2246 {zdepi|depwi,z} %Z1,%0
2250 {mfctl|mfctl,w} %%sar,%0
2254 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
2255 (set_attr "pa_combine_type" "addmove")
2256 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
2259 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2260 (match_operand:SI 1 "register_operand" "f"))]
2262 && !TARGET_DISABLE_INDEXING
2263 && reload_completed"
2265 [(set_attr "type" "fpstore")
2266 (set_attr "pa_combine_type" "addmove")
2267 (set_attr "length" "4")])
2269 ; Rewrite RTL using an indexed store. This will allow the insn that
2270 ; computes the address to be deleted if the register it sets is dead.
2272 [(set (match_operand:SI 0 "register_operand" "")
2273 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2275 (match_operand:SI 2 "register_operand" "")))
2276 (set (mem:SI (match_dup 0))
2277 (match_operand:SI 3 "register_operand" ""))]
2279 && !TARGET_DISABLE_INDEXING
2280 && REG_OK_FOR_BASE_P (operands[2])
2281 && FP_REGNO_P (REGNO (operands[3]))"
2282 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2284 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2289 [(set (match_operand:SI 0 "register_operand" "")
2290 (plus:SI (match_operand:SI 2 "register_operand" "")
2291 (mult:SI (match_operand:SI 1 "register_operand" "")
2293 (set (mem:SI (match_dup 0))
2294 (match_operand:SI 3 "register_operand" ""))]
2296 && !TARGET_DISABLE_INDEXING
2297 && REG_OK_FOR_BASE_P (operands[2])
2298 && FP_REGNO_P (REGNO (operands[3]))"
2299 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2301 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2306 [(set (match_operand:DI 0 "register_operand" "")
2307 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2309 (match_operand:DI 2 "register_operand" "")))
2310 (set (mem:SI (match_dup 0))
2311 (match_operand:SI 3 "register_operand" ""))]
2313 && !TARGET_DISABLE_INDEXING
2315 && REG_OK_FOR_BASE_P (operands[2])
2316 && FP_REGNO_P (REGNO (operands[3]))"
2317 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2319 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2324 [(set (match_operand:DI 0 "register_operand" "")
2325 (plus:DI (match_operand:DI 2 "register_operand" "")
2326 (mult:DI (match_operand:DI 1 "register_operand" "")
2328 (set (mem:SI (match_dup 0))
2329 (match_operand:SI 3 "register_operand" ""))]
2331 && !TARGET_DISABLE_INDEXING
2333 && REG_OK_FOR_BASE_P (operands[2])
2334 && FP_REGNO_P (REGNO (operands[3]))"
2335 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2337 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2342 [(set (match_operand:SI 0 "register_operand" "")
2343 (plus:SI (match_operand:SI 1 "register_operand" "")
2344 (match_operand:SI 2 "register_operand" "")))
2345 (set (mem:SI (match_dup 0))
2346 (match_operand:SI 3 "register_operand" ""))]
2348 && !TARGET_DISABLE_INDEXING
2349 && TARGET_NO_SPACE_REGS
2350 && REG_OK_FOR_INDEX_P (operands[1])
2351 && REG_OK_FOR_BASE_P (operands[2])
2352 && FP_REGNO_P (REGNO (operands[3]))"
2353 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2355 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2359 [(set (match_operand:SI 0 "register_operand" "")
2360 (plus:SI (match_operand:SI 1 "register_operand" "")
2361 (match_operand:SI 2 "register_operand" "")))
2362 (set (mem:SI (match_dup 0))
2363 (match_operand:SI 3 "register_operand" ""))]
2365 && !TARGET_DISABLE_INDEXING
2366 && TARGET_NO_SPACE_REGS
2367 && REG_OK_FOR_BASE_P (operands[1])
2368 && REG_OK_FOR_INDEX_P (operands[2])
2369 && FP_REGNO_P (REGNO (operands[3]))"
2370 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2372 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2376 [(set (match_operand:DI 0 "register_operand" "")
2377 (plus:DI (match_operand:DI 1 "register_operand" "")
2378 (match_operand:DI 2 "register_operand" "")))
2379 (set (mem:SI (match_dup 0))
2380 (match_operand:SI 3 "register_operand" ""))]
2382 && !TARGET_DISABLE_INDEXING
2384 && TARGET_NO_SPACE_REGS
2385 && REG_OK_FOR_INDEX_P (operands[1])
2386 && REG_OK_FOR_BASE_P (operands[2])
2387 && FP_REGNO_P (REGNO (operands[3]))"
2388 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2390 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2394 [(set (match_operand:DI 0 "register_operand" "")
2395 (plus:DI (match_operand:DI 1 "register_operand" "")
2396 (match_operand:DI 2 "register_operand" "")))
2397 (set (mem:SI (match_dup 0))
2398 (match_operand:SI 3 "register_operand" ""))]
2400 && !TARGET_DISABLE_INDEXING
2402 && TARGET_NO_SPACE_REGS
2403 && REG_OK_FOR_BASE_P (operands[1])
2404 && REG_OK_FOR_INDEX_P (operands[2])
2405 && FP_REGNO_P (REGNO (operands[3]))"
2406 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2408 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2412 [(set (match_operand:SI 0 "move_dest_operand"
2413 "=r,r,r,r,r,r,Q,!*q,!r")
2414 (match_operand:SI 1 "move_src_operand"
2415 "A,r,J,N,K,RQ,rM,!rM,!*q"))]
2416 "(register_operand (operands[0], SImode)
2417 || reg_or_0_operand (operands[1], SImode))
2418 && TARGET_SOFT_FLOAT"
2424 {zdepi|depwi,z} %Z1,%0
2428 {mfctl|mfctl,w} %%sar,%0"
2429 [(set_attr "type" "load,move,move,move,move,load,store,move,move")
2430 (set_attr "pa_combine_type" "addmove")
2431 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2433 ;; Load or store with base-register modification.
2435 [(set (match_operand:SI 0 "register_operand" "=r")
2436 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2437 (match_operand:DI 2 "int5_operand" "L"))))
2439 (plus:DI (match_dup 1) (match_dup 2)))]
2442 [(set_attr "type" "load")
2443 (set_attr "length" "4")])
2445 ; And a zero extended variant.
2447 [(set (match_operand:DI 0 "register_operand" "=r")
2448 (zero_extend:DI (mem:SI
2450 (match_operand:DI 1 "register_operand" "+r")
2451 (match_operand:DI 2 "int5_operand" "L")))))
2453 (plus:DI (match_dup 1) (match_dup 2)))]
2456 [(set_attr "type" "load")
2457 (set_attr "length" "4")])
2459 (define_expand "pre_load"
2460 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2461 (mem (plus (match_operand 1 "register_operand" "")
2462 (match_operand 2 "pre_cint_operand" ""))))
2464 (plus (match_dup 1) (match_dup 2)))])]
2470 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2473 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2477 (define_insn "pre_ldw"
2478 [(set (match_operand:SI 0 "register_operand" "=r")
2479 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2480 (match_operand:SI 2 "pre_cint_operand" ""))))
2482 (plus:SI (match_dup 1) (match_dup 2)))]
2486 if (INTVAL (operands[2]) < 0)
2487 return \"{ldwm|ldw,mb} %2(%1),%0\";
2488 return \"{ldws|ldw},mb %2(%1),%0\";
2490 [(set_attr "type" "load")
2491 (set_attr "length" "4")])
2493 (define_insn "pre_ldd"
2494 [(set (match_operand:DI 0 "register_operand" "=r")
2495 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2496 (match_operand:DI 2 "pre_cint_operand" ""))))
2498 (plus:DI (match_dup 1) (match_dup 2)))]
2501 [(set_attr "type" "load")
2502 (set_attr "length" "4")])
2505 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2506 (match_operand:SI 1 "pre_cint_operand" "")))
2507 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2509 (plus:SI (match_dup 0) (match_dup 1)))]
2513 if (INTVAL (operands[1]) < 0)
2514 return \"{stwm|stw,mb} %r2,%1(%0)\";
2515 return \"{stws|stw},mb %r2,%1(%0)\";
2517 [(set_attr "type" "store")
2518 (set_attr "length" "4")])
2521 [(set (match_operand:SI 0 "register_operand" "=r")
2522 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2524 (plus:SI (match_dup 1)
2525 (match_operand:SI 2 "post_cint_operand" "")))]
2529 if (INTVAL (operands[2]) > 0)
2530 return \"{ldwm|ldw,ma} %2(%1),%0\";
2531 return \"{ldws|ldw},ma %2(%1),%0\";
2533 [(set_attr "type" "load")
2534 (set_attr "length" "4")])
2536 (define_expand "post_store"
2537 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2538 (match_operand 1 "reg_or_0_operand" ""))
2541 (match_operand 2 "post_cint_operand" "")))])]
2547 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2550 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2554 (define_insn "post_stw"
2555 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2556 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2558 (plus:SI (match_dup 0)
2559 (match_operand:SI 2 "post_cint_operand" "")))]
2563 if (INTVAL (operands[2]) > 0)
2564 return \"{stwm|stw,ma} %r1,%2(%0)\";
2565 return \"{stws|stw},ma %r1,%2(%0)\";
2567 [(set_attr "type" "store")
2568 (set_attr "length" "4")])
2570 (define_insn "post_std"
2571 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2572 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2574 (plus:DI (match_dup 0)
2575 (match_operand:DI 2 "post_cint_operand" "")))]
2578 [(set_attr "type" "store")
2579 (set_attr "length" "4")])
2581 ;; For loading the address of a label while generating PIC code.
2582 ;; Note since this pattern can be created at reload time (via movsi), all
2583 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2585 [(set (match_operand 0 "pmode_register_operand" "=a")
2586 (match_operand 1 "pic_label_operand" ""))]
2592 xoperands[0] = operands[0];
2593 xoperands[1] = operands[1];
2594 xoperands[2] = gen_label_rtx ();
2596 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2597 CODE_LABEL_NUMBER (xoperands[2]));
2598 output_asm_insn (\"mfia %0\", xoperands);
2600 /* If we're trying to load the address of a label that happens to be
2601 close, then we can use a shorter sequence. */
2602 if (GET_CODE (operands[1]) == LABEL_REF
2603 && !LABEL_REF_NONLOCAL_P (operands[1])
2604 && INSN_ADDRESSES_SET_P ()
2605 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2606 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2607 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2610 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2611 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2615 [(set_attr "type" "multi")
2616 (set_attr "length" "12")]) ; 8 or 12
2619 [(set (match_operand 0 "pmode_register_operand" "=a")
2620 (match_operand 1 "pic_label_operand" ""))]
2626 xoperands[0] = operands[0];
2627 xoperands[1] = operands[1];
2628 xoperands[2] = gen_label_rtx ();
2630 output_asm_insn (\"bl .+8,%0\", xoperands);
2631 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2632 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2633 CODE_LABEL_NUMBER (xoperands[2]));
2635 /* If we're trying to load the address of a label that happens to be
2636 close, then we can use a shorter sequence. */
2637 if (GET_CODE (operands[1]) == LABEL_REF
2638 && !LABEL_REF_NONLOCAL_P (operands[1])
2639 && INSN_ADDRESSES_SET_P ()
2640 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2641 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2642 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2645 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2646 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2650 [(set_attr "type" "multi")
2651 (set_attr "length" "16")]) ; 12 or 16
2654 [(set (match_operand:SI 0 "register_operand" "=a")
2655 (plus:SI (match_operand:SI 1 "register_operand" "r")
2656 (high:SI (match_operand 2 "" ""))))]
2657 "symbolic_operand (operands[2], Pmode)
2658 && ! function_label_operand (operands[2], Pmode)
2661 [(set_attr "type" "binary")
2662 (set_attr "length" "4")])
2665 [(set (match_operand:DI 0 "register_operand" "=a")
2666 (plus:DI (match_operand:DI 1 "register_operand" "r")
2667 (high:DI (match_operand 2 "" ""))))]
2668 "symbolic_operand (operands[2], Pmode)
2669 && ! function_label_operand (operands[2], Pmode)
2673 [(set_attr "type" "binary")
2674 (set_attr "length" "4")])
2677 [(set (match_operand:SI 0 "register_operand" "=r")
2678 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2679 (unspec:SI [(match_operand 2 "" "")] UNSPEC_DLTIND14R)))]
2680 "symbolic_operand (operands[2], Pmode)
2681 && ! function_label_operand (operands[2], Pmode)
2684 [(set_attr "type" "binary")
2685 (set_attr "length" "4")])
2688 [(set (match_operand:DI 0 "register_operand" "=r")
2689 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2690 (unspec:DI [(match_operand 2 "" "")] UNSPEC_DLTIND14R)))]
2691 "symbolic_operand (operands[2], Pmode)
2692 && ! function_label_operand (operands[2], Pmode)
2696 [(set_attr "type" "binary")
2697 (set_attr "length" "4")])
2699 ;; Always use addil rather than ldil;add sequences. This allows the
2700 ;; HP linker to eliminate the dp relocation if the symbolic operand
2701 ;; lives in the TEXT space.
2703 [(set (match_operand:SI 0 "register_operand" "=a")
2704 (high:SI (match_operand 1 "" "")))]
2705 "symbolic_operand (operands[1], Pmode)
2706 && ! function_label_operand (operands[1], Pmode)
2707 && ! read_only_operand (operands[1], Pmode)
2711 if (TARGET_LONG_LOAD_STORE)
2712 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2714 return \"addil LR'%H1,%%r27\";
2716 [(set_attr "type" "binary")
2717 (set (attr "length")
2718 (if_then_else (not (match_test "TARGET_LONG_LOAD_STORE"))
2723 ;; This is for use in the prologue/epilogue code. We need it
2724 ;; to add large constants to a stack pointer or frame pointer.
2725 ;; Because of the additional %r1 pressure, we probably do not
2726 ;; want to use this in general code, so make it available
2727 ;; only after reload.
2729 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2730 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2731 (high:SI (match_operand 2 "const_int_operand" ""))))]
2735 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2736 [(set_attr "type" "binary,binary")
2737 (set_attr "length" "4,8")])
2740 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2741 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2742 (high:DI (match_operand 2 "const_int_operand" ""))))]
2743 "reload_completed && TARGET_64BIT"
2746 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2747 [(set_attr "type" "binary,binary")
2748 (set_attr "length" "4,8")])
2751 [(set (match_operand:SI 0 "register_operand" "=r")
2752 (high:SI (match_operand 1 "" "")))]
2753 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2754 && !pa_is_function_label_plus_const (operands[1])"
2757 if (symbolic_operand (operands[1], Pmode))
2758 return \"ldil LR'%H1,%0\";
2760 return \"ldil L'%G1,%0\";
2762 [(set_attr "type" "move")
2763 (set_attr "length" "4")])
2766 [(set (match_operand:DI 0 "register_operand" "=r")
2767 (high:DI (match_operand 1 "const_int_operand" "")))]
2770 [(set_attr "type" "move")
2771 (set_attr "length" "4")])
2774 [(set (match_operand:DI 0 "register_operand" "=r")
2775 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2776 (match_operand:DI 2 "const_int_operand" "i")))]
2779 [(set_attr "type" "move")
2780 (set_attr "length" "4")])
2783 [(set (match_operand:SI 0 "register_operand" "=r")
2784 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2785 (match_operand:SI 2 "immediate_operand" "i")))]
2786 "!pa_is_function_label_plus_const (operands[2])"
2789 gcc_assert (!flag_pic || !symbolic_operand (operands[2], Pmode));
2791 if (symbolic_operand (operands[2], Pmode))
2792 return \"ldo RR'%G2(%1),%0\";
2794 return \"ldo R'%G2(%1),%0\";
2796 [(set_attr "type" "move")
2797 (set_attr "length" "4")])
2799 ;; Now that a symbolic_address plus a constant is broken up early
2800 ;; in the compilation phase (for better CSE) we need a special
2801 ;; combiner pattern to load the symbolic address plus the constant
2802 ;; in only 2 instructions. (For cases where the symbolic address
2803 ;; was not a common subexpression.)
2805 [(set (match_operand:SI 0 "register_operand" "")
2806 (match_operand:SI 1 "symbolic_operand" ""))
2807 (clobber (match_operand:SI 2 "register_operand" ""))]
2808 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2809 [(set (match_dup 2) (high:SI (match_dup 1)))
2810 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2813 ;; hppa_legitimize_address goes to a great deal of trouble to
2814 ;; create addresses which use indexing. In some cases, this
2815 ;; is a lose because there isn't any store instructions which
2816 ;; allow indexed addresses (with integer register source).
2818 ;; These define_splits try to turn a 3 insn store into
2819 ;; a 2 insn store with some creative RTL rewriting.
2821 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2822 (match_operand:SI 1 "shadd_operand" ""))
2823 (plus:SI (match_operand:SI 2 "register_operand" "")
2824 (match_operand:SI 3 "const_int_operand" ""))))
2825 (match_operand:SI 4 "register_operand" ""))
2826 (clobber (match_operand:SI 5 "register_operand" ""))]
2828 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2830 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2834 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2835 (match_operand:SI 1 "shadd_operand" ""))
2836 (plus:SI (match_operand:SI 2 "register_operand" "")
2837 (match_operand:SI 3 "const_int_operand" ""))))
2838 (match_operand:HI 4 "register_operand" ""))
2839 (clobber (match_operand:SI 5 "register_operand" ""))]
2841 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2843 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2847 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2848 (match_operand:SI 1 "shadd_operand" ""))
2849 (plus:SI (match_operand:SI 2 "register_operand" "")
2850 (match_operand:SI 3 "const_int_operand" ""))))
2851 (match_operand:QI 4 "register_operand" ""))
2852 (clobber (match_operand:SI 5 "register_operand" ""))]
2854 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2856 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2859 (define_expand "movhi"
2860 [(set (match_operand:HI 0 "general_operand" "")
2861 (match_operand:HI 1 "general_operand" ""))]
2865 if (pa_emit_move_sequence (operands, HImode, 0))
2869 ;; Handle HImode input reloads requiring a general register as a
2870 ;; scratch register.
2871 (define_expand "reload_inhi"
2872 [(set (match_operand:HI 0 "register_operand" "=Z")
2873 (match_operand:HI 1 "non_hard_reg_operand" ""))
2874 (clobber (match_operand:HI 2 "register_operand" "=&r"))]
2878 if (pa_emit_move_sequence (operands, HImode, operands[2]))
2881 /* We don't want the clobber emitted, so handle this ourselves. */
2882 emit_insn (gen_rtx_SET (operands[0], operands[1]));
2886 ;; Handle HImode output reloads requiring a general register as a
2887 ;; scratch register.
2888 (define_expand "reload_outhi"
2889 [(set (match_operand:HI 0 "non_hard_reg_operand" "")
2890 (match_operand:HI 1 "register_operand" "Z"))
2891 (clobber (match_operand:HI 2 "register_operand" "=&r"))]
2895 if (pa_emit_move_sequence (operands, HImode, operands[2]))
2898 /* We don't want the clobber emitted, so handle this ourselves. */
2899 emit_insn (gen_rtx_SET (operands[0], operands[1]));
2904 [(set (match_operand:HI 0 "move_dest_operand"
2905 "=r,r,r,r,r,Q,!*q,!r")
2906 (match_operand:HI 1 "move_src_operand"
2907 "r,J,N,K,RQ,rM,!rM,!*q"))]
2908 "(register_operand (operands[0], HImode)
2909 || reg_or_0_operand (operands[1], HImode))"
2914 {zdepi|depwi,z} %Z1,%0
2918 {mfctl|mfctl,w} %sar,%0"
2919 [(set_attr "type" "move,move,move,shift,load,store,move,move")
2920 (set_attr "pa_combine_type" "addmove")
2921 (set_attr "length" "4,4,4,4,4,4,4,4")])
2924 [(set (match_operand:HI 0 "register_operand" "=r")
2925 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2926 (match_operand:SI 2 "int5_operand" "L"))))
2928 (plus:SI (match_dup 1) (match_dup 2)))]
2930 "{ldhs|ldh},mb %2(%1),%0"
2931 [(set_attr "type" "load")
2932 (set_attr "length" "4")])
2935 [(set (match_operand:HI 0 "register_operand" "=r")
2936 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2937 (match_operand:DI 2 "int5_operand" "L"))))
2939 (plus:DI (match_dup 1) (match_dup 2)))]
2942 [(set_attr "type" "load")
2943 (set_attr "length" "4")])
2945 ; And a zero extended variant.
2947 [(set (match_operand:DI 0 "register_operand" "=r")
2948 (zero_extend:DI (mem:HI
2950 (match_operand:DI 1 "register_operand" "+r")
2951 (match_operand:DI 2 "int5_operand" "L")))))
2953 (plus:DI (match_dup 1) (match_dup 2)))]
2956 [(set_attr "type" "load")
2957 (set_attr "length" "4")])
2960 [(set (match_operand:SI 0 "register_operand" "=r")
2961 (zero_extend:SI (mem:HI
2963 (match_operand:SI 1 "register_operand" "+r")
2964 (match_operand:SI 2 "int5_operand" "L")))))
2966 (plus:SI (match_dup 1) (match_dup 2)))]
2968 "{ldhs|ldh},mb %2(%1),%0"
2969 [(set_attr "type" "load")
2970 (set_attr "length" "4")])
2973 [(set (match_operand:SI 0 "register_operand" "=r")
2974 (zero_extend:SI (mem:HI
2976 (match_operand:DI 1 "register_operand" "+r")
2977 (match_operand:DI 2 "int5_operand" "L")))))
2979 (plus:DI (match_dup 1) (match_dup 2)))]
2982 [(set_attr "type" "load")
2983 (set_attr "length" "4")])
2986 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2987 (match_operand:SI 1 "int5_operand" "L")))
2988 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2990 (plus:SI (match_dup 0) (match_dup 1)))]
2992 "{sths|sth},mb %r2,%1(%0)"
2993 [(set_attr "type" "store")
2994 (set_attr "length" "4")])
2997 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
2998 (match_operand:DI 1 "int5_operand" "L")))
2999 (match_operand:HI 2 "reg_or_0_operand" "rM"))
3001 (plus:DI (match_dup 0) (match_dup 1)))]
3004 [(set_attr "type" "store")
3005 (set_attr "length" "4")])
3007 (define_insn "addhi3"
3008 [(set (match_operand:HI 0 "register_operand" "=r,r")
3009 (plus:HI (match_operand:HI 1 "register_operand" "%r,r")
3010 (match_operand:HI 2 "arith14_operand" "r,J")))]
3013 {addl|add,l} %1,%2,%0
3015 [(set_attr "type" "binary,binary")
3016 (set_attr "pa_combine_type" "addmove")
3017 (set_attr "length" "4,4")])
3019 (define_expand "movqi"
3020 [(set (match_operand:QI 0 "general_operand" "")
3021 (match_operand:QI 1 "general_operand" ""))]
3025 if (pa_emit_move_sequence (operands, QImode, 0))
3029 ;; Handle QImode input reloads requiring a general register as a
3030 ;; scratch register.
3031 (define_expand "reload_inqi"
3032 [(set (match_operand:QI 0 "register_operand" "=Z")
3033 (match_operand:QI 1 "non_hard_reg_operand" ""))
3034 (clobber (match_operand:QI 2 "register_operand" "=&r"))]
3038 if (pa_emit_move_sequence (operands, QImode, operands[2]))
3041 /* We don't want the clobber emitted, so handle this ourselves. */
3042 emit_insn (gen_rtx_SET (operands[0], operands[1]));
3046 ;; Handle QImode output reloads requiring a general register as a
3047 ;; scratch register.
3048 (define_expand "reload_outqi"
3049 [(set (match_operand:QI 0 "non_hard_reg_operand" "")
3050 (match_operand:QI 1 "register_operand" "Z"))
3051 (clobber (match_operand:QI 2 "register_operand" "=&r"))]
3055 if (pa_emit_move_sequence (operands, QImode, operands[2]))
3058 /* We don't want the clobber emitted, so handle this ourselves. */
3059 emit_insn (gen_rtx_SET (operands[0], operands[1]));
3064 [(set (match_operand:QI 0 "move_dest_operand"
3065 "=r,r,r,r,r,Q,!*q,!r")
3066 (match_operand:QI 1 "move_src_operand"
3067 "r,J,N,K,RQ,rM,!rM,!*q"))]
3068 "(register_operand (operands[0], QImode)
3069 || reg_or_0_operand (operands[1], QImode))"
3074 {zdepi|depwi,z} %Z1,%0
3078 {mfctl|mfctl,w} %%sar,%0"
3079 [(set_attr "type" "move,move,move,shift,load,store,move,move")
3080 (set_attr "pa_combine_type" "addmove")
3081 (set_attr "length" "4,4,4,4,4,4,4,4")])
3084 [(set (match_operand:QI 0 "register_operand" "=r")
3085 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3086 (match_operand:SI 2 "int5_operand" "L"))))
3087 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3089 "{ldbs|ldb},mb %2(%1),%0"
3090 [(set_attr "type" "load")
3091 (set_attr "length" "4")])
3094 [(set (match_operand:QI 0 "register_operand" "=r")
3095 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3096 (match_operand:DI 2 "int5_operand" "L"))))
3097 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3100 [(set_attr "type" "load")
3101 (set_attr "length" "4")])
3103 ; Now the same thing with zero extensions.
3105 [(set (match_operand:DI 0 "register_operand" "=r")
3106 (zero_extend:DI (mem:QI (plus:DI
3107 (match_operand:DI 1 "register_operand" "+r")
3108 (match_operand:DI 2 "int5_operand" "L")))))
3109 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3112 [(set_attr "type" "load")
3113 (set_attr "length" "4")])
3116 [(set (match_operand:SI 0 "register_operand" "=r")
3117 (zero_extend:SI (mem:QI (plus:SI
3118 (match_operand:SI 1 "register_operand" "+r")
3119 (match_operand:SI 2 "int5_operand" "L")))))
3120 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3122 "{ldbs|ldb},mb %2(%1),%0"
3123 [(set_attr "type" "load")
3124 (set_attr "length" "4")])
3127 [(set (match_operand:SI 0 "register_operand" "=r")
3128 (zero_extend:SI (mem:QI (plus:DI
3129 (match_operand:DI 1 "register_operand" "+r")
3130 (match_operand:DI 2 "int5_operand" "L")))))
3131 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3134 [(set_attr "type" "load")
3135 (set_attr "length" "4")])
3138 [(set (match_operand:HI 0 "register_operand" "=r")
3139 (zero_extend:HI (mem:QI (plus:SI
3140 (match_operand:SI 1 "register_operand" "+r")
3141 (match_operand:SI 2 "int5_operand" "L")))))
3142 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3144 "{ldbs|ldb},mb %2(%1),%0"
3145 [(set_attr "type" "load")
3146 (set_attr "length" "4")])
3149 [(set (match_operand:HI 0 "register_operand" "=r")
3150 (zero_extend:HI (mem:QI (plus:DI
3151 (match_operand:DI 1 "register_operand" "+r")
3152 (match_operand:DI 2 "int5_operand" "L")))))
3153 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3156 [(set_attr "type" "load")
3157 (set_attr "length" "4")])
3160 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3161 (match_operand:SI 1 "int5_operand" "L")))
3162 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3164 (plus:SI (match_dup 0) (match_dup 1)))]
3166 "{stbs|stb},mb %r2,%1(%0)"
3167 [(set_attr "type" "store")
3168 (set_attr "length" "4")])
3171 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3172 (match_operand:DI 1 "int5_operand" "L")))
3173 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3175 (plus:DI (match_dup 0) (match_dup 1)))]
3178 [(set_attr "type" "store")
3179 (set_attr "length" "4")])
3181 ;; The definition of this insn does not really explain what it does,
3182 ;; but it should suffice that anything generated as this insn will be
3183 ;; recognized as a movmemsi operation, and that it will not successfully
3184 ;; combine with anything.
3185 (define_expand "movmemsi"
3186 [(parallel [(set (match_operand:BLK 0 "" "")
3187 (match_operand:BLK 1 "" ""))
3188 (clobber (match_dup 4))
3189 (clobber (match_dup 5))
3190 (clobber (match_dup 6))
3191 (clobber (match_dup 7))
3192 (clobber (match_dup 8))
3193 (use (match_operand:SI 2 "arith14_operand" ""))
3194 (use (match_operand:SI 3 "const_int_operand" ""))])]
3195 "!TARGET_64BIT && optimize > 0"
3200 /* HP provides very fast block move library routine for the PA;
3201 this routine includes:
3203 4x4 byte at a time block moves,
3204 1x4 byte at a time with alignment checked at runtime with
3205 attempts to align the source and destination as needed
3208 With that in mind, here's the heuristics to try and guess when
3209 the inlined block move will be better than the library block
3212 If the size isn't constant, then always use the library routines.
3214 If the size is large in respect to the known alignment, then use
3215 the library routines.
3217 If the size is small in respect to the known alignment, then open
3218 code the copy (since that will lead to better scheduling).
3220 Else use the block move pattern. */
3222 /* Undetermined size, use the library routine. */
3223 if (GET_CODE (operands[2]) != CONST_INT)
3226 size = INTVAL (operands[2]);
3227 align = INTVAL (operands[3]);
3228 align = align > 4 ? 4 : (align ? align : 1);
3230 /* If size/alignment is large, then use the library routines. */
3231 if (size / align > 16)
3234 /* This does happen, but not often enough to worry much about. */
3235 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3238 /* Fall through means we're going to use our block move pattern. */
3240 = replace_equiv_address (operands[0],
3241 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3243 = replace_equiv_address (operands[1],
3244 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3245 operands[4] = gen_reg_rtx (SImode);
3246 operands[5] = gen_reg_rtx (SImode);
3247 operands[6] = gen_reg_rtx (SImode);
3248 operands[7] = gen_reg_rtx (SImode);
3249 operands[8] = gen_reg_rtx (SImode);
3252 ;; The operand constraints are written like this to support both compile-time
3253 ;; and run-time determined byte counts. The expander and pa_output_block_move
3254 ;; only support compile-time determined counts at this time.
3256 ;; If the count is run-time determined, the register with the byte count
3257 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3259 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3260 ;; broke this semantic for pseudo registers. We can't use match_scratch
3261 ;; as this requires two registers in the class R1_REGS when the MEMs for
3262 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3263 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3264 ;; respectively. We then split or peephole optimize after reload.
3265 (define_insn "movmemsi_prereload"
3266 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3267 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3268 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3269 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3270 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3271 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3272 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3273 (use (match_operand:SI 4 "arith14_operand" "J,2")) ;byte count
3274 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3277 [(set_attr "type" "multi,multi")])
3280 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3281 (match_operand:BLK 1 "memory_operand" ""))
3282 (clobber (match_operand:SI 2 "register_operand" ""))
3283 (clobber (match_operand:SI 3 "register_operand" ""))
3284 (clobber (match_operand:SI 6 "register_operand" ""))
3285 (clobber (match_operand:SI 7 "register_operand" ""))
3286 (clobber (match_operand:SI 8 "register_operand" ""))
3287 (use (match_operand:SI 4 "arith14_operand" ""))
3288 (use (match_operand:SI 5 "const_int_operand" ""))])]
3289 "!TARGET_64BIT && reload_completed && !flag_peephole2
3290 && GET_CODE (operands[0]) == MEM
3291 && register_operand (XEXP (operands[0], 0), SImode)
3292 && GET_CODE (operands[1]) == MEM
3293 && register_operand (XEXP (operands[1], 0), SImode)"
3294 [(set (match_dup 7) (match_dup 9))
3295 (set (match_dup 8) (match_dup 10))
3296 (parallel [(set (match_dup 0) (match_dup 1))
3297 (clobber (match_dup 2))
3298 (clobber (match_dup 3))
3299 (clobber (match_dup 6))
3300 (clobber (match_dup 7))
3301 (clobber (match_dup 8))
3307 operands[9] = XEXP (operands[0], 0);
3308 operands[10] = XEXP (operands[1], 0);
3309 operands[0] = replace_equiv_address (operands[0], operands[7]);
3310 operands[1] = replace_equiv_address (operands[1], operands[8]);
3314 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3315 (match_operand:BLK 1 "memory_operand" ""))
3316 (clobber (match_operand:SI 2 "register_operand" ""))
3317 (clobber (match_operand:SI 3 "register_operand" ""))
3318 (clobber (match_operand:SI 6 "register_operand" ""))
3319 (clobber (match_operand:SI 7 "register_operand" ""))
3320 (clobber (match_operand:SI 8 "register_operand" ""))
3321 (use (match_operand:SI 4 "arith14_operand" ""))
3322 (use (match_operand:SI 5 "const_int_operand" ""))])]
3324 && GET_CODE (operands[0]) == MEM
3325 && register_operand (XEXP (operands[0], 0), SImode)
3326 && GET_CODE (operands[1]) == MEM
3327 && register_operand (XEXP (operands[1], 0), SImode)"
3328 [(parallel [(set (match_dup 0) (match_dup 1))
3329 (clobber (match_dup 2))
3330 (clobber (match_dup 3))
3331 (clobber (match_dup 6))
3332 (clobber (match_dup 7))
3333 (clobber (match_dup 8))
3339 rtx addr = XEXP (operands[0], 0);
3340 if (dead_or_set_p (curr_insn, addr))
3344 emit_insn (gen_rtx_SET (operands[7], addr));
3345 operands[0] = replace_equiv_address (operands[0], operands[7]);
3348 addr = XEXP (operands[1], 0);
3349 if (dead_or_set_p (curr_insn, addr))
3353 emit_insn (gen_rtx_SET (operands[8], addr));
3354 operands[1] = replace_equiv_address (operands[1], operands[8]);
3358 (define_insn "movmemsi_postreload"
3359 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3360 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3361 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3362 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3363 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3364 (clobber (match_dup 0))
3365 (clobber (match_dup 1))
3366 (use (match_operand:SI 4 "arith14_operand" "J,2")) ;byte count
3367 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3369 "!TARGET_64BIT && reload_completed"
3370 "* return pa_output_block_move (operands, !which_alternative);"
3371 [(set_attr "type" "multi,multi")])
3373 (define_expand "movmemdi"
3374 [(parallel [(set (match_operand:BLK 0 "" "")
3375 (match_operand:BLK 1 "" ""))
3376 (clobber (match_dup 4))
3377 (clobber (match_dup 5))
3378 (clobber (match_dup 6))
3379 (clobber (match_dup 7))
3380 (clobber (match_dup 8))
3381 (use (match_operand:DI 2 "arith14_operand" ""))
3382 (use (match_operand:DI 3 "const_int_operand" ""))])]
3383 "TARGET_64BIT && optimize > 0"
3388 /* HP provides very fast block move library routine for the PA;
3389 this routine includes:
3391 4x4 byte at a time block moves,
3392 1x4 byte at a time with alignment checked at runtime with
3393 attempts to align the source and destination as needed
3396 With that in mind, here's the heuristics to try and guess when
3397 the inlined block move will be better than the library block
3400 If the size isn't constant, then always use the library routines.
3402 If the size is large in respect to the known alignment, then use
3403 the library routines.
3405 If the size is small in respect to the known alignment, then open
3406 code the copy (since that will lead to better scheduling).
3408 Else use the block move pattern. */
3410 /* Undetermined size, use the library routine. */
3411 if (GET_CODE (operands[2]) != CONST_INT)
3414 size = INTVAL (operands[2]);
3415 align = INTVAL (operands[3]);
3416 align = align > 8 ? 8 : (align ? align : 1);
3418 /* If size/alignment is large, then use the library routines. */
3419 if (size / align > 16)
3422 /* This does happen, but not often enough to worry much about. */
3423 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3426 /* Fall through means we're going to use our block move pattern. */
3428 = replace_equiv_address (operands[0],
3429 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3431 = replace_equiv_address (operands[1],
3432 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3433 operands[4] = gen_reg_rtx (DImode);
3434 operands[5] = gen_reg_rtx (DImode);
3435 operands[6] = gen_reg_rtx (DImode);
3436 operands[7] = gen_reg_rtx (DImode);
3437 operands[8] = gen_reg_rtx (DImode);
3440 ;; The operand constraints are written like this to support both compile-time
3441 ;; and run-time determined byte counts. The expander and pa_output_block_move
3442 ;; only support compile-time determined counts at this time.
3444 ;; If the count is run-time determined, the register with the byte count
3445 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3447 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3448 ;; broke this semantic for pseudo registers. We can't use match_scratch
3449 ;; as this requires two registers in the class R1_REGS when the MEMs for
3450 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3451 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3452 ;; respectively. We then split or peephole optimize after reload.
3453 (define_insn "movmemdi_prereload"
3454 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3455 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3456 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3457 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3458 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3459 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3460 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3461 (use (match_operand:DI 4 "arith14_operand" "J,2")) ;byte count
3462 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3465 [(set_attr "type" "multi,multi")])
3468 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3469 (match_operand:BLK 1 "memory_operand" ""))
3470 (clobber (match_operand:DI 2 "register_operand" ""))
3471 (clobber (match_operand:DI 3 "register_operand" ""))
3472 (clobber (match_operand:DI 6 "register_operand" ""))
3473 (clobber (match_operand:DI 7 "register_operand" ""))
3474 (clobber (match_operand:DI 8 "register_operand" ""))
3475 (use (match_operand:DI 4 "arith14_operand" ""))
3476 (use (match_operand:DI 5 "const_int_operand" ""))])]
3477 "TARGET_64BIT && reload_completed && !flag_peephole2
3478 && GET_CODE (operands[0]) == MEM
3479 && register_operand (XEXP (operands[0], 0), DImode)
3480 && GET_CODE (operands[1]) == MEM
3481 && register_operand (XEXP (operands[1], 0), DImode)"
3482 [(set (match_dup 7) (match_dup 9))
3483 (set (match_dup 8) (match_dup 10))
3484 (parallel [(set (match_dup 0) (match_dup 1))
3485 (clobber (match_dup 2))
3486 (clobber (match_dup 3))
3487 (clobber (match_dup 6))
3488 (clobber (match_dup 7))
3489 (clobber (match_dup 8))
3495 operands[9] = XEXP (operands[0], 0);
3496 operands[10] = XEXP (operands[1], 0);
3497 operands[0] = replace_equiv_address (operands[0], operands[7]);
3498 operands[1] = replace_equiv_address (operands[1], operands[8]);
3502 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3503 (match_operand:BLK 1 "memory_operand" ""))
3504 (clobber (match_operand:DI 2 "register_operand" ""))
3505 (clobber (match_operand:DI 3 "register_operand" ""))
3506 (clobber (match_operand:DI 6 "register_operand" ""))
3507 (clobber (match_operand:DI 7 "register_operand" ""))
3508 (clobber (match_operand:DI 8 "register_operand" ""))
3509 (use (match_operand:DI 4 "arith14_operand" ""))
3510 (use (match_operand:DI 5 "const_int_operand" ""))])]
3512 && GET_CODE (operands[0]) == MEM
3513 && register_operand (XEXP (operands[0], 0), DImode)
3514 && GET_CODE (operands[1]) == MEM
3515 && register_operand (XEXP (operands[1], 0), DImode)"
3516 [(parallel [(set (match_dup 0) (match_dup 1))
3517 (clobber (match_dup 2))
3518 (clobber (match_dup 3))
3519 (clobber (match_dup 6))
3520 (clobber (match_dup 7))
3521 (clobber (match_dup 8))
3527 rtx addr = XEXP (operands[0], 0);
3528 if (dead_or_set_p (curr_insn, addr))
3532 emit_insn (gen_rtx_SET (operands[7], addr));
3533 operands[0] = replace_equiv_address (operands[0], operands[7]);
3536 addr = XEXP (operands[1], 0);
3537 if (dead_or_set_p (curr_insn, addr))
3541 emit_insn (gen_rtx_SET (operands[8], addr));
3542 operands[1] = replace_equiv_address (operands[1], operands[8]);
3546 (define_insn "movmemdi_postreload"
3547 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3548 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3549 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3550 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3551 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3552 (clobber (match_dup 0))
3553 (clobber (match_dup 1))
3554 (use (match_operand:DI 4 "arith14_operand" "J,2")) ;byte count
3555 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3557 "TARGET_64BIT && reload_completed"
3558 "* return pa_output_block_move (operands, !which_alternative);"
3559 [(set_attr "type" "multi,multi")])
3561 (define_expand "setmemsi"
3562 [(parallel [(set (match_operand:BLK 0 "" "")
3563 (match_operand 2 "const_int_operand" ""))
3564 (clobber (match_dup 4))
3565 (clobber (match_dup 5))
3566 (use (match_operand:SI 1 "arith14_operand" ""))
3567 (use (match_operand:SI 3 "const_int_operand" ""))])]
3568 "!TARGET_64BIT && optimize > 0"
3573 /* If value to set is not zero, use the library routine. */
3574 if (operands[2] != const0_rtx)
3577 /* Undetermined size, use the library routine. */
3578 if (GET_CODE (operands[1]) != CONST_INT)
3581 size = INTVAL (operands[1]);
3582 align = INTVAL (operands[3]);
3583 align = align > 4 ? 4 : align;
3585 /* If size/alignment is large, then use the library routines. */
3586 if (size / align > 16)
3589 /* This does happen, but not often enough to worry much about. */
3590 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3593 /* Fall through means we're going to use our block clear pattern. */
3595 = replace_equiv_address (operands[0],
3596 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3597 operands[4] = gen_reg_rtx (SImode);
3598 operands[5] = gen_reg_rtx (SImode);
3601 (define_insn "clrmemsi_prereload"
3602 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3604 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3605 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3606 (use (match_operand:SI 2 "arith14_operand" "J,1")) ;byte count
3607 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3610 [(set_attr "type" "multi,multi")])
3613 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3615 (clobber (match_operand:SI 1 "register_operand" ""))
3616 (clobber (match_operand:SI 4 "register_operand" ""))
3617 (use (match_operand:SI 2 "arith14_operand" ""))
3618 (use (match_operand:SI 3 "const_int_operand" ""))])]
3619 "!TARGET_64BIT && reload_completed && !flag_peephole2
3620 && GET_CODE (operands[0]) == MEM
3621 && register_operand (XEXP (operands[0], 0), SImode)"
3622 [(set (match_dup 4) (match_dup 5))
3623 (parallel [(set (match_dup 0) (const_int 0))
3624 (clobber (match_dup 1))
3625 (clobber (match_dup 4))
3631 operands[5] = XEXP (operands[0], 0);
3632 operands[0] = replace_equiv_address (operands[0], operands[4]);
3636 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3638 (clobber (match_operand:SI 1 "register_operand" ""))
3639 (clobber (match_operand:SI 4 "register_operand" ""))
3640 (use (match_operand:SI 2 "arith14_operand" ""))
3641 (use (match_operand:SI 3 "const_int_operand" ""))])]
3643 && GET_CODE (operands[0]) == MEM
3644 && register_operand (XEXP (operands[0], 0), SImode)"
3645 [(parallel [(set (match_dup 0) (const_int 0))
3646 (clobber (match_dup 1))
3647 (clobber (match_dup 4))
3653 rtx addr = XEXP (operands[0], 0);
3654 if (dead_or_set_p (curr_insn, addr))
3658 emit_insn (gen_rtx_SET (operands[4], addr));
3659 operands[0] = replace_equiv_address (operands[0], operands[4]);
3663 (define_insn "clrmemsi_postreload"
3664 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3666 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3667 (clobber (match_dup 0))
3668 (use (match_operand:SI 2 "arith14_operand" "J,1")) ;byte count
3669 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3671 "!TARGET_64BIT && reload_completed"
3672 "* return pa_output_block_clear (operands, !which_alternative);"
3673 [(set_attr "type" "multi,multi")])
3675 (define_expand "setmemdi"
3676 [(parallel [(set (match_operand:BLK 0 "" "")
3677 (match_operand 2 "const_int_operand" ""))
3678 (clobber (match_dup 4))
3679 (clobber (match_dup 5))
3680 (use (match_operand:DI 1 "arith14_operand" ""))
3681 (use (match_operand:DI 3 "const_int_operand" ""))])]
3682 "TARGET_64BIT && optimize > 0"
3687 /* If value to set is not zero, use the library routine. */
3688 if (operands[2] != const0_rtx)
3691 /* Undetermined size, use the library routine. */
3692 if (GET_CODE (operands[1]) != CONST_INT)
3695 size = INTVAL (operands[1]);
3696 align = INTVAL (operands[3]);
3697 align = align > 8 ? 8 : align;
3699 /* If size/alignment is large, then use the library routines. */
3700 if (size / align > 16)
3703 /* This does happen, but not often enough to worry much about. */
3704 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3707 /* Fall through means we're going to use our block clear pattern. */
3709 = replace_equiv_address (operands[0],
3710 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3711 operands[4] = gen_reg_rtx (DImode);
3712 operands[5] = gen_reg_rtx (DImode);
3715 (define_insn "clrmemdi_prereload"
3716 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3718 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3719 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
3720 (use (match_operand:DI 2 "arith14_operand" "J,1")) ;byte count
3721 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
3724 [(set_attr "type" "multi,multi")])
3727 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3729 (clobber (match_operand:DI 1 "register_operand" ""))
3730 (clobber (match_operand:DI 4 "register_operand" ""))
3731 (use (match_operand:DI 2 "arith14_operand" ""))
3732 (use (match_operand:DI 3 "const_int_operand" ""))])]
3733 "TARGET_64BIT && reload_completed && !flag_peephole2
3734 && GET_CODE (operands[0]) == MEM
3735 && register_operand (XEXP (operands[0], 0), DImode)"
3736 [(set (match_dup 4) (match_dup 5))
3737 (parallel [(set (match_dup 0) (const_int 0))
3738 (clobber (match_dup 1))
3739 (clobber (match_dup 4))
3745 operands[5] = XEXP (operands[0], 0);
3746 operands[0] = replace_equiv_address (operands[0], operands[4]);
3750 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3752 (clobber (match_operand:DI 1 "register_operand" ""))
3753 (clobber (match_operand:DI 4 "register_operand" ""))
3754 (use (match_operand:DI 2 "arith14_operand" ""))
3755 (use (match_operand:DI 3 "const_int_operand" ""))])]
3757 && GET_CODE (operands[0]) == MEM
3758 && register_operand (XEXP (operands[0], 0), DImode)"
3759 [(parallel [(set (match_dup 0) (const_int 0))
3760 (clobber (match_dup 1))
3761 (clobber (match_dup 4))
3767 rtx addr = XEXP (operands[0], 0);
3768 if (dead_or_set_p (curr_insn, addr))
3772 emit_insn (gen_rtx_SET (operands[4], addr));
3773 operands[0] = replace_equiv_address (operands[0], operands[4]);
3777 (define_insn "clrmemdi_postreload"
3778 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3780 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3781 (clobber (match_dup 0))
3782 (use (match_operand:DI 2 "arith14_operand" "J,1")) ;byte count
3783 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
3785 "TARGET_64BIT && reload_completed"
3786 "* return pa_output_block_clear (operands, !which_alternative);"
3787 [(set_attr "type" "multi,multi")])
3789 ;; Floating point move insns
3791 (define_expand "movdf"
3792 [(set (match_operand:DF 0 "general_operand" "")
3793 (match_operand:DF 1 "general_operand" ""))]
3797 if (pa_emit_move_sequence (operands, DFmode, 0))
3801 ;; Handle DFmode input reloads requiring %r1 as a scratch register.
3802 (define_expand "reload_indf_r1"
3803 [(set (match_operand:DF 0 "register_operand" "=Z")
3804 (match_operand:DF 1 "non_hard_reg_operand" ""))
3805 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
3809 if (pa_emit_move_sequence (operands, DFmode, operands[2]))
3812 /* We don't want the clobber emitted, so handle this ourselves. */
3813 emit_insn (gen_rtx_SET (operands[0], operands[1]));
3817 ;; Handle DFmode input reloads requiring a general register as a
3818 ;; scratch register.
3819 (define_expand "reload_indf"
3820 [(set (match_operand:DF 0 "register_operand" "=Z")
3821 (match_operand:DF 1 "non_hard_reg_operand" ""))
3822 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3826 if (pa_emit_move_sequence (operands, DFmode, operands[2]))
3829 /* We don't want the clobber emitted, so handle this ourselves. */
3830 emit_insn (gen_rtx_SET (operands[0], operands[1]));
3834 ;; Handle DFmode output reloads requiring a general register as a
3835 ;; scratch register.
3836 (define_expand "reload_outdf"
3837 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
3838 (match_operand:DF 1 "register_operand" "Z"))
3839 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3843 if (pa_emit_move_sequence (operands, DFmode, operands[2]))
3846 /* We don't want the clobber emitted, so handle this ourselves. */
3847 emit_insn (gen_rtx_SET (operands[0], operands[1]));
3852 [(set (match_operand:DF 0 "move_dest_operand"
3853 "=f,*r,T,?o,?Q,f,*r,*r,?*r,?f")
3854 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3855 "fG,*rG,f,*r,*r,RT,o,RQ,f,*r"))]
3856 "(register_operand (operands[0], DFmode)
3857 || reg_or_0_operand (operands[1], DFmode))
3858 && !(GET_CODE (operands[1]) == CONST_DOUBLE
3859 && GET_CODE (operands[0]) == MEM)
3861 && !TARGET_SOFT_FLOAT"
3864 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3865 || operands[1] == CONST0_RTX (DFmode))
3866 && !(REG_P (operands[0]) && REG_P (operands[1])
3867 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
3868 return pa_output_fp_move_double (operands);
3869 return pa_output_move_double (operands);
3871 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load,fpstore_load,store_fpload")
3872 (set_attr "length" "4,8,4,8,16,4,8,16,12,12")])
3875 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
3876 (match_operand:DF 1 "reg_or_0_operand" "f"))]
3878 && !TARGET_DISABLE_INDEXING
3879 && reload_completed"
3881 [(set_attr "type" "fpstore")
3882 (set_attr "pa_combine_type" "addmove")
3883 (set_attr "length" "4")])
3886 [(set (match_operand:SI 0 "register_operand" "")
3887 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3889 (match_operand:SI 2 "register_operand" "")))
3890 (set (mem:DF (match_dup 0))
3891 (match_operand:DF 3 "register_operand" ""))]
3893 && !TARGET_DISABLE_INDEXING
3894 && REG_OK_FOR_BASE_P (operands[2])
3895 && FP_REGNO_P (REGNO (operands[3]))"
3896 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3898 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3903 [(set (match_operand:SI 0 "register_operand" "")
3904 (plus:SI (match_operand:SI 2 "register_operand" "")
3905 (mult:SI (match_operand:SI 1 "register_operand" "")
3907 (set (mem:DF (match_dup 0))
3908 (match_operand:DF 3 "register_operand" ""))]
3910 && !TARGET_DISABLE_INDEXING
3911 && REG_OK_FOR_BASE_P (operands[2])
3912 && FP_REGNO_P (REGNO (operands[3]))"
3913 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3915 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3920 [(set (match_operand:DI 0 "register_operand" "")
3921 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
3923 (match_operand:DI 2 "register_operand" "")))
3924 (set (mem:DF (match_dup 0))
3925 (match_operand:DF 3 "register_operand" ""))]
3927 && !TARGET_DISABLE_INDEXING
3929 && REG_OK_FOR_BASE_P (operands[2])
3930 && FP_REGNO_P (REGNO (operands[3]))"
3931 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3933 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3938 [(set (match_operand:DI 0 "register_operand" "")
3939 (plus:DI (match_operand:DI 2 "register_operand" "")
3940 (mult:DI (match_operand:DI 1 "register_operand" "")
3942 (set (mem:DF (match_dup 0))
3943 (match_operand:DF 3 "register_operand" ""))]
3945 && !TARGET_DISABLE_INDEXING
3947 && REG_OK_FOR_BASE_P (operands[2])
3948 && FP_REGNO_P (REGNO (operands[3]))"
3949 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3951 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3956 [(set (match_operand:SI 0 "register_operand" "")
3957 (plus:SI (match_operand:SI 1 "register_operand" "")
3958 (match_operand:SI 2 "register_operand" "")))
3959 (set (mem:DF (match_dup 0))
3960 (match_operand:DF 3 "register_operand" ""))]
3962 && !TARGET_DISABLE_INDEXING
3963 && TARGET_NO_SPACE_REGS
3964 && REG_OK_FOR_INDEX_P (operands[1])
3965 && REG_OK_FOR_BASE_P (operands[2])
3966 && FP_REGNO_P (REGNO (operands[3]))"
3967 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
3969 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
3973 [(set (match_operand:SI 0 "register_operand" "")
3974 (plus:SI (match_operand:SI 1 "register_operand" "")
3975 (match_operand:SI 2 "register_operand" "")))
3976 (set (mem:DF (match_dup 0))
3977 (match_operand:DF 3 "register_operand" ""))]
3979 && !TARGET_DISABLE_INDEXING
3980 && TARGET_NO_SPACE_REGS
3981 && REG_OK_FOR_BASE_P (operands[1])
3982 && REG_OK_FOR_INDEX_P (operands[2])
3983 && FP_REGNO_P (REGNO (operands[3]))"
3984 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
3986 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
3990 [(set (match_operand:DI 0 "register_operand" "")
3991 (plus:DI (match_operand:DI 1 "register_operand" "")
3992 (match_operand:DI 2 "register_operand" "")))
3993 (set (mem:DF (match_dup 0))
3994 (match_operand:DF 3 "register_operand" ""))]
3996 && !TARGET_DISABLE_INDEXING
3998 && TARGET_NO_SPACE_REGS
3999 && REG_OK_FOR_INDEX_P (operands[1])
4000 && REG_OK_FOR_BASE_P (operands[2])
4001 && FP_REGNO_P (REGNO (operands[3]))"
4002 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
4004 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4008 [(set (match_operand:DI 0 "register_operand" "")
4009 (plus:DI (match_operand:DI 1 "register_operand" "")
4010 (match_operand:DI 2 "register_operand" "")))
4011 (set (mem:DF (match_dup 0))
4012 (match_operand:DF 3 "register_operand" ""))]
4014 && !TARGET_DISABLE_INDEXING
4016 && TARGET_NO_SPACE_REGS
4017 && REG_OK_FOR_BASE_P (operands[1])
4018 && REG_OK_FOR_INDEX_P (operands[2])
4019 && FP_REGNO_P (REGNO (operands[3]))"
4020 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
4022 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4026 [(set (match_operand:DF 0 "move_dest_operand"
4028 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
4030 "(register_operand (operands[0], DFmode)
4031 || reg_or_0_operand (operands[1], DFmode))
4033 && TARGET_SOFT_FLOAT"
4036 return pa_output_move_double (operands);
4038 [(set_attr "type" "move,store,store,load,load")
4039 (set_attr "length" "8,8,16,8,16")])
4042 [(set (match_operand:DF 0 "move_dest_operand"
4043 "=!*r,*r,*r,*r,*r,Q,f,f,T")
4044 (match_operand:DF 1 "move_src_operand"
4045 "!*r,J,N,K,RQ,*rG,fG,RT,f"))]
4046 "(register_operand (operands[0], DFmode)
4047 || reg_or_0_operand (operands[1], DFmode))
4048 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4059 [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
4060 (set_attr "pa_combine_type" "addmove")
4061 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
4064 (define_expand "movdi"
4065 [(set (match_operand:DI 0 "general_operand" "")
4066 (match_operand:DI 1 "general_operand" ""))]
4070 if (pa_emit_move_sequence (operands, DImode, 0))
4074 ;; Handle DImode input reloads requiring %r1 as a scratch register.
4075 (define_expand "reload_indi_r1"
4076 [(set (match_operand:DI 0 "register_operand" "=Z")
4077 (match_operand:DI 1 "non_hard_reg_operand" ""))
4078 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
4082 if (pa_emit_move_sequence (operands, DImode, operands[2]))
4085 /* We don't want the clobber emitted, so handle this ourselves. */
4086 emit_insn (gen_rtx_SET (operands[0], operands[1]));
4090 ;; Handle DImode input reloads requiring a general register as a
4091 ;; scratch register.
4092 (define_expand "reload_indi"
4093 [(set (match_operand:DI 0 "register_operand" "=Z")
4094 (match_operand:DI 1 "non_hard_reg_operand" ""))
4095 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4099 if (pa_emit_move_sequence (operands, DImode, operands[2]))
4102 /* We don't want the clobber emitted, so handle this ourselves. */
4103 emit_insn (gen_rtx_SET (operands[0], operands[1]));
4107 ;; Handle DImode output reloads requiring a general register as a
4108 ;; scratch register.
4109 (define_expand "reload_outdi"
4110 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
4111 (match_operand:DI 1 "register_operand" "Z"))
4112 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4116 if (pa_emit_move_sequence (operands, DImode, operands[2]))
4119 /* We don't want the clobber emitted, so handle this ourselves. */
4120 emit_insn (gen_rtx_SET (operands[0], operands[1]));
4125 [(set (match_operand:DI 0 "register_operand" "=r")
4126 (high:DI (match_operand 1 "" "")))]
4130 rtx op0 = operands[0];
4131 rtx op1 = operands[1];
4133 switch (GET_CODE (op1))
4136 #if HOST_BITS_PER_WIDE_INT <= 32
4137 operands[0] = operand_subword (op0, 1, 0, DImode);
4138 output_asm_insn (\"ldil L'%1,%0\", operands);
4140 operands[0] = operand_subword (op0, 0, 0, DImode);
4141 if (INTVAL (op1) < 0)
4142 output_asm_insn (\"ldi -1,%0\", operands);
4144 output_asm_insn (\"ldi 0,%0\", operands);
4146 operands[0] = operand_subword (op0, 1, 0, DImode);
4147 operands[1] = GEN_INT (INTVAL (op1) & 0xffffffff);
4148 output_asm_insn (\"ldil L'%1,%0\", operands);
4150 operands[0] = operand_subword (op0, 0, 0, DImode);
4151 operands[1] = GEN_INT (INTVAL (op1) >> 32);
4152 output_asm_insn (pa_singlemove_string (operands), operands);
4157 operands[0] = operand_subword (op0, 1, 0, DImode);
4158 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
4159 output_asm_insn (\"ldil L'%1,%0\", operands);
4161 operands[0] = operand_subword (op0, 0, 0, DImode);
4162 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
4163 output_asm_insn (pa_singlemove_string (operands), operands);
4171 [(set_attr "type" "move")
4172 (set_attr "length" "12")])
4175 [(set (match_operand:DI 0 "move_dest_operand"
4176 "=r,o,Q,r,r,r,*f,*f,T,?r,?*f")
4177 (match_operand:DI 1 "move_src_operand"
4178 "rM,r,r,o*R,Q,i,*fM,RT,*f,*f,r"))]
4179 "(register_operand (operands[0], DImode)
4180 || reg_or_0_operand (operands[1], DImode))
4182 && !TARGET_SOFT_FLOAT"
4185 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4186 || operands[1] == CONST0_RTX (DFmode))
4187 && !(REG_P (operands[0]) && REG_P (operands[1])
4188 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4189 return pa_output_fp_move_double (operands);
4190 return pa_output_move_double (operands);
4193 "move,store,store,load,load,multi,fpalu,fpload,fpstore,fpstore_load,store_fpload")
4194 (set_attr "length" "8,8,16,8,16,16,4,4,4,12,12")])
4197 [(set (match_operand:DI 0 "move_dest_operand"
4198 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
4199 (match_operand:DI 1 "move_src_operand"
4200 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
4201 "(register_operand (operands[0], DImode)
4202 || reg_or_0_operand (operands[1], DImode))
4203 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4213 {mfctl|mfctl,w} %%sar,%0
4217 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
4218 (set_attr "pa_combine_type" "addmove")
4219 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
4222 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4223 (match_operand:DI 1 "register_operand" "f"))]
4226 && !TARGET_DISABLE_INDEXING
4227 && reload_completed"
4229 [(set_attr "type" "fpstore")
4230 (set_attr "pa_combine_type" "addmove")
4231 (set_attr "length" "4")])
4234 [(set (match_operand:DI 0 "register_operand" "")
4235 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4237 (match_operand:DI 2 "register_operand" "")))
4238 (set (mem:DI (match_dup 0))
4239 (match_operand:DI 3 "register_operand" ""))]
4241 && !TARGET_DISABLE_INDEXING
4243 && REG_OK_FOR_BASE_P (operands[2])
4244 && FP_REGNO_P (REGNO (operands[3]))"
4245 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4247 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4252 [(set (match_operand:DI 0 "register_operand" "")
4253 (plus:DI (match_operand:DI 2 "register_operand" "")
4254 (mult:DI (match_operand:DI 1 "register_operand" "")
4256 (set (mem:DI (match_dup 0))
4257 (match_operand:DI 3 "register_operand" ""))]
4259 && !TARGET_DISABLE_INDEXING
4261 && REG_OK_FOR_BASE_P (operands[2])
4262 && FP_REGNO_P (REGNO (operands[3]))"
4263 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4265 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4270 [(set (match_operand:DI 0 "register_operand" "")
4271 (plus:DI (match_operand:DI 1 "register_operand" "")
4272 (match_operand:DI 2 "register_operand" "")))
4273 (set (mem:DI (match_dup 0))
4274 (match_operand:DI 3 "register_operand" ""))]
4276 && !TARGET_DISABLE_INDEXING
4278 && TARGET_NO_SPACE_REGS
4279 && REG_OK_FOR_INDEX_P (operands[1])
4280 && REG_OK_FOR_BASE_P (operands[2])
4281 && FP_REGNO_P (REGNO (operands[3]))"
4282 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4284 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4288 [(set (match_operand:DI 0 "register_operand" "")
4289 (plus:DI (match_operand:DI 1 "register_operand" "")
4290 (match_operand:DI 2 "register_operand" "")))
4291 (set (mem:DI (match_dup 0))
4292 (match_operand:DI 3 "register_operand" ""))]
4294 && !TARGET_DISABLE_INDEXING
4296 && TARGET_NO_SPACE_REGS
4297 && REG_OK_FOR_BASE_P (operands[1])
4298 && REG_OK_FOR_INDEX_P (operands[2])
4299 && FP_REGNO_P (REGNO (operands[3]))"
4300 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4302 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4306 [(set (match_operand:DI 0 "move_dest_operand"
4308 (match_operand:DI 1 "general_operand"
4310 "(register_operand (operands[0], DImode)
4311 || reg_or_0_operand (operands[1], DImode))
4313 && TARGET_SOFT_FLOAT"
4316 return pa_output_move_double (operands);
4318 [(set_attr "type" "move,store,store,load,load,multi")
4319 (set_attr "length" "8,8,16,8,16,16")])
4322 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4323 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4324 (match_operand:DI 2 "immediate_operand" "i,i")))]
4328 /* Don't output a 64-bit constant, since we can't trust the assembler to
4329 handle it correctly. */
4330 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4331 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4332 else if (HOST_BITS_PER_WIDE_INT > 32
4333 && GET_CODE (operands[2]) == CONST_INT)
4334 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffffffff);
4335 if (which_alternative == 1)
4336 output_asm_insn (\"copy %1,%0\", operands);
4337 return \"ldo R'%G2(%R1),%R0\";
4339 [(set_attr "type" "move,move")
4340 (set_attr "length" "4,8")])
4342 (define_expand "movsf"
4343 [(set (match_operand:SF 0 "general_operand" "")
4344 (match_operand:SF 1 "general_operand" ""))]
4348 if (pa_emit_move_sequence (operands, SFmode, 0))
4352 ;; Handle SFmode input reloads requiring %r1 as a scratch register.
4353 (define_expand "reload_insf_r1"
4354 [(set (match_operand:SF 0 "register_operand" "=Z")
4355 (match_operand:SF 1 "non_hard_reg_operand" ""))
4356 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
4360 if (pa_emit_move_sequence (operands, SFmode, operands[2]))
4363 /* We don't want the clobber emitted, so handle this ourselves. */
4364 emit_insn (gen_rtx_SET (operands[0], operands[1]));
4368 ;; Handle SFmode input reloads requiring a general register as a
4369 ;; scratch register.
4370 (define_expand "reload_insf"
4371 [(set (match_operand:SF 0 "register_operand" "=Z")
4372 (match_operand:SF 1 "non_hard_reg_operand" ""))
4373 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4377 if (pa_emit_move_sequence (operands, SFmode, operands[2]))
4380 /* We don't want the clobber emitted, so handle this ourselves. */
4381 emit_insn (gen_rtx_SET (operands[0], operands[1]));
4385 ;; Handle SFmode output reloads requiring a general register as a
4386 ;; scratch register.
4387 (define_expand "reload_outsf"
4388 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4389 (match_operand:SF 1 "register_operand" "Z"))
4390 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4394 if (pa_emit_move_sequence (operands, SFmode, operands[2]))
4397 /* We don't want the clobber emitted, so handle this ourselves. */
4398 emit_insn (gen_rtx_SET (operands[0], operands[1]));
4403 [(set (match_operand:SF 0 "move_dest_operand"
4404 "=f,!*r,f,*r,T,Q,?*r,?f")
4405 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4406 "fG,!*rG,RT,RQ,f,*rG,f,*r"))]
4407 "(register_operand (operands[0], SFmode)
4408 || reg_or_0_operand (operands[1], SFmode))
4409 && !TARGET_SOFT_FLOAT
4418 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
4419 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
4420 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store,fpstore_load,store_fpload")
4421 (set_attr "pa_combine_type" "addmove")
4422 (set_attr "length" "4,4,4,4,4,4,8,8")])
4425 [(set (match_operand:SF 0 "move_dest_operand"
4427 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4428 "fG,!*rG,RT,RQ,f,*rG"))]
4429 "(register_operand (operands[0], SFmode)
4430 || reg_or_0_operand (operands[1], SFmode))
4431 && !TARGET_SOFT_FLOAT
4440 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4441 (set_attr "pa_combine_type" "addmove")
4442 (set_attr "length" "4,4,4,4,4,4")])
4445 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4446 (match_operand:SF 1 "register_operand" "f"))]
4448 && !TARGET_DISABLE_INDEXING
4449 && reload_completed"
4451 [(set_attr "type" "fpstore")
4452 (set_attr "pa_combine_type" "addmove")
4453 (set_attr "length" "4")])
4456 [(set (match_operand:SI 0 "register_operand" "")
4457 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4459 (match_operand:SI 2 "register_operand" "")))
4460 (set (mem:SF (match_dup 0))
4461 (match_operand:SF 3 "register_operand" ""))]
4463 && !TARGET_DISABLE_INDEXING
4464 && REG_OK_FOR_BASE_P (operands[2])
4465 && FP_REGNO_P (REGNO (operands[3]))"
4466 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4468 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4473 [(set (match_operand:SI 0 "register_operand" "")
4474 (plus:SI (match_operand:SI 2 "register_operand" "")
4475 (mult:SI (match_operand:SI 1 "register_operand" "")
4477 (set (mem:SF (match_dup 0))
4478 (match_operand:SF 3 "register_operand" ""))]
4480 && !TARGET_DISABLE_INDEXING
4481 && REG_OK_FOR_BASE_P (operands[2])
4482 && FP_REGNO_P (REGNO (operands[3]))"
4483 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4485 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4490 [(set (match_operand:DI 0 "register_operand" "")
4491 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4493 (match_operand:DI 2 "register_operand" "")))
4494 (set (mem:SF (match_dup 0))
4495 (match_operand:SF 3 "register_operand" ""))]
4497 && !TARGET_DISABLE_INDEXING
4499 && REG_OK_FOR_BASE_P (operands[2])
4500 && FP_REGNO_P (REGNO (operands[3]))"
4501 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4503 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4508 [(set (match_operand:DI 0 "register_operand" "")
4509 (plus:DI (match_operand:DI 2 "register_operand" "")
4510 (mult:DI (match_operand:DI 1 "register_operand" "")
4512 (set (mem:SF (match_dup 0))
4513 (match_operand:SF 3 "register_operand" ""))]
4515 && !TARGET_DISABLE_INDEXING
4517 && REG_OK_FOR_BASE_P (operands[2])
4518 && FP_REGNO_P (REGNO (operands[3]))"
4519 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4521 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4526 [(set (match_operand:SI 0 "register_operand" "")
4527 (plus:SI (match_operand:SI 1 "register_operand" "")
4528 (match_operand:SI 2 "register_operand" "")))
4529 (set (mem:SF (match_dup 0))
4530 (match_operand:SF 3 "register_operand" ""))]
4532 && !TARGET_DISABLE_INDEXING
4533 && TARGET_NO_SPACE_REGS
4534 && REG_OK_FOR_INDEX_P (operands[1])
4535 && REG_OK_FOR_BASE_P (operands[2])
4536 && FP_REGNO_P (REGNO (operands[3]))"
4537 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4539 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4543 [(set (match_operand:SI 0 "register_operand" "")
4544 (plus:SI (match_operand:SI 1 "register_operand" "")
4545 (match_operand:SI 2 "register_operand" "")))
4546 (set (mem:SF (match_dup 0))
4547 (match_operand:SF 3 "register_operand" ""))]
4549 && !TARGET_DISABLE_INDEXING
4550 && TARGET_NO_SPACE_REGS
4551 && REG_OK_FOR_BASE_P (operands[1])
4552 && REG_OK_FOR_INDEX_P (operands[2])
4553 && FP_REGNO_P (REGNO (operands[3]))"
4554 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4556 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4560 [(set (match_operand:DI 0 "register_operand" "")
4561 (plus:DI (match_operand:DI 1 "register_operand" "")
4562 (match_operand:DI 2 "register_operand" "")))
4563 (set (mem:SF (match_dup 0))
4564 (match_operand:SF 3 "register_operand" ""))]
4566 && !TARGET_DISABLE_INDEXING
4568 && TARGET_NO_SPACE_REGS
4569 && REG_OK_FOR_INDEX_P (operands[1])
4570 && REG_OK_FOR_BASE_P (operands[2])
4571 && FP_REGNO_P (REGNO (operands[3]))"
4572 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4574 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4578 [(set (match_operand:DI 0 "register_operand" "")
4579 (plus:DI (match_operand:DI 1 "register_operand" "")
4580 (match_operand:DI 2 "register_operand" "")))
4581 (set (mem:SF (match_dup 0))
4582 (match_operand:SF 3 "register_operand" ""))]
4584 && !TARGET_DISABLE_INDEXING
4586 && TARGET_NO_SPACE_REGS
4587 && REG_OK_FOR_BASE_P (operands[1])
4588 && REG_OK_FOR_INDEX_P (operands[2])
4589 && FP_REGNO_P (REGNO (operands[3]))"
4590 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4592 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4596 [(set (match_operand:SF 0 "move_dest_operand"
4598 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4600 "(register_operand (operands[0], SFmode)
4601 || reg_or_0_operand (operands[1], SFmode))
4602 && TARGET_SOFT_FLOAT"
4607 [(set_attr "type" "move,load,store")
4608 (set_attr "pa_combine_type" "addmove")
4609 (set_attr "length" "4,4,4")])
4613 ;;- zero extension instructions
4614 ;; We have define_expand for zero extension patterns to make sure the
4615 ;; operands get loaded into registers. The define_insns accept
4616 ;; memory operands. This gives us better overall code than just
4617 ;; having a pattern that does or does not accept memory operands.
4619 (define_expand "zero_extendqihi2"
4620 [(set (match_operand:HI 0 "register_operand" "")
4622 (match_operand:QI 1 "register_operand" "")))]
4627 [(set (match_operand:HI 0 "register_operand" "=r,r")
4629 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4630 "GET_CODE (operands[1]) != CONST_INT"
4632 {extru|extrw,u} %1,31,8,%0
4634 [(set_attr "type" "shift,load")
4635 (set_attr "length" "4,4")])
4637 (define_expand "zero_extendqisi2"
4638 [(set (match_operand:SI 0 "register_operand" "")
4640 (match_operand:QI 1 "register_operand" "")))]
4645 [(set (match_operand:SI 0 "register_operand" "=r,r")
4647 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4648 "GET_CODE (operands[1]) != CONST_INT"
4650 {extru|extrw,u} %1,31,8,%0
4652 [(set_attr "type" "shift,load")
4653 (set_attr "length" "4,4")])
4655 (define_expand "zero_extendhisi2"
4656 [(set (match_operand:SI 0 "register_operand" "")
4658 (match_operand:HI 1 "register_operand" "")))]
4663 [(set (match_operand:SI 0 "register_operand" "=r,r")
4665 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4666 "GET_CODE (operands[1]) != CONST_INT"
4668 {extru|extrw,u} %1,31,16,%0
4670 [(set_attr "type" "shift,load")
4671 (set_attr "length" "4,4")])
4673 (define_expand "zero_extendqidi2"
4674 [(set (match_operand:DI 0 "register_operand" "")
4676 (match_operand:QI 1 "register_operand" "")))]
4681 [(set (match_operand:DI 0 "register_operand" "=r,r")
4683 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4684 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4688 [(set_attr "type" "shift,load")
4689 (set_attr "length" "4,4")])
4691 (define_expand "zero_extendhidi2"
4692 [(set (match_operand:DI 0 "register_operand" "")
4694 (match_operand:HI 1 "register_operand" "")))]
4699 [(set (match_operand:DI 0 "register_operand" "=r,r")
4701 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4702 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4706 [(set_attr "type" "shift,load")
4707 (set_attr "length" "4,4")])
4709 (define_expand "zero_extendsidi2"
4710 [(set (match_operand:DI 0 "register_operand" "")
4712 (match_operand:SI 1 "register_operand" "")))]
4717 [(set (match_operand:DI 0 "register_operand" "=r,r")
4719 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
4720 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4724 [(set_attr "type" "shift,load")
4725 (set_attr "length" "4,4")])
4727 ;;- sign extension instructions
4729 (define_insn "extendhisi2"
4730 [(set (match_operand:SI 0 "register_operand" "=r")
4731 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
4733 "{extrs|extrw,s} %1,31,16,%0"
4734 [(set_attr "type" "shift")
4735 (set_attr "length" "4")])
4737 (define_insn "extendqihi2"
4738 [(set (match_operand:HI 0 "register_operand" "=r")
4739 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
4741 "{extrs|extrw,s} %1,31,8,%0"
4742 [(set_attr "type" "shift")
4743 (set_attr "length" "4")])
4745 (define_insn "extendqisi2"
4746 [(set (match_operand:SI 0 "register_operand" "=r")
4747 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
4749 "{extrs|extrw,s} %1,31,8,%0"
4750 [(set_attr "type" "shift")
4751 (set_attr "length" "4")])
4753 (define_insn "extendqidi2"
4754 [(set (match_operand:DI 0 "register_operand" "=r")
4755 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
4757 "extrd,s %1,63,8,%0"
4758 [(set_attr "type" "shift")
4759 (set_attr "length" "4")])
4761 (define_insn "extendhidi2"
4762 [(set (match_operand:DI 0 "register_operand" "=r")
4763 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
4765 "extrd,s %1,63,16,%0"
4766 [(set_attr "type" "shift")
4767 (set_attr "length" "4")])
4769 (define_insn "extendsidi2"
4770 [(set (match_operand:DI 0 "register_operand" "=r")
4771 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
4773 "extrd,s %1,63,32,%0"
4774 [(set_attr "type" "shift")
4775 (set_attr "length" "4")])
4778 ;; Conversions between float and double.
4780 (define_insn "extendsfdf2"
4781 [(set (match_operand:DF 0 "register_operand" "=f")
4783 (match_operand:SF 1 "register_operand" "f")))]
4784 "! TARGET_SOFT_FLOAT"
4785 "{fcnvff|fcnv},sgl,dbl %1,%0"
4786 [(set_attr "type" "fpalu")
4787 (set_attr "length" "4")])
4789 (define_insn "truncdfsf2"
4790 [(set (match_operand:SF 0 "register_operand" "=f")
4792 (match_operand:DF 1 "register_operand" "f")))]
4793 "! TARGET_SOFT_FLOAT"
4794 "{fcnvff|fcnv},dbl,sgl %1,%0"
4795 [(set_attr "type" "fpalu")
4796 (set_attr "length" "4")])
4798 ;; Conversion between fixed point and floating point.
4799 ;; Note that among the fix-to-float insns
4800 ;; the ones that start with SImode come first.
4801 ;; That is so that an operand that is a CONST_INT
4802 ;; (and therefore lacks a specific machine mode).
4803 ;; will be recognized as SImode (which is always valid)
4804 ;; rather than as QImode or HImode.
4806 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
4807 ;; to be reloaded by putting the constant into memory.
4808 ;; It must come before the more general floatsisf2 pattern.
4810 [(set (match_operand:SF 0 "register_operand" "=f")
4811 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
4812 "! TARGET_SOFT_FLOAT"
4813 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
4814 [(set_attr "type" "fpalu")
4815 (set_attr "length" "8")])
4817 (define_insn "floatsisf2"
4818 [(set (match_operand:SF 0 "register_operand" "=f")
4819 (float:SF (match_operand:SI 1 "register_operand" "f")))]
4820 "! TARGET_SOFT_FLOAT"
4821 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
4822 [(set_attr "type" "fpalu")
4823 (set_attr "length" "4")])
4825 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
4826 ;; to be reloaded by putting the constant into memory.
4827 ;; It must come before the more general floatsidf2 pattern.
4829 [(set (match_operand:DF 0 "register_operand" "=f")
4830 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
4831 "! TARGET_SOFT_FLOAT"
4832 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
4833 [(set_attr "type" "fpalu")
4834 (set_attr "length" "8")])
4836 (define_insn "floatsidf2"
4837 [(set (match_operand:DF 0 "register_operand" "=f")
4838 (float:DF (match_operand:SI 1 "register_operand" "f")))]
4839 "! TARGET_SOFT_FLOAT"
4840 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
4841 [(set_attr "type" "fpalu")
4842 (set_attr "length" "4")])
4844 (define_expand "floatunssisf2"
4845 [(set (subreg:SI (match_dup 2) 4)
4846 (match_operand:SI 1 "register_operand" ""))
4847 (set (subreg:SI (match_dup 2) 0)
4849 (set (match_operand:SF 0 "register_operand" "")
4850 (float:SF (match_dup 2)))]
4851 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4856 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
4859 operands[2] = gen_reg_rtx (DImode);
4862 (define_expand "floatunssidf2"
4863 [(set (subreg:SI (match_dup 2) 4)
4864 (match_operand:SI 1 "register_operand" ""))
4865 (set (subreg:SI (match_dup 2) 0)
4867 (set (match_operand:DF 0 "register_operand" "")
4868 (float:DF (match_dup 2)))]
4869 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4874 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
4877 operands[2] = gen_reg_rtx (DImode);
4880 (define_insn "floatdisf2"
4881 [(set (match_operand:SF 0 "register_operand" "=f")
4882 (float:SF (match_operand:DI 1 "register_operand" "f")))]
4883 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4884 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
4885 [(set_attr "type" "fpalu")
4886 (set_attr "length" "4")])
4888 (define_insn "floatdidf2"
4889 [(set (match_operand:DF 0 "register_operand" "=f")
4890 (float:DF (match_operand:DI 1 "register_operand" "f")))]
4891 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4892 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
4893 [(set_attr "type" "fpalu")
4894 (set_attr "length" "4")])
4896 ;; Convert a float to an actual integer.
4897 ;; Truncation is performed as part of the conversion.
4899 (define_insn "fix_truncsfsi2"
4900 [(set (match_operand:SI 0 "register_operand" "=f")
4901 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4902 "! TARGET_SOFT_FLOAT"
4903 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
4904 [(set_attr "type" "fpalu")
4905 (set_attr "length" "4")])
4907 (define_insn "fix_truncdfsi2"
4908 [(set (match_operand:SI 0 "register_operand" "=f")
4909 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4910 "! TARGET_SOFT_FLOAT"
4911 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
4912 [(set_attr "type" "fpalu")
4913 (set_attr "length" "4")])
4915 (define_insn "fix_truncsfdi2"
4916 [(set (match_operand:DI 0 "register_operand" "=f")
4917 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4918 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4919 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
4920 [(set_attr "type" "fpalu")
4921 (set_attr "length" "4")])
4923 (define_insn "fix_truncdfdi2"
4924 [(set (match_operand:DI 0 "register_operand" "=f")
4925 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4926 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4927 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
4928 [(set_attr "type" "fpalu")
4929 (set_attr "length" "4")])
4931 (define_insn "floatunssidf2_pa20"
4932 [(set (match_operand:DF 0 "register_operand" "=f")
4933 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
4934 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4936 [(set_attr "type" "fpalu")
4937 (set_attr "length" "4")])
4939 (define_insn "floatunssisf2_pa20"
4940 [(set (match_operand:SF 0 "register_operand" "=f")
4941 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
4942 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4944 [(set_attr "type" "fpalu")
4945 (set_attr "length" "4")])
4947 (define_insn "floatunsdisf2"
4948 [(set (match_operand:SF 0 "register_operand" "=f")
4949 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
4950 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4951 "fcnv,udw,sgl %1,%0"
4952 [(set_attr "type" "fpalu")
4953 (set_attr "length" "4")])
4955 (define_insn "floatunsdidf2"
4956 [(set (match_operand:DF 0 "register_operand" "=f")
4957 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
4958 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4959 "fcnv,udw,dbl %1,%0"
4960 [(set_attr "type" "fpalu")
4961 (set_attr "length" "4")])
4963 (define_insn "fixuns_truncsfsi2"
4964 [(set (match_operand:SI 0 "register_operand" "=f")
4965 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4966 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4967 "fcnv,t,sgl,uw %1,%0"
4968 [(set_attr "type" "fpalu")
4969 (set_attr "length" "4")])
4971 (define_insn "fixuns_truncdfsi2"
4972 [(set (match_operand:SI 0 "register_operand" "=f")
4973 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4974 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4975 "fcnv,t,dbl,uw %1,%0"
4976 [(set_attr "type" "fpalu")
4977 (set_attr "length" "4")])
4979 (define_insn "fixuns_truncsfdi2"
4980 [(set (match_operand:DI 0 "register_operand" "=f")
4981 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4982 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4983 "fcnv,t,sgl,udw %1,%0"
4984 [(set_attr "type" "fpalu")
4985 (set_attr "length" "4")])
4987 (define_insn "fixuns_truncdfdi2"
4988 [(set (match_operand:DI 0 "register_operand" "=f")
4989 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4990 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4991 "fcnv,t,dbl,udw %1,%0"
4992 [(set_attr "type" "fpalu")
4993 (set_attr "length" "4")])
4995 ;;- arithmetic instructions
4997 (define_expand "adddi3"
4998 [(set (match_operand:DI 0 "register_operand" "")
4999 (plus:DI (match_operand:DI 1 "register_operand" "")
5000 (match_operand:DI 2 "adddi3_operand" "")))]
5005 [(set (match_operand:DI 0 "register_operand" "=r")
5006 (plus:DI (match_operand:DI 1 "register_operand" "%r")
5007 (match_operand:DI 2 "arith11_operand" "rI")))]
5011 if (GET_CODE (operands[2]) == CONST_INT)
5013 if (INTVAL (operands[2]) >= 0)
5014 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
5016 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
5019 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
5021 [(set_attr "type" "binary")
5022 (set_attr "length" "8")])
5025 [(set (match_operand:DI 0 "register_operand" "=r,r")
5026 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
5027 (match_operand:DI 2 "arith14_operand" "r,J")))]
5032 [(set_attr "type" "binary,binary")
5033 (set_attr "pa_combine_type" "addmove")
5034 (set_attr "length" "4,4")])
5037 [(set (match_operand:DI 0 "register_operand" "=r")
5038 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5039 (match_operand:DI 2 "register_operand" "r")))]
5042 [(set_attr "type" "binary")
5043 (set_attr "length" "4")])
5046 [(set (match_operand:SI 0 "register_operand" "=r")
5047 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5048 (match_operand:SI 2 "register_operand" "r")))]
5051 [(set_attr "type" "binary")
5052 (set_attr "length" "4")])
5054 (define_expand "addvdi3"
5055 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5056 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "")
5057 (match_operand:DI 2 "arith11_operand" "")))
5058 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5059 (sign_extend:TI (match_dup 2)))
5060 (sign_extend:TI (plus:DI (match_dup 1)
5067 [(set (match_operand:DI 0 "register_operand" "=r,r")
5068 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM,rM")
5069 (match_operand:DI 2 "arith11_operand" "r,I")))
5070 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5071 (sign_extend:TI (match_dup 2)))
5072 (sign_extend:TI (plus:DI (match_dup 1)
5078 addi,tsv,* %2,%1,%0"
5079 [(set_attr "type" "binary,binary")
5080 (set_attr "length" "4,4")])
5083 [(set (match_operand:DI 0 "register_operand" "=r")
5084 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM")
5085 (match_operand:DI 2 "arith11_operand" "rI")))
5086 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5087 (sign_extend:TI (match_dup 2)))
5088 (sign_extend:TI (plus:DI (match_dup 1)
5094 if (GET_CODE (operands[2]) == CONST_INT)
5096 if (INTVAL (operands[2]) >= 0)
5097 return \"addi %2,%R1,%R0\;{addco|add,c,tsv} %1,%%r0,%0\";
5099 return \"addi %2,%R1,%R0\;{subbo|sub,b,tsv} %1,%%r0,%0\";
5102 return \"add %R2,%R1,%R0\;{addco|add,c,tsv} %2,%1,%0\";
5104 [(set_attr "type" "binary")
5105 (set_attr "length" "8")])
5107 ;; define_splits to optimize cases of adding a constant integer
5108 ;; to a register when the constant does not fit in 14 bits. */
5110 [(set (match_operand:SI 0 "register_operand" "")
5111 (plus:SI (match_operand:SI 1 "register_operand" "")
5112 (match_operand:SI 2 "const_int_operand" "")))
5113 (clobber (match_operand:SI 4 "register_operand" ""))]
5114 "! pa_cint_ok_for_move (INTVAL (operands[2]))
5115 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
5116 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
5117 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
5120 int val = INTVAL (operands[2]);
5121 int low = (val < 0) ? -0x2000 : 0x1fff;
5122 int rest = val - low;
5124 operands[2] = GEN_INT (rest);
5125 operands[3] = GEN_INT (low);
5129 [(set (match_operand:SI 0 "register_operand" "")
5130 (plus:SI (match_operand:SI 1 "register_operand" "")
5131 (match_operand:SI 2 "const_int_operand" "")))
5132 (clobber (match_operand:SI 4 "register_operand" ""))]
5133 "! pa_cint_ok_for_move (INTVAL (operands[2]))"
5134 [(set (match_dup 4) (match_dup 2))
5135 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
5139 HOST_WIDE_INT intval = INTVAL (operands[2]);
5141 /* Try dividing the constant by 2, then 4, and finally 8 to see
5142 if we can get a constant which can be loaded into a register
5143 in a single instruction (pa_cint_ok_for_move).
5145 If that fails, try to negate the constant and subtract it
5146 from our input operand. */
5147 if (intval % 2 == 0 && pa_cint_ok_for_move (intval / 2))
5149 operands[2] = GEN_INT (intval / 2);
5150 operands[3] = const2_rtx;
5152 else if (intval % 4 == 0 && pa_cint_ok_for_move (intval / 4))
5154 operands[2] = GEN_INT (intval / 4);
5155 operands[3] = GEN_INT (4);
5157 else if (intval % 8 == 0 && pa_cint_ok_for_move (intval / 8))
5159 operands[2] = GEN_INT (intval / 8);
5160 operands[3] = GEN_INT (8);
5162 else if (pa_cint_ok_for_move (-intval))
5164 emit_insn (gen_rtx_SET (operands[4], GEN_INT (-intval)));
5165 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
5172 (define_insn "addsi3"
5173 [(set (match_operand:SI 0 "register_operand" "=r,r")
5174 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
5175 (match_operand:SI 2 "arith14_operand" "r,J")))]
5178 {addl|add,l} %1,%2,%0
5180 [(set_attr "type" "binary,binary")
5181 (set_attr "pa_combine_type" "addmove")
5182 (set_attr "length" "4,4")])
5184 (define_insn "addvsi3"
5185 [(set (match_operand:SI 0 "register_operand" "=r,r")
5186 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rM,rM")
5187 (match_operand:SI 2 "arith11_operand" "r,I")))
5188 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
5189 (sign_extend:DI (match_dup 2)))
5190 (sign_extend:DI (plus:SI (match_dup 1)
5195 {addo|add,tsv} %2,%1,%0
5196 {addio|addi,tsv} %2,%1,%0"
5197 [(set_attr "type" "binary,binary")
5198 (set_attr "length" "4,4")])
5200 (define_expand "subdi3"
5201 [(set (match_operand:DI 0 "register_operand" "")
5202 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5203 (match_operand:DI 2 "reg_or_0_operand" "")))]
5208 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
5209 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
5210 (match_operand:DI 2 "reg_or_0_operand" "rM,rM,!rM")))]
5216 [(set_attr "type" "binary,binary,move")
5217 (set_attr "length" "4,4,4")])
5220 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5221 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5222 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))]
5226 if (GET_CODE (operands[1]) == CONST_INT)
5228 if (INTVAL (operands[1]) >= 0)
5229 return \"subi %1,%R2,%R0\;{subb|sub,b} %%r0,%2,%0\";
5231 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subb|sub,b} %0,%2,%0\";
5234 return \"sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0\";
5236 [(set_attr "type" "binary")
5237 (set (attr "length")
5238 (if_then_else (eq_attr "alternative" "0")
5240 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5245 (define_expand "subvdi3"
5246 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5247 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5248 (match_operand:DI 2 "reg_or_0_operand" "")))
5249 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5250 (sign_extend:TI (match_dup 2)))
5251 (sign_extend:TI (minus:DI (match_dup 1)
5258 [(set (match_operand:DI 0 "register_operand" "=r,r")
5259 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5260 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5261 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5262 (sign_extend:TI (match_dup 2)))
5263 (sign_extend:TI (minus:DI (match_dup 1)
5268 {subo|sub,tsv} %1,%2,%0
5269 {subio|subi,tsv} %1,%2,%0"
5270 [(set_attr "type" "binary,binary")
5271 (set_attr "length" "4,4")])
5274 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5275 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5276 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5277 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5278 (sign_extend:TI (match_dup 2)))
5279 (sign_extend:TI (minus:DI (match_dup 1)
5285 if (GET_CODE (operands[1]) == CONST_INT)
5287 if (INTVAL (operands[1]) >= 0)
5288 return \"subi %1,%R2,%R0\;{subbo|sub,b,tsv} %%r0,%2,%0\";
5290 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subbo|sub,b,tsv} %0,%2,%0\";
5293 return \"sub %R1,%R2,%R0\;{subbo|sub,b,tsv} %1,%2,%0\";
5295 [(set_attr "type" "binary,binary")
5296 (set (attr "length")
5297 (if_then_else (eq_attr "alternative" "0")
5299 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5304 (define_expand "subsi3"
5305 [(set (match_operand:SI 0 "register_operand" "")
5306 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5307 (match_operand:SI 2 "register_operand" "")))]
5312 [(set (match_operand:SI 0 "register_operand" "=r,r")
5313 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5314 (match_operand:SI 2 "register_operand" "r,r")))]
5319 [(set_attr "type" "binary,binary")
5320 (set_attr "length" "4,4")])
5323 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5324 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5325 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5331 [(set_attr "type" "binary,binary,move")
5332 (set_attr "length" "4,4,4")])
5334 (define_insn "subvsi3"
5335 [(set (match_operand:SI 0 "register_operand" "=r,r")
5336 (minus:SI (match_operand:SI 1 "arith11_operand" "rM,I")
5337 (match_operand:SI 2 "reg_or_0_operand" "rM,rM")))
5338 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
5339 (sign_extend:DI (match_dup 2)))
5340 (sign_extend:DI (minus:SI (match_dup 1)
5345 {subo|sub,tsv} %1,%2,%0
5346 {subio|subi,tsv} %1,%2,%0"
5347 [(set_attr "type" "binary,binary")
5348 (set_attr "length" "4,4")])
5350 ;; Trap instructions.
5353 [(trap_if (const_int 1) (const_int 0))]
5355 "{addit|addi,tc},<> 1,%%r0,%%r0"
5356 [(set_attr "type" "trap")
5357 (set_attr "length" "4")])
5359 ;; Clobbering a "register_operand" instead of a match_scratch
5360 ;; in operand3 of millicode calls avoids spilling %r1 and
5361 ;; produces better code.
5363 ;; The mulsi3 insns set up registers for the millicode call.
5364 (define_expand "mulsi3"
5365 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5366 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5367 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5368 (clobber (match_dup 3))
5369 (clobber (reg:SI 26))
5370 (clobber (reg:SI 25))
5371 (clobber (match_dup 4))])
5372 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5376 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5377 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5379 rtx scratch = gen_reg_rtx (DImode);
5380 operands[1] = force_reg (SImode, operands[1]);
5381 operands[2] = force_reg (SImode, operands[2]);
5382 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5383 emit_insn (gen_movsi (operands[0],
5384 gen_rtx_SUBREG (SImode, scratch,
5385 GET_MODE_SIZE (SImode))));
5388 operands[3] = gen_reg_rtx (SImode);
5391 (define_insn "umulsidi3"
5392 [(set (match_operand:DI 0 "register_operand" "=f")
5393 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5394 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5395 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5397 [(set_attr "type" "fpmuldbl")
5398 (set_attr "length" "4")])
5401 [(set (match_operand:DI 0 "register_operand" "=f")
5402 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5403 (match_operand:DI 2 "uint32_operand" "f")))]
5404 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5406 [(set_attr "type" "fpmuldbl")
5407 (set_attr "length" "4")])
5410 [(set (match_operand:DI 0 "register_operand" "=f")
5411 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5412 (match_operand:DI 2 "uint32_operand" "f")))]
5413 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5415 [(set_attr "type" "fpmuldbl")
5416 (set_attr "length" "4")])
5419 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5420 (clobber (match_operand:SI 0 "register_operand" "=a"))
5421 (clobber (reg:SI 26))
5422 (clobber (reg:SI 25))
5423 (clobber (reg:SI 31))]
5425 "* return pa_output_mul_insn (0, insn);"
5426 [(set_attr "type" "milli")
5427 (set (attr "length")
5428 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5429 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5432 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5433 (clobber (match_operand:SI 0 "register_operand" "=a"))
5434 (clobber (reg:SI 26))
5435 (clobber (reg:SI 25))
5436 (clobber (reg:SI 2))]
5438 "* return pa_output_mul_insn (0, insn);"
5439 [(set_attr "type" "milli")
5440 (set (attr "length")
5441 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5442 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5444 (define_expand "muldi3"
5445 [(set (match_operand:DI 0 "register_operand" "")
5446 (mult:DI (match_operand:DI 1 "register_operand" "")
5447 (match_operand:DI 2 "register_operand" "")))]
5448 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5451 rtx low_product = gen_reg_rtx (DImode);
5452 rtx cross_product1 = gen_reg_rtx (DImode);
5453 rtx cross_product2 = gen_reg_rtx (DImode);
5454 rtx cross_scratch = gen_reg_rtx (DImode);
5455 rtx cross_product = gen_reg_rtx (DImode);
5456 rtx op1l, op1r, op2l, op2r;
5457 rtx op1shifted, op2shifted;
5459 op1shifted = gen_reg_rtx (DImode);
5460 op2shifted = gen_reg_rtx (DImode);
5461 op1l = gen_reg_rtx (SImode);
5462 op1r = gen_reg_rtx (SImode);
5463 op2l = gen_reg_rtx (SImode);
5464 op2r = gen_reg_rtx (SImode);
5466 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5468 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5470 op1r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[1], 4));
5471 op2r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[2], 4));
5472 op1l = force_reg (SImode, gen_rtx_SUBREG (SImode, op1shifted, 4));
5473 op2l = force_reg (SImode, gen_rtx_SUBREG (SImode, op2shifted, 4));
5475 /* Emit multiplies for the cross products. */
5476 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5477 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5479 /* Emit a multiply for the low sub-word. */
5480 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5482 /* Sum the cross products and shift them into proper position. */
5483 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5484 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5486 /* Add the cross product to the low product and store the result
5487 into the output operand . */
5488 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5492 ;;; Division and mod.
5493 (define_expand "divsi3"
5494 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5495 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5496 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5497 (clobber (match_dup 3))
5498 (clobber (match_dup 4))
5499 (clobber (reg:SI 26))
5500 (clobber (reg:SI 25))
5501 (clobber (match_dup 5))])
5502 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5506 operands[3] = gen_reg_rtx (SImode);
5509 operands[5] = gen_rtx_REG (SImode, 2);
5510 operands[4] = operands[5];
5514 operands[5] = gen_rtx_REG (SImode, 31);
5515 operands[4] = gen_reg_rtx (SImode);
5517 if (GET_CODE (operands[2]) == CONST_INT && pa_emit_hpdiv_const (operands, 0))
5523 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5524 (clobber (match_operand:SI 1 "register_operand" "=a"))
5525 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5526 (clobber (reg:SI 26))
5527 (clobber (reg:SI 25))
5528 (clobber (reg:SI 31))]
5531 return pa_output_div_insn (operands, 0, insn);"
5532 [(set_attr "type" "milli")
5533 (set (attr "length")
5534 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5535 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5539 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5540 (clobber (match_operand:SI 1 "register_operand" "=a"))
5541 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5542 (clobber (reg:SI 26))
5543 (clobber (reg:SI 25))
5544 (clobber (reg:SI 2))]
5547 return pa_output_div_insn (operands, 0, insn);"
5548 [(set_attr "type" "milli")
5549 (set (attr "length")
5550 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5551 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5553 (define_expand "udivsi3"
5554 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5555 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5556 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5557 (clobber (match_dup 3))
5558 (clobber (match_dup 4))
5559 (clobber (reg:SI 26))
5560 (clobber (reg:SI 25))
5561 (clobber (match_dup 5))])
5562 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5566 operands[3] = gen_reg_rtx (SImode);
5570 operands[5] = gen_rtx_REG (SImode, 2);
5571 operands[4] = operands[5];
5575 operands[5] = gen_rtx_REG (SImode, 31);
5576 operands[4] = gen_reg_rtx (SImode);
5578 if (GET_CODE (operands[2]) == CONST_INT && pa_emit_hpdiv_const (operands, 1))
5584 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5585 (clobber (match_operand:SI 1 "register_operand" "=a"))
5586 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5587 (clobber (reg:SI 26))
5588 (clobber (reg:SI 25))
5589 (clobber (reg:SI 31))]
5592 return pa_output_div_insn (operands, 1, insn);"
5593 [(set_attr "type" "milli")
5594 (set (attr "length")
5595 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5596 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5600 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5601 (clobber (match_operand:SI 1 "register_operand" "=a"))
5602 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5603 (clobber (reg:SI 26))
5604 (clobber (reg:SI 25))
5605 (clobber (reg:SI 2))]
5608 return pa_output_div_insn (operands, 1, insn);"
5609 [(set_attr "type" "milli")
5610 (set (attr "length")
5611 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5612 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5614 (define_expand "modsi3"
5615 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5616 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5617 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5618 (clobber (match_dup 3))
5619 (clobber (match_dup 4))
5620 (clobber (reg:SI 26))
5621 (clobber (reg:SI 25))
5622 (clobber (match_dup 5))])
5623 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5629 operands[5] = gen_rtx_REG (SImode, 2);
5630 operands[4] = operands[5];
5634 operands[5] = gen_rtx_REG (SImode, 31);
5635 operands[4] = gen_reg_rtx (SImode);
5637 operands[3] = gen_reg_rtx (SImode);
5641 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5642 (clobber (match_operand:SI 0 "register_operand" "=a"))
5643 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5644 (clobber (reg:SI 26))
5645 (clobber (reg:SI 25))
5646 (clobber (reg:SI 31))]
5649 return pa_output_mod_insn (0, insn);"
5650 [(set_attr "type" "milli")
5651 (set (attr "length")
5652 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5653 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5656 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5657 (clobber (match_operand:SI 0 "register_operand" "=a"))
5658 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5659 (clobber (reg:SI 26))
5660 (clobber (reg:SI 25))
5661 (clobber (reg:SI 2))]
5664 return pa_output_mod_insn (0, insn);"
5665 [(set_attr "type" "milli")
5666 (set (attr "length")
5667 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5668 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5670 (define_expand "umodsi3"
5671 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5672 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5673 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5674 (clobber (match_dup 3))
5675 (clobber (match_dup 4))
5676 (clobber (reg:SI 26))
5677 (clobber (reg:SI 25))
5678 (clobber (match_dup 5))])
5679 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5685 operands[5] = gen_rtx_REG (SImode, 2);
5686 operands[4] = operands[5];
5690 operands[5] = gen_rtx_REG (SImode, 31);
5691 operands[4] = gen_reg_rtx (SImode);
5693 operands[3] = gen_reg_rtx (SImode);
5697 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5698 (clobber (match_operand:SI 0 "register_operand" "=a"))
5699 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5700 (clobber (reg:SI 26))
5701 (clobber (reg:SI 25))
5702 (clobber (reg:SI 31))]
5705 return pa_output_mod_insn (1, insn);"
5706 [(set_attr "type" "milli")
5707 (set (attr "length")
5708 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5709 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5712 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5713 (clobber (match_operand:SI 0 "register_operand" "=a"))
5714 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5715 (clobber (reg:SI 26))
5716 (clobber (reg:SI 25))
5717 (clobber (reg:SI 2))]
5720 return pa_output_mod_insn (1, insn);"
5721 [(set_attr "type" "milli")
5722 (set (attr "length")
5723 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5724 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5726 ;;- and instructions
5727 ;; We define DImode `and` so with DImode `not` we can get
5728 ;; DImode `andn`. Other combinations are possible.
5730 (define_expand "anddi3"
5731 [(set (match_operand:DI 0 "register_operand" "")
5732 (and:DI (match_operand:DI 1 "register_operand" "")
5733 (match_operand:DI 2 "and_operand" "")))]
5738 [(set (match_operand:DI 0 "register_operand" "=r,r")
5739 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
5740 (match_operand:DI 2 "and_operand" "rO,P")))]
5742 "* return pa_output_64bit_and (operands); "
5743 [(set_attr "type" "binary")
5744 (set_attr "length" "4")])
5746 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
5747 ; constant with ldil;ldo.
5748 (define_insn "andsi3"
5749 [(set (match_operand:SI 0 "register_operand" "=r,r")
5750 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
5751 (match_operand:SI 2 "and_operand" "rO,P")))]
5753 "* return pa_output_and (operands); "
5754 [(set_attr "type" "binary,shift")
5755 (set_attr "length" "4,4")])
5758 [(set (match_operand:DI 0 "register_operand" "=r")
5759 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5760 (match_operand:DI 2 "register_operand" "r")))]
5763 [(set_attr "type" "binary")
5764 (set_attr "length" "4")])
5767 [(set (match_operand:SI 0 "register_operand" "=r")
5768 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5769 (match_operand:SI 2 "register_operand" "r")))]
5772 [(set_attr "type" "binary")
5773 (set_attr "length" "4")])
5775 (define_expand "iordi3"
5776 [(set (match_operand:DI 0 "register_operand" "")
5777 (ior:DI (match_operand:DI 1 "register_operand" "")
5778 (match_operand:DI 2 "reg_or_cint_ior_operand" "")))]
5783 [(set (match_operand:DI 0 "register_operand" "=r,r")
5784 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
5785 (match_operand:DI 2 "cint_ior_operand" "M,i")))]
5787 "* return pa_output_64bit_ior (operands); "
5788 [(set_attr "type" "binary,shift")
5789 (set_attr "length" "4,4")])
5792 [(set (match_operand:DI 0 "register_operand" "=r")
5793 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5794 (match_operand:DI 2 "register_operand" "r")))]
5797 [(set_attr "type" "binary")
5798 (set_attr "length" "4")])
5800 ;; Need a define_expand because we've run out of CONST_OK... characters.
5801 (define_expand "iorsi3"
5802 [(set (match_operand:SI 0 "register_operand" "")
5803 (ior:SI (match_operand:SI 1 "register_operand" "")
5804 (match_operand:SI 2 "reg_or_cint_ior_operand" "")))]
5809 [(set (match_operand:SI 0 "register_operand" "=r,r")
5810 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
5811 (match_operand:SI 2 "cint_ior_operand" "M,i")))]
5813 "* return pa_output_ior (operands); "
5814 [(set_attr "type" "binary,shift")
5815 (set_attr "length" "4,4")])
5818 [(set (match_operand:SI 0 "register_operand" "=r")
5819 (ior:SI (match_operand:SI 1 "register_operand" "%r")
5820 (match_operand:SI 2 "register_operand" "r")))]
5823 [(set_attr "type" "binary")
5824 (set_attr "length" "4")])
5826 (define_expand "xordi3"
5827 [(set (match_operand:DI 0 "register_operand" "")
5828 (xor:DI (match_operand:DI 1 "register_operand" "")
5829 (match_operand:DI 2 "register_operand" "")))]
5834 [(set (match_operand:DI 0 "register_operand" "=r")
5835 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5836 (match_operand:DI 2 "register_operand" "r")))]
5839 [(set_attr "type" "binary")
5840 (set_attr "length" "4")])
5842 (define_insn "xorsi3"
5843 [(set (match_operand:SI 0 "register_operand" "=r")
5844 (xor:SI (match_operand:SI 1 "register_operand" "%r")
5845 (match_operand:SI 2 "register_operand" "r")))]
5848 [(set_attr "type" "binary")
5849 (set_attr "length" "4")])
5851 (define_expand "negdi2"
5852 [(set (match_operand:DI 0 "register_operand" "")
5853 (neg:DI (match_operand:DI 1 "register_operand" "")))]
5858 [(set (match_operand:DI 0 "register_operand" "=r")
5859 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5861 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
5862 [(set_attr "type" "unary")
5863 (set_attr "length" "8")])
5866 [(set (match_operand:DI 0 "register_operand" "=r")
5867 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5870 [(set_attr "type" "unary")
5871 (set_attr "length" "4")])
5873 (define_expand "negvdi2"
5874 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5875 (neg:DI (match_operand:DI 1 "register_operand" "")))
5876 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5877 (sign_extend:TI (neg:DI (match_dup 1))))
5883 [(set (match_operand:DI 0 "register_operand" "=r")
5884 (neg:DI (match_operand:DI 1 "register_operand" "r")))
5885 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5886 (sign_extend:TI (neg:DI (match_dup 1))))
5889 "sub %%r0,%R1,%R0\;{subbo|sub,b,tsv} %%r0,%1,%0"
5890 [(set_attr "type" "unary")
5891 (set_attr "length" "8")])
5894 [(set (match_operand:DI 0 "register_operand" "=r")
5895 (neg:DI (match_operand:DI 1 "register_operand" "r")))
5896 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5897 (sign_extend:TI (neg:DI (match_dup 1))))
5900 "sub,tsv %%r0,%1,%0"
5901 [(set_attr "type" "unary")
5902 (set_attr "length" "4")])
5904 (define_insn "negsi2"
5905 [(set (match_operand:SI 0 "register_operand" "=r")
5906 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
5909 [(set_attr "type" "unary")
5910 (set_attr "length" "4")])
5912 (define_insn "negvsi2"
5913 [(set (match_operand:SI 0 "register_operand" "=r")
5914 (neg:SI (match_operand:SI 1 "register_operand" "r")))
5915 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
5916 (sign_extend:DI (neg:SI (match_dup 1))))
5919 "{subo|sub,tsv} %%r0,%1,%0"
5920 [(set_attr "type" "unary")
5921 (set_attr "length" "4")])
5923 (define_expand "one_cmpldi2"
5924 [(set (match_operand:DI 0 "register_operand" "")
5925 (not:DI (match_operand:DI 1 "register_operand" "")))]
5932 [(set (match_operand:DI 0 "register_operand" "=r")
5933 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5935 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
5936 [(set_attr "type" "unary")
5937 (set_attr "length" "8")])
5940 [(set (match_operand:DI 0 "register_operand" "=r")
5941 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5944 [(set_attr "type" "unary")
5945 (set_attr "length" "4")])
5947 (define_insn "one_cmplsi2"
5948 [(set (match_operand:SI 0 "register_operand" "=r")
5949 (not:SI (match_operand:SI 1 "register_operand" "r")))]
5952 [(set_attr "type" "unary")
5953 (set_attr "length" "4")])
5955 ;; Floating point arithmetic instructions.
5957 (define_insn "adddf3"
5958 [(set (match_operand:DF 0 "register_operand" "=f")
5959 (plus:DF (match_operand:DF 1 "register_operand" "f")
5960 (match_operand:DF 2 "register_operand" "f")))]
5961 "! TARGET_SOFT_FLOAT"
5963 [(set_attr "type" "fpalu")
5964 (set_attr "pa_combine_type" "faddsub")
5965 (set_attr "length" "4")])
5967 (define_insn "addsf3"
5968 [(set (match_operand:SF 0 "register_operand" "=f")
5969 (plus:SF (match_operand:SF 1 "register_operand" "f")
5970 (match_operand:SF 2 "register_operand" "f")))]
5971 "! TARGET_SOFT_FLOAT"
5973 [(set_attr "type" "fpalu")
5974 (set_attr "pa_combine_type" "faddsub")
5975 (set_attr "length" "4")])
5977 (define_insn "subdf3"
5978 [(set (match_operand:DF 0 "register_operand" "=f")
5979 (minus:DF (match_operand:DF 1 "register_operand" "f")
5980 (match_operand:DF 2 "register_operand" "f")))]
5981 "! TARGET_SOFT_FLOAT"
5983 [(set_attr "type" "fpalu")
5984 (set_attr "pa_combine_type" "faddsub")
5985 (set_attr "length" "4")])
5987 (define_insn "subsf3"
5988 [(set (match_operand:SF 0 "register_operand" "=f")
5989 (minus:SF (match_operand:SF 1 "register_operand" "f")
5990 (match_operand:SF 2 "register_operand" "f")))]
5991 "! TARGET_SOFT_FLOAT"
5993 [(set_attr "type" "fpalu")
5994 (set_attr "pa_combine_type" "faddsub")
5995 (set_attr "length" "4")])
5997 (define_insn "muldf3"
5998 [(set (match_operand:DF 0 "register_operand" "=f")
5999 (mult:DF (match_operand:DF 1 "register_operand" "f")
6000 (match_operand:DF 2 "register_operand" "f")))]
6001 "! TARGET_SOFT_FLOAT"
6003 [(set_attr "type" "fpmuldbl")
6004 (set_attr "pa_combine_type" "fmpy")
6005 (set_attr "length" "4")])
6007 (define_insn "mulsf3"
6008 [(set (match_operand:SF 0 "register_operand" "=f")
6009 (mult:SF (match_operand:SF 1 "register_operand" "f")
6010 (match_operand:SF 2 "register_operand" "f")))]
6011 "! TARGET_SOFT_FLOAT"
6013 [(set_attr "type" "fpmulsgl")
6014 (set_attr "pa_combine_type" "fmpy")
6015 (set_attr "length" "4")])
6017 (define_insn "divdf3"
6018 [(set (match_operand:DF 0 "register_operand" "=f")
6019 (div:DF (match_operand:DF 1 "register_operand" "f")
6020 (match_operand:DF 2 "register_operand" "f")))]
6021 "! TARGET_SOFT_FLOAT"
6023 [(set_attr "type" "fpdivdbl")
6024 (set_attr "length" "4")])
6026 (define_insn "divsf3"
6027 [(set (match_operand:SF 0 "register_operand" "=f")
6028 (div:SF (match_operand:SF 1 "register_operand" "f")
6029 (match_operand:SF 2 "register_operand" "f")))]
6030 "! TARGET_SOFT_FLOAT"
6032 [(set_attr "type" "fpdivsgl")
6033 (set_attr "length" "4")])
6035 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
6036 ;; negation can be done by subtracting from plus zero. However, this
6037 ;; violates the IEEE standard when negating plus and minus zero.
6038 ;; The slow path toggles the sign bit in the general registers.
6039 (define_expand "negdf2"
6040 [(set (match_operand:DF 0 "register_operand" "")
6041 (neg:DF (match_operand:DF 1 "register_operand" "")))]
6042 "!TARGET_SOFT_FLOAT"
6044 if (TARGET_PA_20 || !flag_signed_zeros)
6045 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
6047 emit_insn (gen_negdf2_slow (operands[0], operands[1]));
6051 (define_insn "negdf2_slow"
6052 [(set (match_operand:DF 0 "register_operand" "=r")
6053 (neg:DF (match_operand:DF 1 "register_operand" "r")))]
6054 "!TARGET_SOFT_FLOAT && !TARGET_PA_20"
6057 if (rtx_equal_p (operands[0], operands[1]))
6058 return \"and,< %1,%1,%0\;depi,tr 1,0,1,%0\;depi 0,0,1,%0\";
6060 return \"and,< %1,%1,%0\;depi,tr 1,0,1,%0\;depi 0,0,1,%0\;copy %R1,%R0\";
6062 [(set_attr "type" "multi")
6063 (set (attr "length")
6064 (if_then_else (match_test "rtx_equal_p (operands[0], operands[1])")
6068 (define_insn "negdf2_fast"
6069 [(set (match_operand:DF 0 "register_operand" "=f")
6070 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
6071 "!TARGET_SOFT_FLOAT"
6075 return \"fneg,dbl %1,%0\";
6077 return \"fsub,dbl %%fr0,%1,%0\";
6079 [(set_attr "type" "fpalu")
6080 (set_attr "length" "4")])
6082 (define_expand "negsf2"
6083 [(set (match_operand:SF 0 "register_operand" "")
6084 (neg:SF (match_operand:SF 1 "register_operand" "")))]
6085 "!TARGET_SOFT_FLOAT"
6087 if (TARGET_PA_20 || !flag_signed_zeros)
6088 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
6090 emit_insn (gen_negsf2_slow (operands[0], operands[1]));
6094 (define_insn "negsf2_slow"
6095 [(set (match_operand:SF 0 "register_operand" "=r")
6096 (neg:SF (match_operand:SF 1 "register_operand" "r")))]
6097 "!TARGET_SOFT_FLOAT && !TARGET_PA_20"
6098 "and,< %1,%1,%0\;depi,tr 1,0,1,%0\;depi 0,0,1,%0"
6099 [(set_attr "type" "multi")
6100 (set_attr "length" "12")])
6102 (define_insn "negsf2_fast"
6103 [(set (match_operand:SF 0 "register_operand" "=f")
6104 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
6105 "!TARGET_SOFT_FLOAT"
6109 return \"fneg,sgl %1,%0\";
6111 return \"fsub,sgl %%fr0,%1,%0\";
6113 [(set_attr "type" "fpalu")
6114 (set_attr "length" "4")])
6116 (define_insn "absdf2"
6117 [(set (match_operand:DF 0 "register_operand" "=f")
6118 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
6119 "! TARGET_SOFT_FLOAT"
6121 [(set_attr "type" "fpalu")
6122 (set_attr "length" "4")])
6124 (define_insn "abssf2"
6125 [(set (match_operand:SF 0 "register_operand" "=f")
6126 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
6127 "! TARGET_SOFT_FLOAT"
6129 [(set_attr "type" "fpalu")
6130 (set_attr "length" "4")])
6132 (define_insn "sqrtdf2"
6133 [(set (match_operand:DF 0 "register_operand" "=f")
6134 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
6135 "! TARGET_SOFT_FLOAT"
6137 [(set_attr "type" "fpsqrtdbl")
6138 (set_attr "length" "4")])
6140 (define_insn "sqrtsf2"
6141 [(set (match_operand:SF 0 "register_operand" "=f")
6142 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
6143 "! TARGET_SOFT_FLOAT"
6145 [(set_attr "type" "fpsqrtsgl")
6146 (set_attr "length" "4")])
6148 ;; PA 2.0 floating point instructions
6151 (define_insn "fmadf4"
6152 [(set (match_operand:DF 0 "register_operand" "=f")
6153 (fma:DF (match_operand:DF 1 "register_operand" "f")
6154 (match_operand:DF 2 "register_operand" "f")
6155 (match_operand:DF 3 "register_operand" "f")))]
6156 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6157 "fmpyfadd,dbl %1,%2,%3,%0"
6158 [(set_attr "type" "fpmuldbl")
6159 (set_attr "length" "4")])
6161 (define_insn "fmasf4"
6162 [(set (match_operand:SF 0 "register_operand" "=f")
6163 (fma:SF (match_operand:SF 1 "register_operand" "f")
6164 (match_operand:SF 2 "register_operand" "f")
6165 (match_operand:SF 3 "register_operand" "f")))]
6166 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6167 "fmpyfadd,sgl %1,%2,%3,%0"
6168 [(set_attr "type" "fpmulsgl")
6169 (set_attr "length" "4")])
6171 ; fmpynfadd patterns
6172 (define_insn "fnmadf4"
6173 [(set (match_operand:DF 0 "register_operand" "=f")
6174 (fma:DF (neg:DF (match_operand:DF 1 "register_operand" "f"))
6175 (match_operand:DF 2 "register_operand" "f")
6176 (match_operand:DF 3 "register_operand" "f")))]
6177 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6178 "fmpynfadd,dbl %1,%2,%3,%0"
6179 [(set_attr "type" "fpmuldbl")
6180 (set_attr "length" "4")])
6182 (define_insn "fnmasf4"
6183 [(set (match_operand:SF 0 "register_operand" "=f")
6184 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
6185 (match_operand:SF 2 "register_operand" "f")
6186 (match_operand:SF 3 "register_operand" "f")))]
6187 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6188 "fmpynfadd,sgl %1,%2,%3,%0"
6189 [(set_attr "type" "fpmulsgl")
6190 (set_attr "length" "4")])
6194 [(set (match_operand:DF 0 "register_operand" "=f")
6195 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
6196 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6198 [(set_attr "type" "fpalu")
6199 (set_attr "length" "4")])
6202 [(set (match_operand:SF 0 "register_operand" "=f")
6203 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
6204 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6206 [(set_attr "type" "fpalu")
6207 (set_attr "length" "4")])
6210 [(set (match_operand:DF 0 "register_operand" "=f")
6211 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6212 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6213 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6214 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6216 [(set_attr "type" "fpalu")
6217 (set_attr "length" "8")])
6220 [(set (match_operand:DF 0 "register_operand" "")
6221 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6222 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6223 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6224 [(set (match_dup 2) (abs:DF (match_dup 1)))
6225 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6229 [(set (match_operand:SF 0 "register_operand" "=f")
6230 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6231 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6232 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6233 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6235 [(set_attr "type" "fpalu")
6236 (set_attr "length" "8")])
6239 [(set (match_operand:SF 0 "register_operand" "")
6240 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6241 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6242 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6243 [(set (match_dup 2) (abs:SF (match_dup 1)))
6244 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6247 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
6248 ;; instruction if we can ignore the sign of zero.
6250 [(set (match_operand:DF 0 "register_operand" "=f")
6251 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6252 (match_operand:DF 2 "register_operand" "f"))))]
6253 "!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros"
6254 "fmpynfadd,dbl %1,%2,%%fr0,%0"
6255 [(set_attr "type" "fpmuldbl")
6256 (set_attr "length" "4")])
6259 [(set (match_operand:SF 0 "register_operand" "=f")
6260 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6261 (match_operand:SF 2 "register_operand" "f"))))]
6262 "!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros"
6263 "fmpynfadd,sgl %1,%2,%%fr0,%0"
6264 [(set_attr "type" "fpmuldbl")
6265 (set_attr "length" "4")])
6268 [(set (match_operand:DF 0 "register_operand" "=f")
6269 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6270 (match_operand:DF 2 "register_operand" "f"))))
6271 (set (match_operand:DF 3 "register_operand" "=&f")
6272 (mult:DF (match_dup 1) (match_dup 2)))]
6273 "(!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros
6274 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6275 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6277 [(set_attr "type" "fpmuldbl")
6278 (set_attr "length" "8")])
6281 [(set (match_operand:DF 0 "register_operand" "")
6282 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6283 (match_operand:DF 2 "register_operand" ""))))
6284 (set (match_operand:DF 3 "register_operand" "")
6285 (mult:DF (match_dup 1) (match_dup 2)))]
6286 "!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros"
6287 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6288 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6292 [(set (match_operand:SF 0 "register_operand" "=f")
6293 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6294 (match_operand:SF 2 "register_operand" "f"))))
6295 (set (match_operand:SF 3 "register_operand" "=&f")
6296 (mult:SF (match_dup 1) (match_dup 2)))]
6297 "(!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros
6298 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6299 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6301 [(set_attr "type" "fpmuldbl")
6302 (set_attr "length" "8")])
6305 [(set (match_operand:SF 0 "register_operand" "")
6306 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6307 (match_operand:SF 2 "register_operand" ""))))
6308 (set (match_operand:SF 3 "register_operand" "")
6309 (mult:SF (match_dup 1) (match_dup 2)))]
6310 "!TARGET_SOFT_FLOAT && TARGET_PA_20&& !flag_signed_zeros"
6311 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6312 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6315 ;;- Shift instructions
6317 ;; Optimized special case of shifting.
6320 [(set (match_operand:SI 0 "register_operand" "=r")
6321 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6325 [(set_attr "type" "load")
6326 (set_attr "length" "4")])
6329 [(set (match_operand:SI 0 "register_operand" "=r")
6330 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6334 [(set_attr "type" "load")
6335 (set_attr "length" "4")])
6338 [(set (match_operand:SI 0 "register_operand" "=r")
6339 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6340 (match_operand:SI 3 "shadd_operand" ""))
6341 (match_operand:SI 1 "register_operand" "r")))]
6343 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6344 [(set_attr "type" "binary")
6345 (set_attr "length" "4")])
6348 [(set (match_operand:DI 0 "register_operand" "=r")
6349 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6350 (match_operand:DI 3 "shadd_operand" ""))
6351 (match_operand:DI 1 "register_operand" "r")))]
6353 "shladd,l %2,%O3,%1,%0"
6354 [(set_attr "type" "binary")
6355 (set_attr "length" "4")])
6357 (define_expand "ashlsi3"
6358 [(set (match_operand:SI 0 "register_operand" "")
6359 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6360 (match_operand:SI 2 "arith32_operand" "")))]
6364 if (GET_CODE (operands[2]) != CONST_INT)
6366 rtx temp = gen_reg_rtx (SImode);
6367 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6368 if (GET_CODE (operands[1]) == CONST_INT)
6369 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6371 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6374 /* Make sure both inputs are not constants,
6375 there are no patterns for that. */
6376 operands[1] = force_reg (SImode, operands[1]);
6380 [(set (match_operand:SI 0 "register_operand" "=r")
6381 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6382 (match_operand:SI 2 "const_int_operand" "n")))]
6384 "{zdep|depw,z} %1,%P2,%L2,%0"
6385 [(set_attr "type" "shift")
6386 (set_attr "length" "4")])
6388 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6389 ; Doing it like this makes slightly better code since reload can
6390 ; replace a register with a known value in range -16..15 with a
6391 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6392 ; but since we have no more CONST_OK... characters, that is not
6394 (define_insn "zvdep32"
6395 [(set (match_operand:SI 0 "register_operand" "=r,r")
6396 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6397 (minus:SI (const_int 31)
6398 (match_operand:SI 2 "register_operand" "q,q"))))]
6401 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6402 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6403 [(set_attr "type" "shift,shift")
6404 (set_attr "length" "4,4")])
6406 (define_insn "zvdep_imm32"
6407 [(set (match_operand:SI 0 "register_operand" "=r")
6408 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6409 (minus:SI (const_int 31)
6410 (match_operand:SI 2 "register_operand" "q"))))]
6414 unsigned HOST_WIDE_INT x = UINTVAL (operands[1]);
6415 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6416 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6417 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6419 [(set_attr "type" "shift")
6420 (set_attr "length" "4")])
6422 (define_insn "vdepi_ior"
6423 [(set (match_operand:SI 0 "register_operand" "=r")
6424 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6425 (minus:SI (const_int 31)
6426 (match_operand:SI 2 "register_operand" "q")))
6427 (match_operand:SI 3 "register_operand" "0")))]
6428 ; accept ...0001...1, can this be generalized?
6429 "exact_log2 (INTVAL (operands[1]) + 1) > 0"
6432 HOST_WIDE_INT x = INTVAL (operands[1]);
6433 operands[2] = GEN_INT (exact_log2 (x + 1));
6434 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6436 [(set_attr "type" "shift")
6437 (set_attr "length" "4")])
6439 (define_insn "vdepi_and"
6440 [(set (match_operand:SI 0 "register_operand" "=r")
6441 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6442 (minus:SI (const_int 31)
6443 (match_operand:SI 2 "register_operand" "q")))
6444 (match_operand:SI 3 "register_operand" "0")))]
6445 ; this can be generalized...!
6446 "INTVAL (operands[1]) == -2"
6449 HOST_WIDE_INT x = INTVAL (operands[1]);
6450 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6451 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
6453 [(set_attr "type" "shift")
6454 (set_attr "length" "4")])
6456 (define_expand "ashldi3"
6457 [(set (match_operand:DI 0 "register_operand" "")
6458 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
6459 (match_operand:DI 2 "arith32_operand" "")))]
6463 if (GET_CODE (operands[2]) != CONST_INT)
6465 rtx temp = gen_reg_rtx (DImode);
6466 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6467 if (GET_CODE (operands[1]) == CONST_INT)
6468 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
6470 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
6473 /* Make sure both inputs are not constants,
6474 there are no patterns for that. */
6475 operands[1] = force_reg (DImode, operands[1]);
6479 [(set (match_operand:DI 0 "register_operand" "=r")
6480 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6481 (match_operand:DI 2 "const_int_operand" "n")))]
6483 "depd,z %1,%p2,%Q2,%0"
6484 [(set_attr "type" "shift")
6485 (set_attr "length" "4")])
6487 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
6488 ; Doing it like this makes slightly better code since reload can
6489 ; replace a register with a known value in range -16..15 with a
6490 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
6491 ; but since we have no more CONST_OK... characters, that is not
6493 (define_insn "zvdep64"
6494 [(set (match_operand:DI 0 "register_operand" "=r,r")
6495 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
6496 (minus:DI (const_int 63)
6497 (match_operand:DI 2 "register_operand" "q,q"))))]
6500 depd,z %1,%%sar,64,%0
6501 depdi,z %1,%%sar,64,%0"
6502 [(set_attr "type" "shift,shift")
6503 (set_attr "length" "4,4")])
6505 (define_insn "zvdep_imm64"
6506 [(set (match_operand:DI 0 "register_operand" "=r")
6507 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
6508 (minus:DI (const_int 63)
6509 (match_operand:DI 2 "register_operand" "q"))))]
6513 unsigned HOST_WIDE_INT x = UINTVAL (operands[1]);
6514 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6515 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
6516 return \"depdi,z %1,%%sar,%2,%0\";
6518 [(set_attr "type" "shift")
6519 (set_attr "length" "4")])
6522 [(set (match_operand:DI 0 "register_operand" "=r")
6523 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
6524 (minus:DI (const_int 63)
6525 (match_operand:DI 2 "register_operand" "q")))
6526 (match_operand:DI 3 "register_operand" "0")))]
6527 ; accept ...0001...1, can this be generalized?
6528 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) > 0"
6531 HOST_WIDE_INT x = INTVAL (operands[1]);
6532 operands[2] = GEN_INT (exact_log2 (x + 1));
6533 return \"depdi -1,%%sar,%2,%0\";
6535 [(set_attr "type" "shift")
6536 (set_attr "length" "4")])
6539 [(set (match_operand:DI 0 "register_operand" "=r")
6540 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
6541 (minus:DI (const_int 63)
6542 (match_operand:DI 2 "register_operand" "q")))
6543 (match_operand:DI 3 "register_operand" "0")))]
6544 ; this can be generalized...!
6545 "TARGET_64BIT && INTVAL (operands[1]) == -2"
6548 HOST_WIDE_INT x = INTVAL (operands[1]);
6549 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6550 return \"depdi 0,%%sar,%2,%0\";
6552 [(set_attr "type" "shift")
6553 (set_attr "length" "4")])
6555 (define_expand "ashrsi3"
6556 [(set (match_operand:SI 0 "register_operand" "")
6557 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
6558 (match_operand:SI 2 "arith32_operand" "")))]
6562 if (GET_CODE (operands[2]) != CONST_INT)
6564 rtx temp = gen_reg_rtx (SImode);
6565 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6566 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
6572 [(set (match_operand:SI 0 "register_operand" "=r")
6573 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6574 (match_operand:SI 2 "const_int_operand" "n")))]
6576 "{extrs|extrw,s} %1,%P2,%L2,%0"
6577 [(set_attr "type" "shift")
6578 (set_attr "length" "4")])
6580 (define_insn "vextrs32"
6581 [(set (match_operand:SI 0 "register_operand" "=r")
6582 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6583 (minus:SI (const_int 31)
6584 (match_operand:SI 2 "register_operand" "q"))))]
6586 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
6587 [(set_attr "type" "shift")
6588 (set_attr "length" "4")])
6590 (define_expand "ashrdi3"
6591 [(set (match_operand:DI 0 "register_operand" "")
6592 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6593 (match_operand:DI 2 "arith32_operand" "")))]
6597 if (GET_CODE (operands[2]) != CONST_INT)
6599 rtx temp = gen_reg_rtx (DImode);
6600 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6601 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
6607 [(set (match_operand:DI 0 "register_operand" "=r")
6608 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6609 (match_operand:DI 2 "const_int_operand" "n")))]
6611 "extrd,s %1,%p2,%Q2,%0"
6612 [(set_attr "type" "shift")
6613 (set_attr "length" "4")])
6615 (define_insn "vextrs64"
6616 [(set (match_operand:DI 0 "register_operand" "=r")
6617 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6618 (minus:DI (const_int 63)
6619 (match_operand:DI 2 "register_operand" "q"))))]
6621 "extrd,s %1,%%sar,64,%0"
6622 [(set_attr "type" "shift")
6623 (set_attr "length" "4")])
6625 (define_insn "lshrsi3"
6626 [(set (match_operand:SI 0 "register_operand" "=r,r")
6627 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
6628 (match_operand:SI 2 "shift5_operand" "q,n")))]
6631 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
6632 {extru|extrw,u} %1,%P2,%L2,%0"
6633 [(set_attr "type" "shift")
6634 (set_attr "length" "4")])
6636 (define_insn "lshrdi3"
6637 [(set (match_operand:DI 0 "register_operand" "=r,r")
6638 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
6639 (match_operand:DI 2 "shift6_operand" "q,n")))]
6642 shrpd %%r0,%1,%%sar,%0
6643 extrd,u %1,%p2,%Q2,%0"
6644 [(set_attr "type" "shift")
6645 (set_attr "length" "4")])
6647 ; Shift right pair word 0 to 31 bits.
6648 (define_insn "shrpsi4"
6649 [(set (match_operand:SI 0 "register_operand" "=r,r")
6650 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
6651 (minus:SI (const_int 32)
6652 (match_operand:SI 3 "shift5_operand" "q,n")))
6653 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r,r")
6657 {vshd %1,%2,%0|shrpw %1,%2,%%sar,%0}
6658 {shd|shrpw} %1,%2,%3,%0"
6659 [(set_attr "type" "shift")
6660 (set_attr "length" "4")])
6662 ; Shift right pair doubleword 0 to 63 bits.
6663 (define_insn "shrpdi4"
6664 [(set (match_operand:DI 0 "register_operand" "=r,r")
6665 (ior:DI (ashift:DI (match_operand:SI 1 "register_operand" "r,r")
6666 (minus:DI (const_int 64)
6667 (match_operand:DI 3 "shift6_operand" "q,n")))
6668 (lshiftrt:DI (match_operand:DI 2 "register_operand" "r,r")
6672 shrpd %1,%2,%%sar,%0
6674 [(set_attr "type" "shift")
6675 (set_attr "length" "4")])
6677 (define_insn "rotrsi3"
6678 [(set (match_operand:SI 0 "register_operand" "=r,r")
6679 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
6680 (match_operand:SI 2 "shift5_operand" "q,n")))]
6684 if (GET_CODE (operands[2]) == CONST_INT)
6686 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
6687 return \"{shd|shrpw} %1,%1,%2,%0\";
6690 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
6692 [(set_attr "type" "shift")
6693 (set_attr "length" "4")])
6695 (define_expand "rotlsi3"
6696 [(set (match_operand:SI 0 "register_operand" "")
6697 (rotate:SI (match_operand:SI 1 "register_operand" "")
6698 (match_operand:SI 2 "arith32_operand" "")))]
6702 if (GET_CODE (operands[2]) != CONST_INT)
6704 rtx temp = gen_reg_rtx (SImode);
6705 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
6706 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
6709 /* Else expand normally. */
6713 [(set (match_operand:SI 0 "register_operand" "=r")
6714 (rotate:SI (match_operand:SI 1 "register_operand" "r")
6715 (match_operand:SI 2 "const_int_operand" "n")))]
6719 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
6720 return \"{shd|shrpw} %1,%1,%2,%0\";
6722 [(set_attr "type" "shift")
6723 (set_attr "length" "4")])
6726 [(set (match_operand:SI 0 "register_operand" "=r")
6727 (match_operator:SI 5 "plus_xor_ior_operator"
6728 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
6729 (match_operand:SI 3 "const_int_operand" "n"))
6730 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6731 (match_operand:SI 4 "const_int_operand" "n"))]))]
6732 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6733 "{shd|shrpw} %1,%2,%4,%0"
6734 [(set_attr "type" "shift")
6735 (set_attr "length" "4")])
6738 [(set (match_operand:SI 0 "register_operand" "=r")
6739 (match_operator:SI 5 "plus_xor_ior_operator"
6740 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6741 (match_operand:SI 4 "const_int_operand" "n"))
6742 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6743 (match_operand:SI 3 "const_int_operand" "n"))]))]
6744 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6745 "{shd|shrpw} %1,%2,%4,%0"
6746 [(set_attr "type" "shift")
6747 (set_attr "length" "4")])
6750 [(set (match_operand:SI 0 "register_operand" "=r")
6751 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
6752 (match_operand:SI 2 "const_int_operand" ""))
6753 (match_operand:SI 3 "const_int_operand" "")))]
6754 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) > 0"
6757 int cnt = INTVAL (operands[2]) & 31;
6758 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
6759 operands[2] = GEN_INT (31 - cnt);
6760 return \"{zdep|depw,z} %1,%2,%3,%0\";
6762 [(set_attr "type" "shift")
6763 (set_attr "length" "4")])
6765 ;; Unconditional and other jump instructions.
6767 ;; Trivial return used when no epilogue is needed.
6768 (define_insn "return"
6771 "pa_can_use_return_insn ()"
6775 return \"bve%* (%%r2)\";
6776 return \"bv%* %%r0(%%r2)\";
6778 [(set_attr "type" "branch")
6779 (set_attr "length" "4")])
6781 ;; This is used for most returns.
6782 (define_insn "return_internal"
6789 return \"bve%* (%%r2)\";
6790 return \"bv%* %%r0(%%r2)\";
6792 [(set_attr "type" "branch")
6793 (set_attr "length" "4")])
6795 ;; This is used for eh returns which bypass the return stub.
6796 (define_insn "return_external_pic"
6798 (clobber (reg:SI 1))
6800 "!TARGET_NO_SPACE_REGS
6802 && flag_pic && crtl->calls_eh_return"
6803 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
6804 [(set_attr "type" "branch")
6805 (set_attr "length" "12")])
6807 (define_expand "prologue"
6810 "pa_expand_prologue ();DONE;")
6812 (define_expand "sibcall_epilogue"
6817 pa_expand_epilogue ();
6821 (define_expand "epilogue"
6828 /* Try to use the trivial return first. Else use the full epilogue. */
6829 if (pa_can_use_return_insn ())
6833 pa_expand_epilogue ();
6835 /* EH returns bypass the normal return stub. Thus, we must do an
6836 interspace branch to return from functions that call eh_return.
6837 This is only a problem for returns from shared code on ports
6838 using space registers. */
6839 if (!TARGET_NO_SPACE_REGS
6841 && flag_pic && crtl->calls_eh_return)
6842 x = gen_return_external_pic ();
6844 x = gen_return_internal ();
6850 ; Used by hppa_profile_hook to load the starting address of the current
6851 ; function; operand 1 contains the address of the label in operand 3
6852 (define_insn "load_offset_label_address"
6853 [(set (match_operand:SI 0 "register_operand" "=r")
6854 (plus:SI (match_operand:SI 1 "register_operand" "r")
6855 (minus:SI (match_operand:SI 2 "" "")
6856 (label_ref:SI (match_operand 3 "" "")))))]
6859 [(set_attr "type" "multi")
6860 (set_attr "length" "4")])
6862 ; Output a code label and load its address.
6863 (define_insn "lcla1"
6864 [(set (match_operand:SI 0 "register_operand" "=r")
6865 (label_ref:SI (match_operand 1 "" "")))
6870 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
6871 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6872 CODE_LABEL_NUMBER (operands[1]));
6875 [(set_attr "type" "multi")
6876 (set_attr "length" "8")])
6878 (define_insn "lcla2"
6879 [(set (match_operand:SI 0 "register_operand" "=r")
6880 (label_ref:SI (match_operand 1 "" "")))
6885 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6886 CODE_LABEL_NUMBER (operands[1]));
6889 [(set_attr "type" "move")
6890 (set_attr "length" "4")])
6892 (define_insn "blockage"
6893 [(unspec_volatile [(const_int 2)] UNSPECV_BLOCKAGE)]
6896 [(set_attr "length" "0")])
6899 [(set (pc) (label_ref (match_operand 0 "" "")))]
6903 /* An unconditional branch which can reach its target. */
6904 if (get_attr_length (insn) < 16)
6907 return pa_output_lbranch (operands[0], insn, 1);
6909 [(set_attr "type" "uncond_branch")
6910 (set_attr "pa_combine_type" "uncond_branch")
6911 (set (attr "length")
6912 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
6913 (const_int MAX_17BIT_OFFSET))
6915 (match_test "TARGET_PORTABLE_RUNTIME")
6917 (not (match_test "flag_pic"))
6921 ;;; Hope this is only within a function...
6922 (define_insn "indirect_jump"
6923 [(set (pc) (match_operand 0 "register_operand" "r"))]
6924 "GET_MODE (operands[0]) == word_mode"
6926 [(set_attr "type" "branch")
6927 (set_attr "length" "4")])
6929 ;;; An indirect jump can be optimized to a direct jump. GAS for the
6930 ;;; SOM target doesn't allow branching to a label inside a function.
6931 ;;; We also don't correctly compute branch distances for labels
6932 ;;; outside the current function. Thus, we use an indirect jump can't
6933 ;;; be optimized to a direct jump for all targets. We assume that
6934 ;;; the branch target is in the same space (i.e., nested function
6935 ;;; jumping to a label in an outer function in the same translation
6937 (define_expand "nonlocal_goto"
6938 [(use (match_operand 0 "general_operand" ""))
6939 (use (match_operand 1 "general_operand" ""))
6940 (use (match_operand 2 "general_operand" ""))
6941 (use (match_operand 3 "general_operand" ""))]
6944 rtx lab = operands[1];
6945 rtx stack = operands[2];
6946 rtx fp = operands[3];
6948 lab = copy_to_reg (lab);
6950 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
6951 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
6953 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
6954 instead of the hard_frame_pointer_rtx in the save area. As a
6955 result, an extra instruction is needed to adjust for the offset
6956 of the virtual stack variables and the hard frame pointer. */
6957 if (GET_CODE (fp) != REG)
6958 fp = force_reg (Pmode, fp);
6959 emit_move_insn (hard_frame_pointer_rtx, plus_constant (Pmode, fp, -8));
6961 emit_stack_restore (SAVE_NONLOCAL, stack);
6963 emit_use (hard_frame_pointer_rtx);
6964 emit_use (stack_pointer_rtx);
6966 /* Nonlocal goto jumps are only used between functions in the same
6967 translation unit. Thus, we can avoid the extra overhead of an
6969 emit_jump_insn (gen_indirect_goto (lab));
6974 (define_insn "indirect_goto"
6975 [(unspec [(match_operand 0 "register_operand" "=r")] UNSPEC_GOTO)]
6976 "GET_MODE (operands[0]) == word_mode"
6978 [(set_attr "type" "branch")
6979 (set_attr "length" "4")])
6981 ;; Subroutines of "casesi".
6982 ;; operand 0 is index
6983 ;; operand 1 is the minimum bound
6984 ;; operand 2 is the maximum bound - minimum bound + 1
6985 ;; operand 3 is CODE_LABEL for the table;
6986 ;; operand 4 is the CODE_LABEL to go to if index out of range.
6988 (define_expand "casesi"
6989 [(match_operand:SI 0 "general_operand" "")
6990 (match_operand:SI 1 "const_int_operand" "")
6991 (match_operand:SI 2 "const_int_operand" "")
6992 (match_operand 3 "" "")
6993 (match_operand 4 "" "")]
6997 if (GET_CODE (operands[0]) != REG)
6998 operands[0] = force_reg (SImode, operands[0]);
7000 if (operands[1] != const0_rtx)
7002 rtx index = gen_reg_rtx (SImode);
7004 operands[1] = gen_int_mode (-INTVAL (operands[1]), SImode);
7005 if (!INT_14_BITS (operands[1]))
7006 operands[1] = force_reg (SImode, operands[1]);
7007 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
7008 operands[0] = index;
7011 if (!INT_5_BITS (operands[2]))
7012 operands[2] = force_reg (SImode, operands[2]);
7014 /* This branch prevents us finding an insn for the delay slot of the
7015 following vectored branch. It might be possible to use the delay
7016 slot if an index value of -1 was used to transfer to the out-of-range
7017 label. In order to do this, we would have to output the -1 vector
7018 element after the delay insn. The casesi output code would have to
7019 check if the casesi insn is in a delay branch sequence and output
7020 the delay insn if one is found. If this was done, then it might
7021 then be worthwhile to split the casesi patterns to improve scheduling.
7022 However, it's not clear that all this extra complexity is worth
7025 rtx test = gen_rtx_GTU (VOIDmode, operands[0], operands[2]);
7026 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4]));
7029 /* In 64bit mode we must make sure to wipe the upper bits of the register
7030 just in case the addition overflowed or we had random bits in the
7031 high part of the register. */
7034 rtx index = gen_reg_rtx (DImode);
7036 emit_insn (gen_extendsidi2 (index, operands[0]));
7037 operands[0] = index;
7041 emit_jump_insn (gen_casesi64p (operands[0], operands[3]));
7043 emit_jump_insn (gen_casesi32p (operands[0], operands[3]));
7045 emit_jump_insn (gen_casesi32 (operands[0], operands[3]));
7049 ;;; 32-bit code, absolute branch table.
7050 (define_insn "casesi32"
7051 [(set (pc) (mem:SI (plus:SI
7052 (mult:SI (match_operand:SI 0 "register_operand" "r")
7054 (label_ref (match_operand 1 "" "")))))
7055 (clobber (match_scratch:SI 2 "=&r"))]
7057 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
7058 [(set_attr "type" "multi")
7059 (set_attr "length" "16")])
7061 ;;; 32-bit code, relative branch table.
7062 (define_insn "casesi32p"
7063 [(set (pc) (mem:SI (plus:SI
7064 (mult:SI (match_operand:SI 0 "register_operand" "r")
7066 (label_ref (match_operand 1 "" "")))))
7067 (clobber (match_scratch:SI 2 "=&r"))
7068 (clobber (match_scratch:SI 3 "=&r"))]
7070 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {%l1-.|%l1+4-.}(%2),%2\;\
7071 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
7072 [(set_attr "type" "multi")
7073 (set (attr "length")
7074 (if_then_else (match_test "TARGET_PA_20")
7078 ;;; 64-bit code, 32-bit relative branch table.
7079 (define_insn "casesi64p"
7080 [(set (pc) (mem:DI (plus:DI
7081 (mult:DI (match_operand:DI 0 "register_operand" "r")
7083 (label_ref (match_operand 1 "" "")))))
7084 (clobber (match_scratch:DI 2 "=&r"))
7085 (clobber (match_scratch:DI 3 "=&r"))]
7087 "mfia %2\;ldo %l1+4-.(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
7088 add,l %2,%3,%3\;bv,n %%r0(%3)"
7089 [(set_attr "type" "multi")
7090 (set_attr "length" "24")])
7094 ;;- jump to subroutine
7096 (define_expand "call"
7097 [(parallel [(call (match_operand:SI 0 "" "")
7098 (match_operand 1 "" ""))
7099 (clobber (reg:SI 2))])]
7104 rtx nb = operands[1];
7106 if (TARGET_PORTABLE_RUNTIME)
7107 op = force_reg (SImode, XEXP (operands[0], 0));
7110 op = XEXP (operands[0], 0);
7112 /* Generate indirect long calls to non-local functions. */
7113 if (!TARGET_64BIT && TARGET_LONG_CALLS && GET_CODE (op) == SYMBOL_REF)
7115 tree call_decl = SYMBOL_REF_DECL (op);
7116 if (!(call_decl && targetm.binds_local_p (call_decl)))
7117 op = force_reg (word_mode, op);
7123 if (!virtuals_instantiated)
7124 emit_move_insn (arg_pointer_rtx,
7125 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7129 /* The loop pass can generate new libcalls after the virtual
7130 registers are instantiated when fpregs are disabled because
7131 the only method that we have for doing DImode multiplication
7132 is with a libcall. This could be trouble if we haven't
7133 allocated enough space for the outgoing arguments. */
7134 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
7136 emit_move_insn (arg_pointer_rtx,
7137 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7138 GEN_INT (STACK_POINTER_OFFSET + 64)));
7142 /* Use two different patterns for calls to explicitly named functions
7143 and calls through function pointers. This is necessary as these two
7144 types of calls use different calling conventions, and CSE might try
7145 to change the named call into an indirect call in some cases (using
7146 two patterns keeps CSE from performing this optimization).
7148 We now use even more call patterns as there was a subtle bug in
7149 attempting to restore the pic register after a call using a simple
7150 move insn. During reload, a instruction involving a pseudo register
7151 with no explicit dependence on the PIC register can be converted
7152 to an equivalent load from memory using the PIC register. If we
7153 emit a simple move to restore the PIC register in the initial rtl
7154 generation, then it can potentially be repositioned during scheduling.
7155 and an instruction that eventually uses the PIC register may end up
7156 between the call and the PIC register restore.
7158 This only worked because there is a post call group of instructions
7159 that are scheduled with the call. These instructions are included
7160 in the same basic block as the call. However, calls can throw in
7161 C++ code and a basic block has to terminate at the call if the call
7162 can throw. This results in the PIC register restore being scheduled
7163 independently from the call. So, we now hide the save and restore
7164 of the PIC register in the call pattern until after reload. Then,
7165 we split the moves out. A small side benefit is that we now don't
7166 need to have a use of the PIC register in the return pattern and
7167 the final save/restore operation is not needed.
7169 I elected to just use register %r4 in the PIC patterns instead
7170 of trying to force hppa_pic_save_rtx () to a callee saved register.
7171 This might have required a new register class and constraint. It
7172 was also simpler to just handle the restore from a register than a
7176 rtx r4 = gen_rtx_REG (word_mode, 4);
7177 if (GET_CODE (op) == SYMBOL_REF)
7178 emit_call_insn (gen_call_symref_64bit (op, nb, r4));
7181 op = force_reg (word_mode, op);
7182 emit_call_insn (gen_call_reg_64bit (op, nb, r4));
7187 if (GET_CODE (op) == SYMBOL_REF)
7191 rtx r4 = gen_rtx_REG (word_mode, 4);
7192 emit_call_insn (gen_call_symref_pic (op, nb, r4));
7195 emit_call_insn (gen_call_symref (op, nb));
7199 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7200 emit_move_insn (tmpreg, force_reg (word_mode, op));
7203 rtx r4 = gen_rtx_REG (word_mode, 4);
7204 emit_call_insn (gen_call_reg_pic (nb, r4));
7207 emit_call_insn (gen_call_reg (nb));
7214 ;; We use function calls to set the attribute length of calls and millicode
7215 ;; calls. This is necessary because of the large variety of call sequences.
7216 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7217 ;; we need the same calculation in several places, maintenance becomes a
7220 ;; However, this has a subtle impact on branch shortening. When the
7221 ;; expression used to set the length attribute of an instruction depends
7222 ;; on a relative address (e.g., pc or a branch address), genattrtab
7223 ;; notes that the insn's length is variable, and attempts to determine a
7224 ;; worst-case default length and code to compute an insn's current length.
7226 ;; The use of a function call hides the variable dependence of our calls
7227 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7228 ;; as variable and it only generates code for the default case using our
7229 ;; function call. Because of this, calls and millicode calls have a fixed
7230 ;; length in the branch shortening pass, and some branches will use a longer
7231 ;; code sequence than necessary. However, the length of any given call
7232 ;; will still reflect its final code location and it may be shorter than
7233 ;; the initial length estimate.
7235 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7236 ;; in the set. However, when genattrtab hits a function call in its attempt
7237 ;; to compute the default length, it marks the result as unknown and sets
7238 ;; the default result to MAX_INT ;-( One possible fix that would allow
7239 ;; calls to participate in branch shortening would be to make the call to
7240 ;; insn_default_length a target option. Then, we could massage unknown
7241 ;; results. Another fix might be to change genattrtab so that it just does
7242 ;; the call in the variable case as it already does for the fixed case.
7244 (define_insn "call_symref"
7245 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7246 (match_operand 1 "" "i"))
7247 (clobber (reg:SI 1))
7248 (clobber (reg:SI 2))
7249 (use (const_int 0))]
7250 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7253 pa_output_arg_descriptor (insn);
7254 return pa_output_call (insn, operands[0], 0);
7256 [(set_attr "type" "call")
7257 (set (attr "length")
7258 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7259 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7261 (define_insn "call_symref_pic"
7262 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7263 (match_operand 1 "" "i"))
7264 (clobber (reg:SI 1))
7265 (clobber (reg:SI 2))
7266 (clobber (match_operand 2))
7268 (use (const_int 0))]
7269 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7272 ;; Split out the PIC register save and restore after reload. As the
7273 ;; split is done after reload, there are some situations in which we
7274 ;; unnecessarily save and restore %r4. This happens when there is a
7275 ;; single call and the PIC register is not used after the call.
7277 ;; The split has to be done since call_from_call_insn () can't handle
7278 ;; the pattern as is. Noreturn calls are special because they have to
7279 ;; terminate the basic block. The split has to contain more than one
7282 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7283 (match_operand 1 "" ""))
7284 (clobber (reg:SI 1))
7285 (clobber (reg:SI 2))
7286 (clobber (match_operand 2))
7288 (use (const_int 0))])]
7289 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed
7290 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7291 [(set (match_dup 2) (reg:SI 19))
7292 (parallel [(call (mem:SI (match_dup 0))
7294 (clobber (reg:SI 1))
7295 (clobber (reg:SI 2))
7297 (use (const_int 0))])]
7301 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7302 (match_operand 1 "" ""))
7303 (clobber (reg:SI 1))
7304 (clobber (reg:SI 2))
7305 (clobber (match_operand 2))
7307 (use (const_int 0))])]
7308 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7309 [(set (match_dup 2) (reg:SI 19))
7310 (parallel [(call (mem:SI (match_dup 0))
7312 (clobber (reg:SI 1))
7313 (clobber (reg:SI 2))
7315 (use (const_int 0))])
7316 (set (reg:SI 19) (match_dup 2))]
7319 (define_insn "*call_symref_pic_post_reload"
7320 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7321 (match_operand 1 "" "i"))
7322 (clobber (reg:SI 1))
7323 (clobber (reg:SI 2))
7325 (use (const_int 0))]
7326 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7329 pa_output_arg_descriptor (insn);
7330 return pa_output_call (insn, operands[0], 0);
7332 [(set_attr "type" "call")
7333 (set (attr "length")
7334 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7335 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7337 ;; This pattern is split if it is necessary to save and restore the
7339 (define_insn "call_symref_64bit"
7340 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7341 (match_operand 1 "" "i"))
7342 (clobber (reg:DI 1))
7343 (clobber (reg:DI 2))
7344 (clobber (match_operand 2))
7347 (use (const_int 0))]
7351 ;; Split out the PIC register save and restore after reload. As the
7352 ;; split is done after reload, there are some situations in which we
7353 ;; unnecessarily save and restore %r4. This happens when there is a
7354 ;; single call and the PIC register is not used after the call.
7356 ;; The split has to be done since call_from_call_insn () can't handle
7357 ;; the pattern as is. Noreturn calls are special because they have to
7358 ;; terminate the basic block. The split has to contain more than one
7361 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7362 (match_operand 1 "" ""))
7363 (clobber (reg:DI 1))
7364 (clobber (reg:DI 2))
7365 (clobber (match_operand 2))
7368 (use (const_int 0))])]
7369 "TARGET_64BIT && reload_completed
7370 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7371 [(set (match_dup 2) (reg:DI 27))
7372 (parallel [(call (mem:SI (match_dup 0))
7374 (clobber (reg:DI 1))
7375 (clobber (reg:DI 2))
7378 (use (const_int 0))])]
7382 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7383 (match_operand 1 "" ""))
7384 (clobber (reg:DI 1))
7385 (clobber (reg:DI 2))
7386 (clobber (match_operand 2))
7389 (use (const_int 0))])]
7390 "TARGET_64BIT && reload_completed"
7391 [(set (match_dup 2) (reg:DI 27))
7392 (parallel [(call (mem:SI (match_dup 0))
7394 (clobber (reg:DI 1))
7395 (clobber (reg:DI 2))
7398 (use (const_int 0))])
7399 (set (reg:DI 27) (match_dup 2))]
7402 (define_insn "*call_symref_64bit_post_reload"
7403 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7404 (match_operand 1 "" "i"))
7405 (clobber (reg:DI 1))
7406 (clobber (reg:DI 2))
7409 (use (const_int 0))]
7413 pa_output_arg_descriptor (insn);
7414 return pa_output_call (insn, operands[0], 0);
7416 [(set_attr "type" "call")
7417 (set (attr "length")
7418 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7419 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7421 (define_insn "call_reg"
7422 [(call (mem:SI (reg:SI 22))
7423 (match_operand 0 "" "i"))
7424 (clobber (reg:SI 1))
7425 (clobber (reg:SI 2))
7426 (use (const_int 1))]
7430 return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7432 [(set_attr "type" "dyncall")
7433 (set (attr "length")
7434 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7435 (symbol_ref "pa_attr_length_indirect_call (insn)")))])
7437 ;; This pattern is split if it is necessary to save and restore the
7439 (define_insn "call_reg_pic"
7440 [(call (mem:SI (reg:SI 22))
7441 (match_operand 0 "" "i"))
7442 (clobber (reg:SI 1))
7443 (clobber (reg:SI 2))
7444 (clobber (match_operand 1))
7446 (use (const_int 1))]
7450 ;; Split out the PIC register save and restore after reload. As the
7451 ;; split is done after reload, there are some situations in which we
7452 ;; unnecessarily save and restore %r4. This happens when there is a
7453 ;; single call and the PIC register is not used after the call.
7455 ;; The split has to be done since call_from_call_insn () can't handle
7456 ;; the pattern as is. Noreturn calls are special because they have to
7457 ;; terminate the basic block. The split has to contain more than one
7460 [(parallel [(call (mem:SI (reg:SI 22))
7461 (match_operand 0 "" ""))
7462 (clobber (reg:SI 1))
7463 (clobber (reg:SI 2))
7464 (clobber (match_operand 1))
7466 (use (const_int 1))])]
7467 "!TARGET_64BIT && reload_completed
7468 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7469 [(set (match_dup 1) (reg:SI 19))
7470 (parallel [(call (mem:SI (reg:SI 22))
7472 (clobber (reg:SI 1))
7473 (clobber (reg:SI 2))
7475 (use (const_int 1))])]
7479 [(parallel [(call (mem:SI (reg:SI 22))
7480 (match_operand 0 "" ""))
7481 (clobber (reg:SI 1))
7482 (clobber (reg:SI 2))
7483 (clobber (match_operand 1))
7485 (use (const_int 1))])]
7486 "!TARGET_64BIT && reload_completed"
7487 [(set (match_dup 1) (reg:SI 19))
7488 (parallel [(call (mem:SI (reg:SI 22))
7490 (clobber (reg:SI 1))
7491 (clobber (reg:SI 2))
7493 (use (const_int 1))])
7494 (set (reg:SI 19) (match_dup 1))]
7497 (define_insn "*call_reg_pic_post_reload"
7498 [(call (mem:SI (reg:SI 22))
7499 (match_operand 0 "" "i"))
7500 (clobber (reg:SI 1))
7501 (clobber (reg:SI 2))
7503 (use (const_int 1))]
7507 return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7509 [(set_attr "type" "dyncall")
7510 (set (attr "length")
7511 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7512 (symbol_ref "pa_attr_length_indirect_call (insn)")))])
7514 ;; This pattern is split if it is necessary to save and restore the
7516 (define_insn "call_reg_64bit"
7517 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7518 (match_operand 1 "" "i"))
7519 (clobber (reg:DI 1))
7520 (clobber (reg:DI 2))
7521 (clobber (match_operand 2))
7524 (use (const_int 1))]
7528 ;; Split out the PIC register save and restore after reload. As the
7529 ;; split is done after reload, there are some situations in which we
7530 ;; unnecessarily save and restore %r4. This happens when there is a
7531 ;; single call and the PIC register is not used after the call.
7533 ;; The split has to be done since call_from_call_insn () can't handle
7534 ;; the pattern as is. Noreturn calls are special because they have to
7535 ;; terminate the basic block. The split has to contain more than one
7538 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7539 (match_operand 1 "" ""))
7540 (clobber (reg:DI 1))
7541 (clobber (reg:DI 2))
7542 (clobber (match_operand 2))
7545 (use (const_int 1))])]
7546 "TARGET_64BIT && reload_completed
7547 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7548 [(set (match_dup 2) (reg:DI 27))
7549 (parallel [(call (mem:SI (match_dup 0))
7551 (clobber (reg:DI 1))
7552 (clobber (reg:DI 2))
7555 (use (const_int 1))])]
7559 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7560 (match_operand 1 "" ""))
7561 (clobber (reg:DI 1))
7562 (clobber (reg:DI 2))
7563 (clobber (match_operand 2))
7566 (use (const_int 1))])]
7567 "TARGET_64BIT && reload_completed"
7568 [(set (match_dup 2) (reg:DI 27))
7569 (parallel [(call (mem:SI (match_dup 0))
7571 (clobber (reg:DI 1))
7572 (clobber (reg:DI 2))
7575 (use (const_int 1))])
7576 (set (reg:DI 27) (match_dup 2))]
7579 (define_insn "*call_reg_64bit_post_reload"
7580 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7581 (match_operand 1 "" "i"))
7582 (clobber (reg:DI 1))
7583 (clobber (reg:DI 2))
7586 (use (const_int 1))]
7590 return pa_output_indirect_call (insn, operands[0]);
7592 [(set_attr "type" "dyncall")
7593 (set (attr "length")
7594 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 12)]
7595 (symbol_ref "pa_attr_length_indirect_call (insn)")))])
7597 (define_expand "call_value"
7598 [(parallel [(set (match_operand 0 "" "")
7599 (call (match_operand:SI 1 "" "")
7600 (match_operand 2 "" "")))
7601 (clobber (reg:SI 2))])]
7605 rtx dst = operands[0];
7606 rtx nb = operands[2];
7607 bool call_powf = false;
7609 if (TARGET_PORTABLE_RUNTIME)
7610 op = force_reg (SImode, XEXP (operands[1], 0));
7613 op = XEXP (operands[1], 0);
7614 if (GET_CODE (op) == SYMBOL_REF)
7616 /* Handle special call to buggy powf function. */
7617 if (TARGET_HPUX && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT
7618 && !strcmp (targetm.strip_name_encoding (XSTR (op, 0)), "powf"))
7621 /* Generate indirect long calls to non-local functions. */
7622 else if (!TARGET_64BIT && TARGET_LONG_CALLS)
7624 tree call_decl = SYMBOL_REF_DECL (op);
7625 if (!(call_decl && targetm.binds_local_p (call_decl)))
7626 op = force_reg (word_mode, op);
7633 if (!virtuals_instantiated)
7634 emit_move_insn (arg_pointer_rtx,
7635 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7639 /* The loop pass can generate new libcalls after the virtual
7640 registers are instantiated when fpregs are disabled because
7641 the only method that we have for doing DImode multiplication
7642 is with a libcall. This could be trouble if we haven't
7643 allocated enough space for the outgoing arguments. */
7644 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
7646 emit_move_insn (arg_pointer_rtx,
7647 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7648 GEN_INT (STACK_POINTER_OFFSET + 64)));
7652 /* Use two different patterns for calls to explicitly named functions
7653 and calls through function pointers. This is necessary as these two
7654 types of calls use different calling conventions, and CSE might try
7655 to change the named call into an indirect call in some cases (using
7656 two patterns keeps CSE from performing this optimization).
7658 We now use even more call patterns as there was a subtle bug in
7659 attempting to restore the pic register after a call using a simple
7660 move insn. During reload, a instruction involving a pseudo register
7661 with no explicit dependence on the PIC register can be converted
7662 to an equivalent load from memory using the PIC register. If we
7663 emit a simple move to restore the PIC register in the initial rtl
7664 generation, then it can potentially be repositioned during scheduling.
7665 and an instruction that eventually uses the PIC register may end up
7666 between the call and the PIC register restore.
7668 This only worked because there is a post call group of instructions
7669 that are scheduled with the call. These instructions are included
7670 in the same basic block as the call. However, calls can throw in
7671 C++ code and a basic block has to terminate at the call if the call
7672 can throw. This results in the PIC register restore being scheduled
7673 independently from the call. So, we now hide the save and restore
7674 of the PIC register in the call pattern until after reload. Then,
7675 we split the moves out. A small side benefit is that we now don't
7676 need to have a use of the PIC register in the return pattern and
7677 the final save/restore operation is not needed.
7679 I elected to just use register %r4 in the PIC patterns instead
7680 of trying to force hppa_pic_save_rtx () to a callee saved register.
7681 This might have required a new register class and constraint. It
7682 was also simpler to just handle the restore from a register than a
7686 rtx r4 = gen_rtx_REG (word_mode, 4);
7687 if (GET_CODE (op) == SYMBOL_REF)
7690 emit_call_insn (gen_call_val_powf_64bit (dst, op, nb, r4));
7692 emit_call_insn (gen_call_val_symref_64bit (dst, op, nb, r4));
7696 op = force_reg (word_mode, op);
7697 emit_call_insn (gen_call_val_reg_64bit (dst, op, nb, r4));
7702 if (GET_CODE (op) == SYMBOL_REF)
7706 rtx r4 = gen_rtx_REG (word_mode, 4);
7709 emit_call_insn (gen_call_val_powf_pic (dst, op, nb, r4));
7711 emit_call_insn (gen_call_val_symref_pic (dst, op, nb, r4));
7716 emit_call_insn (gen_call_val_powf (dst, op, nb));
7718 emit_call_insn (gen_call_val_symref (dst, op, nb));
7723 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7724 emit_move_insn (tmpreg, force_reg (word_mode, op));
7727 rtx r4 = gen_rtx_REG (word_mode, 4);
7728 emit_call_insn (gen_call_val_reg_pic (dst, nb, r4));
7731 emit_call_insn (gen_call_val_reg (dst, nb));
7738 (define_insn "call_val_symref"
7739 [(set (match_operand 0 "" "")
7740 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7741 (match_operand 2 "" "i")))
7742 (clobber (reg:SI 1))
7743 (clobber (reg:SI 2))
7744 (use (const_int 0))]
7745 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7748 pa_output_arg_descriptor (insn);
7749 return pa_output_call (insn, operands[1], 0);
7751 [(set_attr "type" "call")
7752 (set (attr "length")
7753 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7754 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7756 ;; powf function clobbers %fr12
7757 (define_insn "call_val_powf"
7758 [(set (match_operand 0 "" "")
7759 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7760 (match_operand 2 "" "i")))
7761 (clobber (reg:SI 1))
7762 (clobber (reg:SI 2))
7763 (clobber (reg:DF 48))
7764 (use (const_int 1))]
7765 "TARGET_HPUX && !TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7768 pa_output_arg_descriptor (insn);
7769 return pa_output_call (insn, operands[1], 0);
7771 [(set_attr "type" "call")
7772 (set (attr "length")
7773 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7774 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7776 (define_insn "call_val_symref_pic"
7777 [(set (match_operand 0 "" "")
7778 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7779 (match_operand 2 "" "i")))
7780 (clobber (reg:SI 1))
7781 (clobber (reg:SI 2))
7782 (clobber (match_operand 3))
7784 (use (const_int 0))]
7785 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7788 ;; Split out the PIC register save and restore after reload. As the
7789 ;; split is done after reload, there are some situations in which we
7790 ;; unnecessarily save and restore %r4. This happens when there is a
7791 ;; single call and the PIC register is not used after the call.
7793 ;; The split has to be done since call_from_call_insn () can't handle
7794 ;; the pattern as is. Noreturn calls are special because they have to
7795 ;; terminate the basic block. The split has to contain more than one
7798 [(parallel [(set (match_operand 0 "" "")
7799 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7800 (match_operand 2 "" "")))
7801 (clobber (reg:SI 1))
7802 (clobber (reg:SI 2))
7803 (clobber (match_operand 3))
7805 (use (const_int 0))])]
7806 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed
7807 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7808 [(set (match_dup 3) (reg:SI 19))
7809 (parallel [(set (match_dup 0)
7810 (call (mem:SI (match_dup 1))
7812 (clobber (reg:SI 1))
7813 (clobber (reg:SI 2))
7815 (use (const_int 0))])]
7819 [(parallel [(set (match_operand 0 "" "")
7820 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7821 (match_operand 2 "" "")))
7822 (clobber (reg:SI 1))
7823 (clobber (reg:SI 2))
7824 (clobber (match_operand 3))
7826 (use (const_int 0))])]
7827 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7828 [(set (match_dup 3) (reg:SI 19))
7829 (parallel [(set (match_dup 0)
7830 (call (mem:SI (match_dup 1))
7832 (clobber (reg:SI 1))
7833 (clobber (reg:SI 2))
7835 (use (const_int 0))])
7836 (set (reg:SI 19) (match_dup 3))]
7839 (define_insn "*call_val_symref_pic_post_reload"
7840 [(set (match_operand 0 "" "")
7841 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7842 (match_operand 2 "" "i")))
7843 (clobber (reg:SI 1))
7844 (clobber (reg:SI 2))
7846 (use (const_int 0))]
7847 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7850 pa_output_arg_descriptor (insn);
7851 return pa_output_call (insn, operands[1], 0);
7853 [(set_attr "type" "call")
7854 (set (attr "length")
7855 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7856 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7858 ;; powf function clobbers %fr12
7859 (define_insn "call_val_powf_pic"
7860 [(set (match_operand 0 "" "")
7861 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7862 (match_operand 2 "" "i")))
7863 (clobber (reg:SI 1))
7864 (clobber (reg:SI 2))
7865 (clobber (reg:DF 48))
7866 (clobber (match_operand 3))
7868 (use (const_int 1))]
7869 "TARGET_HPUX && !TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7872 ;; Split out the PIC register save and restore after reload. As the
7873 ;; split is done after reload, there are some situations in which we
7874 ;; unnecessarily save and restore %r4. This happens when there is a
7875 ;; single call and the PIC register is not used after the call.
7877 ;; The split has to be done since call_from_call_insn () can't handle
7878 ;; the pattern as is. Noreturn calls are special because they have to
7879 ;; terminate the basic block. The split has to contain more than one
7882 [(parallel [(set (match_operand 0 "" "")
7883 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7884 (match_operand 2 "" "")))
7885 (clobber (reg:SI 1))
7886 (clobber (reg:SI 2))
7887 (clobber (reg:DF 48))
7888 (clobber (match_operand 3))
7890 (use (const_int 1))])]
7891 "TARGET_HPUX && !TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed
7892 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7893 [(set (match_dup 3) (reg:SI 19))
7894 (parallel [(set (match_dup 0)
7895 (call (mem:SI (match_dup 1))
7897 (clobber (reg:SI 1))
7898 (clobber (reg:SI 2))
7899 (clobber (reg:DF 48))
7901 (use (const_int 1))])]
7905 [(parallel [(set (match_operand 0 "" "")
7906 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7907 (match_operand 2 "" "")))
7908 (clobber (reg:SI 1))
7909 (clobber (reg:SI 2))
7910 (clobber (reg:DF 48))
7911 (clobber (match_operand 3))
7913 (use (const_int 1))])]
7914 "TARGET_HPUX && !TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7915 [(set (match_dup 3) (reg:SI 19))
7916 (parallel [(set (match_dup 0)
7917 (call (mem:SI (match_dup 1))
7919 (clobber (reg:SI 1))
7920 (clobber (reg:SI 2))
7921 (clobber (reg:DF 48))
7923 (use (const_int 1))])
7924 (set (reg:SI 19) (match_dup 3))]
7927 (define_insn "*call_val_powf_pic_post_reload"
7928 [(set (match_operand 0 "" "")
7929 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7930 (match_operand 2 "" "i")))
7931 (clobber (reg:SI 1))
7932 (clobber (reg:SI 2))
7933 (clobber (reg:DF 48))
7935 (use (const_int 1))]
7936 "TARGET_HPUX && !TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7939 pa_output_arg_descriptor (insn);
7940 return pa_output_call (insn, operands[1], 0);
7942 [(set_attr "type" "call")
7943 (set (attr "length")
7944 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7945 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7947 ;; This pattern is split if it is necessary to save and restore the
7949 (define_insn "call_val_symref_64bit"
7950 [(set (match_operand 0 "" "")
7951 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7952 (match_operand 2 "" "i")))
7953 (clobber (reg:DI 1))
7954 (clobber (reg:DI 2))
7955 (clobber (match_operand 3))
7958 (use (const_int 0))]
7962 ;; Split out the PIC register save and restore after reload. As the
7963 ;; split is done after reload, there are some situations in which we
7964 ;; unnecessarily save and restore %r4. This happens when there is a
7965 ;; single call and the PIC register is not used after the call.
7967 ;; The split has to be done since call_from_call_insn () can't handle
7968 ;; the pattern as is. Noreturn calls are special because they have to
7969 ;; terminate the basic block. The split has to contain more than one
7972 [(parallel [(set (match_operand 0 "" "")
7973 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7974 (match_operand 2 "" "")))
7975 (clobber (reg:DI 1))
7976 (clobber (reg:DI 2))
7977 (clobber (match_operand 3))
7980 (use (const_int 0))])]
7981 "TARGET_64BIT && reload_completed
7982 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7983 [(set (match_dup 3) (reg:DI 27))
7984 (parallel [(set (match_dup 0)
7985 (call (mem:SI (match_dup 1))
7987 (clobber (reg:DI 1))
7988 (clobber (reg:DI 2))
7991 (use (const_int 0))])]
7995 [(parallel [(set (match_operand 0 "" "")
7996 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7997 (match_operand 2 "" "")))
7998 (clobber (reg:DI 1))
7999 (clobber (reg:DI 2))
8000 (clobber (match_operand 3))
8003 (use (const_int 0))])]
8004 "TARGET_64BIT && reload_completed"
8005 [(set (match_dup 3) (reg:DI 27))
8006 (parallel [(set (match_dup 0)
8007 (call (mem:SI (match_dup 1))
8009 (clobber (reg:DI 1))
8010 (clobber (reg:DI 2))
8013 (use (const_int 0))])
8014 (set (reg:DI 27) (match_dup 3))]
8017 (define_insn "*call_val_symref_64bit_post_reload"
8018 [(set (match_operand 0 "" "")
8019 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8020 (match_operand 2 "" "i")))
8021 (clobber (reg:DI 1))
8022 (clobber (reg:DI 2))
8025 (use (const_int 0))]
8029 pa_output_arg_descriptor (insn);
8030 return pa_output_call (insn, operands[1], 0);
8032 [(set_attr "type" "call")
8033 (set (attr "length")
8034 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8035 (symbol_ref "pa_attr_length_call (insn, 0)")))])
8037 ;; powf function clobbers %fr12
8038 (define_insn "call_val_powf_64bit"
8039 [(set (match_operand 0 "" "")
8040 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8041 (match_operand 2 "" "i")))
8042 (clobber (reg:DI 1))
8043 (clobber (reg:DI 2))
8044 (clobber (reg:DF 40))
8045 (clobber (match_operand 3))
8048 (use (const_int 1))]
8049 "TARGET_64BIT && TARGET_HPUX"
8052 ;; Split out the PIC register save and restore after reload. As the
8053 ;; split is done after reload, there are some situations in which we
8054 ;; unnecessarily save and restore %r4. This happens when there is a
8055 ;; single call and the PIC register is not used after the call.
8057 ;; The split has to be done since call_from_call_insn () can't handle
8058 ;; the pattern as is. Noreturn calls are special because they have to
8059 ;; terminate the basic block. The split has to contain more than one
8062 [(parallel [(set (match_operand 0 "" "")
8063 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8064 (match_operand 2 "" "")))
8065 (clobber (reg:DI 1))
8066 (clobber (reg:DI 2))
8067 (clobber (reg:DF 40))
8068 (clobber (match_operand 3))
8071 (use (const_int 1))])]
8072 "TARGET_64BIT && TARGET_HPUX && reload_completed
8073 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8074 [(set (match_dup 3) (reg:DI 27))
8075 (parallel [(set (match_dup 0)
8076 (call (mem:SI (match_dup 1))
8078 (clobber (reg:DI 1))
8079 (clobber (reg:DI 2))
8080 (clobber (reg:DF 40))
8083 (use (const_int 1))])]
8087 [(parallel [(set (match_operand 0 "" "")
8088 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8089 (match_operand 2 "" "")))
8090 (clobber (reg:DI 1))
8091 (clobber (reg:DI 2))
8092 (clobber (reg:DF 40))
8093 (clobber (match_operand 3))
8096 (use (const_int 1))])]
8097 "TARGET_64BIT && TARGET_HPUX && reload_completed"
8098 [(set (match_dup 3) (reg:DI 27))
8099 (parallel [(set (match_dup 0)
8100 (call (mem:SI (match_dup 1))
8102 (clobber (reg:DI 1))
8103 (clobber (reg:DI 2))
8104 (clobber (reg:DF 40))
8107 (use (const_int 1))])
8108 (set (reg:DI 27) (match_dup 3))]
8111 (define_insn "*call_val_powf_64bit_post_reload"
8112 [(set (match_operand 0 "" "")
8113 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8114 (match_operand 2 "" "i")))
8115 (clobber (reg:DI 1))
8116 (clobber (reg:DI 2))
8117 (clobber (reg:DF 40))
8120 (use (const_int 1))]
8121 "TARGET_64BIT && TARGET_HPUX"
8124 pa_output_arg_descriptor (insn);
8125 return pa_output_call (insn, operands[1], 0);
8127 [(set_attr "type" "call")
8128 (set (attr "length")
8129 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8130 (symbol_ref "pa_attr_length_call (insn, 0)")))])
8132 (define_insn "call_val_reg"
8133 [(set (match_operand 0 "" "")
8134 (call (mem:SI (reg:SI 22))
8135 (match_operand 1 "" "i")))
8136 (clobber (reg:SI 1))
8137 (clobber (reg:SI 2))
8138 (use (const_int 1))]
8142 return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8144 [(set_attr "type" "dyncall")
8145 (set (attr "length")
8146 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8147 (symbol_ref "pa_attr_length_indirect_call (insn)")))])
8149 ;; This pattern is split if it is necessary to save and restore the
8151 (define_insn "call_val_reg_pic"
8152 [(set (match_operand 0 "" "")
8153 (call (mem:SI (reg:SI 22))
8154 (match_operand 1 "" "i")))
8155 (clobber (reg:SI 1))
8156 (clobber (reg:SI 2))
8157 (clobber (match_operand 2))
8159 (use (const_int 1))]
8163 ;; Split out the PIC register save and restore after reload. As the
8164 ;; split is done after reload, there are some situations in which we
8165 ;; unnecessarily save and restore %r4. This happens when there is a
8166 ;; single call and the PIC register is not used after the call.
8168 ;; The split has to be done since call_from_call_insn () can't handle
8169 ;; the pattern as is. Noreturn calls are special because they have to
8170 ;; terminate the basic block. The split has to contain more than one
8173 [(parallel [(set (match_operand 0 "" "")
8174 (call (mem:SI (reg:SI 22))
8175 (match_operand 1 "" "")))
8176 (clobber (reg:SI 1))
8177 (clobber (reg:SI 2))
8178 (clobber (match_operand 2))
8180 (use (const_int 1))])]
8181 "!TARGET_64BIT && reload_completed
8182 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8183 [(set (match_dup 2) (reg:SI 19))
8184 (parallel [(set (match_dup 0)
8185 (call (mem:SI (reg:SI 22))
8187 (clobber (reg:SI 1))
8188 (clobber (reg:SI 2))
8190 (use (const_int 1))])]
8194 [(parallel [(set (match_operand 0 "" "")
8195 (call (mem:SI (reg:SI 22))
8196 (match_operand 1 "" "")))
8197 (clobber (reg:SI 1))
8198 (clobber (reg:SI 2))
8199 (clobber (match_operand 2))
8201 (use (const_int 1))])]
8202 "!TARGET_64BIT && reload_completed"
8203 [(set (match_dup 2) (reg:SI 19))
8204 (parallel [(set (match_dup 0)
8205 (call (mem:SI (reg:SI 22))
8207 (clobber (reg:SI 1))
8208 (clobber (reg:SI 2))
8210 (use (const_int 1))])
8211 (set (reg:SI 19) (match_dup 2))]
8214 (define_insn "*call_val_reg_pic_post_reload"
8215 [(set (match_operand 0 "" "")
8216 (call (mem:SI (reg:SI 22))
8217 (match_operand 1 "" "i")))
8218 (clobber (reg:SI 1))
8219 (clobber (reg:SI 2))
8221 (use (const_int 1))]
8225 return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8227 [(set_attr "type" "dyncall")
8228 (set (attr "length")
8229 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8230 (symbol_ref "pa_attr_length_indirect_call (insn)")))])
8232 ;; This pattern is split if it is necessary to save and restore the
8234 (define_insn "call_val_reg_64bit"
8235 [(set (match_operand 0 "" "")
8236 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8237 (match_operand 2 "" "i")))
8238 (clobber (reg:DI 1))
8239 (clobber (reg:DI 2))
8240 (clobber (match_operand 3))
8243 (use (const_int 1))]
8247 ;; Split out the PIC register save and restore after reload. As the
8248 ;; split is done after reload, there are some situations in which we
8249 ;; unnecessarily save and restore %r4. This happens when there is a
8250 ;; single call and the PIC register is not used after the call.
8252 ;; The split has to be done since call_from_call_insn () can't handle
8253 ;; the pattern as is. Noreturn calls are special because they have to
8254 ;; terminate the basic block. The split has to contain more than one
8257 [(parallel [(set (match_operand 0 "" "")
8258 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8259 (match_operand 2 "" "")))
8260 (clobber (reg:DI 1))
8261 (clobber (reg:DI 2))
8262 (clobber (match_operand 3))
8265 (use (const_int 1))])]
8266 "TARGET_64BIT && reload_completed
8267 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8268 [(set (match_dup 3) (reg:DI 27))
8269 (parallel [(set (match_dup 0)
8270 (call (mem:SI (match_dup 1))
8272 (clobber (reg:DI 1))
8273 (clobber (reg:DI 2))
8276 (use (const_int 1))])]
8280 [(parallel [(set (match_operand 0 "" "")
8281 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8282 (match_operand 2 "" "")))
8283 (clobber (reg:DI 1))
8284 (clobber (reg:DI 2))
8285 (clobber (match_operand 3))
8288 (use (const_int 1))])]
8289 "TARGET_64BIT && reload_completed"
8290 [(set (match_dup 3) (reg:DI 27))
8291 (parallel [(set (match_dup 0)
8292 (call (mem:SI (match_dup 1))
8294 (clobber (reg:DI 1))
8295 (clobber (reg:DI 2))
8298 (use (const_int 1))])
8299 (set (reg:DI 27) (match_dup 3))]
8302 (define_insn "*call_val_reg_64bit_post_reload"
8303 [(set (match_operand 0 "" "")
8304 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8305 (match_operand 2 "" "i")))
8306 (clobber (reg:DI 1))
8307 (clobber (reg:DI 2))
8310 (use (const_int 1))]
8314 return pa_output_indirect_call (insn, operands[1]);
8316 [(set_attr "type" "dyncall")
8317 (set (attr "length")
8318 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 12)]
8319 (symbol_ref "pa_attr_length_indirect_call (insn)")))])
8321 ;; Call subroutine returning any type.
8323 (define_expand "untyped_call"
8324 [(parallel [(call (match_operand 0 "" "")
8326 (match_operand 1 "" "")
8327 (match_operand 2 "" "")])]
8333 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
8335 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8337 rtx set = XVECEXP (operands[2], 0, i);
8338 emit_move_insn (SET_DEST (set), SET_SRC (set));
8341 /* The optimizer does not know that the call sets the function value
8342 registers we stored in the result block. We avoid problems by
8343 claiming that all hard registers are used and clobbered at this
8345 emit_insn (gen_blockage ());
8350 (define_expand "sibcall"
8351 [(call (match_operand:SI 0 "" "")
8352 (match_operand 1 "" ""))]
8353 "!TARGET_PORTABLE_RUNTIME"
8357 rtx nb = operands[1];
8359 op = XEXP (operands[0], 0);
8363 if (!virtuals_instantiated)
8364 emit_move_insn (arg_pointer_rtx,
8365 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8369 /* The loop pass can generate new libcalls after the virtual
8370 registers are instantiated when fpregs are disabled because
8371 the only method that we have for doing DImode multiplication
8372 is with a libcall. This could be trouble if we haven't
8373 allocated enough space for the outgoing arguments. */
8374 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
8376 emit_move_insn (arg_pointer_rtx,
8377 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8378 GEN_INT (STACK_POINTER_OFFSET + 64)));
8382 /* Indirect sibling calls are not allowed. */
8384 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8386 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8388 call_insn = emit_call_insn (call_insn);
8391 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8393 /* We don't have to restore the PIC register. */
8395 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8400 (define_insn "sibcall_internal_symref"
8401 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8402 (match_operand 1 "" "i"))
8403 (clobber (reg:SI 1))
8405 (use (const_int 0))]
8406 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8409 pa_output_arg_descriptor (insn);
8410 return pa_output_call (insn, operands[0], 1);
8412 [(set_attr "type" "sibcall")
8413 (set (attr "length")
8414 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8415 (symbol_ref "pa_attr_length_call (insn, 1)")))])
8417 (define_insn "sibcall_internal_symref_64bit"
8418 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8419 (match_operand 1 "" "i"))
8420 (clobber (reg:DI 1))
8422 (use (const_int 0))]
8426 pa_output_arg_descriptor (insn);
8427 return pa_output_call (insn, operands[0], 1);
8429 [(set_attr "type" "sibcall")
8430 (set (attr "length")
8431 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8432 (symbol_ref "pa_attr_length_call (insn, 1)")))])
8434 (define_expand "sibcall_value"
8435 [(set (match_operand 0 "" "")
8436 (call (match_operand:SI 1 "" "")
8437 (match_operand 2 "" "")))]
8438 "!TARGET_PORTABLE_RUNTIME"
8442 rtx nb = operands[1];
8444 op = XEXP (operands[1], 0);
8448 if (!virtuals_instantiated)
8449 emit_move_insn (arg_pointer_rtx,
8450 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8454 /* The loop pass can generate new libcalls after the virtual
8455 registers are instantiated when fpregs are disabled because
8456 the only method that we have for doing DImode multiplication
8457 is with a libcall. This could be trouble if we haven't
8458 allocated enough space for the outgoing arguments. */
8459 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
8461 emit_move_insn (arg_pointer_rtx,
8462 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8463 GEN_INT (STACK_POINTER_OFFSET + 64)));
8467 /* Indirect sibling calls are not allowed. */
8470 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8473 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8475 call_insn = emit_call_insn (call_insn);
8478 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8480 /* We don't have to restore the PIC register. */
8482 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8487 (define_insn "sibcall_value_internal_symref"
8488 [(set (match_operand 0 "" "")
8489 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8490 (match_operand 2 "" "i")))
8491 (clobber (reg:SI 1))
8493 (use (const_int 0))]
8494 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8497 pa_output_arg_descriptor (insn);
8498 return pa_output_call (insn, operands[1], 1);
8500 [(set_attr "type" "sibcall")
8501 (set (attr "length")
8502 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8503 (symbol_ref "pa_attr_length_call (insn, 1)")))])
8505 (define_insn "sibcall_value_internal_symref_64bit"
8506 [(set (match_operand 0 "" "")
8507 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8508 (match_operand 2 "" "i")))
8509 (clobber (reg:DI 1))
8511 (use (const_int 0))]
8515 pa_output_arg_descriptor (insn);
8516 return pa_output_call (insn, operands[1], 1);
8518 [(set_attr "type" "sibcall")
8519 (set (attr "length")
8520 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8521 (symbol_ref "pa_attr_length_call (insn, 1)")))])
8527 [(set_attr "type" "move")
8528 (set_attr "length" "4")])
8530 ;;; EH does longjmp's from and within the data section. Thus,
8531 ;;; an interspace branch is required for the longjmp implementation.
8532 ;;; Registers r1 and r2 are used as scratch registers for the jump
8534 (define_expand "interspace_jump"
8536 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8537 (clobber (match_dup 1))])]
8541 operands[1] = gen_rtx_REG (word_mode, 2);
8545 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8546 (clobber (reg:SI 2))]
8547 "TARGET_PA_20 && !TARGET_64BIT"
8549 [(set_attr "type" "branch")
8550 (set_attr "length" "4")])
8553 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8554 (clobber (reg:SI 2))]
8555 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8557 [(set_attr "type" "branch")
8558 (set_attr "length" "4")])
8561 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8562 (clobber (reg:SI 2))]
8564 "ldsid (%%sr0,%0),%%r2\;mtsp %%r2,%%sr0\;be%* 0(%%sr0,%0)"
8565 [(set_attr "type" "branch")
8566 (set_attr "length" "12")])
8569 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8570 (clobber (reg:DI 2))]
8573 [(set_attr "type" "branch")
8574 (set_attr "length" "4")])
8576 (define_expand "builtin_longjmp"
8577 [(unspec_volatile [(match_operand 0 "register_operand" "r")] UNSPECV_LONGJMP)]
8581 /* The elements of the buffer are, in order: */
8582 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8583 rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0],
8584 POINTER_SIZE / BITS_PER_UNIT));
8585 rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0],
8586 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8587 rtx pv = gen_rtx_REG (Pmode, 1);
8589 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
8590 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
8592 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
8593 instead of the hard_frame_pointer_rtx in the save area. We need
8594 to adjust for the offset between these two values. */
8595 if (GET_CODE (fp) != REG)
8596 fp = force_reg (Pmode, fp);
8597 emit_move_insn (hard_frame_pointer_rtx, plus_constant (Pmode, fp, -8));
8599 /* This bit is the same as expand_builtin_longjmp. */
8600 emit_stack_restore (SAVE_NONLOCAL, stack);
8601 emit_use (hard_frame_pointer_rtx);
8602 emit_use (stack_pointer_rtx);
8604 /* Load the label we are jumping through into r1 so that we know
8605 where to look for it when we get back to setjmp's function for
8606 restoring the gp. */
8607 emit_move_insn (pv, lab);
8609 /* Prevent the insns above from being scheduled into the delay slot
8610 of the interspace jump because the space register could change. */
8611 emit_insn (gen_blockage ());
8613 emit_jump_insn (gen_interspace_jump (pv));
8618 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8619 (define_expand "extzvsi"
8620 [(set (match_operand:SI 0 "register_operand" "")
8621 (zero_extract:SI (match_operand:SI 1 "register_operand" "")
8622 (match_operand:SI 2 "uint5_operand" "")
8623 (match_operand:SI 3 "uint5_operand" "")))]
8627 unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
8628 unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
8630 /* PA extraction insns don't support zero length bitfields or fields
8631 extending beyond the left or right-most bits. Also, the predicate
8632 rejects lengths equal to a word as they are better handled by
8633 the move patterns. */
8634 if (len == 0 || pos + len > 32)
8637 /* From mips.md: extract_bit_field doesn't verify that our source
8638 matches the predicate, so check it again here. */
8639 if (!register_operand (operands[1], VOIDmode))
8642 emit_insn (gen_extzv_32 (operands[0], operands[1],
8643 operands[2], operands[3]));
8647 (define_insn "extzv_32"
8648 [(set (match_operand:SI 0 "register_operand" "=r")
8649 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8650 (match_operand:SI 2 "uint5_operand" "")
8651 (match_operand:SI 3 "uint5_operand" "")))]
8652 "UINTVAL (operands[2]) > 0
8653 && UINTVAL (operands[2]) + UINTVAL (operands[3]) <= 32"
8654 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
8655 [(set_attr "type" "shift")
8656 (set_attr "length" "4")])
8659 [(set (match_operand:SI 0 "register_operand" "=r")
8660 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8662 (match_operand:SI 2 "register_operand" "q")))]
8664 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
8665 [(set_attr "type" "shift")
8666 (set_attr "length" "4")])
8668 (define_expand "extzvdi"
8669 [(set (match_operand:DI 0 "register_operand" "")
8670 (zero_extract:DI (match_operand:DI 1 "register_operand" "")
8671 (match_operand:DI 2 "uint6_operand" "")
8672 (match_operand:DI 3 "uint6_operand" "")))]
8676 unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
8677 unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
8679 /* PA extraction insns don't support zero length bitfields or fields
8680 extending beyond the left or right-most bits. Also, the predicate
8681 rejects lengths equal to a doubleword as they are better handled by
8682 the move patterns. */
8683 if (len == 0 || pos + len > 64)
8686 /* From mips.md: extract_bit_field doesn't verify that our source
8687 matches the predicate, so check it again here. */
8688 if (!register_operand (operands[1], VOIDmode))
8691 emit_insn (gen_extzv_64 (operands[0], operands[1],
8692 operands[2], operands[3]));
8696 (define_insn "extzv_64"
8697 [(set (match_operand:DI 0 "register_operand" "=r")
8698 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8699 (match_operand:DI 2 "uint6_operand" "")
8700 (match_operand:DI 3 "uint6_operand" "")))]
8702 && UINTVAL (operands[2]) > 0
8703 && UINTVAL (operands[2]) + UINTVAL (operands[3]) <= 64"
8704 "extrd,u %1,%3+%2-1,%2,%0"
8705 [(set_attr "type" "shift")
8706 (set_attr "length" "4")])
8709 [(set (match_operand:DI 0 "register_operand" "=r")
8710 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8712 (match_operand:DI 2 "register_operand" "q")))]
8714 "extrd,u %1,%%sar,1,%0"
8715 [(set_attr "type" "shift")
8716 (set_attr "length" "4")])
8718 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8719 (define_expand "extvsi"
8720 [(set (match_operand:SI 0 "register_operand" "")
8721 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
8722 (match_operand:SI 2 "uint5_operand" "")
8723 (match_operand:SI 3 "uint5_operand" "")))]
8727 unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
8728 unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
8730 /* PA extraction insns don't support zero length bitfields or fields
8731 extending beyond the left or right-most bits. Also, the predicate
8732 rejects lengths equal to a word as they are better handled by
8733 the move patterns. */
8734 if (len == 0 || pos + len > 32)
8737 /* From mips.md: extract_bit_field doesn't verify that our source
8738 matches the predicate, so check it again here. */
8739 if (!register_operand (operands[1], VOIDmode))
8742 emit_insn (gen_extv_32 (operands[0], operands[1],
8743 operands[2], operands[3]));
8747 (define_insn "extv_32"
8748 [(set (match_operand:SI 0 "register_operand" "=r")
8749 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8750 (match_operand:SI 2 "uint5_operand" "")
8751 (match_operand:SI 3 "uint5_operand" "")))]
8752 "UINTVAL (operands[2]) > 0
8753 && UINTVAL (operands[2]) + UINTVAL (operands[3]) <= 32"
8754 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
8755 [(set_attr "type" "shift")
8756 (set_attr "length" "4")])
8759 [(set (match_operand:SI 0 "register_operand" "=r")
8760 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8762 (match_operand:SI 2 "register_operand" "q")))]
8764 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
8765 [(set_attr "type" "shift")
8766 (set_attr "length" "4")])
8768 (define_expand "extvdi"
8769 [(set (match_operand:DI 0 "register_operand" "")
8770 (sign_extract:DI (match_operand:DI 1 "register_operand" "")
8771 (match_operand:DI 2 "uint6_operand" "")
8772 (match_operand:DI 3 "uint6_operand" "")))]
8776 unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
8777 unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
8779 /* PA extraction insns don't support zero length bitfields or fields
8780 extending beyond the left or right-most bits. Also, the predicate
8781 rejects lengths equal to a doubleword as they are better handled by
8782 the move patterns. */
8783 if (len == 0 || pos + len > 64)
8786 /* From mips.md: extract_bit_field doesn't verify that our source
8787 matches the predicate, so check it again here. */
8788 if (!register_operand (operands[1], VOIDmode))
8791 emit_insn (gen_extv_64 (operands[0], operands[1],
8792 operands[2], operands[3]));
8796 (define_insn "extv_64"
8797 [(set (match_operand:DI 0 "register_operand" "=r")
8798 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8799 (match_operand:DI 2 "uint6_operand" "")
8800 (match_operand:DI 3 "uint6_operand" "")))]
8802 && UINTVAL (operands[2]) > 0
8803 && UINTVAL (operands[2]) + UINTVAL (operands[3]) <= 64"
8804 "extrd,s %1,%3+%2-1,%2,%0"
8805 [(set_attr "type" "shift")
8806 (set_attr "length" "4")])
8809 [(set (match_operand:DI 0 "register_operand" "=r")
8810 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8812 (match_operand:DI 2 "register_operand" "q")))]
8814 "extrd,s %1,%%sar,1,%0"
8815 [(set_attr "type" "shift")
8816 (set_attr "length" "4")])
8818 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
8819 (define_expand "insvsi"
8820 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
8821 (match_operand:SI 1 "uint5_operand" "")
8822 (match_operand:SI 2 "uint5_operand" ""))
8823 (match_operand:SI 3 "arith5_operand" ""))]
8827 unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
8828 unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
8830 /* PA insertion insns don't support zero length bitfields or fields
8831 extending beyond the left or right-most bits. Also, the predicate
8832 rejects lengths equal to a word as they are better handled by
8833 the move patterns. */
8834 if (len <= 0 || pos + len > 32)
8837 /* From mips.md: insert_bit_field doesn't verify that our destination
8838 matches the predicate, so check it again here. */
8839 if (!register_operand (operands[0], VOIDmode))
8842 emit_insn (gen_insv_32 (operands[0], operands[1],
8843 operands[2], operands[3]));
8847 (define_insn "insv_32"
8848 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
8849 (match_operand:SI 1 "uint5_operand" "")
8850 (match_operand:SI 2 "uint5_operand" ""))
8851 (match_operand:SI 3 "arith5_operand" "r,L"))]
8852 "UINTVAL (operands[1]) > 0
8853 && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32"
8855 {dep|depw} %3,%2+%1-1,%1,%0
8856 {depi|depwi} %3,%2+%1-1,%1,%0"
8857 [(set_attr "type" "shift,shift")
8858 (set_attr "length" "4,4")])
8860 ;; Optimize insertion of const_int values of type 1...1xxxx.
8862 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
8863 (match_operand:SI 1 "uint5_operand" "")
8864 (match_operand:SI 2 "uint5_operand" ""))
8865 (match_operand:SI 3 "const_int_operand" ""))]
8866 "(INTVAL (operands[3]) & 0x10) != 0 &&
8867 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8870 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8871 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
8873 [(set_attr "type" "shift")
8874 (set_attr "length" "4")])
8876 (define_expand "insvdi"
8877 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
8878 (match_operand:DI 1 "uint6_operand" "")
8879 (match_operand:DI 2 "uint6_operand" ""))
8880 (match_operand:DI 3 "arith5_operand" ""))]
8884 unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
8885 unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
8887 /* PA insertion insns don't support zero length bitfields or fields
8888 extending beyond the left or right-most bits. Also, the predicate
8889 rejects lengths equal to a doubleword as they are better handled by
8890 the move patterns. */
8891 if (len <= 0 || pos + len > 64)
8894 /* From mips.md: insert_bit_field doesn't verify that our destination
8895 matches the predicate, so check it again here. */
8896 if (!register_operand (operands[0], VOIDmode))
8899 emit_insn (gen_insv_64 (operands[0], operands[1],
8900 operands[2], operands[3]));
8904 (define_insn "insv_64"
8905 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
8906 (match_operand:DI 1 "uint6_operand" "")
8907 (match_operand:DI 2 "uint6_operand" ""))
8908 (match_operand:DI 3 "arith5_operand" "r,L"))]
8910 && UINTVAL (operands[1]) > 0
8911 && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 64"
8913 depd %3,%2+%1-1,%1,%0
8914 depdi %3,%2+%1-1,%1,%0"
8915 [(set_attr "type" "shift,shift")
8916 (set_attr "length" "4,4")])
8918 ;; Optimize insertion of const_int values of type 1...1xxxx.
8920 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
8921 (match_operand:DI 1 "uint6_operand" "")
8922 (match_operand:DI 2 "uint6_operand" ""))
8923 (match_operand:DI 3 "const_int_operand" ""))]
8924 "(INTVAL (operands[3]) & 0x10) != 0
8926 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8929 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8930 return \"depdi %3,%2+%1-1,%1,%0\";
8932 [(set_attr "type" "shift")
8933 (set_attr "length" "4")])
8936 [(set (match_operand:DI 0 "register_operand" "=r")
8937 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
8940 "depd,z %1,31,32,%0"
8941 [(set_attr "type" "shift")
8942 (set_attr "length" "4")])
8944 ;; This insn is used for some loop tests, typically loops reversed when
8945 ;; strength reduction is used. It is actually created when the instruction
8946 ;; combination phase combines the special loop test. Since this insn
8947 ;; is both a jump insn and has an output, it must deal with its own
8948 ;; reloads, hence the `Q' constraints. The `!' constraints direct reload
8949 ;; to not choose the register alternatives in the event a reload is needed.
8950 (define_insn "decrement_and_branch_until_zero"
8953 (match_operator 2 "comparison_operator"
8955 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*Q")
8956 (match_operand:SI 1 "int5_operand" "L,L,L"))
8958 (label_ref (match_operand 3 "" ""))
8961 (plus:SI (match_dup 0) (match_dup 1)))
8962 (clobber (match_scratch:SI 4 "=X,r,r"))]
8964 "* return pa_output_dbra (operands, insn, which_alternative); "
8965 ;; Do not expect to understand this the first time through.
8966 [(set_attr "type" "cbranch,multi,multi")
8967 (set (attr "length")
8968 (if_then_else (eq_attr "alternative" "0")
8969 ;; Loop counter in register case
8970 ;; Short branch has length of 4
8971 ;; Long branch has length of 8, 20, 24 or 28
8972 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8973 (const_int MAX_12BIT_OFFSET))
8975 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8976 (const_int MAX_17BIT_OFFSET))
8978 (match_test "TARGET_PORTABLE_RUNTIME")
8980 (not (match_test "flag_pic"))
8984 ;; Loop counter in FP reg case.
8985 ;; Extra goo to deal with additional reload insns.
8986 (if_then_else (eq_attr "alternative" "1")
8987 (if_then_else (lt (match_dup 3) (pc))
8988 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
8989 (const_int MAX_12BIT_OFFSET))
8991 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
8992 (const_int MAX_17BIT_OFFSET))
8994 (match_test "TARGET_PORTABLE_RUNTIME")
8996 (not (match_test "flag_pic"))
8999 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9000 (const_int MAX_12BIT_OFFSET))
9002 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9003 (const_int MAX_17BIT_OFFSET))
9005 (match_test "TARGET_PORTABLE_RUNTIME")
9007 (not (match_test "flag_pic"))
9011 ;; Loop counter in memory case.
9012 ;; Extra goo to deal with additional reload insns.
9013 (if_then_else (lt (match_dup 3) (pc))
9014 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9015 (const_int MAX_12BIT_OFFSET))
9017 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9018 (const_int MAX_17BIT_OFFSET))
9020 (match_test "TARGET_PORTABLE_RUNTIME")
9022 (not (match_test "flag_pic"))
9025 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9026 (const_int MAX_12BIT_OFFSET))
9028 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9029 (const_int MAX_17BIT_OFFSET))
9031 (match_test "TARGET_PORTABLE_RUNTIME")
9033 (not (match_test "flag_pic"))
9035 (const_int 36))))))])
9040 (match_operator 2 "movb_comparison_operator"
9041 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
9042 (label_ref (match_operand 3 "" ""))
9044 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*Q,!*q")
9047 "* return pa_output_movb (operands, insn, which_alternative, 0); "
9048 ;; Do not expect to understand this the first time through.
9049 [(set_attr "type" "cbranch,multi,multi,multi")
9050 (set (attr "length")
9051 (if_then_else (eq_attr "alternative" "0")
9052 ;; Loop counter in register case
9053 ;; Short branch has length of 4
9054 ;; Long branch has length of 8, 20, 24 or 28
9055 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9056 (const_int MAX_12BIT_OFFSET))
9058 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9059 (const_int MAX_17BIT_OFFSET))
9061 (match_test "TARGET_PORTABLE_RUNTIME")
9063 (not (match_test "flag_pic"))
9067 ;; Loop counter in FP reg case.
9068 ;; Extra goo to deal with additional reload insns.
9069 (if_then_else (eq_attr "alternative" "1")
9070 (if_then_else (lt (match_dup 3) (pc))
9071 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9072 (const_int MAX_12BIT_OFFSET))
9074 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9075 (const_int MAX_17BIT_OFFSET))
9077 (match_test "TARGET_PORTABLE_RUNTIME")
9079 (not (match_test "flag_pic"))
9082 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9083 (const_int MAX_12BIT_OFFSET))
9085 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9086 (const_int MAX_17BIT_OFFSET))
9088 (match_test "TARGET_PORTABLE_RUNTIME")
9090 (not (match_test "flag_pic"))
9094 ;; Loop counter in memory or sar case.
9095 ;; Extra goo to deal with additional reload insns.
9096 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9097 (const_int MAX_12BIT_OFFSET))
9099 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9100 (const_int MAX_17BIT_OFFSET))
9102 (match_test "TARGET_PORTABLE_RUNTIME")
9104 (not (match_test "flag_pic"))
9106 (const_int 32)))))])
9108 ;; Handle negated branch.
9112 (match_operator 2 "movb_comparison_operator"
9113 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
9115 (label_ref (match_operand 3 "" ""))))
9116 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*Q,!*q")
9119 "* return pa_output_movb (operands, insn, which_alternative, 1); "
9120 ;; Do not expect to understand this the first time through.
9121 [(set_attr "type" "cbranch,multi,multi,multi")
9122 (set (attr "length")
9123 (if_then_else (eq_attr "alternative" "0")
9124 ;; Loop counter in register case
9125 ;; Short branch has length of 4
9126 ;; Long branch has length of 8
9127 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9128 (const_int MAX_12BIT_OFFSET))
9130 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9131 (const_int MAX_17BIT_OFFSET))
9133 (match_test "TARGET_PORTABLE_RUNTIME")
9135 (not (match_test "flag_pic"))
9139 ;; Loop counter in FP reg case.
9140 ;; Extra goo to deal with additional reload insns.
9141 (if_then_else (eq_attr "alternative" "1")
9142 (if_then_else (lt (match_dup 3) (pc))
9143 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9144 (const_int MAX_12BIT_OFFSET))
9146 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9147 (const_int MAX_17BIT_OFFSET))
9149 (match_test "TARGET_PORTABLE_RUNTIME")
9151 (not (match_test "flag_pic"))
9154 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9155 (const_int MAX_12BIT_OFFSET))
9157 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9158 (const_int MAX_17BIT_OFFSET))
9160 (match_test "TARGET_PORTABLE_RUNTIME")
9162 (not (match_test "flag_pic"))
9166 ;; Loop counter in memory or SAR case.
9167 ;; Extra goo to deal with additional reload insns.
9168 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9169 (const_int MAX_12BIT_OFFSET))
9171 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9172 (const_int MAX_17BIT_OFFSET))
9174 (match_test "TARGET_PORTABLE_RUNTIME")
9176 (not (match_test "flag_pic"))
9178 (const_int 32)))))])
9181 [(set (pc) (label_ref (match_operand 3 "" "" )))
9182 (set (match_operand:SI 0 "ireg_operand" "=r")
9183 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
9184 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
9185 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
9188 return pa_output_parallel_addb (operands, insn);
9190 [(set_attr "type" "parallel_branch")
9191 (set (attr "length")
9192 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9193 (const_int MAX_12BIT_OFFSET))
9195 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9196 (const_int MAX_17BIT_OFFSET))
9198 (match_test "TARGET_PORTABLE_RUNTIME")
9200 (not (match_test "flag_pic"))
9205 [(set (pc) (label_ref (match_operand 2 "" "" )))
9206 (set (match_operand:SF 0 "ireg_operand" "=r")
9207 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
9211 return pa_output_parallel_movb (operands, insn);
9213 [(set_attr "type" "parallel_branch")
9214 (set (attr "length")
9215 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9216 (const_int MAX_12BIT_OFFSET))
9218 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9219 (const_int MAX_17BIT_OFFSET))
9221 (match_test "TARGET_PORTABLE_RUNTIME")
9223 (not (match_test "flag_pic"))
9228 [(set (pc) (label_ref (match_operand 2 "" "" )))
9229 (set (match_operand:SI 0 "ireg_operand" "=r")
9230 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
9234 return pa_output_parallel_movb (operands, insn);
9236 [(set_attr "type" "parallel_branch")
9237 (set (attr "length")
9238 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9239 (const_int MAX_12BIT_OFFSET))
9241 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9242 (const_int MAX_17BIT_OFFSET))
9244 (match_test "TARGET_PORTABLE_RUNTIME")
9246 (not (match_test "flag_pic"))
9251 [(set (pc) (label_ref (match_operand 2 "" "" )))
9252 (set (match_operand:HI 0 "ireg_operand" "=r")
9253 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
9257 return pa_output_parallel_movb (operands, insn);
9259 [(set_attr "type" "parallel_branch")
9260 (set (attr "length")
9261 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9262 (const_int MAX_12BIT_OFFSET))
9264 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9265 (const_int MAX_17BIT_OFFSET))
9267 (match_test "TARGET_PORTABLE_RUNTIME")
9269 (not (match_test "flag_pic"))
9274 [(set (pc) (label_ref (match_operand 2 "" "" )))
9275 (set (match_operand:QI 0 "ireg_operand" "=r")
9276 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
9280 return pa_output_parallel_movb (operands, insn);
9282 [(set_attr "type" "parallel_branch")
9283 (set (attr "length")
9284 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9285 (const_int MAX_12BIT_OFFSET))
9287 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9288 (const_int MAX_17BIT_OFFSET))
9290 (match_test "TARGET_PORTABLE_RUNTIME")
9292 (not (match_test "flag_pic"))
9297 [(set (match_operand 0 "register_operand" "=f")
9298 (mult (match_operand 1 "register_operand" "f")
9299 (match_operand 2 "register_operand" "f")))
9300 (set (match_operand 3 "register_operand" "+f")
9301 (plus (match_operand 4 "register_operand" "f")
9302 (match_operand 5 "register_operand" "f")))]
9303 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9304 && reload_completed && pa_fmpyaddoperands (operands)"
9307 if (GET_MODE (operands[0]) == DFmode)
9309 if (rtx_equal_p (operands[3], operands[5]))
9310 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9312 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9316 if (rtx_equal_p (operands[3], operands[5]))
9317 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9319 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9322 [(set_attr "type" "fpalu")
9323 (set_attr "length" "4")])
9326 [(set (match_operand 3 "register_operand" "+f")
9327 (plus (match_operand 4 "register_operand" "f")
9328 (match_operand 5 "register_operand" "f")))
9329 (set (match_operand 0 "register_operand" "=f")
9330 (mult (match_operand 1 "register_operand" "f")
9331 (match_operand 2 "register_operand" "f")))]
9332 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9333 && reload_completed && pa_fmpyaddoperands (operands)"
9336 if (GET_MODE (operands[0]) == DFmode)
9338 if (rtx_equal_p (operands[3], operands[5]))
9339 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9341 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9345 if (rtx_equal_p (operands[3], operands[5]))
9346 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9348 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9351 [(set_attr "type" "fpalu")
9352 (set_attr "length" "4")])
9355 [(set (match_operand 0 "register_operand" "=f")
9356 (mult (match_operand 1 "register_operand" "f")
9357 (match_operand 2 "register_operand" "f")))
9358 (set (match_operand 3 "register_operand" "+f")
9359 (minus (match_operand 4 "register_operand" "f")
9360 (match_operand 5 "register_operand" "f")))]
9361 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9362 && reload_completed && pa_fmpysuboperands (operands)"
9365 if (GET_MODE (operands[0]) == DFmode)
9366 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9368 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9370 [(set_attr "type" "fpalu")
9371 (set_attr "length" "4")])
9374 [(set (match_operand 3 "register_operand" "+f")
9375 (minus (match_operand 4 "register_operand" "f")
9376 (match_operand 5 "register_operand" "f")))
9377 (set (match_operand 0 "register_operand" "=f")
9378 (mult (match_operand 1 "register_operand" "f")
9379 (match_operand 2 "register_operand" "f")))]
9380 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9381 && reload_completed && pa_fmpysuboperands (operands)"
9384 if (GET_MODE (operands[0]) == DFmode)
9385 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9387 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9389 [(set_attr "type" "fpalu")
9390 (set_attr "length" "4")])
9392 ;; The following two patterns are used by the trampoline code for nested
9393 ;; functions. They flush the I and D cache lines from the start address
9394 ;; (operand0) to the end address (operand1). No lines are flushed if the
9395 ;; end address is less than the start address (unsigned).
9397 ;; Because the range of memory flushed is variable and the size of a MEM
9398 ;; can only be a CONST_INT, the patterns specify that they perform an
9399 ;; unspecified volatile operation on all memory.
9401 ;; The address range for an icache flush must lie within a single
9402 ;; space on targets with non-equivalent space registers.
9404 ;; Operand 0 contains the start address.
9405 ;; Operand 1 contains the end address.
9406 ;; Operand 2 contains the line length to use.
9407 (define_insn "dcacheflush<P:mode>"
9409 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
9410 (use (match_operand 0 "pmode_register_operand" "r"))
9411 (use (match_operand 1 "pmode_register_operand" "r"))
9412 (use (match_operand 2 "pmode_register_operand" "r"))
9413 (clobber (match_scratch:P 3 "=&0"))]
9415 "cmpb,<dwc><<=,n %3,%1,.\;fdc,m %2(%3)\;sync"
9416 [(set_attr "type" "multi")
9417 (set_attr "length" "12")])
9419 (define_insn "icacheflush<P:mode>"
9421 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
9422 (use (match_operand 0 "pmode_register_operand" "r"))
9423 (use (match_operand 1 "pmode_register_operand" "r"))
9424 (use (match_operand 2 "pmode_register_operand" "r"))
9425 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
9426 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
9427 (clobber (match_scratch:P 5 "=&0"))]
9429 "mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<dwc><<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
9430 [(set_attr "type" "multi")
9431 (set_attr "length" "52")])
9433 ;; An out-of-line prologue.
9434 (define_insn "outline_prologue_call"
9435 [(unspec_volatile [(const_int 0)] UNSPECV_OPC)
9436 (clobber (reg:SI 31))
9437 (clobber (reg:SI 22))
9438 (clobber (reg:SI 21))
9439 (clobber (reg:SI 20))
9440 (clobber (reg:SI 19))
9441 (clobber (reg:SI 1))]
9446 /* We need two different versions depending on whether or not we
9447 need a frame pointer. Also note that we return to the instruction
9448 immediately after the branch rather than two instructions after the
9449 break as normally is the case. */
9450 if (frame_pointer_needed)
9452 /* Must import the magic millicode routine(s). */
9453 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
9455 if (TARGET_PORTABLE_RUNTIME)
9457 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
9458 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
9462 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9466 /* Must import the magic millicode routine(s). */
9467 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9469 if (TARGET_PORTABLE_RUNTIME)
9471 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9472 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9475 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9479 [(set_attr "type" "multi")
9480 (set_attr "length" "8")])
9482 ;; An out-of-line epilogue.
9483 (define_insn "outline_epilogue_call"
9484 [(unspec_volatile [(const_int 1)] UNSPECV_OEC)
9487 (clobber (reg:SI 31))
9488 (clobber (reg:SI 22))
9489 (clobber (reg:SI 21))
9490 (clobber (reg:SI 20))
9491 (clobber (reg:SI 19))
9492 (clobber (reg:SI 2))
9493 (clobber (reg:SI 1))]
9498 /* We need two different versions depending on whether or not we
9499 need a frame pointer. Also note that we return to the instruction
9500 immediately after the branch rather than two instructions after the
9501 break as normally is the case. */
9502 if (frame_pointer_needed)
9504 /* Must import the magic millicode routine. */
9505 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9507 /* The out-of-line prologue will make sure we return to the right
9509 if (TARGET_PORTABLE_RUNTIME)
9511 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9512 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9516 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9520 /* Must import the magic millicode routine. */
9521 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9523 /* The out-of-line prologue will make sure we return to the right
9525 if (TARGET_PORTABLE_RUNTIME)
9527 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9528 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9531 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9535 [(set_attr "type" "multi")
9536 (set_attr "length" "8")])
9538 ;; Given a function pointer, canonicalize it so it can be
9539 ;; reliably compared to another function pointer. */
9540 (define_expand "canonicalize_funcptr_for_compare"
9541 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9542 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9543 (clobber (match_dup 2))
9544 (clobber (reg:SI 26))
9545 (clobber (reg:SI 22))
9546 (clobber (reg:SI 31))])
9547 (set (match_operand:SI 0 "register_operand" "")
9549 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9554 rtx canonicalize_funcptr_for_compare_libfunc
9555 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9557 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9558 operands[0], LCT_NORMAL, Pmode,
9559 1, operands[1], Pmode);
9563 operands[2] = gen_reg_rtx (SImode);
9564 if (GET_CODE (operands[1]) != REG)
9566 rtx tmp = gen_reg_rtx (Pmode);
9567 emit_move_insn (tmp, operands[1]);
9572 (define_insn "*$$sh_func_adrs"
9573 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9574 (clobber (match_operand:SI 0 "register_operand" "=a"))
9575 (clobber (reg:SI 26))
9576 (clobber (reg:SI 22))
9577 (clobber (reg:SI 31))]
9581 int length = get_attr_length (insn);
9584 xoperands[0] = GEN_INT (length - 8);
9585 xoperands[1] = GEN_INT (length - 16);
9587 /* Must import the magic millicode routine. */
9588 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9590 /* This is absolutely amazing.
9592 First, copy our input parameter into %r29 just in case we don't
9593 need to call $$sh_func_adrs. */
9594 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9595 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9597 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9598 we use %r26 unchanged. */
9599 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9600 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9602 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9603 4096, then again we use %r26 unchanged. */
9604 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9606 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9607 return pa_output_millicode_call (insn,
9608 gen_rtx_SYMBOL_REF (SImode,
9609 \"$$sh_func_adrs\"));
9611 [(set_attr "type" "sh_func_adrs")
9612 (set (attr "length")
9613 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 28)]
9614 (plus (symbol_ref "pa_attr_length_millicode_call (insn)")
9617 ;; On the PA, the PIC register is call clobbered, so it must
9618 ;; be saved & restored around calls by the caller. If the call
9619 ;; doesn't return normally (nonlocal goto, or an exception is
9620 ;; thrown), then the code at the exception handler label must
9621 ;; restore the PIC register.
9622 (define_expand "exception_receiver"
9627 /* On the 64-bit port, we need a blockage because there is
9628 confusion regarding the dependence of the restore on the
9629 frame pointer. As a result, the frame pointer and pic
9630 register restores sometimes are interchanged erroneously. */
9632 emit_insn (gen_blockage ());
9633 /* Restore the PIC register using hppa_pic_save_rtx (). The
9634 PIC register is not saved in the frame in 64-bit ABI. */
9635 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9636 emit_insn (gen_blockage ());
9640 (define_expand "builtin_setjmp_receiver"
9641 [(label_ref (match_operand 0 "" ""))]
9646 emit_insn (gen_blockage ());
9647 /* Restore the PIC register. Hopefully, this will always be from
9648 a stack slot. The only registers that are valid after a
9649 builtin_longjmp are the stack and frame pointers. */
9650 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9651 emit_insn (gen_blockage ());
9655 ;; Allocate new stack space and update the saved stack pointer in the
9656 ;; frame marker. The HP C compilers also copy additional words in the
9657 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9658 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9659 ;; currently don't copy these values.
9661 ;; Since the copy of the frame marker can't be done atomically, I
9662 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9663 ;; The HP compilers appear to raise the stack and copy the frame
9664 ;; marker in a strict instruction sequence. This suggests that the
9665 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9666 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9667 ;; as GAS doesn't support it, or try to keep the instructions emitted
9668 ;; here in strict sequence.
9669 (define_expand "allocate_stack"
9670 [(match_operand 0 "" "")
9671 (match_operand 1 "" "")]
9677 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9678 in operand 0 before adjusting the stack. */
9679 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9680 anti_adjust_stack (operands[1]);
9681 if (TARGET_HPUX_UNWIND_LIBRARY)
9683 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9684 GEN_INT (TARGET_64BIT ? -8 : -4));
9685 emit_move_insn (gen_rtx_MEM (word_mode, addr), hard_frame_pointer_rtx);
9687 if (!TARGET_64BIT && flag_pic)
9689 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9690 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
9695 (define_expand "prefetch"
9696 [(match_operand 0 "address_operand" "")
9697 (match_operand 1 "const_int_operand" "")
9698 (match_operand 2 "const_int_operand" "")]
9701 operands[0] = copy_addr_to_reg (operands[0]);
9702 emit_insn (gen_prefetch_20 (operands[0], operands[1], operands[2]));
9706 (define_insn "prefetch_20"
9707 [(prefetch (match_operand 0 "pmode_register_operand" "r")
9708 (match_operand:SI 1 "const_int_operand" "n")
9709 (match_operand:SI 2 "const_int_operand" "n"))]
9712 /* The SL cache-control completer indicates good spatial locality but
9713 poor temporal locality. The ldw instruction with a target of general
9714 register 0 prefetches a cache line for a read. The ldd instruction
9715 prefetches a cache line for a write. */
9716 static const char * const instr[2][2] = {
9718 "ldw,sl 0(%0),%%r0",
9726 int read_or_write = INTVAL (operands[1]) == 0 ? 0 : 1;
9727 int locality = INTVAL (operands[2]) == 0 ? 0 : 1;
9729 return instr [locality][read_or_write];
9731 [(set_attr "type" "load")
9732 (set_attr "length" "4")])
9735 (define_insn "tgd_load"
9736 [(set (match_operand:SI 0 "register_operand" "=r")
9737 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD))
9738 (clobber (reg:SI 1))
9743 return \"addil LR'%1-$tls_gdidx$,%%r27\;ldo RR'%1-$tls_gdidx$(%%r1),%0\";
9745 [(set_attr "type" "multi")
9746 (set_attr "length" "8")])
9748 (define_insn "tgd_load_pic"
9749 [(set (match_operand:SI 0 "register_operand" "=r")
9750 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD_PIC))
9751 (clobber (reg:SI 1))
9756 return \"addil LT'%1-$tls_gdidx$,%%r19\;ldo RT'%1-$tls_gdidx$(%%r1),%0\";
9758 [(set_attr "type" "multi")
9759 (set_attr "length" "8")])
9761 (define_insn "tld_load"
9762 [(set (match_operand:SI 0 "register_operand" "=r")
9763 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM))
9764 (clobber (reg:SI 1))
9769 return \"addil LR'%1-$tls_ldidx$,%%r27\;ldo RR'%1-$tls_ldidx$(%%r1),%0\";
9771 [(set_attr "type" "multi")
9772 (set_attr "length" "8")])
9774 (define_insn "tld_load_pic"
9775 [(set (match_operand:SI 0 "register_operand" "=r")
9776 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM_PIC))
9777 (clobber (reg:SI 1))
9782 return \"addil LT'%1-$tls_ldidx$,%%r19\;ldo RT'%1-$tls_ldidx$(%%r1),%0\";
9784 [(set_attr "type" "multi")
9785 (set_attr "length" "8")])
9787 (define_insn "tld_offset_load"
9788 [(set (match_operand:SI 0 "register_operand" "=r")
9789 (plus:SI (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")]
9791 (match_operand:SI 2 "register_operand" "r")))
9792 (clobber (reg:SI 1))]
9796 return \"addil LR'%1-$tls_dtpoff$,%2\;ldo RR'%1-$tls_dtpoff$(%%r1),%0\";
9798 [(set_attr "type" "multi")
9799 (set_attr "length" "8")])
9801 (define_insn "tp_load"
9802 [(set (match_operand:SI 0 "register_operand" "=r")
9803 (unspec:SI [(const_int 0)] UNSPEC_TP))]
9806 [(set_attr "type" "multi")
9807 (set_attr "length" "4")])
9809 (define_insn "tie_load"
9810 [(set (match_operand:SI 0 "register_operand" "=r")
9811 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE))
9812 (clobber (reg:SI 1))
9817 return \"addil LR'%1-$tls_ieoff$,%%r27\;ldw RR'%1-$tls_ieoff$(%%r1),%0\";
9819 [(set_attr "type" "multi")
9820 (set_attr "length" "8")])
9822 (define_insn "tie_load_pic"
9823 [(set (match_operand:SI 0 "register_operand" "=r")
9824 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE_PIC))
9825 (clobber (reg:SI 1))
9830 return \"addil LT'%1-$tls_ieoff$,%%r19\;ldw RT'%1-$tls_ieoff$(%%r1),%0\";
9832 [(set_attr "type" "multi")
9833 (set_attr "length" "8")])
9835 (define_insn "tle_load"
9836 [(set (match_operand:SI 0 "register_operand" "=r")
9837 (plus:SI (unspec:SI [(match_operand 1 "tle_symbolic_operand" "")]
9839 (match_operand:SI 2 "register_operand" "r")))
9840 (clobber (reg:SI 1))]
9842 "addil LR'%1-$tls_leoff$,%2\;ldo RR'%1-$tls_leoff$(%%r1),%0"
9843 [(set_attr "type" "multi")
9844 (set_attr "length" "8")])