1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
27 #include "double-int.h"
34 #include "fold-const.h"
36 #include "stor-layout.h"
39 #include "hard-reg-set.h"
42 #include "insn-config.h"
43 #include "conditions.h"
45 #include "insn-attr.h"
47 #include "diagnostic-core.h"
50 #include "statistics.h"
52 #include "fixed-value.h"
62 #include "target-def.h"
64 #include "dominance.h"
70 #include "cfgcleanup.h"
72 #include "basic-block.h"
74 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
75 #include "sched-int.h"
76 #include "insn-codes.h"
83 enum reg_class regno_reg_class
[] =
85 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
86 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
87 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
88 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
89 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
90 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
95 /* The minimum number of integer registers that we want to save with the
96 movem instruction. Using two movel instructions instead of a single
97 moveml is about 15% faster for the 68020 and 68030 at no expense in
99 #define MIN_MOVEM_REGS 3
101 /* The minimum number of floating point registers that we want to save
102 with the fmovem instruction. */
103 #define MIN_FMOVEM_REGS 1
105 /* Structure describing stack frame layout. */
108 /* Stack pointer to frame pointer offset. */
109 HOST_WIDE_INT offset
;
111 /* Offset of FPU registers. */
112 HOST_WIDE_INT foffset
;
114 /* Frame size in bytes (rounded up). */
117 /* Data and address register. */
119 unsigned int reg_mask
;
123 unsigned int fpu_mask
;
125 /* Offsets relative to ARG_POINTER. */
126 HOST_WIDE_INT frame_pointer_offset
;
127 HOST_WIDE_INT stack_pointer_offset
;
129 /* Function which the above information refers to. */
133 /* Current frame information calculated by m68k_compute_frame_layout(). */
134 static struct m68k_frame current_frame
;
136 /* Structure describing an m68k address.
138 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
139 with null fields evaluating to 0. Here:
141 - BASE satisfies m68k_legitimate_base_reg_p
142 - INDEX satisfies m68k_legitimate_index_reg_p
143 - OFFSET satisfies m68k_legitimate_constant_address_p
145 INDEX is either HImode or SImode. The other fields are SImode.
147 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
148 the address is (BASE)+. */
149 struct m68k_address
{
157 static int m68k_sched_adjust_cost (rtx_insn
*, rtx
, rtx_insn
*, int);
158 static int m68k_sched_issue_rate (void);
159 static int m68k_sched_variable_issue (FILE *, int, rtx_insn
*, int);
160 static void m68k_sched_md_init_global (FILE *, int, int);
161 static void m68k_sched_md_finish_global (FILE *, int);
162 static void m68k_sched_md_init (FILE *, int, int);
163 static void m68k_sched_dfa_pre_advance_cycle (void);
164 static void m68k_sched_dfa_post_advance_cycle (void);
165 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
167 static bool m68k_can_eliminate (const int, const int);
168 static void m68k_conditional_register_usage (void);
169 static bool m68k_legitimate_address_p (machine_mode
, rtx
, bool);
170 static void m68k_option_override (void);
171 static void m68k_override_options_after_change (void);
172 static rtx
find_addr_reg (rtx
);
173 static const char *singlemove_string (rtx
*);
174 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
175 HOST_WIDE_INT
, tree
);
176 static rtx
m68k_struct_value_rtx (tree
, int);
177 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
178 tree args
, int flags
,
180 static void m68k_compute_frame_layout (void);
181 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
182 static bool m68k_ok_for_sibcall_p (tree
, tree
);
183 static bool m68k_tls_symbol_p (rtx
);
184 static rtx
m68k_legitimize_address (rtx
, rtx
, machine_mode
);
185 static bool m68k_rtx_costs (rtx
, int, int, int, int *, bool);
186 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
187 static bool m68k_return_in_memory (const_tree
, const_tree
);
189 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
190 static void m68k_trampoline_init (rtx
, tree
, rtx
);
191 static int m68k_return_pops_args (tree
, tree
, int);
192 static rtx
m68k_delegitimize_address (rtx
);
193 static void m68k_function_arg_advance (cumulative_args_t
, machine_mode
,
195 static rtx
m68k_function_arg (cumulative_args_t
, machine_mode
,
197 static bool m68k_cannot_force_const_mem (machine_mode mode
, rtx x
);
198 static bool m68k_output_addr_const_extra (FILE *, rtx
);
199 static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED
;
201 /* Initialize the GCC target structure. */
203 #if INT_OP_GROUP == INT_OP_DOT_WORD
204 #undef TARGET_ASM_ALIGNED_HI_OP
205 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
208 #if INT_OP_GROUP == INT_OP_NO_DOT
209 #undef TARGET_ASM_BYTE_OP
210 #define TARGET_ASM_BYTE_OP "\tbyte\t"
211 #undef TARGET_ASM_ALIGNED_HI_OP
212 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
213 #undef TARGET_ASM_ALIGNED_SI_OP
214 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
217 #if INT_OP_GROUP == INT_OP_DC
218 #undef TARGET_ASM_BYTE_OP
219 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
220 #undef TARGET_ASM_ALIGNED_HI_OP
221 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
222 #undef TARGET_ASM_ALIGNED_SI_OP
223 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
226 #undef TARGET_ASM_UNALIGNED_HI_OP
227 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
228 #undef TARGET_ASM_UNALIGNED_SI_OP
229 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
231 #undef TARGET_ASM_OUTPUT_MI_THUNK
232 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
233 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
234 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
236 #undef TARGET_ASM_FILE_START_APP_OFF
237 #define TARGET_ASM_FILE_START_APP_OFF true
239 #undef TARGET_LEGITIMIZE_ADDRESS
240 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
242 #undef TARGET_SCHED_ADJUST_COST
243 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
245 #undef TARGET_SCHED_ISSUE_RATE
246 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
248 #undef TARGET_SCHED_VARIABLE_ISSUE
249 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
251 #undef TARGET_SCHED_INIT_GLOBAL
252 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
254 #undef TARGET_SCHED_FINISH_GLOBAL
255 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
257 #undef TARGET_SCHED_INIT
258 #define TARGET_SCHED_INIT m68k_sched_md_init
260 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
261 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
263 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
264 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
266 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
267 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
268 m68k_sched_first_cycle_multipass_dfa_lookahead
270 #undef TARGET_OPTION_OVERRIDE
271 #define TARGET_OPTION_OVERRIDE m68k_option_override
273 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
274 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change
276 #undef TARGET_RTX_COSTS
277 #define TARGET_RTX_COSTS m68k_rtx_costs
279 #undef TARGET_ATTRIBUTE_TABLE
280 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
282 #undef TARGET_PROMOTE_PROTOTYPES
283 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
285 #undef TARGET_STRUCT_VALUE_RTX
286 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
288 #undef TARGET_CANNOT_FORCE_CONST_MEM
289 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
291 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
292 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
294 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
295 #undef TARGET_RETURN_IN_MEMORY
296 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
300 #undef TARGET_HAVE_TLS
301 #define TARGET_HAVE_TLS (true)
303 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
304 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
307 #undef TARGET_LEGITIMATE_ADDRESS_P
308 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
310 #undef TARGET_CAN_ELIMINATE
311 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
313 #undef TARGET_CONDITIONAL_REGISTER_USAGE
314 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
316 #undef TARGET_TRAMPOLINE_INIT
317 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
319 #undef TARGET_RETURN_POPS_ARGS
320 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
322 #undef TARGET_DELEGITIMIZE_ADDRESS
323 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
325 #undef TARGET_FUNCTION_ARG
326 #define TARGET_FUNCTION_ARG m68k_function_arg
328 #undef TARGET_FUNCTION_ARG_ADVANCE
329 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
331 #undef TARGET_LEGITIMATE_CONSTANT_P
332 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
334 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
335 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
337 /* The value stored by TAS. */
338 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
339 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
341 static const struct attribute_spec m68k_attribute_table
[] =
343 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
344 affects_type_identity } */
345 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute
,
347 { "interrupt_handler", 0, 0, true, false, false,
348 m68k_handle_fndecl_attribute
, false },
349 { "interrupt_thread", 0, 0, true, false, false,
350 m68k_handle_fndecl_attribute
, false },
351 { NULL
, 0, 0, false, false, false, NULL
, false }
354 struct gcc_target targetm
= TARGET_INITIALIZER
;
356 /* Base flags for 68k ISAs. */
357 #define FL_FOR_isa_00 FL_ISA_68000
358 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
359 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
360 generated 68881 code for 68020 and 68030 targets unless explicitly told
362 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
363 | FL_BITFIELD | FL_68881 | FL_CAS)
364 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
365 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
367 /* Base flags for ColdFire ISAs. */
368 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
369 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
370 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
371 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
372 /* ISA_C is not upwardly compatible with ISA_B. */
373 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
377 /* Traditional 68000 instruction sets. */
383 /* ColdFire instruction set variants. */
391 /* Information about one of the -march, -mcpu or -mtune arguments. */
392 struct m68k_target_selection
394 /* The argument being described. */
397 /* For -mcpu, this is the device selected by the option.
398 For -mtune and -march, it is a representative device
399 for the microarchitecture or ISA respectively. */
400 enum target_device device
;
402 /* The M68K_DEVICE fields associated with DEVICE. See the comment
403 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
405 enum uarch_type microarch
;
410 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
411 static const struct m68k_target_selection all_devices
[] =
413 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
414 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
415 #include "m68k-devices.def"
417 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
420 /* A list of all ISAs, mapping each one to a representative device.
421 Used for -march selection. */
422 static const struct m68k_target_selection all_isas
[] =
424 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
425 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
426 #include "m68k-isas.def"
428 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
431 /* A list of all microarchitectures, mapping each one to a representative
432 device. Used for -mtune selection. */
433 static const struct m68k_target_selection all_microarchs
[] =
435 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
436 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
437 #include "m68k-microarchs.def"
438 #undef M68K_MICROARCH
439 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
442 /* The entries associated with the -mcpu, -march and -mtune settings,
443 or null for options that have not been used. */
444 const struct m68k_target_selection
*m68k_cpu_entry
;
445 const struct m68k_target_selection
*m68k_arch_entry
;
446 const struct m68k_target_selection
*m68k_tune_entry
;
448 /* Which CPU we are generating code for. */
449 enum target_device m68k_cpu
;
451 /* Which microarchitecture to tune for. */
452 enum uarch_type m68k_tune
;
454 /* Which FPU to use. */
455 enum fpu_type m68k_fpu
;
457 /* The set of FL_* flags that apply to the target processor. */
458 unsigned int m68k_cpu_flags
;
460 /* The set of FL_* flags that apply to the processor to be tuned for. */
461 unsigned int m68k_tune_flags
;
463 /* Asm templates for calling or jumping to an arbitrary symbolic address,
464 or NULL if such calls or jumps are not supported. The address is held
466 const char *m68k_symbolic_call
;
467 const char *m68k_symbolic_jump
;
469 /* Enum variable that corresponds to m68k_symbolic_call values. */
470 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
473 /* Implement TARGET_OPTION_OVERRIDE. */
476 m68k_option_override (void)
478 const struct m68k_target_selection
*entry
;
479 unsigned long target_mask
;
481 if (global_options_set
.x_m68k_arch_option
)
482 m68k_arch_entry
= &all_isas
[m68k_arch_option
];
484 if (global_options_set
.x_m68k_cpu_option
)
485 m68k_cpu_entry
= &all_devices
[(int) m68k_cpu_option
];
487 if (global_options_set
.x_m68k_tune_option
)
488 m68k_tune_entry
= &all_microarchs
[(int) m68k_tune_option
];
496 -march=ARCH should generate code that runs any processor
497 implementing architecture ARCH. -mcpu=CPU should override -march
498 and should generate code that runs on processor CPU, making free
499 use of any instructions that CPU understands. -mtune=UARCH applies
500 on top of -mcpu or -march and optimizes the code for UARCH. It does
501 not change the target architecture. */
504 /* Complain if the -march setting is for a different microarchitecture,
505 or includes flags that the -mcpu setting doesn't. */
507 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
508 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
509 warning (0, "-mcpu=%s conflicts with -march=%s",
510 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
512 entry
= m68k_cpu_entry
;
515 entry
= m68k_arch_entry
;
518 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
520 m68k_cpu_flags
= entry
->flags
;
522 /* Use the architecture setting to derive default values for
526 /* ColdFire is lenient about alignment. */
527 if (!TARGET_COLDFIRE
)
528 target_mask
|= MASK_STRICT_ALIGNMENT
;
530 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
531 target_mask
|= MASK_BITFIELD
;
532 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
533 target_mask
|= MASK_CF_HWDIV
;
534 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
535 target_mask
|= MASK_HARD_FLOAT
;
536 target_flags
|= target_mask
& ~target_flags_explicit
;
538 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
539 m68k_cpu
= entry
->device
;
542 m68k_tune
= m68k_tune_entry
->microarch
;
543 m68k_tune_flags
= m68k_tune_entry
->flags
;
545 #ifdef M68K_DEFAULT_TUNE
546 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
548 enum target_device dev
;
549 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
550 m68k_tune_flags
= all_devices
[dev
].flags
;
555 m68k_tune
= entry
->microarch
;
556 m68k_tune_flags
= entry
->flags
;
559 /* Set the type of FPU. */
560 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
561 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
564 /* Sanity check to ensure that msep-data and mid-sahred-library are not
565 * both specified together. Doing so simply doesn't make sense.
567 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
568 error ("cannot specify both -msep-data and -mid-shared-library");
570 /* If we're generating code for a separate A5 relative data segment,
571 * we've got to enable -fPIC as well. This might be relaxable to
572 * -fpic but it hasn't been tested properly.
574 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
577 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
578 error if the target does not support them. */
579 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
580 error ("-mpcrel -fPIC is not currently supported on selected cpu");
582 /* ??? A historic way of turning on pic, or is this intended to
583 be an embedded thing that doesn't have the same name binding
584 significance that it does on hosted ELF systems? */
585 if (TARGET_PCREL
&& flag_pic
== 0)
590 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
592 m68k_symbolic_jump
= "jra %a0";
594 else if (TARGET_ID_SHARED_LIBRARY
)
595 /* All addresses must be loaded from the GOT. */
597 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
600 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
602 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
605 /* No unconditional long branch */;
606 else if (TARGET_PCREL
)
607 m68k_symbolic_jump
= "bra%.l %c0";
609 m68k_symbolic_jump
= "bra%.l %p0";
610 /* Turn off function cse if we are doing PIC. We always want
611 function call to be done as `bsr foo@PLTPC'. */
612 /* ??? It's traditional to do this for -mpcrel too, but it isn't
613 clear how intentional that is. */
614 flag_no_function_cse
= 1;
617 switch (m68k_symbolic_call_var
)
619 case M68K_SYMBOLIC_CALL_JSR
:
620 m68k_symbolic_call
= "jsr %a0";
623 case M68K_SYMBOLIC_CALL_BSR_C
:
624 m68k_symbolic_call
= "bsr%.l %c0";
627 case M68K_SYMBOLIC_CALL_BSR_P
:
628 m68k_symbolic_call
= "bsr%.l %p0";
631 case M68K_SYMBOLIC_CALL_NONE
:
632 gcc_assert (m68k_symbolic_call
== NULL
);
639 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
640 if (align_labels
> 2)
642 warning (0, "-falign-labels=%d is not supported", align_labels
);
647 warning (0, "-falign-loops=%d is not supported", align_loops
);
652 if (stack_limit_rtx
!= NULL_RTX
&& !TARGET_68020
)
654 warning (0, "-fstack-limit- options are not supported on this cpu");
655 stack_limit_rtx
= NULL_RTX
;
658 SUBTARGET_OVERRIDE_OPTIONS
;
660 /* Setup scheduling options. */
662 m68k_sched_cpu
= CPU_CFV1
;
664 m68k_sched_cpu
= CPU_CFV2
;
666 m68k_sched_cpu
= CPU_CFV3
;
668 m68k_sched_cpu
= CPU_CFV4
;
671 m68k_sched_cpu
= CPU_UNKNOWN
;
672 flag_schedule_insns
= 0;
673 flag_schedule_insns_after_reload
= 0;
674 flag_modulo_sched
= 0;
675 flag_live_range_shrinkage
= 0;
678 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
680 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
681 m68k_sched_mac
= MAC_CF_EMAC
;
682 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
683 m68k_sched_mac
= MAC_CF_MAC
;
685 m68k_sched_mac
= MAC_NO
;
689 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
692 m68k_override_options_after_change (void)
694 if (m68k_sched_cpu
== CPU_UNKNOWN
)
696 flag_schedule_insns
= 0;
697 flag_schedule_insns_after_reload
= 0;
698 flag_modulo_sched
= 0;
699 flag_live_range_shrinkage
= 0;
703 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
704 given argument and NAME is the argument passed to -mcpu. Return NULL
705 if -mcpu was not passed. */
708 m68k_cpp_cpu_ident (const char *prefix
)
712 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
715 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
716 given argument and NAME is the name of the representative device for
717 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
720 m68k_cpp_cpu_family (const char *prefix
)
724 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
727 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
728 "interrupt_handler" attribute and interrupt_thread if FUNC has an
729 "interrupt_thread" attribute. Otherwise, return
730 m68k_fk_normal_function. */
732 enum m68k_function_kind
733 m68k_get_function_kind (tree func
)
737 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
739 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
741 return m68k_fk_interrupt_handler
;
743 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
745 return m68k_fk_interrupt_handler
;
747 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
749 return m68k_fk_interrupt_thread
;
751 return m68k_fk_normal_function
;
754 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
755 struct attribute_spec.handler. */
757 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
758 tree args ATTRIBUTE_UNUSED
,
759 int flags ATTRIBUTE_UNUSED
,
762 if (TREE_CODE (*node
) != FUNCTION_DECL
)
764 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
766 *no_add_attrs
= true;
769 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
771 error ("multiple interrupt attributes not allowed");
772 *no_add_attrs
= true;
776 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
778 error ("interrupt_thread is available only on fido");
779 *no_add_attrs
= true;
786 m68k_compute_frame_layout (void)
790 enum m68k_function_kind func_kind
=
791 m68k_get_function_kind (current_function_decl
);
792 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
793 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
795 /* Only compute the frame once per function.
796 Don't cache information until reload has been completed. */
797 if (current_frame
.funcdef_no
== current_function_funcdef_no
801 current_frame
.size
= (get_frame_size () + 3) & -4;
805 /* Interrupt thread does not need to save any register. */
806 if (!interrupt_thread
)
807 for (regno
= 0; regno
< 16; regno
++)
808 if (m68k_save_reg (regno
, interrupt_handler
))
810 mask
|= 1 << (regno
- D0_REG
);
813 current_frame
.offset
= saved
* 4;
814 current_frame
.reg_no
= saved
;
815 current_frame
.reg_mask
= mask
;
817 current_frame
.foffset
= 0;
819 if (TARGET_HARD_FLOAT
)
821 /* Interrupt thread does not need to save any register. */
822 if (!interrupt_thread
)
823 for (regno
= 16; regno
< 24; regno
++)
824 if (m68k_save_reg (regno
, interrupt_handler
))
826 mask
|= 1 << (regno
- FP0_REG
);
829 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
830 current_frame
.offset
+= current_frame
.foffset
;
832 current_frame
.fpu_no
= saved
;
833 current_frame
.fpu_mask
= mask
;
835 /* Remember what function this frame refers to. */
836 current_frame
.funcdef_no
= current_function_funcdef_no
;
839 /* Worker function for TARGET_CAN_ELIMINATE. */
842 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
844 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
848 m68k_initial_elimination_offset (int from
, int to
)
851 /* The arg pointer points 8 bytes before the start of the arguments,
852 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
853 frame pointer in most frames. */
854 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
855 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
856 return argptr_offset
;
858 m68k_compute_frame_layout ();
860 gcc_assert (to
== STACK_POINTER_REGNUM
);
863 case ARG_POINTER_REGNUM
:
864 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
865 case FRAME_POINTER_REGNUM
:
866 return current_frame
.offset
+ current_frame
.size
;
872 /* Refer to the array `regs_ever_live' to determine which registers
873 to save; `regs_ever_live[I]' is nonzero if register number I
874 is ever used in the function. This function is responsible for
875 knowing which registers should not be saved even if used.
876 Return true if we need to save REGNO. */
879 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
881 if (flag_pic
&& regno
== PIC_REG
)
883 if (crtl
->saves_all_registers
)
885 if (crtl
->uses_pic_offset_table
)
887 /* Reload may introduce constant pool references into a function
888 that thitherto didn't need a PIC register. Note that the test
889 above will not catch that case because we will only set
890 crtl->uses_pic_offset_table when emitting
891 the address reloads. */
892 if (crtl
->uses_const_pool
)
896 if (crtl
->calls_eh_return
)
901 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
902 if (test
== INVALID_REGNUM
)
909 /* Fixed regs we never touch. */
910 if (fixed_regs
[regno
])
913 /* The frame pointer (if it is such) is handled specially. */
914 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
917 /* Interrupt handlers must also save call_used_regs
918 if they are live or when calling nested functions. */
919 if (interrupt_handler
)
921 if (df_regs_ever_live_p (regno
))
924 if (!crtl
->is_leaf
&& call_used_regs
[regno
])
928 /* Never need to save registers that aren't touched. */
929 if (!df_regs_ever_live_p (regno
))
932 /* Otherwise save everything that isn't call-clobbered. */
933 return !call_used_regs
[regno
];
936 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
937 the lowest memory address. COUNT is the number of registers to be
938 moved, with register REGNO + I being moved if bit I of MASK is set.
939 STORE_P specifies the direction of the move and ADJUST_STACK_P says
940 whether or not this is pre-decrement (if STORE_P) or post-increment
941 (if !STORE_P) operation. */
944 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
945 unsigned int count
, unsigned int regno
,
946 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
949 rtx body
, addr
, src
, operands
[2];
952 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
953 mode
= reg_raw_mode
[regno
];
958 src
= plus_constant (Pmode
, base
,
960 * GET_MODE_SIZE (mode
)
961 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
962 XVECEXP (body
, 0, i
++) = gen_rtx_SET (base
, src
);
965 for (; mask
!= 0; mask
>>= 1, regno
++)
968 addr
= plus_constant (Pmode
, base
, offset
);
969 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
970 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
971 XVECEXP (body
, 0, i
++)
972 = gen_rtx_SET (operands
[0], operands
[1]);
973 offset
+= GET_MODE_SIZE (mode
);
975 gcc_assert (i
== XVECLEN (body
, 0));
977 return emit_insn (body
);
980 /* Make INSN a frame-related instruction. */
983 m68k_set_frame_related (rtx_insn
*insn
)
988 RTX_FRAME_RELATED_P (insn
) = 1;
989 body
= PATTERN (insn
);
990 if (GET_CODE (body
) == PARALLEL
)
991 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
992 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
995 /* Emit RTL for the "prologue" define_expand. */
998 m68k_expand_prologue (void)
1000 HOST_WIDE_INT fsize_with_regs
;
1001 rtx limit
, src
, dest
;
1003 m68k_compute_frame_layout ();
1005 if (flag_stack_usage_info
)
1006 current_function_static_stack_size
1007 = current_frame
.size
+ current_frame
.offset
;
1009 /* If the stack limit is a symbol, we can check it here,
1010 before actually allocating the space. */
1011 if (crtl
->limit_stack
1012 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
1014 limit
= plus_constant (Pmode
, stack_limit_rtx
, current_frame
.size
+ 4);
1015 if (!m68k_legitimate_constant_p (Pmode
, limit
))
1017 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
1018 limit
= gen_rtx_REG (Pmode
, D0_REG
);
1020 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
1021 stack_pointer_rtx
, limit
),
1022 stack_pointer_rtx
, limit
,
1026 fsize_with_regs
= current_frame
.size
;
1027 if (TARGET_COLDFIRE
)
1029 /* ColdFire's move multiple instructions do not allow pre-decrement
1030 addressing. Add the size of movem saves to the initial stack
1031 allocation instead. */
1032 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1033 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1034 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1035 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1038 if (frame_pointer_needed
)
1040 if (fsize_with_regs
== 0 && TUNE_68040
)
1042 /* On the 68040, two separate moves are faster than link.w 0. */
1043 dest
= gen_frame_mem (Pmode
,
1044 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1045 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1046 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1047 stack_pointer_rtx
));
1049 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1050 m68k_set_frame_related
1051 (emit_insn (gen_link (frame_pointer_rtx
,
1052 GEN_INT (-4 - fsize_with_regs
))));
1055 m68k_set_frame_related
1056 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1057 m68k_set_frame_related
1058 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1060 GEN_INT (-fsize_with_regs
))));
1063 /* If the frame pointer is needed, emit a special barrier that
1064 will prevent the scheduler from moving stores to the frame
1065 before the stack adjustment. */
1066 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1068 else if (fsize_with_regs
!= 0)
1069 m68k_set_frame_related
1070 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1072 GEN_INT (-fsize_with_regs
))));
1074 if (current_frame
.fpu_mask
)
1076 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1078 m68k_set_frame_related
1079 (m68k_emit_movem (stack_pointer_rtx
,
1080 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1081 current_frame
.fpu_no
, FP0_REG
,
1082 current_frame
.fpu_mask
, true, true));
1087 /* If we're using moveml to save the integer registers,
1088 the stack pointer will point to the bottom of the moveml
1089 save area. Find the stack offset of the first FP register. */
1090 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1093 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1094 m68k_set_frame_related
1095 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1096 current_frame
.fpu_no
, FP0_REG
,
1097 current_frame
.fpu_mask
, true, false));
1101 /* If the stack limit is not a symbol, check it here.
1102 This has the disadvantage that it may be too late... */
1103 if (crtl
->limit_stack
)
1105 if (REG_P (stack_limit_rtx
))
1106 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1108 stack_pointer_rtx
, stack_limit_rtx
,
1111 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1112 warning (0, "stack limit expression is not supported");
1115 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1117 /* Store each register separately in the same order moveml does. */
1120 for (i
= 16; i
-- > 0; )
1121 if (current_frame
.reg_mask
& (1 << i
))
1123 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1124 dest
= gen_frame_mem (SImode
,
1125 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1126 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1131 if (TARGET_COLDFIRE
)
1132 /* The required register save space has already been allocated.
1133 The first register should be stored at (%sp). */
1134 m68k_set_frame_related
1135 (m68k_emit_movem (stack_pointer_rtx
, 0,
1136 current_frame
.reg_no
, D0_REG
,
1137 current_frame
.reg_mask
, true, false));
1139 m68k_set_frame_related
1140 (m68k_emit_movem (stack_pointer_rtx
,
1141 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1142 current_frame
.reg_no
, D0_REG
,
1143 current_frame
.reg_mask
, true, true));
1146 if (!TARGET_SEP_DATA
1147 && crtl
->uses_pic_offset_table
)
1148 emit_insn (gen_load_got (pic_offset_table_rtx
));
1151 /* Return true if a simple (return) instruction is sufficient for this
1152 instruction (i.e. if no epilogue is needed). */
1155 m68k_use_return_insn (void)
1157 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1160 m68k_compute_frame_layout ();
1161 return current_frame
.offset
== 0;
1164 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1165 SIBCALL_P says which.
1167 The function epilogue should not depend on the current stack pointer!
1168 It should use the frame pointer only, if there is a frame pointer.
1169 This is mandatory because of alloca; we also take advantage of it to
1170 omit stack adjustments before returning. */
1173 m68k_expand_epilogue (bool sibcall_p
)
1175 HOST_WIDE_INT fsize
, fsize_with_regs
;
1176 bool big
, restore_from_sp
;
1178 m68k_compute_frame_layout ();
1180 fsize
= current_frame
.size
;
1182 restore_from_sp
= false;
1184 /* FIXME : crtl->is_leaf below is too strong.
1185 What we really need to know there is if there could be pending
1186 stack adjustment needed at that point. */
1187 restore_from_sp
= (!frame_pointer_needed
1188 || (!cfun
->calls_alloca
&& crtl
->is_leaf
));
1190 /* fsize_with_regs is the size we need to adjust the sp when
1191 popping the frame. */
1192 fsize_with_regs
= fsize
;
1193 if (TARGET_COLDFIRE
&& restore_from_sp
)
1195 /* ColdFire's move multiple instructions do not allow post-increment
1196 addressing. Add the size of movem loads to the final deallocation
1198 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1199 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1200 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1201 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1204 if (current_frame
.offset
+ fsize
>= 0x8000
1206 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1209 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1210 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1212 /* ColdFire's move multiple instructions do not support the
1213 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1214 stack-based restore. */
1215 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1216 GEN_INT (-(current_frame
.offset
+ fsize
)));
1217 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1218 gen_rtx_REG (Pmode
, A1_REG
),
1219 frame_pointer_rtx
));
1220 restore_from_sp
= true;
1224 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1230 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1232 /* Restore each register separately in the same order moveml does. */
1234 HOST_WIDE_INT offset
;
1236 offset
= current_frame
.offset
+ fsize
;
1237 for (i
= 0; i
< 16; i
++)
1238 if (current_frame
.reg_mask
& (1 << i
))
1244 /* Generate the address -OFFSET(%fp,%a1.l). */
1245 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1246 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1247 addr
= plus_constant (Pmode
, addr
, -offset
);
1249 else if (restore_from_sp
)
1250 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1252 addr
= plus_constant (Pmode
, frame_pointer_rtx
, -offset
);
1253 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1254 gen_frame_mem (SImode
, addr
));
1255 offset
-= GET_MODE_SIZE (SImode
);
1258 else if (current_frame
.reg_mask
)
1261 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1262 gen_rtx_REG (Pmode
, A1_REG
),
1264 -(current_frame
.offset
+ fsize
),
1265 current_frame
.reg_no
, D0_REG
,
1266 current_frame
.reg_mask
, false, false);
1267 else if (restore_from_sp
)
1268 m68k_emit_movem (stack_pointer_rtx
, 0,
1269 current_frame
.reg_no
, D0_REG
,
1270 current_frame
.reg_mask
, false,
1273 m68k_emit_movem (frame_pointer_rtx
,
1274 -(current_frame
.offset
+ fsize
),
1275 current_frame
.reg_no
, D0_REG
,
1276 current_frame
.reg_mask
, false, false);
1279 if (current_frame
.fpu_no
> 0)
1282 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1283 gen_rtx_REG (Pmode
, A1_REG
),
1285 -(current_frame
.foffset
+ fsize
),
1286 current_frame
.fpu_no
, FP0_REG
,
1287 current_frame
.fpu_mask
, false, false);
1288 else if (restore_from_sp
)
1290 if (TARGET_COLDFIRE
)
1294 /* If we used moveml to restore the integer registers, the
1295 stack pointer will still point to the bottom of the moveml
1296 save area. Find the stack offset of the first FP
1298 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1301 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1302 m68k_emit_movem (stack_pointer_rtx
, offset
,
1303 current_frame
.fpu_no
, FP0_REG
,
1304 current_frame
.fpu_mask
, false, false);
1307 m68k_emit_movem (stack_pointer_rtx
, 0,
1308 current_frame
.fpu_no
, FP0_REG
,
1309 current_frame
.fpu_mask
, false, true);
1312 m68k_emit_movem (frame_pointer_rtx
,
1313 -(current_frame
.foffset
+ fsize
),
1314 current_frame
.fpu_no
, FP0_REG
,
1315 current_frame
.fpu_mask
, false, false);
1318 if (frame_pointer_needed
)
1319 emit_insn (gen_unlink (frame_pointer_rtx
));
1320 else if (fsize_with_regs
)
1321 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1323 GEN_INT (fsize_with_regs
)));
1325 if (crtl
->calls_eh_return
)
1326 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1328 EH_RETURN_STACKADJ_RTX
));
1331 emit_jump_insn (ret_rtx
);
1334 /* Return true if X is a valid comparison operator for the dbcc
1337 Note it rejects floating point comparison operators.
1338 (In the future we could use Fdbcc).
1340 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1343 valid_dbcc_comparison_p_2 (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
)
1345 switch (GET_CODE (x
))
1347 case EQ
: case NE
: case GTU
: case LTU
:
1351 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1353 case GT
: case LT
: case GE
: case LE
:
1354 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1360 /* Return nonzero if flags are currently in the 68881 flag register. */
1362 flags_in_68881 (void)
1364 /* We could add support for these in the future */
1365 return cc_status
.flags
& CC_IN_68881
;
1368 /* Return true if PARALLEL contains register REGNO. */
1370 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1374 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1377 if (GET_CODE (parallel
) != PARALLEL
)
1380 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1384 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1385 if (REG_P (x
) && REGNO (x
) == regno
)
1392 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1395 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1397 enum m68k_function_kind kind
;
1399 /* We cannot use sibcalls for nested functions because we use the
1400 static chain register for indirect calls. */
1401 if (CALL_EXPR_STATIC_CHAIN (exp
))
1404 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1406 /* Check that the return value locations are the same. For
1407 example that we aren't returning a value from the sibling in
1408 a D0 register but then need to transfer it to a A0 register. */
1412 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1414 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1416 /* Check that the values are equal or that the result the callee
1417 function returns is superset of what the current function returns. */
1418 if (!(rtx_equal_p (cfun_value
, call_value
)
1419 || (REG_P (cfun_value
)
1420 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1424 kind
= m68k_get_function_kind (current_function_decl
);
1425 if (kind
== m68k_fk_normal_function
)
1426 /* We can always sibcall from a normal function, because it's
1427 undefined if it is calling an interrupt function. */
1430 /* Otherwise we can only sibcall if the function kind is known to be
1432 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1438 /* On the m68k all args are always pushed. */
1441 m68k_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1442 machine_mode mode ATTRIBUTE_UNUSED
,
1443 const_tree type ATTRIBUTE_UNUSED
,
1444 bool named ATTRIBUTE_UNUSED
)
1450 m68k_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1451 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1453 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1455 *cum
+= (mode
!= BLKmode
1456 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1457 : (int_size_in_bytes (type
) + 3) & ~3);
1460 /* Convert X to a legitimate function call memory reference and return the
1464 m68k_legitimize_call_address (rtx x
)
1466 gcc_assert (MEM_P (x
));
1467 if (call_operand (XEXP (x
, 0), VOIDmode
))
1469 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1472 /* Likewise for sibling calls. */
1475 m68k_legitimize_sibcall_address (rtx x
)
1477 gcc_assert (MEM_P (x
));
1478 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1481 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1482 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1485 /* Convert X to a legitimate address and return it if successful. Otherwise
1488 For the 68000, we handle X+REG by loading X into a register R and
1489 using R+REG. R will go in an address reg and indexing will be used.
1490 However, if REG is a broken-out memory address or multiplication,
1491 nothing needs to be done because REG can certainly go in an address reg. */
1494 m68k_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
1496 if (m68k_tls_symbol_p (x
))
1497 return m68k_legitimize_tls_address (x
);
1499 if (GET_CODE (x
) == PLUS
)
1501 int ch
= (x
) != (oldx
);
1504 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1506 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1509 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1511 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1514 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1518 if (GET_CODE (XEXP (x
, 1)) == REG
1519 && GET_CODE (XEXP (x
, 0)) == REG
)
1521 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1524 x
= force_operand (x
, 0);
1528 if (memory_address_p (mode
, x
))
1531 if (GET_CODE (XEXP (x
, 0)) == REG
1532 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1533 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1534 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1536 rtx temp
= gen_reg_rtx (Pmode
);
1537 rtx val
= force_operand (XEXP (x
, 1), 0);
1538 emit_move_insn (temp
, val
);
1541 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1542 && GET_CODE (XEXP (x
, 0)) == REG
)
1543 x
= force_operand (x
, 0);
1545 else if (GET_CODE (XEXP (x
, 1)) == REG
1546 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1547 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1548 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1550 rtx temp
= gen_reg_rtx (Pmode
);
1551 rtx val
= force_operand (XEXP (x
, 0), 0);
1552 emit_move_insn (temp
, val
);
1555 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1556 && GET_CODE (XEXP (x
, 1)) == REG
)
1557 x
= force_operand (x
, 0);
1565 /* Output a dbCC; jCC sequence. Note we do not handle the
1566 floating point version of this sequence (Fdbcc). We also
1567 do not handle alternative conditions when CC_NO_OVERFLOW is
1568 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1569 kick those out before we get here. */
1572 output_dbcc_and_branch (rtx
*operands
)
1574 switch (GET_CODE (operands
[3]))
1577 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1581 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1585 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1589 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1593 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1597 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1601 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1605 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1609 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1613 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1620 /* If the decrement is to be done in SImode, then we have
1621 to compensate for the fact that dbcc decrements in HImode. */
1622 switch (GET_MODE (operands
[0]))
1625 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1637 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1640 enum rtx_code op_code
= GET_CODE (op
);
1642 /* This does not produce a useful cc. */
1645 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1646 below. Swap the operands and change the op if these requirements
1647 are not fulfilled. */
1648 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1652 operand1
= operand2
;
1654 op_code
= swap_condition (op_code
);
1656 loperands
[0] = operand1
;
1657 if (GET_CODE (operand1
) == REG
)
1658 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1660 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1661 if (operand2
!= const0_rtx
)
1663 loperands
[2] = operand2
;
1664 if (GET_CODE (operand2
) == REG
)
1665 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1667 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1669 loperands
[4] = gen_label_rtx ();
1670 if (operand2
!= const0_rtx
)
1671 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1674 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1675 output_asm_insn ("tst%.l %0", loperands
);
1677 output_asm_insn ("cmp%.w #0,%0", loperands
);
1679 output_asm_insn ("jne %l4", loperands
);
1681 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1682 output_asm_insn ("tst%.l %1", loperands
);
1684 output_asm_insn ("cmp%.w #0,%1", loperands
);
1687 loperands
[5] = dest
;
1692 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1693 CODE_LABEL_NUMBER (loperands
[4]));
1694 output_asm_insn ("seq %5", loperands
);
1698 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1699 CODE_LABEL_NUMBER (loperands
[4]));
1700 output_asm_insn ("sne %5", loperands
);
1704 loperands
[6] = gen_label_rtx ();
1705 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1706 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1707 CODE_LABEL_NUMBER (loperands
[4]));
1708 output_asm_insn ("sgt %5", loperands
);
1709 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1710 CODE_LABEL_NUMBER (loperands
[6]));
1714 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1715 CODE_LABEL_NUMBER (loperands
[4]));
1716 output_asm_insn ("shi %5", loperands
);
1720 loperands
[6] = gen_label_rtx ();
1721 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1722 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1723 CODE_LABEL_NUMBER (loperands
[4]));
1724 output_asm_insn ("slt %5", loperands
);
1725 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1726 CODE_LABEL_NUMBER (loperands
[6]));
1730 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1731 CODE_LABEL_NUMBER (loperands
[4]));
1732 output_asm_insn ("scs %5", loperands
);
1736 loperands
[6] = gen_label_rtx ();
1737 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1738 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1739 CODE_LABEL_NUMBER (loperands
[4]));
1740 output_asm_insn ("sge %5", loperands
);
1741 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1742 CODE_LABEL_NUMBER (loperands
[6]));
1746 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1747 CODE_LABEL_NUMBER (loperands
[4]));
1748 output_asm_insn ("scc %5", loperands
);
1752 loperands
[6] = gen_label_rtx ();
1753 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1754 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1755 CODE_LABEL_NUMBER (loperands
[4]));
1756 output_asm_insn ("sle %5", loperands
);
1757 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1758 CODE_LABEL_NUMBER (loperands
[6]));
1762 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1763 CODE_LABEL_NUMBER (loperands
[4]));
1764 output_asm_insn ("sls %5", loperands
);
1774 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx_insn
*insn
, int signpos
)
1776 operands
[0] = countop
;
1777 operands
[1] = dataop
;
1779 if (GET_CODE (countop
) == CONST_INT
)
1781 register int count
= INTVAL (countop
);
1782 /* If COUNT is bigger than size of storage unit in use,
1783 advance to the containing unit of same size. */
1784 if (count
> signpos
)
1786 int offset
= (count
& ~signpos
) / 8;
1787 count
= count
& signpos
;
1788 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1790 if (count
== signpos
)
1791 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1793 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1795 /* These three statements used to use next_insns_test_no...
1796 but it appears that this should do the same job. */
1798 && next_insn_tests_no_inequality (insn
))
1801 && next_insn_tests_no_inequality (insn
))
1804 && next_insn_tests_no_inequality (insn
))
1806 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1807 On some m68k variants unfortunately that's slower than btst.
1808 On 68000 and higher, that should also work for all HImode operands. */
1809 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1811 if (count
== 3 && DATA_REG_P (operands
[1])
1812 && next_insn_tests_no_inequality (insn
))
1814 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1815 return "move%.w %1,%%ccr";
1817 if (count
== 2 && DATA_REG_P (operands
[1])
1818 && next_insn_tests_no_inequality (insn
))
1820 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1821 return "move%.w %1,%%ccr";
1823 /* count == 1 followed by bvc/bvs and
1824 count == 0 followed by bcc/bcs are also possible, but need
1825 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1828 cc_status
.flags
= CC_NOT_NEGATIVE
;
1830 return "btst %0,%1";
1833 /* Return true if X is a legitimate base register. STRICT_P says
1834 whether we need strict checking. */
1837 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1839 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1840 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1845 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1846 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1849 /* Return true if X is a legitimate index register. STRICT_P says
1850 whether we need strict checking. */
1853 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1855 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1860 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1861 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1864 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1865 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1866 ADDRESS if so. STRICT_P says whether we need strict checking. */
1869 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1873 /* Check for a scale factor. */
1875 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1876 && GET_CODE (x
) == MULT
1877 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1878 && (INTVAL (XEXP (x
, 1)) == 2
1879 || INTVAL (XEXP (x
, 1)) == 4
1880 || (INTVAL (XEXP (x
, 1)) == 8
1881 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1883 scale
= INTVAL (XEXP (x
, 1));
1887 /* Check for a word extension. */
1888 if (!TARGET_COLDFIRE
1889 && GET_CODE (x
) == SIGN_EXTEND
1890 && GET_MODE (XEXP (x
, 0)) == HImode
)
1893 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1895 address
->scale
= scale
;
1903 /* Return true if X is an illegitimate symbolic constant. */
1906 m68k_illegitimate_symbolic_constant_p (rtx x
)
1910 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1912 split_const (x
, &base
, &offset
);
1913 if (GET_CODE (base
) == SYMBOL_REF
1914 && !offset_within_block_p (base
, INTVAL (offset
)))
1917 return m68k_tls_reference_p (x
, false);
1920 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1923 m68k_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1925 return m68k_illegitimate_symbolic_constant_p (x
);
1928 /* Return true if X is a legitimate constant address that can reach
1929 bytes in the range [X, X + REACH). STRICT_P says whether we need
1933 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1937 if (!CONSTANT_ADDRESS_P (x
))
1941 && !(strict_p
&& TARGET_PCREL
)
1942 && symbolic_operand (x
, VOIDmode
))
1945 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1947 split_const (x
, &base
, &offset
);
1948 if (GET_CODE (base
) == SYMBOL_REF
1949 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1953 return !m68k_tls_reference_p (x
, false);
1956 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1957 labels will become jump tables. */
1960 m68k_jump_table_ref_p (rtx x
)
1962 if (GET_CODE (x
) != LABEL_REF
)
1965 rtx_insn
*insn
= as_a
<rtx_insn
*> (XEXP (x
, 0));
1966 if (!NEXT_INSN (insn
) && !PREV_INSN (insn
))
1969 insn
= next_nonnote_insn (insn
);
1970 return insn
&& JUMP_TABLE_DATA_P (insn
);
1973 /* Return true if X is a legitimate address for values of mode MODE.
1974 STRICT_P says whether strict checking is needed. If the address
1975 is valid, describe its components in *ADDRESS. */
1978 m68k_decompose_address (machine_mode mode
, rtx x
,
1979 bool strict_p
, struct m68k_address
*address
)
1983 memset (address
, 0, sizeof (*address
));
1985 if (mode
== BLKmode
)
1988 reach
= GET_MODE_SIZE (mode
);
1990 /* Check for (An) (mode 2). */
1991 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1997 /* Check for -(An) and (An)+ (modes 3 and 4). */
1998 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1999 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
2001 address
->code
= GET_CODE (x
);
2002 address
->base
= XEXP (x
, 0);
2006 /* Check for (d16,An) (mode 5). */
2007 if (GET_CODE (x
) == PLUS
2008 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2009 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
2010 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
2012 address
->base
= XEXP (x
, 0);
2013 address
->offset
= XEXP (x
, 1);
2017 /* Check for GOT loads. These are (bd,An,Xn) addresses if
2018 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
2020 if (GET_CODE (x
) == PLUS
2021 && XEXP (x
, 0) == pic_offset_table_rtx
)
2023 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
2024 they are invalid in this context. */
2025 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
2027 address
->base
= XEXP (x
, 0);
2028 address
->offset
= XEXP (x
, 1);
2033 /* The ColdFire FPU only accepts addressing modes 2-5. */
2034 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2037 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2038 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2039 All these modes are variations of mode 7. */
2040 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
2042 address
->offset
= x
;
2046 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2049 ??? do_tablejump creates these addresses before placing the target
2050 label, so we have to assume that unplaced labels are jump table
2051 references. It seems unlikely that we would ever generate indexed
2052 accesses to unplaced labels in other cases. */
2053 if (GET_CODE (x
) == PLUS
2054 && m68k_jump_table_ref_p (XEXP (x
, 1))
2055 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2057 address
->offset
= XEXP (x
, 1);
2061 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2062 (bd,An,Xn.SIZE*SCALE) addresses. */
2066 /* Check for a nonzero base displacement. */
2067 if (GET_CODE (x
) == PLUS
2068 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2070 address
->offset
= XEXP (x
, 1);
2074 /* Check for a suppressed index register. */
2075 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2081 /* Check for a suppressed base register. Do not allow this case
2082 for non-symbolic offsets as it effectively gives gcc freedom
2083 to treat data registers as base registers, which can generate
2086 && symbolic_operand (address
->offset
, VOIDmode
)
2087 && m68k_decompose_index (x
, strict_p
, address
))
2092 /* Check for a nonzero base displacement. */
2093 if (GET_CODE (x
) == PLUS
2094 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2095 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2097 address
->offset
= XEXP (x
, 1);
2102 /* We now expect the sum of a base and an index. */
2103 if (GET_CODE (x
) == PLUS
)
2105 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2106 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2108 address
->base
= XEXP (x
, 0);
2112 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2113 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2115 address
->base
= XEXP (x
, 1);
2122 /* Return true if X is a legitimate address for values of mode MODE.
2123 STRICT_P says whether strict checking is needed. */
2126 m68k_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
2128 struct m68k_address address
;
2130 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2133 /* Return true if X is a memory, describing its address in ADDRESS if so.
2134 Apply strict checking if called during or after reload. */
2137 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2140 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2141 reload_in_progress
|| reload_completed
,
2145 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2148 m68k_legitimate_constant_p (machine_mode mode
, rtx x
)
2150 return mode
!= XFmode
&& !m68k_illegitimate_symbolic_constant_p (x
);
2153 /* Return true if X matches the 'Q' constraint. It must be a memory
2154 with a base address and no constant offset or index. */
2157 m68k_matches_q_p (rtx x
)
2159 struct m68k_address address
;
2161 return (m68k_legitimate_mem_p (x
, &address
)
2162 && address
.code
== UNKNOWN
2168 /* Return true if X matches the 'U' constraint. It must be a base address
2169 with a constant offset and no index. */
2172 m68k_matches_u_p (rtx x
)
2174 struct m68k_address address
;
2176 return (m68k_legitimate_mem_p (x
, &address
)
2177 && address
.code
== UNKNOWN
2183 /* Return GOT pointer. */
2188 if (pic_offset_table_rtx
== NULL_RTX
)
2189 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2191 crtl
->uses_pic_offset_table
= 1;
2193 return pic_offset_table_rtx
;
2196 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2198 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2199 RELOC_TLSIE
, RELOC_TLSLE
};
2201 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2203 /* Wrap symbol X into unspec representing relocation RELOC.
2204 BASE_REG - register that should be added to the result.
2205 TEMP_REG - if non-null, temporary register. */
2208 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2212 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2214 if (TARGET_COLDFIRE
&& use_x_p
)
2215 /* When compiling with -mx{got, tls} switch the code will look like this:
2217 move.l <X>@<RELOC>,<TEMP_REG>
2218 add.l <BASE_REG>,<TEMP_REG> */
2220 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2221 to put @RELOC after reference. */
2222 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2224 x
= gen_rtx_CONST (Pmode
, x
);
2226 if (temp_reg
== NULL
)
2228 gcc_assert (can_create_pseudo_p ());
2229 temp_reg
= gen_reg_rtx (Pmode
);
2232 emit_move_insn (temp_reg
, x
);
2233 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2238 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2240 x
= gen_rtx_CONST (Pmode
, x
);
2242 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2248 /* Helper for m68k_unwrap_symbol.
2249 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2250 sets *RELOC_PTR to relocation type for the symbol. */
2253 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2254 enum m68k_reloc
*reloc_ptr
)
2256 if (GET_CODE (orig
) == CONST
)
2259 enum m68k_reloc dummy
;
2263 if (reloc_ptr
== NULL
)
2266 /* Handle an addend. */
2267 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2268 && CONST_INT_P (XEXP (x
, 1)))
2271 if (GET_CODE (x
) == UNSPEC
)
2273 switch (XINT (x
, 1))
2275 case UNSPEC_RELOC16
:
2276 orig
= XVECEXP (x
, 0, 0);
2277 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2280 case UNSPEC_RELOC32
:
2281 if (unwrap_reloc32_p
)
2283 orig
= XVECEXP (x
, 0, 0);
2284 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2297 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2298 UNSPEC_RELOC32 wrappers. */
2301 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2303 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2306 /* Prescan insn before outputing assembler for it. */
2309 m68k_final_prescan_insn (rtx_insn
*insn ATTRIBUTE_UNUSED
,
2310 rtx
*operands
, int n_operands
)
2314 /* Combine and, possibly, other optimizations may do good job
2316 (const (unspec [(symbol)]))
2318 (const (plus (unspec [(symbol)])
2320 The problem with this is emitting @TLS or @GOT decorations.
2321 The decoration is emitted when processing (unspec), so the
2322 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2324 It seems that the easiest solution to this is to convert such
2326 (const (unspec [(plus (symbol)
2328 Note, that the top level of operand remains intact, so we don't have
2329 to patch up anything outside of the operand. */
2331 subrtx_var_iterator::array_type array
;
2332 for (i
= 0; i
< n_operands
; ++i
)
2338 FOR_EACH_SUBRTX_VAR (iter
, array
, op
, ALL
)
2341 if (m68k_unwrap_symbol (x
, true) != x
)
2345 gcc_assert (GET_CODE (x
) == CONST
);
2348 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2353 unspec
= XEXP (plus
, 0);
2354 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2355 addend
= XEXP (plus
, 1);
2356 gcc_assert (CONST_INT_P (addend
));
2358 /* We now have all the pieces, rearrange them. */
2360 /* Move symbol to plus. */
2361 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2363 /* Move plus inside unspec. */
2364 XVECEXP (unspec
, 0, 0) = plus
;
2366 /* Move unspec to top level of const. */
2367 XEXP (x
, 0) = unspec
;
2369 iter
.skip_subrtxes ();
2375 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2376 If REG is non-null, use it; generate new pseudo otherwise. */
2379 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2383 if (reg
== NULL_RTX
)
2385 gcc_assert (can_create_pseudo_p ());
2386 reg
= gen_reg_rtx (Pmode
);
2389 insn
= emit_move_insn (reg
, x
);
2390 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2392 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2397 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2401 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2403 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2405 x
= gen_rtx_MEM (Pmode
, x
);
2406 MEM_READONLY_P (x
) = 1;
2411 /* Legitimize PIC addresses. If the address is already
2412 position-independent, we return ORIG. Newly generated
2413 position-independent addresses go to REG. If we need more
2414 than one register, we lose.
2416 An address is legitimized by making an indirect reference
2417 through the Global Offset Table with the name of the symbol
2420 The assembler and linker are responsible for placing the
2421 address of the symbol in the GOT. The function prologue
2422 is responsible for initializing a5 to the starting address
2425 The assembler is also responsible for translating a symbol name
2426 into a constant displacement from the start of the GOT.
2428 A quick example may make things a little clearer:
2430 When not generating PIC code to store the value 12345 into _foo
2431 we would generate the following code:
2435 When generating PIC two transformations are made. First, the compiler
2436 loads the address of foo into a register. So the first transformation makes:
2441 The code in movsi will intercept the lea instruction and call this
2442 routine which will transform the instructions into:
2444 movel a5@(_foo:w), a0
2448 That (in a nutshell) is how *all* symbol and label references are
2452 legitimize_pic_address (rtx orig
, machine_mode mode ATTRIBUTE_UNUSED
,
2457 /* First handle a simple SYMBOL_REF or LABEL_REF */
2458 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2462 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2463 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2465 else if (GET_CODE (orig
) == CONST
)
2469 /* Make sure this has not already been legitimized. */
2470 if (m68k_unwrap_symbol (orig
, true) != orig
)
2475 /* legitimize both operands of the PLUS */
2476 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2478 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2479 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2480 base
== reg
? 0 : reg
);
2482 if (GET_CODE (orig
) == CONST_INT
)
2483 pic_ref
= plus_constant (Pmode
, base
, INTVAL (orig
));
2485 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2491 /* The __tls_get_addr symbol. */
2492 static GTY(()) rtx m68k_tls_get_addr
;
2494 /* Return SYMBOL_REF for __tls_get_addr. */
2497 m68k_get_tls_get_addr (void)
2499 if (m68k_tls_get_addr
== NULL_RTX
)
2500 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2502 return m68k_tls_get_addr
;
2505 /* Return libcall result in A0 instead of usual D0. */
2506 static bool m68k_libcall_value_in_a0_p
= false;
2508 /* Emit instruction sequence that calls __tls_get_addr. X is
2509 the TLS symbol we are referencing and RELOC is the symbol type to use
2510 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2511 emitted. A pseudo register with result of __tls_get_addr call is
2515 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2521 /* Emit the call sequence. */
2524 /* FIXME: Unfortunately, emit_library_call_value does not
2525 consider (plus (%a5) (const (unspec))) to be a good enough
2526 operand for push, so it forces it into a register. The bad
2527 thing about this is that combiner, due to copy propagation and other
2528 optimizations, sometimes can not later fix this. As a consequence,
2529 additional register may be allocated resulting in a spill.
2530 For reference, see args processing loops in
2531 calls.c:emit_library_call_value_1.
2532 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2533 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2535 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2536 is the simpliest way of generating a call. The difference between
2537 __tls_get_addr() and libcall is that the result is returned in D0
2538 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2539 which temporarily switches returning the result to A0. */
2541 m68k_libcall_value_in_a0_p
= true;
2542 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2543 Pmode
, 1, x
, Pmode
);
2544 m68k_libcall_value_in_a0_p
= false;
2546 insns
= get_insns ();
2549 gcc_assert (can_create_pseudo_p ());
2550 dest
= gen_reg_rtx (Pmode
);
2551 emit_libcall_block (insns
, dest
, a0
, eqv
);
2556 /* The __tls_get_addr symbol. */
2557 static GTY(()) rtx m68k_read_tp
;
2559 /* Return SYMBOL_REF for __m68k_read_tp. */
2562 m68k_get_m68k_read_tp (void)
2564 if (m68k_read_tp
== NULL_RTX
)
2565 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2567 return m68k_read_tp
;
2570 /* Emit instruction sequence that calls __m68k_read_tp.
2571 A pseudo register with result of __m68k_read_tp call is returned. */
2574 m68k_call_m68k_read_tp (void)
2583 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2584 is the simpliest way of generating a call. The difference between
2585 __m68k_read_tp() and libcall is that the result is returned in D0
2586 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2587 which temporarily switches returning the result to A0. */
2589 /* Emit the call sequence. */
2590 m68k_libcall_value_in_a0_p
= true;
2591 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2593 m68k_libcall_value_in_a0_p
= false;
2594 insns
= get_insns ();
2597 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2598 share the m68k_read_tp result with other IE/LE model accesses. */
2599 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2601 gcc_assert (can_create_pseudo_p ());
2602 dest
= gen_reg_rtx (Pmode
);
2603 emit_libcall_block (insns
, dest
, a0
, eqv
);
2608 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2609 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2613 m68k_legitimize_tls_address (rtx orig
)
2615 switch (SYMBOL_REF_TLS_MODEL (orig
))
2617 case TLS_MODEL_GLOBAL_DYNAMIC
:
2618 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2621 case TLS_MODEL_LOCAL_DYNAMIC
:
2627 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2628 share the LDM result with other LD model accesses. */
2629 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2632 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2634 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2636 if (can_create_pseudo_p ())
2637 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2643 case TLS_MODEL_INITIAL_EXEC
:
2648 a0
= m68k_call_m68k_read_tp ();
2650 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2651 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2653 if (can_create_pseudo_p ())
2654 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2660 case TLS_MODEL_LOCAL_EXEC
:
2665 a0
= m68k_call_m68k_read_tp ();
2667 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2669 if (can_create_pseudo_p ())
2670 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2683 /* Return true if X is a TLS symbol. */
2686 m68k_tls_symbol_p (rtx x
)
2688 if (!TARGET_HAVE_TLS
)
2691 if (GET_CODE (x
) != SYMBOL_REF
)
2694 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2697 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2698 though illegitimate one.
2699 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2702 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2704 if (!TARGET_HAVE_TLS
)
2709 subrtx_var_iterator::array_type array
;
2710 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, ALL
)
2714 /* Note: this is not the same as m68k_tls_symbol_p. */
2715 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0)
2718 /* Don't recurse into legitimate TLS references. */
2719 if (m68k_tls_reference_p (x
, true))
2720 iter
.skip_subrtxes ();
2726 enum m68k_reloc reloc
= RELOC_GOT
;
2728 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2729 && TLS_RELOC_P (reloc
));
2735 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2737 /* Return the type of move that should be used for integer I. */
2740 m68k_const_method (HOST_WIDE_INT i
)
2747 /* The ColdFire doesn't have byte or word operations. */
2748 /* FIXME: This may not be useful for the m68060 either. */
2749 if (!TARGET_COLDFIRE
)
2751 /* if -256 < N < 256 but N is not in range for a moveq
2752 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2753 if (USE_MOVQ (i
^ 0xff))
2755 /* Likewise, try with not.w */
2756 if (USE_MOVQ (i
^ 0xffff))
2758 /* This is the only value where neg.w is useful */
2763 /* Try also with swap. */
2765 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2770 /* Try using MVZ/MVS with an immediate value to load constants. */
2771 if (i
>= 0 && i
<= 65535)
2773 if (i
>= -32768 && i
<= 32767)
2777 /* Otherwise, use move.l */
2781 /* Return the cost of moving constant I into a data register. */
2784 const_int_cost (HOST_WIDE_INT i
)
2786 switch (m68k_const_method (i
))
2789 /* Constants between -128 and 127 are cheap due to moveq. */
2797 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2807 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
2808 int *total
, bool speed ATTRIBUTE_UNUSED
)
2813 /* Constant zero is super cheap due to clr instruction. */
2814 if (x
== const0_rtx
)
2817 *total
= const_int_cost (INTVAL (x
));
2827 /* Make 0.0 cheaper than other floating constants to
2828 encourage creating tstsf and tstdf insns. */
2829 if (outer_code
== COMPARE
2830 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2836 /* These are vaguely right for a 68020. */
2837 /* The costs for long multiply have been adjusted to work properly
2838 in synth_mult on the 68020, relative to an average of the time
2839 for add and the time for shift, taking away a little more because
2840 sometimes move insns are needed. */
2841 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2846 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2847 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2849 : TARGET_COLDFIRE ? 3 : 13)
2854 : TUNE_68000_10 ? 5 \
2855 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2856 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2858 : TARGET_COLDFIRE ? 2 : 8)
2861 (TARGET_CF_HWDIV ? 11 \
2862 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2865 /* An lea costs about three times as much as a simple add. */
2866 if (GET_MODE (x
) == SImode
2867 && GET_CODE (XEXP (x
, 1)) == REG
2868 && GET_CODE (XEXP (x
, 0)) == MULT
2869 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2870 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2871 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2872 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2873 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2875 /* lea an@(dx:l:i),am */
2876 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2886 *total
= COSTS_N_INSNS(1);
2891 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2893 if (INTVAL (XEXP (x
, 1)) < 16)
2894 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2896 /* We're using clrw + swap for these cases. */
2897 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2900 *total
= COSTS_N_INSNS (10); /* Worst case. */
2903 /* A shift by a big integer takes an extra instruction. */
2904 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2905 && (INTVAL (XEXP (x
, 1)) == 16))
2907 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2910 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2911 && !(INTVAL (XEXP (x
, 1)) > 0
2912 && INTVAL (XEXP (x
, 1)) <= 8))
2914 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2920 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2921 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2922 && GET_MODE (x
) == SImode
)
2923 *total
= COSTS_N_INSNS (MULW_COST
);
2924 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2925 *total
= COSTS_N_INSNS (MULW_COST
);
2927 *total
= COSTS_N_INSNS (MULL_COST
);
2934 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2935 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2936 else if (TARGET_CF_HWDIV
)
2937 *total
= COSTS_N_INSNS (18);
2939 *total
= COSTS_N_INSNS (43); /* div.l */
2943 if (outer_code
== COMPARE
)
2952 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2956 output_move_const_into_data_reg (rtx
*operands
)
2960 i
= INTVAL (operands
[1]);
2961 switch (m68k_const_method (i
))
2964 return "mvzw %1,%0";
2966 return "mvsw %1,%0";
2968 return "moveq %1,%0";
2971 operands
[1] = GEN_INT (i
^ 0xff);
2972 return "moveq %1,%0\n\tnot%.b %0";
2975 operands
[1] = GEN_INT (i
^ 0xffff);
2976 return "moveq %1,%0\n\tnot%.w %0";
2979 return "moveq #-128,%0\n\tneg%.w %0";
2984 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2985 return "moveq %1,%0\n\tswap %0";
2988 return "move%.l %1,%0";
2994 /* Return true if I can be handled by ISA B's mov3q instruction. */
2997 valid_mov3q_const (HOST_WIDE_INT i
)
2999 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
3002 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
3003 I is the value of OPERANDS[1]. */
3006 output_move_simode_const (rtx
*operands
)
3012 src
= INTVAL (operands
[1]);
3014 && (DATA_REG_P (dest
) || MEM_P (dest
))
3015 /* clr insns on 68000 read before writing. */
3016 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3017 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
3019 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
3020 return "mov3q%.l %1,%0";
3021 else if (src
== 0 && ADDRESS_REG_P (dest
))
3022 return "sub%.l %0,%0";
3023 else if (DATA_REG_P (dest
))
3024 return output_move_const_into_data_reg (operands
);
3025 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
3027 if (valid_mov3q_const (src
))
3028 return "mov3q%.l %1,%0";
3029 return "move%.w %1,%0";
3031 else if (MEM_P (dest
)
3032 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
3033 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
3034 && IN_RANGE (src
, -0x8000, 0x7fff))
3036 if (valid_mov3q_const (src
))
3037 return "mov3q%.l %1,%-";
3040 return "move%.l %1,%0";
3044 output_move_simode (rtx
*operands
)
3046 if (GET_CODE (operands
[1]) == CONST_INT
)
3047 return output_move_simode_const (operands
);
3048 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3049 || GET_CODE (operands
[1]) == CONST
)
3050 && push_operand (operands
[0], SImode
))
3052 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3053 || GET_CODE (operands
[1]) == CONST
)
3054 && ADDRESS_REG_P (operands
[0]))
3055 return "lea %a1,%0";
3056 return "move%.l %1,%0";
3060 output_move_himode (rtx
*operands
)
3062 if (GET_CODE (operands
[1]) == CONST_INT
)
3064 if (operands
[1] == const0_rtx
3065 && (DATA_REG_P (operands
[0])
3066 || GET_CODE (operands
[0]) == MEM
)
3067 /* clr insns on 68000 read before writing. */
3068 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3069 || !(GET_CODE (operands
[0]) == MEM
3070 && MEM_VOLATILE_P (operands
[0]))))
3072 else if (operands
[1] == const0_rtx
3073 && ADDRESS_REG_P (operands
[0]))
3074 return "sub%.l %0,%0";
3075 else if (DATA_REG_P (operands
[0])
3076 && INTVAL (operands
[1]) < 128
3077 && INTVAL (operands
[1]) >= -128)
3078 return "moveq %1,%0";
3079 else if (INTVAL (operands
[1]) < 0x8000
3080 && INTVAL (operands
[1]) >= -0x8000)
3081 return "move%.w %1,%0";
3083 else if (CONSTANT_P (operands
[1]))
3084 return "move%.l %1,%0";
3085 return "move%.w %1,%0";
3089 output_move_qimode (rtx
*operands
)
3091 /* 68k family always modifies the stack pointer by at least 2, even for
3092 byte pushes. The 5200 (ColdFire) does not do this. */
3094 /* This case is generated by pushqi1 pattern now. */
3095 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3096 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3097 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3098 && ! ADDRESS_REG_P (operands
[1])
3099 && ! TARGET_COLDFIRE
));
3101 /* clr and st insns on 68000 read before writing. */
3102 if (!ADDRESS_REG_P (operands
[0])
3103 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3104 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3106 if (operands
[1] == const0_rtx
)
3108 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3109 && GET_CODE (operands
[1]) == CONST_INT
3110 && (INTVAL (operands
[1]) & 255) == 255)
3116 if (GET_CODE (operands
[1]) == CONST_INT
3117 && DATA_REG_P (operands
[0])
3118 && INTVAL (operands
[1]) < 128
3119 && INTVAL (operands
[1]) >= -128)
3120 return "moveq %1,%0";
3121 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3122 return "sub%.l %0,%0";
3123 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3124 return "move%.l %1,%0";
3125 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3126 from address registers. */
3127 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3128 return "move%.w %1,%0";
3129 return "move%.b %1,%0";
3133 output_move_stricthi (rtx
*operands
)
3135 if (operands
[1] == const0_rtx
3136 /* clr insns on 68000 read before writing. */
3137 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3138 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3140 return "move%.w %1,%0";
3144 output_move_strictqi (rtx
*operands
)
3146 if (operands
[1] == const0_rtx
3147 /* clr insns on 68000 read before writing. */
3148 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3149 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3151 return "move%.b %1,%0";
3154 /* Return the best assembler insn template
3155 for moving operands[1] into operands[0] as a fullword. */
3158 singlemove_string (rtx
*operands
)
3160 if (GET_CODE (operands
[1]) == CONST_INT
)
3161 return output_move_simode_const (operands
);
3162 return "move%.l %1,%0";
3166 /* Output assembler or rtl code to perform a doubleword move insn
3167 with operands OPERANDS.
3168 Pointers to 3 helper functions should be specified:
3169 HANDLE_REG_ADJUST to adjust a register by a small value,
3170 HANDLE_COMPADR to compute an address and
3171 HANDLE_MOVSI to move 4 bytes. */
3174 handle_move_double (rtx operands
[2],
3175 void (*handle_reg_adjust
) (rtx
, int),
3176 void (*handle_compadr
) (rtx
[2]),
3177 void (*handle_movsi
) (rtx
[2]))
3181 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3186 rtx addreg0
= 0, addreg1
= 0;
3187 int dest_overlapped_low
= 0;
3188 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3193 /* First classify both operands. */
3195 if (REG_P (operands
[0]))
3197 else if (offsettable_memref_p (operands
[0]))
3199 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3201 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3203 else if (GET_CODE (operands
[0]) == MEM
)
3208 if (REG_P (operands
[1]))
3210 else if (CONSTANT_P (operands
[1]))
3212 else if (offsettable_memref_p (operands
[1]))
3214 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3216 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3218 else if (GET_CODE (operands
[1]) == MEM
)
3223 /* Check for the cases that the operand constraints are not supposed
3224 to allow to happen. Generating code for these cases is
3226 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3228 /* If one operand is decrementing and one is incrementing
3229 decrement the former register explicitly
3230 and change that operand into ordinary indexing. */
3232 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3234 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3236 handle_reg_adjust (operands
[0], -size
);
3238 if (GET_MODE (operands
[1]) == XFmode
)
3239 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3240 else if (GET_MODE (operands
[0]) == DFmode
)
3241 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3243 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3246 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3248 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3250 handle_reg_adjust (operands
[1], -size
);
3252 if (GET_MODE (operands
[1]) == XFmode
)
3253 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3254 else if (GET_MODE (operands
[1]) == DFmode
)
3255 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3257 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3261 /* If an operand is an unoffsettable memory ref, find a register
3262 we can increment temporarily to make it refer to the second word. */
3264 if (optype0
== MEMOP
)
3265 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3267 if (optype1
== MEMOP
)
3268 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3270 /* Ok, we can do one word at a time.
3271 Normally we do the low-numbered word first,
3272 but if either operand is autodecrementing then we
3273 do the high-numbered word first.
3275 In either case, set up in LATEHALF the operands to use
3276 for the high-numbered word and in some cases alter the
3277 operands in OPERANDS to be suitable for the low-numbered word. */
3281 if (optype0
== REGOP
)
3283 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3284 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3286 else if (optype0
== OFFSOP
)
3288 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3289 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3293 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3294 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3297 if (optype1
== REGOP
)
3299 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3300 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3302 else if (optype1
== OFFSOP
)
3304 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3305 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3307 else if (optype1
== CNSTOP
)
3309 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3314 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
3315 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
3316 operands
[1] = GEN_INT (l
[0]);
3317 middlehalf
[1] = GEN_INT (l
[1]);
3318 latehalf
[1] = GEN_INT (l
[2]);
3322 /* No non-CONST_DOUBLE constant should ever appear
3324 gcc_assert (!CONSTANT_P (operands
[1]));
3329 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3330 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3334 /* size is not 12: */
3336 if (optype0
== REGOP
)
3337 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3338 else if (optype0
== OFFSOP
)
3339 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3341 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3343 if (optype1
== REGOP
)
3344 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3345 else if (optype1
== OFFSOP
)
3346 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3347 else if (optype1
== CNSTOP
)
3348 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3350 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3353 /* If insn is effectively movd N(REG),-(REG) then we will do the high
3354 word first. We should use the adjusted operand 1 (which is N+4(REG))
3355 for the low word as well, to compensate for the first decrement of
3357 if (optype0
== PUSHOP
3358 && reg_overlap_mentioned_p (XEXP (XEXP (operands
[0], 0), 0), operands
[1]))
3359 operands
[1] = middlehalf
[1] = latehalf
[1];
3361 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3362 if the upper part of reg N does not appear in the MEM, arrange to
3363 emit the move late-half first. Otherwise, compute the MEM address
3364 into the upper part of N and use that as a pointer to the memory
3366 if (optype0
== REGOP
3367 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3369 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3371 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3372 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3374 /* If both halves of dest are used in the src memory address,
3375 compute the address into latehalf of dest.
3376 Note that this can't happen if the dest is two data regs. */
3378 xops
[0] = latehalf
[0];
3379 xops
[1] = XEXP (operands
[1], 0);
3381 handle_compadr (xops
);
3382 if (GET_MODE (operands
[1]) == XFmode
)
3384 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3385 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3386 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3390 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3391 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3395 && reg_overlap_mentioned_p (middlehalf
[0],
3396 XEXP (operands
[1], 0)))
3398 /* Check for two regs used by both source and dest.
3399 Note that this can't happen if the dest is all data regs.
3400 It can happen if the dest is d6, d7, a0.
3401 But in that case, latehalf is an addr reg, so
3402 the code at compadr does ok. */
3404 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3405 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3408 /* JRV says this can't happen: */
3409 gcc_assert (!addreg0
&& !addreg1
);
3411 /* Only the middle reg conflicts; simply put it last. */
3412 handle_movsi (operands
);
3413 handle_movsi (latehalf
);
3414 handle_movsi (middlehalf
);
3418 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3419 /* If the low half of dest is mentioned in the source memory
3420 address, the arrange to emit the move late half first. */
3421 dest_overlapped_low
= 1;
3424 /* If one or both operands autodecrementing,
3425 do the two words, high-numbered first. */
3427 /* Likewise, the first move would clobber the source of the second one,
3428 do them in the other order. This happens only for registers;
3429 such overlap can't happen in memory unless the user explicitly
3430 sets it up, and that is an undefined circumstance. */
3432 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3433 || (optype0
== REGOP
&& optype1
== REGOP
3434 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3435 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3436 || dest_overlapped_low
)
3438 /* Make any unoffsettable addresses point at high-numbered word. */
3440 handle_reg_adjust (addreg0
, size
- 4);
3442 handle_reg_adjust (addreg1
, size
- 4);
3445 handle_movsi (latehalf
);
3447 /* Undo the adds we just did. */
3449 handle_reg_adjust (addreg0
, -4);
3451 handle_reg_adjust (addreg1
, -4);
3455 handle_movsi (middlehalf
);
3458 handle_reg_adjust (addreg0
, -4);
3460 handle_reg_adjust (addreg1
, -4);
3463 /* Do low-numbered word. */
3465 handle_movsi (operands
);
3469 /* Normal case: do the two words, low-numbered first. */
3471 m68k_final_prescan_insn (NULL
, operands
, 2);
3472 handle_movsi (operands
);
3474 /* Do the middle one of the three words for long double */
3478 handle_reg_adjust (addreg0
, 4);
3480 handle_reg_adjust (addreg1
, 4);
3482 m68k_final_prescan_insn (NULL
, middlehalf
, 2);
3483 handle_movsi (middlehalf
);
3486 /* Make any unoffsettable addresses point at high-numbered word. */
3488 handle_reg_adjust (addreg0
, 4);
3490 handle_reg_adjust (addreg1
, 4);
3493 m68k_final_prescan_insn (NULL
, latehalf
, 2);
3494 handle_movsi (latehalf
);
3496 /* Undo the adds we just did. */
3498 handle_reg_adjust (addreg0
, -(size
- 4));
3500 handle_reg_adjust (addreg1
, -(size
- 4));
3505 /* Output assembler code to adjust REG by N. */
3507 output_reg_adjust (rtx reg
, int n
)
3511 gcc_assert (GET_MODE (reg
) == SImode
3512 && -12 <= n
&& n
!= 0 && n
<= 12);
3517 s
= "add%.l #12,%0";
3521 s
= "addq%.l #8,%0";
3525 s
= "addq%.l #4,%0";
3529 s
= "sub%.l #12,%0";
3533 s
= "subq%.l #8,%0";
3537 s
= "subq%.l #4,%0";
3545 output_asm_insn (s
, ®
);
3548 /* Emit rtl code to adjust REG by N. */
3550 emit_reg_adjust (rtx reg1
, int n
)
3554 gcc_assert (GET_MODE (reg1
) == SImode
3555 && -12 <= n
&& n
!= 0 && n
<= 12);
3557 reg1
= copy_rtx (reg1
);
3558 reg2
= copy_rtx (reg1
);
3561 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3563 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3568 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3570 output_compadr (rtx operands
[2])
3572 output_asm_insn ("lea %a1,%0", operands
);
3575 /* Output the best assembler insn for moving operands[1] into operands[0]
3578 output_movsi (rtx operands
[2])
3580 output_asm_insn (singlemove_string (operands
), operands
);
3583 /* Copy OP and change its mode to MODE. */
3585 copy_operand (rtx op
, machine_mode mode
)
3587 /* ??? This looks really ugly. There must be a better way
3588 to change a mode on the operand. */
3589 if (GET_MODE (op
) != VOIDmode
)
3592 op
= gen_rtx_REG (mode
, REGNO (op
));
3596 PUT_MODE (op
, mode
);
3603 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3605 emit_movsi (rtx operands
[2])
3607 operands
[0] = copy_operand (operands
[0], SImode
);
3608 operands
[1] = copy_operand (operands
[1], SImode
);
3610 emit_insn (gen_movsi (operands
[0], operands
[1]));
3613 /* Output assembler code to perform a doubleword move insn
3614 with operands OPERANDS. */
3616 output_move_double (rtx
*operands
)
3618 handle_move_double (operands
,
3619 output_reg_adjust
, output_compadr
, output_movsi
);
3624 /* Output rtl code to perform a doubleword move insn
3625 with operands OPERANDS. */
3627 m68k_emit_move_double (rtx operands
[2])
3629 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3632 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3633 new rtx with the correct mode. */
3636 force_mode (machine_mode mode
, rtx orig
)
3638 if (mode
== GET_MODE (orig
))
3641 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3644 return gen_rtx_REG (mode
, REGNO (orig
));
3648 fp_reg_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
3650 return reg_renumber
&& FP_REG_P (op
);
3653 /* Emit insns to move operands[1] into operands[0].
3655 Return 1 if we have written out everything that needs to be done to
3656 do the move. Otherwise, return 0 and the caller will emit the move
3659 Note SCRATCH_REG may not be in the proper mode depending on how it
3660 will be used. This routine is responsible for creating a new copy
3661 of SCRATCH_REG in the proper mode. */
3664 emit_move_sequence (rtx
*operands
, machine_mode mode
, rtx scratch_reg
)
3666 register rtx operand0
= operands
[0];
3667 register rtx operand1
= operands
[1];
3671 && reload_in_progress
&& GET_CODE (operand0
) == REG
3672 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3673 operand0
= reg_equiv_mem (REGNO (operand0
));
3674 else if (scratch_reg
3675 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3676 && GET_CODE (SUBREG_REG (operand0
)) == REG
3677 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3679 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3680 the code which tracks sets/uses for delete_output_reload. */
3681 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3682 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
3683 SUBREG_BYTE (operand0
));
3684 operand0
= alter_subreg (&temp
, true);
3688 && reload_in_progress
&& GET_CODE (operand1
) == REG
3689 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3690 operand1
= reg_equiv_mem (REGNO (operand1
));
3691 else if (scratch_reg
3692 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3693 && GET_CODE (SUBREG_REG (operand1
)) == REG
3694 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3696 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3697 the code which tracks sets/uses for delete_output_reload. */
3698 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3699 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
3700 SUBREG_BYTE (operand1
));
3701 operand1
= alter_subreg (&temp
, true);
3704 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3705 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3706 != XEXP (operand0
, 0)))
3707 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3708 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3709 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3710 != XEXP (operand1
, 0)))
3711 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3713 /* Handle secondary reloads for loads/stores of FP registers where
3714 the address is symbolic by using the scratch register */
3715 if (fp_reg_operand (operand0
, mode
)
3716 && ((GET_CODE (operand1
) == MEM
3717 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3718 || ((GET_CODE (operand1
) == SUBREG
3719 && GET_CODE (XEXP (operand1
, 0)) == MEM
3720 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3723 if (GET_CODE (operand1
) == SUBREG
)
3724 operand1
= XEXP (operand1
, 0);
3726 /* SCRATCH_REG will hold an address. We want
3727 it in SImode regardless of what mode it was originally given
3729 scratch_reg
= force_mode (SImode
, scratch_reg
);
3731 /* D might not fit in 14 bits either; for such cases load D into
3733 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3735 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3736 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3738 XEXP (XEXP (operand1
, 0), 0),
3742 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3743 emit_insn (gen_rtx_SET (operand0
, gen_rtx_MEM (mode
, scratch_reg
)));
3746 else if (fp_reg_operand (operand1
, mode
)
3747 && ((GET_CODE (operand0
) == MEM
3748 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3749 || ((GET_CODE (operand0
) == SUBREG
)
3750 && GET_CODE (XEXP (operand0
, 0)) == MEM
3751 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3754 if (GET_CODE (operand0
) == SUBREG
)
3755 operand0
= XEXP (operand0
, 0);
3757 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3758 it in SIMODE regardless of what mode it was originally given
3760 scratch_reg
= force_mode (SImode
, scratch_reg
);
3762 /* D might not fit in 14 bits either; for such cases load D into
3764 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3766 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3767 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3770 XEXP (XEXP (operand0
, 0),
3775 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3776 emit_insn (gen_rtx_SET (gen_rtx_MEM (mode
, scratch_reg
), operand1
));
3779 /* Handle secondary reloads for loads of FP registers from constant
3780 expressions by forcing the constant into memory.
3782 use scratch_reg to hold the address of the memory location.
3784 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3785 NO_REGS when presented with a const_int and an register class
3786 containing only FP registers. Doing so unfortunately creates
3787 more problems than it solves. Fix this for 2.5. */
3788 else if (fp_reg_operand (operand0
, mode
)
3789 && CONSTANT_P (operand1
)
3794 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3795 it in SIMODE regardless of what mode it was originally given
3797 scratch_reg
= force_mode (SImode
, scratch_reg
);
3799 /* Force the constant into memory and put the address of the
3800 memory location into scratch_reg. */
3801 xoperands
[0] = scratch_reg
;
3802 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3803 emit_insn (gen_rtx_SET (scratch_reg
, xoperands
[1]));
3805 /* Now load the destination register. */
3806 emit_insn (gen_rtx_SET (operand0
, gen_rtx_MEM (mode
, scratch_reg
)));
3810 /* Now have insn-emit do whatever it normally does. */
3814 /* Split one or more DImode RTL references into pairs of SImode
3815 references. The RTL can be REG, offsettable MEM, integer constant, or
3816 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3817 split and "num" is its length. lo_half and hi_half are output arrays
3818 that parallel "operands". */
3821 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3825 rtx op
= operands
[num
];
3827 /* simplify_subreg refuses to split volatile memory addresses,
3828 but we still have to handle it. */
3829 if (GET_CODE (op
) == MEM
)
3831 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3832 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3836 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3837 GET_MODE (op
) == VOIDmode
3838 ? DImode
: GET_MODE (op
), 4);
3839 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3840 GET_MODE (op
) == VOIDmode
3841 ? DImode
: GET_MODE (op
), 0);
3846 /* Split X into a base and a constant offset, storing them in *BASE
3847 and *OFFSET respectively. */
3850 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3853 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3855 *offset
+= INTVAL (XEXP (x
, 1));
3861 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3862 instruction. STORE_P says whether the move is a load or store.
3864 If the instruction uses post-increment or pre-decrement addressing,
3865 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3866 adjustment. This adjustment will be made by the first element of
3867 PARALLEL, with the loads or stores starting at element 1. If the
3868 instruction does not use post-increment or pre-decrement addressing,
3869 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3870 start at element 0. */
3873 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3874 HOST_WIDE_INT automod_offset
, bool store_p
)
3876 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3877 HOST_WIDE_INT offset
, mem_offset
;
3879 enum reg_class rclass
;
3881 len
= XVECLEN (pattern
, 0);
3882 first
= (automod_base
!= NULL
);
3886 /* Stores must be pre-decrement and loads must be post-increment. */
3887 if (store_p
!= (automod_offset
< 0))
3890 /* Work out the base and offset for lowest memory location. */
3891 base
= automod_base
;
3892 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3896 /* Allow any valid base and offset in the first access. */
3903 for (i
= first
; i
< len
; i
++)
3905 /* We need a plain SET. */
3906 set
= XVECEXP (pattern
, 0, i
);
3907 if (GET_CODE (set
) != SET
)
3910 /* Check that we have a memory location... */
3911 mem
= XEXP (set
, !store_p
);
3912 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3915 /* ...with the right address. */
3918 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3919 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3920 There are no mode restrictions for 680x0 besides the
3921 automodification rules enforced above. */
3923 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3928 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3929 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3933 /* Check that we have a register of the required mode and class. */
3934 reg
= XEXP (set
, store_p
);
3936 || !HARD_REGISTER_P (reg
)
3937 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3942 /* The register must belong to RCLASS and have a higher number
3943 than the register in the previous SET. */
3944 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3945 || REGNO (last_reg
) >= REGNO (reg
))
3950 /* Work out which register class we need. */
3951 if (INT_REGNO_P (REGNO (reg
)))
3952 rclass
= GENERAL_REGS
;
3953 else if (FP_REGNO_P (REGNO (reg
)))
3960 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3963 /* If we have an automodification, check whether the final offset is OK. */
3964 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3967 /* Reject unprofitable cases. */
3968 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3974 /* Return the assembly code template for a movem or fmovem instruction
3975 whose pattern is given by PATTERN. Store the template's operands
3978 If the instruction uses post-increment or pre-decrement addressing,
3979 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3980 is true if this is a store instruction. */
3983 m68k_output_movem (rtx
*operands
, rtx pattern
,
3984 HOST_WIDE_INT automod_offset
, bool store_p
)
3989 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3991 first
= (automod_offset
!= 0);
3992 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3994 /* When using movem with pre-decrement addressing, register X + D0_REG
3995 is controlled by bit 15 - X. For all other addressing modes,
3996 register X + D0_REG is controlled by bit X. Confusingly, the
3997 register mask for fmovem is in the opposite order to that for
4001 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
4002 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
4003 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
4004 if (automod_offset
< 0)
4006 if (FP_REGNO_P (regno
))
4007 mask
|= 1 << (regno
- FP0_REG
);
4009 mask
|= 1 << (15 - (regno
- D0_REG
));
4013 if (FP_REGNO_P (regno
))
4014 mask
|= 1 << (7 - (regno
- FP0_REG
));
4016 mask
|= 1 << (regno
- D0_REG
);
4021 if (automod_offset
== 0)
4022 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
4023 else if (automod_offset
< 0)
4024 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4026 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4027 operands
[1] = GEN_INT (mask
);
4028 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
4031 return "fmovem %1,%a0";
4033 return "fmovem %a0,%1";
4038 return "movem%.l %1,%a0";
4040 return "movem%.l %a0,%1";
4044 /* Return a REG that occurs in ADDR with coefficient 1.
4045 ADDR can be effectively incremented by incrementing REG. */
4048 find_addr_reg (rtx addr
)
4050 while (GET_CODE (addr
) == PLUS
)
4052 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4053 addr
= XEXP (addr
, 0);
4054 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4055 addr
= XEXP (addr
, 1);
4056 else if (CONSTANT_P (XEXP (addr
, 0)))
4057 addr
= XEXP (addr
, 1);
4058 else if (CONSTANT_P (XEXP (addr
, 1)))
4059 addr
= XEXP (addr
, 0);
4063 gcc_assert (GET_CODE (addr
) == REG
);
4067 /* Output assembler code to perform a 32-bit 3-operand add. */
4070 output_addsi3 (rtx
*operands
)
4072 if (! operands_match_p (operands
[0], operands
[1]))
4074 if (!ADDRESS_REG_P (operands
[1]))
4076 rtx tmp
= operands
[1];
4078 operands
[1] = operands
[2];
4082 /* These insns can result from reloads to access
4083 stack slots over 64k from the frame pointer. */
4084 if (GET_CODE (operands
[2]) == CONST_INT
4085 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4086 return "move%.l %2,%0\n\tadd%.l %1,%0";
4087 if (GET_CODE (operands
[2]) == REG
)
4088 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4089 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4091 if (GET_CODE (operands
[2]) == CONST_INT
)
4093 if (INTVAL (operands
[2]) > 0
4094 && INTVAL (operands
[2]) <= 8)
4095 return "addq%.l %2,%0";
4096 if (INTVAL (operands
[2]) < 0
4097 && INTVAL (operands
[2]) >= -8)
4099 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4100 return "subq%.l %2,%0";
4102 /* On the CPU32 it is faster to use two addql instructions to
4103 add a small integer (8 < N <= 16) to a register.
4104 Likewise for subql. */
4105 if (TUNE_CPU32
&& REG_P (operands
[0]))
4107 if (INTVAL (operands
[2]) > 8
4108 && INTVAL (operands
[2]) <= 16)
4110 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4111 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4113 if (INTVAL (operands
[2]) < -8
4114 && INTVAL (operands
[2]) >= -16)
4116 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4117 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4120 if (ADDRESS_REG_P (operands
[0])
4121 && INTVAL (operands
[2]) >= -0x8000
4122 && INTVAL (operands
[2]) < 0x8000)
4125 return "add%.w %2,%0";
4127 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4130 return "add%.l %2,%0";
4133 /* Store in cc_status the expressions that the condition codes will
4134 describe after execution of an instruction whose pattern is EXP.
4135 Do not alter them if the instruction would not alter the cc's. */
4137 /* On the 68000, all the insns to store in an address register fail to
4138 set the cc's. However, in some cases these instructions can make it
4139 possibly invalid to use the saved cc's. In those cases we clear out
4140 some or all of the saved cc's so they won't be used. */
4143 notice_update_cc (rtx exp
, rtx insn
)
4145 if (GET_CODE (exp
) == SET
)
4147 if (GET_CODE (SET_SRC (exp
)) == CALL
)
4149 else if (ADDRESS_REG_P (SET_DEST (exp
)))
4151 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
4152 cc_status
.value1
= 0;
4153 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
4154 cc_status
.value2
= 0;
4156 /* fmoves to memory or data registers do not set the condition
4157 codes. Normal moves _do_ set the condition codes, but not in
4158 a way that is appropriate for comparison with 0, because -0.0
4159 would be treated as a negative nonzero number. Note that it
4160 isn't appropriate to conditionalize this restriction on
4161 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4162 we care about the difference between -0.0 and +0.0. */
4163 else if (!FP_REG_P (SET_DEST (exp
))
4164 && SET_DEST (exp
) != cc0_rtx
4165 && (FP_REG_P (SET_SRC (exp
))
4166 || GET_CODE (SET_SRC (exp
)) == FIX
4167 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
4169 /* A pair of move insns doesn't produce a useful overall cc. */
4170 else if (!FP_REG_P (SET_DEST (exp
))
4171 && !FP_REG_P (SET_SRC (exp
))
4172 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
4173 && (GET_CODE (SET_SRC (exp
)) == REG
4174 || GET_CODE (SET_SRC (exp
)) == MEM
4175 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
4177 else if (SET_DEST (exp
) != pc_rtx
)
4179 cc_status
.flags
= 0;
4180 cc_status
.value1
= SET_DEST (exp
);
4181 cc_status
.value2
= SET_SRC (exp
);
4184 else if (GET_CODE (exp
) == PARALLEL
4185 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
4187 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
4188 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
4190 if (ADDRESS_REG_P (dest
))
4192 else if (dest
!= pc_rtx
)
4194 cc_status
.flags
= 0;
4195 cc_status
.value1
= dest
;
4196 cc_status
.value2
= src
;
4201 if (cc_status
.value2
!= 0
4202 && ADDRESS_REG_P (cc_status
.value2
)
4203 && GET_MODE (cc_status
.value2
) == QImode
)
4205 if (cc_status
.value2
!= 0)
4206 switch (GET_CODE (cc_status
.value2
))
4208 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
4209 case ROTATE
: case ROTATERT
:
4210 /* These instructions always clear the overflow bit, and set
4211 the carry to the bit shifted out. */
4212 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
4215 case PLUS
: case MINUS
: case MULT
:
4216 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
4217 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4218 cc_status
.flags
|= CC_NO_OVERFLOW
;
4221 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4222 ends with a move insn moving r2 in r2's mode.
4223 Thus, the cc's are set for r2.
4224 This can set N bit spuriously. */
4225 cc_status
.flags
|= CC_NOT_NEGATIVE
;
4230 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4232 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4233 cc_status
.value2
= 0;
4234 /* Check for PRE_DEC in dest modifying a register used in src. */
4235 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == MEM
4236 && GET_CODE (XEXP (cc_status
.value1
, 0)) == PRE_DEC
4238 && reg_overlap_mentioned_p (XEXP (XEXP (cc_status
.value1
, 0), 0),
4240 cc_status
.value2
= 0;
4241 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
4242 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
4243 cc_status
.flags
= CC_IN_68881
;
4244 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
4245 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
4247 cc_status
.flags
= CC_IN_68881
;
4248 if (!FP_REG_P (XEXP (cc_status
.value2
, 0))
4249 && FP_REG_P (XEXP (cc_status
.value2
, 1)))
4250 cc_status
.flags
|= CC_REVERSED
;
4255 output_move_const_double (rtx
*operands
)
4257 int code
= standard_68881_constant_p (operands
[1]);
4261 static char buf
[40];
4263 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4266 return "fmove%.d %1,%0";
4270 output_move_const_single (rtx
*operands
)
4272 int code
= standard_68881_constant_p (operands
[1]);
4276 static char buf
[40];
4278 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4281 return "fmove%.s %f1,%0";
4284 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4285 from the "fmovecr" instruction.
4286 The value, anded with 0xff, gives the code to use in fmovecr
4287 to get the desired constant. */
4289 /* This code has been fixed for cross-compilation. */
4291 static int inited_68881_table
= 0;
4293 static const char *const strings_68881
[7] = {
4303 static const int codes_68881
[7] = {
4313 REAL_VALUE_TYPE values_68881
[7];
4315 /* Set up values_68881 array by converting the decimal values
4316 strings_68881 to binary. */
4319 init_68881_table (void)
4326 for (i
= 0; i
< 7; i
++)
4330 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4331 values_68881
[i
] = r
;
4333 inited_68881_table
= 1;
4337 standard_68881_constant_p (rtx x
)
4342 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4343 used at all on those chips. */
4347 if (! inited_68881_table
)
4348 init_68881_table ();
4350 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4352 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
4354 for (i
= 0; i
< 6; i
++)
4356 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
4357 return (codes_68881
[i
]);
4360 if (GET_MODE (x
) == SFmode
)
4363 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
4364 return (codes_68881
[6]);
4366 /* larger powers of ten in the constants ram are not used
4367 because they are not equal to a `double' C constant. */
4371 /* If X is a floating-point constant, return the logarithm of X base 2,
4372 or 0 if X is not a power of 2. */
4375 floating_exact_log2 (rtx x
)
4377 REAL_VALUE_TYPE r
, r1
;
4380 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4382 if (REAL_VALUES_LESS (r
, dconst1
))
4385 exp
= real_exponent (&r
);
4386 real_2expN (&r1
, exp
, DFmode
);
4387 if (REAL_VALUES_EQUAL (r1
, r
))
4393 /* A C compound statement to output to stdio stream STREAM the
4394 assembler syntax for an instruction operand X. X is an RTL
4397 CODE is a value that can be used to specify one of several ways
4398 of printing the operand. It is used when identical operands
4399 must be printed differently depending on the context. CODE
4400 comes from the `%' specification that was used to request
4401 printing of the operand. If the specification was just `%DIGIT'
4402 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4403 is the ASCII code for LTR.
4405 If X is a register, this macro should print the register's name.
4406 The names can be found in an array `reg_names' whose type is
4407 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4409 When the machine description has a specification `%PUNCT' (a `%'
4410 followed by a punctuation character), this macro is called with
4411 a null pointer for X and the punctuation character for CODE.
4413 The m68k specific codes are:
4415 '.' for dot needed in Motorola-style opcode names.
4416 '-' for an operand pushing on the stack:
4417 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4418 '+' for an operand pushing on the stack:
4419 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4420 '@' for a reference to the top word on the stack:
4421 sp@, (sp) or (%sp) depending on the style of syntax.
4422 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4423 but & in SGS syntax).
4424 '!' for the cc register (used in an `and to cc' insn).
4425 '$' for the letter `s' in an op code, but only on the 68040.
4426 '&' for the letter `d' in an op code, but only on the 68040.
4427 '/' for register prefix needed by longlong.h.
4428 '?' for m68k_library_id_string
4430 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4431 'd' to force memory addressing to be absolute, not relative.
4432 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4433 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4434 or print pair of registers as rx:ry.
4435 'p' print an address with @PLTPC attached, but only if the operand
4436 is not locally-bound. */
4439 print_operand (FILE *file
, rtx op
, int letter
)
4444 fprintf (file
, ".");
4446 else if (letter
== '#')
4447 asm_fprintf (file
, "%I");
4448 else if (letter
== '-')
4449 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4450 else if (letter
== '+')
4451 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4452 else if (letter
== '@')
4453 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4454 else if (letter
== '!')
4455 asm_fprintf (file
, "%Rfpcr");
4456 else if (letter
== '$')
4459 fprintf (file
, "s");
4461 else if (letter
== '&')
4464 fprintf (file
, "d");
4466 else if (letter
== '/')
4467 asm_fprintf (file
, "%R");
4468 else if (letter
== '?')
4469 asm_fprintf (file
, m68k_library_id_string
);
4470 else if (letter
== 'p')
4472 output_addr_const (file
, op
);
4473 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4474 fprintf (file
, "@PLTPC");
4476 else if (GET_CODE (op
) == REG
)
4479 /* Print out the second register name of a register pair.
4480 I.e., R (6) => 7. */
4481 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4483 fputs (M68K_REGNAME(REGNO (op
)), file
);
4485 else if (GET_CODE (op
) == MEM
)
4487 output_address (XEXP (op
, 0));
4488 if (letter
== 'd' && ! TARGET_68020
4489 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4490 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4491 && INTVAL (XEXP (op
, 0)) < 0x8000
4492 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4493 fprintf (file
, MOTOROLA
? ".l" : ":l");
4495 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
4499 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4500 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
4501 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
4503 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
4507 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4508 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
4509 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
4510 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
4512 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
4516 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4517 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
4518 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
4522 /* Use `print_operand_address' instead of `output_addr_const'
4523 to ensure that we print relevant PIC stuff. */
4524 asm_fprintf (file
, "%I");
4526 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
4527 print_operand_address (file
, op
);
4529 output_addr_const (file
, op
);
4533 /* Return string for TLS relocation RELOC. */
4536 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
4538 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4539 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
4546 if (flag_pic
== 1 && TARGET_68020
)
4587 /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */
4590 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4592 if (GET_CODE (x
) == UNSPEC
)
4594 switch (XINT (x
, 1))
4596 case UNSPEC_RELOC16
:
4597 case UNSPEC_RELOC32
:
4598 output_addr_const (file
, XVECEXP (x
, 0, 0));
4599 fputs (m68k_get_reloc_decoration
4600 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
4611 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4614 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4616 gcc_assert (size
== 4);
4617 fputs ("\t.long\t", file
);
4618 output_addr_const (file
, x
);
4619 fputs ("@TLSLDO+0x8000", file
);
4622 /* In the name of slightly smaller debug output, and to cater to
4623 general assembler lossage, recognize various UNSPEC sequences
4624 and turn them back into a direct symbol reference. */
4627 m68k_delegitimize_address (rtx orig_x
)
4630 struct m68k_address addr
;
4633 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4638 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
4641 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
4642 || addr
.offset
== NULL_RTX
4643 || GET_CODE (addr
.offset
) != CONST
)
4646 unspec
= XEXP (addr
.offset
, 0);
4647 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
4648 unspec
= XEXP (unspec
, 0);
4649 if (GET_CODE (unspec
) != UNSPEC
4650 || (XINT (unspec
, 1) != UNSPEC_RELOC16
4651 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
4653 x
= XVECEXP (unspec
, 0, 0);
4654 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
4655 if (unspec
!= XEXP (addr
.offset
, 0))
4656 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
4659 rtx idx
= addr
.index
;
4660 if (addr
.scale
!= 1)
4661 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
4662 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
4665 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
4667 x
= replace_equiv_address_nv (orig_x
, x
);
4672 /* A C compound statement to output to stdio stream STREAM the
4673 assembler syntax for an instruction operand that is a memory
4674 reference whose address is ADDR. ADDR is an RTL expression.
4676 Note that this contains a kludge that knows that the only reason
4677 we have an address (plus (label_ref...) (reg...)) when not generating
4678 PIC code is in the insn before a tablejump, and we know that m68k.md
4679 generates a label LInnn: on such an insn.
4681 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4682 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4684 This routine is responsible for distinguishing between -fpic and -fPIC
4685 style relocations in an address. When generating -fpic code the
4686 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4687 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4690 print_operand_address (FILE *file
, rtx addr
)
4692 struct m68k_address address
;
4694 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4697 if (address
.code
== PRE_DEC
)
4698 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4699 M68K_REGNAME (REGNO (address
.base
)));
4700 else if (address
.code
== POST_INC
)
4701 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4702 M68K_REGNAME (REGNO (address
.base
)));
4703 else if (!address
.base
&& !address
.index
)
4705 /* A constant address. */
4706 gcc_assert (address
.offset
== addr
);
4707 if (GET_CODE (addr
) == CONST_INT
)
4709 /* (xxx).w or (xxx).l. */
4710 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4711 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4713 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4715 else if (TARGET_PCREL
)
4717 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4719 output_addr_const (file
, addr
);
4720 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4724 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4725 name ends in `.<letter>', as the last 2 characters can be
4726 mistaken as a size suffix. Put the name in parentheses. */
4727 if (GET_CODE (addr
) == SYMBOL_REF
4728 && strlen (XSTR (addr
, 0)) > 2
4729 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4732 output_addr_const (file
, addr
);
4736 output_addr_const (file
, addr
);
4743 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4744 label being accessed, otherwise it is -1. */
4745 labelno
= (address
.offset
4747 && GET_CODE (address
.offset
) == LABEL_REF
4748 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4752 /* Print the "offset(base" component. */
4754 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4758 output_addr_const (file
, address
.offset
);
4762 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4764 /* Print the ",index" component, if any. */
4769 fprintf (file
, "%s.%c",
4770 M68K_REGNAME (REGNO (address
.index
)),
4771 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4772 if (address
.scale
!= 1)
4773 fprintf (file
, "*%d", address
.scale
);
4777 else /* !MOTOROLA */
4779 if (!address
.offset
&& !address
.index
)
4780 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4783 /* Print the "base@(offset" component. */
4785 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4789 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4790 fprintf (file
, "@(");
4792 output_addr_const (file
, address
.offset
);
4794 /* Print the ",index" component, if any. */
4797 fprintf (file
, ",%s:%c",
4798 M68K_REGNAME (REGNO (address
.index
)),
4799 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4800 if (address
.scale
!= 1)
4801 fprintf (file
, ":%d", address
.scale
);
4809 /* Check for cases where a clr insns can be omitted from code using
4810 strict_low_part sets. For example, the second clrl here is not needed:
4811 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4813 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4814 insn we are checking for redundancy. TARGET is the register set by the
4818 strict_low_part_peephole_ok (machine_mode mode
, rtx_insn
*first_insn
,
4821 rtx_insn
*p
= first_insn
;
4823 while ((p
= PREV_INSN (p
)))
4825 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4831 /* If it isn't an insn, then give up. */
4835 if (reg_set_p (target
, p
))
4837 rtx set
= single_set (p
);
4840 /* If it isn't an easy to recognize insn, then give up. */
4844 dest
= SET_DEST (set
);
4846 /* If this sets the entire target register to zero, then our
4847 first_insn is redundant. */
4848 if (rtx_equal_p (dest
, target
)
4849 && SET_SRC (set
) == const0_rtx
)
4851 else if (GET_CODE (dest
) == STRICT_LOW_PART
4852 && GET_CODE (XEXP (dest
, 0)) == REG
4853 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4854 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4855 <= GET_MODE_SIZE (mode
)))
4856 /* This is a strict low part set which modifies less than
4857 we are using, so it is safe. */
4867 /* Operand predicates for implementing asymmetric pc-relative addressing
4868 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4869 when used as a source operand, but not as a destination operand.
4871 We model this by restricting the meaning of the basic predicates
4872 (general_operand, memory_operand, etc) to forbid the use of this
4873 addressing mode, and then define the following predicates that permit
4874 this addressing mode. These predicates can then be used for the
4875 source operands of the appropriate instructions.
4877 n.b. While it is theoretically possible to change all machine patterns
4878 to use this addressing more where permitted by the architecture,
4879 it has only been implemented for "common" cases: SImode, HImode, and
4880 QImode operands, and only for the principle operations that would
4881 require this addressing mode: data movement and simple integer operations.
4883 In parallel with these new predicates, two new constraint letters
4884 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4885 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4886 In the pcrel case 's' is only valid in combination with 'a' registers.
4887 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4888 of how these constraints are used.
4890 The use of these predicates is strictly optional, though patterns that
4891 don't will cause an extra reload register to be allocated where one
4894 lea (abc:w,%pc),%a0 ; need to reload address
4895 moveq &1,%d1 ; since write to pc-relative space
4896 movel %d1,%a0@ ; is not allowed
4898 lea (abc:w,%pc),%a1 ; no need to reload address here
4899 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4901 For more info, consult tiemann@cygnus.com.
4904 All of the ugliness with predicates and constraints is due to the
4905 simple fact that the m68k does not allow a pc-relative addressing
4906 mode as a destination. gcc does not distinguish between source and
4907 destination addresses. Hence, if we claim that pc-relative address
4908 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4909 end up with invalid code. To get around this problem, we left
4910 pc-relative modes as invalid addresses, and then added special
4911 predicates and constraints to accept them.
4913 A cleaner way to handle this is to modify gcc to distinguish
4914 between source and destination addresses. We can then say that
4915 pc-relative is a valid source address but not a valid destination
4916 address, and hopefully avoid a lot of the predicate and constraint
4917 hackery. Unfortunately, this would be a pretty big change. It would
4918 be a useful change for a number of ports, but there aren't any current
4919 plans to undertake this.
4921 ***************************************************************************/
4925 output_andsi3 (rtx
*operands
)
4928 if (GET_CODE (operands
[2]) == CONST_INT
4929 && (INTVAL (operands
[2]) | 0xffff) == -1
4930 && (DATA_REG_P (operands
[0])
4931 || offsettable_memref_p (operands
[0]))
4932 && !TARGET_COLDFIRE
)
4934 if (GET_CODE (operands
[0]) != REG
)
4935 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4936 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4937 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4939 if (operands
[2] == const0_rtx
)
4941 return "and%.w %2,%0";
4943 if (GET_CODE (operands
[2]) == CONST_INT
4944 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
4945 && (DATA_REG_P (operands
[0])
4946 || offsettable_memref_p (operands
[0])))
4948 if (DATA_REG_P (operands
[0]))
4949 operands
[1] = GEN_INT (logval
);
4952 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4953 operands
[1] = GEN_INT (logval
% 8);
4955 /* This does not set condition codes in a standard way. */
4957 return "bclr %1,%0";
4959 return "and%.l %2,%0";
4963 output_iorsi3 (rtx
*operands
)
4965 register int logval
;
4966 if (GET_CODE (operands
[2]) == CONST_INT
4967 && INTVAL (operands
[2]) >> 16 == 0
4968 && (DATA_REG_P (operands
[0])
4969 || offsettable_memref_p (operands
[0]))
4970 && !TARGET_COLDFIRE
)
4972 if (GET_CODE (operands
[0]) != REG
)
4973 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4974 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4976 if (INTVAL (operands
[2]) == 0xffff)
4977 return "mov%.w %2,%0";
4978 return "or%.w %2,%0";
4980 if (GET_CODE (operands
[2]) == CONST_INT
4981 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4982 && (DATA_REG_P (operands
[0])
4983 || offsettable_memref_p (operands
[0])))
4985 if (DATA_REG_P (operands
[0]))
4986 operands
[1] = GEN_INT (logval
);
4989 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4990 operands
[1] = GEN_INT (logval
% 8);
4993 return "bset %1,%0";
4995 return "or%.l %2,%0";
4999 output_xorsi3 (rtx
*operands
)
5001 register int logval
;
5002 if (GET_CODE (operands
[2]) == CONST_INT
5003 && INTVAL (operands
[2]) >> 16 == 0
5004 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
5005 && !TARGET_COLDFIRE
)
5007 if (! DATA_REG_P (operands
[0]))
5008 operands
[0] = adjust_address (operands
[0], HImode
, 2);
5009 /* Do not delete a following tstl %0 insn; that would be incorrect. */
5011 if (INTVAL (operands
[2]) == 0xffff)
5013 return "eor%.w %2,%0";
5015 if (GET_CODE (operands
[2]) == CONST_INT
5016 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
5017 && (DATA_REG_P (operands
[0])
5018 || offsettable_memref_p (operands
[0])))
5020 if (DATA_REG_P (operands
[0]))
5021 operands
[1] = GEN_INT (logval
);
5024 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
5025 operands
[1] = GEN_INT (logval
% 8);
5028 return "bchg %1,%0";
5030 return "eor%.l %2,%0";
5033 /* Return the instruction that should be used for a call to address X,
5034 which is known to be in operand 0. */
5039 if (symbolic_operand (x
, VOIDmode
))
5040 return m68k_symbolic_call
;
5045 /* Likewise sibling calls. */
5048 output_sibcall (rtx x
)
5050 if (symbolic_operand (x
, VOIDmode
))
5051 return m68k_symbolic_jump
;
5057 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
5058 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
5061 rtx this_slot
, offset
, addr
, mem
, tmp
;
5064 /* Avoid clobbering the struct value reg by using the
5065 static chain reg as a temporary. */
5066 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5068 /* Pretend to be a post-reload pass while generating rtl. */
5069 reload_completed
= 1;
5071 /* The "this" pointer is stored at 4(%sp). */
5072 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
,
5073 stack_pointer_rtx
, 4));
5075 /* Add DELTA to THIS. */
5078 /* Make the offset a legitimate operand for memory addition. */
5079 offset
= GEN_INT (delta
);
5080 if ((delta
< -8 || delta
> 8)
5081 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5083 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5084 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5086 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5087 copy_rtx (this_slot
), offset
));
5090 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5091 if (vcall_offset
!= 0)
5093 /* Set the static chain register to *THIS. */
5094 emit_move_insn (tmp
, this_slot
);
5095 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5097 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5098 addr
= plus_constant (Pmode
, tmp
, vcall_offset
);
5099 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5101 emit_insn (gen_rtx_SET (tmp
, addr
));
5105 /* Load the offset into %d0 and add it to THIS. */
5106 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5107 gen_rtx_MEM (Pmode
, addr
));
5108 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5109 copy_rtx (this_slot
),
5110 gen_rtx_REG (Pmode
, D0_REG
)));
5113 /* Jump to the target function. Use a sibcall if direct jumps are
5114 allowed, otherwise load the address into a register first. */
5115 mem
= DECL_RTL (function
);
5116 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5118 gcc_assert (flag_pic
);
5120 if (!TARGET_SEP_DATA
)
5122 /* Use the static chain register as a temporary (call-clobbered)
5123 GOT pointer for this function. We can use the static chain
5124 register because it isn't live on entry to the thunk. */
5125 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5126 emit_insn (gen_load_got (pic_offset_table_rtx
));
5128 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5129 mem
= replace_equiv_address (mem
, tmp
);
5131 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5132 SIBLING_CALL_P (insn
) = 1;
5134 /* Run just enough of rest_of_compilation. */
5135 insn
= get_insns ();
5136 split_all_insns_noflow ();
5137 final_start_function (insn
, file
, 1);
5138 final (insn
, file
, 1);
5139 final_end_function ();
5141 /* Clean up the vars set above. */
5142 reload_completed
= 0;
5144 /* Restore the original PIC register. */
5146 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5149 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5152 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5153 int incoming ATTRIBUTE_UNUSED
)
5155 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5158 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5160 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5161 unsigned int new_reg
)
5164 /* Interrupt functions can only use registers that have already been
5165 saved by the prologue, even if they would normally be
5168 if ((m68k_get_function_kind (current_function_decl
)
5169 == m68k_fk_interrupt_handler
)
5170 && !df_regs_ever_live_p (new_reg
))
5176 /* Value is true if hard register REGNO can hold a value of machine-mode
5177 MODE. On the 68000, we let the cpu registers can hold any mode, but
5178 restrict the 68881 registers to floating-point modes. */
5181 m68k_regno_mode_ok (int regno
, machine_mode mode
)
5183 if (DATA_REGNO_P (regno
))
5185 /* Data Registers, can hold aggregate if fits in. */
5186 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5189 else if (ADDRESS_REGNO_P (regno
))
5191 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5194 else if (FP_REGNO_P (regno
))
5196 /* FPU registers, hold float or complex float of long double or
5198 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5199 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5200 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5206 /* Implement SECONDARY_RELOAD_CLASS. */
5209 m68k_secondary_reload_class (enum reg_class rclass
,
5210 machine_mode mode
, rtx x
)
5214 regno
= true_regnum (x
);
5216 /* If one operand of a movqi is an address register, the other
5217 operand must be a general register or constant. Other types
5218 of operand must be reloaded through a data register. */
5219 if (GET_MODE_SIZE (mode
) == 1
5220 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5221 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5224 /* PC-relative addresses must be loaded into an address register first. */
5226 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5227 && symbolic_operand (x
, VOIDmode
))
5233 /* Implement PREFERRED_RELOAD_CLASS. */
5236 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5238 enum reg_class secondary_class
;
5240 /* If RCLASS might need a secondary reload, try restricting it to
5241 a class that doesn't. */
5242 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5243 if (secondary_class
!= NO_REGS
5244 && reg_class_subset_p (secondary_class
, rclass
))
5245 return secondary_class
;
5247 /* Prefer to use moveq for in-range constants. */
5248 if (GET_CODE (x
) == CONST_INT
5249 && reg_class_subset_p (DATA_REGS
, rclass
)
5250 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5253 /* ??? Do we really need this now? */
5254 if (GET_CODE (x
) == CONST_DOUBLE
5255 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5257 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5266 /* Return floating point values in a 68881 register. This makes 68881 code
5267 a little bit faster. It also makes -msoft-float code incompatible with
5268 hard-float code, so people have to be careful not to mix the two.
5269 For ColdFire it was decided the ABI incompatibility is undesirable.
5270 If there is need for a hard-float ABI it is probably worth doing it
5271 properly and also passing function arguments in FP registers. */
5273 m68k_libcall_value (machine_mode mode
)
5280 return gen_rtx_REG (mode
, FP0_REG
);
5286 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5289 /* Location in which function value is returned.
5290 NOTE: Due to differences in ABIs, don't call this function directly,
5291 use FUNCTION_VALUE instead. */
5293 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5297 mode
= TYPE_MODE (valtype
);
5303 return gen_rtx_REG (mode
, FP0_REG
);
5309 /* If the function returns a pointer, push that into %a0. */
5310 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5311 /* For compatibility with the large body of existing code which
5312 does not always properly declare external functions returning
5313 pointer types, the m68k/SVR4 convention is to copy the value
5314 returned for pointer functions from a0 to d0 in the function
5315 epilogue, so that callers that have neglected to properly
5316 declare the callee can still find the correct return value in
5318 return gen_rtx_PARALLEL
5321 gen_rtx_EXPR_LIST (VOIDmode
,
5322 gen_rtx_REG (mode
, A0_REG
),
5324 gen_rtx_EXPR_LIST (VOIDmode
,
5325 gen_rtx_REG (mode
, D0_REG
),
5327 else if (POINTER_TYPE_P (valtype
))
5328 return gen_rtx_REG (mode
, A0_REG
);
5330 return gen_rtx_REG (mode
, D0_REG
);
5333 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5334 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5336 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5338 machine_mode mode
= TYPE_MODE (type
);
5340 if (mode
== BLKmode
)
5343 /* If TYPE's known alignment is less than the alignment of MODE that
5344 would contain the structure, then return in memory. We need to
5345 do so to maintain the compatibility between code compiled with
5346 -mstrict-align and that compiled with -mno-strict-align. */
5347 if (AGGREGATE_TYPE_P (type
)
5348 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5355 /* CPU to schedule the program for. */
5356 enum attr_cpu m68k_sched_cpu
;
5358 /* MAC to schedule the program for. */
5359 enum attr_mac m68k_sched_mac
;
5367 /* Integer register. */
5373 /* Implicit mem reference (e.g. stack). */
5376 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5379 /* Memory with offset but without indexing. EA mode 5. */
5382 /* Memory with indexing. EA mode 6. */
5385 /* Memory referenced by absolute address. EA mode 7. */
5388 /* Immediate operand that doesn't require extension word. */
5391 /* Immediate 16 bit operand. */
5394 /* Immediate 32 bit operand. */
5398 /* Return type of memory ADDR_RTX refers to. */
5399 static enum attr_op_type
5400 sched_address_type (machine_mode mode
, rtx addr_rtx
)
5402 struct m68k_address address
;
5404 if (symbolic_operand (addr_rtx
, VOIDmode
))
5405 return OP_TYPE_MEM7
;
5407 if (!m68k_decompose_address (mode
, addr_rtx
,
5408 reload_completed
, &address
))
5410 gcc_assert (!reload_completed
);
5411 /* Reload will likely fix the address to be in the register. */
5412 return OP_TYPE_MEM234
;
5415 if (address
.scale
!= 0)
5416 return OP_TYPE_MEM6
;
5418 if (address
.base
!= NULL_RTX
)
5420 if (address
.offset
== NULL_RTX
)
5421 return OP_TYPE_MEM234
;
5423 return OP_TYPE_MEM5
;
5426 gcc_assert (address
.offset
!= NULL_RTX
);
5428 return OP_TYPE_MEM7
;
5431 /* Return X or Y (depending on OPX_P) operand of INSN. */
5433 sched_get_operand (rtx_insn
*insn
, bool opx_p
)
5437 if (recog_memoized (insn
) < 0)
5440 extract_constrain_insn_cached (insn
);
5443 i
= get_attr_opx (insn
);
5445 i
= get_attr_opy (insn
);
5447 if (i
>= recog_data
.n_operands
)
5450 return recog_data
.operand
[i
];
5453 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5454 If ADDRESS_P is true, return type of memory location operand refers to. */
5455 static enum attr_op_type
5456 sched_attr_op_type (rtx_insn
*insn
, bool opx_p
, bool address_p
)
5460 op
= sched_get_operand (insn
, opx_p
);
5464 gcc_assert (!reload_completed
);
5469 return sched_address_type (QImode
, op
);
5471 if (memory_operand (op
, VOIDmode
))
5472 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
5474 if (register_operand (op
, VOIDmode
))
5476 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
5477 || (reload_completed
&& FP_REG_P (op
)))
5483 if (GET_CODE (op
) == CONST_INT
)
5489 /* Check for quick constants. */
5490 switch (get_attr_type (insn
))
5493 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
5494 return OP_TYPE_IMM_Q
;
5496 gcc_assert (!reload_completed
);
5500 if (USE_MOVQ (ival
))
5501 return OP_TYPE_IMM_Q
;
5503 gcc_assert (!reload_completed
);
5507 if (valid_mov3q_const (ival
))
5508 return OP_TYPE_IMM_Q
;
5510 gcc_assert (!reload_completed
);
5517 if (IN_RANGE (ival
, -0x8000, 0x7fff))
5518 return OP_TYPE_IMM_W
;
5520 return OP_TYPE_IMM_L
;
5523 if (GET_CODE (op
) == CONST_DOUBLE
)
5525 switch (GET_MODE (op
))
5528 return OP_TYPE_IMM_W
;
5532 return OP_TYPE_IMM_L
;
5539 if (GET_CODE (op
) == CONST
5540 || symbolic_operand (op
, VOIDmode
)
5543 switch (GET_MODE (op
))
5546 return OP_TYPE_IMM_Q
;
5549 return OP_TYPE_IMM_W
;
5552 return OP_TYPE_IMM_L
;
5555 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
5557 return OP_TYPE_IMM_W
;
5559 return OP_TYPE_IMM_L
;
5563 gcc_assert (!reload_completed
);
5565 if (FLOAT_MODE_P (GET_MODE (op
)))
5571 /* Implement opx_type attribute.
5572 Return type of INSN's operand X.
5573 If ADDRESS_P is true, return type of memory location operand refers to. */
5575 m68k_sched_attr_opx_type (rtx_insn
*insn
, int address_p
)
5577 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
5583 return OPX_TYPE_FPN
;
5586 return OPX_TYPE_MEM1
;
5588 case OP_TYPE_MEM234
:
5589 return OPX_TYPE_MEM234
;
5592 return OPX_TYPE_MEM5
;
5595 return OPX_TYPE_MEM6
;
5598 return OPX_TYPE_MEM7
;
5601 return OPX_TYPE_IMM_Q
;
5604 return OPX_TYPE_IMM_W
;
5607 return OPX_TYPE_IMM_L
;
5614 /* Implement opy_type attribute.
5615 Return type of INSN's operand Y.
5616 If ADDRESS_P is true, return type of memory location operand refers to. */
5618 m68k_sched_attr_opy_type (rtx_insn
*insn
, int address_p
)
5620 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
5626 return OPY_TYPE_FPN
;
5629 return OPY_TYPE_MEM1
;
5631 case OP_TYPE_MEM234
:
5632 return OPY_TYPE_MEM234
;
5635 return OPY_TYPE_MEM5
;
5638 return OPY_TYPE_MEM6
;
5641 return OPY_TYPE_MEM7
;
5644 return OPY_TYPE_IMM_Q
;
5647 return OPY_TYPE_IMM_W
;
5650 return OPY_TYPE_IMM_L
;
5657 /* Return size of INSN as int. */
5659 sched_get_attr_size_int (rtx_insn
*insn
)
5663 switch (get_attr_type (insn
))
5666 /* There should be no references to m68k_sched_attr_size for 'ignore'
5680 switch (get_attr_opx_type (insn
))
5686 case OPX_TYPE_MEM234
:
5687 case OPY_TYPE_IMM_Q
:
5692 /* Here we assume that most absolute references are short. */
5694 case OPY_TYPE_IMM_W
:
5698 case OPY_TYPE_IMM_L
:
5706 switch (get_attr_opy_type (insn
))
5712 case OPY_TYPE_MEM234
:
5713 case OPY_TYPE_IMM_Q
:
5718 /* Here we assume that most absolute references are short. */
5720 case OPY_TYPE_IMM_W
:
5724 case OPY_TYPE_IMM_L
:
5734 gcc_assert (!reload_completed
);
5742 /* Return size of INSN as attribute enum value. */
5744 m68k_sched_attr_size (rtx_insn
*insn
)
5746 switch (sched_get_attr_size_int (insn
))
5762 /* Return operand X or Y (depending on OPX_P) of INSN,
5763 if it is a MEM, or NULL overwise. */
5764 static enum attr_op_type
5765 sched_get_opxy_mem_type (rtx_insn
*insn
, bool opx_p
)
5769 switch (get_attr_opx_type (insn
))
5774 case OPX_TYPE_IMM_Q
:
5775 case OPX_TYPE_IMM_W
:
5776 case OPX_TYPE_IMM_L
:
5780 case OPX_TYPE_MEM234
:
5783 return OP_TYPE_MEM1
;
5786 return OP_TYPE_MEM6
;
5794 switch (get_attr_opy_type (insn
))
5799 case OPY_TYPE_IMM_Q
:
5800 case OPY_TYPE_IMM_W
:
5801 case OPY_TYPE_IMM_L
:
5805 case OPY_TYPE_MEM234
:
5808 return OP_TYPE_MEM1
;
5811 return OP_TYPE_MEM6
;
5819 /* Implement op_mem attribute. */
5821 m68k_sched_attr_op_mem (rtx_insn
*insn
)
5823 enum attr_op_type opx
;
5824 enum attr_op_type opy
;
5826 opx
= sched_get_opxy_mem_type (insn
, true);
5827 opy
= sched_get_opxy_mem_type (insn
, false);
5829 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5832 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5834 switch (get_attr_opx_access (insn
))
5850 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5852 switch (get_attr_opx_access (insn
))
5868 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5871 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5873 switch (get_attr_opx_access (insn
))
5879 gcc_assert (!reload_completed
);
5884 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5886 switch (get_attr_opx_access (insn
))
5892 gcc_assert (!reload_completed
);
5897 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5900 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5902 switch (get_attr_opx_access (insn
))
5908 gcc_assert (!reload_completed
);
5913 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5914 gcc_assert (!reload_completed
);
5918 /* Data for ColdFire V4 index bypass.
5919 Producer modifies register that is used as index in consumer with
5923 /* Producer instruction. */
5926 /* Consumer instruction. */
5929 /* Scale of indexed memory access within consumer.
5930 Or zero if bypass should not be effective at the moment. */
5932 } sched_cfv4_bypass_data
;
5934 /* An empty state that is used in m68k_sched_adjust_cost. */
5935 static state_t sched_adjust_cost_state
;
5937 /* Implement adjust_cost scheduler hook.
5938 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5940 m68k_sched_adjust_cost (rtx_insn
*insn
, rtx link ATTRIBUTE_UNUSED
,
5941 rtx_insn
*def_insn
, int cost
)
5945 if (recog_memoized (def_insn
) < 0
5946 || recog_memoized (insn
) < 0)
5949 if (sched_cfv4_bypass_data
.scale
== 1)
5950 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5952 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5953 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5954 that the data in sched_cfv4_bypass_data is up to date. */
5955 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5956 && sched_cfv4_bypass_data
.con
== insn
);
5961 sched_cfv4_bypass_data
.pro
= NULL
;
5962 sched_cfv4_bypass_data
.con
= NULL
;
5963 sched_cfv4_bypass_data
.scale
= 0;
5966 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
5967 && sched_cfv4_bypass_data
.con
== NULL
5968 && sched_cfv4_bypass_data
.scale
== 0);
5970 /* Don't try to issue INSN earlier than DFA permits.
5971 This is especially useful for instructions that write to memory,
5972 as their true dependence (default) latency is better to be set to 0
5973 to workaround alias analysis limitations.
5974 This is, in fact, a machine independent tweak, so, probably,
5975 it should be moved to haifa-sched.c: insn_cost (). */
5976 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
5983 /* Return maximal number of insns that can be scheduled on a single cycle. */
5985 m68k_sched_issue_rate (void)
5987 switch (m68k_sched_cpu
)
6003 /* Maximal length of instruction for current CPU.
6004 E.g. it is 3 for any ColdFire core. */
6005 static int max_insn_size
;
6007 /* Data to model instruction buffer of CPU. */
6010 /* True if instruction buffer model is modeled for current CPU. */
6013 /* Size of the instruction buffer in words. */
6016 /* Number of filled words in the instruction buffer. */
6019 /* Additional information about instruction buffer for CPUs that have
6020 a buffer of instruction records, rather then a plain buffer
6021 of instruction words. */
6022 struct _sched_ib_records
6024 /* Size of buffer in records. */
6027 /* Array to hold data on adjustements made to the size of the buffer. */
6030 /* Index of the above array. */
6034 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6038 static struct _sched_ib sched_ib
;
6040 /* ID of memory unit. */
6041 static int sched_mem_unit_code
;
6043 /* Implementation of the targetm.sched.variable_issue () hook.
6044 It is called after INSN was issued. It returns the number of insns
6045 that can possibly get scheduled on the current cycle.
6046 It is used here to determine the effect of INSN on the instruction
6049 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6050 int sched_verbose ATTRIBUTE_UNUSED
,
6051 rtx_insn
*insn
, int can_issue_more
)
6055 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6057 switch (m68k_sched_cpu
)
6061 insn_size
= sched_get_attr_size_int (insn
);
6065 insn_size
= sched_get_attr_size_int (insn
);
6067 /* ColdFire V3 and V4 cores have instruction buffers that can
6068 accumulate up to 8 instructions regardless of instructions'
6069 sizes. So we should take care not to "prefetch" 24 one-word
6070 or 12 two-words instructions.
6071 To model this behavior we temporarily decrease size of the
6072 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6076 adjust
= max_insn_size
- insn_size
;
6077 sched_ib
.size
-= adjust
;
6079 if (sched_ib
.filled
> sched_ib
.size
)
6080 sched_ib
.filled
= sched_ib
.size
;
6082 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6085 ++sched_ib
.records
.adjust_index
;
6086 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6087 sched_ib
.records
.adjust_index
= 0;
6089 /* Undo adjustement we did 7 instructions ago. */
6091 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6096 gcc_assert (!sched_ib
.enabled_p
);
6104 if (insn_size
> sched_ib
.filled
)
6105 /* Scheduling for register pressure does not always take DFA into
6106 account. Workaround instruction buffer not being filled enough. */
6108 gcc_assert (sched_pressure
== SCHED_PRESSURE_WEIGHTED
);
6109 insn_size
= sched_ib
.filled
;
6114 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6115 || asm_noperands (PATTERN (insn
)) >= 0)
6116 insn_size
= sched_ib
.filled
;
6120 sched_ib
.filled
-= insn_size
;
6122 return can_issue_more
;
6125 /* Return how many instructions should scheduler lookahead to choose the
6128 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6130 return m68k_sched_issue_rate () - 1;
6133 /* Implementation of targetm.sched.init_global () hook.
6134 It is invoked once per scheduling pass and is used here
6135 to initialize scheduler constants. */
6137 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6138 int sched_verbose ATTRIBUTE_UNUSED
,
6139 int n_insns ATTRIBUTE_UNUSED
)
6141 #ifdef ENABLE_CHECKING
6142 /* Check that all instructions have DFA reservations and
6143 that all instructions can be issued from a clean state. */
6148 state
= alloca (state_size ());
6150 for (insn
= get_insns (); insn
!= NULL
; insn
= NEXT_INSN (insn
))
6152 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6154 gcc_assert (insn_has_dfa_reservation_p (insn
));
6156 state_reset (state
);
6157 if (state_transition (state
, insn
) >= 0)
6164 /* Setup target cpu. */
6166 /* ColdFire V4 has a set of features to keep its instruction buffer full
6167 (e.g., a separate memory bus for instructions) and, hence, we do not model
6168 buffer for this CPU. */
6169 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6171 switch (m68k_sched_cpu
)
6174 sched_ib
.filled
= 0;
6181 sched_ib
.records
.n_insns
= 0;
6182 sched_ib
.records
.adjust
= NULL
;
6187 sched_ib
.records
.n_insns
= 8;
6188 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6195 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6197 sched_adjust_cost_state
= xmalloc (state_size ());
6198 state_reset (sched_adjust_cost_state
);
6201 emit_insn (gen_ib ());
6202 sched_ib
.insn
= get_insns ();
6206 /* Scheduling pass is now finished. Free/reset static variables. */
6208 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6209 int verbose ATTRIBUTE_UNUSED
)
6211 sched_ib
.insn
= NULL
;
6213 free (sched_adjust_cost_state
);
6214 sched_adjust_cost_state
= NULL
;
6216 sched_mem_unit_code
= 0;
6218 free (sched_ib
.records
.adjust
);
6219 sched_ib
.records
.adjust
= NULL
;
6220 sched_ib
.records
.n_insns
= 0;
6224 /* Implementation of targetm.sched.init () hook.
6225 It is invoked each time scheduler starts on the new block (basic block or
6226 extended basic block). */
6228 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6229 int sched_verbose ATTRIBUTE_UNUSED
,
6230 int n_insns ATTRIBUTE_UNUSED
)
6232 switch (m68k_sched_cpu
)
6240 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6242 memset (sched_ib
.records
.adjust
, 0,
6243 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6244 sched_ib
.records
.adjust_index
= 0;
6248 gcc_assert (!sched_ib
.enabled_p
);
6256 if (sched_ib
.enabled_p
)
6257 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6258 the first cycle. Workaround that. */
6259 sched_ib
.filled
= -2;
6262 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6263 It is invoked just before current cycle finishes and is used here
6264 to track if instruction buffer got its two words this cycle. */
6266 m68k_sched_dfa_pre_advance_cycle (void)
6268 if (!sched_ib
.enabled_p
)
6271 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6273 sched_ib
.filled
+= 2;
6275 if (sched_ib
.filled
> sched_ib
.size
)
6276 sched_ib
.filled
= sched_ib
.size
;
6280 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6281 It is invoked just after new cycle begins and is used here
6282 to setup number of filled words in the instruction buffer so that
6283 instructions which won't have all their words prefetched would be
6284 stalled for a cycle. */
6286 m68k_sched_dfa_post_advance_cycle (void)
6290 if (!sched_ib
.enabled_p
)
6293 /* Setup number of prefetched instruction words in the instruction
6295 i
= max_insn_size
- sched_ib
.filled
;
6299 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6300 /* Pick up scheduler state. */
6305 /* Return X or Y (depending on OPX_P) operand of INSN,
6306 if it is an integer register, or NULL overwise. */
6308 sched_get_reg_operand (rtx_insn
*insn
, bool opx_p
)
6314 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6316 op
= sched_get_operand (insn
, true);
6317 gcc_assert (op
!= NULL
);
6319 if (!reload_completed
&& !REG_P (op
))
6325 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6327 op
= sched_get_operand (insn
, false);
6328 gcc_assert (op
!= NULL
);
6330 if (!reload_completed
&& !REG_P (op
))
6338 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6341 sched_mem_operand_p (rtx_insn
*insn
, bool opx_p
)
6343 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6354 /* Return X or Y (depending on OPX_P) operand of INSN,
6355 if it is a MEM, or NULL overwise. */
6357 sched_get_mem_operand (rtx_insn
*insn
, bool must_read_p
, bool must_write_p
)
6377 if (opy_p
&& sched_mem_operand_p (insn
, false))
6378 return sched_get_operand (insn
, false);
6380 if (opx_p
&& sched_mem_operand_p (insn
, true))
6381 return sched_get_operand (insn
, true);
6387 /* Return non-zero if PRO modifies register used as part of
6390 m68k_sched_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6395 pro_x
= sched_get_reg_operand (pro
, true);
6399 con_mem_read
= sched_get_mem_operand (con
, true, false);
6400 gcc_assert (con_mem_read
!= NULL
);
6402 if (reg_mentioned_p (pro_x
, con_mem_read
))
6408 /* Helper function for m68k_sched_indexed_address_bypass_p.
6409 if PRO modifies register used as index in CON,
6410 return scale of indexed memory access in CON. Return zero overwise. */
6412 sched_get_indexed_address_scale (rtx_insn
*pro
, rtx_insn
*con
)
6416 struct m68k_address address
;
6418 reg
= sched_get_reg_operand (pro
, true);
6422 mem
= sched_get_mem_operand (con
, true, false);
6423 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6425 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6429 if (REGNO (reg
) == REGNO (address
.index
))
6431 gcc_assert (address
.scale
!= 0);
6432 return address
.scale
;
6438 /* Return non-zero if PRO modifies register used
6439 as index with scale 2 or 4 in CON. */
6441 m68k_sched_indexed_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6443 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6444 && sched_cfv4_bypass_data
.con
== NULL
6445 && sched_cfv4_bypass_data
.scale
== 0);
6447 switch (sched_get_indexed_address_scale (pro
, con
))
6450 /* We can't have a variable latency bypass, so
6451 remember to adjust the insn cost in adjust_cost hook. */
6452 sched_cfv4_bypass_data
.pro
= pro
;
6453 sched_cfv4_bypass_data
.con
= con
;
6454 sched_cfv4_bypass_data
.scale
= 1;
6466 /* We generate a two-instructions program at M_TRAMP :
6467 movea.l &CHAIN_VALUE,%a0
6469 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6472 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
6474 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6477 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
6479 mem
= adjust_address (m_tramp
, HImode
, 0);
6480 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
6481 mem
= adjust_address (m_tramp
, SImode
, 2);
6482 emit_move_insn (mem
, chain_value
);
6484 mem
= adjust_address (m_tramp
, HImode
, 6);
6485 emit_move_insn (mem
, GEN_INT(0x4EF9));
6486 mem
= adjust_address (m_tramp
, SImode
, 8);
6487 emit_move_insn (mem
, fnaddr
);
6489 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
6492 /* On the 68000, the RTS insn cannot pop anything.
6493 On the 68010, the RTD insn may be used to pop them if the number
6494 of args is fixed, but if the number is variable then the caller
6495 must pop them all. RTD can't be used for library calls now
6496 because the library is compiled with the Unix compiler.
6497 Use of RTD is a selectable option, since it is incompatible with
6498 standard Unix calling sequences. If the option is not selected,
6499 the caller must always pop the args. */
6502 m68k_return_pops_args (tree fundecl
, tree funtype
, int size
)
6506 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
6507 && (!stdarg_p (funtype
)))
6511 /* Make sure everything's fine if we *don't* have a given processor.
6512 This assumes that putting a register in fixed_regs will keep the
6513 compiler's mitts completely off it. We don't bother to zero it out
6514 of register classes. */
6517 m68k_conditional_register_usage (void)
6521 if (!TARGET_HARD_FLOAT
)
6523 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FP_REGS
]);
6524 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6525 if (TEST_HARD_REG_BIT (x
, i
))
6526 fixed_regs
[i
] = call_used_regs
[i
] = 1;
6529 fixed_regs
[PIC_REG
] = call_used_regs
[PIC_REG
] = 1;
6533 m68k_init_sync_libfuncs (void)
6535 init_sync_libfuncs (UNITS_PER_WORD
);
6538 /* Implements EPILOGUE_USES. All registers are live on exit from an
6539 interrupt routine. */
6541 m68k_epilogue_uses (int regno ATTRIBUTE_UNUSED
)
6543 return (reload_completed
6544 && (m68k_get_function_kind (current_function_decl
)
6545 == m68k_fk_interrupt_handler
));
6548 #include "gt-m68k.h"