| blob | d0eee18aa0e38c18336706dd4c9f11f7d96650ee |
1 ;; iq2000.md Machine Description for Vitesse IQ2000 processors
2 ;; Copyright (C) 2003-2015 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
9 ;; any later version.
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 (define_constants
21 [(UNSPEC_ADO16 0)
22 (UNSPEC_RAM 1)
23 (UNSPEC_CHKHDR 2)
24 (UNSPEC_PKRL 3)
25 (UNSPEC_CFC0 4)
26 (UNSPEC_CFC1 5)
27 (UNSPEC_CFC2 6)
28 (UNSPEC_CFC3 7)
29 (UNSPEC_CTC0 8)
30 (UNSPEC_CTC1 9)
31 (UNSPEC_CTC2 10)
32 (UNSPEC_CTC3 11)
33 (UNSPEC_MFC0 12)
34 (UNSPEC_MFC1 13)
35 (UNSPEC_MFC2 14)
36 (UNSPEC_MFC3 15)
37 (UNSPEC_MTC0 16)
38 (UNSPEC_MTC1 17)
39 (UNSPEC_MTC2 18)
40 (UNSPEC_MTC3 19)
41 (UNSPEC_LUR 20)
42 (UNSPEC_RB 21)
43 (UNSPEC_RX 22)
44 (UNSPEC_SRRD 23)
45 (UNSPEC_SRWR 24)
46 (UNSPEC_WB 25)
47 (UNSPEC_WX 26)
48 (UNSPEC_LUC32 49)
49 (UNSPEC_LUC32L 27)
50 (UNSPEC_LUC64 28)
51 (UNSPEC_LUC64L 29)
52 (UNSPEC_LUK 30)
53 (UNSPEC_LULCK 31)
54 (UNSPEC_LUM32 32)
55 (UNSPEC_LUM32L 33)
56 (UNSPEC_LUM64 34)
57 (UNSPEC_LUM64L 35)
58 (UNSPEC_LURL 36)
59 (UNSPEC_MRGB 37)
60 (UNSPEC_SRRDL 38)
61 (UNSPEC_SRULCK 39)
62 (UNSPEC_SRWRU 40)
63 (UNSPEC_TRAPQFL 41)
64 (UNSPEC_TRAPQNE 42)
65 (UNSPEC_TRAPREL 43)
66 (UNSPEC_WBU 44)
67 (UNSPEC_SYSCALL 45)]
68 )
69 ;; UNSPEC values used in iq2000.md
70 ;; Number USE
71 ;; 0 movsi_ul
72 ;; 1 movsi_us, get_fnaddr
73 ;; 3 eh_set_return
74 ;; 20 builtin_setjmp_setup
75 ;;
76 ;; UNSPEC_VOLATILE values
77 ;; 0 blockage
78 ;; 2 loadgp
79 ;; 3 builtin_longjmp
80 ;; 4 exception_receiver
81 ;; 10 consttable_qi
82 ;; 11 consttable_hi
83 ;; 12 consttable_si
84 ;; 13 consttable_di
85 ;; 14 consttable_sf
86 ;; 15 consttable_df
87 ;; 16 align_2
88 ;; 17 align_4
89 ;; 18 align_8
90 \f
92 ;; ....................
93 ;;
94 ;; Attributes
95 ;;
96 ;; ....................
98 ;; Classification of each insn.
99 ;; branch conditional branch
100 ;; jump unconditional jump
101 ;; call unconditional call
102 ;; load load instruction(s)
103 ;; store store instruction(s)
104 ;; move data movement within same register set
105 ;; xfer transfer to/from coprocessor
106 ;; arith integer arithmetic instruction
107 ;; darith double precision integer arithmetic instructions
108 ;; imul integer multiply
109 ;; idiv integer divide
110 ;; icmp integer compare
111 ;; fadd floating point add/subtract
112 ;; fmul floating point multiply
113 ;; fmadd floating point multiply-add
114 ;; fdiv floating point divide
115 ;; fabs floating point absolute value
116 ;; fneg floating point negation
117 ;; fcmp floating point compare
118 ;; fcvt floating point convert
119 ;; fsqrt floating point square root
120 ;; multi multiword sequence (or user asm statements)
121 ;; nop no operation
123 (define_attr "type"
124 "unknown,branch,jump,call,load,store,move,xfer,arith,darith,imul,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop"
125 (const_string "unknown"))
127 ;; Main data type used by the insn
128 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
130 ;; Length (in # of bytes). A conditional branch is allowed only to a
131 ;; location within a signed 18-bit offset of the delay slot. If that
132 ;; provides too small a range, we use the `j' instruction. This
133 ;; instruction takes a 28-bit value, but that value is not an offset.
134 ;; Instead, it's bitwise-ored with the high-order four bits of the
135 ;; instruction in the delay slot, which means it cannot be used to
136 ;; cross a 256MB boundary. We could fall back back on the jr,
137 ;; instruction which allows full access to the entire address space,
138 ;; but we do not do so at present.
140 (define_attr "length" ""
141 (cond [(eq_attr "type" "branch")
142 (cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4))))
143 (const_int 131072))
144 (const_int 4)]
145 (const_int 12))]
146 (const_int 4)))
148 (define_attr "cpu"
149 "default,iq2000"
150 (const (symbol_ref "iq2000_cpu_attr")))
152 ;; Does the instruction have a mandatory delay slot? has_dslot
153 ;; Can the instruction be in a delay slot? ok_in_dslot
154 ;; Can the instruction not be in a delay slot? not_in_dslot
155 (define_attr "dslot" "has_dslot,ok_in_dslot,not_in_dslot"
156 (if_then_else (eq_attr "type" "branch,jump,call,xfer,fcmp")
157 (const_string "has_dslot")
158 (const_string "ok_in_dslot")))
160 ;; Attribute defining whether or not we can use the branch-likely instructions
162 (define_attr "branch_likely" "no,yes"
163 (const
164 (if_then_else (match_test "GENERATE_BRANCHLIKELY")
165 (const_string "yes")
166 (const_string "no"))))
169 ;; Describe a user's asm statement.
170 (define_asm_attributes
171 [(set_attr "type" "multi")])
173 \f
175 ;; .........................
176 ;;
177 ;; Delay slots, can't describe load/fcmp/xfer delay slots here
178 ;;
179 ;; .........................
181 (define_delay (eq_attr "type" "jump")
182 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
183 (nil)
184 (nil)])
186 (define_delay (eq_attr "type" "branch")
187 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
188 (nil)
189 (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")))])
191 (define_delay (eq_attr "type" "call")
192 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
193 (nil)
194 (nil)])
196 (include "predicates.md")
197 (include "constraints.md")
198 \f
200 ;; .........................
201 ;;
202 ;; Pipeline model
203 ;;
204 ;; .........................
206 (define_automaton "iq2000")
207 (define_cpu_unit "core,memory" "iq2000")
209 (define_insn_reservation "nonmemory" 1
210 (eq_attr "type" "!load,move,store,xfer")
211 "core")
213 (define_insn_reservation "iq2000_load_move" 3
214 (and (eq_attr "type" "load,move")
215 (eq_attr "cpu" "iq2000"))
216 "memory")
218 (define_insn_reservation "other_load_move" 1
219 (and (eq_attr "type" "load,move")
220 (eq_attr "cpu" "!iq2000"))
221 "memory")
223 (define_insn_reservation "store" 1
224 (eq_attr "type" "store")
225 "memory")
227 (define_insn_reservation "xfer" 2
228 (eq_attr "type" "xfer")
229 "memory")
230 \f
231 ;;
232 ;; ....................
233 ;;
234 ;; CONDITIONAL TRAPS
235 ;;
236 ;; ....................
237 ;;
239 (define_insn "trap"
240 [(trap_if (const_int 1) (const_int 0))]
241 ""
242 "*
243 {
244 return \"break\";
245 }")
246 \f
247 ;;
248 ;; ....................
249 ;;
250 ;; ADDITION
251 ;;
252 ;; ....................
253 ;;
255 (define_expand "addsi3"
256 [(set (match_operand:SI 0 "register_operand" "=d")
257 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
258 (match_operand:SI 2 "arith_operand" "dI")))]
259 ""
260 "")
262 (define_insn "addsi3_internal"
263 [(set (match_operand:SI 0 "register_operand" "=d,d")
264 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
265 (match_operand:SI 2 "arith_operand" "d,I")))]
266 ""
267 "@
268 addu\\t%0,%z1,%2
269 addiu\\t%0,%z1,%2"
270 [(set_attr "type" "arith")
271 (set_attr "mode" "SI")])
272 \f
273 ;;
274 ;; ....................
275 ;;
276 ;; SUBTRACTION
277 ;;
278 ;; ....................
279 ;;
281 (define_expand "subsi3"
282 [(set (match_operand:SI 0 "register_operand" "=d")
283 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
284 (match_operand:SI 2 "arith_operand" "dI")))]
285 ""
286 "")
288 (define_insn "subsi3_internal"
289 [(set (match_operand:SI 0 "register_operand" "=d,d")
290 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
291 (match_operand:SI 2 "arith_operand" "d,I")))]
292 ""
293 "@
294 subu\\t%0,%z1,%2
295 addiu\\t%0,%z1,%n2"
296 [(set_attr "type" "arith")
297 (set_attr "mode" "SI")])
298 \f
299 ;;
300 ;; ....................
301 ;;
302 ;; NEGATION and ONE'S COMPLEMENT
303 ;;
304 ;; ....................
306 (define_insn "negsi2"
307 [(set (match_operand:SI 0 "register_operand" "=d")
308 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
309 ""
310 "*
311 {
312 operands[2] = const0_rtx;
313 return \"subu\\t%0,%z2,%1\";
314 }"
315 [(set_attr "type" "arith")
316 (set_attr "mode" "SI")])
318 (define_insn "one_cmplsi2"
319 [(set (match_operand:SI 0 "register_operand" "=d")
320 (not:SI (match_operand:SI 1 "register_operand" "d")))]
321 ""
322 "*
323 {
324 operands[2] = const0_rtx;
325 return \"nor\\t%0,%z2,%1\";
326 }"
327 [(set_attr "type" "arith")
328 (set_attr "mode" "SI")])
329 \f
330 ;;
331 ;; ....................
332 ;;
333 ;; LOGICAL
334 ;;
335 ;; ....................
336 ;;
338 (define_expand "andsi3"
339 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
340 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d")
341 (match_operand:SI 2 "nonmemory_operand" "d,K,N")))]
342 ""
343 "")
345 (define_insn ""
346 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
347 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d")
348 (match_operand:SI 2 "nonmemory_operand" "d,K,N")))]
349 ""
350 "*
351 {
352 if (which_alternative == 0)
353 return \"and\\t%0,%1,%2\";
354 else if (which_alternative == 1)
355 return \"andi\\t%0,%1,%x2\";
356 else if (which_alternative == 2)
357 {
358 if ((INTVAL (operands[2]) & 0xffff) == 0xffff)
359 {
360 operands[2] = GEN_INT (INTVAL (operands[2]) >> 16);
361 return \"andoui\\t%0,%1,%x2\";
362 }
363 else
364 {
365 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
366 return \"andoi\\t%0,%1,%x2\";
367 }
368 }
369 else
370 gcc_unreachable ();
371 }"
372 [(set_attr "type" "arith")
373 (set_attr "mode" "SI")])
375 (define_expand "iorsi3"
376 [(set (match_operand:SI 0 "register_operand" "=d,d")
377 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
378 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
379 ""
380 "")
382 (define_insn ""
383 [(set (match_operand:SI 0 "register_operand" "=d,d")
384 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
385 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
386 ""
387 "@
388 or\\t%0,%1,%2
389 ori\\t%0,%1,%x2"
390 [(set_attr "type" "arith")
391 (set_attr "mode" "SI")])
393 (define_expand "xorsi3"
394 [(set (match_operand:SI 0 "register_operand" "=d,d")
395 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
396 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
397 ""
398 "")
400 (define_insn ""
401 [(set (match_operand:SI 0 "register_operand" "=d,d")
402 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
403 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
404 ""
405 "@
406 xor\\t%0,%1,%2
407 xori\\t%0,%1,%x2"
408 [(set_attr "type" "arith")
409 (set_attr "mode" "SI")])
411 (define_insn "*norsi3"
412 [(set (match_operand:SI 0 "register_operand" "=d")
413 (and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
414 (not:SI (match_operand:SI 2 "register_operand" "d"))))]
415 ""
416 "nor\\t%0,%z1,%z2"
417 [(set_attr "type" "arith")
418 (set_attr "mode" "SI")])
419 \f
420 ;;
421 ;; ....................
422 ;;
423 ;; ZERO EXTENSION
424 ;;
425 ;; ....................
427 ;; Extension insns.
428 ;; Those for integer source operand are ordered widest source type first.
430 (define_expand "zero_extendhisi2"
431 [(set (match_operand:SI 0 "register_operand" "")
432 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
433 ""
434 "")
436 (define_insn ""
437 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
438 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
439 ""
440 "*
441 {
442 if (which_alternative == 0)
443 return \"andi\\t%0,%1,0xffff\";
444 else
445 return iq2000_move_1word (operands, insn, TRUE);
446 }"
447 [(set_attr "type" "arith,load,load")
448 (set_attr "mode" "SI")
449 (set_attr "length" "4,4,8")])
451 (define_expand "zero_extendqihi2"
452 [(set (match_operand:HI 0 "register_operand" "")
453 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
454 ""
455 "")
457 (define_insn ""
458 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
459 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
460 ""
461 "*
462 {
463 if (which_alternative == 0)
464 return \"andi\\t%0,%1,0x00ff\";
465 else
466 return iq2000_move_1word (operands, insn, TRUE);
467 }"
468 [(set_attr "type" "arith,load,load")
469 (set_attr "mode" "HI")
470 (set_attr "length" "4,4,8")])
472 (define_expand "zero_extendqisi2"
473 [(set (match_operand:SI 0 "register_operand" "")
474 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
475 ""
476 "")
478 (define_insn ""
479 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
480 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
481 ""
482 "*
483 {
484 if (which_alternative == 0)
485 return \"andi\\t%0,%1,0x00ff\";
486 else
487 return iq2000_move_1word (operands, insn, TRUE);
488 }"
489 [(set_attr "type" "arith,load,load")
490 (set_attr "mode" "SI")
491 (set_attr "length" "4,4,8")])
493 ;;
494 ;; ....................
495 ;;
496 ;; SIGN EXTENSION
497 ;;
498 ;; ....................
500 ;; Extension insns.
501 ;; Those for integer source operand are ordered widest source type first.
503 ;; These patterns originally accepted general_operands, however, slightly
504 ;; better code is generated by only accepting register_operands, and then
505 ;; letting combine generate the lh and lb insns.
507 (define_expand "extendhisi2"
508 [(set (match_operand:SI 0 "register_operand" "")
509 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
510 ""
511 "
512 {
513 if (optimize && GET_CODE (operands[1]) == MEM)
514 operands[1] = force_not_mem (operands[1]);
516 if (GET_CODE (operands[1]) != MEM)
517 {
518 rtx op1 = gen_lowpart (SImode, operands[1]);
519 rtx temp = gen_reg_rtx (SImode);
520 rtx shift = GEN_INT (16);
522 emit_insn (gen_ashlsi3 (temp, op1, shift));
523 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
524 DONE;
525 }
526 }")
528 (define_insn "extendhisi2_internal"
529 [(set (match_operand:SI 0 "register_operand" "=d,d")
530 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
531 ""
532 "* return iq2000_move_1word (operands, insn, FALSE);"
533 [(set_attr "type" "load")
534 (set_attr "mode" "SI")
535 (set_attr "length" "4,8")])
537 (define_expand "extendqihi2"
538 [(set (match_operand:HI 0 "register_operand" "")
539 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
540 ""
541 "
542 {
543 if (optimize && GET_CODE (operands[1]) == MEM)
544 operands[1] = force_not_mem (operands[1]);
546 if (GET_CODE (operands[1]) != MEM)
547 {
548 rtx op0 = gen_lowpart (SImode, operands[0]);
549 rtx op1 = gen_lowpart (SImode, operands[1]);
550 rtx temp = gen_reg_rtx (SImode);
551 rtx shift = GEN_INT (24);
553 emit_insn (gen_ashlsi3 (temp, op1, shift));
554 emit_insn (gen_ashrsi3 (op0, temp, shift));
555 DONE;
556 }
557 }")
559 (define_insn "extendqihi2_internal"
560 [(set (match_operand:HI 0 "register_operand" "=d,d")
561 (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
562 ""
563 "* return iq2000_move_1word (operands, insn, FALSE);"
564 [(set_attr "type" "load")
565 (set_attr "mode" "SI")
566 (set_attr "length" "4,8")])
569 (define_expand "extendqisi2"
570 [(set (match_operand:SI 0 "register_operand" "")
571 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
572 ""
573 "
574 {
575 if (optimize && GET_CODE (operands[1]) == MEM)
576 operands[1] = force_not_mem (operands[1]);
578 if (GET_CODE (operands[1]) != MEM)
579 {
580 rtx op1 = gen_lowpart (SImode, operands[1]);
581 rtx temp = gen_reg_rtx (SImode);
582 rtx shift = GEN_INT (24);
584 emit_insn (gen_ashlsi3 (temp, op1, shift));
585 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
586 DONE;
587 }
588 }")
590 (define_insn "extendqisi2_insn"
591 [(set (match_operand:SI 0 "register_operand" "=d,d")
592 (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
593 ""
594 "* return iq2000_move_1word (operands, insn, FALSE);"
595 [(set_attr "type" "load")
596 (set_attr "mode" "SI")
597 (set_attr "length" "4,8")])
598 \f
599 ;;
600 ;; ........................
601 ;;
602 ;; BIT FIELD EXTRACTION
603 ;;
604 ;; ........................
606 (define_insn "extzv"
607 [(set (match_operand:SI 0 "register_operand" "=r")
608 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
609 (match_operand:SI 2 "const_int_operand" "O")
610 (match_operand:SI 3 "const_int_operand" "O")))]
611 ""
612 "*
613 {
614 int value[4];
615 value[2] = INTVAL (operands[2]);
616 value[3] = INTVAL (operands[3]);
617 operands[2] = GEN_INT ((value[3]));
618 operands[3] = GEN_INT ((32 - value[2]));
619 return \"ram\\t%0,%1,%2,%3,0x0\";
620 }"
621 [(set_attr "type" "arith")])
622 \f
623 ;;
624 ;; ....................
625 ;;
626 ;; DATA MOVEMENT
627 ;;
628 ;; ....................
630 /* Take care of constants that don't fit in single instruction */
631 (define_split
632 [(set (match_operand:SI 0 "register_operand" "")
633 (match_operand:SI 1 "general_operand" ""))]
634 "(reload_in_progress || reload_completed)
635 && large_int (operands[1], SImode)"
637 [(set (match_dup 0 )
638 (high:SI (match_dup 1)))
639 (set (match_dup 0 )
640 (lo_sum:SI (match_dup 0)
641 (match_dup 1)))]
642 )
644 ;; ??? iq2000_move_1word has support for HIGH, so this pattern may be
645 ;; unnecessary.
647 (define_insn "high"
648 [(set (match_operand:SI 0 "register_operand" "=r")
649 (high:SI (match_operand:SI 1 "immediate_operand" "")))]
650 ""
651 "lui\\t%0,%%hi(%1) # high"
652 [(set_attr "type" "move")])
654 (define_insn "low"
655 [(set (match_operand:SI 0 "register_operand" "=r")
656 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
657 (match_operand:SI 2 "immediate_operand" "")))]
658 ""
659 "addiu\\t%0,%1,%%lo(%2) # low"
660 [(set_attr "type" "arith")
661 (set_attr "mode" "SI")])
663 ;; 32-bit Integer moves
665 (define_split
666 [(set (match_operand:SI 0 "register_operand" "")
667 (match_operand:SI 1 "large_int" ""))]
668 "reload_in_progress | reload_completed"
669 [(set (match_dup 0)
670 (match_dup 2))
671 (set (match_dup 0)
672 (ior:SI (match_dup 0)
673 (match_dup 3)))]
674 "
675 {
676 operands[2] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1])
677 & BITMASK_UPPER16,
678 SImode));
679 operands[3] = GEN_INT (INTVAL (operands[1]) & BITMASK_LOWER16);
680 }")
682 ;; Unlike most other insns, the move insns can't be split with
683 ;; different predicates, because register spilling and other parts of
684 ;; the compiler, have memoized the insn number already.
686 (define_expand "movsi"
687 [(set (match_operand:SI 0 "nonimmediate_operand" "")
688 (match_operand:SI 1 "general_operand" ""))]
689 ""
690 "
691 {
692 if (iq2000_check_split (operands[1], SImode))
693 {
694 machine_mode mode = GET_MODE (operands[0]);
695 rtx tem = ((reload_in_progress | reload_completed)
696 ? operands[0] : gen_reg_rtx (mode));
698 emit_insn (gen_rtx_SET (tem, gen_rtx_HIGH (mode, operands[1])));
700 operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]);
701 }
703 if ((reload_in_progress | reload_completed) == 0
704 && !register_operand (operands[0], SImode)
705 && !register_operand (operands[1], SImode)
706 && (GET_CODE (operands[1]) != CONST_INT
707 || INTVAL (operands[1]) != 0))
708 {
709 rtx temp = force_reg (SImode, operands[1]);
710 emit_move_insn (operands[0], temp);
711 DONE;
712 }
714 /* Take care of constants that don't fit in single instruction */
715 if ((reload_in_progress || reload_completed)
716 && CONSTANT_P (operands[1])
717 && GET_CODE (operands[1]) != HIGH
718 && GET_CODE (operands[1]) != LO_SUM
719 && ! SMALL_INT_UNSIGNED (operands[1]))
720 {
721 rtx tem = ((reload_in_progress | reload_completed)
722 ? operands[0] : gen_reg_rtx (SImode));
724 emit_insn (gen_rtx_SET (tem, gen_rtx_HIGH (SImode, operands[1])));
725 operands[1] = gen_rtx_LO_SUM (SImode, tem, operands[1]);
726 }
727 }")
729 ;; The difference between these two is whether or not ints are allowed
730 ;; in FP registers (off by default, use -mdebugh to enable).
732 (define_insn "movsi_internal2"
733 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,R,m")
734 (match_operand:SI 1 "move_operand" "d,IKL,Mnis,R,m,dJ,dJ"))]
735 "(register_operand (operands[0], SImode)
736 || register_operand (operands[1], SImode)
737 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
738 "* return iq2000_move_1word (operands, insn, FALSE);"
739 [(set_attr "type" "move,arith,arith,load,load,store,store")
740 (set_attr "mode" "SI")
741 (set_attr "length" "4,4,8,8,8,4,8")])
743 ;; 16-bit Integer moves
745 ;; Unlike most other insns, the move insns can't be split with
746 ;; different predicates, because register spilling and other parts of
747 ;; the compiler, have memoized the insn number already.
748 ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
750 (define_expand "movhi"
751 [(set (match_operand:HI 0 "nonimmediate_operand" "")
752 (match_operand:HI 1 "general_operand" ""))]
753 ""
754 "
755 {
756 if ((reload_in_progress | reload_completed) == 0
757 && !register_operand (operands[0], HImode)
758 && !register_operand (operands[1], HImode)
759 && ((GET_CODE (operands[1]) != CONST_INT
760 || INTVAL (operands[1]) != 0)))
761 {
762 rtx temp = force_reg (HImode, operands[1]);
763 emit_move_insn (operands[0], temp);
764 DONE;
765 }
766 }")
768 ;; The difference between these two is whether or not ints are allowed
769 ;; in FP registers (off by default, use -mdebugh to enable).
771 (define_insn "movhi_internal2"
772 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m")
773 (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ"))]
774 "(register_operand (operands[0], HImode)
775 || register_operand (operands[1], HImode)
776 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
777 "* return iq2000_move_1word (operands, insn, TRUE);"
778 [(set_attr "type" "move,arith,load,load,store,store")
779 (set_attr "mode" "HI")
780 (set_attr "length" "4,4,4,8,4,8")])
782 ;; 8-bit Integer moves
784 ;; Unlike most other insns, the move insns can't be split with
785 ;; different predicates, because register spilling and other parts of
786 ;; the compiler, have memoized the insn number already.
787 ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
789 (define_expand "movqi"
790 [(set (match_operand:QI 0 "nonimmediate_operand" "")
791 (match_operand:QI 1 "general_operand" ""))]
792 ""
793 "
794 {
795 if ((reload_in_progress | reload_completed) == 0
796 && !register_operand (operands[0], QImode)
797 && !register_operand (operands[1], QImode)
798 && (GET_CODE (operands[1]) != CONST_INT
799 || INTVAL (operands[1]) != 0))
800 {
801 rtx temp = force_reg (QImode, operands[1]);
802 emit_move_insn (operands[0], temp);
803 DONE;
804 }
805 }")
807 ;; The difference between these two is whether or not ints are allowed
808 ;; in FP registers (off by default, use -mdebugh to enable).
810 (define_insn "movqi_internal2"
811 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m")
812 (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ"))]
813 "(register_operand (operands[0], QImode)
814 || register_operand (operands[1], QImode)
815 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
816 "* return iq2000_move_1word (operands, insn, TRUE);"
817 [(set_attr "type" "move,arith,load,load,store,store")
818 (set_attr "mode" "QI")
819 (set_attr "length" "4,4,4,8,4,8")])
821 ;; 32-bit floating point moves
823 (define_expand "movsf"
824 [(set (match_operand:SF 0 "general_operand" "")
825 (match_operand:SF 1 "general_operand" ""))]
826 ""
827 "
828 {
829 if (!reload_in_progress
830 && !reload_completed
831 && GET_CODE (operands[0]) == MEM
832 && (GET_CODE (operands[1]) == MEM
833 || GET_CODE (operands[1]) == CONST_DOUBLE))
834 operands[1] = copy_to_mode_reg (SFmode, operands[1]);
836 /* Take care of reg <- SF constant */
837 if ( const_double_operand (operands[1], GET_MODE (operands[1]) ) )
838 {
839 emit_insn (gen_movsf_high (operands[0], operands[1]));
840 emit_insn (gen_movsf_lo_sum (operands[0], operands[0], operands[1]));
841 DONE;
842 }
843 }")
845 (define_insn "movsf_lo_sum"
846 [(set (match_operand:SF 0 "register_operand" "=r")
847 (lo_sum:SF (match_operand:SF 1 "register_operand" "r")
848 (match_operand:SF 2 "const_double_operand" "")))]
849 ""
850 "*
851 {
852 REAL_VALUE_TYPE r;
853 long i;
855 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]);
856 REAL_VALUE_TO_TARGET_SINGLE (r, i);
857 operands[2] = GEN_INT (i);
858 return \"addiu\\t%0,%1,%%lo(%2) # low\";
859 }"
860 [(set_attr "length" "4")
861 (set_attr "type" "arith")])
863 (define_insn "movsf_high"
864 [(set (match_operand:SF 0 "register_operand" "=r")
865 (high:SF (match_operand:SF 1 "const_double_operand" "")))]
866 ""
867 "*
868 {
869 REAL_VALUE_TYPE r;
870 long i;
872 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
873 REAL_VALUE_TO_TARGET_SINGLE (r, i);
874 operands[1] = GEN_INT (i);
875 return \"lui\\t%0,%%hi(%1) # high\";
876 }"
877 [(set_attr "length" "4")
878 (set_attr "type" "arith")])
880 (define_insn "*movsf_internal"
881 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
882 (match_operand:SF 1 "nonimmediate_operand" "r,m,r"))]
883 "!memory_operand (operands[0], SFmode) || !memory_operand (operands[1], SFmode)"
884 "*
885 {
886 iq2000_fill_delay_slot (\"\", DELAY_LOAD, operands, insn);
887 if (which_alternative == 0)
888 return \"or\\t%0,%1,%1\";
889 else if (which_alternative == 1)
890 return \"lw\\t%0,%1\";
891 else if (which_alternative == 2)
892 return \"sw\\t%1,%0\";
893 else
894 gcc_unreachable ();
895 }"
896 [(set_attr "length" "4,4,4")
897 (set_attr "type" "arith,load,store")]
898 )
899 \f
900 ;;
901 ;; ....................
902 ;;
903 ;; SHIFTS
904 ;;
905 ;; ....................
907 (define_expand "ashlsi3"
908 [(set (match_operand:SI 0 "register_operand" "=d")
909 (ashift:SI (match_operand:SI 1 "register_operand" "d")
910 (match_operand:SI 2 "arith_operand" "dI")))]
911 ""
912 "")
914 (define_insn "ashlsi3_internal1"
915 [(set (match_operand:SI 0 "register_operand" "=d")
916 (ashift:SI (match_operand:SI 1 "register_operand" "d")
917 (match_operand:SI 2 "arith_operand" "dI")))]
918 ""
919 "*
920 {
921 if (GET_CODE (operands[2]) == CONST_INT)
922 {
923 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
924 return \"sll\\t%0,%1,%2\";
925 }
926 else
927 return \"sllv\\t%0,%1,%2\";
928 }"
929 [(set_attr "type" "arith")
930 (set_attr "mode" "SI")])
932 (define_expand "ashrsi3"
933 [(set (match_operand:SI 0 "register_operand" "=d")
934 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
935 (match_operand:SI 2 "arith_operand" "dI")))]
936 ""
937 "")
939 (define_insn "ashrsi3_internal1"
940 [(set (match_operand:SI 0 "register_operand" "=d")
941 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
942 (match_operand:SI 2 "arith_operand" "dI")))]
943 ""
944 "*
945 {
946 if (GET_CODE (operands[2]) == CONST_INT)
947 {
948 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
949 return \"sra\\t%0,%1,%2\";
950 }
951 else
952 return \"srav\\t%0,%1,%2\";
953 }"
954 [(set_attr "type" "arith")
955 (set_attr "mode" "SI")])
957 (define_expand "lshrsi3"
958 [(set (match_operand:SI 0 "register_operand" "=d")
959 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
960 (match_operand:SI 2 "arith_operand" "dI")))]
961 ""
962 "")
964 (define_insn "lshrsi3_internal1"
965 [(set (match_operand:SI 0 "register_operand" "=d")
966 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
967 (match_operand:SI 2 "arith_operand" "dI")))]
968 ""
969 "*
970 {
971 if (GET_CODE (operands[2]) == CONST_INT)
972 {
973 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
974 return \"srl\\t%0,%1,%2\";
975 }
976 else
977 return \"srlv\\t%0,%1,%2\";
978 }"
979 [(set_attr "type" "arith")
980 (set_attr "mode" "SI")])
982 ;; Rotate Right
983 (define_insn "rotrsi3"
984 [(set (match_operand:SI 0 "register_operand" "=r")
985 (rotatert:SI (match_operand:SI 1 "register_operand" "r")
986 (match_operand:SI 2 "uns_arith_operand" "O")))]
987 ""
988 "ram %0,%1,%2,0x0,0x0"
989 [(set_attr "type" "arith")])
991 \f
992 ;;
993 ;; ....................
994 ;;
995 ;; CONDITIONAL BRANCHES
996 ;;
997 ;; ....................
999 (define_expand "cbranchsi4"
1000 [(set (pc)
1001 (if_then_else
1002 (match_operator 0 "ordered_comparison_operator"
1003 [(match_operand:SI 1 "register_operand")
1004 (match_operand:SI 2 "reg_or_const_operand")])
1005 (label_ref (match_operand 3 ""))
1006 (pc)))]
1007 ""
1008 "
1009 {
1010 gen_conditional_branch (operands, SImode);
1011 DONE;
1012 }")
1015 ;; Conditional branches on comparisons with zero.
1017 (define_insn "branch_zero"
1018 [(set (pc)
1019 (if_then_else
1020 (match_operator 0 "cmp_op"
1021 [(match_operand:SI 2 "register_operand" "d")
1022 (const_int 0)])
1023 (label_ref (match_operand 1 "" ""))
1024 (pc)))]
1025 ""
1026 "*
1027 {
1028 return iq2000_output_conditional_branch (insn,
1029 operands,
1030 /*two_operands_p=*/0,
1031 /*float_p=*/0,
1032 /*inverted_p=*/0,
1033 get_attr_length (insn));
1034 }"
1035 [(set_attr "type" "branch")
1036 (set_attr "mode" "none")])
1038 (define_insn "branch_zero_inverted"
1039 [(set (pc)
1040 (if_then_else
1041 (match_operator 0 "cmp_op"
1042 [(match_operand:SI 2 "register_operand" "d")
1043 (const_int 0)])
1044 (pc)
1045 (label_ref (match_operand 1 "" ""))))]
1046 ""
1047 "*
1048 {
1049 return iq2000_output_conditional_branch (insn,
1050 operands,
1051 /*two_operands_p=*/0,
1052 /*float_p=*/0,
1053 /*inverted_p=*/1,
1054 get_attr_length (insn));
1055 }"
1056 [(set_attr "type" "branch")
1057 (set_attr "mode" "none")])
1059 ;; Conditional branch on equality comparison.
1061 (define_insn "branch_equality"
1062 [(set (pc)
1063 (if_then_else
1064 (match_operator 0 "equality_op"
1065 [(match_operand:SI 2 "register_operand" "d")
1066 (match_operand:SI 3 "register_operand" "d")])
1067 (label_ref (match_operand 1 "" ""))
1068 (pc)))]
1069 ""
1070 "*
1071 {
1072 return iq2000_output_conditional_branch (insn,
1073 operands,
1074 /*two_operands_p=*/1,
1075 /*float_p=*/0,
1076 /*inverted_p=*/0,
1077 get_attr_length (insn));
1078 }"
1079 [(set_attr "type" "branch")
1080 (set_attr "mode" "none")])
1082 (define_insn "branch_equality_inverted"
1083 [(set (pc)
1084 (if_then_else
1085 (match_operator 0 "equality_op"
1086 [(match_operand:SI 2 "register_operand" "d")
1087 (match_operand:SI 3 "register_operand" "d")])
1088 (pc)
1089 (label_ref (match_operand 1 "" ""))))]
1090 ""
1091 "*
1092 {
1093 return iq2000_output_conditional_branch (insn,
1094 operands,
1095 /*two_operands_p=*/1,
1096 /*float_p=*/0,
1097 /*inverted_p=*/1,
1098 get_attr_length (insn));
1099 }"
1100 [(set_attr "type" "branch")
1101 (set_attr "mode" "none")])
1104 ;; Recognize bbi and bbin instructions. These use two unusual template
1105 ;; patterns, %Ax and %Px. %Ax outputs an 'i' if operand `x' is a LABEL_REF
1106 ;; otherwise it outputs an 'in'. %Px does nothing if `x' is PC
1107 ;; and outputs the operand if `x' is a LABEL_REF.
1109 (define_insn ""
1110 [(set (pc)
1111 (if_then_else
1112 (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
1113 (const_int 1)
1114 (match_operand:SI 1 "arith_operand" "I"))
1115 (const_int 0))
1116 (match_operand 2 "pc_or_label_operand" "")
1117 (match_operand 3 "pc_or_label_operand" "")))]
1118 ""
1119 "bb%A2\\t%0(31-%1),%P2%P3"
1120 [(set_attr "length" "4")
1121 (set_attr "type" "branch")])
1123 (define_insn ""
1124 [(set (pc)
1125 (if_then_else
1126 (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
1127 (const_int 1)
1128 (match_operand:SI 1 "arith_operand" "I"))
1129 (const_int 0))
1130 (match_operand 2 "pc_or_label_operand" "")
1131 (match_operand 3 "pc_or_label_operand" "")))]
1132 ""
1133 "bb%A3\\t%0(31-%1),%P2%P3"
1134 [(set_attr "length" "4")
1135 (set_attr "type" "branch")])
1137 (define_insn ""
1138 [(set (pc)
1139 (if_then_else
1140 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1141 (const_int 1)
1142 (match_operand:SI 1 "arith_operand" "I"))
1143 (const_int 0))
1144 (match_operand 2 "pc_or_label_operand" "")
1145 (match_operand 3 "pc_or_label_operand" "")))]
1146 "0"
1147 "bb%A2\\t%0(31-%1),%P2%P3"
1148 [(set_attr "length" "4")
1149 (set_attr "type" "branch")])
1151 (define_insn ""
1152 [(set (pc)
1153 (if_then_else
1154 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1155 (const_int 1)
1156 (match_operand:SI 1 "arith_operand" "I"))
1157 (const_int 0))
1158 (match_operand 2 "pc_or_label_operand" "")
1159 (match_operand 3 "pc_or_label_operand" "")))]
1160 "0"
1161 "bb%A3\\t%0(31-%1),%P2%P3"
1162 [(set_attr "length" "4")
1163 (set_attr "type" "branch")])
1165 (define_insn ""
1166 [(set (pc)
1167 (if_then_else
1168 (eq (and:SI (match_operand:SI 0 "register_operand" "r")
1169 (match_operand:SI 1 "power_of_2_operand" "I"))
1170 (const_int 0))
1171 (match_operand 2 "pc_or_label_operand" "")
1172 (match_operand 3 "pc_or_label_operand" "")))]
1173 ""
1174 "bb%A3\\t%0(%p1),%P2%P3"
1175 [(set_attr "length" "4")
1176 (set_attr "type" "branch")])
1178 (define_insn ""
1179 [(set (pc)
1180 (if_then_else
1181 (ne (and:SI (match_operand:SI 0 "register_operand" "r")
1182 (match_operand:SI 1 "power_of_2_operand" "I"))
1183 (const_int 0))
1184 (match_operand 2 "pc_or_label_operand" "")
1185 (match_operand 3 "pc_or_label_operand" "")))]
1186 ""
1187 "bb%A2\\t%0(%p1),%P2%P3"
1188 [(set_attr "length" "4")
1189 (set_attr "type" "branch")])
1190 \f
1191 ;;
1192 ;; ....................
1193 ;;
1194 ;; SETTING A REGISTER FROM A COMPARISON
1195 ;;
1196 ;; ....................
1198 (define_expand "cstoresi4"
1199 [(set (match_operand:SI 0 "register_operand" "=d")
1200 (match_operator:SI 1 "ordered_comparison_operator"
1201 [(match_operand:SI 2 "register_operand")
1202 (match_operand:SI 3 "reg_or_const_operand")]))]
1203 ""
1204 "
1205 {
1206 gen_int_relational (GET_CODE (operands[1]), operands[0],
1207 operands[2], operands[3], (int *)0);
1208 DONE;
1209 }")
1211 (define_insn "seq_si_zero"
1212 [(set (match_operand:SI 0 "register_operand" "=d")
1213 (eq:SI (match_operand:SI 1 "register_operand" "d")
1214 (const_int 0)))]
1215 ""
1216 "sltiu\\t%0,%1,1"
1217 [(set_attr "type" "arith")
1218 (set_attr "mode" "SI")])
1220 (define_insn "sne_si_zero"
1221 [(set (match_operand:SI 0 "register_operand" "=d")
1222 (ne:SI (match_operand:SI 1 "register_operand" "d")
1223 (const_int 0)))]
1224 ""
1225 "sltu\\t%0,%.,%1"
1226 [(set_attr "type" "arith")
1227 (set_attr "mode" "SI")])
1229 (define_insn "sgt_si"
1230 [(set (match_operand:SI 0 "register_operand" "=d,d")
1231 (gt:SI (match_operand:SI 1 "register_operand" "d,d")
1232 (match_operand:SI 2 "reg_or_0_operand" "d,J")))]
1233 ""
1234 "@
1235 slt\\t%0,%z2,%1
1236 slt\\t%0,%z2,%1"
1237 [(set_attr "type" "arith,arith")
1238 (set_attr "mode" "SI,SI")])
1240 (define_insn "slt_si"
1241 [(set (match_operand:SI 0 "register_operand" "=d,d")
1242 (lt:SI (match_operand:SI 1 "register_operand" "d,d")
1243 (match_operand:SI 2 "arith_operand" "d,I")))]
1244 ""
1245 "@
1246 slt\\t%0,%1,%2
1247 slti\\t%0,%1,%2"
1248 [(set_attr "type" "arith,arith")
1249 (set_attr "mode" "SI,SI")])
1251 (define_insn "sle_si_const"
1252 [(set (match_operand:SI 0 "register_operand" "=d")
1253 (le:SI (match_operand:SI 1 "register_operand" "d")
1254 (match_operand:SI 2 "small_int" "I")))]
1255 "INTVAL (operands[2]) < 32767"
1256 "*
1257 {
1258 operands[2] = GEN_INT (INTVAL (operands[2])+1);
1259 return \"slti\\t%0,%1,%2\";
1260 }"
1261 [(set_attr "type" "arith")
1262 (set_attr "mode" "SI")])
1264 (define_insn "sgtu_si"
1265 [(set (match_operand:SI 0 "register_operand" "=d")
1266 (gtu:SI (match_operand:SI 1 "register_operand" "d")
1267 (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
1268 ""
1269 "sltu\\t%0,%z2,%1"
1270 [(set_attr "type" "arith")
1271 (set_attr "mode" "SI")])
1273 (define_insn "sltu_si"
1274 [(set (match_operand:SI 0 "register_operand" "=d,d")
1275 (ltu:SI (match_operand:SI 1 "register_operand" "d,d")
1276 (match_operand:SI 2 "arith_operand" "d,I")))]
1277 ""
1278 "@
1279 sltu\\t%0,%1,%2
1280 sltiu\\t%0,%1,%2"
1281 [(set_attr "type" "arith,arith")
1282 (set_attr "mode" "SI,SI")])
1284 (define_insn "sleu_si_const"
1285 [(set (match_operand:SI 0 "register_operand" "=d")
1286 (leu:SI (match_operand:SI 1 "register_operand" "d")
1287 (match_operand:SI 2 "small_int" "I")))]
1288 "INTVAL (operands[2]) < 32767"
1289 "*
1290 {
1291 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
1292 return \"sltiu\\t%0,%1,%2\";
1293 }"
1294 [(set_attr "type" "arith")
1295 (set_attr "mode" "SI")])
1297 \f
1298 ;;
1299 ;; ....................
1300 ;;
1301 ;; UNCONDITIONAL BRANCHES
1302 ;;
1303 ;; ....................
1305 ;; Unconditional branches.
1307 (define_insn "jump"
1308 [(set (pc)
1309 (label_ref (match_operand 0 "" "")))]
1310 ""
1311 "*
1312 {
1313 if (GET_CODE (operands[0]) == REG)
1314 return \"j\\t%0\";
1315 return \"j\\t%l0\";
1316 /* return \"b\\t%l0\";*/
1317 }"
1318 [(set_attr "type" "jump")
1319 (set_attr "mode" "none")])
1321 (define_expand "indirect_jump"
1322 [(set (pc) (match_operand 0 "register_operand" "d"))]
1323 ""
1324 "
1325 {
1326 rtx dest;
1328 if (operands[0]) /* eliminate unused code warnings */
1329 {
1330 dest = operands[0];
1331 if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
1332 operands[0] = copy_to_mode_reg (Pmode, dest);
1334 if (!(Pmode == DImode))
1335 emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
1336 else
1337 internal_error (\"unimplemented functionality\");
1339 DONE;
1340 }
1341 }")
1343 (define_insn "indirect_jump_internal1"
1344 [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
1345 "!(Pmode == DImode)"
1346 "j\\t%0"
1347 [(set_attr "type" "jump")
1348 (set_attr "mode" "none")])
1350 (define_expand "tablejump"
1351 [(set (pc)
1352 (match_operand 0 "register_operand" "d"))
1353 (use (label_ref (match_operand 1 "" "")))]
1354 ""
1355 "
1356 {
1357 if (operands[0]) /* eliminate unused code warnings */
1358 {
1359 gcc_assert (GET_MODE (operands[0]) == Pmode);
1361 if (!(Pmode == DImode))
1362 emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
1363 else
1364 internal_error (\"unimplemented functionality\");
1366 DONE;
1367 }
1368 }")
1370 (define_insn "tablejump_internal1"
1371 [(set (pc)
1372 (match_operand:SI 0 "register_operand" "d"))
1373 (use (label_ref (match_operand 1 "" "")))]
1374 "!(Pmode == DImode)"
1375 "j\\t%0"
1376 [(set_attr "type" "jump")
1377 (set_attr "mode" "none")])
1379 (define_expand "tablejump_internal3"
1380 [(parallel [(set (pc)
1381 (plus:SI (match_operand:SI 0 "register_operand" "d")
1382 (label_ref:SI (match_operand 1 "" ""))))
1383 (use (label_ref:SI (match_dup 1)))])]
1384 ""
1385 "")
1387 ;;; Make sure that this only matches the insn before ADDR_DIFF_VEC. Otherwise
1388 ;;; it is not valid. ??? With the USE, the condition tests may not be required
1389 ;;; any longer.
1391 ;;; ??? The length depends on the ABI. It is two for o32, and one for n32.
1392 ;;; We just use the conservative number here.
1394 (define_insn ""
1395 [(set (pc)
1396 (plus:SI (match_operand:SI 0 "register_operand" "d")
1397 (label_ref:SI (match_operand 1 "" ""))))
1398 (use (label_ref:SI (match_dup 1)))]
1399 "!(Pmode == DImode) && NEXT_INSN (as_a <rtx_insn *> (operands[1])) != 0
1400 && GET_CODE (PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[1])))) == ADDR_DIFF_VEC"
1401 "*
1402 {
1403 return \"j\\t%0\";
1404 }"
1405 [(set_attr "type" "jump")
1406 (set_attr "mode" "none")
1407 (set_attr "length" "8")])
1408 \f
1409 ;;
1410 ;; ....................
1411 ;;
1412 ;; Function prologue/epilogue
1413 ;;
1414 ;; ....................
1415 ;;
1417 (define_expand "prologue"
1418 [(const_int 1)]
1419 ""
1420 "
1421 {
1422 if (iq2000_isa >= 0) /* avoid unused code warnings */
1423 {
1424 iq2000_expand_prologue ();
1425 DONE;
1426 }
1427 }")
1429 ;; Block any insns from being moved before this point, since the
1430 ;; profiling call to mcount can use various registers that aren't
1431 ;; saved or used to pass arguments.
1433 (define_insn "blockage"
1434 [(unspec_volatile [(const_int 0)] 0)]
1435 ""
1436 ""
1437 [(set_attr "type" "unknown")
1438 (set_attr "mode" "none")
1439 (set_attr "length" "0")])
1441 (define_expand "epilogue"
1442 [(const_int 2)]
1443 ""
1444 "
1445 {
1446 if (iq2000_isa >= 0) /* avoid unused code warnings */
1447 {
1448 iq2000_expand_epilogue ();
1449 DONE;
1450 }
1451 }")
1453 ;; Trivial return. Make it look like a normal return insn as that
1454 ;; allows jump optimizations to work better .
1455 (define_insn "return"
1456 [(return)]
1457 "iq2000_can_use_return_insn ()"
1458 "j\\t%%31"
1459 [(set_attr "type" "jump")
1460 (set_attr "mode" "none")])
1462 ;; Normal return.
1464 (define_insn "return_internal"
1465 [(use (match_operand 0 "pmode_register_operand" ""))
1466 (return)]
1467 ""
1468 "*
1469 {
1470 return \"j\\t%0\";
1471 }"
1472 [(set_attr "type" "jump")
1473 (set_attr "mode" "none")])
1475 (define_insn "eh_return_internal"
1476 [(const_int 4)
1477 (return)
1478 (use (reg:SI 26))
1479 (use (reg:SI 31))]
1480 ""
1481 "j\\t%%26"
1482 [(set_attr "type" "jump")
1483 (set_attr "mode" "none")])
1485 (define_expand "eh_return"
1486 [(use (match_operand:SI 0 "register_operand" "r"))]
1487 ""
1488 "
1489 {
1490 iq2000_expand_eh_return (operands[0]);
1491 DONE;
1492 }")
1494 \f
1495 ;;
1496 ;; ....................
1497 ;;
1498 ;; FUNCTION CALLS
1499 ;;
1500 ;; ....................
1502 ;; calls.c now passes a third argument, make saber happy
1504 (define_expand "call"
1505 [(parallel [(call (match_operand 0 "memory_operand" "m")
1506 (match_operand 1 "" "i"))
1507 (clobber (reg:SI 31))
1508 (use (match_operand 2 "" "")) ;; next_arg_reg
1509 (use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
1510 ""
1511 "
1512 {
1513 rtx addr;
1515 if (operands[0]) /* eliminate unused code warnings */
1516 {
1517 addr = XEXP (operands[0], 0);
1518 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr)))
1519 || ! call_insn_operand (addr, VOIDmode))
1520 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
1522 /* In order to pass small structures by value in registers
1523 compatibly with the IQ2000 compiler, we need to shift the value
1524 into the high part of the register. Function_arg has encoded
1525 a PARALLEL rtx, holding a vector of adjustments to be made
1526 as the next_arg_reg variable, so we split up the insns,
1527 and emit them separately. */
1529 if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL)
1530 {
1531 rtvec adjust = XVEC (operands[2], 0);
1532 int num = GET_NUM_ELEM (adjust);
1533 int i;
1535 for (i = 0; i < num; i++)
1536 emit_insn (RTVEC_ELT (adjust, i));
1537 }
1539 emit_call_insn (gen_call_internal0 (operands[0], operands[1],
1540 gen_rtx_REG (SImode,
1541 GP_REG_FIRST + 31)));
1542 DONE;
1543 }
1544 }")
1546 (define_expand "call_internal0"
1547 [(parallel [(call (match_operand 0 "" "")
1548 (match_operand 1 "" ""))
1549 (clobber (match_operand:SI 2 "" ""))])]
1550 ""
1551 "")
1553 (define_insn "call_internal1"
1554 [(call (mem (match_operand 0 "call_insn_operand" "ri"))
1555 (match_operand 1 "" "i"))
1556 (clobber (match_operand:SI 2 "register_operand" "=d"))]
1557 ""
1558 "*
1559 {
1560 register rtx target = operands[0];
1562 if (GET_CODE (target) == CONST_INT)
1563 return \"li\\t%@,%0\\n\\tjalr\\t%2,%@\";
1564 else if (CONSTANT_ADDRESS_P (target))
1565 return \"jal\\t%0\";
1566 else
1567 return \"jalr\\t%2,%0\";
1568 }"
1569 [(set_attr "type" "call")
1570 (set_attr "mode" "none")])
1572 ;; calls.c now passes a fourth argument, make saber happy
1574 (define_expand "call_value"
1575 [(parallel [(set (match_operand 0 "register_operand" "=d")
1576 (call (match_operand 1 "memory_operand" "m")
1577 (match_operand 2 "" "i")))
1578 (clobber (reg:SI 31))
1579 (use (match_operand 3 "" ""))])] ;; next_arg_reg
1580 ""
1581 "
1582 {
1583 rtx addr;
1585 if (operands[0]) /* eliminate unused code warning */
1586 {
1587 addr = XEXP (operands[1], 0);
1588 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr)))
1589 || ! call_insn_operand (addr, VOIDmode))
1590 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
1592 /* In order to pass small structures by value in registers
1593 compatibly with the IQ2000 compiler, we need to shift the value
1594 into the high part of the register. Function_arg has encoded
1595 a PARALLEL rtx, holding a vector of adjustments to be made
1596 as the next_arg_reg variable, so we split up the insns,
1597 and emit them separately. */
1599 if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL)
1600 {
1601 rtvec adjust = XVEC (operands[3], 0);
1602 int num = GET_NUM_ELEM (adjust);
1603 int i;
1605 for (i = 0; i < num; i++)
1606 emit_insn (RTVEC_ELT (adjust, i));
1607 }
1609 if (GET_CODE (operands[0]) == PARALLEL && XVECLEN (operands[0], 0) > 1)
1610 {
1611 emit_call_insn (gen_call_value_multiple_internal0
1612 (XEXP (XVECEXP (operands[0], 0, 0), 0),
1613 operands[1], operands[2],
1614 XEXP (XVECEXP (operands[0], 0, 1), 0),
1615 gen_rtx_REG (SImode, GP_REG_FIRST + 31)));
1616 DONE;
1617 }
1619 /* We have a call returning a DImode structure in an FP reg.
1620 Strip off the now unnecessary PARALLEL. */
1621 if (GET_CODE (operands[0]) == PARALLEL)
1622 operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0);
1624 emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2],
1625 gen_rtx_REG (SImode,
1626 GP_REG_FIRST + 31)));
1628 DONE;
1629 }
1630 }")
1632 (define_expand "call_value_internal0"
1633 [(parallel [(set (match_operand 0 "" "")
1634 (call (match_operand 1 "" "")
1635 (match_operand 2 "" "")))
1636 (clobber (match_operand:SI 3 "" ""))])]
1637 ""
1638 "")
1640 (define_insn "call_value_internal1"
1641 [(set (match_operand 0 "register_operand" "=d")
1642 (call (mem (match_operand 1 "call_insn_operand" "r"))
1643 (match_operand 2 "" "i")))
1644 (clobber (match_operand:SI 3 "register_operand" "=d"))]
1645 ""
1646 "*
1647 {
1648 register rtx target = operands[1];
1650 if (GET_CODE (target) == CONST_INT)
1651 return \"li\\t%@,%1\\n\\tjalr\\t%3,%@\";
1652 else if (CONSTANT_ADDRESS_P (target))
1653 return \"jal\\t%1\";
1654 else
1655 return \"jalr\\t%3,%1\";
1656 }"
1657 [(set_attr "type" "call")
1658 (set_attr "mode" "none")])
1660 (define_expand "call_value_multiple_internal0"
1661 [(parallel [(set (match_operand 0 "" "")
1662 (call (match_operand 1 "" "")
1663 (match_operand 2 "" "")))
1664 (set (match_operand 3 "" "")
1665 (call (match_dup 1)
1666 (match_dup 2)))
1667 (clobber (match_operand:SI 4 "" ""))])]
1668 ""
1669 "")
1671 ;; ??? May eventually need all 6 versions of the call patterns with multiple
1672 ;; return values.
1674 (define_insn "call_value_multiple_internal1"
1675 [(set (match_operand 0 "register_operand" "=d")
1676 (call (mem (match_operand 1 "call_insn_operand" "r"))
1677 (match_operand 2 "" "i")))
1678 (set (match_operand 3 "register_operand" "=d")
1679 (call (mem (match_dup 1))
1680 (match_dup 2)))
1681 (clobber (match_operand:SI 4 "register_operand" "=d"))]
1682 ""
1683 "*
1684 {
1685 register rtx target = operands[1];
1687 if (GET_CODE (target) == CONST_INT)
1688 return \"li\\t%@,%1\\n\\tjalr\\t%4,%@\";
1689 else if (CONSTANT_ADDRESS_P (target))
1690 return \"jal\\t%1\";
1691 else
1692 return \"jalr\\t%4,%1\";
1693 }"
1694 [(set_attr "type" "call")
1695 (set_attr "mode" "none")])
1697 ;; Call subroutine returning any type.
1699 (define_expand "untyped_call"
1700 [(parallel [(call (match_operand 0 "" "")
1701 (const_int 0))
1702 (match_operand 1 "" "")
1703 (match_operand 2 "" "")])]
1704 ""
1705 "
1706 {
1707 if (operands[0]) /* silence statement not reached warnings */
1708 {
1709 int i;
1711 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
1713 for (i = 0; i < XVECLEN (operands[2], 0); i++)
1714 {
1715 rtx set = XVECEXP (operands[2], 0, i);
1716 emit_move_insn (SET_DEST (set), SET_SRC (set));
1717 }
1719 emit_insn (gen_blockage ());
1720 DONE;
1721 }
1722 }")
1723 \f
1724 ;;
1725 ;; ....................
1726 ;;
1727 ;; MISC.
1728 ;;
1729 ;; ....................
1730 ;;
1732 (define_insn "nop"
1733 [(const_int 0)]
1734 ""
1735 "nop"
1736 [(set_attr "type" "nop")
1737 (set_attr "mode" "none")])
1739 \f
1740 ;; For the rare case where we need to load an address into a register
1741 ;; that cannot be recognized by the normal movsi/addsi instructions.
1742 ;; I have no idea how many insns this can actually generate. It should
1743 ;; be rare, so over-estimating as 10 instructions should not have any
1744 ;; real performance impact.
1745 (define_insn "leasi"
1746 [(set (match_operand:SI 0 "register_operand" "=d")
1747 (match_operand:SI 1 "address_operand" "p"))]
1748 "Pmode == SImode"
1749 "*
1750 {
1751 rtx xoperands [3];
1753 xoperands[0] = operands[0];
1754 xoperands[1] = XEXP (operands[1], 0);
1755 xoperands[2] = XEXP (operands[1], 1);
1756 output_asm_insn (\"addiu\\t%0,%1,%2\", xoperands);
1757 return \"\";
1758 }"
1759 [(set_attr "type" "arith")
1760 (set_attr "mode" "SI")
1761 (set_attr "length" "40")])
1763 (define_insn "ado16"
1764 [(set (match_operand:SI 0 "register_operand" "=r")
1765 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1766 (match_operand:SI 2 "register_operand" "r")]
1767 UNSPEC_ADO16))]
1768 ""
1769 "ado16\\t%0, %1, %2"
1770 )
1772 (define_insn "ram"
1773 [(set (match_operand:SI 0 "register_operand" "=r")
1774 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1775 (match_operand:SI 2 "const_int_operand" "I")
1776 (match_operand:SI 3 "const_int_operand" "I")
1777 (match_operand:SI 4 "const_int_operand" "I")]
1778 UNSPEC_RAM))]
1779 ""
1780 "ram\\t%0, %1, %2, %3, %4"
1781 )
1783 (define_insn "chkhdr"
1784 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "=r")
1785 (match_operand:SI 1 "register_operand" "r")]
1786 UNSPEC_CHKHDR)]
1787 ""
1788 "* return iq2000_fill_delay_slot (\"chkhdr\\t%0, %1\", DELAY_LOAD, operands, insn);"
1789 [(set_attr "dslot" "not_in_dslot")]
1790 )
1792 (define_insn "pkrl"
1793 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1794 (match_operand:SI 1 "register_operand" "r")]
1795 UNSPEC_PKRL)]
1796 ""
1797 "* return iq2000_fill_delay_slot (\"pkrl\\t%0, %1\", DELAY_NONE, operands, insn);"
1798 [(set_attr "dslot" "not_in_dslot")]
1799 )
1801 (define_insn "cfc0"
1802 [(set (match_operand:SI 0 "register_operand" "=r")
1803 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1804 UNSPEC_CFC0))]
1805 ""
1806 "* return iq2000_fill_delay_slot (\"cfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1807 [(set_attr "dslot" "ok_in_dslot")]
1808 )
1810 (define_insn "cfc1"
1811 [(set (match_operand:SI 0 "register_operand" "=r")
1812 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1813 UNSPEC_CFC1))]
1814 ""
1815 "* return iq2000_fill_delay_slot (\"cfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1816 [(set_attr "dslot" "ok_in_dslot")]
1817 )
1819 (define_insn "cfc2"
1820 [(set (match_operand:SI 0 "register_operand" "=r")
1821 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1822 UNSPEC_CFC2))]
1823 ""
1824 "* return iq2000_fill_delay_slot (\"cfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1825 [(set_attr "dslot" "not_in_dslot")]
1826 )
1828 (define_insn "cfc3"
1829 [(set (match_operand:SI 0 "register_operand" "=r")
1830 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1831 UNSPEC_CFC3))]
1832 ""
1833 "* return iq2000_fill_delay_slot (\"cfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1834 [(set_attr "dslot" "not_in_dslot")]
1835 )
1837 (define_insn "ctc0"
1838 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
1839 (match_operand:SI 1 "const_int_operand" "I")]
1840 UNSPEC_CTC0)]
1841 ""
1842 "* return iq2000_fill_delay_slot (\"ctc0\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
1843 [(set_attr "dslot" "ok_in_dslot")]
1844 )
1846 (define_insn "ctc1"
1847 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
1848 (match_operand:SI 1 "const_int_operand" "I")]
1849 UNSPEC_CTC1)]
1850 ""
1851 "* return iq2000_fill_delay_slot (\"ctc1\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
1852 [(set_attr "dslot" "ok_in_dslot")]
1853 )
1855 (define_insn "ctc2"
1856 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
1857 (match_operand:SI 1 "const_int_operand" "I")]
1858 UNSPEC_CTC2)]
1859 ""
1860 "* return iq2000_fill_delay_slot (\"ctc2\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
1861 [(set_attr "dslot" "ok_in_dslot")]
1862 )
1864 (define_insn "ctc3"
1865 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
1866 (match_operand:SI 1 "const_int_operand" "I")]
1867 UNSPEC_CTC3)]
1868 ""
1869 "* return iq2000_fill_delay_slot (\"ctc3\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
1870 [(set_attr "dslot" "ok_in_dslot")]
1871 )
1873 (define_insn "mfc0"
1874 [(set (match_operand:SI 0 "register_operand" "=r")
1875 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1876 UNSPEC_MFC0))]
1877 ""
1878 "* return iq2000_fill_delay_slot (\"mfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1879 [(set_attr "dslot" "ok_in_dslot")]
1880 )
1882 (define_insn "mfc1"
1883 [(set (match_operand:SI 0 "register_operand" "=r")
1884 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1885 UNSPEC_MFC1))]
1886 ""
1887 "* return iq2000_fill_delay_slot (\"mfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1888 [(set_attr "dslot" "ok_in_dslot")]
1889 )
1891 (define_insn "mfc2"
1892 [(set (match_operand:SI 0 "register_operand" "=r")
1893 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1894 UNSPEC_MFC2))]
1895 ""
1896 "* return iq2000_fill_delay_slot (\"mfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1897 [(set_attr "dslot" "not_in_dslot")]
1898 )
1900 (define_insn "mfc3"
1901 [(set (match_operand:SI 0 "register_operand" "=r")
1902 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1903 UNSPEC_MFC3))]
1904 ""
1905 "* return iq2000_fill_delay_slot (\"mfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1906 [(set_attr "dslot" "not_in_dslot")]
1907 )
1909 (define_insn "mtc0"
1910 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1911 (match_operand:SI 1 "const_int_operand" "I")]
1912 UNSPEC_MTC0)]
1913 ""
1914 "* return iq2000_fill_delay_slot (\"mtc0\\t%0, %%%1\", DELAY_NONE, operands, insn);"
1915 [(set_attr "dslot" "ok_in_dslot")]
1916 )
1918 (define_insn "mtc1"
1919 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1920 (match_operand:SI 1 "const_int_operand" "I")]
1921 UNSPEC_MTC1)]
1922 ""
1923 "* return iq2000_fill_delay_slot (\"mtc1\\t%0, %%%1\", DELAY_NONE, operands, insn);"
1924 [(set_attr "dslot" "ok_in_dslot")]
1925 )
1927 (define_insn "mtc2"
1928 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1929 (match_operand:SI 1 "const_int_operand" "I")]
1930 UNSPEC_MTC2)]
1931 ""
1932 "* return iq2000_fill_delay_slot (\"mtc2\\t%0, %%%1\", DELAY_NONE, operands, insn);"
1933 [(set_attr "dslot" "ok_in_dslot")]
1934 )
1936 (define_insn "mtc3"
1937 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1938 (match_operand:SI 1 "const_int_operand" "I")]
1939 UNSPEC_MTC3)]
1940 ""
1941 "* return iq2000_fill_delay_slot (\"mtc3\\t%0, %%%1\", DELAY_NONE, operands, insn);"
1942 [(set_attr "dslot" "ok_in_dslot")]
1943 )
1945 (define_insn "lur"
1946 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1947 (match_operand:SI 1 "register_operand" "r")]
1948 UNSPEC_LUR)]
1949 ""
1950 "* return iq2000_fill_delay_slot (\"lur\\t%0, %1\", DELAY_NONE, operands, insn);"
1951 [(set_attr "dslot" "not_in_dslot")]
1952 )
1954 (define_insn "rb"
1955 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1956 (match_operand:SI 1 "register_operand" "r")]
1957 UNSPEC_RB)]
1958 ""
1959 "* return iq2000_fill_delay_slot (\"rb\\t%0, %1\", DELAY_NONE, operands, insn);"
1960 [(set_attr "dslot" "not_in_dslot")]
1961 )
1963 (define_insn "rx"
1964 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1965 (match_operand:SI 1 "register_operand" "r")]
1966 UNSPEC_RX)]
1967 ""
1968 "* return iq2000_fill_delay_slot (\"rx\\t%0, %1\", DELAY_NONE, operands, insn);"
1969 [(set_attr "dslot" "not_in_dslot")]
1970 )
1972 (define_insn "srrd"
1973 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
1974 UNSPEC_SRRD)]
1975 ""
1976 "* return iq2000_fill_delay_slot (\"srrd\\t%0\", DELAY_NONE, operands, insn);"
1977 [(set_attr "dslot" "not_in_dslot")]
1978 )
1980 (define_insn "srwr"
1981 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1982 (match_operand:SI 1 "register_operand" "r")]
1983 UNSPEC_SRWR)]
1984 ""
1985 "* return iq2000_fill_delay_slot (\"srwr\\t%0, %1\", DELAY_NONE, operands, insn);"
1986 [(set_attr "dslot" "not_in_dslot")]
1987 )
1989 (define_insn "wb"
1990 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1991 (match_operand:SI 1 "register_operand" "r")]
1992 UNSPEC_WB)]
1993 ""
1994 "* return iq2000_fill_delay_slot (\"wb\\t%0, %1\", DELAY_NONE, operands, insn);"
1995 [(set_attr "dslot" "not_in_dslot")]
1996 )
1998 (define_insn "wx"
1999 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2000 (match_operand:SI 1 "register_operand" "r")]
2001 UNSPEC_WX)]
2002 ""
2003 "* return iq2000_fill_delay_slot (\"wx\\t%0, %1\", DELAY_NONE, operands, insn);"
2004 [(set_attr "dslot" "not_in_dslot")]
2005 )
2007 (define_insn "luc32"
2008 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2009 (match_operand:SI 1 "register_operand" "r")]
2010 UNSPEC_LUC32)]
2011 ""
2012 "* return iq2000_fill_delay_slot (\"luc32\\t%0, %1\", DELAY_NONE, operands, insn);"
2013 [(set_attr "dslot" "not_in_dslot")]
2014 )
2016 (define_insn "luc32l"
2017 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2018 (match_operand:SI 1 "register_operand" "r")]
2019 UNSPEC_LUC32L)]
2020 ""
2021 "* return iq2000_fill_delay_slot (\"luc32l\\t%0, %1\", DELAY_NONE, operands, insn);"
2022 [(set_attr "dslot" "not_in_dslot")]
2023 )
2025 (define_insn "luc64"
2026 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2027 (match_operand:SI 1 "register_operand" "r")]
2028 UNSPEC_LUC64)]
2029 ""
2030 "* return iq2000_fill_delay_slot (\"luc64\\t%0, %1\", DELAY_NONE, operands, insn);"
2031 [(set_attr "dslot" "not_in_dslot")]
2032 )
2034 (define_insn "luc64l"
2035 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2036 (match_operand:SI 1 "register_operand" "r")]
2037 UNSPEC_LUC64L)]
2038 ""
2039 "* return iq2000_fill_delay_slot (\"luc64l\\t%0, %1\", DELAY_NONE, operands, insn);"
2040 [(set_attr "dslot" "not_in_dslot")]
2041 )
2043 (define_insn "luk"
2044 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2045 (match_operand:SI 1 "register_operand" "r")]
2046 UNSPEC_LUK)]
2047 ""
2048 "* return iq2000_fill_delay_slot (\"luk\\t%0, %1\", DELAY_NONE, operands, insn);"
2049 [(set_attr "dslot" "ok_in_dslot")]
2050 )
2052 (define_insn "lulck"
2053 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2054 UNSPEC_LULCK)]
2055 ""
2056 "* return iq2000_fill_delay_slot (\"lulck\\t%0\", DELAY_NONE, operands, insn);"
2057 [(set_attr "dslot" "not_in_dslot")]
2058 )
2060 (define_insn "lum32"
2061 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2062 (match_operand:SI 1 "register_operand" "r")]
2063 UNSPEC_LUM32)]
2064 ""
2065 "* return iq2000_fill_delay_slot (\"lum32\\t%0, %1\", DELAY_NONE, operands, insn);"
2066 [(set_attr "dslot" "not_in_dslot")]
2067 )
2069 (define_insn "lum32l"
2070 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2071 (match_operand:SI 1 "register_operand" "r")]
2072 UNSPEC_LUM32L)]
2073 ""
2074 "* return iq2000_fill_delay_slot (\"lum32l\\t%0, %1\", DELAY_NONE, operands, insn);"
2075 [(set_attr "dslot" "not_in_dslot")]
2076 )
2078 (define_insn "lum64"
2079 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2080 (match_operand:SI 1 "register_operand" "r")]
2081 UNSPEC_LUM64)]
2082 ""
2083 "* return iq2000_fill_delay_slot (\"lum64\\t%0, %1\", DELAY_NONE, operands, insn);"
2084 [(set_attr "dslot" "not_in_dslot")]
2085 )
2087 (define_insn "lum64l"
2088 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2089 (match_operand:SI 1 "register_operand" "r")]
2090 UNSPEC_LUM64L)]
2091 ""
2092 "* return iq2000_fill_delay_slot (\"lum64l\\t%0, %1\", DELAY_NONE, operands, insn);"
2093 [(set_attr "dslot" "not_in_dslot")]
2094 )
2096 (define_insn "lurl"
2097 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2098 (match_operand:SI 1 "register_operand" "r")]
2099 UNSPEC_LURL)]
2100 ""
2101 "* return iq2000_fill_delay_slot (\"lurl\\t%0, %1\", DELAY_NONE, operands, insn);"
2102 [(set_attr "dslot" "not_in_dslot")]
2103 )
2105 (define_insn "mrgb"
2106 [(set (match_operand:SI 0 "register_operand" "=r")
2107 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
2108 (match_operand:SI 2 "register_operand" "r")
2109 (match_operand:SI 3 "const_int_operand" "I")]
2110 UNSPEC_MRGB))]
2111 ""
2112 "* return iq2000_fill_delay_slot (\"mrgb\\t%0, %1, %2, %3\", DELAY_LOAD, operands, insn);"
2113 [(set_attr "dslot" "ok_in_dslot")]
2114 )
2116 (define_insn "srrdl"
2117 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2118 UNSPEC_SRRDL)]
2119 ""
2120 "* return iq2000_fill_delay_slot (\"srrdl\\t%0\", DELAY_NONE, operands, insn);"
2121 [(set_attr "dslot" "not_in_dslot")]
2122 )
2124 (define_insn "srulck"
2125 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2126 UNSPEC_SRULCK)]
2127 ""
2128 "* return iq2000_fill_delay_slot (\"srulck\\t%0\", DELAY_NONE, operands, insn);"
2129 [(set_attr "dslot" "not_in_dslot")]
2130 )
2132 (define_insn "srwru"
2133 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2134 (match_operand:SI 1 "register_operand" "r")]
2135 UNSPEC_SRWRU)]
2136 ""
2137 "* return iq2000_fill_delay_slot (\"srwru\\t%0, %1\", DELAY_NONE, operands, insn);"
2138 [(set_attr "dslot" "not_in_dslot")]
2139 )
2141 (define_insn "trapqfl"
2142 [(unspec_volatile:SI [(const_int 1)] UNSPEC_TRAPQFL)]
2143 ""
2144 "* return iq2000_fill_delay_slot (\"trapqfl\", DELAY_NONE, operands, insn);"
2145 [(set_attr "dslot" "not_in_dslot")]
2146 )
2148 (define_insn "trapqne"
2149 [(unspec_volatile:SI [(const_int 2)] UNSPEC_TRAPQNE)]
2150 ""
2151 "* return iq2000_fill_delay_slot (\"trapqne\", DELAY_NONE, operands, insn);"
2152 [(set_attr "dslot" "not_in_dslot")]
2153 )
2155 (define_insn "traprel"
2156 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2157 UNSPEC_TRAPREL)]
2158 ""
2159 "* return iq2000_fill_delay_slot (\"traprel %0\", DELAY_NONE, operands, insn);"
2160 [(set_attr "dslot" "not_in_dslot")]
2161 )
2163 (define_insn "wbu"
2164 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2165 (match_operand:SI 1 "register_operand" "r")]
2166 UNSPEC_WBU)]
2167 ""
2168 "* return iq2000_fill_delay_slot (\"wbu\\t%0, %1\", DELAY_NONE, operands, insn);"
2169 [(set_attr "dslot" "not_in_dslot")]
2170 )
2172 (define_insn "syscall"
2173 [(unspec_volatile:SI [(const_int 2)] UNSPEC_SYSCALL)]
2174 ""
2175 "syscall"
2176 [(set_attr "dslot" "not_in_dslot")]
2177 )