| blob | 7bd9ff307b6470a68791c98ff14efcb1b0d12114 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
123 #ifndef CHECK_STACK_LIMIT
124 #define CHECK_STACK_LIMIT (-1)
125 #endif
127 /* Return index of given mode in mult and division cost tables. */
128 #define MODE_INDEX(mode) \
129 ((mode) == QImode ? 0 \
130 : (mode) == HImode ? 1 \
131 : (mode) == SImode ? 2 \
132 : (mode) == DImode ? 3 \
133 : 4)
135 /* Processor costs (relative to an add) */
136 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
137 #define COSTS_N_BYTES(N) ((N) * 2)
139 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
148 const
171 in QImode, HImode and SImode.
172 Relative to reg-reg move (2). */
176 in SFmode, DFmode and XFmode */
178 in SFmode, DFmode and XFmode */
181 in SImode and DImode */
183 in SImode and DImode */
186 in SImode, DImode and TImode */
188 in SImode, DImode and TImode */
201 ix86_size_memcpy,
202 ix86_size_memset,
214 };
216 /* Processor costs (relative to an add) */
219 DUMMY_STRINGOP_ALGS};
222 DUMMY_STRINGOP_ALGS};
224 static const
247 in QImode, HImode and SImode.
248 Relative to reg-reg move (2). */
252 in SFmode, DFmode and XFmode */
254 in SFmode, DFmode and XFmode */
257 in SImode and DImode */
259 in SImode and DImode */
262 in SImode, DImode and TImode */
264 in SImode, DImode and TImode */
277 i386_memcpy,
278 i386_memset,
290 };
294 DUMMY_STRINGOP_ALGS};
297 DUMMY_STRINGOP_ALGS};
299 static const
322 in QImode, HImode and SImode.
323 Relative to reg-reg move (2). */
327 in SFmode, DFmode and XFmode */
329 in SFmode, DFmode and XFmode */
332 in SImode and DImode */
334 in SImode and DImode */
337 in SImode, DImode and TImode */
339 in SImode, DImode and TImode */
342 shared for code and data, so 4kB is
343 not really precise. */
354 i486_memcpy,
355 i486_memset,
367 };
371 DUMMY_STRINGOP_ALGS};
374 DUMMY_STRINGOP_ALGS};
376 static const
399 in QImode, HImode and SImode.
400 Relative to reg-reg move (2). */
404 in SFmode, DFmode and XFmode */
406 in SFmode, DFmode and XFmode */
409 in SImode and DImode */
411 in SImode and DImode */
414 in SImode, DImode and TImode */
416 in SImode, DImode and TImode */
429 pentium_memcpy,
430 pentium_memset,
442 };
444 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
445 (we ensure the alignment). For small blocks inline loop is still a
446 noticeable win, for bigger blocks either rep movsl or rep movsb is
447 way to go. Rep movsb has apparently more expensive startup time in CPU,
448 but after 4K the difference is down in the noise. */
453 DUMMY_STRINGOP_ALGS};
458 DUMMY_STRINGOP_ALGS};
459 static const
482 in QImode, HImode and SImode.
483 Relative to reg-reg move (2). */
487 in SFmode, DFmode and XFmode */
489 in SFmode, DFmode and XFmode */
492 in SImode and DImode */
494 in SImode and DImode */
497 in SImode, DImode and TImode */
499 in SImode, DImode and TImode */
512 pentiumpro_memcpy,
513 pentiumpro_memset,
525 };
529 DUMMY_STRINGOP_ALGS};
532 DUMMY_STRINGOP_ALGS};
533 static const
556 in QImode, HImode and SImode.
557 Relative to reg-reg move (2). */
561 in SFmode, DFmode and XFmode */
563 in SFmode, DFmode and XFmode */
567 in SImode and DImode */
569 in SImode and DImode */
572 in SImode, DImode and TImode */
574 in SImode, DImode and TImode */
587 geode_memcpy,
588 geode_memset,
600 };
604 DUMMY_STRINGOP_ALGS};
607 DUMMY_STRINGOP_ALGS};
608 static const
631 in QImode, HImode and SImode.
632 Relative to reg-reg move (2). */
636 in SFmode, DFmode and XFmode */
638 in SFmode, DFmode and XFmode */
641 in SImode and DImode */
643 in SImode and DImode */
646 in SImode, DImode and TImode */
648 in SImode, DImode and TImode */
652 have integrated l2 cache, but
653 optimizing for k6 is not important
654 enough to worry about that. */
664 k6_memcpy,
665 k6_memset,
677 };
679 /* For some reason, Athlon deals better with REP prefix (relative to loops)
680 compared to K8. Alignment becomes important after 8 bytes for memcpy and
681 128 bytes for memset. */
684 DUMMY_STRINGOP_ALGS};
687 DUMMY_STRINGOP_ALGS};
688 static const
711 in QImode, HImode and SImode.
712 Relative to reg-reg move (2). */
716 in SFmode, DFmode and XFmode */
718 in SFmode, DFmode and XFmode */
721 in SImode and DImode */
723 in SImode and DImode */
726 in SImode, DImode and TImode */
728 in SImode, DImode and TImode */
741 athlon_memcpy,
742 athlon_memset,
754 };
756 /* K8 has optimized REP instruction for medium sized blocks, but for very
757 small blocks it is better to use loop. For large blocks, libcall can
758 do nontemporary accesses and beat inline considerably. */
769 static const
792 in QImode, HImode and SImode.
793 Relative to reg-reg move (2). */
797 in SFmode, DFmode and XFmode */
799 in SFmode, DFmode and XFmode */
802 in SImode and DImode */
804 in SImode and DImode */
807 in SImode, DImode and TImode */
809 in SImode, DImode and TImode */
814 /* New AMD processors never drop prefetches; if they cannot be performed
815 immediately, they are queued. We set number of simultaneous prefetches
816 to a large constant to reflect this (it probably is not a good idea not
817 to limit number of prefetches at all, as their execution also takes some
818 time). */
828 k8_memcpy,
829 k8_memset,
841 };
843 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
844 very small blocks it is better to use loop. For large blocks, libcall can
845 do nontemporary accesses and beat inline considerably. */
878 in QImode, HImode and SImode.
879 Relative to reg-reg move (2). */
883 in SFmode, DFmode and XFmode */
885 in SFmode, DFmode and XFmode */
888 in SImode and DImode */
890 in SImode and DImode */
893 in SImode, DImode and TImode */
895 in SImode, DImode and TImode */
897 /* On K8:
898 MOVD reg64, xmmreg Double FSTORE 4
899 MOVD reg32, xmmreg Double FSTORE 4
900 On AMDFAM10:
901 MOVD reg64, xmmreg Double FADD 3
902 1/1 1/1
903 MOVD reg32, xmmreg Double FADD 3
904 1/1 1/1 */
908 /* New AMD processors never drop prefetches; if they cannot be performed
909 immediately, they are queued. We set number of simultaneous prefetches
910 to a large constant to reflect this (it probably is not a good idea not
911 to limit number of prefetches at all, as their execution also takes some
912 time). */
922 amdfam10_memcpy,
923 amdfam10_memset,
935 };
937 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
938 very small blocks it is better to use loop. For large blocks, libcall
939 can do nontemporary accesses and beat inline considerably. */
973 in QImode, HImode and SImode.
974 Relative to reg-reg move (2). */
978 in SFmode, DFmode and XFmode */
980 in SFmode, DFmode and XFmode */
983 in SImode and DImode */
985 in SImode and DImode */
988 in SImode, DImode and TImode */
990 in SImode, DImode and TImode */
992 /* On K8:
993 MOVD reg64, xmmreg Double FSTORE 4
994 MOVD reg32, xmmreg Double FSTORE 4
995 On AMDFAM10:
996 MOVD reg64, xmmreg Double FADD 3
997 1/1 1/1
998 MOVD reg32, xmmreg Double FADD 3
999 1/1 1/1 */
1003 /* New AMD processors never drop prefetches; if they cannot be performed
1004 immediately, they are queued. We set number of simultaneous prefetches
1005 to a large constant to reflect this (it probably is not a good idea not
1006 to limit number of prefetches at all, as their execution also takes some
1007 time). */
1017 bdver1_memcpy,
1018 bdver1_memset,
1030 };
1032 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1033 very small blocks it is better to use loop. For large blocks, libcall
1034 can do nontemporary accesses and beat inline considerably. */
1069 in QImode, HImode and SImode.
1070 Relative to reg-reg move (2). */
1074 in SFmode, DFmode and XFmode */
1076 in SFmode, DFmode and XFmode */
1079 in SImode and DImode */
1081 in SImode and DImode */
1084 in SImode, DImode and TImode */
1086 in SImode, DImode and TImode */
1088 /* On K8:
1089 MOVD reg64, xmmreg Double FSTORE 4
1090 MOVD reg32, xmmreg Double FSTORE 4
1091 On AMDFAM10:
1092 MOVD reg64, xmmreg Double FADD 3
1093 1/1 1/1
1094 MOVD reg32, xmmreg Double FADD 3
1095 1/1 1/1 */
1099 /* New AMD processors never drop prefetches; if they cannot be performed
1100 immediately, they are queued. We set number of simultaneous prefetches
1101 to a large constant to reflect this (it probably is not a good idea not
1102 to limit number of prefetches at all, as their execution also takes some
1103 time). */
1113 bdver2_memcpy,
1114 bdver2_memset,
1126 };
1129 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1130 very small blocks it is better to use loop. For large blocks, libcall
1131 can do nontemporary accesses and beat inline considerably. */
1164 in QImode, HImode and SImode.
1165 Relative to reg-reg move (2). */
1169 in SFmode, DFmode and XFmode */
1171 in SFmode, DFmode and XFmode */
1174 in SImode and DImode */
1176 in SImode and DImode */
1179 in SImode, DImode and TImode */
1181 in SImode, DImode and TImode */
1186 /* New AMD processors never drop prefetches; if they cannot be performed
1187 immediately, they are queued. We set number of simultaneous prefetches
1188 to a large constant to reflect this (it probably is not a good idea not
1189 to limit number of prefetches at all, as their execution also takes some
1190 time). */
1200 bdver3_memcpy,
1201 bdver3_memset,
1213 };
1215 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1216 very small blocks it is better to use loop. For large blocks, libcall
1217 can do nontemporary accesses and beat inline considerably. */
1250 in QImode, HImode and SImode.
1251 Relative to reg-reg move (2). */
1255 in SFmode, DFmode and XFmode */
1257 in SFmode, DFmode and XFmode */
1260 in SImode and DImode */
1262 in SImode and DImode */
1265 in SImode, DImode and TImode */
1267 in SImode, DImode and TImode */
1272 /* New AMD processors never drop prefetches; if they cannot be performed
1273 immediately, they are queued. We set number of simultaneous prefetches
1274 to a large constant to reflect this (it probably is not a good idea not
1275 to limit number of prefetches at all, as their execution also takes some
1276 time). */
1286 bdver4_memcpy,
1287 bdver4_memset,
1299 };
1301 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1302 very small blocks it is better to use loop. For large blocks, libcall can
1303 do nontemporary accesses and beat inline considerably. */
1336 in QImode, HImode and SImode.
1337 Relative to reg-reg move (2). */
1341 in SFmode, DFmode and XFmode */
1343 in SFmode, DFmode and XFmode */
1346 in SImode and DImode */
1348 in SImode and DImode */
1351 in SImode, DImode and TImode */
1353 in SImode, DImode and TImode */
1355 /* On K8:
1356 MOVD reg64, xmmreg Double FSTORE 4
1357 MOVD reg32, xmmreg Double FSTORE 4
1358 On AMDFAM10:
1359 MOVD reg64, xmmreg Double FADD 3
1360 1/1 1/1
1361 MOVD reg32, xmmreg Double FADD 3
1362 1/1 1/1 */
1375 btver1_memcpy,
1376 btver1_memset,
1388 };
1422 in QImode, HImode and SImode.
1423 Relative to reg-reg move (2). */
1427 in SFmode, DFmode and XFmode */
1429 in SFmode, DFmode and XFmode */
1432 in SImode and DImode */
1434 in SImode and DImode */
1437 in SImode, DImode and TImode */
1439 in SImode, DImode and TImode */
1441 /* On K8:
1442 MOVD reg64, xmmreg Double FSTORE 4
1443 MOVD reg32, xmmreg Double FSTORE 4
1444 On AMDFAM10:
1445 MOVD reg64, xmmreg Double FADD 3
1446 1/1 1/1
1447 MOVD reg32, xmmreg Double FADD 3
1448 1/1 1/1 */
1460 btver2_memcpy,
1461 btver2_memset,
1473 };
1477 DUMMY_STRINGOP_ALGS};
1481 DUMMY_STRINGOP_ALGS};
1483 static const
1506 in QImode, HImode and SImode.
1507 Relative to reg-reg move (2). */
1511 in SFmode, DFmode and XFmode */
1513 in SFmode, DFmode and XFmode */
1516 in SImode and DImode */
1518 in SImode and DImode */
1521 in SImode, DImode and TImode */
1523 in SImode, DImode and TImode */
1536 pentium4_memcpy,
1537 pentium4_memset,
1549 };
1562 static const
1585 in QImode, HImode and SImode.
1586 Relative to reg-reg move (2). */
1590 in SFmode, DFmode and XFmode */
1592 in SFmode, DFmode and XFmode */
1595 in SImode and DImode */
1597 in SImode and DImode */
1600 in SImode, DImode and TImode */
1602 in SImode, DImode and TImode */
1615 nocona_memcpy,
1616 nocona_memset,
1628 };
1639 static const
1662 in QImode, HImode and SImode.
1663 Relative to reg-reg move (2). */
1667 in SFmode, DFmode and XFmode */
1669 in SFmode, DFmode and XFmode */
1672 in SImode and DImode */
1674 in SImode and DImode */
1677 in SImode, DImode and TImode */
1679 in SImode, DImode and TImode */
1692 atom_memcpy,
1693 atom_memset,
1705 };
1716 static const
1739 in QImode, HImode and SImode.
1740 Relative to reg-reg move (2). */
1744 in SFmode, DFmode and XFmode */
1746 in SFmode, DFmode and XFmode */
1749 in SImode and DImode */
1751 in SImode and DImode */
1754 in SImode, DImode and TImode */
1756 in SImode, DImode and TImode */
1769 slm_memcpy,
1770 slm_memset,
1782 };
1793 static const
1816 in QImode, HImode and SImode.
1817 Relative to reg-reg move (2). */
1821 in SFmode, DFmode and XFmode */
1823 in SFmode, DFmode and XFmode */
1826 in SImode and DImode */
1828 in SImode and DImode */
1831 in SImode, DImode and TImode */
1833 in SImode, DImode and TImode */
1846 intel_memcpy,
1847 intel_memset,
1859 };
1861 /* Generic should produce code tuned for Core-i7 (and newer chips)
1862 and btver1 (and newer chips). */
1874 static const
1877 /* On all chips taken into consideration lea is 2 cycles and more. With
1878 this cost however our current implementation of synth_mult results in
1879 use of unnecessary temporary registers causing regression on several
1880 SPECfp benchmarks. */
1901 in QImode, HImode and SImode.
1902 Relative to reg-reg move (2). */
1906 in SFmode, DFmode and XFmode */
1908 in SFmode, DFmode and XFmode */
1911 in SImode and DImode */
1913 in SImode and DImode */
1916 in SImode, DImode and TImode */
1918 in SImode, DImode and TImode */
1924 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1925 value is increased to perhaps more appropriate value of 5. */
1933 generic_memcpy,
1934 generic_memset,
1946 };
1948 /* core_cost should produce code tuned for Core familly of CPUs. */
1961 static const
1964 /* On all chips taken into consideration lea is 2 cycles and more. With
1965 this cost however our current implementation of synth_mult results in
1966 use of unnecessary temporary registers causing regression on several
1967 SPECfp benchmarks. */
1988 in QImode, HImode and SImode.
1989 Relative to reg-reg move (2). */
1993 in SFmode, DFmode and XFmode */
1995 in SFmode, DFmode and XFmode */
1998 in SImode and DImode */
2000 in SImode and DImode */
2003 in SImode, DImode and TImode */
2005 in SImode, DImode and TImode */
2011 /* FIXME perhaps more appropriate value is 5. */
2019 core_memcpy,
2020 core_memset,
2032 };
2035 /* Set by -mtune. */
2038 /* Set by -mtune or -Os. */
2041 /* Processor feature/optimization bitmasks. */
2042 #define m_386 (1<<PROCESSOR_I386)
2043 #define m_486 (1<<PROCESSOR_I486)
2044 #define m_PENT (1<<PROCESSOR_PENTIUM)
2045 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2046 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2047 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2048 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2049 #define m_CORE2 (1<<PROCESSOR_CORE2)
2050 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2051 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2052 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2053 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2054 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2055 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2056 #define m_KNL (1<<PROCESSOR_KNL)
2057 #define m_INTEL (1<<PROCESSOR_INTEL)
2059 #define m_GEODE (1<<PROCESSOR_GEODE)
2060 #define m_K6 (1<<PROCESSOR_K6)
2061 #define m_K6_GEODE (m_K6 | m_GEODE)
2062 #define m_K8 (1<<PROCESSOR_K8)
2063 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2064 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2065 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2066 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2067 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2068 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2069 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2070 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2071 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2072 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2073 #define m_BTVER (m_BTVER1 | m_BTVER2)
2074 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2076 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2079 #undef DEF_TUNE
2080 #define DEF_TUNE(tune, name, selector) name,
2082 #undef DEF_TUNE
2083 };
2085 /* Feature tests against the various tunings. */
2088 /* Feature tests against the various tunings used to create ix86_tune_features
2089 based on the processor mask. */
2091 #undef DEF_TUNE
2092 #define DEF_TUNE(tune, name, selector) selector,
2094 #undef DEF_TUNE
2095 };
2097 /* Feature tests against the various architecture variations. */
2100 /* Feature tests against the various architecture variations, used to create
2101 ix86_arch_features based on the processor mask. */
2103 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2106 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2109 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2112 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2115 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2117 };
2119 /* In case the average insn count for single function invocation is
2120 lower than this constant, emit fast (but longer) prologue and
2121 epilogue code. */
2122 #define FAST_PROLOGUE_INSN_COUNT 20
2124 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2129 /* Array of the smallest class containing reg number REGNO, indexed by
2130 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2133 {
2134 /* ax, dx, cx, bx */
2136 /* si, di, bp, sp */
2138 /* FP registers */
2141 /* arg pointer */
2142 NON_Q_REGS,
2143 /* flags, fpsr, fpcr, frame */
2145 /* SSE registers */
2148 /* MMX registers */
2151 /* REX registers */
2154 /* SSE REX registers */
2157 /* AVX-512 SSE registers */
2162 /* Mask registers. */
2165 /* MPX bound registers */
2167 };
2169 /* The "default" register map used in 32bit mode. */
2172 {
2184 };
2186 /* The "default" register map used in 64bit mode. */
2189 {
2201 };
2203 /* Define the register numbers to be used in Dwarf debugging information.
2204 The SVR4 reference port C compiler uses the following register numbers
2205 in its Dwarf output code:
2206 0 for %eax (gcc regno = 0)
2207 1 for %ecx (gcc regno = 2)
2208 2 for %edx (gcc regno = 1)
2209 3 for %ebx (gcc regno = 3)
2210 4 for %esp (gcc regno = 7)
2211 5 for %ebp (gcc regno = 6)
2212 6 for %esi (gcc regno = 4)
2213 7 for %edi (gcc regno = 5)
2214 The following three DWARF register numbers are never generated by
2215 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2216 believes these numbers have these meanings.
2217 8 for %eip (no gcc equivalent)
2218 9 for %eflags (gcc regno = 17)
2219 10 for %trapno (no gcc equivalent)
2220 It is not at all clear how we should number the FP stack registers
2221 for the x86 architecture. If the version of SDB on x86/svr4 were
2222 a bit less brain dead with respect to floating-point then we would
2223 have a precedent to follow with respect to DWARF register numbers
2224 for x86 FP registers, but the SDB on x86/svr4 is so completely
2225 broken with respect to FP registers that it is hardly worth thinking
2226 of it as something to strive for compatibility with.
2227 The version of x86/svr4 SDB I have at the moment does (partially)
2228 seem to believe that DWARF register number 11 is associated with
2229 the x86 register %st(0), but that's about all. Higher DWARF
2230 register numbers don't seem to be associated with anything in
2231 particular, and even for DWARF regno 11, SDB only seems to under-
2232 stand that it should say that a variable lives in %st(0) (when
2233 asked via an `=' command) if we said it was in DWARF regno 11,
2234 but SDB still prints garbage when asked for the value of the
2235 variable in question (via a `/' command).
2236 (Also note that the labels SDB prints for various FP stack regs
2237 when doing an `x' command are all wrong.)
2238 Note that these problems generally don't affect the native SVR4
2239 C compiler because it doesn't allow the use of -O with -g and
2240 because when it is *not* optimizing, it allocates a memory
2241 location for each floating-point variable, and the memory
2242 location is what gets described in the DWARF AT_location
2243 attribute for the variable in question.
2244 Regardless of the severe mental illness of the x86/svr4 SDB, we
2245 do something sensible here and we use the following DWARF
2246 register numbers. Note that these are all stack-top-relative
2247 numbers.
2248 11 for %st(0) (gcc regno = 8)
2249 12 for %st(1) (gcc regno = 9)
2250 13 for %st(2) (gcc regno = 10)
2251 14 for %st(3) (gcc regno = 11)
2252 15 for %st(4) (gcc regno = 12)
2253 16 for %st(5) (gcc regno = 13)
2254 17 for %st(6) (gcc regno = 14)
2255 18 for %st(7) (gcc regno = 15)
2256 */
2258 {
2270 };
2272 /* Define parameter passing and return registers. */
2275 {
2277 };
2280 {
2282 };
2285 {
2287 };
2289 /* Additional registers that are clobbered by SYSV calls. */
2292 {
2297 };
2299 /* Define the structure for the machine field in struct function. */
2304 rtx rtl;
2306 };
2308 /* Structure describing stack frame layout.
2309 Stack grows downward:
2311 [arguments]
2312 <- ARG_POINTER
2313 saved pc
2315 saved static chain if ix86_static_chain_on_stack
2317 saved frame pointer if frame_pointer_needed
2318 <- HARD_FRAME_POINTER
2319 [saved regs]
2320 <- regs_save_offset
2321 [padding0]
2323 [saved SSE regs]
2324 <- sse_regs_save_offset
2325 [padding1] |
2326 | <- FRAME_POINTER
2327 [va_arg registers] |
2328 |
2329 [frame] |
2330 |
2331 [padding2] | = to_allocate
2332 <- STACK_POINTER
2333 */
2334 struct ix86_frame
2335 {
2342 /* The offsets relative to ARG_POINTER. */
2343 HOST_WIDE_INT frame_pointer_offset;
2344 HOST_WIDE_INT hard_frame_pointer_offset;
2345 HOST_WIDE_INT stack_pointer_offset;
2346 HOST_WIDE_INT hfp_save_offset;
2347 HOST_WIDE_INT reg_save_offset;
2348 HOST_WIDE_INT sse_reg_save_offset;
2350 /* When save_regs_using_mov is set, emit prologue using
2351 move instead of push instructions. */
2353 };
2355 /* Which cpu are we scheduling for. */
2358 /* Which cpu are we optimizing for. */
2361 /* Which instruction set architecture to use. */
2364 /* True if processor has SSE prefetch instruction. */
2367 /* -mstackrealign option */
2384 /* Preferred alignment for stack boundary in bits. */
2387 /* Alignment for incoming stack boundary in bits specified at
2388 command line. */
2391 /* Default alignment for incoming stack boundary in bits. */
2394 /* Alignment for incoming stack boundary in bits. */
2397 /* Calling abi specific va_list type nodes. */
2401 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2405 /* Fence to use after loop using movnt. */
2406 tree x86_mfence;
2408 /* Register class used for passing given 64bit part of the argument.
2409 These represent classes as documented by the PS ABI, with the exception
2410 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2411 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2413 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2414 whenever possible (upper half does contain padding). */
2415 enum x86_64_reg_class
2416 {
2417 X86_64_NO_CLASS,
2418 X86_64_INTEGER_CLASS,
2419 X86_64_INTEGERSI_CLASS,
2420 X86_64_SSE_CLASS,
2421 X86_64_SSESF_CLASS,
2422 X86_64_SSEDF_CLASS,
2423 X86_64_SSEUP_CLASS,
2424 X86_64_X87_CLASS,
2425 X86_64_X87UP_CLASS,
2426 X86_64_COMPLEX_X87_CLASS,
2427 X86_64_MEMORY_CLASS
2428 };
2430 #define MAX_CLASSES 8
2432 /* Table of constants used by fldpi, fldln2, etc.... */
2436 \f
2441 const_tree);
2453 enum ix86_function_specific_strings
2454 {
2455 IX86_FUNCTION_SPECIFIC_ARCH,
2456 IX86_FUNCTION_SPECIFIC_TUNE,
2457 IX86_FUNCTION_SPECIFIC_MAX
2458 };
2480 \f
2481 #ifndef SUBTARGET32_DEFAULT_CPU
2483 #endif
2485 /* Whether -mtune= or -march= were specified */
2489 /* Vectorization library interface and handlers. */
2495 /* Processor target table, indexed by processor number */
2496 struct ptt
2497 {
2505 };
2507 /* This table must be in sync with enum processor_type in i386.h. */
2509 {
2536 };
2537 \f
2538 static unsigned int
2540 {
2543 /* vzeroupper instructions are inserted immediately after reload to
2544 account for possible spills from 256bit registers. The pass
2545 reuses mode switching infrastructure by re-running mode insertion
2546 pass, so disable entities that have already been processed. */
2552 /* Call optimize_mode_switching. */
2555 }
2560 {
2570 };
2573 {
2577 {}
2579 /* opt_pass methods: */
2581 {
2585 }
2588 {
2590 }
2596 rtl_opt_pass *
2598 {
2600 }
2602 /* Return true if a red-zone is in use. */
2606 {
2608 }
2609 \f
2610 /* Return a string that documents the current -m options. The caller is
2611 responsible for freeing the string. */
2617 {
2618 struct ix86_target_opts
2619 {
2622 };
2624 /* This table is ordered so that options like -msse4.2 that imply
2625 preceding options while match those first. */
2627 {
2680 };
2682 /* Flag options. */
2684 {
2713 };
2730 /* Add -march= option. */
2732 {
2735 }
2737 /* Add -mtune= option. */
2739 {
2742 }
2744 /* Add -m32/-m64/-mx32. */
2746 {
2749 else
2751 isa &= ~ (OPTION_MASK_ISA_64BIT
2752 | OPTION_MASK_ABI_64
2754 }
2755 else
2759 /* Pick out the options in isa options. */
2761 {
2763 {
2766 }
2767 }
2770 {
2773 isa);
2774 }
2776 /* Add flag options. */
2778 {
2780 {
2783 }
2784 }
2787 {
2790 }
2792 /* Add -fpmath= option. */
2794 {
2797 {
2812 }
2813 }
2815 /* Any options? */
2821 /* Size the string. */
2825 {
2830 }
2832 /* Build the string. */
2837 {
2844 {
2846 line_len++;
2849 {
2853 }
2854 }
2858 {
2862 }
2863 }
2869 }
2871 /* Return true, if profiling code should be emitted before
2872 prologue. Otherwise it returns false.
2873 Note: For x86 with "hotfix" it is sorried. */
2874 static bool
2876 {
2878 }
2880 /* Function that is callable from the debugger to print the current
2881 options. */
2882 void ATTRIBUTE_UNUSED
2884 {
2890 {
2893 }
2894 else
2898 }
2901 #define DEF_ENUM
2902 #define DEF_ALG(alg, name) #name,
2904 #undef DEF_ENUM
2905 #undef DEF_ALG
2906 };
2908 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2909 The string is of the following form (or comma separated list of it):
2911 strategy_alg:max_size:[align|noalign]
2913 where the full size range for the strategy is either [0, max_size] or
2914 [min_size, max_size], in which min_size is the max_size + 1 of the
2915 preceding range. The last size range must have max_size == -1.
2917 Examples:
2919 1.
2920 -mmemcpy-strategy=libcall:-1:noalign
2922 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2925 2.
2926 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2928 This is to tell the compiler to use the following strategy for memset
2929 1) when the expected size is between [1, 16], use rep_8byte strategy;
2930 2) when the size is between [17, 2048], use vector_loop;
2931 3) when the size is > 2048, use libcall. */
2933 struct stringop_size_range
2934 {
2936 stringop_alg alg;
2938 };
2940 static void
2942 {
2950 else
2955 do
2956 {
2966 {
2970 }
2973 {
2977 }
2984 {
2986 alg_name,
2989 }
2993 {
2994 /* rep; movq isn't available in 32-bit code. */
2997 alg_name,
3000 }
3008 else
3009 {
3013 }
3014 n++;
3016 }
3020 {
3025 }
3028 {
3032 }
3034 /* Now override the default algs array. */
3036 {
3042 }
3043 }
3045 \f
3046 /* parse -mtune-ctrl= option. When DUMP is true,
3047 print the features that are explicitly set. */
3049 static void
3051 {
3059 do
3060 {
3067 {
3068 curr_feature_string++;
3070 }
3072 {
3074 {
3080 }
3081 }
3086 }
3089 }
3091 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3092 processor type. */
3094 static void
3096 {
3101 {
3104 else
3106 }
3109 {
3114 }
3117 }
3120 /* Default align_* from the processor table. */
3122 static void
3124 {
3126 {
3129 }
3131 {
3134 }
3136 {
3138 }
3139 }
3141 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE hook. */
3143 static void
3145 {
3147 }
3149 /* Override various settings based on options. If MAIN_ARGS_P, the
3150 options are from the command line, otherwise they are from
3151 attributes. */
3153 static void
3157 {
3165 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3166 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3167 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3168 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3169 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3170 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3171 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3172 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3173 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3174 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3175 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3176 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3177 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3178 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3179 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3180 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3181 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3182 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3183 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3184 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3185 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3186 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3187 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3188 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3189 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3190 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3191 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3192 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3193 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3194 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3195 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3196 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3197 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3198 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3199 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3200 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3201 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3202 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3203 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3204 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3205 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3206 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3207 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3208 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3209 #define PTA_MPX (HOST_WIDE_INT_1 << 44)
3210 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3211 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3212 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3213 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3214 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3215 #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
3216 #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
3217 #define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
3218 #define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
3219 #define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
3220 #define PTA_CLWB (HOST_WIDE_INT_1 << 55)
3221 #define PTA_PCOMMIT (HOST_WIDE_INT_1 << 56)
3223 #define PTA_CORE2 \
3224 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3225 | PTA_CX16 | PTA_FXSR)
3226 #define PTA_NEHALEM \
3227 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3228 #define PTA_WESTMERE \
3229 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3230 #define PTA_SANDYBRIDGE \
3231 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3232 #define PTA_IVYBRIDGE \
3233 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3234 #define PTA_HASWELL \
3235 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3236 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3237 #define PTA_BROADWELL \
3238 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3239 #define PTA_KNL \
3240 (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
3241 #define PTA_BONNELL \
3242 (PTA_CORE2 | PTA_MOVBE)
3243 #define PTA_SILVERMONT \
3244 (PTA_WESTMERE | PTA_MOVBE)
3246 /* if this reaches 64, need to widen struct pta flags below */
3248 static struct pta
3249 {
3254 }
3256 {
3290 PTA_SANDYBRIDGE},
3292 PTA_SANDYBRIDGE},
3294 PTA_IVYBRIDGE},
3296 PTA_IVYBRIDGE},
3388 PTA_64BIT
3390 };
3392 /* -mrecip options. */
3393 static struct
3394 {
3397 }
3399 {
3406 };
3410 /* Set up prefix/suffix so the error messages refer to either the command
3411 line argument, or the attribute(target). */
3413 {
3417 }
3418 else
3419 {
3423 }
3425 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3426 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3429 #ifdef TARGET_BI_ARCH
3430 else
3431 {
3432 #if TARGET_BI_ARCH == 1
3433 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3434 is on and OPTION_MASK_ABI_X32 is off. We turn off
3435 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3436 -mx32. */
3439 #else
3440 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3441 on and OPTION_MASK_ABI_64 is off. We turn off
3442 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3443 -m64 or OPTION_MASK_CODE16 is turned on by -m16. */
3447 #endif
3448 }
3449 #endif
3452 {
3453 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3454 OPTION_MASK_ABI_64 for TARGET_X32. */
3457 }
3460 | OPTION_MASK_ABI_X32
3463 {
3464 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3465 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3468 }
3470 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3471 SUBTARGET_OVERRIDE_OPTIONS;
3472 #endif
3474 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3475 SUBSUBTARGET_OVERRIDE_OPTIONS;
3476 #endif
3478 /* -fPIC is the default for x86_64. */
3482 /* Need to check -mtune=generic first. */
3484 {
3485 /* As special support for cross compilers we read -mtune=native
3486 as -mtune=generic. With native compilers we won't see the
3487 -mtune=native, as it was changed by the driver. */
3489 {
3491 }
3496 }
3497 else
3498 {
3502 {
3503 opts->x_ix86_tune_string
3506 }
3508 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3509 or defaulted. We need to use a sensible tune option. */
3511 {
3513 }
3514 }
3518 {
3519 /* rep; movq isn't available in 32-bit code. */
3522 }
3525 opts->x_ix86_arch_string
3528 else
3532 {
3540 }
3541 else
3548 /* For targets using ms ABI enable ms-extensions, if not
3549 explicit turned off. For non-ms ABI we turn off this
3550 option. */
3555 {
3557 {
3601 {
3604 }
3612 }
3613 }
3614 else
3615 {
3616 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3617 use of rip-relative addressing. This eliminates fixups that
3618 would otherwise be needed if this object is to be placed in a
3619 DLL, and is essentially just as efficient as direct addressing. */
3625 else
3627 }
3629 {
3632 }
3640 {
3643 /* Default cpu tuning to the architecture. */
3821 }
3845 {
3849 {
3851 {
3853 {
3861 }
3862 else
3865 }
3866 }
3867 /* Intel CPUs have always interpreted SSE prefetch instructions as
3868 NOPs; so, we can enable SSE prefetch instructions even when
3869 -mtune (rather than -march) points us to a processor that has them.
3870 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3871 higher processors. */
3876 }
3884 #ifndef USE_IX86_FRAME_POINTER
3885 #define USE_IX86_FRAME_POINTER 0
3886 #endif
3888 #ifndef USE_X86_64_FRAME_POINTER
3889 #define USE_X86_64_FRAME_POINTER 0
3890 #endif
3892 /* Set the default values for switches whose default depends on TARGET_64BIT
3893 in case they weren't overwritten by command line options. */
3895 {
3903 opts->x_flag_unwind_tables
3907 }
3908 else
3909 {
3911 opts->x_flag_omit_frame_pointer
3917 }
3920 /* TODO: ix86_cost should be chosen at instruction or function granuality
3921 so for cold code we use size_cost even in !optimize_size compilation. */
3924 else
3927 /* Arrange to set up i386_stack_locals for all functions. */
3930 /* Validate -mregparm= value. */
3932 {
3936 {
3940 }
3941 }
3945 /* Default align_* from the processor table. */
3948 /* Provide default for -mbranch-cost= value. */
3953 {
3954 opts->x_target_flags
3957 /* Enable by default the SSE and MMX builtins. Do allow the user to
3958 explicitly disable any of these. In particular, disabling SSE and
3959 MMX for kernel code is extremely useful. */
3961 opts->x_ix86_isa_flags
3968 }
3969 else
3970 {
3971 opts->x_target_flags
3975 opts->x_ix86_isa_flags
3978 /* i386 ABI does not specify red zone. It still makes sense to use it
3979 when programmer takes care to stack from being destroyed. */
3982 }
3984 /* Keep nonleaf frame pointers. */
3990 /* If we're doing fast math, we don't care about comparison order
3991 wrt NaNs. This lets us use a shorter comparison sequence. */
3995 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3996 since the insns won't need emulation. */
4000 /* Likewise, if the target doesn't have a 387, or we've specified
4001 software floating point, don't use 387 inline intrinsics. */
4005 /* Turn on MMX builtins for -msse. */
4007 opts->x_ix86_isa_flags
4010 /* Enable SSE prefetch. */
4015 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
4018 opts->x_ix86_isa_flags
4021 /* Enable popcnt instruction for -msse4.2 or -mabm. */
4024 opts->x_ix86_isa_flags
4027 /* Enable lzcnt instruction for -mabm. */
4029 opts->x_ix86_isa_flags
4032 /* Validate -mpreferred-stack-boundary= value or default it to
4033 PREFERRED_STACK_BOUNDARY_DEFAULT. */
4036 {
4043 {
4047 else
4050 }
4051 else
4052 ix86_preferred_stack_boundary
4054 }
4056 /* Set the default value for -mstackrealign. */
4062 /* Validate -mincoming-stack-boundary= value or default it to
4063 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
4066 {
4073 else
4074 {
4075 ix86_user_incoming_stack_boundary
4077 ix86_incoming_stack_boundary
4079 }
4080 }
4082 #ifndef NO_PROFILE_COUNTERS
4085 #endif
4089 /* Accept -msseregparm only if at least SSE support is enabled. */
4095 {
4097 {
4099 {
4102 }
4105 {
4108 }
4109 }
4110 }
4111 /* For all chips supporting SSE2, -mfpmath=sse performs better than
4112 fpmath=387. The second is however default at many targets since the
4113 extra 80bit precision of temporaries is considered to be part of ABI.
4114 Overwrite the default at least for -ffast-math.
4115 TODO: -mfpmath=both seems to produce same performing code with bit
4116 smaller binaries. It is however not clear if register allocation is
4117 ready for this setting.
4118 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
4119 codegen. We may switch to 387 with -ffast-math for size optimized
4120 functions. */
4124 else
4127 /* If the i387 is disabled, then do not return values in it. */
4131 /* Use external vectorized library in vectorizing intrinsics. */
4134 {
4145 }
4151 /* If stack probes are required, the space used for large function
4152 arguments on the stack must also be probed, so enable
4153 -maccumulate-outgoing-args so this happens in the prologue. */
4156 {
4161 }
4163 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4164 {
4170 }
4172 /* When scheduling description is not available, disable scheduler pass
4173 so it won't slow down the compilation and make x87 code slower. */
4194 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4196 && HAVE_prefetch
4202 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4203 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4208 {
4211 {
4213 ix86_gen_tls_local_dynamic_base_64
4215 }
4216 else
4217 {
4219 ix86_gen_tls_local_dynamic_base_64
4221 }
4222 }
4223 else
4227 {
4237 }
4238 else
4239 {
4249 }
4251 #ifdef USE_IX86_CLD
4252 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4255 #endif
4258 {
4263 }
4265 {
4269 }
4271 {
4272 #if defined(PROFILE_BEFORE_PROLOGUE)
4274 #else
4276 #endif
4277 }
4287 /* Enable 128-bit AVX instruction generation
4288 for the auto-vectorizer. */
4294 {
4301 {
4304 {
4306 q++;
4307 }
4308 else
4313 else
4314 {
4317 {
4320 }
4323 {
4327 }
4328 }
4333 else
4335 }
4336 }
4343 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4344 for 64-bit Bionic. */
4349 ? MASK_LONG_DOUBLE_128
4352 /* Only one of them can be active. */
4356 /* Save the initial options in case the user does function specific
4357 options. */
4359 target_option_default_node = target_option_current_node
4362 /* Handle stack protector */
4364 opts->x_ix86_stack_protector_guard
4367 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4369 {
4373 }
4376 {
4380 }
4381 }
4383 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4385 static void
4387 {
4389 struct register_pass_info insert_vzeroupper_info
4392 };
4397 /* This needs to be done at start up. It's convenient to do it here. */
4399 }
4401 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
4404 {
4408 }
4410 /* Update register usage after having seen the compiler flags. */
4412 static void
4414 {
4417 /* For 32-bit targets, squash the REX registers. */
4419 {
4426 }
4428 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4436 {
4437 /* Set/reset conditionally defined registers from
4438 CALL_USED_REGISTERS initializer. */
4442 /* Calculate registers of CLOBBERED_REGS register set
4443 as call used registers from GENERAL_REGS register set. */
4447 }
4449 /* If MMX is disabled, squash the registers. */
4455 /* If SSE is disabled, squash the registers. */
4461 /* If the FPU is disabled, squash the registers. */
4467 /* If AVX512F is disabled, squash the registers. */
4469 {
4475 }
4477 /* If MPX is disabled, squash the registers. */
4481 }
4483 \f
4484 /* Save the current options */
4486 static void
4489 {
4525 /* The fields are char but the variables are not; make sure the
4526 values fit in the fields. */
4531 }
4533 /* Restore the current options */
4535 static void
4538 {
4544 /* We don't change -fPIC. */
4582 /* TODO: ix86_cost should be chosen at instruction or function granuality
4583 so for cold code we use size_cost even in !optimize_size compilation. */
4586 else
4589 /* Recreate the arch feature tests if the arch changed */
4591 {
4596 }
4598 /* Recreate the tune optimization tests */
4601 }
4603 /* Adjust target options after streaming them in. This is mainly about
4604 reconciling them with global options. */
4606 static void
4608 {
4609 /* flag_pic is a global option, but ix86_cmodel is target saved option
4610 partly computed from flag_pic. If flag_pic is on, adjust x_ix86_cmodel
4611 for PIC, or error out. */
4614 {
4633 }
4634 else
4636 {
4651 }
4652 }
4654 /* Print the current options */
4656 static void
4659 {
4677 {
4680 }
4681 }
4683 \f
4684 /* Inner function to process the attribute((target(...))), take an argument and
4685 set the current options from the argument. If we have a list, recursively go
4686 over the list. */
4688 static bool
4693 {
4697 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4698 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4699 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4700 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4701 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4703 enum ix86_opt_type
4704 {
4705 ix86_opt_unknown,
4706 ix86_opt_yes,
4707 ix86_opt_no,
4708 ix86_opt_str,
4709 ix86_opt_enum,
4710 ix86_opt_isa
4711 };
4713 static const struct
4714 {
4721 /* isa options */
4774 /* enum options */
4777 /* string options */
4781 /* flag options */
4783 OPT_mcld,
4784 MASK_CLD),
4787 OPT_mfancy_math_387,
4788 MASK_NO_FANCY_MATH_387),
4791 OPT_mieee_fp,
4792 MASK_IEEE_FP),
4795 OPT_minline_all_stringops,
4796 MASK_INLINE_ALL_STRINGOPS),
4799 OPT_minline_stringops_dynamically,
4800 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4803 OPT_mno_align_stringops,
4804 MASK_NO_ALIGN_STRINGOPS),
4807 OPT_mrecip,
4808 MASK_RECIP),
4810 };
4812 /* If this is a list, recurse to get the options. */
4814 {
4821 enum_opts_set))
4825 }
4828 {
4831 }
4833 /* Handle multiple arguments separated by commas. */
4837 {
4851 {
4855 }
4856 else
4857 {
4860 }
4862 /* Recognize no-xxx. */
4864 {
4868 }
4869 else
4872 /* Find the option. */
4876 {
4884 {
4889 }
4890 }
4892 /* Process the option. */
4894 {
4897 }
4900 {
4906 }
4909 {
4915 else
4917 }
4920 {
4922 {
4925 }
4926 else
4928 }
4931 {
4939 global_dc);
4940 else
4941 {
4944 }
4945 }
4947 else
4949 }
4952 }
4954 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4956 tree
4960 {
4975 /* Process each of the options on the chain. */
4980 /* If the changed options are different from the default, rerun
4981 ix86_option_override_internal, and then save the options away.
4982 The string options are are attribute options, and will be undone
4983 when we copy the save structure. */
4989 {
4990 /* If we are using the default tune= or arch=, undo the string assigned,
4991 and use the default. */
5002 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
5007 {
5010 }
5012 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
5015 /* Add any builtin functions with the new isa if any. */
5018 /* Save the current options unless we are validating options for
5019 #pragma. */
5026 /* Free up memory allocated to hold the strings */
5029 }
5032 }
5034 /* Hook to validate attribute((target("string"))). */
5036 static bool
5039 tree args,
5041 {
5046 /* attribute((target("default"))) does nothing, beyond
5047 affecting multi-versioning. */
5056 /* Get the optimization options of the current function. */
5062 /* Init func_options. */
5070 /* Initialize func_options to the default before its target options can
5071 be set. */
5084 {
5089 }
5092 }
5094 \f
5095 /* Hook to determine if one function can safely inline another. */
5097 static bool
5099 {
5104 /* If callee has no option attributes, then it is ok to inline. */
5108 /* If caller has no option attributes, but callee does then it is not ok to
5109 inline. */
5113 else
5114 {
5118 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
5119 can inline a SSE2 function but a SSE2 function can't inline a SSE4
5120 function. */
5125 /* See if we have the same non-isa options. */
5129 /* See if arch, tune, etc. are the same. */
5142 else
5144 }
5147 }
5149 \f
5150 /* Remember the last target of ix86_set_current_function. */
5153 /* Set targets globals to the default (or current #pragma GCC target
5154 if active). Invalidate ix86_previous_fndecl cache. */
5156 void
5158 {
5165 else
5168 }
5170 /* Establish appropriate back-end context for processing the function
5171 FNDECL. The argument might be NULL to indicate processing at top
5172 level, outside of any function scope. */
5173 static void
5175 {
5176 /* Only change the context if the function changes. This hook is called
5177 several times in the course of compiling a function, and we don't want to
5178 slow things down too much or call target_reinit when it isn't safe. */
5182 tree old_tree;
5187 else
5191 {
5195 }
5202 {
5208 else
5210 }
5212 }
5214 \f
5215 /* Return true if this goes in large data/bss. */
5217 static bool
5219 {
5223 /* Functions are never large data. */
5227 /* Automatic variables are never large data. */
5232 {
5238 }
5239 else
5240 {
5243 /* If this is an incomplete type with size 0, then we can't put it
5244 in data because it might be too big when completed. Also,
5245 int_size_in_bytes returns -1 if size can vary or is larger than
5246 an integer in which case also it is safer to assume that it goes in
5247 large data. */
5250 }
5253 }
5255 /* Switch to the appropriate section for output of DECL.
5256 DECL is either a `VAR_DECL' node or a constant of some sort.
5257 RELOC indicates whether forming the initial value of DECL requires
5258 link-time relocations. */
5263 {
5265 {
5269 {
5303 /* We don't split these for medium model. Place them into
5304 default sections and hope for best. */
5306 }
5308 {
5309 /* We might get called with string constants, but get_named_section
5310 doesn't like them as they are not DECLs. Also, we need to set
5311 flags in that case. */
5315 }
5316 }
5318 }
5320 /* Select a set of attributes for section NAME based on the properties
5321 of DECL and whether or not RELOC indicates that DECL's initializer
5322 might contain runtime relocations. */
5324 static unsigned int ATTRIBUTE_UNUSED
5326 {
5340 }
5342 /* Build up a unique section name, expressed as a
5343 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5344 RELOC indicates whether the initial value of EXP requires
5345 link-time relocations. */
5347 static void ATTRIBUTE_UNUSED
5349 {
5351 {
5353 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5357 {
5381 /* We don't split these for medium model. Place them into
5382 default sections and hope for best. */
5384 }
5386 {
5393 /* If we're using one_only, then there needs to be a .gnu.linkonce
5394 prefix to the section name. */
5401 }
5402 }
5404 }
5406 #ifdef COMMON_ASM_OP
5407 /* This says how to output assembler code to declare an
5408 uninitialized external linkage data object.
5410 For medium model x86-64 we need to use .largecomm opcode for
5411 large objects. */
5412 void
5416 {
5420 else
5425 }
5426 #endif
5428 /* Utility function for targets to use in implementing
5429 ASM_OUTPUT_ALIGNED_BSS. */
5431 void
5434 {
5438 else
5441 #ifdef ASM_DECLARE_OBJECT_NAME
5444 #else
5445 /* Standard thing is just output label for the object. */
5449 }
5450 \f
5451 /* Decide whether we must probe the stack before any space allocation
5452 on this target. It's essentially TARGET_STACK_PROBE except when
5453 -fstack-check causes the stack to be already probed differently. */
5455 bool
5457 {
5458 /* Do not probe the stack twice if static stack checking is enabled. */
5463 }
5464 \f
5465 /* Decide whether we can make a sibling call to a function. DECL is the
5466 declaration of the function being targeted by the call and EXP is the
5467 CALL_EXPR representing the call. */
5469 static bool
5471 {
5475 /* If we are generating position-independent code, we cannot sibcall
5476 optimize any indirect call, or a direct call to a global function,
5477 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5479 && !TARGET_64BIT
5480 && flag_pic
5484 /* If we need to align the outgoing stack, then sibcalling would
5485 unalign the stack, which may break the called function. */
5491 {
5494 }
5495 else
5496 {
5497 /* We're looking at the CALL_EXPR, we need the type of the function. */
5502 }
5504 /* Check that the return value locations are the same. Like
5505 if we are returning floats on the 80387 register stack, we cannot
5506 make a sibcall from a function that doesn't return a float to a
5507 function that does or, conversely, from a function that does return
5508 a float to a function that doesn't; the necessary stack adjustment
5509 would not be executed. This is also the place we notice
5510 differences in the return value ABI. Note that it is ok for one
5511 of the functions to have void return type as long as the return
5512 value of the other is passed in a register. */
5517 {
5520 }
5522 ;
5527 {
5528 /* The SYSV ABI has more call-clobbered registers;
5529 disallow sibcalls from MS to SYSV. */
5533 }
5534 else
5535 {
5536 /* If this call is indirect, we'll need to be able to use a
5537 call-clobbered register for the address of the target function.
5538 Make sure that all such registers are not used for passing
5539 parameters. Note that DLLIMPORT functions are indirect. */
5542 {
5544 {
5545 /* ??? Need to count the actual number of registers to be used,
5546 not the possible number of registers. Fix later. */
5548 }
5549 }
5550 }
5552 /* Otherwise okay. That also includes certain types of indirect calls. */
5554 }
5556 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5557 and "sseregparm" calling convention attributes;
5558 arguments as in struct attribute_spec.handler. */
5560 static tree
5562 tree args,
5565 {
5570 {
5572 name);
5575 }
5577 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5579 {
5580 tree cst;
5583 {
5585 }
5588 {
5590 }
5594 {
5597 name);
5599 }
5601 {
5605 }
5608 }
5611 {
5612 /* Do not warn when emulating the MS ABI. */
5617 name);
5620 }
5622 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5624 {
5626 {
5628 }
5630 {
5632 }
5634 {
5636 }
5638 {
5640 }
5641 }
5643 /* Can combine stdcall with fastcall (redundant), regparm and
5644 sseregparm. */
5646 {
5648 {
5650 }
5652 {
5654 }
5656 {
5658 }
5659 }
5661 /* Can combine cdecl with regparm and sseregparm. */
5663 {
5665 {
5667 }
5669 {
5671 }
5673 {
5675 }
5676 }
5678 {
5681 name);
5683 {
5685 }
5687 {
5689 }
5691 {
5693 }
5694 }
5696 /* Can combine sseregparm with all attributes. */
5699 }
5701 /* The transactional memory builtins are implicitly regparm or fastcall
5702 depending on the ABI. Override the generic do-nothing attribute that
5703 these builtins were declared with, and replace it with one of the two
5704 attributes that we expect elsewhere. */
5706 static tree
5709 {
5710 tree alt;
5712 /* In no case do we want to add the placeholder attribute. */
5715 /* The 64-bit ABI is unchanged for transactional memory. */
5719 /* ??? Is there a better way to validate 32-bit windows? We have
5720 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5723 else
5724 {
5727 }
5731 }
5733 /* This function determines from TYPE the calling-convention. */
5735 unsigned int
5737 {
5740 tree attrs;
5747 {
5757 /* Regparam isn't allowed for thiscall and fastcall. */
5759 {
5764 }
5768 }
5775 || is_stdarg
5781 }
5783 /* Return 0 if the attributes for two types are incompatible, 1 if they
5784 are compatible, and 2 if they are nearly compatible (which causes a
5785 warning to be generated). */
5787 static int
5789 {
5805 }
5806 \f
5807 /* Return the regparm value for a function with the indicated TYPE and DECL.
5808 DECL may be NULL when calling function indirectly
5809 or considering a libcall. */
5811 static int
5813 {
5814 tree attr;
5825 {
5828 {
5831 }
5832 }
5838 /* Use register calling convention for local functions when possible. */
5841 {
5846 /* Caller and callee must agree on the calling convention, so
5847 checking here just optimize means that with
5848 __attribute__((optimize (...))) caller could use regparm convention
5849 and callee not, or vice versa. Instead look at whether the callee
5850 is optimized or not. */
5853 {
5856 {
5859 /* Make sure no regparm register is taken by a
5860 fixed register variable. */
5862 local_regparm++)
5866 /* We don't want to use regparm(3) for nested functions as
5867 these use a static chain pointer in the third argument. */
5871 /* Save a register for the split stack. */
5875 /* Each fixed register usage increases register pressure,
5876 so less registers should be used for argument passing.
5877 This functionality can be overriden by an explicit
5878 regparm value. */
5881 globals++;
5883 local_regparm
5888 }
5889 }
5890 }
5893 }
5895 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5896 DFmode (2) arguments in SSE registers for a function with the
5897 indicated TYPE and DECL. DECL may be NULL when calling function
5898 indirectly or considering a libcall. Otherwise return 0. */
5900 static int
5902 {
5905 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5906 by the sseregparm attribute. */
5909 {
5911 {
5913 {
5917 else
5920 }
5922 }
5925 }
5934 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5935 (and DFmode for SSE2) arguments in SSE registers. */
5937 /* TARGET_SSE_MATH */
5941 {
5944 {
5945 /* Refuse to produce wrong code when local function with SSE enabled
5946 is called from SSE disabled function.
5947 We may work hard to work out these scenarios but hopefully
5948 it doesnot matter in practice. */
5950 {
5954 }
5957 }
5958 }
5961 }
5963 /* Return true if EAX is live at the start of the function. Used by
5964 ix86_expand_prologue to determine if we need special help before
5965 calling allocate_stack_worker. */
5967 static bool
5969 {
5970 /* Cheat. Don't bother working forward from ix86_function_regparm
5971 to the function type to whether an actual argument is located in
5972 eax. Instead just look at cfg info, which is still close enough
5973 to correct at this point. This gives false positives for broken
5974 functions that might use uninitialized data that happens to be
5975 allocated in eax, but who cares? */
5977 }
5979 static bool
5981 {
5982 tree attr;
5985 {
5991 /* For 32-bit MS-ABI the default is to keep aggregate
5992 return pointer. */
5995 }
5997 }
5999 /* Value is the number of bytes of arguments automatically
6000 popped when returning from a subroutine call.
6001 FUNDECL is the declaration node of the function (as a tree),
6002 FUNTYPE is the data type of the function (as a tree),
6003 or for a library call it is an identifier node for the subroutine name.
6004 SIZE is the number of bytes of arguments passed on the stack.
6006 On the 80386, the RTD insn may be used to pop them if the number
6007 of args is fixed, but if the number is variable then the caller
6008 must pop them all. RTD can't be used for library calls now
6009 because the library is compiled with the Unix compiler.
6010 Use of RTD is a selectable option, since it is incompatible with
6011 standard Unix calling sequences. If the option is not selected,
6012 the caller must always pop the args.
6014 The attribute stdcall is equivalent to RTD on a per module basis. */
6016 static int
6018 {
6021 /* None of the 64-bit ABIs pop arguments. */
6032 /* Lose any fake structure return argument if it is passed on the stack. */
6035 {
6039 }
6042 }
6044 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
6046 static bool
6048 {
6049 /* Check operand constraints in case hard registers were propagated
6050 into insn pattern. This check prevents combine pass from
6051 generating insn patterns with invalid hard register operands.
6052 These invalid insns can eventually confuse reload to error out
6053 with a spill failure. See also PRs 46829 and 46843. */
6055 {
6064 {
6072 /* For pre-AVX disallow unaligned loads/stores where the
6073 instructions don't support it. */
6077 {
6081 }
6083 /* A unary operator may be accepted by the predicate, but it
6084 is irrelevant for matching constraints. */
6089 {
6097 }
6104 /* Operand has no constraints, anything is OK. */
6109 {
6114 && operands_match_p
6118 {
6121 }
6122 }
6126 }
6127 }
6130 }
6131 \f
6132 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
6134 static unsigned HOST_WIDE_INT
6136 {
6140 }
6141 \f
6142 /* Argument support functions. */
6144 /* Return true when register may be used to pass function parameters. */
6145 bool
6147 {
6155 {
6159 else
6165 }
6171 /* TODO: The function should depend on current function ABI but
6172 builtins.c would need updating then. Therefore we use the
6173 default ABI. */
6175 /* RAX is used as hidden argument to va_arg functions. */
6181 else
6188 }
6190 /* Return if we do not know how to pass TYPE solely in registers. */
6192 static bool
6194 {
6198 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
6199 The layout_type routine is crafty and tries to trick us into passing
6200 currently unsupported vector types on the stack by using TImode. */
6203 }
6205 /* It returns the size, in bytes, of the area reserved for arguments passed
6206 in registers for the function represented by fndecl dependent to the used
6207 abi format. */
6208 int
6210 {
6214 else
6219 }
6221 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
6222 call abi used. */
6223 enum calling_abi
6225 {
6227 {
6230 {
6232 {
6234 {
6237 {
6240 }
6241 }
6243 }
6244 }
6248 }
6250 }
6252 /* We add this as a workaround in order to use libc_has_function
6253 hook in i386.md. */
6254 bool
6256 {
6258 }
6260 static bool
6262 {
6264 {
6268 else
6270 }
6272 }
6274 static enum calling_abi
6276 {
6280 }
6282 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6283 call abi used. */
6284 enum calling_abi
6286 {
6290 }
6292 /* Write the extra assembler code needed to declare a function properly. */
6294 void
6296 tree decl)
6297 {
6301 {
6307 }
6309 #ifdef SUBTARGET_ASM_UNWIND_INIT
6311 #endif
6315 /* Output magic byte marker, if hot-patch attribute is set. */
6317 {
6319 {
6320 /* leaq [%rsp + 0], %rsp */
6323 }
6324 else
6325 {
6326 /* movl.s %edi, %edi
6327 push %ebp
6328 movl.s %esp, %ebp */
6331 }
6332 }
6333 }
6335 /* regclass.c */
6338 /* Implementation of call abi switching target hook. Specific to FNDECL
6339 the specific call register sets are set. See also
6340 ix86_conditional_register_usage for more details. */
6341 void
6343 {
6346 else
6348 }
6350 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6351 expensive re-initialization of init_regs each time we switch function context
6352 since this is needed only during RTL expansion. */
6353 static void
6355 {
6359 }
6361 /* Return 1 if pseudo register should be created and used to hold
6362 GOT address for PIC code. */
6363 bool
6365 {
6372 }
6374 /* Initialize large model PIC register. */
6376 static void
6378 {
6380 rtx tmp_reg;
6389 label));
6393 }
6395 /* Create and initialize PIC register if required. */
6396 static void
6398 {
6399 edge entry_edge;
6408 {
6411 else
6413 }
6414 else
6415 {
6416 /* If there is future mcount call in the function it is more profitable
6417 to emit SET_GOT into ABI defined REAL_PIC_OFFSET_TABLE_REGNUM. */
6426 }
6434 }
6436 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6437 for a call to a function whose data type is FNTYPE.
6438 For a library call, FNTYPE is 0. */
6440 void
6444 tree fndecl,
6446 {
6453 {
6456 {
6460 }
6461 else
6463 }
6464 else
6469 /* Set up the number of registers to use for passing arguments. */
6472 {
6474 ? X86_64_REGPARM_MAX
6476 }
6478 {
6481 {
6483 ? X86_64_SSE_REGPARM_MAX
6485 }
6486 }
6494 /* Because type might mismatch in between caller and callee, we need to
6495 use actual type of function for local calls.
6496 FIXME: cgraph_analyze can be told to actually record if function uses
6497 va_start so for local functions maybe_vaarg can be made aggressive
6498 helping K&R code.
6499 FIXME: once typesytem is fixed, we won't need this code anymore. */
6512 {
6513 /* If there are variable arguments, then we won't pass anything
6514 in registers in 32-bit mode. */
6516 {
6525 }
6527 /* Use ecx and edx registers if function has fastcall attribute,
6528 else look for regparm information. */
6530 {
6533 {
6536 }
6538 {
6541 }
6542 else
6544 }
6546 /* Set up the number of SSE registers used for passing SFmode
6547 and DFmode arguments. Warn for mismatching ABI. */
6549 }
6550 }
6552 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6553 But in the case of vector types, it is some vector mode.
6555 When we have only some of our vector isa extensions enabled, then there
6556 are some modes for which vector_mode_supported_p is false. For these
6557 modes, the generic vector support in gcc will choose some non-vector mode
6558 in order to implement the type. By computing the natural mode, we'll
6559 select the proper ABI location for the operand and not depend on whatever
6560 the middle-end decides to do with these vector types.
6562 The midde-end can't deal with the vector types > 16 bytes. In this
6563 case, we return the original mode and warn ABI change if CUM isn't
6564 NULL.
6566 If INT_RETURN is true, warn ABI change if the vector mode isn't
6567 available for function return value. */
6569 static machine_mode
6572 {
6576 {
6579 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6581 {
6586 else
6589 /* Get the mode which has this inner mode and number of units. */
6593 {
6595 {
6600 {
6604 }
6606 {
6610 }
6613 }
6615 {
6620 {
6624 }
6626 {
6630 }
6633 }
6636 {
6641 {
6645 }
6647 {
6651 }
6652 }
6654 {
6659 {
6663 }
6665 {
6669 }
6670 }
6672 }
6675 }
6676 }
6679 }
6681 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6682 this may not agree with the mode that the type system has chosen for the
6683 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6684 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6686 static rtx
6689 {
6690 rtx tmp;
6694 else
6695 {
6699 }
6702 }
6704 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6705 of this code is to classify each 8bytes of incoming argument by the register
6706 class and assign registers accordingly. */
6708 /* Return the union class of CLASS1 and CLASS2.
6709 See the x86-64 PS ABI for details. */
6711 static enum x86_64_reg_class
6713 {
6714 /* Rule #1: If both classes are equal, this is the resulting class. */
6718 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6719 the other class. */
6725 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6729 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6737 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6738 MEMORY is used. */
6747 /* Rule #6: Otherwise class SSE is used. */
6749 }
6751 /* Classify the argument of type TYPE and mode MODE.
6752 CLASSES will be filled by the register class used to pass each word
6753 of the operand. The number of words is returned. In case the parameter
6754 should be passed in memory, 0 is returned. As a special case for zero
6755 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6757 BIT_OFFSET is used internally for handling records and specifies offset
6758 of the offset in bits modulo 512 to avoid overflow cases.
6760 See the x86-64 PS ABI for details.
6761 */
6763 static int
6766 {
6767 HOST_WIDE_INT bytes =
6769 int words
6772 /* Variable sized entities are always passed/returned in memory. */
6781 {
6783 tree field;
6786 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6793 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6794 signalize memory class, so handle it as special case. */
6796 {
6799 }
6801 /* Classify each field of record and merge classes. */
6803 {
6805 /* And now merge the fields of structure. */
6807 {
6809 {
6815 /* Bitfields are always classified as integer. Handle them
6816 early, since later code would consider them to be
6817 misaligned integers. */
6819 {
6828 }
6829 else
6830 {
6835 /* Flexible array member is ignored. */
6842 {
6846 {
6849 "the ABI of passing struct with"
6850 " a flexible array member has"
6852 }
6854 }
6856 subclasses,
6866 }
6867 }
6868 }
6872 /* Arrays are handled as small records. */
6873 {
6880 /* The partial classes are now full classes. */
6891 }
6894 /* Unions are similar to RECORD_TYPE but offset is always 0.
6895 */
6897 {
6899 {
6907 bit_offset);
6912 }
6913 }
6918 }
6921 {
6922 /* When size > 16 bytes, if the first one isn't
6923 X86_64_SSE_CLASS or any other ones aren't
6924 X86_64_SSEUP_CLASS, everything should be passed in
6925 memory. */
6932 }
6934 /* Final merger cleanup. */
6936 {
6937 /* If one class is MEMORY, everything should be passed in
6938 memory. */
6942 /* The X86_64_SSEUP_CLASS should be always preceded by
6943 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6947 {
6948 /* The first one should never be X86_64_SSEUP_CLASS. */
6951 }
6953 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6954 everything should be passed in memory. */
6957 {
6960 /* The first one should never be X86_64_X87UP_CLASS. */
6963 {
6966 "the ABI of passing union with long double"
6968 }
6970 }
6971 }
6973 }
6975 /* Compute alignment needed. We align all types to natural boundaries with
6976 exception of XFmode that is aligned to 64bits. */
6978 {
6987 /* Misaligned fields are always returned in memory. */
6990 }
6992 /* for V1xx modes, just use the base mode */
6997 /* Classification of atomic types. */
6999 {
7015 {
7018 /* Analyze last 128 bits only. */
7022 {
7025 }
7027 {
7030 }
7032 {
7036 }
7038 {
7041 }
7042 else
7044 }
7051 /* OImode shouldn't be used directly. */
7058 else
7076 else
7077 {
7081 {
7084 "the ABI of passing structure with complex float"
7086 }
7089 }
7098 /* This modes is larger than 16 bytes. */
7156 else
7160 }
7161 }
7163 /* Examine the argument and return set number of register required in each
7164 class. Return true iff parameter should be passed in memory. */
7166 static bool
7169 {
7180 {
7201 }
7204 }
7206 /* Construct container for the argument used by GCC interface. See
7207 FUNCTION_ARG for the detailed description. */
7209 static rtx
7213 {
7214 /* The following variables hold the static issued_error state. */
7219 machine_mode tmpmode;
7228 rtx ret;
7239 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
7240 some less clueful developer tries to use floating-point anyway. */
7242 {
7244 {
7246 {
7249 }
7250 }
7252 {
7255 }
7257 }
7259 /* Likewise, error if the ABI requires us to return values in the
7260 x87 registers and the user specified -mno-80387. */
7266 {
7268 {
7271 }
7273 }
7275 /* First construct simple cases. Avoid SCmode, since we want to use
7276 single register to pass this type. */
7279 {
7294 /* Zero sized array, struct or class. */
7298 }
7337 /* Otherwise figure out the entries of the PARALLEL. */
7339 {
7343 {
7348 /* Merge TImodes on aligned occasions here too. */
7350 tmpmode
7354 else
7356 /* We've requested 24 bytes we
7357 don't have mode for. Use DImode. */
7364 intreg++;
7372 sse_regno++;
7380 sse_regno++;
7385 {
7391 {
7393 i++;
7394 }
7395 else
7420 }
7426 sse_regno++;
7430 }
7431 }
7433 /* Empty aligned struct, union or class. */
7441 }
7443 /* Update the data in CUM to advance over an argument of mode MODE
7444 and data type TYPE. (TYPE is null for libcalls where that information
7445 may not be available.)
7447 Return a number of integer regsiters advanced over. */
7449 static int
7452 HOST_WIDE_INT words)
7453 {
7457 {
7464 /* FALLTHRU */
7476 {
7479 }
7483 /* OImode shouldn't be used directly. */
7492 /* FALLTHRU */
7514 {
7519 {
7522 }
7523 }
7533 {
7538 {
7541 }
7542 }
7544 }
7547 }
7549 static int
7552 {
7555 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7562 {
7568 }
7569 else
7570 {
7575 }
7576 }
7578 static int
7580 HOST_WIDE_INT words)
7581 {
7582 /* Otherwise, this should be passed indirect. */
7587 {
7591 }
7593 }
7595 /* Update the data in CUM to advance over an argument of mode MODE and
7596 data type TYPE. (TYPE is null for libcalls where that information
7597 may not be available.) */
7599 static void
7602 {
7609 else
7618 {
7619 /* If we pass bounds in BT then just update remained bounds count. */
7621 {
7624 }
7626 /* Update remained number of bounds to force. */
7633 }
7635 /* The first arg not going to Bounds Tables resets this counter. */
7637 /* For unnamed args we always pass bounds to avoid bounds mess when
7638 passed and received types do not match. If bounds do not follow
7639 unnamed arg, still pretend required number of bounds were passed. */
7641 {
7644 }
7650 else
7653 /* For stdarg we expect bounds to be passed for each value passed
7654 in register. */
7657 /* For pointers passed in memory we expect bounds passed in Bounds
7658 Table. */
7661 }
7663 /* Define where to put the arguments to a function.
7664 Value is zero to push the argument on the stack,
7665 or a hard register in which to store the argument.
7667 MODE is the argument's machine mode.
7668 TYPE is the data type of the argument (as a tree).
7669 This is null for libcalls where that information may
7670 not be available.
7671 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7672 the preceding args and about the function being called.
7673 NAMED is nonzero if this argument is a named parameter
7674 (otherwise it is an extra parameter matching an ellipsis). */
7676 static rtx
7680 {
7681 /* Avoid the AL settings for the Unix64 ABI. */
7686 {
7693 /* FALLTHRU */
7699 {
7702 /* Fastcall allocates the first two DWORD (SImode) or
7703 smaller arguments to ECX and EDX if it isn't an
7704 aggregate type . */
7706 {
7712 /* ECX not EAX is the first allocated register. */
7715 }
7717 }
7726 /* FALLTHRU */
7728 /* In 32bit, we pass TImode in xmm registers. */
7736 {
7740 }
7745 /* OImode and XImode shouldn't be used directly. */
7761 {
7765 }
7775 {
7779 }
7781 }
7784 }
7786 static rtx
7789 {
7790 /* Handle a hidden AL argument containing number of registers
7791 for varargs x86-64 functions. */
7795 ? X86_64_SSE_REGPARM_MAX
7800 {
7816 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7820 }
7826 }
7828 static rtx
7831 HOST_WIDE_INT bytes)
7832 {
7835 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7836 We use value of -2 to specify that current function call is MSABI. */
7840 /* If we've run out of registers, it goes on the stack. */
7846 /* Only floating point modes are passed in anything but integer regs. */
7848 {
7851 else
7852 {
7855 /* Unnamed floating parameters are passed in both the
7856 SSE and integer registers. */
7862 }
7863 }
7864 /* Handle aggregated types passed in register. */
7866 {
7871 }
7874 }
7876 /* Return where to put the arguments to a function.
7877 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7879 MODE is the argument's machine mode. TYPE is the data type of the
7880 argument. It is null for libcalls where that information may not be
7881 available. CUM gives information about the preceding args and about
7882 the function being called. NAMED is nonzero if this argument is a
7883 named parameter (otherwise it is an extra parameter matching an
7884 ellipsis). */
7886 static rtx
7889 {
7893 rtx arg;
7895 /* All pointer bounds argumntas are handled separately here. */
7898 {
7899 /* Return NULL if bounds are forced to go in Bounds Table. */
7902 /* Return the next available bound reg if any. */
7905 /* Return the next special slot number otherwise. */
7906 else
7910 }
7914 else
7918 /* To simplify the code below, represent vector types with a vector mode
7919 even if MMX/SSE are not active. */
7927 else
7931 }
7933 /* A C expression that indicates when an argument must be passed by
7934 reference. If nonzero for an argument, a copy of that argument is
7935 made in memory and a pointer to the argument is passed instead of
7936 the argument itself. The pointer is passed in whatever way is
7937 appropriate for passing a pointer to that type. */
7939 static bool
7942 {
7945 /* Bounds are never passed by reference. */
7950 /* See Windows x64 Software Convention. */
7952 {
7955 {
7956 /* Arrays are passed by reference. */
7961 {
7962 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7963 are passed by reference. */
7965 }
7966 }
7968 /* __m128 is passed by reference. */
7974 }
7975 }
7980 }
7982 /* Return true when TYPE should be 128bit aligned for 32bit argument
7983 passing ABI. XXX: This function is obsolete and is only used for
7984 checking psABI compatibility with previous versions of GCC. */
7986 static bool
7988 {
8000 {
8001 /* Walk the aggregates recursively. */
8003 {
8007 {
8008 tree field;
8010 /* Walk all the structure fields. */
8012 {
8016 }
8018 }
8021 /* Just for use if some languages passes arrays by value. */
8028 }
8029 }
8031 }
8033 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
8034 XXX: This function is obsolete and is only used for checking psABI
8035 compatibility with previous versions of GCC. */
8037 static unsigned int
8040 {
8041 /* In 32bit, only _Decimal128 and __float128 are aligned to their
8042 natural boundaries. */
8044 {
8045 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
8046 make an exception for SSE modes since these require 128bit
8047 alignment.
8049 The handling here differs from field_alignment. ICC aligns MMX
8050 arguments to 4 byte boundaries, while structure fields are aligned
8051 to 8 byte boundaries. */
8053 {
8056 }
8057 else
8058 {
8061 }
8062 }
8066 }
8068 /* Return true when TYPE should be 128bit aligned for 32bit argument
8069 passing ABI. */
8071 static bool
8073 {
8083 {
8084 /* Walk the aggregates recursively. */
8086 {
8090 {
8091 tree field;
8093 /* Walk all the structure fields. */
8095 field;
8097 {
8101 }
8103 }
8106 /* Just for use if some languages passes arrays by value. */
8113 }
8114 }
8115 else
8119 }
8121 /* Gives the alignment boundary, in bits, of an argument with the
8122 specified mode and type. */
8124 static unsigned int
8126 {
8129 {
8130 /* Since the main variant type is used for call, we convert it to
8131 the main variant type. */
8134 }
8135 else
8139 else
8140 {
8145 {
8146 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
8148 {
8151 }
8157 }
8160 && !warned
8162 saved_align))
8163 {
8166 "The ABI for passing parameters with %d-byte"
8169 }
8170 }
8173 }
8175 /* Return true if N is a possible register number of function value. */
8177 static bool
8179 {
8181 {
8193 /* Complex values are returned in %st(0)/%st(1) pair. */
8196 /* TODO: The function should depend on current function ABI but
8197 builtins.c would need updating then. Therefore we use the
8198 default ABI. */
8203 /* Complex values are returned in %xmm0/%xmm1 pair. */
8212 }
8215 }
8217 /* Define how to find the value returned by a function.
8218 VALTYPE is the data type of the value (as a tree).
8219 If the precise function being called is known, FUNC is its FUNCTION_DECL;
8220 otherwise, FUNC is 0. */
8222 static rtx
8225 {
8228 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
8229 we normally prevent this case when mmx is not available. However
8230 some ABIs may require the result to be returned like DImode. */
8234 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
8235 we prevent this case when sse is not available. However some ABIs
8236 may require the result to be returned like integer TImode. */
8241 /* 32-byte vector modes in %ymm0. */
8245 /* 64-byte vector modes in %zmm0. */
8249 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
8252 else
8253 /* Most things go in %eax. */
8256 /* Override FP return register with %xmm0 for local functions when
8257 SSE math is enabled or for functions with sseregparm attribute. */
8259 {
8264 }
8266 /* OImode shouldn't be used directly. */
8270 }
8272 static rtx
8274 const_tree valtype)
8275 {
8276 rtx ret;
8278 /* Handle libcalls, which don't provide a type node. */
8280 {
8284 {
8303 }
8306 }
8308 {
8309 /* Pointers are always returned in word_mode. */
8311 }
8317 /* For zero sized structures, construct_container returns NULL, but we
8318 need to keep rest of compiler happy by returning meaningful value. */
8323 }
8325 static rtx
8327 const_tree valtype)
8328 {
8332 {
8334 {
8353 }
8354 }
8356 }
8358 static rtx
8361 {
8376 else
8378 }
8380 static rtx
8382 {
8388 }
8390 /* Return an RTX representing a place where a function returns
8391 or recieves pointer bounds or NULL if no bounds are returned.
8393 VALTYPE is a data type of a value returned by the function.
8395 FN_DECL_OR_TYPE is a tree node representing FUNCTION_DECL
8396 or FUNCTION_TYPE of the function.
8398 If OUTGOING is false, return a place in which the caller will
8399 see the return value. Otherwise, return a place where a
8400 function returns a value. */
8402 static rtx
8404 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
8406 {
8412 {
8413 bitmap slots;
8415 bitmap_iterator bi;
8423 {
8428 }
8434 }
8435 else
8439 }
8441 /* Pointer function arguments and return values are promoted to
8442 word_mode. */
8444 static machine_mode
8448 {
8450 {
8453 }
8455 for_return);
8456 }
8458 /* Return true if a structure, union or array with MODE containing FIELD
8459 should be accessed using BLKmode. */
8461 static bool
8463 {
8464 /* Union with XFmode must be in BLKmode. */
8468 }
8470 rtx
8472 {
8474 }
8476 /* Return true iff type is returned in memory. */
8478 static bool
8480 {
8481 #ifdef SUBTARGET_RETURN_IN_MEMORY
8483 #else
8485 HOST_WIDE_INT size;
8491 {
8493 {
8496 /* __m128 is returned in xmm0. */
8505 /* Otherwise, the size must be exactly in [1248]. */
8507 }
8508 else
8509 {
8514 }
8515 }
8516 else
8517 {
8527 {
8528 /* User-created vectors small enough to fit in EAX. */
8532 /* Unless ABI prescibes otherwise,
8533 MMX/3dNow values are returned in MM0 if available. */
8538 /* SSE values are returned in XMM0 if available. */
8542 /* AVX values are returned in YMM0 if available. */
8546 /* AVX512F values are returned in ZMM0 if available. */
8549 }
8557 /* OImode shouldn't be used directly. */
8561 }
8562 #endif
8563 }
8565 \f
8566 /* Create the va_list data type. */
8568 /* Returns the calling convention specific va_list date type.
8569 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8571 static tree
8573 {
8576 /* For i386 we use plain pointer to argument area. */
8586 unsigned_type_node);
8589 unsigned_type_node);
8592 ptr_type_node);
8595 ptr_type_node);
8614 /* The correct type is an array type of one element. */
8616 }
8618 /* Setup the builtin va_list data type and for 64-bit the additional
8619 calling convention specific va_list data types. */
8621 static tree
8623 {
8626 /* Initialize abi specific va_list builtin types. */
8628 {
8629 tree t;
8631 {
8636 }
8637 else
8638 {
8643 }
8645 {
8650 }
8651 else
8652 {
8657 }
8658 }
8661 }
8663 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8665 static void
8667 {
8669 alias_set_type set;
8672 /* GPR size of varargs save area. */
8675 else
8678 /* FPR size of varargs save area. We don't need it if we don't pass
8679 anything in SSE registers. */
8682 else
8696 {
8704 }
8707 {
8708 machine_mode smode;
8710 rtx test;
8712 /* Now emit code to save SSE registers. The AX parameter contains number
8713 of SSE parameter registers used to call this function, though all we
8714 actually check here is the zero/non-zero status. */
8719 label));
8721 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8722 we used movdqa (i.e. TImode) instead? Perhaps even better would
8723 be if we could determine the real mode of the data, via a hook
8724 into pass_stdarg. Ignore all that for now. */
8734 {
8743 }
8746 }
8747 }
8749 static void
8751 {
8755 /* Reset to zero, as there might be a sysv vaarg used
8756 before. */
8761 {
8772 }
8773 }
8775 static void
8778 {
8780 CUMULATIVE_ARGS next_cum;
8781 tree fntype;
8783 /* This argument doesn't appear to be used anymore. Which is good,
8784 because the old code here didn't suppress rtl generation. */
8792 /* For varargs, we do not want to skip the dummy va_dcl argument.
8793 For stdargs, we do want to skip the last named argument. */
8801 else
8803 }
8805 static void
8808 tree type,
8811 {
8813 CUMULATIVE_ARGS next_cum;
8814 tree fntype;
8815 rtx save_area;
8820 /* Do nothing if we use plain pointer to argument area. */
8826 /* For varargs, we do not want to skip the dummy va_dcl argument.
8827 For stdargs, we do want to skip the last named argument. */
8841 {
8846 rtx bounds;
8850 else
8851 {
8852 rtx ldx_addr =
8859 }
8865 bnd_reg++;
8866 }
8867 }
8870 /* Checks if TYPE is of kind va_list char *. */
8872 static bool
8874 {
8875 tree canonic;
8877 /* For 32-bit it is always true. */
8883 }
8885 /* Implement va_start. */
8887 static void
8889 {
8893 tree type;
8894 rtx ovf_rtx;
8898 {
8901 /* When we are splitting the stack, we can't refer to the stack
8902 arguments using internal_arg_pointer, because they may be on
8903 the old stack. The split stack prologue will arrange to
8904 leave a pointer to the old stack arguments in a scratch
8905 register, which we here copy to a pseudo-register. The split
8906 stack prologue can't set the pseudo-register directly because
8907 it (the prologue) runs before any registers have been saved. */
8911 {
8912 rtx reg;
8926 }
8927 }
8929 /* Only 64bit target needs something special. */
8931 {
8934 else
8935 {
8945 /* Store zero bounds for va_list. */
8949 next));
8951 }
8953 }
8962 /* The following should be folded into the MEM_REF offset. */
8972 /* Count number of gp and fp argument registers used. */
8978 {
8984 }
8987 {
8993 }
8995 /* Find the overflow area. */
8999 else
9005 /* Store zero bounds for overflow area pointer. */
9014 {
9015 /* Find the register save area.
9016 Prologue of the function save it right above stack frame. */
9022 /* Store zero bounds for save area pointer. */
9029 }
9030 }
9032 /* Implement va_arg. */
9034 static tree
9037 {
9044 rtx container;
9046 tree ptrtype;
9047 machine_mode nat_mode;
9050 /* Only 64bit target needs something special. */
9074 {
9087 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
9089 {
9092 }
9100 }
9102 /* Pull the value out of the saved registers. */
9107 {
9121 /* In case we are passing structure, verify that it is consecutive block
9122 on the register save area. If not we need to do moves. */
9124 {
9125 /* Verify that all registers are strictly consecutive */
9127 {
9131 {
9136 }
9137 }
9138 else
9139 {
9143 {
9148 }
9149 }
9150 }
9152 {
9155 }
9156 else
9157 {
9160 }
9162 /* First ensure that we fit completely in registers. */
9164 {
9171 }
9173 {
9181 }
9183 /* Compute index to start of area used for integer regs. */
9185 {
9186 /* int_addr = gpr + sav; */
9189 }
9191 {
9192 /* sse_addr = fpr + sav; */
9195 }
9197 {
9201 /* addr = &temp; */
9206 {
9210 tree piece_type;
9211 tree addr_type;
9212 tree daddr_type;
9221 {
9226 }
9230 else
9237 {
9240 }
9241 else
9242 {
9245 }
9252 {
9257 }
9258 else
9259 {
9260 tree copy
9265 }
9267 }
9268 }
9271 {
9275 }
9278 {
9282 }
9287 }
9289 /* ... otherwise out of the overflow area. */
9291 /* When we align parameter on stack for caller, if the parameter
9292 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
9293 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
9294 here with caller. */
9299 /* Care for on-stack alignment if needed. */
9302 else
9303 {
9308 }
9325 }
9326 \f
9327 /* Return true if OPNUM's MEM should be matched
9328 in movabs* patterns. */
9330 bool
9332 {
9344 }
9345 \f
9346 /* Initialize the table of extra 80387 mathematical constants. */
9348 static void
9350 {
9352 {
9358 };
9362 {
9364 /* Ensure each constant is rounded to XFmode precision. */
9367 }
9370 }
9372 /* Return non-zero if the constant is something that
9373 can be loaded with a special instruction. */
9375 int
9377 {
9380 REAL_VALUE_TYPE r;
9392 /* For XFmode constants, try to find a special 80387 instruction when
9393 optimizing for size or on those CPUs that benefit from them. */
9396 {
9405 }
9407 /* Load of the constant -0.0 or -1.0 will be split as
9408 fldz;fchs or fld1;fchs sequence. */
9415 }
9417 /* Return the opcode of the special instruction to be used to load
9418 the constant X. */
9422 {
9424 {
9444 }
9445 }
9447 /* Return the CONST_DOUBLE representing the 80387 constant that is
9448 loaded by the specified special instruction. The argument IDX
9449 matches the return value from standard_80387_constant_p. */
9451 rtx
9453 {
9460 {
9471 }
9474 XFmode);
9475 }
9477 /* Return 1 if X is all 0s and 2 if x is all 1s
9478 in supported SSE/AVX vector mode. */
9480 int
9482 {
9483 machine_mode mode;
9494 {
9515 }
9518 }
9520 /* Return the opcode of the special instruction to be used to load
9521 the constant X. */
9525 {
9527 {
9530 {
9557 }
9567 else
9572 }
9574 }
9576 /* Returns true if OP contains a symbol reference */
9578 bool
9580 {
9589 {
9591 {
9597 }
9601 }
9604 }
9606 /* Return true if it is appropriate to emit `ret' instructions in the
9607 body of a function. Do this only if the epilogue is simple, needing a
9608 couple of insns. Prior to reloading, we can't tell how many registers
9609 must be saved, so return false then. Return false if there is no frame
9610 marker to de-allocate. */
9612 bool
9614 {
9620 /* Don't allow more than 32k pop, since that's all we can do
9621 with one instruction. */
9628 }
9629 \f
9630 /* Value should be nonzero if functions must have frame pointers.
9631 Zero means the frame pointer need not be set up (and parms may
9632 be accessed via the stack pointer) in functions that seem suitable. */
9634 static bool
9636 {
9637 /* If we accessed previous frames, then the generated code expects
9638 to be able to access the saved ebp value in our frame. */
9642 /* Several x86 os'es need a frame pointer for other reasons,
9643 usually pertaining to setjmp. */
9647 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9651 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9652 allocation is 4GB. */
9656 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9657 turns off the frame pointer by default. Turn it back on now if
9658 we've not got a leaf function. */
9668 }
9670 /* Record that the current function accesses previous call frames. */
9672 void
9674 {
9676 }
9677 \f
9678 #ifndef USE_HIDDEN_LINKONCE
9679 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9680 # define USE_HIDDEN_LINKONCE 1
9681 # else
9682 # define USE_HIDDEN_LINKONCE 0
9683 # endif
9684 #endif
9688 /* Fills in the label name that should be used for a pc thunk for
9689 the given register. */
9691 static void
9693 {
9698 else
9700 }
9703 /* This function generates code for -fpic that loads %ebx with
9704 the return address of the caller and then returns. */
9706 static void
9708 {
9713 {
9715 tree decl;
9731 #if TARGET_MACHO
9733 {
9742 }
9743 else
9744 #endif
9746 {
9757 }
9758 else
9759 {
9762 }
9768 /* Make sure unwind info is emitted for the thunk if needed. */
9771 /* Pad stack IP move with 4 instructions (two NOPs count
9772 as one instruction). */
9774 {
9779 }
9790 }
9794 }
9796 /* Emit code for the SET_GOT patterns. */
9800 {
9806 {
9807 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9812 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9813 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9814 an unadorned address. */
9819 }
9824 {
9826 /* We don't need a pic base, we're not producing pic. */
9833 }
9834 else
9835 {
9844 #if TARGET_MACHO
9845 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9846 This is what will be referenced by the Mach-O PIC subsystem. */
9850 /* When we are restoring the pic base at the site of a nonlocal label,
9851 and we decided to emit the pic base above, we will still output a
9852 local label used for calculating the correction offset (even though
9853 the offset will be 0 in that case). */
9857 #endif
9858 }
9864 }
9866 /* Generate an "push" pattern for input ARG. */
9868 static rtx
9870 {
9882 stack_pointer_rtx)),
9883 arg);
9884 }
9886 /* Generate an "pop" pattern for input ARG. */
9888 static rtx
9890 {
9897 stack_pointer_rtx)));
9898 }
9900 /* Return >= 0 if there is an unused call-clobbered register available
9901 for the entire function. */
9903 static unsigned int
9905 {
9912 {
9914 /* Can't use the same register for both PIC and DRAP. */
9917 else
9922 }
9925 }
9927 /* Return TRUE if we need to save REGNO. */
9929 static bool
9931 {
9934 {
9936 {
9937 /* REAL_PIC_OFFSET_TABLE_REGNUM used by call to
9938 _mcount in prologue. */
9941 }
9948 }
9951 {
9954 {
9960 }
9961 }
9972 }
9974 /* Return number of saved general prupose registers. */
9976 static int
9978 {
9984 nregs ++;
9986 }
9988 /* Return number of saved SSE registrers. */
9990 static int
9992 {
10000 nregs ++;
10002 }
10004 /* Given FROM and TO register numbers, say whether this elimination is
10005 allowed. If stack alignment is needed, we can only replace argument
10006 pointer with hard frame pointer, or replace frame pointer with stack
10007 pointer. Otherwise, frame pointer elimination is automatically
10008 handled and all other eliminations are valid. */
10010 static bool
10012 {
10018 else
10020 }
10022 /* Return the offset between two registers, one to be eliminated, and the other
10023 its replacement, at the start of a routine. */
10025 HOST_WIDE_INT
10027 {
10036 else
10037 {
10045 }
10046 }
10048 /* In a dynamically-aligned function, we can't know the offset from
10049 stack pointer to frame pointer, so we must ensure that setjmp
10050 eliminates fp against the hard fp (%ebp) rather than trying to
10051 index from %esp up to the top of the frame across a gap that is
10052 of unknown (at compile-time) size. */
10053 static rtx
10055 {
10057 }
10059 /* When using -fsplit-stack, the allocation routines set a field in
10060 the TCB to the bottom of the stack plus this much space, measured
10061 in bytes. */
10063 #define SPLIT_STACK_AVAILABLE 256
10065 /* Fill structure ix86_frame about frame of currently computed function. */
10067 static void
10069 {
10071 HOST_WIDE_INT offset;
10074 HOST_WIDE_INT to_allocate;
10079 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
10080 function prologues and leaf. */
10084 {
10087 }
10088 /* preferred_stack_boundary is never updated for call
10089 expanded from tls descriptor. Update it here. We don't update it in
10090 expand stage because according to the comments before
10091 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
10092 away. */
10095 {
10099 }
10108 /* For SEH we have to limit the amount of code movement into the prologue.
10109 At present we do this via a BLOCKAGE, at which point there's very little
10110 scheduling that can be done, which means that there's very little point
10111 in doing anything except PUSHs. */
10115 /* During reload iteration the amount of registers saved can change.
10116 Recompute the value as needed. Do not recompute when amount of registers
10117 didn't change as reload does multiple calls to the function and does not
10118 expect the decision to change within single iteration. */
10121 {
10127 /* The fast prologue uses move instead of push to save registers. This
10128 is significantly longer, but also executes faster as modern hardware
10129 can execute the moves in parallel, but can't do that for push/pop.
10131 Be careful about choosing what prologue to emit: When function takes
10132 many instructions to execute we may use slow version as well as in
10133 case function is known to be outside hot spot (this is known with
10134 feedback only). Weight the size of function by number of registers
10135 to save as it is cheap to use one or two push instructions but very
10136 slow to use many of them. */
10140 || (flag_branch_probabilities
10143 else
10146 }
10148 frame->save_regs_using_mov
10150 /* If static stack checking is enabled and done with probes,
10151 the registers need to be saved before allocating the frame. */
10154 /* Skip return address. */
10157 /* Skip pushed static chain. */
10161 /* Skip saved base pointer. */
10166 /* The traditional frame pointer location is at the top of the frame. */
10169 /* Register save area */
10173 /* On SEH target, registers are pushed just before the frame pointer
10174 location. */
10178 /* Align and set SSE register save area. */
10180 {
10181 /* The only ABI that has saved SSE registers (Win64) also has a
10182 16-byte aligned default stack, and thus we don't need to be
10183 within the re-aligned local stack frame to save them. */
10187 }
10190 /* The re-aligned stack starts here. Values before this point are not
10191 directly comparable with values below this point. In order to make
10192 sure that no value happens to be the same before and after, force
10193 the alignment computation below to add a non-zero value. */
10197 /* Va-arg area */
10201 /* Align start of frame for local function. */
10210 /* Frame pointer points here. */
10215 /* Add outgoing arguments area. Can be skipped if we eliminated
10216 all the function calls as dead code.
10217 Skipping is however impossible when function calls alloca. Alloca
10218 expander assumes that last crtl->outgoing_args_size
10219 of stack frame are unused. */
10223 {
10226 }
10227 else
10230 /* Align stack boundary. Only needed if we're calling another function
10231 or using alloca. */
10236 /* We've reached end of stack frame. */
10239 /* Size prologue needs to allocate. */
10250 {
10256 }
10257 else
10261 /* The SEH frame pointer location is near the bottom of the frame.
10262 This is enforced by the fact that the difference between the
10263 stack pointer and the frame pointer is limited to 240 bytes in
10264 the unwind data structure. */
10266 {
10267 HOST_WIDE_INT diff;
10269 /* If we can leave the frame pointer where it is, do so. Also, returns
10270 the establisher frame for __builtin_frame_address (0). */
10275 {
10276 /* Ideally we'd determine what portion of the local stack frame
10277 (within the constraint of the lowest 240) is most heavily used.
10278 But without that complication, simply bias the frame pointer
10279 by 128 bytes so as to maximize the amount of the local stack
10280 frame that is addressable with 8-bit offsets. */
10282 }
10283 }
10284 }
10286 /* This is semi-inlined memory_address_length, but simplified
10287 since we know that we're always dealing with reg+offset, and
10288 to avoid having to create and discard all that rtl. */
10292 {
10296 {
10297 /* EBP and R13 cannot be encoded without an offset. */
10299 }
10303 /* ESP and R12 must be encoded with a SIB byte. */
10305 len++;
10308 }
10310 /* Return an RTX that points to CFA_OFFSET within the stack frame.
10311 The valid base registers are taken from CFUN->MACHINE->FS. */
10313 static rtx
10315 {
10321 {
10322 /* Choose the base register most likely to allow the most scheduling
10323 opportunities. Generally FP is valid throughout the function,
10324 while DRAP must be reloaded within the epilogue. But choose either
10325 over the SP due to increased encoding size. */
10328 {
10331 }
10333 {
10336 }
10338 {
10341 }
10342 }
10343 else
10344 {
10345 HOST_WIDE_INT toffset;
10348 /* Choose the base register with the smallest address encoding.
10349 With a tie, choose FP > DRAP > SP. */
10351 {
10355 }
10357 {
10361 {
10365 }
10366 }
10368 {
10372 {
10376 }
10377 }
10378 }
10382 }
10384 /* Emit code to save registers in the prologue. */
10386 static void
10388 {
10394 {
10397 }
10398 }
10400 /* Emit a single register save at CFA - CFA_OFFSET. */
10402 static void
10404 HOST_WIDE_INT cfa_offset)
10405 {
10413 /* For SSE saves, we need to indicate the 128-bit alignment. */
10424 /* When saving registers into a re-aligned local stack frame, avoid
10425 any tricky guessing by dwarf2out. */
10427 {
10431 {
10432 /* A bit of a hack. We force the DRAP register to be saved in
10433 the re-aligned stack frame, which provides us with a copy
10434 of the CFA that will last past the prologue. Install it. */
10440 }
10441 else
10442 {
10443 /* The frame pointer is a stable reference within the
10444 aligned frame. Use it. */
10450 }
10451 }
10453 /* The memory may not be relative to the current CFA register,
10454 which means that we may need to generate a new pattern for
10455 use by the unwind info. */
10457 {
10462 }
10463 }
10465 /* Emit code to save registers using MOV insns.
10466 First register is stored at CFA - CFA_OFFSET. */
10467 static void
10469 {
10474 {
10477 }
10478 }
10480 /* Emit code to save SSE registers using MOV insns.
10481 First register is stored at CFA - CFA_OFFSET. */
10482 static void
10484 {
10489 {
10492 }
10493 }
10497 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
10498 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
10499 Don't add the note if the previously saved value will be left untouched
10500 within stack red-zone till return, as unwinders can find the same value
10501 in the register and on the stack. */
10503 static void
10505 {
10511 {
10514 }
10515 else
10516 queued_cfa_restores
10518 }
10520 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
10522 static void
10524 {
10525 rtx last;
10529 ;
10534 }
10536 /* Expand prologue or epilogue stack adjustment.
10537 The pattern exist to put a dependency on all ebp-based memory accesses.
10538 STYLE should be negative if instructions should be marked as frame related,
10539 zero if %r11 register is live and cannot be freely used and positive
10540 otherwise. */
10542 static void
10545 {
10547 rtx insn;
10554 else
10555 {
10556 rtx tmp;
10557 /* r11 is used by indirect sibcall return as well, set before the
10558 epilogue and used after the epilogue. */
10561 else
10562 {
10566 }
10572 }
10579 {
10580 rtx r;
10590 }
10592 {
10595 {
10599 }
10600 }
10603 {
10608 {
10611 }
10613 {
10616 }
10617 else
10618 {
10619 /* Else there are two possibilities: SP itself, which we set
10620 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10621 taken care of this by hand along the eh_return path. */
10624 }
10628 }
10629 }
10631 /* Find an available register to be used as dynamic realign argument
10632 pointer regsiter. Such a register will be written in prologue and
10633 used in begin of body, so it must not be
10634 1. parameter passing register.
10635 2. GOT pointer.
10636 We reuse static-chain register if it is available. Otherwise, we
10637 use DI for i386 and R13 for x86-64. We chose R13 since it has
10638 shorter encoding.
10640 Return: the regno of chosen register. */
10642 static unsigned int
10644 {
10648 {
10649 /* Use R13 for nested function or function need static chain.
10650 Since function with tail call may use any caller-saved
10651 registers in epilogue, DRAP must not use caller-saved
10652 register in such case. */
10657 }
10658 else
10659 {
10660 /* Use DI for nested function or function need static chain.
10661 Since function with tail call may use any caller-saved
10662 registers in epilogue, DRAP must not use caller-saved
10663 register in such case. */
10667 /* Reuse static chain register if it isn't used for parameter
10668 passing. */
10670 {
10674 }
10676 }
10677 }
10679 /* Return minimum incoming stack alignment. */
10681 static unsigned int
10683 {
10686 /* Prefer the one specified at command line. */
10689 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10690 if -mstackrealign is used, it isn't used for sibcall check and
10691 estimated stack alignment is 128bit. */
10693 && !TARGET_64BIT
10694 && ix86_force_align_arg_pointer
10697 else
10700 /* Incoming stack alignment can be changed on individual functions
10701 via force_align_arg_pointer attribute. We use the smallest
10702 incoming stack boundary. */
10708 /* The incoming stack frame has to be aligned at least at
10709 parm_stack_boundary. */
10713 /* Stack at entrance of main is aligned by runtime. We use the
10714 smallest incoming stack boundary. */
10722 }
10724 /* Update incoming stack boundary and estimated stack alignment. */
10726 static void
10728 {
10729 ix86_incoming_stack_boundary
10732 /* x86_64 vararg needs 16byte stack alignment for register save
10733 area. */
10738 }
10740 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10741 needed or an rtx for DRAP otherwise. */
10743 static rtx
10745 {
10750 {
10751 /* Assign DRAP to vDRAP and returns vDRAP */
10753 rtx drap_vreg;
10754 rtx arg_ptr;
10767 {
10770 }
10772 }
10773 else
10775 }
10777 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10779 static rtx
10781 {
10783 }
10786 rtx reg;
10788 };
10790 /* Return a short-lived scratch register for use on function entry.
10791 In 32-bit mode, it is valid only after the registers are saved
10792 in the prologue. This register must be released by means of
10793 release_scratch_register_on_entry once it is dead. */
10795 static void
10797 {
10803 {
10804 /* We always use R11 in 64-bit mode. */
10806 }
10807 else
10808 {
10810 bool fastcall_p
10812 bool thiscall_p
10816 int drap_regno
10819 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10820 for the static chain register. */
10824 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10825 for the static chain register. */
10830 /* ecx is the static chain register. */
10832 && !static_chain_p
10837 /* esi is the static chain register. */
10843 else
10844 {
10847 }
10848 }
10852 {
10855 }
10856 }
10858 /* Release a scratch register obtained from the preceding function. */
10860 static void
10862 {
10864 {
10868 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10874 }
10875 }
10877 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10879 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10881 static void
10883 {
10884 /* We skip the probe for the first interval + a small dope of 4 words and
10885 probe that many bytes past the specified size to maintain a protection
10886 area at the botton of the stack. */
10890 /* See if we have a constant small number of probes to generate. If so,
10891 that's the easy case. The run-time loop is made up of 11 insns in the
10892 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10893 for n # of intervals. */
10895 {
10899 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10900 values of N from 1 until it exceeds SIZE. If only one probe is
10901 needed, this will not generate any code. Then adjust and probe
10902 to PROBE_INTERVAL + SIZE. */
10904 {
10906 {
10909 }
10910 else
10917 }
10921 else
10929 /* Adjust back to account for the additional first interval. */
10933 }
10935 /* Otherwise, do the same as above, but in a loop. Note that we must be
10936 extra careful with variables wrapping around because we might be at
10937 the very top (or the very bottom) of the address space and we have
10938 to be able to handle this case properly; in particular, we use an
10939 equality test for the loop condition. */
10940 else
10941 {
10942 HOST_WIDE_INT rounded_size;
10948 /* Step 1: round SIZE to the previous multiple of the interval. */
10953 /* Step 2: compute initial and final value of the loop counter. */
10955 /* SP = SP_0 + PROBE_INTERVAL. */
10960 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10964 stack_pointer_rtx)));
10967 /* Step 3: the loop
10969 while (SP != LAST_ADDR)
10970 {
10971 SP = SP + PROBE_INTERVAL
10972 probe at SP
10973 }
10975 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10976 values of N from 1 until it is equal to ROUNDED_SIZE. */
10981 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10982 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10985 {
10990 }
10992 /* Adjust back to account for the additional first interval. */
10998 }
11002 /* Even if the stack pointer isn't the CFA register, we need to correctly
11003 describe the adjustments made to it, in particular differentiate the
11004 frame-related ones from the frame-unrelated ones. */
11006 {
11019 }
11021 /* Make sure nothing is scheduled before we are done. */
11023 }
11025 /* Adjust the stack pointer up to REG while probing it. */
11029 {
11039 /* Jump to END_LAB if SP == LAST_ADDR. */
11047 /* SP = SP + PROBE_INTERVAL. */
11051 /* Probe at SP. */
11062 }
11064 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11065 inclusive. These are offsets from the current stack pointer. */
11067 static void
11069 {
11070 /* See if we have a constant small number of probes to generate. If so,
11071 that's the easy case. The run-time loop is made up of 7 insns in the
11072 generic case while the compile-time loop is made up of n insns for n #
11073 of intervals. */
11075 {
11076 HOST_WIDE_INT i;
11078 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11079 it exceeds SIZE. If only one probe is needed, this will not
11080 generate any code. Then probe at FIRST + SIZE. */
11087 }
11089 /* Otherwise, do the same as above, but in a loop. Note that we must be
11090 extra careful with variables wrapping around because we might be at
11091 the very top (or the very bottom) of the address space and we have
11092 to be able to handle this case properly; in particular, we use an
11093 equality test for the loop condition. */
11094 else
11095 {
11102 /* Step 1: round SIZE to the previous multiple of the interval. */
11107 /* Step 2: compute initial and final value of the loop counter. */
11109 /* TEST_OFFSET = FIRST. */
11112 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
11116 /* Step 3: the loop
11118 while (TEST_ADDR != LAST_ADDR)
11119 {
11120 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11121 probe at TEST_ADDR
11122 }
11124 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11125 until it is equal to ROUNDED_SIZE. */
11130 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11131 that SIZE is equal to ROUNDED_SIZE. */
11136 stack_pointer_rtx,
11141 }
11143 /* Make sure nothing is scheduled before we are done. */
11145 }
11147 /* Probe a range of stack addresses from REG to END, inclusive. These are
11148 offsets from the current stack pointer. */
11152 {
11162 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11170 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11174 /* Probe at TEST_ADDR. */
11187 }
11189 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
11190 to be generated in correct form. */
11191 static void
11193 {
11194 /* Check if stack realign is really needed after reload, and
11195 stores result in cfun */
11196 unsigned int incoming_stack_boundary
11205 {
11206 /* After stack_realign_needed is finalized, we can't no longer
11207 change it. */
11210 }
11212 /* If the only reason for frame_pointer_needed is that we conservatively
11213 assumed stack realignment might be needed, but in the end nothing that
11214 needed the stack alignment had been spilled, clear frame_pointer_needed
11215 and say we don't need stack realignment. */
11217 && frame_pointer_needed
11219 && flag_omit_frame_pointer
11221 && !ix86_current_function_calls_tls_descriptor
11230 {
11232 basic_block bb;
11239 HARD_FRAME_POINTER_REGNUM);
11241 {
11246 set_up_by_prologue))
11247 {
11251 }
11252 }
11254 /* If drap has been set, but it actually isn't live at the start
11255 of the function, there is no reason to set it up. */
11257 {
11260 {
11263 }
11264 }
11265 else
11280 }
11284 }
11286 /* Delete SET_GOT right after entry block if it is allocated to reg. */
11288 static void
11290 {
11296 {
11299 {
11305 }
11306 }
11307 }
11309 /* Expand the prologue into a bunch of separate insns. */
11311 void
11313 {
11317 HOST_WIDE_INT allocate;
11323 /* DRAP should not coexist with stack_realign_fp */
11328 /* Initialize CFA state for before the prologue. */
11332 /* Track SP offset to the CFA. We continue tracking this after we've
11333 swapped the CFA register away from SP. In the case of re-alignment
11334 this is fudged; we're interested to offsets within the local frame. */
11341 {
11342 /* We should have already generated an error for any use of
11343 ms_hook on a nested function. */
11346 /* Check if profiling is active and we shall use profiling before
11347 prologue variant. If so sorry. */
11352 /* In ix86_asm_output_function_label we emitted:
11353 8b ff movl.s %edi,%edi
11354 55 push %ebp
11355 8b ec movl.s %esp,%ebp
11357 This matches the hookable function prologue in Win32 API
11358 functions in Microsoft Windows XP Service Pack 2 and newer.
11359 Wine uses this to enable Windows apps to hook the Win32 API
11360 functions provided by Wine.
11362 What that means is that we've already set up the frame pointer. */
11366 {
11369 /* We've decided to use the frame pointer already set up.
11370 Describe this to the unwinder by pretending that both
11371 push and mov insns happen right here.
11373 Putting the unwind info here at the end of the ms_hook
11374 is done so that we can make absolutely certain we get
11375 the required byte sequence at the start of the function,
11376 rather than relying on an assembler that can produce
11377 the exact encoding required.
11379 However it does mean (in the unpatched case) that we have
11380 a 1 insn window where the asynchronous unwind info is
11381 incorrect. However, if we placed the unwind info at
11382 its correct location we would have incorrect unwind info
11383 in the patched case. Which is probably all moot since
11384 I don't expect Wine generates dwarf2 unwind info for the
11385 system libraries that use this feature. */
11391 stack_pointer_rtx);
11399 /* Note that gen_push incremented m->fs.cfa_offset, even
11400 though we didn't emit the push insn here. */
11404 }
11405 else
11406 {
11407 /* The frame pointer is not needed so pop %ebp again.
11408 This leaves us with a pristine state. */
11410 }
11411 }
11413 /* The first insn of a function that accepts its static chain on the
11414 stack is to push the register that would be filled in by a direct
11415 call. This insn will be skipped by the trampoline. */
11417 {
11421 /* We don't want to interpret this push insn as a register save,
11422 only as a stack adjustment. The real copy of the register as
11423 a save will be done later, if needed. */
11428 }
11430 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
11431 of DRAP is needed and stack realignment is really needed after reload */
11433 {
11436 /* Only need to push parameter pointer reg if it is caller saved. */
11438 {
11439 /* Push arg pointer reg */
11442 }
11444 /* Grab the argument pointer. */
11451 /* Align the stack. */
11453 stack_pointer_rtx,
11457 /* Replicate the return address on the stack so that return
11458 address can be reached via (argp - 1) slot. This is needed
11459 to implement macro RETURN_ADDR_RTX and intrinsic function
11460 expand_builtin_return_addr etc. */
11466 /* For the purposes of frame and register save area addressing,
11467 we've started over with a new frame. */
11470 }
11476 {
11477 /* Note: AT&T enter does NOT have reversed args. Enter is probably
11478 slower on all targets. Also sdb doesn't like it. */
11482 /* Push registers now, before setting the frame pointer
11483 on SEH target. */
11485 && TARGET_SEH
11487 {
11491 }
11494 {
11502 }
11503 }
11506 {
11507 /* If saving registers via PUSH, do so now. */
11509 {
11513 }
11515 /* When using red zone we may start register saving before allocating
11516 the stack frame saving one cycle of the prologue. However, avoid
11517 doing this if we have to probe the stack; at least on x86_64 the
11518 stack probe can turn into a call that clobbers a red zone location. */
11520 && (! TARGET_STACK_PROBE
11522 {
11525 }
11526 }
11529 {
11533 /* The computation of the size of the re-aligned stack frame means
11534 that we must allocate the size of the register save area before
11535 performing the actual alignment. Otherwise we cannot guarantee
11536 that there's enough storage above the realignment point. */
11543 /* Align the stack. */
11545 stack_pointer_rtx,
11548 /* For the purposes of register save area addressing, the stack
11549 pointer is no longer valid. As for the value of sp_offset,
11550 see ix86_compute_frame_layout, which we need to match in order
11551 to pass verification of stack_pointer_offset at the end. */
11554 }
11559 {
11560 /* We start to count from ARG_POINTER. */
11563 /* If it was realigned, take into account the fake frame. */
11565 {
11572 /* This over-estimates by 1 minimal-stack-alignment-unit but
11573 mitigates that by counting in the new return address slot. */
11574 current_function_dynamic_stack_size
11576 }
11579 }
11581 /* On SEH target with very large frame size, allocate an area to save
11582 SSE registers (as the very large allocation won't be described). */
11586 {
11587 HOST_WIDE_INT sse_size =
11592 /* No need to do stack checking as the area will be immediately
11593 written. */
11600 }
11602 /* The stack has already been decremented by the instruction calling us
11603 so probe if the size is non-negative to preserve the protection area. */
11605 {
11606 /* We expect the registers to be saved when probes are used. */
11610 {
11613 {
11616 }
11617 }
11618 else
11619 {
11626 {
11628 {
11631 }
11632 else
11634 }
11635 else
11636 {
11638 {
11642 }
11643 else
11645 }
11646 }
11647 }
11650 ;
11653 {
11657 }
11658 else
11659 {
11671 {
11674 /* Note that SEH directives need to continue tracking the stack
11675 pointer even after the frame pointer has been set up. */
11677 {
11685 }
11686 }
11689 {
11694 {
11702 }
11703 }
11708 /* Use the fact that AX still contains ALLOCATE. */
11710 ? gen_pro_epilogue_adjust_stack_di_sub
11717 {
11725 }
11728 /* Use stack_pointer_rtx for relative addressing so that code
11729 works for realigned stack, too. */
11731 {
11738 }
11740 {
11745 }
11746 }
11749 /* If we havn't already set up the frame pointer, do so now. */
11751 {
11763 }
11770 /* For the mcount profiling on 32 bit PIC mode we need to emit SET_GOT
11771 in PROLOGUE. */
11773 {
11779 /* Deleting already emmitted SET_GOT if exist and allocated to
11780 REAL_PIC_OFFSET_TABLE_REGNUM. */
11782 }
11785 {
11786 /* vDRAP is setup but after reload it turns out stack realign
11787 isn't necessary, here we will emit prologue to setup DRAP
11788 without stack realign adjustment */
11791 }
11793 /* Prevent instructions from being scheduled into register save push
11794 sequence when access to the redzone area is done through frame pointer.
11795 The offset between the frame pointer and the stack pointer is calculated
11796 relative to the value of the stack pointer at the end of the function
11797 prologue, and moving instructions that access redzone area via frame
11798 pointer inside push sequence violates this assumption. */
11802 /* Emit cld instruction if stringops are used in the function. */
11806 /* SEH requires that the prologue end within 256 bytes of the start of
11807 the function. Prevent instruction schedules that would extend that.
11808 Further, prevent alloca modifications to the stack pointer from being
11809 combined with prologue modifications. */
11812 }
11814 /* Emit code to restore REG using a POP insn. */
11816 static void
11818 {
11827 {
11828 /* Previously we'd represented the CFA as an expression
11829 like *(%ebp - 8). We've just popped that value from
11830 the stack, which means we need to reset the CFA to
11831 the drap register. This will remain until we restore
11832 the stack pointer. */
11836 /* This means that the DRAP register is valid for addressing too. */
11839 }
11842 {
11849 }
11851 /* When the frame pointer is the CFA, and we pop it, we are
11852 swapping back to the stack pointer as the CFA. This happens
11853 for stack frames that don't allocate other data, so we assume
11854 the stack pointer is now pointing at the return address, i.e.
11855 the function entry state, which makes the offset be 1 word. */
11857 {
11860 {
11868 }
11869 }
11870 }
11872 /* Emit code to restore saved registers using POP insns. */
11874 static void
11876 {
11882 }
11884 /* Emit code and notes for the LEAVE instruction. */
11886 static void
11888 {
11900 {
11908 }
11911 }
11913 /* Emit code to restore saved registers using MOV insns.
11914 First register is restored from CFA - CFA_OFFSET. */
11915 static void
11918 {
11924 {
11926 rtx mem;
11934 {
11935 /* Previously we'd represented the CFA as an expression
11936 like *(%ebp - 8). We've just popped that value from
11937 the stack, which means we need to reset the CFA to
11938 the drap register. This will remain until we restore
11939 the stack pointer. */
11943 /* This means that the DRAP register is valid for addressing. */
11945 }
11946 else
11950 }
11951 }
11953 /* Emit code to restore saved registers using MOV insns.
11954 First register is restored from CFA - CFA_OFFSET. */
11955 static void
11958 {
11963 {
11965 rtx mem;
11975 }
11976 }
11978 /* Restore function stack, frame, and registers. */
11980 void
11982 {
11998 /* The FP must be valid if the frame pointer is present. */
12003 /* We must have *some* valid pointer to the stack frame. */
12006 /* The DRAP is never valid at this point. */
12009 /* See the comment about red zone and frame
12010 pointer usage in ix86_expand_prologue. */
12017 /* Determine the CFA offset of the end of the red-zone. */
12020 {
12021 /* The red-zone begins below the return address. */
12024 /* When the register save area is in the aligned portion of
12025 the stack, determine the maximum runtime displacement that
12026 matches up with the aligned frame. */
12030 }
12032 /* Special care must be taken for the normal return case of a function
12033 using eh_return: the eax and edx registers are marked as saved, but
12034 not restored along this path. Adjust the save location to match. */
12038 /* EH_RETURN requires the use of moves to function properly. */
12041 /* SEH requires the use of pops to identify the epilogue. */
12044 /* If we're only restoring one register and sp is not valid then
12045 using a move instruction to restore the register since it's
12046 less work than reloading sp and popping the register. */
12059 && TARGET_USE_LEAVE
12063 else
12067 {
12068 /* Ensure that the entire register save area is addressable via
12069 the stack pointer, if we will restore via sp. */
12074 {
12078 style,
12080 }
12081 }
12083 /* If there are any SSE registers to restore, then we have to do it
12084 via moves, since there's obviously no pop for SSE regs. */
12090 {
12091 rtx t;
12096 /* eh_return epilogues need %ecx added to the stack pointer. */
12098 {
12102 /* Stack align doesn't work with eh_return. */
12104 /* Neither does regparm nested functions. */
12108 {
12116 /* Note that we use SA as a temporary CFA, as the return
12117 address is at the proper place relative to it. We
12118 pretend this happens at the FP restore insn because
12119 prior to this insn the FP would be stored at the wrong
12120 offset relative to SA, and after this insn we have no
12121 other reasonable register to use for the CFA. We don't
12122 bother resetting the CFA to the SP for the duration of
12123 the return insn. */
12136 }
12137 else
12138 {
12146 {
12150 UNITS_PER_WORD));
12152 }
12153 }
12156 }
12157 }
12158 else
12159 {
12160 /* SEH requires that the function end with (1) a stack adjustment
12161 if necessary, (2) a sequence of pops, and (3) a return or
12162 jump instruction. Prevent insns from the function body from
12163 being scheduled into this sequence. */
12165 {
12166 /* Prevent a catch region from being adjacent to the standard
12167 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
12168 several other flags that would be interesting to test are
12169 not yet set up. */
12172 else
12174 }
12176 /* First step is to deallocate the stack frame so that we can
12177 pop the registers. Also do it on SEH target for very large
12178 frame as the emitted instructions aren't allowed by the ABI in
12179 epilogues. */
12181 || (TARGET_SEH
12184 {
12189 }
12191 {
12195 style,
12197 }
12200 }
12202 /* If we used a stack pointer and haven't already got rid of it,
12203 then do so now. */
12205 {
12206 /* If the stack pointer is valid and pointing at the frame
12207 pointer store address, then we only need a pop. */
12210 /* Leave results in shorter dependency chains on CPUs that are
12211 able to grok it fast. */
12216 else
12217 {
12219 hard_frame_pointer_rtx,
12222 }
12223 }
12226 {
12254 }
12256 /* At this point the stack pointer must be valid, and we must have
12257 restored all of the registers. We may not have deallocated the
12258 entire stack frame. We've delayed this until now because it may
12259 be possible to merge the local stack deallocation with the
12260 deallocation forced by ix86_static_chain_on_stack. */
12265 {
12269 }
12270 else
12273 /* Sibcall epilogues don't want a return instruction. */
12275 {
12278 }
12281 {
12284 /* i386 can only pop 64K bytes. If asked to pop more, pop return
12285 address, do explicit add, and jump indirectly to the caller. */
12288 {
12292 /* There is no "pascal" calling convention in any 64bit ABI. */
12308 }
12309 else
12311 }
12312 else
12315 /* Restore the state back to the state from the prologue,
12316 so that it's correct for the next epilogue. */
12318 }
12320 /* Reset from the function's potential modifications. */
12322 static void
12324 {
12328 #if TARGET_MACHO
12329 /* Mach-O doesn't support labels at the end of objects, so if
12330 it looks like we might want one, insert a NOP. */
12331 {
12337 {
12338 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
12339 notes only, instead set their CODE_LABEL_NUMBER to -1,
12340 otherwise there would be code generation differences
12341 in between -g and -g0. */
12345 }
12355 }
12356 #endif
12358 }
12360 /* Return a scratch register to use in the split stack prologue. The
12361 split stack prologue is used for -fsplit-stack. It is the first
12362 instructions in the function, even before the regular prologue.
12363 The scratch register can be any caller-saved register which is not
12364 used for parameters or for the static chain. */
12366 static unsigned int
12368 {
12371 else
12372 {
12385 {
12387 {
12391 }
12393 }
12395 {
12399 }
12401 {
12404 else
12405 {
12407 {
12411 }
12413 }
12414 }
12415 else
12416 {
12417 /* FIXME: We could make this work by pushing a register
12418 around the addition and comparison. */
12421 }
12422 }
12423 }
12425 /* A SYMBOL_REF for the function which allocates new stackspace for
12426 -fsplit-stack. */
12430 /* A SYMBOL_REF for the more stack function when using the large
12431 model. */
12435 /* Handle -fsplit-stack. These are the first instructions in the
12436 function, even before the regular prologue. */
12438 void
12440 {
12442 HOST_WIDE_INT allocate;
12448 rtx fn;
12456 /* This is the label we will branch to if we have enough stack
12457 space. We expect the basic block reordering pass to reverse this
12458 branch if optimizing, so that we branch in the unlikely case. */
12461 /* We need to compare the stack pointer minus the frame size with
12462 the stack boundary in the TCB. The stack boundary always gives
12463 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
12464 can compare directly. Otherwise we need to do an addition. */
12467 UNSPEC_STACK_CHECK);
12472 else
12473 {
12475 rtx offset;
12477 /* We need a scratch register to hold the stack pointer minus
12478 the required frame size. Since this is the very start of the
12479 function, the scratch register can be any caller-saved
12480 register which is not used for parameters. */
12487 {
12488 /* We don't use ix86_gen_add3 in this case because it will
12489 want to split to lea, but when not optimizing the insn
12490 will not be split after this point. */
12493 offset)));
12494 }
12495 else
12496 {
12499 stack_pointer_rtx));
12500 }
12502 }
12508 /* Mark the jump as very likely to be taken. */
12513 {
12516 }
12519 /* Get more stack space. We pass in the desired stack space and the
12520 size of the arguments to copy to the new stack. In 32-bit mode
12521 we push the parameters; __morestack will return on a new stack
12522 anyhow. In 64-bit mode we pass the parameters in r10 and
12523 r11. */
12528 {
12534 /* If this function uses a static chain, it will be in %r10.
12535 Preserve it across the call to __morestack. */
12537 {
12538 rtx rax;
12543 }
12547 {
12548 HOST_WIDE_INT argval;
12551 /* When using the large model we need to load the address
12552 into a register, and we've run out of registers. So we
12553 switch to a different calling convention, and we call a
12554 different function: __morestack_large. We pass the
12555 argument size in the upper 32 bits of r10 and pass the
12556 frame size in the lower 32 bits. */
12561 {
12562 split_stack_fn_large =
12565 }
12567 {
12569 rtx x;
12578 UNSPEC_GOT);
12584 }
12585 else
12592 }
12593 else
12594 {
12598 }
12601 }
12602 else
12603 {
12606 }
12612 /* In order to make call/return prediction work right, we now need
12613 to execute a return instruction. See
12614 libgcc/config/i386/morestack.S for the details on how this works.
12616 For flow purposes gcc must not see this as a return
12617 instruction--we need control flow to continue at the subsequent
12618 label. Therefore, we use an unspec. */
12622 /* If we are in 64-bit mode and this function uses a static chain,
12623 we saved %r10 in %rax before calling _morestack. */
12628 /* If this function calls va_start, we need to store a pointer to
12629 the arguments on the old stack, because they may not have been
12630 all copied to the new stack. At this point the old stack can be
12631 found at the frame pointer value used by __morestack, because
12632 __morestack has set that up before calling back to us. Here we
12633 store that pointer in a scratch register, and in
12634 ix86_expand_prologue we store the scratch register in a stack
12635 slot. */
12637 {
12639 rtx frame_reg;
12646 /* 64-bit:
12647 fp -> old fp value
12648 return address within this function
12649 return address of caller of this function
12650 stack arguments
12651 So we add three words to get to the stack arguments.
12653 32-bit:
12654 fp -> old fp value
12655 return address within this function
12656 first argument to __morestack
12657 second argument to __morestack
12658 return address of caller of this function
12659 stack arguments
12660 So we add five words to get to the stack arguments.
12661 */
12672 }
12677 /* If this function calls va_start, we now have to set the scratch
12678 register for the case where we do not call __morestack. In this
12679 case we need to set it based on the stack pointer. */
12681 {
12688 }
12689 }
12691 /* We may have to tell the dataflow pass that the split stack prologue
12692 is initializing a scratch register. */
12694 static void
12696 {
12698 {
12701 }
12702 }
12703 \f
12704 /* Extract the parts of an RTL expression that is a valid memory address
12705 for an instruction. Return 0 if the structure of the address is
12706 grossly off. Return -1 if the address contains ASHIFT, so it is not
12707 strictly valid, but still used for computing length of lea instruction. */
12709 int
12711 {
12716 rtx tmp;
12720 /* Allow zero-extended SImode addresses,
12721 they will be emitted with addr32 prefix. */
12723 {
12726 {
12730 }
12733 {
12740 }
12741 }
12743 /* Allow SImode subregs of DImode addresses,
12744 they will be emitted with addr32 prefix. */
12746 {
12749 {
12753 }
12754 }
12759 {
12762 else
12764 }
12766 {
12771 do
12772 {
12777 }
12784 {
12787 {
12812 /* FALLTHRU */
12816 && TARGET_TLS_DIRECT_SEG_REFS
12819 else
12826 /* FALLTHRU */
12833 else
12848 }
12849 }
12850 }
12852 {
12855 }
12857 {
12858 /* We're called for lea too, which implements ashift on occasion. */
12868 }
12869 else
12873 {
12875 ;
12878 ;
12879 else
12881 }
12883 /* Extract the integral value of scale. */
12885 {
12889 }
12894 /* Avoid useless 0 displacement. */
12898 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12903 {
12906 }
12908 /* Special case: %ebp cannot be encoded as a base without a displacement.
12909 Similarly %r13. */
12911 && base_reg
12920 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12921 Avoid this by transforming to [%esi+0].
12922 Reload calls address legitimization without cfun defined, so we need
12923 to test cfun for being non-NULL. */
12929 /* Special case: encode reg+reg instead of reg*2. */
12933 /* Special case: scaling cannot be encoded without base or displacement. */
12944 }
12945 \f
12946 /* Return cost of the memory address x.
12947 For i386, it is better to use a complex address than let gcc copy
12948 the address into a reg and make a new pseudo. But not if the address
12949 requires to two regs - that would mean more pseudos with longer
12950 lifetimes. */
12951 static int
12953 {
12965 /* Attempt to minimize number of registers in the address by increasing
12966 address cost for each used register. We don't increase address cost
12967 for "pic_offset_table_rtx". When a memopt with "pic_offset_table_rtx"
12968 is not invariant itself it most likely means that base or index is not
12969 invariant. Therefore only "pic_offset_table_rtx" could be hoisted out,
12970 which is not profitable for x86. */
12974 || !pic_offset_table_rtx
12977 cost++;
12982 || !pic_offset_table_rtx
12985 cost++;
12987 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12988 since it's predecode logic can't detect the length of instructions
12989 and it degenerates to vector decoded. Increase cost of such
12990 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12991 to split such addresses or even refuse such addresses at all.
12993 Following addressing modes are affected:
12994 [base+scale*index]
12995 [scale*index+disp]
12996 [base+index]
12998 The first and last case may be avoidable by explicitly coding the zero in
12999 memory address, but I don't have AMD-K6 machine handy to check this
13000 theory. */
13009 }
13010 \f
13011 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
13012 this is used for to form addresses to local data when -fPIC is in
13013 use. */
13015 static bool
13017 {
13020 }
13022 /* Determine if a given RTX is a valid constant. We already know this
13023 satisfies CONSTANT_P. */
13025 static bool
13027 {
13028 /* Pointer bounds constants are not valid. */
13033 {
13038 {
13042 }
13047 /* Only some unspecs are valid as "constants". */
13050 {
13066 }
13068 /* We must have drilled down to a symbol. */
13073 /* FALLTHRU */
13076 /* TLS symbols are never valid. */
13080 /* DLLIMPORT symbols are never valid. */
13085 #if TARGET_MACHO
13086 /* mdynamic-no-pic */
13089 #endif
13103 }
13105 /* Otherwise we handle everything else in the move patterns. */
13107 }
13109 /* Determine if it's legal to put X into the constant pool. This
13110 is not possible for the address of thread-local symbols, which
13111 is checked above. */
13113 static bool
13115 {
13116 /* We can always put integral constants and vectors in memory. */
13118 {
13127 }
13129 }
13131 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
13132 otherwise zero. */
13134 static bool
13136 {
13142 }
13145 /* Nonzero if the constant value X is a legitimate general operand
13146 when generating PIC code. It is given that flag_pic is on and
13147 that X satisfies CONSTANT_P. */
13149 bool
13151 {
13152 rtx inner;
13155 {
13162 /* Only some unspecs are valid as "constants". */
13165 {
13178 }
13179 /* FALLTHRU */
13187 }
13188 }
13190 /* Determine if a given CONST RTX is a valid memory displacement
13191 in PIC mode. */
13193 bool
13195 {
13198 /* In 64bit mode we can allow direct addresses of symbols and labels
13199 when they are not dynamic symbols. */
13201 {
13205 {
13229 /* FALLTHRU */
13232 /* TLS references should always be enclosed in UNSPEC.
13233 The dllimported symbol needs always to be resolved. */
13239 {
13247 /* Function-symbols need to be resolved only for
13248 large-model.
13249 For the small-model we don't need to resolve anything
13250 here. */
13255 /* Non-external symbols don't need to be resolved for
13256 large, and medium-model. */
13261 }
13264 || (HAVE_LD_PIE_COPYRELOC
13265 && flag_pie
13274 }
13275 }
13281 {
13282 /* We are unsafe to allow PLUS expressions. This limit allowed distance
13283 of GOT tables. We should not need these anyway. */
13295 }
13299 {
13304 }
13313 {
13317 /* We need to check for both symbols and labels because VxWorks loads
13318 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
13319 details. */
13323 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
13324 While ABI specify also 32bit relocation but we don't produce it in
13325 small PIC model at all. */
13347 }
13350 }
13352 /* Determine if op is suitable RTX for an address register.
13353 Return naked register if a register or a register subreg is
13354 found, otherwise return NULL_RTX. */
13356 static rtx
13358 {
13361 /* Only SImode or DImode registers can form the address. */
13368 {
13376 /* Don't allow SUBREGs that span more than a word. It can
13377 lead to spill failures when the register is one word out
13378 of a two word structure. */
13382 /* Allow only SUBREGs of non-eliminable hard registers. */
13385 }
13387 /* Op is not a register. */
13389 }
13391 /* Recognizes RTL expressions that are valid memory addresses for an
13392 instruction. The MODE argument is the machine mode for the MEM
13393 expression that wants to use this address.
13395 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
13396 convert common non-canonical forms to canonical form so that they will
13397 be recognized. */
13399 static bool
13401 {
13404 HOST_WIDE_INT scale;
13408 /* Decomposition failed. */
13417 /* Validate base register. */
13419 {
13427 /* Base is not valid. */
13429 }
13431 /* Validate index register. */
13433 {
13441 /* Index is not valid. */
13443 }
13445 /* Index and base should have the same mode. */
13450 /* Address override works only on the (%reg) part of %fs:(%reg). */
13456 /* Validate scale factor. */
13458 {
13460 /* Scale without index. */
13464 /* Scale is not a valid multiplier. */
13466 }
13468 /* Validate displacement. */
13470 {
13475 {
13476 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
13477 used. While ABI specify also 32bit relocations, we don't produce
13478 them at all and use IP relative instead. */
13485 /* 64bit address unspec. */
13505 /* Invalid address unspec. */
13507 }
13510 && (flag_pic
13511 || (TARGET_MACHO
13512 #if TARGET_MACHO
13513 && MACHOPIC_INDIRECT
13515 #endif
13516 )))
13517 {
13519 is_legitimate_pic:
13521 {
13522 /* foo@dtpoff(%rX) is ok. */
13529 /* Non-constant pic memory reference. */
13531 }
13534 /* Displacement is an invalid pic construct. */
13536 #if TARGET_MACHO
13539 /* displacment must be referenced via non_lazy_pointer */
13541 #endif
13543 /* This code used to verify that a symbolic pic displacement
13544 includes the pic_offset_table_rtx register.
13546 While this is good idea, unfortunately these constructs may
13547 be created by "adds using lea" optimization for incorrect
13548 code like:
13550 int a;
13551 int foo(int i)
13552 {
13553 return *(&a+i);
13554 }
13556 This code is nonsensical, but results in addressing
13557 GOT table with pic_offset_table_rtx base. We can't
13558 just refuse it easily, since it gets matched by
13559 "addsi3" pattern, that later gets split to lea in the
13560 case output register differs from input. While this
13561 can be handled by separate addsi pattern for this case
13562 that never results in lea, this seems to be easier and
13563 correct fix for crash to disable this test. */
13564 }
13571 /* Displacement is not constant. */
13575 /* Displacement is out of range. */
13577 /* In x32 mode, constant addresses are sign extended to 64bit, so
13578 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13583 }
13585 /* Everything looks valid. */
13587 }
13589 /* Determine if a given RTX is a valid constant address. */
13591 bool
13593 {
13595 }
13596 \f
13597 /* Return a unique alias set for the GOT. */
13599 static alias_set_type
13601 {
13606 }
13608 /* Return a legitimate reference for ORIG (an address) using the
13609 register REG. If REG is 0, a new pseudo is generated.
13611 There are two types of references that must be handled:
13613 1. Global data references must load the address from the GOT, via
13614 the PIC reg. An insn is emitted to do this load, and the reg is
13615 returned.
13617 2. Static data references, constant pool addresses, and code labels
13618 compute the address as an offset from the GOT, whose base is in
13619 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13620 differentiate them from global data objects. The returned
13621 address is the PIC reg + an unspec constant.
13623 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13624 reg also appears in the address. */
13626 static rtx
13628 {
13632 #if TARGET_MACHO
13634 {
13637 /* Use the generic Mach-O PIC machinery. */
13639 }
13640 #endif
13643 {
13647 }
13653 {
13654 rtx tmpreg;
13655 /* This symbol may be referenced via a displacement from the PIC
13656 base address (@GOTOFF). */
13661 {
13663 UNSPEC_GOTOFF);
13665 }
13666 else
13671 else
13676 {
13680 }
13681 else
13683 }
13685 {
13686 /* This symbol may be referenced via a displacement from the PIC
13687 base address (@GOTOFF). */
13692 {
13694 UNSPEC_GOTOFF);
13696 }
13697 else
13703 {
13706 }
13707 }
13709 /* We can't use @GOTOFF for text labels on VxWorks;
13710 see gotoff_operand. */
13712 {
13717 /* For x64 PE-COFF there is no GOT table. So we use address
13718 directly. */
13720 {
13728 }
13730 {
13738 /* Use directly gen_movsi, otherwise the address is loaded
13739 into register for CSE. We don't want to CSE this addresses,
13740 instead we CSE addresses from the GOT table, so skip this. */
13743 }
13744 else
13745 {
13746 /* This symbol must be referenced via a load from the
13747 Global Offset Table (@GOT). */
13761 }
13762 }
13763 else
13764 {
13767 {
13769 {
13772 }
13773 else
13775 }
13777 {
13780 /* We must match stuff we generate before. Assume the only
13781 unspecs that can get here are ours. Not that we could do
13782 anything with them anyway.... */
13788 }
13790 {
13793 /* Check first to see if this is a constant offset from a @GOTOFF
13794 symbol reference. */
13797 {
13799 {
13801 UNSPEC_GOTOFF);
13807 {
13810 }
13811 }
13812 else
13813 {
13816 {
13820 }
13821 }
13822 }
13823 else
13824 {
13827 new_rtx
13831 {
13834 {
13837 new_rtx
13839 }
13840 else
13842 }
13843 else
13844 {
13845 /* For %rip addressing, we have to use just disp32, not
13846 base nor index. */
13853 {
13856 }
13858 }
13859 }
13860 }
13861 }
13863 }
13864 \f
13865 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13867 static rtx
13869 {
13873 {
13878 }
13884 }
13886 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13890 static rtx
13892 {
13894 {
13900 }
13903 {
13905 UNSPEC_PLTOFF);
13908 }
13911 }
13913 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13917 rtx
13919 {
13921 {
13922 ix86_tls_module_base_symbol
13927 }
13930 }
13932 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13933 false if we expect this to be used for a memory address and true if
13934 we expect to load the address into a register. */
13936 static rtx
13938 {
13944 /* Fall back to global dynamic model if tool chain cannot support local
13945 dynamic. */
13952 {
13957 {
13960 else
13961 {
13964 }
13965 }
13968 {
13971 else
13981 }
13982 else
13983 {
13987 {
13992 emit_call_insn
14002 }
14003 else
14005 }
14012 {
14015 else
14016 {
14019 }
14020 }
14023 {
14028 else
14034 }
14035 else
14036 {
14040 {
14043 rtx eqv;
14046 emit_call_insn
14051 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
14052 share the LD_BASE result with other LD model accesses. */
14054 UNSPEC_TLS_LD_BASE);
14058 }
14059 else
14061 }
14069 {
14076 }
14081 {
14083 {
14084 /* The Sun linker took the AMD64 TLS spec literally
14085 and can only handle %rax as destination of the
14086 initial executable code sequence. */
14091 }
14093 /* Generate DImode references to avoid %fs:(%reg32)
14094 problems and linker IE->LE relaxation bug. */
14098 }
14100 {
14103 }
14105 {
14109 }
14110 else
14111 {
14114 }
14124 {
14129 }
14130 else
14131 {
14135 }
14145 {
14149 }
14150 else
14151 {
14155 }
14160 }
14163 }
14165 /* Create or return the unique __imp_DECL dllimport symbol corresponding
14166 to symbol DECL if BEIMPORT is true. Otherwise create or return the
14167 unique refptr-DECL symbol corresponding to symbol DECL. */
14170 {
14174 {
14176 }
14178 static void
14180 {
14186 else
14188 }
14189 };
14193 static tree
14195 {
14201 tree to;
14202 rtx rtl;
14229 else
14242 {
14244 #ifdef SUB_TARGET_RECORD_STUB
14246 #endif
14247 }
14256 }
14258 /* Expand SYMBOL into its corresponding far-addresse symbol.
14259 WANT_REG is true if we require the result be a register. */
14261 static rtx
14263 {
14264 tree imp_decl;
14265 rtx x;
14274 }
14276 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
14277 true if we require the result be a register. */
14279 static rtx
14281 {
14282 tree imp_decl;
14283 rtx x;
14292 }
14294 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
14295 is true if we require the result be a register. */
14297 static rtx
14299 {
14304 {
14311 {
14314 }
14315 }
14331 {
14334 }
14336 }
14338 /* Try machine-dependent ways of modifying an illegitimate address
14339 to be legitimate. If we find one, return the new, valid address.
14340 This macro is used in only one place: `memory_address' in explow.c.
14342 OLDX is the address as it was before break_out_memory_refs was called.
14343 In some cases it is useful to look at this to decide what needs to be done.
14345 It is always safe for this macro to do nothing. It exists to recognize
14346 opportunities to optimize the output.
14348 For the 80386, we handle X+REG by loading X into a register R and
14349 using R+REG. R will go in a general reg and indexing will be used.
14350 However, if REG is a broken-out memory address or multiplication,
14351 nothing needs to be done because REG can certainly go in a general reg.
14353 When -fpic is used, special handling is needed for symbolic references.
14354 See comments by legitimize_pic_address in i386.c for details. */
14356 static rtx
14358 {
14369 {
14373 }
14376 {
14380 }
14385 #if TARGET_MACHO
14388 #endif
14390 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
14394 {
14399 }
14402 {
14403 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
14408 {
14414 }
14419 {
14425 }
14427 /* Put multiply first if it isn't already. */
14429 {
14432 }
14434 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
14435 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
14436 created by virtual register instantiation, register elimination, and
14437 similar optimizations. */
14439 {
14445 }
14447 /* Canonicalize
14448 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
14449 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
14454 {
14455 rtx constant;
14459 {
14462 }
14464 {
14467 }
14468 else
14472 {
14479 }
14480 }
14486 {
14489 }
14492 {
14495 }
14503 {
14506 }
14512 {
14516 {
14519 }
14523 }
14526 {
14530 {
14533 }
14537 }
14538 }
14541 }
14542 \f
14543 /* Print an integer constant expression in assembler syntax. Addition
14544 and subtraction are the only arithmetic that may appear in these
14545 expressions. FILE is the stdio stream to write to, X is the rtx, and
14546 CODE is the operand print code from the output string. */
14548 static void
14550 {
14554 {
14563 else
14564 {
14567 /* Mark the decl as referenced so that cgraph will
14568 output the function. */
14572 #if TARGET_MACHO
14576 #endif
14578 }
14586 /* FALLTHRU */
14597 /* This used to output parentheses around the expression,
14598 but that does not work on the 386 (either ATT or BSD assembler). */
14603 /* We can't handle floating point constants;
14604 TARGET_PRINT_OPERAND must handle them. */
14609 /* Some assemblers need integer constants to appear first. */
14611 {
14615 }
14616 else
14617 {
14622 }
14637 {
14641 }
14646 {
14665 /* FIXME: This might be @TPOFF in Sun ld too. */
14674 else
14684 else
14690 #if TARGET_MACHO
14695 #endif
14699 }
14704 }
14705 }
14707 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14708 We need to emit DTP-relative relocations. */
14710 static void ATTRIBUTE_UNUSED
14712 {
14717 {
14725 }
14726 }
14728 /* Return true if X is a representation of the PIC register. This copes
14729 with calls from ix86_find_base_term, where the register might have
14730 been replaced by a cselib value. */
14732 static bool
14734 {
14741 {
14749 }
14750 else
14752 }
14754 /* Helper function for ix86_delegitimize_address.
14755 Attempt to delegitimize TLS local-exec accesses. */
14757 static rtx
14759 {
14784 {
14789 }
14795 }
14797 /* In the name of slightly smaller debug output, and to cater to
14798 general assembler lossage, recognize PIC+GOTOFF and turn it back
14799 into a direct symbol reference.
14801 On Darwin, this is necessary to avoid a crash, because Darwin
14802 has a different PIC label for each routine but the DWARF debugging
14803 information is not associated with any particular routine, so it's
14804 necessary to remove references to the PIC label from RTL stored by
14805 the DWARF output code. */
14807 static rtx
14809 {
14811 /* addend is NULL or some rtx if x is something+GOTOFF where
14812 something doesn't include the PIC register. */
14814 /* reg_addend is NULL or a multiple of some register. */
14816 /* const_addend is NULL or a const_int. */
14818 /* This is the result, or NULL. */
14827 {
14834 {
14840 }
14847 {
14850 {
14855 }
14857 }
14862 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14863 and -mcmodel=medium -fpic. */
14864 }
14871 /* %ebx + GOT/GOTOFF */
14872 ;
14874 {
14875 /* %ebx + %reg * scale + GOT/GOTOFF */
14881 else
14882 {
14885 }
14886 }
14887 else
14893 {
14896 }
14917 {
14918 /* If the rest of original X doesn't involve the PIC register, add
14919 addend and subtract pic_offset_table_rtx. This can happen e.g.
14920 for code like:
14921 leal (%ebx, %ecx, 4), %ecx
14922 ...
14923 movl foo@GOTOFF(%ecx), %edx
14924 in which case we return (%ecx - %ebx) + foo
14925 or (%ecx - _GLOBAL_OFFSET_TABLE_) + foo if pseudo_pic_reg
14926 and reload has completed. */
14930 pic_offset_table_rtx),
14931 result);
14933 {
14937 }
14938 else
14940 }
14942 {
14946 }
14948 }
14950 /* If X is a machine specific address (i.e. a symbol or label being
14951 referenced as a displacement from the GOT implemented using an
14952 UNSPEC), then return the base term. Otherwise return X. */
14954 rtx
14956 {
14957 rtx term;
14960 {
14973 }
14976 }
14977 \f
14978 static void
14981 {
14985 {
14988 }
14993 {
14996 {
15015 }
15019 {
15038 }
15045 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
15046 Those same assemblers have the same but opposite lossage on cmov. */
15049 else
15054 {
15067 }
15074 else
15079 {
15092 }
15099 else
15109 else
15120 }
15122 }
15124 /* Print the name of register X to FILE based on its machine mode and number.
15125 If CODE is 'w', pretend the mode is HImode.
15126 If CODE is 'b', pretend the mode is QImode.
15127 If CODE is 'k', pretend the mode is SImode.
15128 If CODE is 'q', pretend the mode is DImode.
15129 If CODE is 'x', pretend the mode is V4SFmode.
15130 If CODE is 't', pretend the mode is V8SFmode.
15131 If CODE is 'g', pretend the mode is V16SFmode.
15132 If CODE is 'h', pretend the reg is the 'high' byte register.
15133 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
15134 If CODE is 'd', duplicate the operand for AVX instruction.
15135 */
15137 void
15139 {
15149 {
15153 }
15156 {
15159 }
15177 else
15191 {
15199 normal:
15215 {
15220 }
15224 }
15228 /* Irritatingly, AMD extended registers use
15229 different naming convention: "r%d[bwd]" */
15231 {
15234 {
15248 /* no suffix */
15253 }
15255 }
15258 {
15261 else
15263 }
15264 }
15266 /* Meaning of CODE:
15267 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
15268 C -- print opcode suffix for set/cmov insn.
15269 c -- like C, but print reversed condition
15270 F,f -- likewise, but for floating-point.
15271 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
15272 otherwise nothing
15273 R -- print embeded rounding and sae.
15274 r -- print only sae.
15275 z -- print the opcode suffix for the size of the current operand.
15276 Z -- likewise, with special suffixes for x87 instructions.
15277 * -- print a star (in certain assembler syntax)
15278 A -- print an absolute memory reference.
15279 E -- print address with DImode register names if TARGET_64BIT.
15280 w -- print the operand as if it's a "word" (HImode) even if it isn't.
15281 s -- print a shift double count, followed by the assemblers argument
15282 delimiter.
15283 b -- print the QImode name of the register for the indicated operand.
15284 %b0 would print %al if operands[0] is reg 0.
15285 w -- likewise, print the HImode name of the register.
15286 k -- likewise, print the SImode name of the register.
15287 q -- likewise, print the DImode name of the register.
15288 x -- likewise, print the V4SFmode name of the register.
15289 t -- likewise, print the V8SFmode name of the register.
15290 g -- likewise, print the V16SFmode name of the register.
15291 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
15292 y -- print "st(0)" instead of "st" as a register.
15293 d -- print duplicated register operand for AVX instruction.
15294 D -- print condition for SSE cmp instruction.
15295 P -- if PIC, print an @PLT suffix.
15296 p -- print raw symbol name.
15297 X -- don't print any sort of PIC '@' suffix for a symbol.
15298 & -- print some in-use local-dynamic symbol name.
15299 H -- print a memory address offset by 8; used for sse high-parts
15300 Y -- print condition for XOP pcom* instruction.
15301 + -- print a branch hint as 'cs' or 'ds' prefix
15302 ; -- print a semicolon (after prefixes due to bug in older gas).
15303 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
15304 @ -- print a segment register of thread base pointer load
15305 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
15306 ! -- print MPX prefix for jxx/call/ret instructions if required.
15307 */
15309 void
15311 {
15313 {
15315 {
15318 {
15324 /* Intel syntax. For absolute addresses, registers should not
15325 be surrounded by braces. */
15327 {
15332 }
15337 }
15343 /* Wrap address in an UNSPEC to declare special handling. */
15381 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15386 {
15400 output_operand_lossage
15403 }
15406 #endif
15411 {
15412 /* Opcodes don't get size suffixes if using Intel opcodes. */
15417 {
15435 output_operand_lossage
15438 }
15439 }
15442 warning
15444 /* FALLTHRU */
15447 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
15452 {
15454 {
15456 #ifdef HAVE_AS_IX86_FILDS
15458 #endif
15466 #ifdef HAVE_AS_IX86_FILDQ
15468 #else
15470 #endif
15475 }
15476 }
15478 {
15479 /* 387 opcodes don't get size suffixes
15480 if the operands are registers. */
15485 {
15501 }
15502 }
15503 else
15504 {
15505 output_operand_lossage
15508 }
15510 output_operand_lossage
15531 {
15534 }
15539 {
15590 }
15594 /* Little bit of braindamage here. The SSE compare instructions
15595 does use completely different names for the comparisons that the
15596 fp conditional moves. */
15598 {
15601 {
15604 }
15610 {
15613 }
15619 {
15622 }
15631 {
15634 }
15640 {
15643 }
15649 {
15652 }
15663 }
15668 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15671 #endif
15676 {
15680 }
15684 file);
15689 {
15693 }
15694 /* It doesn't actually matter what mode we use here, as we're
15695 only going to use this for printing. */
15697 /* Output 'qword ptr' for intel assembler dialect. */
15706 #ifdef HAVE_AS_IX86_HLE
15708 #else
15710 #endif
15712 #ifdef HAVE_AS_IX86_HLE
15714 #else
15716 #endif
15717 /* We do not want to print value of the operand. */
15746 {
15761 }
15774 {
15779 else
15782 }
15785 {
15786 rtx x;
15795 {
15800 {
15802 bool cputaken
15805 /* Emit hints only in the case default branch prediction
15806 heuristics would fail. */
15808 {
15809 /* We use 3e (DS) prefix for taken branches and
15810 2e (CS) prefix for not taken branches. */
15813 else
15815 }
15816 }
15817 }
15819 }
15822 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15824 #endif
15831 /* The kernel uses a different segment register for performance
15832 reasons; a system call would not have to trash the userspace
15833 segment register, which would be expensive. */
15836 else
15856 }
15857 }
15863 {
15864 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15867 {
15870 {
15879 else
15886 }
15888 /* Check for explicit size override (codes 'b', 'w', 'k',
15889 'q' and 'x') */
15903 }
15906 /* Avoid (%rip) for call operands. */
15912 else
15914 }
15917 {
15918 REAL_VALUE_TYPE r;
15926 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15930 else
15932 }
15935 {
15936 REAL_VALUE_TYPE r;
15945 }
15947 /* These float cases don't actually occur as immediate operands. */
15949 {
15954 }
15956 else
15957 {
15958 /* We have patterns that allow zero sets of memory, for instance.
15959 In 64-bit mode, we should probably support all 8-byte vectors,
15960 since we can in fact encode that into an immediate. */
15962 {
15965 }
15968 {
15970 {
15973 }
15976 {
15979 else
15981 }
15982 }
15987 else
15989 }
15990 }
15992 static bool
15994 {
15997 }
15998 \f
15999 /* Print a memory operand whose address is ADDR. */
16001 static void
16003 {
16012 {
16019 }
16021 {
16025 }
16027 {
16031 {
16034 }
16037 }
16039 {
16044 }
16045 else
16056 {
16067 }
16069 /* Use one byte shorter RIP relative addressing for 64bit mode. */
16071 {
16083 }
16085 {
16086 /* Displacement only requires special attention. */
16089 {
16093 }
16096 else
16098 }
16099 else
16100 {
16101 /* Print SImode register names to force addr32 prefix. */
16103 {
16104 #ifdef ENABLE_CHECKING
16107 {
16118 }
16119 #endif
16122 }
16124 && TARGET_X32
16125 && disp
16128 {
16129 /* X32 runs in 64-bit mode, where displacement, DISP, in
16130 address DISP(%r64), is encoded as 32-bit immediate sign-
16131 extended from 32-bit to 64-bit. For -0x40000300(%r64),
16132 address is %r64 + 0xffffffffbffffd00. When %r64 <
16133 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
16134 which is invalid for x32. The correct address is %r64
16135 - 0x40000300 == 0xf7ffdd64. To properly encode
16136 -0x40000300(%r64) for x32, we zero-extend negative
16137 displacement by forcing addr32 prefix which truncates
16138 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
16139 zero-extend all negative displacements, including -1(%rsp).
16140 However, for small negative displacements, sign-extension
16141 won't cause overflow. We only zero-extend negative
16142 displacements if they < -16*1024*1024, which is also used
16143 to check legitimate address displacements for PIC. */
16145 }
16148 {
16150 {
16155 else
16157 }
16163 {
16168 }
16170 }
16171 else
16172 {
16176 {
16177 /* Pull out the offset of a symbol; print any symbol itself. */
16181 {
16185 }
16193 else
16195 }
16199 {
16202 {
16206 }
16207 }
16210 else
16214 {
16219 }
16221 }
16222 }
16223 }
16225 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
16227 static bool
16229 {
16230 rtx op;
16237 {
16240 /* FIXME: This might be @TPOFF in Sun ld. */
16251 else
16263 else
16270 #if TARGET_MACHO
16276 #endif
16279 {
16284 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
16286 #else
16288 #endif
16291 }
16296 }
16299 }
16300 \f
16301 /* Split one or more double-mode RTL references into pairs of half-mode
16302 references. The RTL can be REG, offsettable MEM, integer constant, or
16303 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
16304 split and "num" is its length. lo_half and hi_half are output arrays
16305 that parallel "operands". */
16307 void
16310 {
16311 machine_mode half_mode;
16315 {
16324 }
16329 {
16332 /* simplify_subreg refuse to split volatile memory addresses,
16333 but we still have to handle it. */
16335 {
16338 }
16339 else
16340 {
16347 }
16348 }
16349 }
16350 \f
16351 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
16352 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
16353 is the expression of the binary operation. The output may either be
16354 emitted here, or returned to the caller, like all output_* functions.
16356 There is no guarantee that the operands are the same mode, as they
16357 might be within FLOAT or FLOAT_EXTEND expressions. */
16359 #ifndef SYSV386_COMPAT
16360 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
16361 wants to fix the assemblers because that causes incompatibility
16362 with gcc. No-one wants to fix gcc because that causes
16363 incompatibility with assemblers... You can use the option of
16364 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
16365 #define SYSV386_COMPAT 1
16366 #endif
16370 {
16376 #ifdef ENABLE_CHECKING
16377 /* Even if we do not want to check the inputs, this documents input
16378 constraints. Which helps in understanding the following code. */
16388 else
16390 #endif
16393 {
16398 else
16407 else
16416 else
16425 else
16432 }
16435 {
16437 {
16441 else
16443 }
16444 else
16445 {
16449 else
16451 }
16453 }
16457 {
16463 /* know operands[0] == operands[1]. */
16466 {
16469 }
16472 {
16474 /* How is it that we are storing to a dead operand[2]?
16475 Well, presumably operands[1] is dead too. We can't
16476 store the result to st(0) as st(0) gets popped on this
16477 instruction. Instead store to operands[2] (which I
16478 think has to be st(1)). st(1) will be popped later.
16479 gcc <= 2.8.1 didn't have this check and generated
16480 assembly code that the Unixware assembler rejected. */
16482 else
16485 }
16489 else
16496 {
16499 }
16502 {
16505 }
16508 {
16509 #if SYSV386_COMPAT
16510 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16511 derived assemblers, confusingly reverse the direction of
16512 the operation for fsub{r} and fdiv{r} when the
16513 destination register is not st(0). The Intel assembler
16514 doesn't have this brain damage. Read !SYSV386_COMPAT to
16515 figure out what the hardware really does. */
16518 else
16520 #else
16522 /* As above for fmul/fadd, we can't store to st(0). */
16524 else
16526 #endif
16528 }
16531 {
16532 #if SYSV386_COMPAT
16535 else
16537 #else
16540 else
16542 #endif
16544 }
16547 {
16550 else
16553 }
16555 {
16556 #if SYSV386_COMPAT
16558 #else
16560 #endif
16561 }
16562 else
16563 {
16564 #if SYSV386_COMPAT
16566 #else
16568 #endif
16569 }
16574 }
16578 }
16580 /* Check if a 256bit AVX register is referenced inside of EXP. */
16582 static bool
16584 {
16590 }
16592 /* Return needed mode for entity in optimize_mode_switching pass. */
16594 static int
16596 {
16598 {
16599 rtx link;
16601 /* Needed mode is set to AVX_U128_CLEAN if there are
16602 no 256bit modes used in function arguments. */
16604 link;
16606 {
16608 {
16613 }
16614 }
16617 }
16619 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16620 changes state only when a 256bit register is written to, but we need
16621 to prevent the compiler from moving optimal insertion point above
16622 eventual read from 256bit register. */
16629 }
16631 /* Return mode that i387 must be switched into
16632 prior to the execution of insn. */
16634 static int
16636 {
16639 /* The mode UNINITIALIZED is used to store control word after a
16640 function call or ASM pattern. The mode ANY specify that function
16641 has no requirements on the control word and make no changes in the
16642 bits we are interested in. */
16656 {
16679 }
16682 }
16684 /* Return mode that entity must be switched into
16685 prior to the execution of insn. */
16687 static int
16689 {
16691 {
16701 }
16703 }
16705 /* Check if a 256bit AVX register is referenced in stores. */
16707 static void
16709 {
16711 {
16714 }
16715 }
16717 /* Calculate mode of upper 128bit AVX registers after the insn. */
16719 static int
16721 {
16728 /* We know that state is clean after CALL insn if there are no
16729 256bit registers used in the function return register. */
16731 {
16736 }
16738 /* Otherwise, return current mode. Remember that if insn
16739 references AVX 256bit registers, the mode was already changed
16740 to DIRTY from MODE_NEEDED. */
16742 }
16744 /* Return the mode that an insn results in. */
16746 static int
16748 {
16750 {
16760 }
16761 }
16763 static int
16765 {
16766 tree arg;
16768 /* Entry mode is set to AVX_U128_DIRTY if there are
16769 256bit modes used in function arguments. */
16772 {
16777 }
16780 }
16782 /* Return a mode that ENTITY is assumed to be
16783 switched to at function entry. */
16785 static int
16787 {
16789 {
16799 }
16800 }
16802 static int
16804 {
16807 /* Exit mode is set to AVX_U128_DIRTY if there are
16808 256bit modes used in the function return register. */
16813 }
16815 /* Return a mode that ENTITY is assumed to be
16816 switched to at function exit. */
16818 static int
16820 {
16822 {
16832 }
16833 }
16835 static int
16837 {
16839 }
16841 /* Output code to initialize control word copies used by trunc?f?i and
16842 rounding patterns. CURRENT_MODE is set to current control word,
16843 while NEW_MODE is set to new control word. */
16845 static void
16847 {
16849 rtx new_mode;
16860 {
16862 {
16864 /* round toward zero (truncate) */
16870 /* round down toward -oo */
16877 /* round up toward +oo */
16884 /* mask precision exception for nearbyint() */
16891 }
16892 }
16893 else
16894 {
16896 {
16898 /* round toward zero (truncate) */
16904 /* round down toward -oo */
16910 /* round up toward +oo */
16916 /* mask precision exception for nearbyint() */
16923 }
16924 }
16930 }
16932 /* Emit vzeroupper. */
16934 void
16936 {
16939 /* Cancel automatic vzeroupper insertion if there are
16940 live call-saved SSE registers at the insertion point. */
16952 }
16954 /* Generate one or more insns to set ENTITY to MODE. */
16956 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
16957 is the set of hard registers live at the point where the insn(s)
16958 are to be inserted. */
16960 static void
16962 HARD_REG_SET regs_live)
16963 {
16965 {
16980 }
16981 }
16983 /* Output code for INSN to convert a float to a signed int. OPERANDS
16984 are the insn operands. The output may be [HSD]Imode and the input
16985 operand may be [SDX]Fmode. */
16989 {
16994 /* Jump through a hoop or two for DImode, since the hardware has no
16995 non-popping instruction. We used to do this a different way, but
16996 that was somewhat fragile and broke with post-reload splitters. */
17006 else
17007 {
17012 else
17016 }
17019 }
17021 /* Output code for x87 ffreep insn. The OPNO argument, which may only
17022 have the values zero or one, indicates the ffreep insn's operand
17023 from the OPERANDS array. */
17027 {
17029 #ifdef HAVE_AS_IX86_FFREEP
17031 #else
17032 {
17042 }
17043 #endif
17046 }
17049 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
17050 should be used. UNORDERED_P is true when fucom should be used. */
17054 {
17060 {
17063 }
17064 else
17065 {
17068 }
17071 {
17075 else
17077 else
17080 else
17082 }
17089 {
17091 {
17094 }
17095 else
17097 }
17100 && stack_top_dies
17103 {
17104 /* If both the top of the 387 stack dies, and the other operand
17105 is also a stack register that dies, then this must be a
17106 `fcompp' float compare */
17109 {
17110 /* There is no double popping fcomi variant. Fortunately,
17111 eflags is immune from the fstp's cc clobbering. */
17114 else
17117 }
17118 else
17119 {
17122 else
17124 }
17125 }
17126 else
17127 {
17128 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
17131 {
17139 NULL,
17140 NULL,
17147 NULL,
17148 NULL,
17149 NULL,
17150 NULL
17151 };
17166 }
17167 }
17169 void
17171 {
17174 #ifdef ASM_QUAD
17177 #else
17179 #endif
17182 }
17184 void
17186 {
17189 #ifdef ASM_QUAD
17192 #else
17194 #endif
17195 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
17201 #if TARGET_MACHO
17203 {
17207 }
17208 #endif
17209 else
17212 }
17213 \f
17214 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
17215 for the target. */
17217 void
17219 {
17220 rtx tmp;
17222 /* We play register width games, which are only valid after reload. */
17225 /* Avoid HImode and its attendant prefix byte. */
17231 {
17234 }
17237 }
17239 /* X is an unchanging MEM. If it is a constant pool reference, return
17240 the constant pool rtx, else NULL. */
17242 rtx
17244 {
17251 }
17253 void
17255 {
17263 {
17264 rtx tmp;
17268 {
17274 }
17277 }
17281 {
17284 rtx tmp;
17289 else
17293 {
17300 }
17301 }
17305 {
17307 {
17308 #if TARGET_MACHO
17309 /* dynamic-no-pic */
17311 {
17318 }
17320 {
17324 }
17327 else
17328 {
17336 }
17337 /* dynamic-no-pic */
17338 #endif
17339 }
17340 else
17341 {
17345 {
17351 }
17352 }
17353 }
17354 else
17355 {
17366 /* Force large constants in 64bit compilation into register
17367 to get them CSEed. */
17378 {
17379 /* If we are loading a floating point constant to a register,
17380 force the value to memory now, since we'll get better code
17381 out the back end. */
17385 {
17390 }
17391 }
17392 }
17395 }
17397 void
17399 {
17406 /* Force constants other than zero into memory. We do not know how
17407 the instructions used to build constants modify the upper 64 bits
17408 of the register, once we have that information we may be able
17409 to handle some of them more efficiently. */
17418 /* We need to check memory alignment for SSE mode since attribute
17419 can make operands unaligned. */
17424 {
17427 /* ix86_expand_vector_move_misalign() does not like constants ... */
17433 /* ... nor both arguments in memory. */
17441 }
17443 /* Make operand1 a register if it isn't already. */
17447 {
17450 }
17453 }
17455 /* Split 32-byte AVX unaligned load and store if needed. */
17457 static void
17459 {
17460 rtx m;
17464 machine_mode mode;
17467 {
17488 }
17491 {
17494 {
17501 }
17502 /* Normal *mov<mode>_internal pattern will handle
17503 unaligned loads just fine if misaligned_operand
17504 is true, and without the UNSPEC it can be combined
17505 with arithmetic instructions. */
17508 else
17510 }
17512 {
17515 {
17520 }
17521 else
17523 }
17524 else
17526 }
17528 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17529 straight to ix86_expand_vector_move. */
17530 /* Code generation for scalar reg-reg moves of single and double precision data:
17531 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17532 movaps reg, reg
17533 else
17534 movss reg, reg
17535 if (x86_sse_partial_reg_dependency == true)
17536 movapd reg, reg
17537 else
17538 movsd reg, reg
17540 Code generation for scalar loads of double precision data:
17541 if (x86_sse_split_regs == true)
17542 movlpd mem, reg (gas syntax)
17543 else
17544 movsd mem, reg
17546 Code generation for unaligned packed loads of single precision data
17547 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17548 if (x86_sse_unaligned_move_optimal)
17549 movups mem, reg
17551 if (x86_sse_partial_reg_dependency == true)
17552 {
17553 xorps reg, reg
17554 movlps mem, reg
17555 movhps mem+8, reg
17556 }
17557 else
17558 {
17559 movlps mem, reg
17560 movhps mem+8, reg
17561 }
17563 Code generation for unaligned packed loads of double precision data
17564 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17565 if (x86_sse_unaligned_move_optimal)
17566 movupd mem, reg
17568 if (x86_sse_split_regs == true)
17569 {
17570 movlpd mem, reg
17571 movhpd mem+8, reg
17572 }
17573 else
17574 {
17575 movsd mem, reg
17576 movhpd mem+8, reg
17577 }
17578 */
17580 void
17582 {
17591 {
17593 {
17597 {
17599 {
17602 }
17603 else
17605 }
17607 /* FALLTHRU */
17611 {
17626 }
17632 else
17640 }
17643 }
17647 {
17649 {
17653 {
17655 {
17658 }
17659 else
17661 }
17663 /* FALLTHRU */
17673 }
17676 }
17679 {
17680 /* Normal *mov<mode>_internal pattern will handle
17681 unaligned loads just fine if misaligned_operand
17682 is true, and without the UNSPEC it can be combined
17683 with arithmetic instructions. */
17689 /* ??? If we have typed data, then it would appear that using
17690 movdqu is the only way to get unaligned data loaded with
17691 integer type. */
17693 {
17695 {
17698 }
17700 /* We will eventually emit movups based on insn attributes. */
17704 }
17706 {
17707 rtx zero;
17710 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17711 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17713 {
17714 /* We will eventually emit movups based on insn attributes. */
17717 }
17719 /* When SSE registers are split into halves, we can avoid
17720 writing to the top half twice. */
17722 {
17725 }
17726 else
17727 {
17728 /* ??? Not sure about the best option for the Intel chips.
17729 The following would seem to satisfy; the register is
17730 entirely cleared, breaking the dependency chain. We
17731 then store to the upper half, with a dependency depth
17732 of one. A rumor has it that Intel recommends two movsd
17733 followed by an unpacklpd, but this is unconfirmed. And
17734 given that the dependency depth of the unpacklpd would
17735 still be one, I'm not sure why this would be better. */
17737 }
17743 }
17744 else
17745 {
17746 rtx t;
17749 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17750 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17752 {
17754 {
17757 }
17764 }
17768 else
17773 else
17782 }
17783 }
17785 {
17787 {
17790 /* We will eventually emit movups based on insn attributes. */
17792 }
17794 {
17796 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17797 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17799 /* We will eventually emit movups based on insn attributes. */
17801 else
17802 {
17807 }
17808 }
17809 else
17810 {
17815 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17816 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17818 {
17821 }
17822 else
17823 {
17828 }
17829 }
17830 }
17831 else
17833 }
17835 /* Helper function of ix86_fixup_binary_operands to canonicalize
17836 operand order. Returns true if the operands should be swapped. */
17838 static bool
17840 rtx operands[])
17841 {
17846 /* If the operation is not commutative, we can't do anything. */
17850 /* Highest priority is that src1 should match dst. */
17856 /* Next highest priority is that immediate constants come second. */
17862 /* Lowest priority is that memory references should come second. */
17869 }
17872 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17873 destination to use for the operation. If different from the true
17874 destination in operands[0], a copy operation will be required. */
17876 rtx
17878 rtx operands[])
17879 {
17884 /* Canonicalize operand order. */
17886 {
17887 /* It is invalid to swap operands of different modes. */
17891 }
17893 /* Both source operands cannot be in memory. */
17895 {
17896 /* Optimization: Only read from memory once. */
17898 {
17901 }
17904 else
17906 }
17908 /* If the destination is memory, and we do not have matching source
17909 operands, do things in registers. */
17913 /* Source 1 cannot be a constant. */
17917 /* Source 1 cannot be a non-matching memory. */
17921 /* Improve address combine. */
17930 }
17932 /* Similarly, but assume that the destination has already been
17933 set up properly. */
17935 void
17938 {
17941 }
17943 /* Attempt to expand a binary operator. Make the expansion closer to the
17944 actual machine, then just general_operand, which will allow 3 separate
17945 memory references (one output, two input) in a single insn. */
17947 void
17949 rtx operands[])
17950 {
17957 /* Emit the instruction. */
17964 {
17965 /* This is going to be an LEA; avoid splitting it later. */
17967 }
17968 else
17969 {
17972 }
17974 /* Fix up the destination if needed. */
17977 }
17979 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
17980 the given OPERANDS. */
17982 void
17984 rtx operands[])
17985 {
17988 {
17991 }
17993 {
17996 }
17997 /* Optimize (__m128i) d | (__m128i) e and similar code
17998 when d and e are float vectors into float vector logical
17999 insn. In C/C++ without using intrinsics there is no other way
18000 to express vector logical operation on float vectors than
18001 to cast them temporarily to integer vectors. */
18003 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
18012 {
18013 rtx dst;
18015 {
18024 {
18027 }
18028 else
18029 {
18034 }
18045 }
18046 }
18055 }
18057 /* Return TRUE or FALSE depending on whether the binary operator meets the
18058 appropriate constraints. */
18060 bool
18063 {
18068 /* Both source operands cannot be in memory. */
18072 /* Canonicalize operand order for commutative operators. */
18076 /* If the destination is memory, we must have a matching source operand. */
18080 /* Source 1 cannot be a constant. */
18084 /* Source 1 cannot be a non-matching memory. */
18086 /* Support "andhi/andsi/anddi" as a zero-extending move. */
18094 }
18096 /* Attempt to expand a unary operator. Make the expansion closer to the
18097 actual machine, then just general_operand, which will allow 2 separate
18098 memory references (one output, one input) in a single insn. */
18100 void
18102 rtx operands[])
18103 {
18110 /* If the destination is memory, and we do not have matching source
18111 operands, do things in registers. */
18113 {
18116 else
18118 }
18120 /* When source operand is memory, destination must match. */
18124 /* Emit the instruction. */
18130 else
18131 {
18134 }
18136 /* Fix up the destination if needed. */
18139 }
18141 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
18142 divisor are within the range [0-255]. */
18144 void
18147 {
18156 {
18169 }
18176 /* Use 8bit unsigned divimod if dividend and divisor are within
18177 the range [0-255]. */
18186 pc_rtx);
18191 /* Generate original signed/unsigned divimod. */
18196 /* Branch to the end. */
18200 /* Generate 8bit unsigned divide. */
18202 /* Don't use operands[0] for result of 8bit divide since not all
18203 registers support QImode ZERO_EXTRACT. */
18210 {
18213 }
18214 else
18215 {
18218 }
18220 /* Extract remainder from AH. */
18224 else
18225 {
18226 /* Need a new scratch register since the old one has result
18227 of 8bit divide. */
18231 }
18234 /* Zero extend quotient from AL. */
18240 }
18242 #define LEA_MAX_STALL (3)
18243 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
18245 /* Increase given DISTANCE in half-cycles according to
18246 dependencies between PREV and NEXT instructions.
18247 Add 1 half-cycle if there is no dependency and
18248 go to next cycle if there is some dependecy. */
18250 static unsigned int
18252 {
18268 }
18270 /* Function checks if instruction INSN defines register number
18271 REGNO1 or REGNO2. */
18273 static bool
18276 {
18277 df_ref def;
18287 }
18289 /* Function checks if instruction INSN uses register number
18290 REGNO as a part of address expression. */
18292 static bool
18294 {
18295 df_ref use;
18302 }
18304 /* Search backward for non-agu definition of register number REGNO1
18305 or register number REGNO2 in basic block starting from instruction
18306 START up to head of basic block or instruction INSN.
18308 Function puts true value into *FOUND var if definition was found
18309 and false otherwise.
18311 Distance in half-cycles between START and found instruction or head
18312 of BB is added to DISTANCE and returned. */
18314 static int
18318 {
18328 {
18330 {
18333 {
18336 {
18339 }
18340 }
18343 }
18348 }
18351 }
18353 /* Search backward for non-agu definition of register number REGNO1
18354 or register number REGNO2 in INSN's basic block until
18355 1. Pass LEA_SEARCH_THRESHOLD instructions, or
18356 2. Reach neighbour BBs boundary, or
18357 3. Reach agu definition.
18358 Returns the distance between the non-agu definition point and INSN.
18359 If no definition point, returns -1. */
18361 static int
18364 {
18375 {
18376 edge e;
18377 edge_iterator ei;
18382 {
18385 }
18391 else
18392 {
18397 {
18398 int bb_dist
18404 {
18411 }
18412 }
18415 }
18416 }
18418 /* get_attr_type may modify recog data. We want to make sure
18419 that recog data is valid for instruction INSN, on which
18420 distance_non_agu_define is called. INSN is unchanged here. */
18427 }
18429 /* Return the distance in half-cycles between INSN and the next
18430 insn that uses register number REGNO in memory address added
18431 to DISTANCE. Return -1 if REGNO0 is set.
18433 Put true value into *FOUND if register usage was found and
18434 false otherwise.
18435 Put true value into *REDEFINED if register redefinition was
18436 found and false otherwise. */
18438 static int
18442 {
18451 {
18454 /* If insn and start belong to the same bb, set prev to insn,
18455 so the call to increase_distance will increase the distance
18456 between insns by 1. */
18458 }
18463 {
18465 {
18468 {
18469 /* Return DISTANCE if OP0 is used in memory
18470 address in NEXT. */
18473 }
18476 {
18477 /* Return -1 if OP0 is set in NEXT. */
18480 }
18483 }
18489 }
18492 }
18494 /* Return the distance between INSN and the next insn that uses
18495 register number REGNO0 in memory address. Return -1 if no such
18496 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18498 static int
18500 {
18512 {
18513 edge e;
18514 edge_iterator ei;
18519 {
18522 }
18528 else
18529 {
18535 {
18536 int bb_dist
18541 {
18548 }
18549 }
18552 }
18553 }
18559 }
18561 /* Define this macro to tune LEA priority vs ADD, it take effect when
18562 there is a dilemma of choicing LEA or ADD
18563 Negative value: ADD is more preferred than LEA
18564 Zero: Netrual
18565 Positive value: LEA is more preferred than ADD*/
18566 #define IX86_LEA_PRIORITY 0
18568 /* Return true if usage of lea INSN has performance advantage
18569 over a sequence of instructions. Instructions sequence has
18570 SPLIT_COST cycles higher latency than lea latency. */
18572 static bool
18575 {
18578 /* For Silvermont if using a 2-source or 3-source LEA for
18579 non-destructive destination purposes, or due to wanting
18580 ability to use SCALE, the use of LEA is justified. */
18582 {
18590 }
18596 {
18597 /* If there is no non AGU operand definition, no AGU
18598 operand usage and split cost is 0 then both lea
18599 and non lea variants have same priority. Currently
18600 we prefer lea for 64 bit code and non lea on 32 bit
18601 code. */
18604 else
18606 }
18608 /* With longer definitions distance lea is more preferable.
18609 Here we change it to take into account splitting cost and
18610 lea priority. */
18613 /* If there is no use in memory addess then we just check
18614 that split cost exceeds AGU stall. */
18618 /* If this insn has both backward non-agu dependence and forward
18619 agu dependence, the one with short distance takes effect. */
18621 }
18623 /* Return true if it is legal to clobber flags by INSN and
18624 false otherwise. */
18626 static bool
18628 {
18630 df_ref use;
18631 bitmap live;
18634 {
18636 {
18643 }
18649 }
18653 }
18655 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18656 move and add to avoid AGU stalls. */
18658 bool
18660 {
18663 /* Check if we need to optimize. */
18667 /* Check it is correct to split here. */
18675 /* We need to split only adds with non destructive
18676 destination operand. */
18679 else
18681 }
18683 /* Return true if we should emit lea instruction instead of mov
18684 instruction. */
18686 bool
18688 {
18691 /* Check if we need to optimize. */
18695 /* Use lea for reg to reg moves only. */
18703 }
18705 /* Return true if we need to split lea into a sequence of
18706 instructions to avoid AGU stalls. */
18708 bool
18710 {
18716 /* Check we need to optimize. */
18720 /* The "at least two components" test below might not catch simple
18721 move or zero extension insns if parts.base is non-NULL and parts.disp
18722 is const0_rtx as the only components in the address, e.g. if the
18723 register is %rbp or %r13. As this test is much cheaper and moves or
18724 zero extensions are the common case, do this check first. */
18730 /* Check if it is OK to split here. */
18737 /* There should be at least two components in the address. */
18742 /* We should not split into add if non legitimate pic
18743 operand is used as displacement. */
18758 /* Compute how many cycles we will add to execution time
18759 if split lea into a sequence of instructions. */
18761 {
18762 /* Have to use mov instruction if non desctructive
18763 destination form is used. */
18767 /* Have to add index to base if both exist. */
18771 /* Have to use shift and adds if scale is 2 or greater. */
18773 {
18778 else
18780 }
18782 /* Have to use add instruction with immediate if
18783 disp is non zero. */
18787 /* Subtract the price of lea. */
18789 }
18793 }
18795 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18796 matches destination. RTX includes clobber of FLAGS_REG. */
18798 static void
18801 {
18808 }
18810 /* Return true if regno1 def is nearest to the insn. */
18812 static bool
18814 {
18821 {
18823 {
18826 }
18832 }
18834 /* None of the regs is defined in the bb. */
18836 }
18838 /* Split lea instructions into a sequence of instructions
18839 which are executed on ALU to avoid AGU stalls.
18840 It is assumed that it is allowed to clobber flags register
18841 at lea position. */
18843 void
18845 {
18861 {
18864 }
18867 {
18870 }
18876 {
18877 /* Case r1 = r1 + ... */
18879 {
18880 /* If we have a case r1 = r1 + C * r2 then we
18881 should use multiplication which is very
18882 expensive. Assume cost model is wrong if we
18883 have such case here. */
18888 }
18889 else
18890 {
18891 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18895 /* Use shift for scaling. */
18904 }
18905 }
18907 {
18910 }
18911 else
18912 {
18914 {
18917 }
18919 {
18922 }
18923 else
18924 {
18929 else
18930 {
18931 rtx tmp1;
18933 /* Find better operand for SET instruction, depending
18934 on which definition is farther from the insn. */
18937 else
18947 }
18950 }
18954 }
18955 }
18957 /* Return true if it is ok to optimize an ADD operation to LEA
18958 operation to avoid flag register consumation. For most processors,
18959 ADD is faster than LEA. For the processors like BONNELL, if the
18960 destination register of LEA holds an actual address which will be
18961 used soon, LEA is better and otherwise ADD is better. */
18963 bool
18965 {
18970 /* If a = b + c, (a!=b && a!=c), must use lea form. */
18978 }
18980 /* Return true if destination reg of SET_BODY is shift count of
18981 USE_BODY. */
18983 static bool
18985 {
18986 rtx set_dest;
18987 rtx shift_rtx;
18990 /* Retrieve destination of SET_BODY. */
18992 {
19001 use_body))
19006 }
19008 /* Retrieve shift count of USE_BODY. */
19010 {
19022 }
19030 {
19033 /* Return true if shift count is dest of SET_BODY. */
19035 {
19036 /* Add check since it can be invoked before register
19037 allocation in pre-reload schedule. */
19043 }
19044 }
19047 }
19049 /* Return true if destination reg of SET_INSN is shift count of
19050 USE_INSN. */
19052 bool
19054 {
19057 }
19059 /* Return TRUE or FALSE depending on whether the unary operator meets the
19060 appropriate constraints. */
19062 bool
19064 machine_mode,
19066 {
19067 /* If one of operands is memory, source and destination must match. */
19073 }
19075 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
19076 are ok, keeping in mind the possible movddup alternative. */
19078 bool
19080 {
19086 }
19088 /* Post-reload splitter for converting an SF or DFmode value in an
19089 SSE register into an unsigned SImode. */
19091 void
19093 {
19094 machine_mode vecmode;
19104 /* Load up the value into the low element. We must ensure that the other
19105 elements are valid floats -- zero is the easiest such value. */
19107 {
19110 else
19112 }
19113 else
19114 {
19119 else
19121 }
19141 else
19146 }
19148 /* Convert an unsigned DImode value into a DFmode, using only SSE.
19149 Expects the 64-bit DImode to be supplied in a pair of integral
19150 registers. Requires SSE2; will use SSE3 if available. For x86_32,
19151 -mfpmath=sse, !optimize_size only. */
19153 void
19155 {
19159 rtx x;
19165 {
19168 }
19169 else
19170 {
19174 }
19182 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
19185 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
19186 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
19187 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
19188 (0x1.0p84 + double(fp_value_hi_xmm)).
19189 Note these exponents differ by 32. */
19193 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
19194 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
19203 /* Add the upper and lower DFmode values together. */
19206 else
19207 {
19211 }
19214 }
19216 /* Not used, but eases macroization of patterns. */
19217 void
19219 {
19221 }
19223 /* Convert an unsigned SImode value into a DFmode. Only currently used
19224 for SSE, but applicable anywhere. */
19226 void
19228 {
19229 REAL_VALUE_TYPE TWO31r;
19244 }
19246 /* Convert a signed DImode value into a DFmode. Only used for SSE in
19247 32-bit mode; otherwise we have a direct convert instruction. */
19249 void
19251 {
19252 REAL_VALUE_TYPE TWO32r;
19270 }
19272 /* Convert an unsigned SImode value into a SFmode, using only SSE.
19273 For x86_32, -mfpmath=sse, !optimize_size only. */
19274 void
19276 {
19277 REAL_VALUE_TYPE ONE16r;
19296 }
19298 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
19299 a vector of unsigned ints VAL to vector of floats TARGET. */
19301 void
19303 {
19305 REAL_VALUE_TYPE TWO16r;
19312 else
19317 OPTAB_DIRECT);
19328 OPTAB_DIRECT);
19330 OPTAB_DIRECT);
19333 }
19335 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
19336 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
19337 This is done by doing just signed conversion if < 0x1p31, and otherwise by
19338 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
19340 rtx
19342 {
19343 REAL_VALUE_TYPE TWO31r;
19358 {
19364 }
19373 OPTAB_DIRECT);
19374 else
19375 {
19381 OPTAB_DIRECT);
19382 }
19385 }
19387 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
19388 then replicate the value for all elements of the vector
19389 register. */
19391 rtx
19393 {
19395 rtvec v;
19396 machine_mode scalar_mode;
19399 {
19432 }
19433 }
19435 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
19436 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
19437 for an SSE register. If VECT is true, then replicate the mask for
19438 all elements of the vector register. If INVERT is true, then create
19439 a mask excluding the sign bit. */
19441 rtx
19443 {
19445 wide_int w;
19449 {
19480 }
19487 /* Force this value into the low part of a fp vector constant. */
19496 }
19498 /* Generate code for floating point ABS or NEG. */
19500 void
19502 rtx operands[])
19503 {
19514 {
19520 }
19522 /* NEG and ABS performed with SSE use bitwise mask operations.
19523 Create the appropriate mask now. */
19526 else
19536 {
19538 rtvec par;
19543 else
19544 {
19547 }
19549 }
19550 else
19552 }
19554 /* Expand a copysign operation. Special case operand 0 being a constant. */
19556 void
19558 {
19572 else
19576 {
19583 {
19586 else
19587 {
19591 }
19592 }
19602 else
19606 }
19607 else
19608 {
19618 else
19622 }
19623 }
19625 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19626 be a constant, and so has already been expanded into a vector constant. */
19628 void
19630 {
19646 {
19649 }
19650 }
19652 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19653 so we have to do two masks. */
19655 void
19657 {
19672 {
19673 /* Shouldn't happen often (it's useless, obviously), but when it does
19674 we'd generate incorrect code if we continue below. */
19677 }
19680 {
19691 }
19692 else
19693 {
19695 {
19697 }
19699 {
19703 }
19707 {
19710 }
19712 {
19717 }
19719 }
19723 }
19725 /* Return TRUE or FALSE depending on whether the first SET in INSN
19726 has source and destination with matching CC modes, and that the
19727 CC mode is at least as constrained as REQ_MODE. */
19729 bool
19731 {
19732 rtx set;
19733 machine_mode set_mode;
19743 {
19753 /* FALLTHRU */
19757 /* FALLTHRU */
19761 /* FALLTHRU */
19775 }
19778 }
19780 /* Generate insn patterns to do an integer compare of OPERANDS. */
19782 static rtx
19784 {
19785 machine_mode cmpmode;
19791 /* This is very simple, but making the interface the same as in the
19792 FP case makes the rest of the code easier. */
19796 /* Return the test that should be put into the flags user, i.e.
19797 the bcc, scc, or cmov instruction. */
19799 }
19801 /* Figure out whether to use ordered or unordered fp comparisons.
19802 Return the appropriate mode to use. */
19804 machine_mode
19806 {
19807 /* ??? In order to make all comparisons reversible, we do all comparisons
19808 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19809 all forms trapping and nontrapping comparisons, we can make inequality
19810 comparisons trapping again, since it results in better code when using
19811 FCOM based compares. */
19813 }
19815 machine_mode
19817 {
19821 {
19824 }
19827 {
19828 /* Only zero flag is needed. */
19832 /* Codes needing carry flag. */
19835 /* Detect overflow checks. They need just the carry flag. */
19839 else
19844 /* Codes possibly doable only with sign flag when
19845 comparing against zero. */
19850 else
19851 /* For other cases Carry flag is not required. */
19853 /* Codes doable only with sign flag when comparing
19854 against zero, but we miss jump instruction for it
19855 so we need to use relational tests against overflow
19856 that thus needs to be zero. */
19861 else
19863 /* strcmp pattern do (use flags) and combine may ask us for proper
19864 mode. */
19869 }
19870 }
19872 /* Return the fixed registers used for condition codes. */
19874 static bool
19876 {
19880 }
19882 /* If two condition code modes are compatible, return a condition code
19883 mode which is compatible with both. Otherwise, return
19884 VOIDmode. */
19886 static machine_mode
19888 {
19905 {
19919 {
19933 }
19937 /* These are only compatible with themselves, which we already
19938 checked above. */
19940 }
19941 }
19944 /* Return a comparison we can do and that it is equivalent to
19945 swap_condition (code) apart possibly from orderedness.
19946 But, never change orderedness if TARGET_IEEE_FP, returning
19947 UNKNOWN in that case if necessary. */
19949 static enum rtx_code
19951 {
19953 {
19964 }
19965 }
19967 /* Return cost of comparison CODE using the best strategy for performance.
19968 All following functions do use number of instructions as a cost metrics.
19969 In future this should be tweaked to compute bytes for optimize_size and
19970 take into account performance of various instructions on various CPUs. */
19972 static int
19974 {
19977 /* The cost of code using bit-twiddling on %ah. */
19979 {
20002 }
20005 {
20012 }
20013 }
20015 /* Return strategy to use for floating-point. We assume that fcomi is always
20016 preferrable where available, since that is also true when looking at size
20017 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
20019 enum ix86_fpcmp_strategy
20021 {
20022 /* Do fcomi/sahf based test when profitable. */
20031 }
20033 /* Swap, force into registers, or otherwise massage the two operands
20034 to a fp comparison. The operands are updated in place; the new
20035 comparison code is returned. */
20037 static enum rtx_code
20039 {
20045 /* All of the unordered compare instructions only work on registers.
20046 The same is true of the fcomi compare instructions. The XFmode
20047 compare instructions require registers except when comparing
20048 against zero or when converting operand 1 from fixed point to
20049 floating point. */
20058 {
20061 }
20062 else
20063 {
20064 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
20065 things around if they appear profitable, otherwise force op0
20066 into a register. */
20072 {
20075 {
20078 }
20079 }
20085 {
20090 {
20093 }
20094 else
20096 }
20097 }
20099 /* Try to rearrange the comparison to make it cheaper. */
20103 {
20108 }
20113 }
20115 /* Convert comparison codes we use to represent FP comparison to integer
20116 code that will result in proper branch. Return UNKNOWN if no such code
20117 is available. */
20119 enum rtx_code
20121 {
20123 {
20146 }
20147 }
20149 /* Generate insn patterns to do a floating point compare of OPERANDS. */
20151 static rtx
20153 {
20160 /* Do fcomi/sahf based test when profitable. */
20162 {
20182 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
20189 /* In the unordered case, we have to check C2 for NaN's, which
20190 doesn't happen to work out to anything nice combination-wise.
20191 So do some bit twiddling on the value we've got in AH to come
20192 up with an appropriate set of condition codes. */
20196 {
20200 {
20203 }
20204 else
20205 {
20211 }
20216 {
20221 }
20222 else
20223 {
20226 }
20231 {
20234 }
20235 else
20236 {
20240 }
20245 {
20251 }
20252 else
20253 {
20256 }
20261 {
20266 }
20267 else
20268 {
20271 }
20276 {
20281 }
20282 else
20283 {
20286 }
20300 }
20305 }
20307 /* Return the test that should be put into the flags user, i.e.
20308 the bcc, scc, or cmov instruction. */
20311 const0_rtx);
20312 }
20314 static rtx
20316 {
20317 rtx ret;
20323 {
20326 }
20327 else
20331 }
20333 void
20335 {
20337 rtx tmp;
20340 {
20347 simple:
20351 pc_rtx);
20359 /* Expand DImode branch into multiple compare+branch. */
20360 {
20364 machine_mode submode;
20367 {
20370 }
20377 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
20378 avoid two branches. This costs one extra insn, so disable when
20379 optimizing for size. */
20384 {
20402 }
20404 /* Otherwise, if we are doing less-than or greater-or-equal-than,
20405 op1 is a constant and the low word is zero, then we can just
20406 examine the high word. Similarly for low word -1 and
20407 less-or-equal-than or greater-than. */
20411 {
20414 {
20417 }
20421 {
20424 }
20428 }
20430 /* Otherwise, we need two or three jumps. */
20439 {
20453 }
20455 /*
20456 * a < b =>
20457 * if (hi(a) < hi(b)) goto true;
20458 * if (hi(a) > hi(b)) goto false;
20459 * if (lo(a) < lo(b)) goto true;
20460 * false:
20461 */
20473 }
20478 }
20479 }
20481 /* Split branch based on floating point condition. */
20482 void
20485 {
20486 rtx condition;
20487 rtx i;
20490 {
20493 }
20496 tmp);
20504 }
20506 void
20508 {
20509 rtx ret;
20516 }
20518 /* Expand comparison setting or clearing carry flag. Return true when
20519 successful and set pop for the operation. */
20520 static bool
20522 {
20523 machine_mode mode =
20526 /* Do not handle double-mode compares that go through special path. */
20531 {
20532 rtx compare_op;
20537 /* Shortcut: following common codes never translate
20538 into carry flag compares. */
20543 /* These comparisons require zero flag; swap operands so they won't. */
20546 {
20549 }
20551 /* Try to expand the comparison and verify that we end up with
20552 carry flag based comparison. This fails to be true only when
20553 we decide to expand comparison using arithmetic that is not
20554 too common scenario. */
20563 else
20572 }
20578 {
20583 /* Convert a==0 into (unsigned)a<1. */
20592 /* Convert a>b into b<a or a>=b-1. */
20596 {
20598 /* Bail out on overflow. We still can swap operands but that
20599 would force loading of the constant into register. */
20604 }
20605 else
20606 {
20609 }
20612 /* Convert a>=0 into (unsigned)a<0x80000000. */
20630 }
20631 /* Swapping operands may cause constant to appear as first operand. */
20633 {
20637 }
20641 }
20643 bool
20645 {
20648 rtx compare_op;
20670 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20671 HImode insns, we'd be swallowed in word prefix ops. */
20677 {
20681 HOST_WIDE_INT diff;
20684 /* Sign bit compares are better done using shifts than we do by using
20685 sbb. */
20688 {
20689 /* Detect overlap between destination and compare sources. */
20693 {
20694 rtx flags;
20703 {
20705 compare_code
20707 }
20709 /* To simplify rest of code, restrict to the GEU case. */
20711 {
20715 }
20716 else
20717 {
20720 reverse_condition_maybe_unordered
20722 else
20725 }
20734 else
20737 }
20738 else
20739 {
20742 else
20743 {
20746 }
20748 }
20751 {
20752 /*
20753 * cmpl op0,op1
20754 * sbbl dest,dest
20755 * [addl dest, ct]
20756 *
20757 * Size 5 - 8.
20758 */
20763 }
20765 {
20766 /*
20767 * cmpl op0,op1
20768 * sbbl dest,dest
20769 * orl $ct, dest
20770 *
20771 * Size 8.
20772 */
20776 }
20778 {
20779 /*
20780 * cmpl op0,op1
20781 * sbbl dest,dest
20782 * notl dest
20783 * [addl dest, cf]
20784 *
20785 * Size 8 - 11.
20786 */
20792 }
20793 else
20794 {
20795 /*
20796 * cmpl op0,op1
20797 * sbbl dest,dest
20798 * [notl dest]
20799 * andl cf - ct, dest
20800 * [addl dest, ct]
20801 *
20802 * Size 8 - 11.
20803 */
20806 {
20810 }
20820 }
20826 }
20829 {
20834 {
20837 /* We may be reversing unordered compare to normal compare, that
20838 is not valid in general (we may convert non-trapping condition
20839 to trapping one), however on i386 we currently emit all
20840 comparisons unordered. */
20842 }
20843 else
20846 {
20850 }
20851 }
20856 {
20861 {
20866 }
20867 }
20869 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20873 {
20874 /* If lea code below could be used, only optimize
20875 if it results in a 2 insn sequence. */
20881 {
20882 /*
20883 * notl op1 (if necessary)
20884 * sarl $31, op1
20885 * orl cf, op1
20886 */
20888 {
20892 }
20903 }
20904 }
20912 {
20913 /*
20914 * xorl dest,dest
20915 * cmpl op1,op2
20916 * setcc dest
20917 * lea cf(dest*(ct-cf)),dest
20918 *
20919 * Size 14.
20920 *
20921 * This also catches the degenerate setcc-only case.
20922 */
20924 rtx tmp;
20930 /* On x86_64 the lea instruction operates on Pmode, so we need
20931 to get arithmetics done in proper mode to match. */
20934 else
20935 {
20936 rtx out1;
20939 nops++;
20941 {
20943 nops++;
20944 }
20945 }
20947 {
20949 nops++;
20950 }
20952 {
20955 else
20957 }
20962 }
20964 /*
20965 * General case: Jumpful:
20966 * xorl dest,dest cmpl op1, op2
20967 * cmpl op1, op2 movl ct, dest
20968 * setcc dest jcc 1f
20969 * decl dest movl cf, dest
20970 * andl (cf-ct),dest 1:
20971 * addl ct,dest
20972 *
20973 * Size 20. Size 14.
20974 *
20975 * This is reasonably steep, but branch mispredict costs are
20976 * high on modern cpus, so consider failing only if optimizing
20977 * for space.
20978 */
20983 {
20985 {
20990 {
20993 /* We may be reversing unordered compare to normal compare,
20994 that is not valid in general (we may convert non-trapping
20995 condition to trapping one), however on i386 we currently
20996 emit all comparisons unordered. */
20998 }
20999 else
21000 {
21004 }
21007 {
21011 }
21012 }
21015 {
21016 /* notl op1 (if needed)
21017 sarl $31, op1
21018 andl (cf-ct), op1
21019 addl ct, op1
21021 For x < 0 (resp. x <= -1) there will be no notl,
21022 so if possible swap the constants to get rid of the
21023 complement.
21024 True/false will be -1/0 while code below (store flag
21025 followed by decrement) is 0/-1, so the constants need
21026 to be exchanged once more. */
21029 {
21032 }
21033 else
21037 }
21038 else
21039 {
21043 constm1_rtx,
21045 }
21057 }
21058 }
21061 {
21062 /* Try a few things more with specific constants and a variable. */
21064 optab op;
21070 /* If one of the two operands is an interesting constant, load a
21071 constant with the above and mask it in with a logical operation. */
21074 {
21080 else
21082 }
21084 {
21090 else
21092 }
21093 else
21100 /* Recurse to get the constant loaded. */
21104 /* Mask in the interesting variable. */
21106 OPTAB_WIDEN);
21111 }
21113 /*
21114 * For comparison with above,
21115 *
21116 * movl cf,dest
21117 * movl ct,tmp
21118 * cmpl op1,op2
21119 * cmovcc tmp,dest
21120 *
21121 * Size 15.
21122 */
21144 }
21146 /* Swap, force into registers, or otherwise massage the two operands
21147 to an sse comparison with a mask result. Thus we differ a bit from
21148 ix86_prepare_fp_compare_args which expects to produce a flags result.
21150 The DEST operand exists to help determine whether to commute commutative
21151 operators. The POP0/POP1 operands are updated in place. The new
21152 comparison code is returned, or UNKNOWN if not implementable. */
21154 static enum rtx_code
21157 {
21159 {
21162 /* AVX supports all the needed comparisons. */
21165 /* We have no LTGT as an operator. We could implement it with
21166 NE & ORDERED, but this requires an extra temporary. It's
21167 not clear that it's worth it. */
21174 /* These are supported directly. */
21181 /* AVX has 3 operand comparisons, no need to swap anything. */
21184 /* For commutative operators, try to canonicalize the destination
21185 operand to be first in the comparison - this helps reload to
21186 avoid extra moves. */
21189 /* FALLTHRU */
21195 /* These are not supported directly before AVX, and furthermore
21196 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
21197 comparison operands to transform into something that is
21198 supported. */
21205 }
21208 }
21210 /* Detect conditional moves that exactly match min/max operational
21211 semantics. Note that this is IEEE safe, as long as we don't
21212 interchange the operands.
21214 Returns FALSE if this conditional move doesn't match a MIN/MAX,
21215 and TRUE if the operation is successful and instructions are emitted. */
21217 static bool
21220 {
21221 machine_mode mode;
21223 rtx tmp;
21226 ;
21229 else
21236 else
21241 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
21242 but MODE may be a vector mode and thus not appropriate. */
21244 {
21246 rtvec v;
21251 }
21252 else
21253 {
21256 }
21260 }
21262 /* Expand an sse vector comparison. Return the register with the result. */
21264 static rtx
21267 {
21271 /* In general case result of comparison can differ from operands' type. */
21272 machine_mode cmp_mode;
21274 /* In AVX512F the result of comparison is an integer mask. */
21276 rtx x;
21279 {
21284 }
21285 else
21298 /* Compare patterns for int modes are unspec in AVX512F only. */
21300 {
21304 {
21321 }
21324 {
21327 }
21328 }
21332 {
21335 }
21336 else
21340 }
21342 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
21343 operations. This is used for both scalar and vector conditional moves. */
21345 static void
21347 {
21351 /* In AVX512F the result of comparison is an integer mask. */
21359 {
21361 }
21364 {
21368 }
21371 {
21376 }
21379 {
21383 }
21386 {
21393 op_true,
21394 op_false)));
21395 }
21396 else
21397 {
21407 {
21421 {
21428 }
21443 {
21450 }
21474 }
21477 {
21481 }
21482 else
21483 {
21489 else
21501 }
21502 }
21503 }
21505 /* Expand a floating-point conditional move. Return true if successful. */
21507 bool
21509 {
21517 {
21518 machine_mode cmode;
21520 /* Since we've no cmove for sse registers, don't force bad register
21521 allocation just to gain access to it. Deny movcc when the
21522 comparison mode doesn't match the move mode. */
21541 }
21548 /* The floating point conditional move instructions don't directly
21549 support conditions resulting from a signed integer comparison. */
21553 {
21558 }
21565 }
21567 /* Expand a floating-point vector conditional move; a vcond operation
21568 rather than a movcc operation. */
21570 bool
21572 {
21574 rtx cmp;
21579 {
21580 rtx temp;
21582 {
21599 }
21601 OPTAB_DIRECT);
21604 }
21614 }
21616 /* Expand a signed/unsigned integral vector conditional move. */
21618 bool
21620 {
21630 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21631 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21640 {
21644 {
21650 }
21653 {
21659 }
21660 }
21669 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21673 ;
21674 else
21675 {
21676 /* Canonicalize the comparison to EQ, GT, GTU. */
21678 {
21695 /* FALLTHRU */
21705 }
21707 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21709 {
21711 {
21713 /* SSE4.1 supports EQ. */
21720 /* SSE4.2 supports GT/GTU. */
21727 }
21728 }
21730 /* Unsigned parallel compare is not supported by the hardware.
21731 Play some tricks to turn this into a signed comparison
21732 against 0. */
21734 {
21738 {
21745 {
21750 {
21759 }
21760 /* Subtract (-(INT MAX) - 1) from both operands to make
21761 them signed. */
21772 }
21781 /* Perform a parallel unsigned saturating subtraction. */
21793 }
21794 }
21795 }
21797 /* Allow the comparison to be done in one mode, but the movcc to
21798 happen in another mode. */
21800 {
21803 }
21804 else
21805 {
21811 }
21816 }
21818 /* AVX512F does support 64-byte integer vector operations,
21819 thus the longest vector we are faced with is V64QImode. */
21820 #define MAX_VECT_LEN 64
21822 struct expand_vec_perm_d
21823 {
21826 machine_mode vmode;
21830 };
21832 static bool
21835 {
21836 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21837 expander, so args are either in d, or in op0, op1 etc. */
21843 {
21874 {
21877 }
21881 {
21884 }
21888 {
21891 }
21907 {
21910 }
21914 {
21917 }
21921 {
21924 }
21928 }
21933 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21934 expander, so args are either in d, or in op0, op1 etc. */
21936 {
21944 }
21948 }
21950 /* Expand a variable vector permutation. */
21952 void
21954 {
21965 /* Number of elements in the vector. */
21974 {
21976 {
21977 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
21978 an constant shuffle operand. With a tiny bit of effort we can
21979 use VPERMD instead. A re-interpretation stall for V4DFmode is
21980 unfortunate but there's no avoiding it.
21981 Similarly for V16HImode we don't have instructions for variable
21982 shuffling, while for V32QImode we can use after preparing suitable
21983 masks vpshufb; vpshufb; vpermq; vpor. */
21986 {
21990 }
21991 else
21992 {
21996 }
21999 /* Replicate the low bits of the V4DImode mask into V8SImode:
22000 mask = { A B C D }
22001 t1 = { A A B B C C D D }. */
22009 else
22012 /* Multiply the shuffle indicies by two. */
22014 OPTAB_DIRECT);
22016 /* Add one to the odd shuffle indicies:
22017 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
22019 {
22022 }
22026 OPTAB_DIRECT);
22028 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
22033 }
22036 {
22038 /* The VPERMD and VPERMPS instructions already properly ignore
22039 the high bits of the shuffle elements. No need for us to
22040 perform an AND ourselves. */
22042 {
22047 }
22048 else
22049 {
22055 }
22062 else
22063 {
22069 }
22073 /* By combining the two 128-bit input vectors into one 256-bit
22074 input vector, we can use VPERMD and VPERMPS for the full
22075 two-operand shuffle. */
22107 /* From mask create two adjusted masks, which contain the same
22108 bits as mask in the low 7 bits of each vector element.
22109 The first mask will have the most significant bit clear
22110 if it requests element from the same 128-bit lane
22111 and MSB set if it requests element from the other 128-bit lane.
22112 The second mask will have the opposite values of the MSB,
22113 and additionally will have its 128-bit lanes swapped.
22114 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
22115 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
22116 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
22117 stands for other 12 bytes. */
22118 /* The bit whether element is from the same lane or the other
22119 lane is bit 4, so shift it up by 3 to the MSB position. */
22123 /* Clear MSB bits from the mask just in case it had them set. */
22125 /* After this t1 will have MSB set for elements from other lane. */
22127 /* Clear bits other than MSB. */
22129 /* Or in the lower bits from mask into t3. */
22131 /* And invert MSB bits in t1, so MSB is set for elements from the same
22132 lane. */
22134 /* Swap 128-bit lanes in t3. */
22139 /* And or in the lower bits from mask into t1. */
22142 {
22143 /* Each of these shuffles will put 0s in places where
22144 element from the other 128-bit lane is needed, otherwise
22145 will shuffle in the requested value. */
22149 /* For t3 the 128-bit lanes are swapped again. */
22154 /* And oring both together leads to the result. */
22161 }
22164 /* Similarly to the above one_operand_shuffle code,
22165 just for repeated twice for each operand. merge_two:
22166 code will merge the two results together. */
22190 }
22191 }
22194 {
22195 /* The XOP VPPERM insn supports three inputs. By ignoring the
22196 one_operand_shuffle special case, we avoid creating another
22197 set of constant vectors in memory. */
22200 /* mask = mask & {2*w-1, ...} */
22202 }
22203 else
22204 {
22205 /* mask = mask & {w-1, ...} */
22207 }
22215 /* For non-QImode operations, convert the word permutation control
22216 into a byte permutation control. */
22218 {
22223 /* Convert mask to vector of chars. */
22226 /* Replicate each of the input bytes into byte positions:
22227 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
22228 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
22229 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
22236 else
22239 /* Convert it into the byte positions by doing
22240 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
22246 }
22248 /* The actual shuffle operations all operate on V16QImode. */
22253 {
22260 }
22262 {
22269 }
22270 else
22271 {
22275 /* Shuffle the two input vectors independently. */
22281 merge_two:
22282 /* Then merge them together. The key is whether any given control
22283 element contained a bit set that indicates the second word. */
22287 {
22288 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
22289 more shuffle to convert the V2DI input mask into a V4SI
22290 input mask. At which point the masking that expand_int_vcond
22291 will work as desired. */
22299 }
22321 }
22322 }
22324 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
22325 true if we should do zero extension, else sign extension. HIGH_P is
22326 true if we want the N/2 high elements, else the low elements. */
22328 void
22330 {
22332 rtx tmp;
22335 {
22341 {
22345 else
22348 extract
22354 else
22357 extract
22363 else
22366 extract
22372 else
22375 extract
22381 else
22384 extract
22390 else
22393 extract
22399 else
22405 else
22411 else
22416 }
22419 {
22422 }
22424 {
22425 /* Shift higher 8 bytes to lower 8 bytes. */
22430 }
22431 else
22435 }
22436 else
22437 {
22441 {
22445 else
22451 else
22457 else
22462 }
22466 else
22473 }
22474 }
22476 /* Expand conditional increment or decrement using adb/sbb instructions.
22477 The default case using setcc followed by the conditional move can be
22478 done by generic code. */
22479 bool
22481 {
22483 rtx flags;
22485 rtx compare_op;
22488 machine_mode mode;
22503 {
22506 }
22509 {
22513 reverse_condition_maybe_unordered
22515 else
22517 }
22521 /* Construct either adc or sbb insn. */
22523 {
22525 {
22540 }
22541 }
22542 else
22543 {
22545 {
22560 }
22561 }
22565 }
22568 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22569 but works for floating pointer parameters and nonoffsetable memories.
22570 For pushes, it returns just stack offsets; the values will be saved
22571 in the right order. Maximally three parts are generated. */
22573 static int
22575 {
22580 else
22586 /* Optimize constant pool reference to immediates. This is used by fp
22587 moves, that force all constants to memory to allow combining. */
22589 {
22593 }
22596 {
22597 /* The only non-offsetable memories we handle are pushes. */
22606 }
22609 {
22611 /* Caution: if we looked through a constant pool memory above,
22612 the operand may actually have a different mode now. That's
22613 ok, since we want to pun this all the way back to an integer. */
22617 }
22620 {
22623 else
22624 {
22628 {
22632 }
22634 {
22639 }
22641 {
22642 REAL_VALUE_TYPE r;
22647 {
22654 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22655 long double may not be 80-bit. */
22664 }
22667 }
22668 else
22670 }
22671 }
22672 else
22673 {
22677 {
22680 {
22684 }
22686 {
22690 }
22692 {
22693 REAL_VALUE_TYPE r;
22699 /* real_to_target puts 32-bit pieces in each long. */
22701 gen_int_mode
22704 DImode);
22708 else
22710 gen_int_mode
22713 DImode);
22714 }
22715 else
22717 }
22718 }
22721 }
22723 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22724 Return false when normal moves are needed; true when all required
22725 insns have been emitted. Operands 2-4 contain the input values
22726 int the correct order; operands 5-7 contain the output values. */
22728 void
22730 {
22738 /* The DFmode expanders may ask us to move double.
22739 For 64bit target this is single move. By hiding the fact
22740 here we simplify i386.md splitters. */
22742 {
22743 /* Optimize constant pool reference to immediates. This is used by
22744 fp moves, that force all constants to memory to allow combining. */
22751 {
22754 }
22755 else
22760 }
22762 /* The only non-offsettable memory we handle is push. */
22765 else
22772 /* When emitting push, take care for source operands on the stack. */
22775 {
22778 /* Compensate for the stack decrement by 4. */
22783 /* src_base refers to the stack pointer and is
22784 automatically decreased by emitted push. */
22788 }
22790 /* We need to do copy in the right order in case an address register
22791 of the source overlaps the destination. */
22793 {
22794 rtx tmp;
22797 {
22801 collisions++;
22802 }
22804 /* Collision in the middle part can be handled by reordering. */
22806 {
22809 }
22813 {
22815 {
22818 }
22819 else
22820 {
22823 }
22824 }
22826 /* If there are more collisions, we can't handle it by reordering.
22827 Do an lea to the last part and use only one colliding move. */
22829 {
22830 rtx base;
22836 /* Handle the case when the last part isn't valid for lea.
22837 Happens in 64-bit mode storing the 12-byte XFmode. */
22844 {
22847 }
22848 }
22849 }
22852 {
22854 {
22856 {
22861 }
22863 {
22866 }
22867 }
22868 else
22869 {
22870 /* In 64bit mode we don't have 32bit push available. In case this is
22871 register, it is OK - we will just use larger counterpart. We also
22872 retype memory - these comes from attempt to avoid REX prefix on
22873 moving of second half of TFmode value. */
22875 {
22877 {
22888 }
22892 }
22893 }
22897 }
22899 /* Choose correct order to not overwrite the source before it is copied. */
22909 {
22911 {
22914 }
22915 }
22916 else
22917 {
22919 {
22922 }
22923 }
22925 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
22927 {
22936 }
22942 }
22944 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
22945 left shift by a constant, either using a single shift or
22946 a sequence of add instructions. */
22948 static void
22950 {
22956 {
22960 }
22961 else
22962 {
22965 }
22966 }
22968 void
22970 {
22979 {
22984 {
22990 }
22991 else
22992 {
23000 }
23002 }
23009 {
23010 /* Assuming we've chosen a QImode capable registers, then 1 << N
23011 can be done with two 32/64-bit shifts, no branches, no cmoves. */
23013 {
23029 }
23031 /* Otherwise, we can get the same results by manually performing
23032 a bit extract operation on bit 5/6, and then performing the two
23033 shifts. The two methods of getting 0/1 into low/high are exactly
23034 the same size. Avoiding the shift in the bit extract case helps
23035 pentium4 a bit; no one else seems to care much either way. */
23036 else
23037 {
23038 machine_mode half_mode;
23042 HOST_WIDE_INT bits;
23043 rtx x;
23046 {
23052 }
23053 else
23054 {
23060 }
23064 else
23072 }
23077 }
23080 {
23081 /* For -1 << N, we can avoid the shld instruction, because we
23082 know that we're shifting 0...31/63 ones into a -1. */
23086 else
23088 }
23089 else
23090 {
23098 }
23103 {
23109 }
23110 else
23111 {
23116 }
23117 }
23119 void
23121 {
23131 {
23136 {
23142 }
23144 {
23153 }
23154 else
23155 {
23163 }
23164 }
23165 else
23166 {
23178 {
23186 scratch));
23187 }
23188 else
23189 {
23194 }
23195 }
23196 }
23198 void
23200 {
23210 {
23215 {
23222 }
23223 else
23224 {
23232 }
23233 }
23234 else
23235 {
23247 {
23253 scratch));
23254 }
23255 else
23256 {
23261 }
23262 }
23263 }
23265 /* Predict just emitted jump instruction to be taken with probability PROB. */
23266 static void
23268 {
23272 }
23274 /* Helper function for the string operations below. Dest VARIABLE whether
23275 it is aligned to VALUE bytes. If true, jump to the label. */
23278 {
23283 else
23289 else
23292 }
23294 /* Adjust COUNTER by the VALUE. */
23295 static void
23297 {
23302 }
23304 /* Zero extend possibly SImode EXP to Pmode register. */
23305 rtx
23307 {
23309 }
23311 /* Divide COUNTREG by SCALE. */
23312 static rtx
23314 {
23315 rtx sc;
23327 }
23329 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
23330 DImode for constant loop counts. */
23332 static machine_mode
23334 {
23342 }
23344 /* Copy the address to a Pmode register. This is used for x32 to
23345 truncate DImode TLS address to a SImode register. */
23347 static rtx
23349 {
23350 rtx reg;
23352 {
23356 }
23357 else
23358 {
23363 }
23364 }
23366 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
23367 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
23368 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
23369 memory by VALUE (supposed to be in MODE).
23371 The size is rounded down to whole number of chunk size moved at once.
23372 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
23375 static void
23380 {
23387 rtx size;
23396 /* Those two should combine. */
23398 {
23402 }
23409 /* This assert could be relaxed - in this case we'll need to compute
23410 smallest power of two, containing in PIECE_SIZE_N and pass it to
23411 offset_address. */
23417 {
23421 /* When unrolling for chips that reorder memory reads and writes,
23422 we can save registers by using single temporary.
23423 Also using 4 temporaries is overkill in 32bit mode. */
23425 {
23427 {
23429 {
23430 destmem =
23432 srcmem =
23434 }
23436 }
23437 }
23438 else
23439 {
23443 {
23446 {
23447 srcmem =
23449 }
23451 }
23453 {
23455 {
23456 destmem =
23458 }
23460 }
23461 }
23462 }
23463 else
23465 {
23467 destmem =
23470 }
23480 {
23486 else
23488 }
23489 else
23497 {
23502 }
23504 }
23506 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
23507 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
23508 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
23509 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
23510 ORIG_VALUE is the original value passed to memset to fill the memory with.
23511 Other arguments have same meaning as for previous function. */
23513 static void
23516 rtx count,
23518 {
23519 rtx destexp;
23520 rtx srcexp;
23521 rtx countreg;
23522 HOST_WIDE_INT rounded_count;
23524 /* If possible, it is shorter to use rep movs.
23525 TODO: Maybe it is better to move this logic to decide_alg. */
23536 {
23540 }
23541 else
23544 {
23549 }
23554 {
23557 }
23558 else
23559 {
23563 {
23567 }
23568 else
23571 {
23576 }
23577 else
23578 {
23581 }
23584 }
23585 }
23587 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23588 DESTMEM.
23589 SRC is passed by pointer to be updated on return.
23590 Return value is updated DST. */
23591 static rtx
23593 HOST_WIDE_INT size_to_move)
23594 {
23597 machine_mode move_mode;
23600 /* Find the widest mode in which we could perform moves.
23601 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23602 it until move of such size is supported. */
23607 {
23611 }
23613 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23614 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23616 {
23621 {
23625 }
23626 }
23632 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23636 {
23637 /* We move from memory to memory, so we'll need to do it via
23638 a temporary register. */
23649 piece_size);
23651 piece_size);
23652 }
23654 /* Update DST and SRC rtx. */
23657 }
23659 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23660 static void
23663 {
23666 {
23671 /* For now MAX_SIZE should be a power of 2. This assert could be
23672 relaxed, but it'll require a bit more complicated epilogue
23673 expanding. */
23676 {
23679 }
23681 }
23683 {
23689 }
23691 /* When there are stringops, we can cheaply increase dest and src pointers.
23692 Otherwise we save code size by maintaining offset (zero is readily
23693 available from preceding rep operation) and using x86 addressing modes.
23694 */
23696 {
23698 {
23705 }
23707 {
23714 }
23716 {
23723 }
23724 }
23725 else
23726 {
23728 rtx tmp;
23731 {
23742 }
23744 {
23757 }
23759 {
23768 }
23769 }
23770 }
23772 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23773 with value PROMOTED_VAL.
23774 SRC is passed by pointer to be updated on return.
23775 Return value is updated DST. */
23776 static rtx
23778 HOST_WIDE_INT size_to_move)
23779 {
23782 machine_mode move_mode;
23785 /* Find the widest mode in which we could perform moves.
23786 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23787 it until move of such size is supported. */
23792 {
23795 }
23802 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23806 {
23808 {
23811 piece_size);
23813 }
23821 piece_size);
23822 }
23824 /* Update DST rtx. */
23826 }
23827 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23828 static void
23831 {
23832 count =
23838 }
23840 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23841 static void
23844 {
23845 rtx dest;
23848 {
23853 /* For now MAX_SIZE should be a power of 2. This assert could be
23854 relaxed, but it'll require a bit more complicated epilogue
23855 expanding. */
23858 {
23860 {
23863 else
23865 }
23866 }
23868 }
23870 {
23873 }
23875 {
23878 {
23883 }
23884 else
23885 {
23894 }
23897 }
23899 {
23902 {
23905 }
23906 else
23907 {
23912 }
23915 }
23917 {
23923 }
23925 {
23931 }
23933 {
23939 }
23940 }
23942 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
23943 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
23944 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
23945 ignored.
23946 Return value is updated DESTMEM. */
23947 static rtx
23952 {
23955 {
23957 {
23960 {
23963 else
23965 }
23966 else
23972 }
23973 }
23975 }
23977 /* Test if COUNT&SIZE is nonzero and if so, expand movme
23978 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
23979 and jump to DONE_LABEL. */
23980 static void
23986 {
23989 rtx modesize;
23992 /* If we do not have vector value to copy, we must reduce size. */
23994 {
23996 {
24001 }
24002 else
24004 }
24005 else
24006 {
24007 /* Choose appropriate vector mode. */
24013 }
24018 {
24021 else
24022 {
24025 }
24027 }
24033 {
24037 }
24039 {
24042 else
24043 {
24046 }
24048 }
24054 }
24056 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
24057 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
24058 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
24059 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
24060 DONE_LABEL is a label after the whole copying sequence. The label is created
24061 on demand if *DONE_LABEL is NULL.
24062 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
24063 bounds after the initial copies.
24065 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
24066 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
24067 we will dispatch to a library call for large blocks.
24069 In pseudocode we do:
24071 if (COUNT < SIZE)
24072 {
24073 Assume that SIZE is 4. Bigger sizes are handled analogously
24074 if (COUNT & 4)
24075 {
24076 copy 4 bytes from SRCPTR to DESTPTR
24077 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
24078 goto done_label
24079 }
24080 if (!COUNT)
24081 goto done_label;
24082 copy 1 byte from SRCPTR to DESTPTR
24083 if (COUNT & 2)
24084 {
24085 copy 2 bytes from SRCPTR to DESTPTR
24086 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
24087 }
24088 }
24089 else
24090 {
24091 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
24092 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
24094 OLD_DESPTR = DESTPTR;
24095 Align DESTPTR up to DESIRED_ALIGN
24096 SRCPTR += DESTPTR - OLD_DESTPTR
24097 COUNT -= DEST_PTR - OLD_DESTPTR
24098 if (DYNAMIC_CHECK)
24099 Round COUNT down to multiple of SIZE
24100 << optional caller supplied zero size guard is here >>
24101 << optional caller suppplied dynamic check is here >>
24102 << caller supplied main copy loop is here >>
24103 }
24104 done_label:
24105 */
24106 static void
24109 machine_mode mode,
24119 {
24122 rtx modesize;
24124 rtx mode_value;
24126 /* Chose proper value to copy. */
24129 else
24133 /* See if block is big or small, handle small blocks. */
24135 {
24146 /* Handle sizes > 3. */
24153 /* Nothing to copy? Jump to DONE_LABEL if so */
24157 /* Do a byte copy. */
24161 else
24162 {
24165 }
24167 /* Handle sizes 2 and 3. */
24174 else
24175 {
24180 }
24186 }
24187 else
24191 /* Start memcpy for COUNT >= SIZE. */
24193 {
24196 }
24198 /* Copy first desired_align bytes. */
24204 {
24207 else
24208 {
24211 }
24214 }
24217 /* Copy last SIZE bytes. */
24224 else
24225 {
24231 }
24233 {
24237 else
24238 {
24241 }
24242 }
24244 /* Align destination. */
24246 {
24250 /* Align destptr up, place it to new register. */
24259 /* See how many bytes we skipped. */
24263 /* Adjust srcptr and count. */
24269 /* We copied at most size + prolog_size. */
24272 else
24275 /* Our loops always round down the bock size, but for dispatch to library
24276 we need precise value. */
24280 }
24281 else
24282 {
24284 /* Decrease count, so we won't end up copying last word twice. */
24288 else
24292 }
24293 }
24296 /* This function is like the previous one, except here we know how many bytes
24297 need to be copied. That allows us to update alignment not only of DST, which
24298 is returned, but also of SRC, which is passed as a pointer for that
24299 reason. */
24300 static rtx
24305 {
24313 {
24317 }
24322 {
24324 {
24326 {
24329 else
24331 }
24332 else
24335 }
24336 }
24343 {
24349 {
24352 {
24356 }
24361 }
24365 }
24368 }
24370 /* Return true if ALG can be used in current context.
24371 Assume we expand memset if MEMSET is true. */
24372 static bool
24374 {
24379 /* Algorithms using the rep prefix want at least edi and ecx;
24380 additionally, memset wants eax and memcpy wants esi. Don't
24381 consider such algorithms if the user has appropriated those
24382 registers for their own purposes. */
24389 }
24391 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
24392 static enum stringop_alg
24396 {
24407 /* Even if the string operation call is cold, we still might spend a lot
24408 of time processing large blocks. */
24414 else
24420 else
24423 /* See maximal size for user defined algorithm. */
24425 {
24432 }
24434 /* If expected size is not known but max size is small enough
24435 so inline version is a win, set expected size into
24436 the range. */
24441 /* If user specified the algorithm, honnor it if possible. */
24445 /* rep; movq or rep; movl is the smallest variant. */
24447 {
24452 else
24455 }
24456 /* Very tiny blocks are best handled via the loop, REP is expensive to
24457 setup. */
24461 {
24465 {
24466 /* We get here if the algorithms that were not libcall-based
24467 were rep-prefix based and we are unable to use rep prefixes
24468 based on global register usage. Break out of the loop and
24469 use the heuristic below. */
24473 {
24477 {
24480 }
24481 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
24482 last non-libcall inline algorithm. */
24484 {
24485 /* When the current size is best to be copied by a libcall,
24486 but we are still forced to inline, run the heuristic below
24487 that will pick code for medium sized blocks. */
24489 {
24492 }
24495 }
24497 {
24500 }
24501 }
24502 }
24503 }
24504 /* When asked to inline the call anyway, try to pick meaningful choice.
24505 We look for maximal size of block that is faster to copy by hand and
24506 take blocks of at most of that size guessing that average size will
24507 be roughly half of the block.
24509 If this turns out to be bad, we might simply specify the preferred
24510 choice in ix86_costs. */
24514 {
24517 /* If there aren't any usable algorithms, then recursing on
24518 smaller sizes isn't going to find anything. Just return the
24519 simple byte-at-a-time copy loop. */
24521 {
24522 /* Pick something reasonable. */
24526 }
24534 else
24537 }
24540 }
24542 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24543 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24544 static int
24548 machine_mode move_mode)
24549 {
24560 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24561 copying whole cacheline at once. */
24574 }
24577 /* Helper function for memcpy. For QImode value 0xXY produce
24578 0xXYXYXYXY of wide specified by MODE. This is essentially
24579 a * 0x10101010, but we can do slightly better than
24580 synth_mult by unwinding the sequence by hand on CPUs with
24581 slow multiply. */
24582 static rtx
24584 {
24586 rtx tmp;
24593 {
24601 }
24610 nops--;
24615 {
24619 OPTAB_DIRECT);
24620 }
24621 else
24622 {
24628 else
24630 else
24631 {
24634 reg =
24636 }
24646 }
24647 }
24649 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24650 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24651 alignment from ALIGN to DESIRED_ALIGN. */
24652 static rtx
24655 {
24656 rtx promoted_val;
24665 else
24669 }
24671 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24672 operations when profitable. The code depends upon architecture, block size
24673 and alignment, but always has one of the following overall structures:
24675 Aligned move sequence:
24677 1) Prologue guard: Conditional that jumps up to epilogues for small
24678 blocks that can be handled by epilogue alone. This is faster
24679 but also needed for correctness, since prologue assume the block
24680 is larger than the desired alignment.
24682 Optional dynamic check for size and libcall for large
24683 blocks is emitted here too, with -minline-stringops-dynamically.
24685 2) Prologue: copy first few bytes in order to get destination
24686 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24687 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24688 copied. We emit either a jump tree on power of two sized
24689 blocks, or a byte loop.
24691 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24692 with specified algorithm.
24694 4) Epilogue: code copying tail of the block that is too small to be
24695 handled by main body (or up to size guarded by prologue guard).
24697 Misaligned move sequence
24699 1) missaligned move prologue/epilogue containing:
24700 a) Prologue handling small memory blocks and jumping to done_label
24701 (skipped if blocks are known to be large enough)
24702 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24703 needed by single possibly misaligned move
24704 (skipped if alignment is not needed)
24705 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24707 2) Zero size guard dispatching to done_label, if needed
24709 3) dispatch to library call, if needed,
24711 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24712 with specified algorithm. */
24713 bool
24719 {
24720 rtx destreg;
24723 rtx tmp;
24739 /* TODO: Once value ranges are available, fill in proper data. */
24747 /* i386 can do misaligned access on reasonably increased cost. */
24751 /* ALIGN is the minimum of destination and source alignment, but we care here
24752 just about destination alignment. */
24758 {
24761 /* When COUNT is 0, there is nothing to do. */
24764 }
24765 else
24766 {
24775 }
24777 /* Make sure we don't need to care about overflow later on. */
24781 /* Step 0: Decide on preferred algorithm, desired alignment and
24782 size of chunks to be copied by main loop. */
24784 issetmem,
24791 /* For now vector-version of memset is generated only for memory zeroing, as
24792 creating of promoted vector value is very cheap in this case. */
24805 {
24824 /* Find the widest supported mode. */
24830 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24831 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24833 {
24838 }
24850 }
24858 /* Step 1: Prologue guard. */
24860 /* Alignment code needs count to be in register. */
24862 {
24865 {
24866 align_bytes
24870 else
24872 }
24875 }
24878 /* Misaligned move sequences handle both prologue and epilogue at once.
24879 Default code generation results in a smaller code for large alignments
24880 and also avoids redundant job when sizes are known precisely. */
24881 misaligned_prologue_used
24882 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24888 /* Do the cheap promotion to allow better CSE across the
24889 main loop and epilogue (ie one load of the big constant in the
24890 front of all code.
24891 For now the misaligned move sequences do not have fast path
24892 without broadcasting. */
24894 {
24896 {
24902 }
24903 else
24904 {
24907 }
24908 }
24909 /* Misaligned move sequences handles both prologues and epilogues at once.
24910 Default code generation results in smaller code for large alignments and
24911 also avoids redundant job when sizes are known precisely. */
24913 {
24914 /* Misaligned move prologue handled small blocks by itself. */
24915 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
24920 desired_align < align
24929 {
24930 /* It is possible that we copied enough so the main loop will not
24931 execute. */
24941 else
24943 }
24944 }
24945 /* Ensure that alignment prologue won't copy past end of block. */
24947 {
24949 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
24950 Make sure it is power of 2. */
24953 /* To improve performance of small blocks, we jump around the VAL
24954 promoting mode. This mean that if the promoted VAL is not constant,
24955 we might not use it in the epilogue and have to use byte
24956 loop variant. */
24961 {
24962 /* If main algorithm works on QImode, no epilogue is needed.
24963 For small sizes just don't align anything. */
24966 else
24968 }
24971 {
24978 else
24980 }
24981 }
24983 /* Emit code to decide on runtime whether library call or inline should be
24984 used. */
24986 {
24988 {
24990 {
24994 }
24995 }
24996 else
24997 {
25007 else
25011 }
25012 }
25014 /* Step 2: Alignment prologue. */
25015 /* Do the expensive promotion once we branched off the small blocks. */
25021 {
25023 {
25024 /* Except for the first move in prologue, we no longer know
25025 constant offset in aliasing info. It don't seems to worth
25026 the pain to maintain it for the first move, so throw away
25027 the info early. */
25034 issetmem);
25035 /* At most desired_align - align bytes are copied. */
25038 else
25040 }
25041 else
25042 {
25043 /* If we know how many bytes need to be stored before dst is
25044 sufficiently aligned, maintain aliasing info accurately. */
25046 srcreg,
25047 promoted_val,
25048 vec_promoted_val,
25049 desired_align,
25050 align_bytes,
25051 issetmem);
25058 }
25060 && !min_size
25065 {
25066 /* It is possible that we copied enough so the main loop will not
25067 execute. */
25077 else
25079 }
25080 }
25082 {
25089 }
25093 /* Step 3: Main loop. */
25096 {
25119 }
25120 /* Adjust properly the offset of src and dest memory for aliasing. */
25122 {
25128 }
25129 else
25130 {
25134 }
25136 /* Step 4: Epilogue to copy the remaining bytes. */
25137 epilogue:
25139 {
25140 /* When the main loop is done, COUNT_EXP might hold original count,
25141 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
25142 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
25143 bytes. Compensate if needed. */
25146 {
25147 tmp =
25150 OPTAB_DIRECT);
25153 }
25156 }
25159 {
25162 epilogue_size_needed);
25163 else
25164 {
25168 epilogue_size_needed);
25169 else
25171 epilogue_size_needed);
25172 }
25173 }
25177 }
25180 /* Expand the appropriate insns for doing strlen if not just doing
25181 repnz; scasb
25183 out = result, initialized with the start address
25184 align_rtx = alignment of the address.
25185 scratch = scratch register, initialized with the startaddress when
25186 not aligned, otherwise undefined
25188 This is just the body. It needs the initializations mentioned above and
25189 some address computing at the end. These things are done in i386.md. */
25191 static void
25193 {
25195 rtx tmp;
25200 rtx mem;
25203 rtx cmp;
25209 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
25211 /* Is there a known alignment and is it less than 4? */
25213 {
25216 /* Is there a known alignment and is it not 2? */
25218 {
25222 /* Leave just the 3 lower bits. */
25232 }
25233 else
25234 {
25235 /* Since the alignment is 2, we have to check 2 or 0 bytes;
25236 check if is aligned to 4 - byte. */
25243 }
25247 /* Now compare the bytes. */
25249 /* Compare the first n unaligned byte on a byte per byte basis. */
25253 /* Increment the address. */
25256 /* Not needed with an alignment of 2 */
25258 {
25262 end_0_label);
25267 }
25270 end_0_label);
25273 }
25275 /* Generate loop to check 4 bytes at a time. It is not a good idea to
25276 align this loop. It gives only huge programs, but does not help to
25277 speed up. */
25284 /* This formula yields a nonzero result iff one of the bytes is zero.
25285 This saves three branches inside loop and many cycles. */
25293 align_4_label);
25296 {
25302 /* If zero is not in the first two bytes, move two bytes forward. */
25308 reg,
25309 tmpreg)));
25310 /* Emit lea manually to avoid clobbering of flags. */
25317 reg2,
25318 out)));
25319 }
25320 else
25321 {
25323 /* Is zero in the first two bytes? */
25330 pc_rtx);
25334 /* Not in the first two. Move two bytes forward. */
25340 }
25342 /* Avoid branch in fixing the byte. */
25350 }
25352 /* Expand strlen. */
25354 bool
25356 {
25359 /* The generic case of strlen expander is long. Avoid it's
25360 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
25363 && !TARGET_INLINE_ALL_STRINGOPS
25373 {
25374 /* Well it seems that some optimizer does not combine a call like
25375 foo(strlen(bar), strlen(bar));
25376 when the move and the subtraction is done here. It does calculate
25377 the length just once when these instructions are done inside of
25378 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
25379 often used and I use one fewer register for the lifetime of
25380 output_strlen_unroll() this is better. */
25386 /* strlensi_unroll_1 returns the address of the zero at the end of
25387 the string, like memchr(), so compute the length by subtracting
25388 the start address. */
25390 }
25391 else
25392 {
25393 rtx unspec;
25395 /* Can't use this if the user has appropriated eax, ecx, or edi. */
25408 /* If .md starts supporting :P, this can be done in .md. */
25414 }
25416 }
25418 /* For given symbol (function) construct code to compute address of it's PLT
25419 entry in large x86-64 PIC model. */
25420 static rtx
25422 {
25435 }
25437 rtx
25439 rtx callarg2,
25441 {
25451 {
25452 #if TARGET_MACHO
25455 #endif
25456 }
25457 else
25458 {
25459 /* Static functions and indirect calls don't need the pic register. */
25461 && (!TARGET_64BIT
25466 {
25470 pic_offset_table_rtx);
25471 }
25472 }
25474 /* Skip setting up RAX register for -mskip-rax-setup when there are no
25475 parameters passed in vector registers. */
25480 {
25484 }
25487 && !TARGET_PECOFF
25495 {
25498 }
25503 {
25504 /* We should add bounds as destination register in case
25505 pointer with bounds may be returned. */
25507 {
25511 {
25516 }
25517 else
25518 {
25522 }
25523 }
25526 }
25530 {
25534 }
25538 {
25539 int const cregs_size
25544 {
25549 }
25550 }
25559 }
25561 /* Output the assembly for a call instruction. */
25565 {
25571 {
25574 /* SEH epilogue detection requires the indirect branch case
25575 to include REX.W. */
25578 else
25583 }
25585 /* SEH unwinding can require an extra nop to be emitted in several
25586 circumstances. Determine if we have one of those. */
25588 {
25592 {
25593 /* If we get to another real insn, we don't need the nop. */
25597 /* If we get to the epilogue note, prevent a catch region from
25598 being adjacent to the standard epilogue sequence. If non-
25599 call-exceptions, we'll have done this during epilogue emission. */
25601 && !flag_non_call_exceptions
25603 {
25606 }
25607 }
25609 /* If we didn't find a real insn following the call, prevent the
25610 unwinder from looking into the next function. */
25613 }
25617 else
25626 }
25627 \f
25628 /* Clear stack slot assignments remembered from previous functions.
25629 This is called from INIT_EXPANDERS once before RTL is emitted for each
25630 function. */
25634 {
25642 }
25644 /* Return a MEM corresponding to a stack slot with mode MODE.
25645 Allocate a new slot if necessary.
25647 The RTL for a function can have several slots available: N is
25648 which slot to use. */
25650 rtx
25652 {
25669 }
25671 static void
25673 {
25679 }
25680 \f
25681 /* Check whether x86 address PARTS is a pc-relative address. */
25683 static bool
25685 {
25693 {
25695 {
25712 }
25713 }
25715 }
25717 /* Calculate the length of the memory address in the instruction encoding.
25718 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25719 or other prefixes. We never generate addr32 prefix for LEA insn. */
25721 int
25723 {
25740 /* If this is not LEA instruction, add the length of addr32 prefix. */
25745 len++;
25759 /* Rule of thumb:
25760 - esp as the base always wants an index,
25761 - ebp as the base always wants a displacement,
25762 - r12 as the base always wants an index,
25763 - r13 as the base always wants a displacement. */
25765 /* Register Indirect. */
25767 {
25768 /* esp (for its index) and ebp (for its displacement) need
25769 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25770 code. */
25777 len++;
25778 }
25780 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25781 is not disp32, but disp32(%rip), so for disp32
25782 SIB byte is needed, unless print_operand_address
25783 optimizes it into disp32(%rip) or (%rip) is implied
25784 by UNSPEC. */
25786 {
25789 len++;
25790 }
25791 else
25792 {
25793 /* Find the length of the displacement constant. */
25795 {
25798 else
25800 }
25801 /* ebp always wants a displacement. Similarly r13. */
25803 len++;
25805 /* An index requires the two-byte modrm form.... */
25807 /* ...like esp (or r12), which always wants an index. */
25811 len++;
25812 }
25815 }
25817 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25818 is set, expect that insn have 8bit immediate alternative. */
25819 int
25821 {
25827 {
25832 {
25835 {
25847 }
25849 {
25852 }
25853 }
25855 {
25865 /* Immediates for DImode instructions are encoded
25866 as 32bit sign extended values. */
25872 }
25873 }
25875 }
25877 /* Compute default value for "length_address" attribute. */
25878 int
25880 {
25884 {
25895 }
25900 {
25903 {
25908 constraints++;
25911 ;
25912 /* Skip ignored operands. */
25915 }
25917 }
25919 }
25921 /* Compute default value for "length_vex" attribute. It includes
25922 2 or 3 byte VEX prefix and 1 opcode byte. */
25924 int
25927 {
25930 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
25931 byte VEX prefix. */
25935 /* We can always use 2 byte VEX prefix in 32bit. */
25943 {
25944 /* REX.W bit uses 3 byte VEX prefix. */
25948 }
25949 else
25950 {
25951 /* REX.X or REX.B bits use 3 byte VEX prefix. */
25955 }
25958 }
25959 \f
25960 /* Return the maximum number of instructions a cpu can issue. */
25962 static int
25964 {
25966 {
25998 }
25999 }
26001 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
26002 by DEP_INSN and nothing set by DEP_INSN. */
26004 static bool
26006 {
26009 /* Simplify the test for uninteresting insns. */
26017 {
26020 }
26025 {
26028 }
26029 else
26035 /* This test is true if the dependent insn reads the flags but
26036 not any other potentially set register. */
26044 }
26046 /* Return true iff USE_INSN has a memory address with operands set by
26047 SET_INSN. */
26049 bool
26051 {
26056 {
26059 }
26061 }
26063 /* Helper function for exact_store_load_dependency.
26064 Return true if addr is found in insn. */
26065 static bool
26067 {
26074 {
26080 CASE_CONST_ANY:
26089 }
26093 {
26095 {
26105 }
26106 }
26108 }
26110 /* Return true if there exists exact dependency for store & load, i.e.
26111 the same memory address is used in them. */
26112 static bool
26114 {
26128 }
26130 static int
26132 {
26138 /* Anti and output dependencies have zero cost on all CPUs. */
26144 /* If we can't recognize the insns, we can't really do anything. */
26152 {
26154 /* Address Generation Interlock adds a cycle of latency. */
26156 {
26167 }
26171 /* ??? Compares pair with jump/setcc. */
26175 /* Floating point stores require value to be ready one cycle earlier. */
26183 /* INT->FP conversion is expensive. */
26187 /* There is one cycle extra latency between an FP op and a store. */
26197 /* Show ability of reorder buffer to hide latency of load by executing
26198 in parallel with previous instruction in case
26199 previous instruction is not needed to compute the address. */
26202 {
26203 /* Claim moves to take one cycle, as core can issue one load
26204 at time and the next load can start cycle later. */
26209 cost--;
26210 }
26214 /* The esp dependency is resolved before
26215 the instruction is really finished. */
26220 /* INT->FP conversion is expensive. */
26226 /* Show ability of reorder buffer to hide latency of load by executing
26227 in parallel with previous instruction in case
26228 previous instruction is not needed to compute the address. */
26231 {
26232 /* Claim moves to take one cycle, as core can issue one load
26233 at time and the next load can start cycle later. */
26239 else
26241 }
26252 /* Stack engine allows to execute push&pop instructions in parall. */
26256 /* FALLTHRU */
26262 /* Show ability of reorder buffer to hide latency of load by executing
26263 in parallel with previous instruction in case
26264 previous instruction is not needed to compute the address. */
26267 {
26271 /* Because of the difference between the length of integer and
26272 floating unit pipeline preparation stages, the memory operands
26273 for floating point are cheaper.
26275 ??? For Athlon it the difference is most probably 2. */
26278 else
26283 else
26285 }
26292 /* Stack engine allows to execute push&pop instructions in parall. */
26299 /* Show ability of reorder buffer to hide latency of load by executing
26300 in parallel with previous instruction in case
26301 previous instruction is not needed to compute the address. */
26304 {
26307 else
26309 }
26318 /* Increase cost of integer loads. */
26321 {
26324 {
26327 else
26328 {
26329 /* Increase cost of ld/st for short int types only
26330 because of store forwarding issue. */
26334 {
26335 /* Increase cost of store/load insn if exact
26336 dependence exists and it is load insn. */
26341 }
26342 }
26343 }
26344 }
26348 }
26351 }
26353 /* How many alternative schedules to try. This should be as wide as the
26354 scheduling freedom in the DFA, but no wider. Making this value too
26355 large results extra work for the scheduler. */
26357 static int
26359 {
26361 {
26373 /* We use lookahead value 4 for BD both before and after reload
26374 schedules. Plan is to have value 8 included for O3. */
26385 /* Generally, we want haifa-sched:max_issue() to look ahead as far
26386 as many instructions can be executed on a cycle, i.e.,
26387 issue_rate. I wonder why tuning for many CPUs does not do this. */
26390 /* Don't use lookahead for pre-reload schedule to save compile time. */
26395 }
26396 }
26398 /* Return true if target platform supports macro-fusion. */
26400 static bool
26402 {
26404 }
26406 /* Check whether current microarchitecture support macro fusion
26407 for insn pair "CONDGEN + CONDJMP". Refer to
26408 "Intel Architectures Optimization Reference Manual". */
26410 static bool
26412 {
26433 {
26438 {
26442 else
26444 }
26445 }
26452 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
26453 supported. */
26460 /* No fusion for RIP-relative address. */
26467 ix86_address parts;
26473 }
26478 /* Check whether conditional jump use Sign or Overflow Flags. */
26486 /* Return true for TYPE_TEST and TYPE_ICMP. */
26491 /* The following is the case that macro-fusion for alu + jmp. */
26495 /* No fusion for alu op with memory destination operand. */
26500 /* Macro-fusion for inc/dec + unsigned conditional jump is not
26501 supported. */
26510 }
26512 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
26513 execution. It is applied if
26514 (1) IMUL instruction is on the top of list;
26515 (2) There exists the only producer of independent IMUL instruction in
26516 ready list.
26517 Return index of IMUL producer if it was found and -1 otherwise. */
26518 static int
26520 {
26523 sd_iterator_def sd_it;
26524 dep_t dep;
26531 /* Check that IMUL instruction is on the top of ready list. */
26540 /* Search for producer of independent IMUL instruction. */
26542 {
26546 /* Skip IMUL instruction. */
26556 {
26557 rtx con;
26568 {
26569 sd_iterator_def sd_it1;
26570 dep_t dep1;
26571 /* Check if there is no other dependee for IMUL. */
26574 {
26575 rtx pro;
26581 }
26584 }
26585 }
26588 }
26590 }
26592 /* Try to find the best candidate on the top of ready list if two insns
26593 have the same priority - candidate is best if its dependees were
26594 scheduled earlier. Applied for Silvermont only.
26595 Return true if top 2 insns must be interchanged. */
26596 static bool
26598 {
26601 rtx set;
26602 sd_iterator_def sd_it;
26603 dep_t dep;
26606 #define INSN_TICK(INSN) (HID (INSN)->tick)
26627 {
26630 /* Determine winner more precise. */
26632 {
26633 rtx pro;
26639 }
26641 {
26642 rtx pro;
26648 }
26651 {
26652 /* Determine winner - load must win. */
26658 }
26660 }
26662 #undef INSN_TICK
26663 }
26665 /* Perform possible reodering of ready list for Atom/Silvermont only.
26666 Return issue rate. */
26667 static int
26670 {
26677 /* Set up issue rate. */
26680 /* Do reodering for BONNELL/SILVERMONT only. */
26684 /* Nothing to do if ready list contains only 1 instruction. */
26688 /* Do reodering for post-reload scheduler only. */
26693 {
26698 /* Put IMUL producer (ready[index]) at the top of ready list. */
26704 }
26706 /* Skip selective scheduling since HID is not populated in it. */
26710 {
26714 /* Swap 2 top elements of ready list. */
26718 }
26720 }
26722 static bool
26725 /* Returns true if lhs of insn is HW function argument register and set up
26726 is_spilled to true if it is likely spilled HW register. */
26727 static bool
26729 {
26730 rtx dst;
26734 /* Call instructions are not movable, ignore it. */
26745 {
26746 /* Is it likely spilled HW register? */
26751 }
26753 }
26755 /* Add output dependencies for chain of function adjacent arguments if only
26756 there is a move to likely spilled HW register. Return first argument
26757 if at least one dependence was added or NULL otherwise. */
26760 {
26768 /* Find nearest to call argument passing instruction. */
26770 {
26779 }
26783 {
26790 {
26793 }
26795 {
26796 /* Add output depdendence between two function arguments if chain
26797 of output arguments contains likely spilled HW registers. */
26801 }
26802 else
26804 }
26808 }
26810 /* Add output or anti dependency from insn to first_arg to restrict its code
26811 motion. */
26812 static void
26814 {
26815 rtx set;
26816 rtx tmp;
26818 /* Add anti dependencies for bounds stores. */
26823 {
26826 }
26833 {
26834 /* Add output dependency to the first function argument. */
26837 }
26838 /* Add anti dependency. */
26840 }
26842 /* Avoid cross block motion of function argument through adding dependency
26843 from the first non-jump instruction in bb. */
26844 static void
26846 {
26850 {
26852 {
26855 {
26858 }
26859 }
26863 }
26864 }
26866 /* Hook for pre-reload schedule - avoid motion of function arguments
26867 passed in likely spilled HW registers. */
26868 static void
26870 {
26879 {
26882 {
26883 /* Add dependee for first argument to predecessors if only
26884 region contains more than one block. */
26888 /* Skip trivial regions and region head blocks that can have
26889 predecessors outside of region. */
26891 {
26892 edge e;
26893 edge_iterator ei;
26895 /* Regions are SCCs with the exception of selective
26896 scheduling with pipelining of outer blocks enabled.
26897 So also check that immediate predecessors of a non-head
26898 block are in the same region. */
26900 {
26901 /* Avoid creating of loop-carried dependencies through
26902 using topological ordering in the region. */
26906 }
26907 }
26911 }
26912 }
26915 }
26917 /* Hook for pre-reload schedule - set priority of moves from likely spilled
26918 HW registers to maximum, to schedule them at soon as possible. These are
26919 moves from function argument registers at the top of the function entry
26920 and moves from function return value registers after call. */
26921 static int
26923 {
26924 rtx set;
26934 {
26941 }
26944 }
26946 /* Model decoder of Core 2/i7.
26947 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
26948 track the instruction fetch block boundaries and make sure that long
26949 (9+ bytes) instructions are assigned to D0. */
26951 /* Maximum length of an insn that can be handled by
26952 a secondary decoder unit. '8' for Core 2/i7. */
26955 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
26956 '16' for Core 2/i7. */
26959 /* Maximum number of instructions decoder can handle per cycle.
26960 '6' for Core 2/i7. */
26964 ix86_first_cycle_multipass_data_t;
26966 const_ix86_first_cycle_multipass_data_t;
26968 /* A variable to store target state across calls to max_issue within
26969 one cycle. */
26973 /* Initialize DATA. */
26974 static void
26976 {
26977 ix86_first_cycle_multipass_data_t data
26984 }
26986 /* Advancing the cycle; reset ifetch block counts. */
26987 static void
26989 {
26996 }
27000 /* Filter out insns from ready_try that the core will not be able to issue
27001 on current cycle due to decoder. */
27002 static void
27003 core2i7_first_cycle_multipass_filter_ready_try
27006 {
27008 {
27019 (!first_cycle_insn_p
27021 /* ... or it would not fit into the ifetch block ... */
27023 /* ... or the decoder is full already ... */
27025 /* ... mask the insn out. */
27026 {
27031 }
27032 }
27033 }
27035 /* Prepare for a new round of multipass lookahead scheduling. */
27036 static void
27040 {
27041 ix86_first_cycle_multipass_data_t data
27043 const_ix86_first_cycle_multipass_data_t prev_data
27046 /* Restore the state from the end of the previous round. */
27050 /* Filter instructions that cannot be issued on current cycle due to
27051 decoder restrictions. */
27053 first_cycle_insn_p);
27054 }
27056 /* INSN is being issued in current solution. Account for its impact on
27057 the decoder model. */
27058 static void
27062 {
27063 ix86_first_cycle_multipass_data_t data
27065 const_ix86_first_cycle_multipass_data_t prev_data
27075 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
27077 {
27080 }
27082 {
27086 }
27089 /* Filter out insns from ready_try that the core will not be able to issue
27090 on current cycle due to decoder. */
27093 }
27095 /* Revert the effect on ready_try. */
27096 static void
27100 {
27101 const_ix86_first_cycle_multipass_data_t data
27104 sbitmap_iterator sbi;
27108 {
27110 }
27111 }
27113 /* Save the result of multipass lookahead scheduling for the next round. */
27114 static void
27116 {
27117 const_ix86_first_cycle_multipass_data_t data
27119 ix86_first_cycle_multipass_data_t next_data
27123 {
27126 }
27127 }
27129 /* Deallocate target data. */
27130 static void
27132 {
27133 ix86_first_cycle_multipass_data_t data
27137 {
27141 }
27142 }
27144 /* Prepare for scheduling pass. */
27145 static void
27147 {
27148 /* Install scheduling hooks for current CPU. Some of these hooks are used
27149 in time-critical parts of the scheduler, so we only set them up when
27150 they are actually used. */
27152 {
27157 /* Do not perform multipass scheduling for pre-reload schedule
27158 to save compile time. */
27160 {
27176 /* Set decoder parameters. */
27181 }
27182 /* ... Fall through ... */
27192 }
27193 }
27195 \f
27196 /* Compute the alignment given to a constant that is being placed in memory.
27197 EXP is the constant and ALIGN is the alignment that the object would
27198 ordinarily have.
27199 The value of this function is used instead of that alignment to align
27200 the object. */
27202 int
27204 {
27207 {
27212 }
27218 }
27220 /* Compute the alignment for a static variable.
27221 TYPE is the data type, and ALIGN is the alignment that
27222 the object would ordinarily have. The value of this function is used
27223 instead of that alignment to align the object. */
27225 int
27227 {
27228 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
27229 for symbols from other compilation units or symbols that don't need
27230 to bind locally. In order to preserve some ABI compatibility with
27231 those compilers, ensure we don't decrease alignment from what we
27232 used to assume. */
27236 /* A data structure, equal or greater than the size of a cache line
27237 (64 bytes in the Pentium 4 and other recent Intel processors, including
27238 processors based on Intel Core microarchitecture) should be aligned
27239 so that its base address is a multiple of a cache line size. */
27241 int max_align
27248 {
27252 }
27258 {
27265 }
27267 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27268 to 16byte boundary. */
27270 {
27277 }
27283 {
27288 }
27290 {
27297 }
27302 {
27307 }
27310 {
27315 }
27318 }
27320 /* Compute the alignment for a local variable or a stack slot. EXP is
27321 the data type or decl itself, MODE is the widest mode available and
27322 ALIGN is the alignment that the object would ordinarily have. The
27323 value of this macro is used instead of that alignment to align the
27324 object. */
27326 unsigned int
27329 {
27333 {
27336 }
27337 else
27338 {
27341 }
27343 /* Don't do dynamic stack realignment for long long objects with
27344 -mpreferred-stack-boundary=2. */
27353 /* If TYPE is NULL, we are allocating a stack slot for caller-save
27354 register in MODE. We will return the largest alignment of XF
27355 and DF. */
27357 {
27361 }
27363 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27364 to 16byte boundary. Exact wording is:
27366 An array uses the same alignment as its elements, except that a local or
27367 global array variable of length at least 16 bytes or
27368 a C99 variable-length array variable always has alignment of at least 16 bytes.
27370 This was added to allow use of aligned SSE instructions at arrays. This
27371 rule is meant for static storage (where compiler can not do the analysis
27372 by itself). We follow it for automatic variables only when convenient.
27373 We fully control everything in the function compiled and functions from
27374 other unit can not rely on the alignment.
27376 Exclude va_list type. It is the common case of local array where
27377 we can not benefit from the alignment.
27379 TODO: Probably one should optimize for size only when var is not escaping. */
27382 {
27392 }
27394 {
27399 }
27401 {
27407 }
27412 {
27417 }
27420 {
27426 }
27428 }
27430 /* Compute the minimum required alignment for dynamic stack realignment
27431 purposes for a local variable, parameter or a stack slot. EXP is
27432 the data type or decl itself, MODE is its mode and ALIGN is the
27433 alignment that the object would ordinarily have. */
27435 unsigned int
27438 {
27442 {
27445 }
27446 else
27447 {
27450 }
27455 /* Don't do dynamic stack realignment for long long objects with
27456 -mpreferred-stack-boundary=2. */
27463 }
27464 \f
27465 /* Find a location for the static chain incoming to a nested function.
27466 This is a register, unless all free registers are used by arguments. */
27468 static rtx
27470 {
27473 /* While this function won't be called by the middle-end when a static
27474 chain isn't needed, it's also used throughout the backend so it's
27475 easiest to keep this check centralized. */
27480 {
27481 /* We always use R10 in 64-bit mode. */
27483 }
27484 else
27485 {
27489 /* By default in 32-bit mode we use ECX to pass the static chain. */
27493 {
27496 }
27497 else
27498 {
27501 }
27505 {
27506 /* Fastcall functions use ecx/edx for arguments, which leaves
27507 us with EAX for the static chain.
27508 Thiscall functions use ecx for arguments, which also
27509 leaves us with EAX for the static chain. */
27511 }
27513 {
27514 /* Thiscall functions use ecx for arguments, which leaves
27515 us with EAX and EDX for the static chain.
27516 We are using for abi-compatibility EAX. */
27518 }
27520 {
27521 /* For regparm 3, we have no free call-clobbered registers in
27522 which to store the static chain. In order to implement this,
27523 we have the trampoline push the static chain to the stack.
27524 However, we can't push a value below the return address when
27525 we call the nested function directly, so we have to use an
27526 alternate entry point. For this we use ESI, and have the
27527 alternate entry point push ESI, so that things appear the
27528 same once we're executing the nested function. */
27530 {
27536 }
27538 }
27539 }
27542 }
27544 /* Emit RTL insns to initialize the variable parts of a trampoline.
27545 FNDECL is the decl of the target address; M_TRAMP is a MEM for
27546 the trampoline, and CHAIN_VALUE is an RTX for the static chain
27547 to be passed to the target function. */
27549 static void
27551 {
27559 {
27562 /* Load the function address to r11. Try to load address using
27563 the shorter movl instead of movabs. We may want to support
27564 movq for kernel mode, but kernel does not use trampolines at
27565 the moment. FNADDR is a 32bit address and may not be in
27566 DImode when ptr_mode == SImode. Always use movl in this
27567 case. */
27570 {
27579 }
27580 else
27581 {
27588 }
27590 /* Load static chain using movabs to r10. Use the shorter movl
27591 instead of movabs when ptr_mode == SImode. */
27593 {
27596 }
27597 else
27598 {
27601 }
27610 /* Jump to r11; the last (unused) byte is a nop, only there to
27611 pad the write out to a single 32-bit store. */
27615 }
27616 else
27617 {
27620 /* Depending on the static chain location, either load a register
27621 with a constant, or push the constant to the stack. All of the
27622 instructions are the same size. */
27625 {
27627 {
27634 }
27635 }
27636 else
27651 /* Compute offset from the end of the jmp to the target function.
27652 In the case in which the trampoline stores the static chain on
27653 the stack, we need to skip the first insn which pushes the
27654 (call-saved) register static chain; this push is 1 byte. */
27661 }
27665 #ifdef HAVE_ENABLE_EXECUTE_STACK
27666 #ifdef CHECK_EXECUTE_STACK_ENABLED
27668 #endif
27671 #endif
27672 }
27673 \f
27674 /* The following file contains several enumerations and data structures
27675 built from the definitions in i386-builtin-types.def. */
27679 /* Table for the ix86 builtin non-function types. */
27682 /* Retrieve an element from the above table, building some of
27683 the types lazily. */
27685 static tree
27687 {
27699 {
27700 machine_mode mode;
27707 }
27708 else
27709 {
27715 else
27723 }
27727 }
27729 /* Table for the ix86 builtin function types. */
27732 /* Retrieve an element from the above table, building some of
27733 the types lazily. */
27735 static tree
27737 {
27738 tree type;
27747 {
27755 {
27758 }
27761 }
27762 else
27763 {
27769 }
27773 }
27776 /* Codes for all the SSE/MMX builtins. */
27777 enum ix86_builtins
27778 {
27779 IX86_BUILTIN_ADDPS,
27780 IX86_BUILTIN_ADDSS,
27781 IX86_BUILTIN_DIVPS,
27782 IX86_BUILTIN_DIVSS,
27783 IX86_BUILTIN_MULPS,
27784 IX86_BUILTIN_MULSS,
27785 IX86_BUILTIN_SUBPS,
27786 IX86_BUILTIN_SUBSS,
27788 IX86_BUILTIN_CMPEQPS,
27789 IX86_BUILTIN_CMPLTPS,
27790 IX86_BUILTIN_CMPLEPS,
27791 IX86_BUILTIN_CMPGTPS,
27792 IX86_BUILTIN_CMPGEPS,
27793 IX86_BUILTIN_CMPNEQPS,
27794 IX86_BUILTIN_CMPNLTPS,
27795 IX86_BUILTIN_CMPNLEPS,
27796 IX86_BUILTIN_CMPNGTPS,
27797 IX86_BUILTIN_CMPNGEPS,
27798 IX86_BUILTIN_CMPORDPS,
27799 IX86_BUILTIN_CMPUNORDPS,
27800 IX86_BUILTIN_CMPEQSS,
27801 IX86_BUILTIN_CMPLTSS,
27802 IX86_BUILTIN_CMPLESS,
27803 IX86_BUILTIN_CMPNEQSS,
27804 IX86_BUILTIN_CMPNLTSS,
27805 IX86_BUILTIN_CMPNLESS,
27806 IX86_BUILTIN_CMPORDSS,
27807 IX86_BUILTIN_CMPUNORDSS,
27809 IX86_BUILTIN_COMIEQSS,
27810 IX86_BUILTIN_COMILTSS,
27811 IX86_BUILTIN_COMILESS,
27812 IX86_BUILTIN_COMIGTSS,
27813 IX86_BUILTIN_COMIGESS,
27814 IX86_BUILTIN_COMINEQSS,
27815 IX86_BUILTIN_UCOMIEQSS,
27816 IX86_BUILTIN_UCOMILTSS,
27817 IX86_BUILTIN_UCOMILESS,
27818 IX86_BUILTIN_UCOMIGTSS,
27819 IX86_BUILTIN_UCOMIGESS,
27820 IX86_BUILTIN_UCOMINEQSS,
27822 IX86_BUILTIN_CVTPI2PS,
27823 IX86_BUILTIN_CVTPS2PI,
27824 IX86_BUILTIN_CVTSI2SS,
27825 IX86_BUILTIN_CVTSI642SS,
27826 IX86_BUILTIN_CVTSS2SI,
27827 IX86_BUILTIN_CVTSS2SI64,
27828 IX86_BUILTIN_CVTTPS2PI,
27829 IX86_BUILTIN_CVTTSS2SI,
27830 IX86_BUILTIN_CVTTSS2SI64,
27832 IX86_BUILTIN_MAXPS,
27833 IX86_BUILTIN_MAXSS,
27834 IX86_BUILTIN_MINPS,
27835 IX86_BUILTIN_MINSS,
27837 IX86_BUILTIN_LOADUPS,
27838 IX86_BUILTIN_STOREUPS,
27839 IX86_BUILTIN_MOVSS,
27841 IX86_BUILTIN_MOVHLPS,
27842 IX86_BUILTIN_MOVLHPS,
27843 IX86_BUILTIN_LOADHPS,
27844 IX86_BUILTIN_LOADLPS,
27845 IX86_BUILTIN_STOREHPS,
27846 IX86_BUILTIN_STORELPS,
27848 IX86_BUILTIN_MASKMOVQ,
27849 IX86_BUILTIN_MOVMSKPS,
27850 IX86_BUILTIN_PMOVMSKB,
27852 IX86_BUILTIN_MOVNTPS,
27853 IX86_BUILTIN_MOVNTQ,
27855 IX86_BUILTIN_LOADDQU,
27856 IX86_BUILTIN_STOREDQU,
27858 IX86_BUILTIN_PACKSSWB,
27859 IX86_BUILTIN_PACKSSDW,
27860 IX86_BUILTIN_PACKUSWB,
27862 IX86_BUILTIN_PADDB,
27863 IX86_BUILTIN_PADDW,
27864 IX86_BUILTIN_PADDD,
27865 IX86_BUILTIN_PADDQ,
27866 IX86_BUILTIN_PADDSB,
27867 IX86_BUILTIN_PADDSW,
27868 IX86_BUILTIN_PADDUSB,
27869 IX86_BUILTIN_PADDUSW,
27870 IX86_BUILTIN_PSUBB,
27871 IX86_BUILTIN_PSUBW,
27872 IX86_BUILTIN_PSUBD,
27873 IX86_BUILTIN_PSUBQ,
27874 IX86_BUILTIN_PSUBSB,
27875 IX86_BUILTIN_PSUBSW,
27876 IX86_BUILTIN_PSUBUSB,
27877 IX86_BUILTIN_PSUBUSW,
27879 IX86_BUILTIN_PAND,
27880 IX86_BUILTIN_PANDN,
27881 IX86_BUILTIN_POR,
27882 IX86_BUILTIN_PXOR,
27884 IX86_BUILTIN_PAVGB,
27885 IX86_BUILTIN_PAVGW,
27887 IX86_BUILTIN_PCMPEQB,
27888 IX86_BUILTIN_PCMPEQW,
27889 IX86_BUILTIN_PCMPEQD,
27890 IX86_BUILTIN_PCMPGTB,
27891 IX86_BUILTIN_PCMPGTW,
27892 IX86_BUILTIN_PCMPGTD,
27894 IX86_BUILTIN_PMADDWD,
27896 IX86_BUILTIN_PMAXSW,
27897 IX86_BUILTIN_PMAXUB,
27898 IX86_BUILTIN_PMINSW,
27899 IX86_BUILTIN_PMINUB,
27901 IX86_BUILTIN_PMULHUW,
27902 IX86_BUILTIN_PMULHW,
27903 IX86_BUILTIN_PMULLW,
27905 IX86_BUILTIN_PSADBW,
27906 IX86_BUILTIN_PSHUFW,
27908 IX86_BUILTIN_PSLLW,
27909 IX86_BUILTIN_PSLLD,
27910 IX86_BUILTIN_PSLLQ,
27911 IX86_BUILTIN_PSRAW,
27912 IX86_BUILTIN_PSRAD,
27913 IX86_BUILTIN_PSRLW,
27914 IX86_BUILTIN_PSRLD,
27915 IX86_BUILTIN_PSRLQ,
27916 IX86_BUILTIN_PSLLWI,
27917 IX86_BUILTIN_PSLLDI,
27918 IX86_BUILTIN_PSLLQI,
27919 IX86_BUILTIN_PSRAWI,
27920 IX86_BUILTIN_PSRADI,
27921 IX86_BUILTIN_PSRLWI,
27922 IX86_BUILTIN_PSRLDI,
27923 IX86_BUILTIN_PSRLQI,
27925 IX86_BUILTIN_PUNPCKHBW,
27926 IX86_BUILTIN_PUNPCKHWD,
27927 IX86_BUILTIN_PUNPCKHDQ,
27928 IX86_BUILTIN_PUNPCKLBW,
27929 IX86_BUILTIN_PUNPCKLWD,
27930 IX86_BUILTIN_PUNPCKLDQ,
27932 IX86_BUILTIN_SHUFPS,
27934 IX86_BUILTIN_RCPPS,
27935 IX86_BUILTIN_RCPSS,
27936 IX86_BUILTIN_RSQRTPS,
27937 IX86_BUILTIN_RSQRTPS_NR,
27938 IX86_BUILTIN_RSQRTSS,
27939 IX86_BUILTIN_RSQRTF,
27940 IX86_BUILTIN_SQRTPS,
27941 IX86_BUILTIN_SQRTPS_NR,
27942 IX86_BUILTIN_SQRTSS,
27944 IX86_BUILTIN_UNPCKHPS,
27945 IX86_BUILTIN_UNPCKLPS,
27947 IX86_BUILTIN_ANDPS,
27948 IX86_BUILTIN_ANDNPS,
27949 IX86_BUILTIN_ORPS,
27950 IX86_BUILTIN_XORPS,
27952 IX86_BUILTIN_EMMS,
27953 IX86_BUILTIN_LDMXCSR,
27954 IX86_BUILTIN_STMXCSR,
27955 IX86_BUILTIN_SFENCE,
27957 IX86_BUILTIN_FXSAVE,
27958 IX86_BUILTIN_FXRSTOR,
27959 IX86_BUILTIN_FXSAVE64,
27960 IX86_BUILTIN_FXRSTOR64,
27962 IX86_BUILTIN_XSAVE,
27963 IX86_BUILTIN_XRSTOR,
27964 IX86_BUILTIN_XSAVE64,
27965 IX86_BUILTIN_XRSTOR64,
27967 IX86_BUILTIN_XSAVEOPT,
27968 IX86_BUILTIN_XSAVEOPT64,
27970 IX86_BUILTIN_XSAVEC,
27971 IX86_BUILTIN_XSAVEC64,
27973 IX86_BUILTIN_XSAVES,
27974 IX86_BUILTIN_XRSTORS,
27975 IX86_BUILTIN_XSAVES64,
27976 IX86_BUILTIN_XRSTORS64,
27978 /* 3DNow! Original */
27979 IX86_BUILTIN_FEMMS,
27980 IX86_BUILTIN_PAVGUSB,
27981 IX86_BUILTIN_PF2ID,
27982 IX86_BUILTIN_PFACC,
27983 IX86_BUILTIN_PFADD,
27984 IX86_BUILTIN_PFCMPEQ,
27985 IX86_BUILTIN_PFCMPGE,
27986 IX86_BUILTIN_PFCMPGT,
27987 IX86_BUILTIN_PFMAX,
27988 IX86_BUILTIN_PFMIN,
27989 IX86_BUILTIN_PFMUL,
27990 IX86_BUILTIN_PFRCP,
27991 IX86_BUILTIN_PFRCPIT1,
27992 IX86_BUILTIN_PFRCPIT2,
27993 IX86_BUILTIN_PFRSQIT1,
27994 IX86_BUILTIN_PFRSQRT,
27995 IX86_BUILTIN_PFSUB,
27996 IX86_BUILTIN_PFSUBR,
27997 IX86_BUILTIN_PI2FD,
27998 IX86_BUILTIN_PMULHRW,
28000 /* 3DNow! Athlon Extensions */
28001 IX86_BUILTIN_PF2IW,
28002 IX86_BUILTIN_PFNACC,
28003 IX86_BUILTIN_PFPNACC,
28004 IX86_BUILTIN_PI2FW,
28005 IX86_BUILTIN_PSWAPDSI,
28006 IX86_BUILTIN_PSWAPDSF,
28008 /* SSE2 */
28009 IX86_BUILTIN_ADDPD,
28010 IX86_BUILTIN_ADDSD,
28011 IX86_BUILTIN_DIVPD,
28012 IX86_BUILTIN_DIVSD,
28013 IX86_BUILTIN_MULPD,
28014 IX86_BUILTIN_MULSD,
28015 IX86_BUILTIN_SUBPD,
28016 IX86_BUILTIN_SUBSD,
28018 IX86_BUILTIN_CMPEQPD,
28019 IX86_BUILTIN_CMPLTPD,
28020 IX86_BUILTIN_CMPLEPD,
28021 IX86_BUILTIN_CMPGTPD,
28022 IX86_BUILTIN_CMPGEPD,
28023 IX86_BUILTIN_CMPNEQPD,
28024 IX86_BUILTIN_CMPNLTPD,
28025 IX86_BUILTIN_CMPNLEPD,
28026 IX86_BUILTIN_CMPNGTPD,
28027 IX86_BUILTIN_CMPNGEPD,
28028 IX86_BUILTIN_CMPORDPD,
28029 IX86_BUILTIN_CMPUNORDPD,
28030 IX86_BUILTIN_CMPEQSD,
28031 IX86_BUILTIN_CMPLTSD,
28032 IX86_BUILTIN_CMPLESD,
28033 IX86_BUILTIN_CMPNEQSD,
28034 IX86_BUILTIN_CMPNLTSD,
28035 IX86_BUILTIN_CMPNLESD,
28036 IX86_BUILTIN_CMPORDSD,
28037 IX86_BUILTIN_CMPUNORDSD,
28039 IX86_BUILTIN_COMIEQSD,
28040 IX86_BUILTIN_COMILTSD,
28041 IX86_BUILTIN_COMILESD,
28042 IX86_BUILTIN_COMIGTSD,
28043 IX86_BUILTIN_COMIGESD,
28044 IX86_BUILTIN_COMINEQSD,
28045 IX86_BUILTIN_UCOMIEQSD,
28046 IX86_BUILTIN_UCOMILTSD,
28047 IX86_BUILTIN_UCOMILESD,
28048 IX86_BUILTIN_UCOMIGTSD,
28049 IX86_BUILTIN_UCOMIGESD,
28050 IX86_BUILTIN_UCOMINEQSD,
28052 IX86_BUILTIN_MAXPD,
28053 IX86_BUILTIN_MAXSD,
28054 IX86_BUILTIN_MINPD,
28055 IX86_BUILTIN_MINSD,
28057 IX86_BUILTIN_ANDPD,
28058 IX86_BUILTIN_ANDNPD,
28059 IX86_BUILTIN_ORPD,
28060 IX86_BUILTIN_XORPD,
28062 IX86_BUILTIN_SQRTPD,
28063 IX86_BUILTIN_SQRTSD,
28065 IX86_BUILTIN_UNPCKHPD,
28066 IX86_BUILTIN_UNPCKLPD,
28068 IX86_BUILTIN_SHUFPD,
28070 IX86_BUILTIN_LOADUPD,
28071 IX86_BUILTIN_STOREUPD,
28072 IX86_BUILTIN_MOVSD,
28074 IX86_BUILTIN_LOADHPD,
28075 IX86_BUILTIN_LOADLPD,
28077 IX86_BUILTIN_CVTDQ2PD,
28078 IX86_BUILTIN_CVTDQ2PS,
28080 IX86_BUILTIN_CVTPD2DQ,
28081 IX86_BUILTIN_CVTPD2PI,
28082 IX86_BUILTIN_CVTPD2PS,
28083 IX86_BUILTIN_CVTTPD2DQ,
28084 IX86_BUILTIN_CVTTPD2PI,
28086 IX86_BUILTIN_CVTPI2PD,
28087 IX86_BUILTIN_CVTSI2SD,
28088 IX86_BUILTIN_CVTSI642SD,
28090 IX86_BUILTIN_CVTSD2SI,
28091 IX86_BUILTIN_CVTSD2SI64,
28092 IX86_BUILTIN_CVTSD2SS,
28093 IX86_BUILTIN_CVTSS2SD,
28094 IX86_BUILTIN_CVTTSD2SI,
28095 IX86_BUILTIN_CVTTSD2SI64,
28097 IX86_BUILTIN_CVTPS2DQ,
28098 IX86_BUILTIN_CVTPS2PD,
28099 IX86_BUILTIN_CVTTPS2DQ,
28101 IX86_BUILTIN_MOVNTI,
28102 IX86_BUILTIN_MOVNTI64,
28103 IX86_BUILTIN_MOVNTPD,
28104 IX86_BUILTIN_MOVNTDQ,
28106 IX86_BUILTIN_MOVQ128,
28108 /* SSE2 MMX */
28109 IX86_BUILTIN_MASKMOVDQU,
28110 IX86_BUILTIN_MOVMSKPD,
28111 IX86_BUILTIN_PMOVMSKB128,
28113 IX86_BUILTIN_PACKSSWB128,
28114 IX86_BUILTIN_PACKSSDW128,
28115 IX86_BUILTIN_PACKUSWB128,
28117 IX86_BUILTIN_PADDB128,
28118 IX86_BUILTIN_PADDW128,
28119 IX86_BUILTIN_PADDD128,
28120 IX86_BUILTIN_PADDQ128,
28121 IX86_BUILTIN_PADDSB128,
28122 IX86_BUILTIN_PADDSW128,
28123 IX86_BUILTIN_PADDUSB128,
28124 IX86_BUILTIN_PADDUSW128,
28125 IX86_BUILTIN_PSUBB128,
28126 IX86_BUILTIN_PSUBW128,
28127 IX86_BUILTIN_PSUBD128,
28128 IX86_BUILTIN_PSUBQ128,
28129 IX86_BUILTIN_PSUBSB128,
28130 IX86_BUILTIN_PSUBSW128,
28131 IX86_BUILTIN_PSUBUSB128,
28132 IX86_BUILTIN_PSUBUSW128,
28134 IX86_BUILTIN_PAND128,
28135 IX86_BUILTIN_PANDN128,
28136 IX86_BUILTIN_POR128,
28137 IX86_BUILTIN_PXOR128,
28139 IX86_BUILTIN_PAVGB128,
28140 IX86_BUILTIN_PAVGW128,
28142 IX86_BUILTIN_PCMPEQB128,
28143 IX86_BUILTIN_PCMPEQW128,
28144 IX86_BUILTIN_PCMPEQD128,
28145 IX86_BUILTIN_PCMPGTB128,
28146 IX86_BUILTIN_PCMPGTW128,
28147 IX86_BUILTIN_PCMPGTD128,
28149 IX86_BUILTIN_PMADDWD128,
28151 IX86_BUILTIN_PMAXSW128,
28152 IX86_BUILTIN_PMAXUB128,
28153 IX86_BUILTIN_PMINSW128,
28154 IX86_BUILTIN_PMINUB128,
28156 IX86_BUILTIN_PMULUDQ,
28157 IX86_BUILTIN_PMULUDQ128,
28158 IX86_BUILTIN_PMULHUW128,
28159 IX86_BUILTIN_PMULHW128,
28160 IX86_BUILTIN_PMULLW128,
28162 IX86_BUILTIN_PSADBW128,
28163 IX86_BUILTIN_PSHUFHW,
28164 IX86_BUILTIN_PSHUFLW,
28165 IX86_BUILTIN_PSHUFD,
28167 IX86_BUILTIN_PSLLDQI128,
28168 IX86_BUILTIN_PSLLWI128,
28169 IX86_BUILTIN_PSLLDI128,
28170 IX86_BUILTIN_PSLLQI128,
28171 IX86_BUILTIN_PSRAWI128,
28172 IX86_BUILTIN_PSRADI128,
28173 IX86_BUILTIN_PSRLDQI128,
28174 IX86_BUILTIN_PSRLWI128,
28175 IX86_BUILTIN_PSRLDI128,
28176 IX86_BUILTIN_PSRLQI128,
28178 IX86_BUILTIN_PSLLDQ128,
28179 IX86_BUILTIN_PSLLW128,
28180 IX86_BUILTIN_PSLLD128,
28181 IX86_BUILTIN_PSLLQ128,
28182 IX86_BUILTIN_PSRAW128,
28183 IX86_BUILTIN_PSRAD128,
28184 IX86_BUILTIN_PSRLW128,
28185 IX86_BUILTIN_PSRLD128,
28186 IX86_BUILTIN_PSRLQ128,
28188 IX86_BUILTIN_PUNPCKHBW128,
28189 IX86_BUILTIN_PUNPCKHWD128,
28190 IX86_BUILTIN_PUNPCKHDQ128,
28191 IX86_BUILTIN_PUNPCKHQDQ128,
28192 IX86_BUILTIN_PUNPCKLBW128,
28193 IX86_BUILTIN_PUNPCKLWD128,
28194 IX86_BUILTIN_PUNPCKLDQ128,
28195 IX86_BUILTIN_PUNPCKLQDQ128,
28197 IX86_BUILTIN_CLFLUSH,
28198 IX86_BUILTIN_MFENCE,
28199 IX86_BUILTIN_LFENCE,
28200 IX86_BUILTIN_PAUSE,
28202 IX86_BUILTIN_FNSTENV,
28203 IX86_BUILTIN_FLDENV,
28204 IX86_BUILTIN_FNSTSW,
28205 IX86_BUILTIN_FNCLEX,
28207 IX86_BUILTIN_BSRSI,
28208 IX86_BUILTIN_BSRDI,
28209 IX86_BUILTIN_RDPMC,
28210 IX86_BUILTIN_RDTSC,
28211 IX86_BUILTIN_RDTSCP,
28212 IX86_BUILTIN_ROLQI,
28213 IX86_BUILTIN_ROLHI,
28214 IX86_BUILTIN_RORQI,
28215 IX86_BUILTIN_RORHI,
28217 /* SSE3. */
28218 IX86_BUILTIN_ADDSUBPS,
28219 IX86_BUILTIN_HADDPS,
28220 IX86_BUILTIN_HSUBPS,
28221 IX86_BUILTIN_MOVSHDUP,
28222 IX86_BUILTIN_MOVSLDUP,
28223 IX86_BUILTIN_ADDSUBPD,
28224 IX86_BUILTIN_HADDPD,
28225 IX86_BUILTIN_HSUBPD,
28226 IX86_BUILTIN_LDDQU,
28228 IX86_BUILTIN_MONITOR,
28229 IX86_BUILTIN_MWAIT,
28231 /* SSSE3. */
28232 IX86_BUILTIN_PHADDW,
28233 IX86_BUILTIN_PHADDD,
28234 IX86_BUILTIN_PHADDSW,
28235 IX86_BUILTIN_PHSUBW,
28236 IX86_BUILTIN_PHSUBD,
28237 IX86_BUILTIN_PHSUBSW,
28238 IX86_BUILTIN_PMADDUBSW,
28239 IX86_BUILTIN_PMULHRSW,
28240 IX86_BUILTIN_PSHUFB,
28241 IX86_BUILTIN_PSIGNB,
28242 IX86_BUILTIN_PSIGNW,
28243 IX86_BUILTIN_PSIGND,
28244 IX86_BUILTIN_PALIGNR,
28245 IX86_BUILTIN_PABSB,
28246 IX86_BUILTIN_PABSW,
28247 IX86_BUILTIN_PABSD,
28249 IX86_BUILTIN_PHADDW128,
28250 IX86_BUILTIN_PHADDD128,
28251 IX86_BUILTIN_PHADDSW128,
28252 IX86_BUILTIN_PHSUBW128,
28253 IX86_BUILTIN_PHSUBD128,
28254 IX86_BUILTIN_PHSUBSW128,
28255 IX86_BUILTIN_PMADDUBSW128,
28256 IX86_BUILTIN_PMULHRSW128,
28257 IX86_BUILTIN_PSHUFB128,
28258 IX86_BUILTIN_PSIGNB128,
28259 IX86_BUILTIN_PSIGNW128,
28260 IX86_BUILTIN_PSIGND128,
28261 IX86_BUILTIN_PALIGNR128,
28262 IX86_BUILTIN_PABSB128,
28263 IX86_BUILTIN_PABSW128,
28264 IX86_BUILTIN_PABSD128,
28266 /* AMDFAM10 - SSE4A New Instructions. */
28267 IX86_BUILTIN_MOVNTSD,
28268 IX86_BUILTIN_MOVNTSS,
28269 IX86_BUILTIN_EXTRQI,
28270 IX86_BUILTIN_EXTRQ,
28271 IX86_BUILTIN_INSERTQI,
28272 IX86_BUILTIN_INSERTQ,
28274 /* SSE4.1. */
28275 IX86_BUILTIN_BLENDPD,
28276 IX86_BUILTIN_BLENDPS,
28277 IX86_BUILTIN_BLENDVPD,
28278 IX86_BUILTIN_BLENDVPS,
28279 IX86_BUILTIN_PBLENDVB128,
28280 IX86_BUILTIN_PBLENDW128,
28282 IX86_BUILTIN_DPPD,
28283 IX86_BUILTIN_DPPS,
28285 IX86_BUILTIN_INSERTPS128,
28287 IX86_BUILTIN_MOVNTDQA,
28288 IX86_BUILTIN_MPSADBW128,
28289 IX86_BUILTIN_PACKUSDW128,
28290 IX86_BUILTIN_PCMPEQQ,
28291 IX86_BUILTIN_PHMINPOSUW128,
28293 IX86_BUILTIN_PMAXSB128,
28294 IX86_BUILTIN_PMAXSD128,
28295 IX86_BUILTIN_PMAXUD128,
28296 IX86_BUILTIN_PMAXUW128,
28298 IX86_BUILTIN_PMINSB128,
28299 IX86_BUILTIN_PMINSD128,
28300 IX86_BUILTIN_PMINUD128,
28301 IX86_BUILTIN_PMINUW128,
28303 IX86_BUILTIN_PMOVSXBW128,
28304 IX86_BUILTIN_PMOVSXBD128,
28305 IX86_BUILTIN_PMOVSXBQ128,
28306 IX86_BUILTIN_PMOVSXWD128,
28307 IX86_BUILTIN_PMOVSXWQ128,
28308 IX86_BUILTIN_PMOVSXDQ128,
28310 IX86_BUILTIN_PMOVZXBW128,
28311 IX86_BUILTIN_PMOVZXBD128,
28312 IX86_BUILTIN_PMOVZXBQ128,
28313 IX86_BUILTIN_PMOVZXWD128,
28314 IX86_BUILTIN_PMOVZXWQ128,
28315 IX86_BUILTIN_PMOVZXDQ128,
28317 IX86_BUILTIN_PMULDQ128,
28318 IX86_BUILTIN_PMULLD128,
28320 IX86_BUILTIN_ROUNDSD,
28321 IX86_BUILTIN_ROUNDSS,
28323 IX86_BUILTIN_ROUNDPD,
28324 IX86_BUILTIN_ROUNDPS,
28326 IX86_BUILTIN_FLOORPD,
28327 IX86_BUILTIN_CEILPD,
28328 IX86_BUILTIN_TRUNCPD,
28329 IX86_BUILTIN_RINTPD,
28330 IX86_BUILTIN_ROUNDPD_AZ,
28332 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
28333 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
28334 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
28336 IX86_BUILTIN_FLOORPS,
28337 IX86_BUILTIN_CEILPS,
28338 IX86_BUILTIN_TRUNCPS,
28339 IX86_BUILTIN_RINTPS,
28340 IX86_BUILTIN_ROUNDPS_AZ,
28342 IX86_BUILTIN_FLOORPS_SFIX,
28343 IX86_BUILTIN_CEILPS_SFIX,
28344 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
28346 IX86_BUILTIN_PTESTZ,
28347 IX86_BUILTIN_PTESTC,
28348 IX86_BUILTIN_PTESTNZC,
28350 IX86_BUILTIN_VEC_INIT_V2SI,
28351 IX86_BUILTIN_VEC_INIT_V4HI,
28352 IX86_BUILTIN_VEC_INIT_V8QI,
28353 IX86_BUILTIN_VEC_EXT_V2DF,
28354 IX86_BUILTIN_VEC_EXT_V2DI,
28355 IX86_BUILTIN_VEC_EXT_V4SF,
28356 IX86_BUILTIN_VEC_EXT_V4SI,
28357 IX86_BUILTIN_VEC_EXT_V8HI,
28358 IX86_BUILTIN_VEC_EXT_V2SI,
28359 IX86_BUILTIN_VEC_EXT_V4HI,
28360 IX86_BUILTIN_VEC_EXT_V16QI,
28361 IX86_BUILTIN_VEC_SET_V2DI,
28362 IX86_BUILTIN_VEC_SET_V4SF,
28363 IX86_BUILTIN_VEC_SET_V4SI,
28364 IX86_BUILTIN_VEC_SET_V8HI,
28365 IX86_BUILTIN_VEC_SET_V4HI,
28366 IX86_BUILTIN_VEC_SET_V16QI,
28368 IX86_BUILTIN_VEC_PACK_SFIX,
28369 IX86_BUILTIN_VEC_PACK_SFIX256,
28371 /* SSE4.2. */
28372 IX86_BUILTIN_CRC32QI,
28373 IX86_BUILTIN_CRC32HI,
28374 IX86_BUILTIN_CRC32SI,
28375 IX86_BUILTIN_CRC32DI,
28377 IX86_BUILTIN_PCMPESTRI128,
28378 IX86_BUILTIN_PCMPESTRM128,
28379 IX86_BUILTIN_PCMPESTRA128,
28380 IX86_BUILTIN_PCMPESTRC128,
28381 IX86_BUILTIN_PCMPESTRO128,
28382 IX86_BUILTIN_PCMPESTRS128,
28383 IX86_BUILTIN_PCMPESTRZ128,
28384 IX86_BUILTIN_PCMPISTRI128,
28385 IX86_BUILTIN_PCMPISTRM128,
28386 IX86_BUILTIN_PCMPISTRA128,
28387 IX86_BUILTIN_PCMPISTRC128,
28388 IX86_BUILTIN_PCMPISTRO128,
28389 IX86_BUILTIN_PCMPISTRS128,
28390 IX86_BUILTIN_PCMPISTRZ128,
28392 IX86_BUILTIN_PCMPGTQ,
28394 /* AES instructions */
28395 IX86_BUILTIN_AESENC128,
28396 IX86_BUILTIN_AESENCLAST128,
28397 IX86_BUILTIN_AESDEC128,
28398 IX86_BUILTIN_AESDECLAST128,
28399 IX86_BUILTIN_AESIMC128,
28400 IX86_BUILTIN_AESKEYGENASSIST128,
28402 /* PCLMUL instruction */
28403 IX86_BUILTIN_PCLMULQDQ128,
28405 /* AVX */
28406 IX86_BUILTIN_ADDPD256,
28407 IX86_BUILTIN_ADDPS256,
28408 IX86_BUILTIN_ADDSUBPD256,
28409 IX86_BUILTIN_ADDSUBPS256,
28410 IX86_BUILTIN_ANDPD256,
28411 IX86_BUILTIN_ANDPS256,
28412 IX86_BUILTIN_ANDNPD256,
28413 IX86_BUILTIN_ANDNPS256,
28414 IX86_BUILTIN_BLENDPD256,
28415 IX86_BUILTIN_BLENDPS256,
28416 IX86_BUILTIN_BLENDVPD256,
28417 IX86_BUILTIN_BLENDVPS256,
28418 IX86_BUILTIN_DIVPD256,
28419 IX86_BUILTIN_DIVPS256,
28420 IX86_BUILTIN_DPPS256,
28421 IX86_BUILTIN_HADDPD256,
28422 IX86_BUILTIN_HADDPS256,
28423 IX86_BUILTIN_HSUBPD256,
28424 IX86_BUILTIN_HSUBPS256,
28425 IX86_BUILTIN_MAXPD256,
28426 IX86_BUILTIN_MAXPS256,
28427 IX86_BUILTIN_MINPD256,
28428 IX86_BUILTIN_MINPS256,
28429 IX86_BUILTIN_MULPD256,
28430 IX86_BUILTIN_MULPS256,
28431 IX86_BUILTIN_ORPD256,
28432 IX86_BUILTIN_ORPS256,
28433 IX86_BUILTIN_SHUFPD256,
28434 IX86_BUILTIN_SHUFPS256,
28435 IX86_BUILTIN_SUBPD256,
28436 IX86_BUILTIN_SUBPS256,
28437 IX86_BUILTIN_XORPD256,
28438 IX86_BUILTIN_XORPS256,
28439 IX86_BUILTIN_CMPSD,
28440 IX86_BUILTIN_CMPSS,
28441 IX86_BUILTIN_CMPPD,
28442 IX86_BUILTIN_CMPPS,
28443 IX86_BUILTIN_CMPPD256,
28444 IX86_BUILTIN_CMPPS256,
28445 IX86_BUILTIN_CVTDQ2PD256,
28446 IX86_BUILTIN_CVTDQ2PS256,
28447 IX86_BUILTIN_CVTPD2PS256,
28448 IX86_BUILTIN_CVTPS2DQ256,
28449 IX86_BUILTIN_CVTPS2PD256,
28450 IX86_BUILTIN_CVTTPD2DQ256,
28451 IX86_BUILTIN_CVTPD2DQ256,
28452 IX86_BUILTIN_CVTTPS2DQ256,
28453 IX86_BUILTIN_EXTRACTF128PD256,
28454 IX86_BUILTIN_EXTRACTF128PS256,
28455 IX86_BUILTIN_EXTRACTF128SI256,
28456 IX86_BUILTIN_VZEROALL,
28457 IX86_BUILTIN_VZEROUPPER,
28458 IX86_BUILTIN_VPERMILVARPD,
28459 IX86_BUILTIN_VPERMILVARPS,
28460 IX86_BUILTIN_VPERMILVARPD256,
28461 IX86_BUILTIN_VPERMILVARPS256,
28462 IX86_BUILTIN_VPERMILPD,
28463 IX86_BUILTIN_VPERMILPS,
28464 IX86_BUILTIN_VPERMILPD256,
28465 IX86_BUILTIN_VPERMILPS256,
28466 IX86_BUILTIN_VPERMIL2PD,
28467 IX86_BUILTIN_VPERMIL2PS,
28468 IX86_BUILTIN_VPERMIL2PD256,
28469 IX86_BUILTIN_VPERMIL2PS256,
28470 IX86_BUILTIN_VPERM2F128PD256,
28471 IX86_BUILTIN_VPERM2F128PS256,
28472 IX86_BUILTIN_VPERM2F128SI256,
28473 IX86_BUILTIN_VBROADCASTSS,
28474 IX86_BUILTIN_VBROADCASTSD256,
28475 IX86_BUILTIN_VBROADCASTSS256,
28476 IX86_BUILTIN_VBROADCASTPD256,
28477 IX86_BUILTIN_VBROADCASTPS256,
28478 IX86_BUILTIN_VINSERTF128PD256,
28479 IX86_BUILTIN_VINSERTF128PS256,
28480 IX86_BUILTIN_VINSERTF128SI256,
28481 IX86_BUILTIN_LOADUPD256,
28482 IX86_BUILTIN_LOADUPS256,
28483 IX86_BUILTIN_STOREUPD256,
28484 IX86_BUILTIN_STOREUPS256,
28485 IX86_BUILTIN_LDDQU256,
28486 IX86_BUILTIN_MOVNTDQ256,
28487 IX86_BUILTIN_MOVNTPD256,
28488 IX86_BUILTIN_MOVNTPS256,
28489 IX86_BUILTIN_LOADDQU256,
28490 IX86_BUILTIN_STOREDQU256,
28491 IX86_BUILTIN_MASKLOADPD,
28492 IX86_BUILTIN_MASKLOADPS,
28493 IX86_BUILTIN_MASKSTOREPD,
28494 IX86_BUILTIN_MASKSTOREPS,
28495 IX86_BUILTIN_MASKLOADPD256,
28496 IX86_BUILTIN_MASKLOADPS256,
28497 IX86_BUILTIN_MASKSTOREPD256,
28498 IX86_BUILTIN_MASKSTOREPS256,
28499 IX86_BUILTIN_MOVSHDUP256,
28500 IX86_BUILTIN_MOVSLDUP256,
28501 IX86_BUILTIN_MOVDDUP256,
28503 IX86_BUILTIN_SQRTPD256,
28504 IX86_BUILTIN_SQRTPS256,
28505 IX86_BUILTIN_SQRTPS_NR256,
28506 IX86_BUILTIN_RSQRTPS256,
28507 IX86_BUILTIN_RSQRTPS_NR256,
28509 IX86_BUILTIN_RCPPS256,
28511 IX86_BUILTIN_ROUNDPD256,
28512 IX86_BUILTIN_ROUNDPS256,
28514 IX86_BUILTIN_FLOORPD256,
28515 IX86_BUILTIN_CEILPD256,
28516 IX86_BUILTIN_TRUNCPD256,
28517 IX86_BUILTIN_RINTPD256,
28518 IX86_BUILTIN_ROUNDPD_AZ256,
28520 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
28521 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
28522 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
28524 IX86_BUILTIN_FLOORPS256,
28525 IX86_BUILTIN_CEILPS256,
28526 IX86_BUILTIN_TRUNCPS256,
28527 IX86_BUILTIN_RINTPS256,
28528 IX86_BUILTIN_ROUNDPS_AZ256,
28530 IX86_BUILTIN_FLOORPS_SFIX256,
28531 IX86_BUILTIN_CEILPS_SFIX256,
28532 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
28534 IX86_BUILTIN_UNPCKHPD256,
28535 IX86_BUILTIN_UNPCKLPD256,
28536 IX86_BUILTIN_UNPCKHPS256,
28537 IX86_BUILTIN_UNPCKLPS256,
28539 IX86_BUILTIN_SI256_SI,
28540 IX86_BUILTIN_PS256_PS,
28541 IX86_BUILTIN_PD256_PD,
28542 IX86_BUILTIN_SI_SI256,
28543 IX86_BUILTIN_PS_PS256,
28544 IX86_BUILTIN_PD_PD256,
28546 IX86_BUILTIN_VTESTZPD,
28547 IX86_BUILTIN_VTESTCPD,
28548 IX86_BUILTIN_VTESTNZCPD,
28549 IX86_BUILTIN_VTESTZPS,
28550 IX86_BUILTIN_VTESTCPS,
28551 IX86_BUILTIN_VTESTNZCPS,
28552 IX86_BUILTIN_VTESTZPD256,
28553 IX86_BUILTIN_VTESTCPD256,
28554 IX86_BUILTIN_VTESTNZCPD256,
28555 IX86_BUILTIN_VTESTZPS256,
28556 IX86_BUILTIN_VTESTCPS256,
28557 IX86_BUILTIN_VTESTNZCPS256,
28558 IX86_BUILTIN_PTESTZ256,
28559 IX86_BUILTIN_PTESTC256,
28560 IX86_BUILTIN_PTESTNZC256,
28562 IX86_BUILTIN_MOVMSKPD256,
28563 IX86_BUILTIN_MOVMSKPS256,
28565 /* AVX2 */
28566 IX86_BUILTIN_MPSADBW256,
28567 IX86_BUILTIN_PABSB256,
28568 IX86_BUILTIN_PABSW256,
28569 IX86_BUILTIN_PABSD256,
28570 IX86_BUILTIN_PACKSSDW256,
28571 IX86_BUILTIN_PACKSSWB256,
28572 IX86_BUILTIN_PACKUSDW256,
28573 IX86_BUILTIN_PACKUSWB256,
28574 IX86_BUILTIN_PADDB256,
28575 IX86_BUILTIN_PADDW256,
28576 IX86_BUILTIN_PADDD256,
28577 IX86_BUILTIN_PADDQ256,
28578 IX86_BUILTIN_PADDSB256,
28579 IX86_BUILTIN_PADDSW256,
28580 IX86_BUILTIN_PADDUSB256,
28581 IX86_BUILTIN_PADDUSW256,
28582 IX86_BUILTIN_PALIGNR256,
28583 IX86_BUILTIN_AND256I,
28584 IX86_BUILTIN_ANDNOT256I,
28585 IX86_BUILTIN_PAVGB256,
28586 IX86_BUILTIN_PAVGW256,
28587 IX86_BUILTIN_PBLENDVB256,
28588 IX86_BUILTIN_PBLENDVW256,
28589 IX86_BUILTIN_PCMPEQB256,
28590 IX86_BUILTIN_PCMPEQW256,
28591 IX86_BUILTIN_PCMPEQD256,
28592 IX86_BUILTIN_PCMPEQQ256,
28593 IX86_BUILTIN_PCMPGTB256,
28594 IX86_BUILTIN_PCMPGTW256,
28595 IX86_BUILTIN_PCMPGTD256,
28596 IX86_BUILTIN_PCMPGTQ256,
28597 IX86_BUILTIN_PHADDW256,
28598 IX86_BUILTIN_PHADDD256,
28599 IX86_BUILTIN_PHADDSW256,
28600 IX86_BUILTIN_PHSUBW256,
28601 IX86_BUILTIN_PHSUBD256,
28602 IX86_BUILTIN_PHSUBSW256,
28603 IX86_BUILTIN_PMADDUBSW256,
28604 IX86_BUILTIN_PMADDWD256,
28605 IX86_BUILTIN_PMAXSB256,
28606 IX86_BUILTIN_PMAXSW256,
28607 IX86_BUILTIN_PMAXSD256,
28608 IX86_BUILTIN_PMAXUB256,
28609 IX86_BUILTIN_PMAXUW256,
28610 IX86_BUILTIN_PMAXUD256,
28611 IX86_BUILTIN_PMINSB256,
28612 IX86_BUILTIN_PMINSW256,
28613 IX86_BUILTIN_PMINSD256,
28614 IX86_BUILTIN_PMINUB256,
28615 IX86_BUILTIN_PMINUW256,
28616 IX86_BUILTIN_PMINUD256,
28617 IX86_BUILTIN_PMOVMSKB256,
28618 IX86_BUILTIN_PMOVSXBW256,
28619 IX86_BUILTIN_PMOVSXBD256,
28620 IX86_BUILTIN_PMOVSXBQ256,
28621 IX86_BUILTIN_PMOVSXWD256,
28622 IX86_BUILTIN_PMOVSXWQ256,
28623 IX86_BUILTIN_PMOVSXDQ256,
28624 IX86_BUILTIN_PMOVZXBW256,
28625 IX86_BUILTIN_PMOVZXBD256,
28626 IX86_BUILTIN_PMOVZXBQ256,
28627 IX86_BUILTIN_PMOVZXWD256,
28628 IX86_BUILTIN_PMOVZXWQ256,
28629 IX86_BUILTIN_PMOVZXDQ256,
28630 IX86_BUILTIN_PMULDQ256,
28631 IX86_BUILTIN_PMULHRSW256,
28632 IX86_BUILTIN_PMULHUW256,
28633 IX86_BUILTIN_PMULHW256,
28634 IX86_BUILTIN_PMULLW256,
28635 IX86_BUILTIN_PMULLD256,
28636 IX86_BUILTIN_PMULUDQ256,
28637 IX86_BUILTIN_POR256,
28638 IX86_BUILTIN_PSADBW256,
28639 IX86_BUILTIN_PSHUFB256,
28640 IX86_BUILTIN_PSHUFD256,
28641 IX86_BUILTIN_PSHUFHW256,
28642 IX86_BUILTIN_PSHUFLW256,
28643 IX86_BUILTIN_PSIGNB256,
28644 IX86_BUILTIN_PSIGNW256,
28645 IX86_BUILTIN_PSIGND256,
28646 IX86_BUILTIN_PSLLDQI256,
28647 IX86_BUILTIN_PSLLWI256,
28648 IX86_BUILTIN_PSLLW256,
28649 IX86_BUILTIN_PSLLDI256,
28650 IX86_BUILTIN_PSLLD256,
28651 IX86_BUILTIN_PSLLQI256,
28652 IX86_BUILTIN_PSLLQ256,
28653 IX86_BUILTIN_PSRAWI256,
28654 IX86_BUILTIN_PSRAW256,
28655 IX86_BUILTIN_PSRADI256,
28656 IX86_BUILTIN_PSRAD256,
28657 IX86_BUILTIN_PSRLDQI256,
28658 IX86_BUILTIN_PSRLWI256,
28659 IX86_BUILTIN_PSRLW256,
28660 IX86_BUILTIN_PSRLDI256,
28661 IX86_BUILTIN_PSRLD256,
28662 IX86_BUILTIN_PSRLQI256,
28663 IX86_BUILTIN_PSRLQ256,
28664 IX86_BUILTIN_PSUBB256,
28665 IX86_BUILTIN_PSUBW256,
28666 IX86_BUILTIN_PSUBD256,
28667 IX86_BUILTIN_PSUBQ256,
28668 IX86_BUILTIN_PSUBSB256,
28669 IX86_BUILTIN_PSUBSW256,
28670 IX86_BUILTIN_PSUBUSB256,
28671 IX86_BUILTIN_PSUBUSW256,
28672 IX86_BUILTIN_PUNPCKHBW256,
28673 IX86_BUILTIN_PUNPCKHWD256,
28674 IX86_BUILTIN_PUNPCKHDQ256,
28675 IX86_BUILTIN_PUNPCKHQDQ256,
28676 IX86_BUILTIN_PUNPCKLBW256,
28677 IX86_BUILTIN_PUNPCKLWD256,
28678 IX86_BUILTIN_PUNPCKLDQ256,
28679 IX86_BUILTIN_PUNPCKLQDQ256,
28680 IX86_BUILTIN_PXOR256,
28681 IX86_BUILTIN_MOVNTDQA256,
28682 IX86_BUILTIN_VBROADCASTSS_PS,
28683 IX86_BUILTIN_VBROADCASTSS_PS256,
28684 IX86_BUILTIN_VBROADCASTSD_PD256,
28685 IX86_BUILTIN_VBROADCASTSI256,
28686 IX86_BUILTIN_PBLENDD256,
28687 IX86_BUILTIN_PBLENDD128,
28688 IX86_BUILTIN_PBROADCASTB256,
28689 IX86_BUILTIN_PBROADCASTW256,
28690 IX86_BUILTIN_PBROADCASTD256,
28691 IX86_BUILTIN_PBROADCASTQ256,
28692 IX86_BUILTIN_PBROADCASTB128,
28693 IX86_BUILTIN_PBROADCASTW128,
28694 IX86_BUILTIN_PBROADCASTD128,
28695 IX86_BUILTIN_PBROADCASTQ128,
28696 IX86_BUILTIN_VPERMVARSI256,
28697 IX86_BUILTIN_VPERMDF256,
28698 IX86_BUILTIN_VPERMVARSF256,
28699 IX86_BUILTIN_VPERMDI256,
28700 IX86_BUILTIN_VPERMTI256,
28701 IX86_BUILTIN_VEXTRACT128I256,
28702 IX86_BUILTIN_VINSERT128I256,
28703 IX86_BUILTIN_MASKLOADD,
28704 IX86_BUILTIN_MASKLOADQ,
28705 IX86_BUILTIN_MASKLOADD256,
28706 IX86_BUILTIN_MASKLOADQ256,
28707 IX86_BUILTIN_MASKSTORED,
28708 IX86_BUILTIN_MASKSTOREQ,
28709 IX86_BUILTIN_MASKSTORED256,
28710 IX86_BUILTIN_MASKSTOREQ256,
28711 IX86_BUILTIN_PSLLVV4DI,
28712 IX86_BUILTIN_PSLLVV2DI,
28713 IX86_BUILTIN_PSLLVV8SI,
28714 IX86_BUILTIN_PSLLVV4SI,
28715 IX86_BUILTIN_PSRAVV8SI,
28716 IX86_BUILTIN_PSRAVV4SI,
28717 IX86_BUILTIN_PSRLVV4DI,
28718 IX86_BUILTIN_PSRLVV2DI,
28719 IX86_BUILTIN_PSRLVV8SI,
28720 IX86_BUILTIN_PSRLVV4SI,
28722 IX86_BUILTIN_GATHERSIV2DF,
28723 IX86_BUILTIN_GATHERSIV4DF,
28724 IX86_BUILTIN_GATHERDIV2DF,
28725 IX86_BUILTIN_GATHERDIV4DF,
28726 IX86_BUILTIN_GATHERSIV4SF,
28727 IX86_BUILTIN_GATHERSIV8SF,
28728 IX86_BUILTIN_GATHERDIV4SF,
28729 IX86_BUILTIN_GATHERDIV8SF,
28730 IX86_BUILTIN_GATHERSIV2DI,
28731 IX86_BUILTIN_GATHERSIV4DI,
28732 IX86_BUILTIN_GATHERDIV2DI,
28733 IX86_BUILTIN_GATHERDIV4DI,
28734 IX86_BUILTIN_GATHERSIV4SI,
28735 IX86_BUILTIN_GATHERSIV8SI,
28736 IX86_BUILTIN_GATHERDIV4SI,
28737 IX86_BUILTIN_GATHERDIV8SI,
28739 /* AVX512F */
28740 IX86_BUILTIN_SI512_SI256,
28741 IX86_BUILTIN_PD512_PD256,
28742 IX86_BUILTIN_PS512_PS256,
28743 IX86_BUILTIN_SI512_SI,
28744 IX86_BUILTIN_PD512_PD,
28745 IX86_BUILTIN_PS512_PS,
28746 IX86_BUILTIN_ADDPD512,
28747 IX86_BUILTIN_ADDPS512,
28748 IX86_BUILTIN_ADDSD_ROUND,
28749 IX86_BUILTIN_ADDSS_ROUND,
28750 IX86_BUILTIN_ALIGND512,
28751 IX86_BUILTIN_ALIGNQ512,
28752 IX86_BUILTIN_BLENDMD512,
28753 IX86_BUILTIN_BLENDMPD512,
28754 IX86_BUILTIN_BLENDMPS512,
28755 IX86_BUILTIN_BLENDMQ512,
28756 IX86_BUILTIN_BROADCASTF32X4_512,
28757 IX86_BUILTIN_BROADCASTF64X4_512,
28758 IX86_BUILTIN_BROADCASTI32X4_512,
28759 IX86_BUILTIN_BROADCASTI64X4_512,
28760 IX86_BUILTIN_BROADCASTSD512,
28761 IX86_BUILTIN_BROADCASTSS512,
28762 IX86_BUILTIN_CMPD512,
28763 IX86_BUILTIN_CMPPD512,
28764 IX86_BUILTIN_CMPPS512,
28765 IX86_BUILTIN_CMPQ512,
28766 IX86_BUILTIN_CMPSD_MASK,
28767 IX86_BUILTIN_CMPSS_MASK,
28768 IX86_BUILTIN_COMIDF,
28769 IX86_BUILTIN_COMISF,
28770 IX86_BUILTIN_COMPRESSPD512,
28771 IX86_BUILTIN_COMPRESSPDSTORE512,
28772 IX86_BUILTIN_COMPRESSPS512,
28773 IX86_BUILTIN_COMPRESSPSSTORE512,
28774 IX86_BUILTIN_CVTDQ2PD512,
28775 IX86_BUILTIN_CVTDQ2PS512,
28776 IX86_BUILTIN_CVTPD2DQ512,
28777 IX86_BUILTIN_CVTPD2PS512,
28778 IX86_BUILTIN_CVTPD2UDQ512,
28779 IX86_BUILTIN_CVTPH2PS512,
28780 IX86_BUILTIN_CVTPS2DQ512,
28781 IX86_BUILTIN_CVTPS2PD512,
28782 IX86_BUILTIN_CVTPS2PH512,
28783 IX86_BUILTIN_CVTPS2UDQ512,
28784 IX86_BUILTIN_CVTSD2SS_ROUND,
28785 IX86_BUILTIN_CVTSI2SD64,
28786 IX86_BUILTIN_CVTSI2SS32,
28787 IX86_BUILTIN_CVTSI2SS64,
28788 IX86_BUILTIN_CVTSS2SD_ROUND,
28789 IX86_BUILTIN_CVTTPD2DQ512,
28790 IX86_BUILTIN_CVTTPD2UDQ512,
28791 IX86_BUILTIN_CVTTPS2DQ512,
28792 IX86_BUILTIN_CVTTPS2UDQ512,
28793 IX86_BUILTIN_CVTUDQ2PD512,
28794 IX86_BUILTIN_CVTUDQ2PS512,
28795 IX86_BUILTIN_CVTUSI2SD32,
28796 IX86_BUILTIN_CVTUSI2SD64,
28797 IX86_BUILTIN_CVTUSI2SS32,
28798 IX86_BUILTIN_CVTUSI2SS64,
28799 IX86_BUILTIN_DIVPD512,
28800 IX86_BUILTIN_DIVPS512,
28801 IX86_BUILTIN_DIVSD_ROUND,
28802 IX86_BUILTIN_DIVSS_ROUND,
28803 IX86_BUILTIN_EXPANDPD512,
28804 IX86_BUILTIN_EXPANDPD512Z,
28805 IX86_BUILTIN_EXPANDPDLOAD512,
28806 IX86_BUILTIN_EXPANDPDLOAD512Z,
28807 IX86_BUILTIN_EXPANDPS512,
28808 IX86_BUILTIN_EXPANDPS512Z,
28809 IX86_BUILTIN_EXPANDPSLOAD512,
28810 IX86_BUILTIN_EXPANDPSLOAD512Z,
28811 IX86_BUILTIN_EXTRACTF32X4,
28812 IX86_BUILTIN_EXTRACTF64X4,
28813 IX86_BUILTIN_EXTRACTI32X4,
28814 IX86_BUILTIN_EXTRACTI64X4,
28815 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28816 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28817 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28818 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28819 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28820 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28821 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28822 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28823 IX86_BUILTIN_GETEXPPD512,
28824 IX86_BUILTIN_GETEXPPS512,
28825 IX86_BUILTIN_GETEXPSD128,
28826 IX86_BUILTIN_GETEXPSS128,
28827 IX86_BUILTIN_GETMANTPD512,
28828 IX86_BUILTIN_GETMANTPS512,
28829 IX86_BUILTIN_GETMANTSD128,
28830 IX86_BUILTIN_GETMANTSS128,
28831 IX86_BUILTIN_INSERTF32X4,
28832 IX86_BUILTIN_INSERTF64X4,
28833 IX86_BUILTIN_INSERTI32X4,
28834 IX86_BUILTIN_INSERTI64X4,
28835 IX86_BUILTIN_LOADAPD512,
28836 IX86_BUILTIN_LOADAPS512,
28837 IX86_BUILTIN_LOADDQUDI512,
28838 IX86_BUILTIN_LOADDQUSI512,
28839 IX86_BUILTIN_LOADUPD512,
28840 IX86_BUILTIN_LOADUPS512,
28841 IX86_BUILTIN_MAXPD512,
28842 IX86_BUILTIN_MAXPS512,
28843 IX86_BUILTIN_MAXSD_ROUND,
28844 IX86_BUILTIN_MAXSS_ROUND,
28845 IX86_BUILTIN_MINPD512,
28846 IX86_BUILTIN_MINPS512,
28847 IX86_BUILTIN_MINSD_ROUND,
28848 IX86_BUILTIN_MINSS_ROUND,
28849 IX86_BUILTIN_MOVAPD512,
28850 IX86_BUILTIN_MOVAPS512,
28851 IX86_BUILTIN_MOVDDUP512,
28852 IX86_BUILTIN_MOVDQA32LOAD512,
28853 IX86_BUILTIN_MOVDQA32STORE512,
28854 IX86_BUILTIN_MOVDQA32_512,
28855 IX86_BUILTIN_MOVDQA64LOAD512,
28856 IX86_BUILTIN_MOVDQA64STORE512,
28857 IX86_BUILTIN_MOVDQA64_512,
28858 IX86_BUILTIN_MOVNTDQ512,
28859 IX86_BUILTIN_MOVNTDQA512,
28860 IX86_BUILTIN_MOVNTPD512,
28861 IX86_BUILTIN_MOVNTPS512,
28862 IX86_BUILTIN_MOVSHDUP512,
28863 IX86_BUILTIN_MOVSLDUP512,
28864 IX86_BUILTIN_MULPD512,
28865 IX86_BUILTIN_MULPS512,
28866 IX86_BUILTIN_MULSD_ROUND,
28867 IX86_BUILTIN_MULSS_ROUND,
28868 IX86_BUILTIN_PABSD512,
28869 IX86_BUILTIN_PABSQ512,
28870 IX86_BUILTIN_PADDD512,
28871 IX86_BUILTIN_PADDQ512,
28872 IX86_BUILTIN_PANDD512,
28873 IX86_BUILTIN_PANDND512,
28874 IX86_BUILTIN_PANDNQ512,
28875 IX86_BUILTIN_PANDQ512,
28876 IX86_BUILTIN_PBROADCASTD512,
28877 IX86_BUILTIN_PBROADCASTD512_GPR,
28878 IX86_BUILTIN_PBROADCASTMB512,
28879 IX86_BUILTIN_PBROADCASTMW512,
28880 IX86_BUILTIN_PBROADCASTQ512,
28881 IX86_BUILTIN_PBROADCASTQ512_GPR,
28882 IX86_BUILTIN_PCMPEQD512_MASK,
28883 IX86_BUILTIN_PCMPEQQ512_MASK,
28884 IX86_BUILTIN_PCMPGTD512_MASK,
28885 IX86_BUILTIN_PCMPGTQ512_MASK,
28886 IX86_BUILTIN_PCOMPRESSD512,
28887 IX86_BUILTIN_PCOMPRESSDSTORE512,
28888 IX86_BUILTIN_PCOMPRESSQ512,
28889 IX86_BUILTIN_PCOMPRESSQSTORE512,
28890 IX86_BUILTIN_PEXPANDD512,
28891 IX86_BUILTIN_PEXPANDD512Z,
28892 IX86_BUILTIN_PEXPANDDLOAD512,
28893 IX86_BUILTIN_PEXPANDDLOAD512Z,
28894 IX86_BUILTIN_PEXPANDQ512,
28895 IX86_BUILTIN_PEXPANDQ512Z,
28896 IX86_BUILTIN_PEXPANDQLOAD512,
28897 IX86_BUILTIN_PEXPANDQLOAD512Z,
28898 IX86_BUILTIN_PMAXSD512,
28899 IX86_BUILTIN_PMAXSQ512,
28900 IX86_BUILTIN_PMAXUD512,
28901 IX86_BUILTIN_PMAXUQ512,
28902 IX86_BUILTIN_PMINSD512,
28903 IX86_BUILTIN_PMINSQ512,
28904 IX86_BUILTIN_PMINUD512,
28905 IX86_BUILTIN_PMINUQ512,
28906 IX86_BUILTIN_PMOVDB512,
28907 IX86_BUILTIN_PMOVDB512_MEM,
28908 IX86_BUILTIN_PMOVDW512,
28909 IX86_BUILTIN_PMOVDW512_MEM,
28910 IX86_BUILTIN_PMOVQB512,
28911 IX86_BUILTIN_PMOVQB512_MEM,
28912 IX86_BUILTIN_PMOVQD512,
28913 IX86_BUILTIN_PMOVQD512_MEM,
28914 IX86_BUILTIN_PMOVQW512,
28915 IX86_BUILTIN_PMOVQW512_MEM,
28916 IX86_BUILTIN_PMOVSDB512,
28917 IX86_BUILTIN_PMOVSDB512_MEM,
28918 IX86_BUILTIN_PMOVSDW512,
28919 IX86_BUILTIN_PMOVSDW512_MEM,
28920 IX86_BUILTIN_PMOVSQB512,
28921 IX86_BUILTIN_PMOVSQB512_MEM,
28922 IX86_BUILTIN_PMOVSQD512,
28923 IX86_BUILTIN_PMOVSQD512_MEM,
28924 IX86_BUILTIN_PMOVSQW512,
28925 IX86_BUILTIN_PMOVSQW512_MEM,
28926 IX86_BUILTIN_PMOVSXBD512,
28927 IX86_BUILTIN_PMOVSXBQ512,
28928 IX86_BUILTIN_PMOVSXDQ512,
28929 IX86_BUILTIN_PMOVSXWD512,
28930 IX86_BUILTIN_PMOVSXWQ512,
28931 IX86_BUILTIN_PMOVUSDB512,
28932 IX86_BUILTIN_PMOVUSDB512_MEM,
28933 IX86_BUILTIN_PMOVUSDW512,
28934 IX86_BUILTIN_PMOVUSDW512_MEM,
28935 IX86_BUILTIN_PMOVUSQB512,
28936 IX86_BUILTIN_PMOVUSQB512_MEM,
28937 IX86_BUILTIN_PMOVUSQD512,
28938 IX86_BUILTIN_PMOVUSQD512_MEM,
28939 IX86_BUILTIN_PMOVUSQW512,
28940 IX86_BUILTIN_PMOVUSQW512_MEM,
28941 IX86_BUILTIN_PMOVZXBD512,
28942 IX86_BUILTIN_PMOVZXBQ512,
28943 IX86_BUILTIN_PMOVZXDQ512,
28944 IX86_BUILTIN_PMOVZXWD512,
28945 IX86_BUILTIN_PMOVZXWQ512,
28946 IX86_BUILTIN_PMULDQ512,
28947 IX86_BUILTIN_PMULLD512,
28948 IX86_BUILTIN_PMULUDQ512,
28949 IX86_BUILTIN_PORD512,
28950 IX86_BUILTIN_PORQ512,
28951 IX86_BUILTIN_PROLD512,
28952 IX86_BUILTIN_PROLQ512,
28953 IX86_BUILTIN_PROLVD512,
28954 IX86_BUILTIN_PROLVQ512,
28955 IX86_BUILTIN_PRORD512,
28956 IX86_BUILTIN_PRORQ512,
28957 IX86_BUILTIN_PRORVD512,
28958 IX86_BUILTIN_PRORVQ512,
28959 IX86_BUILTIN_PSHUFD512,
28960 IX86_BUILTIN_PSLLD512,
28961 IX86_BUILTIN_PSLLDI512,
28962 IX86_BUILTIN_PSLLQ512,
28963 IX86_BUILTIN_PSLLQI512,
28964 IX86_BUILTIN_PSLLVV16SI,
28965 IX86_BUILTIN_PSLLVV8DI,
28966 IX86_BUILTIN_PSRAD512,
28967 IX86_BUILTIN_PSRADI512,
28968 IX86_BUILTIN_PSRAQ512,
28969 IX86_BUILTIN_PSRAQI512,
28970 IX86_BUILTIN_PSRAVV16SI,
28971 IX86_BUILTIN_PSRAVV8DI,
28972 IX86_BUILTIN_PSRLD512,
28973 IX86_BUILTIN_PSRLDI512,
28974 IX86_BUILTIN_PSRLQ512,
28975 IX86_BUILTIN_PSRLQI512,
28976 IX86_BUILTIN_PSRLVV16SI,
28977 IX86_BUILTIN_PSRLVV8DI,
28978 IX86_BUILTIN_PSUBD512,
28979 IX86_BUILTIN_PSUBQ512,
28980 IX86_BUILTIN_PTESTMD512,
28981 IX86_BUILTIN_PTESTMQ512,
28982 IX86_BUILTIN_PTESTNMD512,
28983 IX86_BUILTIN_PTESTNMQ512,
28984 IX86_BUILTIN_PUNPCKHDQ512,
28985 IX86_BUILTIN_PUNPCKHQDQ512,
28986 IX86_BUILTIN_PUNPCKLDQ512,
28987 IX86_BUILTIN_PUNPCKLQDQ512,
28988 IX86_BUILTIN_PXORD512,
28989 IX86_BUILTIN_PXORQ512,
28990 IX86_BUILTIN_RCP14PD512,
28991 IX86_BUILTIN_RCP14PS512,
28992 IX86_BUILTIN_RCP14SD,
28993 IX86_BUILTIN_RCP14SS,
28994 IX86_BUILTIN_RNDSCALEPD,
28995 IX86_BUILTIN_RNDSCALEPS,
28996 IX86_BUILTIN_RNDSCALESD,
28997 IX86_BUILTIN_RNDSCALESS,
28998 IX86_BUILTIN_RSQRT14PD512,
28999 IX86_BUILTIN_RSQRT14PS512,
29000 IX86_BUILTIN_RSQRT14SD,
29001 IX86_BUILTIN_RSQRT14SS,
29002 IX86_BUILTIN_SCALEFPD512,
29003 IX86_BUILTIN_SCALEFPS512,
29004 IX86_BUILTIN_SCALEFSD,
29005 IX86_BUILTIN_SCALEFSS,
29006 IX86_BUILTIN_SHUFPD512,
29007 IX86_BUILTIN_SHUFPS512,
29008 IX86_BUILTIN_SHUF_F32x4,
29009 IX86_BUILTIN_SHUF_F64x2,
29010 IX86_BUILTIN_SHUF_I32x4,
29011 IX86_BUILTIN_SHUF_I64x2,
29012 IX86_BUILTIN_SQRTPD512,
29013 IX86_BUILTIN_SQRTPD512_MASK,
29014 IX86_BUILTIN_SQRTPS512_MASK,
29015 IX86_BUILTIN_SQRTPS_NR512,
29016 IX86_BUILTIN_SQRTSD_ROUND,
29017 IX86_BUILTIN_SQRTSS_ROUND,
29018 IX86_BUILTIN_STOREAPD512,
29019 IX86_BUILTIN_STOREAPS512,
29020 IX86_BUILTIN_STOREDQUDI512,
29021 IX86_BUILTIN_STOREDQUSI512,
29022 IX86_BUILTIN_STOREUPD512,
29023 IX86_BUILTIN_STOREUPS512,
29024 IX86_BUILTIN_SUBPD512,
29025 IX86_BUILTIN_SUBPS512,
29026 IX86_BUILTIN_SUBSD_ROUND,
29027 IX86_BUILTIN_SUBSS_ROUND,
29028 IX86_BUILTIN_UCMPD512,
29029 IX86_BUILTIN_UCMPQ512,
29030 IX86_BUILTIN_UNPCKHPD512,
29031 IX86_BUILTIN_UNPCKHPS512,
29032 IX86_BUILTIN_UNPCKLPD512,
29033 IX86_BUILTIN_UNPCKLPS512,
29034 IX86_BUILTIN_VCVTSD2SI32,
29035 IX86_BUILTIN_VCVTSD2SI64,
29036 IX86_BUILTIN_VCVTSD2USI32,
29037 IX86_BUILTIN_VCVTSD2USI64,
29038 IX86_BUILTIN_VCVTSS2SI32,
29039 IX86_BUILTIN_VCVTSS2SI64,
29040 IX86_BUILTIN_VCVTSS2USI32,
29041 IX86_BUILTIN_VCVTSS2USI64,
29042 IX86_BUILTIN_VCVTTSD2SI32,
29043 IX86_BUILTIN_VCVTTSD2SI64,
29044 IX86_BUILTIN_VCVTTSD2USI32,
29045 IX86_BUILTIN_VCVTTSD2USI64,
29046 IX86_BUILTIN_VCVTTSS2SI32,
29047 IX86_BUILTIN_VCVTTSS2SI64,
29048 IX86_BUILTIN_VCVTTSS2USI32,
29049 IX86_BUILTIN_VCVTTSS2USI64,
29050 IX86_BUILTIN_VFMADDPD512_MASK,
29051 IX86_BUILTIN_VFMADDPD512_MASK3,
29052 IX86_BUILTIN_VFMADDPD512_MASKZ,
29053 IX86_BUILTIN_VFMADDPS512_MASK,
29054 IX86_BUILTIN_VFMADDPS512_MASK3,
29055 IX86_BUILTIN_VFMADDPS512_MASKZ,
29056 IX86_BUILTIN_VFMADDSD3_ROUND,
29057 IX86_BUILTIN_VFMADDSS3_ROUND,
29058 IX86_BUILTIN_VFMADDSUBPD512_MASK,
29059 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
29060 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
29061 IX86_BUILTIN_VFMADDSUBPS512_MASK,
29062 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
29063 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
29064 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
29065 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
29066 IX86_BUILTIN_VFMSUBPD512_MASK3,
29067 IX86_BUILTIN_VFMSUBPS512_MASK3,
29068 IX86_BUILTIN_VFMSUBSD3_MASK3,
29069 IX86_BUILTIN_VFMSUBSS3_MASK3,
29070 IX86_BUILTIN_VFNMADDPD512_MASK,
29071 IX86_BUILTIN_VFNMADDPS512_MASK,
29072 IX86_BUILTIN_VFNMSUBPD512_MASK,
29073 IX86_BUILTIN_VFNMSUBPD512_MASK3,
29074 IX86_BUILTIN_VFNMSUBPS512_MASK,
29075 IX86_BUILTIN_VFNMSUBPS512_MASK3,
29076 IX86_BUILTIN_VPCLZCNTD512,
29077 IX86_BUILTIN_VPCLZCNTQ512,
29078 IX86_BUILTIN_VPCONFLICTD512,
29079 IX86_BUILTIN_VPCONFLICTQ512,
29080 IX86_BUILTIN_VPERMDF512,
29081 IX86_BUILTIN_VPERMDI512,
29082 IX86_BUILTIN_VPERMI2VARD512,
29083 IX86_BUILTIN_VPERMI2VARPD512,
29084 IX86_BUILTIN_VPERMI2VARPS512,
29085 IX86_BUILTIN_VPERMI2VARQ512,
29086 IX86_BUILTIN_VPERMILPD512,
29087 IX86_BUILTIN_VPERMILPS512,
29088 IX86_BUILTIN_VPERMILVARPD512,
29089 IX86_BUILTIN_VPERMILVARPS512,
29090 IX86_BUILTIN_VPERMT2VARD512,
29091 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
29092 IX86_BUILTIN_VPERMT2VARPD512,
29093 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
29094 IX86_BUILTIN_VPERMT2VARPS512,
29095 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
29096 IX86_BUILTIN_VPERMT2VARQ512,
29097 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
29098 IX86_BUILTIN_VPERMVARDF512,
29099 IX86_BUILTIN_VPERMVARDI512,
29100 IX86_BUILTIN_VPERMVARSF512,
29101 IX86_BUILTIN_VPERMVARSI512,
29102 IX86_BUILTIN_VTERNLOGD512_MASK,
29103 IX86_BUILTIN_VTERNLOGD512_MASKZ,
29104 IX86_BUILTIN_VTERNLOGQ512_MASK,
29105 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
29107 /* Mask arithmetic operations */
29108 IX86_BUILTIN_KAND16,
29109 IX86_BUILTIN_KANDN16,
29110 IX86_BUILTIN_KNOT16,
29111 IX86_BUILTIN_KOR16,
29112 IX86_BUILTIN_KORTESTC16,
29113 IX86_BUILTIN_KORTESTZ16,
29114 IX86_BUILTIN_KUNPCKBW,
29115 IX86_BUILTIN_KXNOR16,
29116 IX86_BUILTIN_KXOR16,
29117 IX86_BUILTIN_KMOV16,
29119 /* AVX512VL. */
29120 IX86_BUILTIN_PMOVUSQD256_MEM,
29121 IX86_BUILTIN_PMOVUSQD128_MEM,
29122 IX86_BUILTIN_PMOVSQD256_MEM,
29123 IX86_BUILTIN_PMOVSQD128_MEM,
29124 IX86_BUILTIN_PMOVQD256_MEM,
29125 IX86_BUILTIN_PMOVQD128_MEM,
29126 IX86_BUILTIN_PMOVUSQW256_MEM,
29127 IX86_BUILTIN_PMOVUSQW128_MEM,
29128 IX86_BUILTIN_PMOVSQW256_MEM,
29129 IX86_BUILTIN_PMOVSQW128_MEM,
29130 IX86_BUILTIN_PMOVQW256_MEM,
29131 IX86_BUILTIN_PMOVQW128_MEM,
29132 IX86_BUILTIN_PMOVUSQB256_MEM,
29133 IX86_BUILTIN_PMOVUSQB128_MEM,
29134 IX86_BUILTIN_PMOVSQB256_MEM,
29135 IX86_BUILTIN_PMOVSQB128_MEM,
29136 IX86_BUILTIN_PMOVQB256_MEM,
29137 IX86_BUILTIN_PMOVQB128_MEM,
29138 IX86_BUILTIN_PMOVUSDW256_MEM,
29139 IX86_BUILTIN_PMOVUSDW128_MEM,
29140 IX86_BUILTIN_PMOVSDW256_MEM,
29141 IX86_BUILTIN_PMOVSDW128_MEM,
29142 IX86_BUILTIN_PMOVDW256_MEM,
29143 IX86_BUILTIN_PMOVDW128_MEM,
29144 IX86_BUILTIN_PMOVUSDB256_MEM,
29145 IX86_BUILTIN_PMOVUSDB128_MEM,
29146 IX86_BUILTIN_PMOVSDB256_MEM,
29147 IX86_BUILTIN_PMOVSDB128_MEM,
29148 IX86_BUILTIN_PMOVDB256_MEM,
29149 IX86_BUILTIN_PMOVDB128_MEM,
29150 IX86_BUILTIN_MOVDQA64LOAD256_MASK,
29151 IX86_BUILTIN_MOVDQA64LOAD128_MASK,
29152 IX86_BUILTIN_MOVDQA32LOAD256_MASK,
29153 IX86_BUILTIN_MOVDQA32LOAD128_MASK,
29154 IX86_BUILTIN_MOVDQA64STORE256_MASK,
29155 IX86_BUILTIN_MOVDQA64STORE128_MASK,
29156 IX86_BUILTIN_MOVDQA32STORE256_MASK,
29157 IX86_BUILTIN_MOVDQA32STORE128_MASK,
29158 IX86_BUILTIN_LOADAPD256_MASK,
29159 IX86_BUILTIN_LOADAPD128_MASK,
29160 IX86_BUILTIN_LOADAPS256_MASK,
29161 IX86_BUILTIN_LOADAPS128_MASK,
29162 IX86_BUILTIN_STOREAPD256_MASK,
29163 IX86_BUILTIN_STOREAPD128_MASK,
29164 IX86_BUILTIN_STOREAPS256_MASK,
29165 IX86_BUILTIN_STOREAPS128_MASK,
29166 IX86_BUILTIN_LOADUPD256_MASK,
29167 IX86_BUILTIN_LOADUPD128_MASK,
29168 IX86_BUILTIN_LOADUPS256_MASK,
29169 IX86_BUILTIN_LOADUPS128_MASK,
29170 IX86_BUILTIN_STOREUPD256_MASK,
29171 IX86_BUILTIN_STOREUPD128_MASK,
29172 IX86_BUILTIN_STOREUPS256_MASK,
29173 IX86_BUILTIN_STOREUPS128_MASK,
29174 IX86_BUILTIN_LOADDQUDI256_MASK,
29175 IX86_BUILTIN_LOADDQUDI128_MASK,
29176 IX86_BUILTIN_LOADDQUSI256_MASK,
29177 IX86_BUILTIN_LOADDQUSI128_MASK,
29178 IX86_BUILTIN_LOADDQUHI256_MASK,
29179 IX86_BUILTIN_LOADDQUHI128_MASK,
29180 IX86_BUILTIN_LOADDQUQI256_MASK,
29181 IX86_BUILTIN_LOADDQUQI128_MASK,
29182 IX86_BUILTIN_STOREDQUDI256_MASK,
29183 IX86_BUILTIN_STOREDQUDI128_MASK,
29184 IX86_BUILTIN_STOREDQUSI256_MASK,
29185 IX86_BUILTIN_STOREDQUSI128_MASK,
29186 IX86_BUILTIN_STOREDQUHI256_MASK,
29187 IX86_BUILTIN_STOREDQUHI128_MASK,
29188 IX86_BUILTIN_STOREDQUQI256_MASK,
29189 IX86_BUILTIN_STOREDQUQI128_MASK,
29190 IX86_BUILTIN_COMPRESSPDSTORE256,
29191 IX86_BUILTIN_COMPRESSPDSTORE128,
29192 IX86_BUILTIN_COMPRESSPSSTORE256,
29193 IX86_BUILTIN_COMPRESSPSSTORE128,
29194 IX86_BUILTIN_PCOMPRESSQSTORE256,
29195 IX86_BUILTIN_PCOMPRESSQSTORE128,
29196 IX86_BUILTIN_PCOMPRESSDSTORE256,
29197 IX86_BUILTIN_PCOMPRESSDSTORE128,
29198 IX86_BUILTIN_EXPANDPDLOAD256,
29199 IX86_BUILTIN_EXPANDPDLOAD128,
29200 IX86_BUILTIN_EXPANDPSLOAD256,
29201 IX86_BUILTIN_EXPANDPSLOAD128,
29202 IX86_BUILTIN_PEXPANDQLOAD256,
29203 IX86_BUILTIN_PEXPANDQLOAD128,
29204 IX86_BUILTIN_PEXPANDDLOAD256,
29205 IX86_BUILTIN_PEXPANDDLOAD128,
29206 IX86_BUILTIN_EXPANDPDLOAD256Z,
29207 IX86_BUILTIN_EXPANDPDLOAD128Z,
29208 IX86_BUILTIN_EXPANDPSLOAD256Z,
29209 IX86_BUILTIN_EXPANDPSLOAD128Z,
29210 IX86_BUILTIN_PEXPANDQLOAD256Z,
29211 IX86_BUILTIN_PEXPANDQLOAD128Z,
29212 IX86_BUILTIN_PEXPANDDLOAD256Z,
29213 IX86_BUILTIN_PEXPANDDLOAD128Z,
29214 IX86_BUILTIN_PALIGNR256_MASK,
29215 IX86_BUILTIN_PALIGNR128_MASK,
29216 IX86_BUILTIN_MOVDQA64_256_MASK,
29217 IX86_BUILTIN_MOVDQA64_128_MASK,
29218 IX86_BUILTIN_MOVDQA32_256_MASK,
29219 IX86_BUILTIN_MOVDQA32_128_MASK,
29220 IX86_BUILTIN_MOVAPD256_MASK,
29221 IX86_BUILTIN_MOVAPD128_MASK,
29222 IX86_BUILTIN_MOVAPS256_MASK,
29223 IX86_BUILTIN_MOVAPS128_MASK,
29224 IX86_BUILTIN_MOVDQUHI256_MASK,
29225 IX86_BUILTIN_MOVDQUHI128_MASK,
29226 IX86_BUILTIN_MOVDQUQI256_MASK,
29227 IX86_BUILTIN_MOVDQUQI128_MASK,
29228 IX86_BUILTIN_MINPS128_MASK,
29229 IX86_BUILTIN_MAXPS128_MASK,
29230 IX86_BUILTIN_MINPD128_MASK,
29231 IX86_BUILTIN_MAXPD128_MASK,
29232 IX86_BUILTIN_MAXPD256_MASK,
29233 IX86_BUILTIN_MAXPS256_MASK,
29234 IX86_BUILTIN_MINPD256_MASK,
29235 IX86_BUILTIN_MINPS256_MASK,
29236 IX86_BUILTIN_MULPS128_MASK,
29237 IX86_BUILTIN_DIVPS128_MASK,
29238 IX86_BUILTIN_MULPD128_MASK,
29239 IX86_BUILTIN_DIVPD128_MASK,
29240 IX86_BUILTIN_DIVPD256_MASK,
29241 IX86_BUILTIN_DIVPS256_MASK,
29242 IX86_BUILTIN_MULPD256_MASK,
29243 IX86_BUILTIN_MULPS256_MASK,
29244 IX86_BUILTIN_ADDPD128_MASK,
29245 IX86_BUILTIN_ADDPD256_MASK,
29246 IX86_BUILTIN_ADDPS128_MASK,
29247 IX86_BUILTIN_ADDPS256_MASK,
29248 IX86_BUILTIN_SUBPD128_MASK,
29249 IX86_BUILTIN_SUBPD256_MASK,
29250 IX86_BUILTIN_SUBPS128_MASK,
29251 IX86_BUILTIN_SUBPS256_MASK,
29252 IX86_BUILTIN_XORPD256_MASK,
29253 IX86_BUILTIN_XORPD128_MASK,
29254 IX86_BUILTIN_XORPS256_MASK,
29255 IX86_BUILTIN_XORPS128_MASK,
29256 IX86_BUILTIN_ORPD256_MASK,
29257 IX86_BUILTIN_ORPD128_MASK,
29258 IX86_BUILTIN_ORPS256_MASK,
29259 IX86_BUILTIN_ORPS128_MASK,
29260 IX86_BUILTIN_BROADCASTF32x2_256,
29261 IX86_BUILTIN_BROADCASTI32x2_256,
29262 IX86_BUILTIN_BROADCASTI32x2_128,
29263 IX86_BUILTIN_BROADCASTF64X2_256,
29264 IX86_BUILTIN_BROADCASTI64X2_256,
29265 IX86_BUILTIN_BROADCASTF32X4_256,
29266 IX86_BUILTIN_BROADCASTI32X4_256,
29267 IX86_BUILTIN_EXTRACTF32X4_256,
29268 IX86_BUILTIN_EXTRACTI32X4_256,
29269 IX86_BUILTIN_DBPSADBW256,
29270 IX86_BUILTIN_DBPSADBW128,
29271 IX86_BUILTIN_CVTTPD2QQ256,
29272 IX86_BUILTIN_CVTTPD2QQ128,
29273 IX86_BUILTIN_CVTTPD2UQQ256,
29274 IX86_BUILTIN_CVTTPD2UQQ128,
29275 IX86_BUILTIN_CVTPD2QQ256,
29276 IX86_BUILTIN_CVTPD2QQ128,
29277 IX86_BUILTIN_CVTPD2UQQ256,
29278 IX86_BUILTIN_CVTPD2UQQ128,
29279 IX86_BUILTIN_CVTPD2UDQ256_MASK,
29280 IX86_BUILTIN_CVTPD2UDQ128_MASK,
29281 IX86_BUILTIN_CVTTPS2QQ256,
29282 IX86_BUILTIN_CVTTPS2QQ128,
29283 IX86_BUILTIN_CVTTPS2UQQ256,
29284 IX86_BUILTIN_CVTTPS2UQQ128,
29285 IX86_BUILTIN_CVTTPS2DQ256_MASK,
29286 IX86_BUILTIN_CVTTPS2DQ128_MASK,
29287 IX86_BUILTIN_CVTTPS2UDQ256,
29288 IX86_BUILTIN_CVTTPS2UDQ128,
29289 IX86_BUILTIN_CVTTPD2DQ256_MASK,
29290 IX86_BUILTIN_CVTTPD2DQ128_MASK,
29291 IX86_BUILTIN_CVTTPD2UDQ256_MASK,
29292 IX86_BUILTIN_CVTTPD2UDQ128_MASK,
29293 IX86_BUILTIN_CVTPD2DQ256_MASK,
29294 IX86_BUILTIN_CVTPD2DQ128_MASK,
29295 IX86_BUILTIN_CVTDQ2PD256_MASK,
29296 IX86_BUILTIN_CVTDQ2PD128_MASK,
29297 IX86_BUILTIN_CVTUDQ2PD256_MASK,
29298 IX86_BUILTIN_CVTUDQ2PD128_MASK,
29299 IX86_BUILTIN_CVTDQ2PS256_MASK,
29300 IX86_BUILTIN_CVTDQ2PS128_MASK,
29301 IX86_BUILTIN_CVTUDQ2PS256_MASK,
29302 IX86_BUILTIN_CVTUDQ2PS128_MASK,
29303 IX86_BUILTIN_CVTPS2PD256_MASK,
29304 IX86_BUILTIN_CVTPS2PD128_MASK,
29305 IX86_BUILTIN_PBROADCASTB256_MASK,
29306 IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
29307 IX86_BUILTIN_PBROADCASTB128_MASK,
29308 IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
29309 IX86_BUILTIN_PBROADCASTW256_MASK,
29310 IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
29311 IX86_BUILTIN_PBROADCASTW128_MASK,
29312 IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
29313 IX86_BUILTIN_PBROADCASTD256_MASK,
29314 IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
29315 IX86_BUILTIN_PBROADCASTD128_MASK,
29316 IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
29317 IX86_BUILTIN_PBROADCASTQ256_MASK,
29318 IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
29319 IX86_BUILTIN_PBROADCASTQ128_MASK,
29320 IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
29321 IX86_BUILTIN_BROADCASTSS256,
29322 IX86_BUILTIN_BROADCASTSS128,
29323 IX86_BUILTIN_BROADCASTSD256,
29324 IX86_BUILTIN_EXTRACTF64X2_256,
29325 IX86_BUILTIN_EXTRACTI64X2_256,
29326 IX86_BUILTIN_INSERTF32X4_256,
29327 IX86_BUILTIN_INSERTI32X4_256,
29328 IX86_BUILTIN_PMOVSXBW256_MASK,
29329 IX86_BUILTIN_PMOVSXBW128_MASK,
29330 IX86_BUILTIN_PMOVSXBD256_MASK,
29331 IX86_BUILTIN_PMOVSXBD128_MASK,
29332 IX86_BUILTIN_PMOVSXBQ256_MASK,
29333 IX86_BUILTIN_PMOVSXBQ128_MASK,
29334 IX86_BUILTIN_PMOVSXWD256_MASK,
29335 IX86_BUILTIN_PMOVSXWD128_MASK,
29336 IX86_BUILTIN_PMOVSXWQ256_MASK,
29337 IX86_BUILTIN_PMOVSXWQ128_MASK,
29338 IX86_BUILTIN_PMOVSXDQ256_MASK,
29339 IX86_BUILTIN_PMOVSXDQ128_MASK,
29340 IX86_BUILTIN_PMOVZXBW256_MASK,
29341 IX86_BUILTIN_PMOVZXBW128_MASK,
29342 IX86_BUILTIN_PMOVZXBD256_MASK,
29343 IX86_BUILTIN_PMOVZXBD128_MASK,
29344 IX86_BUILTIN_PMOVZXBQ256_MASK,
29345 IX86_BUILTIN_PMOVZXBQ128_MASK,
29346 IX86_BUILTIN_PMOVZXWD256_MASK,
29347 IX86_BUILTIN_PMOVZXWD128_MASK,
29348 IX86_BUILTIN_PMOVZXWQ256_MASK,
29349 IX86_BUILTIN_PMOVZXWQ128_MASK,
29350 IX86_BUILTIN_PMOVZXDQ256_MASK,
29351 IX86_BUILTIN_PMOVZXDQ128_MASK,
29352 IX86_BUILTIN_REDUCEPD256_MASK,
29353 IX86_BUILTIN_REDUCEPD128_MASK,
29354 IX86_BUILTIN_REDUCEPS256_MASK,
29355 IX86_BUILTIN_REDUCEPS128_MASK,
29356 IX86_BUILTIN_REDUCESD_MASK,
29357 IX86_BUILTIN_REDUCESS_MASK,
29358 IX86_BUILTIN_VPERMVARHI256_MASK,
29359 IX86_BUILTIN_VPERMVARHI128_MASK,
29360 IX86_BUILTIN_VPERMT2VARHI256,
29361 IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
29362 IX86_BUILTIN_VPERMT2VARHI128,
29363 IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
29364 IX86_BUILTIN_VPERMI2VARHI256,
29365 IX86_BUILTIN_VPERMI2VARHI128,
29366 IX86_BUILTIN_RCP14PD256,
29367 IX86_BUILTIN_RCP14PD128,
29368 IX86_BUILTIN_RCP14PS256,
29369 IX86_BUILTIN_RCP14PS128,
29370 IX86_BUILTIN_RSQRT14PD256_MASK,
29371 IX86_BUILTIN_RSQRT14PD128_MASK,
29372 IX86_BUILTIN_RSQRT14PS256_MASK,
29373 IX86_BUILTIN_RSQRT14PS128_MASK,
29374 IX86_BUILTIN_SQRTPD256_MASK,
29375 IX86_BUILTIN_SQRTPD128_MASK,
29376 IX86_BUILTIN_SQRTPS256_MASK,
29377 IX86_BUILTIN_SQRTPS128_MASK,
29378 IX86_BUILTIN_PADDB128_MASK,
29379 IX86_BUILTIN_PADDW128_MASK,
29380 IX86_BUILTIN_PADDD128_MASK,
29381 IX86_BUILTIN_PADDQ128_MASK,
29382 IX86_BUILTIN_PSUBB128_MASK,
29383 IX86_BUILTIN_PSUBW128_MASK,
29384 IX86_BUILTIN_PSUBD128_MASK,
29385 IX86_BUILTIN_PSUBQ128_MASK,
29386 IX86_BUILTIN_PADDSB128_MASK,
29387 IX86_BUILTIN_PADDSW128_MASK,
29388 IX86_BUILTIN_PSUBSB128_MASK,
29389 IX86_BUILTIN_PSUBSW128_MASK,
29390 IX86_BUILTIN_PADDUSB128_MASK,
29391 IX86_BUILTIN_PADDUSW128_MASK,
29392 IX86_BUILTIN_PSUBUSB128_MASK,
29393 IX86_BUILTIN_PSUBUSW128_MASK,
29394 IX86_BUILTIN_PADDB256_MASK,
29395 IX86_BUILTIN_PADDW256_MASK,
29396 IX86_BUILTIN_PADDD256_MASK,
29397 IX86_BUILTIN_PADDQ256_MASK,
29398 IX86_BUILTIN_PADDSB256_MASK,
29399 IX86_BUILTIN_PADDSW256_MASK,
29400 IX86_BUILTIN_PADDUSB256_MASK,
29401 IX86_BUILTIN_PADDUSW256_MASK,
29402 IX86_BUILTIN_PSUBB256_MASK,
29403 IX86_BUILTIN_PSUBW256_MASK,
29404 IX86_BUILTIN_PSUBD256_MASK,
29405 IX86_BUILTIN_PSUBQ256_MASK,
29406 IX86_BUILTIN_PSUBSB256_MASK,
29407 IX86_BUILTIN_PSUBSW256_MASK,
29408 IX86_BUILTIN_PSUBUSB256_MASK,
29409 IX86_BUILTIN_PSUBUSW256_MASK,
29410 IX86_BUILTIN_SHUF_F64x2_256,
29411 IX86_BUILTIN_SHUF_I64x2_256,
29412 IX86_BUILTIN_SHUF_I32x4_256,
29413 IX86_BUILTIN_SHUF_F32x4_256,
29414 IX86_BUILTIN_PMOVWB128,
29415 IX86_BUILTIN_PMOVWB256,
29416 IX86_BUILTIN_PMOVSWB128,
29417 IX86_BUILTIN_PMOVSWB256,
29418 IX86_BUILTIN_PMOVUSWB128,
29419 IX86_BUILTIN_PMOVUSWB256,
29420 IX86_BUILTIN_PMOVDB128,
29421 IX86_BUILTIN_PMOVDB256,
29422 IX86_BUILTIN_PMOVSDB128,
29423 IX86_BUILTIN_PMOVSDB256,
29424 IX86_BUILTIN_PMOVUSDB128,
29425 IX86_BUILTIN_PMOVUSDB256,
29426 IX86_BUILTIN_PMOVDW128,
29427 IX86_BUILTIN_PMOVDW256,
29428 IX86_BUILTIN_PMOVSDW128,
29429 IX86_BUILTIN_PMOVSDW256,
29430 IX86_BUILTIN_PMOVUSDW128,
29431 IX86_BUILTIN_PMOVUSDW256,
29432 IX86_BUILTIN_PMOVQB128,
29433 IX86_BUILTIN_PMOVQB256,
29434 IX86_BUILTIN_PMOVSQB128,
29435 IX86_BUILTIN_PMOVSQB256,
29436 IX86_BUILTIN_PMOVUSQB128,
29437 IX86_BUILTIN_PMOVUSQB256,
29438 IX86_BUILTIN_PMOVQW128,
29439 IX86_BUILTIN_PMOVQW256,
29440 IX86_BUILTIN_PMOVSQW128,
29441 IX86_BUILTIN_PMOVSQW256,
29442 IX86_BUILTIN_PMOVUSQW128,
29443 IX86_BUILTIN_PMOVUSQW256,
29444 IX86_BUILTIN_PMOVQD128,
29445 IX86_BUILTIN_PMOVQD256,
29446 IX86_BUILTIN_PMOVSQD128,
29447 IX86_BUILTIN_PMOVSQD256,
29448 IX86_BUILTIN_PMOVUSQD128,
29449 IX86_BUILTIN_PMOVUSQD256,
29450 IX86_BUILTIN_RANGEPD256,
29451 IX86_BUILTIN_RANGEPD128,
29452 IX86_BUILTIN_RANGEPS256,
29453 IX86_BUILTIN_RANGEPS128,
29454 IX86_BUILTIN_GETEXPPS256,
29455 IX86_BUILTIN_GETEXPPD256,
29456 IX86_BUILTIN_GETEXPPS128,
29457 IX86_BUILTIN_GETEXPPD128,
29458 IX86_BUILTIN_FIXUPIMMPD256_MASK,
29459 IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
29460 IX86_BUILTIN_FIXUPIMMPS256_MASK,
29461 IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
29462 IX86_BUILTIN_FIXUPIMMPD128_MASK,
29463 IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
29464 IX86_BUILTIN_FIXUPIMMPS128_MASK,
29465 IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
29466 IX86_BUILTIN_PABSQ256,
29467 IX86_BUILTIN_PABSQ128,
29468 IX86_BUILTIN_PABSD256_MASK,
29469 IX86_BUILTIN_PABSD128_MASK,
29470 IX86_BUILTIN_PMULHRSW256_MASK,
29471 IX86_BUILTIN_PMULHRSW128_MASK,
29472 IX86_BUILTIN_PMULHUW128_MASK,
29473 IX86_BUILTIN_PMULHUW256_MASK,
29474 IX86_BUILTIN_PMULHW256_MASK,
29475 IX86_BUILTIN_PMULHW128_MASK,
29476 IX86_BUILTIN_PMULLW256_MASK,
29477 IX86_BUILTIN_PMULLW128_MASK,
29478 IX86_BUILTIN_PMULLQ256,
29479 IX86_BUILTIN_PMULLQ128,
29480 IX86_BUILTIN_ANDPD256_MASK,
29481 IX86_BUILTIN_ANDPD128_MASK,
29482 IX86_BUILTIN_ANDPS256_MASK,
29483 IX86_BUILTIN_ANDPS128_MASK,
29484 IX86_BUILTIN_ANDNPD256_MASK,
29485 IX86_BUILTIN_ANDNPD128_MASK,
29486 IX86_BUILTIN_ANDNPS256_MASK,
29487 IX86_BUILTIN_ANDNPS128_MASK,
29488 IX86_BUILTIN_PSLLWI128_MASK,
29489 IX86_BUILTIN_PSLLDI128_MASK,
29490 IX86_BUILTIN_PSLLQI128_MASK,
29491 IX86_BUILTIN_PSLLW128_MASK,
29492 IX86_BUILTIN_PSLLD128_MASK,
29493 IX86_BUILTIN_PSLLQ128_MASK,
29494 IX86_BUILTIN_PSLLWI256_MASK ,
29495 IX86_BUILTIN_PSLLW256_MASK,
29496 IX86_BUILTIN_PSLLDI256_MASK,
29497 IX86_BUILTIN_PSLLD256_MASK,
29498 IX86_BUILTIN_PSLLQI256_MASK,
29499 IX86_BUILTIN_PSLLQ256_MASK,
29500 IX86_BUILTIN_PSRADI128_MASK,
29501 IX86_BUILTIN_PSRAD128_MASK,
29502 IX86_BUILTIN_PSRADI256_MASK,
29503 IX86_BUILTIN_PSRAD256_MASK,
29504 IX86_BUILTIN_PSRAQI128_MASK,
29505 IX86_BUILTIN_PSRAQ128_MASK,
29506 IX86_BUILTIN_PSRAQI256_MASK,
29507 IX86_BUILTIN_PSRAQ256_MASK,
29508 IX86_BUILTIN_PANDD256,
29509 IX86_BUILTIN_PANDD128,
29510 IX86_BUILTIN_PSRLDI128_MASK,
29511 IX86_BUILTIN_PSRLD128_MASK,
29512 IX86_BUILTIN_PSRLDI256_MASK,
29513 IX86_BUILTIN_PSRLD256_MASK,
29514 IX86_BUILTIN_PSRLQI128_MASK,
29515 IX86_BUILTIN_PSRLQ128_MASK,
29516 IX86_BUILTIN_PSRLQI256_MASK,
29517 IX86_BUILTIN_PSRLQ256_MASK,
29518 IX86_BUILTIN_PANDQ256,
29519 IX86_BUILTIN_PANDQ128,
29520 IX86_BUILTIN_PANDND256,
29521 IX86_BUILTIN_PANDND128,
29522 IX86_BUILTIN_PANDNQ256,
29523 IX86_BUILTIN_PANDNQ128,
29524 IX86_BUILTIN_PORD256,
29525 IX86_BUILTIN_PORD128,
29526 IX86_BUILTIN_PORQ256,
29527 IX86_BUILTIN_PORQ128,
29528 IX86_BUILTIN_PXORD256,
29529 IX86_BUILTIN_PXORD128,
29530 IX86_BUILTIN_PXORQ256,
29531 IX86_BUILTIN_PXORQ128,
29532 IX86_BUILTIN_PACKSSWB256_MASK,
29533 IX86_BUILTIN_PACKSSWB128_MASK,
29534 IX86_BUILTIN_PACKUSWB256_MASK,
29535 IX86_BUILTIN_PACKUSWB128_MASK,
29536 IX86_BUILTIN_RNDSCALEPS256,
29537 IX86_BUILTIN_RNDSCALEPD256,
29538 IX86_BUILTIN_RNDSCALEPS128,
29539 IX86_BUILTIN_RNDSCALEPD128,
29540 IX86_BUILTIN_VTERNLOGQ256_MASK,
29541 IX86_BUILTIN_VTERNLOGQ256_MASKZ,
29542 IX86_BUILTIN_VTERNLOGD256_MASK,
29543 IX86_BUILTIN_VTERNLOGD256_MASKZ,
29544 IX86_BUILTIN_VTERNLOGQ128_MASK,
29545 IX86_BUILTIN_VTERNLOGQ128_MASKZ,
29546 IX86_BUILTIN_VTERNLOGD128_MASK,
29547 IX86_BUILTIN_VTERNLOGD128_MASKZ,
29548 IX86_BUILTIN_SCALEFPD256,
29549 IX86_BUILTIN_SCALEFPS256,
29550 IX86_BUILTIN_SCALEFPD128,
29551 IX86_BUILTIN_SCALEFPS128,
29552 IX86_BUILTIN_VFMADDPD256_MASK,
29553 IX86_BUILTIN_VFMADDPD256_MASK3,
29554 IX86_BUILTIN_VFMADDPD256_MASKZ,
29555 IX86_BUILTIN_VFMADDPD128_MASK,
29556 IX86_BUILTIN_VFMADDPD128_MASK3,
29557 IX86_BUILTIN_VFMADDPD128_MASKZ,
29558 IX86_BUILTIN_VFMADDPS256_MASK,
29559 IX86_BUILTIN_VFMADDPS256_MASK3,
29560 IX86_BUILTIN_VFMADDPS256_MASKZ,
29561 IX86_BUILTIN_VFMADDPS128_MASK,
29562 IX86_BUILTIN_VFMADDPS128_MASK3,
29563 IX86_BUILTIN_VFMADDPS128_MASKZ,
29564 IX86_BUILTIN_VFMSUBPD256_MASK3,
29565 IX86_BUILTIN_VFMSUBPD128_MASK3,
29566 IX86_BUILTIN_VFMSUBPS256_MASK3,
29567 IX86_BUILTIN_VFMSUBPS128_MASK3,
29568 IX86_BUILTIN_VFNMADDPD256_MASK,
29569 IX86_BUILTIN_VFNMADDPD128_MASK,
29570 IX86_BUILTIN_VFNMADDPS256_MASK,
29571 IX86_BUILTIN_VFNMADDPS128_MASK,
29572 IX86_BUILTIN_VFNMSUBPD256_MASK,
29573 IX86_BUILTIN_VFNMSUBPD256_MASK3,
29574 IX86_BUILTIN_VFNMSUBPD128_MASK,
29575 IX86_BUILTIN_VFNMSUBPD128_MASK3,
29576 IX86_BUILTIN_VFNMSUBPS256_MASK,
29577 IX86_BUILTIN_VFNMSUBPS256_MASK3,
29578 IX86_BUILTIN_VFNMSUBPS128_MASK,
29579 IX86_BUILTIN_VFNMSUBPS128_MASK3,
29580 IX86_BUILTIN_VFMADDSUBPD256_MASK,
29581 IX86_BUILTIN_VFMADDSUBPD256_MASK3,
29582 IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
29583 IX86_BUILTIN_VFMADDSUBPD128_MASK,
29584 IX86_BUILTIN_VFMADDSUBPD128_MASK3,
29585 IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
29586 IX86_BUILTIN_VFMADDSUBPS256_MASK,
29587 IX86_BUILTIN_VFMADDSUBPS256_MASK3,
29588 IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
29589 IX86_BUILTIN_VFMADDSUBPS128_MASK,
29590 IX86_BUILTIN_VFMADDSUBPS128_MASK3,
29591 IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
29592 IX86_BUILTIN_VFMSUBADDPD256_MASK3,
29593 IX86_BUILTIN_VFMSUBADDPD128_MASK3,
29594 IX86_BUILTIN_VFMSUBADDPS256_MASK3,
29595 IX86_BUILTIN_VFMSUBADDPS128_MASK3,
29596 IX86_BUILTIN_INSERTF64X2_256,
29597 IX86_BUILTIN_INSERTI64X2_256,
29598 IX86_BUILTIN_PSRAVV16HI,
29599 IX86_BUILTIN_PSRAVV8HI,
29600 IX86_BUILTIN_PMADDUBSW256_MASK,
29601 IX86_BUILTIN_PMADDUBSW128_MASK,
29602 IX86_BUILTIN_PMADDWD256_MASK,
29603 IX86_BUILTIN_PMADDWD128_MASK,
29604 IX86_BUILTIN_PSRLVV16HI,
29605 IX86_BUILTIN_PSRLVV8HI,
29606 IX86_BUILTIN_CVTPS2DQ256_MASK,
29607 IX86_BUILTIN_CVTPS2DQ128_MASK,
29608 IX86_BUILTIN_CVTPS2UDQ256,
29609 IX86_BUILTIN_CVTPS2UDQ128,
29610 IX86_BUILTIN_CVTPS2QQ256,
29611 IX86_BUILTIN_CVTPS2QQ128,
29612 IX86_BUILTIN_CVTPS2UQQ256,
29613 IX86_BUILTIN_CVTPS2UQQ128,
29614 IX86_BUILTIN_GETMANTPS256,
29615 IX86_BUILTIN_GETMANTPS128,
29616 IX86_BUILTIN_GETMANTPD256,
29617 IX86_BUILTIN_GETMANTPD128,
29618 IX86_BUILTIN_MOVDDUP256_MASK,
29619 IX86_BUILTIN_MOVDDUP128_MASK,
29620 IX86_BUILTIN_MOVSHDUP256_MASK,
29621 IX86_BUILTIN_MOVSHDUP128_MASK,
29622 IX86_BUILTIN_MOVSLDUP256_MASK,
29623 IX86_BUILTIN_MOVSLDUP128_MASK,
29624 IX86_BUILTIN_CVTQQ2PS256,
29625 IX86_BUILTIN_CVTQQ2PS128,
29626 IX86_BUILTIN_CVTUQQ2PS256,
29627 IX86_BUILTIN_CVTUQQ2PS128,
29628 IX86_BUILTIN_CVTQQ2PD256,
29629 IX86_BUILTIN_CVTQQ2PD128,
29630 IX86_BUILTIN_CVTUQQ2PD256,
29631 IX86_BUILTIN_CVTUQQ2PD128,
29632 IX86_BUILTIN_VPERMT2VARQ256,
29633 IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
29634 IX86_BUILTIN_VPERMT2VARD256,
29635 IX86_BUILTIN_VPERMT2VARD256_MASKZ,
29636 IX86_BUILTIN_VPERMI2VARQ256,
29637 IX86_BUILTIN_VPERMI2VARD256,
29638 IX86_BUILTIN_VPERMT2VARPD256,
29639 IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
29640 IX86_BUILTIN_VPERMT2VARPS256,
29641 IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
29642 IX86_BUILTIN_VPERMI2VARPD256,
29643 IX86_BUILTIN_VPERMI2VARPS256,
29644 IX86_BUILTIN_VPERMT2VARQ128,
29645 IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
29646 IX86_BUILTIN_VPERMT2VARD128,
29647 IX86_BUILTIN_VPERMT2VARD128_MASKZ,
29648 IX86_BUILTIN_VPERMI2VARQ128,
29649 IX86_BUILTIN_VPERMI2VARD128,
29650 IX86_BUILTIN_VPERMT2VARPD128,
29651 IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
29652 IX86_BUILTIN_VPERMT2VARPS128,
29653 IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
29654 IX86_BUILTIN_VPERMI2VARPD128,
29655 IX86_BUILTIN_VPERMI2VARPS128,
29656 IX86_BUILTIN_PSHUFB256_MASK,
29657 IX86_BUILTIN_PSHUFB128_MASK,
29658 IX86_BUILTIN_PSHUFHW256_MASK,
29659 IX86_BUILTIN_PSHUFHW128_MASK,
29660 IX86_BUILTIN_PSHUFLW256_MASK,
29661 IX86_BUILTIN_PSHUFLW128_MASK,
29662 IX86_BUILTIN_PSHUFD256_MASK,
29663 IX86_BUILTIN_PSHUFD128_MASK,
29664 IX86_BUILTIN_SHUFPD256_MASK,
29665 IX86_BUILTIN_SHUFPD128_MASK,
29666 IX86_BUILTIN_SHUFPS256_MASK,
29667 IX86_BUILTIN_SHUFPS128_MASK,
29668 IX86_BUILTIN_PROLVQ256,
29669 IX86_BUILTIN_PROLVQ128,
29670 IX86_BUILTIN_PROLQ256,
29671 IX86_BUILTIN_PROLQ128,
29672 IX86_BUILTIN_PRORVQ256,
29673 IX86_BUILTIN_PRORVQ128,
29674 IX86_BUILTIN_PRORQ256,
29675 IX86_BUILTIN_PRORQ128,
29676 IX86_BUILTIN_PSRAVQ128,
29677 IX86_BUILTIN_PSRAVQ256,
29678 IX86_BUILTIN_PSLLVV4DI_MASK,
29679 IX86_BUILTIN_PSLLVV2DI_MASK,
29680 IX86_BUILTIN_PSLLVV8SI_MASK,
29681 IX86_BUILTIN_PSLLVV4SI_MASK,
29682 IX86_BUILTIN_PSRAVV8SI_MASK,
29683 IX86_BUILTIN_PSRAVV4SI_MASK,
29684 IX86_BUILTIN_PSRLVV4DI_MASK,
29685 IX86_BUILTIN_PSRLVV2DI_MASK,
29686 IX86_BUILTIN_PSRLVV8SI_MASK,
29687 IX86_BUILTIN_PSRLVV4SI_MASK,
29688 IX86_BUILTIN_PSRAWI256_MASK,
29689 IX86_BUILTIN_PSRAW256_MASK,
29690 IX86_BUILTIN_PSRAWI128_MASK,
29691 IX86_BUILTIN_PSRAW128_MASK,
29692 IX86_BUILTIN_PSRLWI256_MASK,
29693 IX86_BUILTIN_PSRLW256_MASK,
29694 IX86_BUILTIN_PSRLWI128_MASK,
29695 IX86_BUILTIN_PSRLW128_MASK,
29696 IX86_BUILTIN_PRORVD256,
29697 IX86_BUILTIN_PROLVD256,
29698 IX86_BUILTIN_PRORD256,
29699 IX86_BUILTIN_PROLD256,
29700 IX86_BUILTIN_PRORVD128,
29701 IX86_BUILTIN_PROLVD128,
29702 IX86_BUILTIN_PRORD128,
29703 IX86_BUILTIN_PROLD128,
29704 IX86_BUILTIN_FPCLASSPD256,
29705 IX86_BUILTIN_FPCLASSPD128,
29706 IX86_BUILTIN_FPCLASSSD,
29707 IX86_BUILTIN_FPCLASSPS256,
29708 IX86_BUILTIN_FPCLASSPS128,
29709 IX86_BUILTIN_FPCLASSSS,
29710 IX86_BUILTIN_CVTB2MASK128,
29711 IX86_BUILTIN_CVTB2MASK256,
29712 IX86_BUILTIN_CVTW2MASK128,
29713 IX86_BUILTIN_CVTW2MASK256,
29714 IX86_BUILTIN_CVTD2MASK128,
29715 IX86_BUILTIN_CVTD2MASK256,
29716 IX86_BUILTIN_CVTQ2MASK128,
29717 IX86_BUILTIN_CVTQ2MASK256,
29718 IX86_BUILTIN_CVTMASK2B128,
29719 IX86_BUILTIN_CVTMASK2B256,
29720 IX86_BUILTIN_CVTMASK2W128,
29721 IX86_BUILTIN_CVTMASK2W256,
29722 IX86_BUILTIN_CVTMASK2D128,
29723 IX86_BUILTIN_CVTMASK2D256,
29724 IX86_BUILTIN_CVTMASK2Q128,
29725 IX86_BUILTIN_CVTMASK2Q256,
29726 IX86_BUILTIN_PCMPEQB128_MASK,
29727 IX86_BUILTIN_PCMPEQB256_MASK,
29728 IX86_BUILTIN_PCMPEQW128_MASK,
29729 IX86_BUILTIN_PCMPEQW256_MASK,
29730 IX86_BUILTIN_PCMPEQD128_MASK,
29731 IX86_BUILTIN_PCMPEQD256_MASK,
29732 IX86_BUILTIN_PCMPEQQ128_MASK,
29733 IX86_BUILTIN_PCMPEQQ256_MASK,
29734 IX86_BUILTIN_PCMPGTB128_MASK,
29735 IX86_BUILTIN_PCMPGTB256_MASK,
29736 IX86_BUILTIN_PCMPGTW128_MASK,
29737 IX86_BUILTIN_PCMPGTW256_MASK,
29738 IX86_BUILTIN_PCMPGTD128_MASK,
29739 IX86_BUILTIN_PCMPGTD256_MASK,
29740 IX86_BUILTIN_PCMPGTQ128_MASK,
29741 IX86_BUILTIN_PCMPGTQ256_MASK,
29742 IX86_BUILTIN_PTESTMB128,
29743 IX86_BUILTIN_PTESTMB256,
29744 IX86_BUILTIN_PTESTMW128,
29745 IX86_BUILTIN_PTESTMW256,
29746 IX86_BUILTIN_PTESTMD128,
29747 IX86_BUILTIN_PTESTMD256,
29748 IX86_BUILTIN_PTESTMQ128,
29749 IX86_BUILTIN_PTESTMQ256,
29750 IX86_BUILTIN_PTESTNMB128,
29751 IX86_BUILTIN_PTESTNMB256,
29752 IX86_BUILTIN_PTESTNMW128,
29753 IX86_BUILTIN_PTESTNMW256,
29754 IX86_BUILTIN_PTESTNMD128,
29755 IX86_BUILTIN_PTESTNMD256,
29756 IX86_BUILTIN_PTESTNMQ128,
29757 IX86_BUILTIN_PTESTNMQ256,
29758 IX86_BUILTIN_PBROADCASTMB128,
29759 IX86_BUILTIN_PBROADCASTMB256,
29760 IX86_BUILTIN_PBROADCASTMW128,
29761 IX86_BUILTIN_PBROADCASTMW256,
29762 IX86_BUILTIN_COMPRESSPD256,
29763 IX86_BUILTIN_COMPRESSPD128,
29764 IX86_BUILTIN_COMPRESSPS256,
29765 IX86_BUILTIN_COMPRESSPS128,
29766 IX86_BUILTIN_PCOMPRESSQ256,
29767 IX86_BUILTIN_PCOMPRESSQ128,
29768 IX86_BUILTIN_PCOMPRESSD256,
29769 IX86_BUILTIN_PCOMPRESSD128,
29770 IX86_BUILTIN_EXPANDPD256,
29771 IX86_BUILTIN_EXPANDPD128,
29772 IX86_BUILTIN_EXPANDPS256,
29773 IX86_BUILTIN_EXPANDPS128,
29774 IX86_BUILTIN_PEXPANDQ256,
29775 IX86_BUILTIN_PEXPANDQ128,
29776 IX86_BUILTIN_PEXPANDD256,
29777 IX86_BUILTIN_PEXPANDD128,
29778 IX86_BUILTIN_EXPANDPD256Z,
29779 IX86_BUILTIN_EXPANDPD128Z,
29780 IX86_BUILTIN_EXPANDPS256Z,
29781 IX86_BUILTIN_EXPANDPS128Z,
29782 IX86_BUILTIN_PEXPANDQ256Z,
29783 IX86_BUILTIN_PEXPANDQ128Z,
29784 IX86_BUILTIN_PEXPANDD256Z,
29785 IX86_BUILTIN_PEXPANDD128Z,
29786 IX86_BUILTIN_PMAXSD256_MASK,
29787 IX86_BUILTIN_PMINSD256_MASK,
29788 IX86_BUILTIN_PMAXUD256_MASK,
29789 IX86_BUILTIN_PMINUD256_MASK,
29790 IX86_BUILTIN_PMAXSD128_MASK,
29791 IX86_BUILTIN_PMINSD128_MASK,
29792 IX86_BUILTIN_PMAXUD128_MASK,
29793 IX86_BUILTIN_PMINUD128_MASK,
29794 IX86_BUILTIN_PMAXSQ256_MASK,
29795 IX86_BUILTIN_PMINSQ256_MASK,
29796 IX86_BUILTIN_PMAXUQ256_MASK,
29797 IX86_BUILTIN_PMINUQ256_MASK,
29798 IX86_BUILTIN_PMAXSQ128_MASK,
29799 IX86_BUILTIN_PMINSQ128_MASK,
29800 IX86_BUILTIN_PMAXUQ128_MASK,
29801 IX86_BUILTIN_PMINUQ128_MASK,
29802 IX86_BUILTIN_PMINSB256_MASK,
29803 IX86_BUILTIN_PMINUB256_MASK,
29804 IX86_BUILTIN_PMAXSB256_MASK,
29805 IX86_BUILTIN_PMAXUB256_MASK,
29806 IX86_BUILTIN_PMINSB128_MASK,
29807 IX86_BUILTIN_PMINUB128_MASK,
29808 IX86_BUILTIN_PMAXSB128_MASK,
29809 IX86_BUILTIN_PMAXUB128_MASK,
29810 IX86_BUILTIN_PMINSW256_MASK,
29811 IX86_BUILTIN_PMINUW256_MASK,
29812 IX86_BUILTIN_PMAXSW256_MASK,
29813 IX86_BUILTIN_PMAXUW256_MASK,
29814 IX86_BUILTIN_PMINSW128_MASK,
29815 IX86_BUILTIN_PMINUW128_MASK,
29816 IX86_BUILTIN_PMAXSW128_MASK,
29817 IX86_BUILTIN_PMAXUW128_MASK,
29818 IX86_BUILTIN_VPCONFLICTQ256,
29819 IX86_BUILTIN_VPCONFLICTD256,
29820 IX86_BUILTIN_VPCLZCNTQ256,
29821 IX86_BUILTIN_VPCLZCNTD256,
29822 IX86_BUILTIN_UNPCKHPD256_MASK,
29823 IX86_BUILTIN_UNPCKHPD128_MASK,
29824 IX86_BUILTIN_UNPCKHPS256_MASK,
29825 IX86_BUILTIN_UNPCKHPS128_MASK,
29826 IX86_BUILTIN_UNPCKLPD256_MASK,
29827 IX86_BUILTIN_UNPCKLPD128_MASK,
29828 IX86_BUILTIN_UNPCKLPS256_MASK,
29829 IX86_BUILTIN_VPCONFLICTQ128,
29830 IX86_BUILTIN_VPCONFLICTD128,
29831 IX86_BUILTIN_VPCLZCNTQ128,
29832 IX86_BUILTIN_VPCLZCNTD128,
29833 IX86_BUILTIN_UNPCKLPS128_MASK,
29834 IX86_BUILTIN_ALIGND256,
29835 IX86_BUILTIN_ALIGNQ256,
29836 IX86_BUILTIN_ALIGND128,
29837 IX86_BUILTIN_ALIGNQ128,
29838 IX86_BUILTIN_CVTPS2PH256_MASK,
29839 IX86_BUILTIN_CVTPS2PH_MASK,
29840 IX86_BUILTIN_CVTPH2PS_MASK,
29841 IX86_BUILTIN_CVTPH2PS256_MASK,
29842 IX86_BUILTIN_PUNPCKHDQ128_MASK,
29843 IX86_BUILTIN_PUNPCKHDQ256_MASK,
29844 IX86_BUILTIN_PUNPCKHQDQ128_MASK,
29845 IX86_BUILTIN_PUNPCKHQDQ256_MASK,
29846 IX86_BUILTIN_PUNPCKLDQ128_MASK,
29847 IX86_BUILTIN_PUNPCKLDQ256_MASK,
29848 IX86_BUILTIN_PUNPCKLQDQ128_MASK,
29849 IX86_BUILTIN_PUNPCKLQDQ256_MASK,
29850 IX86_BUILTIN_PUNPCKHBW128_MASK,
29851 IX86_BUILTIN_PUNPCKHBW256_MASK,
29852 IX86_BUILTIN_PUNPCKHWD128_MASK,
29853 IX86_BUILTIN_PUNPCKHWD256_MASK,
29854 IX86_BUILTIN_PUNPCKLBW128_MASK,
29855 IX86_BUILTIN_PUNPCKLBW256_MASK,
29856 IX86_BUILTIN_PUNPCKLWD128_MASK,
29857 IX86_BUILTIN_PUNPCKLWD256_MASK,
29858 IX86_BUILTIN_PSLLVV16HI,
29859 IX86_BUILTIN_PSLLVV8HI,
29860 IX86_BUILTIN_PACKSSDW256_MASK,
29861 IX86_BUILTIN_PACKSSDW128_MASK,
29862 IX86_BUILTIN_PACKUSDW256_MASK,
29863 IX86_BUILTIN_PACKUSDW128_MASK,
29864 IX86_BUILTIN_PAVGB256_MASK,
29865 IX86_BUILTIN_PAVGW256_MASK,
29866 IX86_BUILTIN_PAVGB128_MASK,
29867 IX86_BUILTIN_PAVGW128_MASK,
29868 IX86_BUILTIN_VPERMVARSF256_MASK,
29869 IX86_BUILTIN_VPERMVARDF256_MASK,
29870 IX86_BUILTIN_VPERMDF256_MASK,
29871 IX86_BUILTIN_PABSB256_MASK,
29872 IX86_BUILTIN_PABSB128_MASK,
29873 IX86_BUILTIN_PABSW256_MASK,
29874 IX86_BUILTIN_PABSW128_MASK,
29875 IX86_BUILTIN_VPERMILVARPD_MASK,
29876 IX86_BUILTIN_VPERMILVARPS_MASK,
29877 IX86_BUILTIN_VPERMILVARPD256_MASK,
29878 IX86_BUILTIN_VPERMILVARPS256_MASK,
29879 IX86_BUILTIN_VPERMILPD_MASK,
29880 IX86_BUILTIN_VPERMILPS_MASK,
29881 IX86_BUILTIN_VPERMILPD256_MASK,
29882 IX86_BUILTIN_VPERMILPS256_MASK,
29883 IX86_BUILTIN_BLENDMQ256,
29884 IX86_BUILTIN_BLENDMD256,
29885 IX86_BUILTIN_BLENDMPD256,
29886 IX86_BUILTIN_BLENDMPS256,
29887 IX86_BUILTIN_BLENDMQ128,
29888 IX86_BUILTIN_BLENDMD128,
29889 IX86_BUILTIN_BLENDMPD128,
29890 IX86_BUILTIN_BLENDMPS128,
29891 IX86_BUILTIN_BLENDMW256,
29892 IX86_BUILTIN_BLENDMB256,
29893 IX86_BUILTIN_BLENDMW128,
29894 IX86_BUILTIN_BLENDMB128,
29895 IX86_BUILTIN_PMULLD256_MASK,
29896 IX86_BUILTIN_PMULLD128_MASK,
29897 IX86_BUILTIN_PMULUDQ256_MASK,
29898 IX86_BUILTIN_PMULDQ256_MASK,
29899 IX86_BUILTIN_PMULDQ128_MASK,
29900 IX86_BUILTIN_PMULUDQ128_MASK,
29901 IX86_BUILTIN_CVTPD2PS256_MASK,
29902 IX86_BUILTIN_CVTPD2PS_MASK,
29903 IX86_BUILTIN_VPERMVARSI256_MASK,
29904 IX86_BUILTIN_VPERMVARDI256_MASK,
29905 IX86_BUILTIN_VPERMDI256_MASK,
29906 IX86_BUILTIN_CMPQ256,
29907 IX86_BUILTIN_CMPD256,
29908 IX86_BUILTIN_UCMPQ256,
29909 IX86_BUILTIN_UCMPD256,
29910 IX86_BUILTIN_CMPB256,
29911 IX86_BUILTIN_CMPW256,
29912 IX86_BUILTIN_UCMPB256,
29913 IX86_BUILTIN_UCMPW256,
29914 IX86_BUILTIN_CMPPD256_MASK,
29915 IX86_BUILTIN_CMPPS256_MASK,
29916 IX86_BUILTIN_CMPQ128,
29917 IX86_BUILTIN_CMPD128,
29918 IX86_BUILTIN_UCMPQ128,
29919 IX86_BUILTIN_UCMPD128,
29920 IX86_BUILTIN_CMPB128,
29921 IX86_BUILTIN_CMPW128,
29922 IX86_BUILTIN_UCMPB128,
29923 IX86_BUILTIN_UCMPW128,
29924 IX86_BUILTIN_CMPPD128_MASK,
29925 IX86_BUILTIN_CMPPS128_MASK,
29927 IX86_BUILTIN_GATHER3SIV8SF,
29928 IX86_BUILTIN_GATHER3SIV4SF,
29929 IX86_BUILTIN_GATHER3SIV4DF,
29930 IX86_BUILTIN_GATHER3SIV2DF,
29931 IX86_BUILTIN_GATHER3DIV8SF,
29932 IX86_BUILTIN_GATHER3DIV4SF,
29933 IX86_BUILTIN_GATHER3DIV4DF,
29934 IX86_BUILTIN_GATHER3DIV2DF,
29935 IX86_BUILTIN_GATHER3SIV8SI,
29936 IX86_BUILTIN_GATHER3SIV4SI,
29937 IX86_BUILTIN_GATHER3SIV4DI,
29938 IX86_BUILTIN_GATHER3SIV2DI,
29939 IX86_BUILTIN_GATHER3DIV8SI,
29940 IX86_BUILTIN_GATHER3DIV4SI,
29941 IX86_BUILTIN_GATHER3DIV4DI,
29942 IX86_BUILTIN_GATHER3DIV2DI,
29943 IX86_BUILTIN_SCATTERSIV8SF,
29944 IX86_BUILTIN_SCATTERSIV4SF,
29945 IX86_BUILTIN_SCATTERSIV4DF,
29946 IX86_BUILTIN_SCATTERSIV2DF,
29947 IX86_BUILTIN_SCATTERDIV8SF,
29948 IX86_BUILTIN_SCATTERDIV4SF,
29949 IX86_BUILTIN_SCATTERDIV4DF,
29950 IX86_BUILTIN_SCATTERDIV2DF,
29951 IX86_BUILTIN_SCATTERSIV8SI,
29952 IX86_BUILTIN_SCATTERSIV4SI,
29953 IX86_BUILTIN_SCATTERSIV4DI,
29954 IX86_BUILTIN_SCATTERSIV2DI,
29955 IX86_BUILTIN_SCATTERDIV8SI,
29956 IX86_BUILTIN_SCATTERDIV4SI,
29957 IX86_BUILTIN_SCATTERDIV4DI,
29958 IX86_BUILTIN_SCATTERDIV2DI,
29960 /* AVX512DQ. */
29961 IX86_BUILTIN_RANGESD128,
29962 IX86_BUILTIN_RANGESS128,
29963 IX86_BUILTIN_KUNPCKWD,
29964 IX86_BUILTIN_KUNPCKDQ,
29965 IX86_BUILTIN_BROADCASTF32x2_512,
29966 IX86_BUILTIN_BROADCASTI32x2_512,
29967 IX86_BUILTIN_BROADCASTF64X2_512,
29968 IX86_BUILTIN_BROADCASTI64X2_512,
29969 IX86_BUILTIN_BROADCASTF32X8_512,
29970 IX86_BUILTIN_BROADCASTI32X8_512,
29971 IX86_BUILTIN_EXTRACTF64X2_512,
29972 IX86_BUILTIN_EXTRACTF32X8,
29973 IX86_BUILTIN_EXTRACTI64X2_512,
29974 IX86_BUILTIN_EXTRACTI32X8,
29975 IX86_BUILTIN_REDUCEPD512_MASK,
29976 IX86_BUILTIN_REDUCEPS512_MASK,
29977 IX86_BUILTIN_PMULLQ512,
29978 IX86_BUILTIN_XORPD512,
29979 IX86_BUILTIN_XORPS512,
29980 IX86_BUILTIN_ORPD512,
29981 IX86_BUILTIN_ORPS512,
29982 IX86_BUILTIN_ANDPD512,
29983 IX86_BUILTIN_ANDPS512,
29984 IX86_BUILTIN_ANDNPD512,
29985 IX86_BUILTIN_ANDNPS512,
29986 IX86_BUILTIN_INSERTF32X8,
29987 IX86_BUILTIN_INSERTI32X8,
29988 IX86_BUILTIN_INSERTF64X2_512,
29989 IX86_BUILTIN_INSERTI64X2_512,
29990 IX86_BUILTIN_FPCLASSPD512,
29991 IX86_BUILTIN_FPCLASSPS512,
29992 IX86_BUILTIN_CVTD2MASK512,
29993 IX86_BUILTIN_CVTQ2MASK512,
29994 IX86_BUILTIN_CVTMASK2D512,
29995 IX86_BUILTIN_CVTMASK2Q512,
29996 IX86_BUILTIN_CVTPD2QQ512,
29997 IX86_BUILTIN_CVTPS2QQ512,
29998 IX86_BUILTIN_CVTPD2UQQ512,
29999 IX86_BUILTIN_CVTPS2UQQ512,
30000 IX86_BUILTIN_CVTQQ2PS512,
30001 IX86_BUILTIN_CVTUQQ2PS512,
30002 IX86_BUILTIN_CVTQQ2PD512,
30003 IX86_BUILTIN_CVTUQQ2PD512,
30004 IX86_BUILTIN_CVTTPS2QQ512,
30005 IX86_BUILTIN_CVTTPS2UQQ512,
30006 IX86_BUILTIN_CVTTPD2QQ512,
30007 IX86_BUILTIN_CVTTPD2UQQ512,
30008 IX86_BUILTIN_RANGEPS512,
30009 IX86_BUILTIN_RANGEPD512,
30011 /* AVX512BW. */
30012 IX86_BUILTIN_PACKUSDW512,
30013 IX86_BUILTIN_PACKSSDW512,
30014 IX86_BUILTIN_LOADDQUHI512_MASK,
30015 IX86_BUILTIN_LOADDQUQI512_MASK,
30016 IX86_BUILTIN_PSLLDQ512,
30017 IX86_BUILTIN_PSRLDQ512,
30018 IX86_BUILTIN_STOREDQUHI512_MASK,
30019 IX86_BUILTIN_STOREDQUQI512_MASK,
30020 IX86_BUILTIN_PALIGNR512,
30021 IX86_BUILTIN_PALIGNR512_MASK,
30022 IX86_BUILTIN_MOVDQUHI512_MASK,
30023 IX86_BUILTIN_MOVDQUQI512_MASK,
30024 IX86_BUILTIN_PSADBW512,
30025 IX86_BUILTIN_DBPSADBW512,
30026 IX86_BUILTIN_PBROADCASTB512,
30027 IX86_BUILTIN_PBROADCASTB512_GPR,
30028 IX86_BUILTIN_PBROADCASTW512,
30029 IX86_BUILTIN_PBROADCASTW512_GPR,
30030 IX86_BUILTIN_PMOVSXBW512_MASK,
30031 IX86_BUILTIN_PMOVZXBW512_MASK,
30032 IX86_BUILTIN_VPERMVARHI512_MASK,
30033 IX86_BUILTIN_VPERMT2VARHI512,
30034 IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
30035 IX86_BUILTIN_VPERMI2VARHI512,
30036 IX86_BUILTIN_PAVGB512,
30037 IX86_BUILTIN_PAVGW512,
30038 IX86_BUILTIN_PADDB512,
30039 IX86_BUILTIN_PSUBB512,
30040 IX86_BUILTIN_PSUBSB512,
30041 IX86_BUILTIN_PADDSB512,
30042 IX86_BUILTIN_PSUBUSB512,
30043 IX86_BUILTIN_PADDUSB512,
30044 IX86_BUILTIN_PSUBW512,
30045 IX86_BUILTIN_PADDW512,
30046 IX86_BUILTIN_PSUBSW512,
30047 IX86_BUILTIN_PADDSW512,
30048 IX86_BUILTIN_PSUBUSW512,
30049 IX86_BUILTIN_PADDUSW512,
30050 IX86_BUILTIN_PMAXUW512,
30051 IX86_BUILTIN_PMAXSW512,
30052 IX86_BUILTIN_PMINUW512,
30053 IX86_BUILTIN_PMINSW512,
30054 IX86_BUILTIN_PMAXUB512,
30055 IX86_BUILTIN_PMAXSB512,
30056 IX86_BUILTIN_PMINUB512,
30057 IX86_BUILTIN_PMINSB512,
30058 IX86_BUILTIN_PMOVWB512,
30059 IX86_BUILTIN_PMOVSWB512,
30060 IX86_BUILTIN_PMOVUSWB512,
30061 IX86_BUILTIN_PMULHRSW512_MASK,
30062 IX86_BUILTIN_PMULHUW512_MASK,
30063 IX86_BUILTIN_PMULHW512_MASK,
30064 IX86_BUILTIN_PMULLW512_MASK,
30065 IX86_BUILTIN_PSLLWI512_MASK,
30066 IX86_BUILTIN_PSLLW512_MASK,
30067 IX86_BUILTIN_PACKSSWB512,
30068 IX86_BUILTIN_PACKUSWB512,
30069 IX86_BUILTIN_PSRAVV32HI,
30070 IX86_BUILTIN_PMADDUBSW512_MASK,
30071 IX86_BUILTIN_PMADDWD512_MASK,
30072 IX86_BUILTIN_PSRLVV32HI,
30073 IX86_BUILTIN_PUNPCKHBW512,
30074 IX86_BUILTIN_PUNPCKHWD512,
30075 IX86_BUILTIN_PUNPCKLBW512,
30076 IX86_BUILTIN_PUNPCKLWD512,
30077 IX86_BUILTIN_PSHUFB512,
30078 IX86_BUILTIN_PSHUFHW512,
30079 IX86_BUILTIN_PSHUFLW512,
30080 IX86_BUILTIN_PSRAWI512,
30081 IX86_BUILTIN_PSRAW512,
30082 IX86_BUILTIN_PSRLWI512,
30083 IX86_BUILTIN_PSRLW512,
30084 IX86_BUILTIN_CVTB2MASK512,
30085 IX86_BUILTIN_CVTW2MASK512,
30086 IX86_BUILTIN_CVTMASK2B512,
30087 IX86_BUILTIN_CVTMASK2W512,
30088 IX86_BUILTIN_PCMPEQB512_MASK,
30089 IX86_BUILTIN_PCMPEQW512_MASK,
30090 IX86_BUILTIN_PCMPGTB512_MASK,
30091 IX86_BUILTIN_PCMPGTW512_MASK,
30092 IX86_BUILTIN_PTESTMB512,
30093 IX86_BUILTIN_PTESTMW512,
30094 IX86_BUILTIN_PTESTNMB512,
30095 IX86_BUILTIN_PTESTNMW512,
30096 IX86_BUILTIN_PSLLVV32HI,
30097 IX86_BUILTIN_PABSB512,
30098 IX86_BUILTIN_PABSW512,
30099 IX86_BUILTIN_BLENDMW512,
30100 IX86_BUILTIN_BLENDMB512,
30101 IX86_BUILTIN_CMPB512,
30102 IX86_BUILTIN_CMPW512,
30103 IX86_BUILTIN_UCMPB512,
30104 IX86_BUILTIN_UCMPW512,
30106 /* Alternate 4 and 8 element gather/scatter for the vectorizer
30107 where all operands are 32-byte or 64-byte wide respectively. */
30108 IX86_BUILTIN_GATHERALTSIV4DF,
30109 IX86_BUILTIN_GATHERALTDIV8SF,
30110 IX86_BUILTIN_GATHERALTSIV4DI,
30111 IX86_BUILTIN_GATHERALTDIV8SI,
30112 IX86_BUILTIN_GATHER3ALTDIV16SF,
30113 IX86_BUILTIN_GATHER3ALTDIV16SI,
30114 IX86_BUILTIN_GATHER3ALTSIV4DF,
30115 IX86_BUILTIN_GATHER3ALTDIV8SF,
30116 IX86_BUILTIN_GATHER3ALTSIV4DI,
30117 IX86_BUILTIN_GATHER3ALTDIV8SI,
30118 IX86_BUILTIN_GATHER3ALTSIV8DF,
30119 IX86_BUILTIN_GATHER3ALTSIV8DI,
30120 IX86_BUILTIN_GATHER3DIV16SF,
30121 IX86_BUILTIN_GATHER3DIV16SI,
30122 IX86_BUILTIN_GATHER3DIV8DF,
30123 IX86_BUILTIN_GATHER3DIV8DI,
30124 IX86_BUILTIN_GATHER3SIV16SF,
30125 IX86_BUILTIN_GATHER3SIV16SI,
30126 IX86_BUILTIN_GATHER3SIV8DF,
30127 IX86_BUILTIN_GATHER3SIV8DI,
30128 IX86_BUILTIN_SCATTERDIV16SF,
30129 IX86_BUILTIN_SCATTERDIV16SI,
30130 IX86_BUILTIN_SCATTERDIV8DF,
30131 IX86_BUILTIN_SCATTERDIV8DI,
30132 IX86_BUILTIN_SCATTERSIV16SF,
30133 IX86_BUILTIN_SCATTERSIV16SI,
30134 IX86_BUILTIN_SCATTERSIV8DF,
30135 IX86_BUILTIN_SCATTERSIV8DI,
30137 /* AVX512PF */
30138 IX86_BUILTIN_GATHERPFQPD,
30139 IX86_BUILTIN_GATHERPFDPS,
30140 IX86_BUILTIN_GATHERPFDPD,
30141 IX86_BUILTIN_GATHERPFQPS,
30142 IX86_BUILTIN_SCATTERPFDPD,
30143 IX86_BUILTIN_SCATTERPFDPS,
30144 IX86_BUILTIN_SCATTERPFQPD,
30145 IX86_BUILTIN_SCATTERPFQPS,
30147 /* AVX-512ER */
30148 IX86_BUILTIN_EXP2PD_MASK,
30149 IX86_BUILTIN_EXP2PS_MASK,
30150 IX86_BUILTIN_EXP2PS,
30151 IX86_BUILTIN_RCP28PD,
30152 IX86_BUILTIN_RCP28PS,
30153 IX86_BUILTIN_RCP28SD,
30154 IX86_BUILTIN_RCP28SS,
30155 IX86_BUILTIN_RSQRT28PD,
30156 IX86_BUILTIN_RSQRT28PS,
30157 IX86_BUILTIN_RSQRT28SD,
30158 IX86_BUILTIN_RSQRT28SS,
30160 /* AVX-512IFMA */
30161 IX86_BUILTIN_VPMADD52LUQ512,
30162 IX86_BUILTIN_VPMADD52HUQ512,
30163 IX86_BUILTIN_VPMADD52LUQ256,
30164 IX86_BUILTIN_VPMADD52HUQ256,
30165 IX86_BUILTIN_VPMADD52LUQ128,
30166 IX86_BUILTIN_VPMADD52HUQ128,
30167 IX86_BUILTIN_VPMADD52LUQ512_MASKZ,
30168 IX86_BUILTIN_VPMADD52HUQ512_MASKZ,
30169 IX86_BUILTIN_VPMADD52LUQ256_MASKZ,
30170 IX86_BUILTIN_VPMADD52HUQ256_MASKZ,
30171 IX86_BUILTIN_VPMADD52LUQ128_MASKZ,
30172 IX86_BUILTIN_VPMADD52HUQ128_MASKZ,
30174 /* AVX-512VBMI */
30175 IX86_BUILTIN_VPMULTISHIFTQB512,
30176 IX86_BUILTIN_VPMULTISHIFTQB256,
30177 IX86_BUILTIN_VPMULTISHIFTQB128,
30178 IX86_BUILTIN_VPERMVARQI512_MASK,
30179 IX86_BUILTIN_VPERMT2VARQI512,
30180 IX86_BUILTIN_VPERMT2VARQI512_MASKZ,
30181 IX86_BUILTIN_VPERMI2VARQI512,
30182 IX86_BUILTIN_VPERMVARQI256_MASK,
30183 IX86_BUILTIN_VPERMVARQI128_MASK,
30184 IX86_BUILTIN_VPERMT2VARQI256,
30185 IX86_BUILTIN_VPERMT2VARQI256_MASKZ,
30186 IX86_BUILTIN_VPERMT2VARQI128,
30187 IX86_BUILTIN_VPERMT2VARQI128_MASKZ,
30188 IX86_BUILTIN_VPERMI2VARQI256,
30189 IX86_BUILTIN_VPERMI2VARQI128,
30191 /* SHA builtins. */
30192 IX86_BUILTIN_SHA1MSG1,
30193 IX86_BUILTIN_SHA1MSG2,
30194 IX86_BUILTIN_SHA1NEXTE,
30195 IX86_BUILTIN_SHA1RNDS4,
30196 IX86_BUILTIN_SHA256MSG1,
30197 IX86_BUILTIN_SHA256MSG2,
30198 IX86_BUILTIN_SHA256RNDS2,
30200 /* CLWB instructions. */
30201 IX86_BUILTIN_CLWB,
30203 /* PCOMMIT instructions. */
30204 IX86_BUILTIN_PCOMMIT,
30206 /* CLFLUSHOPT instructions. */
30207 IX86_BUILTIN_CLFLUSHOPT,
30209 /* TFmode support builtins. */
30210 IX86_BUILTIN_INFQ,
30211 IX86_BUILTIN_HUGE_VALQ,
30212 IX86_BUILTIN_FABSQ,
30213 IX86_BUILTIN_COPYSIGNQ,
30215 /* Vectorizer support builtins. */
30216 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
30217 IX86_BUILTIN_CPYSGNPS,
30218 IX86_BUILTIN_CPYSGNPD,
30219 IX86_BUILTIN_CPYSGNPS256,
30220 IX86_BUILTIN_CPYSGNPS512,
30221 IX86_BUILTIN_CPYSGNPD256,
30222 IX86_BUILTIN_CPYSGNPD512,
30223 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
30224 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
30227 /* FMA4 instructions. */
30228 IX86_BUILTIN_VFMADDSS,
30229 IX86_BUILTIN_VFMADDSD,
30230 IX86_BUILTIN_VFMADDPS,
30231 IX86_BUILTIN_VFMADDPD,
30232 IX86_BUILTIN_VFMADDPS256,
30233 IX86_BUILTIN_VFMADDPD256,
30234 IX86_BUILTIN_VFMADDSUBPS,
30235 IX86_BUILTIN_VFMADDSUBPD,
30236 IX86_BUILTIN_VFMADDSUBPS256,
30237 IX86_BUILTIN_VFMADDSUBPD256,
30239 /* FMA3 instructions. */
30240 IX86_BUILTIN_VFMADDSS3,
30241 IX86_BUILTIN_VFMADDSD3,
30243 /* XOP instructions. */
30244 IX86_BUILTIN_VPCMOV,
30245 IX86_BUILTIN_VPCMOV_V2DI,
30246 IX86_BUILTIN_VPCMOV_V4SI,
30247 IX86_BUILTIN_VPCMOV_V8HI,
30248 IX86_BUILTIN_VPCMOV_V16QI,
30249 IX86_BUILTIN_VPCMOV_V4SF,
30250 IX86_BUILTIN_VPCMOV_V2DF,
30251 IX86_BUILTIN_VPCMOV256,
30252 IX86_BUILTIN_VPCMOV_V4DI256,
30253 IX86_BUILTIN_VPCMOV_V8SI256,
30254 IX86_BUILTIN_VPCMOV_V16HI256,
30255 IX86_BUILTIN_VPCMOV_V32QI256,
30256 IX86_BUILTIN_VPCMOV_V8SF256,
30257 IX86_BUILTIN_VPCMOV_V4DF256,
30259 IX86_BUILTIN_VPPERM,
30261 IX86_BUILTIN_VPMACSSWW,
30262 IX86_BUILTIN_VPMACSWW,
30263 IX86_BUILTIN_VPMACSSWD,
30264 IX86_BUILTIN_VPMACSWD,
30265 IX86_BUILTIN_VPMACSSDD,
30266 IX86_BUILTIN_VPMACSDD,
30267 IX86_BUILTIN_VPMACSSDQL,
30268 IX86_BUILTIN_VPMACSSDQH,
30269 IX86_BUILTIN_VPMACSDQL,
30270 IX86_BUILTIN_VPMACSDQH,
30271 IX86_BUILTIN_VPMADCSSWD,
30272 IX86_BUILTIN_VPMADCSWD,
30274 IX86_BUILTIN_VPHADDBW,
30275 IX86_BUILTIN_VPHADDBD,
30276 IX86_BUILTIN_VPHADDBQ,
30277 IX86_BUILTIN_VPHADDWD,
30278 IX86_BUILTIN_VPHADDWQ,
30279 IX86_BUILTIN_VPHADDDQ,
30280 IX86_BUILTIN_VPHADDUBW,
30281 IX86_BUILTIN_VPHADDUBD,
30282 IX86_BUILTIN_VPHADDUBQ,
30283 IX86_BUILTIN_VPHADDUWD,
30284 IX86_BUILTIN_VPHADDUWQ,
30285 IX86_BUILTIN_VPHADDUDQ,
30286 IX86_BUILTIN_VPHSUBBW,
30287 IX86_BUILTIN_VPHSUBWD,
30288 IX86_BUILTIN_VPHSUBDQ,
30290 IX86_BUILTIN_VPROTB,
30291 IX86_BUILTIN_VPROTW,
30292 IX86_BUILTIN_VPROTD,
30293 IX86_BUILTIN_VPROTQ,
30294 IX86_BUILTIN_VPROTB_IMM,
30295 IX86_BUILTIN_VPROTW_IMM,
30296 IX86_BUILTIN_VPROTD_IMM,
30297 IX86_BUILTIN_VPROTQ_IMM,
30299 IX86_BUILTIN_VPSHLB,
30300 IX86_BUILTIN_VPSHLW,
30301 IX86_BUILTIN_VPSHLD,
30302 IX86_BUILTIN_VPSHLQ,
30303 IX86_BUILTIN_VPSHAB,
30304 IX86_BUILTIN_VPSHAW,
30305 IX86_BUILTIN_VPSHAD,
30306 IX86_BUILTIN_VPSHAQ,
30308 IX86_BUILTIN_VFRCZSS,
30309 IX86_BUILTIN_VFRCZSD,
30310 IX86_BUILTIN_VFRCZPS,
30311 IX86_BUILTIN_VFRCZPD,
30312 IX86_BUILTIN_VFRCZPS256,
30313 IX86_BUILTIN_VFRCZPD256,
30315 IX86_BUILTIN_VPCOMEQUB,
30316 IX86_BUILTIN_VPCOMNEUB,
30317 IX86_BUILTIN_VPCOMLTUB,
30318 IX86_BUILTIN_VPCOMLEUB,
30319 IX86_BUILTIN_VPCOMGTUB,
30320 IX86_BUILTIN_VPCOMGEUB,
30321 IX86_BUILTIN_VPCOMFALSEUB,
30322 IX86_BUILTIN_VPCOMTRUEUB,
30324 IX86_BUILTIN_VPCOMEQUW,
30325 IX86_BUILTIN_VPCOMNEUW,
30326 IX86_BUILTIN_VPCOMLTUW,
30327 IX86_BUILTIN_VPCOMLEUW,
30328 IX86_BUILTIN_VPCOMGTUW,
30329 IX86_BUILTIN_VPCOMGEUW,
30330 IX86_BUILTIN_VPCOMFALSEUW,
30331 IX86_BUILTIN_VPCOMTRUEUW,
30333 IX86_BUILTIN_VPCOMEQUD,
30334 IX86_BUILTIN_VPCOMNEUD,
30335 IX86_BUILTIN_VPCOMLTUD,
30336 IX86_BUILTIN_VPCOMLEUD,
30337 IX86_BUILTIN_VPCOMGTUD,
30338 IX86_BUILTIN_VPCOMGEUD,
30339 IX86_BUILTIN_VPCOMFALSEUD,
30340 IX86_BUILTIN_VPCOMTRUEUD,
30342 IX86_BUILTIN_VPCOMEQUQ,
30343 IX86_BUILTIN_VPCOMNEUQ,
30344 IX86_BUILTIN_VPCOMLTUQ,
30345 IX86_BUILTIN_VPCOMLEUQ,
30346 IX86_BUILTIN_VPCOMGTUQ,
30347 IX86_BUILTIN_VPCOMGEUQ,
30348 IX86_BUILTIN_VPCOMFALSEUQ,
30349 IX86_BUILTIN_VPCOMTRUEUQ,
30351 IX86_BUILTIN_VPCOMEQB,
30352 IX86_BUILTIN_VPCOMNEB,
30353 IX86_BUILTIN_VPCOMLTB,
30354 IX86_BUILTIN_VPCOMLEB,
30355 IX86_BUILTIN_VPCOMGTB,
30356 IX86_BUILTIN_VPCOMGEB,
30357 IX86_BUILTIN_VPCOMFALSEB,
30358 IX86_BUILTIN_VPCOMTRUEB,
30360 IX86_BUILTIN_VPCOMEQW,
30361 IX86_BUILTIN_VPCOMNEW,
30362 IX86_BUILTIN_VPCOMLTW,
30363 IX86_BUILTIN_VPCOMLEW,
30364 IX86_BUILTIN_VPCOMGTW,
30365 IX86_BUILTIN_VPCOMGEW,
30366 IX86_BUILTIN_VPCOMFALSEW,
30367 IX86_BUILTIN_VPCOMTRUEW,
30369 IX86_BUILTIN_VPCOMEQD,
30370 IX86_BUILTIN_VPCOMNED,
30371 IX86_BUILTIN_VPCOMLTD,
30372 IX86_BUILTIN_VPCOMLED,
30373 IX86_BUILTIN_VPCOMGTD,
30374 IX86_BUILTIN_VPCOMGED,
30375 IX86_BUILTIN_VPCOMFALSED,
30376 IX86_BUILTIN_VPCOMTRUED,
30378 IX86_BUILTIN_VPCOMEQQ,
30379 IX86_BUILTIN_VPCOMNEQ,
30380 IX86_BUILTIN_VPCOMLTQ,
30381 IX86_BUILTIN_VPCOMLEQ,
30382 IX86_BUILTIN_VPCOMGTQ,
30383 IX86_BUILTIN_VPCOMGEQ,
30384 IX86_BUILTIN_VPCOMFALSEQ,
30385 IX86_BUILTIN_VPCOMTRUEQ,
30387 /* LWP instructions. */
30388 IX86_BUILTIN_LLWPCB,
30389 IX86_BUILTIN_SLWPCB,
30390 IX86_BUILTIN_LWPVAL32,
30391 IX86_BUILTIN_LWPVAL64,
30392 IX86_BUILTIN_LWPINS32,
30393 IX86_BUILTIN_LWPINS64,
30395 IX86_BUILTIN_CLZS,
30397 /* RTM */
30398 IX86_BUILTIN_XBEGIN,
30399 IX86_BUILTIN_XEND,
30400 IX86_BUILTIN_XABORT,
30401 IX86_BUILTIN_XTEST,
30403 /* MPX */
30404 IX86_BUILTIN_BNDMK,
30405 IX86_BUILTIN_BNDSTX,
30406 IX86_BUILTIN_BNDLDX,
30407 IX86_BUILTIN_BNDCL,
30408 IX86_BUILTIN_BNDCU,
30409 IX86_BUILTIN_BNDRET,
30410 IX86_BUILTIN_BNDNARROW,
30411 IX86_BUILTIN_BNDINT,
30412 IX86_BUILTIN_SIZEOF,
30413 IX86_BUILTIN_BNDLOWER,
30414 IX86_BUILTIN_BNDUPPER,
30416 /* BMI instructions. */
30417 IX86_BUILTIN_BEXTR32,
30418 IX86_BUILTIN_BEXTR64,
30419 IX86_BUILTIN_CTZS,
30421 /* TBM instructions. */
30422 IX86_BUILTIN_BEXTRI32,
30423 IX86_BUILTIN_BEXTRI64,
30425 /* BMI2 instructions. */
30426 IX86_BUILTIN_BZHI32,
30427 IX86_BUILTIN_BZHI64,
30428 IX86_BUILTIN_PDEP32,
30429 IX86_BUILTIN_PDEP64,
30430 IX86_BUILTIN_PEXT32,
30431 IX86_BUILTIN_PEXT64,
30433 /* ADX instructions. */
30434 IX86_BUILTIN_ADDCARRYX32,
30435 IX86_BUILTIN_ADDCARRYX64,
30437 /* SBB instructions. */
30438 IX86_BUILTIN_SBB32,
30439 IX86_BUILTIN_SBB64,
30441 /* FSGSBASE instructions. */
30442 IX86_BUILTIN_RDFSBASE32,
30443 IX86_BUILTIN_RDFSBASE64,
30444 IX86_BUILTIN_RDGSBASE32,
30445 IX86_BUILTIN_RDGSBASE64,
30446 IX86_BUILTIN_WRFSBASE32,
30447 IX86_BUILTIN_WRFSBASE64,
30448 IX86_BUILTIN_WRGSBASE32,
30449 IX86_BUILTIN_WRGSBASE64,
30451 /* RDRND instructions. */
30452 IX86_BUILTIN_RDRAND16_STEP,
30453 IX86_BUILTIN_RDRAND32_STEP,
30454 IX86_BUILTIN_RDRAND64_STEP,
30456 /* RDSEED instructions. */
30457 IX86_BUILTIN_RDSEED16_STEP,
30458 IX86_BUILTIN_RDSEED32_STEP,
30459 IX86_BUILTIN_RDSEED64_STEP,
30461 /* F16C instructions. */
30462 IX86_BUILTIN_CVTPH2PS,
30463 IX86_BUILTIN_CVTPH2PS256,
30464 IX86_BUILTIN_CVTPS2PH,
30465 IX86_BUILTIN_CVTPS2PH256,
30467 /* CFString built-in for darwin */
30468 IX86_BUILTIN_CFSTRING,
30470 /* Builtins to get CPU type and supported features. */
30471 IX86_BUILTIN_CPU_INIT,
30472 IX86_BUILTIN_CPU_IS,
30473 IX86_BUILTIN_CPU_SUPPORTS,
30475 /* Read/write FLAGS register built-ins. */
30476 IX86_BUILTIN_READ_FLAGS,
30477 IX86_BUILTIN_WRITE_FLAGS,
30479 IX86_BUILTIN_MAX
30480 };
30482 /* Table for the ix86 builtin decls. */
30485 /* Table of all of the builtin functions that are possible with different ISA's
30486 but are waiting to be built until a function is declared to use that
30487 ISA. */
30496 };
30500 /* Bits that can still enable any inclusion of a builtin. */
30503 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
30504 of which isa_flags to use in the ix86_builtins_isa array. Stores the
30505 function decl in the ix86_builtins array. Returns the function decl or
30506 NULL_TREE, if the builtin was not added.
30508 If the front end has a special hook for builtin functions, delay adding
30509 builtin functions that aren't in the current ISA until the ISA is changed
30510 with function specific optimization. Doing so, can save about 300K for the
30511 default compiler. When the builtin is expanded, check at that time whether
30512 it is valid.
30514 If the front end doesn't have a special hook, record all builtins, even if
30515 it isn't an instruction set in the current ISA in case the user uses
30516 function specific options for a different ISA, so that we don't get scope
30517 errors if a builtin is added in the middle of a function scope. */
30523 {
30527 {
30536 {
30542 }
30543 else
30544 {
30545 /* Just a MASK where set_and_not_built_p == true can potentially
30546 include a builtin. */
30555 }
30556 }
30559 }
30561 /* Like def_builtin, but also marks the function decl "const". */
30566 {
30570 else
30574 }
30576 /* Add any new builtin functions for a given ISA that may not have been
30577 declared. This saves a bit of space compared to adding all of the
30578 declarations to the tree, even if we didn't use them. */
30580 static void
30582 {
30586 /* Bits in ISA value can be removed from potential isa values. */
30594 {
30597 {
30600 /* Don't define the builtin again. */
30606 NULL_TREE);
30613 NULL_TREE);
30616 }
30617 }
30620 }
30622 /* Bits for builtin_description.flag. */
30624 /* Set when we don't support the comparison natively, and should
30625 swap_comparison in order to support it. */
30626 #define BUILTIN_DESC_SWAP_OPERANDS 1
30628 struct builtin_description
30629 {
30636 };
30639 {
30640 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
30641 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
30642 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
30643 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
30644 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
30645 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
30646 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
30647 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
30648 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
30649 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
30650 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
30651 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
30652 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
30653 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
30654 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
30655 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
30656 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
30657 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
30658 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
30659 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
30660 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
30661 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
30662 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
30663 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
30664 };
30667 {
30668 /* SSE4.2 */
30669 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
30670 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
30671 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
30672 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
30673 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
30674 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
30675 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
30676 };
30679 {
30680 /* SSE4.2 */
30681 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
30682 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
30683 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
30684 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
30685 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
30686 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
30687 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
30688 };
30690 /* Special builtins with variable number of arguments. */
30692 {
30693 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
30694 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
30695 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
30697 /* 80387 (for use internally for atomic compound assignment). */
30698 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
30699 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
30700 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) USHORT_FTYPE_VOID },
30701 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
30703 /* MMX */
30704 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30706 /* 3DNow! */
30707 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30709 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
30710 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
30711 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
30712 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30713 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30714 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30715 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30716 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30717 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30719 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30720 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30721 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30722 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30723 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30724 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30725 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30726 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30728 /* SSE */
30729 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30730 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30731 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30733 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30734 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30735 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30736 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30738 /* SSE or 3DNow!A */
30739 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30740 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
30742 /* SSE2 */
30743 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30744 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30745 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30746 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
30747 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30748 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
30749 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
30750 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
30751 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
30752 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30754 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30755 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30757 /* SSE3 */
30758 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30760 /* SSE4.1 */
30761 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
30763 /* SSE4A */
30764 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30765 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30767 /* AVX */
30768 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
30769 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
30771 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30772 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30773 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30774 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
30775 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
30777 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30778 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30779 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30780 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30781 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30782 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
30783 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30785 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
30786 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30787 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30789 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
30790 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
30791 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
30792 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
30793 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
30794 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
30795 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
30796 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
30798 /* AVX2 */
30799 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
30800 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
30801 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
30802 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
30803 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
30804 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
30805 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
30806 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
30807 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
30809 /* AVX512F */
30810 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30811 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30812 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30813 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30814 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30815 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30816 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30817 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30818 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30819 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30820 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30821 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30822 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30823 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30824 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30825 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30826 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30827 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30828 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30829 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30830 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
30831 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
30832 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
30833 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
30834 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30835 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30836 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30837 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30838 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30839 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30840 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30841 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30842 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30843 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30844 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30845 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30846 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30847 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30848 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30849 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30850 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30851 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30852 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30853 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30854 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30855 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30856 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30858 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
30859 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
30860 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
30861 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
30862 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
30863 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
30865 /* FSGSBASE */
30866 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30867 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30868 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30869 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30870 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30871 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30872 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30873 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30875 /* RTM */
30876 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30877 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
30878 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
30880 /* AVX512BW */
30881 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_SI },
30882 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_DI },
30883 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_SI },
30884 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_DI },
30886 /* AVX512VL */
30887 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_HI },
30888 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_QI },
30889 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_SI },
30890 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_HI },
30891 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30892 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30893 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30894 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30895 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30896 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30897 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30898 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30899 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30900 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30901 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30902 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30903 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30904 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30905 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30906 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30907 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30908 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30909 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30910 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30911 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30912 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30913 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30914 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30915 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30916 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30917 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30918 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30919 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30920 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30921 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30922 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30923 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_HI },
30924 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_QI },
30925 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_SI },
30926 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_HI },
30927 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30928 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30929 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30930 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30931 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30932 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30933 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30934 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30935 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30936 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30937 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30938 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30939 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30940 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30941 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30942 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30943 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30944 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30945 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30946 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30947 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30948 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30949 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30950 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30951 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30952 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30953 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30954 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30955 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30956 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30957 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30958 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30959 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30960 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30961 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30962 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30963 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30964 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30965 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30966 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30967 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30968 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30969 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30970 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30971 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30972 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30973 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30974 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30975 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30976 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30977 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30978 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30979 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30980 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30982 /* PCOMMIT. */
30983 { OPTION_MASK_ISA_PCOMMIT, CODE_FOR_pcommit, "__builtin_ia32_pcommit", IX86_BUILTIN_PCOMMIT, UNKNOWN, (int) VOID_FTYPE_VOID },
30984 };
30986 /* Builtins with variable number of arguments. */
30988 {
30989 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
30990 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
30991 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
30992 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
30993 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
30994 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
30995 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
30997 /* MMX */
30998 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30999 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31000 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31001 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31002 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31003 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31005 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31006 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31007 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31008 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31009 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31010 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31011 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31012 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31014 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31015 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31017 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31018 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31019 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31020 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31022 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31023 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31024 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31025 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31026 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31027 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31029 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31030 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31031 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31032 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31033 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
31034 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
31036 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31037 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
31038 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31040 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
31042 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31043 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31044 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31045 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31046 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31047 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31049 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31050 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31051 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31052 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31053 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31054 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31056 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31057 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31058 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31059 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31061 /* 3DNow! */
31062 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31063 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31064 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31065 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31067 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31068 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31069 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31070 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31071 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31072 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31073 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31074 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31075 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31076 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31077 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31078 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31079 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31080 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31081 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31083 /* 3DNow!A */
31084 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31085 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31086 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31087 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31088 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31089 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31091 /* SSE */
31092 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
31093 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31094 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31095 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31096 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31097 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31098 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31099 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31100 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31101 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31102 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31103 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31105 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31107 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31108 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31109 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31110 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31111 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31112 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31113 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31114 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31116 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31117 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31118 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31119 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31120 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31121 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31122 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31123 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31124 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31125 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31126 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
31127 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31128 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31129 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31130 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31131 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31132 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31133 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31134 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31135 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31137 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31138 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31139 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31140 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31142 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31143 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31144 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31145 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31147 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31149 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31150 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31151 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31152 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31153 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31155 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
31156 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
31157 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
31159 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
31161 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31162 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31163 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31165 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
31166 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
31168 /* SSE MMX or 3Dnow!A */
31169 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31170 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31171 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31173 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31174 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31175 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31176 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31178 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
31179 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
31181 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
31183 /* SSE2 */
31184 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31186 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
31187 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
31188 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31189 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
31190 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
31192 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31193 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31194 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
31195 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31196 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31198 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
31200 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31201 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31202 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31203 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31205 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31206 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
31207 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31209 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31210 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31211 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31212 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31213 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31214 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31215 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31216 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31218 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31219 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31220 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31221 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31222 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
31223 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31224 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31225 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31226 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31227 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31228 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31229 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31230 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31231 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31232 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31233 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31234 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31235 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31236 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31237 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31239 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31240 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31241 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31242 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31244 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31245 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31246 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31247 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31249 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31251 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31252 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31253 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31255 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31257 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31258 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31259 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31260 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31261 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31262 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31263 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31264 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31266 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31267 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31268 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31269 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31270 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31271 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31272 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31273 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31275 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31276 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
31278 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31279 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31280 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31281 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31283 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31284 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31286 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31287 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31288 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31289 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31290 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31291 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31293 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31294 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31295 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31296 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31298 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31299 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31300 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31301 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31302 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31303 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31304 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31305 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31307 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31308 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31309 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31311 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31312 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
31314 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
31315 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31317 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
31319 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
31320 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
31321 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
31322 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
31324 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31325 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31326 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31327 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31328 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31329 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31330 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31332 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31333 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31334 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31335 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31336 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31337 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31338 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31340 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31341 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31342 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31343 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31345 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
31346 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31347 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31349 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
31351 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31353 /* SSE2 MMX */
31354 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31355 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31357 /* SSE3 */
31358 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
31359 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31361 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31362 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31363 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31364 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31365 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31366 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31368 /* SSSE3 */
31369 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31370 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
31371 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31372 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
31373 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31374 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31376 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31377 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31378 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31379 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31380 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31381 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31382 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31383 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31384 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31385 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31386 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31387 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31388 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
31389 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
31390 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31391 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31392 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31393 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31394 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31395 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31396 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31397 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31398 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31399 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31401 /* SSSE3. */
31402 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
31403 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
31405 /* SSE4.1 */
31406 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31407 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31408 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
31409 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
31410 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31411 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31412 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31413 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
31414 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
31415 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
31417 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31418 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31419 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31420 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31421 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31422 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31423 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31424 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31425 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31426 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31427 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31428 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31429 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31431 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31432 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31433 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31434 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31435 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31436 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31437 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31438 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31439 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31440 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31441 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31442 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31444 /* SSE4.1 */
31445 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31446 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31447 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31448 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31450 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
31451 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
31452 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
31453 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
31455 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31456 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31458 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31459 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31461 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
31462 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
31463 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
31464 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
31466 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
31467 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
31469 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31470 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31472 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31473 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31474 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31476 /* SSE4.2 */
31477 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31478 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
31479 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
31480 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31481 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31483 /* SSE4A */
31484 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
31485 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
31486 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
31487 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31489 /* AES */
31490 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
31491 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31493 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31494 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31495 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31496 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31498 /* PCLMUL */
31499 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
31501 /* AVX */
31502 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31503 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31504 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31505 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31506 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31507 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31508 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31509 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31510 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31511 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31512 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31513 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31514 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31515 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31516 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31517 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31518 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31519 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31520 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31521 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31522 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31523 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31524 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31525 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31526 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31527 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31529 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
31530 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
31531 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
31532 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31534 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31535 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31536 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
31537 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
31538 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31539 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31540 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31541 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31542 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31543 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31544 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31545 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31546 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31547 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
31548 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
31549 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
31550 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
31551 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
31552 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
31553 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31554 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
31555 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31556 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31557 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31558 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31559 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31560 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31561 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31562 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31563 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31564 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31565 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
31566 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
31567 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
31569 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31570 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31571 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31573 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31574 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31575 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31576 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31577 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31579 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31581 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31582 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31584 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
31585 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
31586 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
31587 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
31589 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31590 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31592 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31593 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31595 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
31596 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
31597 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
31598 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
31600 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
31601 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
31603 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31604 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31606 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31607 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31608 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31609 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31611 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31612 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31613 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31614 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
31615 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
31616 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
31618 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31619 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31620 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31621 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31622 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31623 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31624 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31625 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31626 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31627 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31628 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31629 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31630 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31631 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31632 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31634 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
31635 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
31637 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31638 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31640 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31642 /* AVX2 */
31643 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
31644 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
31645 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
31646 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
31647 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31648 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31649 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31650 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31651 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31652 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31653 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31654 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31655 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31656 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31657 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31658 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31659 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
31660 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31661 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31662 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31663 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31664 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
31665 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
31666 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31667 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31668 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31669 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31670 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31671 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31672 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31673 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31674 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31675 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31676 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31677 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31678 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31679 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31680 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31681 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
31682 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31683 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31684 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31685 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31686 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31687 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31688 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31689 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31690 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31691 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31692 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31693 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31694 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
31695 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31696 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31697 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31698 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31699 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31700 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31701 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31702 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31703 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31704 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31705 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31706 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31707 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31708 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31709 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31710 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31711 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31712 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31713 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31714 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31715 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31716 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31717 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
31718 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31719 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31720 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31721 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31722 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31723 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31724 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31725 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31726 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31727 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31728 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31729 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31730 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31731 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31732 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31733 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31734 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31735 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31736 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31737 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31738 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31739 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31740 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31741 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31742 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31743 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31744 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31745 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31746 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31747 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31748 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31749 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31750 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31751 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31752 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31753 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31754 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31755 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31756 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31757 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31758 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31759 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31760 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31761 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31762 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
31763 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31764 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
31765 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
31766 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31767 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31768 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31769 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31770 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31771 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31772 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31773 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31774 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31775 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
31776 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
31777 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vextractf128v4di, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
31778 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vinsertf128v4di, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
31779 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31780 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31781 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31782 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31783 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31784 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31785 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31786 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31787 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31788 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31790 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31792 /* BMI */
31793 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31794 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31795 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31797 /* TBM */
31798 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31799 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31801 /* F16C */
31802 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
31803 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
31804 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
31805 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
31807 /* BMI2 */
31808 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31809 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31810 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31811 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31812 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31813 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31815 /* AVX512F */
31816 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_256si, "__builtin_ia32_si512_256si", IX86_BUILTIN_SI512_SI256, UNKNOWN, (int) V16SI_FTYPE_V8SI },
31817 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_256ps, "__builtin_ia32_ps512_256ps", IX86_BUILTIN_PS512_PS256, UNKNOWN, (int) V16SF_FTYPE_V8SF },
31818 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_256pd, "__builtin_ia32_pd512_256pd", IX86_BUILTIN_PD512_PD256, UNKNOWN, (int) V8DF_FTYPE_V4DF },
31819 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_si, "__builtin_ia32_si512_si", IX86_BUILTIN_SI512_SI, UNKNOWN, (int) V16SI_FTYPE_V4SI },
31820 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_ps, "__builtin_ia32_ps512_ps", IX86_BUILTIN_PS512_PS, UNKNOWN, (int) V16SF_FTYPE_V4SF },
31821 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_pd, "__builtin_ia32_pd512_pd", IX86_BUILTIN_PD512_PD, UNKNOWN, (int) V8DF_FTYPE_V2DF },
31822 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31823 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31824 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31825 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31826 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31827 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31828 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31829 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
31830 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31831 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
31832 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
31833 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31834 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31835 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31836 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31837 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31838 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31839 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
31840 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31841 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
31842 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31843 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31844 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31845 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31846 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
31847 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
31848 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
31849 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
31850 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
31851 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
31852 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
31853 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
31854 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31855 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31856 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31857 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31858 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31859 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31860 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31861 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31862 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31863 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31864 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31865 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31866 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31867 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31868 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31869 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31870 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
31871 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
31872 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
31873 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
31874 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
31875 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31876 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31877 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31878 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31879 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31880 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31881 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31882 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31883 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31884 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31885 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31886 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31887 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31888 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31889 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31890 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31891 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31892 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31893 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31894 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31895 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31896 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31897 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31898 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31899 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31900 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31901 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31902 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31903 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
31904 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
31905 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
31906 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
31907 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
31908 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31909 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31910 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31911 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31912 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31913 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
31914 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
31915 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
31916 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
31917 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
31918 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
31919 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31920 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
31921 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31922 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31923 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31924 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31925 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31926 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31927 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31928 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31929 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31930 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31931 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31932 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31933 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31934 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31935 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31936 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31937 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31938 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31945 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31947 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31956 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31958 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31960 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31962 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31964 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31966 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31967 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31968 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31970 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
31971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
31972 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
31973 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
31974 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31975 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31976 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31977 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31978 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
31979 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
31980 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
31981 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
31982 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31983 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31984 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31985 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31986 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
31987 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31988 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31989 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31990 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31991 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31992 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
31993 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
31994 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31995 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31996 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31997 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31998 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
31999 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
32000 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
32001 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
32002 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32003 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32004 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32005 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32006 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32007 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32008 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
32009 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
32010 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
32011 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
32013 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
32014 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
32015 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
32016 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32017 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32018 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
32019 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32020 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32022 /* Mask arithmetic operations */
32023 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32024 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32025 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
32026 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32027 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32028 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32029 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
32030 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32031 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32032 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
32034 /* SHA */
32035 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32036 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32037 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32038 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
32039 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32040 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32041 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
32043 /* AVX512VL. */
32044 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT },
32045 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT },
32046 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32047 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32048 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32049 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32050 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32051 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32052 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32053 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32054 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32055 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32056 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32057 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32058 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32059 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32060 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32061 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32062 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32063 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32064 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32065 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32066 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32067 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32068 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32069 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32070 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32071 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32072 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32073 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32074 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32075 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32076 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32077 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32078 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32079 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32080 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32081 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32082 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32083 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32084 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32085 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32086 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32087 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32088 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32089 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32090 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32091 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32092 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32093 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32094 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32095 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32096 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32097 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_QI },
32098 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_QI },
32099 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI },
32100 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI },
32101 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32102 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32103 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32104 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32105 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32106 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32107 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32108 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32109 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32110 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32111 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32112 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32113 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32114 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32115 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32116 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32117 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32118 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32119 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32120 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32121 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32122 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32123 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32124 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32125 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32126 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32127 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32128 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32129 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32130 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32131 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32132 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32133 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_QI },
32134 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_QI },
32135 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_SI },
32136 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_SI },
32137 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32138 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_HI },
32139 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_HI },
32140 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_HI },
32141 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32142 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_QI },
32143 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32144 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_QI },
32145 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32146 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_QI },
32147 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32148 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
32149 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32150 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
32151 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32152 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32153 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32154 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_QI },
32155 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_QI },
32156 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI },
32157 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI },
32158 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32159 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32160 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32161 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32162 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32163 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32164 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32165 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32166 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32167 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32168 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32169 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32170 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32171 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32172 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32173 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32174 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32175 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32176 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32177 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32178 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32179 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32180 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32181 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32182 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32183 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32184 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32185 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32186 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32187 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32188 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32189 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32190 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32191 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32192 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32193 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32194 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32195 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32196 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32197 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32198 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32199 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32200 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32201 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32202 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32203 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32204 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32205 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32206 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32207 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32208 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32209 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32210 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32211 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32212 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32213 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32214 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32215 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32216 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32217 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32218 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32219 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32220 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32221 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32222 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32223 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32224 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32225 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32226 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32227 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32228 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32229 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32230 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32231 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32232 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32233 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32234 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32235 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32236 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32237 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32238 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32239 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32240 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32241 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32242 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32243 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32244 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32245 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32246 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32247 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32248 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32249 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32250 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32251 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32252 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32253 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32254 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32255 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32256 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32257 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32258 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32259 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32260 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32261 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32262 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32263 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32264 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32265 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32266 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32267 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32268 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32269 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32270 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32271 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32272 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32273 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32274 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32275 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32276 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32277 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32278 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32279 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32280 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32281 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32282 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32283 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32284 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32285 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32286 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32287 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32288 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32289 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32290 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32291 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32292 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32293 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32294 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32295 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32296 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32297 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32298 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32299 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32300 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32301 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32302 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32303 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32304 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32305 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32306 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32307 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32308 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32309 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32310 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32311 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32312 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32313 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32314 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32315 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32316 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32317 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32318 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32319 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32320 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32321 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32322 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32323 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32324 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32325 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32326 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32327 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32328 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32329 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32330 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32331 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32332 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32333 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32334 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32335 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32336 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32337 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32338 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32339 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32340 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32341 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32342 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32343 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32344 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32345 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32346 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32347 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32348 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32349 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32350 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32351 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32352 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32353 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32354 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32355 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32356 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32357 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32358 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32359 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32360 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32361 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32362 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32363 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32364 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32365 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32366 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32367 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32368 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32369 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32370 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32371 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32372 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32373 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32374 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32375 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32376 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32377 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32378 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32379 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32380 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32381 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32382 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32383 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32384 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32385 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32386 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32387 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32388 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32389 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32390 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32391 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32392 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32393 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32394 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32395 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32396 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32397 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32398 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32399 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32400 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32401 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32402 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32403 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32404 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32405 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32406 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32407 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32408 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32409 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32410 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32411 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32412 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32413 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32414 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32415 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32416 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32417 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32418 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32419 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32420 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32421 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32422 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32423 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32424 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32425 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32426 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI },
32427 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI },
32428 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32429 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32430 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_HI },
32431 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_QI },
32432 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_QI },
32433 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_QI },
32434 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32435 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32436 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32437 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32438 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32439 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32440 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32441 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32442 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32443 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32444 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32445 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32446 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32447 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32448 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32449 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32450 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32451 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32452 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32453 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32454 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32455 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32456 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32457 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32458 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32459 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32460 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32461 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32462 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32463 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32464 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32465 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32466 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32467 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32468 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32469 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32470 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32471 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32472 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32473 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32474 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32475 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32476 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32477 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32478 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32479 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32480 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32481 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32482 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32483 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32484 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32485 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32486 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32487 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32488 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32489 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32490 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32491 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32492 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32493 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32494 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32495 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32496 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32497 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32498 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32499 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32500 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32501 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32502 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32503 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32504 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32505 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32506 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32507 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32508 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32509 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32510 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32511 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32512 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32513 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32514 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32515 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32516 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32517 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32518 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32519 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32520 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32521 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32522 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32523 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32524 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32525 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32526 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32527 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32528 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32529 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32530 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32531 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32532 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32533 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32534 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_QI },
32535 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_QI },
32536 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
32537 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_QI },
32538 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_QI },
32539 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
32540 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) HI_FTYPE_V16QI },
32541 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) SI_FTYPE_V32QI },
32542 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) QI_FTYPE_V8HI },
32543 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) HI_FTYPE_V16HI },
32544 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) QI_FTYPE_V4SI },
32545 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) QI_FTYPE_V8SI },
32546 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) QI_FTYPE_V2DI },
32547 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) QI_FTYPE_V4DI },
32548 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_HI },
32549 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_SI },
32550 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_QI },
32551 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_HI },
32552 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_QI },
32553 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_QI },
32554 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_QI },
32555 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_QI },
32556 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32557 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32558 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32559 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32560 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32561 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32562 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32563 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32564 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32565 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32566 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32567 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32568 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32569 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32570 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32571 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32572 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32573 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32574 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32575 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32576 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32577 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32578 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32579 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32580 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32581 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32582 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32583 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32584 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32585 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32586 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32587 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32588 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_QI },
32589 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_QI },
32590 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_HI },
32591 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_HI },
32592 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32593 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32594 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32595 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32596 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32597 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32598 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32599 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32600 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32601 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32602 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32603 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32604 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32605 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32606 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32607 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32608 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32609 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32610 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32611 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32612 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32613 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32614 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32615 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32616 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32617 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32618 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32619 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32620 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32621 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32622 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32623 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32624 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32625 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32626 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32627 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32628 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32629 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32630 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32631 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32632 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32633 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32634 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32635 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32636 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32637 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32638 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32639 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32640 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32641 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32642 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32643 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32644 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32645 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32646 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32647 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32648 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32649 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32650 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32651 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32652 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32653 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32654 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32655 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32656 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32657 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32658 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32659 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32660 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32661 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32662 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32663 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32664 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32665 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32666 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI },
32667 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI },
32668 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_QI },
32669 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_QI },
32670 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_QI },
32671 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_QI },
32672 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32673 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32674 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32675 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32676 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32677 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32678 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32679 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32680 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32681 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32682 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32683 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32684 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32685 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32686 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32687 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32688 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32689 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32690 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32691 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32692 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32693 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32694 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32695 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32696 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32697 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32698 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32699 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32700 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32701 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32702 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32703 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32704 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32705 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32706 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32707 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32708 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32709 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32710 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32711 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32712 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32713 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32714 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32715 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32716 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32717 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32718 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32719 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32720 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32721 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32722 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32723 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32724 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32725 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32726 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32727 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32728 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32729 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32730 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32731 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_QI },
32732 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_QI },
32733 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32734 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32735 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32736 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32737 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32738 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32739 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32740 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32741 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32742 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32743 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32744 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_QI },
32745 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_QI },
32746 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32747 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32748 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32749 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32750 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32751 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32752 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32753 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32754 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI },
32755 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI },
32757 /* AVX512DQ. */
32758 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
32759 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
32760 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
32761 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
32762 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_HI },
32763 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_HI },
32764 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_QI },
32765 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_QI },
32766 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_QI },
32767 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_QI },
32768 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32769 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32770 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32771 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32772 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32773 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32774 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32775 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32776 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32777 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI},
32778 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32779 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI },
32780 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI },
32781 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI },
32782 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI },
32783 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_QI },
32784 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_HI },
32785 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) HI_FTYPE_V16SI },
32786 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) QI_FTYPE_V8DI },
32787 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_HI },
32788 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_QI },
32790 /* AVX512BW. */
32791 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) SI_FTYPE_SI_SI },
32792 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) DI_FTYPE_DI_DI },
32793 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32794 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32795 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32796 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32797 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
32798 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT },
32799 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32800 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32801 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
32802 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI },
32803 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_DI },
32804 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_DI },
32805 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_SI },
32806 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_SI },
32807 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32808 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32809 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32810 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32811 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32812 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32813 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32814 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32815 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32816 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32817 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32818 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32819 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32820 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32821 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32822 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32823 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32824 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32825 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32826 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32827 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32828 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32829 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32830 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32831 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32832 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32833 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32834 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32835 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32836 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32837 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32838 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32839 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32840 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32841 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32842 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32843 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32844 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32845 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32846 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32847 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_SI },
32848 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_HI },
32849 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32850 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32851 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32852 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32853 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32854 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32855 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32856 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32857 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32858 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32859 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32860 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32861 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) DI_FTYPE_V64QI },
32862 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) SI_FTYPE_V32HI },
32863 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_DI },
32864 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_SI },
32865 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32866 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32867 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32868 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32869 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32870 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32871 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32872 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32873 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32874 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32875 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32876 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32877 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32878 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32879 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32880 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32881 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32883 /* AVX512IFMA */
32884 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_mask, "__builtin_ia32_vpmadd52luq512_mask", IX86_BUILTIN_VPMADD52LUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32885 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_maskz, "__builtin_ia32_vpmadd52luq512_maskz", IX86_BUILTIN_VPMADD52LUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32886 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_mask, "__builtin_ia32_vpmadd52huq512_mask", IX86_BUILTIN_VPMADD52HUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32887 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_maskz, "__builtin_ia32_vpmadd52huq512_maskz", IX86_BUILTIN_VPMADD52HUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32888 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_mask, "__builtin_ia32_vpmadd52luq256_mask", IX86_BUILTIN_VPMADD52LUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32889 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_maskz, "__builtin_ia32_vpmadd52luq256_maskz", IX86_BUILTIN_VPMADD52LUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32890 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_mask, "__builtin_ia32_vpmadd52huq256_mask", IX86_BUILTIN_VPMADD52HUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32891 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_maskz, "__builtin_ia32_vpmadd52huq256_maskz", IX86_BUILTIN_VPMADD52HUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32892 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_mask, "__builtin_ia32_vpmadd52luq128_mask", IX86_BUILTIN_VPMADD52LUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32893 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_maskz, "__builtin_ia32_vpmadd52luq128_maskz", IX86_BUILTIN_VPMADD52LUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32894 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_mask, "__builtin_ia32_vpmadd52huq128_mask", IX86_BUILTIN_VPMADD52HUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32895 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_maskz, "__builtin_ia32_vpmadd52huq128_maskz", IX86_BUILTIN_VPMADD52HUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32897 /* AVX512VBMI */
32898 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_vpmultishiftqbv64qi_mask, "__builtin_ia32_vpmultishiftqb512_mask", IX86_BUILTIN_VPMULTISHIFTQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32899 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv32qi_mask, "__builtin_ia32_vpmultishiftqb256_mask", IX86_BUILTIN_VPMULTISHIFTQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32900 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv16qi_mask, "__builtin_ia32_vpmultishiftqb128_mask", IX86_BUILTIN_VPMULTISHIFTQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32901 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_permvarv64qi_mask, "__builtin_ia32_permvarqi512_mask", IX86_BUILTIN_VPERMVARQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32902 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_mask, "__builtin_ia32_vpermt2varqi512_mask", IX86_BUILTIN_VPERMT2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32903 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_maskz, "__builtin_ia32_vpermt2varqi512_maskz", IX86_BUILTIN_VPERMT2VARQI512_MASKZ, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32904 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermi2varv64qi3_mask, "__builtin_ia32_vpermi2varqi512_mask", IX86_BUILTIN_VPERMI2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32905 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv32qi_mask, "__builtin_ia32_permvarqi256_mask", IX86_BUILTIN_VPERMVARQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32906 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16qi_mask, "__builtin_ia32_permvarqi128_mask", IX86_BUILTIN_VPERMVARQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32907 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_mask, "__builtin_ia32_vpermt2varqi256_mask", IX86_BUILTIN_VPERMT2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32908 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_maskz, "__builtin_ia32_vpermt2varqi256_maskz", IX86_BUILTIN_VPERMT2VARQI256_MASKZ, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32909 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_mask, "__builtin_ia32_vpermt2varqi128_mask", IX86_BUILTIN_VPERMT2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32910 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_maskz, "__builtin_ia32_vpermt2varqi128_maskz", IX86_BUILTIN_VPERMT2VARQI128_MASKZ, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32911 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv32qi3_mask, "__builtin_ia32_vpermi2varqi256_mask", IX86_BUILTIN_VPERMI2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32912 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16qi3_mask, "__builtin_ia32_vpermi2varqi128_mask", IX86_BUILTIN_VPERMI2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32913 };
32915 /* Builtins with rounding support. */
32917 {
32918 /* AVX512F */
32919 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32920 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32921 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32922 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32923 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
32924 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
32925 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
32926 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
32927 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
32928 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
32929 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
32930 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32931 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
32932 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32933 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
32934 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32935 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
32936 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32937 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
32938 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
32939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
32940 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
32941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
32942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32945 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
32947 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
32948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
32949 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
32950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
32955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
32956 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
32957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
32958 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
32959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
32960 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
32961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
32962 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32964 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32966 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
32967 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
32968 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32970 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32972 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32973 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32974 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32975 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32976 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32977 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32978 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32979 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32980 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32981 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32982 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
32983 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
32984 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32985 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32986 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32987 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32988 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32989 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32990 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32991 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32992 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32993 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32994 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32995 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32996 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32997 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32998 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
32999 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33000 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33001 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33002 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33003 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33004 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33005 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33006 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33007 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33008 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33009 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33010 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33011 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33012 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33013 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33014 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33015 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33016 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33017 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33018 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33019 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33020 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
33021 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
33022 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33023 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33024 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33025 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33026 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33027 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33028 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33029 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33030 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33031 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33032 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33033 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33034 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33035 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33036 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33037 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33039 /* AVX512ER */
33040 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33041 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33042 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33043 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33044 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33045 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33046 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33047 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33048 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33049 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33051 /* AVX512DQ. */
33052 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33053 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33054 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33055 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33056 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33057 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33058 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33059 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33060 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33061 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33062 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33063 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33064 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33065 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33066 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
33067 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
33068 };
33070 /* Bultins for MPX. */
33072 {
33073 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndstx", IX86_BUILTIN_BNDSTX, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND_PCVOID },
33074 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcl", IX86_BUILTIN_BNDCL, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33075 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcu", IX86_BUILTIN_BNDCU, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33076 };
33078 /* Const builtins for MPX. */
33080 {
33081 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndmk", IX86_BUILTIN_BNDMK, UNKNOWN, (int) BND_FTYPE_PCVOID_ULONG },
33082 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndldx", IX86_BUILTIN_BNDLDX, UNKNOWN, (int) BND_FTYPE_PCVOID_PCVOID },
33083 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_narrow_bounds", IX86_BUILTIN_BNDNARROW, UNKNOWN, (int) PVOID_FTYPE_PCVOID_BND_ULONG },
33084 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndint", IX86_BUILTIN_BNDINT, UNKNOWN, (int) BND_FTYPE_BND_BND },
33085 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_sizeof", IX86_BUILTIN_SIZEOF, UNKNOWN, (int) ULONG_FTYPE_VOID },
33086 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndlower", IX86_BUILTIN_BNDLOWER, UNKNOWN, (int) PVOID_FTYPE_BND },
33087 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndupper", IX86_BUILTIN_BNDUPPER, UNKNOWN, (int) PVOID_FTYPE_BND },
33088 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndret", IX86_BUILTIN_BNDRET, UNKNOWN, (int) BND_FTYPE_PCVOID },
33089 };
33091 /* FMA4 and XOP. */
33092 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
33093 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
33094 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
33095 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
33096 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
33097 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
33098 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
33099 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
33100 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
33101 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
33102 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
33103 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
33104 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
33105 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
33106 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
33107 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
33108 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
33109 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
33110 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
33111 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
33112 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
33113 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
33114 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
33115 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
33116 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
33117 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
33118 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
33119 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
33120 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
33121 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
33122 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
33123 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
33124 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
33125 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
33126 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
33127 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
33128 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
33129 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
33130 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
33131 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
33132 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
33133 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
33134 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
33135 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
33136 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
33137 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
33138 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
33139 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
33140 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
33141 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
33142 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
33143 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
33146 {
33187 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
33188 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
33189 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
33190 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
33191 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
33192 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
33193 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
33195 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33196 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33197 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
33198 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
33199 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
33200 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
33201 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
33203 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
33205 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33206 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33207 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33208 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33209 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33210 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33211 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33212 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33213 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33214 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33215 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33216 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33218 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33219 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
33220 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
33221 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
33222 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
33223 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
33224 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
33225 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
33226 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33227 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
33228 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
33229 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
33230 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33231 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
33232 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
33233 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
33235 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
33236 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
33237 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
33238 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
33239 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
33240 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
33242 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33243 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33244 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33245 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33246 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33247 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33248 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33249 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33250 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33251 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33252 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33253 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33254 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33255 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33256 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33258 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
33259 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33260 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33261 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
33262 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
33263 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
33264 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
33266 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
33267 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33268 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33269 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
33270 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
33271 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
33272 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
33274 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
33275 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33276 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33277 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
33278 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
33279 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
33280 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
33282 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33283 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33284 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33285 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
33286 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
33287 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
33288 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
33290 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
33291 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33292 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33293 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
33294 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
33295 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
33296 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
33298 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
33299 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33300 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33301 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
33302 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
33303 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
33304 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
33306 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
33307 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33308 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33309 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
33310 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
33311 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
33312 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
33314 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33315 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33316 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33317 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
33318 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
33319 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
33320 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
33322 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33323 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33324 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33325 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33326 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33327 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33328 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33329 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33331 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33332 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33333 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33334 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33335 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33336 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33337 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33338 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33340 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
33341 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
33342 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
33343 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
33345 };
33346 \f
33347 /* TM vector builtins. */
33349 /* Reuse the existing x86-specific `struct builtin_description' cause
33350 we're lazy. Add casts to make them fit. */
33352 {
33353 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33354 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33355 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33356 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33357 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33358 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33359 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33361 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33362 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33363 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33364 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33365 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33366 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33367 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33369 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33370 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33371 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33372 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33373 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33374 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33375 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33377 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
33378 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
33379 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
33380 };
33382 /* TM callbacks. */
33384 /* Return the builtin decl needed to load a vector of TYPE. */
33386 static tree
33388 {
33390 {
33392 {
33399 }
33400 }
33402 }
33404 /* Return the builtin decl needed to store a vector of TYPE. */
33406 static tree
33408 {
33410 {
33412 {
33419 }
33420 }
33422 }
33423 \f
33424 /* Initialize the transactional memory vector load/store builtins. */
33426 static void
33428 {
33432 tree decl;
33439 /* If there are no builtins defined, we must be compiling in a
33440 language without trans-mem support. */
33444 /* Use whatever attributes a normal TM load has. */
33448 /* Use whatever attributes a normal TM store has. */
33452 /* Use whatever attributes a normal TM log has. */
33460 {
33464 {
33472 {
33475 }
33477 {
33480 }
33481 else
33482 {
33485 }
33487 /* The builtin without the prefix for
33488 calling it directly. */
33490 attrs);
33491 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
33492 set the TYPE_ATTRIBUTES. */
33496 }
33497 }
33498 }
33500 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
33501 in the current target ISA to allow the user to compile particular modules
33502 with different target specific options that differ from the command line
33503 options. */
33504 static void
33506 {
33511 /* Add all special builtins with variable number of operands. */
33515 {
33521 }
33523 /* Add all builtins with variable number of operands. */
33527 {
33533 }
33535 /* Add all builtins with rounding. */
33539 {
33545 }
33547 /* pcmpestr[im] insns. */
33551 {
33554 else
33557 }
33559 /* pcmpistr[im] insns. */
33563 {
33566 else
33569 }
33571 /* comi/ucomi insns. */
33573 {
33576 else
33579 }
33581 /* SSE */
33587 /* SSE or 3DNow!A */
33590 IX86_BUILTIN_MASKMOVQ);
33592 /* SSE2 */
33601 /* SSE3. */
33607 /* AES */
33621 /* PCLMUL */
33625 /* RDRND */
33632 IX86_BUILTIN_RDRAND64_STEP);
33634 /* AVX2 */
33636 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
33637 IX86_BUILTIN_GATHERSIV2DF);
33640 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
33641 IX86_BUILTIN_GATHERSIV4DF);
33644 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
33645 IX86_BUILTIN_GATHERDIV2DF);
33648 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
33649 IX86_BUILTIN_GATHERDIV4DF);
33652 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
33653 IX86_BUILTIN_GATHERSIV4SF);
33656 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
33657 IX86_BUILTIN_GATHERSIV8SF);
33660 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
33661 IX86_BUILTIN_GATHERDIV4SF);
33664 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
33665 IX86_BUILTIN_GATHERDIV8SF);
33668 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
33669 IX86_BUILTIN_GATHERSIV2DI);
33672 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
33673 IX86_BUILTIN_GATHERSIV4DI);
33676 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
33677 IX86_BUILTIN_GATHERDIV2DI);
33680 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
33681 IX86_BUILTIN_GATHERDIV4DI);
33684 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
33685 IX86_BUILTIN_GATHERSIV4SI);
33688 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
33689 IX86_BUILTIN_GATHERSIV8SI);
33692 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
33693 IX86_BUILTIN_GATHERDIV4SI);
33696 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
33697 IX86_BUILTIN_GATHERDIV8SI);
33700 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
33701 IX86_BUILTIN_GATHERALTSIV4DF);
33704 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
33705 IX86_BUILTIN_GATHERALTDIV8SF);
33708 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
33709 IX86_BUILTIN_GATHERALTSIV4DI);
33712 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
33713 IX86_BUILTIN_GATHERALTDIV8SI);
33715 /* AVX512F */
33717 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
33718 IX86_BUILTIN_GATHER3SIV16SF);
33721 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
33722 IX86_BUILTIN_GATHER3SIV8DF);
33725 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
33726 IX86_BUILTIN_GATHER3DIV16SF);
33729 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
33730 IX86_BUILTIN_GATHER3DIV8DF);
33733 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
33734 IX86_BUILTIN_GATHER3SIV16SI);
33737 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
33738 IX86_BUILTIN_GATHER3SIV8DI);
33741 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
33742 IX86_BUILTIN_GATHER3DIV16SI);
33745 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
33746 IX86_BUILTIN_GATHER3DIV8DI);
33749 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
33750 IX86_BUILTIN_GATHER3ALTSIV8DF);
33753 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
33754 IX86_BUILTIN_GATHER3ALTDIV16SF);
33757 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
33758 IX86_BUILTIN_GATHER3ALTSIV8DI);
33761 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
33762 IX86_BUILTIN_GATHER3ALTDIV16SI);
33765 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
33766 IX86_BUILTIN_SCATTERSIV16SF);
33769 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
33770 IX86_BUILTIN_SCATTERSIV8DF);
33773 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
33774 IX86_BUILTIN_SCATTERDIV16SF);
33777 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
33778 IX86_BUILTIN_SCATTERDIV8DF);
33781 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
33782 IX86_BUILTIN_SCATTERSIV16SI);
33785 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
33786 IX86_BUILTIN_SCATTERSIV8DI);
33789 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
33790 IX86_BUILTIN_SCATTERDIV16SI);
33793 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
33794 IX86_BUILTIN_SCATTERDIV8DI);
33796 /* AVX512VL */
33798 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT,
33799 IX86_BUILTIN_GATHER3SIV2DF);
33802 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT,
33803 IX86_BUILTIN_GATHER3SIV4DF);
33806 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT,
33807 IX86_BUILTIN_GATHER3DIV2DF);
33810 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT,
33811 IX86_BUILTIN_GATHER3DIV4DF);
33814 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT,
33815 IX86_BUILTIN_GATHER3SIV4SF);
33818 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT,
33819 IX86_BUILTIN_GATHER3SIV8SF);
33822 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT,
33823 IX86_BUILTIN_GATHER3DIV4SF);
33826 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT,
33827 IX86_BUILTIN_GATHER3DIV8SF);
33830 V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT,
33831 IX86_BUILTIN_GATHER3SIV2DI);
33834 V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT,
33835 IX86_BUILTIN_GATHER3SIV4DI);
33838 V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT,
33839 IX86_BUILTIN_GATHER3DIV2DI);
33842 V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT,
33843 IX86_BUILTIN_GATHER3DIV4DI);
33846 V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT,
33847 IX86_BUILTIN_GATHER3SIV4SI);
33850 V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT,
33851 IX86_BUILTIN_GATHER3SIV8SI);
33854 V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT,
33855 IX86_BUILTIN_GATHER3DIV4SI);
33858 V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT,
33859 IX86_BUILTIN_GATHER3DIV8SI);
33862 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
33863 IX86_BUILTIN_GATHER3ALTSIV4DF);
33866 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
33867 IX86_BUILTIN_GATHER3ALTDIV8SF);
33870 V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
33871 IX86_BUILTIN_GATHER3ALTSIV4DI);
33874 V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
33875 IX86_BUILTIN_GATHER3ALTDIV8SI);
33878 VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT,
33879 IX86_BUILTIN_SCATTERSIV8SF);
33882 VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT,
33883 IX86_BUILTIN_SCATTERSIV4SF);
33886 VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT,
33887 IX86_BUILTIN_SCATTERSIV4DF);
33890 VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT,
33891 IX86_BUILTIN_SCATTERSIV2DF);
33894 VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT,
33895 IX86_BUILTIN_SCATTERDIV8SF);
33898 VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT,
33899 IX86_BUILTIN_SCATTERDIV4SF);
33902 VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT,
33903 IX86_BUILTIN_SCATTERDIV4DF);
33906 VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT,
33907 IX86_BUILTIN_SCATTERDIV2DF);
33910 VOID_FTYPE_PINT_QI_V8SI_V8SI_INT,
33911 IX86_BUILTIN_SCATTERSIV8SI);
33914 VOID_FTYPE_PINT_QI_V4SI_V4SI_INT,
33915 IX86_BUILTIN_SCATTERSIV4SI);
33918 VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT,
33919 IX86_BUILTIN_SCATTERSIV4DI);
33922 VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT,
33923 IX86_BUILTIN_SCATTERSIV2DI);
33926 VOID_FTYPE_PINT_QI_V4DI_V4SI_INT,
33927 IX86_BUILTIN_SCATTERDIV8SI);
33930 VOID_FTYPE_PINT_QI_V2DI_V4SI_INT,
33931 IX86_BUILTIN_SCATTERDIV4SI);
33934 VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT,
33935 IX86_BUILTIN_SCATTERDIV4DI);
33938 VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT,
33939 IX86_BUILTIN_SCATTERDIV2DI);
33941 /* AVX512PF */
33943 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
33944 IX86_BUILTIN_GATHERPFDPD);
33946 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
33947 IX86_BUILTIN_GATHERPFDPS);
33949 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
33950 IX86_BUILTIN_GATHERPFQPD);
33952 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
33953 IX86_BUILTIN_GATHERPFQPS);
33955 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
33956 IX86_BUILTIN_SCATTERPFDPD);
33958 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
33959 IX86_BUILTIN_SCATTERPFDPS);
33961 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
33962 IX86_BUILTIN_SCATTERPFQPD);
33964 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
33965 IX86_BUILTIN_SCATTERPFQPS);
33967 /* SHA */
33983 /* RTM. */
33987 /* MMX access to the vec_init patterns. */
33992 V4HI_FTYPE_HI_HI_HI_HI,
33993 IX86_BUILTIN_VEC_INIT_V4HI);
33996 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
33997 IX86_BUILTIN_VEC_INIT_V8QI);
33999 /* Access to the vec_extract patterns. */
34021 /* Access to the vec_set patterns. */
34042 /* RDSEED */
34051 /* ADCX */
34056 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34057 IX86_BUILTIN_ADDCARRYX64);
34059 /* SBB */
34064 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34065 IX86_BUILTIN_SBB64);
34067 /* Read/write FLAGS. */
34077 /* CLFLUSHOPT. */
34081 /* CLWB. */
34085 /* Add FMA4 multi-arg argument instructions */
34087 {
34093 }
34094 }
34096 static void
34098 {
34101 tree decl;
34107 {
34114 /* With no leaf and nothrow flags for MPX builtins
34115 abnormal edges may follow its call when setjmp
34116 presents in the function. Since we may have a lot
34117 of MPX builtins calls it causes lots of useless
34118 edges and enormous PHI nodes. To avoid this we mark
34119 MPX builtins as leaf and nothrow. */
34121 {
34123 NULL_TREE);
34125 }
34126 else
34127 {
34130 }
34131 }
34136 {
34144 {
34146 NULL_TREE);
34148 }
34149 else
34150 {
34153 }
34154 }
34155 }
34157 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
34158 to return a pointer to VERSION_DECL if the outcome of the expression
34159 formed by PREDICATE_CHAIN is true. This function will be called during
34160 version dispatch to decide which function version to execute. It returns
34161 the basic block at the end, to which more conditions can be added. */
34163 static basic_block
34166 {
34167 gimple return_stmt;
34169 gimple convert_stmt;
34170 gimple call_cond_stmt;
34171 gimple if_else_stmt;
34177 gimple_seq gseq;
34194 {
34202 }
34205 {
34220 else
34221 {
34222 gimple assign_stmt;
34223 /* Use MIN_EXPR to check if any integer is zero?.
34224 and_expr_var = min_expr <cond_var, and_expr_var> */
34232 }
34233 }
34236 integer_zero_node,
34266 }
34268 /* This parses the attribute arguments to target in DECL and determines
34269 the right builtin to use to match the platform specification.
34270 It returns the priority value for this version decl. If PREDICATE_LIST
34271 is not NULL, it stores the list of cpu features that need to be checked
34272 before dispatching this function. */
34274 static unsigned int
34276 {
34277 tree attrs;
34279 tree target_node;
34286 /* Priority of i386 features, greater value is higher priority. This is
34287 used to decide the order in which function dispatch must happen. For
34288 instance, a version specialized for SSE4.2 should be checked for dispatch
34289 before a version for SSE3, as SSE4.2 implies SSE3. */
34290 enum feature_priority
34291 {
34293 P_MMX,
34294 P_SSE,
34295 P_SSE2,
34296 P_SSE3,
34297 P_SSSE3,
34298 P_PROC_SSSE3,
34299 P_SSE4_A,
34300 P_PROC_SSE4_A,
34301 P_SSE4_1,
34302 P_SSE4_2,
34303 P_PROC_SSE4_2,
34304 P_POPCNT,
34305 P_AVX,
34306 P_PROC_AVX,
34307 P_BMI,
34308 P_PROC_BMI,
34309 P_FMA4,
34310 P_XOP,
34311 P_PROC_XOP,
34312 P_FMA,
34313 P_PROC_FMA,
34314 P_BMI2,
34315 P_AVX2,
34316 P_PROC_AVX2,
34317 P_AVX512F,
34318 P_PROC_AVX512F
34319 };
34323 /* These are the target attribute strings for which a dispatcher is
34324 available, from fold_builtin_cpu. */
34326 static struct _feature_list
34327 {
34330 }
34332 {
34350 };
34353 static unsigned int NUM_FEATURES
34369 /* Return priority zero for default function. */
34373 /* Handle arch= if specified. For priority, set it to be 1 more than
34374 the best instruction set the processor can handle. For instance, if
34375 there is a version for atom and a version for ssse3 (the highest ISA
34376 priority for atom), the atom version must be checked for dispatch
34377 before the ssse3 version. */
34379 {
34389 {
34391 {
34399 else
34400 /* We translate "arch=corei7" and "arch=nehalem" to
34401 "corei7" so that it will be mapped to M_INTEL_COREI7
34402 as cpu type to cover all M_INTEL_COREI7_XXXs. */
34409 else
34416 else
34460 }
34461 }
34466 {
34470 }
34473 {
34475 /* For a C string literal the length includes the trailing NULL. */
34478 predicate_chain);
34479 }
34480 }
34482 /* Process feature name. */
34489 {
34490 /* Do not process "arch=" */
34492 {
34495 }
34497 {
34499 {
34501 {
34506 predicate_chain);
34507 }
34508 /* Find the maximum priority feature. */
34513 }
34514 }
34516 {
34520 }
34522 }
34526 {
34529 attrs_str);
34531 }
34533 {
34536 }
34539 }
34541 /* This compares the priority of target features in function DECL1
34542 and DECL2. It returns positive value if DECL1 is higher priority,
34543 negative value if DECL2 is higher priority and 0 if they are the
34544 same. */
34546 static int
34548 {
34553 }
34555 /* V1 and V2 point to function versions with different priorities
34556 based on the target ISA. This function compares their priorities. */
34558 static int
34560 {
34562 {
34563 tree version_decl;
34564 tree predicate_chain;
34571 }
34573 /* This function generates the dispatch function for
34574 multi-versioned functions. DISPATCH_DECL is the function which will
34575 contain the dispatch logic. FNDECLS are the function choices for
34576 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
34577 in DISPATCH_DECL in which the dispatch code is generated. */
34579 static int
34583 {
34584 tree default_decl;
34585 gimple ifunc_cpu_init_stmt;
34586 gimple_seq gseq;
34588 tree ele;
34594 struct _function_version_info
34595 {
34596 tree version_decl;
34597 tree predicate_chain;
34605 /*fndecls_p is actually a vector. */
34608 /* At least one more version other than the default. */
34615 /* The first version in the vector is the default decl. */
34621 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
34622 constructors, so explicity call __builtin_cpu_init here. */
34633 {
34637 /* Get attribute string, parse it and find the right predicate decl.
34638 The predicate function could be a lengthy combination of many
34639 features, like arch-type and various isa-variants. */
34650 actual_versions++;
34651 }
34653 /* Sort the versions according to descending order of dispatch priority. The
34654 priority is based on the ISA. This is not a perfect solution. There
34655 could still be ambiguity. If more than one function version is suitable
34656 to execute, which one should be dispatched? In future, allow the user
34657 to specify a dispatch priority next to the version. */
34667 /* dispatch default version at the end. */
34673 }
34675 /* Comparator function to be used in qsort routine to sort attribute
34676 specification strings to "target". */
34678 static int
34680 {
34684 }
34686 /* ARGLIST is the argument to target attribute. This function tokenizes
34687 the comma separated arguments, sorts them and returns a string which
34688 is a unique identifier for the comma separated arguments. It also
34689 replaces non-identifier characters "=,-" with "_". */
34693 {
34694 tree arg;
34703 {
34708 argnum++;
34711 argnum++;
34712 }
34717 {
34723 }
34725 /* Replace "=,-" with "_". */
34738 {
34740 i++;
34742 }
34749 {
34754 }
34759 }
34761 /* This function changes the assembler name for functions that are
34762 versions. If DECL is a function version and has a "target"
34763 attribute, it appends the attribute string to its assembler name. */
34765 static tree
34767 {
34768 tree version_attr;
34776 "Function versions cannot be marked as gnu_inline,"
34785 /* target attribute string cannot be NULL. */
34789 version_string
34800 /* Allow assembler name to be modified if already set. */
34808 }
34810 /* This function returns true if FN1 and FN2 are versions of the same function,
34811 that is, the target strings of the function decls are different. This assumes
34812 that FN1 and FN2 have the same signature. */
34814 static bool
34816 {
34828 /* At least one function decl should have the target attribute specified. */
34832 /* Diagnose missing target attribute if one of the decls is already
34833 multi-versioned. */
34835 {
34837 {
34839 {
34844 }
34847 fn2);
34850 /* Prevent diagnosing of the same error multiple times. */
34855 }
34857 }
34862 /* The sorted target strings must be different for fn1 and fn2
34863 to be versions. */
34866 else
34873 }
34875 static tree
34877 {
34878 /* For function version, add the target suffix to the assembler name. */
34882 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
34884 #endif
34887 }
34889 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
34890 is true, append the full path name of the source file. */
34894 {
34902 /* Get a unique name that can be used globally without any chances
34903 of collision at link time. */
34913 /* Use '.' to concatenate names as it is demangler friendly. */
34916 suffix);
34917 else
34921 }
34923 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
34925 /* Make a dispatcher declaration for the multi-versioned function DECL.
34926 Calls to DECL function will be replaced with calls to the dispatcher
34927 by the front-end. Return the decl created. */
34929 static tree
34931 {
34932 tree func_decl;
34952 /* Mark this func as external, the resolver will flip it again if
34953 it gets generated. */
34955 /* This will be of type IFUNCs have to be externally visible. */
34959 }
34961 #endif
34963 /* Returns true if decl is multi-versioned and DECL is the default function,
34964 that is it is not tagged with target specific optimization. */
34966 static bool
34968 {
34977 }
34979 /* Make a dispatcher declaration for the multi-versioned function DECL.
34980 Calls to DECL function will be replaced with calls to the dispatcher
34981 by the front-end. Returns the decl of the dispatcher function. */
34983 static tree
34985 {
35007 /* Find the default version and make it the first node. */
35009 /* Go to the beginning of the chain. */
35014 {
35019 }
35021 /* If there is no default node, just return NULL. */
35025 /* Make default info the first node. */
35027 {
35034 }
35038 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35040 {
35045 /* Right now, the dispatching is done via ifunc. */
35051 dispatcher_version_info
35056 /* Set the dispatcher for all the versions. */
35059 {
35062 }
35063 }
35064 else
35065 #endif
35066 {
35068 "multiversioning needs ifunc which is not supported "
35070 }
35073 }
35075 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
35076 it to CHAIN. */
35078 static tree
35080 {
35081 tree attr_name;
35082 tree attr_arg_name;
35083 tree attr_args;
35084 tree attr;
35091 }
35093 /* Make the resolver function decl to dispatch the versions of
35094 a multi-versioned function, DEFAULT_DECL. Create an
35095 empty basic block in the resolver and store the pointer in
35096 EMPTY_BB. Return the decl of the resolver function. */
35098 static tree
35102 {
35107 /* IFUNC's have to be globally visible. So, if the default_decl is
35108 not, then the name of the IFUNC should be made unique. */
35112 /* Append the filename to the resolver function if the versions are
35113 not externally visible. This is because the resolver function has
35114 to be externally visible for the loader to find it. So, appending
35115 the filename will prevent conflicts with a resolver function from
35116 another module which is based on the same version name. */
35119 /* The resolver function should return a (void *). */
35130 /* IFUNC resolvers have to be externally visible. */
35134 /* Resolver is not external, body is generated. */
35144 {
35145 /* In this case, each translation unit with a call to this
35146 versioned function will put out a resolver. Ensure it
35147 is comdat to keep just one copy. */
35150 }
35151 /* Build result decl and add to function_decl. */
35167 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
35171 /* Create the alias for dispatch to resolver here. */
35172 /*cgraph_create_function_alias (dispatch_decl, decl);*/
35176 }
35178 /* Generate the dispatching code body to dispatch multi-versioned function
35179 DECL. The target hook is called to process the "target" attributes and
35180 provide the code to dispatch the right function at run-time. NODE points
35181 to the dispatcher decl whose body will be created. */
35183 static tree
35185 {
35186 tree resolver_decl;
35187 basic_block empty_bb;
35188 tree default_ver_decl;
35204 /* The first version in the chain corresponds to the default version. */
35207 /* node is going to be an alias, so remove the finalized bit. */
35221 {
35223 /* Check for virtual functions here again, as by this time it should
35224 have been determined if this function needs a vtable index or
35225 not. This happens for methods in derived classes that override
35226 virtual methods in base classes but are not explicitly marked as
35227 virtual. */
35232 }
35238 }
35239 /* This builds the processor_model struct type defined in
35240 libgcc/config/i386/cpuinfo.c */
35242 static tree
35244 {
35251 /* The first 3 fields are unsigned int. */
35253 {
35259 }
35261 /* The last field is an array of unsigned integers of size one. */
35272 }
35274 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
35276 static tree
35278 {
35279 tree new_decl;
35282 VAR_DECL,
35284 type);
35297 }
35299 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
35300 into an integer defined in libgcc/config/i386/cpuinfo.c */
35302 static tree
35304 {
35310 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
35311 enum processor_features
35312 {
35314 F_MMX,
35315 F_POPCNT,
35316 F_SSE,
35317 F_SSE2,
35318 F_SSE3,
35319 F_SSSE3,
35320 F_SSE4_1,
35321 F_SSE4_2,
35322 F_AVX,
35323 F_AVX2,
35324 F_SSE4_A,
35325 F_FMA4,
35326 F_XOP,
35327 F_FMA,
35328 F_AVX512F,
35329 F_BMI,
35330 F_BMI2,
35331 F_MAX
35332 };
35334 /* These are the values for vendor types and cpu types and subtypes
35335 in cpuinfo.c. Cpu types and subtypes should be subtracted by
35336 the corresponding start value. */
35337 enum processor_model
35338 {
35340 M_AMD,
35341 M_CPU_TYPE_START,
35342 M_INTEL_BONNELL,
35343 M_INTEL_CORE2,
35344 M_INTEL_COREI7,
35345 M_AMDFAM10H,
35346 M_AMDFAM15H,
35347 M_INTEL_SILVERMONT,
35348 M_INTEL_KNL,
35349 M_AMD_BTVER1,
35350 M_AMD_BTVER2,
35351 M_CPU_SUBTYPE_START,
35352 M_INTEL_COREI7_NEHALEM,
35353 M_INTEL_COREI7_WESTMERE,
35354 M_INTEL_COREI7_SANDYBRIDGE,
35355 M_AMDFAM10H_BARCELONA,
35356 M_AMDFAM10H_SHANGHAI,
35357 M_AMDFAM10H_ISTANBUL,
35358 M_AMDFAM15H_BDVER1,
35359 M_AMDFAM15H_BDVER2,
35360 M_AMDFAM15H_BDVER3,
35361 M_AMDFAM15H_BDVER4,
35362 M_INTEL_COREI7_IVYBRIDGE,
35363 M_INTEL_COREI7_HASWELL,
35364 M_INTEL_COREI7_BROADWELL
35365 };
35367 static struct _arch_names_table
35368 {
35371 }
35373 {
35400 };
35402 static struct _isa_names_table
35403 {
35406 }
35408 {
35427 };
35441 {
35442 /* *args must be a expr that can contain other EXPRS leading to a
35443 STRING_CST. */
35445 {
35448 }
35450 }
35455 {
35456 tree ref;
35457 tree field;
35458 tree final;
35461 unsigned int NUM_ARCH_NAMES
35470 {
35474 }
35479 /* CPU types are stored in the next field. */
35482 {
35485 }
35487 /* CPU subtypes are stored in the next field. */
35489 {
35492 }
35494 /* Get the appropriate field in __cpu_model. */
35498 /* Check the value. */
35502 }
35504 {
35505 tree ref;
35506 tree array_elt;
35507 tree field;
35508 tree final;
35511 unsigned int NUM_ISA_NAMES
35520 {
35524 }
35527 /* Get the last field, which is __cpu_features. */
35531 /* Get the appropriate field: __cpu_model.__cpu_features */
35535 /* Access the 0th element of __cpu_features array. */
35540 /* Return __cpu_model.__cpu_features[0] & field_val */
35544 }
35546 }
35548 static tree
35551 {
35553 {
35558 {
35561 }
35562 }
35564 #ifdef SUBTARGET_FOLD_BUILTIN
35566 #endif
35569 }
35571 /* Make builtins to detect cpu type and features supported. NAME is
35572 the builtin name, CODE is the builtin code, and FTYPE is the function
35573 type of the builtin. */
35575 static void
35578 {
35579 tree decl;
35580 tree type;
35588 }
35590 /* Make builtins to get CPU type and features supported. The created
35591 builtins are :
35593 __builtin_cpu_init (), to detect cpu type and features,
35594 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
35595 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
35596 */
35598 static void
35600 {
35607 }
35609 /* Internal method for ix86_init_builtins. */
35611 static void
35613 {
35625 sysv_va_ref =
35628 fnvoid_va_end_ms =
35630 fnvoid_va_start_ms =
35632 fnvoid_va_end_sysv =
35634 fnvoid_va_start_sysv =
35636 NULL_TREE);
35637 fnvoid_va_copy_ms =
35639 NULL_TREE);
35640 fnvoid_va_copy_sysv =
35656 }
35658 static void
35660 {
35663 /* The __float80 type. */
35666 {
35667 /* The __float80 type. */
35672 }
35675 /* The __float128 type. */
35681 /* This macro is built by i386-builtin-types.awk. */
35682 DEFINE_BUILTIN_PRIMITIVE_TYPES;
35683 }
35685 static void
35687 {
35688 tree t;
35692 /* Builtins to get CPU type and features. */
35695 /* TFmode support builtins. */
35701 /* We will expand them to normal call if SSE isn't available since
35702 they are used by libgcc. */
35722 #ifdef SUBTARGET_INIT_BUILTINS
35723 SUBTARGET_INIT_BUILTINS;
35724 #endif
35725 }
35727 /* Return the ix86 builtin for CODE. */
35729 static tree
35731 {
35736 }
35738 /* Errors in the source file can cause expand_expr to return const0_rtx
35739 where we expect a vector. To avoid crashing, use one of the vector
35740 clear instructions. */
35741 static rtx
35743 {
35747 }
35749 /* Fixup modeless constants to fit required mode. */
35750 static rtx
35752 {
35756 }
35758 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
35760 static rtx
35762 {
35763 rtx pat;
35783 {
35787 }
35801 }
35803 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
35805 static rtx
35809 {
35810 rtx pat;
35818 rtx op;
35819 machine_mode mode;
35825 {
35905 }
35915 {
35922 {
35924 {
35927 {
35945 xop_rotl:
35947 {
35950 gcc_checking_assert
35952 }
35953 else
35954 {
35955 gcc_checking_assert
35966 }
35970 }
35971 }
35972 }
35973 else
35974 {
35975 non_constant:
35979 /* If we aren't optimizing, only allow one memory operand to be
35980 generated. */
35982 num_memory++;
35990 }
35994 }
35997 {
36008 else
36009 {
36015 }
36028 }
36035 }
36037 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
36038 insns with vec_merge. */
36040 static rtx
36042 rtx target)
36043 {
36044 rtx pat;
36071 }
36073 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
36075 static rtx
36078 {
36079 rtx pat;
36084 rtx op2;
36095 /* Swap operands if we have a comparison that isn't available in
36096 hardware. */
36118 }
36120 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
36122 static rtx
36124 rtx target)
36125 {
36126 rtx pat;
36140 /* Swap operands if we have a comparison that isn't available in
36141 hardware. */
36163 const0_rtx)));
36166 }
36168 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
36170 static rtx
36172 rtx target)
36173 {
36174 rtx pat;
36199 }
36201 static rtx
36204 {
36205 rtx pat;
36210 rtx op2;
36237 }
36239 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
36241 static rtx
36243 rtx target)
36244 {
36245 rtx pat;
36277 const0_rtx)));
36280 }
36282 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
36284 static rtx
36287 {
36288 rtx pat;
36326 {
36329 }
36332 {
36341 }
36343 {
36352 }
36353 else
36354 {
36361 }
36369 {
36374 emit_insn
36378 FLAGS_REG),
36379 const0_rtx)));
36381 }
36382 else
36384 }
36387 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
36389 static rtx
36392 {
36393 rtx pat;
36421 {
36424 }
36427 {
36436 }
36438 {
36447 }
36448 else
36449 {
36456 }
36464 {
36469 emit_insn
36473 FLAGS_REG),
36474 const0_rtx)));
36476 }
36477 else
36479 }
36481 /* Subroutine of ix86_expand_builtin to take care of insns with
36482 variable number of operands. */
36484 static rtx
36487 {
36493 struct
36494 {
36495 rtx op;
36496 machine_mode mode;
36507 {
37217 }
37222 {
37225 }
37228 {
37235 }
37236 else
37237 {
37240 }
37243 {
37250 {
37251 /* SIMD shift insns take either an 8-bit immediate or
37252 register as count. But builtin functions take int as
37253 count. If count doesn't match, we put it in register. */
37255 {
37259 }
37260 }
37263 {
37266 {
37375 {
37379 {
37382 }
37388 }
37390 }
37391 }
37392 else
37393 {
37397 /* If we aren't optimizing, only allow one memory operand to
37398 be generated. */
37400 num_memory++;
37405 {
37408 }
37409 else
37410 {
37413 }
37414 }
37418 }
37421 {
37446 }
37453 }
37455 /* Transform pattern of following layout:
37456 (parallel [
37457 set (A B)
37458 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
37459 ])
37460 into:
37461 (set (A B))
37463 Or:
37464 (parallel [ A B
37465 ...
37466 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
37467 ...
37468 ])
37469 into:
37470 (parallel [ A B ... ]) */
37472 static rtx
37474 {
37481 {
37490 }
37491 else
37492 {
37498 {
37503 }
37505 /* No more than 1 occurence was removed. */
37509 }
37510 }
37512 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
37513 with rounding. */
37514 static rtx
37517 {
37534 /* See avxintrin.h for values. */
37536 {
37540 };
37542 {
37547 };
37550 {
37553 }
37555 {
37558 }
37561 {
37564 }
37587 ? CODE_FOR_sse_ucomi_round
37594 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
37596 {
37602 }
37603 else
37604 {
37607 }
37612 set_dst,
37613 const0_rtx)));
37616 }
37618 static rtx
37621 {
37622 rtx pat;
37624 struct
37625 {
37626 rtx op;
37627 machine_mode mode;
37636 {
37719 }
37729 {
37736 {
37738 {
37740 {
37756 }
37757 }
37758 }
37760 {
37762 {
37765 }
37767 /* If there is no rounding use normal version of the pattern. */
37770 }
37771 else
37772 {
37779 {
37782 }
37783 else
37784 {
37787 }
37788 }
37792 }
37795 {
37820 }
37830 }
37832 /* Subroutine of ix86_expand_builtin to take care of special insns
37833 with variable number of operands. */
37835 static rtx
37838 {
37839 tree arg;
37843 struct
37844 {
37845 rtx op;
37846 machine_mode mode;
37855 {
37895 {
37903 }
37922 /* Reserve memory operand for target. */
37925 {
37926 /* These builtins and instructions require the memory
37927 to be properly aligned. */
37946 }
37975 {
37976 /* These builtins and instructions require the memory
37977 to be properly aligned. */
37994 }
37995 /* FALLTHRU */
38033 /* Reserve memory operand for target. */
38060 {
38061 /* These builtins and instructions require the memory
38062 to be properly aligned. */
38085 }
38098 }
38103 {
38108 {
38111 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
38112 on it. Try to improve it using get_pointer_alignment,
38113 and if the special builtin is one that requires strict
38114 mode alignment, also from it's GET_MODE_ALIGNMENT.
38115 Failure to do so could lead to ix86_legitimate_combined_insn
38116 rejecting all changes to such insns. */
38122 }
38123 else
38126 }
38127 else
38128 {
38135 }
38138 {
38147 {
38149 {
38155 else
38158 }
38159 }
38160 else
38161 {
38163 {
38164 /* This must be the memory operand. */
38167 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
38168 on it. Try to improve it using get_pointer_alignment,
38169 and if the special builtin is one that requires strict
38170 mode alignment, also from it's GET_MODE_ALIGNMENT.
38171 Failure to do so could lead to ix86_legitimate_combined_insn
38172 rejecting all changes to such insns. */
38178 }
38179 else
38180 {
38181 /* This must be register. */
38189 else
38190 {
38193 }
38194 }
38195 }
38199 }
38202 {
38217 }
38223 }
38225 /* Return the integer constant in ARG. Constrain it to be in the range
38226 of the subparts of VEC_TYPE; issue an error if not. */
38228 static int
38230 {
38235 {
38238 }
38241 }
38243 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38244 ix86_expand_vector_init. We DO have language-level syntax for this, in
38245 the form of (type){ init-list }. Except that since we can't place emms
38246 instructions from inside the compiler, we can't allow the use of MMX
38247 registers unless the user explicitly asks for it. So we do *not* define
38248 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
38249 we have builtins invoked by mmintrin.h that gives us license to emit
38250 these sorts of instructions. */
38252 static rtx
38254 {
38264 {
38267 }
38274 }
38276 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38277 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
38278 had a language-level syntax for referencing vector elements. */
38280 static rtx
38282 {
38286 rtx op0;
38306 }
38308 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38309 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
38310 a language-level syntax for referencing vector elements. */
38312 static rtx
38314 {
38338 /* OP0 is the source of these builtin functions and shouldn't be
38339 modified. Create a copy, use it and return it as target. */
38345 }
38347 /* Emit conditional move of SRC to DST with condition
38348 OP1 CODE OP2. */
38349 static void
38351 {
38352 rtx t;
38355 {
38359 }
38360 else
38361 {
38367 }
38368 }
38370 /* Choose max of DST and SRC and put it to DST. */
38371 static void
38373 {
38375 }
38377 /* Expand an expression EXP that calls a built-in function,
38378 with result going to TARGET if that's convenient
38379 (and in mode MODE if that's convenient).
38380 SUBTARGET may be used as the target for computing one of EXP's operands.
38381 IGNORE is nonzero if the value is to be ignored. */
38383 static rtx
38386 {
38396 /* For CPU builtins that can be folded, fold first and expand the fold. */
38398 {
38400 {
38401 /* Make it call __cpu_indicator_init in libgcc. */
38407 }
38410 {
38415 }
38416 }
38418 /* Determine whether the builtin function is available under the current ISA.
38419 Originally the builtin was not created if it wasn't applicable to the
38420 current ISA based on the command line switches. With function specific
38421 options, we need to check in the context of the function making the call
38422 whether it is supported. */
38425 {
38431 else
38432 {
38436 }
38438 }
38441 {
38459 /* Builtin arg1 is size of block but instruction op1 should
38460 be (size - 1). */
38551 /* If no bounds were specified for returned value,
38552 then use INIT bounds. It usually happens when
38553 some built-in function is expanded. */
38555 {
38564 }
38570 {
38573 /* Return value and lb. */
38575 /* Bounds. */
38577 /* Size. */
38584 /* Size was passed but we need to use (size - 1) as for bndmk. */
38588 /* Add LB to size and inverse to get UB. */
38598 /* We need to move bounds to memory before any computations. */
38601 else
38602 {
38605 }
38607 /* Generate mem expression to be used for access to LB and UB. */
38613 /* Compute LB. */
38618 /* Compute UB. UB is stored in 1's complement form. Therefore
38619 we also use max here. */
38628 }
38631 {
38649 /* Put first bounds to temporaries. */
38653 {
38657 }
38658 else
38659 {
38663 }
38665 /* Put second bounds to temporaries. */
38669 {
38673 }
38674 else
38675 {
38679 }
38681 /* Compute LB. */
38685 /* Compute UB. UB is stored in 1's complement form. Therefore
38686 we also use max here. */
38693 }
38696 {
38697 tree name;
38698 rtx symbol;
38716 }
38719 {
38730 /* We need to move bounds to memory first. */
38733 else
38734 {
38737 }
38739 /* Generate mem expression to access LB and load it. */
38744 }
38747 {
38758 /* We need to move bounds to memory first. */
38761 else
38762 {
38765 }
38767 /* Generate mem expression to access UB. */
38770 /* We need to inverse all bits of UB. */
38777 }
38782 ? CODE_FOR_mmx_maskmovq
38784 /* Note the arg order is different from the operand order. */
38905 {
38906 REAL_VALUE_TYPE inf;
38907 rtx tmp;
38919 }
38929 {
38935 insn = (TARGET_64BIT
38939 }
38941 {
38942 insn = (TARGET_64BIT
38946 }
38947 else
38948 {
38951 insn = (TARGET_64BIT
38959 {
38962 }
38964 }
38967 {
38968 /* mode is VOIDmode if __builtin_rd* has been called
38969 without lhs. */
38973 }
38976 {
38981 }
38994 {
39015 }
39021 {
39024 }
39050 {
39053 }
39059 {
39063 {
39102 }
39107 }
39108 else
39109 {
39111 {
39132 }
39134 }
39164 ? CODE_FOR_tbm_bextri_si
39167 {
39170 }
39171 else
39172 {
39181 }
39197 rdrand_step:
39204 {
39207 }
39213 /* Emit SImode conditional move. */
39215 {
39218 }
39221 else
39229 const0_rtx);
39248 rdseed_step:
39255 {
39258 }
39264 const0_rtx);
39293 addcarryx:
39301 /* Generate CF from input operand. */
39306 /* Gen ADCX instruction to compute X+Y+CF. */
39321 /* Store the result. */
39324 {
39327 }
39330 /* Return current CF value. */
39372 kortest:
39386 /* Emit kortest. */
39388 /* And use setcc to return result from flags. */
39646 gather_gen:
39647 rtx half;
39660 /* Note the arg order is different from the operand order. */
39671 else
39675 {
39699 else
39706 {
39711 }
39720 else
39727 {
39732 }
39736 }
39738 /* Force memory operand only with base register here. But we
39739 don't want to do it on memory operand for other builtin
39740 functions. */
39753 {
39756 }
39757 else
39758 {
39761 }
39763 {
39766 }
39768 /* Optimize. If mask is known to have all high bits set,
39769 replace op0 with pc_rtx to signal that the instruction
39770 overwrites the whole destination and doesn't use its
39771 previous contents. */
39773 {
39775 {
39778 }
39780 {
39783 {
39787 negative++;
39790 negative++;
39791 }
39794 }
39797 {
39798 /* Recognize also when mask is like:
39799 __v2df src = _mm_setzero_pd ();
39800 __v2df mask = _mm_cmpeq_pd (src, src);
39801 or
39802 __v8sf src = _mm256_setzero_ps ();
39803 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
39804 as that is a cheaper way to load all ones into
39805 a register than having to load a constant from
39806 memory. */
39809 {
39814 {
39821 /* FALLTHRU */
39831 }
39832 }
39833 }
39834 }
39842 {
39868 }
39871 scatter_gen:
39887 /* Force memory operand only with base register here. But we
39888 don't want to do it on memory operand for other builtin
39889 functions. */
39898 {
39901 }
39902 else
39903 {
39906 }
39915 {
39918 }
39927 vec_prefetch_gen:
39947 {
39950 }
39952 {
39955 }
39960 /* Force memory operand only with base register here. But we
39961 don't want to do it on memory operand for other builtin
39962 functions. */
39969 {
39972 }
39975 {
39978 }
39994 {
39997 }
40003 }
40016 {
40020 /* Emit a normal call if SSE isn't available. */
40024 }
40053 }
40055 /* This returns the target-specific builtin with code CODE if
40056 current_function_decl has visibility on this builtin, which is checked
40057 using isa flags. Returns NULL_TREE otherwise. */
40060 {
40064 /* Determine the isa flags of current_function_decl. */
40076 else
40078 }
40080 /* Return function decl for target specific builtin
40081 for given MPX builtin passed i FCODE. */
40082 static tree
40084 {
40086 {
40122 }
40125 }
40127 /* Helper function for ix86_load_bounds and ix86_store_bounds.
40129 Return an address to be used to load/store bounds for pointer
40130 passed in SLOT.
40132 SLOT_NO is an integer constant holding number of a target
40133 dependent special slot to be used in case SLOT is not a memory.
40135 SPECIAL_BASE is a pointer to be used as a base of fake address
40136 to access special slots in Bounds Table. SPECIAL_BASE[-1],
40137 SPECIAL_BASE[-2] etc. will be used as fake pointer locations. */
40139 static rtx
40141 {
40144 /* NULL slot means we pass bounds for pointer not passed to the
40145 function at all. Register slot means we pass pointer in a
40146 register. In both these cases bounds are passed via Bounds
40147 Table. Since we do not have actual pointer stored in memory,
40148 we have to use fake addresses to access Bounds Table. We
40149 start with (special_base - sizeof (void*)) and decrease this
40150 address by pointer size to get addresses for other slots. */
40152 {
40156 }
40157 /* If pointer is passed in a memory then its address is used to
40158 access Bounds Table. */
40160 {
40164 }
40165 else
40169 }
40171 /* Expand pass uses this hook to load bounds for function parameter
40172 PTR passed in SLOT in case its bounds are not passed in a register.
40174 If SLOT is a memory, then bounds are loaded as for regular pointer
40175 loaded from memory. PTR may be NULL in case SLOT is a memory.
40176 In such case value of PTR (if required) may be loaded from SLOT.
40178 If SLOT is NULL or a register then SLOT_NO is an integer constant
40179 holding number of the target dependent special slot which should be
40180 used to obtain bounds.
40182 Return loaded bounds. */
40184 static rtx
40186 {
40188 rtx addr;
40190 /* Get address to be used to access Bounds Table. Special slots start
40191 at the location of return address of the current function. */
40194 /* Load pointer value from a memory if we don't have it. */
40196 {
40199 }
40206 }
40208 /* Expand pass uses this hook to store BOUNDS for call argument PTR
40209 passed in SLOT in case BOUNDS are not passed in a register.
40211 If SLOT is a memory, then BOUNDS are stored as for regular pointer
40212 stored in memory. PTR may be NULL in case SLOT is a memory.
40213 In such case value of PTR (if required) may be loaded from SLOT.
40215 If SLOT is NULL or a register then SLOT_NO is an integer constant
40216 holding number of the target dependent special slot which should be
40217 used to store BOUNDS. */
40219 static void
40221 {
40222 rtx addr;
40224 /* Get address to be used to access Bounds Table. Special slots start
40225 at the location of return address of a called function. */
40228 /* Load pointer value from a memory if we don't have it. */
40230 {
40233 }
40242 }
40244 /* Load and return bounds returned by function in SLOT. */
40246 static rtx
40248 {
40249 rtx res;
40256 }
40258 /* Store BOUNDS returned by function into SLOT. */
40260 static void
40262 {
40265 }
40267 /* Returns a function decl for a vectorized version of the builtin function
40268 with builtin function code FN and the result vector type TYPE, or NULL_TREE
40269 if it is not available. */
40271 static tree
40273 tree type_in)
40274 {
40290 {
40293 {
40300 }
40305 {
40308 }
40313 {
40320 }
40326 /* The round insn does not trap on denormals. */
40331 {
40338 }
40344 /* The round insn does not trap on denormals. */
40349 {
40354 }
40360 /* The round insn does not trap on denormals. */
40365 {
40372 }
40378 /* The round insn does not trap on denormals. */
40383 {
40388 }
40395 {
40400 }
40407 {
40412 }
40418 /* The round insn does not trap on denormals. */
40423 {
40430 }
40436 /* The round insn does not trap on denormals. */
40441 {
40446 }
40451 {
40458 }
40463 {
40470 }
40474 /* The round insn does not trap on denormals. */
40479 {
40484 }
40488 /* The round insn does not trap on denormals. */
40493 {
40498 }
40502 /* The round insn does not trap on denormals. */
40507 {
40512 }
40516 /* The round insn does not trap on denormals. */
40521 {
40526 }
40530 /* The round insn does not trap on denormals. */
40535 {
40540 }
40544 /* The round insn does not trap on denormals. */
40549 {
40554 }
40558 /* The round insn does not trap on denormals. */
40563 {
40568 }
40572 /* The round insn does not trap on denormals. */
40577 {
40582 }
40586 /* The round insn does not trap on denormals. */
40591 {
40596 }
40600 /* The round insn does not trap on denormals. */
40605 {
40610 }
40615 {
40620 }
40625 {
40630 }
40635 }
40637 /* Dispatch to a handler for a vectorization library. */
40640 type_in);
40643 }
40645 /* Handler for an SVML-style interface to
40646 a library with vectorized intrinsics. */
40648 static tree
40650 {
40658 /* The SVML is suitable for unsafe math only. */
40671 {
40718 }
40727 {
40730 }
40731 else
40734 /* Convert to uppercase. */
40739 args;
40741 arity++;
40745 else
40748 /* Build a function declaration for the vectorized function. */
40757 }
40759 /* Handler for an ACML-style interface to
40760 a library with vectorized intrinsics. */
40762 static tree
40764 {
40772 /* The ACML is 64bits only and suitable for unsafe math only as
40773 it does not correctly support parts of IEEE with the required
40774 precision such as denormals. */
40788 {
40818 }
40825 args;
40827 arity++;
40831 else
40834 /* Build a function declaration for the vectorized function. */
40843 }
40845 /* Returns a decl of a function that implements gather load with
40846 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
40847 Return NULL_TREE if it is not available. */
40849 static tree
40852 {
40868 /* v*gather* insn sign extends index to pointer mode. */
40880 {
40884 else
40890 else
40896 else
40902 else
40908 else
40914 else
40920 else
40926 else
40932 else
40938 else
40944 else
40950 else
40955 }
40958 }
40960 /* Returns a code for a target-specific builtin that implements
40961 reciprocal of the function, or NULL_TREE if not available. */
40963 static tree
40965 {
40972 /* Machine dependent builtins. */
40974 {
40975 /* Vectorized version of sqrt to rsqrt conversion. */
40984 }
40985 else
40986 /* Normal builtins. */
40988 {
40989 /* Sqrt to rsqrt conversion. */
40995 }
40996 }
40997 \f
40998 /* Helper for avx_vpermilps256_operand et al. This is also used by
40999 the expansion functions to turn the parallel back into a mask.
41000 The return value is 0 for no match and the imm8+1 for a match. */
41002 int
41004 {
41012 /* Validate that all of the elements are constants, and not totally
41013 out of range. Copy the data into an integral array to make the
41014 subsequent checks easier. */
41016 {
41026 }
41029 {
41031 /* In the 512-bit DFmode case, we can only move elements within
41032 a 128-bit lane. First fill the second part of the mask,
41033 then fallthru. */
41035 {
41039 }
41041 {
41045 }
41046 /* FALLTHRU */
41049 /* In the 256-bit DFmode case, we can only move elements within
41050 a 128-bit lane. */
41052 {
41056 }
41058 {
41062 }
41066 /* In 512 bit SFmode case, permutation in the upper 256 bits
41067 must mirror the permutation in the lower 256-bits. */
41071 /* FALLTHRU */
41074 /* In 256 bit SFmode case, we have full freedom of
41075 movement within the low 128-bit lane, but the high 128-bit
41076 lane must mirror the exact same pattern. */
41081 /* FALLTHRU */
41085 /* In the 128-bit case, we've full freedom in the placement of
41086 the elements from the source operand. */
41093 }
41095 /* Make sure success has a non-zero value by adding one. */
41097 }
41099 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
41100 the expansion functions to turn the parallel back into a mask.
41101 The return value is 0 for no match and the imm8+1 for a match. */
41103 int
41105 {
41113 /* Validate that all of the elements are constants, and not totally
41114 out of range. Copy the data into an integral array to make the
41115 subsequent checks easier. */
41117 {
41127 }
41129 /* Validate that the halves of the permute are halves. */
41137 /* Reconstruct the mask. */
41139 {
41145 }
41147 /* Make sure success has a non-zero value by adding one. */
41149 }
41150 \f
41151 /* Return a register priority for hard reg REGNO. */
41152 static int
41154 {
41155 /* ebp and r13 as the base always wants a displacement, r12 as the
41156 base always wants an index. So discourage their usage in an
41157 address. */
41162 /* New x86-64 int registers result in bigger code size. Discourage
41163 them. */
41166 /* New x86-64 SSE registers result in bigger code size. Discourage
41167 them. */
41170 /* Usage of AX register results in smaller code. Prefer it. */
41174 }
41176 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
41178 Put float CONST_DOUBLE in the constant pool instead of fp regs.
41179 QImode must go into class Q_REGS.
41180 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
41181 movdf to do mem-to-mem moves through integer regs. */
41183 static reg_class_t
41185 {
41188 /* We're only allowed to return a subclass of CLASS. Many of the
41189 following checks fail for NO_REGS, so eliminate that early. */
41193 /* All classes can load zeros. */
41197 /* Force constants into memory if we are loading a (nonzero) constant into
41198 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
41199 instructions to load from a constant. */
41206 /* Prefer SSE regs only, if we can use them for math. */
41210 /* Floating-point constants need more complex checks. */
41212 {
41213 /* General regs can load everything. */
41217 /* Floats can load 0 and 1 plus some others. Note that we eliminated
41218 zero above. We only want to wind up preferring 80387 registers if
41219 we plan on doing computation with them. */
41222 {
41223 /* Limit class to non-sse. */
41232 }
41235 }
41237 /* Generally when we see PLUS here, it's the function invariant
41238 (plus soft-fp const_int). Which can only be computed into general
41239 regs. */
41243 /* QImode constants are easy to load, but non-constant QImode data
41244 must go into Q_REGS. */
41246 {
41252 }
41255 }
41257 /* Discourage putting floating-point values in SSE registers unless
41258 SSE math is being used, and likewise for the 387 registers. */
41259 static reg_class_t
41261 {
41264 /* Restrict the output reload class to the register bank that we are doing
41265 math on. If we would like not to return a subset of CLASS, reject this
41266 alternative: if reload cannot do this, it will still use its choice. */
41272 {
41277 else
41279 }
41282 }
41284 static reg_class_t
41287 {
41288 /* Double-word spills from general registers to non-offsettable memory
41289 references (zero-extended addresses) require special handling. */
41295 {
41297 ? CODE_FOR_reload_noff_load
41299 /* Add the cost of moving address to a temporary. */
41303 }
41305 /* QImode spills from non-QI registers require
41306 intermediate register on 32bit targets. */
41312 {
41317 else
41323 /* Return Q_REGS if the operand is in memory. */
41326 }
41328 /* This condition handles corner case where an expression involving
41329 pointers gets vectorized. We're trying to use the address of a
41330 stack slot as a vector initializer.
41332 (set (reg:V2DI 74 [ vect_cst_.2 ])
41333 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
41335 Eventually frame gets turned into sp+offset like this:
41337 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41338 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41339 (const_int 392 [0x188]))))
41341 That later gets turned into:
41343 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41344 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41345 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
41347 We'll have the following reload recorded:
41349 Reload 0: reload_in (DI) =
41350 (plus:DI (reg/f:DI 7 sp)
41351 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
41352 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41353 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
41354 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
41355 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41356 reload_reg_rtx: (reg:V2DI 22 xmm1)
41358 Which isn't going to work since SSE instructions can't handle scalar
41359 additions. Returning GENERAL_REGS forces the addition into integer
41360 register and reload can handle subsequent reloads without problems. */
41368 }
41370 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
41372 static bool
41374 {
41376 {
41392 }
41395 }
41397 /* If we are copying between general and FP registers, we need a memory
41398 location. The same is true for SSE and MMX registers.
41400 To optimize register_move_cost performance, allow inline variant.
41402 The macro can't work reliably when one of the CLASSES is class containing
41403 registers from multiple units (SSE, MMX, integer). We avoid this by never
41404 combining those units in single alternative in the machine description.
41405 Ensure that this constraint holds to avoid unexpected surprises.
41407 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
41408 enforce these sanity checks. */
41413 {
41422 {
41425 }
41430 /* Between mask and general, we have moves no larger than word size. */
41435 /* ??? This is a lie. We do have moves between mmx/general, and for
41436 mmx/sse2. But by saying we need secondary memory we discourage the
41437 register allocator from using the mmx registers unless needed. */
41442 {
41443 /* SSE1 doesn't have any direct moves from other classes. */
41447 /* If the target says that inter-unit moves are more expensive
41448 than moving through memory, then don't generate them. */
41453 /* Between SSE and general, we have moves no larger than word size. */
41456 }
41459 }
41461 bool
41464 {
41466 }
41468 /* Implement the TARGET_CLASS_MAX_NREGS hook.
41470 On the 80386, this is the size of MODE in words,
41471 except in the FP regs, where a single reg is always enough. */
41473 static unsigned char
41475 {
41477 {
41482 else
41484 }
41485 else
41486 {
41489 else
41491 }
41492 }
41494 /* Return true if the registers in CLASS cannot represent the change from
41495 modes FROM to TO. */
41497 bool
41500 {
41504 /* x87 registers can't do subreg at all, as all values are reformatted
41505 to extended precision. */
41510 {
41511 /* Vector registers do not support QI or HImode loads. If we don't
41512 disallow a change to these modes, reload will assume it's ok to
41513 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
41514 the vec_dupv4hi pattern. */
41517 }
41520 }
41522 /* Return the cost of moving data of mode M between a
41523 register and memory. A value of 2 is the default; this cost is
41524 relative to those in `REGISTER_MOVE_COST'.
41526 This function is used extensively by register_move_cost that is used to
41527 build tables at startup. Make it inline in this case.
41528 When IN is 2, return maximum of in and out move cost.
41530 If moving between registers and memory is more expensive than
41531 between two registers, you should define this macro to express the
41532 relative cost.
41534 Model also increased moving costs of QImode registers in non
41535 Q_REGS classes.
41536 */
41540 {
41543 {
41546 {
41558 }
41562 }
41564 {
41567 {
41579 }
41583 }
41585 {
41588 {
41597 }
41601 }
41603 {
41606 {
41612 else
41617 }
41618 else
41619 {
41624 else
41626 }
41633 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
41640 else
41644 }
41645 }
41647 static int
41650 {
41652 }
41655 /* Return the cost of moving data from a register in class CLASS1 to
41656 one in class CLASS2.
41658 It is not required that the cost always equal 2 when FROM is the same as TO;
41659 on some machines it is expensive to move between registers if they are not
41660 general registers. */
41662 static int
41664 reg_class_t class2_i)
41665 {
41669 /* In case we require secondary memory, compute cost of the store followed
41670 by load. In order to avoid bad register allocation choices, we need
41671 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
41674 {
41680 /* In case of copying from general_purpose_register we may emit multiple
41681 stores followed by single load causing memory size mismatch stall.
41682 Count this as arbitrarily high cost of 20. */
41687 /* In the case of FP/MMX moves, the registers actually overlap, and we
41688 have to switch modes in order to treat them differently. */
41694 }
41696 /* Moves between SSE/MMX and integer unit are expensive. */
41700 /* ??? By keeping returned value relatively high, we limit the number
41701 of moves between integer and MMX/SSE registers for all targets.
41702 Additionally, high value prevents problem with x86_modes_tieable_p(),
41703 where integer modes in MMX/SSE registers are not tieable
41704 because of missing QImode and HImode moves to, from or between
41705 MMX/SSE registers. */
41715 }
41717 /* Return TRUE if hard register REGNO can hold a value of machine-mode
41718 MODE. */
41720 bool
41722 {
41723 /* Flags and only flags can only hold CCmode values. */
41734 || (TARGET_AVX512BW
41739 {
41740 /* We implement the move patterns for all vector modes into and
41741 out of SSE registers, even when no operation instructions
41742 are available. */
41744 /* For AVX-512 we allow, regardless of regno:
41745 - XI mode
41746 - any of 512-bit wide vector mode
41747 - any scalar mode. */
41754 /* TODO check for QI/HI scalars. */
41755 /* AVX512VL allows sse regs16+ for 128/256 bit modes. */
41763 /* xmm16-xmm31 are only available for AVX-512. */
41767 /* OImode and AVX modes are available only when AVX is enabled. */
41774 }
41776 {
41777 /* We implement the move patterns for 3DNOW modes even in MMX mode,
41778 so if the register is available at all, then we can move data of
41779 the given mode into or out of it. */
41782 }
41785 {
41786 /* Take care for QImode values - they can be in non-QI regs,
41787 but then they do cause partial register stalls. */
41792 /* LRA checks if the hard register is OK for the given mode.
41793 QImode values can live in non-QI regs, so we allow all
41794 registers here. */
41798 }
41799 /* We handle both integer and floats in the general purpose registers. */
41806 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
41807 on to use that value in smaller contexts, this can easily force a
41808 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
41809 supporting DImode, allow it. */
41814 }
41816 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
41817 tieable integer mode. */
41819 static bool
41821 {
41823 {
41836 }
41837 }
41839 /* Return true if MODE1 is accessible in a register that can hold MODE2
41840 without copying. That is, all register classes that can hold MODE2
41841 can also hold MODE1. */
41843 bool
41845 {
41853 /* MODE2 being XFmode implies fp stack or general regs, which means we
41854 can tie any smaller floating point modes to it. Note that we do not
41855 tie this with TFmode. */
41859 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
41860 that we can tie it with SFmode. */
41864 /* If MODE2 is only appropriate for an SSE register, then tie with
41865 any other mode acceptable to SSE registers. */
41875 /* If MODE2 is appropriate for an MMX register, then tie
41876 with any other mode acceptable to MMX registers. */
41883 }
41885 /* Return the cost of moving between two registers of mode MODE. */
41887 static int
41889 {
41893 {
41925 }
41927 /* Return the cost of moving between two registers of mode MODE,
41928 assuming that the move will be in pieces of at most UNITS bytes. */
41930 }
41932 /* Compute a (partial) cost for rtx X. Return true if the complete
41933 cost has been computed, and false if subexpressions should be
41934 scanned. In either case, *TOTAL contains the cost result. */
41936 static bool
41939 {
41940 rtx mask;
41947 {
41951 {
41954 }
41966 && !(TARGET_64BIT
41971 else
41981 {
41991 }
41993 {
41996 {
42005 }
42006 }
42007 /* Fall back to (MEM (SYMBOL_REF)), since that's where
42008 it'll probably end up. Add a penalty for size. */
42015 /* The zero extensions is often completely free on x86_64, so make
42016 it as cheap as possible. */
42022 else
42034 {
42037 {
42040 }
42043 {
42046 }
42047 }
42048 /* FALLTHRU */
42055 {
42056 /* ??? Should be SSE vector operation cost. */
42057 /* At least for published AMD latencies, this really is the same
42058 as the latency for a simple fpu operation like fabs. */
42059 /* V*QImode is emulated with 1-11 insns. */
42061 {
42064 {
42065 /* For XOP we use vpshab, which requires a broadcast of the
42066 value to the variable shift insn. For constants this
42067 means a V16Q const in mem; even when we can perform the
42068 shift with one insn set the cost to prefer paddb. */
42070 {
42075 }
42077 }
42081 }
42082 else
42084 }
42086 {
42088 {
42091 else
42093 }
42094 else
42095 {
42098 else
42100 }
42101 }
42102 else
42103 {
42108 {
42109 /* Return the cost after shift-and truncation. */
42112 }
42113 else
42115 }
42119 {
42120 rtx sub;
42125 /* ??? SSE scalar/vector cost should be used here. */
42126 /* ??? Bald assumption that fma has the same cost as fmul. */
42130 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
42141 }
42145 {
42146 /* ??? SSE scalar cost should be used here. */
42149 }
42151 {
42154 }
42156 {
42157 /* ??? SSE vector cost should be used here. */
42160 }
42162 {
42163 /* V*QImode is emulated with 7-13 insns. */
42165 {
42172 }
42173 /* V*DImode is emulated with 5-8 insns. */
42175 {
42178 else
42180 }
42181 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
42182 insns, including two PMULUDQ. */
42185 else
42188 }
42189 else
42190 {
42195 {
42198 nbits++;
42199 }
42200 else
42201 /* This is arbitrary. */
42204 /* Compute costs correctly for widening multiplication. */
42208 {
42215 {
42219 else
42221 }
42225 }
42233 }
42240 /* ??? SSE cost should be used here. */
42245 /* ??? SSE vector cost should be used here. */
42247 else
42254 {
42259 {
42262 {
42270 }
42271 }
42274 {
42277 {
42283 }
42284 }
42286 {
42294 }
42295 }
42296 /* FALLTHRU */
42300 {
42301 /* ??? SSE cost should be used here. */
42304 }
42306 {
42309 }
42311 {
42312 /* ??? SSE vector cost should be used here. */
42315 }
42316 /* FALLTHRU */
42323 {
42330 }
42331 /* FALLTHRU */
42335 {
42336 /* ??? SSE cost should be used here. */
42339 }
42341 {
42344 }
42346 {
42347 /* ??? SSE vector cost should be used here. */
42350 }
42351 /* FALLTHRU */
42355 {
42356 /* ??? Should be SSE vector operation cost. */
42357 /* At least for published AMD latencies, this really is the same
42358 as the latency for a simple fpu operation like fabs. */
42360 }
42363 else
42372 {
42373 /* This kind of construct is implemented using test[bwl].
42374 Treat it as if we had an AND. */
42379 }
42389 /* ??? SSE cost should be used here. */
42394 /* ??? SSE vector cost should be used here. */
42400 /* ??? SSE cost should be used here. */
42405 /* ??? SSE vector cost should be used here. */
42417 /* ??? Assume all of these vector manipulation patterns are
42418 recognizable. In which case they all pretty much have the
42419 same cost. */
42424 /* This is masked instruction, assume the same cost,
42425 as nonmasked variant. */
42428 else
42434 }
42435 }
42437 #if TARGET_MACHO
42441 /* Given a symbol name and its associated stub, write out the
42442 definition of the stub. */
42444 void
42446 {
42451 /* For 64-bit we shouldn't get here. */
42454 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
42471 else
42478 {
42480 }
42482 {
42483 /* PIC stub. */
42484 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42490 }
42491 else
42494 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
42495 it needs no stub-binding-helper. */
42502 {
42505 }
42506 else
42511 /* N.B. Keep the correspondence of these
42512 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
42513 old-pic/new-pic/non-pic stubs; altering this will break
42514 compatibility with existing dylibs. */
42516 {
42517 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42519 }
42520 else
42521 /* 16-byte -mdynamic-no-pic stub. */
42527 }
42530 /* Order the registers for register allocator. */
42532 void
42534 {
42538 /* First allocate the local general purpose registers. */
42543 /* Global general purpose registers. */
42548 /* x87 registers come first in case we are doing FP math
42549 using them. */
42554 /* SSE registers. */
42560 /* Extended REX SSE registers. */
42564 /* Mask register. */
42568 /* MPX bound registers. */
42572 /* x87 registers. */
42580 /* Initialize the rest of array as we do not allocate some registers
42581 at all. */
42584 }
42586 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
42587 in struct attribute_spec handler. */
42588 static tree
42590 tree args,
42593 {
42598 {
42600 name);
42603 }
42605 {
42607 name);
42610 }
42612 {
42613 tree cst;
42617 {
42620 name);
42622 }
42625 {
42628 name);
42630 }
42633 }
42636 }
42638 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
42639 struct attribute_spec.handler. */
42640 static tree
42643 {
42648 {
42650 name);
42653 }
42655 /* Can combine regparm with all attributes but fastcall. */
42657 {
42659 {
42661 }
42664 }
42666 {
42668 {
42670 }
42673 }
42676 }
42678 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
42679 struct attribute_spec.handler. */
42680 static tree
42683 {
42686 {
42689 }
42690 else
42694 {
42696 name);
42698 }
42704 {
42706 name);
42708 }
42711 }
42713 static tree
42716 {
42718 {
42720 name);
42722 }
42724 }
42726 static bool
42728 {
42732 }
42734 /* Returns an expression indicating where the this parameter is
42735 located on entry to the FUNCTION. */
42737 static rtx
42739 {
42745 {
42750 else
42753 }
42758 {
42765 {
42770 }
42771 else
42772 {
42775 {
42781 }
42782 }
42784 }
42788 }
42790 /* Determine whether x86_output_mi_thunk can succeed. */
42792 static bool
42794 const_tree function)
42795 {
42796 /* 64-bit can handle anything. */
42800 /* For 32-bit, everything's fine if we have one free register. */
42804 /* Need a free register for vcall_offset. */
42808 /* Need a free register for GOT references. */
42812 /* Otherwise ok. */
42814 }
42816 /* Output the assembler code for a thunk function. THUNK_DECL is the
42817 declaration for the thunk function itself, FUNCTION is the decl for
42818 the target function. DELTA is an immediate constant offset to be
42819 added to THIS. If VCALL_OFFSET is nonzero, the word at
42820 *(*this + vcall_offset) should be added to THIS. */
42822 static void
42825 {
42833 else
42834 {
42840 else
42842 }
42846 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
42847 pull it in now and let DELTA benefit. */
42851 {
42852 /* Put the this parameter into %eax. */
42855 }
42856 else
42859 /* Adjust the this parameter by a fixed constant. */
42861 {
42866 {
42868 {
42872 }
42873 }
42876 }
42878 /* Adjust the this parameter by a value stored in the vtable. */
42880 {
42890 /* Adjust the this parameter. */
42894 {
42898 }
42905 vcall_mem));
42906 else
42908 }
42910 /* If necessary, drop THIS back to its stack slot. */
42916 {
42919 ;
42920 else
42921 {
42925 }
42926 }
42927 else
42928 {
42930 ;
42931 #if TARGET_MACHO
42933 {
42936 }
42938 else
42939 {
42947 }
42948 }
42950 /* Our sibling call patterns do not allow memories, because we have no
42951 predicate that can distinguish between frame and non-frame memory.
42952 For our purposes here, we can get away with (ab)using a jump pattern,
42953 because we're going to do no optimization. */
42955 {
42957 {
42963 }
42964 else
42966 }
42967 else
42968 {
42970 {
42971 // CM_LARGE_PIC always uses pseudo PIC register which is
42972 // uninitialized. Since FUNCTION is local and calling it
42973 // doesn't go through PLT, we use scratch register %r11 as
42974 // PIC register and initialize it here.
42979 }
42982 {
42988 }
42994 }
42997 /* Emit just enough of rest_of_compilation to get the insns emitted.
42998 Note that use_thunk calls assemble_start_function et al. */
43004 }
43006 static void
43008 {
43012 #if TARGET_MACHO
43014 #endif
43021 }
43023 int
43025 {
43026 machine_mode mode;
43037 }
43039 /* Print call to TARGET to FILE. */
43041 static void
43043 {
43046 else
43048 }
43050 /* Output assembler code to FILE to increment profiler label # LABELNO
43051 for profiling a function entry. */
43052 void
43054 {
43058 {
43059 #ifndef NO_PROFILE_COUNTERS
43061 #endif
43065 else
43067 }
43069 {
43070 #ifndef NO_PROFILE_COUNTERS
43073 #endif
43075 }
43076 else
43077 {
43078 #ifndef NO_PROFILE_COUNTERS
43081 #endif
43083 }
43086 {
43090 }
43091 }
43093 /* We don't have exact information about the insn sizes, but we may assume
43094 quite safely that we are informed about all 1 byte insns and memory
43095 address sizes. This is enough to eliminate unnecessary padding in
43096 99% of cases. */
43098 static int
43100 {
43106 /* Discard alignments we've emit and jump instructions. */
43111 /* Important case - calls are always 5 bytes.
43112 It is common to have many calls in the row. */
43121 /* For normal instructions we rely on get_attr_length being exact,
43122 with a few exceptions. */
43124 {
43128 {
43138 /* Otherwise trust get_attr_length. */
43140 }
43145 }
43148 else
43150 }
43152 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43154 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
43155 window. */
43157 static void
43159 {
43164 /* Look for all minimal intervals of instructions containing 4 jumps.
43165 The intervals are bounded by START and INSN. NBYTES is the total
43166 size of instructions in the interval including INSN and not including
43167 START. When the NBYTES is smaller than 16 bytes, it is possible
43168 that the end of START and INSN ends up in the same 16byte page.
43170 The smallest offset in the page INSN can start is the case where START
43171 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
43172 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
43174 Don't consider asm goto as jump, while it can contain a jump, it doesn't
43175 have to, control transfer to label(s) can be performed through other
43176 means, and also we estimate minimum length of all asm stmts as 0. */
43178 {
43182 {
43188 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
43189 already in the current 16 byte page, because otherwise
43190 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
43191 bytes to reach 16 byte boundary. */
43199 {
43201 {
43206 else
43209 }
43210 }
43212 }
43221 njumps++;
43222 else
43226 {
43231 else
43234 }
43241 {
43248 }
43249 }
43250 }
43251 #endif
43253 /* AMD Athlon works faster
43254 when RET is not destination of conditional jump or directly preceded
43255 by other jump instruction. We avoid the penalty by inserting NOP just
43256 before the RET instructions in such cases. */
43257 static void
43259 {
43260 edge e;
43261 edge_iterator ei;
43264 {
43277 {
43278 edge e;
43279 edge_iterator ei;
43284 {
43287 }
43288 }
43290 {
43296 /* Empty functions get branch mispredict even when
43297 the jump destination is not visible to us. */
43300 }
43302 {
43305 }
43306 }
43307 }
43309 /* Count the minimum number of instructions in BB. Return 4 if the
43310 number of instructions >= 4. */
43312 static int
43314 {
43318 /* Count number of instructions in this block. Return 4 if the number
43319 of instructions >= 4. */
43321 {
43322 /* Only happen in exit blocks. */
43330 {
43331 insn_count++;
43334 }
43335 }
43338 }
43341 /* Count the minimum number of instructions in code path in BB.
43342 Return 4 if the number of instructions >= 4. */
43344 static int
43346 {
43347 edge e;
43348 edge_iterator ei;
43351 /* Only bother counting instructions along paths with no
43352 more than 2 basic blocks between entry and exit. Given
43353 that BB has an edge to exit, determine if a predecessor
43354 of BB has an edge from entry. If so, compute the number
43355 of instructions in the predecessor block. If there
43356 happen to be multiple such blocks, compute the minimum. */
43359 {
43360 edge prev_e;
43361 edge_iterator prev_ei;
43364 {
43367 }
43369 {
43371 {
43376 }
43377 }
43378 }
43384 }
43386 /* Pad short function to 4 instructions. */
43388 static void
43390 {
43391 edge e;
43392 edge_iterator ei;
43395 {
43398 {
43401 /* Pad short function. */
43403 {
43406 /* Find epilogue. */
43415 /* Two NOPs count as one instruction. */
43418 }
43419 }
43420 }
43421 }
43423 /* Fix up a Windows system unwinder issue. If an EH region falls through into
43424 the epilogue, the Windows system unwinder will apply epilogue logic and
43425 produce incorrect offsets. This can be avoided by adding a nop between
43426 the last insn that can throw and the first insn of the epilogue. */
43428 static void
43430 {
43431 edge e;
43432 edge_iterator ei;
43435 {
43438 /* Find the beginning of the epilogue. */
43445 /* We only care about preceding insns that can throw. */
43450 /* Do not separate calls from their debug information. */
43456 else
43460 }
43461 }
43463 /* Implement machine specific optimizations. We implement padding of returns
43464 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
43465 static void
43467 {
43468 /* We are freeing block_for_insn in the toplev to keep compatibility
43469 with old MDEP_REORGS that are not CFG based. Recompute it now. */
43476 {
43481 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43484 #endif
43485 }
43486 }
43488 /* Return nonzero when QImode register that must be represented via REX prefix
43489 is used. */
43490 bool
43492 {
43500 }
43502 /* Return true when INSN mentions register that must be encoded using REX
43503 prefix. */
43504 bool
43506 {
43509 {
43514 }
43516 }
43518 /* If profitable, negate (without causing overflow) integer constant
43519 of mode MODE at location LOC. Return true in this case. */
43520 bool
43522 {
43523 HOST_WIDE_INT val;
43529 {
43531 /* DImode x86_64 constants must fit in 32 bits. */
43544 }
43546 /* Avoid overflows. */
43552 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
43553 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
43556 {
43559 }
43562 }
43564 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
43565 optabs would emit if we didn't have TFmode patterns. */
43567 void
43569 {
43604 }
43605 \f
43611 /* Get a vector mode of the same size as the original but with elements
43612 twice as wide. This is only guaranteed to apply to integral vectors. */
43616 {
43617 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
43622 }
43624 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
43625 fill target with val via vec_duplicate. */
43627 static bool
43629 {
43632 rtx dup;
43634 /* First attempt to recognize VAL as-is. */
43638 {
43640 /* If that fails, force VAL into a register. */
43651 }
43653 }
43655 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43656 with all elements equal to VAR. Return true if successful. */
43658 static bool
43661 {
43665 {
43670 /* FALLTHRU */
43690 {
43691 rtx x;
43698 }
43711 {
43715 permute:
43723 /* Extend to SImode using a paradoxical SUBREG. */
43727 /* Insert the SImode value as low element of a V4SImode vector. */
43736 }
43747 widen:
43748 /* Replicate the value once into the next wider mode and recurse. */
43749 {
43751 rtx x;
43768 }
43774 else
43775 {
43784 }
43791 else
43792 {
43801 }
43806 }
43807 }
43809 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43810 whose ONE_VAR element is VAR, and other elements are zero. Return true
43811 if successful. */
43813 static bool
43816 {
43817 machine_mode vsimode;
43818 rtx new_target;
43823 {
43825 /* For SSE4.1, we normally use vector set. But if the second
43826 element is zero and inter-unit moves are OK, we use movq
43827 instead. */
43829 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
43851 /* Use ix86_expand_vector_set in 64bit mode only. */
43856 }
43859 {
43864 }
43867 {
43872 /* FALLTHRU */
43887 else
43894 {
43895 /* We need to shuffle the value to the correct position, so
43896 create a new pseudo to store the intermediate result. */
43898 /* With SSE2, we can use the integer shuffle insns. */
43900 {
43902 const1_rtx,
43909 }
43911 /* Otherwise convert the intermediate result to V4SFmode and
43912 use the SSE1 shuffle instructions. */
43914 {
43917 }
43918 else
43922 const1_rtx,
43931 }
43946 widen:
43950 /* Zero extend the variable element to SImode and recurse. */
43963 }
43964 }
43966 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43967 consisting of the values in VALS. It is known that all elements
43968 except ONE_VAR are constants. Return true if successful. */
43970 static bool
43973 {
43975 machine_mode wmode;
43983 {
43988 /* For the two element vectors, it's just as easy to use
43989 the general case. */
43993 /* Use ix86_expand_vector_set in 64bit mode only. */
44015 widen:
44016 /* There's no way to set one QImode entry easily. Combine
44017 the variable value with its adjacent constant value, and
44018 promote to an HImode set. */
44021 {
44026 }
44027 else
44028 {
44031 }
44045 }
44050 }
44052 /* A subroutine of ix86_expand_vector_init_general. Use vector
44053 concatenate to handle the most general case: all values variable,
44054 and none identical. */
44056 static void
44059 {
44062 rtvec v;
44066 {
44069 {
44114 }
44126 {
44141 }
44146 {
44165 }
44170 {
44183 }
44186 half:
44187 /* FIXME: We process inputs backward to help RA. PR 36222. */
44191 {
44196 }
44200 {
44204 {
44208 }
44211 {
44215 }
44218 }
44220 {
44223 {
44227 }
44230 }
44231 else
44237 }
44238 }
44240 /* A subroutine of ix86_expand_vector_init_general. Use vector
44241 interleave to handle the most general case: all values variable,
44242 and none identical. */
44244 static void
44247 {
44256 {
44277 }
44280 {
44281 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
44285 /* Insert the SImode value as low element of V4SImode vector. */
44289 op0),
44291 const1_rtx);
44294 /* Cast the V4SImode vector back to a vector in orignal mode. */
44298 /* Load even elements into the second position. */
44302 const1_rtx));
44304 /* Cast vector to FIRST_IMODE vector. */
44307 }
44309 /* Interleave low FIRST_IMODE vectors. */
44311 {
44315 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
44318 }
44320 /* Interleave low SECOND_IMODE vectors. */
44322 {
44325 {
44330 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
44331 vector. */
44334 }
44337 /* FALLTHRU */
44344 /* Cast the SECOND_IMODE vector back to a vector on original
44345 mode. */
44351 }
44352 }
44354 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
44355 all values variable, and none identical. */
44357 static void
44360 {
44367 {
44372 /* FALLTHRU */
44400 half:
44423 quarter:
44449 /* FALLTHRU */
44455 /* Don't use ix86_expand_vector_init_interleave if we can't
44456 move from GPR to SSE register directly. */
44472 }
44474 {
44476 machine_mode inner_mode;
44486 {
44490 {
44496 else
44497 {
44502 }
44503 }
44506 }
44511 {
44517 }
44519 {
44525 }
44526 else
44528 }
44529 }
44531 /* Initialize vector TARGET via VALS. Suppress the use of MMX
44532 instructions unless MMX_OK is true. */
44534 void
44536 {
44543 rtx x;
44546 {
44556 }
44558 /* Constants are best loaded from the constant pool. */
44560 {
44563 }
44565 /* If all values are identical, broadcast the value. */
44571 /* Values where only one field is non-constant are best loaded from
44572 the pool and overwritten via move later. */
44574 {
44578 one_var))
44583 }
44586 }
44588 void
44590 {
44593 machine_mode half_mode;
44595 rtx tmp;
44597 = {
44604 };
44606 = {
44613 };
44617 {
44621 {
44626 else
44630 }
44642 else
44648 {
44651 /* For the two element vectors, we implement a VEC_CONCAT with
44652 the extraction of the other element. */
44659 else
44664 }
44673 {
44679 /* tmp = target = A B C D */
44681 /* target = A A B B */
44683 /* target = X A B B */
44685 /* target = A X C D */
44692 /* tmp = target = A B C D */
44694 /* tmp = X B C D */
44696 /* target = A B X D */
44703 /* tmp = target = A B C D */
44705 /* tmp = X B C D */
44707 /* target = A B X D */
44715 }
44723 /* Element 0 handled by vec_merge below. */
44725 {
44728 }
44731 {
44732 /* With SSE2, use integer shuffles to swap element 0 and ELT,
44733 store into element 0, then shuffle them back. */
44750 }
44751 else
44752 {
44753 /* For SSE1, we have to reuse the V4SF code. */
44757 }
44810 half:
44811 /* Compute offset. */
44817 /* Extract the half. */
44821 /* Put val in tmp at elt. */
44824 /* Put it back. */
44830 {
44836 }
44837 else
44841 {
44847 }
44848 else
44852 {
44858 }
44859 else
44863 {
44869 }
44870 else
44874 {
44880 }
44881 else
44885 {
44891 }
44892 else
44897 }
44900 {
44904 }
44905 else
44906 {
44915 }
44916 }
44918 void
44920 {
44924 rtx tmp;
44927 {
44932 /* FALLTHRU */
44945 {
44965 }
44977 {
44979 {
44999 }
45003 }
45004 else
45005 {
45006 /* For SSE1, we have to reuse the V4SF code. */
45010 }
45026 {
45030 else
45034 }
45039 {
45043 else
45047 }
45052 {
45056 else
45060 }
45065 {
45069 else
45073 }
45078 {
45082 else
45086 }
45091 {
45095 else
45099 }
45104 {
45108 else
45112 }
45117 {
45121 else
45125 }
45132 else
45141 else
45150 else
45159 else
45165 /* ??? Could extract the appropriate HImode element and shift. */
45168 }
45171 {
45175 /* Let the rtl optimizers know about the zero extension performed. */
45177 {
45180 }
45183 }
45184 else
45185 {
45192 }
45193 }
45195 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
45196 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
45197 The upper bits of DEST are undefined, though they shouldn't cause
45198 exceptions (some bits from src or all zeros are ok). */
45200 static void
45202 {
45205 {
45209 else
45227 else
45234 else
45242 {
45247 const1_rtx);
45248 }
45249 else
45250 {
45254 }
45276 else
45298 }
45302 }
45304 /* Expand a vector reduction. FN is the binary pattern to reduce;
45305 DEST is the destination; IN is the input vector. */
45307 void
45309 {
45314 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
45318 {
45321 }
45326 {
45331 else
45335 }
45336 }
45337 \f
45338 /* Target hook for scalar_mode_supported_p. */
45339 static bool
45341 {
45346 else
45348 }
45350 /* Implements target hook vector_mode_supported_p. */
45351 static bool
45353 {
45367 }
45369 /* Implement target hook libgcc_floating_mode_supported_p. */
45370 static bool
45372 {
45374 {
45381 #ifdef IX86_NO_LIBGCC_TFMODE
45383 #elif defined IX86_MAYBE_NO_LIBGCC_TFMODE
45385 #else
45387 #endif
45391 }
45392 }
45394 /* Target hook for c_mode_for_suffix. */
45395 static machine_mode
45397 {
45404 }
45406 /* Worker function for TARGET_MD_ASM_CLOBBERS.
45408 We do this in the new i386 backend to maintain source compatibility
45409 with the old cc0-based compiler. */
45411 static tree
45413 {
45415 clobbers);
45417 clobbers);
45419 }
45421 /* Implements target vector targetm.asm.encode_section_info. */
45423 static void ATTRIBUTE_UNUSED
45425 {
45430 }
45432 /* Worker function for REVERSE_CONDITION. */
45434 enum rtx_code
45436 {
45440 }
45442 /* Output code to perform an x87 FP register move, from OPERANDS[1]
45443 to OPERANDS[0]. */
45447 {
45449 {
45452 {
45456 }
45460 }
45462 {
45466 else
45467 {
45468 /* There is no non-popping store to memory for XFmode.
45469 So if we need one, follow the store with a load. */
45472 else
45474 }
45475 }
45476 else
45478 }
45480 /* Output code to perform a conditional jump to LABEL, if C2 flag in
45481 FP status register is set. */
45483 void
45485 {
45487 rtx temp;
45492 {
45497 }
45498 else
45499 {
45504 }
45508 pc_rtx);
45513 }
45515 /* Output code to perform a log1p XFmode calculation. */
45518 {
45524 rtx test;
45530 XFmode));
45544 }
45546 /* Emit code for round calculation. */
45548 {
45555 rtx insn;
45560 {
45572 }
45575 {
45596 }
45604 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
45606 /* scratch = fxam(op1) */
45609 UNSPEC_FXAM)));
45610 /* e1 = fabs(op1) */
45613 /* e2 = e1 + 0.5 */
45617 /* res = floor(e2) */
45619 {
45623 }
45624 else
45628 {
45631 {
45638 UNSPEC_TRUNC_NOOP)));
45639 }
45655 }
45657 /* flags = signbit(a) */
45660 /* if (flags) then res = -res */
45664 pc_rtx);
45675 }
45677 /* Output code to perform a Newton-Rhapson approximation of a single precision
45678 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
45681 {
45689 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
45693 /* x0 = rcp(b) estimate */
45696 UNSPEC_RCP14)));
45697 else
45699 UNSPEC_RCP)));
45701 /* e0 = x0 * b */
45704 /* e0 = x0 * e0 */
45707 /* e1 = x0 + x0 */
45710 /* x1 = e1 - e0 */
45713 /* res = a * x1 */
45715 }
45717 /* Output code to perform a Newton-Rhapson approximation of a
45718 single precision floating point [reciprocal] square root. */
45722 {
45724 REAL_VALUE_TYPE r;
45741 {
45744 /* There is no 512-bit rsqrt. There is however rsqrt14. */
45747 }
45749 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
45750 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
45754 /* x0 = rsqrt(a) estimate */
45756 unspec)));
45758 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
45760 {
45768 /* Handle masked compare. */
45770 {
45772 /* Imm value 0x4 corresponds to not-equal comparison. */
45775 }
45776 else
45777 {
45781 }
45782 }
45784 /* e0 = x0 * a */
45786 /* e1 = e0 * x0 */
45789 /* e2 = e1 - 3. */
45795 /* e3 = -.5 * x0 */
45797 else
45798 /* e3 = -.5 * e0 */
45800 /* ret = e2 * e3 */
45802 }
45804 #ifdef TARGET_SOLARIS
45805 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
45807 static void
45809 tree decl)
45810 {
45811 /* With Binutils 2.15, the "@unwind" marker must be specified on
45812 every occurrence of the ".eh_frame" section, not just the first
45813 one. */
45816 {
45820 }
45822 #ifndef USE_GAS
45824 {
45827 }
45828 #endif
45831 }
45834 /* Return the mangling of TYPE if it is an extended fundamental type. */
45838 {
45846 {
45848 /* __float128 is "g". */
45851 /* "long double" or __float80 is "e". */
45855 }
45856 }
45858 /* For 32-bit code we can save PIC register setup by using
45859 __stack_chk_fail_local hidden function instead of calling
45860 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
45861 register, so it is better to call __stack_chk_fail directly. */
45863 static tree ATTRIBUTE_UNUSED
45865 {
45866 return TARGET_64BIT
45869 }
45871 /* Select a format to encode pointers in exception handling data. CODE
45872 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
45873 true if the symbol may be affected by dynamic relocations.
45875 ??? All x86 object file formats are capable of representing this.
45876 After all, the relocation needed is the same as for the call insn.
45877 Whether or not a particular assembler allows us to enter such, I
45878 guess we'll have to see. */
45879 int
45881 {
45883 {
45890 }
45895 }
45896 \f
45897 /* Expand copysign from SIGN to the positive value ABS_VALUE
45898 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
45899 the sign-bit. */
45900 static void
45902 {
45906 {
45907 machine_mode vmode;
45913 else
45918 {
45919 /* We need to generate a scalar mode mask in this case. */
45924 }
45925 }
45926 else
45930 }
45932 /* Expand fabs (OP0) and return a new rtx that holds the result. The
45933 mask for masking out the sign-bit is stored in *SMASK, if that is
45934 non-null. */
45935 static rtx
45937 {
45946 else
45950 {
45951 /* We need to generate a scalar mode mask in this case. */
45956 }
45963 }
45965 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
45966 swapping the operands if SWAP_OPERANDS is true. The expanded
45967 code is a forward jump to a newly created label in case the
45968 comparison is true. The generated label rtx is returned. */
45972 {
45975 rtx tmp;
45990 }
45992 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
45993 using comparison code CODE. Operands are swapped for the comparison if
45994 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
45995 static rtx
45998 {
46011 }
46013 /* Generate and return a rtx of mode MODE for 2**n where n is the number
46014 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
46015 static rtx
46017 {
46018 REAL_VALUE_TYPE TWO52r;
46019 rtx TWO52;
46026 }
46028 /* Expand SSE sequence for computing lround from OP1 storing
46029 into OP0. */
46030 void
46032 {
46033 /* C code for the stuff we're doing below:
46034 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
46035 return (long)tmp;
46036 */
46040 rtx adj;
46042 /* load nextafter (0.5, 0.0) */
46047 /* adj = copysign (0.5, op1) */
46051 /* adj = op1 + adj */
46054 /* op0 = (imode)adj */
46056 }
46058 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
46059 into OPERAND0. */
46060 void
46062 {
46063 /* C code for the stuff we're doing below (for do_floor):
46064 xi = (long)op1;
46065 xi -= (double)xi > op1 ? 1 : 0;
46066 return xi;
46067 */
46073 /* reg = (long)op1 */
46077 /* freg = (double)reg */
46081 /* ireg = (freg > op1) ? ireg - 1 : ireg */
46092 }
46094 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
46095 result in OPERAND0. */
46096 void
46098 {
46099 /* C code for the stuff we're doing below:
46100 xa = fabs (operand1);
46101 if (!isless (xa, 2**52))
46102 return operand1;
46103 xa = xa + 2**52 - 2**52;
46104 return copysign (xa, operand1);
46105 */
46113 /* xa = abs (operand1) */
46116 /* if (!isless (xa, TWO52)) goto label; */
46129 }
46131 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46132 into OPERAND0. */
46133 void
46135 {
46136 /* C code for the stuff we expand below.
46137 double xa = fabs (x), x2;
46138 if (!isless (xa, TWO52))
46139 return x;
46140 xa = xa + TWO52 - TWO52;
46141 x2 = copysign (xa, x);
46142 Compensate. Floor:
46143 if (x2 > x)
46144 x2 -= 1;
46145 Compensate. Ceil:
46146 if (x2 < x)
46147 x2 -= -1;
46148 return x2;
46149 */
46156 /* Temporary for holding the result, initialized to the input
46157 operand to ease control flow. */
46161 /* xa = abs (operand1) */
46164 /* if (!isless (xa, TWO52)) goto label; */
46167 /* xa = xa + TWO52 - TWO52; */
46171 /* xa = copysign (xa, operand1) */
46174 /* generate 1.0 or -1.0 */
46179 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46182 /* We always need to subtract here to preserve signed zero. */
46191 }
46193 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46194 into OPERAND0. */
46195 void
46197 {
46198 /* C code for the stuff we expand below.
46199 double xa = fabs (x), x2;
46200 if (!isless (xa, TWO52))
46201 return x;
46202 x2 = (double)(long)x;
46203 Compensate. Floor:
46204 if (x2 > x)
46205 x2 -= 1;
46206 Compensate. Ceil:
46207 if (x2 < x)
46208 x2 += 1;
46209 if (HONOR_SIGNED_ZEROS (mode))
46210 return copysign (x2, x);
46211 return x2;
46212 */
46219 /* Temporary for holding the result, initialized to the input
46220 operand to ease control flow. */
46224 /* xa = abs (operand1) */
46227 /* if (!isless (xa, TWO52)) goto label; */
46230 /* xa = (double)(long)x */
46235 /* generate 1.0 */
46238 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46252 }
46254 /* Expand SSE sequence for computing round from OPERAND1 storing
46255 into OPERAND0. Sequence that works without relying on DImode truncation
46256 via cvttsd2siq that is only available on 64bit targets. */
46257 void
46259 {
46260 /* C code for the stuff we expand below.
46261 double xa = fabs (x), xa2, x2;
46262 if (!isless (xa, TWO52))
46263 return x;
46264 Using the absolute value and copying back sign makes
46265 -0.0 -> -0.0 correct.
46266 xa2 = xa + TWO52 - TWO52;
46267 Compensate.
46268 dxa = xa2 - xa;
46269 if (dxa <= -0.5)
46270 xa2 += 1;
46271 else if (dxa > 0.5)
46272 xa2 -= 1;
46273 x2 = copysign (xa2, x);
46274 return x2;
46275 */
46282 /* Temporary for holding the result, initialized to the input
46283 operand to ease control flow. */
46287 /* xa = abs (operand1) */
46290 /* if (!isless (xa, TWO52)) goto label; */
46293 /* xa2 = xa + TWO52 - TWO52; */
46297 /* dxa = xa2 - xa; */
46300 /* generate 0.5, 1.0 and -0.5 */
46306 /* Compensate. */
46308 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
46312 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
46317 /* res = copysign (xa2, operand1) */
46324 }
46326 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46327 into OPERAND0. */
46328 void
46330 {
46331 /* C code for SSE variant we expand below.
46332 double xa = fabs (x), x2;
46333 if (!isless (xa, TWO52))
46334 return x;
46335 x2 = (double)(long)x;
46336 if (HONOR_SIGNED_ZEROS (mode))
46337 return copysign (x2, x);
46338 return x2;
46339 */
46346 /* Temporary for holding the result, initialized to the input
46347 operand to ease control flow. */
46351 /* xa = abs (operand1) */
46354 /* if (!isless (xa, TWO52)) goto label; */
46357 /* x = (double)(long)x */
46369 }
46371 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46372 into OPERAND0. */
46373 void
46375 {
46380 /* C code for SSE variant we expand below.
46381 double xa = fabs (x), x2;
46382 if (!isless (xa, TWO52))
46383 return x;
46384 xa2 = xa + TWO52 - TWO52;
46385 Compensate:
46386 if (xa2 > xa)
46387 xa2 -= 1.0;
46388 x2 = copysign (xa2, x);
46389 return x2;
46390 */
46394 /* Temporary for holding the result, initialized to the input
46395 operand to ease control flow. */
46399 /* xa = abs (operand1) */
46402 /* if (!isless (xa, TWO52)) goto label; */
46405 /* res = xa + TWO52 - TWO52; */
46410 /* generate 1.0 */
46413 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
46420 /* res = copysign (res, operand1) */
46427 }
46429 /* Expand SSE sequence for computing round from OPERAND1 storing
46430 into OPERAND0. */
46431 void
46433 {
46434 /* C code for the stuff we're doing below:
46435 double xa = fabs (x);
46436 if (!isless (xa, TWO52))
46437 return x;
46438 xa = (double)(long)(xa + nextafter (0.5, 0.0));
46439 return copysign (xa, x);
46440 */
46447 /* Temporary for holding the result, initialized to the input
46448 operand to ease control flow. */
46456 /* load nextafter (0.5, 0.0) */
46461 /* xa = xa + 0.5 */
46465 /* xa = (double)(int64_t)xa */
46470 /* res = copysign (xa, operand1) */
46477 }
46479 /* Expand SSE sequence for computing round
46480 from OP1 storing into OP0 using sse4 round insn. */
46481 void
46483 {
46492 {
46503 }
46505 /* round (a) = trunc (a + copysign (0.5, a)) */
46507 /* load nextafter (0.5, 0.0) */
46513 /* e1 = copysign (0.5, op1) */
46517 /* e2 = op1 + e1 */
46520 /* res = trunc (e2) */
46525 }
46526 \f
46528 /* Table of valid machine attributes. */
46530 {
46531 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
46532 affects_type_identity } */
46533 /* Stdcall attribute says callee is responsible for popping arguments
46534 if they are not variable. */
46537 /* Fastcall attribute says callee is responsible for popping arguments
46538 if they are not variable. */
46541 /* Thiscall attribute says callee is responsible for popping arguments
46542 if they are not variable. */
46545 /* Cdecl attribute says the callee is a normal C declaration */
46548 /* Regparm attribute specifies how many integer arguments are to be
46549 passed in registers. */
46552 /* Sseregparm attribute says we are using x86_64 calling conventions
46553 for FP arguments. */
46556 /* The transactional memory builtins are implicitly regparm or fastcall
46557 depending on the ABI. Override the generic do-nothing attribute that
46558 these builtins were declared with. */
46561 /* force_align_arg_pointer says this function realigns the stack at entry. */
46564 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46569 #endif
46574 #ifdef SUBTARGET_ATTRIBUTE_TABLE
46575 SUBTARGET_ATTRIBUTE_TABLE,
46576 #endif
46577 /* ms_abi and sysv_abi calling convention function attributes. */
46584 /* End element. */
46586 };
46588 /* Implement targetm.vectorize.builtin_vectorization_cost. */
46589 static int
46592 {
46596 {
46641 }
46642 }
46644 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
46645 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
46646 insn every time. */
46650 /* Initialize vselect_insn. */
46652 static void
46654 {
46656 rtx x;
46667 }
46669 /* Construct (set target (vec_select op0 (parallel perm))) and
46670 return true if that's a valid instruction in the active ISA. */
46672 static bool
46675 {
46701 }
46703 /* Similar, but generate a vec_concat from op0 and op1 as well. */
46705 static bool
46709 {
46710 machine_mode v2mode;
46711 rtx x;
46726 }
46728 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46729 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
46731 static bool
46733 {
46743 ;
46745 ;
46747 ;
46749 ;
46750 else
46753 /* This is a blend, not a permute. Elements must stay in their
46754 respective lanes. */
46756 {
46760 }
46765 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
46766 decision should be extracted elsewhere, so that we only try that
46767 sequence once all budget==3 options have been tried. */
46774 {
46804 /* See if bytes move in pairs so we can use pblendw with
46805 an immediate argument, rather than pblendvb with a vector
46806 argument. */
46809 {
46810 use_pblendvb:
46814 finish_pblendvb:
46820 else
46825 }
46830 /* FALLTHRU */
46832 do_subreg:
46839 /* See if bytes move in pairs. If not, vpblendvb must be used. */
46843 /* See if bytes move in quadruplets. If yes, vpblendd
46844 with immediate can be used. */
46849 {
46850 /* See if bytes move the same in both lanes. If yes,
46851 vpblendw with immediate can be used. */
46856 /* Use vpblendw. */
46861 }
46863 /* Use vpblendd. */
46870 /* See if words move in pairs. If yes, vpblendd can be used. */
46875 {
46876 /* See if words move the same in both lanes. If not,
46877 vpblendvb must be used. */
46880 {
46881 /* Use vpblendvb. */
46891 }
46893 /* Use vpblendw. */
46897 }
46899 /* Use vpblendd. */
46906 /* Use vpblendd. */
46914 }
46916 /* This matches five different patterns with the different modes. */
46924 }
46926 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46927 in terms of the variable form of vpermilps.
46929 Note that we will have already failed the immediate input vpermilps,
46930 which requires that the high and low part shuffle be identical; the
46931 variable form doesn't require that. */
46933 static bool
46935 {
46942 /* We can only permute within the 128-bit lane. */
46944 {
46948 }
46954 {
46957 /* Within each 128-bit lane, the elements of op0 are numbered
46958 from 0 and the elements of op1 are numbered from 4. */
46965 }
46972 }
46974 /* Return true if permutation D can be performed as VMODE permutation
46975 instead. */
46977 static bool
46979 {
46994 else
47000 }
47002 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47003 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
47005 static bool
47007 {
47016 {
47018 {
47021 {
47025 /* Use vperm2i128 insn. The pattern uses
47026 V4DImode instead of V2TImode. */
47039 }
47041 }
47042 }
47043 else
47044 {
47046 {
47049 }
47051 {
47055 /* V4DImode should be already handled through
47056 expand_vselect by vpermq instruction. */
47063 {
47064 /* First see if vpermq can be used for
47065 V8SImode/V16HImode/V32QImode. */
47067 {
47075 {
47079 }
47081 }
47083 /* Next see if vpermd can be used. */
47086 }
47087 /* Or if vpermps can be used. */
47092 {
47093 /* vpshufb only works intra lanes, it is not
47094 possible to shuffle bytes in between the lanes. */
47098 }
47099 }
47101 {
47105 /* If vpermq didn't work, vpshufb won't work either. */
47113 {
47114 /* First see if vpermq can be used for
47115 V16SImode/V32HImode/V64QImode. */
47117 {
47125 {
47129 }
47131 }
47133 /* Next see if vpermd can be used. */
47136 }
47137 /* Or if vpermps can be used. */
47141 {
47142 /* vpshufb only works intra lanes, it is not
47143 possible to shuffle bytes in between the lanes. */
47147 }
47148 }
47149 else
47151 }
47162 else
47163 {
47171 else
47175 {
47179 }
47180 }
47191 {
47206 else
47208 }
47209 else
47210 {
47213 }
47218 }
47220 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
47221 in a single instruction. */
47223 static bool
47225 {
47229 /* Check plain VEC_SELECT first, because AVX has instructions that could
47230 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
47231 input where SEL+CONCAT may not. */
47233 {
47239 {
47245 }
47248 {
47252 }
47254 {
47255 /* Use vpbroadcast{b,w,d}. */
47258 {
47301 /* For other modes prefer other shuffles this function creates. */
47303 }
47305 {
47309 }
47310 }
47315 /* There are plenty of patterns in sse.md that are written for
47316 SEL+CONCAT and are not replicated for a single op. Perhaps
47317 that should be changed, to avoid the nastiness here. */
47319 /* Recognize interleave style patterns, which means incrementing
47320 every other permutation operand. */
47322 {
47325 }
47330 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
47332 {
47334 {
47339 }
47344 }
47345 }
47347 /* Finally, try the fully general two operand permute. */
47352 /* Recognize interleave style patterns with reversed operands. */
47354 {
47356 {
47360 else
47363 }
47368 }
47370 /* Try the SSE4.1 blend variable merge instructions. */
47374 /* Try one of the AVX vpermil variable permutations. */
47378 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
47379 vpshufb, vpermd, vpermps or vpermq variable permutation. */
47383 /* Try the AVX2 vpalignr instruction. */
47387 /* Try the AVX512F vpermi2 instructions. */
47392 }
47394 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47395 in terms of a pair of pshuflw + pshufhw instructions. */
47397 static bool
47399 {
47407 /* The two permutations only operate in 64-bit lanes. */
47418 /* Emit the pshuflw. */
47425 /* Emit the pshufhw. */
47433 }
47435 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47436 the permutation using the SSSE3 palignr instruction. This succeeds
47437 when all of the elements in PERM fit within one vector and we merely
47438 need to shift them down so that a single vector permutation has a
47439 chance to succeed. If SINGLE_INSN_ONLY_P, succeed if only
47440 the vpalignr instruction itself can perform the requested permutation. */
47442 static bool
47444 {
47451 /* Even with AVX, palignr only operates on 128-bit vectors,
47452 in AVX2 palignr operates on both 128-bit lanes. */
47462 {
47466 {
47469 }
47478 }
47481 {
47490 }
47492 /* Given that we have SSSE3, we know we'll be able to implement the
47493 single operand permutation after the palignr with pshufb for
47494 128-bit vectors. If SINGLE_INSN_ONLY_P, in_order has to be computed
47495 first. */
47501 {
47506 }
47510 {
47516 else
47521 }
47527 /* For AVX2, test whether we can permute the result in one instruction. */
47529 {
47534 }
47538 {
47542 }
47543 else
47544 {
47549 shift));
47550 }
47554 /* Test for the degenerate case where the alignment by itself
47555 produces the desired permutation. */
47557 {
47560 }
47566 }
47568 /* A subroutine of ix86_expand_vec_perm_const_1. Try to simplify
47569 the permutation using the SSE4_1 pblendv instruction. Potentially
47570 reduces permutation from 2 pshufb and or to 1 pshufb and pblendv. */
47572 static bool
47574 {
47580 /* Use the same checks as in expand_vec_perm_blend. */
47584 ;
47586 ;
47588 ;
47589 else
47592 /* Figure out where permutation elements stay not in their
47593 respective lanes. */
47595 {
47599 }
47600 /* We can pblend the part where elements stay not in their
47601 respective lanes only when these elements are all in one
47602 half of a permutation.
47603 {0 1 8 3 4 5 9 7} is ok as 8, 9 are at not at their respective
47604 lanes, but both 8 and 9 >= 8
47605 {0 1 8 3 4 5 2 7} is not ok as 2 and 8 are not at their
47606 respective lanes and 8 >= 8, but 2 not. */
47612 /* First we apply one operand permutation to the part where
47613 elements stay not in their respective lanes. */
47617 else
47629 else
47634 /* Next we put permuted elements into their positions. */
47638 else
47648 }
47652 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47653 a two vector permutation into a single vector permutation by using
47654 an interleave operation to merge the vectors. */
47656 static bool
47658 {
47667 {
47670 }
47672 {
47675 /* For 32-byte modes allow even d->one_operand_p.
47676 The lack of cross-lane shuffling in some instructions
47677 might prevent a single insn shuffle. */
47680 /* If expand_vec_perm_interleave3 can expand this into
47681 a 3 insn sequence, give up and let it be expanded as
47682 3 insn sequence. While that is one insn longer,
47683 it doesn't need a memory operand and in the common
47684 case that both interleave low and high permutations
47685 with the same operands are adjacent needs 4 insns
47686 for both after CSE. */
47689 }
47690 else
47693 /* Examine from whence the elements come. */
47702 {
47705 /* Split the two input vectors into 4 halves. */
47711 /* If the elements from the low halves use interleave low, and similarly
47712 for interleave high. If the elements are from mis-matched halves, we
47713 can use shufps for V4SF/V4SI or do a DImode shuffle. */
47715 {
47716 /* punpckl* */
47718 {
47723 }
47726 }
47728 {
47729 /* punpckh* */
47731 {
47736 }
47739 }
47741 {
47742 /* shufps */
47744 {
47749 }
47751 {
47752 /* shufpd */
47757 }
47758 }
47760 {
47761 /* shufps */
47763 {
47768 }
47770 {
47771 /* shufpd */
47776 }
47777 }
47778 else
47780 }
47781 else
47782 {
47787 /* Split the two input vectors into 8 quarters. */
47793 {
47796 }
47799 {
47803 }
47805 {
47808 }
47811 {
47813 {
47814 /* Attempt to increase the likelihood that dfinal
47815 shuffle will be intra-lane. */
47819 }
47821 /* vperm2f128 or vperm2i128. */
47823 {
47828 }
47833 {
47837 {
47840 }
47841 }
47842 }
47847 {
47848 /* vpunpckl* */
47850 {
47859 }
47860 }
47863 {
47864 /* vpunpckh* */
47866 {
47875 }
47876 }
47877 else
47879 }
47881 /* Use the remapping array set up above to move the elements from their
47882 swizzled locations into their final destinations. */
47885 {
47888 /* If same_halves is true, both halves of the remapped vector are the
47889 same. Avoid cross-lane accesses if possible. */
47891 {
47894 }
47895 else
47897 }
47899 {
47902 }
47906 /* Test if the final remap can be done with a single insn. For V4SFmode or
47907 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
47920 {
47923 }
47930 }
47932 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47933 a single vector cross-lane permutation into vpermq followed
47934 by any of the single insn permutations. */
47936 static bool
47938 {
47952 {
47955 }
47958 {
47963 }
47976 {
47983 }
47990 {
47995 ;
47998 else
48000 }
48009 }
48011 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
48012 a vector permutation using two instructions, vperm2f128 resp.
48013 vperm2i128 followed by any single in-lane permutation. */
48015 static bool
48017 {
48031 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
48032 immediate. For perm < 16 the second permutation uses
48033 d->op0 as first operand, for perm >= 16 it uses d->op1
48034 as first operand. The second operand is the result of
48035 vperm2[fi]128. */
48037 {
48038 /* Ignore permutations which do not move anything cross-lane. */
48040 {
48041 /* The second shuffle for e.g. V4DFmode has
48042 0123 and ABCD operands.
48043 Ignore AB23, as 23 is already in the second lane
48044 of the first operand. */
48046 /* And 01CD, as 01 is in the first lane of the first
48047 operand. */
48049 /* And 4567, as then the vperm2[fi]128 doesn't change
48050 anything on the original 4567 second operand. */
48052 }
48053 else
48054 {
48055 /* The second shuffle for e.g. V4DFmode has
48056 4567 and ABCD operands.
48057 Ignore AB67, as 67 is already in the second lane
48058 of the first operand. */
48060 /* And 45CD, as 45 is in the first lane of the first
48061 operand. */
48063 /* And 0123, as then the vperm2[fi]128 doesn't change
48064 anything on the original 0123 first operand. */
48066 }
48069 {
48075 else
48077 }
48080 {
48084 }
48085 else
48089 {
48093 /* Found a usable second shuffle. dfirst will be
48094 vperm2f128 on d->op0 and d->op1. */
48106 /* And dsecond is some single insn shuffle, taking
48107 d->op0 and result of vperm2f128 (if perm < 16) or
48108 d->op1 and result of vperm2f128 (otherwise). */
48117 }
48119 /* For one operand, the only useful vperm2f128 permutation is 0x01
48120 aka lanes swap. */
48123 }
48126 }
48128 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48129 a two vector permutation using 2 intra-lane interleave insns
48130 and cross-lane shuffle for 32-byte vectors. */
48132 static bool
48134 {
48141 ;
48143 ;
48144 else
48159 {
48163 else
48169 else
48175 else
48181 else
48187 else
48193 else
48198 }
48202 }
48204 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
48205 a single vector permutation using a single intra-lane vector
48206 permutation, vperm2f128 swapping the lanes and vblend* insn blending
48207 the non-swapped and swapped vectors together. */
48209 static bool
48211 {
48219 || TARGET_AVX2
48228 {
48235 }
48270 }
48272 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
48273 permutation using two vperm2f128, followed by a vshufpd insn blending
48274 the two vectors together. */
48276 static bool
48278 {
48321 }
48323 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
48324 permutation with two pshufb insns and an ior. We should have already
48325 failed all two instruction sequences. */
48327 static bool
48329 {
48343 /* Generate two permutation masks. If the required element is within
48344 the given vector it is shuffled into the proper lane. If the required
48345 element is in the other vector, force a zero into the lane by setting
48346 bit 7 in the permutation mask. */
48349 {
48356 {
48359 }
48360 }
48384 }
48386 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
48387 with two vpshufb insns, vpermq and vpor. We should have already failed
48388 all two or three instruction sequences. */
48390 static bool
48392 {
48407 /* Generate two permutation masks. If the required element is within
48408 the same lane, it is shuffled in. If the required element from the
48409 other lane, force a zero by setting bit 7 in the permutation mask.
48410 In the other mask the mask has non-negative elements if element
48411 is requested from the other lane, but also moved to the other lane,
48412 so that the result of vpshufb can have the two V2TImode halves
48413 swapped. */
48416 {
48421 {
48424 }
48425 }
48434 /* Swap the 128-byte lanes of h into hp. */
48438 const1_rtx));
48455 }
48457 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48458 and extract-odd permutations of two V32QImode and V16QImode operand
48459 with two vpshufb insns, vpor and vpermq. We should have already
48460 failed all two or three instruction sequences. */
48462 static bool
48464 {
48483 /* Generate two permutation masks. In the first permutation mask
48484 the first quarter will contain indexes for the first half
48485 of the op0, the second quarter will contain bit 7 set, third quarter
48486 will contain indexes for the second half of the op0 and the
48487 last quarter bit 7 set. In the second permutation mask
48488 the first quarter will contain bit 7 set, the second quarter
48489 indexes for the first half of the op1, the third quarter bit 7 set
48490 and last quarter indexes for the second half of the op1.
48491 I.e. the first mask e.g. for V32QImode extract even will be:
48492 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
48493 (all values masked with 0xf except for -128) and second mask
48494 for extract even will be
48495 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
48498 {
48504 {
48507 }
48508 }
48527 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
48535 }
48537 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48538 and extract-odd permutations of two V16QI, V8HI, V16HI or V32QI operands
48539 with two "and" and "pack" or two "shift" and "pack" insns. We should
48540 have already failed all two instruction sequences. */
48542 static bool
48544 {
48548 machine_mode half_mode;
48557 {
48559 /* Required for "pack". */
48570 /* No check as all instructions are SSE2. */
48601 /* Only V8HI, V16QI, V16HI and V32QI modes are more profitable than
48602 general shuffles. */
48604 }
48606 /* Check that permutation is even or odd. */
48621 {
48628 }
48629 else
48630 {
48637 }
48638 /* In AVX2 for 256 bit case we need to permute pack result. */
48640 {
48646 const0_rtx,
48647 const2_rtx,
48648 const1_rtx,
48651 }
48652 else
48656 }
48658 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
48659 and extract-odd permutations. */
48661 static bool
48663 {
48667 {
48674 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48678 /* Now an unpck[lh]pd will produce the result required. */
48681 else
48687 {
48696 /* Shuffle within the 128-bit lanes to produce:
48697 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
48701 /* Shuffle the lanes around to produce:
48702 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
48706 /* Shuffle within the 128-bit lanes to produce:
48707 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
48710 /* Shuffle within the 128-bit lanes to produce:
48711 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
48714 /* Shuffle the lanes around to produce:
48715 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
48718 }
48725 /* These are always directly implementable by expand_vec_perm_1. */
48733 else
48734 {
48737 /* We need 2*log2(N)-1 operations to achieve odd/even
48738 with interleave. */
48747 else
48750 }
48762 {
48767 else
48772 {
48777 }
48779 }
48787 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48791 /* Now an vpunpck[lh]qdq will produce the result required. */
48794 else
48801 {
48806 else
48811 {
48816 }
48818 }
48829 /* Shuffle the lanes around into
48830 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
48838 /* Swap the 2nd and 3rd position in each lane into
48839 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
48845 /* Now an vpunpck[lh]qdq will produce
48846 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
48850 else
48859 }
48862 }
48864 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
48865 extract-even and extract-odd permutations. */
48867 static bool
48869 {
48881 }
48883 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
48884 permutations. We assume that expand_vec_perm_1 has already failed. */
48886 static bool
48888 {
48896 {
48899 /* These are special-cased in sse.md so that we can optionally
48900 use the vbroadcast instruction. They expand to two insns
48901 if the input happens to be in a register. */
48908 /* These are always implementable using standard shuffle patterns. */
48913 /* These can be implemented via interleave. We save one insn by
48914 stopping once we have promoted to V4SImode and then use pshufd. */
48917 do
48918 {
48919 rtx dest;
48925 {
48929 }
48936 }
48952 /* For AVX2 broadcasts of the first element vpbroadcast* or
48953 vpermq should be used by expand_vec_perm_1. */
48959 }
48960 }
48962 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
48963 broadcast permutations. */
48965 static bool
48967 {
48979 }
48981 /* Implement arbitrary permutations of two V64QImode operands
48982 will 2 vpermi2w, 2 vpshufb and one vpor instruction. */
48983 static bool
48985 {
48995 machine_mode vmode;
49001 {
49008 }
49010 /* Prepare permutations such that the first one takes care of
49011 putting the even bytes into the right positions or one higher
49012 positions (ds[0]) and the second one takes care of
49013 putting the odd bytes into the right positions or one below
49014 (ds[1]). */
49017 {
49020 {
49023 }
49024 else
49025 {
49028 }
49029 }
49051 }
49053 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
49054 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
49055 all the shorter instruction sequences. */
49057 static bool
49059 {
49075 /* Generate 4 permutation masks. If the required element is within
49076 the same lane, it is shuffled in. If the required element from the
49077 other lane, force a zero by setting bit 7 in the permutation mask.
49078 In the other mask the mask has non-negative elements if element
49079 is requested from the other lane, but also moved to the other lane,
49080 so that the result of vpshufb can have the two V2TImode halves
49081 swapped. */
49084 {
49089 }
49095 {
49103 }
49106 {
49108 {
49111 }
49118 }
49120 /* Swap the 128-byte lanes of h[X]. */
49122 {
49128 const1_rtx));
49130 }
49133 {
49135 {
49138 }
49144 }
49147 {
49149 {
49153 }
49156 }
49166 }
49168 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
49169 With all of the interface bits taken care of, perform the expansion
49170 in D and return true on success. */
49172 static bool
49174 {
49175 /* Try a single instruction expansion. */
49179 /* Try sequences of two instructions. */
49202 /* Try sequences of three instructions. */
49219 /* Try sequences of four instructions. */
49230 /* ??? Look for narrow permutations whose element orderings would
49231 allow the promotion to a wider mode. */
49233 /* ??? Look for sequences of interleave or a wider permute that place
49234 the data into the correct lanes for a half-vector shuffle like
49235 pshuf[lh]w or vpermilps. */
49237 /* ??? Look for sequences of interleave that produce the desired results.
49238 The combinatorics of punpck[lh] get pretty ugly... */
49243 /* Even longer sequences. */
49248 }
49250 /* If a permutation only uses one operand, make it clear. Returns true
49251 if the permutation references both operands. */
49253 static bool
49255 {
49263 {
49269 {
49272 }
49273 /* The elements of PERM do not suggest that only the first operand
49274 is used, but both operands are identical. Allow easier matching
49275 of the permutation by folding the permutation into the single
49276 input vector. */
49277 /* FALLTHRU */
49288 }
49291 }
49293 bool
49295 {
49300 rtx sel;
49317 {
49322 }
49329 /* If the selector says both arguments are needed, but the operands are the
49330 same, the above tried to expand with one_operand_p and flattened selector.
49331 If that didn't work, retry without one_operand_p; we succeeded with that
49332 during testing. */
49334 {
49338 }
49341 }
49343 /* Implement targetm.vectorize.vec_perm_const_ok. */
49345 static bool
49348 {
49357 /* Given sufficient ISA support we can just return true here
49358 for selected vector modes. */
49360 {
49366 /* All implementable with a single vpermi2 insn. */
49371 /* All implementable with a single vpermi2 insn. */
49376 /* Implementable with 2 vpermi2, 2 vpshufb and 1 or insn. */
49384 /* All implementable with a single vpermi2 insn. */
49389 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49394 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49401 /* All implementable with a single vpperm insn. */
49404 /* All implementable with 2 pshufb + 1 ior. */
49410 /* All implementable with shufpd or unpck[lh]pd. */
49414 }
49416 /* Extract the values from the vector CST into the permutation
49417 array in D. */
49420 {
49424 }
49426 /* For all elements from second vector, fold the elements to first. */
49431 /* Check whether the mask can be applied to the vector type. */
49434 /* Implementable with shufps or pshufd. */
49438 /* Otherwise we have to go through the motions and see if we can
49439 figure out how to generate the requested permutation. */
49450 }
49452 void
49454 {
49469 /* We'll either be able to implement the permutation directly... */
49473 /* ... or we use the special-case patterns. */
49475 }
49477 static void
49479 {
49494 {
49497 }
49499 /* Note that for AVX this isn't one instruction. */
49502 }
49505 /* Expand a vector operation CODE for a V*QImode in terms of the
49506 same operation on V*HImode. */
49508 void
49510 {
49512 machine_mode himode;
49522 {
49540 }
49544 {
49546 /* Unpack data such that we've got a source byte in each low byte of
49547 each word. We don't care what goes into the high byte of each word.
49548 Rather than trying to get zero in there, most convenient is to let
49549 it be a copy of the low byte. */
49554 /* FALLTHRU */
49566 /* FALLTHRU */
49576 }
49578 /* Perform the operation. */
49585 /* Merge the data back into the right place. */
49595 {
49596 /* For SSE2, we used an full interleave, so the desired
49597 results are in the even elements. */
49600 }
49601 else
49602 {
49603 /* For AVX, the interleave used above was not cross-lane. So the
49604 extraction is evens but with the second and third quarter swapped.
49605 Happily, that is even one insn shorter than even extraction. */
49608 }
49615 }
49617 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
49618 if op is CONST_VECTOR with all odd elements equal to their
49619 preceding element. */
49621 static bool
49623 {
49633 }
49635 void
49638 {
49641 rtx x;
49649 /* We only play even/odd games with vectors of SImode. */
49652 /* If we're looking for the odd results, shift those members down to
49653 the even slots. For some cpus this is faster than a PSHUFD. */
49655 {
49656 /* For XOP use vpmacsdqh, but only for smult, as it is only
49657 signed. */
49659 {
49663 }
49674 }
49677 {
49680 else
49682 }
49684 {
49687 else
49689 }
49694 else
49695 {
49698 /* The easiest way to implement this without PMULDQ is to go through
49699 the motions as if we are performing a full 64-bit multiply. With
49700 the exception that we need to do less shuffling of the elements. */
49702 /* Compute the sign-extension, aka highparts, of the two operands. */
49708 /* Multiply LO(A) * HI(B), and vice-versa. */
49714 /* Multiply LO(A) * LO(B). */
49718 /* Combine and shift the highparts into place. */
49723 /* Combine high and low parts. */
49726 }
49728 }
49730 void
49733 {
49739 {
49744 {
49745 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
49746 shuffle the elements once so that all elements are in the right
49747 place for immediate use: { A C B D }. */
49752 }
49753 else
49754 {
49755 /* Put the elements into place for the multiply. */
49759 }
49764 /* Shuffle the elements between the lanes. After this we
49765 have { A B E F | C D G H } for each operand. */
49775 /* Shuffle the elements within the lanes. After this we
49776 have { A A B B | C C D D } or { E E F F | G G H H }. */
49817 }
49818 }
49820 void
49822 {
49832 /* Move the results in element 2 down to element 1; we don't care
49833 what goes in elements 2 and 3. Then we can merge the parts
49834 back together with an interleave.
49836 Note that two other sequences were tried:
49837 (1) Use interleaves at the start instead of psrldq, which allows
49838 us to use a single shufps to merge things back at the end.
49839 (2) Use shufps here to combine the two vectors, then pshufd to
49840 put the elements in the correct order.
49841 In both cases the cost of the reformatting stall was too high
49842 and the overall sequence slower. */
49853 }
49855 void
49857 {
49868 {
49869 /* op1: A,B,C,D, op2: E,F,G,H */
49878 /* t1: B,A,D,C */
49885 /* t2: (B*E),(A*F),(D*G),(C*H) */
49888 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
49891 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
49894 /* Multiply lower parts and add all */
49901 }
49902 else
49903 {
49904 machine_mode nmode;
49908 {
49911 }
49913 {
49916 }
49918 {
49921 }
49922 else
49926 /* Multiply low parts. */
49930 /* Shift input vectors right 32 bits so we can multiply high parts. */
49935 /* Multiply high parts by low parts. */
49941 /* Combine and shift the highparts back. */
49945 /* Combine high and low parts. */
49947 }
49951 }
49953 /* Return 1 if control tansfer instruction INSN
49954 should be encoded with bnd prefix.
49955 If insn is NULL then return 1 when control
49956 transfer instructions should be prefixed with
49957 bnd by default for current function. */
49959 bool
49961 {
49962 /* For call insns check special flag. */
49964 {
49968 }
49970 /* All other insns are prefixed only if function is instrumented. */
49972 }
49974 /* Calculate integer abs() using only SSE2 instructions. */
49976 void
49978 {
49983 {
49984 /* For 32-bit signed integer X, the best way to calculate the absolute
49985 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
49997 /* For 16-bit signed integer X, the best way to calculate the absolute
49998 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
50006 /* For 8-bit signed integer X, the best way to calculate the absolute
50007 value of X is min ((unsigned char) X, (unsigned char) (-X)),
50008 as SSE2 provides the PMINUB insn. */
50018 }
50022 }
50024 /* Expand an insert into a vector register through pinsr insn.
50025 Return true if successful. */
50027 bool
50029 {
50037 {
50040 }
50046 {
50051 {
50058 {
50090 }
50104 }
50108 }
50109 }
50110 \f
50111 /* This function returns the calling abi specific va_list type node.
50112 It returns the FNDECL specific va_list type. */
50114 static tree
50116 {
50123 else
50125 }
50127 /* Returns the canonical va_list type specified by TYPE. If there
50128 is no valid TYPE provided, it return NULL_TREE. */
50130 static tree
50132 {
50135 /* Resolve references and pointers to va_list type. */
50144 {
50149 {
50150 /* If va_list is an array type, the argument may have decayed
50151 to a pointer type, e.g. by being passed to another function.
50152 In that case, unwrap both types so that we can compare the
50153 underlying records. */
50156 {
50159 }
50160 }
50167 {
50168 /* If va_list is an array type, the argument may have decayed
50169 to a pointer type, e.g. by being passed to another function.
50170 In that case, unwrap both types so that we can compare the
50171 underlying records. */
50174 {
50177 }
50178 }
50185 {
50186 /* If va_list is an array type, the argument may have decayed
50187 to a pointer type, e.g. by being passed to another function.
50188 In that case, unwrap both types so that we can compare the
50189 underlying records. */
50192 {
50195 }
50196 }
50200 }
50202 }
50204 /* Iterate through the target-specific builtin types for va_list.
50205 IDX denotes the iterator, *PTREE is set to the result type of
50206 the va_list builtin, and *PNAME to its internal type.
50207 Returns zero if there is no element for this index, otherwise
50208 IDX should be increased upon the next call.
50209 Note, do not iterate a base builtin's name like __builtin_va_list.
50210 Used from c_common_nodes_and_builtins. */
50212 static int
50214 {
50216 {
50218 {
50231 }
50232 }
50235 }
50237 #undef TARGET_SCHED_DISPATCH
50238 #define TARGET_SCHED_DISPATCH has_dispatch
50239 #undef TARGET_SCHED_DISPATCH_DO
50240 #define TARGET_SCHED_DISPATCH_DO do_dispatch
50241 #undef TARGET_SCHED_REASSOCIATION_WIDTH
50242 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
50243 #undef TARGET_SCHED_REORDER
50244 #define TARGET_SCHED_REORDER ix86_sched_reorder
50245 #undef TARGET_SCHED_ADJUST_PRIORITY
50246 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
50247 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
50248 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
50249 ix86_dependencies_evaluation_hook
50251 /* The size of the dispatch window is the total number of bytes of
50252 object code allowed in a window. */
50253 #define DISPATCH_WINDOW_SIZE 16
50255 /* Number of dispatch windows considered for scheduling. */
50256 #define MAX_DISPATCH_WINDOWS 3
50258 /* Maximum number of instructions in a window. */
50259 #define MAX_INSN 4
50261 /* Maximum number of immediate operands in a window. */
50262 #define MAX_IMM 4
50264 /* Maximum number of immediate bits allowed in a window. */
50265 #define MAX_IMM_SIZE 128
50267 /* Maximum number of 32 bit immediates allowed in a window. */
50268 #define MAX_IMM_32 4
50270 /* Maximum number of 64 bit immediates allowed in a window. */
50271 #define MAX_IMM_64 2
50273 /* Maximum total of loads or prefetches allowed in a window. */
50274 #define MAX_LOAD 2
50276 /* Maximum total of stores allowed in a window. */
50277 #define MAX_STORE 1
50279 #undef BIG
50280 #define BIG 100
50283 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
50286 disp_load,
50287 disp_store,
50288 disp_load_store,
50289 disp_prefetch,
50290 disp_imm,
50291 disp_imm_32,
50292 disp_imm_64,
50293 disp_branch,
50294 disp_cmp,
50295 disp_jcc,
50296 disp_last
50297 };
50299 /* Number of allowable groups in a dispatch window. It is an array
50300 indexed by dispatch_group enum. 100 is used as a big number,
50301 because the number of these kind of operations does not have any
50302 effect in dispatch window, but we need them for other reasons in
50303 the table. */
50306 };
50312 };
50314 /* Instruction path. */
50320 last_path
50321 };
50323 /* sched_insn_info defines a window to the instructions scheduled in
50324 the basic block. It contains a pointer to the insn_info table and
50325 the instruction scheduled.
50327 Windows are allocated for each basic block and are linked
50328 together. */
50330 rtx insn;
50337 /* Linked list of dispatch windows. This is a two way list of
50338 dispatch windows of a basic block. It contains information about
50339 the number of uops in the window and the total number of
50340 instructions and of bytes in the object code for this dispatch
50341 window. */
50359 /* Immediate valuse used in an insn. */
50361 {
50370 /* Get dispatch group of insn. */
50372 static enum dispatch_group
50374 {
50390 }
50392 /* Return true if insn is a compare instruction. */
50394 static bool
50396 {
50404 }
50406 /* Return true if a dispatch violation encountered. */
50408 static bool
50410 {
50414 }
50416 /* Return true if insn is a branch instruction. */
50418 static bool
50420 {
50422 }
50424 /* Return true if insn is a prefetch instruction. */
50426 static bool
50428 {
50430 }
50432 /* This function initializes a dispatch window and the list container holding a
50433 pointer to the window. */
50435 static void
50437 {
50443 else
50461 {
50467 }
50469 }
50471 /* This function allocates and initializes a dispatch window and the
50472 list container holding a pointer to the window. */
50476 {
50481 }
50483 /* This routine initializes the dispatch scheduling information. It
50484 initiates building dispatch scheduler tables and constructs the
50485 first dispatch window. */
50487 static void
50489 {
50490 /* Allocate a dispatch list and a window. */
50495 }
50497 /* This function returns true if a branch is detected. End of a basic block
50498 does not have to be a branch, but here we assume only branches end a
50499 window. */
50501 static bool
50503 {
50505 }
50507 /* This function is called when the end of a window processing is reached. */
50509 static void
50511 {
50514 {
50519 }
50521 }
50523 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
50524 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
50525 for 48 bytes of instructions. Note that these windows are not dispatch
50526 windows that their sizes are DISPATCH_WINDOW_SIZE. */
50530 {
50532 {
50537 }
50543 }
50545 /* Compute number of immediate operands of an instruction. */
50547 static void
50549 {
50556 {
50563 else
50575 {
50578 }
50583 }
50584 }
50586 /* Return total size of immediate operands of an instruction along with number
50587 of corresponding immediate-operands. It initializes its parameters to zero
50588 befor calling FIND_CONSTANT.
50589 INSN is the input instruction. IMM is the total of immediates.
50590 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
50591 bit immediates. */
50593 static int
50595 {
50603 }
50605 /* This function indicates if an operand of an instruction is an
50606 immediate. */
50608 static bool
50610 {
50619 }
50621 /* Return single or double path for instructions. */
50623 static enum insn_path
50625 {
50635 }
50637 /* Return insn dispatch group. */
50639 static enum dispatch_group
50641 {
50659 }
50661 /* Count number of GROUP restricted instructions in a dispatch
50662 window WINDOW_LIST. */
50664 static int
50666 {
50677 {
50696 }
50709 }
50711 /* This function returns true if insn satisfies dispatch rules on the
50712 last window scheduled. */
50714 static bool
50716 {
50724 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
50725 instructions should be given the lowest priority in the
50726 scheduling process in Haifa scheduler to make sure they will be
50727 scheduled in the same dispatch window as the reference to them. */
50731 /* Check nonrestricted. */
50735 /* Get last dispatch window. */
50740 {
50745 /* Window 1 is full. Go for next window. */
50747 }
50754 /* See if it fits in the first window. */
50756 {
50757 /* The first widow should have only single and double path
50758 uops. */
50764 }
50766 }
50768 /* Add an instruction INSN with NUM_UOPS micro-operations to the
50769 dispatch window WINDOW_LIST. */
50771 static void
50773 {
50791 /* Initialize window with new instruction. */
50812 {
50815 }
50816 }
50818 /* Adds a scheduled instruction, INSN, to the current dispatch window.
50819 If the total bytes of instructions or the number of instructions in
50820 the window exceed allowable, it allocates a new window. */
50822 static void
50824 {
50847 /* Get the last dispatch window. */
50855 else
50858 /* If current window is full, get a new window.
50859 Window number zero is full, if MAX_INSN uops are scheduled in it.
50860 Window number one is full, if window zero's bytes plus window
50861 one's bytes is 32, or if the bytes of the new instruction added
50862 to the total makes it greater than 48, or it has already MAX_INSN
50863 instructions in it. */
50872 {
50875 }
50878 {
50882 {
50885 }
50886 }
50888 {
50893 {
50896 }
50899 }
50900 else
50904 {
50905 /* End of basic block is reached do end-basic-block process. */
50908 }
50909 }
50911 /* Print the dispatch window, WINDOW_NUM, to FILE. */
50913 DEBUG_FUNCTION static void
50915 {
50921 else
50935 {
50938 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
50944 }
50945 }
50947 /* Print to stdout a dispatch window. */
50949 DEBUG_FUNCTION void
50951 {
50953 }
50955 /* Print INSN dispatch information to FILE. */
50957 DEBUG_FUNCTION static void
50959 {
50982 }
50984 /* Print to STDERR the status of the ready list with respect to
50985 dispatch windows. */
50987 DEBUG_FUNCTION void
50989 {
50997 }
50999 /* This routine is the driver of the dispatch scheduler. */
51001 static void
51003 {
51008 }
51010 /* Return TRUE if Dispatch Scheduling is supported. */
51012 static bool
51014 {
51018 {
51034 }
51037 }
51039 /* Implementation of reassociation_width target hook used by
51040 reassoc phase to identify parallelism level in reassociated
51041 tree. Statements tree_code is passed in OPC. Arguments type
51042 is passed in MODE.
51044 Currently parallel reassociation is enabled for Atom
51045 processors only and we set reassociation width to be 2
51046 because Atom may issue up to 2 instructions per cycle.
51048 Return value should be fixed if parallel reassociation is
51049 enabled for other processors. */
51051 static int
51053 {
51054 /* Vector part. */
51056 {
51059 else
51061 }
51063 /* Scalar part. */
51068 else
51070 }
51072 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
51073 place emms and femms instructions. */
51075 static machine_mode
51077 {
51082 {
51101 else
51113 /* FALLTHRU */
51117 }
51118 }
51120 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
51121 vectors. If AVX512F is enabled then try vectorizing with 512bit,
51122 256bit and 128bit vectors. */
51124 static unsigned int
51126 {
51129 }
51131 \f
51133 /* Return class of registers which could be used for pseudo of MODE
51134 and of class RCLASS for spilling instead of memory. Return NO_REGS
51135 if it is not possible or non-profitable. */
51136 static reg_class_t
51138 {
51144 }
51146 /* Implement targetm.vectorize.init_cost. */
51150 {
51154 }
51156 /* Implement targetm.vectorize.add_stmt_cost. */
51158 static unsigned
51162 {
51169 /* Statements in an inner loop relative to the loop being
51170 vectorized are weighted more heavily. The value here is
51171 arbitrary and could potentially be improved with analysis. */
51177 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
51178 for Silvermont as it has out of order integer pipeline and can execute
51179 2 scalar instruction per tick, but has in order SIMD pipeline. */
51182 {
51186 }
51191 }
51193 /* Implement targetm.vectorize.finish_cost. */
51195 static void
51198 {
51203 }
51205 /* Implement targetm.vectorize.destroy_cost_data. */
51207 static void
51209 {
51211 }
51213 /* Validate target specific memory model bits in VAL. */
51215 static unsigned HOST_WIDE_INT
51217 {
51224 {
51228 }
51231 {
51235 }
51237 {
51241 }
51243 }
51245 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
51246 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
51247 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
51248 or number of vecsize_mangle variants that should be emitted. */
51250 static int
51254 {
51261 {
51265 }
51270 {
51277 /* case SCmode: */
51278 /* case DCmode: */
51284 }
51286 tree t;
51290 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
51292 {
51299 /* case SCmode: */
51300 /* case DCmode: */
51306 }
51309 {
51310 /* Parse here processor clause. If not present, default to 'b'. */
51312 }
51314 {
51315 /* If the function isn't exported, we can pick up just one ISA
51316 for the clones. */
51321 else
51324 }
51325 else
51326 {
51329 }
51331 {
51344 }
51346 {
51349 else
51354 }
51356 }
51358 /* Add target attribute to SIMD clone NODE if needed. */
51360 static void
51362 {
51366 {
51381 }
51391 }
51393 /* If SIMD clone NODE can't be used in a vectorized loop
51394 in current function, return -1, otherwise return a badness of using it
51395 (0 if it is most desirable from vecsize_mangle point of view, 1
51396 slightly less desirable, etc.). */
51398 static int
51400 {
51402 {
51420 }
51421 }
51423 /* This function adjusts the unroll factor based on
51424 the hardware capabilities. For ex, bdver3 has
51425 a loop buffer which makes unrolling of smaller
51426 loops less important. This function decides the
51427 unroll factor using number of memory references
51428 (value 32 is used) as a heuristic. */
51430 static unsigned
51432 {
51441 /* Count the number of memory references within the loop body.
51442 This value determines the unrolling factor for bdver3 and bdver4
51443 architectures. */
51452 {
51457 else
51459 }
51466 }
51469 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
51471 static bool
51473 {
51474 /* For x87 floating point with standard excess precision handling,
51475 there is no adddf3 pattern (since x87 floating point only has
51476 XFmode operations) so the default hook implementation gets this
51477 wrong. */
51479 }
51481 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
51483 static void
51485 {
51490 {
51505 hold_fnclex);
51518 }
51520 {
51529 mxcsr_orig_var,
51539 ldmxcsr_hold_call);
51542 else
51547 ldmxcsr_clear_call);
51548 else
51552 stxmcsr_update_call);
51554 {
51560 exceptions_assign);
51561 }
51562 else
51567 ldmxcsr_update_call);
51568 }
51569 tree atomic_feraiseexcept
51574 atomic_feraiseexcept_call);
51575 }
51577 /* Return mode to be used for bounds or VOIDmode
51578 if bounds are not supported. */
51580 static enum machine_mode
51582 {
51583 /* Do not support pointer checker if MPX
51584 is not enabled. */
51586 {
51591 }
51594 }
51596 /* Return constant used to statically initialize constant bounds.
51598 This function is used to create special bound values. For now
51599 only INIT bounds and NONE bounds are expected. More special
51600 values may be added later. */
51602 static tree
51604 {
51610 /* This function is supposed to be used to create INIT and
51611 NONE bounds only. */
51616 }
51618 /* Generate a list of statements STMTS to initialize pointer bounds
51619 variable VAR with bounds LB and UB. Return the number of generated
51620 statements. */
51622 static int
51624 {
51642 }
51644 #if !TARGET_MACHO && !TARGET_DLLIMPORT_DECL_ATTRIBUTES
51645 /* For i386, common symbol is local only for non-PIE binaries. For
51646 x86-64, common symbol is local only for non-PIE binaries or linker
51647 supports copy reloc in PIE binaries. */
51649 static bool
51651 {
51653 (!flag_pic
51654 || (TARGET_64BIT
51656 }
51657 #endif
51659 /* If MEM is in the form of [base+offset], extract the two parts
51660 of address and set to BASE and OFFSET, otherwise return false. */
51662 static bool
51664 {
51665 rtx addr;
51675 {
51679 }
51685 {
51689 }
51692 }
51694 /* Given OPERANDS of consecutive load/store, check if we can merge
51695 them into move multiple. LOAD is true if they are load instructions.
51696 MODE is the mode of memory operands. */
51698 bool
51701 {
51706 {
51711 }
51712 else
51713 {
51718 }
51725 /* Check if the addresses are in the form of [base+offset]. */
51731 /* Check if the bases are the same. */
51738 /* Check if mem_1 is adjacent to mem_2 and mem_1 has lower address. */
51743 }
51745 /* Initialize the GCC target structure. */
51746 #undef TARGET_RETURN_IN_MEMORY
51747 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
51749 #undef TARGET_LEGITIMIZE_ADDRESS
51750 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
51752 #undef TARGET_ATTRIBUTE_TABLE
51753 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
51754 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
51755 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
51756 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51757 # undef TARGET_MERGE_DECL_ATTRIBUTES
51758 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
51759 #endif
51761 #undef TARGET_COMP_TYPE_ATTRIBUTES
51762 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
51764 #undef TARGET_INIT_BUILTINS
51765 #define TARGET_INIT_BUILTINS ix86_init_builtins
51766 #undef TARGET_BUILTIN_DECL
51767 #define TARGET_BUILTIN_DECL ix86_builtin_decl
51768 #undef TARGET_EXPAND_BUILTIN
51769 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
51771 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
51772 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
51773 ix86_builtin_vectorized_function
51775 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
51776 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
51778 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
51779 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
51781 #undef TARGET_VECTORIZE_BUILTIN_GATHER
51782 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
51784 #undef TARGET_BUILTIN_RECIPROCAL
51785 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
51787 #undef TARGET_ASM_FUNCTION_EPILOGUE
51788 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
51790 #undef TARGET_ENCODE_SECTION_INFO
51791 #ifndef SUBTARGET_ENCODE_SECTION_INFO
51792 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
51793 #else
51794 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
51795 #endif
51797 #undef TARGET_ASM_OPEN_PAREN
51799 #undef TARGET_ASM_CLOSE_PAREN
51802 #undef TARGET_ASM_BYTE_OP
51803 #define TARGET_ASM_BYTE_OP ASM_BYTE
51805 #undef TARGET_ASM_ALIGNED_HI_OP
51806 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
51807 #undef TARGET_ASM_ALIGNED_SI_OP
51808 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
51809 #ifdef ASM_QUAD
51810 #undef TARGET_ASM_ALIGNED_DI_OP
51811 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
51812 #endif
51814 #undef TARGET_PROFILE_BEFORE_PROLOGUE
51815 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
51817 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
51818 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
51820 #undef TARGET_ASM_UNALIGNED_HI_OP
51821 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
51822 #undef TARGET_ASM_UNALIGNED_SI_OP
51823 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
51824 #undef TARGET_ASM_UNALIGNED_DI_OP
51825 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
51827 #undef TARGET_PRINT_OPERAND
51828 #define TARGET_PRINT_OPERAND ix86_print_operand
51829 #undef TARGET_PRINT_OPERAND_ADDRESS
51830 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
51831 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
51832 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
51833 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
51834 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
51836 #undef TARGET_SCHED_INIT_GLOBAL
51837 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
51838 #undef TARGET_SCHED_ADJUST_COST
51839 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
51840 #undef TARGET_SCHED_ISSUE_RATE
51841 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
51842 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
51843 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
51844 ia32_multipass_dfa_lookahead
51845 #undef TARGET_SCHED_MACRO_FUSION_P
51846 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
51847 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
51848 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
51850 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
51851 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
51853 #undef TARGET_MEMMODEL_CHECK
51854 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
51856 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
51857 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
51859 #ifdef HAVE_AS_TLS
51860 #undef TARGET_HAVE_TLS
51861 #define TARGET_HAVE_TLS true
51862 #endif
51863 #undef TARGET_CANNOT_FORCE_CONST_MEM
51864 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
51865 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
51866 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
51868 #undef TARGET_DELEGITIMIZE_ADDRESS
51869 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
51871 #undef TARGET_MS_BITFIELD_LAYOUT_P
51872 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
51874 #if TARGET_MACHO
51875 #undef TARGET_BINDS_LOCAL_P
51876 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
51877 #else
51878 #undef TARGET_BINDS_LOCAL_P
51879 #define TARGET_BINDS_LOCAL_P ix86_binds_local_p
51880 #endif
51881 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51882 #undef TARGET_BINDS_LOCAL_P
51883 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
51884 #endif
51886 #undef TARGET_ASM_OUTPUT_MI_THUNK
51887 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
51888 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
51889 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
51891 #undef TARGET_ASM_FILE_START
51892 #define TARGET_ASM_FILE_START x86_file_start
51894 #undef TARGET_OPTION_OVERRIDE
51895 #define TARGET_OPTION_OVERRIDE ix86_option_override
51897 #undef TARGET_REGISTER_MOVE_COST
51898 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
51899 #undef TARGET_MEMORY_MOVE_COST
51900 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
51901 #undef TARGET_RTX_COSTS
51902 #define TARGET_RTX_COSTS ix86_rtx_costs
51903 #undef TARGET_ADDRESS_COST
51904 #define TARGET_ADDRESS_COST ix86_address_cost
51906 #undef TARGET_FIXED_CONDITION_CODE_REGS
51907 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
51908 #undef TARGET_CC_MODES_COMPATIBLE
51909 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
51911 #undef TARGET_MACHINE_DEPENDENT_REORG
51912 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
51914 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
51915 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
51917 #undef TARGET_BUILD_BUILTIN_VA_LIST
51918 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
51920 #undef TARGET_FOLD_BUILTIN
51921 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
51923 #undef TARGET_COMPARE_VERSION_PRIORITY
51924 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
51926 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
51927 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
51928 ix86_generate_version_dispatcher_body
51930 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
51931 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
51932 ix86_get_function_versions_dispatcher
51934 #undef TARGET_ENUM_VA_LIST_P
51935 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
51937 #undef TARGET_FN_ABI_VA_LIST
51938 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
51940 #undef TARGET_CANONICAL_VA_LIST_TYPE
51941 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
51943 #undef TARGET_EXPAND_BUILTIN_VA_START
51944 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
51946 #undef TARGET_MD_ASM_CLOBBERS
51947 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
51949 #undef TARGET_PROMOTE_PROTOTYPES
51950 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
51951 #undef TARGET_SETUP_INCOMING_VARARGS
51952 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
51953 #undef TARGET_MUST_PASS_IN_STACK
51954 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
51955 #undef TARGET_FUNCTION_ARG_ADVANCE
51956 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
51957 #undef TARGET_FUNCTION_ARG
51958 #define TARGET_FUNCTION_ARG ix86_function_arg
51959 #undef TARGET_INIT_PIC_REG
51960 #define TARGET_INIT_PIC_REG ix86_init_pic_reg
51961 #undef TARGET_USE_PSEUDO_PIC_REG
51962 #define TARGET_USE_PSEUDO_PIC_REG ix86_use_pseudo_pic_reg
51963 #undef TARGET_FUNCTION_ARG_BOUNDARY
51964 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
51965 #undef TARGET_PASS_BY_REFERENCE
51966 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
51967 #undef TARGET_INTERNAL_ARG_POINTER
51968 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
51969 #undef TARGET_UPDATE_STACK_BOUNDARY
51970 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
51971 #undef TARGET_GET_DRAP_RTX
51972 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
51973 #undef TARGET_STRICT_ARGUMENT_NAMING
51974 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
51975 #undef TARGET_STATIC_CHAIN
51976 #define TARGET_STATIC_CHAIN ix86_static_chain
51977 #undef TARGET_TRAMPOLINE_INIT
51978 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
51979 #undef TARGET_RETURN_POPS_ARGS
51980 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
51982 #undef TARGET_LEGITIMATE_COMBINED_INSN
51983 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
51985 #undef TARGET_ASAN_SHADOW_OFFSET
51986 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
51988 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
51989 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
51991 #undef TARGET_SCALAR_MODE_SUPPORTED_P
51992 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
51994 #undef TARGET_VECTOR_MODE_SUPPORTED_P
51995 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
51997 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
51998 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
51999 ix86_libgcc_floating_mode_supported_p
52001 #undef TARGET_C_MODE_FOR_SUFFIX
52002 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
52004 #ifdef HAVE_AS_TLS
52005 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
52006 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
52007 #endif
52009 #ifdef SUBTARGET_INSERT_ATTRIBUTES
52010 #undef TARGET_INSERT_ATTRIBUTES
52011 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
52012 #endif
52014 #undef TARGET_MANGLE_TYPE
52015 #define TARGET_MANGLE_TYPE ix86_mangle_type
52017 #if !TARGET_MACHO
52018 #undef TARGET_STACK_PROTECT_FAIL
52019 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
52020 #endif
52022 #undef TARGET_FUNCTION_VALUE
52023 #define TARGET_FUNCTION_VALUE ix86_function_value
52025 #undef TARGET_FUNCTION_VALUE_REGNO_P
52026 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
52028 #undef TARGET_PROMOTE_FUNCTION_MODE
52029 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
52031 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
52032 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ix86_override_options_after_change
52034 #undef TARGET_MEMBER_TYPE_FORCES_BLK
52035 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
52037 #undef TARGET_INSTANTIATE_DECLS
52038 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
52040 #undef TARGET_SECONDARY_RELOAD
52041 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
52043 #undef TARGET_CLASS_MAX_NREGS
52044 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
52046 #undef TARGET_PREFERRED_RELOAD_CLASS
52047 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
52048 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
52049 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
52050 #undef TARGET_CLASS_LIKELY_SPILLED_P
52051 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
52053 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
52054 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
52055 ix86_builtin_vectorization_cost
52056 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
52057 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
52058 ix86_vectorize_vec_perm_const_ok
52059 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
52060 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
52061 ix86_preferred_simd_mode
52062 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
52063 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
52064 ix86_autovectorize_vector_sizes
52065 #undef TARGET_VECTORIZE_INIT_COST
52066 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
52067 #undef TARGET_VECTORIZE_ADD_STMT_COST
52068 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
52069 #undef TARGET_VECTORIZE_FINISH_COST
52070 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
52071 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
52072 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
52074 #undef TARGET_SET_CURRENT_FUNCTION
52075 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
52077 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
52078 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
52080 #undef TARGET_OPTION_SAVE
52081 #define TARGET_OPTION_SAVE ix86_function_specific_save
52083 #undef TARGET_OPTION_RESTORE
52084 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
52086 #undef TARGET_OPTION_POST_STREAM_IN
52087 #define TARGET_OPTION_POST_STREAM_IN ix86_function_specific_post_stream_in
52089 #undef TARGET_OPTION_PRINT
52090 #define TARGET_OPTION_PRINT ix86_function_specific_print
52092 #undef TARGET_OPTION_FUNCTION_VERSIONS
52093 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
52095 #undef TARGET_CAN_INLINE_P
52096 #define TARGET_CAN_INLINE_P ix86_can_inline_p
52098 #undef TARGET_EXPAND_TO_RTL_HOOK
52099 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
52101 #undef TARGET_LEGITIMATE_ADDRESS_P
52102 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
52104 #undef TARGET_LRA_P
52105 #define TARGET_LRA_P hook_bool_void_true
52107 #undef TARGET_REGISTER_PRIORITY
52108 #define TARGET_REGISTER_PRIORITY ix86_register_priority
52110 #undef TARGET_REGISTER_USAGE_LEVELING_P
52111 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
52113 #undef TARGET_LEGITIMATE_CONSTANT_P
52114 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
52116 #undef TARGET_FRAME_POINTER_REQUIRED
52117 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
52119 #undef TARGET_CAN_ELIMINATE
52120 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
52122 #undef TARGET_EXTRA_LIVE_ON_ENTRY
52123 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
52125 #undef TARGET_ASM_CODE_END
52126 #define TARGET_ASM_CODE_END ix86_code_end
52128 #undef TARGET_CONDITIONAL_REGISTER_USAGE
52129 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
52131 #if TARGET_MACHO
52132 #undef TARGET_INIT_LIBFUNCS
52133 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
52134 #endif
52136 #undef TARGET_LOOP_UNROLL_ADJUST
52137 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
52139 #undef TARGET_SPILL_CLASS
52140 #define TARGET_SPILL_CLASS ix86_spill_class
52142 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
52143 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
52144 ix86_simd_clone_compute_vecsize_and_simdlen
52146 #undef TARGET_SIMD_CLONE_ADJUST
52147 #define TARGET_SIMD_CLONE_ADJUST \
52148 ix86_simd_clone_adjust
52150 #undef TARGET_SIMD_CLONE_USABLE
52151 #define TARGET_SIMD_CLONE_USABLE \
52152 ix86_simd_clone_usable
52154 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
52155 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
52156 ix86_float_exceptions_rounding_supported_p
52158 #undef TARGET_MODE_EMIT
52159 #define TARGET_MODE_EMIT ix86_emit_mode_set
52161 #undef TARGET_MODE_NEEDED
52162 #define TARGET_MODE_NEEDED ix86_mode_needed
52164 #undef TARGET_MODE_AFTER
52165 #define TARGET_MODE_AFTER ix86_mode_after
52167 #undef TARGET_MODE_ENTRY
52168 #define TARGET_MODE_ENTRY ix86_mode_entry
52170 #undef TARGET_MODE_EXIT
52171 #define TARGET_MODE_EXIT ix86_mode_exit
52173 #undef TARGET_MODE_PRIORITY
52174 #define TARGET_MODE_PRIORITY ix86_mode_priority
52176 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
52177 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
52179 #undef TARGET_LOAD_BOUNDS_FOR_ARG
52180 #define TARGET_LOAD_BOUNDS_FOR_ARG ix86_load_bounds
52182 #undef TARGET_STORE_BOUNDS_FOR_ARG
52183 #define TARGET_STORE_BOUNDS_FOR_ARG ix86_store_bounds
52185 #undef TARGET_LOAD_RETURNED_BOUNDS
52186 #define TARGET_LOAD_RETURNED_BOUNDS ix86_load_returned_bounds
52188 #undef TARGET_STORE_RETURNED_BOUNDS
52189 #define TARGET_STORE_RETURNED_BOUNDS ix86_store_returned_bounds
52191 #undef TARGET_CHKP_BOUND_MODE
52192 #define TARGET_CHKP_BOUND_MODE ix86_mpx_bound_mode
52194 #undef TARGET_BUILTIN_CHKP_FUNCTION
52195 #define TARGET_BUILTIN_CHKP_FUNCTION ix86_builtin_mpx_function
52197 #undef TARGET_CHKP_FUNCTION_VALUE_BOUNDS
52198 #define TARGET_CHKP_FUNCTION_VALUE_BOUNDS ix86_function_value_bounds
52200 #undef TARGET_CHKP_MAKE_BOUNDS_CONSTANT
52201 #define TARGET_CHKP_MAKE_BOUNDS_CONSTANT ix86_make_bounds_constant
52203 #undef TARGET_CHKP_INITIALIZE_BOUNDS
52204 #define TARGET_CHKP_INITIALIZE_BOUNDS ix86_initialize_bounds
52206 #undef TARGET_SETUP_INCOMING_VARARG_BOUNDS
52207 #define TARGET_SETUP_INCOMING_VARARG_BOUNDS ix86_setup_incoming_vararg_bounds
52209 #undef TARGET_OFFLOAD_OPTIONS
52210 #define TARGET_OFFLOAD_OPTIONS \
52211 ix86_offload_options
52213 #undef TARGET_ABSOLUTE_BIGGEST_ALIGNMENT
52214 #define TARGET_ABSOLUTE_BIGGEST_ALIGNMENT 512
52217 \f