1 /* Definitions for GCC. Part of the machine description for CRIS.
2 Copyright (C) 1998-2015 Free Software Foundation, Inc.
3 Contributed by Axis Communications. Written by Hans-Peter Nilsson.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
35 #include "double-int.h"
42 #include "fold-const.h"
44 #include "stor-layout.h"
49 #include "statistics.h"
51 #include "fixed-value.h"
58 #include "diagnostic-core.h"
64 #include "tm-constrs.h"
66 #include "target-def.h"
68 #include "insn-codes.h"
70 #include "dominance.h"
76 #include "cfgcleanup.h"
78 #include "basic-block.h"
83 #include "plugin-api.h"
88 /* Usable when we have an amount to add or subtract, and want the
89 optimal size of the insn. */
90 #define ADDITIVE_SIZE_MODIFIER(size) \
91 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
93 #define LOSE_AND_RETURN(msgid, x) \
96 cris_operand_lossage (msgid, x); \
100 enum cris_retinsn_type
101 { CRIS_RETINSN_UNKNOWN
= 0, CRIS_RETINSN_RET
, CRIS_RETINSN_JUMP
};
103 /* Per-function machine data. */
104 struct GTY(()) machine_function
106 int needs_return_address_on_stack
;
108 /* This is the number of registers we save in the prologue due to
112 enum cris_retinsn_type return_type
;
115 /* This little fix suppresses the 'u' or 's' when '%e' in assembly
117 static char cris_output_insn_is_bound
= 0;
119 /* In code for output macros, this is how we know whether e.g. constant
120 goes in code or in a static initializer. */
121 static int in_code
= 0;
123 /* Fix for reg_overlap_mentioned_p. */
124 static int cris_reg_overlap_mentioned_p (rtx
, rtx
);
126 static machine_mode
cris_promote_function_mode (const_tree
, machine_mode
,
127 int *, const_tree
, int);
129 static unsigned int cris_atomic_align_for_mode (machine_mode
);
131 static void cris_print_base (rtx
, FILE *);
133 static void cris_print_index (rtx
, FILE *);
135 static void cris_output_addr_const (FILE *, rtx
);
137 static struct machine_function
* cris_init_machine_status (void);
139 static rtx
cris_struct_value_rtx (tree
, int);
141 static void cris_setup_incoming_varargs (cumulative_args_t
, machine_mode
,
142 tree type
, int *, int);
144 static int cris_initial_frame_pointer_offset (void);
146 static void cris_operand_lossage (const char *, rtx
);
148 static int cris_reg_saved_in_regsave_area (unsigned int, bool);
150 static void cris_print_operand (FILE *, rtx
, int);
152 static void cris_print_operand_address (FILE *, rtx
);
154 static bool cris_print_operand_punct_valid_p (unsigned char code
);
156 static bool cris_output_addr_const_extra (FILE *, rtx
);
158 static void cris_conditional_register_usage (void);
160 static void cris_asm_output_mi_thunk
161 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
163 static void cris_file_start (void);
164 static void cris_init_libfuncs (void);
166 static reg_class_t
cris_preferred_reload_class (rtx
, reg_class_t
);
168 static int cris_register_move_cost (machine_mode
, reg_class_t
, reg_class_t
);
169 static int cris_memory_move_cost (machine_mode
, reg_class_t
, bool);
170 static bool cris_rtx_costs (rtx
, int, int, int, int *, bool);
171 static int cris_address_cost (rtx
, machine_mode
, addr_space_t
, bool);
172 static bool cris_pass_by_reference (cumulative_args_t
, machine_mode
,
174 static int cris_arg_partial_bytes (cumulative_args_t
, machine_mode
,
176 static rtx
cris_function_arg (cumulative_args_t
, machine_mode
,
178 static rtx
cris_function_incoming_arg (cumulative_args_t
,
179 machine_mode
, const_tree
, bool);
180 static void cris_function_arg_advance (cumulative_args_t
, machine_mode
,
182 static tree
cris_md_asm_clobbers (tree
, tree
, tree
);
183 static bool cris_cannot_force_const_mem (machine_mode
, rtx
);
185 static void cris_option_override (void);
187 static bool cris_frame_pointer_required (void);
189 static void cris_asm_trampoline_template (FILE *);
190 static void cris_trampoline_init (rtx
, tree
, rtx
);
192 static rtx
cris_function_value(const_tree
, const_tree
, bool);
193 static rtx
cris_libcall_value (machine_mode
, const_rtx
);
194 static bool cris_function_value_regno_p (const unsigned int);
195 static void cris_file_end (void);
197 /* This is the parsed result of the "-max-stack-stackframe=" option. If
198 it (still) is zero, then there was no such option given. */
199 int cris_max_stackframe
= 0;
201 /* This is the parsed result of the "-march=" option, if given. */
202 int cris_cpu_version
= CRIS_DEFAULT_CPU_VERSION
;
204 #undef TARGET_ASM_ALIGNED_HI_OP
205 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
206 #undef TARGET_ASM_ALIGNED_SI_OP
207 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
208 #undef TARGET_ASM_ALIGNED_DI_OP
209 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
211 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only
212 available in ELF. These "normal" pseudos do not have any alignment
213 constraints or side-effects. */
214 #undef TARGET_ASM_UNALIGNED_HI_OP
215 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
217 #undef TARGET_ASM_UNALIGNED_SI_OP
218 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
220 #undef TARGET_ASM_UNALIGNED_DI_OP
221 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
223 #undef TARGET_PRINT_OPERAND
224 #define TARGET_PRINT_OPERAND cris_print_operand
225 #undef TARGET_PRINT_OPERAND_ADDRESS
226 #define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address
227 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
228 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p
229 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
230 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA cris_output_addr_const_extra
232 #undef TARGET_CONDITIONAL_REGISTER_USAGE
233 #define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage
235 #undef TARGET_ASM_OUTPUT_MI_THUNK
236 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
237 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
238 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
240 #undef TARGET_ASM_FILE_START
241 #define TARGET_ASM_FILE_START cris_file_start
242 #undef TARGET_ASM_FILE_END
243 #define TARGET_ASM_FILE_END cris_file_end
245 #undef TARGET_INIT_LIBFUNCS
246 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs
248 #undef TARGET_LEGITIMATE_ADDRESS_P
249 #define TARGET_LEGITIMATE_ADDRESS_P cris_legitimate_address_p
251 #undef TARGET_LEGITIMATE_CONSTANT_P
252 #define TARGET_LEGITIMATE_CONSTANT_P cris_legitimate_constant_p
254 #undef TARGET_PREFERRED_RELOAD_CLASS
255 #define TARGET_PREFERRED_RELOAD_CLASS cris_preferred_reload_class
257 #undef TARGET_REGISTER_MOVE_COST
258 #define TARGET_REGISTER_MOVE_COST cris_register_move_cost
259 #undef TARGET_MEMORY_MOVE_COST
260 #define TARGET_MEMORY_MOVE_COST cris_memory_move_cost
261 #undef TARGET_RTX_COSTS
262 #define TARGET_RTX_COSTS cris_rtx_costs
263 #undef TARGET_ADDRESS_COST
264 #define TARGET_ADDRESS_COST cris_address_cost
266 #undef TARGET_PROMOTE_FUNCTION_MODE
267 #define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode
269 #undef TARGET_ATOMIC_ALIGN_FOR_MODE
270 #define TARGET_ATOMIC_ALIGN_FOR_MODE cris_atomic_align_for_mode
272 #undef TARGET_STRUCT_VALUE_RTX
273 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
274 #undef TARGET_SETUP_INCOMING_VARARGS
275 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
276 #undef TARGET_PASS_BY_REFERENCE
277 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
278 #undef TARGET_ARG_PARTIAL_BYTES
279 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
280 #undef TARGET_FUNCTION_ARG
281 #define TARGET_FUNCTION_ARG cris_function_arg
282 #undef TARGET_FUNCTION_INCOMING_ARG
283 #define TARGET_FUNCTION_INCOMING_ARG cris_function_incoming_arg
284 #undef TARGET_FUNCTION_ARG_ADVANCE
285 #define TARGET_FUNCTION_ARG_ADVANCE cris_function_arg_advance
286 #undef TARGET_MD_ASM_CLOBBERS
287 #define TARGET_MD_ASM_CLOBBERS cris_md_asm_clobbers
289 #undef TARGET_CANNOT_FORCE_CONST_MEM
290 #define TARGET_CANNOT_FORCE_CONST_MEM cris_cannot_force_const_mem
292 #undef TARGET_FRAME_POINTER_REQUIRED
293 #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required
295 #undef TARGET_OPTION_OVERRIDE
296 #define TARGET_OPTION_OVERRIDE cris_option_override
298 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
299 #define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template
300 #undef TARGET_TRAMPOLINE_INIT
301 #define TARGET_TRAMPOLINE_INIT cris_trampoline_init
303 #undef TARGET_FUNCTION_VALUE
304 #define TARGET_FUNCTION_VALUE cris_function_value
305 #undef TARGET_LIBCALL_VALUE
306 #define TARGET_LIBCALL_VALUE cris_libcall_value
307 #undef TARGET_FUNCTION_VALUE_REGNO_P
308 #define TARGET_FUNCTION_VALUE_REGNO_P cris_function_value_regno_p
310 struct gcc_target targetm
= TARGET_INITIALIZER
;
312 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */
315 cris_movem_load_rest_p (rtx op
, int offs
)
317 unsigned int reg_count
= XVECLEN (op
, 0) - offs
;
323 unsigned int regno
= 0;
325 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
326 other than (MEM reg). */
328 || GET_CODE (XVECEXP (op
, 0, offs
)) != SET
329 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
)))
330 || !MEM_P (SET_SRC (XVECEXP (op
, 0, offs
))))
333 /* Check a possible post-inc indicator. */
334 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, offs
+ 1))) == PLUS
)
336 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 0);
337 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 1);
343 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
344 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
345 || !CONST_INT_P (inc
)
346 || INTVAL (inc
) != (HOST_WIDE_INT
) reg_count
* 4)
356 regno
= reg_count
- 1;
359 elt
= XVECEXP (op
, 0, offs
);
360 src_addr
= XEXP (SET_SRC (elt
), 0);
362 if (GET_CODE (elt
) != SET
363 || !REG_P (SET_DEST (elt
))
364 || GET_MODE (SET_DEST (elt
)) != SImode
365 || REGNO (SET_DEST (elt
)) != regno
366 || !MEM_P (SET_SRC (elt
))
367 || GET_MODE (SET_SRC (elt
)) != SImode
368 || !memory_address_p (SImode
, src_addr
))
371 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
373 rtx elt
= XVECEXP (op
, 0, i
);
376 if (GET_CODE (elt
) != SET
377 || !REG_P (SET_DEST (elt
))
378 || GET_MODE (SET_DEST (elt
)) != SImode
379 || REGNO (SET_DEST (elt
)) != regno
380 || !MEM_P (SET_SRC (elt
))
381 || GET_MODE (SET_SRC (elt
)) != SImode
382 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
383 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
384 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt
), 0), 1))
385 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != setno
* 4)
392 /* Worker function for predicate for the parallel contents in a movem
396 cris_store_multiple_op_p (rtx op
)
398 int reg_count
= XVECLEN (op
, 0);
409 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
410 other than (MEM reg) and (MEM (PLUS reg const)). */
414 elt
= XVECEXP (op
, 0, 0);
416 if (GET_CODE (elt
) != SET
)
419 dest
= SET_DEST (elt
);
421 if (!REG_P (SET_SRC (elt
)) || !MEM_P (dest
))
424 dest_addr
= XEXP (dest
, 0);
426 /* Check a possible post-inc indicator. */
427 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, 1))) == PLUS
)
429 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 0);
430 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 1);
436 || !REG_P (SET_DEST (XVECEXP (op
, 0, 1)))
437 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, 1)))
438 || !CONST_INT_P (inc
)
439 /* Support increment by number of registers, and by the offset
440 of the destination, if it has the form (MEM (PLUS reg
442 || !((REG_P (dest_addr
)
443 && REGNO (dest_addr
) == REGNO (reg
)
444 && INTVAL (inc
) == (HOST_WIDE_INT
) reg_count
* 4)
445 || (GET_CODE (dest_addr
) == PLUS
446 && REG_P (XEXP (dest_addr
, 0))
447 && REGNO (XEXP (dest_addr
, 0)) == REGNO (reg
)
448 && CONST_INT_P (XEXP (dest_addr
, 1))
449 && INTVAL (XEXP (dest_addr
, 1)) == INTVAL (inc
))))
460 regno
= reg_count
- 1;
463 if (GET_CODE (elt
) != SET
464 || !REG_P (SET_SRC (elt
))
465 || GET_MODE (SET_SRC (elt
)) != SImode
466 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
467 || !MEM_P (SET_DEST (elt
))
468 || GET_MODE (SET_DEST (elt
)) != SImode
)
471 if (REG_P (dest_addr
))
473 dest_base
= dest_addr
;
476 else if (GET_CODE (dest_addr
) == PLUS
477 && REG_P (XEXP (dest_addr
, 0))
478 && CONST_INT_P (XEXP (dest_addr
, 1)))
480 dest_base
= XEXP (dest_addr
, 0);
481 offset
= INTVAL (XEXP (dest_addr
, 1));
486 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
488 rtx elt
= XVECEXP (op
, 0, i
);
491 if (GET_CODE (elt
) != SET
492 || !REG_P (SET_SRC (elt
))
493 || GET_MODE (SET_SRC (elt
)) != SImode
494 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
495 || !MEM_P (SET_DEST (elt
))
496 || GET_MODE (SET_DEST (elt
)) != SImode
497 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
498 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_base
)
499 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt
), 0), 1))
500 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != setno
* 4 + offset
)
507 /* The TARGET_CONDITIONAL_REGISTER_USAGE worker. */
510 cris_conditional_register_usage (void)
512 /* FIXME: This isn't nice. We should be able to use that register for
513 something else if the PIC table isn't needed. */
515 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
]
516 = call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
518 /* Allow use of ACR (PC in pre-V32) and tweak order. */
521 static const int reg_alloc_order_v32
[] = REG_ALLOC_ORDER_V32
;
524 fixed_regs
[CRIS_ACR_REGNUM
] = 0;
527 i
< sizeof (reg_alloc_order_v32
)/sizeof (reg_alloc_order_v32
[0]);
529 reg_alloc_order
[i
] = reg_alloc_order_v32
[i
];
532 if (TARGET_HAS_MUL_INSNS
)
533 fixed_regs
[CRIS_MOF_REGNUM
] = 0;
535 /* On early versions, we must use the 16-bit condition-code register,
536 which has another name. */
537 if (cris_cpu_version
< 8)
538 reg_names
[CRIS_CC0_REGNUM
] = "ccr";
541 /* Return crtl->uses_pic_offset_table. For use in cris.md,
542 since some generated files do not include function.h. */
545 cris_cfun_uses_pic_table (void)
547 return crtl
->uses_pic_offset_table
;
550 /* Worker function for TARGET_CANNOT_FORCE_CONST_MEM.
551 We can't put PIC addresses in the constant pool, not even the ones that
552 can be reached as pc-relative as we can't tell when or how to do that. */
555 cris_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
557 enum cris_symbol_type t
= cris_symbol_type_of (x
);
561 || t
== cris_got_symbol
562 || t
== cris_rel_symbol
;
565 /* Given an rtx, return the text string corresponding to the CODE of X.
566 Intended for use in the assembly language output section of a
572 cris_output_insn_is_bound
= 0;
573 switch (GET_CODE (x
))
584 /* This function is for retrieving a part of an instruction name for
585 an operator, for immediate output. If that ever happens for
586 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure
588 internal_error ("MULT case in cris_op_str");
624 /* Used to control the sign/zero-extend character for the 'E' modifier.
626 cris_output_insn_is_bound
= 1;
631 return "Unknown operator";
636 /* Emit an error message when we're in an asm, and a fatal error for
637 "normal" insns. Formatted output isn't easily implemented, since we
638 use output_operand_lossage to output the actual message and handle the
639 categorization of the error. */
642 cris_operand_lossage (const char *msgid
, rtx op
)
645 output_operand_lossage ("%s", msgid
);
648 /* Print an index part of an address to file. */
651 cris_print_index (rtx index
, FILE *file
)
653 /* Make the index "additive" unless we'll output a negative number, in
654 which case the sign character is free (as in free beer). */
655 if (!CONST_INT_P (index
) || INTVAL (index
) >= 0)
659 fprintf (file
, "$%s.b", reg_names
[REGNO (index
)]);
660 else if (CRIS_CONSTANT_P (index
))
661 cris_output_addr_const (file
, index
);
662 else if (GET_CODE (index
) == MULT
)
664 fprintf (file
, "$%s.",
665 reg_names
[REGNO (XEXP (index
, 0))]);
667 putc (INTVAL (XEXP (index
, 1)) == 2 ? 'w' : 'd', file
);
669 else if (GET_CODE (index
) == SIGN_EXTEND
&& MEM_P (XEXP (index
, 0)))
671 rtx inner
= XEXP (index
, 0);
672 rtx inner_inner
= XEXP (inner
, 0);
674 if (GET_CODE (inner_inner
) == POST_INC
)
676 fprintf (file
, "[$%s+].",
677 reg_names
[REGNO (XEXP (inner_inner
, 0))]);
678 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
682 fprintf (file
, "[$%s].", reg_names
[REGNO (inner_inner
)]);
684 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
687 else if (MEM_P (index
))
689 rtx inner
= XEXP (index
, 0);
690 if (GET_CODE (inner
) == POST_INC
)
691 fprintf (file
, "[$%s+].d", reg_names
[REGNO (XEXP (inner
, 0))]);
693 fprintf (file
, "[$%s].d", reg_names
[REGNO (inner
)]);
696 cris_operand_lossage ("unexpected index-type in cris_print_index",
700 /* Print a base rtx of an address to file. */
703 cris_print_base (rtx base
, FILE *file
)
706 fprintf (file
, "$%s", reg_names
[REGNO (base
)]);
707 else if (GET_CODE (base
) == POST_INC
)
709 gcc_assert (REGNO (XEXP (base
, 0)) != CRIS_ACR_REGNUM
);
710 fprintf (file
, "$%s+", reg_names
[REGNO (XEXP (base
, 0))]);
713 cris_operand_lossage ("unexpected base-type in cris_print_base",
717 /* Usable as a guard in expressions. */
720 cris_fatal (char *arg
)
722 internal_error (arg
);
724 /* We'll never get here; this is just to appease compilers. */
728 /* Return nonzero if REGNO is an ordinary register that *needs* to be
729 saved together with other registers, possibly by a MOVEM instruction,
730 or is saved for target-independent reasons. There may be
731 target-dependent reasons to save the register anyway; this is just a
732 wrapper for a complicated conditional. */
735 cris_reg_saved_in_regsave_area (unsigned int regno
, bool got_really_used
)
738 (((df_regs_ever_live_p (regno
)
739 && !call_used_regs
[regno
])
740 || (regno
== PIC_OFFSET_TABLE_REGNUM
742 /* It is saved anyway, if there would be a gap. */
744 && df_regs_ever_live_p (regno
+ 1)
745 && !call_used_regs
[regno
+ 1]))))
746 && (regno
!= FRAME_POINTER_REGNUM
|| !frame_pointer_needed
)
747 && regno
!= CRIS_SRP_REGNUM
)
748 || (crtl
->calls_eh_return
749 && (regno
== EH_RETURN_DATA_REGNO (0)
750 || regno
== EH_RETURN_DATA_REGNO (1)
751 || regno
== EH_RETURN_DATA_REGNO (2)
752 || regno
== EH_RETURN_DATA_REGNO (3)));
755 /* The PRINT_OPERAND worker. */
758 cris_print_operand (FILE *file
, rtx x
, int code
)
762 /* Size-strings corresponding to MULT expressions. */
763 static const char *const mults
[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
765 /* New code entries should just be added to the switch below. If
766 handling is finished, just return. If handling was just a
767 modification of the operand, the modified operand should be put in
768 "operand", and then do a break to let default handling
769 (zero-modifier) output the operand. */
774 /* Print the unsigned supplied integer as if it were signed
775 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */
776 if (!satisfies_constraint_O (x
))
777 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x
);
778 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
779 INTVAL (x
)| (INTVAL (x
) <= 255 ? ~255 : ~65535));
783 /* Print assembler code for operator. */
784 fprintf (file
, "%s", cris_op_str (operand
));
789 /* A movem modifier working on a parallel; output the register
793 if (GET_CODE (x
) != PARALLEL
)
794 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x
);
796 /* The second item can be (set reg (plus reg const)) to denote a
799 = (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
801 : XVECLEN (x
, 0) - 1);
803 fprintf (file
, "$%s", reg_names
[regno
]);
809 /* A similar movem modifier; output the memory operand. */
812 if (GET_CODE (x
) != PARALLEL
)
813 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x
);
815 /* The lowest mem operand is in the first item, but perhaps it
816 needs to be output as postincremented. */
817 addr
= MEM_P (SET_SRC (XVECEXP (x
, 0, 0)))
818 ? XEXP (SET_SRC (XVECEXP (x
, 0, 0)), 0)
819 : XEXP (SET_DEST (XVECEXP (x
, 0, 0)), 0);
821 /* The second item can be a (set reg (plus reg const)) to denote
823 if (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
)
825 /* It's a post-increment, if the address is a naked (reg). */
827 addr
= gen_rtx_POST_INC (SImode
, addr
);
830 /* Otherwise, it's a side-effect; RN=RN+M. */
831 fprintf (file
, "[$%s=$%s%s%d]",
832 reg_names
[REGNO (SET_DEST (XVECEXP (x
, 0, 1)))],
833 reg_names
[REGNO (XEXP (addr
, 0))],
834 INTVAL (XEXP (addr
, 1)) < 0 ? "" : "+",
835 (int) INTVAL (XEXP (addr
, 1)));
839 output_address (addr
);
844 /* Adjust a power of two to its log2. */
845 if (!CONST_INT_P (x
) || exact_log2 (INTVAL (x
)) < 0 )
846 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x
);
847 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
851 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
852 respectively. This modifier also terminates the inhibiting
853 effects of the 'x' modifier. */
854 cris_output_insn_is_bound
= 0;
855 if (GET_MODE (x
) == VOIDmode
&& CONST_INT_P (x
))
859 if (INTVAL (x
) <= 255)
861 else if (INTVAL (x
) <= 65535)
871 /* For a non-integer, print the size of the operand. */
872 putc ((GET_MODE (x
) == SImode
|| GET_MODE (x
) == SFmode
)
873 ? 'd' : GET_MODE (x
) == HImode
? 'w'
874 : GET_MODE (x
) == QImode
? 'b'
875 /* If none of the above, emit an erroneous size letter. */
881 /* Const_int: print b for -127 <= x <= 255,
882 w for -32768 <= x <= 65535, else die. */
884 || INTVAL (x
) < -32768 || INTVAL (x
) > 65535)
885 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x
);
886 putc (INTVAL (x
) >= -128 && INTVAL (x
) <= 255 ? 'b' : 'w', file
);
890 /* If this is a GOT-symbol, print the size-letter corresponding to
891 -fpic/-fPIC. For everything else, print "d". */
893 && GET_CODE (x
) == CONST
894 && GET_CODE (XEXP (x
, 0)) == UNSPEC
895 && XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREAD
)
900 /* Output a 'nop' if there's nothing for the delay slot.
901 This method stolen from the sparc files. */
902 if (dbr_sequence_length () == 0)
903 fputs ("\n\tnop", file
);
907 /* Output directive for alignment padded with "nop" insns.
908 Optimizing for size, it's plain 4-byte alignment, otherwise we
909 align the section to a cache-line (32 bytes) and skip at max 2
910 bytes, i.e. we skip if it's the last insn on a cache-line. The
911 latter is faster by a small amount (for two test-programs 99.6%
912 and 99.9%) and larger by a small amount (ditto 100.1% and
913 100.2%). This is supposed to be the simplest yet performance-
914 wise least intrusive way to make sure the immediately following
915 (supposed) muls/mulu insn isn't located at the end of a
919 ? ".p2alignw 2,0x050f\n\t"
920 : ".p2alignw 5,0x050f,2\n\t", file
);
924 /* The PIC register. */
926 internal_error ("invalid use of ':' modifier");
927 fprintf (file
, "$%s", reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
931 /* Print high (most significant) part of something. */
932 switch (GET_CODE (operand
))
935 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
936 value is kept here, and so may be other than 0 or -1. */
937 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
938 INTVAL (operand_subword (operand
, 1, 0, DImode
)));
942 /* High part of a long long constant. */
943 if (GET_MODE (operand
) == VOIDmode
)
945 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_HIGH (x
));
949 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
952 /* Print reg + 1. Check that there's not an attempt to print
953 high-parts of registers like stack-pointer or higher, except
954 for SRP (where the "high part" is MOF). */
955 if (REGNO (operand
) > STACK_POINTER_REGNUM
- 2
956 && (REGNO (operand
) != CRIS_SRP_REGNUM
957 || CRIS_SRP_REGNUM
+ 1 != CRIS_MOF_REGNUM
958 || fixed_regs
[CRIS_MOF_REGNUM
] != 0))
959 LOSE_AND_RETURN ("bad register", operand
);
960 fprintf (file
, "$%s", reg_names
[REGNO (operand
) + 1]);
964 /* Adjust memory address to high part. */
966 rtx adj_mem
= operand
;
968 = GET_MODE_BITSIZE (GET_MODE (operand
)) / BITS_PER_UNIT
;
970 /* Adjust so we can use two SImode in DImode.
971 Calling adj_offsettable_operand will make sure it is an
972 offsettable address. Don't do this for a postincrement
973 though; it should remain as it was. */
974 if (GET_CODE (XEXP (adj_mem
, 0)) != POST_INC
)
976 = adjust_address (adj_mem
, GET_MODE (adj_mem
), size
/ 2);
978 output_address (XEXP (adj_mem
, 0));
983 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
987 /* Strip the MEM expression. */
988 operand
= XEXP (operand
, 0);
992 /* Like 'E', but ignore state set by 'x'. FIXME: Use code
993 iterators and attributes in cris.md to avoid the need for %x
994 and %E (and %e) and state passed between those modifiers. */
995 cris_output_insn_is_bound
= 0;
998 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
999 cris_output_insn_is_bound is nonzero. */
1000 if (GET_CODE (operand
) != SIGN_EXTEND
1001 && GET_CODE (operand
) != ZERO_EXTEND
1002 && !CONST_INT_P (operand
))
1003 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x
);
1005 if (cris_output_insn_is_bound
)
1007 cris_output_insn_is_bound
= 0;
1011 putc (GET_CODE (operand
) == SIGN_EXTEND
1012 || (CONST_INT_P (operand
) && INTVAL (operand
) < 0)
1017 /* Print the size letter of the inner element. We can do it by
1018 calling ourselves with the 's' modifier. */
1019 if (GET_CODE (operand
) != SIGN_EXTEND
&& GET_CODE (operand
) != ZERO_EXTEND
)
1020 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x
);
1021 cris_print_operand (file
, XEXP (operand
, 0), 's');
1025 /* Print the least significant part of operand. */
1026 if (GET_CODE (operand
) == CONST_DOUBLE
)
1028 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_LOW (x
));
1031 else if (HOST_BITS_PER_WIDE_INT
> 32 && CONST_INT_P (operand
))
1033 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
1034 INTVAL (x
) & ((unsigned int) 0x7fffffff * 2 + 1));
1037 /* Otherwise the least significant part equals the normal part,
1038 so handle it normally. */
1042 /* When emitting an add for the high part of a DImode constant, we
1043 want to use addq for 0 and adds.w for -1. */
1044 if (!CONST_INT_P (operand
))
1045 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x
);
1046 fprintf (file
, INTVAL (operand
) < 0 ? "adds.w" : "addq");
1050 /* For const_int operands, print the additive mnemonic and the
1051 modified operand (byte-sized operands don't save anything):
1052 N=MIN_INT..-65536: add.d N
1053 -65535..-64: subu.w -N
1057 65536..MAX_INT: add.d N.
1058 (Emitted mnemonics are capitalized to simplify testing.)
1059 For anything else (N.B: only register is valid), print "add.d". */
1060 if (REG_P (operand
))
1062 fprintf (file
, "Add.d ");
1064 /* Deal with printing the operand by dropping through to the
1071 gcc_assert (CONST_INT_P (operand
));
1073 val
= INTVAL (operand
);
1074 if (!IN_RANGE (val
, -65535, 65535))
1075 fprintf (file
, "Add.d %d", val
);
1076 else if (val
<= -64)
1077 fprintf (file
, "Subu.w %d", -val
);
1079 fprintf (file
, "Subq %d", -val
);
1081 fprintf (file
, "Addq %d", val
);
1082 else if (val
<= 65535)
1083 fprintf (file
, "Addu.w %d", val
);
1089 /* If the operand is an integer -31..31, print "q" else ".d". */
1090 if (CONST_INT_P (operand
) && IN_RANGE (INTVAL (operand
), -31, 31))
1091 fprintf (file
, "q");
1093 fprintf (file
, ".d");
1097 /* If this is a GOT symbol, force it to be emitted as :GOT and
1098 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16).
1099 Avoid making this too much of a special case. */
1100 if (flag_pic
== 1 && CRIS_CONSTANT_P (operand
))
1102 int flag_pic_save
= flag_pic
;
1105 cris_output_addr_const (file
, operand
);
1106 flag_pic
= flag_pic_save
;
1112 /* When emitting an sub for the high part of a DImode constant, we
1113 want to use subq for 0 and subs.w for -1. */
1114 if (!CONST_INT_P (operand
))
1115 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x
);
1116 fprintf (file
, INTVAL (operand
) < 0 ? "subs.w" : "subq");
1120 /* Print the operand as the index-part of an address.
1121 Easiest way out is to use cris_print_index. */
1122 cris_print_index (operand
, file
);
1126 /* Print the size letter for an operand to a MULT, which must be a
1127 const_int with a suitable value. */
1128 if (!CONST_INT_P (operand
) || INTVAL (operand
) > 4)
1129 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x
);
1130 fprintf (file
, "%s", mults
[INTVAL (operand
)]);
1134 /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */
1136 && GET_CODE (operand
) == CONST
1137 && GET_CODE (XEXP (operand
, 0)) == UNSPEC
1138 && XINT (XEXP (operand
, 0), 1) == CRIS_UNSPEC_GOTREAD
)
1139 fprintf (file
, "u.w");
1141 fprintf (file
, ".d");
1145 /* No code, print as usual. */
1149 LOSE_AND_RETURN ("invalid operand modifier letter", x
);
1152 /* Print an operand as without a modifier letter. */
1153 switch (GET_CODE (operand
))
1156 if (REGNO (operand
) > 15
1157 && REGNO (operand
) != CRIS_MOF_REGNUM
1158 && REGNO (operand
) != CRIS_SRP_REGNUM
1159 && REGNO (operand
) != CRIS_CC0_REGNUM
)
1160 internal_error ("internal error: bad register: %d", REGNO (operand
));
1161 fprintf (file
, "$%s", reg_names
[REGNO (operand
)]);
1165 output_address (XEXP (operand
, 0));
1169 if (GET_MODE (operand
) == VOIDmode
)
1170 /* A long long constant. */
1171 output_addr_const (file
, operand
);
1174 /* Only single precision is allowed as plain operands the
1175 moment. FIXME: REAL_VALUE_FROM_CONST_DOUBLE isn't
1180 /* FIXME: Perhaps check overflow of the "single". */
1181 REAL_VALUE_FROM_CONST_DOUBLE (r
, operand
);
1182 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
1184 fprintf (file
, "0x%lx", l
);
1191 cris_output_addr_const (file
, operand
);
1197 /* For a (MULT (reg X) const_int) we output "rX.S". */
1198 int i
= CONST_INT_P (XEXP (operand
, 1))
1199 ? INTVAL (XEXP (operand
, 1)) : INTVAL (XEXP (operand
, 0));
1200 rtx reg
= CONST_INT_P (XEXP (operand
, 1))
1201 ? XEXP (operand
, 0) : XEXP (operand
, 1);
1204 || (!CONST_INT_P (XEXP (operand
, 0))
1205 && !CONST_INT_P (XEXP (operand
, 1))))
1206 LOSE_AND_RETURN ("unexpected multiplicative operand", x
);
1208 cris_print_base (reg
, file
);
1209 fprintf (file
, ".%c",
1210 i
== 0 || (i
== 1 && GET_CODE (operand
) == MULT
) ? 'b'
1212 : (i
== 2 && GET_CODE (operand
) == MULT
) || i
== 1 ? 'w'
1218 /* No need to handle all strange variants, let output_addr_const
1220 if (CRIS_CONSTANT_P (operand
))
1222 cris_output_addr_const (file
, operand
);
1226 LOSE_AND_RETURN ("unexpected operand", x
);
1231 cris_print_operand_punct_valid_p (unsigned char code
)
1233 return (code
== '#' || code
== '!' || code
== ':');
1236 /* The PRINT_OPERAND_ADDRESS worker. */
1239 cris_print_operand_address (FILE *file
, rtx x
)
1241 /* All these were inside MEM:s so output indirection characters. */
1244 if (CONSTANT_ADDRESS_P (x
))
1245 cris_output_addr_const (file
, x
);
1246 else if (cris_base_or_autoincr_p (x
, true))
1247 cris_print_base (x
, file
);
1248 else if (GET_CODE (x
) == PLUS
)
1254 if (cris_base_p (x1
, true))
1256 cris_print_base (x1
, file
);
1257 cris_print_index (x2
, file
);
1259 else if (cris_base_p (x2
, true))
1261 cris_print_base (x2
, file
);
1262 cris_print_index (x1
, file
);
1265 LOSE_AND_RETURN ("unrecognized address", x
);
1269 /* A DIP. Output more indirection characters. */
1271 cris_print_base (XEXP (x
, 0), file
);
1275 LOSE_AND_RETURN ("unrecognized address", x
);
1280 /* The RETURN_ADDR_RTX worker.
1281 We mark that the return address is used, either by EH or
1282 __builtin_return_address, for use by the function prologue and
1283 epilogue. FIXME: This isn't optimal; we just use the mark in the
1284 prologue and epilogue to say that the return address is to be stored
1285 in the stack frame. We could return SRP for leaf-functions and use the
1286 initial-value machinery. */
1289 cris_return_addr_rtx (int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
1291 cfun
->machine
->needs_return_address_on_stack
= 1;
1293 /* The return-address is stored just above the saved frame-pointer (if
1294 present). Apparently we can't eliminate from the frame-pointer in
1295 that direction, so use the incoming args (maybe pretended) pointer. */
1297 ? gen_rtx_MEM (Pmode
, plus_constant (Pmode
, virtual_incoming_args_rtx
, -4))
1301 /* Accessor used in cris.md:return because cfun->machine isn't available
1305 cris_return_address_on_stack (void)
1307 return df_regs_ever_live_p (CRIS_SRP_REGNUM
)
1308 || cfun
->machine
->needs_return_address_on_stack
;
1311 /* Accessor used in cris.md:return because cfun->machine isn't available
1315 cris_return_address_on_stack_for_return (void)
1317 return cfun
->machine
->return_type
== CRIS_RETINSN_RET
? false
1318 : cris_return_address_on_stack ();
1321 /* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only
1322 handles FP -> SP elimination offset. */
1325 cris_initial_frame_pointer_offset (void)
1329 /* Initial offset is 0 if we don't have a frame pointer. */
1331 bool got_really_used
= false;
1333 if (crtl
->uses_pic_offset_table
)
1335 push_topmost_sequence ();
1337 = reg_used_between_p (pic_offset_table_rtx
, get_insns (),
1339 pop_topmost_sequence ();
1342 /* And 4 for each register pushed. */
1343 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1344 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
1347 /* And then, last, we add the locals allocated. */
1348 offs
+= get_frame_size ();
1350 /* And more; the accumulated args size. */
1351 offs
+= crtl
->outgoing_args_size
;
1353 /* Then round it off, in case we use aligned stack. */
1354 if (TARGET_STACK_ALIGN
)
1355 offs
= TARGET_ALIGN_BY_32
? (offs
+ 3) & ~3 : (offs
+ 1) & ~1;
1360 /* The INITIAL_ELIMINATION_OFFSET worker.
1361 Calculate the difference between imaginary registers such as frame
1362 pointer and the stack pointer. Used to eliminate the frame pointer
1363 and imaginary arg pointer. */
1366 cris_initial_elimination_offset (int fromreg
, int toreg
)
1369 = cris_initial_frame_pointer_offset ();
1371 /* We should be able to use regs_ever_live and related prologue
1372 information here, or alpha should not as well. */
1373 bool return_address_on_stack
= cris_return_address_on_stack ();
1375 /* Here we act as if the frame-pointer were needed. */
1376 int ap_fp_offset
= 4 + (return_address_on_stack
? 4 : 0);
1378 if (fromreg
== ARG_POINTER_REGNUM
1379 && toreg
== FRAME_POINTER_REGNUM
)
1380 return ap_fp_offset
;
1382 /* Between the frame pointer and the stack are only "normal" stack
1383 variables and saved registers. */
1384 if (fromreg
== FRAME_POINTER_REGNUM
1385 && toreg
== STACK_POINTER_REGNUM
)
1386 return fp_sp_offset
;
1388 /* We need to balance out the frame pointer here. */
1389 if (fromreg
== ARG_POINTER_REGNUM
1390 && toreg
== STACK_POINTER_REGNUM
)
1391 return ap_fp_offset
+ fp_sp_offset
- 4;
1396 /* Nonzero if X is a hard reg that can be used as an index. */
1398 reg_ok_for_base_p (const_rtx x
, bool strict
)
1400 return ((! strict
&& ! HARD_REGISTER_P (x
))
1401 || REGNO_OK_FOR_BASE_P (REGNO (x
)));
1404 /* Nonzero if X is a hard reg that can be used as an index. */
1406 reg_ok_for_index_p (const_rtx x
, bool strict
)
1408 return reg_ok_for_base_p (x
, strict
);
1411 /* No symbol can be used as an index (or more correct, as a base) together
1412 with a register with PIC; the PIC register must be there. */
1415 cris_constant_index_p (const_rtx x
)
1417 return (CRIS_CONSTANT_P (x
) && (!flag_pic
|| cris_valid_pic_const (x
, true)));
1420 /* True if X is a valid base register. */
1423 cris_base_p (const_rtx x
, bool strict
)
1425 return (REG_P (x
) && reg_ok_for_base_p (x
, strict
));
1428 /* True if X is a valid index register. */
1431 cris_index_p (const_rtx x
, bool strict
)
1433 return (REG_P (x
) && reg_ok_for_index_p (x
, strict
));
1436 /* True if X is a valid base register with or without autoincrement. */
1439 cris_base_or_autoincr_p (const_rtx x
, bool strict
)
1441 return (cris_base_p (x
, strict
)
1442 || (GET_CODE (x
) == POST_INC
1443 && cris_base_p (XEXP (x
, 0), strict
)
1444 && REGNO (XEXP (x
, 0)) != CRIS_ACR_REGNUM
));
1447 /* True if X is a valid (register) index for BDAP, i.e. [Rs].S or [Rs+].S. */
1450 cris_bdap_index_p (const_rtx x
, bool strict
)
1453 && GET_MODE (x
) == SImode
1454 && cris_base_or_autoincr_p (XEXP (x
, 0), strict
))
1455 || (GET_CODE (x
) == SIGN_EXTEND
1456 && MEM_P (XEXP (x
, 0))
1457 && (GET_MODE (XEXP (x
, 0)) == HImode
1458 || GET_MODE (XEXP (x
, 0)) == QImode
)
1459 && cris_base_or_autoincr_p (XEXP (XEXP (x
, 0), 0), strict
)));
1462 /* True if X is a valid (register) index for BIAP, i.e. Rd.m. */
1465 cris_biap_index_p (const_rtx x
, bool strict
)
1467 return (cris_index_p (x
, strict
)
1468 || (GET_CODE (x
) == MULT
1469 && cris_index_p (XEXP (x
, 0), strict
)
1470 && cris_scale_int_operand (XEXP (x
, 1), VOIDmode
)));
1473 /* Worker function for TARGET_LEGITIMATE_ADDRESS_P.
1475 A PIC operand looks like a normal symbol here. At output we dress it
1476 in "[rPIC+symbol:GOT]" (global symbol) or "rPIC+symbol:GOTOFF" (local
1477 symbol) so we exclude all addressing modes where we can't replace a
1478 plain "symbol" with that. A global PIC symbol does not fit anywhere
1479 here (but is thankfully a general_operand in itself). A local PIC
1480 symbol is valid for the plain "symbol + offset" case. */
1483 cris_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
1487 if (cris_base_or_autoincr_p (x
, strict
))
1489 else if (TARGET_V32
)
1490 /* Nothing else is valid then. */
1492 else if (cris_constant_index_p (x
))
1495 else if (GET_CODE (x
) == PLUS
)
1500 if ((cris_base_p (x1
, strict
) && cris_constant_index_p (x2
))
1501 || (cris_base_p (x2
, strict
) && cris_constant_index_p (x1
))
1502 /* BDAP Rs[+], Rd. */
1503 || (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1504 && ((cris_base_p (x1
, strict
)
1505 && cris_bdap_index_p (x2
, strict
))
1506 || (cris_base_p (x2
, strict
)
1507 && cris_bdap_index_p (x1
, strict
))
1509 || (cris_base_p (x1
, strict
)
1510 && cris_biap_index_p (x2
, strict
))
1511 || (cris_base_p (x2
, strict
)
1512 && cris_biap_index_p (x1
, strict
)))))
1517 /* DIP (Rs). Reject [[reg+]] and [[reg]] for DImode (long long). */
1518 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1519 && cris_base_or_autoincr_p (XEXP (x
, 0), strict
))
1526 /* Worker function for TARGET_LEGITIMATE_CONSTANT_P. We have to handle
1527 PIC constants that aren't legitimized. FIXME: there used to be a
1528 guarantee that the target LEGITIMATE_CONSTANT_P didn't have to handle
1529 PIC constants, but no more (4.7 era); testcase: glibc init-first.c.
1530 While that may be seen as a bug, that guarantee seems a wart by design,
1531 so don't bother; fix the documentation instead. */
1534 cris_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1536 enum cris_symbol_type t
;
1539 return LEGITIMATE_PIC_OPERAND_P (x
);
1541 t
= cris_symbol_type_of (x
);
1545 || t
== cris_offsettable_symbol
1546 || t
== cris_unspec
;
1549 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */
1552 cris_reload_address_legitimized (rtx x
,
1553 machine_mode mode ATTRIBUTE_UNUSED
,
1554 int opnum ATTRIBUTE_UNUSED
,
1556 int ind_levels ATTRIBUTE_UNUSED
)
1558 enum reload_type type
= (enum reload_type
) itype
;
1562 if (GET_CODE (x
) != PLUS
)
1570 op1p
= &XEXP (x
, 1);
1575 if (GET_CODE (op0
) == SIGN_EXTEND
&& MEM_P (XEXP (op0
, 0)))
1577 rtx op00
= XEXP (op0
, 0);
1578 rtx op000
= XEXP (op00
, 0);
1579 rtx
*op000p
= &XEXP (op00
, 0);
1581 if ((GET_MODE (op00
) == HImode
|| GET_MODE (op00
) == QImode
)
1583 || (GET_CODE (op000
) == POST_INC
&& REG_P (XEXP (op000
, 0)))))
1585 bool something_reloaded
= false;
1587 if (GET_CODE (op000
) == POST_INC
1588 && REG_P (XEXP (op000
, 0))
1589 && REGNO (XEXP (op000
, 0)) > CRIS_LAST_GENERAL_REGISTER
)
1590 /* No, this gets too complicated and is too rare to care
1591 about trying to improve on the general code Here.
1592 As the return-value is an all-or-nothing indicator, we
1593 punt on the other register too. */
1597 && REGNO (op000
) > CRIS_LAST_GENERAL_REGISTER
))
1599 /* The address of the inner mem is a pseudo or wrong
1600 reg: reload that. */
1601 push_reload (op000
, NULL_RTX
, op000p
, NULL
, GENERAL_REGS
,
1602 GET_MODE (x
), VOIDmode
, 0, 0, opnum
, type
);
1603 something_reloaded
= true;
1606 if (REGNO (op1
) > CRIS_LAST_GENERAL_REGISTER
)
1608 /* Base register is a pseudo or wrong reg: reload it. */
1609 push_reload (op1
, NULL_RTX
, op1p
, NULL
, GENERAL_REGS
,
1610 GET_MODE (x
), VOIDmode
, 0, 0,
1612 something_reloaded
= true;
1615 gcc_assert (something_reloaded
);
1625 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS.
1627 It seems like gcc (2.7.2 and 2.9x of 2000-03-22) may send "NO_REGS" as
1628 the class for a constant (testcase: __Mul in arit.c). To avoid forcing
1629 out a constant into the constant pool, we will trap this case and
1630 return something a bit more sane. FIXME: Check if this is a bug.
1631 Beware that we must not "override" classes that can be specified as
1632 constraint letters, or else asm operands using them will fail when
1633 they need to be reloaded. FIXME: Investigate whether that constitutes
1637 cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED
, reg_class_t rclass
)
1639 if (rclass
!= ACR_REGS
1640 && rclass
!= MOF_REGS
1641 && rclass
!= MOF_SRP_REGS
1642 && rclass
!= SRP_REGS
1643 && rclass
!= CC0_REGS
1644 && rclass
!= SPECIAL_REGS
)
1645 return GENERAL_REGS
;
1650 /* Worker function for TARGET_REGISTER_MOVE_COST. */
1653 cris_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
1654 reg_class_t from
, reg_class_t to
)
1656 /* Can't move to and from a SPECIAL_REGS register, so we have to say
1657 their move cost within that class is higher. How about 7? That's 3
1658 for a move to a GENERAL_REGS register, 3 for the move from the
1659 GENERAL_REGS register, and 1 for the increased register pressure.
1660 Also, it's higher than the memory move cost, as it should.
1661 We also do this for ALL_REGS, since we don't want that class to be
1662 preferred (even to memory) at all where GENERAL_REGS doesn't fit.
1663 Whenever it's about to be used, it's for SPECIAL_REGS. If we don't
1664 present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be
1665 used when a GENERAL_REGS should be used, even if there are call-saved
1666 GENERAL_REGS left to allocate. This is because the fall-back when
1667 the most preferred register class isn't available, isn't the next
1668 (or next good) wider register class, but the *most widest* register
1669 class. FIXME: pre-IRA comment, perhaps obsolete now. */
1671 if ((reg_classes_intersect_p (from
, SPECIAL_REGS
)
1672 && reg_classes_intersect_p (to
, SPECIAL_REGS
))
1673 || from
== ALL_REGS
|| to
== ALL_REGS
)
1676 /* Make moves to/from SPECIAL_REGS slightly more expensive, as we
1677 generally prefer GENERAL_REGS. */
1678 if (reg_classes_intersect_p (from
, SPECIAL_REGS
)
1679 || reg_classes_intersect_p (to
, SPECIAL_REGS
))
1685 /* Worker function for TARGET_MEMORY_MOVE_COST.
1687 This isn't strictly correct for v0..3 in buswidth-8bit mode, but should
1691 cris_memory_move_cost (machine_mode mode
,
1692 reg_class_t rclass ATTRIBUTE_UNUSED
,
1693 bool in ATTRIBUTE_UNUSED
)
1702 /* Worker for cris_notice_update_cc; handles the "normal" cases.
1703 FIXME: this code is historical; its functionality should be
1704 refactored to look at insn attributes and moved to
1705 cris_notice_update_cc. Except, we better lose cc0 entirely. */
1708 cris_normal_notice_update_cc (rtx exp
, rtx insn
)
1710 /* "Normal" means, for:
1715 CC is (reg) and (...) - unless (...) is 0 or reg is a special
1716 register or (v32 and (...) is -32..-1), then CC does not change.
1717 CC_NO_OVERFLOW unless (...) is reg or mem.
1726 (set (reg1) (mem (bdap/biap)))
1727 (set (reg2) (bdap/biap))):
1728 CC is (reg1) and (mem (reg2))
1731 (set (mem (bdap/biap)) (reg1)) [or 0]
1732 (set (reg2) (bdap/biap))):
1735 (where reg and mem includes strict_low_parts variants thereof)
1737 For all others, assume CC is clobbered.
1738 Note that we do not have to care about setting CC_NO_OVERFLOW,
1739 since the overflow flag is set to 0 (i.e. right) for
1740 instructions where it does not have any sane sense, but where
1741 other flags have meanings. (This includes shifts; the carry is
1744 Note that there are other parallel constructs we could match,
1745 but we don't do that yet. */
1747 if (GET_CODE (exp
) == SET
)
1749 /* FIXME: Check when this happens. It looks like we should
1750 actually do a CC_STATUS_INIT here to be safe. */
1751 if (SET_DEST (exp
) == pc_rtx
)
1754 /* Record CC0 changes, so we do not have to output multiple
1756 if (SET_DEST (exp
) == cc0_rtx
)
1760 if (GET_CODE (SET_SRC (exp
)) == COMPARE
1761 && XEXP (SET_SRC (exp
), 1) == const0_rtx
)
1762 cc_status
.value1
= XEXP (SET_SRC (exp
), 0);
1764 cc_status
.value1
= SET_SRC (exp
);
1766 /* Handle flags for the special btstq on one bit. */
1767 if (GET_CODE (cc_status
.value1
) == ZERO_EXTRACT
1768 && XEXP (cc_status
.value1
, 1) == const1_rtx
)
1770 if (CONST_INT_P (XEXP (cc_status
.value1
, 0)))
1772 cc_status
.flags
= CC_INVERTED
;
1774 /* A one-bit btstq. */
1775 cc_status
.flags
= CC_Z_IN_NOT_N
;
1778 else if (GET_CODE (SET_SRC (exp
)) == COMPARE
)
1780 if (!REG_P (XEXP (SET_SRC (exp
), 0))
1781 && XEXP (SET_SRC (exp
), 1) != const0_rtx
)
1782 /* For some reason gcc will not canonicalize compare
1783 operations, reversing the sign by itself if
1784 operands are in wrong order. */
1785 /* (But NOT inverted; eq is still eq.) */
1786 cc_status
.flags
= CC_REVERSED
;
1788 /* This seems to be overlooked by gcc. FIXME: Check again.
1789 FIXME: Is it really safe? */
1791 = gen_rtx_MINUS (GET_MODE (SET_SRC (exp
)),
1792 XEXP (SET_SRC (exp
), 0),
1793 XEXP (SET_SRC (exp
), 1));
1797 else if (REG_P (SET_DEST (exp
))
1798 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1799 && REG_P (XEXP (SET_DEST (exp
), 0))))
1801 /* A register is set; normally CC is set to show that no
1802 test insn is needed. Catch the exceptions. */
1804 /* If not to cc0, then no "set"s in non-natural mode give
1806 if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp
))) > UNITS_PER_WORD
1807 || GET_MODE_CLASS (GET_MODE (SET_DEST (exp
))) == MODE_FLOAT
)
1809 /* ... except add:s and sub:s in DImode. */
1810 if (GET_MODE (SET_DEST (exp
)) == DImode
1811 && (GET_CODE (SET_SRC (exp
)) == PLUS
1812 || GET_CODE (SET_SRC (exp
)) == MINUS
))
1815 cc_status
.value1
= SET_DEST (exp
);
1816 cc_status
.value2
= SET_SRC (exp
);
1818 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1820 cc_status
.value2
= 0;
1822 /* Add and sub may set V, which gets us
1823 unoptimizable results in "gt" and "le" condition
1825 cc_status
.flags
|= CC_NO_OVERFLOW
;
1830 else if (SET_SRC (exp
) == const0_rtx
1831 || (REG_P (SET_SRC (exp
))
1832 && (REGNO (SET_SRC (exp
))
1833 > CRIS_LAST_GENERAL_REGISTER
))
1835 && REG_P (SET_DEST (exp
))
1836 && satisfies_constraint_I (SET_SRC (exp
))))
1838 /* There's no CC0 change for this case. Just check
1840 if (cc_status
.value1
1841 && modified_in_p (cc_status
.value1
, insn
))
1842 cc_status
.value1
= 0;
1844 if (cc_status
.value2
1845 && modified_in_p (cc_status
.value2
, insn
))
1846 cc_status
.value2
= 0;
1853 cc_status
.value1
= SET_DEST (exp
);
1854 cc_status
.value2
= SET_SRC (exp
);
1856 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1858 cc_status
.value2
= 0;
1860 /* Some operations may set V, which gets us
1861 unoptimizable results in "gt" and "le" condition
1863 if (GET_CODE (SET_SRC (exp
)) == PLUS
1864 || GET_CODE (SET_SRC (exp
)) == MINUS
1865 || GET_CODE (SET_SRC (exp
)) == NEG
)
1866 cc_status
.flags
|= CC_NO_OVERFLOW
;
1868 /* For V32, nothing with a register destination sets
1869 C and V usefully. */
1871 cc_status
.flags
|= CC_NO_OVERFLOW
;
1876 else if (MEM_P (SET_DEST (exp
))
1877 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1878 && MEM_P (XEXP (SET_DEST (exp
), 0))))
1880 /* When SET to MEM, then CC is not changed (except for
1882 if (cc_status
.value1
1883 && modified_in_p (cc_status
.value1
, insn
))
1884 cc_status
.value1
= 0;
1886 if (cc_status
.value2
1887 && modified_in_p (cc_status
.value2
, insn
))
1888 cc_status
.value2
= 0;
1893 else if (GET_CODE (exp
) == PARALLEL
)
1895 if (GET_CODE (XVECEXP (exp
, 0, 0)) == SET
1896 && GET_CODE (XVECEXP (exp
, 0, 1)) == SET
1897 && REG_P (XEXP (XVECEXP (exp
, 0, 1), 0)))
1899 if (REG_P (XEXP (XVECEXP (exp
, 0, 0), 0))
1900 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 1)))
1904 /* For "move.S [rx=ry+o],rz", say CC reflects
1905 value1=rz and value2=[rx] */
1906 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
1908 = replace_equiv_address (XEXP (XVECEXP (exp
, 0, 0), 1),
1909 XEXP (XVECEXP (exp
, 0, 1), 0));
1911 /* Huh? A side-effect cannot change the destination
1913 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1915 internal_error ("internal error: sideeffect-insn affecting main effect");
1917 /* For V32, moves to registers don't set C and V. */
1919 cc_status
.flags
|= CC_NO_OVERFLOW
;
1922 else if ((REG_P (XEXP (XVECEXP (exp
, 0, 0), 1))
1923 || XEXP (XVECEXP (exp
, 0, 0), 1) == const0_rtx
)
1924 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
1926 /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]",
1927 say flags are not changed, except for overlap. */
1928 if (cc_status
.value1
1929 && modified_in_p (cc_status
.value1
, insn
))
1930 cc_status
.value1
= 0;
1932 if (cc_status
.value2
1933 && modified_in_p (cc_status
.value2
, insn
))
1934 cc_status
.value2
= 0;
1941 /* If we got here, the case wasn't covered by the code above. */
1945 /* This function looks into the pattern to see how this insn affects
1948 Used when to eliminate test insns before a condition-code user,
1949 such as a "scc" insn or a conditional branch. This includes
1950 checking if the entities that cc was updated by, are changed by the
1953 Currently a jumble of the old peek-inside-the-insn and the newer
1954 check-cc-attribute methods. */
1957 cris_notice_update_cc (rtx exp
, rtx_insn
*insn
)
1959 enum attr_cc attrval
= get_attr_cc (insn
);
1961 /* Check if user specified "-mcc-init" as a bug-workaround. Remember
1962 to still set CC_REVERSED as below, since that's required by some
1963 compare insn alternatives. (FIXME: GCC should do this virtual
1964 operand swap by itself.) A test-case that may otherwise fail is
1965 gcc.c-torture/execute/20000217-1.c -O0 and -O1. */
1970 if (attrval
== CC_REV
)
1971 cc_status
.flags
= CC_REVERSED
;
1975 /* Slowly, we're converting to using attributes to control the setting
1976 of condition-code status. */
1980 /* Even if it is "none", a setting may clobber a previous
1981 cc-value, so check. */
1982 if (GET_CODE (exp
) == SET
)
1984 if (cc_status
.value1
1985 && modified_in_p (cc_status
.value1
, insn
))
1986 cc_status
.value1
= 0;
1988 if (cc_status
.value2
1989 && modified_in_p (cc_status
.value2
, insn
))
1990 cc_status
.value2
= 0;
2001 cris_normal_notice_update_cc (exp
, insn
);
2003 /* The "test" insn doesn't clear (carry and) overflow on V32. We
2004 can change bge => bpl and blt => bmi by passing on to the cc0
2005 user that V should not be considered; bgt and ble are taken
2006 care of by other methods (see {tst,cmp}{si,hi,qi}). */
2007 if (attrval
== CC_NOOV32
&& TARGET_V32
)
2008 cc_status
.flags
|= CC_NO_OVERFLOW
;
2012 internal_error ("unknown cc_attr value");
2018 /* Return != 0 if the return sequence for the current function is short,
2019 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if
2020 registers must be saved, so return 0 then. */
2023 cris_simple_epilogue (void)
2026 unsigned int reglimit
= STACK_POINTER_REGNUM
;
2027 bool got_really_used
= false;
2029 if (! reload_completed
2030 || frame_pointer_needed
2031 || get_frame_size () != 0
2032 || crtl
->args
.pretend_args_size
2034 || crtl
->outgoing_args_size
2035 || crtl
->calls_eh_return
2037 /* If we're not supposed to emit prologue and epilogue, we must
2038 not emit return-type instructions. */
2039 || !TARGET_PROLOGUE_EPILOGUE
)
2042 /* Can't return from stacked return address with v32. */
2043 if (TARGET_V32
&& cris_return_address_on_stack ())
2046 if (crtl
->uses_pic_offset_table
)
2048 push_topmost_sequence ();
2050 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
2051 pop_topmost_sequence ();
2054 /* No simple epilogue if there are saved registers. */
2055 for (regno
= 0; regno
< reglimit
; regno
++)
2056 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
2062 /* Emit checking that MEM is aligned for an access in MODE, failing
2063 that, executing a "break 8" (or call to abort, if "break 8" is
2067 cris_emit_trap_for_misalignment (rtx mem
)
2069 rtx addr
, reg
, ok_label
, andop
;
2071 int natural_alignment
;
2072 gcc_assert (MEM_P (mem
));
2074 natural_alignment
= GET_MODE_SIZE (GET_MODE (mem
));
2075 addr
= XEXP (mem
, 0);
2076 reg
= force_reg (Pmode
, addr
);
2077 ok_label
= gen_label_rtx ();
2079 /* This will yield a btstq without a separate register used, usually -
2080 with the exception for PRE hoisting the "and" but not the branch
2081 around the trap: see testsuite/gcc.target/cris/sync-3s.c. */
2082 andop
= gen_rtx_AND (Pmode
, reg
, GEN_INT (natural_alignment
- 1));
2083 emit_cmp_and_jump_insns (force_reg (SImode
, andop
), const0_rtx
, EQ
,
2084 NULL_RTX
, Pmode
, 1, ok_label
);
2085 jmp
= get_last_insn ();
2086 gcc_assert (JUMP_P (jmp
));
2088 predict_insn_def (jmp
, PRED_NORETURN
, TAKEN
);
2089 expand_builtin_trap ();
2090 emit_label (ok_label
);
2093 /* Expand a return insn (just one insn) marked as using SRP or stack
2094 slot depending on parameter ON_STACK. */
2097 cris_expand_return (bool on_stack
)
2099 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
2100 tell "ret" from "jump [sp+]". Some, but not all, other parts of
2101 GCC expect just (return) to do the right thing when optimizing, so
2102 we do that until they're fixed. Currently, all return insns in a
2103 function must be the same (not really a limiting factor) so we need
2104 to check that it doesn't change half-way through. */
2105 emit_jump_insn (ret_rtx
);
2107 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_RET
|| !on_stack
);
2108 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_JUMP
|| on_stack
);
2110 cfun
->machine
->return_type
2111 = on_stack
? CRIS_RETINSN_JUMP
: CRIS_RETINSN_RET
;
2114 /* Compute a (partial) cost for rtx X. Return true if the complete
2115 cost has been computed, and false if subexpressions should be
2116 scanned. In either case, *TOTAL contains the cost result. */
2119 cris_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
2126 HOST_WIDE_INT val
= INTVAL (x
);
2129 else if (val
< 32 && val
>= -32)
2131 /* Eight or 16 bits are a word and cycle more expensive. */
2132 else if (val
<= 32767 && val
>= -32768)
2134 /* A 32-bit constant (or very seldom, unsigned 16 bits) costs
2135 another word. FIXME: This isn't linear to 16 bits. */
2151 if (x
!= CONST0_RTX (GET_MODE (x
) == VOIDmode
? DImode
: GET_MODE (x
)))
2154 /* Make 0.0 cheap, else test-insns will not be used. */
2159 /* If we have one arm of an ADDI, make sure it gets the cost of
2160 one insn, i.e. zero cost for this operand, and just the cost
2161 of the PLUS, as the insn is created by combine from a PLUS
2162 and an ASHIFT, and the MULT cost below would make the
2163 combined value be larger than the separate insns. The insn
2164 validity is checked elsewhere by combine.
2166 FIXME: this case is a stop-gap for 4.3 and 4.4, this whole
2167 function should be rewritten. */
2168 if (outer_code
== PLUS
&& cris_biap_index_p (x
, false))
2174 /* Identify values that are no powers of two. Powers of 2 are
2175 taken care of already and those values should not be changed. */
2176 if (!CONST_INT_P (XEXP (x
, 1))
2177 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
2179 /* If we have a multiply insn, then the cost is between
2180 1 and 2 "fast" instructions. */
2181 if (TARGET_HAS_MUL_INSNS
)
2183 *total
= COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
2187 /* Estimate as 4 + 4 * #ofbits. */
2188 *total
= COSTS_N_INSNS (132);
2197 if (!CONST_INT_P (XEXP (x
, 1))
2198 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
2200 /* Estimate this as 4 + 8 * #of bits. */
2201 *total
= COSTS_N_INSNS (260);
2207 if (CONST_INT_P (XEXP (x
, 1))
2208 /* Two constants may actually happen before optimization. */
2209 && !CONST_INT_P (XEXP (x
, 0))
2210 && !satisfies_constraint_I (XEXP (x
, 1)))
2213 = (rtx_cost (XEXP (x
, 0), (enum rtx_code
) outer_code
,
2215 + 2 * GET_MODE_NUNITS (GET_MODE (XEXP (x
, 0))));
2221 if (outer_code
!= COMPARE
)
2225 case ZERO_EXTEND
: case SIGN_EXTEND
:
2226 *total
= rtx_cost (XEXP (x
, 0), (enum rtx_code
) outer_code
, opno
, speed
);
2234 /* The ADDRESS_COST worker. */
2237 cris_address_cost (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
,
2238 addr_space_t as ATTRIBUTE_UNUSED
,
2239 bool speed ATTRIBUTE_UNUSED
)
2241 /* The metric to use for the cost-macros is unclear.
2242 The metric used here is (the number of cycles needed) / 2,
2243 where we consider equal a cycle for a word of code and a cycle to
2244 read memory. FIXME: Adding "+ 1" to all values would avoid
2245 returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes"
2246 0 to 1, thereby giving equal costs to [rN + rM] and [rN].
2247 Unfortunately(?) such a hack would expose other pessimizations,
2248 at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the
2249 loop there, without apparent reason. */
2251 /* The cheapest addressing modes get 0, since nothing extra is needed. */
2252 if (cris_base_or_autoincr_p (x
, false))
2255 /* An indirect mem must be a DIP. This means two bytes extra for code,
2256 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */
2260 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
2261 an extra DIP prefix and 4 bytes of constant in most cases. */
2265 /* Handle BIAP and BDAP prefixes. */
2266 if (GET_CODE (x
) == PLUS
)
2268 rtx tem1
= XEXP (x
, 0);
2269 rtx tem2
= XEXP (x
, 1);
2271 /* Local extended canonicalization rule: the first operand must
2272 be REG, unless it's an operation (MULT). */
2273 if (!REG_P (tem1
) && GET_CODE (tem1
) != MULT
)
2274 tem1
= tem2
, tem2
= XEXP (x
, 0);
2276 /* We'll "assume" we have canonical RTX now. */
2277 gcc_assert (REG_P (tem1
) || GET_CODE (tem1
) == MULT
);
2279 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We
2280 recognize the typical MULT which is always in tem1 because of
2281 insn canonicalization. */
2282 if ((GET_CODE (tem1
) == MULT
&& cris_biap_index_p (tem1
, false))
2286 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the
2287 PLUS is always found in tem2. */
2288 if (CONST_INT_P (tem2
) && INTVAL (tem2
) < 128 && INTVAL (tem2
) >= -128)
2291 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
2293 if (satisfies_constraint_L (tem2
))
2296 /* A BDAP with some other constant is 2 bytes extra. */
2297 if (CRIS_CONSTANT_P (tem2
))
2298 return (2 + 2 + 2) / 2;
2300 /* BDAP with something indirect should have a higher cost than
2301 BIAP with register. FIXME: Should it cost like a MEM or more? */
2302 return (2 + 2 + 2) / 2;
2305 /* What else? Return a high cost. It matters only for valid
2306 addressing modes. */
2310 /* Check various objections to the side-effect. Used in the test-part
2311 of an anonymous insn describing an insn with a possible side-effect.
2312 Returns nonzero if the implied side-effect is ok.
2315 ops : An array of rtx:es. lreg, rreg, rval,
2316 The variables multop and other_op are indexes into this,
2317 or -1 if they are not applicable.
2318 lreg : The register that gets assigned in the side-effect.
2319 rreg : One register in the side-effect expression
2320 rval : The other register, or an int.
2321 multop : An integer to multiply rval with.
2322 other_op : One of the entities of the main effect,
2323 whose mode we must consider. */
2326 cris_side_effect_mode_ok (enum rtx_code code
, rtx
*ops
,
2327 int lreg
, int rreg
, int rval
,
2328 int multop
, int other_op
)
2330 /* Find what value to multiply with, for rx =ry + rz * n. */
2331 int mult
= multop
< 0 ? 1 : INTVAL (ops
[multop
]);
2333 rtx reg_rtx
= ops
[rreg
];
2334 rtx val_rtx
= ops
[rval
];
2336 /* The operands may be swapped. Canonicalize them in reg_rtx and
2337 val_rtx, where reg_rtx always is a reg (for this constraint to
2339 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2340 reg_rtx
= val_rtx
, val_rtx
= ops
[rreg
];
2342 /* Don't forget to check that reg_rtx really is a reg. If it isn't,
2343 we have no business. */
2344 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2347 /* Don't do this when -mno-split. */
2348 if (!TARGET_SIDE_EFFECT_PREFIXES
)
2351 /* The mult expression may be hidden in lreg. FIXME: Add more
2352 commentary about that. */
2353 if (GET_CODE (val_rtx
) == MULT
)
2355 mult
= INTVAL (XEXP (val_rtx
, 1));
2356 val_rtx
= XEXP (val_rtx
, 0);
2360 /* First check the "other operand". */
2363 if (GET_MODE_SIZE (GET_MODE (ops
[other_op
])) > UNITS_PER_WORD
)
2366 /* Check if the lvalue register is the same as the "other
2367 operand". If so, the result is undefined and we shouldn't do
2368 this. FIXME: Check again. */
2369 if ((cris_base_p (ops
[lreg
], reload_in_progress
|| reload_completed
)
2370 && cris_base_p (ops
[other_op
],
2371 reload_in_progress
|| reload_completed
)
2372 && REGNO (ops
[lreg
]) == REGNO (ops
[other_op
]))
2373 || rtx_equal_p (ops
[other_op
], ops
[lreg
]))
2377 /* Do not accept frame_pointer_rtx as any operand. */
2378 if (ops
[lreg
] == frame_pointer_rtx
|| ops
[rreg
] == frame_pointer_rtx
2379 || ops
[rval
] == frame_pointer_rtx
2380 || (other_op
>= 0 && ops
[other_op
] == frame_pointer_rtx
))
2384 && ! cris_base_p (val_rtx
, reload_in_progress
|| reload_completed
))
2387 /* Do not allow rx = rx + n if a normal add or sub with same size
2389 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2390 && CONST_INT_P (val_rtx
)
2391 && (INTVAL (val_rtx
) <= 63 && INTVAL (val_rtx
) >= -63))
2394 /* Check allowed cases, like [r(+)?].[bwd] and const. */
2395 if (CRIS_CONSTANT_P (val_rtx
))
2399 && cris_base_or_autoincr_p (XEXP (val_rtx
, 0),
2400 reload_in_progress
|| reload_completed
))
2403 if (GET_CODE (val_rtx
) == SIGN_EXTEND
2404 && MEM_P (XEXP (val_rtx
, 0))
2405 && cris_base_or_autoincr_p (XEXP (XEXP (val_rtx
, 0), 0),
2406 reload_in_progress
|| reload_completed
))
2409 /* If we got here, it's not a valid addressing mode. */
2412 else if (code
== MULT
2414 && cris_base_p (val_rtx
,
2415 reload_in_progress
|| reload_completed
)))
2417 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */
2418 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2419 || (mult
== 1 && rtx_equal_p (ops
[lreg
], val_rtx
)))
2422 /* Do not allow bad multiply-values. */
2423 if (mult
!= 1 && mult
!= 2 && mult
!= 4)
2426 /* Only allow r + ... */
2427 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2430 /* If we got here, all seems ok.
2431 (All checks need to be done above). */
2435 /* If we get here, the caller got its initial tests wrong. */
2436 internal_error ("internal error: cris_side_effect_mode_ok with bad operands");
2439 /* Whether next_cc0_user of insn is LE or GT or requires a real compare
2440 insn for other reasons. */
2443 cris_cc0_user_requires_cmp (rtx insn
)
2445 rtx_insn
*cc0_user
= NULL
;
2449 gcc_assert (insn
!= NULL
);
2454 cc0_user
= next_cc0_user (insn
);
2455 if (cc0_user
== NULL
)
2458 body
= PATTERN (cc0_user
);
2459 set
= single_set (cc0_user
);
2461 /* Users can be sCC and bCC. */
2462 if (JUMP_P (cc0_user
)
2463 && GET_CODE (body
) == SET
2464 && SET_DEST (body
) == pc_rtx
2465 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
2466 && XEXP (XEXP (SET_SRC (body
), 0), 0) == cc0_rtx
)
2469 GET_CODE (XEXP (SET_SRC (body
), 0)) == GT
2470 || GET_CODE (XEXP (SET_SRC (body
), 0)) == LE
;
2475 GET_CODE (SET_SRC (body
)) == GT
2476 || GET_CODE (SET_SRC (body
)) == LE
;
2482 /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16)
2483 does not handle the case where the IN operand is strict_low_part; it
2484 does handle it for X. Test-case in Axis-20010516. This function takes
2485 care of that for THIS port. FIXME: strict_low_part is going away
2489 cris_reg_overlap_mentioned_p (rtx x
, rtx in
)
2491 /* The function reg_overlap_mentioned now handles when X is
2492 strict_low_part, but not when IN is a STRICT_LOW_PART. */
2493 if (GET_CODE (in
) == STRICT_LOW_PART
)
2496 return reg_overlap_mentioned_p (x
, in
);
2499 /* Return TRUE iff X is a CONST valid for e.g. indexing.
2500 ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1
2504 cris_valid_pic_const (const_rtx x
, bool any_operand
)
2506 gcc_assert (flag_pic
);
2508 switch (GET_CODE (x
))
2517 if (GET_CODE (x
) != CONST
)
2522 /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */
2523 if (GET_CODE (x
) == PLUS
2524 && GET_CODE (XEXP (x
, 0)) == UNSPEC
2525 && (XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREL
2526 || XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_PCREL
)
2527 && CONST_INT_P (XEXP (x
, 1)))
2530 if (GET_CODE (x
) == UNSPEC
)
2531 switch (XINT (x
, 1))
2533 /* A PCREL operand is only valid for call and movsi. */
2534 case CRIS_UNSPEC_PLT_PCREL
:
2535 case CRIS_UNSPEC_PCREL
:
2536 return !any_operand
;
2538 case CRIS_UNSPEC_PLT_GOTREL
:
2539 case CRIS_UNSPEC_PLTGOTREAD
:
2540 case CRIS_UNSPEC_GOTREAD
:
2541 case CRIS_UNSPEC_GOTREL
:
2547 return cris_symbol_type_of (x
) == cris_no_symbol
;
2550 /* Helper function to find the right symbol-type to generate,
2551 given the original (non-PIC) representation. */
2553 enum cris_symbol_type
2554 cris_symbol_type_of (const_rtx x
)
2556 switch (GET_CODE (x
))
2560 ? (SYMBOL_REF_LOCAL_P (x
)
2561 ? cris_rel_symbol
: cris_got_symbol
)
2562 : cris_offsettable_symbol
;
2565 return flag_pic
? cris_rel_symbol
: cris_offsettable_symbol
;
2568 return cris_symbol_type_of (XEXP (x
, 0));
2573 enum cris_symbol_type t1
= cris_symbol_type_of (XEXP (x
, 0));
2574 enum cris_symbol_type t2
= cris_symbol_type_of (XEXP (x
, 1));
2576 gcc_assert (t1
== cris_no_symbol
|| t2
== cris_no_symbol
);
2578 if (t1
== cris_got_symbol
|| t2
== cris_got_symbol
)
2579 return cris_got_symbol_needing_fixup
;
2581 return t1
!= cris_no_symbol
? t1
: t2
;
2586 return cris_no_symbol
;
2592 fatal_insn ("unrecognized supposed constant", x
);
2598 /* The LEGITIMATE_PIC_OPERAND_P worker. */
2601 cris_legitimate_pic_operand (rtx x
)
2603 /* Symbols are not valid PIC operands as-is; just constants. */
2604 return cris_valid_pic_const (x
, true);
2607 /* Queue an .ident string in the queue of top-level asm statements.
2608 If the front-end is done, we must be being called from toplev.c.
2609 In that case, do nothing. */
2611 cris_asm_output_ident (const char *string
)
2613 if (symtab
->state
!= PARSING
)
2616 default_asm_output_ident_directive (string
);
2619 /* The ASM_OUTPUT_CASE_END worker. */
2622 cris_asm_output_case_end (FILE *stream
, int num
, rtx table
)
2624 /* Step back, over the label for the table, to the actual casejump and
2625 assert that we find only what's expected. */
2626 rtx whole_jump_insn
= prev_nonnote_nondebug_insn (table
);
2627 gcc_assert (whole_jump_insn
!= NULL_RTX
&& LABEL_P (whole_jump_insn
));
2628 whole_jump_insn
= prev_nonnote_nondebug_insn (whole_jump_insn
);
2629 gcc_assert (whole_jump_insn
!= NULL_RTX
2630 && (JUMP_P (whole_jump_insn
)
2631 || (TARGET_V32
&& INSN_P (whole_jump_insn
)
2632 && GET_CODE (PATTERN (whole_jump_insn
)) == SEQUENCE
)));
2633 /* Get the pattern of the casejump, so we can extract the default label. */
2634 whole_jump_insn
= PATTERN (whole_jump_insn
);
2638 /* This can be a SEQUENCE, meaning the delay-slot of the jump is
2639 filled. We also output the offset word a little differently. */
2641 = (GET_CODE (whole_jump_insn
) == SEQUENCE
2642 ? PATTERN (XVECEXP (whole_jump_insn
, 0, 0)) : whole_jump_insn
);
2644 asm_fprintf (stream
,
2645 "\t.word %LL%d-.%s\n",
2646 CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP
2647 (parallel_jump
, 0, 0),
2649 (TARGET_PDEBUG
? "; default" : ""));
2653 asm_fprintf (stream
,
2654 "\t.word %LL%d-%LL%d%s\n",
2655 CODE_LABEL_NUMBER (XEXP
2657 (XEXP (XVECEXP (whole_jump_insn
, 0, 0), 1),
2660 (TARGET_PDEBUG
? "; default" : ""));
2663 /* The TARGET_OPTION_OVERRIDE worker.
2664 As is the norm, this also parses -mfoo=bar type parameters. */
2667 cris_option_override (void)
2669 if (cris_max_stackframe_str
)
2671 cris_max_stackframe
= atoi (cris_max_stackframe_str
);
2673 /* Do some sanity checking. */
2674 if (cris_max_stackframe
< 0 || cris_max_stackframe
> 0x20000000)
2675 internal_error ("-max-stackframe=%d is not usable, not between 0 and %d",
2676 cris_max_stackframe
, 0x20000000);
2679 /* Let "-metrax4" and "-metrax100" change the cpu version. */
2680 if (TARGET_SVINTO
&& cris_cpu_version
< CRIS_CPU_SVINTO
)
2681 cris_cpu_version
= CRIS_CPU_SVINTO
;
2682 else if (TARGET_ETRAX4_ADD
&& cris_cpu_version
< CRIS_CPU_ETRAX4
)
2683 cris_cpu_version
= CRIS_CPU_ETRAX4
;
2685 /* Parse -march=... and its synonym, the deprecated -mcpu=... */
2689 = (*cris_cpu_str
== 'v' ? atoi (cris_cpu_str
+ 1) : -1);
2691 if (strcmp ("etrax4", cris_cpu_str
) == 0)
2692 cris_cpu_version
= 3;
2694 if (strcmp ("svinto", cris_cpu_str
) == 0
2695 || strcmp ("etrax100", cris_cpu_str
) == 0)
2696 cris_cpu_version
= 8;
2698 if (strcmp ("ng", cris_cpu_str
) == 0
2699 || strcmp ("etrax100lx", cris_cpu_str
) == 0)
2700 cris_cpu_version
= 10;
2702 if (cris_cpu_version
< 0 || cris_cpu_version
> 32)
2703 error ("unknown CRIS version specification in -march= or -mcpu= : %s",
2706 /* Set the target flags. */
2707 if (cris_cpu_version
>= CRIS_CPU_ETRAX4
)
2708 target_flags
|= MASK_ETRAX4_ADD
;
2710 /* If this is Svinto or higher, align for 32 bit accesses. */
2711 if (cris_cpu_version
>= CRIS_CPU_SVINTO
)
2713 |= (MASK_SVINTO
| MASK_ALIGN_BY_32
2714 | MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2717 /* Note that we do not add new flags when it can be completely
2718 described with a macro that uses -mcpu=X. So
2719 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */
2725 = (*cris_tune_str
== 'v' ? atoi (cris_tune_str
+ 1) : -1);
2727 if (strcmp ("etrax4", cris_tune_str
) == 0)
2730 if (strcmp ("svinto", cris_tune_str
) == 0
2731 || strcmp ("etrax100", cris_tune_str
) == 0)
2734 if (strcmp ("ng", cris_tune_str
) == 0
2735 || strcmp ("etrax100lx", cris_tune_str
) == 0)
2738 if (cris_tune
< 0 || cris_tune
> 32)
2739 error ("unknown CRIS cpu version specification in -mtune= : %s",
2742 if (cris_tune
>= CRIS_CPU_SVINTO
)
2743 /* We have currently nothing more to tune than alignment for
2746 |= (MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2747 | MASK_DATA_ALIGN
| MASK_ALIGN_BY_32
);
2750 if (cris_cpu_version
>= CRIS_CPU_V32
)
2751 target_flags
&= ~(MASK_SIDE_EFFECT_PREFIXES
|MASK_MUL_BUG
);
2755 /* Use error rather than warning, so invalid use is easily
2756 detectable. Still change to the values we expect, to avoid
2760 error ("-fPIC and -fpic are not supported in this configuration");
2764 /* Turn off function CSE. We need to have the addresses reach the
2765 call expanders to get PLT-marked, as they could otherwise be
2766 compared against zero directly or indirectly. After visiting the
2767 call expanders they will then be cse:ed, as the call expanders
2768 force_reg the addresses, effectively forcing flag_no_function_cse
2770 flag_no_function_cse
= 1;
2773 /* Set the per-function-data initializer. */
2774 init_machine_status
= cris_init_machine_status
;
2777 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */
2780 cris_asm_output_mi_thunk (FILE *stream
,
2781 tree thunkdecl ATTRIBUTE_UNUSED
,
2782 HOST_WIDE_INT delta
,
2783 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
2786 /* Make sure unwind info is emitted for the thunk if needed. */
2787 final_start_function (emit_barrier (), stream
, 1);
2790 fprintf (stream
, "\tadd%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2791 ADDITIVE_SIZE_MODIFIER (delta
), delta
,
2792 reg_names
[CRIS_FIRST_ARG_REG
]);
2794 fprintf (stream
, "\tsub%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2795 ADDITIVE_SIZE_MODIFIER (-delta
), -delta
,
2796 reg_names
[CRIS_FIRST_ARG_REG
]);
2800 const char *name
= XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0);
2802 name
= (* targetm
.strip_name_encoding
) (name
);
2806 fprintf (stream
, "\tba ");
2807 assemble_name (stream
, name
);
2808 fprintf (stream
, "%s\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2812 fprintf (stream
, "add.d ");
2813 assemble_name (stream
, name
);
2814 fprintf (stream
, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2819 fprintf (stream
, "jump ");
2820 assemble_name (stream
, XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0));
2821 fprintf (stream
, "\n");
2824 fprintf (stream
, "\tnop\n");
2827 final_end_function ();
2830 /* Boilerplate emitted at start of file.
2832 NO_APP *only at file start* means faster assembly. It also means
2833 comments are not allowed. In some cases comments will be output
2834 for debugging purposes. Make sure they are allowed then. */
2836 cris_file_start (void)
2838 /* These expressions can vary at run time, so we cannot put
2839 them into TARGET_INITIALIZER. */
2840 targetm
.asm_file_start_app_off
= !(TARGET_PDEBUG
|| flag_print_asm_name
);
2842 default_file_start ();
2845 /* Output that goes at the end of the file, similarly. */
2848 cris_file_end (void)
2850 /* For CRIS, the default is to assume *no* executable stack, so output
2851 an executable-stack-note only when needed. */
2852 if (TARGET_LINUX
&& trampolines_created
)
2853 file_end_indicate_exec_stack ();
2856 /* Rename the function calls for integer multiply and divide. */
2858 cris_init_libfuncs (void)
2860 set_optab_libfunc (smul_optab
, SImode
, "__Mul");
2861 set_optab_libfunc (sdiv_optab
, SImode
, "__Div");
2862 set_optab_libfunc (udiv_optab
, SImode
, "__Udiv");
2863 set_optab_libfunc (smod_optab
, SImode
, "__Mod");
2864 set_optab_libfunc (umod_optab
, SImode
, "__Umod");
2866 /* Atomic data being unaligned is unfortunately a reality.
2868 if (TARGET_ATOMICS_MAY_CALL_LIBFUNCS
)
2870 set_optab_libfunc (sync_compare_and_swap_optab
, SImode
,
2871 "__cris_atcmpxchgr32");
2872 set_optab_libfunc (sync_compare_and_swap_optab
, HImode
,
2873 "__cris_atcmpxchgr16");
2877 /* The INIT_EXPANDERS worker sets the per-function-data initializer and
2881 cris_init_expanders (void)
2883 /* Nothing here at the moment. */
2886 /* Zero initialization is OK for all current fields. */
2888 static struct machine_function
*
2889 cris_init_machine_status (void)
2891 return ggc_cleared_alloc
<machine_function
> ();
2894 /* Split a 2 word move (DI or presumably DF) into component parts.
2895 Originally a copy of gen_split_move_double in m32r.c. */
2898 cris_split_movdx (rtx
*operands
)
2900 machine_mode mode
= GET_MODE (operands
[0]);
2901 rtx dest
= operands
[0];
2902 rtx src
= operands
[1];
2905 /* We used to have to handle (SUBREG (MEM)) here, but that should no
2906 longer happen; after reload there are no SUBREGs any more, and we're
2907 only called after reload. */
2908 CRIS_ASSERT (GET_CODE (dest
) != SUBREG
&& GET_CODE (src
) != SUBREG
);
2913 int dregno
= REGNO (dest
);
2915 /* Reg-to-reg copy. */
2918 int sregno
= REGNO (src
);
2920 int reverse
= (dregno
== sregno
+ 1);
2922 /* We normally copy the low-numbered register first. However, if
2923 the first register operand 0 is the same as the second register of
2924 operand 1, we must copy in the opposite order. */
2925 emit_insn (gen_rtx_SET (operand_subword (dest
, reverse
, TRUE
, mode
),
2926 operand_subword (src
, reverse
, TRUE
, mode
)));
2928 emit_insn (gen_rtx_SET (operand_subword (dest
, !reverse
, TRUE
, mode
),
2929 operand_subword (src
, !reverse
, TRUE
, mode
)));
2931 /* Constant-to-reg copy. */
2932 else if (CONST_INT_P (src
) || GET_CODE (src
) == CONST_DOUBLE
)
2935 split_double (src
, &words
[0], &words
[1]);
2936 emit_insn (gen_rtx_SET (operand_subword (dest
, 0, TRUE
, mode
),
2939 emit_insn (gen_rtx_SET (operand_subword (dest
, 1, TRUE
, mode
),
2942 /* Mem-to-reg copy. */
2943 else if (MEM_P (src
))
2945 /* If the high-address word is used in the address, we must load it
2946 last. Otherwise, load it first. */
2947 rtx addr
= XEXP (src
, 0);
2948 int reverse
= (refers_to_regno_p (dregno
, addr
) != 0);
2950 /* The original code implies that we can't do
2951 move.x [rN+],rM move.x [rN],rM+1
2952 when rN is dead, because of REG_NOTES damage. That is
2953 consistent with what I've seen, so don't try it.
2955 We have two different cases here; if the addr is POST_INC,
2956 just pass it through, otherwise add constants. */
2958 if (GET_CODE (addr
) == POST_INC
)
2963 /* Whenever we emit insns with post-incremented
2964 addresses ourselves, we must add a post-inc note
2966 mem
= change_address (src
, SImode
, addr
);
2968 = gen_rtx_SET (operand_subword (dest
, 0, TRUE
, mode
), mem
);
2969 insn
= emit_insn (insn
);
2970 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2972 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2975 mem
= copy_rtx (mem
);
2977 = gen_rtx_SET (operand_subword (dest
, 1, TRUE
, mode
), mem
);
2978 insn
= emit_insn (insn
);
2979 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2981 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2986 /* Make sure we don't get any other addresses with
2987 embedded postincrements. They should be stopped in
2988 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2990 if (side_effects_p (addr
))
2991 fatal_insn ("unexpected side-effects in address", addr
);
2993 emit_insn (gen_rtx_SET
2994 (operand_subword (dest
, reverse
, TRUE
, mode
),
2997 plus_constant (Pmode
, addr
,
2998 reverse
* UNITS_PER_WORD
))));
2999 emit_insn (gen_rtx_SET
3000 (operand_subword (dest
, ! reverse
, TRUE
, mode
),
3003 plus_constant (Pmode
, addr
,
3009 internal_error ("unknown src");
3011 /* Reg-to-mem copy or clear mem. */
3012 else if (MEM_P (dest
)
3014 || src
== const0_rtx
3015 || src
== CONST0_RTX (DFmode
)))
3017 rtx addr
= XEXP (dest
, 0);
3019 if (GET_CODE (addr
) == POST_INC
)
3024 /* Whenever we emit insns with post-incremented addresses
3025 ourselves, we must add a post-inc note manually. */
3026 mem
= change_address (dest
, SImode
, addr
);
3028 = gen_rtx_SET (mem
, operand_subword (src
, 0, TRUE
, mode
));
3029 insn
= emit_insn (insn
);
3030 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
3032 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
3035 mem
= copy_rtx (mem
);
3036 insn
= gen_rtx_SET (mem
, operand_subword (src
, 1, TRUE
, mode
));
3037 insn
= emit_insn (insn
);
3038 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
3040 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
3045 /* Make sure we don't get any other addresses with embedded
3046 postincrements. They should be stopped in
3047 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */
3048 if (side_effects_p (addr
))
3049 fatal_insn ("unexpected side-effects in address", addr
);
3051 emit_insn (gen_rtx_SET
3052 (change_address (dest
, SImode
, addr
),
3053 operand_subword (src
, 0, TRUE
, mode
)));
3055 emit_insn (gen_rtx_SET
3056 (change_address (dest
, SImode
,
3057 plus_constant (Pmode
, addr
,
3059 operand_subword (src
, 1, TRUE
, mode
)));
3064 internal_error ("unknown dest");
3071 /* The expander for the prologue pattern name. */
3074 cris_expand_prologue (void)
3077 int size
= get_frame_size ();
3078 /* Shorten the used name for readability. */
3079 int cfoa_size
= crtl
->outgoing_args_size
;
3080 int last_movem_reg
= -1;
3083 int return_address_on_stack
= cris_return_address_on_stack ();
3084 int got_really_used
= false;
3085 int n_movem_regs
= 0;
3086 int pretend
= crtl
->args
.pretend_args_size
;
3088 /* Don't do anything if no prologues or epilogues are wanted. */
3089 if (!TARGET_PROLOGUE_EPILOGUE
)
3092 CRIS_ASSERT (size
>= 0);
3094 if (crtl
->uses_pic_offset_table
)
3096 /* A reference may have been optimized out (like the abort () in
3097 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3099 push_topmost_sequence ();
3101 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
3102 pop_topmost_sequence ();
3105 /* Align the size to what's best for the CPU model. */
3106 if (TARGET_STACK_ALIGN
)
3107 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
3111 /* See also cris_setup_incoming_varargs where
3112 cfun->machine->stdarg_regs is set. There are other setters of
3113 crtl->args.pretend_args_size than stdarg handling, like
3114 for an argument passed with parts in R13 and stack. We must
3115 not store R13 into the pretend-area for that case, as GCC does
3116 that itself. "Our" store would be marked as redundant and GCC
3117 will attempt to remove it, which will then be flagged as an
3118 internal error; trying to remove a frame-related insn. */
3119 int stdarg_regs
= cfun
->machine
->stdarg_regs
;
3121 framesize
+= pretend
;
3123 for (regno
= CRIS_FIRST_ARG_REG
+ CRIS_MAX_ARGS_IN_REGS
- 1;
3125 regno
--, pretend
-= 4, stdarg_regs
--)
3127 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3128 plus_constant (Pmode
,
3131 /* FIXME: When dwarf2 frame output and unless asynchronous
3132 exceptions, make dwarf2 bundle together all stack
3133 adjustments like it does for registers between stack
3135 RTX_FRAME_RELATED_P (insn
) = 1;
3137 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3138 set_mem_alias_set (mem
, get_varargs_alias_set ());
3139 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, regno
));
3141 /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
3142 the value isn't restored, so we don't want to tell dwarf2
3143 that it's been stored to stack, else EH handling info would
3147 /* For other setters of crtl->args.pretend_args_size, we
3148 just adjust the stack by leaving the remaining size in
3149 "pretend", handled below. */
3152 /* Save SRP if not a leaf function. */
3153 if (return_address_on_stack
)
3155 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3156 plus_constant (Pmode
, stack_pointer_rtx
,
3159 RTX_FRAME_RELATED_P (insn
) = 1;
3161 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3162 set_mem_alias_set (mem
, get_frame_alias_set ());
3163 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
));
3164 RTX_FRAME_RELATED_P (insn
) = 1;
3168 /* Set up the frame pointer, if needed. */
3169 if (frame_pointer_needed
)
3171 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3172 plus_constant (Pmode
, stack_pointer_rtx
,
3175 RTX_FRAME_RELATED_P (insn
) = 1;
3177 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3178 set_mem_alias_set (mem
, get_frame_alias_set ());
3179 insn
= emit_move_insn (mem
, frame_pointer_rtx
);
3180 RTX_FRAME_RELATED_P (insn
) = 1;
3182 insn
= emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
3183 RTX_FRAME_RELATED_P (insn
) = 1;
3188 /* Between frame-pointer and saved registers lie the area for local
3189 variables. If we get here with "pretended" size remaining, count
3190 it into the general stack size. */
3193 /* Get a contiguous sequence of registers, starting with R0, that need
3195 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3197 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3201 /* Check if movem may be used for registers so far. */
3202 if (regno
== last_movem_reg
+ 1)
3203 /* Yes, update next expected register. */
3204 last_movem_reg
= regno
;
3207 /* We cannot use movem for all registers. We have to flush
3208 any movem:ed registers we got so far. */
3209 if (last_movem_reg
!= -1)
3212 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
3214 /* It is a win to use a side-effect assignment for
3215 64 <= size <= 128. But side-effect on movem was
3216 not usable for CRIS v0..3. Also only do it if
3217 side-effects insns are allowed. */
3218 if ((last_movem_reg
+ 1) * 4 + size
>= 64
3219 && (last_movem_reg
+ 1) * 4 + size
<= 128
3220 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
3221 && TARGET_SIDE_EFFECT_PREFIXES
)
3224 = gen_rtx_MEM (SImode
,
3225 plus_constant (Pmode
, stack_pointer_rtx
,
3226 -(n_saved
* 4 + size
)));
3227 set_mem_alias_set (mem
, get_frame_alias_set ());
3229 = cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3230 -(n_saved
* 4 + size
),
3236 = gen_rtx_SET (stack_pointer_rtx
,
3237 plus_constant (Pmode
, stack_pointer_rtx
,
3238 -(n_saved
* 4 + size
)));
3239 insn
= emit_insn (insn
);
3240 RTX_FRAME_RELATED_P (insn
) = 1;
3242 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3243 set_mem_alias_set (mem
, get_frame_alias_set ());
3244 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3248 framesize
+= n_saved
* 4 + size
;
3249 last_movem_reg
= -1;
3253 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3254 plus_constant (Pmode
,
3257 RTX_FRAME_RELATED_P (insn
) = 1;
3259 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3260 set_mem_alias_set (mem
, get_frame_alias_set ());
3261 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, regno
));
3262 RTX_FRAME_RELATED_P (insn
) = 1;
3264 framesize
+= 4 + size
;
3270 /* Check after, if we could movem all registers. This is the normal case. */
3271 if (last_movem_reg
!= -1)
3274 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
3276 /* Side-effect on movem was not usable for CRIS v0..3. Also only
3277 do it if side-effects insns are allowed. */
3278 if ((last_movem_reg
+ 1) * 4 + size
>= 64
3279 && (last_movem_reg
+ 1) * 4 + size
<= 128
3280 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
3281 && TARGET_SIDE_EFFECT_PREFIXES
)
3284 = gen_rtx_MEM (SImode
,
3285 plus_constant (Pmode
, stack_pointer_rtx
,
3286 -(n_saved
* 4 + size
)));
3287 set_mem_alias_set (mem
, get_frame_alias_set ());
3288 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3289 -(n_saved
* 4 + size
), true);
3294 = gen_rtx_SET (stack_pointer_rtx
,
3295 plus_constant (Pmode
, stack_pointer_rtx
,
3296 -(n_saved
* 4 + size
)));
3297 insn
= emit_insn (insn
);
3298 RTX_FRAME_RELATED_P (insn
) = 1;
3300 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3301 set_mem_alias_set (mem
, get_frame_alias_set ());
3302 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
), 0, true);
3305 framesize
+= n_saved
* 4 + size
;
3306 /* We have to put outgoing argument space after regs. */
3309 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3310 plus_constant (Pmode
,
3313 RTX_FRAME_RELATED_P (insn
) = 1;
3314 framesize
+= cfoa_size
;
3317 else if ((size
+ cfoa_size
) > 0)
3319 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3320 plus_constant (Pmode
,
3322 -(cfoa_size
+ size
))));
3323 RTX_FRAME_RELATED_P (insn
) = 1;
3324 framesize
+= size
+ cfoa_size
;
3327 /* Set up the PIC register, if it is used. */
3328 if (got_really_used
)
3331 = gen_rtx_UNSPEC (SImode
, gen_rtvec (1, const0_rtx
), CRIS_UNSPEC_GOT
);
3332 emit_move_insn (pic_offset_table_rtx
, got
);
3334 /* FIXME: This is a cover-up for flow2 messing up; it doesn't
3335 follow exceptional paths and tries to delete the GOT load as
3336 unused, if it isn't used on the non-exceptional paths. Other
3337 ports have similar or other cover-ups, or plain bugs marking
3338 the GOT register load as maybe-dead. To see this, remove the
3339 line below and try libsupc++/vec.cc or a trivial
3340 "static void y (); void x () {try {y ();} catch (...) {}}". */
3341 emit_use (pic_offset_table_rtx
);
3344 if (cris_max_stackframe
&& framesize
> cris_max_stackframe
)
3345 warning (0, "stackframe too big: %d bytes", framesize
);
3348 /* The expander for the epilogue pattern. */
3351 cris_expand_epilogue (void)
3354 int size
= get_frame_size ();
3355 int last_movem_reg
= -1;
3356 int argspace_offset
= crtl
->outgoing_args_size
;
3357 int pretend
= crtl
->args
.pretend_args_size
;
3359 bool return_address_on_stack
= cris_return_address_on_stack ();
3360 /* A reference may have been optimized out
3361 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
3362 so check that it's still used. */
3363 int got_really_used
= false;
3364 int n_movem_regs
= 0;
3366 if (!TARGET_PROLOGUE_EPILOGUE
)
3369 if (crtl
->uses_pic_offset_table
)
3371 /* A reference may have been optimized out (like the abort () in
3372 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3374 push_topmost_sequence ();
3376 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
3377 pop_topmost_sequence ();
3380 /* Align byte count of stack frame. */
3381 if (TARGET_STACK_ALIGN
)
3382 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
3384 /* Check how many saved regs we can movem. They start at r0 and must
3387 regno
< FIRST_PSEUDO_REGISTER
;
3389 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3393 if (regno
== last_movem_reg
+ 1)
3394 last_movem_reg
= regno
;
3399 /* If there was only one register that really needed to be saved
3400 through movem, don't use movem. */
3401 if (n_movem_regs
== 1)
3402 last_movem_reg
= -1;
3404 /* Now emit "normal" move insns for all regs higher than the movem
3406 for (regno
= FIRST_PSEUDO_REGISTER
- 1;
3407 regno
> last_movem_reg
;
3409 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3413 if (argspace_offset
)
3415 /* There is an area for outgoing parameters located before
3416 the saved registers. We have to adjust for that. */
3417 emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3418 plus_constant (Pmode
, stack_pointer_rtx
,
3420 /* Make sure we only do this once. */
3421 argspace_offset
= 0;
3424 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3425 stack_pointer_rtx
));
3426 set_mem_alias_set (mem
, get_frame_alias_set ());
3427 insn
= emit_move_insn (gen_rtx_raw_REG (SImode
, regno
), mem
);
3429 /* Whenever we emit insns with post-incremented addresses
3430 ourselves, we must add a post-inc note manually. */
3432 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3435 /* If we have any movem-restore, do it now. */
3436 if (last_movem_reg
!= -1)
3440 if (argspace_offset
)
3442 emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3443 plus_constant (Pmode
, stack_pointer_rtx
,
3445 argspace_offset
= 0;
3448 mem
= gen_rtx_MEM (SImode
,
3449 gen_rtx_POST_INC (SImode
, stack_pointer_rtx
));
3450 set_mem_alias_set (mem
, get_frame_alias_set ());
3452 = emit_insn (cris_gen_movem_load (mem
,
3453 GEN_INT (last_movem_reg
+ 1), 0));
3454 /* Whenever we emit insns with post-incremented addresses
3455 ourselves, we must add a post-inc note manually. */
3456 if (side_effects_p (PATTERN (insn
)))
3458 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3461 /* If we don't clobber all of the allocated stack area (we've already
3462 deallocated saved registers), GCC might want to schedule loads from
3463 the stack to *after* the stack-pointer restore, which introduces an
3464 interrupt race condition. This happened for the initial-value
3465 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
3466 other failure for that test). It also happened for the stack slot
3467 for the return value in (one version of)
3468 linux/fs/dcache.c:__d_lookup, at least with "-O2
3469 -fno-omit-frame-pointer". */
3471 /* Restore frame pointer if necessary. */
3472 if (frame_pointer_needed
)
3476 emit_insn (gen_cris_frame_deallocated_barrier ());
3478 emit_move_insn (stack_pointer_rtx
, frame_pointer_rtx
);
3479 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3480 stack_pointer_rtx
));
3481 set_mem_alias_set (mem
, get_frame_alias_set ());
3482 insn
= emit_move_insn (frame_pointer_rtx
, mem
);
3484 /* Whenever we emit insns with post-incremented addresses
3485 ourselves, we must add a post-inc note manually. */
3487 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3489 else if ((size
+ argspace_offset
) != 0)
3491 emit_insn (gen_cris_frame_deallocated_barrier ());
3493 /* If there was no frame-pointer to restore sp from, we must
3494 explicitly deallocate local variables. */
3496 /* Handle space for outgoing parameters that hasn't been handled
3498 size
+= argspace_offset
;
3500 emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3501 plus_constant (Pmode
, stack_pointer_rtx
, size
)));
3504 /* If this function has no pushed register parameters
3505 (stdargs/varargs), and if it is not a leaf function, then we have
3506 the return address on the stack. */
3507 if (return_address_on_stack
&& pretend
== 0)
3509 if (TARGET_V32
|| crtl
->calls_eh_return
)
3513 rtx srpreg
= gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3514 mem
= gen_rtx_MEM (SImode
,
3515 gen_rtx_POST_INC (SImode
,
3516 stack_pointer_rtx
));
3517 set_mem_alias_set (mem
, get_frame_alias_set ());
3518 insn
= emit_move_insn (srpreg
, mem
);
3520 /* Whenever we emit insns with post-incremented addresses
3521 ourselves, we must add a post-inc note manually. */
3523 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3525 if (crtl
->calls_eh_return
)
3526 emit_insn (gen_addsi3 (stack_pointer_rtx
,
3528 gen_rtx_raw_REG (SImode
,
3529 CRIS_STACKADJ_REG
)));
3530 cris_expand_return (false);
3533 cris_expand_return (true);
3538 /* If we pushed some register parameters, then adjust the stack for
3542 /* If SRP is stored on the way, we need to restore it first. */
3543 if (return_address_on_stack
)
3546 rtx srpreg
= gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3549 mem
= gen_rtx_MEM (SImode
,
3550 gen_rtx_POST_INC (SImode
,
3551 stack_pointer_rtx
));
3552 set_mem_alias_set (mem
, get_frame_alias_set ());
3553 insn
= emit_move_insn (srpreg
, mem
);
3555 /* Whenever we emit insns with post-incremented addresses
3556 ourselves, we must add a post-inc note manually. */
3558 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3561 emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3562 plus_constant (Pmode
, stack_pointer_rtx
,
3566 /* Perform the "physical" unwinding that the EH machinery calculated. */
3567 if (crtl
->calls_eh_return
)
3568 emit_insn (gen_addsi3 (stack_pointer_rtx
,
3570 gen_rtx_raw_REG (SImode
,
3571 CRIS_STACKADJ_REG
)));
3572 cris_expand_return (false);
3575 /* Worker function for generating movem from mem for load_multiple. */
3578 cris_gen_movem_load (rtx src
, rtx nregs_rtx
, int nprefix
)
3580 int nregs
= INTVAL (nregs_rtx
);
3584 rtx srcreg
= XEXP (src
, 0);
3585 unsigned int regno
= nregs
- 1;
3594 if (GET_CODE (srcreg
) == POST_INC
)
3595 srcreg
= XEXP (srcreg
, 0);
3597 CRIS_ASSERT (REG_P (srcreg
));
3599 /* Don't use movem for just one insn. The insns are equivalent except
3600 for the pipeline hazard (on v32); movem does not forward the loaded
3601 registers so there's a three cycles penalty for their use. */
3603 return gen_movsi (gen_rtx_REG (SImode
, 0), src
);
3605 vec
= rtvec_alloc (nprefix
+ nregs
3606 + (GET_CODE (XEXP (src
, 0)) == POST_INC
));
3608 if (GET_CODE (XEXP (src
, 0)) == POST_INC
)
3610 RTVEC_ELT (vec
, nprefix
+ 1)
3611 = gen_rtx_SET (srcreg
, plus_constant (Pmode
, srcreg
, nregs
* 4));
3615 src
= replace_equiv_address (src
, srcreg
);
3616 RTVEC_ELT (vec
, nprefix
)
3617 = gen_rtx_SET (gen_rtx_REG (SImode
, regno
), src
);
3620 for (i
= 1; i
< nregs
; i
++, eltno
++)
3622 RTVEC_ELT (vec
, nprefix
+ eltno
)
3623 = gen_rtx_SET (gen_rtx_REG (SImode
, regno
),
3624 adjust_address_nv (src
, SImode
, i
* 4));
3628 return gen_rtx_PARALLEL (VOIDmode
, vec
);
3631 /* Worker function for generating movem to mem. If FRAME_RELATED, notes
3632 are added that the dwarf2 machinery understands. */
3635 cris_emit_movem_store (rtx dest
, rtx nregs_rtx
, int increment
,
3638 int nregs
= INTVAL (nregs_rtx
);
3643 rtx destreg
= XEXP (dest
, 0);
3644 unsigned int regno
= nregs
- 1;
3653 if (GET_CODE (destreg
) == POST_INC
)
3654 increment
+= nregs
* 4;
3656 if (GET_CODE (destreg
) == POST_INC
|| GET_CODE (destreg
) == PLUS
)
3657 destreg
= XEXP (destreg
, 0);
3659 CRIS_ASSERT (REG_P (destreg
));
3661 /* Don't use movem for just one insn. The insns are equivalent except
3662 for the pipeline hazard (on v32); movem does not forward the loaded
3663 registers so there's a three cycles penalty for use. */
3666 rtx mov
= gen_rtx_SET (dest
, gen_rtx_REG (SImode
, 0));
3670 insn
= emit_insn (mov
);
3672 RTX_FRAME_RELATED_P (insn
) = 1;
3676 /* If there was a request for a side-effect, create the ordinary
3678 vec
= rtvec_alloc (2);
3680 RTVEC_ELT (vec
, 0) = mov
;
3681 RTVEC_ELT (vec
, 1) = gen_rtx_SET (destreg
, plus_constant (Pmode
, destreg
,
3685 RTX_FRAME_RELATED_P (mov
) = 1;
3686 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3691 vec
= rtvec_alloc (nregs
+ (increment
!= 0 ? 1 : 0));
3693 = gen_rtx_SET (replace_equiv_address (dest
,
3694 plus_constant (Pmode
, destreg
,
3696 gen_rtx_REG (SImode
, regno
));
3699 /* The dwarf2 info wants this mark on each component in a parallel
3700 that's part of the prologue (though it's optional on the first
3703 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 0)) = 1;
3708 = gen_rtx_SET (destreg
, plus_constant (Pmode
, destreg
,
3710 ? increment
: nregs
* 4));
3714 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3716 /* Don't call adjust_address_nv on a post-incremented address if
3718 if (GET_CODE (XEXP (dest
, 0)) == POST_INC
)
3719 dest
= replace_equiv_address (dest
, destreg
);
3722 for (i
= 1; i
< nregs
; i
++, eltno
++)
3724 RTVEC_ELT (vec
, eltno
)
3725 = gen_rtx_SET (adjust_address_nv (dest
, SImode
, i
* 4),
3726 gen_rtx_REG (SImode
, regno
));
3728 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, eltno
)) = 1;
3733 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
3735 /* Because dwarf2out.c handles the insns in a parallel as a sequence,
3736 we need to keep the stack adjustment separate, after the
3737 MEM-setters. Else the stack-adjustment in the second component of
3738 the parallel would be mishandled; the offsets for the SETs that
3739 follow it would be wrong. We prepare for this by adding a
3740 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3741 followed by the increment. Note that we have FRAME_RELATED_P on
3742 all the SETs, including the original stack adjustment SET in the
3748 rtx seq
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (nregs
+ 1));
3749 XVECEXP (seq
, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 0));
3750 for (i
= 1; i
< nregs
; i
++)
3752 = copy_rtx (XVECEXP (PATTERN (insn
), 0, i
+ 1));
3753 XVECEXP (seq
, 0, nregs
) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 1));
3754 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, seq
);
3757 RTX_FRAME_RELATED_P (insn
) = 1;
3763 /* Worker function for expanding the address for PIC function calls. */
3766 cris_expand_pic_call_address (rtx
*opp
, rtx
*markerp
)
3770 gcc_assert (flag_pic
&& MEM_P (op
));
3773 /* It might be that code can be generated that jumps to 0 (or to a
3774 specific address). Don't die on that. (There is a
3776 if (CONSTANT_P (op
) && !CONST_INT_P (op
))
3778 enum cris_symbol_type t
= cris_symbol_type_of (op
);
3780 CRIS_ASSERT (can_create_pseudo_p ());
3782 /* For local symbols (non-PLT), just get the plain symbol
3783 reference into a register. For symbols that can be PLT, make
3785 if (t
== cris_rel_symbol
)
3787 /* For v32, we're fine as-is; just PICify the symbol. Forcing
3788 into a register caused performance regression for 3.2.1,
3789 observable in __floatdidf and elsewhere in libgcc. */
3792 rtx sym
= GET_CODE (op
) != CONST
? op
: get_related_value (op
);
3793 HOST_WIDE_INT offs
= get_integer_term (op
);
3795 /* We can't get calls to sym+N, N integer, can we? */
3796 gcc_assert (offs
== 0);
3798 op
= gen_rtx_CONST (Pmode
,
3799 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, sym
),
3800 CRIS_UNSPEC_PCREL
));
3803 op
= force_reg (Pmode
, op
);
3806 *markerp
= const0_rtx
;
3808 else if (t
== cris_got_symbol
)
3810 if (TARGET_AVOID_GOTPLT
)
3812 /* Change a "jsr sym" into (allocate register rM, rO)
3813 "move.d (const (unspec [sym] CRIS_UNSPEC_PLT_GOTREL)),rM"
3814 "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and
3815 "jsr (const (unspec [sym] CRIS_UNSPEC_PLT_PCREL))"
3819 crtl
->uses_pic_offset_table
= 1;
3820 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3822 ? CRIS_UNSPEC_PLT_PCREL
3823 : CRIS_UNSPEC_PLT_GOTREL
);
3824 tem
= gen_rtx_CONST (Pmode
, tem
);
3829 rm
= gen_reg_rtx (Pmode
);
3830 emit_move_insn (rm
, tem
);
3831 ro
= gen_reg_rtx (Pmode
);
3832 if (expand_binop (Pmode
, add_optab
, rm
,
3833 pic_offset_table_rtx
,
3834 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3835 internal_error ("expand_binop failed in movsi got");
3841 /* Change a "jsr sym" into (allocate register rM, rO)
3842 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM"
3843 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access
3844 marked as not trapping and not aliasing. No "move.d
3845 [rO],rP" as that would invite to re-use of a value
3846 that should not be reused. FIXME: Need a peephole2
3847 for cases when this is cse:d from the call, to change
3848 back to just get the PLT entry address, so we don't
3849 resolve the same symbol over and over (the memory
3850 access of the PLTGOT isn't constant). */
3851 rtx tem
, mem
, rm
, ro
;
3853 gcc_assert (can_create_pseudo_p ());
3854 crtl
->uses_pic_offset_table
= 1;
3855 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3856 CRIS_UNSPEC_PLTGOTREAD
);
3857 rm
= gen_reg_rtx (Pmode
);
3858 emit_move_insn (rm
, gen_rtx_CONST (Pmode
, tem
));
3859 ro
= gen_reg_rtx (Pmode
);
3860 if (expand_binop (Pmode
, add_optab
, rm
,
3861 pic_offset_table_rtx
,
3862 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3863 internal_error ("expand_binop failed in movsi got");
3864 mem
= gen_rtx_MEM (Pmode
, ro
);
3866 /* This MEM doesn't alias anything. Whether it aliases
3867 other same symbols is unimportant. */
3868 set_mem_alias_set (mem
, new_alias_set ());
3869 MEM_NOTRAP_P (mem
) = 1;
3873 /* We need to prepare this call to go through the PLT; we
3874 need to make GOT available. */
3875 *markerp
= pic_offset_table_rtx
;
3878 /* Can't possibly get anything else for a function-call, right? */
3879 fatal_insn ("unidentifiable call op", op
);
3881 /* If the validizing variant is called, it will try to validize
3882 the address as a valid any-operand constant, but as it's only
3883 valid for calls and moves, it will fail and always be forced
3885 *opp
= replace_equiv_address_nv (*opp
, op
);
3888 /* Can't tell what locality a call to a non-constant address has;
3889 better make the GOT register alive at it.
3890 FIXME: Can we see whether the register has known constant
3892 *markerp
= pic_offset_table_rtx
;
3895 /* Make sure operands are in the right order for an addsi3 insn as
3896 generated by a define_split. Nothing but REG_P as the first
3897 operand is recognized by addsi3 after reload. OPERANDS contains
3898 the operands, with the first at OPERANDS[N] and the second at
3902 cris_order_for_addsi3 (rtx
*operands
, int n
)
3904 if (!REG_P (operands
[n
]))
3906 rtx tem
= operands
[n
];
3907 operands
[n
] = operands
[n
+ 1];
3908 operands
[n
+ 1] = tem
;
3912 /* Use from within code, from e.g. PRINT_OPERAND and
3913 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit
3914 different things depending on whether code operand or constant is
3918 cris_output_addr_const (FILE *file
, rtx x
)
3921 output_addr_const (file
, x
);
3925 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */
3928 cris_asm_output_symbol_ref (FILE *file
, rtx x
)
3930 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
3932 if (flag_pic
&& in_code
> 0)
3934 const char *origstr
= XSTR (x
, 0);
3936 str
= (* targetm
.strip_name_encoding
) (origstr
);
3937 assemble_name (file
, str
);
3940 if (!TARGET_V32
&& !crtl
->uses_pic_offset_table
)
3941 output_operand_lossage ("PIC register isn't set up");
3944 assemble_name (file
, XSTR (x
, 0));
3947 /* Worker function for ASM_OUTPUT_LABEL_REF. */
3950 cris_asm_output_label_ref (FILE *file
, char *buf
)
3952 if (flag_pic
&& in_code
> 0)
3954 assemble_name (file
, buf
);
3957 if (!TARGET_V32
&& !crtl
->uses_pic_offset_table
)
3958 internal_error ("emitting PIC operand, but PIC register "
3962 assemble_name (file
, buf
);
3965 /* Worker function for TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
3968 cris_output_addr_const_extra (FILE *file
, rtx xconst
)
3970 switch (GET_CODE (xconst
))
3975 x
= XVECEXP (xconst
, 0, 0);
3976 CRIS_ASSERT (GET_CODE (x
) == SYMBOL_REF
3977 || GET_CODE (x
) == LABEL_REF
3978 || GET_CODE (x
) == CONST
);
3979 output_addr_const (file
, x
);
3980 switch (XINT (xconst
, 1))
3982 case CRIS_UNSPEC_PCREL
:
3983 /* We only get this with -fpic/PIC to tell it apart from an
3984 invalid symbol. We can't tell here, but it should only
3985 be the operand of a call or movsi. */
3986 gcc_assert (TARGET_V32
&& flag_pic
);
3989 case CRIS_UNSPEC_PLT_PCREL
:
3990 gcc_assert (TARGET_V32
);
3991 fprintf (file
, ":PLT");
3994 case CRIS_UNSPEC_PLT_GOTREL
:
3995 gcc_assert (!TARGET_V32
);
3996 fprintf (file
, ":PLTG");
3999 case CRIS_UNSPEC_GOTREL
:
4000 gcc_assert (!TARGET_V32
);
4001 fprintf (file
, ":GOTOFF");
4004 case CRIS_UNSPEC_GOTREAD
:
4006 fprintf (file
, ":GOT16");
4008 fprintf (file
, ":GOT");
4011 case CRIS_UNSPEC_PLTGOTREAD
:
4013 fprintf (file
, CRIS_GOTPLT_SUFFIX
"16");
4015 fprintf (file
, CRIS_GOTPLT_SUFFIX
);
4028 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
4031 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
4032 int incoming ATTRIBUTE_UNUSED
)
4034 return gen_rtx_REG (Pmode
, CRIS_STRUCT_VALUE_REGNUM
);
4037 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
4040 cris_setup_incoming_varargs (cumulative_args_t ca_v
,
4041 machine_mode mode ATTRIBUTE_UNUSED
,
4042 tree type ATTRIBUTE_UNUSED
,
4043 int *pretend_arg_size
,
4046 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4048 if (ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
4050 int stdarg_regs
= CRIS_MAX_ARGS_IN_REGS
- ca
->regs
;
4051 cfun
->machine
->stdarg_regs
= stdarg_regs
;
4052 *pretend_arg_size
= stdarg_regs
* 4;
4056 fprintf (asm_out_file
,
4057 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
4058 ca
->regs
, *pretend_arg_size
, second_time
);
4061 /* Return true if TYPE must be passed by invisible reference.
4062 For cris, we pass <= 8 bytes by value, others by reference. */
4065 cris_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
4066 machine_mode mode
, const_tree type
,
4067 bool named ATTRIBUTE_UNUSED
)
4069 return (targetm
.calls
.must_pass_in_stack (mode
, type
)
4070 || CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 8);
4073 /* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments
4074 and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the
4075 best code size and speed for gcc, ipps and products in gcc-2.7.2. */
4078 cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
4080 int *punsignedp ATTRIBUTE_UNUSED
,
4081 const_tree fntype ATTRIBUTE_UNUSED
,
4084 /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even
4085 when modifying TARGET_FUNCTION_VALUE to return the promoted mode).
4086 Maybe pointless as of now, but let's keep the old behavior. */
4087 if (for_return
== 1)
4089 return CRIS_PROMOTED_MODE (mode
, *punsignedp
, type
);
4092 /* Atomic types require alignment to be at least their "natural" size. */
4095 cris_atomic_align_for_mode (machine_mode mode
)
4097 return GET_MODE_BITSIZE (mode
);
4100 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4104 cris_function_value(const_tree type
,
4105 const_tree func ATTRIBUTE_UNUSED
,
4106 bool outgoing ATTRIBUTE_UNUSED
)
4108 return gen_rtx_REG (TYPE_MODE (type
), CRIS_FIRST_ARG_REG
);
4111 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4115 cris_libcall_value (machine_mode mode
,
4116 const_rtx fun ATTRIBUTE_UNUSED
)
4118 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
);
4121 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4125 cris_function_value_regno_p (const unsigned int regno
)
4127 return (regno
== CRIS_FIRST_ARG_REG
);
4131 cris_arg_partial_bytes (cumulative_args_t ca
, machine_mode mode
,
4132 tree type
, bool named ATTRIBUTE_UNUSED
)
4134 if (get_cumulative_args (ca
)->regs
== CRIS_MAX_ARGS_IN_REGS
- 1
4135 && !targetm
.calls
.must_pass_in_stack (mode
, type
)
4136 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 4
4137 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) <= 8)
4138 return UNITS_PER_WORD
;
4144 cris_function_arg_1 (cumulative_args_t ca_v
,
4145 machine_mode mode ATTRIBUTE_UNUSED
,
4146 const_tree type ATTRIBUTE_UNUSED
,
4147 bool named
, bool incoming
)
4149 const CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4151 if ((!incoming
|| named
) && ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
4152 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
+ ca
->regs
);
4157 /* Worker function for TARGET_FUNCTION_ARG.
4158 The void_type_node is sent as a "closing" call. */
4161 cris_function_arg (cumulative_args_t ca
, machine_mode mode
,
4162 const_tree type
, bool named
)
4164 return cris_function_arg_1 (ca
, mode
, type
, named
, false);
4167 /* Worker function for TARGET_FUNCTION_INCOMING_ARG.
4169 The differences between this and the previous, is that this one checks
4170 that an argument is named, since incoming stdarg/varargs arguments are
4171 pushed onto the stack, and we don't have to check against the "closing"
4172 void_type_node TYPE parameter. */
4175 cris_function_incoming_arg (cumulative_args_t ca
, machine_mode mode
,
4176 const_tree type
, bool named
)
4178 return cris_function_arg_1 (ca
, mode
, type
, named
, true);
4181 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. */
4184 cris_function_arg_advance (cumulative_args_t ca_v
, machine_mode mode
,
4185 const_tree type
, bool named ATTRIBUTE_UNUSED
)
4187 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4189 ca
->regs
+= (3 + CRIS_FUNCTION_ARG_SIZE (mode
, type
)) / 4;
4192 /* Worker function for TARGET_MD_ASM_CLOBBERS. */
4195 cris_md_asm_clobbers (tree outputs
, tree inputs
, tree in_clobbers
)
4197 HARD_REG_SET mof_set
;
4201 CLEAR_HARD_REG_SET (mof_set
);
4202 SET_HARD_REG_BIT (mof_set
, CRIS_MOF_REGNUM
);
4204 /* For the time being, all asms clobber condition codes. Revisit when
4205 there's a reasonable use for inputs/outputs that mention condition
4208 = tree_cons (NULL_TREE
,
4209 build_string (strlen (reg_names
[CRIS_CC0_REGNUM
]),
4210 reg_names
[CRIS_CC0_REGNUM
]),
4213 for (t
= outputs
; t
!= NULL
; t
= TREE_CHAIN (t
))
4215 tree val
= TREE_VALUE (t
);
4217 /* The constraint letter for the singleton register class of MOF
4218 is 'h'. If it's mentioned in the constraints, the asm is
4219 MOF-aware and adding it to the clobbers would cause it to have
4220 impossible constraints. */
4221 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t
))),
4223 || tree_overlaps_hard_reg_set (val
, &mof_set
) != NULL_TREE
)
4227 for (t
= inputs
; t
!= NULL
; t
= TREE_CHAIN (t
))
4229 tree val
= TREE_VALUE (t
);
4231 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t
))),
4233 || tree_overlaps_hard_reg_set (val
, &mof_set
) != NULL_TREE
)
4237 return tree_cons (NULL_TREE
,
4238 build_string (strlen (reg_names
[CRIS_MOF_REGNUM
]),
4239 reg_names
[CRIS_MOF_REGNUM
]),
4243 /* Implement TARGET_FRAME_POINTER_REQUIRED.
4245 Really only needed if the stack frame has variable length (alloca
4246 or variable sized local arguments (GNU C extension). See PR39499 and
4247 PR38609 for the reason this isn't just 0. */
4250 cris_frame_pointer_required (void)
4252 return !crtl
->sp_is_unchanging
;
4255 /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE.
4257 This looks too complicated, and it is. I assigned r7 to be the
4258 static chain register, but it is call-saved, so we have to save it,
4259 and come back to restore it after the call, so we have to save srp...
4260 Anyway, trampolines are rare enough that we can cope with this
4261 somewhat lack of elegance.
4262 (Do not be tempted to "straighten up" whitespace in the asms; the
4263 assembler #NO_APP state mandates strict spacing). */
4264 /* ??? See the i386 regparm=3 implementation that pushes the static
4265 chain value to the stack in the trampoline, and uses a call-saved
4266 register when called directly. */
4269 cris_asm_trampoline_template (FILE *f
)
4273 /* This normally-unused nop insn acts as an instruction to
4274 the simulator to flush its instruction cache. None of
4275 the other instructions in the trampoline template suits
4276 as a trigger for V32. The pc-relative addressing mode
4277 works nicely as a trigger for V10.
4278 FIXME: Have specific V32 template (possibly avoiding the
4279 use of a special instruction). */
4280 fprintf (f
, "\tclearf x\n");
4281 /* We have to use a register as an intermediate, choosing
4282 semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM),
4283 so we can use it for address indirection and jsr target. */
4284 fprintf (f
, "\tmove $r1,$mof\n");
4286 fprintf (f
, "\tmove.d 0,$r1\n");
4287 fprintf (f
, "\tmove.d $%s,[$r1]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4288 fprintf (f
, "\taddq 6,$r1\n");
4289 fprintf (f
, "\tmove $mof,[$r1]\n");
4290 fprintf (f
, "\taddq 6,$r1\n");
4291 fprintf (f
, "\tmove $srp,[$r1]\n");
4293 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4295 fprintf (f
, "\tmove.d 0,$r1\n");
4296 fprintf (f
, "\tjsr $r1\n");
4297 fprintf (f
, "\tsetf\n");
4299 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4301 fprintf (f
, "\tmove.d 0,$r1\n");
4303 fprintf (f
, "\tmove.d 0,$r9\n");
4304 fprintf (f
, "\tjump $r9\n");
4305 fprintf (f
, "\tsetf\n");
4309 fprintf (f
, "\tmove.d $%s,[$pc+20]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4310 fprintf (f
, "\tmove $srp,[$pc+22]\n");
4311 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4312 fprintf (f
, "\tjsr 0\n");
4313 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4314 fprintf (f
, "\tjump 0\n");
4318 /* Implement TARGET_TRAMPOLINE_INIT. */
4321 cris_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
4323 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
4324 rtx tramp
= XEXP (m_tramp
, 0);
4327 emit_block_move (m_tramp
, assemble_trampoline_template (),
4328 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
4332 mem
= adjust_address (m_tramp
, SImode
, 6);
4333 emit_move_insn (mem
, plus_constant (Pmode
, tramp
, 38));
4334 mem
= adjust_address (m_tramp
, SImode
, 22);
4335 emit_move_insn (mem
, chain_value
);
4336 mem
= adjust_address (m_tramp
, SImode
, 28);
4337 emit_move_insn (mem
, fnaddr
);
4341 mem
= adjust_address (m_tramp
, SImode
, 10);
4342 emit_move_insn (mem
, chain_value
);
4343 mem
= adjust_address (m_tramp
, SImode
, 16);
4344 emit_move_insn (mem
, fnaddr
);
4347 /* Note that there is no need to do anything with the cache for
4348 sake of a trampoline. */
4353 /* Various small functions to replace macros. Only called from a
4354 debugger. They might collide with gcc functions or system functions,
4355 so only emit them when '#if 1' above. */
4357 enum rtx_code
Get_code (rtx
);
4362 return GET_CODE (x
);
4365 const char *Get_mode (rtx
);
4370 return GET_MODE_NAME (GET_MODE (x
));
4373 rtx
Xexp (rtx
, int);
4381 rtx
Xvecexp (rtx
, int, int);
4384 Xvecexp (rtx x
, int n
, int m
)
4386 return XVECEXP (x
, n
, m
);
4389 int Get_rtx_len (rtx
);
4394 return GET_RTX_LENGTH (GET_CODE (x
));
4397 /* Use upper-case to distinguish from local variables that are sometimes
4398 called next_insn and prev_insn. */
4400 rtx
Next_insn (rtx
);
4403 Next_insn (rtx insn
)
4405 return NEXT_INSN (insn
);
4408 rtx
Prev_insn (rtx
);
4411 Prev_insn (rtx insn
)
4413 return PREV_INSN (insn
);
4417 #include "gt-cris.h"
4421 * eval: (c-set-style "gnu")
4422 * indent-tabs-mode: t