1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004
4 ;; Free Software Foundation, Inc.
5 ;; Mostly by William Schelter.
6 ;; x86_64 support added by Jan Hubicka
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA. */
25 ;; The original PO technology requires these to be ordered by speed,
26 ;; so that assigner will pick the fastest.
28 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
31 ;; constraint letters.
33 ;; The special asm out single letter directives following a '%' are:
34 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
36 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
37 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
38 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
39 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
40 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
41 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
42 ;; 'J' Print the appropriate jump operand.
44 ;; 'b' Print the QImode name of the register for the indicated operand.
45 ;; %b0 would print %al if operands[0] is reg 0.
46 ;; 'w' Likewise, print the HImode name of the register.
47 ;; 'k' Likewise, print the SImode name of the register.
48 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
49 ;; 'y' Print "st(0)" instead of "st" as a register.
54 [; Relocation specifiers
66 (UNSPEC_STACK_ALLOC 11)
68 (UNSPEC_SSE_PROLOGUE_SAVE 13)
73 (UNSPEC_TLS_LD_BASE 17)
75 ; Other random patterns
85 ; For SSE/MMX support:
96 (UNSPEC_NOP 45) ; prevents combiner cleverness
123 ; x87 Double output FP
124 (UNSPEC_SINCOS_COS 80)
125 (UNSPEC_SINCOS_SIN 81)
128 (UNSPEC_XTRACT_FRACT 84)
129 (UNSPEC_XTRACT_EXP 85)
130 (UNSPEC_FSCALE_FRACT 86)
131 (UNSPEC_FSCALE_EXP 87)
138 (UNSPEC_FRNDINT_FLOOR 96)
139 (UNSPEC_FRNDINT_CEIL 97)
140 (UNSPEC_FRNDINT_TRUNC 98)
141 (UNSPEC_FRNDINT_MASK_PM 99)
146 (UNSPEC_EH_RETURN 76)
150 [(UNSPECV_BLOCKAGE 0)
151 (UNSPECV_STACK_PROBE 10)
162 ;; Registers by name.
171 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
174 ;; In C guard expressions, put expressions which may be compile-time
175 ;; constants first. This allows for better optimization. For
176 ;; example, write "TARGET_64BIT && reload_completed", not
177 ;; "reload_completed && TARGET_64BIT".
180 ;; Processor type. This attribute must exactly match the processor_type
181 ;; enumeration in i386.h.
182 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4,k8,nocona"
183 (const (symbol_ref "ix86_tune")))
185 ;; A basic instruction type. Refinements due to arguments to be
186 ;; provided in other attributes.
189 alu,alu1,negnot,imov,imovx,lea,
190 incdec,ishift,ishift1,rotate,rotate1,imul,idiv,
191 icmp,test,ibr,setcc,icmov,
192 push,pop,call,callv,leave,
194 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,frndint,
195 sselog,sseiadd,sseishft,sseimul,
196 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,
197 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
198 (const_string "other"))
200 ;; Main data type used by the insn
202 "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF"
203 (const_string "unknown"))
205 ;; The CPU unit operations uses.
206 (define_attr "unit" "integer,i387,sse,mmx,unknown"
207 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,frndint")
208 (const_string "i387")
209 (eq_attr "type" "sselog,sseiadd,sseishft,sseimul,
210 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv")
212 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
214 (eq_attr "type" "other")
215 (const_string "unknown")]
216 (const_string "integer")))
218 ;; The (bounding maximum) length of an instruction immediate.
219 (define_attr "length_immediate" ""
220 (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave")
222 (eq_attr "unit" "i387,sse,mmx")
224 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1,
226 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
227 (eq_attr "type" "imov,test")
228 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
229 (eq_attr "type" "call")
230 (if_then_else (match_operand 0 "constant_call_address_operand" "")
233 (eq_attr "type" "callv")
234 (if_then_else (match_operand 1 "constant_call_address_operand" "")
237 ;; We don't know the size before shorten_branches. Expect
238 ;; the instruction to fit for better scheduling.
239 (eq_attr "type" "ibr")
242 (symbol_ref "/* Update immediate_length and other attributes! */
245 ;; The (bounding maximum) length of an instruction address.
246 (define_attr "length_address" ""
247 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
249 (and (eq_attr "type" "call")
250 (match_operand 0 "constant_call_address_operand" ""))
252 (and (eq_attr "type" "callv")
253 (match_operand 1 "constant_call_address_operand" ""))
256 (symbol_ref "ix86_attr_length_address_default (insn)")))
258 ;; Set when length prefix is used.
259 (define_attr "prefix_data16" ""
260 (if_then_else (ior (eq_attr "mode" "HI")
261 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
265 ;; Set when string REP prefix is used.
266 (define_attr "prefix_rep" ""
267 (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
271 ;; Set when 0f opcode prefix is used.
272 (define_attr "prefix_0f" ""
274 (ior (eq_attr "type" "imovx,setcc,icmov")
275 (eq_attr "unit" "sse,mmx"))
279 ;; Set when REX opcode prefix is used.
280 (define_attr "prefix_rex" ""
281 (cond [(and (eq_attr "mode" "DI")
282 (eq_attr "type" "!push,pop,call,callv,leave,ibr"))
284 (and (eq_attr "mode" "QI")
285 (ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
288 (ne (symbol_ref "x86_extended_reg_mentioned_p (insn)")
294 ;; Set when modrm byte is used.
295 (define_attr "modrm" ""
296 (cond [(eq_attr "type" "str,cld,leave")
298 (eq_attr "unit" "i387")
300 (and (eq_attr "type" "incdec")
301 (ior (match_operand:SI 1 "register_operand" "")
302 (match_operand:HI 1 "register_operand" "")))
304 (and (eq_attr "type" "push")
305 (not (match_operand 1 "memory_operand" "")))
307 (and (eq_attr "type" "pop")
308 (not (match_operand 0 "memory_operand" "")))
310 (and (eq_attr "type" "imov")
311 (and (match_operand 0 "register_operand" "")
312 (match_operand 1 "immediate_operand" "")))
314 (and (eq_attr "type" "call")
315 (match_operand 0 "constant_call_address_operand" ""))
317 (and (eq_attr "type" "callv")
318 (match_operand 1 "constant_call_address_operand" ""))
323 ;; The (bounding maximum) length of an instruction in bytes.
324 ;; ??? fistp and frndint are in fact fldcw/{fistp,frndint}/fldcw sequences.
325 ;; Later we may want to split them and compute proper length as for
327 (define_attr "length" ""
328 (cond [(eq_attr "type" "other,multi,fistp,frndint")
330 (eq_attr "type" "fcmp")
332 (eq_attr "unit" "i387")
334 (plus (attr "prefix_data16")
335 (attr "length_address")))]
336 (plus (plus (attr "modrm")
337 (plus (attr "prefix_0f")
338 (plus (attr "prefix_rex")
340 (plus (attr "prefix_rep")
341 (plus (attr "prefix_data16")
342 (plus (attr "length_immediate")
343 (attr "length_address")))))))
345 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
346 ;; `store' if there is a simple memory reference therein, or `unknown'
347 ;; if the instruction is complex.
349 (define_attr "memory" "none,load,store,both,unknown"
350 (cond [(eq_attr "type" "other,multi,str")
351 (const_string "unknown")
352 (eq_attr "type" "lea,fcmov,fpspc,cld")
353 (const_string "none")
354 (eq_attr "type" "fistp,leave")
355 (const_string "both")
356 (eq_attr "type" "frndint")
357 (const_string "load")
358 (eq_attr "type" "push")
359 (if_then_else (match_operand 1 "memory_operand" "")
360 (const_string "both")
361 (const_string "store"))
362 (eq_attr "type" "pop")
363 (if_then_else (match_operand 0 "memory_operand" "")
364 (const_string "both")
365 (const_string "load"))
366 (eq_attr "type" "setcc")
367 (if_then_else (match_operand 0 "memory_operand" "")
368 (const_string "store")
369 (const_string "none"))
370 (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
371 (if_then_else (ior (match_operand 0 "memory_operand" "")
372 (match_operand 1 "memory_operand" ""))
373 (const_string "load")
374 (const_string "none"))
375 (eq_attr "type" "ibr")
376 (if_then_else (match_operand 0 "memory_operand" "")
377 (const_string "load")
378 (const_string "none"))
379 (eq_attr "type" "call")
380 (if_then_else (match_operand 0 "constant_call_address_operand" "")
381 (const_string "none")
382 (const_string "load"))
383 (eq_attr "type" "callv")
384 (if_then_else (match_operand 1 "constant_call_address_operand" "")
385 (const_string "none")
386 (const_string "load"))
387 (and (eq_attr "type" "alu1,negnot,ishift1")
388 (match_operand 1 "memory_operand" ""))
389 (const_string "both")
390 (and (match_operand 0 "memory_operand" "")
391 (match_operand 1 "memory_operand" ""))
392 (const_string "both")
393 (match_operand 0 "memory_operand" "")
394 (const_string "store")
395 (match_operand 1 "memory_operand" "")
396 (const_string "load")
398 "!alu1,negnot,ishift1,
399 imov,imovx,icmp,test,
401 sse,ssemov,ssecmp,ssecomi,ssecvt,sseicvt,
402 mmx,mmxmov,mmxcmp,mmxcvt")
403 (match_operand 2 "memory_operand" ""))
404 (const_string "load")
405 (and (eq_attr "type" "icmov")
406 (match_operand 3 "memory_operand" ""))
407 (const_string "load")
409 (const_string "none")))
411 ;; Indicates if an instruction has both an immediate and a displacement.
413 (define_attr "imm_disp" "false,true,unknown"
414 (cond [(eq_attr "type" "other,multi")
415 (const_string "unknown")
416 (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
417 (and (match_operand 0 "memory_displacement_operand" "")
418 (match_operand 1 "immediate_operand" "")))
419 (const_string "true")
420 (and (eq_attr "type" "alu,ishift,rotate,imul,idiv")
421 (and (match_operand 0 "memory_displacement_operand" "")
422 (match_operand 2 "immediate_operand" "")))
423 (const_string "true")
425 (const_string "false")))
427 ;; Indicates if an FP operation has an integer source.
429 (define_attr "fp_int_src" "false,true"
430 (const_string "false"))
432 ;; Defines rounding mode of an FP operation.
434 (define_attr "i387_cw" "floor,ceil,trunc,mask_pm,uninitialized,any"
435 (const_string "any"))
437 ;; Describe a user's asm statement.
438 (define_asm_attributes
439 [(set_attr "length" "128")
440 (set_attr "type" "multi")])
442 ;; Scheduling descriptions
444 (include "pentium.md")
447 (include "athlon.md")
450 ;; Operand and operator predicates
452 (include "predicates.md")
455 ;; Compare instructions.
457 ;; All compare insns have expanders that save the operands away without
458 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
459 ;; after the cmp) will actually emit the cmpM.
461 (define_expand "cmpdi"
462 [(set (reg:CC FLAGS_REG)
463 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
464 (match_operand:DI 1 "x86_64_general_operand" "")))]
467 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
468 operands[0] = force_reg (DImode, operands[0]);
469 ix86_compare_op0 = operands[0];
470 ix86_compare_op1 = operands[1];
474 (define_expand "cmpsi"
475 [(set (reg:CC FLAGS_REG)
476 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
477 (match_operand:SI 1 "general_operand" "")))]
480 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
481 operands[0] = force_reg (SImode, operands[0]);
482 ix86_compare_op0 = operands[0];
483 ix86_compare_op1 = operands[1];
487 (define_expand "cmphi"
488 [(set (reg:CC FLAGS_REG)
489 (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
490 (match_operand:HI 1 "general_operand" "")))]
493 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
494 operands[0] = force_reg (HImode, operands[0]);
495 ix86_compare_op0 = operands[0];
496 ix86_compare_op1 = operands[1];
500 (define_expand "cmpqi"
501 [(set (reg:CC FLAGS_REG)
502 (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
503 (match_operand:QI 1 "general_operand" "")))]
506 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
507 operands[0] = force_reg (QImode, operands[0]);
508 ix86_compare_op0 = operands[0];
509 ix86_compare_op1 = operands[1];
513 (define_insn "cmpdi_ccno_1_rex64"
515 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
516 (match_operand:DI 1 "const0_operand" "n,n")))]
517 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
519 test{q}\t{%0, %0|%0, %0}
520 cmp{q}\t{%1, %0|%0, %1}"
521 [(set_attr "type" "test,icmp")
522 (set_attr "length_immediate" "0,1")
523 (set_attr "mode" "DI")])
525 (define_insn "*cmpdi_minus_1_rex64"
527 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
528 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
530 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)"
531 "cmp{q}\t{%1, %0|%0, %1}"
532 [(set_attr "type" "icmp")
533 (set_attr "mode" "DI")])
535 (define_expand "cmpdi_1_rex64"
536 [(set (reg:CC FLAGS_REG)
537 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
538 (match_operand:DI 1 "general_operand" "")))]
542 (define_insn "cmpdi_1_insn_rex64"
544 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
545 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
546 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
547 "cmp{q}\t{%1, %0|%0, %1}"
548 [(set_attr "type" "icmp")
549 (set_attr "mode" "DI")])
552 (define_insn "*cmpsi_ccno_1"
554 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
555 (match_operand:SI 1 "const0_operand" "n,n")))]
556 "ix86_match_ccmode (insn, CCNOmode)"
558 test{l}\t{%0, %0|%0, %0}
559 cmp{l}\t{%1, %0|%0, %1}"
560 [(set_attr "type" "test,icmp")
561 (set_attr "length_immediate" "0,1")
562 (set_attr "mode" "SI")])
564 (define_insn "*cmpsi_minus_1"
566 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
567 (match_operand:SI 1 "general_operand" "ri,mr"))
569 "ix86_match_ccmode (insn, CCGOCmode)"
570 "cmp{l}\t{%1, %0|%0, %1}"
571 [(set_attr "type" "icmp")
572 (set_attr "mode" "SI")])
574 (define_expand "cmpsi_1"
575 [(set (reg:CC FLAGS_REG)
576 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
577 (match_operand:SI 1 "general_operand" "ri,mr")))]
581 (define_insn "*cmpsi_1_insn"
583 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
584 (match_operand:SI 1 "general_operand" "ri,mr")))]
585 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
586 && ix86_match_ccmode (insn, CCmode)"
587 "cmp{l}\t{%1, %0|%0, %1}"
588 [(set_attr "type" "icmp")
589 (set_attr "mode" "SI")])
591 (define_insn "*cmphi_ccno_1"
593 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
594 (match_operand:HI 1 "const0_operand" "n,n")))]
595 "ix86_match_ccmode (insn, CCNOmode)"
597 test{w}\t{%0, %0|%0, %0}
598 cmp{w}\t{%1, %0|%0, %1}"
599 [(set_attr "type" "test,icmp")
600 (set_attr "length_immediate" "0,1")
601 (set_attr "mode" "HI")])
603 (define_insn "*cmphi_minus_1"
605 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
606 (match_operand:HI 1 "general_operand" "ri,mr"))
608 "ix86_match_ccmode (insn, CCGOCmode)"
609 "cmp{w}\t{%1, %0|%0, %1}"
610 [(set_attr "type" "icmp")
611 (set_attr "mode" "HI")])
613 (define_insn "*cmphi_1"
615 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
616 (match_operand:HI 1 "general_operand" "ri,mr")))]
617 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
618 && ix86_match_ccmode (insn, CCmode)"
619 "cmp{w}\t{%1, %0|%0, %1}"
620 [(set_attr "type" "icmp")
621 (set_attr "mode" "HI")])
623 (define_insn "*cmpqi_ccno_1"
625 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
626 (match_operand:QI 1 "const0_operand" "n,n")))]
627 "ix86_match_ccmode (insn, CCNOmode)"
629 test{b}\t{%0, %0|%0, %0}
630 cmp{b}\t{$0, %0|%0, 0}"
631 [(set_attr "type" "test,icmp")
632 (set_attr "length_immediate" "0,1")
633 (set_attr "mode" "QI")])
635 (define_insn "*cmpqi_1"
637 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
638 (match_operand:QI 1 "general_operand" "qi,mq")))]
639 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
640 && ix86_match_ccmode (insn, CCmode)"
641 "cmp{b}\t{%1, %0|%0, %1}"
642 [(set_attr "type" "icmp")
643 (set_attr "mode" "QI")])
645 (define_insn "*cmpqi_minus_1"
647 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
648 (match_operand:QI 1 "general_operand" "qi,mq"))
650 "ix86_match_ccmode (insn, CCGOCmode)"
651 "cmp{b}\t{%1, %0|%0, %1}"
652 [(set_attr "type" "icmp")
653 (set_attr "mode" "QI")])
655 (define_insn "*cmpqi_ext_1"
658 (match_operand:QI 0 "general_operand" "Qm")
661 (match_operand 1 "ext_register_operand" "Q")
664 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
665 "cmp{b}\t{%h1, %0|%0, %h1}"
666 [(set_attr "type" "icmp")
667 (set_attr "mode" "QI")])
669 (define_insn "*cmpqi_ext_1_rex64"
672 (match_operand:QI 0 "register_operand" "Q")
675 (match_operand 1 "ext_register_operand" "Q")
678 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
679 "cmp{b}\t{%h1, %0|%0, %h1}"
680 [(set_attr "type" "icmp")
681 (set_attr "mode" "QI")])
683 (define_insn "*cmpqi_ext_2"
688 (match_operand 0 "ext_register_operand" "Q")
691 (match_operand:QI 1 "const0_operand" "n")))]
692 "ix86_match_ccmode (insn, CCNOmode)"
694 [(set_attr "type" "test")
695 (set_attr "length_immediate" "0")
696 (set_attr "mode" "QI")])
698 (define_expand "cmpqi_ext_3"
699 [(set (reg:CC FLAGS_REG)
703 (match_operand 0 "ext_register_operand" "")
706 (match_operand:QI 1 "general_operand" "")))]
710 (define_insn "cmpqi_ext_3_insn"
715 (match_operand 0 "ext_register_operand" "Q")
718 (match_operand:QI 1 "general_operand" "Qmn")))]
719 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
720 "cmp{b}\t{%1, %h0|%h0, %1}"
721 [(set_attr "type" "icmp")
722 (set_attr "mode" "QI")])
724 (define_insn "cmpqi_ext_3_insn_rex64"
729 (match_operand 0 "ext_register_operand" "Q")
732 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
733 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
734 "cmp{b}\t{%1, %h0|%h0, %1}"
735 [(set_attr "type" "icmp")
736 (set_attr "mode" "QI")])
738 (define_insn "*cmpqi_ext_4"
743 (match_operand 0 "ext_register_operand" "Q")
748 (match_operand 1 "ext_register_operand" "Q")
751 "ix86_match_ccmode (insn, CCmode)"
752 "cmp{b}\t{%h1, %h0|%h0, %h1}"
753 [(set_attr "type" "icmp")
754 (set_attr "mode" "QI")])
756 ;; These implement float point compares.
757 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
758 ;; which would allow mix and match FP modes on the compares. Which is what
759 ;; the old patterns did, but with many more of them.
761 (define_expand "cmpxf"
762 [(set (reg:CC FLAGS_REG)
763 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
764 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
767 ix86_compare_op0 = operands[0];
768 ix86_compare_op1 = operands[1];
772 (define_expand "cmpdf"
773 [(set (reg:CC FLAGS_REG)
774 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
775 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
776 "TARGET_80387 || TARGET_SSE2"
778 ix86_compare_op0 = operands[0];
779 ix86_compare_op1 = operands[1];
783 (define_expand "cmpsf"
784 [(set (reg:CC FLAGS_REG)
785 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
786 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
787 "TARGET_80387 || TARGET_SSE"
789 ix86_compare_op0 = operands[0];
790 ix86_compare_op1 = operands[1];
794 ;; FP compares, step 1:
795 ;; Set the FP condition codes.
797 ;; CCFPmode compare with exceptions
798 ;; CCFPUmode compare with no exceptions
800 (define_insn "*cmpfp_0_sf"
801 [(set (match_operand:HI 0 "register_operand" "=a")
804 (match_operand:SF 1 "register_operand" "f")
805 (match_operand:SF 2 "const0_operand" "X"))]
808 "* return output_fp_compare (insn, operands, 2, 0);"
809 [(set_attr "type" "multi")
810 (set_attr "mode" "SF")])
812 (define_insn "*cmpfp_0_df"
813 [(set (match_operand:HI 0 "register_operand" "=a")
816 (match_operand:DF 1 "register_operand" "f")
817 (match_operand:DF 2 "const0_operand" "X"))]
820 "* return output_fp_compare (insn, operands, 2, 0);"
821 [(set_attr "type" "multi")
822 (set_attr "mode" "DF")])
824 (define_insn "*cmpfp_0_xf"
825 [(set (match_operand:HI 0 "register_operand" "=a")
828 (match_operand:XF 1 "register_operand" "f")
829 (match_operand:XF 2 "const0_operand" "X"))]
832 "* return output_fp_compare (insn, operands, 2, 0);"
833 [(set_attr "type" "multi")
834 (set_attr "mode" "XF")])
836 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
837 ;; used to manage the reg stack popping would not be preserved.
839 (define_insn "*cmpfp_2_sf"
840 [(set (reg:CCFP FPSR_REG)
842 (match_operand:SF 0 "register_operand" "f")
843 (match_operand:SF 1 "nonimmediate_operand" "fm")))]
845 "* return output_fp_compare (insn, operands, 0, 0);"
846 [(set_attr "type" "fcmp")
847 (set_attr "mode" "SF")])
849 (define_insn "*cmpfp_2_sf_1"
850 [(set (match_operand:HI 0 "register_operand" "=a")
853 (match_operand:SF 1 "register_operand" "f")
854 (match_operand:SF 2 "nonimmediate_operand" "fm"))]
857 "* return output_fp_compare (insn, operands, 2, 0);"
858 [(set_attr "type" "fcmp")
859 (set_attr "mode" "SF")])
861 (define_insn "*cmpfp_2_df"
862 [(set (reg:CCFP FPSR_REG)
864 (match_operand:DF 0 "register_operand" "f")
865 (match_operand:DF 1 "nonimmediate_operand" "fm")))]
867 "* return output_fp_compare (insn, operands, 0, 0);"
868 [(set_attr "type" "fcmp")
869 (set_attr "mode" "DF")])
871 (define_insn "*cmpfp_2_df_1"
872 [(set (match_operand:HI 0 "register_operand" "=a")
875 (match_operand:DF 1 "register_operand" "f")
876 (match_operand:DF 2 "nonimmediate_operand" "fm"))]
879 "* return output_fp_compare (insn, operands, 2, 0);"
880 [(set_attr "type" "multi")
881 (set_attr "mode" "DF")])
883 (define_insn "*cmpfp_2_xf"
884 [(set (reg:CCFP FPSR_REG)
886 (match_operand:XF 0 "register_operand" "f")
887 (match_operand:XF 1 "register_operand" "f")))]
889 "* return output_fp_compare (insn, operands, 0, 0);"
890 [(set_attr "type" "fcmp")
891 (set_attr "mode" "XF")])
893 (define_insn "*cmpfp_2_xf_1"
894 [(set (match_operand:HI 0 "register_operand" "=a")
897 (match_operand:XF 1 "register_operand" "f")
898 (match_operand:XF 2 "register_operand" "f"))]
901 "* return output_fp_compare (insn, operands, 2, 0);"
902 [(set_attr "type" "multi")
903 (set_attr "mode" "XF")])
905 (define_insn "*cmpfp_2u"
906 [(set (reg:CCFPU FPSR_REG)
908 (match_operand 0 "register_operand" "f")
909 (match_operand 1 "register_operand" "f")))]
911 && FLOAT_MODE_P (GET_MODE (operands[0]))
912 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
913 "* return output_fp_compare (insn, operands, 0, 1);"
914 [(set_attr "type" "fcmp")
916 (cond [(match_operand:SF 1 "" "")
918 (match_operand:DF 1 "" "")
921 (const_string "XF")))])
923 (define_insn "*cmpfp_2u_1"
924 [(set (match_operand:HI 0 "register_operand" "=a")
927 (match_operand 1 "register_operand" "f")
928 (match_operand 2 "register_operand" "f"))]
931 && FLOAT_MODE_P (GET_MODE (operands[1]))
932 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
933 "* return output_fp_compare (insn, operands, 2, 1);"
934 [(set_attr "type" "multi")
936 (cond [(match_operand:SF 1 "" "")
938 (match_operand:DF 1 "" "")
941 (const_string "XF")))])
943 ;; Patterns to match the SImode-in-memory ficom instructions.
945 ;; %%% Play games with accepting gp registers, as otherwise we have to
946 ;; force them to memory during rtl generation, which is no good. We
947 ;; can get rid of this once we teach reload to do memory input reloads
950 (define_insn "*ficom_1"
951 [(set (reg:CCFP FPSR_REG)
953 (match_operand 0 "register_operand" "f,f")
954 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
955 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0]))
956 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])"
959 ;; Split the not-really-implemented gp register case into a
960 ;; push-op-pop sequence.
962 ;; %%% This is most efficient, but am I gonna get in trouble
963 ;; for separating cc0_setter and cc0_user?
966 [(set (reg:CCFP FPSR_REG)
968 (match_operand:SF 0 "register_operand" "")
969 (float (match_operand:SI 1 "register_operand" ""))))]
970 "0 && TARGET_80387 && reload_completed"
971 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 1))
972 (set (reg:CCFP FPSR_REG) (compare:CCFP (match_dup 0) (match_dup 2)))
973 (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
974 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
975 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
976 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
978 ;; FP compares, step 2
979 ;; Move the fpsw to ax.
981 (define_insn "x86_fnstsw_1"
982 [(set (match_operand:HI 0 "register_operand" "=a")
983 (unspec:HI [(reg:CCFP FPSR_REG)] UNSPEC_FNSTSW))]
986 [(set_attr "length" "2")
987 (set_attr "mode" "SI")
988 (set_attr "unit" "i387")])
990 ;; FP compares, step 3
991 ;; Get ax into flags, general case.
993 (define_insn "x86_sahf_1"
994 [(set (reg:CC FLAGS_REG)
995 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
998 [(set_attr "length" "1")
999 (set_attr "athlon_decode" "vector")
1000 (set_attr "mode" "SI")])
1002 ;; Pentium Pro can do steps 1 through 3 in one go.
1004 (define_insn "*cmpfp_i"
1005 [(set (reg:CCFP FLAGS_REG)
1006 (compare:CCFP (match_operand 0 "register_operand" "f")
1007 (match_operand 1 "register_operand" "f")))]
1008 "TARGET_80387 && TARGET_CMOVE
1009 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1010 && FLOAT_MODE_P (GET_MODE (operands[0]))
1011 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1012 "* return output_fp_compare (insn, operands, 1, 0);"
1013 [(set_attr "type" "fcmp")
1015 (cond [(match_operand:SF 1 "" "")
1017 (match_operand:DF 1 "" "")
1020 (const_string "XF")))
1021 (set_attr "athlon_decode" "vector")])
1023 (define_insn "*cmpfp_i_sse"
1024 [(set (reg:CCFP FLAGS_REG)
1025 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
1026 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1028 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1029 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1030 "* return output_fp_compare (insn, operands, 1, 0);"
1031 [(set_attr "type" "fcmp,ssecomi")
1033 (if_then_else (match_operand:SF 1 "" "")
1035 (const_string "DF")))
1036 (set_attr "athlon_decode" "vector")])
1038 (define_insn "*cmpfp_i_sse_only"
1039 [(set (reg:CCFP FLAGS_REG)
1040 (compare:CCFP (match_operand 0 "register_operand" "x")
1041 (match_operand 1 "nonimmediate_operand" "xm")))]
1042 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1043 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1044 "* return output_fp_compare (insn, operands, 1, 0);"
1045 [(set_attr "type" "ssecomi")
1047 (if_then_else (match_operand:SF 1 "" "")
1049 (const_string "DF")))
1050 (set_attr "athlon_decode" "vector")])
1052 (define_insn "*cmpfp_iu"
1053 [(set (reg:CCFPU FLAGS_REG)
1054 (compare:CCFPU (match_operand 0 "register_operand" "f")
1055 (match_operand 1 "register_operand" "f")))]
1056 "TARGET_80387 && TARGET_CMOVE
1057 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1058 && FLOAT_MODE_P (GET_MODE (operands[0]))
1059 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1060 "* return output_fp_compare (insn, operands, 1, 1);"
1061 [(set_attr "type" "fcmp")
1063 (cond [(match_operand:SF 1 "" "")
1065 (match_operand:DF 1 "" "")
1068 (const_string "XF")))
1069 (set_attr "athlon_decode" "vector")])
1071 (define_insn "*cmpfp_iu_sse"
1072 [(set (reg:CCFPU FLAGS_REG)
1073 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1074 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1076 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1077 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1078 "* return output_fp_compare (insn, operands, 1, 1);"
1079 [(set_attr "type" "fcmp,ssecomi")
1081 (if_then_else (match_operand:SF 1 "" "")
1083 (const_string "DF")))
1084 (set_attr "athlon_decode" "vector")])
1086 (define_insn "*cmpfp_iu_sse_only"
1087 [(set (reg:CCFPU FLAGS_REG)
1088 (compare:CCFPU (match_operand 0 "register_operand" "x")
1089 (match_operand 1 "nonimmediate_operand" "xm")))]
1090 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1091 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1092 "* return output_fp_compare (insn, operands, 1, 1);"
1093 [(set_attr "type" "ssecomi")
1095 (if_then_else (match_operand:SF 1 "" "")
1097 (const_string "DF")))
1098 (set_attr "athlon_decode" "vector")])
1100 ;; Move instructions.
1102 ;; General case of fullword move.
1104 (define_expand "movsi"
1105 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1106 (match_operand:SI 1 "general_operand" ""))]
1108 "ix86_expand_move (SImode, operands); DONE;")
1110 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1113 ;; %%% We don't use a post-inc memory reference because x86 is not a
1114 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1115 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1116 ;; targets without our curiosities, and it is just as easy to represent
1117 ;; this differently.
1119 (define_insn "*pushsi2"
1120 [(set (match_operand:SI 0 "push_operand" "=<")
1121 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1124 [(set_attr "type" "push")
1125 (set_attr "mode" "SI")])
1127 ;; For 64BIT abi we always round up to 8 bytes.
1128 (define_insn "*pushsi2_rex64"
1129 [(set (match_operand:SI 0 "push_operand" "=X")
1130 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1133 [(set_attr "type" "push")
1134 (set_attr "mode" "SI")])
1136 (define_insn "*pushsi2_prologue"
1137 [(set (match_operand:SI 0 "push_operand" "=<")
1138 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1139 (clobber (mem:BLK (scratch)))]
1142 [(set_attr "type" "push")
1143 (set_attr "mode" "SI")])
1145 (define_insn "*popsi1_epilogue"
1146 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1147 (mem:SI (reg:SI SP_REG)))
1148 (set (reg:SI SP_REG)
1149 (plus:SI (reg:SI SP_REG) (const_int 4)))
1150 (clobber (mem:BLK (scratch)))]
1153 [(set_attr "type" "pop")
1154 (set_attr "mode" "SI")])
1156 (define_insn "popsi1"
1157 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1158 (mem:SI (reg:SI SP_REG)))
1159 (set (reg:SI SP_REG)
1160 (plus:SI (reg:SI SP_REG) (const_int 4)))]
1163 [(set_attr "type" "pop")
1164 (set_attr "mode" "SI")])
1166 (define_insn "*movsi_xor"
1167 [(set (match_operand:SI 0 "register_operand" "=r")
1168 (match_operand:SI 1 "const0_operand" "i"))
1169 (clobber (reg:CC FLAGS_REG))]
1170 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1171 "xor{l}\t{%0, %0|%0, %0}"
1172 [(set_attr "type" "alu1")
1173 (set_attr "mode" "SI")
1174 (set_attr "length_immediate" "0")])
1176 (define_insn "*movsi_or"
1177 [(set (match_operand:SI 0 "register_operand" "=r")
1178 (match_operand:SI 1 "immediate_operand" "i"))
1179 (clobber (reg:CC FLAGS_REG))]
1181 && operands[1] == constm1_rtx
1182 && (TARGET_PENTIUM || optimize_size)"
1184 operands[1] = constm1_rtx;
1185 return "or{l}\t{%1, %0|%0, %1}";
1187 [(set_attr "type" "alu1")
1188 (set_attr "mode" "SI")
1189 (set_attr "length_immediate" "1")])
1191 (define_insn "*movsi_1"
1192 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
1193 (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,rm,*Y,*Y,rm"))]
1194 "(TARGET_INTER_UNIT_MOVES || optimize_size)
1195 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1197 switch (get_attr_type (insn))
1200 if (get_attr_mode (insn) == MODE_TI)
1201 return "movdqa\t{%1, %0|%0, %1}";
1202 return "movd\t{%1, %0|%0, %1}";
1205 if (get_attr_mode (insn) == MODE_DI)
1206 return "movq\t{%1, %0|%0, %1}";
1207 return "movd\t{%1, %0|%0, %1}";
1210 return "lea{l}\t{%1, %0|%0, %1}";
1213 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1215 return "mov{l}\t{%1, %0|%0, %1}";
1219 (cond [(eq_attr "alternative" "2,3,4")
1220 (const_string "mmxmov")
1221 (eq_attr "alternative" "5,6,7")
1222 (const_string "ssemov")
1223 (and (ne (symbol_ref "flag_pic") (const_int 0))
1224 (match_operand:SI 1 "symbolic_operand" ""))
1225 (const_string "lea")
1227 (const_string "imov")))
1228 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1230 (define_insn "*movsi_1_nointernunit"
1231 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!m,!*y,!*Y,!m,!*Y")
1232 (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,m,*Y,*Y,m"))]
1233 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
1234 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1236 switch (get_attr_type (insn))
1239 if (get_attr_mode (insn) == MODE_TI)
1240 return "movdqa\t{%1, %0|%0, %1}";
1241 return "movd\t{%1, %0|%0, %1}";
1244 if (get_attr_mode (insn) == MODE_DI)
1245 return "movq\t{%1, %0|%0, %1}";
1246 return "movd\t{%1, %0|%0, %1}";
1249 return "lea{l}\t{%1, %0|%0, %1}";
1252 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1254 return "mov{l}\t{%1, %0|%0, %1}";
1258 (cond [(eq_attr "alternative" "2,3,4")
1259 (const_string "mmxmov")
1260 (eq_attr "alternative" "5,6,7")
1261 (const_string "ssemov")
1262 (and (ne (symbol_ref "flag_pic") (const_int 0))
1263 (match_operand:SI 1 "symbolic_operand" ""))
1264 (const_string "lea")
1266 (const_string "imov")))
1267 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1269 ;; Stores and loads of ax to arbitrary constant address.
1270 ;; We fake an second form of instruction to force reload to load address
1271 ;; into register when rax is not available
1272 (define_insn "*movabssi_1_rex64"
1273 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1274 (match_operand:SI 1 "nonmemory_operand" "a,er"))]
1275 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1277 movabs{l}\t{%1, %P0|%P0, %1}
1278 mov{l}\t{%1, %a0|%a0, %1}"
1279 [(set_attr "type" "imov")
1280 (set_attr "modrm" "0,*")
1281 (set_attr "length_address" "8,0")
1282 (set_attr "length_immediate" "0,*")
1283 (set_attr "memory" "store")
1284 (set_attr "mode" "SI")])
1286 (define_insn "*movabssi_2_rex64"
1287 [(set (match_operand:SI 0 "register_operand" "=a,r")
1288 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1289 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1291 movabs{l}\t{%P1, %0|%0, %P1}
1292 mov{l}\t{%a1, %0|%0, %a1}"
1293 [(set_attr "type" "imov")
1294 (set_attr "modrm" "0,*")
1295 (set_attr "length_address" "8,0")
1296 (set_attr "length_immediate" "0")
1297 (set_attr "memory" "load")
1298 (set_attr "mode" "SI")])
1300 (define_insn "*swapsi"
1301 [(set (match_operand:SI 0 "register_operand" "+r")
1302 (match_operand:SI 1 "register_operand" "+r"))
1307 [(set_attr "type" "imov")
1308 (set_attr "pent_pair" "np")
1309 (set_attr "athlon_decode" "vector")
1310 (set_attr "mode" "SI")
1311 (set_attr "modrm" "0")])
1313 (define_expand "movhi"
1314 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1315 (match_operand:HI 1 "general_operand" ""))]
1317 "ix86_expand_move (HImode, operands); DONE;")
1319 (define_insn "*pushhi2"
1320 [(set (match_operand:HI 0 "push_operand" "=<,<")
1321 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1324 push{w}\t{|WORD PTR }%1
1326 [(set_attr "type" "push")
1327 (set_attr "mode" "HI")])
1329 ;; For 64BIT abi we always round up to 8 bytes.
1330 (define_insn "*pushhi2_rex64"
1331 [(set (match_operand:HI 0 "push_operand" "=X")
1332 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1335 [(set_attr "type" "push")
1336 (set_attr "mode" "QI")])
1338 (define_insn "*movhi_1"
1339 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
1340 (match_operand:HI 1 "general_operand" "r,rn,rm,rn"))]
1341 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1343 switch (get_attr_type (insn))
1346 /* movzwl is faster than movw on p2 due to partial word stalls,
1347 though not as fast as an aligned movl. */
1348 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
1350 if (get_attr_mode (insn) == MODE_SI)
1351 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1353 return "mov{w}\t{%1, %0|%0, %1}";
1357 (cond [(ne (symbol_ref "optimize_size") (const_int 0))
1358 (const_string "imov")
1359 (and (eq_attr "alternative" "0")
1360 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1362 (eq (symbol_ref "TARGET_HIMODE_MATH")
1364 (const_string "imov")
1365 (and (eq_attr "alternative" "1,2")
1366 (match_operand:HI 1 "aligned_operand" ""))
1367 (const_string "imov")
1368 (and (ne (symbol_ref "TARGET_MOVX")
1370 (eq_attr "alternative" "0,2"))
1371 (const_string "imovx")
1373 (const_string "imov")))
1375 (cond [(eq_attr "type" "imovx")
1377 (and (eq_attr "alternative" "1,2")
1378 (match_operand:HI 1 "aligned_operand" ""))
1380 (and (eq_attr "alternative" "0")
1381 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1383 (eq (symbol_ref "TARGET_HIMODE_MATH")
1387 (const_string "HI")))])
1389 ;; Stores and loads of ax to arbitrary constant address.
1390 ;; We fake an second form of instruction to force reload to load address
1391 ;; into register when rax is not available
1392 (define_insn "*movabshi_1_rex64"
1393 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1394 (match_operand:HI 1 "nonmemory_operand" "a,er"))]
1395 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1397 movabs{w}\t{%1, %P0|%P0, %1}
1398 mov{w}\t{%1, %a0|%a0, %1}"
1399 [(set_attr "type" "imov")
1400 (set_attr "modrm" "0,*")
1401 (set_attr "length_address" "8,0")
1402 (set_attr "length_immediate" "0,*")
1403 (set_attr "memory" "store")
1404 (set_attr "mode" "HI")])
1406 (define_insn "*movabshi_2_rex64"
1407 [(set (match_operand:HI 0 "register_operand" "=a,r")
1408 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1409 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1411 movabs{w}\t{%P1, %0|%0, %P1}
1412 mov{w}\t{%a1, %0|%0, %a1}"
1413 [(set_attr "type" "imov")
1414 (set_attr "modrm" "0,*")
1415 (set_attr "length_address" "8,0")
1416 (set_attr "length_immediate" "0")
1417 (set_attr "memory" "load")
1418 (set_attr "mode" "HI")])
1420 (define_insn "*swaphi_1"
1421 [(set (match_operand:HI 0 "register_operand" "+r")
1422 (match_operand:HI 1 "register_operand" "+r"))
1425 "TARGET_PARTIAL_REG_STALL"
1427 [(set_attr "type" "imov")
1428 (set_attr "pent_pair" "np")
1429 (set_attr "mode" "HI")
1430 (set_attr "modrm" "0")])
1432 (define_insn "*swaphi_2"
1433 [(set (match_operand:HI 0 "register_operand" "+r")
1434 (match_operand:HI 1 "register_operand" "+r"))
1437 "! TARGET_PARTIAL_REG_STALL"
1439 [(set_attr "type" "imov")
1440 (set_attr "pent_pair" "np")
1441 (set_attr "mode" "SI")
1442 (set_attr "modrm" "0")])
1444 (define_expand "movstricthi"
1445 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1446 (match_operand:HI 1 "general_operand" ""))]
1447 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1449 /* Don't generate memory->memory moves, go through a register */
1450 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1451 operands[1] = force_reg (HImode, operands[1]);
1454 (define_insn "*movstricthi_1"
1455 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1456 (match_operand:HI 1 "general_operand" "rn,m"))]
1457 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1458 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1459 "mov{w}\t{%1, %0|%0, %1}"
1460 [(set_attr "type" "imov")
1461 (set_attr "mode" "HI")])
1463 (define_insn "*movstricthi_xor"
1464 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1465 (match_operand:HI 1 "const0_operand" "i"))
1466 (clobber (reg:CC FLAGS_REG))]
1468 && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
1469 "xor{w}\t{%0, %0|%0, %0}"
1470 [(set_attr "type" "alu1")
1471 (set_attr "mode" "HI")
1472 (set_attr "length_immediate" "0")])
1474 (define_expand "movqi"
1475 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1476 (match_operand:QI 1 "general_operand" ""))]
1478 "ix86_expand_move (QImode, operands); DONE;")
1480 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1481 ;; "push a byte". But actually we use pushw, which has the effect
1482 ;; of rounding the amount pushed up to a halfword.
1484 (define_insn "*pushqi2"
1485 [(set (match_operand:QI 0 "push_operand" "=X,X")
1486 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1489 push{w}\t{|word ptr }%1
1491 [(set_attr "type" "push")
1492 (set_attr "mode" "HI")])
1494 ;; For 64BIT abi we always round up to 8 bytes.
1495 (define_insn "*pushqi2_rex64"
1496 [(set (match_operand:QI 0 "push_operand" "=X")
1497 (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
1500 [(set_attr "type" "push")
1501 (set_attr "mode" "QI")])
1503 ;; Situation is quite tricky about when to choose full sized (SImode) move
1504 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
1505 ;; partial register dependency machines (such as AMD Athlon), where QImode
1506 ;; moves issue extra dependency and for partial register stalls machines
1507 ;; that don't use QImode patterns (and QImode move cause stall on the next
1510 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
1511 ;; register stall machines with, where we use QImode instructions, since
1512 ;; partial register stall can be caused there. Then we use movzx.
1513 (define_insn "*movqi_1"
1514 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
1515 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
1516 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1518 switch (get_attr_type (insn))
1521 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
1523 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
1525 if (get_attr_mode (insn) == MODE_SI)
1526 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1528 return "mov{b}\t{%1, %0|%0, %1}";
1532 (cond [(ne (symbol_ref "optimize_size") (const_int 0))
1533 (const_string "imov")
1534 (and (eq_attr "alternative" "3")
1535 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1537 (eq (symbol_ref "TARGET_QIMODE_MATH")
1539 (const_string "imov")
1540 (eq_attr "alternative" "3,5")
1541 (const_string "imovx")
1542 (and (ne (symbol_ref "TARGET_MOVX")
1544 (eq_attr "alternative" "2"))
1545 (const_string "imovx")
1547 (const_string "imov")))
1549 (cond [(eq_attr "alternative" "3,4,5")
1551 (eq_attr "alternative" "6")
1553 (eq_attr "type" "imovx")
1555 (and (eq_attr "type" "imov")
1556 (and (eq_attr "alternative" "0,1,2")
1557 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
1560 ;; Avoid partial register stalls when not using QImode arithmetic
1561 (and (eq_attr "type" "imov")
1562 (and (eq_attr "alternative" "0,1,2")
1563 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
1565 (eq (symbol_ref "TARGET_QIMODE_MATH")
1569 (const_string "QI")))])
1571 (define_expand "reload_outqi"
1572 [(parallel [(match_operand:QI 0 "" "=m")
1573 (match_operand:QI 1 "register_operand" "r")
1574 (match_operand:QI 2 "register_operand" "=&q")])]
1578 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
1580 if (reg_overlap_mentioned_p (op2, op0))
1582 if (! q_regs_operand (op1, QImode))
1584 emit_insn (gen_movqi (op2, op1));
1587 emit_insn (gen_movqi (op0, op1));
1591 (define_insn "*swapqi"
1592 [(set (match_operand:QI 0 "register_operand" "+r")
1593 (match_operand:QI 1 "register_operand" "+r"))
1598 [(set_attr "type" "imov")
1599 (set_attr "pent_pair" "np")
1600 (set_attr "mode" "QI")
1601 (set_attr "modrm" "0")])
1603 (define_expand "movstrictqi"
1604 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1605 (match_operand:QI 1 "general_operand" ""))]
1606 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1608 /* Don't generate memory->memory moves, go through a register. */
1609 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1610 operands[1] = force_reg (QImode, operands[1]);
1613 (define_insn "*movstrictqi_1"
1614 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1615 (match_operand:QI 1 "general_operand" "*qn,m"))]
1616 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1617 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1618 "mov{b}\t{%1, %0|%0, %1}"
1619 [(set_attr "type" "imov")
1620 (set_attr "mode" "QI")])
1622 (define_insn "*movstrictqi_xor"
1623 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
1624 (match_operand:QI 1 "const0_operand" "i"))
1625 (clobber (reg:CC FLAGS_REG))]
1626 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1627 "xor{b}\t{%0, %0|%0, %0}"
1628 [(set_attr "type" "alu1")
1629 (set_attr "mode" "QI")
1630 (set_attr "length_immediate" "0")])
1632 (define_insn "*movsi_extv_1"
1633 [(set (match_operand:SI 0 "register_operand" "=R")
1634 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
1638 "movs{bl|x}\t{%h1, %0|%0, %h1}"
1639 [(set_attr "type" "imovx")
1640 (set_attr "mode" "SI")])
1642 (define_insn "*movhi_extv_1"
1643 [(set (match_operand:HI 0 "register_operand" "=R")
1644 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
1648 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
1649 [(set_attr "type" "imovx")
1650 (set_attr "mode" "SI")])
1652 (define_insn "*movqi_extv_1"
1653 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
1654 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1659 switch (get_attr_type (insn))
1662 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1664 return "mov{b}\t{%h1, %0|%0, %h1}";
1668 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1669 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1670 (ne (symbol_ref "TARGET_MOVX")
1672 (const_string "imovx")
1673 (const_string "imov")))
1675 (if_then_else (eq_attr "type" "imovx")
1677 (const_string "QI")))])
1679 (define_insn "*movqi_extv_1_rex64"
1680 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1681 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1686 switch (get_attr_type (insn))
1689 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1691 return "mov{b}\t{%h1, %0|%0, %h1}";
1695 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1696 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1697 (ne (symbol_ref "TARGET_MOVX")
1699 (const_string "imovx")
1700 (const_string "imov")))
1702 (if_then_else (eq_attr "type" "imovx")
1704 (const_string "QI")))])
1706 ;; Stores and loads of ax to arbitrary constant address.
1707 ;; We fake an second form of instruction to force reload to load address
1708 ;; into register when rax is not available
1709 (define_insn "*movabsqi_1_rex64"
1710 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1711 (match_operand:QI 1 "nonmemory_operand" "a,er"))]
1712 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1714 movabs{b}\t{%1, %P0|%P0, %1}
1715 mov{b}\t{%1, %a0|%a0, %1}"
1716 [(set_attr "type" "imov")
1717 (set_attr "modrm" "0,*")
1718 (set_attr "length_address" "8,0")
1719 (set_attr "length_immediate" "0,*")
1720 (set_attr "memory" "store")
1721 (set_attr "mode" "QI")])
1723 (define_insn "*movabsqi_2_rex64"
1724 [(set (match_operand:QI 0 "register_operand" "=a,r")
1725 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1726 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1728 movabs{b}\t{%P1, %0|%0, %P1}
1729 mov{b}\t{%a1, %0|%0, %a1}"
1730 [(set_attr "type" "imov")
1731 (set_attr "modrm" "0,*")
1732 (set_attr "length_address" "8,0")
1733 (set_attr "length_immediate" "0")
1734 (set_attr "memory" "load")
1735 (set_attr "mode" "QI")])
1737 (define_insn "*movsi_extzv_1"
1738 [(set (match_operand:SI 0 "register_operand" "=R")
1739 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
1743 "movz{bl|x}\t{%h1, %0|%0, %h1}"
1744 [(set_attr "type" "imovx")
1745 (set_attr "mode" "SI")])
1747 (define_insn "*movqi_extzv_2"
1748 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
1749 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1754 switch (get_attr_type (insn))
1757 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1759 return "mov{b}\t{%h1, %0|%0, %h1}";
1763 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1764 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1765 (ne (symbol_ref "TARGET_MOVX")
1767 (const_string "imovx")
1768 (const_string "imov")))
1770 (if_then_else (eq_attr "type" "imovx")
1772 (const_string "QI")))])
1774 (define_insn "*movqi_extzv_2_rex64"
1775 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1776 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1781 switch (get_attr_type (insn))
1784 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1786 return "mov{b}\t{%h1, %0|%0, %h1}";
1790 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1791 (ne (symbol_ref "TARGET_MOVX")
1793 (const_string "imovx")
1794 (const_string "imov")))
1796 (if_then_else (eq_attr "type" "imovx")
1798 (const_string "QI")))])
1800 (define_insn "movsi_insv_1"
1801 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1804 (match_operand:SI 1 "general_operand" "Qmn"))]
1806 "mov{b}\t{%b1, %h0|%h0, %b1}"
1807 [(set_attr "type" "imov")
1808 (set_attr "mode" "QI")])
1810 (define_insn "movdi_insv_1_rex64"
1811 [(set (zero_extract:DI (match_operand 0 "ext_register_operand" "+Q")
1814 (match_operand:DI 1 "nonmemory_operand" "Qn"))]
1816 "mov{b}\t{%b1, %h0|%h0, %b1}"
1817 [(set_attr "type" "imov")
1818 (set_attr "mode" "QI")])
1820 (define_insn "*movqi_insv_2"
1821 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1824 (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
1827 "mov{b}\t{%h1, %h0|%h0, %h1}"
1828 [(set_attr "type" "imov")
1829 (set_attr "mode" "QI")])
1831 (define_expand "movdi"
1832 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1833 (match_operand:DI 1 "general_operand" ""))]
1835 "ix86_expand_move (DImode, operands); DONE;")
1837 (define_insn "*pushdi"
1838 [(set (match_operand:DI 0 "push_operand" "=<")
1839 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
1843 (define_insn "pushdi2_rex64"
1844 [(set (match_operand:DI 0 "push_operand" "=<,!<")
1845 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
1850 [(set_attr "type" "push,multi")
1851 (set_attr "mode" "DI")])
1853 ;; Convert impossible pushes of immediate to existing instructions.
1854 ;; First try to get scratch register and go through it. In case this
1855 ;; fails, push sign extended lower part first and then overwrite
1856 ;; upper part by 32bit move.
1858 [(match_scratch:DI 2 "r")
1859 (set (match_operand:DI 0 "push_operand" "")
1860 (match_operand:DI 1 "immediate_operand" ""))]
1861 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1862 && !x86_64_immediate_operand (operands[1], DImode)"
1863 [(set (match_dup 2) (match_dup 1))
1864 (set (match_dup 0) (match_dup 2))]
1867 ;; We need to define this as both peepholer and splitter for case
1868 ;; peephole2 pass is not run.
1870 [(set (match_operand:DI 0 "push_operand" "")
1871 (match_operand:DI 1 "immediate_operand" ""))]
1872 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1873 && !x86_64_immediate_operand (operands[1], DImode)"
1874 [(set (match_dup 0) (match_dup 1))
1875 (set (match_dup 2) (match_dup 3))]
1876 "split_di (operands + 1, 1, operands + 2, operands + 3);
1877 operands[1] = gen_lowpart (DImode, operands[2]);
1878 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1883 [(set (match_operand:DI 0 "push_operand" "")
1884 (match_operand:DI 1 "immediate_operand" ""))]
1885 "TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)
1886 && !symbolic_operand (operands[1], DImode)
1887 && !x86_64_immediate_operand (operands[1], DImode)"
1888 [(set (match_dup 0) (match_dup 1))
1889 (set (match_dup 2) (match_dup 3))]
1890 "split_di (operands + 1, 1, operands + 2, operands + 3);
1891 operands[1] = gen_lowpart (DImode, operands[2]);
1892 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1896 (define_insn "*pushdi2_prologue_rex64"
1897 [(set (match_operand:DI 0 "push_operand" "=<")
1898 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
1899 (clobber (mem:BLK (scratch)))]
1902 [(set_attr "type" "push")
1903 (set_attr "mode" "DI")])
1905 (define_insn "*popdi1_epilogue_rex64"
1906 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1907 (mem:DI (reg:DI SP_REG)))
1908 (set (reg:DI SP_REG)
1909 (plus:DI (reg:DI SP_REG) (const_int 8)))
1910 (clobber (mem:BLK (scratch)))]
1913 [(set_attr "type" "pop")
1914 (set_attr "mode" "DI")])
1916 (define_insn "popdi1"
1917 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1918 (mem:DI (reg:DI SP_REG)))
1919 (set (reg:DI SP_REG)
1920 (plus:DI (reg:DI SP_REG) (const_int 8)))]
1923 [(set_attr "type" "pop")
1924 (set_attr "mode" "DI")])
1926 (define_insn "*movdi_xor_rex64"
1927 [(set (match_operand:DI 0 "register_operand" "=r")
1928 (match_operand:DI 1 "const0_operand" "i"))
1929 (clobber (reg:CC FLAGS_REG))]
1930 "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
1931 && reload_completed"
1932 "xor{l}\t{%k0, %k0|%k0, %k0}"
1933 [(set_attr "type" "alu1")
1934 (set_attr "mode" "SI")
1935 (set_attr "length_immediate" "0")])
1937 (define_insn "*movdi_or_rex64"
1938 [(set (match_operand:DI 0 "register_operand" "=r")
1939 (match_operand:DI 1 "const_int_operand" "i"))
1940 (clobber (reg:CC FLAGS_REG))]
1941 "TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
1943 && operands[1] == constm1_rtx"
1945 operands[1] = constm1_rtx;
1946 return "or{q}\t{%1, %0|%0, %1}";
1948 [(set_attr "type" "alu1")
1949 (set_attr "mode" "DI")
1950 (set_attr "length_immediate" "1")])
1952 (define_insn "*movdi_2"
1953 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y")
1954 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
1956 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1960 movq\t{%1, %0|%0, %1}
1961 movq\t{%1, %0|%0, %1}
1962 movq\t{%1, %0|%0, %1}
1963 movdqa\t{%1, %0|%0, %1}
1964 movq\t{%1, %0|%0, %1}"
1965 [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov")
1966 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
1969 [(set (match_operand:DI 0 "push_operand" "")
1970 (match_operand:DI 1 "general_operand" ""))]
1971 "!TARGET_64BIT && reload_completed
1972 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1974 "ix86_split_long_move (operands); DONE;")
1976 ;; %%% This multiword shite has got to go.
1978 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1979 (match_operand:DI 1 "general_operand" ""))]
1980 "!TARGET_64BIT && reload_completed
1981 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
1982 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1984 "ix86_split_long_move (operands); DONE;")
1986 (define_insn "*movdi_1_rex64"
1987 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!rm,!*y,!*Y,!rm,!*Y,!*Y,!*y")
1988 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,rm,*Y,*Y,rm,*y,*Y"))]
1990 && (TARGET_INTER_UNIT_MOVES || optimize_size)
1991 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1993 switch (get_attr_type (insn))
1996 if (which_alternative == 11)
1997 return "movq2dq\t{%1, %0|%0, %1}";
1999 return "movdq2q\t{%1, %0|%0, %1}";
2001 if (get_attr_mode (insn) == MODE_TI)
2002 return "movdqa\t{%1, %0|%0, %1}";
2005 /* Moves from and into integer register is done using movd opcode with
2007 if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
2008 return "movd\t{%1, %0|%0, %1}";
2009 return "movq\t{%1, %0|%0, %1}";
2013 return "lea{q}\t{%a1, %0|%0, %a1}";
2015 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
2017 if (get_attr_mode (insn) == MODE_SI)
2018 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2019 else if (which_alternative == 2)
2020 return "movabs{q}\t{%1, %0|%0, %1}";
2022 return "mov{q}\t{%1, %0|%0, %1}";
2026 (cond [(eq_attr "alternative" "5,6,7")
2027 (const_string "mmxmov")
2028 (eq_attr "alternative" "8,9,10")
2029 (const_string "ssemov")
2030 (eq_attr "alternative" "11,12")
2031 (const_string "ssecvt")
2032 (eq_attr "alternative" "4")
2033 (const_string "multi")
2034 (and (ne (symbol_ref "flag_pic") (const_int 0))
2035 (match_operand:DI 1 "symbolic_operand" ""))
2036 (const_string "lea")
2038 (const_string "imov")))
2039 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*,*,*")
2040 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*,*,*")
2041 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI,DI,DI")])
2043 (define_insn "*movdi_1_rex64_nointerunit"
2044 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!m,!*y,!*Y,!m,!*Y")
2045 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,m,*Y,*Y,m"))]
2047 && (!TARGET_INTER_UNIT_MOVES && !optimize_size)
2048 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2050 switch (get_attr_type (insn))
2053 if (get_attr_mode (insn) == MODE_TI)
2054 return "movdqa\t{%1, %0|%0, %1}";
2057 return "movq\t{%1, %0|%0, %1}";
2061 return "lea{q}\t{%a1, %0|%0, %a1}";
2063 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
2065 if (get_attr_mode (insn) == MODE_SI)
2066 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2067 else if (which_alternative == 2)
2068 return "movabs{q}\t{%1, %0|%0, %1}";
2070 return "mov{q}\t{%1, %0|%0, %1}";
2074 (cond [(eq_attr "alternative" "5,6,7")
2075 (const_string "mmxmov")
2076 (eq_attr "alternative" "8,9,10")
2077 (const_string "ssemov")
2078 (eq_attr "alternative" "4")
2079 (const_string "multi")
2080 (and (ne (symbol_ref "flag_pic") (const_int 0))
2081 (match_operand:DI 1 "symbolic_operand" ""))
2082 (const_string "lea")
2084 (const_string "imov")))
2085 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*")
2086 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*")
2087 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI")])
2089 ;; Stores and loads of ax to arbitrary constant address.
2090 ;; We fake an second form of instruction to force reload to load address
2091 ;; into register when rax is not available
2092 (define_insn "*movabsdi_1_rex64"
2093 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
2094 (match_operand:DI 1 "nonmemory_operand" "a,er"))]
2095 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
2097 movabs{q}\t{%1, %P0|%P0, %1}
2098 mov{q}\t{%1, %a0|%a0, %1}"
2099 [(set_attr "type" "imov")
2100 (set_attr "modrm" "0,*")
2101 (set_attr "length_address" "8,0")
2102 (set_attr "length_immediate" "0,*")
2103 (set_attr "memory" "store")
2104 (set_attr "mode" "DI")])
2106 (define_insn "*movabsdi_2_rex64"
2107 [(set (match_operand:DI 0 "register_operand" "=a,r")
2108 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2109 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
2111 movabs{q}\t{%P1, %0|%0, %P1}
2112 mov{q}\t{%a1, %0|%0, %a1}"
2113 [(set_attr "type" "imov")
2114 (set_attr "modrm" "0,*")
2115 (set_attr "length_address" "8,0")
2116 (set_attr "length_immediate" "0")
2117 (set_attr "memory" "load")
2118 (set_attr "mode" "DI")])
2120 ;; Convert impossible stores of immediate to existing instructions.
2121 ;; First try to get scratch register and go through it. In case this
2122 ;; fails, move by 32bit parts.
2124 [(match_scratch:DI 2 "r")
2125 (set (match_operand:DI 0 "memory_operand" "")
2126 (match_operand:DI 1 "immediate_operand" ""))]
2127 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2128 && !x86_64_immediate_operand (operands[1], DImode)"
2129 [(set (match_dup 2) (match_dup 1))
2130 (set (match_dup 0) (match_dup 2))]
2133 ;; We need to define this as both peepholer and splitter for case
2134 ;; peephole2 pass is not run.
2136 [(set (match_operand:DI 0 "memory_operand" "")
2137 (match_operand:DI 1 "immediate_operand" ""))]
2138 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2139 && !x86_64_immediate_operand (operands[1], DImode)"
2140 [(set (match_dup 2) (match_dup 3))
2141 (set (match_dup 4) (match_dup 5))]
2142 "split_di (operands, 2, operands + 2, operands + 4);")
2145 [(set (match_operand:DI 0 "memory_operand" "")
2146 (match_operand:DI 1 "immediate_operand" ""))]
2147 "TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)
2148 && !symbolic_operand (operands[1], DImode)
2149 && !x86_64_immediate_operand (operands[1], DImode)"
2150 [(set (match_dup 2) (match_dup 3))
2151 (set (match_dup 4) (match_dup 5))]
2152 "split_di (operands, 2, operands + 2, operands + 4);")
2154 (define_insn "*swapdi_rex64"
2155 [(set (match_operand:DI 0 "register_operand" "+r")
2156 (match_operand:DI 1 "register_operand" "+r"))
2161 [(set_attr "type" "imov")
2162 (set_attr "pent_pair" "np")
2163 (set_attr "athlon_decode" "vector")
2164 (set_attr "mode" "DI")
2165 (set_attr "modrm" "0")])
2168 (define_expand "movsf"
2169 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2170 (match_operand:SF 1 "general_operand" ""))]
2172 "ix86_expand_move (SFmode, operands); DONE;")
2174 (define_insn "*pushsf"
2175 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2176 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2179 switch (which_alternative)
2182 return "push{l}\t%1";
2185 /* This insn should be already split before reg-stack. */
2189 [(set_attr "type" "multi,push,multi")
2190 (set_attr "mode" "SF,SI,SF")])
2192 (define_insn "*pushsf_rex64"
2193 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2194 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2197 switch (which_alternative)
2200 return "push{q}\t%q1";
2203 /* This insn should be already split before reg-stack. */
2207 [(set_attr "type" "multi,push,multi")
2208 (set_attr "mode" "SF,DI,SF")])
2211 [(set (match_operand:SF 0 "push_operand" "")
2212 (match_operand:SF 1 "memory_operand" ""))]
2214 && GET_CODE (operands[1]) == MEM
2215 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2216 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2219 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2222 ;; %%% Kill this when call knows how to work this out.
2224 [(set (match_operand:SF 0 "push_operand" "")
2225 (match_operand:SF 1 "any_fp_register_operand" ""))]
2227 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
2228 (set (mem:SF (reg:SI SP_REG)) (match_dup 1))])
2231 [(set (match_operand:SF 0 "push_operand" "")
2232 (match_operand:SF 1 "any_fp_register_operand" ""))]
2234 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
2235 (set (mem:SF (reg:DI SP_REG)) (match_dup 1))])
2237 (define_insn "*movsf_1"
2238 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y")
2239 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,rm,*y,*y"))]
2240 "(TARGET_INTER_UNIT_MOVES || optimize_size)
2241 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2242 && (reload_in_progress || reload_completed
2243 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2244 || GET_CODE (operands[1]) != CONST_DOUBLE
2245 || memory_operand (operands[0], SFmode))"
2247 switch (which_alternative)
2250 return output_387_reg_move (insn, operands);
2253 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2254 return "fstp%z0\t%y0";
2256 return "fst%z0\t%y0";
2259 return standard_80387_constant_opcode (operands[1]);
2263 return "mov{l}\t{%1, %0|%0, %1}";
2265 if (get_attr_mode (insn) == MODE_TI)
2266 return "pxor\t%0, %0";
2268 return "xorps\t%0, %0";
2270 if (get_attr_mode (insn) == MODE_V4SF)
2271 return "movaps\t{%1, %0|%0, %1}";
2273 return "movss\t{%1, %0|%0, %1}";
2276 return "movss\t{%1, %0|%0, %1}";
2280 return "movd\t{%1, %0|%0, %1}";
2283 return "movq\t{%1, %0|%0, %1}";
2289 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2291 (cond [(eq_attr "alternative" "3,4,9,10")
2293 (eq_attr "alternative" "5")
2295 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2297 (ne (symbol_ref "TARGET_SSE2")
2299 (eq (symbol_ref "optimize_size")
2302 (const_string "V4SF"))
2303 /* For architectures resolving dependencies on
2304 whole SSE registers use APS move to break dependency
2305 chains, otherwise use short move to avoid extra work.
2307 Do the same for architectures resolving dependencies on
2308 the parts. While in DF mode it is better to always handle
2309 just register parts, the SF mode is different due to lack
2310 of instructions to load just part of the register. It is
2311 better to maintain the whole registers in single format
2312 to avoid problems on using packed logical operations. */
2313 (eq_attr "alternative" "6")
2315 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2317 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2319 (const_string "V4SF")
2320 (const_string "SF"))
2321 (eq_attr "alternative" "11")
2322 (const_string "DI")]
2323 (const_string "SF")))])
2325 (define_insn "*movsf_1_nointerunit"
2326 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!m,!*y")
2327 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,m,*y,*y"))]
2328 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
2329 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2330 && (reload_in_progress || reload_completed
2331 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2332 || GET_CODE (operands[1]) != CONST_DOUBLE
2333 || memory_operand (operands[0], SFmode))"
2335 switch (which_alternative)
2338 return output_387_reg_move (insn, operands);
2341 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2342 return "fstp%z0\t%y0";
2344 return "fst%z0\t%y0";
2347 return standard_80387_constant_opcode (operands[1]);
2351 return "mov{l}\t{%1, %0|%0, %1}";
2353 if (get_attr_mode (insn) == MODE_TI)
2354 return "pxor\t%0, %0";
2356 return "xorps\t%0, %0";
2358 if (get_attr_mode (insn) == MODE_V4SF)
2359 return "movaps\t{%1, %0|%0, %1}";
2361 return "movss\t{%1, %0|%0, %1}";
2364 return "movss\t{%1, %0|%0, %1}";
2368 return "movd\t{%1, %0|%0, %1}";
2371 return "movq\t{%1, %0|%0, %1}";
2377 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2379 (cond [(eq_attr "alternative" "3,4,9,10")
2381 (eq_attr "alternative" "5")
2383 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2385 (ne (symbol_ref "TARGET_SSE2")
2387 (eq (symbol_ref "optimize_size")
2390 (const_string "V4SF"))
2391 /* For architectures resolving dependencies on
2392 whole SSE registers use APS move to break dependency
2393 chains, otherwise use short move to avoid extra work.
2395 Do the same for architectures resolving dependencies on
2396 the parts. While in DF mode it is better to always handle
2397 just register parts, the SF mode is different due to lack
2398 of instructions to load just part of the register. It is
2399 better to maintain the whole registers in single format
2400 to avoid problems on using packed logical operations. */
2401 (eq_attr "alternative" "6")
2403 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2405 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2407 (const_string "V4SF")
2408 (const_string "SF"))
2409 (eq_attr "alternative" "11")
2410 (const_string "DI")]
2411 (const_string "SF")))])
2413 (define_insn "*swapsf"
2414 [(set (match_operand:SF 0 "register_operand" "+f")
2415 (match_operand:SF 1 "register_operand" "+f"))
2418 "reload_completed || !TARGET_SSE"
2420 if (STACK_TOP_P (operands[0]))
2425 [(set_attr "type" "fxch")
2426 (set_attr "mode" "SF")])
2428 (define_expand "movdf"
2429 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2430 (match_operand:DF 1 "general_operand" ""))]
2432 "ix86_expand_move (DFmode, operands); DONE;")
2434 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2435 ;; Size of pushdf using integer instructions is 2+2*memory operand size
2436 ;; On the average, pushdf using integers can be still shorter. Allow this
2437 ;; pattern for optimize_size too.
2439 (define_insn "*pushdf_nointeger"
2440 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2441 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2442 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2444 /* This insn should be already split before reg-stack. */
2447 [(set_attr "type" "multi")
2448 (set_attr "mode" "DF,SI,SI,DF")])
2450 (define_insn "*pushdf_integer"
2451 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2452 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2453 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2455 /* This insn should be already split before reg-stack. */
2458 [(set_attr "type" "multi")
2459 (set_attr "mode" "DF,SI,DF")])
2461 ;; %%% Kill this when call knows how to work this out.
2463 [(set (match_operand:DF 0 "push_operand" "")
2464 (match_operand:DF 1 "any_fp_register_operand" ""))]
2465 "!TARGET_64BIT && reload_completed"
2466 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
2467 (set (mem:DF (reg:SI SP_REG)) (match_dup 1))]
2471 [(set (match_operand:DF 0 "push_operand" "")
2472 (match_operand:DF 1 "any_fp_register_operand" ""))]
2473 "TARGET_64BIT && reload_completed"
2474 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
2475 (set (mem:DF (reg:DI SP_REG)) (match_dup 1))]
2479 [(set (match_operand:DF 0 "push_operand" "")
2480 (match_operand:DF 1 "general_operand" ""))]
2483 "ix86_split_long_move (operands); DONE;")
2485 ;; Moving is usually shorter when only FP registers are used. This separate
2486 ;; movdf pattern avoids the use of integer registers for FP operations
2487 ;; when optimizing for size.
2489 (define_insn "*movdf_nointeger"
2490 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2491 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,C,Y#f,YHm#f,Y#f"))]
2492 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2493 && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
2494 && (reload_in_progress || reload_completed
2495 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2496 || GET_CODE (operands[1]) != CONST_DOUBLE
2497 || memory_operand (operands[0], DFmode))"
2499 switch (which_alternative)
2502 return output_387_reg_move (insn, operands);
2505 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2506 return "fstp%z0\t%y0";
2508 return "fst%z0\t%y0";
2511 return standard_80387_constant_opcode (operands[1]);
2517 switch (get_attr_mode (insn))
2520 return "xorps\t%0, %0";
2522 return "xorpd\t%0, %0";
2524 return "pxor\t%0, %0";
2529 switch (get_attr_mode (insn))
2532 return "movaps\t{%1, %0|%0, %1}";
2534 return "movapd\t{%1, %0|%0, %1}";
2536 return "movsd\t{%1, %0|%0, %1}";
2541 if (get_attr_mode (insn) == MODE_V2DF)
2542 return "movlpd\t{%1, %0|%0, %1}";
2544 return "movsd\t{%1, %0|%0, %1}";
2546 return "movsd\t{%1, %0|%0, %1}";
2552 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2554 (cond [(eq_attr "alternative" "3,4")
2556 /* xorps is one byte shorter. */
2557 (eq_attr "alternative" "5")
2558 (cond [(ne (symbol_ref "optimize_size")
2560 (const_string "V4SF")
2561 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2563 (const_string "TI")]
2564 (const_string "V2DF"))
2565 /* For architectures resolving dependencies on
2566 whole SSE registers use APD move to break dependency
2567 chains, otherwise use short move to avoid extra work.
2569 movaps encodes one byte shorter. */
2570 (eq_attr "alternative" "6")
2572 [(ne (symbol_ref "optimize_size")
2574 (const_string "V4SF")
2575 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2577 (const_string "V2DF")]
2578 (const_string "DF"))
2579 /* For architectures resolving dependencies on register
2580 parts we may avoid extra work to zero out upper part
2582 (eq_attr "alternative" "7")
2584 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2586 (const_string "V2DF")
2587 (const_string "DF"))]
2588 (const_string "DF")))])
2590 (define_insn "*movdf_integer"
2591 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2592 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,C,Y#rf,Ym#rf,Y#rf"))]
2593 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2594 && ((!optimize_size && TARGET_INTEGER_DFMODE_MOVES) || TARGET_64BIT)
2595 && (reload_in_progress || reload_completed
2596 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2597 || GET_CODE (operands[1]) != CONST_DOUBLE
2598 || memory_operand (operands[0], DFmode))"
2600 switch (which_alternative)
2603 return output_387_reg_move (insn, operands);
2606 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2607 return "fstp%z0\t%y0";
2609 return "fst%z0\t%y0";
2612 return standard_80387_constant_opcode (operands[1]);
2619 switch (get_attr_mode (insn))
2622 return "xorps\t%0, %0";
2624 return "xorpd\t%0, %0";
2626 return "pxor\t%0, %0";
2631 switch (get_attr_mode (insn))
2634 return "movaps\t{%1, %0|%0, %1}";
2636 return "movapd\t{%1, %0|%0, %1}";
2638 return "movsd\t{%1, %0|%0, %1}";
2643 if (get_attr_mode (insn) == MODE_V2DF)
2644 return "movlpd\t{%1, %0|%0, %1}";
2646 return "movsd\t{%1, %0|%0, %1}";
2648 return "movsd\t{%1, %0|%0, %1}";
2654 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2656 (cond [(eq_attr "alternative" "3,4")
2658 /* xorps is one byte shorter. */
2659 (eq_attr "alternative" "5")
2660 (cond [(ne (symbol_ref "optimize_size")
2662 (const_string "V4SF")
2663 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2665 (const_string "TI")]
2666 (const_string "V2DF"))
2667 /* For architectures resolving dependencies on
2668 whole SSE registers use APD move to break dependency
2669 chains, otherwise use short move to avoid extra work.
2671 movaps encodes one byte shorter. */
2672 (eq_attr "alternative" "6")
2674 [(ne (symbol_ref "optimize_size")
2676 (const_string "V4SF")
2677 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2679 (const_string "V2DF")]
2680 (const_string "DF"))
2681 /* For architectures resolving dependencies on register
2682 parts we may avoid extra work to zero out upper part
2684 (eq_attr "alternative" "7")
2686 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2688 (const_string "V2DF")
2689 (const_string "DF"))]
2690 (const_string "DF")))])
2693 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2694 (match_operand:DF 1 "general_operand" ""))]
2696 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2697 && ! (ANY_FP_REG_P (operands[0]) ||
2698 (GET_CODE (operands[0]) == SUBREG
2699 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2700 && ! (ANY_FP_REG_P (operands[1]) ||
2701 (GET_CODE (operands[1]) == SUBREG
2702 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2704 "ix86_split_long_move (operands); DONE;")
2706 (define_insn "*swapdf"
2707 [(set (match_operand:DF 0 "register_operand" "+f")
2708 (match_operand:DF 1 "register_operand" "+f"))
2711 "reload_completed || !TARGET_SSE2"
2713 if (STACK_TOP_P (operands[0]))
2718 [(set_attr "type" "fxch")
2719 (set_attr "mode" "DF")])
2721 (define_expand "movxf"
2722 [(set (match_operand:XF 0 "nonimmediate_operand" "")
2723 (match_operand:XF 1 "general_operand" ""))]
2725 "ix86_expand_move (XFmode, operands); DONE;")
2727 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2728 ;; Size of pushdf using integer instructions is 3+3*memory operand size
2729 ;; Pushing using integer instructions is longer except for constants
2730 ;; and direct memory references.
2731 ;; (assuming that any given constant is pushed only once, but this ought to be
2732 ;; handled elsewhere).
2734 (define_insn "*pushxf_nointeger"
2735 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
2736 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
2739 /* This insn should be already split before reg-stack. */
2742 [(set_attr "type" "multi")
2743 (set_attr "mode" "XF,SI,SI")])
2745 (define_insn "*pushxf_integer"
2746 [(set (match_operand:XF 0 "push_operand" "=<,<")
2747 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
2750 /* This insn should be already split before reg-stack. */
2753 [(set_attr "type" "multi")
2754 (set_attr "mode" "XF,SI")])
2757 [(set (match_operand 0 "push_operand" "")
2758 (match_operand 1 "general_operand" ""))]
2760 && (GET_MODE (operands[0]) == XFmode
2761 || GET_MODE (operands[0]) == DFmode)
2762 && !ANY_FP_REG_P (operands[1])"
2764 "ix86_split_long_move (operands); DONE;")
2767 [(set (match_operand:XF 0 "push_operand" "")
2768 (match_operand:XF 1 "any_fp_register_operand" ""))]
2770 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
2771 (set (mem:XF (reg:SI SP_REG)) (match_dup 1))]
2772 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
2775 [(set (match_operand:XF 0 "push_operand" "")
2776 (match_operand:XF 1 "any_fp_register_operand" ""))]
2778 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
2779 (set (mem:XF (reg:DI SP_REG)) (match_dup 1))]
2780 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
2782 ;; Do not use integer registers when optimizing for size
2783 (define_insn "*movxf_nointeger"
2784 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2785 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2787 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2788 && (reload_in_progress || reload_completed
2789 || GET_CODE (operands[1]) != CONST_DOUBLE
2790 || memory_operand (operands[0], XFmode))"
2792 switch (which_alternative)
2795 return output_387_reg_move (insn, operands);
2798 /* There is no non-popping store to memory for XFmode. So if
2799 we need one, follow the store with a load. */
2800 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2801 return "fstp%z0\t%y0\;fld%z0\t%y0";
2803 return "fstp%z0\t%y0";
2806 return standard_80387_constant_opcode (operands[1]);
2813 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2814 (set_attr "mode" "XF,XF,XF,SI,SI")])
2816 (define_insn "*movxf_integer"
2817 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2818 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2820 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2821 && (reload_in_progress || reload_completed
2822 || GET_CODE (operands[1]) != CONST_DOUBLE
2823 || memory_operand (operands[0], XFmode))"
2825 switch (which_alternative)
2828 return output_387_reg_move (insn, operands);
2831 /* There is no non-popping store to memory for XFmode. So if
2832 we need one, follow the store with a load. */
2833 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2834 return "fstp%z0\t%y0\;fld%z0\t%y0";
2836 return "fstp%z0\t%y0";
2839 return standard_80387_constant_opcode (operands[1]);
2846 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2847 (set_attr "mode" "XF,XF,XF,SI,SI")])
2850 [(set (match_operand 0 "nonimmediate_operand" "")
2851 (match_operand 1 "general_operand" ""))]
2853 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2854 && GET_MODE (operands[0]) == XFmode
2855 && ! (ANY_FP_REG_P (operands[0]) ||
2856 (GET_CODE (operands[0]) == SUBREG
2857 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2858 && ! (ANY_FP_REG_P (operands[1]) ||
2859 (GET_CODE (operands[1]) == SUBREG
2860 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2862 "ix86_split_long_move (operands); DONE;")
2865 [(set (match_operand 0 "register_operand" "")
2866 (match_operand 1 "memory_operand" ""))]
2868 && GET_CODE (operands[1]) == MEM
2869 && (GET_MODE (operands[0]) == XFmode
2870 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
2871 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2872 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2873 [(set (match_dup 0) (match_dup 1))]
2875 rtx c = get_pool_constant (XEXP (operands[1], 0));
2876 rtx r = operands[0];
2878 if (GET_CODE (r) == SUBREG)
2883 if (!standard_sse_constant_p (c))
2886 else if (FP_REG_P (r))
2888 if (!standard_80387_constant_p (c))
2891 else if (MMX_REG_P (r))
2897 (define_insn "swapxf"
2898 [(set (match_operand:XF 0 "register_operand" "+f")
2899 (match_operand:XF 1 "register_operand" "+f"))
2904 if (STACK_TOP_P (operands[0]))
2909 [(set_attr "type" "fxch")
2910 (set_attr "mode" "XF")])
2912 ;; Zero extension instructions
2914 (define_expand "zero_extendhisi2"
2915 [(set (match_operand:SI 0 "register_operand" "")
2916 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
2919 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
2921 operands[1] = force_reg (HImode, operands[1]);
2922 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
2927 (define_insn "zero_extendhisi2_and"
2928 [(set (match_operand:SI 0 "register_operand" "=r")
2929 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
2930 (clobber (reg:CC FLAGS_REG))]
2931 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2933 [(set_attr "type" "alu1")
2934 (set_attr "mode" "SI")])
2937 [(set (match_operand:SI 0 "register_operand" "")
2938 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
2939 (clobber (reg:CC FLAGS_REG))]
2940 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2941 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
2942 (clobber (reg:CC FLAGS_REG))])]
2945 (define_insn "*zero_extendhisi2_movzwl"
2946 [(set (match_operand:SI 0 "register_operand" "=r")
2947 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
2948 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2949 "movz{wl|x}\t{%1, %0|%0, %1}"
2950 [(set_attr "type" "imovx")
2951 (set_attr "mode" "SI")])
2953 (define_expand "zero_extendqihi2"
2955 [(set (match_operand:HI 0 "register_operand" "")
2956 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2957 (clobber (reg:CC FLAGS_REG))])]
2961 (define_insn "*zero_extendqihi2_and"
2962 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
2963 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
2964 (clobber (reg:CC FLAGS_REG))]
2965 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2967 [(set_attr "type" "alu1")
2968 (set_attr "mode" "HI")])
2970 (define_insn "*zero_extendqihi2_movzbw_and"
2971 [(set (match_operand:HI 0 "register_operand" "=r,r")
2972 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
2973 (clobber (reg:CC FLAGS_REG))]
2974 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2976 [(set_attr "type" "imovx,alu1")
2977 (set_attr "mode" "HI")])
2979 (define_insn "*zero_extendqihi2_movzbw"
2980 [(set (match_operand:HI 0 "register_operand" "=r")
2981 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
2982 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
2983 "movz{bw|x}\t{%1, %0|%0, %1}"
2984 [(set_attr "type" "imovx")
2985 (set_attr "mode" "HI")])
2987 ;; For the movzbw case strip only the clobber
2989 [(set (match_operand:HI 0 "register_operand" "")
2990 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2991 (clobber (reg:CC FLAGS_REG))]
2993 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
2994 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
2995 [(set (match_operand:HI 0 "register_operand" "")
2996 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
2998 ;; When source and destination does not overlap, clear destination
2999 ;; first and then do the movb
3001 [(set (match_operand:HI 0 "register_operand" "")
3002 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3003 (clobber (reg:CC FLAGS_REG))]
3005 && ANY_QI_REG_P (operands[0])
3006 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3007 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3008 [(set (match_dup 0) (const_int 0))
3009 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3010 "operands[2] = gen_lowpart (QImode, operands[0]);")
3012 ;; Rest is handled by single and.
3014 [(set (match_operand:HI 0 "register_operand" "")
3015 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3016 (clobber (reg:CC FLAGS_REG))]
3018 && true_regnum (operands[0]) == true_regnum (operands[1])"
3019 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3020 (clobber (reg:CC FLAGS_REG))])]
3023 (define_expand "zero_extendqisi2"
3025 [(set (match_operand:SI 0 "register_operand" "")
3026 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3027 (clobber (reg:CC FLAGS_REG))])]
3031 (define_insn "*zero_extendqisi2_and"
3032 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3033 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3034 (clobber (reg:CC FLAGS_REG))]
3035 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3037 [(set_attr "type" "alu1")
3038 (set_attr "mode" "SI")])
3040 (define_insn "*zero_extendqisi2_movzbw_and"
3041 [(set (match_operand:SI 0 "register_operand" "=r,r")
3042 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3043 (clobber (reg:CC FLAGS_REG))]
3044 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3046 [(set_attr "type" "imovx,alu1")
3047 (set_attr "mode" "SI")])
3049 (define_insn "*zero_extendqisi2_movzbw"
3050 [(set (match_operand:SI 0 "register_operand" "=r")
3051 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3052 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3053 "movz{bl|x}\t{%1, %0|%0, %1}"
3054 [(set_attr "type" "imovx")
3055 (set_attr "mode" "SI")])
3057 ;; For the movzbl case strip only the clobber
3059 [(set (match_operand:SI 0 "register_operand" "")
3060 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3061 (clobber (reg:CC FLAGS_REG))]
3063 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3064 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3066 (zero_extend:SI (match_dup 1)))])
3068 ;; When source and destination does not overlap, clear destination
3069 ;; first and then do the movb
3071 [(set (match_operand:SI 0 "register_operand" "")
3072 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3073 (clobber (reg:CC FLAGS_REG))]
3075 && ANY_QI_REG_P (operands[0])
3076 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3077 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3078 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3079 [(set (match_dup 0) (const_int 0))
3080 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3081 "operands[2] = gen_lowpart (QImode, operands[0]);")
3083 ;; Rest is handled by single and.
3085 [(set (match_operand:SI 0 "register_operand" "")
3086 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3087 (clobber (reg:CC FLAGS_REG))]
3089 && true_regnum (operands[0]) == true_regnum (operands[1])"
3090 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3091 (clobber (reg:CC FLAGS_REG))])]
3094 ;; %%% Kill me once multi-word ops are sane.
3095 (define_expand "zero_extendsidi2"
3096 [(set (match_operand:DI 0 "register_operand" "=r")
3097 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3101 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3106 (define_insn "zero_extendsidi2_32"
3107 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
3108 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,m,m")))
3109 (clobber (reg:CC FLAGS_REG))]
3110 "!TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
3115 movd\t{%1, %0|%0, %1}
3116 movd\t{%1, %0|%0, %1}"
3117 [(set_attr "mode" "SI,SI,SI,DI,TI")
3118 (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
3120 (define_insn "*zero_extendsidi2_32_1"
3121 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
3122 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,rm,rm")))
3123 (clobber (reg:CC FLAGS_REG))]
3124 "!TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
3129 movd\t{%1, %0|%0, %1}
3130 movd\t{%1, %0|%0, %1}"
3131 [(set_attr "mode" "SI,SI,SI,DI,TI")
3132 (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
3134 (define_insn "zero_extendsidi2_rex64"
3135 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!?Y")
3136 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,m,m")))]
3137 "TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
3139 mov\t{%k1, %k0|%k0, %k1}
3141 movd\t{%1, %0|%0, %1}
3142 movd\t{%1, %0|%0, %1}"
3143 [(set_attr "type" "imovx,imov,mmxmov,ssemov")
3144 (set_attr "mode" "SI,DI,DI,TI")])
3146 (define_insn "*zero_extendsidi2_rex64_1"
3147 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!*?")
3148 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,rm,rm")))]
3149 "TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
3151 mov\t{%k1, %k0|%k0, %k1}
3153 movd\t{%1, %0|%0, %1}
3154 movd\t{%1, %0|%0, %1}"
3155 [(set_attr "type" "imovx,imov,mmxmov,ssemov")
3156 (set_attr "mode" "SI,DI,SI,SI")])
3159 [(set (match_operand:DI 0 "memory_operand" "")
3160 (zero_extend:DI (match_dup 0)))]
3162 [(set (match_dup 4) (const_int 0))]
3163 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3166 [(set (match_operand:DI 0 "register_operand" "")
3167 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3168 (clobber (reg:CC FLAGS_REG))]
3169 "!TARGET_64BIT && reload_completed
3170 && true_regnum (operands[0]) == true_regnum (operands[1])"
3171 [(set (match_dup 4) (const_int 0))]
3172 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3175 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3176 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3177 (clobber (reg:CC FLAGS_REG))]
3178 "!TARGET_64BIT && reload_completed
3179 && !SSE_REG_P (operands[0]) && !MMX_REG_P (operands[0])"
3180 [(set (match_dup 3) (match_dup 1))
3181 (set (match_dup 4) (const_int 0))]
3182 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3184 (define_insn "zero_extendhidi2"
3185 [(set (match_operand:DI 0 "register_operand" "=r,r")
3186 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3189 movz{wl|x}\t{%1, %k0|%k0, %1}
3190 movz{wq|x}\t{%1, %0|%0, %1}"
3191 [(set_attr "type" "imovx")
3192 (set_attr "mode" "SI,DI")])
3194 (define_insn "zero_extendqidi2"
3195 [(set (match_operand:DI 0 "register_operand" "=r,r")
3196 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3199 movz{bl|x}\t{%1, %k0|%k0, %1}
3200 movz{bq|x}\t{%1, %0|%0, %1}"
3201 [(set_attr "type" "imovx")
3202 (set_attr "mode" "SI,DI")])
3204 ;; Sign extension instructions
3206 (define_expand "extendsidi2"
3207 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3208 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3209 (clobber (reg:CC FLAGS_REG))
3210 (clobber (match_scratch:SI 2 ""))])]
3215 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3220 (define_insn "*extendsidi2_1"
3221 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3222 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3223 (clobber (reg:CC FLAGS_REG))
3224 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3228 (define_insn "extendsidi2_rex64"
3229 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3230 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3234 movs{lq|x}\t{%1,%0|%0, %1}"
3235 [(set_attr "type" "imovx")
3236 (set_attr "mode" "DI")
3237 (set_attr "prefix_0f" "0")
3238 (set_attr "modrm" "0,1")])
3240 (define_insn "extendhidi2"
3241 [(set (match_operand:DI 0 "register_operand" "=r")
3242 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3244 "movs{wq|x}\t{%1,%0|%0, %1}"
3245 [(set_attr "type" "imovx")
3246 (set_attr "mode" "DI")])
3248 (define_insn "extendqidi2"
3249 [(set (match_operand:DI 0 "register_operand" "=r")
3250 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3252 "movs{bq|x}\t{%1,%0|%0, %1}"
3253 [(set_attr "type" "imovx")
3254 (set_attr "mode" "DI")])
3256 ;; Extend to memory case when source register does die.
3258 [(set (match_operand:DI 0 "memory_operand" "")
3259 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3260 (clobber (reg:CC FLAGS_REG))
3261 (clobber (match_operand:SI 2 "register_operand" ""))]
3263 && dead_or_set_p (insn, operands[1])
3264 && !reg_mentioned_p (operands[1], operands[0]))"
3265 [(set (match_dup 3) (match_dup 1))
3266 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3267 (clobber (reg:CC FLAGS_REG))])
3268 (set (match_dup 4) (match_dup 1))]
3269 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3271 ;; Extend to memory case when source register does not die.
3273 [(set (match_operand:DI 0 "memory_operand" "")
3274 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3275 (clobber (reg:CC FLAGS_REG))
3276 (clobber (match_operand:SI 2 "register_operand" ""))]
3280 split_di (&operands[0], 1, &operands[3], &operands[4]);
3282 emit_move_insn (operands[3], operands[1]);
3284 /* Generate a cltd if possible and doing so it profitable. */
3285 if (true_regnum (operands[1]) == 0
3286 && true_regnum (operands[2]) == 1
3287 && (optimize_size || TARGET_USE_CLTD))
3289 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3293 emit_move_insn (operands[2], operands[1]);
3294 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3296 emit_move_insn (operands[4], operands[2]);
3300 ;; Extend to register case. Optimize case where source and destination
3301 ;; registers match and cases where we can use cltd.
3303 [(set (match_operand:DI 0 "register_operand" "")
3304 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3305 (clobber (reg:CC FLAGS_REG))
3306 (clobber (match_scratch:SI 2 ""))]
3310 split_di (&operands[0], 1, &operands[3], &operands[4]);
3312 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3313 emit_move_insn (operands[3], operands[1]);
3315 /* Generate a cltd if possible and doing so it profitable. */
3316 if (true_regnum (operands[3]) == 0
3317 && (optimize_size || TARGET_USE_CLTD))
3319 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3323 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3324 emit_move_insn (operands[4], operands[1]);
3326 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3330 (define_insn "extendhisi2"
3331 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3332 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3335 switch (get_attr_prefix_0f (insn))
3338 return "{cwtl|cwde}";
3340 return "movs{wl|x}\t{%1,%0|%0, %1}";
3343 [(set_attr "type" "imovx")
3344 (set_attr "mode" "SI")
3345 (set (attr "prefix_0f")
3346 ;; movsx is short decodable while cwtl is vector decoded.
3347 (if_then_else (and (eq_attr "cpu" "!k6")
3348 (eq_attr "alternative" "0"))
3350 (const_string "1")))
3352 (if_then_else (eq_attr "prefix_0f" "0")
3354 (const_string "1")))])
3356 (define_insn "*extendhisi2_zext"
3357 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3359 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3362 switch (get_attr_prefix_0f (insn))
3365 return "{cwtl|cwde}";
3367 return "movs{wl|x}\t{%1,%k0|%k0, %1}";
3370 [(set_attr "type" "imovx")
3371 (set_attr "mode" "SI")
3372 (set (attr "prefix_0f")
3373 ;; movsx is short decodable while cwtl is vector decoded.
3374 (if_then_else (and (eq_attr "cpu" "!k6")
3375 (eq_attr "alternative" "0"))
3377 (const_string "1")))
3379 (if_then_else (eq_attr "prefix_0f" "0")
3381 (const_string "1")))])
3383 (define_insn "extendqihi2"
3384 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3385 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3388 switch (get_attr_prefix_0f (insn))
3391 return "{cbtw|cbw}";
3393 return "movs{bw|x}\t{%1,%0|%0, %1}";
3396 [(set_attr "type" "imovx")
3397 (set_attr "mode" "HI")
3398 (set (attr "prefix_0f")
3399 ;; movsx is short decodable while cwtl is vector decoded.
3400 (if_then_else (and (eq_attr "cpu" "!k6")
3401 (eq_attr "alternative" "0"))
3403 (const_string "1")))
3405 (if_then_else (eq_attr "prefix_0f" "0")
3407 (const_string "1")))])
3409 (define_insn "extendqisi2"
3410 [(set (match_operand:SI 0 "register_operand" "=r")
3411 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3413 "movs{bl|x}\t{%1,%0|%0, %1}"
3414 [(set_attr "type" "imovx")
3415 (set_attr "mode" "SI")])
3417 (define_insn "*extendqisi2_zext"
3418 [(set (match_operand:DI 0 "register_operand" "=r")
3420 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3422 "movs{bl|x}\t{%1,%k0|%k0, %1}"
3423 [(set_attr "type" "imovx")
3424 (set_attr "mode" "SI")])
3426 ;; Conversions between float and double.
3428 ;; These are all no-ops in the model used for the 80387. So just
3431 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3432 (define_insn "*dummy_extendsfdf2"
3433 [(set (match_operand:DF 0 "push_operand" "=<")
3434 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3439 [(set (match_operand:DF 0 "push_operand" "")
3440 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3442 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
3443 (set (mem:DF (reg:SI SP_REG)) (float_extend:DF (match_dup 1)))])
3446 [(set (match_operand:DF 0 "push_operand" "")
3447 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3449 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
3450 (set (mem:DF (reg:DI SP_REG)) (float_extend:DF (match_dup 1)))])
3452 (define_insn "*dummy_extendsfxf2"
3453 [(set (match_operand:XF 0 "push_operand" "=<")
3454 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3459 [(set (match_operand:XF 0 "push_operand" "")
3460 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3462 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
3463 (set (mem:XF (reg:SI SP_REG)) (float_extend:XF (match_dup 1)))]
3464 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3467 [(set (match_operand:XF 0 "push_operand" "")
3468 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3470 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
3471 (set (mem:DF (reg:DI SP_REG)) (float_extend:XF (match_dup 1)))]
3472 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3475 [(set (match_operand:XF 0 "push_operand" "")
3476 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3478 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
3479 (set (mem:DF (reg:SI SP_REG)) (float_extend:XF (match_dup 1)))]
3480 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3483 [(set (match_operand:XF 0 "push_operand" "")
3484 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3486 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
3487 (set (mem:XF (reg:DI SP_REG)) (float_extend:XF (match_dup 1)))]
3488 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3490 (define_expand "extendsfdf2"
3491 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3492 (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
3493 "TARGET_80387 || TARGET_SSE2"
3495 /* ??? Needed for compress_float_constant since all fp constants
3496 are LEGITIMATE_CONSTANT_P. */
3497 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3498 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3499 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3500 operands[1] = force_reg (SFmode, operands[1]);
3503 (define_insn "*extendsfdf2_1"
3504 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
3505 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
3506 "(TARGET_80387 || TARGET_SSE2)
3507 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3509 switch (which_alternative)
3512 return output_387_reg_move (insn, operands);
3515 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3516 return "fstp%z0\t%y0";
3518 return "fst%z0\t%y0";
3521 return "cvtss2sd\t{%1, %0|%0, %1}";
3527 [(set_attr "type" "fmov,fmov,ssecvt")
3528 (set_attr "mode" "SF,XF,DF")])
3530 (define_insn "*extendsfdf2_1_sse_only"
3531 [(set (match_operand:DF 0 "register_operand" "=Y")
3532 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
3533 "!TARGET_80387 && TARGET_SSE2
3534 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3535 "cvtss2sd\t{%1, %0|%0, %1}"
3536 [(set_attr "type" "ssecvt")
3537 (set_attr "mode" "DF")])
3539 (define_expand "extendsfxf2"
3540 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3541 (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
3544 /* ??? Needed for compress_float_constant since all fp constants
3545 are LEGITIMATE_CONSTANT_P. */
3546 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3547 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3548 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3549 operands[1] = force_reg (SFmode, operands[1]);
3552 (define_insn "*extendsfxf2_1"
3553 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3554 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3556 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3558 switch (which_alternative)
3561 return output_387_reg_move (insn, operands);
3564 /* There is no non-popping store to memory for XFmode. So if
3565 we need one, follow the store with a load. */
3566 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3567 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3569 return "fstp%z0\t%y0";
3575 [(set_attr "type" "fmov")
3576 (set_attr "mode" "SF,XF")])
3578 (define_expand "extenddfxf2"
3579 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3580 (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
3583 /* ??? Needed for compress_float_constant since all fp constants
3584 are LEGITIMATE_CONSTANT_P. */
3585 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3586 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3587 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3588 operands[1] = force_reg (DFmode, operands[1]);
3591 (define_insn "*extenddfxf2_1"
3592 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3593 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3595 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3597 switch (which_alternative)
3600 return output_387_reg_move (insn, operands);
3603 /* There is no non-popping store to memory for XFmode. So if
3604 we need one, follow the store with a load. */
3605 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3606 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3608 return "fstp%z0\t%y0";
3614 [(set_attr "type" "fmov")
3615 (set_attr "mode" "DF,XF")])
3617 ;; %%% This seems bad bad news.
3618 ;; This cannot output into an f-reg because there is no way to be sure
3619 ;; of truncating in that case. Otherwise this is just like a simple move
3620 ;; insn. So we pretend we can output to a reg in order to get better
3621 ;; register preferencing, but we really use a stack slot.
3623 (define_expand "truncdfsf2"
3624 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3626 (match_operand:DF 1 "register_operand" "")))
3627 (clobber (match_dup 2))])]
3628 "TARGET_80387 || TARGET_SSE2"
3632 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
3635 else if (flag_unsafe_math_optimizations)
3637 rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SFmode);
3638 emit_insn (gen_truncdfsf2_noop (reg, operands[1]));
3639 if (reg != operands[0])
3640 emit_move_insn (operands[0], reg);
3644 operands[2] = assign_386_stack_local (SFmode, 0);
3647 (define_insn "truncdfsf2_noop"
3648 [(set (match_operand:SF 0 "register_operand" "=f")
3649 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3650 "TARGET_80387 && flag_unsafe_math_optimizations"
3652 return output_387_reg_move (insn, operands);
3654 [(set_attr "type" "fmov")
3655 (set_attr "mode" "SF")])
3657 (define_insn "*truncdfsf2_1"
3658 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3660 (match_operand:DF 1 "register_operand" "f,f,f,f")))
3661 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3662 "TARGET_80387 && !TARGET_SSE2"
3664 switch (which_alternative)
3667 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3668 return "fstp%z0\t%y0";
3670 return "fst%z0\t%y0";
3675 [(set_attr "type" "fmov,multi,multi,multi")
3676 (set_attr "mode" "SF,SF,SF,SF")])
3678 (define_insn "*truncdfsf2_1_sse"
3679 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m#fxr,?f#xr,?r#fx,?x#fr,Y#fr")
3681 (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
3682 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3683 "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3685 switch (which_alternative)
3688 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3689 return "fstp%z0\t%y0";
3691 return "fst%z0\t%y0";
3698 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3699 (set_attr "mode" "SF,SF,SF,SF,DF")])
3701 (define_insn "*truncdfsf2_1_sse_nooverlap"
3702 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,&Y")
3704 (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
3705 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3706 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3708 switch (which_alternative)
3711 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3712 return "fstp%z0\t%y0";
3714 return "fst%z0\t%y0";
3721 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3722 (set_attr "mode" "SF,SF,SF,SF,DF")])
3724 (define_insn "*truncdfsf2_2"
3725 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,Y,!m")
3727 (match_operand:DF 1 "nonimmediate_operand" "Y,mY,f#Y")))]
3728 "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
3729 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3731 switch (which_alternative)
3735 return "cvtsd2ss\t{%1, %0|%0, %1}";
3737 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3738 return "fstp%z0\t%y0";
3740 return "fst%z0\t%y0";
3745 [(set_attr "type" "ssecvt,ssecvt,fmov")
3746 (set_attr "athlon_decode" "vector,double,*")
3747 (set_attr "mode" "SF,SF,SF")])
3749 (define_insn "*truncdfsf2_2_nooverlap"
3750 [(set (match_operand:SF 0 "nonimmediate_operand" "=&Y,!m")
3752 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
3753 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
3754 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3756 switch (which_alternative)
3761 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3762 return "fstp%z0\t%y0";
3764 return "fst%z0\t%y0";
3769 [(set_attr "type" "ssecvt,fmov")
3770 (set_attr "mode" "DF,SF")])
3772 (define_insn "*truncdfsf2_3"
3773 [(set (match_operand:SF 0 "memory_operand" "=m")
3775 (match_operand:DF 1 "register_operand" "f")))]
3778 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3779 return "fstp%z0\t%y0";
3781 return "fst%z0\t%y0";
3783 [(set_attr "type" "fmov")
3784 (set_attr "mode" "SF")])
3786 (define_insn "truncdfsf2_sse_only"
3787 [(set (match_operand:SF 0 "register_operand" "=Y,Y")
3789 (match_operand:DF 1 "nonimmediate_operand" "Y,mY")))]
3790 "!TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3791 "cvtsd2ss\t{%1, %0|%0, %1}"
3792 [(set_attr "type" "ssecvt")
3793 (set_attr "athlon_decode" "vector,double")
3794 (set_attr "mode" "SF")])
3796 (define_insn "*truncdfsf2_sse_only_nooverlap"
3797 [(set (match_operand:SF 0 "register_operand" "=&Y")
3799 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
3800 "!TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3802 [(set_attr "type" "ssecvt")
3803 (set_attr "mode" "DF")])
3806 [(set (match_operand:SF 0 "memory_operand" "")
3808 (match_operand:DF 1 "register_operand" "")))
3809 (clobber (match_operand:SF 2 "memory_operand" ""))]
3811 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3814 ; Avoid possible reformatting penalty on the destination by first
3817 [(set (match_operand:SF 0 "register_operand" "")
3819 (match_operand:DF 1 "nonimmediate_operand" "")))
3820 (clobber (match_operand 2 "" ""))]
3821 "TARGET_80387 && reload_completed
3822 && SSE_REG_P (operands[0])
3823 && !STACK_REG_P (operands[1])"
3827 if (!TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS)
3828 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
3831 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
3832 src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
3833 /* simplify_gen_subreg refuses to widen memory references. */
3834 if (GET_CODE (src) == SUBREG)
3835 alter_subreg (&src);
3836 if (reg_overlap_mentioned_p (operands[0], operands[1]))
3838 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
3839 emit_insn (gen_cvtsd2ss (dest, dest, src));
3845 [(set (match_operand:SF 0 "register_operand" "")
3847 (match_operand:DF 1 "nonimmediate_operand" "")))]
3848 "TARGET_80387 && reload_completed
3849 && SSE_REG_P (operands[0]) && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3853 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
3854 src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
3855 /* simplify_gen_subreg refuses to widen memory references. */
3856 if (GET_CODE (src) == SUBREG)
3857 alter_subreg (&src);
3858 if (reg_overlap_mentioned_p (operands[0], operands[1]))
3860 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
3861 emit_insn (gen_cvtsd2ss (dest, dest, src));
3866 [(set (match_operand:SF 0 "register_operand" "")
3868 (match_operand:DF 1 "fp_register_operand" "")))
3869 (clobber (match_operand:SF 2 "memory_operand" ""))]
3870 "TARGET_80387 && reload_completed"
3871 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3872 (set (match_dup 0) (match_dup 2))]
3875 (define_expand "truncxfsf2"
3876 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3878 (match_operand:XF 1 "register_operand" "")))
3879 (clobber (match_dup 2))])]
3882 if (flag_unsafe_math_optimizations)
3884 rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SFmode);
3885 emit_insn (gen_truncxfsf2_noop (reg, operands[1]));
3886 if (reg != operands[0])
3887 emit_move_insn (operands[0], reg);
3891 operands[2] = assign_386_stack_local (SFmode, 0);
3894 (define_insn "truncxfsf2_noop"
3895 [(set (match_operand:SF 0 "register_operand" "=f")
3896 (float_truncate:SF (match_operand:XF 1 "register_operand" "f")))]
3897 "TARGET_80387 && flag_unsafe_math_optimizations"
3899 return output_387_reg_move (insn, operands);
3901 [(set_attr "type" "fmov")
3902 (set_attr "mode" "SF")])
3904 (define_insn "*truncxfsf2_1"
3905 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3907 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3908 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3911 switch (which_alternative)
3914 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3915 return "fstp%z0\t%y0";
3917 return "fst%z0\t%y0";
3922 [(set_attr "type" "fmov,multi,multi,multi")
3923 (set_attr "mode" "SF")])
3925 (define_insn "*truncxfsf2_2"
3926 [(set (match_operand:SF 0 "memory_operand" "=m")
3928 (match_operand:XF 1 "register_operand" "f")))]
3931 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3932 return "fstp%z0\t%y0";
3934 return "fst%z0\t%y0";
3936 [(set_attr "type" "fmov")
3937 (set_attr "mode" "SF")])
3940 [(set (match_operand:SF 0 "memory_operand" "")
3942 (match_operand:XF 1 "register_operand" "")))
3943 (clobber (match_operand:SF 2 "memory_operand" ""))]
3945 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3949 [(set (match_operand:SF 0 "register_operand" "")
3951 (match_operand:XF 1 "register_operand" "")))
3952 (clobber (match_operand:SF 2 "memory_operand" ""))]
3953 "TARGET_80387 && reload_completed"
3954 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3955 (set (match_dup 0) (match_dup 2))]
3958 (define_expand "truncxfdf2"
3959 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
3961 (match_operand:XF 1 "register_operand" "")))
3962 (clobber (match_dup 2))])]
3965 if (flag_unsafe_math_optimizations)
3967 rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DFmode);
3968 emit_insn (gen_truncxfdf2_noop (reg, operands[1]));
3969 if (reg != operands[0])
3970 emit_move_insn (operands[0], reg);
3974 operands[2] = assign_386_stack_local (DFmode, 0);
3977 (define_insn "truncxfdf2_noop"
3978 [(set (match_operand:DF 0 "register_operand" "=f")
3979 (float_truncate:DF (match_operand:XF 1 "register_operand" "f")))]
3980 "TARGET_80387 && flag_unsafe_math_optimizations"
3982 return output_387_reg_move (insn, operands);
3984 [(set_attr "type" "fmov")
3985 (set_attr "mode" "DF")])
3987 (define_insn "*truncxfdf2_1"
3988 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
3990 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3991 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
3994 switch (which_alternative)
3997 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3998 return "fstp%z0\t%y0";
4000 return "fst%z0\t%y0";
4006 [(set_attr "type" "fmov,multi,multi,multi")
4007 (set_attr "mode" "DF")])
4009 (define_insn "*truncxfdf2_2"
4010 [(set (match_operand:DF 0 "memory_operand" "=m")
4012 (match_operand:XF 1 "register_operand" "f")))]
4015 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4016 return "fstp%z0\t%y0";
4018 return "fst%z0\t%y0";
4020 [(set_attr "type" "fmov")
4021 (set_attr "mode" "DF")])
4024 [(set (match_operand:DF 0 "memory_operand" "")
4026 (match_operand:XF 1 "register_operand" "")))
4027 (clobber (match_operand:DF 2 "memory_operand" ""))]
4029 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4033 [(set (match_operand:DF 0 "register_operand" "")
4035 (match_operand:XF 1 "register_operand" "")))
4036 (clobber (match_operand:DF 2 "memory_operand" ""))]
4037 "TARGET_80387 && reload_completed"
4038 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4039 (set (match_dup 0) (match_dup 2))]
4043 ;; %%% Break up all these bad boys.
4045 ;; Signed conversion to DImode.
4047 (define_expand "fix_truncxfdi2"
4048 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4049 (fix:DI (match_operand:XF 1 "register_operand" "")))
4050 (clobber (reg:CC FLAGS_REG))])]
4054 (define_expand "fix_truncdfdi2"
4055 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4056 (fix:DI (match_operand:DF 1 "register_operand" "")))
4057 (clobber (reg:CC FLAGS_REG))])]
4058 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
4060 if (TARGET_64BIT && TARGET_SSE2)
4062 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4063 emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
4064 if (out != operands[0])
4065 emit_move_insn (operands[0], out);
4070 (define_expand "fix_truncsfdi2"
4071 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4072 (fix:DI (match_operand:SF 1 "register_operand" "")))
4073 (clobber (reg:CC FLAGS_REG))])]
4074 "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
4076 if (TARGET_SSE && TARGET_64BIT)
4078 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4079 emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
4080 if (out != operands[0])
4081 emit_move_insn (operands[0], out);
4086 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4087 ;; of the machinery.
4088 (define_insn_and_split "*fix_truncdi_1"
4089 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4090 (fix:DI (match_operand 1 "register_operand" "f,f")))
4091 (clobber (reg:CC FLAGS_REG))]
4092 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4093 && !reload_completed && !reload_in_progress
4094 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4099 ix86_optimize_mode_switching = 1;
4100 operands[2] = assign_386_stack_local (HImode, 1);
4101 operands[3] = assign_386_stack_local (HImode, 2);
4102 if (memory_operand (operands[0], VOIDmode))
4103 emit_insn (gen_fix_truncdi_memory (operands[0], operands[1],
4104 operands[2], operands[3]));
4107 operands[4] = assign_386_stack_local (DImode, 0);
4108 emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1],
4109 operands[2], operands[3],
4114 [(set_attr "type" "fistp")
4115 (set_attr "i387_cw" "trunc")
4116 (set_attr "mode" "DI")])
4118 (define_insn "fix_truncdi_nomemory"
4119 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4120 (fix:DI (match_operand 1 "register_operand" "f,f")))
4121 (use (match_operand:HI 2 "memory_operand" "m,m"))
4122 (use (match_operand:HI 3 "memory_operand" "m,m"))
4123 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
4124 (clobber (match_scratch:DF 5 "=&1f,&1f"))]
4125 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4126 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4128 [(set_attr "type" "fistp")
4129 (set_attr "i387_cw" "trunc")
4130 (set_attr "mode" "DI")])
4132 (define_insn "fix_truncdi_memory"
4133 [(set (match_operand:DI 0 "memory_operand" "=m")
4134 (fix:DI (match_operand 1 "register_operand" "f")))
4135 (use (match_operand:HI 2 "memory_operand" "m"))
4136 (use (match_operand:HI 3 "memory_operand" "m"))
4137 (clobber (match_scratch:DF 4 "=&1f"))]
4138 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4139 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4140 "* return output_fix_trunc (insn, operands);"
4141 [(set_attr "type" "fistp")
4142 (set_attr "i387_cw" "trunc")
4143 (set_attr "mode" "DI")])
4146 [(set (match_operand:DI 0 "register_operand" "")
4147 (fix:DI (match_operand 1 "register_operand" "")))
4148 (use (match_operand:HI 2 "memory_operand" ""))
4149 (use (match_operand:HI 3 "memory_operand" ""))
4150 (clobber (match_operand:DI 4 "memory_operand" ""))
4151 (clobber (match_scratch 5 ""))]
4153 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
4156 (clobber (match_dup 5))])
4157 (set (match_dup 0) (match_dup 4))]
4161 [(set (match_operand:DI 0 "memory_operand" "")
4162 (fix:DI (match_operand 1 "register_operand" "")))
4163 (use (match_operand:HI 2 "memory_operand" ""))
4164 (use (match_operand:HI 3 "memory_operand" ""))
4165 (clobber (match_operand:DI 4 "memory_operand" ""))
4166 (clobber (match_scratch 5 ""))]
4168 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
4171 (clobber (match_dup 5))])]
4174 ;; When SSE available, it is always faster to use it!
4175 (define_insn "fix_truncsfdi_sse"
4176 [(set (match_operand:DI 0 "register_operand" "=r,r")
4177 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4178 "TARGET_64BIT && TARGET_SSE"
4179 "cvttss2si{q}\t{%1, %0|%0, %1}"
4180 [(set_attr "type" "sseicvt")
4181 (set_attr "mode" "SF")
4182 (set_attr "athlon_decode" "double,vector")])
4184 ;; Avoid vector decoded form of the instruction.
4186 [(match_scratch:SF 2 "x")
4187 (set (match_operand:DI 0 "register_operand" "")
4188 (fix:DI (match_operand:SF 1 "memory_operand" "")))]
4189 "TARGET_K8 && !optimize_size"
4190 [(set (match_dup 2) (match_dup 1))
4191 (set (match_dup 0) (fix:DI (match_dup 2)))]
4194 (define_insn "fix_truncdfdi_sse"
4195 [(set (match_operand:DI 0 "register_operand" "=r,r")
4196 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4197 "TARGET_64BIT && TARGET_SSE2"
4198 "cvttsd2si{q}\t{%1, %0|%0, %1}"
4199 [(set_attr "type" "sseicvt,sseicvt")
4200 (set_attr "mode" "DF")
4201 (set_attr "athlon_decode" "double,vector")])
4203 ;; Avoid vector decoded form of the instruction.
4205 [(match_scratch:DF 2 "Y")
4206 (set (match_operand:DI 0 "register_operand" "")
4207 (fix:DI (match_operand:DF 1 "memory_operand" "")))]
4208 "TARGET_K8 && !optimize_size"
4209 [(set (match_dup 2) (match_dup 1))
4210 (set (match_dup 0) (fix:DI (match_dup 2)))]
4213 ;; Signed conversion to SImode.
4215 (define_expand "fix_truncxfsi2"
4216 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4217 (fix:SI (match_operand:XF 1 "register_operand" "")))
4218 (clobber (reg:CC FLAGS_REG))])]
4222 (define_expand "fix_truncdfsi2"
4223 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4224 (fix:SI (match_operand:DF 1 "register_operand" "")))
4225 (clobber (reg:CC FLAGS_REG))])]
4226 "TARGET_80387 || TARGET_SSE2"
4230 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4231 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4232 if (out != operands[0])
4233 emit_move_insn (operands[0], out);
4238 (define_expand "fix_truncsfsi2"
4239 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4240 (fix:SI (match_operand:SF 1 "register_operand" "")))
4241 (clobber (reg:CC FLAGS_REG))])]
4242 "TARGET_80387 || TARGET_SSE"
4246 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4247 emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
4248 if (out != operands[0])
4249 emit_move_insn (operands[0], out);
4254 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4255 ;; of the machinery.
4256 (define_insn_and_split "*fix_truncsi_1"
4257 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4258 (fix:SI (match_operand 1 "register_operand" "f,f")))
4259 (clobber (reg:CC FLAGS_REG))]
4260 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4261 && !reload_completed && !reload_in_progress
4262 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4267 ix86_optimize_mode_switching = 1;
4268 operands[2] = assign_386_stack_local (HImode, 1);
4269 operands[3] = assign_386_stack_local (HImode, 2);
4270 if (memory_operand (operands[0], VOIDmode))
4271 emit_insn (gen_fix_truncsi_memory (operands[0], operands[1],
4272 operands[2], operands[3]));
4275 operands[4] = assign_386_stack_local (SImode, 0);
4276 emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1],
4277 operands[2], operands[3],
4282 [(set_attr "type" "fistp")
4283 (set_attr "i387_cw" "trunc")
4284 (set_attr "mode" "SI")])
4286 (define_insn "fix_truncsi_nomemory"
4287 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4288 (fix:SI (match_operand 1 "register_operand" "f,f")))
4289 (use (match_operand:HI 2 "memory_operand" "m,m"))
4290 (use (match_operand:HI 3 "memory_operand" "m,m"))
4291 (clobber (match_operand:SI 4 "memory_operand" "=m,m"))]
4292 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4293 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4295 [(set_attr "type" "fistp")
4296 (set_attr "i387_cw" "trunc")
4297 (set_attr "mode" "SI")])
4299 (define_insn "fix_truncsi_memory"
4300 [(set (match_operand:SI 0 "memory_operand" "=m")
4301 (fix:SI (match_operand 1 "register_operand" "f")))
4302 (use (match_operand:HI 2 "memory_operand" "m"))
4303 (use (match_operand:HI 3 "memory_operand" "m"))]
4304 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4305 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4306 "* return output_fix_trunc (insn, operands);"
4307 [(set_attr "type" "fistp")
4308 (set_attr "i387_cw" "trunc")
4309 (set_attr "mode" "SI")])
4311 ;; When SSE available, it is always faster to use it!
4312 (define_insn "fix_truncsfsi_sse"
4313 [(set (match_operand:SI 0 "register_operand" "=r,r")
4314 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4316 "cvttss2si\t{%1, %0|%0, %1}"
4317 [(set_attr "type" "sseicvt")
4318 (set_attr "mode" "DF")
4319 (set_attr "athlon_decode" "double,vector")])
4321 ;; Avoid vector decoded form of the instruction.
4323 [(match_scratch:SF 2 "x")
4324 (set (match_operand:SI 0 "register_operand" "")
4325 (fix:SI (match_operand:SF 1 "memory_operand" "")))]
4326 "TARGET_K8 && !optimize_size"
4327 [(set (match_dup 2) (match_dup 1))
4328 (set (match_dup 0) (fix:SI (match_dup 2)))]
4331 (define_insn "fix_truncdfsi_sse"
4332 [(set (match_operand:SI 0 "register_operand" "=r,r")
4333 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4335 "cvttsd2si\t{%1, %0|%0, %1}"
4336 [(set_attr "type" "sseicvt")
4337 (set_attr "mode" "DF")
4338 (set_attr "athlon_decode" "double,vector")])
4340 ;; Avoid vector decoded form of the instruction.
4342 [(match_scratch:DF 2 "Y")
4343 (set (match_operand:SI 0 "register_operand" "")
4344 (fix:SI (match_operand:DF 1 "memory_operand" "")))]
4345 "TARGET_K8 && !optimize_size"
4346 [(set (match_dup 2) (match_dup 1))
4347 (set (match_dup 0) (fix:SI (match_dup 2)))]
4351 [(set (match_operand:SI 0 "register_operand" "")
4352 (fix:SI (match_operand 1 "register_operand" "")))
4353 (use (match_operand:HI 2 "memory_operand" ""))
4354 (use (match_operand:HI 3 "memory_operand" ""))
4355 (clobber (match_operand:SI 4 "memory_operand" ""))]
4357 [(parallel [(set (match_dup 4) (fix:SI (match_dup 1)))
4359 (use (match_dup 3))])
4360 (set (match_dup 0) (match_dup 4))]
4364 [(set (match_operand:SI 0 "memory_operand" "")
4365 (fix:SI (match_operand 1 "register_operand" "")))
4366 (use (match_operand:HI 2 "memory_operand" ""))
4367 (use (match_operand:HI 3 "memory_operand" ""))
4368 (clobber (match_operand:SI 4 "memory_operand" ""))]
4370 [(parallel [(set (match_dup 0) (fix:SI (match_dup 1)))
4372 (use (match_dup 3))])]
4375 ;; Signed conversion to HImode.
4377 (define_expand "fix_truncxfhi2"
4378 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4379 (fix:HI (match_operand:XF 1 "register_operand" "")))
4380 (clobber (reg:CC FLAGS_REG))])]
4384 (define_expand "fix_truncdfhi2"
4385 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4386 (fix:HI (match_operand:DF 1 "register_operand" "")))
4387 (clobber (reg:CC FLAGS_REG))])]
4388 "TARGET_80387 && !TARGET_SSE2"
4391 (define_expand "fix_truncsfhi2"
4392 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4393 (fix:HI (match_operand:SF 1 "register_operand" "")))
4394 (clobber (reg:CC FLAGS_REG))])]
4395 "TARGET_80387 && !TARGET_SSE"
4398 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4399 ;; of the machinery.
4400 (define_insn_and_split "*fix_trunchi_1"
4401 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4402 (fix:HI (match_operand 1 "register_operand" "f,f")))
4403 (clobber (reg:CC FLAGS_REG))]
4404 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4405 && !reload_completed && !reload_in_progress
4406 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4411 ix86_optimize_mode_switching = 1;
4412 operands[2] = assign_386_stack_local (HImode, 1);
4413 operands[3] = assign_386_stack_local (HImode, 2);
4414 if (memory_operand (operands[0], VOIDmode))
4415 emit_insn (gen_fix_trunchi_memory (operands[0], operands[1],
4416 operands[2], operands[3]));
4419 operands[4] = assign_386_stack_local (HImode, 0);
4420 emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1],
4421 operands[2], operands[3],
4426 [(set_attr "type" "fistp")
4427 (set_attr "i387_cw" "trunc")
4428 (set_attr "mode" "HI")])
4430 (define_insn "fix_trunchi_nomemory"
4431 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4432 (fix:HI (match_operand 1 "register_operand" "f,f")))
4433 (use (match_operand:HI 2 "memory_operand" "m,m"))
4434 (use (match_operand:HI 3 "memory_operand" "m,m"))
4435 (clobber (match_operand:HI 4 "memory_operand" "=m,m"))]
4436 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4437 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4439 [(set_attr "type" "fistp")
4440 (set_attr "i387_cw" "trunc")
4441 (set_attr "mode" "HI")])
4443 (define_insn "fix_trunchi_memory"
4444 [(set (match_operand:HI 0 "memory_operand" "=m")
4445 (fix:HI (match_operand 1 "register_operand" "f")))
4446 (use (match_operand:HI 2 "memory_operand" "m"))
4447 (use (match_operand:HI 3 "memory_operand" "m"))]
4448 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4449 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4450 "* return output_fix_trunc (insn, operands);"
4451 [(set_attr "type" "fistp")
4452 (set_attr "i387_cw" "trunc")
4453 (set_attr "mode" "HI")])
4456 [(set (match_operand:HI 0 "memory_operand" "")
4457 (fix:HI (match_operand 1 "register_operand" "")))
4458 (use (match_operand:HI 2 "memory_operand" ""))
4459 (use (match_operand:HI 3 "memory_operand" ""))
4460 (clobber (match_operand:HI 4 "memory_operand" ""))]
4462 [(parallel [(set (match_dup 0) (fix:HI (match_dup 1)))
4464 (use (match_dup 3))])]
4468 [(set (match_operand:HI 0 "register_operand" "")
4469 (fix:HI (match_operand 1 "register_operand" "")))
4470 (use (match_operand:HI 2 "memory_operand" ""))
4471 (use (match_operand:HI 3 "memory_operand" ""))
4472 (clobber (match_operand:HI 4 "memory_operand" ""))]
4474 [(parallel [(set (match_dup 4) (fix:HI (match_dup 1)))
4477 (clobber (match_dup 4))])
4478 (set (match_dup 0) (match_dup 4))]
4481 (define_insn "x86_fnstcw_1"
4482 [(set (match_operand:HI 0 "memory_operand" "=m")
4483 (unspec:HI [(reg:HI FPSR_REG)] UNSPEC_FSTCW))]
4486 [(set_attr "length" "2")
4487 (set_attr "mode" "HI")
4488 (set_attr "unit" "i387")])
4490 (define_insn "x86_fldcw_1"
4491 [(set (reg:HI FPSR_REG)
4492 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
4495 [(set_attr "length" "2")
4496 (set_attr "mode" "HI")
4497 (set_attr "unit" "i387")
4498 (set_attr "athlon_decode" "vector")])
4500 ;; Conversion between fixed point and floating point.
4502 ;; Even though we only accept memory inputs, the backend _really_
4503 ;; wants to be able to do this between registers.
4505 (define_expand "floathisf2"
4506 [(set (match_operand:SF 0 "register_operand" "")
4507 (float:SF (match_operand:HI 1 "nonimmediate_operand" "")))]
4508 "TARGET_SSE || TARGET_80387"
4510 if (TARGET_SSE && TARGET_SSE_MATH)
4512 emit_insn (gen_floatsisf2 (operands[0],
4513 convert_to_mode (SImode, operands[1], 0)));
4518 (define_insn "*floathisf2_1"
4519 [(set (match_operand:SF 0 "register_operand" "=f,f")
4520 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4521 "TARGET_80387 && (!TARGET_SSE || !TARGET_SSE_MATH)"
4525 [(set_attr "type" "fmov,multi")
4526 (set_attr "mode" "SF")
4527 (set_attr "fp_int_src" "true")])
4529 (define_expand "floatsisf2"
4530 [(set (match_operand:SF 0 "register_operand" "")
4531 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4532 "TARGET_SSE || TARGET_80387"
4535 (define_insn "*floatsisf2_i387"
4536 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4537 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4538 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4542 cvtsi2ss\t{%1, %0|%0, %1}
4543 cvtsi2ss\t{%1, %0|%0, %1}"
4544 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4545 (set_attr "mode" "SF")
4546 (set_attr "athlon_decode" "*,*,vector,double")
4547 (set_attr "fp_int_src" "true")])
4549 (define_insn "*floatsisf2_sse"
4550 [(set (match_operand:SF 0 "register_operand" "=x,x")
4551 (float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4553 "cvtsi2ss\t{%1, %0|%0, %1}"
4554 [(set_attr "type" "sseicvt")
4555 (set_attr "mode" "SF")
4556 (set_attr "athlon_decode" "vector,double")
4557 (set_attr "fp_int_src" "true")])
4559 ; Avoid possible reformatting penalty on the destination by first
4562 [(set (match_operand:SF 0 "register_operand" "")
4563 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4564 "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
4565 && SSE_REG_P (operands[0])"
4569 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4570 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4571 emit_insn (gen_cvtsi2ss (dest, dest, operands[1]));
4575 (define_expand "floatdisf2"
4576 [(set (match_operand:SF 0 "register_operand" "")
4577 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4578 "(TARGET_64BIT && TARGET_SSE) || TARGET_80387"
4581 (define_insn "*floatdisf2_i387_only"
4582 [(set (match_operand:SF 0 "register_operand" "=f,?f")
4583 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4584 "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
4588 [(set_attr "type" "fmov,multi")
4589 (set_attr "mode" "SF")
4590 (set_attr "fp_int_src" "true")])
4592 (define_insn "*floatdisf2_i387"
4593 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4594 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4595 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4599 cvtsi2ss{q}\t{%1, %0|%0, %1}
4600 cvtsi2ss{q}\t{%1, %0|%0, %1}"
4601 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4602 (set_attr "mode" "SF")
4603 (set_attr "athlon_decode" "*,*,vector,double")
4604 (set_attr "fp_int_src" "true")])
4606 (define_insn "*floatdisf2_sse"
4607 [(set (match_operand:SF 0 "register_operand" "=x,x")
4608 (float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4609 "TARGET_64BIT && TARGET_SSE"
4610 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
4611 [(set_attr "type" "sseicvt")
4612 (set_attr "mode" "SF")
4613 (set_attr "athlon_decode" "vector,double")
4614 (set_attr "fp_int_src" "true")])
4616 ; Avoid possible reformatting penalty on the destination by first
4619 [(set (match_operand:SF 0 "register_operand" "")
4620 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4621 "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
4622 && SSE_REG_P (operands[0])"
4626 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4627 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4628 emit_insn (gen_cvtsi2ssq (dest, dest, operands[1]));
4632 (define_expand "floathidf2"
4633 [(set (match_operand:DF 0 "register_operand" "")
4634 (float:DF (match_operand:HI 1 "nonimmediate_operand" "")))]
4635 "TARGET_SSE2 || TARGET_80387"
4637 if (TARGET_SSE && TARGET_SSE_MATH)
4639 emit_insn (gen_floatsidf2 (operands[0],
4640 convert_to_mode (SImode, operands[1], 0)));
4645 (define_insn "*floathidf2_1"
4646 [(set (match_operand:DF 0 "register_operand" "=f,f")
4647 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4648 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
4652 [(set_attr "type" "fmov,multi")
4653 (set_attr "mode" "DF")
4654 (set_attr "fp_int_src" "true")])
4656 (define_expand "floatsidf2"
4657 [(set (match_operand:DF 0 "register_operand" "")
4658 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
4659 "TARGET_80387 || TARGET_SSE2"
4662 (define_insn "*floatsidf2_i387"
4663 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
4664 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4665 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4669 cvtsi2sd\t{%1, %0|%0, %1}
4670 cvtsi2sd\t{%1, %0|%0, %1}"
4671 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4672 (set_attr "mode" "DF")
4673 (set_attr "athlon_decode" "*,*,double,direct")
4674 (set_attr "fp_int_src" "true")])
4676 (define_insn "*floatsidf2_sse"
4677 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
4678 (float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4680 "cvtsi2sd\t{%1, %0|%0, %1}"
4681 [(set_attr "type" "sseicvt")
4682 (set_attr "mode" "DF")
4683 (set_attr "athlon_decode" "double,direct")
4684 (set_attr "fp_int_src" "true")])
4686 (define_expand "floatdidf2"
4687 [(set (match_operand:DF 0 "register_operand" "")
4688 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
4689 "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387"
4692 (define_insn "*floatdidf2_i387_only"
4693 [(set (match_operand:DF 0 "register_operand" "=f,?f")
4694 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4695 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
4699 [(set_attr "type" "fmov,multi")
4700 (set_attr "mode" "DF")
4701 (set_attr "fp_int_src" "true")])
4703 (define_insn "*floatdidf2_i387"
4704 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
4705 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4706 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4710 cvtsi2sd{q}\t{%1, %0|%0, %1}
4711 cvtsi2sd{q}\t{%1, %0|%0, %1}"
4712 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4713 (set_attr "mode" "DF")
4714 (set_attr "athlon_decode" "*,*,double,direct")
4715 (set_attr "fp_int_src" "true")])
4717 (define_insn "*floatdidf2_sse"
4718 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
4719 (float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4721 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
4722 [(set_attr "type" "sseicvt")
4723 (set_attr "mode" "DF")
4724 (set_attr "athlon_decode" "double,direct")
4725 (set_attr "fp_int_src" "true")])
4727 (define_insn "floathixf2"
4728 [(set (match_operand:XF 0 "register_operand" "=f,f")
4729 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4734 [(set_attr "type" "fmov,multi")
4735 (set_attr "mode" "XF")
4736 (set_attr "fp_int_src" "true")])
4738 (define_insn "floatsixf2"
4739 [(set (match_operand:XF 0 "register_operand" "=f,f")
4740 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
4745 [(set_attr "type" "fmov,multi")
4746 (set_attr "mode" "XF")
4747 (set_attr "fp_int_src" "true")])
4749 (define_insn "floatdixf2"
4750 [(set (match_operand:XF 0 "register_operand" "=f,f")
4751 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4756 [(set_attr "type" "fmov,multi")
4757 (set_attr "mode" "XF")
4758 (set_attr "fp_int_src" "true")])
4760 ;; %%% Kill these when reload knows how to do it.
4762 [(set (match_operand 0 "fp_register_operand" "")
4763 (float (match_operand 1 "register_operand" "")))]
4764 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
4767 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
4768 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
4769 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
4770 ix86_free_from_memory (GET_MODE (operands[1]));
4774 (define_expand "floatunssisf2"
4775 [(use (match_operand:SF 0 "register_operand" ""))
4776 (use (match_operand:SI 1 "register_operand" ""))]
4777 "TARGET_SSE && TARGET_SSE_MATH && !TARGET_64BIT"
4778 "x86_emit_floatuns (operands); DONE;")
4780 (define_expand "floatunsdisf2"
4781 [(use (match_operand:SF 0 "register_operand" ""))
4782 (use (match_operand:DI 1 "register_operand" ""))]
4783 "TARGET_SSE && TARGET_SSE_MATH && TARGET_64BIT"
4784 "x86_emit_floatuns (operands); DONE;")
4786 (define_expand "floatunsdidf2"
4787 [(use (match_operand:DF 0 "register_operand" ""))
4788 (use (match_operand:DI 1 "register_operand" ""))]
4789 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_64BIT"
4790 "x86_emit_floatuns (operands); DONE;")
4792 ;; SSE extract/set expanders
4794 (define_expand "vec_setv2df"
4795 [(match_operand:V2DF 0 "register_operand" "")
4796 (match_operand:DF 1 "register_operand" "")
4797 (match_operand 2 "const_int_operand" "")]
4800 switch (INTVAL (operands[2]))
4803 emit_insn (gen_sse2_movsd (operands[0], operands[0],
4804 simplify_gen_subreg (V2DFmode, operands[1],
4809 rtx op1 = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
4811 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], op1));
4820 (define_expand "vec_extractv2df"
4821 [(match_operand:DF 0 "register_operand" "")
4822 (match_operand:V2DF 1 "register_operand" "")
4823 (match_operand 2 "const_int_operand" "")]
4826 switch (INTVAL (operands[2]))
4829 emit_move_insn (operands[0], gen_lowpart (DFmode, operands[1]));
4833 rtx dest = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
4835 emit_insn (gen_sse2_unpckhpd (dest, operands[1], operands[1]));
4844 (define_expand "vec_initv2df"
4845 [(match_operand:V2DF 0 "register_operand" "")
4846 (match_operand 1 "" "")]
4849 ix86_expand_vector_init (operands[0], operands[1]);
4853 (define_expand "vec_setv4sf"
4854 [(match_operand:V4SF 0 "register_operand" "")
4855 (match_operand:SF 1 "register_operand" "")
4856 (match_operand 2 "const_int_operand" "")]
4859 switch (INTVAL (operands[2]))
4862 emit_insn (gen_sse_movss (operands[0], operands[0],
4863 simplify_gen_subreg (V4SFmode, operands[1],
4868 rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4869 rtx tmp = gen_reg_rtx (V4SFmode);
4871 emit_move_insn (tmp, operands[0]);
4872 emit_insn (gen_sse_unpcklps (operands[0], operands[0], operands[0]));
4873 emit_insn (gen_sse_movss (operands[0], operands[0], op1));
4874 emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
4875 GEN_INT (1 + (0<<2) + (2<<4) + (3<<6))));
4880 rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4881 rtx tmp = gen_reg_rtx (V4SFmode);
4883 emit_move_insn (tmp, operands[0]);
4884 emit_insn (gen_sse_movss (tmp, tmp, op1));
4885 emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
4886 GEN_INT (0 + (1<<2) + (0<<4) + (3<<6))));
4891 rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4892 rtx tmp = gen_reg_rtx (V4SFmode);
4894 emit_move_insn (tmp, operands[0]);
4895 emit_insn (gen_sse_movss (tmp, tmp, op1));
4896 emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
4897 GEN_INT (0 + (1<<2) + (2<<4) + (0<<6))));
4906 (define_expand "vec_extractv4sf"
4907 [(match_operand:SF 0 "register_operand" "")
4908 (match_operand:V4SF 1 "register_operand" "")
4909 (match_operand 2 "const_int_operand" "")]
4912 switch (INTVAL (operands[2]))
4915 emit_move_insn (operands[0], gen_lowpart (SFmode, operands[1]));
4919 rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4920 rtx tmp = gen_reg_rtx (V4SFmode);
4922 emit_move_insn (tmp, operands[1]);
4923 emit_insn (gen_sse_shufps (op0, tmp, tmp,
4929 rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4930 rtx tmp = gen_reg_rtx (V4SFmode);
4932 emit_move_insn (tmp, operands[1]);
4933 emit_insn (gen_sse_unpckhps (op0, tmp, tmp));
4938 rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4939 rtx tmp = gen_reg_rtx (V4SFmode);
4941 emit_move_insn (tmp, operands[1]);
4942 emit_insn (gen_sse_shufps (op0, tmp, tmp,
4952 (define_expand "vec_initv4sf"
4953 [(match_operand:V4SF 0 "register_operand" "")
4954 (match_operand 1 "" "")]
4957 ix86_expand_vector_init (operands[0], operands[1]);
4963 ;; %%% splits for addsidi3
4964 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
4965 ; (plus:DI (match_operand:DI 1 "general_operand" "")
4966 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
4968 (define_expand "adddi3"
4969 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4970 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4971 (match_operand:DI 2 "x86_64_general_operand" "")))
4972 (clobber (reg:CC FLAGS_REG))]
4974 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
4976 (define_insn "*adddi3_1"
4977 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
4978 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4979 (match_operand:DI 2 "general_operand" "roiF,riF")))
4980 (clobber (reg:CC FLAGS_REG))]
4981 "!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4985 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4986 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4987 (match_operand:DI 2 "general_operand" "")))
4988 (clobber (reg:CC FLAGS_REG))]
4989 "!TARGET_64BIT && reload_completed"
4990 [(parallel [(set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 1) (match_dup 2)]
4992 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
4993 (parallel [(set (match_dup 3)
4994 (plus:SI (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
4997 (clobber (reg:CC FLAGS_REG))])]
4998 "split_di (operands+0, 1, operands+0, operands+3);
4999 split_di (operands+1, 1, operands+1, operands+4);
5000 split_di (operands+2, 1, operands+2, operands+5);")
5002 (define_insn "adddi3_carry_rex64"
5003 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5004 (plus:DI (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
5005 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
5006 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
5007 (clobber (reg:CC FLAGS_REG))]
5008 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5009 "adc{q}\t{%2, %0|%0, %2}"
5010 [(set_attr "type" "alu")
5011 (set_attr "pent_pair" "pu")
5012 (set_attr "mode" "DI")])
5014 (define_insn "*adddi3_cc_rex64"
5015 [(set (reg:CC FLAGS_REG)
5016 (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
5017 (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
5019 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5020 (plus:DI (match_dup 1) (match_dup 2)))]
5021 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5022 "add{q}\t{%2, %0|%0, %2}"
5023 [(set_attr "type" "alu")
5024 (set_attr "mode" "DI")])
5026 (define_insn "addqi3_carry"
5027 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5028 (plus:QI (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
5029 (match_operand:QI 1 "nonimmediate_operand" "%0,0"))
5030 (match_operand:QI 2 "general_operand" "qi,qm")))
5031 (clobber (reg:CC FLAGS_REG))]
5032 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5033 "adc{b}\t{%2, %0|%0, %2}"
5034 [(set_attr "type" "alu")
5035 (set_attr "pent_pair" "pu")
5036 (set_attr "mode" "QI")])
5038 (define_insn "addhi3_carry"
5039 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5040 (plus:HI (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
5041 (match_operand:HI 1 "nonimmediate_operand" "%0,0"))
5042 (match_operand:HI 2 "general_operand" "ri,rm")))
5043 (clobber (reg:CC FLAGS_REG))]
5044 "ix86_binary_operator_ok (PLUS, HImode, operands)"
5045 "adc{w}\t{%2, %0|%0, %2}"
5046 [(set_attr "type" "alu")
5047 (set_attr "pent_pair" "pu")
5048 (set_attr "mode" "HI")])
5050 (define_insn "addsi3_carry"
5051 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5052 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5053 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
5054 (match_operand:SI 2 "general_operand" "ri,rm")))
5055 (clobber (reg:CC FLAGS_REG))]
5056 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5057 "adc{l}\t{%2, %0|%0, %2}"
5058 [(set_attr "type" "alu")
5059 (set_attr "pent_pair" "pu")
5060 (set_attr "mode" "SI")])
5062 (define_insn "*addsi3_carry_zext"
5063 [(set (match_operand:DI 0 "register_operand" "=r")
5065 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5066 (match_operand:SI 1 "nonimmediate_operand" "%0"))
5067 (match_operand:SI 2 "general_operand" "rim"))))
5068 (clobber (reg:CC FLAGS_REG))]
5069 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5070 "adc{l}\t{%2, %k0|%k0, %2}"
5071 [(set_attr "type" "alu")
5072 (set_attr "pent_pair" "pu")
5073 (set_attr "mode" "SI")])
5075 (define_insn "*addsi3_cc"
5076 [(set (reg:CC FLAGS_REG)
5077 (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5078 (match_operand:SI 2 "general_operand" "ri,rm")]
5080 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5081 (plus:SI (match_dup 1) (match_dup 2)))]
5082 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5083 "add{l}\t{%2, %0|%0, %2}"
5084 [(set_attr "type" "alu")
5085 (set_attr "mode" "SI")])
5087 (define_insn "addqi3_cc"
5088 [(set (reg:CC FLAGS_REG)
5089 (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5090 (match_operand:QI 2 "general_operand" "qi,qm")]
5092 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5093 (plus:QI (match_dup 1) (match_dup 2)))]
5094 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5095 "add{b}\t{%2, %0|%0, %2}"
5096 [(set_attr "type" "alu")
5097 (set_attr "mode" "QI")])
5099 (define_expand "addsi3"
5100 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5101 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5102 (match_operand:SI 2 "general_operand" "")))
5103 (clobber (reg:CC FLAGS_REG))])]
5105 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
5107 (define_insn "*lea_1"
5108 [(set (match_operand:SI 0 "register_operand" "=r")
5109 (match_operand:SI 1 "no_seg_address_operand" "p"))]
5111 "lea{l}\t{%a1, %0|%0, %a1}"
5112 [(set_attr "type" "lea")
5113 (set_attr "mode" "SI")])
5115 (define_insn "*lea_1_rex64"
5116 [(set (match_operand:SI 0 "register_operand" "=r")
5117 (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0))]
5119 "lea{l}\t{%a1, %0|%0, %a1}"
5120 [(set_attr "type" "lea")
5121 (set_attr "mode" "SI")])
5123 (define_insn "*lea_1_zext"
5124 [(set (match_operand:DI 0 "register_operand" "=r")
5126 (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0)))]
5128 "lea{l}\t{%a1, %k0|%k0, %a1}"
5129 [(set_attr "type" "lea")
5130 (set_attr "mode" "SI")])
5132 (define_insn "*lea_2_rex64"
5133 [(set (match_operand:DI 0 "register_operand" "=r")
5134 (match_operand:DI 1 "no_seg_address_operand" "p"))]
5136 "lea{q}\t{%a1, %0|%0, %a1}"
5137 [(set_attr "type" "lea")
5138 (set_attr "mode" "DI")])
5140 ;; The lea patterns for non-Pmodes needs to be matched by several
5141 ;; insns converted to real lea by splitters.
5143 (define_insn_and_split "*lea_general_1"
5144 [(set (match_operand 0 "register_operand" "=r")
5145 (plus (plus (match_operand 1 "index_register_operand" "r")
5146 (match_operand 2 "register_operand" "r"))
5147 (match_operand 3 "immediate_operand" "i")))]
5148 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5149 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5150 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5151 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5152 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5153 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5154 || GET_MODE (operands[3]) == VOIDmode)"
5156 "&& reload_completed"
5160 operands[0] = gen_lowpart (SImode, operands[0]);
5161 operands[1] = gen_lowpart (Pmode, operands[1]);
5162 operands[2] = gen_lowpart (Pmode, operands[2]);
5163 operands[3] = gen_lowpart (Pmode, operands[3]);
5164 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
5166 if (Pmode != SImode)
5167 pat = gen_rtx_SUBREG (SImode, pat, 0);
5168 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5171 [(set_attr "type" "lea")
5172 (set_attr "mode" "SI")])
5174 (define_insn_and_split "*lea_general_1_zext"
5175 [(set (match_operand:DI 0 "register_operand" "=r")
5177 (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "r")
5178 (match_operand:SI 2 "register_operand" "r"))
5179 (match_operand:SI 3 "immediate_operand" "i"))))]
5182 "&& reload_completed"
5184 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
5186 (match_dup 3)) 0)))]
5188 operands[1] = gen_lowpart (Pmode, operands[1]);
5189 operands[2] = gen_lowpart (Pmode, operands[2]);
5190 operands[3] = gen_lowpart (Pmode, operands[3]);
5192 [(set_attr "type" "lea")
5193 (set_attr "mode" "SI")])
5195 (define_insn_and_split "*lea_general_2"
5196 [(set (match_operand 0 "register_operand" "=r")
5197 (plus (mult (match_operand 1 "index_register_operand" "r")
5198 (match_operand 2 "const248_operand" "i"))
5199 (match_operand 3 "nonmemory_operand" "ri")))]
5200 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5201 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5202 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5203 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5204 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5205 || GET_MODE (operands[3]) == VOIDmode)"
5207 "&& reload_completed"
5211 operands[0] = gen_lowpart (SImode, operands[0]);
5212 operands[1] = gen_lowpart (Pmode, operands[1]);
5213 operands[3] = gen_lowpart (Pmode, operands[3]);
5214 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5216 if (Pmode != SImode)
5217 pat = gen_rtx_SUBREG (SImode, pat, 0);
5218 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5221 [(set_attr "type" "lea")
5222 (set_attr "mode" "SI")])
5224 (define_insn_and_split "*lea_general_2_zext"
5225 [(set (match_operand:DI 0 "register_operand" "=r")
5227 (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
5228 (match_operand:SI 2 "const248_operand" "n"))
5229 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
5232 "&& reload_completed"
5234 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
5236 (match_dup 3)) 0)))]
5238 operands[1] = gen_lowpart (Pmode, operands[1]);
5239 operands[3] = gen_lowpart (Pmode, operands[3]);
5241 [(set_attr "type" "lea")
5242 (set_attr "mode" "SI")])
5244 (define_insn_and_split "*lea_general_3"
5245 [(set (match_operand 0 "register_operand" "=r")
5246 (plus (plus (mult (match_operand 1 "index_register_operand" "r")
5247 (match_operand 2 "const248_operand" "i"))
5248 (match_operand 3 "register_operand" "r"))
5249 (match_operand 4 "immediate_operand" "i")))]
5250 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5251 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5252 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5253 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5254 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5256 "&& reload_completed"
5260 operands[0] = gen_lowpart (SImode, operands[0]);
5261 operands[1] = gen_lowpart (Pmode, operands[1]);
5262 operands[3] = gen_lowpart (Pmode, operands[3]);
5263 operands[4] = gen_lowpart (Pmode, operands[4]);
5264 pat = gen_rtx_PLUS (Pmode,
5265 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5269 if (Pmode != SImode)
5270 pat = gen_rtx_SUBREG (SImode, pat, 0);
5271 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5274 [(set_attr "type" "lea")
5275 (set_attr "mode" "SI")])
5277 (define_insn_and_split "*lea_general_3_zext"
5278 [(set (match_operand:DI 0 "register_operand" "=r")
5280 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
5281 (match_operand:SI 2 "const248_operand" "n"))
5282 (match_operand:SI 3 "register_operand" "r"))
5283 (match_operand:SI 4 "immediate_operand" "i"))))]
5286 "&& reload_completed"
5288 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
5291 (match_dup 4)) 0)))]
5293 operands[1] = gen_lowpart (Pmode, operands[1]);
5294 operands[3] = gen_lowpart (Pmode, operands[3]);
5295 operands[4] = gen_lowpart (Pmode, operands[4]);
5297 [(set_attr "type" "lea")
5298 (set_attr "mode" "SI")])
5300 (define_insn "*adddi_1_rex64"
5301 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5302 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5303 (match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
5304 (clobber (reg:CC FLAGS_REG))]
5305 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5307 switch (get_attr_type (insn))
5310 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5311 return "lea{q}\t{%a2, %0|%0, %a2}";
5314 if (! rtx_equal_p (operands[0], operands[1]))
5316 if (operands[2] == const1_rtx)
5317 return "inc{q}\t%0";
5318 else if (operands[2] == constm1_rtx)
5319 return "dec{q}\t%0";
5324 if (! rtx_equal_p (operands[0], operands[1]))
5327 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5328 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5329 if (GET_CODE (operands[2]) == CONST_INT
5330 /* Avoid overflows. */
5331 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5332 && (INTVAL (operands[2]) == 128
5333 || (INTVAL (operands[2]) < 0
5334 && INTVAL (operands[2]) != -128)))
5336 operands[2] = GEN_INT (-INTVAL (operands[2]));
5337 return "sub{q}\t{%2, %0|%0, %2}";
5339 return "add{q}\t{%2, %0|%0, %2}";
5343 (cond [(eq_attr "alternative" "2")
5344 (const_string "lea")
5345 ; Current assemblers are broken and do not allow @GOTOFF in
5346 ; ought but a memory context.
5347 (match_operand:DI 2 "pic_symbolic_operand" "")
5348 (const_string "lea")
5349 (match_operand:DI 2 "incdec_operand" "")
5350 (const_string "incdec")
5352 (const_string "alu")))
5353 (set_attr "mode" "DI")])
5355 ;; Convert lea to the lea pattern to avoid flags dependency.
5357 [(set (match_operand:DI 0 "register_operand" "")
5358 (plus:DI (match_operand:DI 1 "register_operand" "")
5359 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5360 (clobber (reg:CC FLAGS_REG))]
5361 "TARGET_64BIT && reload_completed
5362 && true_regnum (operands[0]) != true_regnum (operands[1])"
5364 (plus:DI (match_dup 1)
5368 (define_insn "*adddi_2_rex64"
5371 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5372 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5374 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5375 (plus:DI (match_dup 1) (match_dup 2)))]
5376 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5377 && ix86_binary_operator_ok (PLUS, DImode, operands)
5378 /* Current assemblers are broken and do not allow @GOTOFF in
5379 ought but a memory context. */
5380 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5382 switch (get_attr_type (insn))
5385 if (! rtx_equal_p (operands[0], operands[1]))
5387 if (operands[2] == const1_rtx)
5388 return "inc{q}\t%0";
5389 else if (operands[2] == constm1_rtx)
5390 return "dec{q}\t%0";
5395 if (! rtx_equal_p (operands[0], operands[1]))
5397 /* ???? We ought to handle there the 32bit case too
5398 - do we need new constraint? */
5399 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5400 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5401 if (GET_CODE (operands[2]) == CONST_INT
5402 /* Avoid overflows. */
5403 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5404 && (INTVAL (operands[2]) == 128
5405 || (INTVAL (operands[2]) < 0
5406 && INTVAL (operands[2]) != -128)))
5408 operands[2] = GEN_INT (-INTVAL (operands[2]));
5409 return "sub{q}\t{%2, %0|%0, %2}";
5411 return "add{q}\t{%2, %0|%0, %2}";
5415 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5416 (const_string "incdec")
5417 (const_string "alu")))
5418 (set_attr "mode" "DI")])
5420 (define_insn "*adddi_3_rex64"
5422 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5423 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5424 (clobber (match_scratch:DI 0 "=r"))]
5426 && ix86_match_ccmode (insn, CCZmode)
5427 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5428 /* Current assemblers are broken and do not allow @GOTOFF in
5429 ought but a memory context. */
5430 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5432 switch (get_attr_type (insn))
5435 if (! rtx_equal_p (operands[0], operands[1]))
5437 if (operands[2] == const1_rtx)
5438 return "inc{q}\t%0";
5439 else if (operands[2] == constm1_rtx)
5440 return "dec{q}\t%0";
5445 if (! rtx_equal_p (operands[0], operands[1]))
5447 /* ???? We ought to handle there the 32bit case too
5448 - do we need new constraint? */
5449 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5450 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5451 if (GET_CODE (operands[2]) == CONST_INT
5452 /* Avoid overflows. */
5453 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5454 && (INTVAL (operands[2]) == 128
5455 || (INTVAL (operands[2]) < 0
5456 && INTVAL (operands[2]) != -128)))
5458 operands[2] = GEN_INT (-INTVAL (operands[2]));
5459 return "sub{q}\t{%2, %0|%0, %2}";
5461 return "add{q}\t{%2, %0|%0, %2}";
5465 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5466 (const_string "incdec")
5467 (const_string "alu")))
5468 (set_attr "mode" "DI")])
5470 ; For comparisons against 1, -1 and 128, we may generate better code
5471 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5472 ; is matched then. We can't accept general immediate, because for
5473 ; case of overflows, the result is messed up.
5474 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5476 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5477 ; only for comparisons not depending on it.
5478 (define_insn "*adddi_4_rex64"
5480 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5481 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5482 (clobber (match_scratch:DI 0 "=rm"))]
5484 && ix86_match_ccmode (insn, CCGCmode)"
5486 switch (get_attr_type (insn))
5489 if (operands[2] == constm1_rtx)
5490 return "inc{q}\t%0";
5491 else if (operands[2] == const1_rtx)
5492 return "dec{q}\t%0";
5497 if (! rtx_equal_p (operands[0], operands[1]))
5499 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5500 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5501 if ((INTVAL (operands[2]) == -128
5502 || (INTVAL (operands[2]) > 0
5503 && INTVAL (operands[2]) != 128))
5504 /* Avoid overflows. */
5505 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
5506 return "sub{q}\t{%2, %0|%0, %2}";
5507 operands[2] = GEN_INT (-INTVAL (operands[2]));
5508 return "add{q}\t{%2, %0|%0, %2}";
5512 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5513 (const_string "incdec")
5514 (const_string "alu")))
5515 (set_attr "mode" "DI")])
5517 (define_insn "*adddi_5_rex64"
5520 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5521 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5523 (clobber (match_scratch:DI 0 "=r"))]
5525 && ix86_match_ccmode (insn, CCGOCmode)
5526 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5527 /* Current assemblers are broken and do not allow @GOTOFF in
5528 ought but a memory context. */
5529 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5531 switch (get_attr_type (insn))
5534 if (! rtx_equal_p (operands[0], operands[1]))
5536 if (operands[2] == const1_rtx)
5537 return "inc{q}\t%0";
5538 else if (operands[2] == constm1_rtx)
5539 return "dec{q}\t%0";
5544 if (! rtx_equal_p (operands[0], operands[1]))
5546 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5547 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5548 if (GET_CODE (operands[2]) == CONST_INT
5549 /* Avoid overflows. */
5550 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5551 && (INTVAL (operands[2]) == 128
5552 || (INTVAL (operands[2]) < 0
5553 && INTVAL (operands[2]) != -128)))
5555 operands[2] = GEN_INT (-INTVAL (operands[2]));
5556 return "sub{q}\t{%2, %0|%0, %2}";
5558 return "add{q}\t{%2, %0|%0, %2}";
5562 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5563 (const_string "incdec")
5564 (const_string "alu")))
5565 (set_attr "mode" "DI")])
5568 (define_insn "*addsi_1"
5569 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5570 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5571 (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
5572 (clobber (reg:CC FLAGS_REG))]
5573 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5575 switch (get_attr_type (insn))
5578 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5579 return "lea{l}\t{%a2, %0|%0, %a2}";
5582 if (! rtx_equal_p (operands[0], operands[1]))
5584 if (operands[2] == const1_rtx)
5585 return "inc{l}\t%0";
5586 else if (operands[2] == constm1_rtx)
5587 return "dec{l}\t%0";
5592 if (! rtx_equal_p (operands[0], operands[1]))
5595 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5596 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5597 if (GET_CODE (operands[2]) == CONST_INT
5598 && (INTVAL (operands[2]) == 128
5599 || (INTVAL (operands[2]) < 0
5600 && INTVAL (operands[2]) != -128)))
5602 operands[2] = GEN_INT (-INTVAL (operands[2]));
5603 return "sub{l}\t{%2, %0|%0, %2}";
5605 return "add{l}\t{%2, %0|%0, %2}";
5609 (cond [(eq_attr "alternative" "2")
5610 (const_string "lea")
5611 ; Current assemblers are broken and do not allow @GOTOFF in
5612 ; ought but a memory context.
5613 (match_operand:SI 2 "pic_symbolic_operand" "")
5614 (const_string "lea")
5615 (match_operand:SI 2 "incdec_operand" "")
5616 (const_string "incdec")
5618 (const_string "alu")))
5619 (set_attr "mode" "SI")])
5621 ;; Convert lea to the lea pattern to avoid flags dependency.
5623 [(set (match_operand 0 "register_operand" "")
5624 (plus (match_operand 1 "register_operand" "")
5625 (match_operand 2 "nonmemory_operand" "")))
5626 (clobber (reg:CC FLAGS_REG))]
5628 && true_regnum (operands[0]) != true_regnum (operands[1])"
5632 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5633 may confuse gen_lowpart. */
5634 if (GET_MODE (operands[0]) != Pmode)
5636 operands[1] = gen_lowpart (Pmode, operands[1]);
5637 operands[2] = gen_lowpart (Pmode, operands[2]);
5639 operands[0] = gen_lowpart (SImode, operands[0]);
5640 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5641 if (Pmode != SImode)
5642 pat = gen_rtx_SUBREG (SImode, pat, 0);
5643 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5647 ;; It may seem that nonimmediate operand is proper one for operand 1.
5648 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5649 ;; we take care in ix86_binary_operator_ok to not allow two memory
5650 ;; operands so proper swapping will be done in reload. This allow
5651 ;; patterns constructed from addsi_1 to match.
5652 (define_insn "addsi_1_zext"
5653 [(set (match_operand:DI 0 "register_operand" "=r,r")
5655 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5656 (match_operand:SI 2 "general_operand" "rmni,rni"))))
5657 (clobber (reg:CC FLAGS_REG))]
5658 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5660 switch (get_attr_type (insn))
5663 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5664 return "lea{l}\t{%a2, %k0|%k0, %a2}";
5667 if (operands[2] == const1_rtx)
5668 return "inc{l}\t%k0";
5669 else if (operands[2] == constm1_rtx)
5670 return "dec{l}\t%k0";
5675 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5676 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5677 if (GET_CODE (operands[2]) == CONST_INT
5678 && (INTVAL (operands[2]) == 128
5679 || (INTVAL (operands[2]) < 0
5680 && INTVAL (operands[2]) != -128)))
5682 operands[2] = GEN_INT (-INTVAL (operands[2]));
5683 return "sub{l}\t{%2, %k0|%k0, %2}";
5685 return "add{l}\t{%2, %k0|%k0, %2}";
5689 (cond [(eq_attr "alternative" "1")
5690 (const_string "lea")
5691 ; Current assemblers are broken and do not allow @GOTOFF in
5692 ; ought but a memory context.
5693 (match_operand:SI 2 "pic_symbolic_operand" "")
5694 (const_string "lea")
5695 (match_operand:SI 2 "incdec_operand" "")
5696 (const_string "incdec")
5698 (const_string "alu")))
5699 (set_attr "mode" "SI")])
5701 ;; Convert lea to the lea pattern to avoid flags dependency.
5703 [(set (match_operand:DI 0 "register_operand" "")
5705 (plus:SI (match_operand:SI 1 "register_operand" "")
5706 (match_operand:SI 2 "nonmemory_operand" ""))))
5707 (clobber (reg:CC FLAGS_REG))]
5708 "TARGET_64BIT && reload_completed
5709 && true_regnum (operands[0]) != true_regnum (operands[1])"
5711 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5713 operands[1] = gen_lowpart (Pmode, operands[1]);
5714 operands[2] = gen_lowpart (Pmode, operands[2]);
5717 (define_insn "*addsi_2"
5720 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5721 (match_operand:SI 2 "general_operand" "rmni,rni"))
5723 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5724 (plus:SI (match_dup 1) (match_dup 2)))]
5725 "ix86_match_ccmode (insn, CCGOCmode)
5726 && ix86_binary_operator_ok (PLUS, SImode, operands)
5727 /* Current assemblers are broken and do not allow @GOTOFF in
5728 ought but a memory context. */
5729 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5731 switch (get_attr_type (insn))
5734 if (! rtx_equal_p (operands[0], operands[1]))
5736 if (operands[2] == const1_rtx)
5737 return "inc{l}\t%0";
5738 else if (operands[2] == constm1_rtx)
5739 return "dec{l}\t%0";
5744 if (! rtx_equal_p (operands[0], operands[1]))
5746 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5747 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5748 if (GET_CODE (operands[2]) == CONST_INT
5749 && (INTVAL (operands[2]) == 128
5750 || (INTVAL (operands[2]) < 0
5751 && INTVAL (operands[2]) != -128)))
5753 operands[2] = GEN_INT (-INTVAL (operands[2]));
5754 return "sub{l}\t{%2, %0|%0, %2}";
5756 return "add{l}\t{%2, %0|%0, %2}";
5760 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5761 (const_string "incdec")
5762 (const_string "alu")))
5763 (set_attr "mode" "SI")])
5765 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5766 (define_insn "*addsi_2_zext"
5769 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5770 (match_operand:SI 2 "general_operand" "rmni"))
5772 (set (match_operand:DI 0 "register_operand" "=r")
5773 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5774 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5775 && ix86_binary_operator_ok (PLUS, SImode, operands)
5776 /* Current assemblers are broken and do not allow @GOTOFF in
5777 ought but a memory context. */
5778 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5780 switch (get_attr_type (insn))
5783 if (operands[2] == const1_rtx)
5784 return "inc{l}\t%k0";
5785 else if (operands[2] == constm1_rtx)
5786 return "dec{l}\t%k0";
5791 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5792 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5793 if (GET_CODE (operands[2]) == CONST_INT
5794 && (INTVAL (operands[2]) == 128
5795 || (INTVAL (operands[2]) < 0
5796 && INTVAL (operands[2]) != -128)))
5798 operands[2] = GEN_INT (-INTVAL (operands[2]));
5799 return "sub{l}\t{%2, %k0|%k0, %2}";
5801 return "add{l}\t{%2, %k0|%k0, %2}";
5805 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5806 (const_string "incdec")
5807 (const_string "alu")))
5808 (set_attr "mode" "SI")])
5810 (define_insn "*addsi_3"
5812 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5813 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5814 (clobber (match_scratch:SI 0 "=r"))]
5815 "ix86_match_ccmode (insn, CCZmode)
5816 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5817 /* Current assemblers are broken and do not allow @GOTOFF in
5818 ought but a memory context. */
5819 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5821 switch (get_attr_type (insn))
5824 if (! rtx_equal_p (operands[0], operands[1]))
5826 if (operands[2] == const1_rtx)
5827 return "inc{l}\t%0";
5828 else if (operands[2] == constm1_rtx)
5829 return "dec{l}\t%0";
5834 if (! rtx_equal_p (operands[0], operands[1]))
5836 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5837 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5838 if (GET_CODE (operands[2]) == CONST_INT
5839 && (INTVAL (operands[2]) == 128
5840 || (INTVAL (operands[2]) < 0
5841 && INTVAL (operands[2]) != -128)))
5843 operands[2] = GEN_INT (-INTVAL (operands[2]));
5844 return "sub{l}\t{%2, %0|%0, %2}";
5846 return "add{l}\t{%2, %0|%0, %2}";
5850 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5851 (const_string "incdec")
5852 (const_string "alu")))
5853 (set_attr "mode" "SI")])
5855 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5856 (define_insn "*addsi_3_zext"
5858 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5859 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5860 (set (match_operand:DI 0 "register_operand" "=r")
5861 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5862 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
5863 && ix86_binary_operator_ok (PLUS, SImode, operands)
5864 /* Current assemblers are broken and do not allow @GOTOFF in
5865 ought but a memory context. */
5866 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5868 switch (get_attr_type (insn))
5871 if (operands[2] == const1_rtx)
5872 return "inc{l}\t%k0";
5873 else if (operands[2] == constm1_rtx)
5874 return "dec{l}\t%k0";
5879 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5880 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5881 if (GET_CODE (operands[2]) == CONST_INT
5882 && (INTVAL (operands[2]) == 128
5883 || (INTVAL (operands[2]) < 0
5884 && INTVAL (operands[2]) != -128)))
5886 operands[2] = GEN_INT (-INTVAL (operands[2]));
5887 return "sub{l}\t{%2, %k0|%k0, %2}";
5889 return "add{l}\t{%2, %k0|%k0, %2}";
5893 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5894 (const_string "incdec")
5895 (const_string "alu")))
5896 (set_attr "mode" "SI")])
5898 ; For comparisons against 1, -1 and 128, we may generate better code
5899 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5900 ; is matched then. We can't accept general immediate, because for
5901 ; case of overflows, the result is messed up.
5902 ; This pattern also don't hold of 0x80000000, since the value overflows
5904 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5905 ; only for comparisons not depending on it.
5906 (define_insn "*addsi_4"
5908 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
5909 (match_operand:SI 2 "const_int_operand" "n")))
5910 (clobber (match_scratch:SI 0 "=rm"))]
5911 "ix86_match_ccmode (insn, CCGCmode)
5912 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
5914 switch (get_attr_type (insn))
5917 if (operands[2] == constm1_rtx)
5918 return "inc{l}\t%0";
5919 else if (operands[2] == const1_rtx)
5920 return "dec{l}\t%0";
5925 if (! rtx_equal_p (operands[0], operands[1]))
5927 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5928 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5929 if ((INTVAL (operands[2]) == -128
5930 || (INTVAL (operands[2]) > 0
5931 && INTVAL (operands[2]) != 128)))
5932 return "sub{l}\t{%2, %0|%0, %2}";
5933 operands[2] = GEN_INT (-INTVAL (operands[2]));
5934 return "add{l}\t{%2, %0|%0, %2}";
5938 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5939 (const_string "incdec")
5940 (const_string "alu")))
5941 (set_attr "mode" "SI")])
5943 (define_insn "*addsi_5"
5946 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5947 (match_operand:SI 2 "general_operand" "rmni"))
5949 (clobber (match_scratch:SI 0 "=r"))]
5950 "ix86_match_ccmode (insn, CCGOCmode)
5951 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5952 /* Current assemblers are broken and do not allow @GOTOFF in
5953 ought but a memory context. */
5954 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5956 switch (get_attr_type (insn))
5959 if (! rtx_equal_p (operands[0], operands[1]))
5961 if (operands[2] == const1_rtx)
5962 return "inc{l}\t%0";
5963 else if (operands[2] == constm1_rtx)
5964 return "dec{l}\t%0";
5969 if (! rtx_equal_p (operands[0], operands[1]))
5971 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5972 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5973 if (GET_CODE (operands[2]) == CONST_INT
5974 && (INTVAL (operands[2]) == 128
5975 || (INTVAL (operands[2]) < 0
5976 && INTVAL (operands[2]) != -128)))
5978 operands[2] = GEN_INT (-INTVAL (operands[2]));
5979 return "sub{l}\t{%2, %0|%0, %2}";
5981 return "add{l}\t{%2, %0|%0, %2}";
5985 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5986 (const_string "incdec")
5987 (const_string "alu")))
5988 (set_attr "mode" "SI")])
5990 (define_expand "addhi3"
5991 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
5992 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
5993 (match_operand:HI 2 "general_operand" "")))
5994 (clobber (reg:CC FLAGS_REG))])]
5995 "TARGET_HIMODE_MATH"
5996 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
5998 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
5999 ;; type optimizations enabled by define-splits. This is not important
6000 ;; for PII, and in fact harmful because of partial register stalls.
6002 (define_insn "*addhi_1_lea"
6003 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
6004 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
6005 (match_operand:HI 2 "general_operand" "ri,rm,rni")))
6006 (clobber (reg:CC FLAGS_REG))]
6007 "!TARGET_PARTIAL_REG_STALL
6008 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6010 switch (get_attr_type (insn))
6015 if (operands[2] == const1_rtx)
6016 return "inc{w}\t%0";
6017 else if (operands[2] == constm1_rtx)
6018 return "dec{w}\t%0";
6022 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6023 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6024 if (GET_CODE (operands[2]) == CONST_INT
6025 && (INTVAL (operands[2]) == 128
6026 || (INTVAL (operands[2]) < 0
6027 && INTVAL (operands[2]) != -128)))
6029 operands[2] = GEN_INT (-INTVAL (operands[2]));
6030 return "sub{w}\t{%2, %0|%0, %2}";
6032 return "add{w}\t{%2, %0|%0, %2}";
6036 (if_then_else (eq_attr "alternative" "2")
6037 (const_string "lea")
6038 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6039 (const_string "incdec")
6040 (const_string "alu"))))
6041 (set_attr "mode" "HI,HI,SI")])
6043 (define_insn "*addhi_1"
6044 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6045 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6046 (match_operand:HI 2 "general_operand" "ri,rm")))
6047 (clobber (reg:CC FLAGS_REG))]
6048 "TARGET_PARTIAL_REG_STALL
6049 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6051 switch (get_attr_type (insn))
6054 if (operands[2] == const1_rtx)
6055 return "inc{w}\t%0";
6056 else if (operands[2] == constm1_rtx)
6057 return "dec{w}\t%0";
6061 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6062 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6063 if (GET_CODE (operands[2]) == CONST_INT
6064 && (INTVAL (operands[2]) == 128
6065 || (INTVAL (operands[2]) < 0
6066 && INTVAL (operands[2]) != -128)))
6068 operands[2] = GEN_INT (-INTVAL (operands[2]));
6069 return "sub{w}\t{%2, %0|%0, %2}";
6071 return "add{w}\t{%2, %0|%0, %2}";
6075 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6076 (const_string "incdec")
6077 (const_string "alu")))
6078 (set_attr "mode" "HI")])
6080 (define_insn "*addhi_2"
6083 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6084 (match_operand:HI 2 "general_operand" "rmni,rni"))
6086 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6087 (plus:HI (match_dup 1) (match_dup 2)))]
6088 "ix86_match_ccmode (insn, CCGOCmode)
6089 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6091 switch (get_attr_type (insn))
6094 if (operands[2] == const1_rtx)
6095 return "inc{w}\t%0";
6096 else if (operands[2] == constm1_rtx)
6097 return "dec{w}\t%0";
6101 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6102 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6103 if (GET_CODE (operands[2]) == CONST_INT
6104 && (INTVAL (operands[2]) == 128
6105 || (INTVAL (operands[2]) < 0
6106 && INTVAL (operands[2]) != -128)))
6108 operands[2] = GEN_INT (-INTVAL (operands[2]));
6109 return "sub{w}\t{%2, %0|%0, %2}";
6111 return "add{w}\t{%2, %0|%0, %2}";
6115 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6116 (const_string "incdec")
6117 (const_string "alu")))
6118 (set_attr "mode" "HI")])
6120 (define_insn "*addhi_3"
6122 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
6123 (match_operand:HI 1 "nonimmediate_operand" "%0")))
6124 (clobber (match_scratch:HI 0 "=r"))]
6125 "ix86_match_ccmode (insn, CCZmode)
6126 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6128 switch (get_attr_type (insn))
6131 if (operands[2] == const1_rtx)
6132 return "inc{w}\t%0";
6133 else if (operands[2] == constm1_rtx)
6134 return "dec{w}\t%0";
6138 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6139 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6140 if (GET_CODE (operands[2]) == CONST_INT
6141 && (INTVAL (operands[2]) == 128
6142 || (INTVAL (operands[2]) < 0
6143 && INTVAL (operands[2]) != -128)))
6145 operands[2] = GEN_INT (-INTVAL (operands[2]));
6146 return "sub{w}\t{%2, %0|%0, %2}";
6148 return "add{w}\t{%2, %0|%0, %2}";
6152 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6153 (const_string "incdec")
6154 (const_string "alu")))
6155 (set_attr "mode" "HI")])
6157 ; See comments above addsi_3_imm for details.
6158 (define_insn "*addhi_4"
6160 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
6161 (match_operand:HI 2 "const_int_operand" "n")))
6162 (clobber (match_scratch:HI 0 "=rm"))]
6163 "ix86_match_ccmode (insn, CCGCmode)
6164 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
6166 switch (get_attr_type (insn))
6169 if (operands[2] == constm1_rtx)
6170 return "inc{w}\t%0";
6171 else if (operands[2] == const1_rtx)
6172 return "dec{w}\t%0";
6177 if (! rtx_equal_p (operands[0], operands[1]))
6179 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6180 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6181 if ((INTVAL (operands[2]) == -128
6182 || (INTVAL (operands[2]) > 0
6183 && INTVAL (operands[2]) != 128)))
6184 return "sub{w}\t{%2, %0|%0, %2}";
6185 operands[2] = GEN_INT (-INTVAL (operands[2]));
6186 return "add{w}\t{%2, %0|%0, %2}";
6190 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6191 (const_string "incdec")
6192 (const_string "alu")))
6193 (set_attr "mode" "SI")])
6196 (define_insn "*addhi_5"
6199 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6200 (match_operand:HI 2 "general_operand" "rmni"))
6202 (clobber (match_scratch:HI 0 "=r"))]
6203 "ix86_match_ccmode (insn, CCGOCmode)
6204 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6206 switch (get_attr_type (insn))
6209 if (operands[2] == const1_rtx)
6210 return "inc{w}\t%0";
6211 else if (operands[2] == constm1_rtx)
6212 return "dec{w}\t%0";
6216 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6217 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6218 if (GET_CODE (operands[2]) == CONST_INT
6219 && (INTVAL (operands[2]) == 128
6220 || (INTVAL (operands[2]) < 0
6221 && INTVAL (operands[2]) != -128)))
6223 operands[2] = GEN_INT (-INTVAL (operands[2]));
6224 return "sub{w}\t{%2, %0|%0, %2}";
6226 return "add{w}\t{%2, %0|%0, %2}";
6230 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6231 (const_string "incdec")
6232 (const_string "alu")))
6233 (set_attr "mode" "HI")])
6235 (define_expand "addqi3"
6236 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6237 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6238 (match_operand:QI 2 "general_operand" "")))
6239 (clobber (reg:CC FLAGS_REG))])]
6240 "TARGET_QIMODE_MATH"
6241 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
6243 ;; %%% Potential partial reg stall on alternative 2. What to do?
6244 (define_insn "*addqi_1_lea"
6245 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
6246 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
6247 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
6248 (clobber (reg:CC FLAGS_REG))]
6249 "!TARGET_PARTIAL_REG_STALL
6250 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6252 int widen = (which_alternative == 2);
6253 switch (get_attr_type (insn))
6258 if (operands[2] == const1_rtx)
6259 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6260 else if (operands[2] == constm1_rtx)
6261 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6265 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6266 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6267 if (GET_CODE (operands[2]) == CONST_INT
6268 && (INTVAL (operands[2]) == 128
6269 || (INTVAL (operands[2]) < 0
6270 && INTVAL (operands[2]) != -128)))
6272 operands[2] = GEN_INT (-INTVAL (operands[2]));
6274 return "sub{l}\t{%2, %k0|%k0, %2}";
6276 return "sub{b}\t{%2, %0|%0, %2}";
6279 return "add{l}\t{%k2, %k0|%k0, %k2}";
6281 return "add{b}\t{%2, %0|%0, %2}";
6285 (if_then_else (eq_attr "alternative" "3")
6286 (const_string "lea")
6287 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6288 (const_string "incdec")
6289 (const_string "alu"))))
6290 (set_attr "mode" "QI,QI,SI,SI")])
6292 (define_insn "*addqi_1"
6293 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6294 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6295 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6296 (clobber (reg:CC FLAGS_REG))]
6297 "TARGET_PARTIAL_REG_STALL
6298 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6300 int widen = (which_alternative == 2);
6301 switch (get_attr_type (insn))
6304 if (operands[2] == const1_rtx)
6305 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6306 else if (operands[2] == constm1_rtx)
6307 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6311 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6312 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6313 if (GET_CODE (operands[2]) == CONST_INT
6314 && (INTVAL (operands[2]) == 128
6315 || (INTVAL (operands[2]) < 0
6316 && INTVAL (operands[2]) != -128)))
6318 operands[2] = GEN_INT (-INTVAL (operands[2]));
6320 return "sub{l}\t{%2, %k0|%k0, %2}";
6322 return "sub{b}\t{%2, %0|%0, %2}";
6325 return "add{l}\t{%k2, %k0|%k0, %k2}";
6327 return "add{b}\t{%2, %0|%0, %2}";
6331 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6332 (const_string "incdec")
6333 (const_string "alu")))
6334 (set_attr "mode" "QI,QI,SI")])
6336 (define_insn "*addqi_1_slp"
6337 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6338 (plus:QI (match_dup 0)
6339 (match_operand:QI 1 "general_operand" "qn,qnm")))
6340 (clobber (reg:CC FLAGS_REG))]
6341 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6342 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6344 switch (get_attr_type (insn))
6347 if (operands[1] == const1_rtx)
6348 return "inc{b}\t%0";
6349 else if (operands[1] == constm1_rtx)
6350 return "dec{b}\t%0";
6354 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */
6355 if (GET_CODE (operands[1]) == CONST_INT
6356 && INTVAL (operands[1]) < 0)
6358 operands[1] = GEN_INT (-INTVAL (operands[1]));
6359 return "sub{b}\t{%1, %0|%0, %1}";
6361 return "add{b}\t{%1, %0|%0, %1}";
6365 (if_then_else (match_operand:QI 1 "incdec_operand" "")
6366 (const_string "incdec")
6367 (const_string "alu1")))
6368 (set_attr "mode" "QI")])
6370 (define_insn "*addqi_2"
6373 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6374 (match_operand:QI 2 "general_operand" "qmni,qni"))
6376 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6377 (plus:QI (match_dup 1) (match_dup 2)))]
6378 "ix86_match_ccmode (insn, CCGOCmode)
6379 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6381 switch (get_attr_type (insn))
6384 if (operands[2] == const1_rtx)
6385 return "inc{b}\t%0";
6386 else if (operands[2] == constm1_rtx
6387 || (GET_CODE (operands[2]) == CONST_INT
6388 && INTVAL (operands[2]) == 255))
6389 return "dec{b}\t%0";
6393 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6394 if (GET_CODE (operands[2]) == CONST_INT
6395 && INTVAL (operands[2]) < 0)
6397 operands[2] = GEN_INT (-INTVAL (operands[2]));
6398 return "sub{b}\t{%2, %0|%0, %2}";
6400 return "add{b}\t{%2, %0|%0, %2}";
6404 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6405 (const_string "incdec")
6406 (const_string "alu")))
6407 (set_attr "mode" "QI")])
6409 (define_insn "*addqi_3"
6411 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6412 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6413 (clobber (match_scratch:QI 0 "=q"))]
6414 "ix86_match_ccmode (insn, CCZmode)
6415 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6417 switch (get_attr_type (insn))
6420 if (operands[2] == const1_rtx)
6421 return "inc{b}\t%0";
6422 else if (operands[2] == constm1_rtx
6423 || (GET_CODE (operands[2]) == CONST_INT
6424 && INTVAL (operands[2]) == 255))
6425 return "dec{b}\t%0";
6429 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6430 if (GET_CODE (operands[2]) == CONST_INT
6431 && INTVAL (operands[2]) < 0)
6433 operands[2] = GEN_INT (-INTVAL (operands[2]));
6434 return "sub{b}\t{%2, %0|%0, %2}";
6436 return "add{b}\t{%2, %0|%0, %2}";
6440 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6441 (const_string "incdec")
6442 (const_string "alu")))
6443 (set_attr "mode" "QI")])
6445 ; See comments above addsi_3_imm for details.
6446 (define_insn "*addqi_4"
6448 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6449 (match_operand:QI 2 "const_int_operand" "n")))
6450 (clobber (match_scratch:QI 0 "=qm"))]
6451 "ix86_match_ccmode (insn, CCGCmode)
6452 && (INTVAL (operands[2]) & 0xff) != 0x80"
6454 switch (get_attr_type (insn))
6457 if (operands[2] == constm1_rtx
6458 || (GET_CODE (operands[2]) == CONST_INT
6459 && INTVAL (operands[2]) == 255))
6460 return "inc{b}\t%0";
6461 else if (operands[2] == const1_rtx)
6462 return "dec{b}\t%0";
6467 if (! rtx_equal_p (operands[0], operands[1]))
6469 if (INTVAL (operands[2]) < 0)
6471 operands[2] = GEN_INT (-INTVAL (operands[2]));
6472 return "add{b}\t{%2, %0|%0, %2}";
6474 return "sub{b}\t{%2, %0|%0, %2}";
6478 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6479 (const_string "incdec")
6480 (const_string "alu")))
6481 (set_attr "mode" "QI")])
6484 (define_insn "*addqi_5"
6487 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6488 (match_operand:QI 2 "general_operand" "qmni"))
6490 (clobber (match_scratch:QI 0 "=q"))]
6491 "ix86_match_ccmode (insn, CCGOCmode)
6492 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6494 switch (get_attr_type (insn))
6497 if (operands[2] == const1_rtx)
6498 return "inc{b}\t%0";
6499 else if (operands[2] == constm1_rtx
6500 || (GET_CODE (operands[2]) == CONST_INT
6501 && INTVAL (operands[2]) == 255))
6502 return "dec{b}\t%0";
6506 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6507 if (GET_CODE (operands[2]) == CONST_INT
6508 && INTVAL (operands[2]) < 0)
6510 operands[2] = GEN_INT (-INTVAL (operands[2]));
6511 return "sub{b}\t{%2, %0|%0, %2}";
6513 return "add{b}\t{%2, %0|%0, %2}";
6517 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6518 (const_string "incdec")
6519 (const_string "alu")))
6520 (set_attr "mode" "QI")])
6523 (define_insn "addqi_ext_1"
6524 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6529 (match_operand 1 "ext_register_operand" "0")
6532 (match_operand:QI 2 "general_operand" "Qmn")))
6533 (clobber (reg:CC FLAGS_REG))]
6536 switch (get_attr_type (insn))
6539 if (operands[2] == const1_rtx)
6540 return "inc{b}\t%h0";
6541 else if (operands[2] == constm1_rtx
6542 || (GET_CODE (operands[2]) == CONST_INT
6543 && INTVAL (operands[2]) == 255))
6544 return "dec{b}\t%h0";
6548 return "add{b}\t{%2, %h0|%h0, %2}";
6552 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6553 (const_string "incdec")
6554 (const_string "alu")))
6555 (set_attr "mode" "QI")])
6557 (define_insn "*addqi_ext_1_rex64"
6558 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6563 (match_operand 1 "ext_register_operand" "0")
6566 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6567 (clobber (reg:CC FLAGS_REG))]
6570 switch (get_attr_type (insn))
6573 if (operands[2] == const1_rtx)
6574 return "inc{b}\t%h0";
6575 else if (operands[2] == constm1_rtx
6576 || (GET_CODE (operands[2]) == CONST_INT
6577 && INTVAL (operands[2]) == 255))
6578 return "dec{b}\t%h0";
6582 return "add{b}\t{%2, %h0|%h0, %2}";
6586 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6587 (const_string "incdec")
6588 (const_string "alu")))
6589 (set_attr "mode" "QI")])
6591 (define_insn "*addqi_ext_2"
6592 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6597 (match_operand 1 "ext_register_operand" "%0")
6601 (match_operand 2 "ext_register_operand" "Q")
6604 (clobber (reg:CC FLAGS_REG))]
6606 "add{b}\t{%h2, %h0|%h0, %h2}"
6607 [(set_attr "type" "alu")
6608 (set_attr "mode" "QI")])
6610 ;; The patterns that match these are at the end of this file.
6612 (define_expand "addxf3"
6613 [(set (match_operand:XF 0 "register_operand" "")
6614 (plus:XF (match_operand:XF 1 "register_operand" "")
6615 (match_operand:XF 2 "register_operand" "")))]
6619 (define_expand "adddf3"
6620 [(set (match_operand:DF 0 "register_operand" "")
6621 (plus:DF (match_operand:DF 1 "register_operand" "")
6622 (match_operand:DF 2 "nonimmediate_operand" "")))]
6623 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6626 (define_expand "addsf3"
6627 [(set (match_operand:SF 0 "register_operand" "")
6628 (plus:SF (match_operand:SF 1 "register_operand" "")
6629 (match_operand:SF 2 "nonimmediate_operand" "")))]
6630 "TARGET_80387 || TARGET_SSE_MATH"
6633 ;; Subtract instructions
6635 ;; %%% splits for subsidi3
6637 (define_expand "subdi3"
6638 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6639 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6640 (match_operand:DI 2 "x86_64_general_operand" "")))
6641 (clobber (reg:CC FLAGS_REG))])]
6643 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6645 (define_insn "*subdi3_1"
6646 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6647 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6648 (match_operand:DI 2 "general_operand" "roiF,riF")))
6649 (clobber (reg:CC FLAGS_REG))]
6650 "!TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6654 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6655 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6656 (match_operand:DI 2 "general_operand" "")))
6657 (clobber (reg:CC FLAGS_REG))]
6658 "!TARGET_64BIT && reload_completed"
6659 [(parallel [(set (reg:CC FLAGS_REG) (compare:CC (match_dup 1) (match_dup 2)))
6660 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6661 (parallel [(set (match_dup 3)
6662 (minus:SI (match_dup 4)
6663 (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
6665 (clobber (reg:CC FLAGS_REG))])]
6666 "split_di (operands+0, 1, operands+0, operands+3);
6667 split_di (operands+1, 1, operands+1, operands+4);
6668 split_di (operands+2, 1, operands+2, operands+5);")
6670 (define_insn "subdi3_carry_rex64"
6671 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6672 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6673 (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
6674 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6675 (clobber (reg:CC FLAGS_REG))]
6676 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6677 "sbb{q}\t{%2, %0|%0, %2}"
6678 [(set_attr "type" "alu")
6679 (set_attr "pent_pair" "pu")
6680 (set_attr "mode" "DI")])
6682 (define_insn "*subdi_1_rex64"
6683 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6684 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6685 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6686 (clobber (reg:CC FLAGS_REG))]
6687 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6688 "sub{q}\t{%2, %0|%0, %2}"
6689 [(set_attr "type" "alu")
6690 (set_attr "mode" "DI")])
6692 (define_insn "*subdi_2_rex64"
6695 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6696 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6698 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6699 (minus:DI (match_dup 1) (match_dup 2)))]
6700 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6701 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6702 "sub{q}\t{%2, %0|%0, %2}"
6703 [(set_attr "type" "alu")
6704 (set_attr "mode" "DI")])
6706 (define_insn "*subdi_3_rex63"
6708 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6709 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6710 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6711 (minus:DI (match_dup 1) (match_dup 2)))]
6712 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6713 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6714 "sub{q}\t{%2, %0|%0, %2}"
6715 [(set_attr "type" "alu")
6716 (set_attr "mode" "DI")])
6718 (define_insn "subqi3_carry"
6719 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6720 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6721 (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
6722 (match_operand:QI 2 "general_operand" "qi,qm"))))
6723 (clobber (reg:CC FLAGS_REG))]
6724 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6725 "sbb{b}\t{%2, %0|%0, %2}"
6726 [(set_attr "type" "alu")
6727 (set_attr "pent_pair" "pu")
6728 (set_attr "mode" "QI")])
6730 (define_insn "subhi3_carry"
6731 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6732 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6733 (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
6734 (match_operand:HI 2 "general_operand" "ri,rm"))))
6735 (clobber (reg:CC FLAGS_REG))]
6736 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6737 "sbb{w}\t{%2, %0|%0, %2}"
6738 [(set_attr "type" "alu")
6739 (set_attr "pent_pair" "pu")
6740 (set_attr "mode" "HI")])
6742 (define_insn "subsi3_carry"
6743 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6744 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6745 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6746 (match_operand:SI 2 "general_operand" "ri,rm"))))
6747 (clobber (reg:CC FLAGS_REG))]
6748 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6749 "sbb{l}\t{%2, %0|%0, %2}"
6750 [(set_attr "type" "alu")
6751 (set_attr "pent_pair" "pu")
6752 (set_attr "mode" "SI")])
6754 (define_insn "subsi3_carry_zext"
6755 [(set (match_operand:DI 0 "register_operand" "=rm,r")
6757 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6758 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6759 (match_operand:SI 2 "general_operand" "ri,rm")))))
6760 (clobber (reg:CC FLAGS_REG))]
6761 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6762 "sbb{l}\t{%2, %k0|%k0, %2}"
6763 [(set_attr "type" "alu")
6764 (set_attr "pent_pair" "pu")
6765 (set_attr "mode" "SI")])
6767 (define_expand "subsi3"
6768 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
6769 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
6770 (match_operand:SI 2 "general_operand" "")))
6771 (clobber (reg:CC FLAGS_REG))])]
6773 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
6775 (define_insn "*subsi_1"
6776 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6777 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6778 (match_operand:SI 2 "general_operand" "ri,rm")))
6779 (clobber (reg:CC FLAGS_REG))]
6780 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6781 "sub{l}\t{%2, %0|%0, %2}"
6782 [(set_attr "type" "alu")
6783 (set_attr "mode" "SI")])
6785 (define_insn "*subsi_1_zext"
6786 [(set (match_operand:DI 0 "register_operand" "=r")
6788 (minus:SI (match_operand:SI 1 "register_operand" "0")
6789 (match_operand:SI 2 "general_operand" "rim"))))
6790 (clobber (reg:CC FLAGS_REG))]
6791 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6792 "sub{l}\t{%2, %k0|%k0, %2}"
6793 [(set_attr "type" "alu")
6794 (set_attr "mode" "SI")])
6796 (define_insn "*subsi_2"
6799 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6800 (match_operand:SI 2 "general_operand" "ri,rm"))
6802 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6803 (minus:SI (match_dup 1) (match_dup 2)))]
6804 "ix86_match_ccmode (insn, CCGOCmode)
6805 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6806 "sub{l}\t{%2, %0|%0, %2}"
6807 [(set_attr "type" "alu")
6808 (set_attr "mode" "SI")])
6810 (define_insn "*subsi_2_zext"
6813 (minus:SI (match_operand:SI 1 "register_operand" "0")
6814 (match_operand:SI 2 "general_operand" "rim"))
6816 (set (match_operand:DI 0 "register_operand" "=r")
6818 (minus:SI (match_dup 1)
6820 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6821 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6822 "sub{l}\t{%2, %k0|%k0, %2}"
6823 [(set_attr "type" "alu")
6824 (set_attr "mode" "SI")])
6826 (define_insn "*subsi_3"
6828 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
6829 (match_operand:SI 2 "general_operand" "ri,rm")))
6830 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6831 (minus:SI (match_dup 1) (match_dup 2)))]
6832 "ix86_match_ccmode (insn, CCmode)
6833 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6834 "sub{l}\t{%2, %0|%0, %2}"
6835 [(set_attr "type" "alu")
6836 (set_attr "mode" "SI")])
6838 (define_insn "*subsi_3_zext"
6840 (compare (match_operand:SI 1 "register_operand" "0")
6841 (match_operand:SI 2 "general_operand" "rim")))
6842 (set (match_operand:DI 0 "register_operand" "=r")
6844 (minus:SI (match_dup 1)
6846 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6847 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6848 "sub{q}\t{%2, %0|%0, %2}"
6849 [(set_attr "type" "alu")
6850 (set_attr "mode" "DI")])
6852 (define_expand "subhi3"
6853 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6854 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6855 (match_operand:HI 2 "general_operand" "")))
6856 (clobber (reg:CC FLAGS_REG))])]
6857 "TARGET_HIMODE_MATH"
6858 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
6860 (define_insn "*subhi_1"
6861 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6862 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6863 (match_operand:HI 2 "general_operand" "ri,rm")))
6864 (clobber (reg:CC FLAGS_REG))]
6865 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6866 "sub{w}\t{%2, %0|%0, %2}"
6867 [(set_attr "type" "alu")
6868 (set_attr "mode" "HI")])
6870 (define_insn "*subhi_2"
6873 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6874 (match_operand:HI 2 "general_operand" "ri,rm"))
6876 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6877 (minus:HI (match_dup 1) (match_dup 2)))]
6878 "ix86_match_ccmode (insn, CCGOCmode)
6879 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6880 "sub{w}\t{%2, %0|%0, %2}"
6881 [(set_attr "type" "alu")
6882 (set_attr "mode" "HI")])
6884 (define_insn "*subhi_3"
6886 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
6887 (match_operand:HI 2 "general_operand" "ri,rm")))
6888 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6889 (minus:HI (match_dup 1) (match_dup 2)))]
6890 "ix86_match_ccmode (insn, CCmode)
6891 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6892 "sub{w}\t{%2, %0|%0, %2}"
6893 [(set_attr "type" "alu")
6894 (set_attr "mode" "HI")])
6896 (define_expand "subqi3"
6897 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6898 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6899 (match_operand:QI 2 "general_operand" "")))
6900 (clobber (reg:CC FLAGS_REG))])]
6901 "TARGET_QIMODE_MATH"
6902 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
6904 (define_insn "*subqi_1"
6905 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6906 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6907 (match_operand:QI 2 "general_operand" "qn,qmn")))
6908 (clobber (reg:CC FLAGS_REG))]
6909 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6910 "sub{b}\t{%2, %0|%0, %2}"
6911 [(set_attr "type" "alu")
6912 (set_attr "mode" "QI")])
6914 (define_insn "*subqi_1_slp"
6915 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6916 (minus:QI (match_dup 0)
6917 (match_operand:QI 1 "general_operand" "qn,qmn")))
6918 (clobber (reg:CC FLAGS_REG))]
6919 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6920 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6921 "sub{b}\t{%1, %0|%0, %1}"
6922 [(set_attr "type" "alu1")
6923 (set_attr "mode" "QI")])
6925 (define_insn "*subqi_2"
6928 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6929 (match_operand:QI 2 "general_operand" "qi,qm"))
6931 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6932 (minus:HI (match_dup 1) (match_dup 2)))]
6933 "ix86_match_ccmode (insn, CCGOCmode)
6934 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6935 "sub{b}\t{%2, %0|%0, %2}"
6936 [(set_attr "type" "alu")
6937 (set_attr "mode" "QI")])
6939 (define_insn "*subqi_3"
6941 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
6942 (match_operand:QI 2 "general_operand" "qi,qm")))
6943 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6944 (minus:HI (match_dup 1) (match_dup 2)))]
6945 "ix86_match_ccmode (insn, CCmode)
6946 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6947 "sub{b}\t{%2, %0|%0, %2}"
6948 [(set_attr "type" "alu")
6949 (set_attr "mode" "QI")])
6951 ;; The patterns that match these are at the end of this file.
6953 (define_expand "subxf3"
6954 [(set (match_operand:XF 0 "register_operand" "")
6955 (minus:XF (match_operand:XF 1 "register_operand" "")
6956 (match_operand:XF 2 "register_operand" "")))]
6960 (define_expand "subdf3"
6961 [(set (match_operand:DF 0 "register_operand" "")
6962 (minus:DF (match_operand:DF 1 "register_operand" "")
6963 (match_operand:DF 2 "nonimmediate_operand" "")))]
6964 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6967 (define_expand "subsf3"
6968 [(set (match_operand:SF 0 "register_operand" "")
6969 (minus:SF (match_operand:SF 1 "register_operand" "")
6970 (match_operand:SF 2 "nonimmediate_operand" "")))]
6971 "TARGET_80387 || TARGET_SSE_MATH"
6974 ;; Multiply instructions
6976 (define_expand "muldi3"
6977 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6978 (mult:DI (match_operand:DI 1 "register_operand" "")
6979 (match_operand:DI 2 "x86_64_general_operand" "")))
6980 (clobber (reg:CC FLAGS_REG))])]
6984 (define_insn "*muldi3_1_rex64"
6985 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6986 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0")
6987 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
6988 (clobber (reg:CC FLAGS_REG))]
6990 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6992 imul{q}\t{%2, %1, %0|%0, %1, %2}
6993 imul{q}\t{%2, %1, %0|%0, %1, %2}
6994 imul{q}\t{%2, %0|%0, %2}"
6995 [(set_attr "type" "imul")
6996 (set_attr "prefix_0f" "0,0,1")
6997 (set (attr "athlon_decode")
6998 (cond [(eq_attr "cpu" "athlon")
6999 (const_string "vector")
7000 (eq_attr "alternative" "1")
7001 (const_string "vector")
7002 (and (eq_attr "alternative" "2")
7003 (match_operand 1 "memory_operand" ""))
7004 (const_string "vector")]
7005 (const_string "direct")))
7006 (set_attr "mode" "DI")])
7008 (define_expand "mulsi3"
7009 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7010 (mult:SI (match_operand:SI 1 "register_operand" "")
7011 (match_operand:SI 2 "general_operand" "")))
7012 (clobber (reg:CC FLAGS_REG))])]
7016 (define_insn "*mulsi3_1"
7017 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7018 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
7019 (match_operand:SI 2 "general_operand" "K,i,mr")))
7020 (clobber (reg:CC FLAGS_REG))]
7021 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7023 imul{l}\t{%2, %1, %0|%0, %1, %2}
7024 imul{l}\t{%2, %1, %0|%0, %1, %2}
7025 imul{l}\t{%2, %0|%0, %2}"
7026 [(set_attr "type" "imul")
7027 (set_attr "prefix_0f" "0,0,1")
7028 (set (attr "athlon_decode")
7029 (cond [(eq_attr "cpu" "athlon")
7030 (const_string "vector")
7031 (eq_attr "alternative" "1")
7032 (const_string "vector")
7033 (and (eq_attr "alternative" "2")
7034 (match_operand 1 "memory_operand" ""))
7035 (const_string "vector")]
7036 (const_string "direct")))
7037 (set_attr "mode" "SI")])
7039 (define_insn "*mulsi3_1_zext"
7040 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7042 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
7043 (match_operand:SI 2 "general_operand" "K,i,mr"))))
7044 (clobber (reg:CC FLAGS_REG))]
7046 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7048 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7049 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7050 imul{l}\t{%2, %k0|%k0, %2}"
7051 [(set_attr "type" "imul")
7052 (set_attr "prefix_0f" "0,0,1")
7053 (set (attr "athlon_decode")
7054 (cond [(eq_attr "cpu" "athlon")
7055 (const_string "vector")
7056 (eq_attr "alternative" "1")
7057 (const_string "vector")
7058 (and (eq_attr "alternative" "2")
7059 (match_operand 1 "memory_operand" ""))
7060 (const_string "vector")]
7061 (const_string "direct")))
7062 (set_attr "mode" "SI")])
7064 (define_expand "mulhi3"
7065 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7066 (mult:HI (match_operand:HI 1 "register_operand" "")
7067 (match_operand:HI 2 "general_operand" "")))
7068 (clobber (reg:CC FLAGS_REG))])]
7069 "TARGET_HIMODE_MATH"
7072 (define_insn "*mulhi3_1"
7073 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
7074 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
7075 (match_operand:HI 2 "general_operand" "K,i,mr")))
7076 (clobber (reg:CC FLAGS_REG))]
7077 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7079 imul{w}\t{%2, %1, %0|%0, %1, %2}
7080 imul{w}\t{%2, %1, %0|%0, %1, %2}
7081 imul{w}\t{%2, %0|%0, %2}"
7082 [(set_attr "type" "imul")
7083 (set_attr "prefix_0f" "0,0,1")
7084 (set (attr "athlon_decode")
7085 (cond [(eq_attr "cpu" "athlon")
7086 (const_string "vector")
7087 (eq_attr "alternative" "1,2")
7088 (const_string "vector")]
7089 (const_string "direct")))
7090 (set_attr "mode" "HI")])
7092 (define_expand "mulqi3"
7093 [(parallel [(set (match_operand:QI 0 "register_operand" "")
7094 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
7095 (match_operand:QI 2 "register_operand" "")))
7096 (clobber (reg:CC FLAGS_REG))])]
7097 "TARGET_QIMODE_MATH"
7100 (define_insn "*mulqi3_1"
7101 [(set (match_operand:QI 0 "register_operand" "=a")
7102 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
7103 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7104 (clobber (reg:CC FLAGS_REG))]
7106 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7108 [(set_attr "type" "imul")
7109 (set_attr "length_immediate" "0")
7110 (set (attr "athlon_decode")
7111 (if_then_else (eq_attr "cpu" "athlon")
7112 (const_string "vector")
7113 (const_string "direct")))
7114 (set_attr "mode" "QI")])
7116 (define_expand "umulqihi3"
7117 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7118 (mult:HI (zero_extend:HI
7119 (match_operand:QI 1 "nonimmediate_operand" ""))
7121 (match_operand:QI 2 "register_operand" ""))))
7122 (clobber (reg:CC FLAGS_REG))])]
7123 "TARGET_QIMODE_MATH"
7126 (define_insn "*umulqihi3_1"
7127 [(set (match_operand:HI 0 "register_operand" "=a")
7128 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7129 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7130 (clobber (reg:CC FLAGS_REG))]
7132 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7134 [(set_attr "type" "imul")
7135 (set_attr "length_immediate" "0")
7136 (set (attr "athlon_decode")
7137 (if_then_else (eq_attr "cpu" "athlon")
7138 (const_string "vector")
7139 (const_string "direct")))
7140 (set_attr "mode" "QI")])
7142 (define_expand "mulqihi3"
7143 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7144 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
7145 (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
7146 (clobber (reg:CC FLAGS_REG))])]
7147 "TARGET_QIMODE_MATH"
7150 (define_insn "*mulqihi3_insn"
7151 [(set (match_operand:HI 0 "register_operand" "=a")
7152 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7153 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7154 (clobber (reg:CC FLAGS_REG))]
7156 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7158 [(set_attr "type" "imul")
7159 (set_attr "length_immediate" "0")
7160 (set (attr "athlon_decode")
7161 (if_then_else (eq_attr "cpu" "athlon")
7162 (const_string "vector")
7163 (const_string "direct")))
7164 (set_attr "mode" "QI")])
7166 (define_expand "umulditi3"
7167 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7168 (mult:TI (zero_extend:TI
7169 (match_operand:DI 1 "nonimmediate_operand" ""))
7171 (match_operand:DI 2 "register_operand" ""))))
7172 (clobber (reg:CC FLAGS_REG))])]
7176 (define_insn "*umulditi3_insn"
7177 [(set (match_operand:TI 0 "register_operand" "=A")
7178 (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7179 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7180 (clobber (reg:CC FLAGS_REG))]
7182 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7184 [(set_attr "type" "imul")
7185 (set_attr "length_immediate" "0")
7186 (set (attr "athlon_decode")
7187 (if_then_else (eq_attr "cpu" "athlon")
7188 (const_string "vector")
7189 (const_string "double")))
7190 (set_attr "mode" "DI")])
7192 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7193 (define_expand "umulsidi3"
7194 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7195 (mult:DI (zero_extend:DI
7196 (match_operand:SI 1 "nonimmediate_operand" ""))
7198 (match_operand:SI 2 "register_operand" ""))))
7199 (clobber (reg:CC FLAGS_REG))])]
7203 (define_insn "*umulsidi3_insn"
7204 [(set (match_operand:DI 0 "register_operand" "=A")
7205 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7206 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7207 (clobber (reg:CC FLAGS_REG))]
7209 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7211 [(set_attr "type" "imul")
7212 (set_attr "length_immediate" "0")
7213 (set (attr "athlon_decode")
7214 (if_then_else (eq_attr "cpu" "athlon")
7215 (const_string "vector")
7216 (const_string "double")))
7217 (set_attr "mode" "SI")])
7219 (define_expand "mulditi3"
7220 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7221 (mult:TI (sign_extend:TI
7222 (match_operand:DI 1 "nonimmediate_operand" ""))
7224 (match_operand:DI 2 "register_operand" ""))))
7225 (clobber (reg:CC FLAGS_REG))])]
7229 (define_insn "*mulditi3_insn"
7230 [(set (match_operand:TI 0 "register_operand" "=A")
7231 (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7232 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7233 (clobber (reg:CC FLAGS_REG))]
7235 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7237 [(set_attr "type" "imul")
7238 (set_attr "length_immediate" "0")
7239 (set (attr "athlon_decode")
7240 (if_then_else (eq_attr "cpu" "athlon")
7241 (const_string "vector")
7242 (const_string "double")))
7243 (set_attr "mode" "DI")])
7245 (define_expand "mulsidi3"
7246 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7247 (mult:DI (sign_extend:DI
7248 (match_operand:SI 1 "nonimmediate_operand" ""))
7250 (match_operand:SI 2 "register_operand" ""))))
7251 (clobber (reg:CC FLAGS_REG))])]
7255 (define_insn "*mulsidi3_insn"
7256 [(set (match_operand:DI 0 "register_operand" "=A")
7257 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7258 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7259 (clobber (reg:CC FLAGS_REG))]
7261 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7263 [(set_attr "type" "imul")
7264 (set_attr "length_immediate" "0")
7265 (set (attr "athlon_decode")
7266 (if_then_else (eq_attr "cpu" "athlon")
7267 (const_string "vector")
7268 (const_string "double")))
7269 (set_attr "mode" "SI")])
7271 (define_expand "umuldi3_highpart"
7272 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7275 (mult:TI (zero_extend:TI
7276 (match_operand:DI 1 "nonimmediate_operand" ""))
7278 (match_operand:DI 2 "register_operand" "")))
7280 (clobber (match_scratch:DI 3 ""))
7281 (clobber (reg:CC FLAGS_REG))])]
7285 (define_insn "*umuldi3_highpart_rex64"
7286 [(set (match_operand:DI 0 "register_operand" "=d")
7289 (mult:TI (zero_extend:TI
7290 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7292 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7294 (clobber (match_scratch:DI 3 "=1"))
7295 (clobber (reg:CC FLAGS_REG))]
7297 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7299 [(set_attr "type" "imul")
7300 (set_attr "length_immediate" "0")
7301 (set (attr "athlon_decode")
7302 (if_then_else (eq_attr "cpu" "athlon")
7303 (const_string "vector")
7304 (const_string "double")))
7305 (set_attr "mode" "DI")])
7307 (define_expand "umulsi3_highpart"
7308 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7311 (mult:DI (zero_extend:DI
7312 (match_operand:SI 1 "nonimmediate_operand" ""))
7314 (match_operand:SI 2 "register_operand" "")))
7316 (clobber (match_scratch:SI 3 ""))
7317 (clobber (reg:CC FLAGS_REG))])]
7321 (define_insn "*umulsi3_highpart_insn"
7322 [(set (match_operand:SI 0 "register_operand" "=d")
7325 (mult:DI (zero_extend:DI
7326 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7328 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7330 (clobber (match_scratch:SI 3 "=1"))
7331 (clobber (reg:CC FLAGS_REG))]
7332 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7334 [(set_attr "type" "imul")
7335 (set_attr "length_immediate" "0")
7336 (set (attr "athlon_decode")
7337 (if_then_else (eq_attr "cpu" "athlon")
7338 (const_string "vector")
7339 (const_string "double")))
7340 (set_attr "mode" "SI")])
7342 (define_insn "*umulsi3_highpart_zext"
7343 [(set (match_operand:DI 0 "register_operand" "=d")
7344 (zero_extend:DI (truncate:SI
7346 (mult:DI (zero_extend:DI
7347 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7349 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7351 (clobber (match_scratch:SI 3 "=1"))
7352 (clobber (reg:CC FLAGS_REG))]
7354 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7356 [(set_attr "type" "imul")
7357 (set_attr "length_immediate" "0")
7358 (set (attr "athlon_decode")
7359 (if_then_else (eq_attr "cpu" "athlon")
7360 (const_string "vector")
7361 (const_string "double")))
7362 (set_attr "mode" "SI")])
7364 (define_expand "smuldi3_highpart"
7365 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
7368 (mult:TI (sign_extend:TI
7369 (match_operand:DI 1 "nonimmediate_operand" ""))
7371 (match_operand:DI 2 "register_operand" "")))
7373 (clobber (match_scratch:DI 3 ""))
7374 (clobber (reg:CC FLAGS_REG))])]
7378 (define_insn "*smuldi3_highpart_rex64"
7379 [(set (match_operand:DI 0 "register_operand" "=d")
7382 (mult:TI (sign_extend:TI
7383 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7385 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7387 (clobber (match_scratch:DI 3 "=1"))
7388 (clobber (reg:CC FLAGS_REG))]
7390 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7392 [(set_attr "type" "imul")
7393 (set (attr "athlon_decode")
7394 (if_then_else (eq_attr "cpu" "athlon")
7395 (const_string "vector")
7396 (const_string "double")))
7397 (set_attr "mode" "DI")])
7399 (define_expand "smulsi3_highpart"
7400 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7403 (mult:DI (sign_extend:DI
7404 (match_operand:SI 1 "nonimmediate_operand" ""))
7406 (match_operand:SI 2 "register_operand" "")))
7408 (clobber (match_scratch:SI 3 ""))
7409 (clobber (reg:CC FLAGS_REG))])]
7413 (define_insn "*smulsi3_highpart_insn"
7414 [(set (match_operand:SI 0 "register_operand" "=d")
7417 (mult:DI (sign_extend:DI
7418 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7420 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7422 (clobber (match_scratch:SI 3 "=1"))
7423 (clobber (reg:CC FLAGS_REG))]
7424 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7426 [(set_attr "type" "imul")
7427 (set (attr "athlon_decode")
7428 (if_then_else (eq_attr "cpu" "athlon")
7429 (const_string "vector")
7430 (const_string "double")))
7431 (set_attr "mode" "SI")])
7433 (define_insn "*smulsi3_highpart_zext"
7434 [(set (match_operand:DI 0 "register_operand" "=d")
7435 (zero_extend:DI (truncate:SI
7437 (mult:DI (sign_extend:DI
7438 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7440 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7442 (clobber (match_scratch:SI 3 "=1"))
7443 (clobber (reg:CC FLAGS_REG))]
7445 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7447 [(set_attr "type" "imul")
7448 (set (attr "athlon_decode")
7449 (if_then_else (eq_attr "cpu" "athlon")
7450 (const_string "vector")
7451 (const_string "double")))
7452 (set_attr "mode" "SI")])
7454 ;; The patterns that match these are at the end of this file.
7456 (define_expand "mulxf3"
7457 [(set (match_operand:XF 0 "register_operand" "")
7458 (mult:XF (match_operand:XF 1 "register_operand" "")
7459 (match_operand:XF 2 "register_operand" "")))]
7463 (define_expand "muldf3"
7464 [(set (match_operand:DF 0 "register_operand" "")
7465 (mult:DF (match_operand:DF 1 "register_operand" "")
7466 (match_operand:DF 2 "nonimmediate_operand" "")))]
7467 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7470 (define_expand "mulsf3"
7471 [(set (match_operand:SF 0 "register_operand" "")
7472 (mult:SF (match_operand:SF 1 "register_operand" "")
7473 (match_operand:SF 2 "nonimmediate_operand" "")))]
7474 "TARGET_80387 || TARGET_SSE_MATH"
7477 ;; Divide instructions
7479 (define_insn "divqi3"
7480 [(set (match_operand:QI 0 "register_operand" "=a")
7481 (div:QI (match_operand:HI 1 "register_operand" "0")
7482 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7483 (clobber (reg:CC FLAGS_REG))]
7484 "TARGET_QIMODE_MATH"
7486 [(set_attr "type" "idiv")
7487 (set_attr "mode" "QI")])
7489 (define_insn "udivqi3"
7490 [(set (match_operand:QI 0 "register_operand" "=a")
7491 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7492 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7493 (clobber (reg:CC FLAGS_REG))]
7494 "TARGET_QIMODE_MATH"
7496 [(set_attr "type" "idiv")
7497 (set_attr "mode" "QI")])
7499 ;; The patterns that match these are at the end of this file.
7501 (define_expand "divxf3"
7502 [(set (match_operand:XF 0 "register_operand" "")
7503 (div:XF (match_operand:XF 1 "register_operand" "")
7504 (match_operand:XF 2 "register_operand" "")))]
7508 (define_expand "divdf3"
7509 [(set (match_operand:DF 0 "register_operand" "")
7510 (div:DF (match_operand:DF 1 "register_operand" "")
7511 (match_operand:DF 2 "nonimmediate_operand" "")))]
7512 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7515 (define_expand "divsf3"
7516 [(set (match_operand:SF 0 "register_operand" "")
7517 (div:SF (match_operand:SF 1 "register_operand" "")
7518 (match_operand:SF 2 "nonimmediate_operand" "")))]
7519 "TARGET_80387 || TARGET_SSE_MATH"
7522 ;; Remainder instructions.
7524 (define_expand "divmoddi4"
7525 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7526 (div:DI (match_operand:DI 1 "register_operand" "")
7527 (match_operand:DI 2 "nonimmediate_operand" "")))
7528 (set (match_operand:DI 3 "register_operand" "")
7529 (mod:DI (match_dup 1) (match_dup 2)))
7530 (clobber (reg:CC FLAGS_REG))])]
7534 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7535 ;; Penalize eax case slightly because it results in worse scheduling
7537 (define_insn "*divmoddi4_nocltd_rex64"
7538 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7539 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7540 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7541 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7542 (mod:DI (match_dup 2) (match_dup 3)))
7543 (clobber (reg:CC FLAGS_REG))]
7544 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7546 [(set_attr "type" "multi")])
7548 (define_insn "*divmoddi4_cltd_rex64"
7549 [(set (match_operand:DI 0 "register_operand" "=a")
7550 (div:DI (match_operand:DI 2 "register_operand" "a")
7551 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7552 (set (match_operand:DI 1 "register_operand" "=&d")
7553 (mod:DI (match_dup 2) (match_dup 3)))
7554 (clobber (reg:CC FLAGS_REG))]
7555 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7557 [(set_attr "type" "multi")])
7559 (define_insn "*divmoddi_noext_rex64"
7560 [(set (match_operand:DI 0 "register_operand" "=a")
7561 (div:DI (match_operand:DI 1 "register_operand" "0")
7562 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7563 (set (match_operand:DI 3 "register_operand" "=d")
7564 (mod:DI (match_dup 1) (match_dup 2)))
7565 (use (match_operand:DI 4 "register_operand" "3"))
7566 (clobber (reg:CC FLAGS_REG))]
7569 [(set_attr "type" "idiv")
7570 (set_attr "mode" "DI")])
7573 [(set (match_operand:DI 0 "register_operand" "")
7574 (div:DI (match_operand:DI 1 "register_operand" "")
7575 (match_operand:DI 2 "nonimmediate_operand" "")))
7576 (set (match_operand:DI 3 "register_operand" "")
7577 (mod:DI (match_dup 1) (match_dup 2)))
7578 (clobber (reg:CC FLAGS_REG))]
7579 "TARGET_64BIT && reload_completed"
7580 [(parallel [(set (match_dup 3)
7581 (ashiftrt:DI (match_dup 4) (const_int 63)))
7582 (clobber (reg:CC FLAGS_REG))])
7583 (parallel [(set (match_dup 0)
7584 (div:DI (reg:DI 0) (match_dup 2)))
7586 (mod:DI (reg:DI 0) (match_dup 2)))
7588 (clobber (reg:CC FLAGS_REG))])]
7590 /* Avoid use of cltd in favor of a mov+shift. */
7591 if (!TARGET_USE_CLTD && !optimize_size)
7593 if (true_regnum (operands[1]))
7594 emit_move_insn (operands[0], operands[1]);
7596 emit_move_insn (operands[3], operands[1]);
7597 operands[4] = operands[3];
7601 if (true_regnum (operands[1]))
7603 operands[4] = operands[1];
7608 (define_expand "divmodsi4"
7609 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7610 (div:SI (match_operand:SI 1 "register_operand" "")
7611 (match_operand:SI 2 "nonimmediate_operand" "")))
7612 (set (match_operand:SI 3 "register_operand" "")
7613 (mod:SI (match_dup 1) (match_dup 2)))
7614 (clobber (reg:CC FLAGS_REG))])]
7618 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7619 ;; Penalize eax case slightly because it results in worse scheduling
7621 (define_insn "*divmodsi4_nocltd"
7622 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7623 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7624 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7625 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7626 (mod:SI (match_dup 2) (match_dup 3)))
7627 (clobber (reg:CC FLAGS_REG))]
7628 "!optimize_size && !TARGET_USE_CLTD"
7630 [(set_attr "type" "multi")])
7632 (define_insn "*divmodsi4_cltd"
7633 [(set (match_operand:SI 0 "register_operand" "=a")
7634 (div:SI (match_operand:SI 2 "register_operand" "a")
7635 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7636 (set (match_operand:SI 1 "register_operand" "=&d")
7637 (mod:SI (match_dup 2) (match_dup 3)))
7638 (clobber (reg:CC FLAGS_REG))]
7639 "optimize_size || TARGET_USE_CLTD"
7641 [(set_attr "type" "multi")])
7643 (define_insn "*divmodsi_noext"
7644 [(set (match_operand:SI 0 "register_operand" "=a")
7645 (div:SI (match_operand:SI 1 "register_operand" "0")
7646 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7647 (set (match_operand:SI 3 "register_operand" "=d")
7648 (mod:SI (match_dup 1) (match_dup 2)))
7649 (use (match_operand:SI 4 "register_operand" "3"))
7650 (clobber (reg:CC FLAGS_REG))]
7653 [(set_attr "type" "idiv")
7654 (set_attr "mode" "SI")])
7657 [(set (match_operand:SI 0 "register_operand" "")
7658 (div:SI (match_operand:SI 1 "register_operand" "")
7659 (match_operand:SI 2 "nonimmediate_operand" "")))
7660 (set (match_operand:SI 3 "register_operand" "")
7661 (mod:SI (match_dup 1) (match_dup 2)))
7662 (clobber (reg:CC FLAGS_REG))]
7664 [(parallel [(set (match_dup 3)
7665 (ashiftrt:SI (match_dup 4) (const_int 31)))
7666 (clobber (reg:CC FLAGS_REG))])
7667 (parallel [(set (match_dup 0)
7668 (div:SI (reg:SI 0) (match_dup 2)))
7670 (mod:SI (reg:SI 0) (match_dup 2)))
7672 (clobber (reg:CC FLAGS_REG))])]
7674 /* Avoid use of cltd in favor of a mov+shift. */
7675 if (!TARGET_USE_CLTD && !optimize_size)
7677 if (true_regnum (operands[1]))
7678 emit_move_insn (operands[0], operands[1]);
7680 emit_move_insn (operands[3], operands[1]);
7681 operands[4] = operands[3];
7685 if (true_regnum (operands[1]))
7687 operands[4] = operands[1];
7691 (define_insn "divmodhi4"
7692 [(set (match_operand:HI 0 "register_operand" "=a")
7693 (div:HI (match_operand:HI 1 "register_operand" "0")
7694 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7695 (set (match_operand:HI 3 "register_operand" "=&d")
7696 (mod:HI (match_dup 1) (match_dup 2)))
7697 (clobber (reg:CC FLAGS_REG))]
7698 "TARGET_HIMODE_MATH"
7700 [(set_attr "type" "multi")
7701 (set_attr "length_immediate" "0")
7702 (set_attr "mode" "SI")])
7704 (define_insn "udivmoddi4"
7705 [(set (match_operand:DI 0 "register_operand" "=a")
7706 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7707 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7708 (set (match_operand:DI 3 "register_operand" "=&d")
7709 (umod:DI (match_dup 1) (match_dup 2)))
7710 (clobber (reg:CC FLAGS_REG))]
7712 "xor{q}\t%3, %3\;div{q}\t%2"
7713 [(set_attr "type" "multi")
7714 (set_attr "length_immediate" "0")
7715 (set_attr "mode" "DI")])
7717 (define_insn "*udivmoddi4_noext"
7718 [(set (match_operand:DI 0 "register_operand" "=a")
7719 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7720 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7721 (set (match_operand:DI 3 "register_operand" "=d")
7722 (umod:DI (match_dup 1) (match_dup 2)))
7724 (clobber (reg:CC FLAGS_REG))]
7727 [(set_attr "type" "idiv")
7728 (set_attr "mode" "DI")])
7731 [(set (match_operand:DI 0 "register_operand" "")
7732 (udiv:DI (match_operand:DI 1 "register_operand" "")
7733 (match_operand:DI 2 "nonimmediate_operand" "")))
7734 (set (match_operand:DI 3 "register_operand" "")
7735 (umod:DI (match_dup 1) (match_dup 2)))
7736 (clobber (reg:CC FLAGS_REG))]
7737 "TARGET_64BIT && reload_completed"
7738 [(set (match_dup 3) (const_int 0))
7739 (parallel [(set (match_dup 0)
7740 (udiv:DI (match_dup 1) (match_dup 2)))
7742 (umod:DI (match_dup 1) (match_dup 2)))
7744 (clobber (reg:CC FLAGS_REG))])]
7747 (define_insn "udivmodsi4"
7748 [(set (match_operand:SI 0 "register_operand" "=a")
7749 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7750 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7751 (set (match_operand:SI 3 "register_operand" "=&d")
7752 (umod:SI (match_dup 1) (match_dup 2)))
7753 (clobber (reg:CC FLAGS_REG))]
7755 "xor{l}\t%3, %3\;div{l}\t%2"
7756 [(set_attr "type" "multi")
7757 (set_attr "length_immediate" "0")
7758 (set_attr "mode" "SI")])
7760 (define_insn "*udivmodsi4_noext"
7761 [(set (match_operand:SI 0 "register_operand" "=a")
7762 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7763 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7764 (set (match_operand:SI 3 "register_operand" "=d")
7765 (umod:SI (match_dup 1) (match_dup 2)))
7767 (clobber (reg:CC FLAGS_REG))]
7770 [(set_attr "type" "idiv")
7771 (set_attr "mode" "SI")])
7774 [(set (match_operand:SI 0 "register_operand" "")
7775 (udiv:SI (match_operand:SI 1 "register_operand" "")
7776 (match_operand:SI 2 "nonimmediate_operand" "")))
7777 (set (match_operand:SI 3 "register_operand" "")
7778 (umod:SI (match_dup 1) (match_dup 2)))
7779 (clobber (reg:CC FLAGS_REG))]
7781 [(set (match_dup 3) (const_int 0))
7782 (parallel [(set (match_dup 0)
7783 (udiv:SI (match_dup 1) (match_dup 2)))
7785 (umod:SI (match_dup 1) (match_dup 2)))
7787 (clobber (reg:CC FLAGS_REG))])]
7790 (define_expand "udivmodhi4"
7791 [(set (match_dup 4) (const_int 0))
7792 (parallel [(set (match_operand:HI 0 "register_operand" "")
7793 (udiv:HI (match_operand:HI 1 "register_operand" "")
7794 (match_operand:HI 2 "nonimmediate_operand" "")))
7795 (set (match_operand:HI 3 "register_operand" "")
7796 (umod:HI (match_dup 1) (match_dup 2)))
7798 (clobber (reg:CC FLAGS_REG))])]
7799 "TARGET_HIMODE_MATH"
7800 "operands[4] = gen_reg_rtx (HImode);")
7802 (define_insn "*udivmodhi_noext"
7803 [(set (match_operand:HI 0 "register_operand" "=a")
7804 (udiv:HI (match_operand:HI 1 "register_operand" "0")
7805 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7806 (set (match_operand:HI 3 "register_operand" "=d")
7807 (umod:HI (match_dup 1) (match_dup 2)))
7808 (use (match_operand:HI 4 "register_operand" "3"))
7809 (clobber (reg:CC FLAGS_REG))]
7812 [(set_attr "type" "idiv")
7813 (set_attr "mode" "HI")])
7815 ;; We cannot use div/idiv for double division, because it causes
7816 ;; "division by zero" on the overflow and that's not what we expect
7817 ;; from truncate. Because true (non truncating) double division is
7818 ;; never generated, we can't create this insn anyway.
7821 ; [(set (match_operand:SI 0 "register_operand" "=a")
7823 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
7825 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
7826 ; (set (match_operand:SI 3 "register_operand" "=d")
7828 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
7829 ; (clobber (reg:CC FLAGS_REG))]
7831 ; "div{l}\t{%2, %0|%0, %2}"
7832 ; [(set_attr "type" "idiv")])
7834 ;;- Logical AND instructions
7836 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
7837 ;; Note that this excludes ah.
7839 (define_insn "*testdi_1_rex64"
7842 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%!*a,r,!*a,r,rm")
7843 (match_operand:DI 1 "x86_64_szext_general_operand" "Z,Z,e,e,re"))
7845 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7846 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7848 test{l}\t{%k1, %k0|%k0, %k1}
7849 test{l}\t{%k1, %k0|%k0, %k1}
7850 test{q}\t{%1, %0|%0, %1}
7851 test{q}\t{%1, %0|%0, %1}
7852 test{q}\t{%1, %0|%0, %1}"
7853 [(set_attr "type" "test")
7854 (set_attr "modrm" "0,1,0,1,1")
7855 (set_attr "mode" "SI,SI,DI,DI,DI")
7856 (set_attr "pent_pair" "uv,np,uv,np,uv")])
7858 (define_insn "testsi_1"
7861 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%!*a,r,rm")
7862 (match_operand:SI 1 "general_operand" "in,in,rin"))
7864 "ix86_match_ccmode (insn, CCNOmode)
7865 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7866 "test{l}\t{%1, %0|%0, %1}"
7867 [(set_attr "type" "test")
7868 (set_attr "modrm" "0,1,1")
7869 (set_attr "mode" "SI")
7870 (set_attr "pent_pair" "uv,np,uv")])
7872 (define_expand "testsi_ccno_1"
7873 [(set (reg:CCNO FLAGS_REG)
7875 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
7876 (match_operand:SI 1 "nonmemory_operand" ""))
7881 (define_insn "*testhi_1"
7883 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%!*a,r,rm")
7884 (match_operand:HI 1 "general_operand" "n,n,rn"))
7886 "ix86_match_ccmode (insn, CCNOmode)
7887 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7888 "test{w}\t{%1, %0|%0, %1}"
7889 [(set_attr "type" "test")
7890 (set_attr "modrm" "0,1,1")
7891 (set_attr "mode" "HI")
7892 (set_attr "pent_pair" "uv,np,uv")])
7894 (define_expand "testqi_ccz_1"
7895 [(set (reg:CCZ FLAGS_REG)
7896 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
7897 (match_operand:QI 1 "nonmemory_operand" ""))
7902 (define_insn "*testqi_1"
7903 [(set (reg FLAGS_REG)
7904 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm,r")
7905 (match_operand:QI 1 "general_operand" "n,n,qn,n"))
7907 "ix86_match_ccmode (insn, CCNOmode)
7908 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7910 if (which_alternative == 3)
7912 if (GET_CODE (operands[1]) == CONST_INT
7913 && (INTVAL (operands[1]) & 0xffffff00))
7914 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
7915 return "test{l}\t{%1, %k0|%k0, %1}";
7917 return "test{b}\t{%1, %0|%0, %1}";
7919 [(set_attr "type" "test")
7920 (set_attr "modrm" "0,1,1,1")
7921 (set_attr "mode" "QI,QI,QI,SI")
7922 (set_attr "pent_pair" "uv,np,uv,np")])
7924 (define_expand "testqi_ext_ccno_0"
7925 [(set (reg:CCNO FLAGS_REG)
7929 (match_operand 0 "ext_register_operand" "")
7932 (match_operand 1 "const_int_operand" ""))
7937 (define_insn "*testqi_ext_0"
7942 (match_operand 0 "ext_register_operand" "Q")
7945 (match_operand 1 "const_int_operand" "n"))
7947 "ix86_match_ccmode (insn, CCNOmode)"
7948 "test{b}\t{%1, %h0|%h0, %1}"
7949 [(set_attr "type" "test")
7950 (set_attr "mode" "QI")
7951 (set_attr "length_immediate" "1")
7952 (set_attr "pent_pair" "np")])
7954 (define_insn "*testqi_ext_1"
7959 (match_operand 0 "ext_register_operand" "Q")
7963 (match_operand:QI 1 "general_operand" "Qm")))
7965 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7966 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7967 "test{b}\t{%1, %h0|%h0, %1}"
7968 [(set_attr "type" "test")
7969 (set_attr "mode" "QI")])
7971 (define_insn "*testqi_ext_1_rex64"
7976 (match_operand 0 "ext_register_operand" "Q")
7980 (match_operand:QI 1 "register_operand" "Q")))
7982 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7983 "test{b}\t{%1, %h0|%h0, %1}"
7984 [(set_attr "type" "test")
7985 (set_attr "mode" "QI")])
7987 (define_insn "*testqi_ext_2"
7992 (match_operand 0 "ext_register_operand" "Q")
7996 (match_operand 1 "ext_register_operand" "Q")
8000 "ix86_match_ccmode (insn, CCNOmode)"
8001 "test{b}\t{%h1, %h0|%h0, %h1}"
8002 [(set_attr "type" "test")
8003 (set_attr "mode" "QI")])
8005 ;; Combine likes to form bit extractions for some tests. Humor it.
8006 (define_insn "*testqi_ext_3"
8008 (compare (zero_extract:SI
8009 (match_operand 0 "nonimmediate_operand" "rm")
8010 (match_operand:SI 1 "const_int_operand" "")
8011 (match_operand:SI 2 "const_int_operand" ""))
8013 "ix86_match_ccmode (insn, CCNOmode)
8014 && (GET_MODE (operands[0]) == SImode
8015 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
8016 || GET_MODE (operands[0]) == HImode
8017 || GET_MODE (operands[0]) == QImode)"
8020 (define_insn "*testqi_ext_3_rex64"
8022 (compare (zero_extract:DI
8023 (match_operand 0 "nonimmediate_operand" "rm")
8024 (match_operand:DI 1 "const_int_operand" "")
8025 (match_operand:DI 2 "const_int_operand" ""))
8028 && ix86_match_ccmode (insn, CCNOmode)
8029 /* The code below cannot deal with constants outside HOST_WIDE_INT. */
8030 && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT
8031 /* Ensure that resulting mask is zero or sign extended operand. */
8032 && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
8033 || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64
8034 && INTVAL (operands[1]) > 32))
8035 && (GET_MODE (operands[0]) == SImode
8036 || GET_MODE (operands[0]) == DImode
8037 || GET_MODE (operands[0]) == HImode
8038 || GET_MODE (operands[0]) == QImode)"
8043 (compare (zero_extract
8044 (match_operand 0 "nonimmediate_operand" "")
8045 (match_operand 1 "const_int_operand" "")
8046 (match_operand 2 "const_int_operand" ""))
8048 "ix86_match_ccmode (insn, CCNOmode)"
8049 [(set (reg:CCNO FLAGS_REG) (compare:CCNO (match_dup 3) (const_int 0)))]
8051 HOST_WIDE_INT len = INTVAL (operands[1]);
8052 HOST_WIDE_INT pos = INTVAL (operands[2]);
8054 enum machine_mode mode, submode;
8056 mode = GET_MODE (operands[0]);
8057 if (GET_CODE (operands[0]) == MEM)
8059 /* ??? Combine likes to put non-volatile mem extractions in QImode
8060 no matter the size of the test. So find a mode that works. */
8061 if (! MEM_VOLATILE_P (operands[0]))
8063 mode = smallest_mode_for_size (pos + len, MODE_INT);
8064 operands[0] = adjust_address (operands[0], mode, 0);
8067 else if (GET_CODE (operands[0]) == SUBREG
8068 && (submode = GET_MODE (SUBREG_REG (operands[0])),
8069 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
8070 && pos + len <= GET_MODE_BITSIZE (submode))
8072 /* Narrow a paradoxical subreg to prevent partial register stalls. */
8074 operands[0] = SUBREG_REG (operands[0]);
8076 else if (mode == HImode && pos + len <= 8)
8078 /* Small HImode tests can be converted to QImode. */
8080 operands[0] = gen_lowpart (QImode, operands[0]);
8083 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
8084 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
8086 operands[3] = gen_rtx_AND (mode, operands[0], gen_int_mode (mask, mode));
8089 ;; Convert HImode/SImode test instructions with immediate to QImode ones.
8090 ;; i386 does not allow to encode test with 8bit sign extended immediate, so
8091 ;; this is relatively important trick.
8092 ;; Do the conversion only post-reload to avoid limiting of the register class
8097 (and (match_operand 0 "register_operand" "")
8098 (match_operand 1 "const_int_operand" ""))
8101 && QI_REG_P (operands[0])
8102 && ((ix86_match_ccmode (insn, CCZmode)
8103 && !(INTVAL (operands[1]) & ~(255 << 8)))
8104 || (ix86_match_ccmode (insn, CCNOmode)
8105 && !(INTVAL (operands[1]) & ~(127 << 8))))
8106 && GET_MODE (operands[0]) != QImode"
8107 [(set (reg:CCNO FLAGS_REG)
8109 (and:SI (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8112 "operands[0] = gen_lowpart (SImode, operands[0]);
8113 operands[1] = gen_int_mode (INTVAL (operands[1]) >> 8, SImode);")
8118 (and (match_operand 0 "nonimmediate_operand" "")
8119 (match_operand 1 "const_int_operand" ""))
8122 && (!REG_P (operands[0]) || ANY_QI_REG_P (operands[0]))
8123 && ((ix86_match_ccmode (insn, CCZmode)
8124 && !(INTVAL (operands[1]) & ~255))
8125 || (ix86_match_ccmode (insn, CCNOmode)
8126 && !(INTVAL (operands[1]) & ~127)))
8127 && GET_MODE (operands[0]) != QImode"
8128 [(set (reg:CCNO FLAGS_REG)
8130 (and:QI (match_dup 0)
8133 "operands[0] = gen_lowpart (QImode, operands[0]);
8134 operands[1] = gen_lowpart (QImode, operands[1]);")
8137 ;; %%% This used to optimize known byte-wide and operations to memory,
8138 ;; and sometimes to QImode registers. If this is considered useful,
8139 ;; it should be done with splitters.
8141 (define_expand "anddi3"
8142 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8143 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
8144 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
8145 (clobber (reg:CC FLAGS_REG))]
8147 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
8149 (define_insn "*anddi_1_rex64"
8150 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
8151 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
8152 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
8153 (clobber (reg:CC FLAGS_REG))]
8154 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
8156 switch (get_attr_type (insn))
8160 enum machine_mode mode;
8162 if (GET_CODE (operands[2]) != CONST_INT)
8164 if (INTVAL (operands[2]) == 0xff)
8166 else if (INTVAL (operands[2]) == 0xffff)
8171 operands[1] = gen_lowpart (mode, operands[1]);
8173 return "movz{bq|x}\t{%1,%0|%0, %1}";
8175 return "movz{wq|x}\t{%1,%0|%0, %1}";
8179 if (! rtx_equal_p (operands[0], operands[1]))
8181 if (get_attr_mode (insn) == MODE_SI)
8182 return "and{l}\t{%k2, %k0|%k0, %k2}";
8184 return "and{q}\t{%2, %0|%0, %2}";
8187 [(set_attr "type" "alu,alu,alu,imovx")
8188 (set_attr "length_immediate" "*,*,*,0")
8189 (set_attr "mode" "SI,DI,DI,DI")])
8191 (define_insn "*anddi_2"
8193 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
8194 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
8196 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
8197 (and:DI (match_dup 1) (match_dup 2)))]
8198 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8199 && ix86_binary_operator_ok (AND, DImode, operands)"
8201 and{l}\t{%k2, %k0|%k0, %k2}
8202 and{q}\t{%2, %0|%0, %2}
8203 and{q}\t{%2, %0|%0, %2}"
8204 [(set_attr "type" "alu")
8205 (set_attr "mode" "SI,DI,DI")])
8207 (define_expand "andsi3"
8208 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8209 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
8210 (match_operand:SI 2 "general_operand" "")))
8211 (clobber (reg:CC FLAGS_REG))]
8213 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
8215 (define_insn "*andsi_1"
8216 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
8217 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
8218 (match_operand:SI 2 "general_operand" "ri,rm,L")))
8219 (clobber (reg:CC FLAGS_REG))]
8220 "ix86_binary_operator_ok (AND, SImode, operands)"
8222 switch (get_attr_type (insn))
8226 enum machine_mode mode;
8228 if (GET_CODE (operands[2]) != CONST_INT)
8230 if (INTVAL (operands[2]) == 0xff)
8232 else if (INTVAL (operands[2]) == 0xffff)
8237 operands[1] = gen_lowpart (mode, operands[1]);
8239 return "movz{bl|x}\t{%1,%0|%0, %1}";
8241 return "movz{wl|x}\t{%1,%0|%0, %1}";
8245 if (! rtx_equal_p (operands[0], operands[1]))
8247 return "and{l}\t{%2, %0|%0, %2}";
8250 [(set_attr "type" "alu,alu,imovx")
8251 (set_attr "length_immediate" "*,*,0")
8252 (set_attr "mode" "SI")])
8255 [(set (match_operand 0 "register_operand" "")
8257 (const_int -65536)))
8258 (clobber (reg:CC FLAGS_REG))]
8259 "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
8260 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8261 "operands[1] = gen_lowpart (HImode, operands[0]);")
8264 [(set (match_operand 0 "ext_register_operand" "")
8267 (clobber (reg:CC FLAGS_REG))]
8268 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8269 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8270 "operands[1] = gen_lowpart (QImode, operands[0]);")
8273 [(set (match_operand 0 "ext_register_operand" "")
8275 (const_int -65281)))
8276 (clobber (reg:CC FLAGS_REG))]
8277 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8278 [(parallel [(set (zero_extract:SI (match_dup 0)
8282 (zero_extract:SI (match_dup 0)
8285 (zero_extract:SI (match_dup 0)
8288 (clobber (reg:CC FLAGS_REG))])]
8289 "operands[0] = gen_lowpart (SImode, operands[0]);")
8291 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8292 (define_insn "*andsi_1_zext"
8293 [(set (match_operand:DI 0 "register_operand" "=r")
8295 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8296 (match_operand:SI 2 "general_operand" "rim"))))
8297 (clobber (reg:CC FLAGS_REG))]
8298 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
8299 "and{l}\t{%2, %k0|%k0, %2}"
8300 [(set_attr "type" "alu")
8301 (set_attr "mode" "SI")])
8303 (define_insn "*andsi_2"
8305 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8306 (match_operand:SI 2 "general_operand" "rim,ri"))
8308 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8309 (and:SI (match_dup 1) (match_dup 2)))]
8310 "ix86_match_ccmode (insn, CCNOmode)
8311 && ix86_binary_operator_ok (AND, SImode, operands)"
8312 "and{l}\t{%2, %0|%0, %2}"
8313 [(set_attr "type" "alu")
8314 (set_attr "mode" "SI")])
8316 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8317 (define_insn "*andsi_2_zext"
8319 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8320 (match_operand:SI 2 "general_operand" "rim"))
8322 (set (match_operand:DI 0 "register_operand" "=r")
8323 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
8324 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8325 && ix86_binary_operator_ok (AND, SImode, operands)"
8326 "and{l}\t{%2, %k0|%k0, %2}"
8327 [(set_attr "type" "alu")
8328 (set_attr "mode" "SI")])
8330 (define_expand "andhi3"
8331 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8332 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
8333 (match_operand:HI 2 "general_operand" "")))
8334 (clobber (reg:CC FLAGS_REG))]
8335 "TARGET_HIMODE_MATH"
8336 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8338 (define_insn "*andhi_1"
8339 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8340 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8341 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8342 (clobber (reg:CC FLAGS_REG))]
8343 "ix86_binary_operator_ok (AND, HImode, operands)"
8345 switch (get_attr_type (insn))
8348 if (GET_CODE (operands[2]) != CONST_INT)
8350 if (INTVAL (operands[2]) == 0xff)
8351 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
8355 if (! rtx_equal_p (operands[0], operands[1]))
8358 return "and{w}\t{%2, %0|%0, %2}";
8361 [(set_attr "type" "alu,alu,imovx")
8362 (set_attr "length_immediate" "*,*,0")
8363 (set_attr "mode" "HI,HI,SI")])
8365 (define_insn "*andhi_2"
8367 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8368 (match_operand:HI 2 "general_operand" "rim,ri"))
8370 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8371 (and:HI (match_dup 1) (match_dup 2)))]
8372 "ix86_match_ccmode (insn, CCNOmode)
8373 && ix86_binary_operator_ok (AND, HImode, operands)"
8374 "and{w}\t{%2, %0|%0, %2}"
8375 [(set_attr "type" "alu")
8376 (set_attr "mode" "HI")])
8378 (define_expand "andqi3"
8379 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8380 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8381 (match_operand:QI 2 "general_operand" "")))
8382 (clobber (reg:CC FLAGS_REG))]
8383 "TARGET_QIMODE_MATH"
8384 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8386 ;; %%% Potential partial reg stall on alternative 2. What to do?
8387 (define_insn "*andqi_1"
8388 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8389 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8390 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8391 (clobber (reg:CC FLAGS_REG))]
8392 "ix86_binary_operator_ok (AND, QImode, operands)"
8394 and{b}\t{%2, %0|%0, %2}
8395 and{b}\t{%2, %0|%0, %2}
8396 and{l}\t{%k2, %k0|%k0, %k2}"
8397 [(set_attr "type" "alu")
8398 (set_attr "mode" "QI,QI,SI")])
8400 (define_insn "*andqi_1_slp"
8401 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8402 (and:QI (match_dup 0)
8403 (match_operand:QI 1 "general_operand" "qi,qmi")))
8404 (clobber (reg:CC FLAGS_REG))]
8405 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8406 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8407 "and{b}\t{%1, %0|%0, %1}"
8408 [(set_attr "type" "alu1")
8409 (set_attr "mode" "QI")])
8411 (define_insn "*andqi_2"
8414 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8415 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8417 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8418 (and:QI (match_dup 1) (match_dup 2)))]
8419 "ix86_match_ccmode (insn, CCNOmode)
8420 && ix86_binary_operator_ok (AND, QImode, operands)"
8422 if (which_alternative == 2)
8424 if (GET_CODE (operands[2]) == CONST_INT
8425 && (INTVAL (operands[2]) & 0xffffff00))
8426 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8427 return "and{l}\t{%2, %k0|%k0, %2}";
8429 return "and{b}\t{%2, %0|%0, %2}";
8431 [(set_attr "type" "alu")
8432 (set_attr "mode" "QI,QI,SI")])
8434 (define_insn "*andqi_2_slp"
8437 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8438 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8440 (set (strict_low_part (match_dup 0))
8441 (and:QI (match_dup 0) (match_dup 1)))]
8442 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8443 && ix86_match_ccmode (insn, CCNOmode)
8444 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8445 "and{b}\t{%1, %0|%0, %1}"
8446 [(set_attr "type" "alu1")
8447 (set_attr "mode" "QI")])
8449 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8450 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8451 ;; for a QImode operand, which of course failed.
8453 (define_insn "andqi_ext_0"
8454 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8459 (match_operand 1 "ext_register_operand" "0")
8462 (match_operand 2 "const_int_operand" "n")))
8463 (clobber (reg:CC FLAGS_REG))]
8465 "and{b}\t{%2, %h0|%h0, %2}"
8466 [(set_attr "type" "alu")
8467 (set_attr "length_immediate" "1")
8468 (set_attr "mode" "QI")])
8470 ;; Generated by peephole translating test to and. This shows up
8471 ;; often in fp comparisons.
8473 (define_insn "*andqi_ext_0_cc"
8478 (match_operand 1 "ext_register_operand" "0")
8481 (match_operand 2 "const_int_operand" "n"))
8483 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8492 "ix86_match_ccmode (insn, CCNOmode)"
8493 "and{b}\t{%2, %h0|%h0, %2}"
8494 [(set_attr "type" "alu")
8495 (set_attr "length_immediate" "1")
8496 (set_attr "mode" "QI")])
8498 (define_insn "*andqi_ext_1"
8499 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8504 (match_operand 1 "ext_register_operand" "0")
8508 (match_operand:QI 2 "general_operand" "Qm"))))
8509 (clobber (reg:CC FLAGS_REG))]
8511 "and{b}\t{%2, %h0|%h0, %2}"
8512 [(set_attr "type" "alu")
8513 (set_attr "length_immediate" "0")
8514 (set_attr "mode" "QI")])
8516 (define_insn "*andqi_ext_1_rex64"
8517 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8522 (match_operand 1 "ext_register_operand" "0")
8526 (match_operand 2 "ext_register_operand" "Q"))))
8527 (clobber (reg:CC FLAGS_REG))]
8529 "and{b}\t{%2, %h0|%h0, %2}"
8530 [(set_attr "type" "alu")
8531 (set_attr "length_immediate" "0")
8532 (set_attr "mode" "QI")])
8534 (define_insn "*andqi_ext_2"
8535 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8540 (match_operand 1 "ext_register_operand" "%0")
8544 (match_operand 2 "ext_register_operand" "Q")
8547 (clobber (reg:CC FLAGS_REG))]
8549 "and{b}\t{%h2, %h0|%h0, %h2}"
8550 [(set_attr "type" "alu")
8551 (set_attr "length_immediate" "0")
8552 (set_attr "mode" "QI")])
8554 ;; Convert wide AND instructions with immediate operand to shorter QImode
8555 ;; equivalents when possible.
8556 ;; Don't do the splitting with memory operands, since it introduces risk
8557 ;; of memory mismatch stalls. We may want to do the splitting for optimizing
8558 ;; for size, but that can (should?) be handled by generic code instead.
8560 [(set (match_operand 0 "register_operand" "")
8561 (and (match_operand 1 "register_operand" "")
8562 (match_operand 2 "const_int_operand" "")))
8563 (clobber (reg:CC FLAGS_REG))]
8565 && QI_REG_P (operands[0])
8566 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8567 && !(~INTVAL (operands[2]) & ~(255 << 8))
8568 && GET_MODE (operands[0]) != QImode"
8569 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8570 (and:SI (zero_extract:SI (match_dup 1)
8571 (const_int 8) (const_int 8))
8573 (clobber (reg:CC FLAGS_REG))])]
8574 "operands[0] = gen_lowpart (SImode, operands[0]);
8575 operands[1] = gen_lowpart (SImode, operands[1]);
8576 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8578 ;; Since AND can be encoded with sign extended immediate, this is only
8579 ;; profitable when 7th bit is not set.
8581 [(set (match_operand 0 "register_operand" "")
8582 (and (match_operand 1 "general_operand" "")
8583 (match_operand 2 "const_int_operand" "")))
8584 (clobber (reg:CC FLAGS_REG))]
8586 && ANY_QI_REG_P (operands[0])
8587 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8588 && !(~INTVAL (operands[2]) & ~255)
8589 && !(INTVAL (operands[2]) & 128)
8590 && GET_MODE (operands[0]) != QImode"
8591 [(parallel [(set (strict_low_part (match_dup 0))
8592 (and:QI (match_dup 1)
8594 (clobber (reg:CC FLAGS_REG))])]
8595 "operands[0] = gen_lowpart (QImode, operands[0]);
8596 operands[1] = gen_lowpart (QImode, operands[1]);
8597 operands[2] = gen_lowpart (QImode, operands[2]);")
8599 ;; Logical inclusive OR instructions
8601 ;; %%% This used to optimize known byte-wide and operations to memory.
8602 ;; If this is considered useful, it should be done with splitters.
8604 (define_expand "iordi3"
8605 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8606 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8607 (match_operand:DI 2 "x86_64_general_operand" "")))
8608 (clobber (reg:CC FLAGS_REG))]
8610 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8612 (define_insn "*iordi_1_rex64"
8613 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8614 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8615 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8616 (clobber (reg:CC FLAGS_REG))]
8618 && ix86_binary_operator_ok (IOR, DImode, operands)"
8619 "or{q}\t{%2, %0|%0, %2}"
8620 [(set_attr "type" "alu")
8621 (set_attr "mode" "DI")])
8623 (define_insn "*iordi_2_rex64"
8625 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8626 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8628 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8629 (ior:DI (match_dup 1) (match_dup 2)))]
8631 && ix86_match_ccmode (insn, CCNOmode)
8632 && ix86_binary_operator_ok (IOR, DImode, operands)"
8633 "or{q}\t{%2, %0|%0, %2}"
8634 [(set_attr "type" "alu")
8635 (set_attr "mode" "DI")])
8637 (define_insn "*iordi_3_rex64"
8639 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8640 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8642 (clobber (match_scratch:DI 0 "=r"))]
8644 && ix86_match_ccmode (insn, CCNOmode)
8645 && ix86_binary_operator_ok (IOR, DImode, operands)"
8646 "or{q}\t{%2, %0|%0, %2}"
8647 [(set_attr "type" "alu")
8648 (set_attr "mode" "DI")])
8651 (define_expand "iorsi3"
8652 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8653 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8654 (match_operand:SI 2 "general_operand" "")))
8655 (clobber (reg:CC FLAGS_REG))]
8657 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8659 (define_insn "*iorsi_1"
8660 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8661 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8662 (match_operand:SI 2 "general_operand" "ri,rmi")))
8663 (clobber (reg:CC FLAGS_REG))]
8664 "ix86_binary_operator_ok (IOR, SImode, operands)"
8665 "or{l}\t{%2, %0|%0, %2}"
8666 [(set_attr "type" "alu")
8667 (set_attr "mode" "SI")])
8669 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8670 (define_insn "*iorsi_1_zext"
8671 [(set (match_operand:DI 0 "register_operand" "=rm")
8673 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8674 (match_operand:SI 2 "general_operand" "rim"))))
8675 (clobber (reg:CC FLAGS_REG))]
8676 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8677 "or{l}\t{%2, %k0|%k0, %2}"
8678 [(set_attr "type" "alu")
8679 (set_attr "mode" "SI")])
8681 (define_insn "*iorsi_1_zext_imm"
8682 [(set (match_operand:DI 0 "register_operand" "=rm")
8683 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8684 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8685 (clobber (reg:CC FLAGS_REG))]
8687 "or{l}\t{%2, %k0|%k0, %2}"
8688 [(set_attr "type" "alu")
8689 (set_attr "mode" "SI")])
8691 (define_insn "*iorsi_2"
8693 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8694 (match_operand:SI 2 "general_operand" "rim,ri"))
8696 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8697 (ior:SI (match_dup 1) (match_dup 2)))]
8698 "ix86_match_ccmode (insn, CCNOmode)
8699 && ix86_binary_operator_ok (IOR, SImode, operands)"
8700 "or{l}\t{%2, %0|%0, %2}"
8701 [(set_attr "type" "alu")
8702 (set_attr "mode" "SI")])
8704 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8705 ;; ??? Special case for immediate operand is missing - it is tricky.
8706 (define_insn "*iorsi_2_zext"
8708 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8709 (match_operand:SI 2 "general_operand" "rim"))
8711 (set (match_operand:DI 0 "register_operand" "=r")
8712 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8713 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8714 && ix86_binary_operator_ok (IOR, SImode, operands)"
8715 "or{l}\t{%2, %k0|%k0, %2}"
8716 [(set_attr "type" "alu")
8717 (set_attr "mode" "SI")])
8719 (define_insn "*iorsi_2_zext_imm"
8721 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8722 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8724 (set (match_operand:DI 0 "register_operand" "=r")
8725 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8726 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8727 && ix86_binary_operator_ok (IOR, SImode, operands)"
8728 "or{l}\t{%2, %k0|%k0, %2}"
8729 [(set_attr "type" "alu")
8730 (set_attr "mode" "SI")])
8732 (define_insn "*iorsi_3"
8734 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8735 (match_operand:SI 2 "general_operand" "rim"))
8737 (clobber (match_scratch:SI 0 "=r"))]
8738 "ix86_match_ccmode (insn, CCNOmode)
8739 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8740 "or{l}\t{%2, %0|%0, %2}"
8741 [(set_attr "type" "alu")
8742 (set_attr "mode" "SI")])
8744 (define_expand "iorhi3"
8745 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8746 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
8747 (match_operand:HI 2 "general_operand" "")))
8748 (clobber (reg:CC FLAGS_REG))]
8749 "TARGET_HIMODE_MATH"
8750 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
8752 (define_insn "*iorhi_1"
8753 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8754 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8755 (match_operand:HI 2 "general_operand" "rmi,ri")))
8756 (clobber (reg:CC FLAGS_REG))]
8757 "ix86_binary_operator_ok (IOR, HImode, operands)"
8758 "or{w}\t{%2, %0|%0, %2}"
8759 [(set_attr "type" "alu")
8760 (set_attr "mode" "HI")])
8762 (define_insn "*iorhi_2"
8764 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8765 (match_operand:HI 2 "general_operand" "rim,ri"))
8767 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8768 (ior:HI (match_dup 1) (match_dup 2)))]
8769 "ix86_match_ccmode (insn, CCNOmode)
8770 && ix86_binary_operator_ok (IOR, HImode, operands)"
8771 "or{w}\t{%2, %0|%0, %2}"
8772 [(set_attr "type" "alu")
8773 (set_attr "mode" "HI")])
8775 (define_insn "*iorhi_3"
8777 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8778 (match_operand:HI 2 "general_operand" "rim"))
8780 (clobber (match_scratch:HI 0 "=r"))]
8781 "ix86_match_ccmode (insn, CCNOmode)
8782 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8783 "or{w}\t{%2, %0|%0, %2}"
8784 [(set_attr "type" "alu")
8785 (set_attr "mode" "HI")])
8787 (define_expand "iorqi3"
8788 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8789 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
8790 (match_operand:QI 2 "general_operand" "")))
8791 (clobber (reg:CC FLAGS_REG))]
8792 "TARGET_QIMODE_MATH"
8793 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
8795 ;; %%% Potential partial reg stall on alternative 2. What to do?
8796 (define_insn "*iorqi_1"
8797 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8798 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8799 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8800 (clobber (reg:CC FLAGS_REG))]
8801 "ix86_binary_operator_ok (IOR, QImode, operands)"
8803 or{b}\t{%2, %0|%0, %2}
8804 or{b}\t{%2, %0|%0, %2}
8805 or{l}\t{%k2, %k0|%k0, %k2}"
8806 [(set_attr "type" "alu")
8807 (set_attr "mode" "QI,QI,SI")])
8809 (define_insn "*iorqi_1_slp"
8810 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
8811 (ior:QI (match_dup 0)
8812 (match_operand:QI 1 "general_operand" "qmi,qi")))
8813 (clobber (reg:CC FLAGS_REG))]
8814 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8815 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8816 "or{b}\t{%1, %0|%0, %1}"
8817 [(set_attr "type" "alu1")
8818 (set_attr "mode" "QI")])
8820 (define_insn "*iorqi_2"
8822 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8823 (match_operand:QI 2 "general_operand" "qim,qi"))
8825 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8826 (ior:QI (match_dup 1) (match_dup 2)))]
8827 "ix86_match_ccmode (insn, CCNOmode)
8828 && ix86_binary_operator_ok (IOR, QImode, operands)"
8829 "or{b}\t{%2, %0|%0, %2}"
8830 [(set_attr "type" "alu")
8831 (set_attr "mode" "QI")])
8833 (define_insn "*iorqi_2_slp"
8835 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8836 (match_operand:QI 1 "general_operand" "qim,qi"))
8838 (set (strict_low_part (match_dup 0))
8839 (ior:QI (match_dup 0) (match_dup 1)))]
8840 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8841 && ix86_match_ccmode (insn, CCNOmode)
8842 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8843 "or{b}\t{%1, %0|%0, %1}"
8844 [(set_attr "type" "alu1")
8845 (set_attr "mode" "QI")])
8847 (define_insn "*iorqi_3"
8849 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8850 (match_operand:QI 2 "general_operand" "qim"))
8852 (clobber (match_scratch:QI 0 "=q"))]
8853 "ix86_match_ccmode (insn, CCNOmode)
8854 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8855 "or{b}\t{%2, %0|%0, %2}"
8856 [(set_attr "type" "alu")
8857 (set_attr "mode" "QI")])
8859 (define_insn "iorqi_ext_0"
8860 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8865 (match_operand 1 "ext_register_operand" "0")
8868 (match_operand 2 "const_int_operand" "n")))
8869 (clobber (reg:CC FLAGS_REG))]
8870 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8871 "or{b}\t{%2, %h0|%h0, %2}"
8872 [(set_attr "type" "alu")
8873 (set_attr "length_immediate" "1")
8874 (set_attr "mode" "QI")])
8876 (define_insn "*iorqi_ext_1"
8877 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8882 (match_operand 1 "ext_register_operand" "0")
8886 (match_operand:QI 2 "general_operand" "Qm"))))
8887 (clobber (reg:CC FLAGS_REG))]
8889 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8890 "or{b}\t{%2, %h0|%h0, %2}"
8891 [(set_attr "type" "alu")
8892 (set_attr "length_immediate" "0")
8893 (set_attr "mode" "QI")])
8895 (define_insn "*iorqi_ext_1_rex64"
8896 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8901 (match_operand 1 "ext_register_operand" "0")
8905 (match_operand 2 "ext_register_operand" "Q"))))
8906 (clobber (reg:CC FLAGS_REG))]
8908 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8909 "or{b}\t{%2, %h0|%h0, %2}"
8910 [(set_attr "type" "alu")
8911 (set_attr "length_immediate" "0")
8912 (set_attr "mode" "QI")])
8914 (define_insn "*iorqi_ext_2"
8915 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8919 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
8922 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
8925 (clobber (reg:CC FLAGS_REG))]
8926 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8927 "ior{b}\t{%h2, %h0|%h0, %h2}"
8928 [(set_attr "type" "alu")
8929 (set_attr "length_immediate" "0")
8930 (set_attr "mode" "QI")])
8933 [(set (match_operand 0 "register_operand" "")
8934 (ior (match_operand 1 "register_operand" "")
8935 (match_operand 2 "const_int_operand" "")))
8936 (clobber (reg:CC FLAGS_REG))]
8938 && QI_REG_P (operands[0])
8939 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8940 && !(INTVAL (operands[2]) & ~(255 << 8))
8941 && GET_MODE (operands[0]) != QImode"
8942 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8943 (ior:SI (zero_extract:SI (match_dup 1)
8944 (const_int 8) (const_int 8))
8946 (clobber (reg:CC FLAGS_REG))])]
8947 "operands[0] = gen_lowpart (SImode, operands[0]);
8948 operands[1] = gen_lowpart (SImode, operands[1]);
8949 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8951 ;; Since OR can be encoded with sign extended immediate, this is only
8952 ;; profitable when 7th bit is set.
8954 [(set (match_operand 0 "register_operand" "")
8955 (ior (match_operand 1 "general_operand" "")
8956 (match_operand 2 "const_int_operand" "")))
8957 (clobber (reg:CC FLAGS_REG))]
8959 && ANY_QI_REG_P (operands[0])
8960 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8961 && !(INTVAL (operands[2]) & ~255)
8962 && (INTVAL (operands[2]) & 128)
8963 && GET_MODE (operands[0]) != QImode"
8964 [(parallel [(set (strict_low_part (match_dup 0))
8965 (ior:QI (match_dup 1)
8967 (clobber (reg:CC FLAGS_REG))])]
8968 "operands[0] = gen_lowpart (QImode, operands[0]);
8969 operands[1] = gen_lowpart (QImode, operands[1]);
8970 operands[2] = gen_lowpart (QImode, operands[2]);")
8972 ;; Logical XOR instructions
8974 ;; %%% This used to optimize known byte-wide and operations to memory.
8975 ;; If this is considered useful, it should be done with splitters.
8977 (define_expand "xordi3"
8978 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8979 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
8980 (match_operand:DI 2 "x86_64_general_operand" "")))
8981 (clobber (reg:CC FLAGS_REG))]
8983 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
8985 (define_insn "*xordi_1_rex64"
8986 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8987 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8988 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
8989 (clobber (reg:CC FLAGS_REG))]
8991 && ix86_binary_operator_ok (XOR, DImode, operands)"
8993 xor{q}\t{%2, %0|%0, %2}
8994 xor{q}\t{%2, %0|%0, %2}"
8995 [(set_attr "type" "alu")
8996 (set_attr "mode" "DI,DI")])
8998 (define_insn "*xordi_2_rex64"
9000 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
9001 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
9003 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
9004 (xor:DI (match_dup 1) (match_dup 2)))]
9006 && ix86_match_ccmode (insn, CCNOmode)
9007 && ix86_binary_operator_ok (XOR, DImode, operands)"
9009 xor{q}\t{%2, %0|%0, %2}
9010 xor{q}\t{%2, %0|%0, %2}"
9011 [(set_attr "type" "alu")
9012 (set_attr "mode" "DI,DI")])
9014 (define_insn "*xordi_3_rex64"
9016 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
9017 (match_operand:DI 2 "x86_64_general_operand" "rem"))
9019 (clobber (match_scratch:DI 0 "=r"))]
9021 && ix86_match_ccmode (insn, CCNOmode)
9022 && ix86_binary_operator_ok (XOR, DImode, operands)"
9023 "xor{q}\t{%2, %0|%0, %2}"
9024 [(set_attr "type" "alu")
9025 (set_attr "mode" "DI")])
9027 (define_expand "xorsi3"
9028 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9029 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
9030 (match_operand:SI 2 "general_operand" "")))
9031 (clobber (reg:CC FLAGS_REG))]
9033 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
9035 (define_insn "*xorsi_1"
9036 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
9037 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9038 (match_operand:SI 2 "general_operand" "ri,rm")))
9039 (clobber (reg:CC FLAGS_REG))]
9040 "ix86_binary_operator_ok (XOR, SImode, operands)"
9041 "xor{l}\t{%2, %0|%0, %2}"
9042 [(set_attr "type" "alu")
9043 (set_attr "mode" "SI")])
9045 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9046 ;; Add speccase for immediates
9047 (define_insn "*xorsi_1_zext"
9048 [(set (match_operand:DI 0 "register_operand" "=r")
9050 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9051 (match_operand:SI 2 "general_operand" "rim"))))
9052 (clobber (reg:CC FLAGS_REG))]
9053 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9054 "xor{l}\t{%2, %k0|%k0, %2}"
9055 [(set_attr "type" "alu")
9056 (set_attr "mode" "SI")])
9058 (define_insn "*xorsi_1_zext_imm"
9059 [(set (match_operand:DI 0 "register_operand" "=r")
9060 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
9061 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
9062 (clobber (reg:CC FLAGS_REG))]
9063 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9064 "xor{l}\t{%2, %k0|%k0, %2}"
9065 [(set_attr "type" "alu")
9066 (set_attr "mode" "SI")])
9068 (define_insn "*xorsi_2"
9070 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9071 (match_operand:SI 2 "general_operand" "rim,ri"))
9073 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
9074 (xor:SI (match_dup 1) (match_dup 2)))]
9075 "ix86_match_ccmode (insn, CCNOmode)
9076 && ix86_binary_operator_ok (XOR, SImode, operands)"
9077 "xor{l}\t{%2, %0|%0, %2}"
9078 [(set_attr "type" "alu")
9079 (set_attr "mode" "SI")])
9081 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9082 ;; ??? Special case for immediate operand is missing - it is tricky.
9083 (define_insn "*xorsi_2_zext"
9085 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9086 (match_operand:SI 2 "general_operand" "rim"))
9088 (set (match_operand:DI 0 "register_operand" "=r")
9089 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
9090 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9091 && ix86_binary_operator_ok (XOR, SImode, operands)"
9092 "xor{l}\t{%2, %k0|%k0, %2}"
9093 [(set_attr "type" "alu")
9094 (set_attr "mode" "SI")])
9096 (define_insn "*xorsi_2_zext_imm"
9098 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9099 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
9101 (set (match_operand:DI 0 "register_operand" "=r")
9102 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
9103 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9104 && ix86_binary_operator_ok (XOR, SImode, operands)"
9105 "xor{l}\t{%2, %k0|%k0, %2}"
9106 [(set_attr "type" "alu")
9107 (set_attr "mode" "SI")])
9109 (define_insn "*xorsi_3"
9111 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9112 (match_operand:SI 2 "general_operand" "rim"))
9114 (clobber (match_scratch:SI 0 "=r"))]
9115 "ix86_match_ccmode (insn, CCNOmode)
9116 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9117 "xor{l}\t{%2, %0|%0, %2}"
9118 [(set_attr "type" "alu")
9119 (set_attr "mode" "SI")])
9121 (define_expand "xorhi3"
9122 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9123 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
9124 (match_operand:HI 2 "general_operand" "")))
9125 (clobber (reg:CC FLAGS_REG))]
9126 "TARGET_HIMODE_MATH"
9127 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
9129 (define_insn "*xorhi_1"
9130 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9131 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9132 (match_operand:HI 2 "general_operand" "rmi,ri")))
9133 (clobber (reg:CC FLAGS_REG))]
9134 "ix86_binary_operator_ok (XOR, HImode, operands)"
9135 "xor{w}\t{%2, %0|%0, %2}"
9136 [(set_attr "type" "alu")
9137 (set_attr "mode" "HI")])
9139 (define_insn "*xorhi_2"
9141 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9142 (match_operand:HI 2 "general_operand" "rim,ri"))
9144 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9145 (xor:HI (match_dup 1) (match_dup 2)))]
9146 "ix86_match_ccmode (insn, CCNOmode)
9147 && ix86_binary_operator_ok (XOR, HImode, operands)"
9148 "xor{w}\t{%2, %0|%0, %2}"
9149 [(set_attr "type" "alu")
9150 (set_attr "mode" "HI")])
9152 (define_insn "*xorhi_3"
9154 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9155 (match_operand:HI 2 "general_operand" "rim"))
9157 (clobber (match_scratch:HI 0 "=r"))]
9158 "ix86_match_ccmode (insn, CCNOmode)
9159 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9160 "xor{w}\t{%2, %0|%0, %2}"
9161 [(set_attr "type" "alu")
9162 (set_attr "mode" "HI")])
9164 (define_expand "xorqi3"
9165 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9166 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
9167 (match_operand:QI 2 "general_operand" "")))
9168 (clobber (reg:CC FLAGS_REG))]
9169 "TARGET_QIMODE_MATH"
9170 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
9172 ;; %%% Potential partial reg stall on alternative 2. What to do?
9173 (define_insn "*xorqi_1"
9174 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9175 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9176 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9177 (clobber (reg:CC FLAGS_REG))]
9178 "ix86_binary_operator_ok (XOR, QImode, operands)"
9180 xor{b}\t{%2, %0|%0, %2}
9181 xor{b}\t{%2, %0|%0, %2}
9182 xor{l}\t{%k2, %k0|%k0, %k2}"
9183 [(set_attr "type" "alu")
9184 (set_attr "mode" "QI,QI,SI")])
9186 (define_insn "*xorqi_1_slp"
9187 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
9188 (xor:QI (match_dup 0)
9189 (match_operand:QI 1 "general_operand" "qi,qmi")))
9190 (clobber (reg:CC FLAGS_REG))]
9191 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9192 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9193 "xor{b}\t{%1, %0|%0, %1}"
9194 [(set_attr "type" "alu1")
9195 (set_attr "mode" "QI")])
9197 (define_insn "xorqi_ext_0"
9198 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9203 (match_operand 1 "ext_register_operand" "0")
9206 (match_operand 2 "const_int_operand" "n")))
9207 (clobber (reg:CC FLAGS_REG))]
9208 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9209 "xor{b}\t{%2, %h0|%h0, %2}"
9210 [(set_attr "type" "alu")
9211 (set_attr "length_immediate" "1")
9212 (set_attr "mode" "QI")])
9214 (define_insn "*xorqi_ext_1"
9215 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9220 (match_operand 1 "ext_register_operand" "0")
9224 (match_operand:QI 2 "general_operand" "Qm"))))
9225 (clobber (reg:CC FLAGS_REG))]
9227 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9228 "xor{b}\t{%2, %h0|%h0, %2}"
9229 [(set_attr "type" "alu")
9230 (set_attr "length_immediate" "0")
9231 (set_attr "mode" "QI")])
9233 (define_insn "*xorqi_ext_1_rex64"
9234 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9239 (match_operand 1 "ext_register_operand" "0")
9243 (match_operand 2 "ext_register_operand" "Q"))))
9244 (clobber (reg:CC FLAGS_REG))]
9246 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9247 "xor{b}\t{%2, %h0|%h0, %2}"
9248 [(set_attr "type" "alu")
9249 (set_attr "length_immediate" "0")
9250 (set_attr "mode" "QI")])
9252 (define_insn "*xorqi_ext_2"
9253 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9257 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9260 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9263 (clobber (reg:CC FLAGS_REG))]
9264 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9265 "xor{b}\t{%h2, %h0|%h0, %h2}"
9266 [(set_attr "type" "alu")
9267 (set_attr "length_immediate" "0")
9268 (set_attr "mode" "QI")])
9270 (define_insn "*xorqi_cc_1"
9273 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9274 (match_operand:QI 2 "general_operand" "qim,qi"))
9276 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9277 (xor:QI (match_dup 1) (match_dup 2)))]
9278 "ix86_match_ccmode (insn, CCNOmode)
9279 && ix86_binary_operator_ok (XOR, QImode, operands)"
9280 "xor{b}\t{%2, %0|%0, %2}"
9281 [(set_attr "type" "alu")
9282 (set_attr "mode" "QI")])
9284 (define_insn "*xorqi_2_slp"
9286 (compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
9287 (match_operand:QI 1 "general_operand" "qim,qi"))
9289 (set (strict_low_part (match_dup 0))
9290 (xor:QI (match_dup 0) (match_dup 1)))]
9291 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9292 && ix86_match_ccmode (insn, CCNOmode)
9293 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9294 "xor{b}\t{%1, %0|%0, %1}"
9295 [(set_attr "type" "alu1")
9296 (set_attr "mode" "QI")])
9298 (define_insn "*xorqi_cc_2"
9301 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9302 (match_operand:QI 2 "general_operand" "qim"))
9304 (clobber (match_scratch:QI 0 "=q"))]
9305 "ix86_match_ccmode (insn, CCNOmode)
9306 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9307 "xor{b}\t{%2, %0|%0, %2}"
9308 [(set_attr "type" "alu")
9309 (set_attr "mode" "QI")])
9311 (define_insn "*xorqi_cc_ext_1"
9316 (match_operand 1 "ext_register_operand" "0")
9319 (match_operand:QI 2 "general_operand" "qmn"))
9321 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
9325 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9327 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9328 "xor{b}\t{%2, %h0|%h0, %2}"
9329 [(set_attr "type" "alu")
9330 (set_attr "mode" "QI")])
9332 (define_insn "*xorqi_cc_ext_1_rex64"
9337 (match_operand 1 "ext_register_operand" "0")
9340 (match_operand:QI 2 "nonmemory_operand" "Qn"))
9342 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9346 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9348 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9349 "xor{b}\t{%2, %h0|%h0, %2}"
9350 [(set_attr "type" "alu")
9351 (set_attr "mode" "QI")])
9353 (define_expand "xorqi_cc_ext_1"
9355 (set (reg:CCNO FLAGS_REG)
9359 (match_operand 1 "ext_register_operand" "")
9362 (match_operand:QI 2 "general_operand" ""))
9364 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9368 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9374 [(set (match_operand 0 "register_operand" "")
9375 (xor (match_operand 1 "register_operand" "")
9376 (match_operand 2 "const_int_operand" "")))
9377 (clobber (reg:CC FLAGS_REG))]
9379 && QI_REG_P (operands[0])
9380 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9381 && !(INTVAL (operands[2]) & ~(255 << 8))
9382 && GET_MODE (operands[0]) != QImode"
9383 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9384 (xor:SI (zero_extract:SI (match_dup 1)
9385 (const_int 8) (const_int 8))
9387 (clobber (reg:CC FLAGS_REG))])]
9388 "operands[0] = gen_lowpart (SImode, operands[0]);
9389 operands[1] = gen_lowpart (SImode, operands[1]);
9390 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9392 ;; Since XOR can be encoded with sign extended immediate, this is only
9393 ;; profitable when 7th bit is set.
9395 [(set (match_operand 0 "register_operand" "")
9396 (xor (match_operand 1 "general_operand" "")
9397 (match_operand 2 "const_int_operand" "")))
9398 (clobber (reg:CC FLAGS_REG))]
9400 && ANY_QI_REG_P (operands[0])
9401 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9402 && !(INTVAL (operands[2]) & ~255)
9403 && (INTVAL (operands[2]) & 128)
9404 && GET_MODE (operands[0]) != QImode"
9405 [(parallel [(set (strict_low_part (match_dup 0))
9406 (xor:QI (match_dup 1)
9408 (clobber (reg:CC FLAGS_REG))])]
9409 "operands[0] = gen_lowpart (QImode, operands[0]);
9410 operands[1] = gen_lowpart (QImode, operands[1]);
9411 operands[2] = gen_lowpart (QImode, operands[2]);")
9413 ;; Negation instructions
9415 (define_expand "negdi2"
9416 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9417 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9418 (clobber (reg:CC FLAGS_REG))])]
9420 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
9422 (define_insn "*negdi2_1"
9423 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
9424 (neg:DI (match_operand:DI 1 "general_operand" "0")))
9425 (clobber (reg:CC FLAGS_REG))]
9427 && ix86_unary_operator_ok (NEG, DImode, operands)"
9431 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9432 (neg:DI (match_operand:DI 1 "general_operand" "")))
9433 (clobber (reg:CC FLAGS_REG))]
9434 "!TARGET_64BIT && reload_completed"
9436 [(set (reg:CCZ FLAGS_REG)
9437 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
9438 (set (match_dup 0) (neg:SI (match_dup 2)))])
9441 (plus:SI (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
9444 (clobber (reg:CC FLAGS_REG))])
9447 (neg:SI (match_dup 1)))
9448 (clobber (reg:CC FLAGS_REG))])]
9449 "split_di (operands+1, 1, operands+2, operands+3);
9450 split_di (operands+0, 1, operands+0, operands+1);")
9452 (define_insn "*negdi2_1_rex64"
9453 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9454 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9455 (clobber (reg:CC FLAGS_REG))]
9456 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9458 [(set_attr "type" "negnot")
9459 (set_attr "mode" "DI")])
9461 ;; The problem with neg is that it does not perform (compare x 0),
9462 ;; it really performs (compare 0 x), which leaves us with the zero
9463 ;; flag being the only useful item.
9465 (define_insn "*negdi2_cmpz_rex64"
9466 [(set (reg:CCZ FLAGS_REG)
9467 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9469 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9470 (neg:DI (match_dup 1)))]
9471 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9473 [(set_attr "type" "negnot")
9474 (set_attr "mode" "DI")])
9477 (define_expand "negsi2"
9478 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9479 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9480 (clobber (reg:CC FLAGS_REG))])]
9482 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9484 (define_insn "*negsi2_1"
9485 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9486 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9487 (clobber (reg:CC FLAGS_REG))]
9488 "ix86_unary_operator_ok (NEG, SImode, operands)"
9490 [(set_attr "type" "negnot")
9491 (set_attr "mode" "SI")])
9493 ;; Combine is quite creative about this pattern.
9494 (define_insn "*negsi2_1_zext"
9495 [(set (match_operand:DI 0 "register_operand" "=r")
9496 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9499 (clobber (reg:CC FLAGS_REG))]
9500 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9502 [(set_attr "type" "negnot")
9503 (set_attr "mode" "SI")])
9505 ;; The problem with neg is that it does not perform (compare x 0),
9506 ;; it really performs (compare 0 x), which leaves us with the zero
9507 ;; flag being the only useful item.
9509 (define_insn "*negsi2_cmpz"
9510 [(set (reg:CCZ FLAGS_REG)
9511 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9513 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9514 (neg:SI (match_dup 1)))]
9515 "ix86_unary_operator_ok (NEG, SImode, operands)"
9517 [(set_attr "type" "negnot")
9518 (set_attr "mode" "SI")])
9520 (define_insn "*negsi2_cmpz_zext"
9521 [(set (reg:CCZ FLAGS_REG)
9522 (compare:CCZ (lshiftrt:DI
9524 (match_operand:DI 1 "register_operand" "0")
9528 (set (match_operand:DI 0 "register_operand" "=r")
9529 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9532 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9534 [(set_attr "type" "negnot")
9535 (set_attr "mode" "SI")])
9537 (define_expand "neghi2"
9538 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9539 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9540 (clobber (reg:CC FLAGS_REG))])]
9541 "TARGET_HIMODE_MATH"
9542 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9544 (define_insn "*neghi2_1"
9545 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9546 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9547 (clobber (reg:CC FLAGS_REG))]
9548 "ix86_unary_operator_ok (NEG, HImode, operands)"
9550 [(set_attr "type" "negnot")
9551 (set_attr "mode" "HI")])
9553 (define_insn "*neghi2_cmpz"
9554 [(set (reg:CCZ FLAGS_REG)
9555 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9557 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9558 (neg:HI (match_dup 1)))]
9559 "ix86_unary_operator_ok (NEG, HImode, operands)"
9561 [(set_attr "type" "negnot")
9562 (set_attr "mode" "HI")])
9564 (define_expand "negqi2"
9565 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9566 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9567 (clobber (reg:CC FLAGS_REG))])]
9568 "TARGET_QIMODE_MATH"
9569 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9571 (define_insn "*negqi2_1"
9572 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9573 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9574 (clobber (reg:CC FLAGS_REG))]
9575 "ix86_unary_operator_ok (NEG, QImode, operands)"
9577 [(set_attr "type" "negnot")
9578 (set_attr "mode" "QI")])
9580 (define_insn "*negqi2_cmpz"
9581 [(set (reg:CCZ FLAGS_REG)
9582 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9584 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9585 (neg:QI (match_dup 1)))]
9586 "ix86_unary_operator_ok (NEG, QImode, operands)"
9588 [(set_attr "type" "negnot")
9589 (set_attr "mode" "QI")])
9591 ;; Changing of sign for FP values is doable using integer unit too.
9593 (define_expand "negsf2"
9594 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9595 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9596 (clobber (reg:CC FLAGS_REG))])]
9600 /* In case operand is in memory, we will not use SSE. */
9601 if (memory_operand (operands[0], VOIDmode)
9602 && rtx_equal_p (operands[0], operands[1]))
9603 emit_insn (gen_negsf2_memory (operands[0], operands[1]));
9606 /* Using SSE is tricky, since we need bitwise negation of -0
9608 rtx reg = gen_reg_rtx (SFmode);
9609 rtx dest = operands[0];
9610 rtx imm = gen_lowpart (SFmode, gen_int_mode (0x80000000, SImode));
9612 operands[1] = force_reg (SFmode, operands[1]);
9613 operands[0] = force_reg (SFmode, operands[0]);
9614 reg = force_reg (V4SFmode,
9615 gen_rtx_CONST_VECTOR (V4SFmode,
9616 gen_rtvec (4, imm, CONST0_RTX (SFmode),
9617 CONST0_RTX (SFmode),
9618 CONST0_RTX (SFmode))));
9619 emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
9620 if (dest != operands[0])
9621 emit_move_insn (dest, operands[0]);
9625 ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
9627 (define_insn "negsf2_memory"
9628 [(set (match_operand:SF 0 "memory_operand" "=m")
9629 (neg:SF (match_operand:SF 1 "memory_operand" "0")))
9630 (clobber (reg:CC FLAGS_REG))]
9631 "ix86_unary_operator_ok (NEG, SFmode, operands)"
9634 (define_insn "negsf2_ifs"
9635 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
9636 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
9637 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
9638 (clobber (reg:CC FLAGS_REG))]
9640 && (reload_in_progress || reload_completed
9641 || (register_operand (operands[0], VOIDmode)
9642 && register_operand (operands[1], VOIDmode)))"
9646 [(set (match_operand:SF 0 "memory_operand" "")
9647 (neg:SF (match_operand:SF 1 "memory_operand" "")))
9648 (use (match_operand:SF 2 "" ""))
9649 (clobber (reg:CC FLAGS_REG))]
9651 [(parallel [(set (match_dup 0)
9652 (neg:SF (match_dup 1)))
9653 (clobber (reg:CC FLAGS_REG))])])
9656 [(set (match_operand:SF 0 "register_operand" "")
9657 (neg:SF (match_operand:SF 1 "register_operand" "")))
9658 (use (match_operand:V4SF 2 "" ""))
9659 (clobber (reg:CC FLAGS_REG))]
9660 "reload_completed && !SSE_REG_P (operands[0])"
9661 [(parallel [(set (match_dup 0)
9662 (neg:SF (match_dup 1)))
9663 (clobber (reg:CC FLAGS_REG))])])
9666 [(set (match_operand:SF 0 "register_operand" "")
9667 (neg:SF (match_operand:SF 1 "register_operand" "")))
9668 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
9669 (clobber (reg:CC FLAGS_REG))]
9670 "reload_completed && SSE_REG_P (operands[0])"
9672 (xor:V4SF (match_dup 1)
9675 operands[0] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
9676 operands[1] = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
9677 if (operands_match_p (operands[0], operands[2]))
9681 operands[1] = operands[2];
9687 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9688 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9690 (define_insn "*negsf2_if"
9691 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9692 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9693 (clobber (reg:CC FLAGS_REG))]
9694 "TARGET_80387 && !TARGET_SSE
9695 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9699 [(set (match_operand:SF 0 "fp_register_operand" "")
9700 (neg:SF (match_operand:SF 1 "register_operand" "")))
9701 (clobber (reg:CC FLAGS_REG))]
9702 "TARGET_80387 && reload_completed"
9704 (neg:SF (match_dup 1)))]
9708 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
9709 (neg:SF (match_operand:SF 1 "register_operand" "")))
9710 (clobber (reg:CC FLAGS_REG))]
9711 "TARGET_80387 && reload_completed"
9712 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9713 (clobber (reg:CC FLAGS_REG))])]
9714 "operands[1] = gen_int_mode (0x80000000, SImode);
9715 operands[0] = gen_lowpart (SImode, operands[0]);")
9718 [(set (match_operand 0 "memory_operand" "")
9719 (neg (match_operand 1 "memory_operand" "")))
9720 (clobber (reg:CC FLAGS_REG))]
9721 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9722 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
9723 (clobber (reg:CC FLAGS_REG))])]
9725 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9727 if (GET_MODE (operands[1]) == XFmode)
9729 operands[0] = adjust_address (operands[0], QImode, size - 1);
9730 operands[1] = gen_int_mode (0x80, QImode);
9733 (define_expand "negdf2"
9734 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9735 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9736 (clobber (reg:CC FLAGS_REG))])]
9740 /* In case operand is in memory, we will not use SSE. */
9741 if (memory_operand (operands[0], VOIDmode)
9742 && rtx_equal_p (operands[0], operands[1]))
9743 emit_insn (gen_negdf2_memory (operands[0], operands[1]));
9746 /* Using SSE is tricky, since we need bitwise negation of -0
9749 #if HOST_BITS_PER_WIDE_INT >= 64
9750 rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
9752 rtx imm = immed_double_const (0, 0x80000000, DImode);
9754 rtx dest = operands[0];
9756 operands[1] = force_reg (DFmode, operands[1]);
9757 operands[0] = force_reg (DFmode, operands[0]);
9758 imm = gen_lowpart (DFmode, imm);
9759 reg = force_reg (V2DFmode,
9760 gen_rtx_CONST_VECTOR (V2DFmode,
9761 gen_rtvec (2, imm, CONST0_RTX (DFmode))));
9762 emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg));
9763 if (dest != operands[0])
9764 emit_move_insn (dest, operands[0]);
9768 ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
9770 (define_insn "negdf2_memory"
9771 [(set (match_operand:DF 0 "memory_operand" "=m")
9772 (neg:DF (match_operand:DF 1 "memory_operand" "0")))
9773 (clobber (reg:CC FLAGS_REG))]
9774 "ix86_unary_operator_ok (NEG, DFmode, operands)"
9777 (define_insn "negdf2_ifs"
9778 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
9779 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9780 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
9781 (clobber (reg:CC FLAGS_REG))]
9782 "!TARGET_64BIT && TARGET_SSE2
9783 && (reload_in_progress || reload_completed
9784 || (register_operand (operands[0], VOIDmode)
9785 && register_operand (operands[1], VOIDmode)))"
9788 (define_insn "*negdf2_ifs_rex64"
9789 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#f,Y#f,fm#Y")
9790 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
9791 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
9792 (clobber (reg:CC FLAGS_REG))]
9793 "TARGET_64BIT && TARGET_SSE2
9794 && (reload_in_progress || reload_completed
9795 || (register_operand (operands[0], VOIDmode)
9796 && register_operand (operands[1], VOIDmode)))"
9800 [(set (match_operand:DF 0 "memory_operand" "")
9801 (neg:DF (match_operand:DF 1 "memory_operand" "")))
9802 (use (match_operand:V2DF 2 "" ""))
9803 (clobber (reg:CC FLAGS_REG))]
9805 [(parallel [(set (match_dup 0)
9806 (neg:DF (match_dup 1)))
9807 (clobber (reg:CC FLAGS_REG))])])
9810 [(set (match_operand:DF 0 "register_operand" "")
9811 (neg:DF (match_operand:DF 1 "register_operand" "")))
9812 (use (match_operand:V2DF 2 "" ""))
9813 (clobber (reg:CC FLAGS_REG))]
9814 "reload_completed && !SSE_REG_P (operands[0])
9815 && (!TARGET_64BIT || FP_REG_P (operands[0]))"
9816 [(parallel [(set (match_dup 0)
9817 (neg:DF (match_dup 1)))
9818 (clobber (reg:CC FLAGS_REG))])])
9821 [(set (match_operand:DF 0 "register_operand" "")
9822 (neg:DF (match_operand:DF 1 "register_operand" "")))
9823 (use (match_operand:V2DF 2 "" ""))
9824 (clobber (reg:CC FLAGS_REG))]
9825 "TARGET_64BIT && reload_completed && GENERAL_REG_P (operands[0])"
9826 [(parallel [(set (match_dup 0)
9827 (xor:DI (match_dup 1) (match_dup 2)))
9828 (clobber (reg:CC FLAGS_REG))])]
9829 "operands[0] = gen_lowpart (DImode, operands[0]);
9830 operands[1] = gen_lowpart (DImode, operands[1]);
9831 operands[2] = gen_lowpart (DImode, operands[2]);")
9834 [(set (match_operand:DF 0 "register_operand" "")
9835 (neg:DF (match_operand:DF 1 "register_operand" "")))
9836 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
9837 (clobber (reg:CC FLAGS_REG))]
9838 "reload_completed && SSE_REG_P (operands[0])"
9840 (xor:V2DF (match_dup 1)
9843 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
9844 operands[1] = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
9845 /* Avoid possible reformatting on the operands. */
9846 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
9847 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
9848 if (operands_match_p (operands[0], operands[2]))
9852 operands[1] = operands[2];
9857 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9858 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9860 (define_insn "*negdf2_if"
9861 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9862 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9863 (clobber (reg:CC FLAGS_REG))]
9864 "!TARGET_64BIT && TARGET_80387
9865 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9868 ;; FIXME: We should to allow integer registers here. Problem is that
9869 ;; we need another scratch register to get constant from.
9870 ;; Forcing constant to mem if no register available in peep2 should be
9871 ;; safe even for PIC mode, because of RIP relative addressing.
9872 (define_insn "*negdf2_if_rex64"
9873 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
9874 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9875 (clobber (reg:CC FLAGS_REG))]
9876 "TARGET_64BIT && TARGET_80387
9877 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9881 [(set (match_operand:DF 0 "fp_register_operand" "")
9882 (neg:DF (match_operand:DF 1 "register_operand" "")))
9883 (clobber (reg:CC FLAGS_REG))]
9884 "TARGET_80387 && reload_completed"
9886 (neg:DF (match_dup 1)))]
9890 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
9891 (neg:DF (match_operand:DF 1 "register_operand" "")))
9892 (clobber (reg:CC FLAGS_REG))]
9893 "!TARGET_64BIT && TARGET_80387 && reload_completed"
9894 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
9895 (clobber (reg:CC FLAGS_REG))])]
9896 "operands[4] = gen_int_mode (0x80000000, SImode);
9897 split_di (operands+0, 1, operands+2, operands+3);")
9899 (define_expand "negxf2"
9900 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
9901 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
9902 (clobber (reg:CC FLAGS_REG))])]
9904 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
9906 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9907 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9909 (define_insn "*negxf2_if"
9910 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9911 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
9912 (clobber (reg:CC FLAGS_REG))]
9914 && ix86_unary_operator_ok (NEG, XFmode, operands)"
9918 [(set (match_operand:XF 0 "fp_register_operand" "")
9919 (neg:XF (match_operand:XF 1 "register_operand" "")))
9920 (clobber (reg:CC FLAGS_REG))]
9921 "TARGET_80387 && reload_completed"
9923 (neg:XF (match_dup 1)))]
9927 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
9928 (neg:XF (match_operand:XF 1 "register_operand" "")))
9929 (clobber (reg:CC FLAGS_REG))]
9930 "TARGET_80387 && reload_completed"
9931 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9932 (clobber (reg:CC FLAGS_REG))])]
9933 "operands[1] = GEN_INT (0x8000);
9934 operands[0] = gen_rtx_REG (SImode,
9935 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9937 ;; Conditionalize these after reload. If they matches before reload, we
9938 ;; lose the clobber and ability to use integer instructions.
9940 (define_insn "*negsf2_1"
9941 [(set (match_operand:SF 0 "register_operand" "=f")
9942 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
9943 "TARGET_80387 && reload_completed"
9945 [(set_attr "type" "fsgn")
9946 (set_attr "mode" "SF")])
9948 (define_insn "*negdf2_1"
9949 [(set (match_operand:DF 0 "register_operand" "=f")
9950 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
9951 "TARGET_80387 && reload_completed"
9953 [(set_attr "type" "fsgn")
9954 (set_attr "mode" "DF")])
9956 (define_insn "*negextendsfdf2"
9957 [(set (match_operand:DF 0 "register_operand" "=f")
9958 (neg:DF (float_extend:DF
9959 (match_operand:SF 1 "register_operand" "0"))))]
9962 [(set_attr "type" "fsgn")
9963 (set_attr "mode" "DF")])
9965 (define_insn "*negxf2_1"
9966 [(set (match_operand:XF 0 "register_operand" "=f")
9967 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
9968 "TARGET_80387 && reload_completed"
9970 [(set_attr "type" "fsgn")
9971 (set_attr "mode" "XF")])
9973 (define_insn "*negextenddfxf2"
9974 [(set (match_operand:XF 0 "register_operand" "=f")
9975 (neg:XF (float_extend:XF
9976 (match_operand:DF 1 "register_operand" "0"))))]
9979 [(set_attr "type" "fsgn")
9980 (set_attr "mode" "XF")])
9982 (define_insn "*negextendsfxf2"
9983 [(set (match_operand:XF 0 "register_operand" "=f")
9984 (neg:XF (float_extend:XF
9985 (match_operand:SF 1 "register_operand" "0"))))]
9988 [(set_attr "type" "fsgn")
9989 (set_attr "mode" "XF")])
9991 ;; Absolute value instructions
9993 (define_expand "abssf2"
9994 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9995 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9996 (clobber (reg:CC FLAGS_REG))])]
10000 /* In case operand is in memory, we will not use SSE. */
10001 if (memory_operand (operands[0], VOIDmode)
10002 && rtx_equal_p (operands[0], operands[1]))
10003 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
10006 /* Using SSE is tricky, since we need bitwise negation of -0
10008 rtx reg = gen_reg_rtx (V4SFmode);
10009 rtx dest = operands[0];
10012 operands[1] = force_reg (SFmode, operands[1]);
10013 operands[0] = force_reg (SFmode, operands[0]);
10014 imm = gen_lowpart (SFmode, gen_int_mode(~0x80000000, SImode));
10015 reg = force_reg (V4SFmode,
10016 gen_rtx_CONST_VECTOR (V4SFmode,
10017 gen_rtvec (4, imm, CONST0_RTX (SFmode),
10018 CONST0_RTX (SFmode),
10019 CONST0_RTX (SFmode))));
10020 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
10021 if (dest != operands[0])
10022 emit_move_insn (dest, operands[0]);
10026 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
10028 (define_insn "abssf2_memory"
10029 [(set (match_operand:SF 0 "memory_operand" "=m")
10030 (abs:SF (match_operand:SF 1 "memory_operand" "0")))
10031 (clobber (reg:CC FLAGS_REG))]
10032 "ix86_unary_operator_ok (ABS, SFmode, operands)"
10035 (define_insn "abssf2_ifs"
10036 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
10037 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
10038 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
10039 (clobber (reg:CC FLAGS_REG))]
10041 && (reload_in_progress || reload_completed
10042 || (register_operand (operands[0], VOIDmode)
10043 && register_operand (operands[1], VOIDmode)))"
10047 [(set (match_operand:SF 0 "memory_operand" "")
10048 (abs:SF (match_operand:SF 1 "memory_operand" "")))
10049 (use (match_operand:V4SF 2 "" ""))
10050 (clobber (reg:CC FLAGS_REG))]
10052 [(parallel [(set (match_dup 0)
10053 (abs:SF (match_dup 1)))
10054 (clobber (reg:CC FLAGS_REG))])])
10057 [(set (match_operand:SF 0 "register_operand" "")
10058 (abs:SF (match_operand:SF 1 "register_operand" "")))
10059 (use (match_operand:V4SF 2 "" ""))
10060 (clobber (reg:CC FLAGS_REG))]
10061 "reload_completed && !SSE_REG_P (operands[0])"
10062 [(parallel [(set (match_dup 0)
10063 (abs:SF (match_dup 1)))
10064 (clobber (reg:CC FLAGS_REG))])])
10067 [(set (match_operand:SF 0 "register_operand" "")
10068 (abs:SF (match_operand:SF 1 "register_operand" "")))
10069 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
10070 (clobber (reg:CC FLAGS_REG))]
10071 "reload_completed && SSE_REG_P (operands[0])"
10072 [(set (match_dup 0)
10073 (and:V4SF (match_dup 1)
10076 operands[0] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
10077 operands[1] = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
10078 if (operands_match_p (operands[0], operands[2]))
10082 operands[1] = operands[2];
10087 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10088 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10090 (define_insn "*abssf2_if"
10091 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
10092 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
10093 (clobber (reg:CC FLAGS_REG))]
10094 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
10098 [(set (match_operand:SF 0 "fp_register_operand" "")
10099 (abs:SF (match_operand:SF 1 "register_operand" "")))
10100 (clobber (reg:CC FLAGS_REG))]
10101 "TARGET_80387 && reload_completed"
10102 [(set (match_dup 0)
10103 (abs:SF (match_dup 1)))]
10107 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
10108 (abs:SF (match_operand:SF 1 "register_operand" "")))
10109 (clobber (reg:CC FLAGS_REG))]
10110 "TARGET_80387 && reload_completed"
10111 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10112 (clobber (reg:CC FLAGS_REG))])]
10113 "operands[1] = gen_int_mode (~0x80000000, SImode);
10114 operands[0] = gen_lowpart (SImode, operands[0]);")
10117 [(set (match_operand 0 "memory_operand" "")
10118 (abs (match_operand 1 "memory_operand" "")))
10119 (clobber (reg:CC FLAGS_REG))]
10120 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
10121 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
10122 (clobber (reg:CC FLAGS_REG))])]
10124 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
10126 if (GET_MODE (operands[1]) == XFmode)
10128 operands[0] = adjust_address (operands[0], QImode, size - 1);
10129 operands[1] = gen_int_mode (~0x80, QImode);
10132 (define_expand "absdf2"
10133 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
10134 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
10135 (clobber (reg:CC FLAGS_REG))])]
10139 /* In case operand is in memory, we will not use SSE. */
10140 if (memory_operand (operands[0], VOIDmode)
10141 && rtx_equal_p (operands[0], operands[1]))
10142 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
10145 /* Using SSE is tricky, since we need bitwise negation of -0
10147 rtx reg = gen_reg_rtx (V2DFmode);
10148 #if HOST_BITS_PER_WIDE_INT >= 64
10149 rtx imm = gen_int_mode (~(((HOST_WIDE_INT)1) << 63), DImode);
10151 rtx imm = immed_double_const (~0, ~0x80000000, DImode);
10153 rtx dest = operands[0];
10155 operands[1] = force_reg (DFmode, operands[1]);
10156 operands[0] = force_reg (DFmode, operands[0]);
10158 /* Produce LONG_DOUBLE with the proper immediate argument. */
10159 imm = gen_lowpart (DFmode, imm);
10160 reg = force_reg (V2DFmode,
10161 gen_rtx_CONST_VECTOR (V2DFmode,
10162 gen_rtvec (2, imm, CONST0_RTX (DFmode))));
10163 emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
10164 if (dest != operands[0])
10165 emit_move_insn (dest, operands[0]);
10169 ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
10171 (define_insn "absdf2_memory"
10172 [(set (match_operand:DF 0 "memory_operand" "=m")
10173 (abs:DF (match_operand:DF 1 "memory_operand" "0")))
10174 (clobber (reg:CC FLAGS_REG))]
10175 "ix86_unary_operator_ok (ABS, DFmode, operands)"
10178 (define_insn "absdf2_ifs"
10179 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr,mr#Yf")
10180 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
10181 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
10182 (clobber (reg:CC FLAGS_REG))]
10183 "!TARGET_64BIT && TARGET_SSE2
10184 && (reload_in_progress || reload_completed
10185 || (register_operand (operands[0], VOIDmode)
10186 && register_operand (operands[1], VOIDmode)))"
10189 (define_insn "*absdf2_ifs_rex64"
10190 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr")
10191 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
10192 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
10193 (clobber (reg:CC FLAGS_REG))]
10194 "TARGET_64BIT && TARGET_SSE2
10195 && (reload_in_progress || reload_completed
10196 || (register_operand (operands[0], VOIDmode)
10197 && register_operand (operands[1], VOIDmode)))"
10201 [(set (match_operand:DF 0 "memory_operand" "")
10202 (abs:DF (match_operand:DF 1 "memory_operand" "")))
10203 (use (match_operand:V2DF 2 "" ""))
10204 (clobber (reg:CC FLAGS_REG))]
10206 [(parallel [(set (match_dup 0)
10207 (abs:DF (match_dup 1)))
10208 (clobber (reg:CC FLAGS_REG))])])
10211 [(set (match_operand:DF 0 "register_operand" "")
10212 (abs:DF (match_operand:DF 1 "register_operand" "")))
10213 (use (match_operand:V2DF 2 "" ""))
10214 (clobber (reg:CC FLAGS_REG))]
10215 "reload_completed && !SSE_REG_P (operands[0])"
10216 [(parallel [(set (match_dup 0)
10217 (abs:DF (match_dup 1)))
10218 (clobber (reg:CC FLAGS_REG))])])
10221 [(set (match_operand:DF 0 "register_operand" "")
10222 (abs:DF (match_operand:DF 1 "register_operand" "")))
10223 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
10224 (clobber (reg:CC FLAGS_REG))]
10225 "reload_completed && SSE_REG_P (operands[0])"
10226 [(set (match_dup 0)
10227 (and:V2DF (match_dup 1)
10230 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
10231 operands[1] = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
10232 /* Avoid possible reformatting on the operands. */
10233 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
10234 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
10235 if (operands_match_p (operands[0], operands[2]))
10239 operands[1] = operands[2];
10245 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10246 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10248 (define_insn "*absdf2_if"
10249 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
10250 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10251 (clobber (reg:CC FLAGS_REG))]
10252 "!TARGET_64BIT && TARGET_80387
10253 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10256 ;; FIXME: We should to allow integer registers here. Problem is that
10257 ;; we need another scratch register to get constant from.
10258 ;; Forcing constant to mem if no register available in peep2 should be
10259 ;; safe even for PIC mode, because of RIP relative addressing.
10260 (define_insn "*absdf2_if_rex64"
10261 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
10262 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10263 (clobber (reg:CC FLAGS_REG))]
10264 "TARGET_64BIT && TARGET_80387
10265 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10269 [(set (match_operand:DF 0 "fp_register_operand" "")
10270 (abs:DF (match_operand:DF 1 "register_operand" "")))
10271 (clobber (reg:CC FLAGS_REG))]
10272 "TARGET_80387 && reload_completed"
10273 [(set (match_dup 0)
10274 (abs:DF (match_dup 1)))]
10278 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
10279 (abs:DF (match_operand:DF 1 "register_operand" "")))
10280 (clobber (reg:CC FLAGS_REG))]
10281 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10282 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
10283 (clobber (reg:CC FLAGS_REG))])]
10284 "operands[4] = gen_int_mode (~0x80000000, SImode);
10285 split_di (operands+0, 1, operands+2, operands+3);")
10287 (define_expand "absxf2"
10288 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
10289 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
10290 (clobber (reg:CC FLAGS_REG))])]
10292 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
10294 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10295 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10297 (define_insn "*absxf2_if"
10298 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
10299 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
10300 (clobber (reg:CC FLAGS_REG))]
10302 && ix86_unary_operator_ok (ABS, XFmode, operands)"
10306 [(set (match_operand:XF 0 "fp_register_operand" "")
10307 (abs:XF (match_operand:XF 1 "register_operand" "")))
10308 (clobber (reg:CC FLAGS_REG))]
10309 "TARGET_80387 && reload_completed"
10310 [(set (match_dup 0)
10311 (abs:XF (match_dup 1)))]
10315 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
10316 (abs:XF (match_operand:XF 1 "register_operand" "")))
10317 (clobber (reg:CC FLAGS_REG))]
10318 "TARGET_80387 && reload_completed"
10319 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10320 (clobber (reg:CC FLAGS_REG))])]
10321 "operands[1] = GEN_INT (~0x8000);
10322 operands[0] = gen_rtx_REG (SImode,
10323 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10325 (define_insn "*abssf2_1"
10326 [(set (match_operand:SF 0 "register_operand" "=f")
10327 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
10328 "TARGET_80387 && reload_completed"
10330 [(set_attr "type" "fsgn")
10331 (set_attr "mode" "SF")])
10333 (define_insn "*absdf2_1"
10334 [(set (match_operand:DF 0 "register_operand" "=f")
10335 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
10336 "TARGET_80387 && reload_completed"
10338 [(set_attr "type" "fsgn")
10339 (set_attr "mode" "DF")])
10341 (define_insn "*absextendsfdf2"
10342 [(set (match_operand:DF 0 "register_operand" "=f")
10343 (abs:DF (float_extend:DF
10344 (match_operand:SF 1 "register_operand" "0"))))]
10347 [(set_attr "type" "fsgn")
10348 (set_attr "mode" "DF")])
10350 (define_insn "*absxf2_1"
10351 [(set (match_operand:XF 0 "register_operand" "=f")
10352 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
10353 "TARGET_80387 && reload_completed"
10355 [(set_attr "type" "fsgn")
10356 (set_attr "mode" "DF")])
10358 (define_insn "*absextenddfxf2"
10359 [(set (match_operand:XF 0 "register_operand" "=f")
10360 (abs:XF (float_extend:XF
10361 (match_operand:DF 1 "register_operand" "0"))))]
10364 [(set_attr "type" "fsgn")
10365 (set_attr "mode" "XF")])
10367 (define_insn "*absextendsfxf2"
10368 [(set (match_operand:XF 0 "register_operand" "=f")
10369 (abs:XF (float_extend:XF
10370 (match_operand:SF 1 "register_operand" "0"))))]
10373 [(set_attr "type" "fsgn")
10374 (set_attr "mode" "XF")])
10376 ;; One complement instructions
10378 (define_expand "one_cmpldi2"
10379 [(set (match_operand:DI 0 "nonimmediate_operand" "")
10380 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
10382 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
10384 (define_insn "*one_cmpldi2_1_rex64"
10385 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10386 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
10387 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
10389 [(set_attr "type" "negnot")
10390 (set_attr "mode" "DI")])
10392 (define_insn "*one_cmpldi2_2_rex64"
10394 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
10396 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10397 (not:DI (match_dup 1)))]
10398 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10399 && ix86_unary_operator_ok (NOT, DImode, operands)"
10401 [(set_attr "type" "alu1")
10402 (set_attr "mode" "DI")])
10406 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
10408 (set (match_operand:DI 0 "nonimmediate_operand" "")
10409 (not:DI (match_dup 1)))]
10410 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
10411 [(parallel [(set (reg:CCNO FLAGS_REG)
10412 (compare:CCNO (xor:DI (match_dup 1) (const_int -1))
10415 (xor:DI (match_dup 1) (const_int -1)))])]
10418 (define_expand "one_cmplsi2"
10419 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10420 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
10422 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
10424 (define_insn "*one_cmplsi2_1"
10425 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10426 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
10427 "ix86_unary_operator_ok (NOT, SImode, operands)"
10429 [(set_attr "type" "negnot")
10430 (set_attr "mode" "SI")])
10432 ;; ??? Currently never generated - xor is used instead.
10433 (define_insn "*one_cmplsi2_1_zext"
10434 [(set (match_operand:DI 0 "register_operand" "=r")
10435 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
10436 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
10438 [(set_attr "type" "negnot")
10439 (set_attr "mode" "SI")])
10441 (define_insn "*one_cmplsi2_2"
10443 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
10445 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10446 (not:SI (match_dup 1)))]
10447 "ix86_match_ccmode (insn, CCNOmode)
10448 && ix86_unary_operator_ok (NOT, SImode, operands)"
10450 [(set_attr "type" "alu1")
10451 (set_attr "mode" "SI")])
10455 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
10457 (set (match_operand:SI 0 "nonimmediate_operand" "")
10458 (not:SI (match_dup 1)))]
10459 "ix86_match_ccmode (insn, CCNOmode)"
10460 [(parallel [(set (reg:CCNO FLAGS_REG)
10461 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10464 (xor:SI (match_dup 1) (const_int -1)))])]
10467 ;; ??? Currently never generated - xor is used instead.
10468 (define_insn "*one_cmplsi2_2_zext"
10470 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10472 (set (match_operand:DI 0 "register_operand" "=r")
10473 (zero_extend:DI (not:SI (match_dup 1))))]
10474 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10475 && ix86_unary_operator_ok (NOT, SImode, operands)"
10477 [(set_attr "type" "alu1")
10478 (set_attr "mode" "SI")])
10482 (compare (not:SI (match_operand:SI 1 "register_operand" ""))
10484 (set (match_operand:DI 0 "register_operand" "")
10485 (zero_extend:DI (not:SI (match_dup 1))))]
10486 "ix86_match_ccmode (insn, CCNOmode)"
10487 [(parallel [(set (reg:CCNO FLAGS_REG)
10488 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10491 (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])]
10494 (define_expand "one_cmplhi2"
10495 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10496 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10497 "TARGET_HIMODE_MATH"
10498 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10500 (define_insn "*one_cmplhi2_1"
10501 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10502 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10503 "ix86_unary_operator_ok (NOT, HImode, operands)"
10505 [(set_attr "type" "negnot")
10506 (set_attr "mode" "HI")])
10508 (define_insn "*one_cmplhi2_2"
10510 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10512 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10513 (not:HI (match_dup 1)))]
10514 "ix86_match_ccmode (insn, CCNOmode)
10515 && ix86_unary_operator_ok (NEG, HImode, operands)"
10517 [(set_attr "type" "alu1")
10518 (set_attr "mode" "HI")])
10522 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
10524 (set (match_operand:HI 0 "nonimmediate_operand" "")
10525 (not:HI (match_dup 1)))]
10526 "ix86_match_ccmode (insn, CCNOmode)"
10527 [(parallel [(set (reg:CCNO FLAGS_REG)
10528 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
10531 (xor:HI (match_dup 1) (const_int -1)))])]
10534 ;; %%% Potential partial reg stall on alternative 1. What to do?
10535 (define_expand "one_cmplqi2"
10536 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10537 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10538 "TARGET_QIMODE_MATH"
10539 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10541 (define_insn "*one_cmplqi2_1"
10542 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10543 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10544 "ix86_unary_operator_ok (NOT, QImode, operands)"
10548 [(set_attr "type" "negnot")
10549 (set_attr "mode" "QI,SI")])
10551 (define_insn "*one_cmplqi2_2"
10553 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10555 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10556 (not:QI (match_dup 1)))]
10557 "ix86_match_ccmode (insn, CCNOmode)
10558 && ix86_unary_operator_ok (NOT, QImode, operands)"
10560 [(set_attr "type" "alu1")
10561 (set_attr "mode" "QI")])
10565 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
10567 (set (match_operand:QI 0 "nonimmediate_operand" "")
10568 (not:QI (match_dup 1)))]
10569 "ix86_match_ccmode (insn, CCNOmode)"
10570 [(parallel [(set (reg:CCNO FLAGS_REG)
10571 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
10574 (xor:QI (match_dup 1) (const_int -1)))])]
10577 ;; Arithmetic shift instructions
10579 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10580 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10581 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10582 ;; from the assembler input.
10584 ;; This instruction shifts the target reg/mem as usual, but instead of
10585 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10586 ;; is a left shift double, bits are taken from the high order bits of
10587 ;; reg, else if the insn is a shift right double, bits are taken from the
10588 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10589 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10591 ;; Since sh[lr]d does not change the `reg' operand, that is done
10592 ;; separately, making all shifts emit pairs of shift double and normal
10593 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10594 ;; support a 63 bit shift, each shift where the count is in a reg expands
10595 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10597 ;; If the shift count is a constant, we need never emit more than one
10598 ;; shift pair, instead using moves and sign extension for counts greater
10601 (define_expand "ashldi3"
10602 [(set (match_operand:DI 0 "shiftdi_operand" "")
10603 (ashift:DI (match_operand:DI 1 "ashldi_input_operand" "")
10604 (match_operand:QI 2 "nonmemory_operand" "")))]
10606 "ix86_expand_binary_operator (ASHIFT, DImode, operands); DONE;")
10608 (define_insn "*ashldi3_1_rex64"
10609 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
10610 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
10611 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
10612 (clobber (reg:CC FLAGS_REG))]
10613 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10615 switch (get_attr_type (insn))
10618 if (operands[2] != const1_rtx)
10620 if (!rtx_equal_p (operands[0], operands[1]))
10622 return "add{q}\t{%0, %0|%0, %0}";
10625 if (GET_CODE (operands[2]) != CONST_INT
10626 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
10628 operands[1] = gen_rtx_MULT (DImode, operands[1],
10629 GEN_INT (1 << INTVAL (operands[2])));
10630 return "lea{q}\t{%a1, %0|%0, %a1}";
10633 if (REG_P (operands[2]))
10634 return "sal{q}\t{%b2, %0|%0, %b2}";
10635 else if (operands[2] == const1_rtx
10636 && (TARGET_SHIFT1 || optimize_size))
10637 return "sal{q}\t%0";
10639 return "sal{q}\t{%2, %0|%0, %2}";
10642 [(set (attr "type")
10643 (cond [(eq_attr "alternative" "1")
10644 (const_string "lea")
10645 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10647 (match_operand 0 "register_operand" ""))
10648 (match_operand 2 "const1_operand" ""))
10649 (const_string "alu")
10651 (const_string "ishift")))
10652 (set_attr "mode" "DI")])
10654 ;; Convert lea to the lea pattern to avoid flags dependency.
10656 [(set (match_operand:DI 0 "register_operand" "")
10657 (ashift:DI (match_operand:DI 1 "register_operand" "")
10658 (match_operand:QI 2 "immediate_operand" "")))
10659 (clobber (reg:CC FLAGS_REG))]
10660 "TARGET_64BIT && reload_completed
10661 && true_regnum (operands[0]) != true_regnum (operands[1])"
10662 [(set (match_dup 0)
10663 (mult:DI (match_dup 1)
10665 "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);")
10667 ;; This pattern can't accept a variable shift count, since shifts by
10668 ;; zero don't affect the flags. We assume that shifts by constant
10669 ;; zero are optimized away.
10670 (define_insn "*ashldi3_cmp_rex64"
10673 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10674 (match_operand:QI 2 "immediate_operand" "e"))
10676 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10677 (ashift:DI (match_dup 1) (match_dup 2)))]
10678 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10679 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10681 switch (get_attr_type (insn))
10684 if (operands[2] != const1_rtx)
10686 return "add{q}\t{%0, %0|%0, %0}";
10689 if (REG_P (operands[2]))
10690 return "sal{q}\t{%b2, %0|%0, %b2}";
10691 else if (operands[2] == const1_rtx
10692 && (TARGET_SHIFT1 || optimize_size))
10693 return "sal{q}\t%0";
10695 return "sal{q}\t{%2, %0|%0, %2}";
10698 [(set (attr "type")
10699 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10701 (match_operand 0 "register_operand" ""))
10702 (match_operand 2 "const1_operand" ""))
10703 (const_string "alu")
10705 (const_string "ishift")))
10706 (set_attr "mode" "DI")])
10708 (define_insn "*ashldi3_1"
10709 [(set (match_operand:DI 0 "register_operand" "=&r,r")
10710 (ashift:DI (match_operand:DI 1 "reg_or_pm1_operand" "n,0")
10711 (match_operand:QI 2 "nonmemory_operand" "Jc,Jc")))
10712 (clobber (reg:CC FLAGS_REG))]
10715 [(set_attr "type" "multi")])
10717 ;; By default we don't ask for a scratch register, because when DImode
10718 ;; values are manipulated, registers are already at a premium. But if
10719 ;; we have one handy, we won't turn it away.
10721 [(match_scratch:SI 3 "r")
10722 (parallel [(set (match_operand:DI 0 "register_operand" "")
10723 (ashift:DI (match_operand:DI 1 "nonmemory_operand" "")
10724 (match_operand:QI 2 "nonmemory_operand" "")))
10725 (clobber (reg:CC FLAGS_REG))])
10727 "!TARGET_64BIT && TARGET_CMOVE"
10729 "ix86_split_ashldi (operands, operands[3]); DONE;")
10732 [(set (match_operand:DI 0 "register_operand" "")
10733 (ashift:DI (match_operand:DI 1 "nonmemory_operand" "")
10734 (match_operand:QI 2 "nonmemory_operand" "")))
10735 (clobber (reg:CC FLAGS_REG))]
10736 "!TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)"
10738 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
10740 (define_insn "x86_shld_1"
10741 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10742 (ior:SI (ashift:SI (match_dup 0)
10743 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10744 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
10745 (minus:QI (const_int 32) (match_dup 2)))))
10746 (clobber (reg:CC FLAGS_REG))]
10749 shld{l}\t{%2, %1, %0|%0, %1, %2}
10750 shld{l}\t{%s2%1, %0|%0, %1, %2}"
10751 [(set_attr "type" "ishift")
10752 (set_attr "prefix_0f" "1")
10753 (set_attr "mode" "SI")
10754 (set_attr "pent_pair" "np")
10755 (set_attr "athlon_decode" "vector")])
10757 (define_expand "x86_shift_adj_1"
10758 [(set (reg:CCZ FLAGS_REG)
10759 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
10762 (set (match_operand:SI 0 "register_operand" "")
10763 (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0))
10764 (match_operand:SI 1 "register_operand" "")
10767 (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0))
10768 (match_operand:SI 3 "register_operand" "r")
10773 (define_expand "x86_shift_adj_2"
10774 [(use (match_operand:SI 0 "register_operand" ""))
10775 (use (match_operand:SI 1 "register_operand" ""))
10776 (use (match_operand:QI 2 "register_operand" ""))]
10779 rtx label = gen_label_rtx ();
10782 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
10784 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
10785 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
10786 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10787 gen_rtx_LABEL_REF (VOIDmode, label),
10789 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10790 JUMP_LABEL (tmp) = label;
10792 emit_move_insn (operands[0], operands[1]);
10793 ix86_expand_clear (operands[1]);
10795 emit_label (label);
10796 LABEL_NUSES (label) = 1;
10801 (define_expand "ashlsi3"
10802 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10803 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
10804 (match_operand:QI 2 "nonmemory_operand" "")))
10805 (clobber (reg:CC FLAGS_REG))]
10807 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
10809 (define_insn "*ashlsi3_1"
10810 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
10811 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
10812 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10813 (clobber (reg:CC FLAGS_REG))]
10814 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10816 switch (get_attr_type (insn))
10819 if (operands[2] != const1_rtx)
10821 if (!rtx_equal_p (operands[0], operands[1]))
10823 return "add{l}\t{%0, %0|%0, %0}";
10829 if (REG_P (operands[2]))
10830 return "sal{l}\t{%b2, %0|%0, %b2}";
10831 else if (operands[2] == const1_rtx
10832 && (TARGET_SHIFT1 || optimize_size))
10833 return "sal{l}\t%0";
10835 return "sal{l}\t{%2, %0|%0, %2}";
10838 [(set (attr "type")
10839 (cond [(eq_attr "alternative" "1")
10840 (const_string "lea")
10841 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10843 (match_operand 0 "register_operand" ""))
10844 (match_operand 2 "const1_operand" ""))
10845 (const_string "alu")
10847 (const_string "ishift")))
10848 (set_attr "mode" "SI")])
10850 ;; Convert lea to the lea pattern to avoid flags dependency.
10852 [(set (match_operand 0 "register_operand" "")
10853 (ashift (match_operand 1 "index_register_operand" "")
10854 (match_operand:QI 2 "const_int_operand" "")))
10855 (clobber (reg:CC FLAGS_REG))]
10857 && true_regnum (operands[0]) != true_regnum (operands[1])"
10861 operands[0] = gen_lowpart (SImode, operands[0]);
10862 operands[1] = gen_lowpart (Pmode, operands[1]);
10863 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10864 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
10865 if (Pmode != SImode)
10866 pat = gen_rtx_SUBREG (SImode, pat, 0);
10867 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
10871 ;; Rare case of shifting RSP is handled by generating move and shift
10873 [(set (match_operand 0 "register_operand" "")
10874 (ashift (match_operand 1 "register_operand" "")
10875 (match_operand:QI 2 "const_int_operand" "")))
10876 (clobber (reg:CC FLAGS_REG))]
10878 && true_regnum (operands[0]) != true_regnum (operands[1])"
10882 emit_move_insn (operands[1], operands[0]);
10883 pat = gen_rtx_SET (VOIDmode, operands[0],
10884 gen_rtx_ASHIFT (GET_MODE (operands[0]),
10885 operands[0], operands[2]));
10886 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10887 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob)));
10891 (define_insn "*ashlsi3_1_zext"
10892 [(set (match_operand:DI 0 "register_operand" "=r,r")
10893 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
10894 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
10895 (clobber (reg:CC FLAGS_REG))]
10896 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10898 switch (get_attr_type (insn))
10901 if (operands[2] != const1_rtx)
10903 return "add{l}\t{%k0, %k0|%k0, %k0}";
10909 if (REG_P (operands[2]))
10910 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10911 else if (operands[2] == const1_rtx
10912 && (TARGET_SHIFT1 || optimize_size))
10913 return "sal{l}\t%k0";
10915 return "sal{l}\t{%2, %k0|%k0, %2}";
10918 [(set (attr "type")
10919 (cond [(eq_attr "alternative" "1")
10920 (const_string "lea")
10921 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10923 (match_operand 2 "const1_operand" ""))
10924 (const_string "alu")
10926 (const_string "ishift")))
10927 (set_attr "mode" "SI")])
10929 ;; Convert lea to the lea pattern to avoid flags dependency.
10931 [(set (match_operand:DI 0 "register_operand" "")
10932 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
10933 (match_operand:QI 2 "const_int_operand" ""))))
10934 (clobber (reg:CC FLAGS_REG))]
10935 "TARGET_64BIT && reload_completed
10936 && true_regnum (operands[0]) != true_regnum (operands[1])"
10937 [(set (match_dup 0) (zero_extend:DI
10938 (subreg:SI (mult:SI (match_dup 1)
10939 (match_dup 2)) 0)))]
10941 operands[1] = gen_lowpart (Pmode, operands[1]);
10942 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10945 ;; This pattern can't accept a variable shift count, since shifts by
10946 ;; zero don't affect the flags. We assume that shifts by constant
10947 ;; zero are optimized away.
10948 (define_insn "*ashlsi3_cmp"
10951 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
10952 (match_operand:QI 2 "const_int_1_31_operand" "I"))
10954 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10955 (ashift:SI (match_dup 1) (match_dup 2)))]
10956 "ix86_match_ccmode (insn, CCGOCmode)
10957 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10959 switch (get_attr_type (insn))
10962 if (operands[2] != const1_rtx)
10964 return "add{l}\t{%0, %0|%0, %0}";
10967 if (REG_P (operands[2]))
10968 return "sal{l}\t{%b2, %0|%0, %b2}";
10969 else if (operands[2] == const1_rtx
10970 && (TARGET_SHIFT1 || optimize_size))
10971 return "sal{l}\t%0";
10973 return "sal{l}\t{%2, %0|%0, %2}";
10976 [(set (attr "type")
10977 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10979 (match_operand 0 "register_operand" ""))
10980 (match_operand 2 "const1_operand" ""))
10981 (const_string "alu")
10983 (const_string "ishift")))
10984 (set_attr "mode" "SI")])
10986 (define_insn "*ashlsi3_cmp_zext"
10989 (ashift:SI (match_operand:SI 1 "register_operand" "0")
10990 (match_operand:QI 2 "const_int_1_31_operand" "I"))
10992 (set (match_operand:DI 0 "register_operand" "=r")
10993 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
10994 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10995 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10997 switch (get_attr_type (insn))
11000 if (operands[2] != const1_rtx)
11002 return "add{l}\t{%k0, %k0|%k0, %k0}";
11005 if (REG_P (operands[2]))
11006 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11007 else if (operands[2] == const1_rtx
11008 && (TARGET_SHIFT1 || optimize_size))
11009 return "sal{l}\t%k0";
11011 return "sal{l}\t{%2, %k0|%k0, %2}";
11014 [(set (attr "type")
11015 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11017 (match_operand 2 "const1_operand" ""))
11018 (const_string "alu")
11020 (const_string "ishift")))
11021 (set_attr "mode" "SI")])
11023 (define_expand "ashlhi3"
11024 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11025 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
11026 (match_operand:QI 2 "nonmemory_operand" "")))
11027 (clobber (reg:CC FLAGS_REG))]
11028 "TARGET_HIMODE_MATH"
11029 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
11031 (define_insn "*ashlhi3_1_lea"
11032 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
11033 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
11034 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
11035 (clobber (reg:CC FLAGS_REG))]
11036 "!TARGET_PARTIAL_REG_STALL
11037 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11039 switch (get_attr_type (insn))
11044 if (operands[2] != const1_rtx)
11046 return "add{w}\t{%0, %0|%0, %0}";
11049 if (REG_P (operands[2]))
11050 return "sal{w}\t{%b2, %0|%0, %b2}";
11051 else if (operands[2] == const1_rtx
11052 && (TARGET_SHIFT1 || optimize_size))
11053 return "sal{w}\t%0";
11055 return "sal{w}\t{%2, %0|%0, %2}";
11058 [(set (attr "type")
11059 (cond [(eq_attr "alternative" "1")
11060 (const_string "lea")
11061 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11063 (match_operand 0 "register_operand" ""))
11064 (match_operand 2 "const1_operand" ""))
11065 (const_string "alu")
11067 (const_string "ishift")))
11068 (set_attr "mode" "HI,SI")])
11070 (define_insn "*ashlhi3_1"
11071 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11072 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11073 (match_operand:QI 2 "nonmemory_operand" "cI")))
11074 (clobber (reg:CC FLAGS_REG))]
11075 "TARGET_PARTIAL_REG_STALL
11076 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11078 switch (get_attr_type (insn))
11081 if (operands[2] != const1_rtx)
11083 return "add{w}\t{%0, %0|%0, %0}";
11086 if (REG_P (operands[2]))
11087 return "sal{w}\t{%b2, %0|%0, %b2}";
11088 else if (operands[2] == const1_rtx
11089 && (TARGET_SHIFT1 || optimize_size))
11090 return "sal{w}\t%0";
11092 return "sal{w}\t{%2, %0|%0, %2}";
11095 [(set (attr "type")
11096 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11098 (match_operand 0 "register_operand" ""))
11099 (match_operand 2 "const1_operand" ""))
11100 (const_string "alu")
11102 (const_string "ishift")))
11103 (set_attr "mode" "HI")])
11105 ;; This pattern can't accept a variable shift count, since shifts by
11106 ;; zero don't affect the flags. We assume that shifts by constant
11107 ;; zero are optimized away.
11108 (define_insn "*ashlhi3_cmp"
11111 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11112 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11114 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11115 (ashift:HI (match_dup 1) (match_dup 2)))]
11116 "ix86_match_ccmode (insn, CCGOCmode)
11117 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11119 switch (get_attr_type (insn))
11122 if (operands[2] != const1_rtx)
11124 return "add{w}\t{%0, %0|%0, %0}";
11127 if (REG_P (operands[2]))
11128 return "sal{w}\t{%b2, %0|%0, %b2}";
11129 else if (operands[2] == const1_rtx
11130 && (TARGET_SHIFT1 || optimize_size))
11131 return "sal{w}\t%0";
11133 return "sal{w}\t{%2, %0|%0, %2}";
11136 [(set (attr "type")
11137 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11139 (match_operand 0 "register_operand" ""))
11140 (match_operand 2 "const1_operand" ""))
11141 (const_string "alu")
11143 (const_string "ishift")))
11144 (set_attr "mode" "HI")])
11146 (define_expand "ashlqi3"
11147 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11148 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
11149 (match_operand:QI 2 "nonmemory_operand" "")))
11150 (clobber (reg:CC FLAGS_REG))]
11151 "TARGET_QIMODE_MATH"
11152 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
11154 ;; %%% Potential partial reg stall on alternative 2. What to do?
11156 (define_insn "*ashlqi3_1_lea"
11157 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
11158 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
11159 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
11160 (clobber (reg:CC FLAGS_REG))]
11161 "!TARGET_PARTIAL_REG_STALL
11162 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11164 switch (get_attr_type (insn))
11169 if (operands[2] != const1_rtx)
11171 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11172 return "add{l}\t{%k0, %k0|%k0, %k0}";
11174 return "add{b}\t{%0, %0|%0, %0}";
11177 if (REG_P (operands[2]))
11179 if (get_attr_mode (insn) == MODE_SI)
11180 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11182 return "sal{b}\t{%b2, %0|%0, %b2}";
11184 else if (operands[2] == const1_rtx
11185 && (TARGET_SHIFT1 || optimize_size))
11187 if (get_attr_mode (insn) == MODE_SI)
11188 return "sal{l}\t%0";
11190 return "sal{b}\t%0";
11194 if (get_attr_mode (insn) == MODE_SI)
11195 return "sal{l}\t{%2, %k0|%k0, %2}";
11197 return "sal{b}\t{%2, %0|%0, %2}";
11201 [(set (attr "type")
11202 (cond [(eq_attr "alternative" "2")
11203 (const_string "lea")
11204 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11206 (match_operand 0 "register_operand" ""))
11207 (match_operand 2 "const1_operand" ""))
11208 (const_string "alu")
11210 (const_string "ishift")))
11211 (set_attr "mode" "QI,SI,SI")])
11213 (define_insn "*ashlqi3_1"
11214 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
11215 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11216 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
11217 (clobber (reg:CC FLAGS_REG))]
11218 "TARGET_PARTIAL_REG_STALL
11219 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11221 switch (get_attr_type (insn))
11224 if (operands[2] != const1_rtx)
11226 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11227 return "add{l}\t{%k0, %k0|%k0, %k0}";
11229 return "add{b}\t{%0, %0|%0, %0}";
11232 if (REG_P (operands[2]))
11234 if (get_attr_mode (insn) == MODE_SI)
11235 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11237 return "sal{b}\t{%b2, %0|%0, %b2}";
11239 else if (operands[2] == const1_rtx
11240 && (TARGET_SHIFT1 || optimize_size))
11242 if (get_attr_mode (insn) == MODE_SI)
11243 return "sal{l}\t%0";
11245 return "sal{b}\t%0";
11249 if (get_attr_mode (insn) == MODE_SI)
11250 return "sal{l}\t{%2, %k0|%k0, %2}";
11252 return "sal{b}\t{%2, %0|%0, %2}";
11256 [(set (attr "type")
11257 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11259 (match_operand 0 "register_operand" ""))
11260 (match_operand 2 "const1_operand" ""))
11261 (const_string "alu")
11263 (const_string "ishift")))
11264 (set_attr "mode" "QI,SI")])
11266 ;; This pattern can't accept a variable shift count, since shifts by
11267 ;; zero don't affect the flags. We assume that shifts by constant
11268 ;; zero are optimized away.
11269 (define_insn "*ashlqi3_cmp"
11272 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11273 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11275 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11276 (ashift:QI (match_dup 1) (match_dup 2)))]
11277 "ix86_match_ccmode (insn, CCGOCmode)
11278 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11280 switch (get_attr_type (insn))
11283 if (operands[2] != const1_rtx)
11285 return "add{b}\t{%0, %0|%0, %0}";
11288 if (REG_P (operands[2]))
11289 return "sal{b}\t{%b2, %0|%0, %b2}";
11290 else if (operands[2] == const1_rtx
11291 && (TARGET_SHIFT1 || optimize_size))
11292 return "sal{b}\t%0";
11294 return "sal{b}\t{%2, %0|%0, %2}";
11297 [(set (attr "type")
11298 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11300 (match_operand 0 "register_operand" ""))
11301 (match_operand 2 "const1_operand" ""))
11302 (const_string "alu")
11304 (const_string "ishift")))
11305 (set_attr "mode" "QI")])
11307 ;; See comment above `ashldi3' about how this works.
11309 (define_expand "ashrdi3"
11310 [(set (match_operand:DI 0 "shiftdi_operand" "")
11311 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11312 (match_operand:QI 2 "nonmemory_operand" "")))]
11314 "ix86_expand_binary_operator (ASHIFTRT, DImode, operands); DONE;")
11316 (define_insn "*ashrdi3_63_rex64"
11317 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
11318 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
11319 (match_operand:DI 2 "const_int_operand" "i,i")))
11320 (clobber (reg:CC FLAGS_REG))]
11321 "TARGET_64BIT && INTVAL (operands[2]) == 63
11322 && (TARGET_USE_CLTD || optimize_size)
11323 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11326 sar{q}\t{%2, %0|%0, %2}"
11327 [(set_attr "type" "imovx,ishift")
11328 (set_attr "prefix_0f" "0,*")
11329 (set_attr "length_immediate" "0,*")
11330 (set_attr "modrm" "0,1")
11331 (set_attr "mode" "DI")])
11333 (define_insn "*ashrdi3_1_one_bit_rex64"
11334 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11335 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11336 (match_operand:QI 2 "const1_operand" "")))
11337 (clobber (reg:CC FLAGS_REG))]
11338 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
11339 && (TARGET_SHIFT1 || optimize_size)"
11341 [(set_attr "type" "ishift")
11342 (set (attr "length")
11343 (if_then_else (match_operand:DI 0 "register_operand" "")
11345 (const_string "*")))])
11347 (define_insn "*ashrdi3_1_rex64"
11348 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11349 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11350 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11351 (clobber (reg:CC FLAGS_REG))]
11352 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11354 sar{q}\t{%2, %0|%0, %2}
11355 sar{q}\t{%b2, %0|%0, %b2}"
11356 [(set_attr "type" "ishift")
11357 (set_attr "mode" "DI")])
11359 ;; This pattern can't accept a variable shift count, since shifts by
11360 ;; zero don't affect the flags. We assume that shifts by constant
11361 ;; zero are optimized away.
11362 (define_insn "*ashrdi3_one_bit_cmp_rex64"
11365 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11366 (match_operand:QI 2 "const1_operand" ""))
11368 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11369 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11370 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11371 && (TARGET_SHIFT1 || optimize_size)
11372 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11374 [(set_attr "type" "ishift")
11375 (set (attr "length")
11376 (if_then_else (match_operand:DI 0 "register_operand" "")
11378 (const_string "*")))])
11380 ;; This pattern can't accept a variable shift count, since shifts by
11381 ;; zero don't affect the flags. We assume that shifts by constant
11382 ;; zero are optimized away.
11383 (define_insn "*ashrdi3_cmp_rex64"
11386 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11387 (match_operand:QI 2 "const_int_operand" "n"))
11389 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11390 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11391 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11392 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11393 "sar{q}\t{%2, %0|%0, %2}"
11394 [(set_attr "type" "ishift")
11395 (set_attr "mode" "DI")])
11397 (define_insn "*ashrdi3_1"
11398 [(set (match_operand:DI 0 "register_operand" "=r")
11399 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11400 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11401 (clobber (reg:CC FLAGS_REG))]
11404 [(set_attr "type" "multi")])
11406 ;; By default we don't ask for a scratch register, because when DImode
11407 ;; values are manipulated, registers are already at a premium. But if
11408 ;; we have one handy, we won't turn it away.
11410 [(match_scratch:SI 3 "r")
11411 (parallel [(set (match_operand:DI 0 "register_operand" "")
11412 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11413 (match_operand:QI 2 "nonmemory_operand" "")))
11414 (clobber (reg:CC FLAGS_REG))])
11416 "!TARGET_64BIT && TARGET_CMOVE"
11418 "ix86_split_ashrdi (operands, operands[3]); DONE;")
11421 [(set (match_operand:DI 0 "register_operand" "")
11422 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11423 (match_operand:QI 2 "nonmemory_operand" "")))
11424 (clobber (reg:CC FLAGS_REG))]
11425 "!TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)"
11427 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
11429 (define_insn "x86_shrd_1"
11430 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11431 (ior:SI (ashiftrt:SI (match_dup 0)
11432 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11433 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
11434 (minus:QI (const_int 32) (match_dup 2)))))
11435 (clobber (reg:CC FLAGS_REG))]
11438 shrd{l}\t{%2, %1, %0|%0, %1, %2}
11439 shrd{l}\t{%s2%1, %0|%0, %1, %2}"
11440 [(set_attr "type" "ishift")
11441 (set_attr "prefix_0f" "1")
11442 (set_attr "pent_pair" "np")
11443 (set_attr "mode" "SI")])
11445 (define_expand "x86_shift_adj_3"
11446 [(use (match_operand:SI 0 "register_operand" ""))
11447 (use (match_operand:SI 1 "register_operand" ""))
11448 (use (match_operand:QI 2 "register_operand" ""))]
11451 rtx label = gen_label_rtx ();
11454 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11456 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11457 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11458 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11459 gen_rtx_LABEL_REF (VOIDmode, label),
11461 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11462 JUMP_LABEL (tmp) = label;
11464 emit_move_insn (operands[0], operands[1]);
11465 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
11467 emit_label (label);
11468 LABEL_NUSES (label) = 1;
11473 (define_insn "ashrsi3_31"
11474 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
11475 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
11476 (match_operand:SI 2 "const_int_operand" "i,i")))
11477 (clobber (reg:CC FLAGS_REG))]
11478 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11479 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11482 sar{l}\t{%2, %0|%0, %2}"
11483 [(set_attr "type" "imovx,ishift")
11484 (set_attr "prefix_0f" "0,*")
11485 (set_attr "length_immediate" "0,*")
11486 (set_attr "modrm" "0,1")
11487 (set_attr "mode" "SI")])
11489 (define_insn "*ashrsi3_31_zext"
11490 [(set (match_operand:DI 0 "register_operand" "=*d,r")
11491 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
11492 (match_operand:SI 2 "const_int_operand" "i,i"))))
11493 (clobber (reg:CC FLAGS_REG))]
11494 "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
11495 && INTVAL (operands[2]) == 31
11496 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11499 sar{l}\t{%2, %k0|%k0, %2}"
11500 [(set_attr "type" "imovx,ishift")
11501 (set_attr "prefix_0f" "0,*")
11502 (set_attr "length_immediate" "0,*")
11503 (set_attr "modrm" "0,1")
11504 (set_attr "mode" "SI")])
11506 (define_expand "ashrsi3"
11507 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11508 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11509 (match_operand:QI 2 "nonmemory_operand" "")))
11510 (clobber (reg:CC FLAGS_REG))]
11512 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11514 (define_insn "*ashrsi3_1_one_bit"
11515 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11516 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11517 (match_operand:QI 2 "const1_operand" "")))
11518 (clobber (reg:CC FLAGS_REG))]
11519 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11520 && (TARGET_SHIFT1 || optimize_size)"
11522 [(set_attr "type" "ishift")
11523 (set (attr "length")
11524 (if_then_else (match_operand:SI 0 "register_operand" "")
11526 (const_string "*")))])
11528 (define_insn "*ashrsi3_1_one_bit_zext"
11529 [(set (match_operand:DI 0 "register_operand" "=r")
11530 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11531 (match_operand:QI 2 "const1_operand" ""))))
11532 (clobber (reg:CC FLAGS_REG))]
11533 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11534 && (TARGET_SHIFT1 || optimize_size)"
11536 [(set_attr "type" "ishift")
11537 (set_attr "length" "2")])
11539 (define_insn "*ashrsi3_1"
11540 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11541 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11542 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11543 (clobber (reg:CC FLAGS_REG))]
11544 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11546 sar{l}\t{%2, %0|%0, %2}
11547 sar{l}\t{%b2, %0|%0, %b2}"
11548 [(set_attr "type" "ishift")
11549 (set_attr "mode" "SI")])
11551 (define_insn "*ashrsi3_1_zext"
11552 [(set (match_operand:DI 0 "register_operand" "=r,r")
11553 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11554 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11555 (clobber (reg:CC FLAGS_REG))]
11556 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11558 sar{l}\t{%2, %k0|%k0, %2}
11559 sar{l}\t{%b2, %k0|%k0, %b2}"
11560 [(set_attr "type" "ishift")
11561 (set_attr "mode" "SI")])
11563 ;; This pattern can't accept a variable shift count, since shifts by
11564 ;; zero don't affect the flags. We assume that shifts by constant
11565 ;; zero are optimized away.
11566 (define_insn "*ashrsi3_one_bit_cmp"
11569 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11570 (match_operand:QI 2 "const1_operand" ""))
11572 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11573 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11574 "ix86_match_ccmode (insn, CCGOCmode)
11575 && (TARGET_SHIFT1 || optimize_size)
11576 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11578 [(set_attr "type" "ishift")
11579 (set (attr "length")
11580 (if_then_else (match_operand:SI 0 "register_operand" "")
11582 (const_string "*")))])
11584 (define_insn "*ashrsi3_one_bit_cmp_zext"
11587 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11588 (match_operand:QI 2 "const1_operand" ""))
11590 (set (match_operand:DI 0 "register_operand" "=r")
11591 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11592 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
11593 && (TARGET_SHIFT1 || optimize_size)
11594 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11596 [(set_attr "type" "ishift")
11597 (set_attr "length" "2")])
11599 ;; This pattern can't accept a variable shift count, since shifts by
11600 ;; zero don't affect the flags. We assume that shifts by constant
11601 ;; zero are optimized away.
11602 (define_insn "*ashrsi3_cmp"
11605 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11606 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11608 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11609 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11610 "ix86_match_ccmode (insn, CCGOCmode)
11611 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11612 "sar{l}\t{%2, %0|%0, %2}"
11613 [(set_attr "type" "ishift")
11614 (set_attr "mode" "SI")])
11616 (define_insn "*ashrsi3_cmp_zext"
11619 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11620 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11622 (set (match_operand:DI 0 "register_operand" "=r")
11623 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11624 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11625 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11626 "sar{l}\t{%2, %k0|%k0, %2}"
11627 [(set_attr "type" "ishift")
11628 (set_attr "mode" "SI")])
11630 (define_expand "ashrhi3"
11631 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11632 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11633 (match_operand:QI 2 "nonmemory_operand" "")))
11634 (clobber (reg:CC FLAGS_REG))]
11635 "TARGET_HIMODE_MATH"
11636 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
11638 (define_insn "*ashrhi3_1_one_bit"
11639 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11640 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11641 (match_operand:QI 2 "const1_operand" "")))
11642 (clobber (reg:CC FLAGS_REG))]
11643 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
11644 && (TARGET_SHIFT1 || optimize_size)"
11646 [(set_attr "type" "ishift")
11647 (set (attr "length")
11648 (if_then_else (match_operand 0 "register_operand" "")
11650 (const_string "*")))])
11652 (define_insn "*ashrhi3_1"
11653 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11654 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11655 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11656 (clobber (reg:CC FLAGS_REG))]
11657 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11659 sar{w}\t{%2, %0|%0, %2}
11660 sar{w}\t{%b2, %0|%0, %b2}"
11661 [(set_attr "type" "ishift")
11662 (set_attr "mode" "HI")])
11664 ;; This pattern can't accept a variable shift count, since shifts by
11665 ;; zero don't affect the flags. We assume that shifts by constant
11666 ;; zero are optimized away.
11667 (define_insn "*ashrhi3_one_bit_cmp"
11670 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11671 (match_operand:QI 2 "const1_operand" ""))
11673 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11674 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11675 "ix86_match_ccmode (insn, CCGOCmode)
11676 && (TARGET_SHIFT1 || optimize_size)
11677 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11679 [(set_attr "type" "ishift")
11680 (set (attr "length")
11681 (if_then_else (match_operand 0 "register_operand" "")
11683 (const_string "*")))])
11685 ;; This pattern can't accept a variable shift count, since shifts by
11686 ;; zero don't affect the flags. We assume that shifts by constant
11687 ;; zero are optimized away.
11688 (define_insn "*ashrhi3_cmp"
11691 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11692 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11694 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11695 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11696 "ix86_match_ccmode (insn, CCGOCmode)
11697 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11698 "sar{w}\t{%2, %0|%0, %2}"
11699 [(set_attr "type" "ishift")
11700 (set_attr "mode" "HI")])
11702 (define_expand "ashrqi3"
11703 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11704 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11705 (match_operand:QI 2 "nonmemory_operand" "")))
11706 (clobber (reg:CC FLAGS_REG))]
11707 "TARGET_QIMODE_MATH"
11708 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
11710 (define_insn "*ashrqi3_1_one_bit"
11711 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11712 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11713 (match_operand:QI 2 "const1_operand" "")))
11714 (clobber (reg:CC FLAGS_REG))]
11715 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11716 && (TARGET_SHIFT1 || optimize_size)"
11718 [(set_attr "type" "ishift")
11719 (set (attr "length")
11720 (if_then_else (match_operand 0 "register_operand" "")
11722 (const_string "*")))])
11724 (define_insn "*ashrqi3_1_one_bit_slp"
11725 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11726 (ashiftrt:QI (match_dup 0)
11727 (match_operand:QI 1 "const1_operand" "")))
11728 (clobber (reg:CC FLAGS_REG))]
11729 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11730 && (! TARGET_PARTIAL_REG_STALL || optimize_size)
11731 && (TARGET_SHIFT1 || optimize_size)"
11733 [(set_attr "type" "ishift1")
11734 (set (attr "length")
11735 (if_then_else (match_operand 0 "register_operand" "")
11737 (const_string "*")))])
11739 (define_insn "*ashrqi3_1"
11740 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11741 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11742 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11743 (clobber (reg:CC FLAGS_REG))]
11744 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11746 sar{b}\t{%2, %0|%0, %2}
11747 sar{b}\t{%b2, %0|%0, %b2}"
11748 [(set_attr "type" "ishift")
11749 (set_attr "mode" "QI")])
11751 (define_insn "*ashrqi3_1_slp"
11752 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11753 (ashiftrt:QI (match_dup 0)
11754 (match_operand:QI 1 "nonmemory_operand" "I,c")))
11755 (clobber (reg:CC FLAGS_REG))]
11756 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11757 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
11759 sar{b}\t{%1, %0|%0, %1}
11760 sar{b}\t{%b1, %0|%0, %b1}"
11761 [(set_attr "type" "ishift1")
11762 (set_attr "mode" "QI")])
11764 ;; This pattern can't accept a variable shift count, since shifts by
11765 ;; zero don't affect the flags. We assume that shifts by constant
11766 ;; zero are optimized away.
11767 (define_insn "*ashrqi3_one_bit_cmp"
11770 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11771 (match_operand:QI 2 "const1_operand" "I"))
11773 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11774 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11775 "ix86_match_ccmode (insn, CCGOCmode)
11776 && (TARGET_SHIFT1 || optimize_size)
11777 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11779 [(set_attr "type" "ishift")
11780 (set (attr "length")
11781 (if_then_else (match_operand 0 "register_operand" "")
11783 (const_string "*")))])
11785 ;; This pattern can't accept a variable shift count, since shifts by
11786 ;; zero don't affect the flags. We assume that shifts by constant
11787 ;; zero are optimized away.
11788 (define_insn "*ashrqi3_cmp"
11791 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11792 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11794 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11795 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11796 "ix86_match_ccmode (insn, CCGOCmode)
11797 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11798 "sar{b}\t{%2, %0|%0, %2}"
11799 [(set_attr "type" "ishift")
11800 (set_attr "mode" "QI")])
11802 ;; Logical shift instructions
11804 ;; See comment above `ashldi3' about how this works.
11806 (define_expand "lshrdi3"
11807 [(set (match_operand:DI 0 "shiftdi_operand" "")
11808 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11809 (match_operand:QI 2 "nonmemory_operand" "")))]
11811 "ix86_expand_binary_operator (LSHIFTRT, DImode, operands); DONE;")
11813 (define_insn "*lshrdi3_1_one_bit_rex64"
11814 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11815 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11816 (match_operand:QI 2 "const1_operand" "")))
11817 (clobber (reg:CC FLAGS_REG))]
11818 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11819 && (TARGET_SHIFT1 || optimize_size)"
11821 [(set_attr "type" "ishift")
11822 (set (attr "length")
11823 (if_then_else (match_operand:DI 0 "register_operand" "")
11825 (const_string "*")))])
11827 (define_insn "*lshrdi3_1_rex64"
11828 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11829 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11830 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11831 (clobber (reg:CC FLAGS_REG))]
11832 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11834 shr{q}\t{%2, %0|%0, %2}
11835 shr{q}\t{%b2, %0|%0, %b2}"
11836 [(set_attr "type" "ishift")
11837 (set_attr "mode" "DI")])
11839 ;; This pattern can't accept a variable shift count, since shifts by
11840 ;; zero don't affect the flags. We assume that shifts by constant
11841 ;; zero are optimized away.
11842 (define_insn "*lshrdi3_cmp_one_bit_rex64"
11845 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11846 (match_operand:QI 2 "const1_operand" ""))
11848 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11849 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11850 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11851 && (TARGET_SHIFT1 || optimize_size)
11852 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11854 [(set_attr "type" "ishift")
11855 (set (attr "length")
11856 (if_then_else (match_operand:DI 0 "register_operand" "")
11858 (const_string "*")))])
11860 ;; This pattern can't accept a variable shift count, since shifts by
11861 ;; zero don't affect the flags. We assume that shifts by constant
11862 ;; zero are optimized away.
11863 (define_insn "*lshrdi3_cmp_rex64"
11866 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11867 (match_operand:QI 2 "const_int_operand" "e"))
11869 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11870 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11871 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11872 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11873 "shr{q}\t{%2, %0|%0, %2}"
11874 [(set_attr "type" "ishift")
11875 (set_attr "mode" "DI")])
11877 (define_insn "*lshrdi3_1"
11878 [(set (match_operand:DI 0 "register_operand" "=r")
11879 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11880 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11881 (clobber (reg:CC FLAGS_REG))]
11884 [(set_attr "type" "multi")])
11886 ;; By default we don't ask for a scratch register, because when DImode
11887 ;; values are manipulated, registers are already at a premium. But if
11888 ;; we have one handy, we won't turn it away.
11890 [(match_scratch:SI 3 "r")
11891 (parallel [(set (match_operand:DI 0 "register_operand" "")
11892 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11893 (match_operand:QI 2 "nonmemory_operand" "")))
11894 (clobber (reg:CC FLAGS_REG))])
11896 "!TARGET_64BIT && TARGET_CMOVE"
11898 "ix86_split_lshrdi (operands, operands[3]); DONE;")
11901 [(set (match_operand:DI 0 "register_operand" "")
11902 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11903 (match_operand:QI 2 "nonmemory_operand" "")))
11904 (clobber (reg:CC FLAGS_REG))]
11905 "!TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)"
11907 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
11909 (define_expand "lshrsi3"
11910 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11911 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11912 (match_operand:QI 2 "nonmemory_operand" "")))
11913 (clobber (reg:CC FLAGS_REG))]
11915 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
11917 (define_insn "*lshrsi3_1_one_bit"
11918 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11919 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11920 (match_operand:QI 2 "const1_operand" "")))
11921 (clobber (reg:CC FLAGS_REG))]
11922 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11923 && (TARGET_SHIFT1 || optimize_size)"
11925 [(set_attr "type" "ishift")
11926 (set (attr "length")
11927 (if_then_else (match_operand:SI 0 "register_operand" "")
11929 (const_string "*")))])
11931 (define_insn "*lshrsi3_1_one_bit_zext"
11932 [(set (match_operand:DI 0 "register_operand" "=r")
11933 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
11934 (match_operand:QI 2 "const1_operand" "")))
11935 (clobber (reg:CC FLAGS_REG))]
11936 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11937 && (TARGET_SHIFT1 || optimize_size)"
11939 [(set_attr "type" "ishift")
11940 (set_attr "length" "2")])
11942 (define_insn "*lshrsi3_1"
11943 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11944 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11945 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11946 (clobber (reg:CC FLAGS_REG))]
11947 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11949 shr{l}\t{%2, %0|%0, %2}
11950 shr{l}\t{%b2, %0|%0, %b2}"
11951 [(set_attr "type" "ishift")
11952 (set_attr "mode" "SI")])
11954 (define_insn "*lshrsi3_1_zext"
11955 [(set (match_operand:DI 0 "register_operand" "=r,r")
11957 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11958 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11959 (clobber (reg:CC FLAGS_REG))]
11960 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11962 shr{l}\t{%2, %k0|%k0, %2}
11963 shr{l}\t{%b2, %k0|%k0, %b2}"
11964 [(set_attr "type" "ishift")
11965 (set_attr "mode" "SI")])
11967 ;; This pattern can't accept a variable shift count, since shifts by
11968 ;; zero don't affect the flags. We assume that shifts by constant
11969 ;; zero are optimized away.
11970 (define_insn "*lshrsi3_one_bit_cmp"
11973 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11974 (match_operand:QI 2 "const1_operand" ""))
11976 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11977 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11978 "ix86_match_ccmode (insn, CCGOCmode)
11979 && (TARGET_SHIFT1 || optimize_size)
11980 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11982 [(set_attr "type" "ishift")
11983 (set (attr "length")
11984 (if_then_else (match_operand:SI 0 "register_operand" "")
11986 (const_string "*")))])
11988 (define_insn "*lshrsi3_cmp_one_bit_zext"
11991 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11992 (match_operand:QI 2 "const1_operand" ""))
11994 (set (match_operand:DI 0 "register_operand" "=r")
11995 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11996 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11997 && (TARGET_SHIFT1 || optimize_size)
11998 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12000 [(set_attr "type" "ishift")
12001 (set_attr "length" "2")])
12003 ;; This pattern can't accept a variable shift count, since shifts by
12004 ;; zero don't affect the flags. We assume that shifts by constant
12005 ;; zero are optimized away.
12006 (define_insn "*lshrsi3_cmp"
12009 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12010 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12012 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12013 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
12014 "ix86_match_ccmode (insn, CCGOCmode)
12015 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12016 "shr{l}\t{%2, %0|%0, %2}"
12017 [(set_attr "type" "ishift")
12018 (set_attr "mode" "SI")])
12020 (define_insn "*lshrsi3_cmp_zext"
12023 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12024 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12026 (set (match_operand:DI 0 "register_operand" "=r")
12027 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
12028 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12029 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12030 "shr{l}\t{%2, %k0|%k0, %2}"
12031 [(set_attr "type" "ishift")
12032 (set_attr "mode" "SI")])
12034 (define_expand "lshrhi3"
12035 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12036 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
12037 (match_operand:QI 2 "nonmemory_operand" "")))
12038 (clobber (reg:CC FLAGS_REG))]
12039 "TARGET_HIMODE_MATH"
12040 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
12042 (define_insn "*lshrhi3_1_one_bit"
12043 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12044 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12045 (match_operand:QI 2 "const1_operand" "")))
12046 (clobber (reg:CC FLAGS_REG))]
12047 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12048 && (TARGET_SHIFT1 || optimize_size)"
12050 [(set_attr "type" "ishift")
12051 (set (attr "length")
12052 (if_then_else (match_operand 0 "register_operand" "")
12054 (const_string "*")))])
12056 (define_insn "*lshrhi3_1"
12057 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12058 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12059 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12060 (clobber (reg:CC FLAGS_REG))]
12061 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12063 shr{w}\t{%2, %0|%0, %2}
12064 shr{w}\t{%b2, %0|%0, %b2}"
12065 [(set_attr "type" "ishift")
12066 (set_attr "mode" "HI")])
12068 ;; This pattern can't accept a variable shift count, since shifts by
12069 ;; zero don't affect the flags. We assume that shifts by constant
12070 ;; zero are optimized away.
12071 (define_insn "*lshrhi3_one_bit_cmp"
12074 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12075 (match_operand:QI 2 "const1_operand" ""))
12077 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12078 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
12079 "ix86_match_ccmode (insn, CCGOCmode)
12080 && (TARGET_SHIFT1 || optimize_size)
12081 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12083 [(set_attr "type" "ishift")
12084 (set (attr "length")
12085 (if_then_else (match_operand:SI 0 "register_operand" "")
12087 (const_string "*")))])
12089 ;; This pattern can't accept a variable shift count, since shifts by
12090 ;; zero don't affect the flags. We assume that shifts by constant
12091 ;; zero are optimized away.
12092 (define_insn "*lshrhi3_cmp"
12095 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12096 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12098 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12099 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
12100 "ix86_match_ccmode (insn, CCGOCmode)
12101 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12102 "shr{w}\t{%2, %0|%0, %2}"
12103 [(set_attr "type" "ishift")
12104 (set_attr "mode" "HI")])
12106 (define_expand "lshrqi3"
12107 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12108 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
12109 (match_operand:QI 2 "nonmemory_operand" "")))
12110 (clobber (reg:CC FLAGS_REG))]
12111 "TARGET_QIMODE_MATH"
12112 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
12114 (define_insn "*lshrqi3_1_one_bit"
12115 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12116 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12117 (match_operand:QI 2 "const1_operand" "")))
12118 (clobber (reg:CC FLAGS_REG))]
12119 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
12120 && (TARGET_SHIFT1 || optimize_size)"
12122 [(set_attr "type" "ishift")
12123 (set (attr "length")
12124 (if_then_else (match_operand 0 "register_operand" "")
12126 (const_string "*")))])
12128 (define_insn "*lshrqi3_1_one_bit_slp"
12129 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12130 (lshiftrt:QI (match_dup 0)
12131 (match_operand:QI 1 "const1_operand" "")))
12132 (clobber (reg:CC FLAGS_REG))]
12133 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12134 && (TARGET_SHIFT1 || optimize_size)"
12136 [(set_attr "type" "ishift1")
12137 (set (attr "length")
12138 (if_then_else (match_operand 0 "register_operand" "")
12140 (const_string "*")))])
12142 (define_insn "*lshrqi3_1"
12143 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12144 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12145 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12146 (clobber (reg:CC FLAGS_REG))]
12147 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12149 shr{b}\t{%2, %0|%0, %2}
12150 shr{b}\t{%b2, %0|%0, %b2}"
12151 [(set_attr "type" "ishift")
12152 (set_attr "mode" "QI")])
12154 (define_insn "*lshrqi3_1_slp"
12155 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12156 (lshiftrt:QI (match_dup 0)
12157 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12158 (clobber (reg:CC FLAGS_REG))]
12159 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12160 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12162 shr{b}\t{%1, %0|%0, %1}
12163 shr{b}\t{%b1, %0|%0, %b1}"
12164 [(set_attr "type" "ishift1")
12165 (set_attr "mode" "QI")])
12167 ;; This pattern can't accept a variable shift count, since shifts by
12168 ;; zero don't affect the flags. We assume that shifts by constant
12169 ;; zero are optimized away.
12170 (define_insn "*lshrqi2_one_bit_cmp"
12173 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12174 (match_operand:QI 2 "const1_operand" ""))
12176 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12177 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12178 "ix86_match_ccmode (insn, CCGOCmode)
12179 && (TARGET_SHIFT1 || optimize_size)
12180 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12182 [(set_attr "type" "ishift")
12183 (set (attr "length")
12184 (if_then_else (match_operand:SI 0 "register_operand" "")
12186 (const_string "*")))])
12188 ;; This pattern can't accept a variable shift count, since shifts by
12189 ;; zero don't affect the flags. We assume that shifts by constant
12190 ;; zero are optimized away.
12191 (define_insn "*lshrqi2_cmp"
12194 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12195 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12197 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12198 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12199 "ix86_match_ccmode (insn, CCGOCmode)
12200 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12201 "shr{b}\t{%2, %0|%0, %2}"
12202 [(set_attr "type" "ishift")
12203 (set_attr "mode" "QI")])
12205 ;; Rotate instructions
12207 (define_expand "rotldi3"
12208 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12209 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
12210 (match_operand:QI 2 "nonmemory_operand" "")))
12211 (clobber (reg:CC FLAGS_REG))]
12213 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
12215 (define_insn "*rotlsi3_1_one_bit_rex64"
12216 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12217 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12218 (match_operand:QI 2 "const1_operand" "")))
12219 (clobber (reg:CC FLAGS_REG))]
12220 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
12221 && (TARGET_SHIFT1 || optimize_size)"
12223 [(set_attr "type" "rotate")
12224 (set (attr "length")
12225 (if_then_else (match_operand:DI 0 "register_operand" "")
12227 (const_string "*")))])
12229 (define_insn "*rotldi3_1_rex64"
12230 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12231 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12232 (match_operand:QI 2 "nonmemory_operand" "e,c")))
12233 (clobber (reg:CC FLAGS_REG))]
12234 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
12236 rol{q}\t{%2, %0|%0, %2}
12237 rol{q}\t{%b2, %0|%0, %b2}"
12238 [(set_attr "type" "rotate")
12239 (set_attr "mode" "DI")])
12241 (define_expand "rotlsi3"
12242 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12243 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
12244 (match_operand:QI 2 "nonmemory_operand" "")))
12245 (clobber (reg:CC FLAGS_REG))]
12247 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
12249 (define_insn "*rotlsi3_1_one_bit"
12250 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12251 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12252 (match_operand:QI 2 "const1_operand" "")))
12253 (clobber (reg:CC FLAGS_REG))]
12254 "ix86_binary_operator_ok (ROTATE, SImode, operands)
12255 && (TARGET_SHIFT1 || optimize_size)"
12257 [(set_attr "type" "rotate")
12258 (set (attr "length")
12259 (if_then_else (match_operand:SI 0 "register_operand" "")
12261 (const_string "*")))])
12263 (define_insn "*rotlsi3_1_one_bit_zext"
12264 [(set (match_operand:DI 0 "register_operand" "=r")
12266 (rotate:SI (match_operand:SI 1 "register_operand" "0")
12267 (match_operand:QI 2 "const1_operand" ""))))
12268 (clobber (reg:CC FLAGS_REG))]
12269 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
12270 && (TARGET_SHIFT1 || optimize_size)"
12272 [(set_attr "type" "rotate")
12273 (set_attr "length" "2")])
12275 (define_insn "*rotlsi3_1"
12276 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12277 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12278 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12279 (clobber (reg:CC FLAGS_REG))]
12280 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
12282 rol{l}\t{%2, %0|%0, %2}
12283 rol{l}\t{%b2, %0|%0, %b2}"
12284 [(set_attr "type" "rotate")
12285 (set_attr "mode" "SI")])
12287 (define_insn "*rotlsi3_1_zext"
12288 [(set (match_operand:DI 0 "register_operand" "=r,r")
12290 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
12291 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12292 (clobber (reg:CC FLAGS_REG))]
12293 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
12295 rol{l}\t{%2, %k0|%k0, %2}
12296 rol{l}\t{%b2, %k0|%k0, %b2}"
12297 [(set_attr "type" "rotate")
12298 (set_attr "mode" "SI")])
12300 (define_expand "rotlhi3"
12301 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12302 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
12303 (match_operand:QI 2 "nonmemory_operand" "")))
12304 (clobber (reg:CC FLAGS_REG))]
12305 "TARGET_HIMODE_MATH"
12306 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
12308 (define_insn "*rotlhi3_1_one_bit"
12309 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12310 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12311 (match_operand:QI 2 "const1_operand" "")))
12312 (clobber (reg:CC FLAGS_REG))]
12313 "ix86_binary_operator_ok (ROTATE, HImode, operands)
12314 && (TARGET_SHIFT1 || optimize_size)"
12316 [(set_attr "type" "rotate")
12317 (set (attr "length")
12318 (if_then_else (match_operand 0 "register_operand" "")
12320 (const_string "*")))])
12322 (define_insn "*rotlhi3_1"
12323 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12324 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12325 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12326 (clobber (reg:CC FLAGS_REG))]
12327 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
12329 rol{w}\t{%2, %0|%0, %2}
12330 rol{w}\t{%b2, %0|%0, %b2}"
12331 [(set_attr "type" "rotate")
12332 (set_attr "mode" "HI")])
12334 (define_expand "rotlqi3"
12335 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12336 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
12337 (match_operand:QI 2 "nonmemory_operand" "")))
12338 (clobber (reg:CC FLAGS_REG))]
12339 "TARGET_QIMODE_MATH"
12340 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
12342 (define_insn "*rotlqi3_1_one_bit_slp"
12343 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12344 (rotate:QI (match_dup 0)
12345 (match_operand:QI 1 "const1_operand" "")))
12346 (clobber (reg:CC FLAGS_REG))]
12347 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12348 && (TARGET_SHIFT1 || optimize_size)"
12350 [(set_attr "type" "rotate1")
12351 (set (attr "length")
12352 (if_then_else (match_operand 0 "register_operand" "")
12354 (const_string "*")))])
12356 (define_insn "*rotlqi3_1_one_bit"
12357 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12358 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12359 (match_operand:QI 2 "const1_operand" "")))
12360 (clobber (reg:CC FLAGS_REG))]
12361 "ix86_binary_operator_ok (ROTATE, QImode, operands)
12362 && (TARGET_SHIFT1 || optimize_size)"
12364 [(set_attr "type" "rotate")
12365 (set (attr "length")
12366 (if_then_else (match_operand 0 "register_operand" "")
12368 (const_string "*")))])
12370 (define_insn "*rotlqi3_1_slp"
12371 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12372 (rotate:QI (match_dup 0)
12373 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12374 (clobber (reg:CC FLAGS_REG))]
12375 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12376 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12378 rol{b}\t{%1, %0|%0, %1}
12379 rol{b}\t{%b1, %0|%0, %b1}"
12380 [(set_attr "type" "rotate1")
12381 (set_attr "mode" "QI")])
12383 (define_insn "*rotlqi3_1"
12384 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12385 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12386 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12387 (clobber (reg:CC FLAGS_REG))]
12388 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
12390 rol{b}\t{%2, %0|%0, %2}
12391 rol{b}\t{%b2, %0|%0, %b2}"
12392 [(set_attr "type" "rotate")
12393 (set_attr "mode" "QI")])
12395 (define_expand "rotrdi3"
12396 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12397 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
12398 (match_operand:QI 2 "nonmemory_operand" "")))
12399 (clobber (reg:CC FLAGS_REG))]
12401 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
12403 (define_insn "*rotrdi3_1_one_bit_rex64"
12404 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12405 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12406 (match_operand:QI 2 "const1_operand" "")))
12407 (clobber (reg:CC FLAGS_REG))]
12408 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
12409 && (TARGET_SHIFT1 || optimize_size)"
12411 [(set_attr "type" "rotate")
12412 (set (attr "length")
12413 (if_then_else (match_operand:DI 0 "register_operand" "")
12415 (const_string "*")))])
12417 (define_insn "*rotrdi3_1_rex64"
12418 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12419 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12420 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12421 (clobber (reg:CC FLAGS_REG))]
12422 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
12424 ror{q}\t{%2, %0|%0, %2}
12425 ror{q}\t{%b2, %0|%0, %b2}"
12426 [(set_attr "type" "rotate")
12427 (set_attr "mode" "DI")])
12429 (define_expand "rotrsi3"
12430 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12431 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
12432 (match_operand:QI 2 "nonmemory_operand" "")))
12433 (clobber (reg:CC FLAGS_REG))]
12435 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
12437 (define_insn "*rotrsi3_1_one_bit"
12438 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12439 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12440 (match_operand:QI 2 "const1_operand" "")))
12441 (clobber (reg:CC FLAGS_REG))]
12442 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
12443 && (TARGET_SHIFT1 || optimize_size)"
12445 [(set_attr "type" "rotate")
12446 (set (attr "length")
12447 (if_then_else (match_operand:SI 0 "register_operand" "")
12449 (const_string "*")))])
12451 (define_insn "*rotrsi3_1_one_bit_zext"
12452 [(set (match_operand:DI 0 "register_operand" "=r")
12454 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12455 (match_operand:QI 2 "const1_operand" ""))))
12456 (clobber (reg:CC FLAGS_REG))]
12457 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12458 && (TARGET_SHIFT1 || optimize_size)"
12460 [(set_attr "type" "rotate")
12461 (set (attr "length")
12462 (if_then_else (match_operand:SI 0 "register_operand" "")
12464 (const_string "*")))])
12466 (define_insn "*rotrsi3_1"
12467 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12468 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12469 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12470 (clobber (reg:CC FLAGS_REG))]
12471 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12473 ror{l}\t{%2, %0|%0, %2}
12474 ror{l}\t{%b2, %0|%0, %b2}"
12475 [(set_attr "type" "rotate")
12476 (set_attr "mode" "SI")])
12478 (define_insn "*rotrsi3_1_zext"
12479 [(set (match_operand:DI 0 "register_operand" "=r,r")
12481 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12482 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12483 (clobber (reg:CC FLAGS_REG))]
12484 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12486 ror{l}\t{%2, %k0|%k0, %2}
12487 ror{l}\t{%b2, %k0|%k0, %b2}"
12488 [(set_attr "type" "rotate")
12489 (set_attr "mode" "SI")])
12491 (define_expand "rotrhi3"
12492 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12493 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12494 (match_operand:QI 2 "nonmemory_operand" "")))
12495 (clobber (reg:CC FLAGS_REG))]
12496 "TARGET_HIMODE_MATH"
12497 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12499 (define_insn "*rotrhi3_one_bit"
12500 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12501 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12502 (match_operand:QI 2 "const1_operand" "")))
12503 (clobber (reg:CC FLAGS_REG))]
12504 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12505 && (TARGET_SHIFT1 || optimize_size)"
12507 [(set_attr "type" "rotate")
12508 (set (attr "length")
12509 (if_then_else (match_operand 0 "register_operand" "")
12511 (const_string "*")))])
12513 (define_insn "*rotrhi3"
12514 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12515 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12516 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12517 (clobber (reg:CC FLAGS_REG))]
12518 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12520 ror{w}\t{%2, %0|%0, %2}
12521 ror{w}\t{%b2, %0|%0, %b2}"
12522 [(set_attr "type" "rotate")
12523 (set_attr "mode" "HI")])
12525 (define_expand "rotrqi3"
12526 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12527 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12528 (match_operand:QI 2 "nonmemory_operand" "")))
12529 (clobber (reg:CC FLAGS_REG))]
12530 "TARGET_QIMODE_MATH"
12531 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12533 (define_insn "*rotrqi3_1_one_bit"
12534 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12535 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12536 (match_operand:QI 2 "const1_operand" "")))
12537 (clobber (reg:CC FLAGS_REG))]
12538 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12539 && (TARGET_SHIFT1 || optimize_size)"
12541 [(set_attr "type" "rotate")
12542 (set (attr "length")
12543 (if_then_else (match_operand 0 "register_operand" "")
12545 (const_string "*")))])
12547 (define_insn "*rotrqi3_1_one_bit_slp"
12548 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12549 (rotatert:QI (match_dup 0)
12550 (match_operand:QI 1 "const1_operand" "")))
12551 (clobber (reg:CC FLAGS_REG))]
12552 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12553 && (TARGET_SHIFT1 || optimize_size)"
12555 [(set_attr "type" "rotate1")
12556 (set (attr "length")
12557 (if_then_else (match_operand 0 "register_operand" "")
12559 (const_string "*")))])
12561 (define_insn "*rotrqi3_1"
12562 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12563 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12564 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12565 (clobber (reg:CC FLAGS_REG))]
12566 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
12568 ror{b}\t{%2, %0|%0, %2}
12569 ror{b}\t{%b2, %0|%0, %b2}"
12570 [(set_attr "type" "rotate")
12571 (set_attr "mode" "QI")])
12573 (define_insn "*rotrqi3_1_slp"
12574 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12575 (rotatert:QI (match_dup 0)
12576 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12577 (clobber (reg:CC FLAGS_REG))]
12578 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12579 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12581 ror{b}\t{%1, %0|%0, %1}
12582 ror{b}\t{%b1, %0|%0, %b1}"
12583 [(set_attr "type" "rotate1")
12584 (set_attr "mode" "QI")])
12586 ;; Bit set / bit test instructions
12588 (define_expand "extv"
12589 [(set (match_operand:SI 0 "register_operand" "")
12590 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
12591 (match_operand:SI 2 "immediate_operand" "")
12592 (match_operand:SI 3 "immediate_operand" "")))]
12595 /* Handle extractions from %ah et al. */
12596 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12599 /* From mips.md: extract_bit_field doesn't verify that our source
12600 matches the predicate, so check it again here. */
12601 if (! register_operand (operands[1], VOIDmode))
12605 (define_expand "extzv"
12606 [(set (match_operand:SI 0 "register_operand" "")
12607 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
12608 (match_operand:SI 2 "immediate_operand" "")
12609 (match_operand:SI 3 "immediate_operand" "")))]
12612 /* Handle extractions from %ah et al. */
12613 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12616 /* From mips.md: extract_bit_field doesn't verify that our source
12617 matches the predicate, so check it again here. */
12618 if (! register_operand (operands[1], VOIDmode))
12622 (define_expand "insv"
12623 [(set (zero_extract (match_operand 0 "ext_register_operand" "")
12624 (match_operand 1 "immediate_operand" "")
12625 (match_operand 2 "immediate_operand" ""))
12626 (match_operand 3 "register_operand" ""))]
12629 /* Handle extractions from %ah et al. */
12630 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
12633 /* From mips.md: insert_bit_field doesn't verify that our source
12634 matches the predicate, so check it again here. */
12635 if (! register_operand (operands[0], VOIDmode))
12639 emit_insn (gen_movdi_insv_1_rex64 (operands[0], operands[3]));
12641 emit_insn (gen_movsi_insv_1 (operands[0], operands[3]));
12646 ;; %%% bts, btr, btc, bt.
12648 ;; Store-flag instructions.
12650 ;; For all sCOND expanders, also expand the compare or test insn that
12651 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
12653 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
12654 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
12655 ;; way, which can later delete the movzx if only QImode is needed.
12657 (define_expand "seq"
12658 [(set (match_operand:QI 0 "register_operand" "")
12659 (eq:QI (reg:CC FLAGS_REG) (const_int 0)))]
12661 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
12663 (define_expand "sne"
12664 [(set (match_operand:QI 0 "register_operand" "")
12665 (ne:QI (reg:CC FLAGS_REG) (const_int 0)))]
12667 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
12669 (define_expand "sgt"
12670 [(set (match_operand:QI 0 "register_operand" "")
12671 (gt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12673 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
12675 (define_expand "sgtu"
12676 [(set (match_operand:QI 0 "register_operand" "")
12677 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12679 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
12681 (define_expand "slt"
12682 [(set (match_operand:QI 0 "register_operand" "")
12683 (lt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12685 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
12687 (define_expand "sltu"
12688 [(set (match_operand:QI 0 "register_operand" "")
12689 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12691 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
12693 (define_expand "sge"
12694 [(set (match_operand:QI 0 "register_operand" "")
12695 (ge:QI (reg:CC FLAGS_REG) (const_int 0)))]
12697 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
12699 (define_expand "sgeu"
12700 [(set (match_operand:QI 0 "register_operand" "")
12701 (geu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12703 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
12705 (define_expand "sle"
12706 [(set (match_operand:QI 0 "register_operand" "")
12707 (le:QI (reg:CC FLAGS_REG) (const_int 0)))]
12709 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
12711 (define_expand "sleu"
12712 [(set (match_operand:QI 0 "register_operand" "")
12713 (leu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12715 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
12717 (define_expand "sunordered"
12718 [(set (match_operand:QI 0 "register_operand" "")
12719 (unordered:QI (reg:CC FLAGS_REG) (const_int 0)))]
12720 "TARGET_80387 || TARGET_SSE"
12721 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
12723 (define_expand "sordered"
12724 [(set (match_operand:QI 0 "register_operand" "")
12725 (ordered:QI (reg:CC FLAGS_REG) (const_int 0)))]
12727 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
12729 (define_expand "suneq"
12730 [(set (match_operand:QI 0 "register_operand" "")
12731 (uneq:QI (reg:CC FLAGS_REG) (const_int 0)))]
12732 "TARGET_80387 || TARGET_SSE"
12733 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
12735 (define_expand "sunge"
12736 [(set (match_operand:QI 0 "register_operand" "")
12737 (unge:QI (reg:CC FLAGS_REG) (const_int 0)))]
12738 "TARGET_80387 || TARGET_SSE"
12739 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
12741 (define_expand "sungt"
12742 [(set (match_operand:QI 0 "register_operand" "")
12743 (ungt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12744 "TARGET_80387 || TARGET_SSE"
12745 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
12747 (define_expand "sunle"
12748 [(set (match_operand:QI 0 "register_operand" "")
12749 (unle:QI (reg:CC FLAGS_REG) (const_int 0)))]
12750 "TARGET_80387 || TARGET_SSE"
12751 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
12753 (define_expand "sunlt"
12754 [(set (match_operand:QI 0 "register_operand" "")
12755 (unlt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12756 "TARGET_80387 || TARGET_SSE"
12757 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
12759 (define_expand "sltgt"
12760 [(set (match_operand:QI 0 "register_operand" "")
12761 (ltgt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12762 "TARGET_80387 || TARGET_SSE"
12763 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
12765 (define_insn "*setcc_1"
12766 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12767 (match_operator:QI 1 "ix86_comparison_operator"
12768 [(reg 17) (const_int 0)]))]
12771 [(set_attr "type" "setcc")
12772 (set_attr "mode" "QI")])
12774 (define_insn "*setcc_2"
12775 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12776 (match_operator:QI 1 "ix86_comparison_operator"
12777 [(reg 17) (const_int 0)]))]
12780 [(set_attr "type" "setcc")
12781 (set_attr "mode" "QI")])
12783 ;; In general it is not safe to assume too much about CCmode registers,
12784 ;; so simplify-rtx stops when it sees a second one. Under certain
12785 ;; conditions this is safe on x86, so help combine not create
12792 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12793 (ne:QI (match_operator 1 "ix86_comparison_operator"
12794 [(reg 17) (const_int 0)])
12797 [(set (match_dup 0) (match_dup 1))]
12799 PUT_MODE (operands[1], QImode);
12803 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12804 (ne:QI (match_operator 1 "ix86_comparison_operator"
12805 [(reg 17) (const_int 0)])
12808 [(set (match_dup 0) (match_dup 1))]
12810 PUT_MODE (operands[1], QImode);
12814 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12815 (eq:QI (match_operator 1 "ix86_comparison_operator"
12816 [(reg 17) (const_int 0)])
12819 [(set (match_dup 0) (match_dup 1))]
12821 rtx new_op1 = copy_rtx (operands[1]);
12822 operands[1] = new_op1;
12823 PUT_MODE (new_op1, QImode);
12824 PUT_CODE (new_op1, ix86_reverse_condition (GET_CODE (new_op1),
12825 GET_MODE (XEXP (new_op1, 0))));
12827 /* Make sure that (a) the CCmode we have for the flags is strong
12828 enough for the reversed compare or (b) we have a valid FP compare. */
12829 if (! ix86_comparison_operator (new_op1, VOIDmode))
12834 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12835 (eq:QI (match_operator 1 "ix86_comparison_operator"
12836 [(reg 17) (const_int 0)])
12839 [(set (match_dup 0) (match_dup 1))]
12841 rtx new_op1 = copy_rtx (operands[1]);
12842 operands[1] = new_op1;
12843 PUT_MODE (new_op1, QImode);
12844 PUT_CODE (new_op1, ix86_reverse_condition (GET_CODE (new_op1),
12845 GET_MODE (XEXP (new_op1, 0))));
12847 /* Make sure that (a) the CCmode we have for the flags is strong
12848 enough for the reversed compare or (b) we have a valid FP compare. */
12849 if (! ix86_comparison_operator (new_op1, VOIDmode))
12853 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
12854 ;; subsequent logical operations are used to imitate conditional moves.
12855 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
12856 ;; it directly. Further holding this value in pseudo register might bring
12857 ;; problem in implicit normalization in spill code.
12858 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
12859 ;; instructions after reload by splitting the conditional move patterns.
12861 (define_insn "*sse_setccsf"
12862 [(set (match_operand:SF 0 "register_operand" "=x")
12863 (match_operator:SF 1 "sse_comparison_operator"
12864 [(match_operand:SF 2 "register_operand" "0")
12865 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
12866 "TARGET_SSE && reload_completed"
12867 "cmp%D1ss\t{%3, %0|%0, %3}"
12868 [(set_attr "type" "ssecmp")
12869 (set_attr "mode" "SF")])
12871 (define_insn "*sse_setccdf"
12872 [(set (match_operand:DF 0 "register_operand" "=Y")
12873 (match_operator:DF 1 "sse_comparison_operator"
12874 [(match_operand:DF 2 "register_operand" "0")
12875 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
12876 "TARGET_SSE2 && reload_completed"
12877 "cmp%D1sd\t{%3, %0|%0, %3}"
12878 [(set_attr "type" "ssecmp")
12879 (set_attr "mode" "DF")])
12881 ;; Basic conditional jump instructions.
12882 ;; We ignore the overflow flag for signed branch instructions.
12884 ;; For all bCOND expanders, also expand the compare or test insn that
12885 ;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
12887 (define_expand "beq"
12889 (if_then_else (match_dup 1)
12890 (label_ref (match_operand 0 "" ""))
12893 "ix86_expand_branch (EQ, operands[0]); DONE;")
12895 (define_expand "bne"
12897 (if_then_else (match_dup 1)
12898 (label_ref (match_operand 0 "" ""))
12901 "ix86_expand_branch (NE, operands[0]); DONE;")
12903 (define_expand "bgt"
12905 (if_then_else (match_dup 1)
12906 (label_ref (match_operand 0 "" ""))
12909 "ix86_expand_branch (GT, operands[0]); DONE;")
12911 (define_expand "bgtu"
12913 (if_then_else (match_dup 1)
12914 (label_ref (match_operand 0 "" ""))
12917 "ix86_expand_branch (GTU, operands[0]); DONE;")
12919 (define_expand "blt"
12921 (if_then_else (match_dup 1)
12922 (label_ref (match_operand 0 "" ""))
12925 "ix86_expand_branch (LT, operands[0]); DONE;")
12927 (define_expand "bltu"
12929 (if_then_else (match_dup 1)
12930 (label_ref (match_operand 0 "" ""))
12933 "ix86_expand_branch (LTU, operands[0]); DONE;")
12935 (define_expand "bge"
12937 (if_then_else (match_dup 1)
12938 (label_ref (match_operand 0 "" ""))
12941 "ix86_expand_branch (GE, operands[0]); DONE;")
12943 (define_expand "bgeu"
12945 (if_then_else (match_dup 1)
12946 (label_ref (match_operand 0 "" ""))
12949 "ix86_expand_branch (GEU, operands[0]); DONE;")
12951 (define_expand "ble"
12953 (if_then_else (match_dup 1)
12954 (label_ref (match_operand 0 "" ""))
12957 "ix86_expand_branch (LE, operands[0]); DONE;")
12959 (define_expand "bleu"
12961 (if_then_else (match_dup 1)
12962 (label_ref (match_operand 0 "" ""))
12965 "ix86_expand_branch (LEU, operands[0]); DONE;")
12967 (define_expand "bunordered"
12969 (if_then_else (match_dup 1)
12970 (label_ref (match_operand 0 "" ""))
12972 "TARGET_80387 || TARGET_SSE"
12973 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
12975 (define_expand "bordered"
12977 (if_then_else (match_dup 1)
12978 (label_ref (match_operand 0 "" ""))
12980 "TARGET_80387 || TARGET_SSE"
12981 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
12983 (define_expand "buneq"
12985 (if_then_else (match_dup 1)
12986 (label_ref (match_operand 0 "" ""))
12988 "TARGET_80387 || TARGET_SSE"
12989 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
12991 (define_expand "bunge"
12993 (if_then_else (match_dup 1)
12994 (label_ref (match_operand 0 "" ""))
12996 "TARGET_80387 || TARGET_SSE"
12997 "ix86_expand_branch (UNGE, operands[0]); DONE;")
12999 (define_expand "bungt"
13001 (if_then_else (match_dup 1)
13002 (label_ref (match_operand 0 "" ""))
13004 "TARGET_80387 || TARGET_SSE"
13005 "ix86_expand_branch (UNGT, operands[0]); DONE;")
13007 (define_expand "bunle"
13009 (if_then_else (match_dup 1)
13010 (label_ref (match_operand 0 "" ""))
13012 "TARGET_80387 || TARGET_SSE"
13013 "ix86_expand_branch (UNLE, operands[0]); DONE;")
13015 (define_expand "bunlt"
13017 (if_then_else (match_dup 1)
13018 (label_ref (match_operand 0 "" ""))
13020 "TARGET_80387 || TARGET_SSE"
13021 "ix86_expand_branch (UNLT, operands[0]); DONE;")
13023 (define_expand "bltgt"
13025 (if_then_else (match_dup 1)
13026 (label_ref (match_operand 0 "" ""))
13028 "TARGET_80387 || TARGET_SSE"
13029 "ix86_expand_branch (LTGT, operands[0]); DONE;")
13031 (define_insn "*jcc_1"
13033 (if_then_else (match_operator 1 "ix86_comparison_operator"
13034 [(reg 17) (const_int 0)])
13035 (label_ref (match_operand 0 "" ""))
13039 [(set_attr "type" "ibr")
13040 (set_attr "modrm" "0")
13041 (set (attr "length")
13042 (if_then_else (and (ge (minus (match_dup 0) (pc))
13044 (lt (minus (match_dup 0) (pc))
13049 (define_insn "*jcc_2"
13051 (if_then_else (match_operator 1 "ix86_comparison_operator"
13052 [(reg 17) (const_int 0)])
13054 (label_ref (match_operand 0 "" ""))))]
13057 [(set_attr "type" "ibr")
13058 (set_attr "modrm" "0")
13059 (set (attr "length")
13060 (if_then_else (and (ge (minus (match_dup 0) (pc))
13062 (lt (minus (match_dup 0) (pc))
13067 ;; In general it is not safe to assume too much about CCmode registers,
13068 ;; so simplify-rtx stops when it sees a second one. Under certain
13069 ;; conditions this is safe on x86, so help combine not create
13077 (if_then_else (ne (match_operator 0 "ix86_comparison_operator"
13078 [(reg 17) (const_int 0)])
13080 (label_ref (match_operand 1 "" ""))
13084 (if_then_else (match_dup 0)
13085 (label_ref (match_dup 1))
13088 PUT_MODE (operands[0], VOIDmode);
13093 (if_then_else (eq (match_operator 0 "ix86_comparison_operator"
13094 [(reg 17) (const_int 0)])
13096 (label_ref (match_operand 1 "" ""))
13100 (if_then_else (match_dup 0)
13101 (label_ref (match_dup 1))
13104 rtx new_op0 = copy_rtx (operands[0]);
13105 operands[0] = new_op0;
13106 PUT_MODE (new_op0, VOIDmode);
13107 PUT_CODE (new_op0, ix86_reverse_condition (GET_CODE (new_op0),
13108 GET_MODE (XEXP (new_op0, 0))));
13110 /* Make sure that (a) the CCmode we have for the flags is strong
13111 enough for the reversed compare or (b) we have a valid FP compare. */
13112 if (! ix86_comparison_operator (new_op0, VOIDmode))
13116 ;; Define combination compare-and-branch fp compare instructions to use
13117 ;; during early optimization. Splitting the operation apart early makes
13118 ;; for bad code when we want to reverse the operation.
13120 (define_insn "*fp_jcc_1"
13122 (if_then_else (match_operator 0 "comparison_operator"
13123 [(match_operand 1 "register_operand" "f")
13124 (match_operand 2 "register_operand" "f")])
13125 (label_ref (match_operand 3 "" ""))
13127 (clobber (reg:CCFP FPSR_REG))
13128 (clobber (reg:CCFP FLAGS_REG))]
13129 "TARGET_CMOVE && TARGET_80387
13130 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13131 && FLOAT_MODE_P (GET_MODE (operands[1]))
13132 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13133 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13136 (define_insn "*fp_jcc_1_sse"
13138 (if_then_else (match_operator 0 "comparison_operator"
13139 [(match_operand 1 "register_operand" "f#x,x#f")
13140 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
13141 (label_ref (match_operand 3 "" ""))
13143 (clobber (reg:CCFP FPSR_REG))
13144 (clobber (reg:CCFP FLAGS_REG))]
13146 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13147 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13148 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13151 (define_insn "*fp_jcc_1_sse_only"
13153 (if_then_else (match_operator 0 "comparison_operator"
13154 [(match_operand 1 "register_operand" "x")
13155 (match_operand 2 "nonimmediate_operand" "xm")])
13156 (label_ref (match_operand 3 "" ""))
13158 (clobber (reg:CCFP FPSR_REG))
13159 (clobber (reg:CCFP FLAGS_REG))]
13160 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13161 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13162 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13165 (define_insn "*fp_jcc_2"
13167 (if_then_else (match_operator 0 "comparison_operator"
13168 [(match_operand 1 "register_operand" "f")
13169 (match_operand 2 "register_operand" "f")])
13171 (label_ref (match_operand 3 "" ""))))
13172 (clobber (reg:CCFP FPSR_REG))
13173 (clobber (reg:CCFP FLAGS_REG))]
13174 "TARGET_CMOVE && TARGET_80387
13175 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13176 && FLOAT_MODE_P (GET_MODE (operands[1]))
13177 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13178 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13181 (define_insn "*fp_jcc_2_sse"
13183 (if_then_else (match_operator 0 "comparison_operator"
13184 [(match_operand 1 "register_operand" "f#x,x#f")
13185 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
13187 (label_ref (match_operand 3 "" ""))))
13188 (clobber (reg:CCFP FPSR_REG))
13189 (clobber (reg:CCFP FLAGS_REG))]
13191 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13192 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13193 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13196 (define_insn "*fp_jcc_2_sse_only"
13198 (if_then_else (match_operator 0 "comparison_operator"
13199 [(match_operand 1 "register_operand" "x")
13200 (match_operand 2 "nonimmediate_operand" "xm")])
13202 (label_ref (match_operand 3 "" ""))))
13203 (clobber (reg:CCFP FPSR_REG))
13204 (clobber (reg:CCFP FLAGS_REG))]
13205 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13206 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13207 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13210 (define_insn "*fp_jcc_3"
13212 (if_then_else (match_operator 0 "comparison_operator"
13213 [(match_operand 1 "register_operand" "f")
13214 (match_operand 2 "nonimmediate_operand" "fm")])
13215 (label_ref (match_operand 3 "" ""))
13217 (clobber (reg:CCFP FPSR_REG))
13218 (clobber (reg:CCFP FLAGS_REG))
13219 (clobber (match_scratch:HI 4 "=a"))]
13221 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13222 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13223 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13224 && SELECT_CC_MODE (GET_CODE (operands[0]),
13225 operands[1], operands[2]) == CCFPmode
13226 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13229 (define_insn "*fp_jcc_4"
13231 (if_then_else (match_operator 0 "comparison_operator"
13232 [(match_operand 1 "register_operand" "f")
13233 (match_operand 2 "nonimmediate_operand" "fm")])
13235 (label_ref (match_operand 3 "" ""))))
13236 (clobber (reg:CCFP FPSR_REG))
13237 (clobber (reg:CCFP FLAGS_REG))
13238 (clobber (match_scratch:HI 4 "=a"))]
13240 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13241 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13242 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13243 && SELECT_CC_MODE (GET_CODE (operands[0]),
13244 operands[1], operands[2]) == CCFPmode
13245 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13248 (define_insn "*fp_jcc_5"
13250 (if_then_else (match_operator 0 "comparison_operator"
13251 [(match_operand 1 "register_operand" "f")
13252 (match_operand 2 "register_operand" "f")])
13253 (label_ref (match_operand 3 "" ""))
13255 (clobber (reg:CCFP FPSR_REG))
13256 (clobber (reg:CCFP FLAGS_REG))
13257 (clobber (match_scratch:HI 4 "=a"))]
13259 && FLOAT_MODE_P (GET_MODE (operands[1]))
13260 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13261 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13264 (define_insn "*fp_jcc_6"
13266 (if_then_else (match_operator 0 "comparison_operator"
13267 [(match_operand 1 "register_operand" "f")
13268 (match_operand 2 "register_operand" "f")])
13270 (label_ref (match_operand 3 "" ""))))
13271 (clobber (reg:CCFP FPSR_REG))
13272 (clobber (reg:CCFP FLAGS_REG))
13273 (clobber (match_scratch:HI 4 "=a"))]
13275 && FLOAT_MODE_P (GET_MODE (operands[1]))
13276 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13277 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13280 (define_insn "*fp_jcc_7"
13282 (if_then_else (match_operator 0 "comparison_operator"
13283 [(match_operand 1 "register_operand" "f")
13284 (match_operand 2 "const_double_operand" "C")])
13285 (label_ref (match_operand 3 "" ""))
13287 (clobber (reg:CCFP FPSR_REG))
13288 (clobber (reg:CCFP FLAGS_REG))
13289 (clobber (match_scratch:HI 4 "=a"))]
13291 && FLOAT_MODE_P (GET_MODE (operands[1]))
13292 && operands[2] == CONST0_RTX (GET_MODE (operands[1]))
13293 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13294 && SELECT_CC_MODE (GET_CODE (operands[0]),
13295 operands[1], operands[2]) == CCFPmode
13296 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13301 (if_then_else (match_operator 0 "comparison_operator"
13302 [(match_operand 1 "register_operand" "")
13303 (match_operand 2 "nonimmediate_operand" "")])
13304 (match_operand 3 "" "")
13305 (match_operand 4 "" "")))
13306 (clobber (reg:CCFP FPSR_REG))
13307 (clobber (reg:CCFP FLAGS_REG))]
13311 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13312 operands[3], operands[4], NULL_RTX);
13318 (if_then_else (match_operator 0 "comparison_operator"
13319 [(match_operand 1 "register_operand" "")
13320 (match_operand 2 "general_operand" "")])
13321 (match_operand 3 "" "")
13322 (match_operand 4 "" "")))
13323 (clobber (reg:CCFP FPSR_REG))
13324 (clobber (reg:CCFP FLAGS_REG))
13325 (clobber (match_scratch:HI 5 "=a"))]
13329 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13330 operands[3], operands[4], operands[5]);
13334 ;; Unconditional and other jump instructions
13336 (define_insn "jump"
13338 (label_ref (match_operand 0 "" "")))]
13341 [(set_attr "type" "ibr")
13342 (set (attr "length")
13343 (if_then_else (and (ge (minus (match_dup 0) (pc))
13345 (lt (minus (match_dup 0) (pc))
13349 (set_attr "modrm" "0")])
13351 (define_expand "indirect_jump"
13352 [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))]
13356 (define_insn "*indirect_jump"
13357 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
13360 [(set_attr "type" "ibr")
13361 (set_attr "length_immediate" "0")])
13363 (define_insn "*indirect_jump_rtx64"
13364 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))]
13367 [(set_attr "type" "ibr")
13368 (set_attr "length_immediate" "0")])
13370 (define_expand "tablejump"
13371 [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))
13372 (use (label_ref (match_operand 1 "" "")))])]
13375 /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
13376 relative. Convert the relative address to an absolute address. */
13380 enum rtx_code code;
13386 op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
13388 else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA)
13392 op1 = pic_offset_table_rtx;
13397 op0 = pic_offset_table_rtx;
13401 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
13406 (define_insn "*tablejump_1"
13407 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13408 (use (label_ref (match_operand 1 "" "")))]
13411 [(set_attr "type" "ibr")
13412 (set_attr "length_immediate" "0")])
13414 (define_insn "*tablejump_1_rtx64"
13415 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))
13416 (use (label_ref (match_operand 1 "" "")))]
13419 [(set_attr "type" "ibr")
13420 (set_attr "length_immediate" "0")])
13422 ;; Loop instruction
13424 ;; This is all complicated by the fact that since this is a jump insn
13425 ;; we must handle our own reloads.
13427 (define_expand "doloop_end"
13428 [(use (match_operand 0 "" "")) ; loop pseudo
13429 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13430 (use (match_operand 2 "" "")) ; max iterations
13431 (use (match_operand 3 "" "")) ; loop level
13432 (use (match_operand 4 "" ""))] ; label
13433 "!TARGET_64BIT && TARGET_USE_LOOP"
13436 /* Only use cloop on innermost loops. */
13437 if (INTVAL (operands[3]) > 1)
13439 if (GET_MODE (operands[0]) != SImode)
13441 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
13446 (define_insn "doloop_end_internal"
13448 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
13450 (label_ref (match_operand 0 "" ""))
13452 (set (match_operand:SI 2 "nonimmediate_operand" "=1,1,*m*r")
13453 (plus:SI (match_dup 1)
13455 (clobber (match_scratch:SI 3 "=X,X,r"))
13456 (clobber (reg:CC FLAGS_REG))]
13457 "!TARGET_64BIT && TARGET_USE_LOOP
13458 && (reload_in_progress || reload_completed
13459 || register_operand (operands[2], VOIDmode))"
13461 if (which_alternative != 0)
13463 if (get_attr_length (insn) == 2)
13464 return "%+loop\t%l0";
13466 return "dec{l}\t%1\;%+jne\t%l0";
13468 [(set (attr "length")
13469 (if_then_else (and (eq_attr "alternative" "0")
13470 (and (ge (minus (match_dup 0) (pc))
13472 (lt (minus (match_dup 0) (pc))
13476 ;; We don't know the type before shorten branches. Optimistically expect
13477 ;; the loop instruction to match.
13478 (set (attr "type") (const_string "ibr"))])
13482 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13484 (match_operand 0 "" "")
13487 (plus:SI (match_dup 1)
13489 (clobber (match_scratch:SI 2 ""))
13490 (clobber (reg:CC FLAGS_REG))]
13491 "!TARGET_64BIT && TARGET_USE_LOOP
13492 && reload_completed
13493 && REGNO (operands[1]) != 2"
13494 [(parallel [(set (reg:CCZ FLAGS_REG)
13495 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
13497 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
13498 (set (pc) (if_then_else (ne (reg:CCZ FLAGS_REG) (const_int 0))
13505 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13507 (match_operand 0 "" "")
13509 (set (match_operand:SI 2 "nonimmediate_operand" "")
13510 (plus:SI (match_dup 1)
13512 (clobber (match_scratch:SI 3 ""))
13513 (clobber (reg:CC FLAGS_REG))]
13514 "!TARGET_64BIT && TARGET_USE_LOOP
13515 && reload_completed
13516 && (! REG_P (operands[2])
13517 || ! rtx_equal_p (operands[1], operands[2]))"
13518 [(set (match_dup 3) (match_dup 1))
13519 (parallel [(set (reg:CCZ FLAGS_REG)
13520 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
13522 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
13523 (set (match_dup 2) (match_dup 3))
13524 (set (pc) (if_then_else (ne (reg:CCZ FLAGS_REG) (const_int 0))
13529 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
13532 [(set (reg 17) (match_operand 0 "" ""))
13533 (set (match_operand:QI 1 "register_operand" "")
13534 (match_operator:QI 2 "ix86_comparison_operator"
13535 [(reg 17) (const_int 0)]))
13536 (set (match_operand 3 "q_regs_operand" "")
13537 (zero_extend (match_dup 1)))]
13538 "(peep2_reg_dead_p (3, operands[1])
13539 || operands_match_p (operands[1], operands[3]))
13540 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13541 [(set (match_dup 4) (match_dup 0))
13542 (set (strict_low_part (match_dup 5))
13545 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13546 operands[5] = gen_lowpart (QImode, operands[3]);
13547 ix86_expand_clear (operands[3]);
13550 ;; Similar, but match zero_extendhisi2_and, which adds a clobber.
13553 [(set (reg 17) (match_operand 0 "" ""))
13554 (set (match_operand:QI 1 "register_operand" "")
13555 (match_operator:QI 2 "ix86_comparison_operator"
13556 [(reg 17) (const_int 0)]))
13557 (parallel [(set (match_operand 3 "q_regs_operand" "")
13558 (zero_extend (match_dup 1)))
13559 (clobber (reg:CC FLAGS_REG))])]
13560 "(peep2_reg_dead_p (3, operands[1])
13561 || operands_match_p (operands[1], operands[3]))
13562 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13563 [(set (match_dup 4) (match_dup 0))
13564 (set (strict_low_part (match_dup 5))
13567 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13568 operands[5] = gen_lowpart (QImode, operands[3]);
13569 ix86_expand_clear (operands[3]);
13572 ;; Call instructions.
13574 ;; The predicates normally associated with named expanders are not properly
13575 ;; checked for calls. This is a bug in the generic code, but it isn't that
13576 ;; easy to fix. Ignore it for now and be prepared to fix things up.
13578 ;; Call subroutine returning no value.
13580 (define_expand "call_pop"
13581 [(parallel [(call (match_operand:QI 0 "" "")
13582 (match_operand:SI 1 "" ""))
13583 (set (reg:SI SP_REG)
13584 (plus:SI (reg:SI SP_REG)
13585 (match_operand:SI 3 "" "")))])]
13588 ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3], 0);
13592 (define_insn "*call_pop_0"
13593 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
13594 (match_operand:SI 1 "" ""))
13595 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
13596 (match_operand:SI 2 "immediate_operand" "")))]
13599 if (SIBLING_CALL_P (insn))
13602 return "call\t%P0";
13604 [(set_attr "type" "call")])
13606 (define_insn "*call_pop_1"
13607 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13608 (match_operand:SI 1 "" ""))
13609 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
13610 (match_operand:SI 2 "immediate_operand" "i")))]
13613 if (constant_call_address_operand (operands[0], Pmode))
13615 if (SIBLING_CALL_P (insn))
13618 return "call\t%P0";
13620 if (SIBLING_CALL_P (insn))
13623 return "call\t%A0";
13625 [(set_attr "type" "call")])
13627 (define_expand "call"
13628 [(call (match_operand:QI 0 "" "")
13629 (match_operand 1 "" ""))
13630 (use (match_operand 2 "" ""))]
13633 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 0);
13637 (define_expand "sibcall"
13638 [(call (match_operand:QI 0 "" "")
13639 (match_operand 1 "" ""))
13640 (use (match_operand 2 "" ""))]
13643 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 1);
13647 (define_insn "*call_0"
13648 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
13649 (match_operand 1 "" ""))]
13652 if (SIBLING_CALL_P (insn))
13655 return "call\t%P0";
13657 [(set_attr "type" "call")])
13659 (define_insn "*call_1"
13660 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13661 (match_operand 1 "" ""))]
13662 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
13664 if (constant_call_address_operand (operands[0], Pmode))
13665 return "call\t%P0";
13666 return "call\t%A0";
13668 [(set_attr "type" "call")])
13670 (define_insn "*sibcall_1"
13671 [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,c,d,a"))
13672 (match_operand 1 "" ""))]
13673 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
13675 if (constant_call_address_operand (operands[0], Pmode))
13679 [(set_attr "type" "call")])
13681 (define_insn "*call_1_rex64"
13682 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
13683 (match_operand 1 "" ""))]
13684 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
13686 if (constant_call_address_operand (operands[0], Pmode))
13687 return "call\t%P0";
13688 return "call\t%A0";
13690 [(set_attr "type" "call")])
13692 (define_insn "*sibcall_1_rex64"
13693 [(call (mem:QI (match_operand:DI 0 "constant_call_address_operand" ""))
13694 (match_operand 1 "" ""))]
13695 "SIBLING_CALL_P (insn) && TARGET_64BIT"
13697 [(set_attr "type" "call")])
13699 (define_insn "*sibcall_1_rex64_v"
13700 [(call (mem:QI (reg:DI 40))
13701 (match_operand 0 "" ""))]
13702 "SIBLING_CALL_P (insn) && TARGET_64BIT"
13704 [(set_attr "type" "call")])
13707 ;; Call subroutine, returning value in operand 0
13709 (define_expand "call_value_pop"
13710 [(parallel [(set (match_operand 0 "" "")
13711 (call (match_operand:QI 1 "" "")
13712 (match_operand:SI 2 "" "")))
13713 (set (reg:SI SP_REG)
13714 (plus:SI (reg:SI SP_REG)
13715 (match_operand:SI 4 "" "")))])]
13718 ix86_expand_call (operands[0], operands[1], operands[2],
13719 operands[3], operands[4], 0);
13723 (define_expand "call_value"
13724 [(set (match_operand 0 "" "")
13725 (call (match_operand:QI 1 "" "")
13726 (match_operand:SI 2 "" "")))
13727 (use (match_operand:SI 3 "" ""))]
13728 ;; Operand 2 not used on the i386.
13731 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 0);
13735 (define_expand "sibcall_value"
13736 [(set (match_operand 0 "" "")
13737 (call (match_operand:QI 1 "" "")
13738 (match_operand:SI 2 "" "")))
13739 (use (match_operand:SI 3 "" ""))]
13740 ;; Operand 2 not used on the i386.
13743 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 1);
13747 ;; Call subroutine returning any type.
13749 (define_expand "untyped_call"
13750 [(parallel [(call (match_operand 0 "" "")
13752 (match_operand 1 "" "")
13753 (match_operand 2 "" "")])]
13758 /* In order to give reg-stack an easier job in validating two
13759 coprocessor registers as containing a possible return value,
13760 simply pretend the untyped call returns a complex long double
13763 ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
13764 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
13765 operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1),
13768 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13770 rtx set = XVECEXP (operands[2], 0, i);
13771 emit_move_insn (SET_DEST (set), SET_SRC (set));
13774 /* The optimizer does not know that the call sets the function value
13775 registers we stored in the result block. We avoid problems by
13776 claiming that all hard registers are used and clobbered at this
13778 emit_insn (gen_blockage (const0_rtx));
13783 ;; Prologue and epilogue instructions
13785 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13786 ;; all of memory. This blocks insns from being moved across this point.
13788 (define_insn "blockage"
13789 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_BLOCKAGE)]
13792 [(set_attr "length" "0")])
13794 ;; Insn emitted into the body of a function to return from a function.
13795 ;; This is only done if the function's epilogue is known to be simple.
13796 ;; See comments for ix86_can_use_return_insn_p in i386.c.
13798 (define_expand "return"
13800 "ix86_can_use_return_insn_p ()"
13802 if (current_function_pops_args)
13804 rtx popc = GEN_INT (current_function_pops_args);
13805 emit_jump_insn (gen_return_pop_internal (popc));
13810 (define_insn "return_internal"
13814 [(set_attr "length" "1")
13815 (set_attr "length_immediate" "0")
13816 (set_attr "modrm" "0")])
13818 ;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET
13819 ;; instruction Athlon and K8 have.
13821 (define_insn "return_internal_long"
13823 (unspec [(const_int 0)] UNSPEC_REP)]
13826 [(set_attr "length" "1")
13827 (set_attr "length_immediate" "0")
13828 (set_attr "prefix_rep" "1")
13829 (set_attr "modrm" "0")])
13831 (define_insn "return_pop_internal"
13833 (use (match_operand:SI 0 "const_int_operand" ""))]
13836 [(set_attr "length" "3")
13837 (set_attr "length_immediate" "2")
13838 (set_attr "modrm" "0")])
13840 (define_insn "return_indirect_internal"
13842 (use (match_operand:SI 0 "register_operand" "r"))]
13845 [(set_attr "type" "ibr")
13846 (set_attr "length_immediate" "0")])
13852 [(set_attr "length" "1")
13853 (set_attr "length_immediate" "0")
13854 (set_attr "modrm" "0")])
13856 ;; Align to 16-byte boundary, max skip in op0. Used to avoid
13857 ;; branch prediction penalty for the third jump in a 16-byte
13860 (define_insn "align"
13861 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_ALIGN)]
13864 #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
13865 ASM_OUTPUT_MAX_SKIP_ALIGN (asm_out_file, 4, (int)INTVAL (operands[0]));
13867 /* It is tempting to use ASM_OUTPUT_ALIGN here, but we don't want to do that.
13868 The align insn is used to avoid 3 jump instructions in the row to improve
13869 branch prediction and the benefits hardly outweight the cost of extra 8
13870 nops on the average inserted by full alignment pseudo operation. */
13874 [(set_attr "length" "16")])
13876 (define_expand "prologue"
13879 "ix86_expand_prologue (); DONE;")
13881 (define_insn "set_got"
13882 [(set (match_operand:SI 0 "register_operand" "=r")
13883 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
13884 (clobber (reg:CC FLAGS_REG))]
13886 { return output_set_got (operands[0]); }
13887 [(set_attr "type" "multi")
13888 (set_attr "length" "12")])
13890 (define_expand "epilogue"
13893 "ix86_expand_epilogue (1); DONE;")
13895 (define_expand "sibcall_epilogue"
13898 "ix86_expand_epilogue (0); DONE;")
13900 (define_expand "eh_return"
13901 [(use (match_operand 0 "register_operand" ""))]
13904 rtx tmp, sa = EH_RETURN_STACKADJ_RTX, ra = operands[0];
13906 /* Tricky bit: we write the address of the handler to which we will
13907 be returning into someone else's stack frame, one word below the
13908 stack address we wish to restore. */
13909 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
13910 tmp = plus_constant (tmp, -UNITS_PER_WORD);
13911 tmp = gen_rtx_MEM (Pmode, tmp);
13912 emit_move_insn (tmp, ra);
13914 if (Pmode == SImode)
13915 emit_jump_insn (gen_eh_return_si (sa));
13917 emit_jump_insn (gen_eh_return_di (sa));
13922 (define_insn_and_split "eh_return_si"
13924 (unspec [(match_operand:SI 0 "register_operand" "c")]
13925 UNSPEC_EH_RETURN))]
13930 "ix86_expand_epilogue (2); DONE;")
13932 (define_insn_and_split "eh_return_di"
13934 (unspec [(match_operand:DI 0 "register_operand" "c")]
13935 UNSPEC_EH_RETURN))]
13940 "ix86_expand_epilogue (2); DONE;")
13942 (define_insn "leave"
13943 [(set (reg:SI SP_REG) (plus:SI (reg:SI BP_REG) (const_int 4)))
13944 (set (reg:SI BP_REG) (mem:SI (reg:SI BP_REG)))
13945 (clobber (mem:BLK (scratch)))]
13948 [(set_attr "type" "leave")])
13950 (define_insn "leave_rex64"
13951 [(set (reg:DI SP_REG) (plus:DI (reg:DI BP_REG) (const_int 8)))
13952 (set (reg:DI BP_REG) (mem:DI (reg:DI BP_REG)))
13953 (clobber (mem:BLK (scratch)))]
13956 [(set_attr "type" "leave")])
13958 (define_expand "ffssi2"
13960 [(set (match_operand:SI 0 "register_operand" "")
13961 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))
13962 (clobber (match_scratch:SI 2 ""))
13963 (clobber (reg:CC FLAGS_REG))])]
13967 (define_insn_and_split "*ffs_cmove"
13968 [(set (match_operand:SI 0 "register_operand" "=r")
13969 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
13970 (clobber (match_scratch:SI 2 "=&r"))
13971 (clobber (reg:CC FLAGS_REG))]
13974 "&& reload_completed"
13975 [(set (match_dup 2) (const_int -1))
13976 (parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 1) (const_int 0)))
13977 (set (match_dup 0) (ctz:SI (match_dup 1)))])
13978 (set (match_dup 0) (if_then_else:SI
13979 (eq (reg:CCZ FLAGS_REG) (const_int 0))
13982 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
13983 (clobber (reg:CC FLAGS_REG))])]
13986 (define_insn_and_split "*ffs_no_cmove"
13987 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
13988 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
13989 (clobber (match_scratch:SI 2 "=&q"))
13990 (clobber (reg:CC FLAGS_REG))]
13994 [(parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 1) (const_int 0)))
13995 (set (match_dup 0) (ctz:SI (match_dup 1)))])
13996 (set (strict_low_part (match_dup 3))
13997 (eq:QI (reg:CCZ FLAGS_REG) (const_int 0)))
13998 (parallel [(set (match_dup 2) (neg:SI (match_dup 2)))
13999 (clobber (reg:CC FLAGS_REG))])
14000 (parallel [(set (match_dup 0) (ior:SI (match_dup 0) (match_dup 2)))
14001 (clobber (reg:CC FLAGS_REG))])
14002 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14003 (clobber (reg:CC FLAGS_REG))])]
14005 operands[3] = gen_lowpart (QImode, operands[2]);
14006 ix86_expand_clear (operands[2]);
14009 (define_insn "*ffssi_1"
14010 [(set (reg:CCZ FLAGS_REG)
14011 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
14013 (set (match_operand:SI 0 "register_operand" "=r")
14014 (ctz:SI (match_dup 1)))]
14016 "bsf{l}\t{%1, %0|%0, %1}"
14017 [(set_attr "prefix_0f" "1")])
14019 (define_expand "ffsdi2"
14021 [(set (match_operand:DI 0 "register_operand" "")
14022 (ffs:DI (match_operand:DI 1 "nonimmediate_operand" "")))
14023 (clobber (match_scratch:DI 2 ""))
14024 (clobber (reg:CC 17))])]
14025 "TARGET_64BIT && TARGET_CMOVE"
14028 (define_insn_and_split "*ffs_rex64"
14029 [(set (match_operand:DI 0 "register_operand" "=r")
14030 (ffs:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
14031 (clobber (match_scratch:DI 2 "=&r"))
14032 (clobber (reg:CC 17))]
14033 "TARGET_64BIT && TARGET_CMOVE"
14035 "&& reload_completed"
14036 [(set (match_dup 2) (const_int -1))
14037 (parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
14038 (set (match_dup 0) (ctz:DI (match_dup 1)))])
14039 (set (match_dup 0) (if_then_else:DI
14040 (eq (reg:CCZ 17) (const_int 0))
14043 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
14044 (clobber (reg:CC 17))])]
14047 (define_insn "*ffsdi_1"
14049 (compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "rm")
14051 (set (match_operand:DI 0 "register_operand" "=r")
14052 (ctz:DI (match_dup 1)))]
14054 "bsf{q}\t{%1, %0|%0, %1}"
14055 [(set_attr "prefix_0f" "1")])
14057 (define_insn "ctzsi2"
14058 [(set (match_operand:SI 0 "register_operand" "=r")
14059 (ctz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14060 (clobber (reg:CC FLAGS_REG))]
14062 "bsf{l}\t{%1, %0|%0, %1}"
14063 [(set_attr "prefix_0f" "1")])
14065 (define_insn "ctzdi2"
14066 [(set (match_operand:DI 0 "register_operand" "=r")
14067 (ctz:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
14068 (clobber (reg:CC 17))]
14070 "bsf{q}\t{%1, %0|%0, %1}"
14071 [(set_attr "prefix_0f" "1")])
14073 (define_expand "clzsi2"
14075 [(set (match_operand:SI 0 "register_operand" "")
14076 (minus:SI (const_int 31)
14077 (clz:SI (match_operand:SI 1 "nonimmediate_operand" ""))))
14078 (clobber (reg:CC FLAGS_REG))])
14080 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31)))
14081 (clobber (reg:CC FLAGS_REG))])]
14085 (define_insn "*bsr"
14086 [(set (match_operand:SI 0 "register_operand" "=r")
14087 (minus:SI (const_int 31)
14088 (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
14089 (clobber (reg:CC FLAGS_REG))]
14091 "bsr{l}\t{%1, %0|%0, %1}"
14092 [(set_attr "prefix_0f" "1")])
14094 (define_expand "clzdi2"
14096 [(set (match_operand:DI 0 "register_operand" "")
14097 (minus:DI (const_int 63)
14098 (clz:DI (match_operand:DI 1 "nonimmediate_operand" ""))))
14099 (clobber (reg:CC 17))])
14101 [(set (match_dup 0) (xor:DI (match_dup 0) (const_int 63)))
14102 (clobber (reg:CC 17))])]
14106 (define_insn "*bsr_rex64"
14107 [(set (match_operand:DI 0 "register_operand" "=r")
14108 (minus:DI (const_int 63)
14109 (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))))
14110 (clobber (reg:CC 17))]
14112 "bsr{q}\t{%1, %0|%0, %1}"
14113 [(set_attr "prefix_0f" "1")])
14115 ;; Thread-local storage patterns for ELF.
14117 ;; Note that these code sequences must appear exactly as shown
14118 ;; in order to allow linker relaxation.
14120 (define_insn "*tls_global_dynamic_32_gnu"
14121 [(set (match_operand:SI 0 "register_operand" "=a")
14122 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14123 (match_operand:SI 2 "tls_symbolic_operand" "")
14124 (match_operand:SI 3 "call_insn_operand" "")]
14126 (clobber (match_scratch:SI 4 "=d"))
14127 (clobber (match_scratch:SI 5 "=c"))
14128 (clobber (reg:CC FLAGS_REG))]
14129 "!TARGET_64BIT && TARGET_GNU_TLS"
14130 "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3"
14131 [(set_attr "type" "multi")
14132 (set_attr "length" "12")])
14134 (define_insn "*tls_global_dynamic_32_sun"
14135 [(set (match_operand:SI 0 "register_operand" "=a")
14136 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14137 (match_operand:SI 2 "tls_symbolic_operand" "")
14138 (match_operand:SI 3 "call_insn_operand" "")]
14140 (clobber (match_scratch:SI 4 "=d"))
14141 (clobber (match_scratch:SI 5 "=c"))
14142 (clobber (reg:CC FLAGS_REG))]
14143 "!TARGET_64BIT && TARGET_SUN_TLS"
14144 "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]}
14145 push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop"
14146 [(set_attr "type" "multi")
14147 (set_attr "length" "14")])
14149 (define_expand "tls_global_dynamic_32"
14150 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14153 (match_operand:SI 1 "tls_symbolic_operand" "")
14156 (clobber (match_scratch:SI 4 ""))
14157 (clobber (match_scratch:SI 5 ""))
14158 (clobber (reg:CC FLAGS_REG))])]
14162 operands[2] = pic_offset_table_rtx;
14165 operands[2] = gen_reg_rtx (Pmode);
14166 emit_insn (gen_set_got (operands[2]));
14168 operands[3] = ix86_tls_get_addr ();
14171 (define_insn "*tls_global_dynamic_64"
14172 [(set (match_operand:DI 0 "register_operand" "=a")
14173 (call (mem:QI (match_operand:DI 2 "call_insn_operand" ""))
14174 (match_operand:DI 3 "" "")))
14175 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
14178 ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|%%rdi, %a1@TLSGD[%%rip]}\;.word\t0x6666\;rex64\;call\t%P2"
14179 [(set_attr "type" "multi")
14180 (set_attr "length" "16")])
14182 (define_expand "tls_global_dynamic_64"
14183 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14184 (call (mem:QI (match_dup 2)) (const_int 0)))
14185 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
14189 operands[2] = ix86_tls_get_addr ();
14192 (define_insn "*tls_local_dynamic_base_32_gnu"
14193 [(set (match_operand:SI 0 "register_operand" "=a")
14194 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14195 (match_operand:SI 2 "call_insn_operand" "")]
14196 UNSPEC_TLS_LD_BASE))
14197 (clobber (match_scratch:SI 3 "=d"))
14198 (clobber (match_scratch:SI 4 "=c"))
14199 (clobber (reg:CC FLAGS_REG))]
14200 "!TARGET_64BIT && TARGET_GNU_TLS"
14201 "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2"
14202 [(set_attr "type" "multi")
14203 (set_attr "length" "11")])
14205 (define_insn "*tls_local_dynamic_base_32_sun"
14206 [(set (match_operand:SI 0 "register_operand" "=a")
14207 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14208 (match_operand:SI 2 "call_insn_operand" "")]
14209 UNSPEC_TLS_LD_BASE))
14210 (clobber (match_scratch:SI 3 "=d"))
14211 (clobber (match_scratch:SI 4 "=c"))
14212 (clobber (reg:CC FLAGS_REG))]
14213 "!TARGET_64BIT && TARGET_SUN_TLS"
14214 "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]}
14215 push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3"
14216 [(set_attr "type" "multi")
14217 (set_attr "length" "13")])
14219 (define_expand "tls_local_dynamic_base_32"
14220 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14221 (unspec:SI [(match_dup 1) (match_dup 2)]
14222 UNSPEC_TLS_LD_BASE))
14223 (clobber (match_scratch:SI 3 ""))
14224 (clobber (match_scratch:SI 4 ""))
14225 (clobber (reg:CC FLAGS_REG))])]
14229 operands[1] = pic_offset_table_rtx;
14232 operands[1] = gen_reg_rtx (Pmode);
14233 emit_insn (gen_set_got (operands[1]));
14235 operands[2] = ix86_tls_get_addr ();
14238 (define_insn "*tls_local_dynamic_base_64"
14239 [(set (match_operand:DI 0 "register_operand" "=a")
14240 (call (mem:QI (match_operand:DI 1 "call_insn_operand" ""))
14241 (match_operand:DI 2 "" "")))
14242 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
14244 "lea{q}\t{%&@TLSLD(%%rip), %%rdi|%%rdi, %&@TLSLD[%%rip]}\;call\t%P1"
14245 [(set_attr "type" "multi")
14246 (set_attr "length" "12")])
14248 (define_expand "tls_local_dynamic_base_64"
14249 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14250 (call (mem:QI (match_dup 1)) (const_int 0)))
14251 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)])]
14254 operands[1] = ix86_tls_get_addr ();
14257 ;; Local dynamic of a single variable is a lose. Show combine how
14258 ;; to convert that back to global dynamic.
14260 (define_insn_and_split "*tls_local_dynamic_32_once"
14261 [(set (match_operand:SI 0 "register_operand" "=a")
14262 (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14263 (match_operand:SI 2 "call_insn_operand" "")]
14264 UNSPEC_TLS_LD_BASE)
14265 (const:SI (unspec:SI
14266 [(match_operand:SI 3 "tls_symbolic_operand" "")]
14268 (clobber (match_scratch:SI 4 "=d"))
14269 (clobber (match_scratch:SI 5 "=c"))
14270 (clobber (reg:CC FLAGS_REG))]
14274 [(parallel [(set (match_dup 0)
14275 (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)]
14277 (clobber (match_dup 4))
14278 (clobber (match_dup 5))
14279 (clobber (reg:CC FLAGS_REG))])]
14282 ;; Load and add the thread base pointer from %gs:0.
14284 (define_insn "*load_tp_si"
14285 [(set (match_operand:SI 0 "register_operand" "=r")
14286 (unspec:SI [(const_int 0)] UNSPEC_TP))]
14288 "mov{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
14289 [(set_attr "type" "imov")
14290 (set_attr "modrm" "0")
14291 (set_attr "length" "7")
14292 (set_attr "memory" "load")
14293 (set_attr "imm_disp" "false")])
14295 (define_insn "*add_tp_si"
14296 [(set (match_operand:SI 0 "register_operand" "=r")
14297 (plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP)
14298 (match_operand:SI 1 "register_operand" "0")))
14299 (clobber (reg:CC FLAGS_REG))]
14301 "add{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
14302 [(set_attr "type" "alu")
14303 (set_attr "modrm" "0")
14304 (set_attr "length" "7")
14305 (set_attr "memory" "load")
14306 (set_attr "imm_disp" "false")])
14308 (define_insn "*load_tp_di"
14309 [(set (match_operand:DI 0 "register_operand" "=r")
14310 (unspec:DI [(const_int 0)] UNSPEC_TP))]
14312 "mov{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
14313 [(set_attr "type" "imov")
14314 (set_attr "modrm" "0")
14315 (set_attr "length" "7")
14316 (set_attr "memory" "load")
14317 (set_attr "imm_disp" "false")])
14319 (define_insn "*add_tp_di"
14320 [(set (match_operand:DI 0 "register_operand" "=r")
14321 (plus:DI (unspec:DI [(const_int 0)] UNSPEC_TP)
14322 (match_operand:DI 1 "register_operand" "0")))
14323 (clobber (reg:CC FLAGS_REG))]
14325 "add{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
14326 [(set_attr "type" "alu")
14327 (set_attr "modrm" "0")
14328 (set_attr "length" "7")
14329 (set_attr "memory" "load")
14330 (set_attr "imm_disp" "false")])
14332 ;; These patterns match the binary 387 instructions for addM3, subM3,
14333 ;; mulM3 and divM3. There are three patterns for each of DFmode and
14334 ;; SFmode. The first is the normal insn, the second the same insn but
14335 ;; with one operand a conversion, and the third the same insn but with
14336 ;; the other operand a conversion. The conversion may be SFmode or
14337 ;; SImode if the target mode DFmode, but only SImode if the target mode
14340 ;; Gcc is slightly more smart about handling normal two address instructions
14341 ;; so use special patterns for add and mull.
14342 (define_insn "*fop_sf_comm_nosse"
14343 [(set (match_operand:SF 0 "register_operand" "=f")
14344 (match_operator:SF 3 "binary_fp_operator"
14345 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14346 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
14347 "TARGET_80387 && !TARGET_SSE_MATH
14348 && COMMUTATIVE_ARITH_P (operands[3])
14349 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14350 "* return output_387_binary_op (insn, operands);"
14351 [(set (attr "type")
14352 (if_then_else (match_operand:SF 3 "mult_operator" "")
14353 (const_string "fmul")
14354 (const_string "fop")))
14355 (set_attr "mode" "SF")])
14357 (define_insn "*fop_sf_comm"
14358 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14359 (match_operator:SF 3 "binary_fp_operator"
14360 [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
14361 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
14362 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14363 && COMMUTATIVE_ARITH_P (operands[3])
14364 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14365 "* return output_387_binary_op (insn, operands);"
14366 [(set (attr "type")
14367 (if_then_else (eq_attr "alternative" "1")
14368 (if_then_else (match_operand:SF 3 "mult_operator" "")
14369 (const_string "ssemul")
14370 (const_string "sseadd"))
14371 (if_then_else (match_operand:SF 3 "mult_operator" "")
14372 (const_string "fmul")
14373 (const_string "fop"))))
14374 (set_attr "mode" "SF")])
14376 (define_insn "*fop_sf_comm_sse"
14377 [(set (match_operand:SF 0 "register_operand" "=x")
14378 (match_operator:SF 3 "binary_fp_operator"
14379 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14380 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14381 "TARGET_SSE_MATH && COMMUTATIVE_ARITH_P (operands[3])
14382 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14383 "* return output_387_binary_op (insn, operands);"
14384 [(set (attr "type")
14385 (if_then_else (match_operand:SF 3 "mult_operator" "")
14386 (const_string "ssemul")
14387 (const_string "sseadd")))
14388 (set_attr "mode" "SF")])
14390 (define_insn "*fop_df_comm_nosse"
14391 [(set (match_operand:DF 0 "register_operand" "=f")
14392 (match_operator:DF 3 "binary_fp_operator"
14393 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14394 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
14395 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14396 && COMMUTATIVE_ARITH_P (operands[3])
14397 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14398 "* return output_387_binary_op (insn, operands);"
14399 [(set (attr "type")
14400 (if_then_else (match_operand:SF 3 "mult_operator" "")
14401 (const_string "fmul")
14402 (const_string "fop")))
14403 (set_attr "mode" "DF")])
14405 (define_insn "*fop_df_comm"
14406 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14407 (match_operator:DF 3 "binary_fp_operator"
14408 [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
14409 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
14410 "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
14411 && COMMUTATIVE_ARITH_P (operands[3])
14412 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14413 "* return output_387_binary_op (insn, operands);"
14414 [(set (attr "type")
14415 (if_then_else (eq_attr "alternative" "1")
14416 (if_then_else (match_operand:SF 3 "mult_operator" "")
14417 (const_string "ssemul")
14418 (const_string "sseadd"))
14419 (if_then_else (match_operand:SF 3 "mult_operator" "")
14420 (const_string "fmul")
14421 (const_string "fop"))))
14422 (set_attr "mode" "DF")])
14424 (define_insn "*fop_df_comm_sse"
14425 [(set (match_operand:DF 0 "register_operand" "=Y")
14426 (match_operator:DF 3 "binary_fp_operator"
14427 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14428 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14429 "TARGET_SSE2 && TARGET_SSE_MATH
14430 && COMMUTATIVE_ARITH_P (operands[3])
14431 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14432 "* return output_387_binary_op (insn, operands);"
14433 [(set (attr "type")
14434 (if_then_else (match_operand:SF 3 "mult_operator" "")
14435 (const_string "ssemul")
14436 (const_string "sseadd")))
14437 (set_attr "mode" "DF")])
14439 (define_insn "*fop_xf_comm"
14440 [(set (match_operand:XF 0 "register_operand" "=f")
14441 (match_operator:XF 3 "binary_fp_operator"
14442 [(match_operand:XF 1 "register_operand" "%0")
14443 (match_operand:XF 2 "register_operand" "f")]))]
14445 && COMMUTATIVE_ARITH_P (operands[3])"
14446 "* return output_387_binary_op (insn, operands);"
14447 [(set (attr "type")
14448 (if_then_else (match_operand:XF 3 "mult_operator" "")
14449 (const_string "fmul")
14450 (const_string "fop")))
14451 (set_attr "mode" "XF")])
14453 (define_insn "*fop_sf_1_nosse"
14454 [(set (match_operand:SF 0 "register_operand" "=f,f")
14455 (match_operator:SF 3 "binary_fp_operator"
14456 [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
14457 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
14458 "TARGET_80387 && !TARGET_SSE_MATH
14459 && !COMMUTATIVE_ARITH_P (operands[3])
14460 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14461 "* return output_387_binary_op (insn, operands);"
14462 [(set (attr "type")
14463 (cond [(match_operand:SF 3 "mult_operator" "")
14464 (const_string "fmul")
14465 (match_operand:SF 3 "div_operator" "")
14466 (const_string "fdiv")
14468 (const_string "fop")))
14469 (set_attr "mode" "SF")])
14471 (define_insn "*fop_sf_1"
14472 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
14473 (match_operator:SF 3 "binary_fp_operator"
14474 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
14475 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
14476 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14477 && !COMMUTATIVE_ARITH_P (operands[3])
14478 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14479 "* return output_387_binary_op (insn, operands);"
14480 [(set (attr "type")
14481 (cond [(and (eq_attr "alternative" "2")
14482 (match_operand:SF 3 "mult_operator" ""))
14483 (const_string "ssemul")
14484 (and (eq_attr "alternative" "2")
14485 (match_operand:SF 3 "div_operator" ""))
14486 (const_string "ssediv")
14487 (eq_attr "alternative" "2")
14488 (const_string "sseadd")
14489 (match_operand:SF 3 "mult_operator" "")
14490 (const_string "fmul")
14491 (match_operand:SF 3 "div_operator" "")
14492 (const_string "fdiv")
14494 (const_string "fop")))
14495 (set_attr "mode" "SF")])
14497 (define_insn "*fop_sf_1_sse"
14498 [(set (match_operand:SF 0 "register_operand" "=x")
14499 (match_operator:SF 3 "binary_fp_operator"
14500 [(match_operand:SF 1 "register_operand" "0")
14501 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14503 && !COMMUTATIVE_ARITH_P (operands[3])"
14504 "* return output_387_binary_op (insn, operands);"
14505 [(set (attr "type")
14506 (cond [(match_operand:SF 3 "mult_operator" "")
14507 (const_string "ssemul")
14508 (match_operand:SF 3 "div_operator" "")
14509 (const_string "ssediv")
14511 (const_string "sseadd")))
14512 (set_attr "mode" "SF")])
14514 ;; ??? Add SSE splitters for these!
14515 (define_insn "*fop_sf_2"
14516 [(set (match_operand:SF 0 "register_operand" "=f,f")
14517 (match_operator:SF 3 "binary_fp_operator"
14518 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14519 (match_operand:SF 2 "register_operand" "0,0")]))]
14520 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14521 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14522 [(set (attr "type")
14523 (cond [(match_operand:SF 3 "mult_operator" "")
14524 (const_string "fmul")
14525 (match_operand:SF 3 "div_operator" "")
14526 (const_string "fdiv")
14528 (const_string "fop")))
14529 (set_attr "fp_int_src" "true")
14530 (set_attr "mode" "SI")])
14532 (define_insn "*fop_sf_3"
14533 [(set (match_operand:SF 0 "register_operand" "=f,f")
14534 (match_operator:SF 3 "binary_fp_operator"
14535 [(match_operand:SF 1 "register_operand" "0,0")
14536 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14537 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14538 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14539 [(set (attr "type")
14540 (cond [(match_operand:SF 3 "mult_operator" "")
14541 (const_string "fmul")
14542 (match_operand:SF 3 "div_operator" "")
14543 (const_string "fdiv")
14545 (const_string "fop")))
14546 (set_attr "fp_int_src" "true")
14547 (set_attr "mode" "SI")])
14549 (define_insn "*fop_df_1_nosse"
14550 [(set (match_operand:DF 0 "register_operand" "=f,f")
14551 (match_operator:DF 3 "binary_fp_operator"
14552 [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
14553 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
14554 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14555 && !COMMUTATIVE_ARITH_P (operands[3])
14556 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14557 "* return output_387_binary_op (insn, operands);"
14558 [(set (attr "type")
14559 (cond [(match_operand:DF 3 "mult_operator" "")
14560 (const_string "fmul")
14561 (match_operand:DF 3 "div_operator" "")
14562 (const_string "fdiv")
14564 (const_string "fop")))
14565 (set_attr "mode" "DF")])
14568 (define_insn "*fop_df_1"
14569 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
14570 (match_operator:DF 3 "binary_fp_operator"
14571 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
14572 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
14573 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14574 && !COMMUTATIVE_ARITH_P (operands[3])
14575 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14576 "* return output_387_binary_op (insn, operands);"
14577 [(set (attr "type")
14578 (cond [(and (eq_attr "alternative" "2")
14579 (match_operand:SF 3 "mult_operator" ""))
14580 (const_string "ssemul")
14581 (and (eq_attr "alternative" "2")
14582 (match_operand:SF 3 "div_operator" ""))
14583 (const_string "ssediv")
14584 (eq_attr "alternative" "2")
14585 (const_string "sseadd")
14586 (match_operand:DF 3 "mult_operator" "")
14587 (const_string "fmul")
14588 (match_operand:DF 3 "div_operator" "")
14589 (const_string "fdiv")
14591 (const_string "fop")))
14592 (set_attr "mode" "DF")])
14594 (define_insn "*fop_df_1_sse"
14595 [(set (match_operand:DF 0 "register_operand" "=Y")
14596 (match_operator:DF 3 "binary_fp_operator"
14597 [(match_operand:DF 1 "register_operand" "0")
14598 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14599 "TARGET_SSE2 && TARGET_SSE_MATH
14600 && !COMMUTATIVE_ARITH_P (operands[3])"
14601 "* return output_387_binary_op (insn, operands);"
14602 [(set_attr "mode" "DF")
14604 (cond [(match_operand:SF 3 "mult_operator" "")
14605 (const_string "ssemul")
14606 (match_operand:SF 3 "div_operator" "")
14607 (const_string "ssediv")
14609 (const_string "sseadd")))])
14611 ;; ??? Add SSE splitters for these!
14612 (define_insn "*fop_df_2"
14613 [(set (match_operand:DF 0 "register_operand" "=f,f")
14614 (match_operator:DF 3 "binary_fp_operator"
14615 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14616 (match_operand:DF 2 "register_operand" "0,0")]))]
14617 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14618 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14619 [(set (attr "type")
14620 (cond [(match_operand:DF 3 "mult_operator" "")
14621 (const_string "fmul")
14622 (match_operand:DF 3 "div_operator" "")
14623 (const_string "fdiv")
14625 (const_string "fop")))
14626 (set_attr "fp_int_src" "true")
14627 (set_attr "mode" "SI")])
14629 (define_insn "*fop_df_3"
14630 [(set (match_operand:DF 0 "register_operand" "=f,f")
14631 (match_operator:DF 3 "binary_fp_operator"
14632 [(match_operand:DF 1 "register_operand" "0,0")
14633 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14634 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14635 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14636 [(set (attr "type")
14637 (cond [(match_operand:DF 3 "mult_operator" "")
14638 (const_string "fmul")
14639 (match_operand:DF 3 "div_operator" "")
14640 (const_string "fdiv")
14642 (const_string "fop")))
14643 (set_attr "fp_int_src" "true")
14644 (set_attr "mode" "SI")])
14646 (define_insn "*fop_df_4"
14647 [(set (match_operand:DF 0 "register_operand" "=f,f")
14648 (match_operator:DF 3 "binary_fp_operator"
14649 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14650 (match_operand:DF 2 "register_operand" "0,f")]))]
14651 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14652 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14653 "* return output_387_binary_op (insn, operands);"
14654 [(set (attr "type")
14655 (cond [(match_operand:DF 3 "mult_operator" "")
14656 (const_string "fmul")
14657 (match_operand:DF 3 "div_operator" "")
14658 (const_string "fdiv")
14660 (const_string "fop")))
14661 (set_attr "mode" "SF")])
14663 (define_insn "*fop_df_5"
14664 [(set (match_operand:DF 0 "register_operand" "=f,f")
14665 (match_operator:DF 3 "binary_fp_operator"
14666 [(match_operand:DF 1 "register_operand" "0,f")
14668 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14669 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14670 "* return output_387_binary_op (insn, operands);"
14671 [(set (attr "type")
14672 (cond [(match_operand:DF 3 "mult_operator" "")
14673 (const_string "fmul")
14674 (match_operand:DF 3 "div_operator" "")
14675 (const_string "fdiv")
14677 (const_string "fop")))
14678 (set_attr "mode" "SF")])
14680 (define_insn "*fop_df_6"
14681 [(set (match_operand:DF 0 "register_operand" "=f,f")
14682 (match_operator:DF 3 "binary_fp_operator"
14684 (match_operand:SF 1 "register_operand" "0,f"))
14686 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14687 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14688 "* return output_387_binary_op (insn, operands);"
14689 [(set (attr "type")
14690 (cond [(match_operand:DF 3 "mult_operator" "")
14691 (const_string "fmul")
14692 (match_operand:DF 3 "div_operator" "")
14693 (const_string "fdiv")
14695 (const_string "fop")))
14696 (set_attr "mode" "SF")])
14698 (define_insn "*fop_xf_1"
14699 [(set (match_operand:XF 0 "register_operand" "=f,f")
14700 (match_operator:XF 3 "binary_fp_operator"
14701 [(match_operand:XF 1 "register_operand" "0,f")
14702 (match_operand:XF 2 "register_operand" "f,0")]))]
14704 && !COMMUTATIVE_ARITH_P (operands[3])"
14705 "* return output_387_binary_op (insn, operands);"
14706 [(set (attr "type")
14707 (cond [(match_operand:XF 3 "mult_operator" "")
14708 (const_string "fmul")
14709 (match_operand:XF 3 "div_operator" "")
14710 (const_string "fdiv")
14712 (const_string "fop")))
14713 (set_attr "mode" "XF")])
14715 (define_insn "*fop_xf_2"
14716 [(set (match_operand:XF 0 "register_operand" "=f,f")
14717 (match_operator:XF 3 "binary_fp_operator"
14718 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14719 (match_operand:XF 2 "register_operand" "0,0")]))]
14720 "TARGET_80387 && TARGET_USE_FIOP"
14721 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14722 [(set (attr "type")
14723 (cond [(match_operand:XF 3 "mult_operator" "")
14724 (const_string "fmul")
14725 (match_operand:XF 3 "div_operator" "")
14726 (const_string "fdiv")
14728 (const_string "fop")))
14729 (set_attr "fp_int_src" "true")
14730 (set_attr "mode" "SI")])
14732 (define_insn "*fop_xf_3"
14733 [(set (match_operand:XF 0 "register_operand" "=f,f")
14734 (match_operator:XF 3 "binary_fp_operator"
14735 [(match_operand:XF 1 "register_operand" "0,0")
14736 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14737 "TARGET_80387 && TARGET_USE_FIOP"
14738 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14739 [(set (attr "type")
14740 (cond [(match_operand:XF 3 "mult_operator" "")
14741 (const_string "fmul")
14742 (match_operand:XF 3 "div_operator" "")
14743 (const_string "fdiv")
14745 (const_string "fop")))
14746 (set_attr "fp_int_src" "true")
14747 (set_attr "mode" "SI")])
14749 (define_insn "*fop_xf_4"
14750 [(set (match_operand:XF 0 "register_operand" "=f,f")
14751 (match_operator:XF 3 "binary_fp_operator"
14752 [(float_extend:XF (match_operand 1 "nonimmediate_operand" "fm,0"))
14753 (match_operand:XF 2 "register_operand" "0,f")]))]
14755 "* return output_387_binary_op (insn, operands);"
14756 [(set (attr "type")
14757 (cond [(match_operand:XF 3 "mult_operator" "")
14758 (const_string "fmul")
14759 (match_operand:XF 3 "div_operator" "")
14760 (const_string "fdiv")
14762 (const_string "fop")))
14763 (set_attr "mode" "SF")])
14765 (define_insn "*fop_xf_5"
14766 [(set (match_operand:XF 0 "register_operand" "=f,f")
14767 (match_operator:XF 3 "binary_fp_operator"
14768 [(match_operand:XF 1 "register_operand" "0,f")
14770 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
14772 "* return output_387_binary_op (insn, operands);"
14773 [(set (attr "type")
14774 (cond [(match_operand:XF 3 "mult_operator" "")
14775 (const_string "fmul")
14776 (match_operand:XF 3 "div_operator" "")
14777 (const_string "fdiv")
14779 (const_string "fop")))
14780 (set_attr "mode" "SF")])
14782 (define_insn "*fop_xf_6"
14783 [(set (match_operand:XF 0 "register_operand" "=f,f")
14784 (match_operator:XF 3 "binary_fp_operator"
14786 (match_operand 1 "register_operand" "0,f"))
14788 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
14790 "* return output_387_binary_op (insn, operands);"
14791 [(set (attr "type")
14792 (cond [(match_operand:XF 3 "mult_operator" "")
14793 (const_string "fmul")
14794 (match_operand:XF 3 "div_operator" "")
14795 (const_string "fdiv")
14797 (const_string "fop")))
14798 (set_attr "mode" "SF")])
14801 [(set (match_operand 0 "register_operand" "")
14802 (match_operator 3 "binary_fp_operator"
14803 [(float (match_operand:SI 1 "register_operand" ""))
14804 (match_operand 2 "register_operand" "")]))]
14805 "TARGET_80387 && reload_completed
14806 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14809 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
14810 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14811 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14812 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14813 GET_MODE (operands[3]),
14816 ix86_free_from_memory (GET_MODE (operands[1]));
14821 [(set (match_operand 0 "register_operand" "")
14822 (match_operator 3 "binary_fp_operator"
14823 [(match_operand 1 "register_operand" "")
14824 (float (match_operand:SI 2 "register_operand" ""))]))]
14825 "TARGET_80387 && reload_completed
14826 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14829 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
14830 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14831 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14832 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14833 GET_MODE (operands[3]),
14836 ix86_free_from_memory (GET_MODE (operands[2]));
14840 ;; FPU special functions.
14842 (define_expand "sqrtsf2"
14843 [(set (match_operand:SF 0 "register_operand" "")
14844 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
14845 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE_MATH"
14847 if (!TARGET_SSE_MATH)
14848 operands[1] = force_reg (SFmode, operands[1]);
14851 (define_insn "sqrtsf2_1"
14852 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14853 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
14854 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14855 && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
14858 sqrtss\t{%1, %0|%0, %1}"
14859 [(set_attr "type" "fpspc,sse")
14860 (set_attr "mode" "SF,SF")
14861 (set_attr "athlon_decode" "direct,*")])
14863 (define_insn "sqrtsf2_1_sse_only"
14864 [(set (match_operand:SF 0 "register_operand" "=x")
14865 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
14866 "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14867 "sqrtss\t{%1, %0|%0, %1}"
14868 [(set_attr "type" "sse")
14869 (set_attr "mode" "SF")
14870 (set_attr "athlon_decode" "*")])
14872 (define_insn "sqrtsf2_i387"
14873 [(set (match_operand:SF 0 "register_operand" "=f")
14874 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
14875 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14876 && !TARGET_SSE_MATH"
14878 [(set_attr "type" "fpspc")
14879 (set_attr "mode" "SF")
14880 (set_attr "athlon_decode" "direct")])
14882 (define_expand "sqrtdf2"
14883 [(set (match_operand:DF 0 "register_operand" "")
14884 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
14885 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387)
14886 || (TARGET_SSE2 && TARGET_SSE_MATH)"
14888 if (!TARGET_SSE2 || !TARGET_SSE_MATH)
14889 operands[1] = force_reg (DFmode, operands[1]);
14892 (define_insn "sqrtdf2_1"
14893 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14894 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
14895 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14896 && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
14899 sqrtsd\t{%1, %0|%0, %1}"
14900 [(set_attr "type" "fpspc,sse")
14901 (set_attr "mode" "DF,DF")
14902 (set_attr "athlon_decode" "direct,*")])
14904 (define_insn "sqrtdf2_1_sse_only"
14905 [(set (match_operand:DF 0 "register_operand" "=Y")
14906 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
14907 "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14908 "sqrtsd\t{%1, %0|%0, %1}"
14909 [(set_attr "type" "sse")
14910 (set_attr "mode" "DF")
14911 (set_attr "athlon_decode" "*")])
14913 (define_insn "sqrtdf2_i387"
14914 [(set (match_operand:DF 0 "register_operand" "=f")
14915 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
14916 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14917 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
14919 [(set_attr "type" "fpspc")
14920 (set_attr "mode" "DF")
14921 (set_attr "athlon_decode" "direct")])
14923 (define_insn "*sqrtextendsfdf2"
14924 [(set (match_operand:DF 0 "register_operand" "=f")
14925 (sqrt:DF (float_extend:DF
14926 (match_operand:SF 1 "register_operand" "0"))))]
14927 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14928 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14930 [(set_attr "type" "fpspc")
14931 (set_attr "mode" "DF")
14932 (set_attr "athlon_decode" "direct")])
14934 (define_insn "sqrtxf2"
14935 [(set (match_operand:XF 0 "register_operand" "=f")
14936 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
14937 "TARGET_80387 && !TARGET_NO_FANCY_MATH_387
14938 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14940 [(set_attr "type" "fpspc")
14941 (set_attr "mode" "XF")
14942 (set_attr "athlon_decode" "direct")])
14944 (define_insn "*sqrtextenddfxf2"
14945 [(set (match_operand:XF 0 "register_operand" "=f")
14946 (sqrt:XF (float_extend:XF
14947 (match_operand:DF 1 "register_operand" "0"))))]
14948 "TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
14950 [(set_attr "type" "fpspc")
14951 (set_attr "mode" "XF")
14952 (set_attr "athlon_decode" "direct")])
14954 (define_insn "*sqrtextendsfxf2"
14955 [(set (match_operand:XF 0 "register_operand" "=f")
14956 (sqrt:XF (float_extend:XF
14957 (match_operand:SF 1 "register_operand" "0"))))]
14958 "TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
14960 [(set_attr "type" "fpspc")
14961 (set_attr "mode" "XF")
14962 (set_attr "athlon_decode" "direct")])
14964 (define_insn "fpremxf4"
14965 [(set (match_operand:XF 0 "register_operand" "=f")
14966 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
14967 (match_operand:XF 3 "register_operand" "1")]
14969 (set (match_operand:XF 1 "register_operand" "=u")
14970 (unspec:XF [(match_dup 2) (match_dup 3)]
14972 (set (reg:CCFP FPSR_REG)
14973 (unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
14974 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14975 && flag_unsafe_math_optimizations"
14977 [(set_attr "type" "fpspc")
14978 (set_attr "mode" "XF")])
14980 (define_expand "fmodsf3"
14981 [(use (match_operand:SF 0 "register_operand" ""))
14982 (use (match_operand:SF 1 "register_operand" ""))
14983 (use (match_operand:SF 2 "register_operand" ""))]
14984 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14985 && flag_unsafe_math_optimizations"
14987 rtx label = gen_label_rtx ();
14989 rtx op1 = gen_reg_rtx (XFmode);
14990 rtx op2 = gen_reg_rtx (XFmode);
14992 emit_insn(gen_extendsfxf2 (op1, operands[1]));
14993 emit_insn(gen_extendsfxf2 (op2, operands[2]));
14995 emit_label (label);
14997 emit_insn (gen_fpremxf4 (op1, op2, op1, op2));
14998 ix86_emit_fp_unordered_jump (label);
15000 emit_insn (gen_truncxfsf2_noop (operands[0], op1));
15004 (define_expand "fmoddf3"
15005 [(use (match_operand:DF 0 "register_operand" ""))
15006 (use (match_operand:DF 1 "register_operand" ""))
15007 (use (match_operand:DF 2 "register_operand" ""))]
15008 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15009 && flag_unsafe_math_optimizations"
15011 rtx label = gen_label_rtx ();
15013 rtx op1 = gen_reg_rtx (XFmode);
15014 rtx op2 = gen_reg_rtx (XFmode);
15016 emit_insn (gen_extenddfxf2 (op1, operands[1]));
15017 emit_insn (gen_extenddfxf2 (op2, operands[2]));
15019 emit_label (label);
15021 emit_insn (gen_fpremxf4 (op1, op2, op1, op2));
15022 ix86_emit_fp_unordered_jump (label);
15024 emit_insn (gen_truncxfdf2_noop (operands[0], op1));
15028 (define_expand "fmodxf3"
15029 [(use (match_operand:XF 0 "register_operand" ""))
15030 (use (match_operand:XF 1 "register_operand" ""))
15031 (use (match_operand:XF 2 "register_operand" ""))]
15032 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15033 && flag_unsafe_math_optimizations"
15035 rtx label = gen_label_rtx ();
15037 emit_label (label);
15039 emit_insn (gen_fpremxf4 (operands[1], operands[2],
15040 operands[1], operands[2]));
15041 ix86_emit_fp_unordered_jump (label);
15043 emit_move_insn (operands[0], operands[1]);
15047 (define_insn "fprem1xf4"
15048 [(set (match_operand:XF 0 "register_operand" "=f")
15049 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15050 (match_operand:XF 3 "register_operand" "1")]
15052 (set (match_operand:XF 1 "register_operand" "=u")
15053 (unspec:XF [(match_dup 2) (match_dup 3)]
15055 (set (reg:CCFP FPSR_REG)
15056 (unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
15057 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15058 && flag_unsafe_math_optimizations"
15060 [(set_attr "type" "fpspc")
15061 (set_attr "mode" "XF")])
15063 (define_expand "dremsf3"
15064 [(use (match_operand:SF 0 "register_operand" ""))
15065 (use (match_operand:SF 1 "register_operand" ""))
15066 (use (match_operand:SF 2 "register_operand" ""))]
15067 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15068 && flag_unsafe_math_optimizations"
15070 rtx label = gen_label_rtx ();
15072 rtx op1 = gen_reg_rtx (XFmode);
15073 rtx op2 = gen_reg_rtx (XFmode);
15075 emit_insn(gen_extendsfxf2 (op1, operands[1]));
15076 emit_insn(gen_extendsfxf2 (op2, operands[2]));
15078 emit_label (label);
15080 emit_insn (gen_fprem1xf4 (op1, op2, op1, op2));
15081 ix86_emit_fp_unordered_jump (label);
15083 emit_insn (gen_truncxfsf2_noop (operands[0], op1));
15087 (define_expand "dremdf3"
15088 [(use (match_operand:DF 0 "register_operand" ""))
15089 (use (match_operand:DF 1 "register_operand" ""))
15090 (use (match_operand:DF 2 "register_operand" ""))]
15091 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15092 && flag_unsafe_math_optimizations"
15094 rtx label = gen_label_rtx ();
15096 rtx op1 = gen_reg_rtx (XFmode);
15097 rtx op2 = gen_reg_rtx (XFmode);
15099 emit_insn (gen_extenddfxf2 (op1, operands[1]));
15100 emit_insn (gen_extenddfxf2 (op2, operands[2]));
15102 emit_label (label);
15104 emit_insn (gen_fprem1xf4 (op1, op2, op1, op2));
15105 ix86_emit_fp_unordered_jump (label);
15107 emit_insn (gen_truncxfdf2_noop (operands[0], op1));
15111 (define_expand "dremxf3"
15112 [(use (match_operand:XF 0 "register_operand" ""))
15113 (use (match_operand:XF 1 "register_operand" ""))
15114 (use (match_operand:XF 2 "register_operand" ""))]
15115 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15116 && flag_unsafe_math_optimizations"
15118 rtx label = gen_label_rtx ();
15120 emit_label (label);
15122 emit_insn (gen_fprem1xf4 (operands[1], operands[2],
15123 operands[1], operands[2]));
15124 ix86_emit_fp_unordered_jump (label);
15126 emit_move_insn (operands[0], operands[1]);
15130 (define_insn "*sindf2"
15131 [(set (match_operand:DF 0 "register_operand" "=f")
15132 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
15133 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15134 && flag_unsafe_math_optimizations"
15136 [(set_attr "type" "fpspc")
15137 (set_attr "mode" "DF")])
15139 (define_insn "*sinsf2"
15140 [(set (match_operand:SF 0 "register_operand" "=f")
15141 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
15142 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15143 && flag_unsafe_math_optimizations"
15145 [(set_attr "type" "fpspc")
15146 (set_attr "mode" "SF")])
15148 (define_insn "*sinextendsfdf2"
15149 [(set (match_operand:DF 0 "register_operand" "=f")
15150 (unspec:DF [(float_extend:DF
15151 (match_operand:SF 1 "register_operand" "0"))]
15153 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15154 && flag_unsafe_math_optimizations"
15156 [(set_attr "type" "fpspc")
15157 (set_attr "mode" "DF")])
15159 (define_insn "*sinxf2"
15160 [(set (match_operand:XF 0 "register_operand" "=f")
15161 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
15162 "TARGET_80387 && !TARGET_NO_FANCY_MATH_387
15163 && flag_unsafe_math_optimizations"
15165 [(set_attr "type" "fpspc")
15166 (set_attr "mode" "XF")])
15168 (define_insn "*cosdf2"
15169 [(set (match_operand:DF 0 "register_operand" "=f")
15170 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
15171 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15172 && flag_unsafe_math_optimizations"
15174 [(set_attr "type" "fpspc")
15175 (set_attr "mode" "DF")])
15177 (define_insn "*cossf2"
15178 [(set (match_operand:SF 0 "register_operand" "=f")
15179 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
15180 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15181 && flag_unsafe_math_optimizations"
15183 [(set_attr "type" "fpspc")
15184 (set_attr "mode" "SF")])
15186 (define_insn "*cosextendsfdf2"
15187 [(set (match_operand:DF 0 "register_operand" "=f")
15188 (unspec:DF [(float_extend:DF
15189 (match_operand:SF 1 "register_operand" "0"))]
15191 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15192 && flag_unsafe_math_optimizations"
15194 [(set_attr "type" "fpspc")
15195 (set_attr "mode" "DF")])
15197 (define_insn "*cosxf2"
15198 [(set (match_operand:XF 0 "register_operand" "=f")
15199 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
15200 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15201 && flag_unsafe_math_optimizations"
15203 [(set_attr "type" "fpspc")
15204 (set_attr "mode" "XF")])
15206 ;; With sincos pattern defined, sin and cos builtin function will be
15207 ;; expanded to sincos pattern with one of its outputs left unused.
15208 ;; Cse pass will detected, if two sincos patterns can be combined,
15209 ;; otherwise sincos pattern will be split back to sin or cos pattern,
15210 ;; depending on the unused output.
15212 (define_insn "sincosdf3"
15213 [(set (match_operand:DF 0 "register_operand" "=f")
15214 (unspec:DF [(match_operand:DF 2 "register_operand" "0")]
15215 UNSPEC_SINCOS_COS))
15216 (set (match_operand:DF 1 "register_operand" "=u")
15217 (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15218 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15219 && flag_unsafe_math_optimizations"
15221 [(set_attr "type" "fpspc")
15222 (set_attr "mode" "DF")])
15225 [(set (match_operand:DF 0 "register_operand" "")
15226 (unspec:DF [(match_operand:DF 2 "register_operand" "")]
15227 UNSPEC_SINCOS_COS))
15228 (set (match_operand:DF 1 "register_operand" "")
15229 (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15230 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15231 && !reload_completed && !reload_in_progress"
15232 [(set (match_dup 1) (unspec:DF [(match_dup 2)] UNSPEC_SIN))]
15236 [(set (match_operand:DF 0 "register_operand" "")
15237 (unspec:DF [(match_operand:DF 2 "register_operand" "")]
15238 UNSPEC_SINCOS_COS))
15239 (set (match_operand:DF 1 "register_operand" "")
15240 (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15241 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15242 && !reload_completed && !reload_in_progress"
15243 [(set (match_dup 0) (unspec:DF [(match_dup 2)] UNSPEC_COS))]
15246 (define_insn "sincossf3"
15247 [(set (match_operand:SF 0 "register_operand" "=f")
15248 (unspec:SF [(match_operand:SF 2 "register_operand" "0")]
15249 UNSPEC_SINCOS_COS))
15250 (set (match_operand:SF 1 "register_operand" "=u")
15251 (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15252 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15253 && flag_unsafe_math_optimizations"
15255 [(set_attr "type" "fpspc")
15256 (set_attr "mode" "SF")])
15259 [(set (match_operand:SF 0 "register_operand" "")
15260 (unspec:SF [(match_operand:SF 2 "register_operand" "")]
15261 UNSPEC_SINCOS_COS))
15262 (set (match_operand:SF 1 "register_operand" "")
15263 (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15264 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15265 && !reload_completed && !reload_in_progress"
15266 [(set (match_dup 1) (unspec:SF [(match_dup 2)] UNSPEC_SIN))]
15270 [(set (match_operand:SF 0 "register_operand" "")
15271 (unspec:SF [(match_operand:SF 2 "register_operand" "")]
15272 UNSPEC_SINCOS_COS))
15273 (set (match_operand:SF 1 "register_operand" "")
15274 (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15275 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15276 && !reload_completed && !reload_in_progress"
15277 [(set (match_dup 0) (unspec:SF [(match_dup 2)] UNSPEC_COS))]
15280 (define_insn "*sincosextendsfdf3"
15281 [(set (match_operand:DF 0 "register_operand" "=f")
15282 (unspec:DF [(float_extend:DF
15283 (match_operand:SF 2 "register_operand" "0"))]
15284 UNSPEC_SINCOS_COS))
15285 (set (match_operand:DF 1 "register_operand" "=u")
15286 (unspec:DF [(float_extend:DF
15287 (match_dup 2))] UNSPEC_SINCOS_SIN))]
15288 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15289 && flag_unsafe_math_optimizations"
15291 [(set_attr "type" "fpspc")
15292 (set_attr "mode" "DF")])
15295 [(set (match_operand:DF 0 "register_operand" "")
15296 (unspec:DF [(float_extend:DF
15297 (match_operand:SF 2 "register_operand" ""))]
15298 UNSPEC_SINCOS_COS))
15299 (set (match_operand:DF 1 "register_operand" "")
15300 (unspec:DF [(float_extend:DF
15301 (match_dup 2))] UNSPEC_SINCOS_SIN))]
15302 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15303 && !reload_completed && !reload_in_progress"
15304 [(set (match_dup 1) (unspec:DF [(float_extend:DF
15305 (match_dup 2))] UNSPEC_SIN))]
15309 [(set (match_operand:DF 0 "register_operand" "")
15310 (unspec:DF [(float_extend:DF
15311 (match_operand:SF 2 "register_operand" ""))]
15312 UNSPEC_SINCOS_COS))
15313 (set (match_operand:DF 1 "register_operand" "")
15314 (unspec:DF [(float_extend:DF
15315 (match_dup 2))] UNSPEC_SINCOS_SIN))]
15316 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15317 && !reload_completed && !reload_in_progress"
15318 [(set (match_dup 0) (unspec:DF [(float_extend:DF
15319 (match_dup 2))] UNSPEC_COS))]
15322 (define_insn "sincosxf3"
15323 [(set (match_operand:XF 0 "register_operand" "=f")
15324 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15325 UNSPEC_SINCOS_COS))
15326 (set (match_operand:XF 1 "register_operand" "=u")
15327 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15328 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15329 && flag_unsafe_math_optimizations"
15331 [(set_attr "type" "fpspc")
15332 (set_attr "mode" "XF")])
15335 [(set (match_operand:XF 0 "register_operand" "")
15336 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
15337 UNSPEC_SINCOS_COS))
15338 (set (match_operand:XF 1 "register_operand" "")
15339 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15340 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15341 && !reload_completed && !reload_in_progress"
15342 [(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))]
15346 [(set (match_operand:XF 0 "register_operand" "")
15347 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
15348 UNSPEC_SINCOS_COS))
15349 (set (match_operand:XF 1 "register_operand" "")
15350 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15351 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15352 && !reload_completed && !reload_in_progress"
15353 [(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_COS))]
15356 (define_insn "*tandf3_1"
15357 [(set (match_operand:DF 0 "register_operand" "=f")
15358 (unspec:DF [(match_operand:DF 2 "register_operand" "0")]
15360 (set (match_operand:DF 1 "register_operand" "=u")
15361 (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))]
15362 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15363 && flag_unsafe_math_optimizations"
15365 [(set_attr "type" "fpspc")
15366 (set_attr "mode" "DF")])
15368 ;; optimize sequence: fptan
15371 ;; into fptan insn.
15374 [(parallel[(set (match_operand:DF 0 "register_operand" "")
15375 (unspec:DF [(match_operand:DF 2 "register_operand" "")]
15377 (set (match_operand:DF 1 "register_operand" "")
15378 (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))])
15380 (match_operand:DF 3 "immediate_operand" ""))]
15381 "standard_80387_constant_p (operands[3]) == 2"
15382 [(parallel[(set (match_dup 0) (unspec:DF [(match_dup 2)] UNSPEC_TAN_ONE))
15383 (set (match_dup 1) (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))])]
15386 (define_expand "tandf2"
15387 [(parallel [(set (match_dup 2)
15388 (unspec:DF [(match_operand:DF 1 "register_operand" "")]
15390 (set (match_operand:DF 0 "register_operand" "")
15391 (unspec:DF [(match_dup 1)] UNSPEC_TAN_TAN))])]
15392 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15393 && flag_unsafe_math_optimizations"
15395 operands[2] = gen_reg_rtx (DFmode);
15398 (define_insn "*tansf3_1"
15399 [(set (match_operand:SF 0 "register_operand" "=f")
15400 (unspec:SF [(match_operand:SF 2 "register_operand" "0")]
15402 (set (match_operand:SF 1 "register_operand" "=u")
15403 (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))]
15404 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15405 && flag_unsafe_math_optimizations"
15407 [(set_attr "type" "fpspc")
15408 (set_attr "mode" "SF")])
15410 ;; optimize sequence: fptan
15413 ;; into fptan insn.
15416 [(parallel[(set (match_operand:SF 0 "register_operand" "")
15417 (unspec:SF [(match_operand:SF 2 "register_operand" "")]
15419 (set (match_operand:SF 1 "register_operand" "")
15420 (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))])
15422 (match_operand:SF 3 "immediate_operand" ""))]
15423 "standard_80387_constant_p (operands[3]) == 2"
15424 [(parallel[(set (match_dup 0) (unspec:SF [(match_dup 2)] UNSPEC_TAN_ONE))
15425 (set (match_dup 1) (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))])]
15428 (define_expand "tansf2"
15429 [(parallel [(set (match_dup 2)
15430 (unspec:SF [(match_operand:SF 1 "register_operand" "")]
15432 (set (match_operand:SF 0 "register_operand" "")
15433 (unspec:SF [(match_dup 1)] UNSPEC_TAN_TAN))])]
15434 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15435 && flag_unsafe_math_optimizations"
15437 operands[2] = gen_reg_rtx (SFmode);
15440 (define_insn "*tanxf3_1"
15441 [(set (match_operand:XF 0 "register_operand" "=f")
15442 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15444 (set (match_operand:XF 1 "register_operand" "=u")
15445 (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))]
15446 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15447 && flag_unsafe_math_optimizations"
15449 [(set_attr "type" "fpspc")
15450 (set_attr "mode" "XF")])
15452 ;; optimize sequence: fptan
15455 ;; into fptan insn.
15458 [(parallel[(set (match_operand:XF 0 "register_operand" "")
15459 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
15461 (set (match_operand:XF 1 "register_operand" "")
15462 (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))])
15464 (match_operand:XF 3 "immediate_operand" ""))]
15465 "standard_80387_constant_p (operands[3]) == 2"
15466 [(parallel[(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_TAN_ONE))
15467 (set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))])]
15470 (define_expand "tanxf2"
15471 [(parallel [(set (match_dup 2)
15472 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
15474 (set (match_operand:XF 0 "register_operand" "")
15475 (unspec:XF [(match_dup 1)] UNSPEC_TAN_TAN))])]
15476 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15477 && flag_unsafe_math_optimizations"
15479 operands[2] = gen_reg_rtx (XFmode);
15482 (define_insn "atan2df3_1"
15483 [(set (match_operand:DF 0 "register_operand" "=f")
15484 (unspec:DF [(match_operand:DF 2 "register_operand" "0")
15485 (match_operand:DF 1 "register_operand" "u")]
15487 (clobber (match_scratch:DF 3 "=1"))]
15488 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15489 && flag_unsafe_math_optimizations"
15491 [(set_attr "type" "fpspc")
15492 (set_attr "mode" "DF")])
15494 (define_expand "atan2df3"
15495 [(use (match_operand:DF 0 "register_operand" "=f"))
15496 (use (match_operand:DF 2 "register_operand" "0"))
15497 (use (match_operand:DF 1 "register_operand" "u"))]
15498 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15499 && flag_unsafe_math_optimizations"
15501 rtx copy = gen_reg_rtx (DFmode);
15502 emit_move_insn (copy, operands[1]);
15503 emit_insn (gen_atan2df3_1 (operands[0], copy, operands[2]));
15507 (define_expand "atandf2"
15508 [(parallel [(set (match_operand:DF 0 "register_operand" "")
15509 (unspec:DF [(match_dup 2)
15510 (match_operand:DF 1 "register_operand" "")]
15512 (clobber (match_scratch:DF 3 ""))])]
15513 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15514 && flag_unsafe_math_optimizations"
15516 operands[2] = gen_reg_rtx (DFmode);
15517 emit_move_insn (operands[2], CONST1_RTX (DFmode)); /* fld1 */
15520 (define_insn "atan2sf3_1"
15521 [(set (match_operand:SF 0 "register_operand" "=f")
15522 (unspec:SF [(match_operand:SF 2 "register_operand" "0")
15523 (match_operand:SF 1 "register_operand" "u")]
15525 (clobber (match_scratch:SF 3 "=1"))]
15526 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15527 && flag_unsafe_math_optimizations"
15529 [(set_attr "type" "fpspc")
15530 (set_attr "mode" "SF")])
15532 (define_expand "atan2sf3"
15533 [(use (match_operand:SF 0 "register_operand" "=f"))
15534 (use (match_operand:SF 2 "register_operand" "0"))
15535 (use (match_operand:SF 1 "register_operand" "u"))]
15536 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15537 && flag_unsafe_math_optimizations"
15539 rtx copy = gen_reg_rtx (SFmode);
15540 emit_move_insn (copy, operands[1]);
15541 emit_insn (gen_atan2sf3_1 (operands[0], copy, operands[2]));
15545 (define_expand "atansf2"
15546 [(parallel [(set (match_operand:SF 0 "register_operand" "")
15547 (unspec:SF [(match_dup 2)
15548 (match_operand:SF 1 "register_operand" "")]
15550 (clobber (match_scratch:SF 3 ""))])]
15551 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15552 && flag_unsafe_math_optimizations"
15554 operands[2] = gen_reg_rtx (SFmode);
15555 emit_move_insn (operands[2], CONST1_RTX (SFmode)); /* fld1 */
15558 (define_insn "atan2xf3_1"
15559 [(set (match_operand:XF 0 "register_operand" "=f")
15560 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15561 (match_operand:XF 1 "register_operand" "u")]
15563 (clobber (match_scratch:XF 3 "=1"))]
15564 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15565 && flag_unsafe_math_optimizations"
15567 [(set_attr "type" "fpspc")
15568 (set_attr "mode" "XF")])
15570 (define_expand "atan2xf3"
15571 [(use (match_operand:XF 0 "register_operand" "=f"))
15572 (use (match_operand:XF 2 "register_operand" "0"))
15573 (use (match_operand:XF 1 "register_operand" "u"))]
15574 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15575 && flag_unsafe_math_optimizations"
15577 rtx copy = gen_reg_rtx (XFmode);
15578 emit_move_insn (copy, operands[1]);
15579 emit_insn (gen_atan2xf3_1 (operands[0], copy, operands[2]));
15583 (define_expand "atanxf2"
15584 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15585 (unspec:XF [(match_dup 2)
15586 (match_operand:XF 1 "register_operand" "")]
15588 (clobber (match_scratch:XF 3 ""))])]
15589 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15590 && flag_unsafe_math_optimizations"
15592 operands[2] = gen_reg_rtx (XFmode);
15593 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
15596 (define_expand "asindf2"
15597 [(set (match_dup 2)
15598 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15599 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15600 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15601 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15602 (parallel [(set (match_dup 7)
15603 (unspec:XF [(match_dup 6) (match_dup 2)]
15605 (clobber (match_scratch:XF 8 ""))])
15606 (set (match_operand:DF 0 "register_operand" "")
15607 (float_truncate:DF (match_dup 7)))]
15608 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15609 && flag_unsafe_math_optimizations"
15613 for (i=2; i<8; i++)
15614 operands[i] = gen_reg_rtx (XFmode);
15616 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15619 (define_expand "asinsf2"
15620 [(set (match_dup 2)
15621 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15622 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15623 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15624 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15625 (parallel [(set (match_dup 7)
15626 (unspec:XF [(match_dup 6) (match_dup 2)]
15628 (clobber (match_scratch:XF 8 ""))])
15629 (set (match_operand:SF 0 "register_operand" "")
15630 (float_truncate:SF (match_dup 7)))]
15631 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15632 && flag_unsafe_math_optimizations"
15636 for (i=2; i<8; i++)
15637 operands[i] = gen_reg_rtx (XFmode);
15639 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15642 (define_expand "asinxf2"
15643 [(set (match_dup 2)
15644 (mult:XF (match_operand:XF 1 "register_operand" "")
15646 (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
15647 (set (match_dup 5) (sqrt:XF (match_dup 4)))
15648 (parallel [(set (match_operand:XF 0 "register_operand" "")
15649 (unspec:XF [(match_dup 5) (match_dup 1)]
15651 (clobber (match_scratch:XF 6 ""))])]
15652 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15653 && flag_unsafe_math_optimizations"
15657 for (i=2; i<6; i++)
15658 operands[i] = gen_reg_rtx (XFmode);
15660 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15663 (define_expand "acosdf2"
15664 [(set (match_dup 2)
15665 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15666 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15667 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15668 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15669 (parallel [(set (match_dup 7)
15670 (unspec:XF [(match_dup 2) (match_dup 6)]
15672 (clobber (match_scratch:XF 8 ""))])
15673 (set (match_operand:DF 0 "register_operand" "")
15674 (float_truncate:DF (match_dup 7)))]
15675 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15676 && flag_unsafe_math_optimizations"
15680 for (i=2; i<8; i++)
15681 operands[i] = gen_reg_rtx (XFmode);
15683 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15686 (define_expand "acossf2"
15687 [(set (match_dup 2)
15688 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15689 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15690 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15691 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15692 (parallel [(set (match_dup 7)
15693 (unspec:XF [(match_dup 2) (match_dup 6)]
15695 (clobber (match_scratch:XF 8 ""))])
15696 (set (match_operand:SF 0 "register_operand" "")
15697 (float_truncate:SF (match_dup 7)))]
15698 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15699 && flag_unsafe_math_optimizations"
15703 for (i=2; i<8; i++)
15704 operands[i] = gen_reg_rtx (XFmode);
15706 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15709 (define_expand "acosxf2"
15710 [(set (match_dup 2)
15711 (mult:XF (match_operand:XF 1 "register_operand" "")
15713 (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
15714 (set (match_dup 5) (sqrt:XF (match_dup 4)))
15715 (parallel [(set (match_operand:XF 0 "register_operand" "")
15716 (unspec:XF [(match_dup 1) (match_dup 5)]
15718 (clobber (match_scratch:XF 6 ""))])]
15719 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15720 && flag_unsafe_math_optimizations"
15724 for (i=2; i<6; i++)
15725 operands[i] = gen_reg_rtx (XFmode);
15727 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15730 (define_insn "fyl2x_xf3"
15731 [(set (match_operand:XF 0 "register_operand" "=f")
15732 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15733 (match_operand:XF 1 "register_operand" "u")]
15735 (clobber (match_scratch:XF 3 "=1"))]
15736 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15737 && flag_unsafe_math_optimizations"
15739 [(set_attr "type" "fpspc")
15740 (set_attr "mode" "XF")])
15742 (define_expand "logsf2"
15743 [(set (match_dup 2)
15744 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15745 (parallel [(set (match_dup 4)
15746 (unspec:XF [(match_dup 2)
15747 (match_dup 3)] UNSPEC_FYL2X))
15748 (clobber (match_scratch:XF 5 ""))])
15749 (set (match_operand:SF 0 "register_operand" "")
15750 (float_truncate:SF (match_dup 4)))]
15751 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15752 && flag_unsafe_math_optimizations"
15756 operands[2] = gen_reg_rtx (XFmode);
15757 operands[3] = gen_reg_rtx (XFmode);
15758 operands[4] = gen_reg_rtx (XFmode);
15760 temp = standard_80387_constant_rtx (4); /* fldln2 */
15761 emit_move_insn (operands[3], temp);
15764 (define_expand "logdf2"
15765 [(set (match_dup 2)
15766 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15767 (parallel [(set (match_dup 4)
15768 (unspec:XF [(match_dup 2)
15769 (match_dup 3)] UNSPEC_FYL2X))
15770 (clobber (match_scratch:XF 5 ""))])
15771 (set (match_operand:DF 0 "register_operand" "")
15772 (float_truncate:DF (match_dup 4)))]
15773 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15774 && flag_unsafe_math_optimizations"
15778 operands[2] = gen_reg_rtx (XFmode);
15779 operands[3] = gen_reg_rtx (XFmode);
15780 operands[4] = gen_reg_rtx (XFmode);
15782 temp = standard_80387_constant_rtx (4); /* fldln2 */
15783 emit_move_insn (operands[3], temp);
15786 (define_expand "logxf2"
15787 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15788 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15789 (match_dup 2)] UNSPEC_FYL2X))
15790 (clobber (match_scratch:XF 3 ""))])]
15791 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15792 && flag_unsafe_math_optimizations"
15796 operands[2] = gen_reg_rtx (XFmode);
15797 temp = standard_80387_constant_rtx (4); /* fldln2 */
15798 emit_move_insn (operands[2], temp);
15801 (define_expand "log10sf2"
15802 [(set (match_dup 2)
15803 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15804 (parallel [(set (match_dup 4)
15805 (unspec:XF [(match_dup 2)
15806 (match_dup 3)] UNSPEC_FYL2X))
15807 (clobber (match_scratch:XF 5 ""))])
15808 (set (match_operand:SF 0 "register_operand" "")
15809 (float_truncate:SF (match_dup 4)))]
15810 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15811 && flag_unsafe_math_optimizations"
15815 operands[2] = gen_reg_rtx (XFmode);
15816 operands[3] = gen_reg_rtx (XFmode);
15817 operands[4] = gen_reg_rtx (XFmode);
15819 temp = standard_80387_constant_rtx (3); /* fldlg2 */
15820 emit_move_insn (operands[3], temp);
15823 (define_expand "log10df2"
15824 [(set (match_dup 2)
15825 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15826 (parallel [(set (match_dup 4)
15827 (unspec:XF [(match_dup 2)
15828 (match_dup 3)] UNSPEC_FYL2X))
15829 (clobber (match_scratch:XF 5 ""))])
15830 (set (match_operand:DF 0 "register_operand" "")
15831 (float_truncate:DF (match_dup 4)))]
15832 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15833 && flag_unsafe_math_optimizations"
15837 operands[2] = gen_reg_rtx (XFmode);
15838 operands[3] = gen_reg_rtx (XFmode);
15839 operands[4] = gen_reg_rtx (XFmode);
15841 temp = standard_80387_constant_rtx (3); /* fldlg2 */
15842 emit_move_insn (operands[3], temp);
15845 (define_expand "log10xf2"
15846 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15847 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15848 (match_dup 2)] UNSPEC_FYL2X))
15849 (clobber (match_scratch:XF 3 ""))])]
15850 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15851 && flag_unsafe_math_optimizations"
15855 operands[2] = gen_reg_rtx (XFmode);
15856 temp = standard_80387_constant_rtx (3); /* fldlg2 */
15857 emit_move_insn (operands[2], temp);
15860 (define_expand "log2sf2"
15861 [(set (match_dup 2)
15862 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15863 (parallel [(set (match_dup 4)
15864 (unspec:XF [(match_dup 2)
15865 (match_dup 3)] UNSPEC_FYL2X))
15866 (clobber (match_scratch:XF 5 ""))])
15867 (set (match_operand:SF 0 "register_operand" "")
15868 (float_truncate:SF (match_dup 4)))]
15869 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15870 && flag_unsafe_math_optimizations"
15872 operands[2] = gen_reg_rtx (XFmode);
15873 operands[3] = gen_reg_rtx (XFmode);
15874 operands[4] = gen_reg_rtx (XFmode);
15876 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15879 (define_expand "log2df2"
15880 [(set (match_dup 2)
15881 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15882 (parallel [(set (match_dup 4)
15883 (unspec:XF [(match_dup 2)
15884 (match_dup 3)] UNSPEC_FYL2X))
15885 (clobber (match_scratch:XF 5 ""))])
15886 (set (match_operand:DF 0 "register_operand" "")
15887 (float_truncate:DF (match_dup 4)))]
15888 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15889 && flag_unsafe_math_optimizations"
15891 operands[2] = gen_reg_rtx (XFmode);
15892 operands[3] = gen_reg_rtx (XFmode);
15893 operands[4] = gen_reg_rtx (XFmode);
15895 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15898 (define_expand "log2xf2"
15899 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15900 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15901 (match_dup 2)] UNSPEC_FYL2X))
15902 (clobber (match_scratch:XF 3 ""))])]
15903 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15904 && flag_unsafe_math_optimizations"
15906 operands[2] = gen_reg_rtx (XFmode);
15907 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
15910 (define_insn "fyl2xp1_xf3"
15911 [(set (match_operand:XF 0 "register_operand" "=f")
15912 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15913 (match_operand:XF 1 "register_operand" "u")]
15915 (clobber (match_scratch:XF 3 "=1"))]
15916 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15917 && flag_unsafe_math_optimizations"
15919 [(set_attr "type" "fpspc")
15920 (set_attr "mode" "XF")])
15922 (define_expand "log1psf2"
15923 [(use (match_operand:XF 0 "register_operand" ""))
15924 (use (match_operand:XF 1 "register_operand" ""))]
15925 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15926 && flag_unsafe_math_optimizations"
15928 rtx op0 = gen_reg_rtx (XFmode);
15929 rtx op1 = gen_reg_rtx (XFmode);
15931 emit_insn (gen_extendsfxf2 (op1, operands[1]));
15932 ix86_emit_i387_log1p (op0, op1);
15933 emit_insn (gen_truncxfsf2_noop (operands[0], op0));
15937 (define_expand "log1pdf2"
15938 [(use (match_operand:XF 0 "register_operand" ""))
15939 (use (match_operand:XF 1 "register_operand" ""))]
15940 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15941 && flag_unsafe_math_optimizations"
15943 rtx op0 = gen_reg_rtx (XFmode);
15944 rtx op1 = gen_reg_rtx (XFmode);
15946 emit_insn (gen_extenddfxf2 (op1, operands[1]));
15947 ix86_emit_i387_log1p (op0, op1);
15948 emit_insn (gen_truncxfdf2_noop (operands[0], op0));
15952 (define_expand "log1pxf2"
15953 [(use (match_operand:XF 0 "register_operand" ""))
15954 (use (match_operand:XF 1 "register_operand" ""))]
15955 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15956 && flag_unsafe_math_optimizations"
15958 ix86_emit_i387_log1p (operands[0], operands[1]);
15962 (define_insn "*fxtractxf3"
15963 [(set (match_operand:XF 0 "register_operand" "=f")
15964 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15965 UNSPEC_XTRACT_FRACT))
15966 (set (match_operand:XF 1 "register_operand" "=u")
15967 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))]
15968 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15969 && flag_unsafe_math_optimizations"
15971 [(set_attr "type" "fpspc")
15972 (set_attr "mode" "XF")])
15974 (define_expand "logbsf2"
15975 [(set (match_dup 2)
15976 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15977 (parallel [(set (match_dup 3)
15978 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_FRACT))
15980 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
15981 (set (match_operand:SF 0 "register_operand" "")
15982 (float_truncate:SF (match_dup 4)))]
15983 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15984 && flag_unsafe_math_optimizations"
15986 operands[2] = gen_reg_rtx (XFmode);
15987 operands[3] = gen_reg_rtx (XFmode);
15988 operands[4] = gen_reg_rtx (XFmode);
15991 (define_expand "logbdf2"
15992 [(set (match_dup 2)
15993 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15994 (parallel [(set (match_dup 3)
15995 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_FRACT))
15997 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
15998 (set (match_operand:DF 0 "register_operand" "")
15999 (float_truncate:DF (match_dup 4)))]
16000 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16001 && flag_unsafe_math_optimizations"
16003 operands[2] = gen_reg_rtx (XFmode);
16004 operands[3] = gen_reg_rtx (XFmode);
16005 operands[4] = gen_reg_rtx (XFmode);
16008 (define_expand "logbxf2"
16009 [(parallel [(set (match_dup 2)
16010 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
16011 UNSPEC_XTRACT_FRACT))
16012 (set (match_operand:XF 0 "register_operand" "")
16013 (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
16014 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16015 && flag_unsafe_math_optimizations"
16017 operands[2] = gen_reg_rtx (XFmode);
16020 (define_expand "ilogbsi2"
16021 [(parallel [(set (match_dup 2)
16022 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
16023 UNSPEC_XTRACT_FRACT))
16024 (set (match_operand:XF 3 "register_operand" "")
16025 (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])
16026 (parallel [(set (match_operand:SI 0 "register_operand" "")
16027 (fix:SI (match_dup 3)))
16028 (clobber (reg:CC FLAGS_REG))])]
16029 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16030 && flag_unsafe_math_optimizations"
16032 operands[2] = gen_reg_rtx (XFmode);
16033 operands[3] = gen_reg_rtx (XFmode);
16036 (define_insn "*f2xm1xf2"
16037 [(set (match_operand:XF 0 "register_operand" "=f")
16038 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16040 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16041 && flag_unsafe_math_optimizations"
16043 [(set_attr "type" "fpspc")
16044 (set_attr "mode" "XF")])
16046 (define_insn "*fscalexf4"
16047 [(set (match_operand:XF 0 "register_operand" "=f")
16048 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
16049 (match_operand:XF 3 "register_operand" "1")]
16050 UNSPEC_FSCALE_FRACT))
16051 (set (match_operand:XF 1 "register_operand" "=u")
16052 (unspec:XF [(match_dup 2) (match_dup 3)]
16053 UNSPEC_FSCALE_EXP))]
16054 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16055 && flag_unsafe_math_optimizations"
16057 [(set_attr "type" "fpspc")
16058 (set_attr "mode" "XF")])
16060 (define_expand "expsf2"
16061 [(set (match_dup 2)
16062 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
16063 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16064 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16065 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16066 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16067 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
16068 (parallel [(set (match_dup 10)
16069 (unspec:XF [(match_dup 9) (match_dup 5)]
16070 UNSPEC_FSCALE_FRACT))
16071 (set (match_dup 11)
16072 (unspec:XF [(match_dup 9) (match_dup 5)]
16073 UNSPEC_FSCALE_EXP))])
16074 (set (match_operand:SF 0 "register_operand" "")
16075 (float_truncate:SF (match_dup 10)))]
16076 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16077 && flag_unsafe_math_optimizations"
16082 for (i=2; i<12; i++)
16083 operands[i] = gen_reg_rtx (XFmode);
16084 temp = standard_80387_constant_rtx (5); /* fldl2e */
16085 emit_move_insn (operands[3], temp);
16086 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
16089 (define_expand "expdf2"
16090 [(set (match_dup 2)
16091 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16092 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16093 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16094 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16095 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16096 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
16097 (parallel [(set (match_dup 10)
16098 (unspec:XF [(match_dup 9) (match_dup 5)]
16099 UNSPEC_FSCALE_FRACT))
16100 (set (match_dup 11)
16101 (unspec:XF [(match_dup 9) (match_dup 5)]
16102 UNSPEC_FSCALE_EXP))])
16103 (set (match_operand:DF 0 "register_operand" "")
16104 (float_truncate:DF (match_dup 10)))]
16105 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16106 && flag_unsafe_math_optimizations"
16111 for (i=2; i<12; i++)
16112 operands[i] = gen_reg_rtx (XFmode);
16113 temp = standard_80387_constant_rtx (5); /* fldl2e */
16114 emit_move_insn (operands[3], temp);
16115 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
16118 (define_expand "expxf2"
16119 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
16121 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
16122 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
16123 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
16124 (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
16125 (parallel [(set (match_operand:XF 0 "register_operand" "")
16126 (unspec:XF [(match_dup 8) (match_dup 4)]
16127 UNSPEC_FSCALE_FRACT))
16129 (unspec:XF [(match_dup 8) (match_dup 4)]
16130 UNSPEC_FSCALE_EXP))])]
16131 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16132 && flag_unsafe_math_optimizations"
16137 for (i=2; i<10; i++)
16138 operands[i] = gen_reg_rtx (XFmode);
16139 temp = standard_80387_constant_rtx (5); /* fldl2e */
16140 emit_move_insn (operands[2], temp);
16141 emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
16144 (define_expand "exp10sf2"
16145 [(set (match_dup 2)
16146 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
16147 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16148 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16149 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16150 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16151 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
16152 (parallel [(set (match_dup 10)
16153 (unspec:XF [(match_dup 9) (match_dup 5)]
16154 UNSPEC_FSCALE_FRACT))
16155 (set (match_dup 11)
16156 (unspec:XF [(match_dup 9) (match_dup 5)]
16157 UNSPEC_FSCALE_EXP))])
16158 (set (match_operand:SF 0 "register_operand" "")
16159 (float_truncate:SF (match_dup 10)))]
16160 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16161 && flag_unsafe_math_optimizations"
16166 for (i=2; i<12; i++)
16167 operands[i] = gen_reg_rtx (XFmode);
16168 temp = standard_80387_constant_rtx (6); /* fldl2t */
16169 emit_move_insn (operands[3], temp);
16170 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
16173 (define_expand "exp10df2"
16174 [(set (match_dup 2)
16175 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16176 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16177 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16178 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16179 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16180 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
16181 (parallel [(set (match_dup 10)
16182 (unspec:XF [(match_dup 9) (match_dup 5)]
16183 UNSPEC_FSCALE_FRACT))
16184 (set (match_dup 11)
16185 (unspec:XF [(match_dup 9) (match_dup 5)]
16186 UNSPEC_FSCALE_EXP))])
16187 (set (match_operand:DF 0 "register_operand" "")
16188 (float_truncate:DF (match_dup 10)))]
16189 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16190 && flag_unsafe_math_optimizations"
16195 for (i=2; i<12; i++)
16196 operands[i] = gen_reg_rtx (XFmode);
16197 temp = standard_80387_constant_rtx (6); /* fldl2t */
16198 emit_move_insn (operands[3], temp);
16199 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
16202 (define_expand "exp10xf2"
16203 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
16205 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
16206 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
16207 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
16208 (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
16209 (parallel [(set (match_operand:XF 0 "register_operand" "")
16210 (unspec:XF [(match_dup 8) (match_dup 4)]
16211 UNSPEC_FSCALE_FRACT))
16213 (unspec:XF [(match_dup 8) (match_dup 4)]
16214 UNSPEC_FSCALE_EXP))])]
16215 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16216 && flag_unsafe_math_optimizations"
16221 for (i=2; i<10; i++)
16222 operands[i] = gen_reg_rtx (XFmode);
16223 temp = standard_80387_constant_rtx (6); /* fldl2t */
16224 emit_move_insn (operands[2], temp);
16225 emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
16228 (define_expand "exp2sf2"
16229 [(set (match_dup 2)
16230 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
16231 (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
16232 (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
16233 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
16234 (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
16235 (parallel [(set (match_dup 8)
16236 (unspec:XF [(match_dup 7) (match_dup 3)]
16237 UNSPEC_FSCALE_FRACT))
16239 (unspec:XF [(match_dup 7) (match_dup 3)]
16240 UNSPEC_FSCALE_EXP))])
16241 (set (match_operand:SF 0 "register_operand" "")
16242 (float_truncate:SF (match_dup 8)))]
16243 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16244 && flag_unsafe_math_optimizations"
16248 for (i=2; i<10; i++)
16249 operands[i] = gen_reg_rtx (XFmode);
16250 emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
16253 (define_expand "exp2df2"
16254 [(set (match_dup 2)
16255 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16256 (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
16257 (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
16258 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
16259 (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
16260 (parallel [(set (match_dup 8)
16261 (unspec:XF [(match_dup 7) (match_dup 3)]
16262 UNSPEC_FSCALE_FRACT))
16264 (unspec:XF [(match_dup 7) (match_dup 3)]
16265 UNSPEC_FSCALE_EXP))])
16266 (set (match_operand:DF 0 "register_operand" "")
16267 (float_truncate:DF (match_dup 8)))]
16268 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16269 && flag_unsafe_math_optimizations"
16273 for (i=2; i<10; i++)
16274 operands[i] = gen_reg_rtx (XFmode);
16275 emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
16278 (define_expand "exp2xf2"
16279 [(set (match_dup 2) (match_operand:XF 1 "register_operand" ""))
16280 (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
16281 (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
16282 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
16283 (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
16284 (parallel [(set (match_operand:XF 0 "register_operand" "")
16285 (unspec:XF [(match_dup 7) (match_dup 3)]
16286 UNSPEC_FSCALE_FRACT))
16288 (unspec:XF [(match_dup 7) (match_dup 3)]
16289 UNSPEC_FSCALE_EXP))])]
16290 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16291 && flag_unsafe_math_optimizations"
16295 for (i=2; i<9; i++)
16296 operands[i] = gen_reg_rtx (XFmode);
16297 emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
16300 (define_expand "expm1df2"
16301 [(set (match_dup 2)
16302 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16303 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16304 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16305 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16306 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16307 (parallel [(set (match_dup 8)
16308 (unspec:XF [(match_dup 7) (match_dup 5)]
16309 UNSPEC_FSCALE_FRACT))
16311 (unspec:XF [(match_dup 7) (match_dup 5)]
16312 UNSPEC_FSCALE_EXP))])
16313 (parallel [(set (match_dup 11)
16314 (unspec:XF [(match_dup 10) (match_dup 9)]
16315 UNSPEC_FSCALE_FRACT))
16316 (set (match_dup 12)
16317 (unspec:XF [(match_dup 10) (match_dup 9)]
16318 UNSPEC_FSCALE_EXP))])
16319 (set (match_dup 13) (minus:XF (match_dup 11) (match_dup 10)))
16320 (set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
16321 (set (match_operand:DF 0 "register_operand" "")
16322 (float_truncate:DF (match_dup 14)))]
16323 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16324 && flag_unsafe_math_optimizations"
16329 for (i=2; i<15; i++)
16330 operands[i] = gen_reg_rtx (XFmode);
16331 temp = standard_80387_constant_rtx (5); /* fldl2e */
16332 emit_move_insn (operands[3], temp);
16333 emit_move_insn (operands[10], CONST1_RTX (XFmode)); /* fld1 */
16336 (define_expand "expm1sf2"
16337 [(set (match_dup 2)
16338 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
16339 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16340 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16341 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16342 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16343 (parallel [(set (match_dup 8)
16344 (unspec:XF [(match_dup 7) (match_dup 5)]
16345 UNSPEC_FSCALE_FRACT))
16347 (unspec:XF [(match_dup 7) (match_dup 5)]
16348 UNSPEC_FSCALE_EXP))])
16349 (parallel [(set (match_dup 11)
16350 (unspec:XF [(match_dup 10) (match_dup 9)]
16351 UNSPEC_FSCALE_FRACT))
16352 (set (match_dup 12)
16353 (unspec:XF [(match_dup 10) (match_dup 9)]
16354 UNSPEC_FSCALE_EXP))])
16355 (set (match_dup 13) (minus:XF (match_dup 11) (match_dup 10)))
16356 (set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
16357 (set (match_operand:SF 0 "register_operand" "")
16358 (float_truncate:SF (match_dup 14)))]
16359 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16360 && flag_unsafe_math_optimizations"
16365 for (i=2; i<15; i++)
16366 operands[i] = gen_reg_rtx (XFmode);
16367 temp = standard_80387_constant_rtx (5); /* fldl2e */
16368 emit_move_insn (operands[3], temp);
16369 emit_move_insn (operands[10], CONST1_RTX (XFmode)); /* fld1 */
16372 (define_expand "expm1xf2"
16373 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
16375 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
16376 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
16377 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
16378 (parallel [(set (match_dup 7)
16379 (unspec:XF [(match_dup 6) (match_dup 4)]
16380 UNSPEC_FSCALE_FRACT))
16382 (unspec:XF [(match_dup 6) (match_dup 4)]
16383 UNSPEC_FSCALE_EXP))])
16384 (parallel [(set (match_dup 10)
16385 (unspec:XF [(match_dup 9) (match_dup 8)]
16386 UNSPEC_FSCALE_FRACT))
16387 (set (match_dup 11)
16388 (unspec:XF [(match_dup 9) (match_dup 8)]
16389 UNSPEC_FSCALE_EXP))])
16390 (set (match_dup 12) (minus:XF (match_dup 10) (match_dup 9)))
16391 (set (match_operand:XF 0 "register_operand" "")
16392 (plus:XF (match_dup 12) (match_dup 7)))]
16393 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16394 && flag_unsafe_math_optimizations"
16399 for (i=2; i<13; i++)
16400 operands[i] = gen_reg_rtx (XFmode);
16401 temp = standard_80387_constant_rtx (5); /* fldl2e */
16402 emit_move_insn (operands[2], temp);
16403 emit_move_insn (operands[9], CONST1_RTX (XFmode)); /* fld1 */
16407 (define_insn "frndintxf2"
16408 [(set (match_operand:XF 0 "register_operand" "=f")
16409 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16411 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16412 && flag_unsafe_math_optimizations"
16414 [(set_attr "type" "fpspc")
16415 (set_attr "mode" "XF")])
16417 (define_expand "rintdf2"
16418 [(use (match_operand:DF 0 "register_operand" ""))
16419 (use (match_operand:DF 1 "register_operand" ""))]
16420 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16421 && flag_unsafe_math_optimizations"
16423 rtx op0 = gen_reg_rtx (XFmode);
16424 rtx op1 = gen_reg_rtx (XFmode);
16426 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16427 emit_insn (gen_frndintxf2 (op0, op1));
16429 emit_insn (gen_truncxfdf2_noop (operands[0], op0));
16433 (define_expand "rintsf2"
16434 [(use (match_operand:SF 0 "register_operand" ""))
16435 (use (match_operand:SF 1 "register_operand" ""))]
16436 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16437 && flag_unsafe_math_optimizations"
16439 rtx op0 = gen_reg_rtx (XFmode);
16440 rtx op1 = gen_reg_rtx (XFmode);
16442 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16443 emit_insn (gen_frndintxf2 (op0, op1));
16445 emit_insn (gen_truncxfsf2_noop (operands[0], op0));
16449 (define_expand "rintxf2"
16450 [(use (match_operand:XF 0 "register_operand" ""))
16451 (use (match_operand:XF 1 "register_operand" ""))]
16452 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16453 && flag_unsafe_math_optimizations"
16455 emit_insn (gen_frndintxf2 (operands[0], operands[1]));
16459 (define_insn "frndintxf2_floor"
16460 [(set (match_operand:XF 0 "register_operand" "=f")
16461 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16462 UNSPEC_FRNDINT_FLOOR))
16463 (use (match_operand:HI 2 "memory_operand" "m"))
16464 (use (match_operand:HI 3 "memory_operand" "m"))]
16465 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16466 && flag_unsafe_math_optimizations"
16467 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
16468 [(set_attr "type" "frndint")
16469 (set_attr "i387_cw" "floor")
16470 (set_attr "mode" "XF")])
16472 (define_expand "floordf2"
16473 [(use (match_operand:DF 0 "register_operand" ""))
16474 (use (match_operand:DF 1 "register_operand" ""))]
16475 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16476 && flag_unsafe_math_optimizations"
16478 rtx op0 = gen_reg_rtx (XFmode);
16479 rtx op1 = gen_reg_rtx (XFmode);
16480 rtx op2 = assign_386_stack_local (HImode, 1);
16481 rtx op3 = assign_386_stack_local (HImode, 2);
16483 ix86_optimize_mode_switching = 1;
16485 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16486 emit_insn (gen_frndintxf2_floor (op0, op1, op2, op3));
16488 emit_insn (gen_truncxfdf2_noop (operands[0], op0));
16492 (define_expand "floorsf2"
16493 [(use (match_operand:SF 0 "register_operand" ""))
16494 (use (match_operand:SF 1 "register_operand" ""))]
16495 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16496 && flag_unsafe_math_optimizations"
16498 rtx op0 = gen_reg_rtx (XFmode);
16499 rtx op1 = gen_reg_rtx (XFmode);
16500 rtx op2 = assign_386_stack_local (HImode, 1);
16501 rtx op3 = assign_386_stack_local (HImode, 2);
16503 ix86_optimize_mode_switching = 1;
16505 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16506 emit_insn (gen_frndintxf2_floor (op0, op1, op2, op3));
16508 emit_insn (gen_truncxfsf2_noop (operands[0], op0));
16512 (define_expand "floorxf2"
16513 [(use (match_operand:XF 0 "register_operand" ""))
16514 (use (match_operand:XF 1 "register_operand" ""))]
16515 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16516 && flag_unsafe_math_optimizations"
16518 rtx op2 = assign_386_stack_local (HImode, 1);
16519 rtx op3 = assign_386_stack_local (HImode, 2);
16521 ix86_optimize_mode_switching = 1;
16523 emit_insn (gen_frndintxf2_floor (operands[0], operands[1], op2, op3));
16527 (define_insn "frndintxf2_ceil"
16528 [(set (match_operand:XF 0 "register_operand" "=f")
16529 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16530 UNSPEC_FRNDINT_CEIL))
16531 (use (match_operand:HI 2 "memory_operand" "m"))
16532 (use (match_operand:HI 3 "memory_operand" "m"))]
16533 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16534 && flag_unsafe_math_optimizations"
16535 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
16536 [(set_attr "type" "frndint")
16537 (set_attr "i387_cw" "ceil")
16538 (set_attr "mode" "XF")])
16540 (define_expand "ceildf2"
16541 [(use (match_operand:DF 0 "register_operand" ""))
16542 (use (match_operand:DF 1 "register_operand" ""))]
16543 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16544 && flag_unsafe_math_optimizations"
16546 rtx op0 = gen_reg_rtx (XFmode);
16547 rtx op1 = gen_reg_rtx (XFmode);
16548 rtx op2 = assign_386_stack_local (HImode, 1);
16549 rtx op3 = assign_386_stack_local (HImode, 2);
16551 ix86_optimize_mode_switching = 1;
16553 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16554 emit_insn (gen_frndintxf2_ceil (op0, op1, op2, op3));
16556 emit_insn (gen_truncxfdf2_noop (operands[0], op0));
16560 (define_expand "ceilsf2"
16561 [(use (match_operand:SF 0 "register_operand" ""))
16562 (use (match_operand:SF 1 "register_operand" ""))]
16563 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16564 && flag_unsafe_math_optimizations"
16566 rtx op0 = gen_reg_rtx (XFmode);
16567 rtx op1 = gen_reg_rtx (XFmode);
16568 rtx op2 = assign_386_stack_local (HImode, 1);
16569 rtx op3 = assign_386_stack_local (HImode, 2);
16571 ix86_optimize_mode_switching = 1;
16573 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16574 emit_insn (gen_frndintxf2_ceil (op0, op1, op2, op3));
16576 emit_insn (gen_truncxfsf2_noop (operands[0], op0));
16580 (define_expand "ceilxf2"
16581 [(use (match_operand:XF 0 "register_operand" ""))
16582 (use (match_operand:XF 1 "register_operand" ""))]
16583 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16584 && flag_unsafe_math_optimizations"
16586 rtx op2 = assign_386_stack_local (HImode, 1);
16587 rtx op3 = assign_386_stack_local (HImode, 2);
16589 ix86_optimize_mode_switching = 1;
16591 emit_insn (gen_frndintxf2_ceil (operands[0], operands[1], op2, op3));
16595 (define_insn "frndintxf2_trunc"
16596 [(set (match_operand:XF 0 "register_operand" "=f")
16597 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16598 UNSPEC_FRNDINT_TRUNC))
16599 (use (match_operand:HI 2 "memory_operand" "m"))
16600 (use (match_operand:HI 3 "memory_operand" "m"))]
16601 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16602 && flag_unsafe_math_optimizations"
16603 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
16604 [(set_attr "type" "frndint")
16605 (set_attr "i387_cw" "trunc")
16606 (set_attr "mode" "XF")])
16608 (define_expand "btruncdf2"
16609 [(use (match_operand:DF 0 "register_operand" ""))
16610 (use (match_operand:DF 1 "register_operand" ""))]
16611 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16612 && flag_unsafe_math_optimizations"
16614 rtx op0 = gen_reg_rtx (XFmode);
16615 rtx op1 = gen_reg_rtx (XFmode);
16616 rtx op2 = assign_386_stack_local (HImode, 1);
16617 rtx op3 = assign_386_stack_local (HImode, 2);
16619 ix86_optimize_mode_switching = 1;
16621 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16622 emit_insn (gen_frndintxf2_trunc (op0, op1, op2, op3));
16624 emit_insn (gen_truncxfdf2_noop (operands[0], op0));
16628 (define_expand "btruncsf2"
16629 [(use (match_operand:SF 0 "register_operand" ""))
16630 (use (match_operand:SF 1 "register_operand" ""))]
16631 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16632 && flag_unsafe_math_optimizations"
16634 rtx op0 = gen_reg_rtx (XFmode);
16635 rtx op1 = gen_reg_rtx (XFmode);
16636 rtx op2 = assign_386_stack_local (HImode, 1);
16637 rtx op3 = assign_386_stack_local (HImode, 2);
16639 ix86_optimize_mode_switching = 1;
16641 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16642 emit_insn (gen_frndintxf2_trunc (op0, op1, op2, op3));
16644 emit_insn (gen_truncxfsf2_noop (operands[0], op0));
16648 (define_expand "btruncxf2"
16649 [(use (match_operand:XF 0 "register_operand" ""))
16650 (use (match_operand:XF 1 "register_operand" ""))]
16651 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16652 && flag_unsafe_math_optimizations"
16654 rtx op2 = assign_386_stack_local (HImode, 1);
16655 rtx op3 = assign_386_stack_local (HImode, 2);
16657 ix86_optimize_mode_switching = 1;
16659 emit_insn (gen_frndintxf2_trunc (operands[0], operands[1], op2, op3));
16663 (define_insn "frndintxf2_mask_pm"
16664 [(set (match_operand:XF 0 "register_operand" "=f")
16665 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16666 UNSPEC_FRNDINT_MASK_PM))
16667 (use (match_operand:HI 2 "memory_operand" "m"))
16668 (use (match_operand:HI 3 "memory_operand" "m"))]
16669 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16670 && flag_unsafe_math_optimizations"
16671 "fldcw\t%3\n\tfrndint\n\tfclex\n\tfldcw\t%2"
16672 [(set_attr "type" "frndint")
16673 (set_attr "i387_cw" "mask_pm")
16674 (set_attr "mode" "XF")])
16676 (define_expand "nearbyintdf2"
16677 [(use (match_operand:DF 0 "register_operand" ""))
16678 (use (match_operand:DF 1 "register_operand" ""))]
16679 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16680 && flag_unsafe_math_optimizations"
16682 rtx op0 = gen_reg_rtx (XFmode);
16683 rtx op1 = gen_reg_rtx (XFmode);
16684 rtx op2 = assign_386_stack_local (HImode, 1);
16685 rtx op3 = assign_386_stack_local (HImode, 2);
16687 ix86_optimize_mode_switching = 1;
16689 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16690 emit_insn (gen_frndintxf2_mask_pm (op0, op1, op2, op3));
16692 emit_insn (gen_truncxfdf2_noop (operands[0], op0));
16696 (define_expand "nearbyintsf2"
16697 [(use (match_operand:SF 0 "register_operand" ""))
16698 (use (match_operand:SF 1 "register_operand" ""))]
16699 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16700 && flag_unsafe_math_optimizations"
16702 rtx op0 = gen_reg_rtx (XFmode);
16703 rtx op1 = gen_reg_rtx (XFmode);
16704 rtx op2 = assign_386_stack_local (HImode, 1);
16705 rtx op3 = assign_386_stack_local (HImode, 2);
16707 ix86_optimize_mode_switching = 1;
16709 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16710 emit_insn (gen_frndintxf2_mask_pm (op0, op1, op2, op3));
16712 emit_insn (gen_truncxfsf2_noop (operands[0], op0));
16716 (define_expand "nearbyintxf2"
16717 [(use (match_operand:XF 0 "register_operand" ""))
16718 (use (match_operand:XF 1 "register_operand" ""))]
16719 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16720 && flag_unsafe_math_optimizations"
16722 rtx op2 = assign_386_stack_local (HImode, 1);
16723 rtx op3 = assign_386_stack_local (HImode, 2);
16725 ix86_optimize_mode_switching = 1;
16727 emit_insn (gen_frndintxf2_mask_pm (operands[0], operands[1],
16733 ;; Block operation instructions
16736 [(set (reg:SI DIRFLAG_REG) (const_int 0))]
16739 [(set_attr "type" "cld")])
16741 (define_expand "movmemsi"
16742 [(use (match_operand:BLK 0 "memory_operand" ""))
16743 (use (match_operand:BLK 1 "memory_operand" ""))
16744 (use (match_operand:SI 2 "nonmemory_operand" ""))
16745 (use (match_operand:SI 3 "const_int_operand" ""))]
16748 if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
16754 (define_expand "movmemdi"
16755 [(use (match_operand:BLK 0 "memory_operand" ""))
16756 (use (match_operand:BLK 1 "memory_operand" ""))
16757 (use (match_operand:DI 2 "nonmemory_operand" ""))
16758 (use (match_operand:DI 3 "const_int_operand" ""))]
16761 if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
16767 ;; Most CPUs don't like single string operations
16768 ;; Handle this case here to simplify previous expander.
16770 (define_expand "strmov"
16771 [(set (match_dup 4) (match_operand 3 "memory_operand" ""))
16772 (set (match_operand 1 "memory_operand" "") (match_dup 4))
16773 (parallel [(set (match_operand 0 "register_operand" "") (match_dup 5))
16774 (clobber (reg:CC FLAGS_REG))])
16775 (parallel [(set (match_operand 2 "register_operand" "") (match_dup 6))
16776 (clobber (reg:CC FLAGS_REG))])]
16779 rtx adjust = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[1])));
16781 /* If .md ever supports :P for Pmode, these can be directly
16782 in the pattern above. */
16783 operands[5] = gen_rtx_PLUS (Pmode, operands[0], adjust);
16784 operands[6] = gen_rtx_PLUS (Pmode, operands[2], adjust);
16786 if (TARGET_SINGLE_STRINGOP || optimize_size)
16788 emit_insn (gen_strmov_singleop (operands[0], operands[1],
16789 operands[2], operands[3],
16790 operands[5], operands[6]));
16794 operands[4] = gen_reg_rtx (GET_MODE (operands[1]));
16797 (define_expand "strmov_singleop"
16798 [(parallel [(set (match_operand 1 "memory_operand" "")
16799 (match_operand 3 "memory_operand" ""))
16800 (set (match_operand 0 "register_operand" "")
16801 (match_operand 4 "" ""))
16802 (set (match_operand 2 "register_operand" "")
16803 (match_operand 5 "" ""))
16804 (use (reg:SI DIRFLAG_REG))])]
16805 "TARGET_SINGLE_STRINGOP || optimize_size"
16808 (define_insn "*strmovdi_rex_1"
16809 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
16810 (mem:DI (match_operand:DI 3 "register_operand" "1")))
16811 (set (match_operand:DI 0 "register_operand" "=D")
16812 (plus:DI (match_dup 2)
16814 (set (match_operand:DI 1 "register_operand" "=S")
16815 (plus:DI (match_dup 3)
16817 (use (reg:SI DIRFLAG_REG))]
16818 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16820 [(set_attr "type" "str")
16821 (set_attr "mode" "DI")
16822 (set_attr "memory" "both")])
16824 (define_insn "*strmovsi_1"
16825 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
16826 (mem:SI (match_operand:SI 3 "register_operand" "1")))
16827 (set (match_operand:SI 0 "register_operand" "=D")
16828 (plus:SI (match_dup 2)
16830 (set (match_operand:SI 1 "register_operand" "=S")
16831 (plus:SI (match_dup 3)
16833 (use (reg:SI DIRFLAG_REG))]
16834 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16836 [(set_attr "type" "str")
16837 (set_attr "mode" "SI")
16838 (set_attr "memory" "both")])
16840 (define_insn "*strmovsi_rex_1"
16841 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
16842 (mem:SI (match_operand:DI 3 "register_operand" "1")))
16843 (set (match_operand:DI 0 "register_operand" "=D")
16844 (plus:DI (match_dup 2)
16846 (set (match_operand:DI 1 "register_operand" "=S")
16847 (plus:DI (match_dup 3)
16849 (use (reg:SI DIRFLAG_REG))]
16850 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16852 [(set_attr "type" "str")
16853 (set_attr "mode" "SI")
16854 (set_attr "memory" "both")])
16856 (define_insn "*strmovhi_1"
16857 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
16858 (mem:HI (match_operand:SI 3 "register_operand" "1")))
16859 (set (match_operand:SI 0 "register_operand" "=D")
16860 (plus:SI (match_dup 2)
16862 (set (match_operand:SI 1 "register_operand" "=S")
16863 (plus:SI (match_dup 3)
16865 (use (reg:SI DIRFLAG_REG))]
16866 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16868 [(set_attr "type" "str")
16869 (set_attr "memory" "both")
16870 (set_attr "mode" "HI")])
16872 (define_insn "*strmovhi_rex_1"
16873 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
16874 (mem:HI (match_operand:DI 3 "register_operand" "1")))
16875 (set (match_operand:DI 0 "register_operand" "=D")
16876 (plus:DI (match_dup 2)
16878 (set (match_operand:DI 1 "register_operand" "=S")
16879 (plus:DI (match_dup 3)
16881 (use (reg:SI DIRFLAG_REG))]
16882 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16884 [(set_attr "type" "str")
16885 (set_attr "memory" "both")
16886 (set_attr "mode" "HI")])
16888 (define_insn "*strmovqi_1"
16889 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
16890 (mem:QI (match_operand:SI 3 "register_operand" "1")))
16891 (set (match_operand:SI 0 "register_operand" "=D")
16892 (plus:SI (match_dup 2)
16894 (set (match_operand:SI 1 "register_operand" "=S")
16895 (plus:SI (match_dup 3)
16897 (use (reg:SI DIRFLAG_REG))]
16898 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16900 [(set_attr "type" "str")
16901 (set_attr "memory" "both")
16902 (set_attr "mode" "QI")])
16904 (define_insn "*strmovqi_rex_1"
16905 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
16906 (mem:QI (match_operand:DI 3 "register_operand" "1")))
16907 (set (match_operand:DI 0 "register_operand" "=D")
16908 (plus:DI (match_dup 2)
16910 (set (match_operand:DI 1 "register_operand" "=S")
16911 (plus:DI (match_dup 3)
16913 (use (reg:SI DIRFLAG_REG))]
16914 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16916 [(set_attr "type" "str")
16917 (set_attr "memory" "both")
16918 (set_attr "mode" "QI")])
16920 (define_expand "rep_mov"
16921 [(parallel [(set (match_operand 4 "register_operand" "") (const_int 0))
16922 (set (match_operand 0 "register_operand" "")
16923 (match_operand 5 "" ""))
16924 (set (match_operand 2 "register_operand" "")
16925 (match_operand 6 "" ""))
16926 (set (match_operand 1 "memory_operand" "")
16927 (match_operand 3 "memory_operand" ""))
16928 (use (match_dup 4))
16929 (use (reg:SI DIRFLAG_REG))])]
16933 (define_insn "*rep_movdi_rex64"
16934 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
16935 (set (match_operand:DI 0 "register_operand" "=D")
16936 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
16938 (match_operand:DI 3 "register_operand" "0")))
16939 (set (match_operand:DI 1 "register_operand" "=S")
16940 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
16941 (match_operand:DI 4 "register_operand" "1")))
16942 (set (mem:BLK (match_dup 3))
16943 (mem:BLK (match_dup 4)))
16944 (use (match_dup 5))
16945 (use (reg:SI DIRFLAG_REG))]
16947 "{rep\;movsq|rep movsq}"
16948 [(set_attr "type" "str")
16949 (set_attr "prefix_rep" "1")
16950 (set_attr "memory" "both")
16951 (set_attr "mode" "DI")])
16953 (define_insn "*rep_movsi"
16954 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
16955 (set (match_operand:SI 0 "register_operand" "=D")
16956 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
16958 (match_operand:SI 3 "register_operand" "0")))
16959 (set (match_operand:SI 1 "register_operand" "=S")
16960 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
16961 (match_operand:SI 4 "register_operand" "1")))
16962 (set (mem:BLK (match_dup 3))
16963 (mem:BLK (match_dup 4)))
16964 (use (match_dup 5))
16965 (use (reg:SI DIRFLAG_REG))]
16967 "{rep\;movsl|rep movsd}"
16968 [(set_attr "type" "str")
16969 (set_attr "prefix_rep" "1")
16970 (set_attr "memory" "both")
16971 (set_attr "mode" "SI")])
16973 (define_insn "*rep_movsi_rex64"
16974 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
16975 (set (match_operand:DI 0 "register_operand" "=D")
16976 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
16978 (match_operand:DI 3 "register_operand" "0")))
16979 (set (match_operand:DI 1 "register_operand" "=S")
16980 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
16981 (match_operand:DI 4 "register_operand" "1")))
16982 (set (mem:BLK (match_dup 3))
16983 (mem:BLK (match_dup 4)))
16984 (use (match_dup 5))
16985 (use (reg:SI DIRFLAG_REG))]
16987 "{rep\;movsl|rep movsd}"
16988 [(set_attr "type" "str")
16989 (set_attr "prefix_rep" "1")
16990 (set_attr "memory" "both")
16991 (set_attr "mode" "SI")])
16993 (define_insn "*rep_movqi"
16994 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
16995 (set (match_operand:SI 0 "register_operand" "=D")
16996 (plus:SI (match_operand:SI 3 "register_operand" "0")
16997 (match_operand:SI 5 "register_operand" "2")))
16998 (set (match_operand:SI 1 "register_operand" "=S")
16999 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
17000 (set (mem:BLK (match_dup 3))
17001 (mem:BLK (match_dup 4)))
17002 (use (match_dup 5))
17003 (use (reg:SI DIRFLAG_REG))]
17005 "{rep\;movsb|rep movsb}"
17006 [(set_attr "type" "str")
17007 (set_attr "prefix_rep" "1")
17008 (set_attr "memory" "both")
17009 (set_attr "mode" "SI")])
17011 (define_insn "*rep_movqi_rex64"
17012 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
17013 (set (match_operand:DI 0 "register_operand" "=D")
17014 (plus:DI (match_operand:DI 3 "register_operand" "0")
17015 (match_operand:DI 5 "register_operand" "2")))
17016 (set (match_operand:DI 1 "register_operand" "=S")
17017 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
17018 (set (mem:BLK (match_dup 3))
17019 (mem:BLK (match_dup 4)))
17020 (use (match_dup 5))
17021 (use (reg:SI DIRFLAG_REG))]
17023 "{rep\;movsb|rep movsb}"
17024 [(set_attr "type" "str")
17025 (set_attr "prefix_rep" "1")
17026 (set_attr "memory" "both")
17027 (set_attr "mode" "SI")])
17029 (define_expand "clrmemsi"
17030 [(use (match_operand:BLK 0 "memory_operand" ""))
17031 (use (match_operand:SI 1 "nonmemory_operand" ""))
17032 (use (match_operand 2 "const_int_operand" ""))]
17035 if (ix86_expand_clrmem (operands[0], operands[1], operands[2]))
17041 (define_expand "clrmemdi"
17042 [(use (match_operand:BLK 0 "memory_operand" ""))
17043 (use (match_operand:DI 1 "nonmemory_operand" ""))
17044 (use (match_operand 2 "const_int_operand" ""))]
17047 if (ix86_expand_clrmem (operands[0], operands[1], operands[2]))
17053 ;; Most CPUs don't like single string operations
17054 ;; Handle this case here to simplify previous expander.
17056 (define_expand "strset"
17057 [(set (match_operand 1 "memory_operand" "")
17058 (match_operand 2 "register_operand" ""))
17059 (parallel [(set (match_operand 0 "register_operand" "")
17061 (clobber (reg:CC FLAGS_REG))])]
17064 if (GET_MODE (operands[1]) != GET_MODE (operands[2]))
17065 operands[1] = adjust_address_nv (operands[1], GET_MODE (operands[2]), 0);
17067 /* If .md ever supports :P for Pmode, this can be directly
17068 in the pattern above. */
17069 operands[3] = gen_rtx_PLUS (Pmode, operands[0],
17070 GEN_INT (GET_MODE_SIZE (GET_MODE
17072 if (TARGET_SINGLE_STRINGOP || optimize_size)
17074 emit_insn (gen_strset_singleop (operands[0], operands[1], operands[2],
17080 (define_expand "strset_singleop"
17081 [(parallel [(set (match_operand 1 "memory_operand" "")
17082 (match_operand 2 "register_operand" ""))
17083 (set (match_operand 0 "register_operand" "")
17084 (match_operand 3 "" ""))
17085 (use (reg:SI DIRFLAG_REG))])]
17086 "TARGET_SINGLE_STRINGOP || optimize_size"
17089 (define_insn "*strsetdi_rex_1"
17090 [(set (mem:DI (match_operand:DI 1 "register_operand" "0"))
17091 (match_operand:DI 2 "register_operand" "a"))
17092 (set (match_operand:DI 0 "register_operand" "=D")
17093 (plus:DI (match_dup 1)
17095 (use (reg:SI DIRFLAG_REG))]
17096 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17098 [(set_attr "type" "str")
17099 (set_attr "memory" "store")
17100 (set_attr "mode" "DI")])
17102 (define_insn "*strsetsi_1"
17103 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
17104 (match_operand:SI 2 "register_operand" "a"))
17105 (set (match_operand:SI 0 "register_operand" "=D")
17106 (plus:SI (match_dup 1)
17108 (use (reg:SI DIRFLAG_REG))]
17109 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17111 [(set_attr "type" "str")
17112 (set_attr "memory" "store")
17113 (set_attr "mode" "SI")])
17115 (define_insn "*strsetsi_rex_1"
17116 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
17117 (match_operand:SI 2 "register_operand" "a"))
17118 (set (match_operand:DI 0 "register_operand" "=D")
17119 (plus:DI (match_dup 1)
17121 (use (reg:SI DIRFLAG_REG))]
17122 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17124 [(set_attr "type" "str")
17125 (set_attr "memory" "store")
17126 (set_attr "mode" "SI")])
17128 (define_insn "*strsethi_1"
17129 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
17130 (match_operand:HI 2 "register_operand" "a"))
17131 (set (match_operand:SI 0 "register_operand" "=D")
17132 (plus:SI (match_dup 1)
17134 (use (reg:SI DIRFLAG_REG))]
17135 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17137 [(set_attr "type" "str")
17138 (set_attr "memory" "store")
17139 (set_attr "mode" "HI")])
17141 (define_insn "*strsethi_rex_1"
17142 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
17143 (match_operand:HI 2 "register_operand" "a"))
17144 (set (match_operand:DI 0 "register_operand" "=D")
17145 (plus:DI (match_dup 1)
17147 (use (reg:SI DIRFLAG_REG))]
17148 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17150 [(set_attr "type" "str")
17151 (set_attr "memory" "store")
17152 (set_attr "mode" "HI")])
17154 (define_insn "*strsetqi_1"
17155 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
17156 (match_operand:QI 2 "register_operand" "a"))
17157 (set (match_operand:SI 0 "register_operand" "=D")
17158 (plus:SI (match_dup 1)
17160 (use (reg:SI DIRFLAG_REG))]
17161 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17163 [(set_attr "type" "str")
17164 (set_attr "memory" "store")
17165 (set_attr "mode" "QI")])
17167 (define_insn "*strsetqi_rex_1"
17168 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
17169 (match_operand:QI 2 "register_operand" "a"))
17170 (set (match_operand:DI 0 "register_operand" "=D")
17171 (plus:DI (match_dup 1)
17173 (use (reg:SI DIRFLAG_REG))]
17174 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17176 [(set_attr "type" "str")
17177 (set_attr "memory" "store")
17178 (set_attr "mode" "QI")])
17180 (define_expand "rep_stos"
17181 [(parallel [(set (match_operand 1 "register_operand" "") (const_int 0))
17182 (set (match_operand 0 "register_operand" "")
17183 (match_operand 4 "" ""))
17184 (set (match_operand 2 "memory_operand" "") (const_int 0))
17185 (use (match_operand 3 "register_operand" ""))
17186 (use (match_dup 1))
17187 (use (reg:SI DIRFLAG_REG))])]
17191 (define_insn "*rep_stosdi_rex64"
17192 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
17193 (set (match_operand:DI 0 "register_operand" "=D")
17194 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
17196 (match_operand:DI 3 "register_operand" "0")))
17197 (set (mem:BLK (match_dup 3))
17199 (use (match_operand:DI 2 "register_operand" "a"))
17200 (use (match_dup 4))
17201 (use (reg:SI DIRFLAG_REG))]
17203 "{rep\;stosq|rep stosq}"
17204 [(set_attr "type" "str")
17205 (set_attr "prefix_rep" "1")
17206 (set_attr "memory" "store")
17207 (set_attr "mode" "DI")])
17209 (define_insn "*rep_stossi"
17210 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
17211 (set (match_operand:SI 0 "register_operand" "=D")
17212 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
17214 (match_operand:SI 3 "register_operand" "0")))
17215 (set (mem:BLK (match_dup 3))
17217 (use (match_operand:SI 2 "register_operand" "a"))
17218 (use (match_dup 4))
17219 (use (reg:SI DIRFLAG_REG))]
17221 "{rep\;stosl|rep stosd}"
17222 [(set_attr "type" "str")
17223 (set_attr "prefix_rep" "1")
17224 (set_attr "memory" "store")
17225 (set_attr "mode" "SI")])
17227 (define_insn "*rep_stossi_rex64"
17228 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
17229 (set (match_operand:DI 0 "register_operand" "=D")
17230 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
17232 (match_operand:DI 3 "register_operand" "0")))
17233 (set (mem:BLK (match_dup 3))
17235 (use (match_operand:SI 2 "register_operand" "a"))
17236 (use (match_dup 4))
17237 (use (reg:SI DIRFLAG_REG))]
17239 "{rep\;stosl|rep stosd}"
17240 [(set_attr "type" "str")
17241 (set_attr "prefix_rep" "1")
17242 (set_attr "memory" "store")
17243 (set_attr "mode" "SI")])
17245 (define_insn "*rep_stosqi"
17246 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
17247 (set (match_operand:SI 0 "register_operand" "=D")
17248 (plus:SI (match_operand:SI 3 "register_operand" "0")
17249 (match_operand:SI 4 "register_operand" "1")))
17250 (set (mem:BLK (match_dup 3))
17252 (use (match_operand:QI 2 "register_operand" "a"))
17253 (use (match_dup 4))
17254 (use (reg:SI DIRFLAG_REG))]
17256 "{rep\;stosb|rep stosb}"
17257 [(set_attr "type" "str")
17258 (set_attr "prefix_rep" "1")
17259 (set_attr "memory" "store")
17260 (set_attr "mode" "QI")])
17262 (define_insn "*rep_stosqi_rex64"
17263 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
17264 (set (match_operand:DI 0 "register_operand" "=D")
17265 (plus:DI (match_operand:DI 3 "register_operand" "0")
17266 (match_operand:DI 4 "register_operand" "1")))
17267 (set (mem:BLK (match_dup 3))
17269 (use (match_operand:QI 2 "register_operand" "a"))
17270 (use (match_dup 4))
17271 (use (reg:SI DIRFLAG_REG))]
17273 "{rep\;stosb|rep stosb}"
17274 [(set_attr "type" "str")
17275 (set_attr "prefix_rep" "1")
17276 (set_attr "memory" "store")
17277 (set_attr "mode" "QI")])
17279 (define_expand "cmpstrsi"
17280 [(set (match_operand:SI 0 "register_operand" "")
17281 (compare:SI (match_operand:BLK 1 "general_operand" "")
17282 (match_operand:BLK 2 "general_operand" "")))
17283 (use (match_operand 3 "general_operand" ""))
17284 (use (match_operand 4 "immediate_operand" ""))]
17285 "! optimize_size || TARGET_INLINE_ALL_STRINGOPS"
17287 rtx addr1, addr2, out, outlow, count, countreg, align;
17289 /* Can't use this if the user has appropriated esi or edi. */
17290 if (global_regs[4] || global_regs[5])
17294 if (GET_CODE (out) != REG)
17295 out = gen_reg_rtx (SImode);
17297 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
17298 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
17299 if (addr1 != XEXP (operands[1], 0))
17300 operands[1] = replace_equiv_address_nv (operands[1], addr1);
17301 if (addr2 != XEXP (operands[2], 0))
17302 operands[2] = replace_equiv_address_nv (operands[2], addr2);
17304 count = operands[3];
17305 countreg = ix86_zero_extend_to_Pmode (count);
17307 /* %%% Iff we are testing strict equality, we can use known alignment
17308 to good advantage. This may be possible with combine, particularly
17309 once cc0 is dead. */
17310 align = operands[4];
17312 emit_insn (gen_cld ());
17313 if (GET_CODE (count) == CONST_INT)
17315 if (INTVAL (count) == 0)
17317 emit_move_insn (operands[0], const0_rtx);
17320 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
17321 operands[1], operands[2]));
17326 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
17328 emit_insn (gen_cmpsi_1 (countreg, countreg));
17329 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
17330 operands[1], operands[2]));
17333 outlow = gen_lowpart (QImode, out);
17334 emit_insn (gen_cmpintqi (outlow));
17335 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
17337 if (operands[0] != out)
17338 emit_move_insn (operands[0], out);
17343 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
17345 (define_expand "cmpintqi"
17346 [(set (match_dup 1)
17347 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
17349 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
17350 (parallel [(set (match_operand:QI 0 "register_operand" "")
17351 (minus:QI (match_dup 1)
17353 (clobber (reg:CC FLAGS_REG))])]
17355 "operands[1] = gen_reg_rtx (QImode);
17356 operands[2] = gen_reg_rtx (QImode);")
17358 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
17359 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
17361 (define_expand "cmpstrqi_nz_1"
17362 [(parallel [(set (reg:CC FLAGS_REG)
17363 (compare:CC (match_operand 4 "memory_operand" "")
17364 (match_operand 5 "memory_operand" "")))
17365 (use (match_operand 2 "register_operand" ""))
17366 (use (match_operand:SI 3 "immediate_operand" ""))
17367 (use (reg:SI DIRFLAG_REG))
17368 (clobber (match_operand 0 "register_operand" ""))
17369 (clobber (match_operand 1 "register_operand" ""))
17370 (clobber (match_dup 2))])]
17374 (define_insn "*cmpstrqi_nz_1"
17375 [(set (reg:CC FLAGS_REG)
17376 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
17377 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
17378 (use (match_operand:SI 6 "register_operand" "2"))
17379 (use (match_operand:SI 3 "immediate_operand" "i"))
17380 (use (reg:SI DIRFLAG_REG))
17381 (clobber (match_operand:SI 0 "register_operand" "=S"))
17382 (clobber (match_operand:SI 1 "register_operand" "=D"))
17383 (clobber (match_operand:SI 2 "register_operand" "=c"))]
17386 [(set_attr "type" "str")
17387 (set_attr "mode" "QI")
17388 (set_attr "prefix_rep" "1")])
17390 (define_insn "*cmpstrqi_nz_rex_1"
17391 [(set (reg:CC FLAGS_REG)
17392 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
17393 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
17394 (use (match_operand:DI 6 "register_operand" "2"))
17395 (use (match_operand:SI 3 "immediate_operand" "i"))
17396 (use (reg:SI DIRFLAG_REG))
17397 (clobber (match_operand:DI 0 "register_operand" "=S"))
17398 (clobber (match_operand:DI 1 "register_operand" "=D"))
17399 (clobber (match_operand:DI 2 "register_operand" "=c"))]
17402 [(set_attr "type" "str")
17403 (set_attr "mode" "QI")
17404 (set_attr "prefix_rep" "1")])
17406 ;; The same, but the count is not known to not be zero.
17408 (define_expand "cmpstrqi_1"
17409 [(parallel [(set (reg:CC FLAGS_REG)
17410 (if_then_else:CC (ne (match_operand 2 "register_operand" "")
17412 (compare:CC (match_operand 4 "memory_operand" "")
17413 (match_operand 5 "memory_operand" ""))
17415 (use (match_operand:SI 3 "immediate_operand" ""))
17416 (use (reg:CC FLAGS_REG))
17417 (use (reg:SI DIRFLAG_REG))
17418 (clobber (match_operand 0 "register_operand" ""))
17419 (clobber (match_operand 1 "register_operand" ""))
17420 (clobber (match_dup 2))])]
17424 (define_insn "*cmpstrqi_1"
17425 [(set (reg:CC FLAGS_REG)
17426 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
17428 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
17429 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
17431 (use (match_operand:SI 3 "immediate_operand" "i"))
17432 (use (reg:CC FLAGS_REG))
17433 (use (reg:SI DIRFLAG_REG))
17434 (clobber (match_operand:SI 0 "register_operand" "=S"))
17435 (clobber (match_operand:SI 1 "register_operand" "=D"))
17436 (clobber (match_operand:SI 2 "register_operand" "=c"))]
17439 [(set_attr "type" "str")
17440 (set_attr "mode" "QI")
17441 (set_attr "prefix_rep" "1")])
17443 (define_insn "*cmpstrqi_rex_1"
17444 [(set (reg:CC FLAGS_REG)
17445 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
17447 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
17448 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
17450 (use (match_operand:SI 3 "immediate_operand" "i"))
17451 (use (reg:CC FLAGS_REG))
17452 (use (reg:SI DIRFLAG_REG))
17453 (clobber (match_operand:DI 0 "register_operand" "=S"))
17454 (clobber (match_operand:DI 1 "register_operand" "=D"))
17455 (clobber (match_operand:DI 2 "register_operand" "=c"))]
17458 [(set_attr "type" "str")
17459 (set_attr "mode" "QI")
17460 (set_attr "prefix_rep" "1")])
17462 (define_expand "strlensi"
17463 [(set (match_operand:SI 0 "register_operand" "")
17464 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
17465 (match_operand:QI 2 "immediate_operand" "")
17466 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
17469 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
17475 (define_expand "strlendi"
17476 [(set (match_operand:DI 0 "register_operand" "")
17477 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
17478 (match_operand:QI 2 "immediate_operand" "")
17479 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
17482 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
17488 (define_expand "strlenqi_1"
17489 [(parallel [(set (match_operand 0 "register_operand" "") (match_operand 2 "" ""))
17490 (use (reg:SI DIRFLAG_REG))
17491 (clobber (match_operand 1 "register_operand" ""))
17492 (clobber (reg:CC FLAGS_REG))])]
17496 (define_insn "*strlenqi_1"
17497 [(set (match_operand:SI 0 "register_operand" "=&c")
17498 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
17499 (match_operand:QI 2 "register_operand" "a")
17500 (match_operand:SI 3 "immediate_operand" "i")
17501 (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
17502 (use (reg:SI DIRFLAG_REG))
17503 (clobber (match_operand:SI 1 "register_operand" "=D"))
17504 (clobber (reg:CC FLAGS_REG))]
17507 [(set_attr "type" "str")
17508 (set_attr "mode" "QI")
17509 (set_attr "prefix_rep" "1")])
17511 (define_insn "*strlenqi_rex_1"
17512 [(set (match_operand:DI 0 "register_operand" "=&c")
17513 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
17514 (match_operand:QI 2 "register_operand" "a")
17515 (match_operand:DI 3 "immediate_operand" "i")
17516 (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
17517 (use (reg:SI DIRFLAG_REG))
17518 (clobber (match_operand:DI 1 "register_operand" "=D"))
17519 (clobber (reg:CC FLAGS_REG))]
17522 [(set_attr "type" "str")
17523 (set_attr "mode" "QI")
17524 (set_attr "prefix_rep" "1")])
17526 ;; Peephole optimizations to clean up after cmpstr*. This should be
17527 ;; handled in combine, but it is not currently up to the task.
17528 ;; When used for their truth value, the cmpstr* expanders generate
17537 ;; The intermediate three instructions are unnecessary.
17539 ;; This one handles cmpstr*_nz_1...
17542 (set (reg:CC FLAGS_REG)
17543 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
17544 (mem:BLK (match_operand 5 "register_operand" ""))))
17545 (use (match_operand 6 "register_operand" ""))
17546 (use (match_operand:SI 3 "immediate_operand" ""))
17547 (use (reg:SI DIRFLAG_REG))
17548 (clobber (match_operand 0 "register_operand" ""))
17549 (clobber (match_operand 1 "register_operand" ""))
17550 (clobber (match_operand 2 "register_operand" ""))])
17551 (set (match_operand:QI 7 "register_operand" "")
17552 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
17553 (set (match_operand:QI 8 "register_operand" "")
17554 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
17556 (compare (match_dup 7) (match_dup 8)))
17558 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
17560 (set (reg:CC FLAGS_REG)
17561 (compare:CC (mem:BLK (match_dup 4))
17562 (mem:BLK (match_dup 5))))
17563 (use (match_dup 6))
17564 (use (match_dup 3))
17565 (use (reg:SI DIRFLAG_REG))
17566 (clobber (match_dup 0))
17567 (clobber (match_dup 1))
17568 (clobber (match_dup 2))])]
17571 ;; ...and this one handles cmpstr*_1.
17574 (set (reg:CC FLAGS_REG)
17575 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
17577 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
17578 (mem:BLK (match_operand 5 "register_operand" "")))
17580 (use (match_operand:SI 3 "immediate_operand" ""))
17581 (use (reg:CC FLAGS_REG))
17582 (use (reg:SI DIRFLAG_REG))
17583 (clobber (match_operand 0 "register_operand" ""))
17584 (clobber (match_operand 1 "register_operand" ""))
17585 (clobber (match_operand 2 "register_operand" ""))])
17586 (set (match_operand:QI 7 "register_operand" "")
17587 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
17588 (set (match_operand:QI 8 "register_operand" "")
17589 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
17591 (compare (match_dup 7) (match_dup 8)))
17593 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
17595 (set (reg:CC FLAGS_REG)
17596 (if_then_else:CC (ne (match_dup 6)
17598 (compare:CC (mem:BLK (match_dup 4))
17599 (mem:BLK (match_dup 5)))
17601 (use (match_dup 3))
17602 (use (reg:CC FLAGS_REG))
17603 (use (reg:SI DIRFLAG_REG))
17604 (clobber (match_dup 0))
17605 (clobber (match_dup 1))
17606 (clobber (match_dup 2))])]
17611 ;; Conditional move instructions.
17613 (define_expand "movdicc"
17614 [(set (match_operand:DI 0 "register_operand" "")
17615 (if_then_else:DI (match_operand 1 "comparison_operator" "")
17616 (match_operand:DI 2 "general_operand" "")
17617 (match_operand:DI 3 "general_operand" "")))]
17619 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17621 (define_insn "x86_movdicc_0_m1_rex64"
17622 [(set (match_operand:DI 0 "register_operand" "=r")
17623 (if_then_else:DI (match_operand 1 "ix86_carry_flag_operator" "")
17626 (clobber (reg:CC FLAGS_REG))]
17629 ; Since we don't have the proper number of operands for an alu insn,
17630 ; fill in all the blanks.
17631 [(set_attr "type" "alu")
17632 (set_attr "pent_pair" "pu")
17633 (set_attr "memory" "none")
17634 (set_attr "imm_disp" "false")
17635 (set_attr "mode" "DI")
17636 (set_attr "length_immediate" "0")])
17638 (define_insn "movdicc_c_rex64"
17639 [(set (match_operand:DI 0 "register_operand" "=r,r")
17640 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
17641 [(reg 17) (const_int 0)])
17642 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
17643 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
17644 "TARGET_64BIT && TARGET_CMOVE
17645 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17647 cmov%O2%C1\t{%2, %0|%0, %2}
17648 cmov%O2%c1\t{%3, %0|%0, %3}"
17649 [(set_attr "type" "icmov")
17650 (set_attr "mode" "DI")])
17652 (define_expand "movsicc"
17653 [(set (match_operand:SI 0 "register_operand" "")
17654 (if_then_else:SI (match_operand 1 "comparison_operator" "")
17655 (match_operand:SI 2 "general_operand" "")
17656 (match_operand:SI 3 "general_operand" "")))]
17658 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17660 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
17661 ;; the register first winds up with `sbbl $0,reg', which is also weird.
17662 ;; So just document what we're doing explicitly.
17664 (define_insn "x86_movsicc_0_m1"
17665 [(set (match_operand:SI 0 "register_operand" "=r")
17666 (if_then_else:SI (match_operand 1 "ix86_carry_flag_operator" "")
17669 (clobber (reg:CC FLAGS_REG))]
17672 ; Since we don't have the proper number of operands for an alu insn,
17673 ; fill in all the blanks.
17674 [(set_attr "type" "alu")
17675 (set_attr "pent_pair" "pu")
17676 (set_attr "memory" "none")
17677 (set_attr "imm_disp" "false")
17678 (set_attr "mode" "SI")
17679 (set_attr "length_immediate" "0")])
17681 (define_insn "*movsicc_noc"
17682 [(set (match_operand:SI 0 "register_operand" "=r,r")
17683 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
17684 [(reg 17) (const_int 0)])
17685 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
17686 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
17688 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17690 cmov%O2%C1\t{%2, %0|%0, %2}
17691 cmov%O2%c1\t{%3, %0|%0, %3}"
17692 [(set_attr "type" "icmov")
17693 (set_attr "mode" "SI")])
17695 (define_expand "movhicc"
17696 [(set (match_operand:HI 0 "register_operand" "")
17697 (if_then_else:HI (match_operand 1 "comparison_operator" "")
17698 (match_operand:HI 2 "general_operand" "")
17699 (match_operand:HI 3 "general_operand" "")))]
17700 "TARGET_HIMODE_MATH"
17701 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17703 (define_insn "*movhicc_noc"
17704 [(set (match_operand:HI 0 "register_operand" "=r,r")
17705 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
17706 [(reg 17) (const_int 0)])
17707 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
17708 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
17710 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17712 cmov%O2%C1\t{%2, %0|%0, %2}
17713 cmov%O2%c1\t{%3, %0|%0, %3}"
17714 [(set_attr "type" "icmov")
17715 (set_attr "mode" "HI")])
17717 (define_expand "movqicc"
17718 [(set (match_operand:QI 0 "register_operand" "")
17719 (if_then_else:QI (match_operand 1 "comparison_operator" "")
17720 (match_operand:QI 2 "general_operand" "")
17721 (match_operand:QI 3 "general_operand" "")))]
17722 "TARGET_QIMODE_MATH"
17723 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17725 (define_insn_and_split "*movqicc_noc"
17726 [(set (match_operand:QI 0 "register_operand" "=r,r")
17727 (if_then_else:QI (match_operator 1 "ix86_comparison_operator"
17728 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
17729 (match_operand:QI 2 "register_operand" "r,0")
17730 (match_operand:QI 3 "register_operand" "0,r")))]
17731 "TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
17733 "&& reload_completed"
17734 [(set (match_dup 0)
17735 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
17738 "operands[0] = gen_lowpart (SImode, operands[0]);
17739 operands[2] = gen_lowpart (SImode, operands[2]);
17740 operands[3] = gen_lowpart (SImode, operands[3]);"
17741 [(set_attr "type" "icmov")
17742 (set_attr "mode" "SI")])
17744 (define_expand "movsfcc"
17745 [(set (match_operand:SF 0 "register_operand" "")
17746 (if_then_else:SF (match_operand 1 "comparison_operator" "")
17747 (match_operand:SF 2 "register_operand" "")
17748 (match_operand:SF 3 "register_operand" "")))]
17750 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
17752 (define_insn "*movsfcc_1"
17753 [(set (match_operand:SF 0 "register_operand" "=f#r,f#r,r#f,r#f")
17754 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
17755 [(reg 17) (const_int 0)])
17756 (match_operand:SF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
17757 (match_operand:SF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
17759 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17761 fcmov%F1\t{%2, %0|%0, %2}
17762 fcmov%f1\t{%3, %0|%0, %3}
17763 cmov%O2%C1\t{%2, %0|%0, %2}
17764 cmov%O2%c1\t{%3, %0|%0, %3}"
17765 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
17766 (set_attr "mode" "SF,SF,SI,SI")])
17768 (define_expand "movdfcc"
17769 [(set (match_operand:DF 0 "register_operand" "")
17770 (if_then_else:DF (match_operand 1 "comparison_operator" "")
17771 (match_operand:DF 2 "register_operand" "")
17772 (match_operand:DF 3 "register_operand" "")))]
17774 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
17776 (define_insn "*movdfcc_1"
17777 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,&r#f,&r#f")
17778 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17779 [(reg 17) (const_int 0)])
17780 (match_operand:DF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
17781 (match_operand:DF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
17782 "!TARGET_64BIT && TARGET_CMOVE
17783 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17785 fcmov%F1\t{%2, %0|%0, %2}
17786 fcmov%f1\t{%3, %0|%0, %3}
17789 [(set_attr "type" "fcmov,fcmov,multi,multi")
17790 (set_attr "mode" "DF")])
17792 (define_insn "*movdfcc_1_rex64"
17793 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,r#f,r#f")
17794 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17795 [(reg 17) (const_int 0)])
17796 (match_operand:DF 2 "nonimmediate_operand" "f#r,0#r,rm#f,0#f")
17797 (match_operand:DF 3 "nonimmediate_operand" "0#r,f#r,0#f,rm#f")))]
17798 "TARGET_64BIT && TARGET_CMOVE
17799 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17801 fcmov%F1\t{%2, %0|%0, %2}
17802 fcmov%f1\t{%3, %0|%0, %3}
17803 cmov%O2%C1\t{%2, %0|%0, %2}
17804 cmov%O2%c1\t{%3, %0|%0, %3}"
17805 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
17806 (set_attr "mode" "DF")])
17809 [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
17810 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17811 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
17812 (match_operand:DF 2 "nonimmediate_operand" "")
17813 (match_operand:DF 3 "nonimmediate_operand" "")))]
17814 "!TARGET_64BIT && reload_completed"
17815 [(set (match_dup 2)
17816 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
17820 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
17823 "split_di (operands+2, 1, operands+5, operands+6);
17824 split_di (operands+3, 1, operands+7, operands+8);
17825 split_di (operands, 1, operands+2, operands+3);")
17827 (define_expand "movxfcc"
17828 [(set (match_operand:XF 0 "register_operand" "")
17829 (if_then_else:XF (match_operand 1 "comparison_operator" "")
17830 (match_operand:XF 2 "register_operand" "")
17831 (match_operand:XF 3 "register_operand" "")))]
17833 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
17835 (define_insn "*movxfcc_1"
17836 [(set (match_operand:XF 0 "register_operand" "=f,f")
17837 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
17838 [(reg 17) (const_int 0)])
17839 (match_operand:XF 2 "register_operand" "f,0")
17840 (match_operand:XF 3 "register_operand" "0,f")))]
17843 fcmov%F1\t{%2, %0|%0, %2}
17844 fcmov%f1\t{%3, %0|%0, %3}"
17845 [(set_attr "type" "fcmov")
17846 (set_attr "mode" "XF")])
17848 (define_expand "minsf3"
17850 (set (match_operand:SF 0 "register_operand" "")
17851 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
17852 (match_operand:SF 2 "nonimmediate_operand" ""))
17855 (clobber (reg:CC FLAGS_REG))])]
17859 (define_insn "*minsf"
17860 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
17861 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
17862 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
17865 (clobber (reg:CC FLAGS_REG))]
17866 "TARGET_SSE && TARGET_IEEE_FP"
17869 (define_insn "*minsf_nonieee"
17870 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
17871 (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
17872 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
17875 (clobber (reg:CC FLAGS_REG))]
17876 "TARGET_SSE && !TARGET_IEEE_FP
17877 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17881 [(set (match_operand:SF 0 "register_operand" "")
17882 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
17883 (match_operand:SF 2 "nonimmediate_operand" ""))
17884 (match_operand:SF 3 "register_operand" "")
17885 (match_operand:SF 4 "nonimmediate_operand" "")))
17886 (clobber (reg:CC FLAGS_REG))]
17887 "SSE_REG_P (operands[0]) && reload_completed
17888 && ((operands_match_p (operands[1], operands[3])
17889 && operands_match_p (operands[2], operands[4]))
17890 || (operands_match_p (operands[1], operands[4])
17891 && operands_match_p (operands[2], operands[3])))"
17892 [(set (match_dup 0)
17893 (if_then_else:SF (lt (match_dup 1)
17898 ;; Conditional addition patterns
17899 (define_expand "addqicc"
17900 [(match_operand:QI 0 "register_operand" "")
17901 (match_operand 1 "comparison_operator" "")
17902 (match_operand:QI 2 "register_operand" "")
17903 (match_operand:QI 3 "const_int_operand" "")]
17905 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17907 (define_expand "addhicc"
17908 [(match_operand:HI 0 "register_operand" "")
17909 (match_operand 1 "comparison_operator" "")
17910 (match_operand:HI 2 "register_operand" "")
17911 (match_operand:HI 3 "const_int_operand" "")]
17913 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17915 (define_expand "addsicc"
17916 [(match_operand:SI 0 "register_operand" "")
17917 (match_operand 1 "comparison_operator" "")
17918 (match_operand:SI 2 "register_operand" "")
17919 (match_operand:SI 3 "const_int_operand" "")]
17921 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17923 (define_expand "adddicc"
17924 [(match_operand:DI 0 "register_operand" "")
17925 (match_operand 1 "comparison_operator" "")
17926 (match_operand:DI 2 "register_operand" "")
17927 (match_operand:DI 3 "const_int_operand" "")]
17929 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17931 ;; We can't represent the LT test directly. Do this by swapping the operands.
17934 [(set (match_operand:SF 0 "fp_register_operand" "")
17935 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
17936 (match_operand:SF 2 "register_operand" ""))
17937 (match_operand:SF 3 "register_operand" "")
17938 (match_operand:SF 4 "register_operand" "")))
17939 (clobber (reg:CC FLAGS_REG))]
17941 && ((operands_match_p (operands[1], operands[3])
17942 && operands_match_p (operands[2], operands[4]))
17943 || (operands_match_p (operands[1], operands[4])
17944 && operands_match_p (operands[2], operands[3])))"
17945 [(set (reg:CCFP FLAGS_REG)
17946 (compare:CCFP (match_dup 2)
17949 (if_then_else:SF (ge (reg:CCFP FLAGS_REG) (const_int 0))
17953 (define_insn "*minsf_sse"
17954 [(set (match_operand:SF 0 "register_operand" "=x")
17955 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
17956 (match_operand:SF 2 "nonimmediate_operand" "xm"))
17959 "TARGET_SSE && reload_completed"
17960 "minss\t{%2, %0|%0, %2}"
17961 [(set_attr "type" "sse")
17962 (set_attr "mode" "SF")])
17964 (define_expand "mindf3"
17966 (set (match_operand:DF 0 "register_operand" "")
17967 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17968 (match_operand:DF 2 "nonimmediate_operand" ""))
17971 (clobber (reg:CC FLAGS_REG))])]
17972 "TARGET_SSE2 && TARGET_SSE_MATH"
17975 (define_insn "*mindf"
17976 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
17977 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
17978 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
17981 (clobber (reg:CC FLAGS_REG))]
17982 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
17985 (define_insn "*mindf_nonieee"
17986 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
17987 (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
17988 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
17991 (clobber (reg:CC FLAGS_REG))]
17992 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
17993 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17997 [(set (match_operand:DF 0 "register_operand" "")
17998 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17999 (match_operand:DF 2 "nonimmediate_operand" ""))
18000 (match_operand:DF 3 "register_operand" "")
18001 (match_operand:DF 4 "nonimmediate_operand" "")))
18002 (clobber (reg:CC FLAGS_REG))]
18003 "SSE_REG_P (operands[0]) && reload_completed
18004 && ((operands_match_p (operands[1], operands[3])
18005 && operands_match_p (operands[2], operands[4]))
18006 || (operands_match_p (operands[1], operands[4])
18007 && operands_match_p (operands[2], operands[3])))"
18008 [(set (match_dup 0)
18009 (if_then_else:DF (lt (match_dup 1)
18014 ;; We can't represent the LT test directly. Do this by swapping the operands.
18016 [(set (match_operand:DF 0 "fp_register_operand" "")
18017 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
18018 (match_operand:DF 2 "register_operand" ""))
18019 (match_operand:DF 3 "register_operand" "")
18020 (match_operand:DF 4 "register_operand" "")))
18021 (clobber (reg:CC FLAGS_REG))]
18023 && ((operands_match_p (operands[1], operands[3])
18024 && operands_match_p (operands[2], operands[4]))
18025 || (operands_match_p (operands[1], operands[4])
18026 && operands_match_p (operands[2], operands[3])))"
18027 [(set (reg:CCFP FLAGS_REG)
18028 (compare:CCFP (match_dup 2)
18031 (if_then_else:DF (ge (reg:CCFP FLAGS_REG) (const_int 0))
18035 (define_insn "*mindf_sse"
18036 [(set (match_operand:DF 0 "register_operand" "=Y")
18037 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
18038 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
18041 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
18042 "minsd\t{%2, %0|%0, %2}"
18043 [(set_attr "type" "sse")
18044 (set_attr "mode" "DF")])
18046 (define_expand "maxsf3"
18048 (set (match_operand:SF 0 "register_operand" "")
18049 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
18050 (match_operand:SF 2 "nonimmediate_operand" ""))
18053 (clobber (reg:CC FLAGS_REG))])]
18057 (define_insn "*maxsf"
18058 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
18059 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
18060 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
18063 (clobber (reg:CC FLAGS_REG))]
18064 "TARGET_SSE && TARGET_IEEE_FP"
18067 (define_insn "*maxsf_nonieee"
18068 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
18069 (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
18070 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
18073 (clobber (reg:CC FLAGS_REG))]
18074 "TARGET_SSE && !TARGET_IEEE_FP
18075 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18079 [(set (match_operand:SF 0 "register_operand" "")
18080 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
18081 (match_operand:SF 2 "nonimmediate_operand" ""))
18082 (match_operand:SF 3 "register_operand" "")
18083 (match_operand:SF 4 "nonimmediate_operand" "")))
18084 (clobber (reg:CC FLAGS_REG))]
18085 "SSE_REG_P (operands[0]) && reload_completed
18086 && ((operands_match_p (operands[1], operands[3])
18087 && operands_match_p (operands[2], operands[4]))
18088 || (operands_match_p (operands[1], operands[4])
18089 && operands_match_p (operands[2], operands[3])))"
18090 [(set (match_dup 0)
18091 (if_then_else:SF (gt (match_dup 1)
18097 [(set (match_operand:SF 0 "fp_register_operand" "")
18098 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
18099 (match_operand:SF 2 "register_operand" ""))
18100 (match_operand:SF 3 "register_operand" "")
18101 (match_operand:SF 4 "register_operand" "")))
18102 (clobber (reg:CC FLAGS_REG))]
18104 && ((operands_match_p (operands[1], operands[3])
18105 && operands_match_p (operands[2], operands[4]))
18106 || (operands_match_p (operands[1], operands[4])
18107 && operands_match_p (operands[2], operands[3])))"
18108 [(set (reg:CCFP FLAGS_REG)
18109 (compare:CCFP (match_dup 1)
18112 (if_then_else:SF (gt (reg:CCFP FLAGS_REG) (const_int 0))
18116 (define_insn "*maxsf_sse"
18117 [(set (match_operand:SF 0 "register_operand" "=x")
18118 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
18119 (match_operand:SF 2 "nonimmediate_operand" "xm"))
18122 "TARGET_SSE && reload_completed"
18123 "maxss\t{%2, %0|%0, %2}"
18124 [(set_attr "type" "sse")
18125 (set_attr "mode" "SF")])
18127 (define_expand "maxdf3"
18129 (set (match_operand:DF 0 "register_operand" "")
18130 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
18131 (match_operand:DF 2 "nonimmediate_operand" ""))
18134 (clobber (reg:CC FLAGS_REG))])]
18135 "TARGET_SSE2 && TARGET_SSE_MATH"
18138 (define_insn "*maxdf"
18139 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
18140 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
18141 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
18144 (clobber (reg:CC FLAGS_REG))]
18145 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
18148 (define_insn "*maxdf_nonieee"
18149 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
18150 (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
18151 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
18154 (clobber (reg:CC FLAGS_REG))]
18155 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
18156 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18160 [(set (match_operand:DF 0 "register_operand" "")
18161 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
18162 (match_operand:DF 2 "nonimmediate_operand" ""))
18163 (match_operand:DF 3 "register_operand" "")
18164 (match_operand:DF 4 "nonimmediate_operand" "")))
18165 (clobber (reg:CC FLAGS_REG))]
18166 "SSE_REG_P (operands[0]) && reload_completed
18167 && ((operands_match_p (operands[1], operands[3])
18168 && operands_match_p (operands[2], operands[4]))
18169 || (operands_match_p (operands[1], operands[4])
18170 && operands_match_p (operands[2], operands[3])))"
18171 [(set (match_dup 0)
18172 (if_then_else:DF (gt (match_dup 1)
18178 [(set (match_operand:DF 0 "fp_register_operand" "")
18179 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
18180 (match_operand:DF 2 "register_operand" ""))
18181 (match_operand:DF 3 "register_operand" "")
18182 (match_operand:DF 4 "register_operand" "")))
18183 (clobber (reg:CC FLAGS_REG))]
18185 && ((operands_match_p (operands[1], operands[3])
18186 && operands_match_p (operands[2], operands[4]))
18187 || (operands_match_p (operands[1], operands[4])
18188 && operands_match_p (operands[2], operands[3])))"
18189 [(set (reg:CCFP FLAGS_REG)
18190 (compare:CCFP (match_dup 1)
18193 (if_then_else:DF (gt (reg:CCFP FLAGS_REG) (const_int 0))
18197 (define_insn "*maxdf_sse"
18198 [(set (match_operand:DF 0 "register_operand" "=Y")
18199 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
18200 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
18203 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
18204 "maxsd\t{%2, %0|%0, %2}"
18205 [(set_attr "type" "sse")
18206 (set_attr "mode" "DF")])
18208 ;; Misc patterns (?)
18210 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
18211 ;; Otherwise there will be nothing to keep
18213 ;; [(set (reg ebp) (reg esp))]
18214 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
18215 ;; (clobber (eflags)]
18216 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
18218 ;; in proper program order.
18219 (define_insn "pro_epilogue_adjust_stack_1"
18220 [(set (match_operand:SI 0 "register_operand" "=r,r")
18221 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
18222 (match_operand:SI 2 "immediate_operand" "i,i")))
18223 (clobber (reg:CC FLAGS_REG))
18224 (clobber (mem:BLK (scratch)))]
18227 switch (get_attr_type (insn))
18230 return "mov{l}\t{%1, %0|%0, %1}";
18233 if (GET_CODE (operands[2]) == CONST_INT
18234 && (INTVAL (operands[2]) == 128
18235 || (INTVAL (operands[2]) < 0
18236 && INTVAL (operands[2]) != -128)))
18238 operands[2] = GEN_INT (-INTVAL (operands[2]));
18239 return "sub{l}\t{%2, %0|%0, %2}";
18241 return "add{l}\t{%2, %0|%0, %2}";
18244 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
18245 return "lea{l}\t{%a2, %0|%0, %a2}";
18251 [(set (attr "type")
18252 (cond [(eq_attr "alternative" "0")
18253 (const_string "alu")
18254 (match_operand:SI 2 "const0_operand" "")
18255 (const_string "imov")
18257 (const_string "lea")))
18258 (set_attr "mode" "SI")])
18260 (define_insn "pro_epilogue_adjust_stack_rex64"
18261 [(set (match_operand:DI 0 "register_operand" "=r,r")
18262 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
18263 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
18264 (clobber (reg:CC FLAGS_REG))
18265 (clobber (mem:BLK (scratch)))]
18268 switch (get_attr_type (insn))
18271 return "mov{q}\t{%1, %0|%0, %1}";
18274 if (GET_CODE (operands[2]) == CONST_INT
18275 /* Avoid overflows. */
18276 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
18277 && (INTVAL (operands[2]) == 128
18278 || (INTVAL (operands[2]) < 0
18279 && INTVAL (operands[2]) != -128)))
18281 operands[2] = GEN_INT (-INTVAL (operands[2]));
18282 return "sub{q}\t{%2, %0|%0, %2}";
18284 return "add{q}\t{%2, %0|%0, %2}";
18287 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
18288 return "lea{q}\t{%a2, %0|%0, %a2}";
18294 [(set (attr "type")
18295 (cond [(eq_attr "alternative" "0")
18296 (const_string "alu")
18297 (match_operand:DI 2 "const0_operand" "")
18298 (const_string "imov")
18300 (const_string "lea")))
18301 (set_attr "mode" "DI")])
18303 (define_insn "pro_epilogue_adjust_stack_rex64_2"
18304 [(set (match_operand:DI 0 "register_operand" "=r,r")
18305 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
18306 (match_operand:DI 3 "immediate_operand" "i,i")))
18307 (use (match_operand:DI 2 "register_operand" "r,r"))
18308 (clobber (reg:CC FLAGS_REG))
18309 (clobber (mem:BLK (scratch)))]
18312 switch (get_attr_type (insn))
18315 return "add{q}\t{%2, %0|%0, %2}";
18318 operands[2] = gen_rtx_PLUS (DImode, operands[1], operands[2]);
18319 return "lea{q}\t{%a2, %0|%0, %a2}";
18325 [(set_attr "type" "alu,lea")
18326 (set_attr "mode" "DI")])
18328 ;; Placeholder for the conditional moves. This one is split either to SSE
18329 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
18330 ;; fact is that compares supported by the cmp??ss instructions are exactly
18331 ;; swapped of those supported by cmove sequence.
18332 ;; The EQ/NE comparisons also needs bit care, since they are not directly
18333 ;; supported by i387 comparisons and we do need to emit two conditional moves
18336 (define_insn "sse_movsfcc"
18337 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
18338 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
18339 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
18340 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
18341 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
18342 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
18343 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
18344 (clobber (reg:CC FLAGS_REG))]
18346 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
18347 /* Avoid combine from being smart and converting min/max
18348 instruction patterns into conditional moves. */
18349 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
18350 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
18351 || !rtx_equal_p (operands[4], operands[2])
18352 || !rtx_equal_p (operands[5], operands[3]))
18353 && (!TARGET_IEEE_FP
18354 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
18357 (define_insn "sse_movsfcc_eq"
18358 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
18359 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
18360 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
18361 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
18362 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
18363 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
18364 (clobber (reg:CC FLAGS_REG))]
18366 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
18369 (define_insn "sse_movdfcc"
18370 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?f#Yr,?f#Yr,?r#Yf,?r#Yf,?r#Yf,?r#Yf")
18371 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
18372 [(match_operand:DF 4 "nonimmediate_operand" "0#fY,Y#fY,f#Y,f#Y,Ym#f,Ym#f,f#Y,f#Y,Ym#f,Ym#f")
18373 (match_operand:DF 5 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,f#Y,Y#f,Y#f,f#Y,f#Y,Y#f,Y#f")])
18374 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY")
18375 (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY")))
18376 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
18377 (clobber (reg:CC FLAGS_REG))]
18379 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
18380 /* Avoid combine from being smart and converting min/max
18381 instruction patterns into conditional moves. */
18382 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
18383 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
18384 || !rtx_equal_p (operands[4], operands[2])
18385 || !rtx_equal_p (operands[5], operands[3]))
18386 && (!TARGET_IEEE_FP
18387 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
18390 (define_insn "sse_movdfcc_eq"
18391 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?r#Yf,?r#Yf")
18392 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fY,Y#fY,f#Y,Ym#f,f#Y,Ym#f")
18393 (match_operand:DF 4 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,Y#f,f#Y,Y#f"))
18394 (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY")
18395 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY")))
18396 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
18397 (clobber (reg:CC FLAGS_REG))]
18399 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
18402 ;; For non-sse moves just expand the usual cmove sequence.
18404 [(set (match_operand 0 "register_operand" "")
18405 (if_then_else (match_operator 1 "comparison_operator"
18406 [(match_operand 4 "nonimmediate_operand" "")
18407 (match_operand 5 "register_operand" "")])
18408 (match_operand 2 "nonimmediate_operand" "")
18409 (match_operand 3 "nonimmediate_operand" "")))
18410 (clobber (match_operand 6 "" ""))
18411 (clobber (reg:CC FLAGS_REG))]
18412 "!SSE_REG_P (operands[0]) && reload_completed
18413 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
18416 ix86_compare_op0 = operands[5];
18417 ix86_compare_op1 = operands[4];
18418 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
18419 VOIDmode, operands[5], operands[4]);
18420 ix86_expand_fp_movcc (operands);
18424 ;; Split SSE based conditional move into sequence:
18425 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
18426 ;; and op2, op0 - zero op2 if comparison was false
18427 ;; nand op0, op3 - load op3 to op0 if comparison was false
18428 ;; or op2, op0 - get the nonzero one into the result.
18430 [(set (match_operand:SF 0 "register_operand" "")
18431 (if_then_else (match_operator:SF 1 "sse_comparison_operator"
18432 [(match_operand:SF 4 "register_operand" "")
18433 (match_operand:SF 5 "nonimmediate_operand" "")])
18434 (match_operand:SF 2 "register_operand" "")
18435 (match_operand:SF 3 "register_operand" "")))
18436 (clobber (match_operand 6 "" ""))
18437 (clobber (reg:CC FLAGS_REG))]
18438 "SSE_REG_P (operands[0]) && reload_completed"
18439 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
18440 (set (match_dup 2) (and:V4SF (match_dup 2)
18442 (set (match_dup 8) (and:V4SF (not:V4SF (match_dup 8))
18444 (set (match_dup 0) (ior:V4SF (match_dup 6)
18447 /* If op2 == op3, op3 would be clobbered before it is used. */
18448 if (operands_match_p (operands[2], operands[3]))
18450 emit_move_insn (operands[0], operands[2]);
18454 PUT_MODE (operands[1], GET_MODE (operands[0]));
18455 if (operands_match_p (operands[0], operands[4]))
18456 operands[6] = operands[4], operands[7] = operands[2];
18458 operands[6] = operands[2], operands[7] = operands[4];
18459 operands[0] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
18460 operands[2] = simplify_gen_subreg (V4SFmode, operands[2], SFmode, 0);
18461 operands[3] = simplify_gen_subreg (V4SFmode, operands[3], SFmode, 0);
18462 operands[8] = simplify_gen_subreg (V4SFmode, operands[4], SFmode, 0);
18463 operands[6] = simplify_gen_subreg (V4SFmode, operands[6], SFmode, 0);
18464 operands[7] = simplify_gen_subreg (V4SFmode, operands[7], SFmode, 0);
18468 [(set (match_operand:DF 0 "register_operand" "")
18469 (if_then_else (match_operator:DF 1 "sse_comparison_operator"
18470 [(match_operand:DF 4 "register_operand" "")
18471 (match_operand:DF 5 "nonimmediate_operand" "")])
18472 (match_operand:DF 2 "register_operand" "")
18473 (match_operand:DF 3 "register_operand" "")))
18474 (clobber (match_operand 6 "" ""))
18475 (clobber (reg:CC FLAGS_REG))]
18476 "SSE_REG_P (operands[0]) && reload_completed"
18477 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
18478 (set (match_dup 2) (and:V2DF (match_dup 2)
18480 (set (match_dup 8) (and:V2DF (not:V2DF (match_dup 8))
18482 (set (match_dup 0) (ior:V2DF (match_dup 6)
18485 if (GET_MODE (operands[2]) == DFmode
18486 && TARGET_SSE_PARTIAL_REGS && !optimize_size)
18488 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
18489 emit_insn (gen_sse2_unpcklpd (op, op, op));
18490 op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
18491 emit_insn (gen_sse2_unpcklpd (op, op, op));
18494 /* If op2 == op3, op3 would be clobbered before it is used. */
18495 if (operands_match_p (operands[2], operands[3]))
18497 emit_move_insn (operands[0], operands[2]);
18501 PUT_MODE (operands[1], GET_MODE (operands[0]));
18502 if (operands_match_p (operands[0], operands[4]))
18503 operands[6] = operands[4], operands[7] = operands[2];
18505 operands[6] = operands[2], operands[7] = operands[4];
18506 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
18507 operands[2] = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
18508 operands[3] = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
18509 operands[8] = simplify_gen_subreg (V2DFmode, operands[4], DFmode, 0);
18510 operands[6] = simplify_gen_subreg (V2DFmode, operands[6], DFmode, 0);
18511 operands[7] = simplify_gen_subreg (V2DFmode, operands[7], DFmode, 0);
18514 ;; Special case of conditional move we can handle effectively.
18515 ;; Do not brother with the integer/floating point case, since these are
18516 ;; bot considerably slower, unlike in the generic case.
18517 (define_insn "*sse_movsfcc_const0_1"
18518 [(set (match_operand:SF 0 "register_operand" "=&x")
18519 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
18520 [(match_operand:SF 4 "register_operand" "0")
18521 (match_operand:SF 5 "nonimmediate_operand" "xm")])
18522 (match_operand:SF 2 "register_operand" "x")
18523 (match_operand:SF 3 "const0_operand" "X")))]
18527 (define_insn "*sse_movsfcc_const0_2"
18528 [(set (match_operand:SF 0 "register_operand" "=&x")
18529 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
18530 [(match_operand:SF 4 "register_operand" "0")
18531 (match_operand:SF 5 "nonimmediate_operand" "xm")])
18532 (match_operand:SF 2 "const0_operand" "X")
18533 (match_operand:SF 3 "register_operand" "x")))]
18537 (define_insn "*sse_movsfcc_const0_3"
18538 [(set (match_operand:SF 0 "register_operand" "=&x")
18539 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
18540 [(match_operand:SF 4 "nonimmediate_operand" "xm")
18541 (match_operand:SF 5 "register_operand" "0")])
18542 (match_operand:SF 2 "register_operand" "x")
18543 (match_operand:SF 3 "const0_operand" "X")))]
18547 (define_insn "*sse_movsfcc_const0_4"
18548 [(set (match_operand:SF 0 "register_operand" "=&x")
18549 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
18550 [(match_operand:SF 4 "nonimmediate_operand" "xm")
18551 (match_operand:SF 5 "register_operand" "0")])
18552 (match_operand:SF 2 "const0_operand" "X")
18553 (match_operand:SF 3 "register_operand" "x")))]
18557 (define_insn "*sse_movdfcc_const0_1"
18558 [(set (match_operand:DF 0 "register_operand" "=&Y")
18559 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
18560 [(match_operand:DF 4 "register_operand" "0")
18561 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
18562 (match_operand:DF 2 "register_operand" "Y")
18563 (match_operand:DF 3 "const0_operand" "X")))]
18567 (define_insn "*sse_movdfcc_const0_2"
18568 [(set (match_operand:DF 0 "register_operand" "=&Y")
18569 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
18570 [(match_operand:DF 4 "register_operand" "0")
18571 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
18572 (match_operand:DF 2 "const0_operand" "X")
18573 (match_operand:DF 3 "register_operand" "Y")))]
18577 (define_insn "*sse_movdfcc_const0_3"
18578 [(set (match_operand:DF 0 "register_operand" "=&Y")
18579 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
18580 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
18581 (match_operand:DF 5 "register_operand" "0")])
18582 (match_operand:DF 2 "register_operand" "Y")
18583 (match_operand:DF 3 "const0_operand" "X")))]
18587 (define_insn "*sse_movdfcc_const0_4"
18588 [(set (match_operand:DF 0 "register_operand" "=&Y")
18589 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
18590 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
18591 (match_operand:DF 5 "register_operand" "0")])
18592 (match_operand:DF 2 "const0_operand" "X")
18593 (match_operand:DF 3 "register_operand" "Y")))]
18598 [(set (match_operand:SF 0 "register_operand" "")
18599 (if_then_else (match_operator 1 "comparison_operator"
18600 [(match_operand:SF 4 "nonimmediate_operand" "")
18601 (match_operand:SF 5 "nonimmediate_operand" "")])
18602 (match_operand:SF 2 "nonmemory_operand" "")
18603 (match_operand:SF 3 "nonmemory_operand" "")))]
18604 "SSE_REG_P (operands[0]) && reload_completed
18605 && (const0_operand (operands[2], GET_MODE (operands[0]))
18606 || const0_operand (operands[3], GET_MODE (operands[0])))"
18607 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
18608 (set (match_dup 8) (and:V4SF (match_dup 6) (match_dup 7)))]
18610 PUT_MODE (operands[1], GET_MODE (operands[0]));
18611 if (!sse_comparison_operator (operands[1], VOIDmode)
18612 || !rtx_equal_p (operands[0], operands[4]))
18614 rtx tmp = operands[5];
18615 operands[5] = operands[4];
18617 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
18619 if (!rtx_equal_p (operands[0], operands[4]))
18621 operands[8] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
18622 if (const0_operand (operands[2], GET_MODE (operands[2])))
18624 operands[7] = operands[3];
18625 operands[6] = gen_rtx_NOT (V4SFmode, operands[8]);
18629 operands[7] = operands[2];
18630 operands[6] = operands[8];
18632 operands[7] = simplify_gen_subreg (V4SFmode, operands[7], SFmode, 0);
18636 [(set (match_operand:DF 0 "register_operand" "")
18637 (if_then_else (match_operator 1 "comparison_operator"
18638 [(match_operand:DF 4 "nonimmediate_operand" "")
18639 (match_operand:DF 5 "nonimmediate_operand" "")])
18640 (match_operand:DF 2 "nonmemory_operand" "")
18641 (match_operand:DF 3 "nonmemory_operand" "")))]
18642 "SSE_REG_P (operands[0]) && reload_completed
18643 && (const0_operand (operands[2], GET_MODE (operands[0]))
18644 || const0_operand (operands[3], GET_MODE (operands[0])))"
18645 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
18646 (set (match_dup 8) (and:V2DF (match_dup 6) (match_dup 7)))]
18648 if (TARGET_SSE_PARTIAL_REGS && !optimize_size
18649 && GET_MODE (operands[2]) == DFmode)
18651 if (REG_P (operands[2]))
18653 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
18654 emit_insn (gen_sse2_unpcklpd (op, op, op));
18656 if (REG_P (operands[3]))
18658 rtx op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
18659 emit_insn (gen_sse2_unpcklpd (op, op, op));
18662 PUT_MODE (operands[1], GET_MODE (operands[0]));
18663 if (!sse_comparison_operator (operands[1], VOIDmode)
18664 || !rtx_equal_p (operands[0], operands[4]))
18666 rtx tmp = operands[5];
18667 operands[5] = operands[4];
18669 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
18671 if (!rtx_equal_p (operands[0], operands[4]))
18673 operands[8] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
18674 if (const0_operand (operands[2], GET_MODE (operands[2])))
18676 operands[7] = operands[3];
18677 operands[6] = gen_rtx_NOT (V2DFmode, operands[8]);
18681 operands[7] = operands[2];
18682 operands[6] = operands[8];
18684 operands[7] = simplify_gen_subreg (V2DFmode, operands[7], DFmode, 0);
18687 (define_expand "allocate_stack_worker"
18688 [(match_operand:SI 0 "register_operand" "")]
18689 "TARGET_STACK_PROBE"
18691 if (reload_completed)
18694 emit_insn (gen_allocate_stack_worker_rex64_postreload (operands[0]));
18696 emit_insn (gen_allocate_stack_worker_postreload (operands[0]));
18701 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
18703 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
18708 (define_insn "allocate_stack_worker_1"
18709 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "a")]
18710 UNSPECV_STACK_PROBE)
18711 (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0)))
18712 (clobber (match_scratch:SI 1 "=0"))
18713 (clobber (reg:CC FLAGS_REG))]
18714 "!TARGET_64BIT && TARGET_STACK_PROBE"
18716 [(set_attr "type" "multi")
18717 (set_attr "length" "5")])
18719 (define_expand "allocate_stack_worker_postreload"
18720 [(parallel [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "a")]
18721 UNSPECV_STACK_PROBE)
18722 (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0)))
18723 (clobber (match_dup 0))
18724 (clobber (reg:CC FLAGS_REG))])]
18728 (define_insn "allocate_stack_worker_rex64"
18729 [(unspec_volatile:DI [(match_operand:DI 0 "register_operand" "a")]
18730 UNSPECV_STACK_PROBE)
18731 (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 0)))
18732 (clobber (match_scratch:DI 1 "=0"))
18733 (clobber (reg:CC FLAGS_REG))]
18734 "TARGET_64BIT && TARGET_STACK_PROBE"
18736 [(set_attr "type" "multi")
18737 (set_attr "length" "5")])
18739 (define_expand "allocate_stack_worker_rex64_postreload"
18740 [(parallel [(unspec_volatile:DI [(match_operand:DI 0 "register_operand" "a")]
18741 UNSPECV_STACK_PROBE)
18742 (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 0)))
18743 (clobber (match_dup 0))
18744 (clobber (reg:CC FLAGS_REG))])]
18748 (define_expand "allocate_stack"
18749 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
18750 (minus:SI (reg:SI SP_REG)
18751 (match_operand:SI 1 "general_operand" "")))
18752 (clobber (reg:CC FLAGS_REG))])
18753 (parallel [(set (reg:SI SP_REG)
18754 (minus:SI (reg:SI SP_REG) (match_dup 1)))
18755 (clobber (reg:CC FLAGS_REG))])]
18756 "TARGET_STACK_PROBE"
18758 #ifdef CHECK_STACK_LIMIT
18759 if (GET_CODE (operands[1]) == CONST_INT
18760 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
18761 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
18765 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
18768 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
18772 (define_expand "builtin_setjmp_receiver"
18773 [(label_ref (match_operand 0 "" ""))]
18774 "!TARGET_64BIT && flag_pic"
18776 emit_insn (gen_set_got (pic_offset_table_rtx));
18780 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
18783 [(set (match_operand 0 "register_operand" "")
18784 (match_operator 3 "promotable_binary_operator"
18785 [(match_operand 1 "register_operand" "")
18786 (match_operand 2 "aligned_operand" "")]))
18787 (clobber (reg:CC FLAGS_REG))]
18788 "! TARGET_PARTIAL_REG_STALL && reload_completed
18789 && ((GET_MODE (operands[0]) == HImode
18790 && ((!optimize_size && !TARGET_FAST_PREFIX)
18791 || GET_CODE (operands[2]) != CONST_INT
18792 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
18793 || (GET_MODE (operands[0]) == QImode
18794 && (TARGET_PROMOTE_QImode || optimize_size)))"
18795 [(parallel [(set (match_dup 0)
18796 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
18797 (clobber (reg:CC FLAGS_REG))])]
18798 "operands[0] = gen_lowpart (SImode, operands[0]);
18799 operands[1] = gen_lowpart (SImode, operands[1]);
18800 if (GET_CODE (operands[3]) != ASHIFT)
18801 operands[2] = gen_lowpart (SImode, operands[2]);
18802 PUT_MODE (operands[3], SImode);")
18804 ; Promote the QImode tests, as i386 has encoding of the AND
18805 ; instruction with 32-bit sign-extended immediate and thus the
18806 ; instruction size is unchanged, except in the %eax case for
18807 ; which it is increased by one byte, hence the ! optimize_size.
18810 (compare (and (match_operand 1 "aligned_operand" "")
18811 (match_operand 2 "const_int_operand" ""))
18813 (set (match_operand 0 "register_operand" "")
18814 (and (match_dup 1) (match_dup 2)))]
18815 "! TARGET_PARTIAL_REG_STALL && reload_completed
18816 /* Ensure that the operand will remain sign-extended immediate. */
18817 && ix86_match_ccmode (insn, INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode)
18819 && ((GET_MODE (operands[0]) == HImode && ! TARGET_FAST_PREFIX)
18820 || (GET_MODE (operands[0]) == QImode && TARGET_PROMOTE_QImode))"
18821 [(parallel [(set (reg:CCNO FLAGS_REG)
18822 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
18825 (and:SI (match_dup 1) (match_dup 2)))])]
18827 = gen_int_mode (INTVAL (operands[2])
18828 & GET_MODE_MASK (GET_MODE (operands[0])),
18830 operands[0] = gen_lowpart (SImode, operands[0]);
18831 operands[1] = gen_lowpart (SImode, operands[1]);")
18833 ; Don't promote the QImode tests, as i386 doesn't have encoding of
18834 ; the TEST instruction with 32-bit sign-extended immediate and thus
18835 ; the instruction size would at least double, which is not what we
18836 ; want even with ! optimize_size.
18839 (compare (and (match_operand:HI 0 "aligned_operand" "")
18840 (match_operand:HI 1 "const_int_operand" ""))
18842 "! TARGET_PARTIAL_REG_STALL && reload_completed
18843 /* Ensure that the operand will remain sign-extended immediate. */
18844 && ix86_match_ccmode (insn, INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)
18845 && ! TARGET_FAST_PREFIX
18846 && ! optimize_size"
18847 [(set (reg:CCNO FLAGS_REG)
18848 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
18851 = gen_int_mode (INTVAL (operands[1])
18852 & GET_MODE_MASK (GET_MODE (operands[0])),
18854 operands[0] = gen_lowpart (SImode, operands[0]);")
18857 [(set (match_operand 0 "register_operand" "")
18858 (neg (match_operand 1 "register_operand" "")))
18859 (clobber (reg:CC FLAGS_REG))]
18860 "! TARGET_PARTIAL_REG_STALL && reload_completed
18861 && (GET_MODE (operands[0]) == HImode
18862 || (GET_MODE (operands[0]) == QImode
18863 && (TARGET_PROMOTE_QImode || optimize_size)))"
18864 [(parallel [(set (match_dup 0)
18865 (neg:SI (match_dup 1)))
18866 (clobber (reg:CC FLAGS_REG))])]
18867 "operands[0] = gen_lowpart (SImode, operands[0]);
18868 operands[1] = gen_lowpart (SImode, operands[1]);")
18871 [(set (match_operand 0 "register_operand" "")
18872 (not (match_operand 1 "register_operand" "")))]
18873 "! TARGET_PARTIAL_REG_STALL && reload_completed
18874 && (GET_MODE (operands[0]) == HImode
18875 || (GET_MODE (operands[0]) == QImode
18876 && (TARGET_PROMOTE_QImode || optimize_size)))"
18877 [(set (match_dup 0)
18878 (not:SI (match_dup 1)))]
18879 "operands[0] = gen_lowpart (SImode, operands[0]);
18880 operands[1] = gen_lowpart (SImode, operands[1]);")
18883 [(set (match_operand 0 "register_operand" "")
18884 (if_then_else (match_operator 1 "comparison_operator"
18885 [(reg 17) (const_int 0)])
18886 (match_operand 2 "register_operand" "")
18887 (match_operand 3 "register_operand" "")))]
18888 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
18889 && (GET_MODE (operands[0]) == HImode
18890 || (GET_MODE (operands[0]) == QImode
18891 && (TARGET_PROMOTE_QImode || optimize_size)))"
18892 [(set (match_dup 0)
18893 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
18894 "operands[0] = gen_lowpart (SImode, operands[0]);
18895 operands[2] = gen_lowpart (SImode, operands[2]);
18896 operands[3] = gen_lowpart (SImode, operands[3]);")
18899 ;; RTL Peephole optimizations, run before sched2. These primarily look to
18900 ;; transform a complex memory operation into two memory to register operations.
18902 ;; Don't push memory operands
18904 [(set (match_operand:SI 0 "push_operand" "")
18905 (match_operand:SI 1 "memory_operand" ""))
18906 (match_scratch:SI 2 "r")]
18907 "! optimize_size && ! TARGET_PUSH_MEMORY"
18908 [(set (match_dup 2) (match_dup 1))
18909 (set (match_dup 0) (match_dup 2))]
18913 [(set (match_operand:DI 0 "push_operand" "")
18914 (match_operand:DI 1 "memory_operand" ""))
18915 (match_scratch:DI 2 "r")]
18916 "! optimize_size && ! TARGET_PUSH_MEMORY"
18917 [(set (match_dup 2) (match_dup 1))
18918 (set (match_dup 0) (match_dup 2))]
18921 ;; We need to handle SFmode only, because DFmode and XFmode is split to
18924 [(set (match_operand:SF 0 "push_operand" "")
18925 (match_operand:SF 1 "memory_operand" ""))
18926 (match_scratch:SF 2 "r")]
18927 "! optimize_size && ! TARGET_PUSH_MEMORY"
18928 [(set (match_dup 2) (match_dup 1))
18929 (set (match_dup 0) (match_dup 2))]
18933 [(set (match_operand:HI 0 "push_operand" "")
18934 (match_operand:HI 1 "memory_operand" ""))
18935 (match_scratch:HI 2 "r")]
18936 "! optimize_size && ! TARGET_PUSH_MEMORY"
18937 [(set (match_dup 2) (match_dup 1))
18938 (set (match_dup 0) (match_dup 2))]
18942 [(set (match_operand:QI 0 "push_operand" "")
18943 (match_operand:QI 1 "memory_operand" ""))
18944 (match_scratch:QI 2 "q")]
18945 "! optimize_size && ! TARGET_PUSH_MEMORY"
18946 [(set (match_dup 2) (match_dup 1))
18947 (set (match_dup 0) (match_dup 2))]
18950 ;; Don't move an immediate directly to memory when the instruction
18953 [(match_scratch:SI 1 "r")
18954 (set (match_operand:SI 0 "memory_operand" "")
18957 && ! TARGET_USE_MOV0
18958 && TARGET_SPLIT_LONG_MOVES
18959 && get_attr_length (insn) >= ix86_cost->large_insn
18960 && peep2_regno_dead_p (0, FLAGS_REG)"
18961 [(parallel [(set (match_dup 1) (const_int 0))
18962 (clobber (reg:CC FLAGS_REG))])
18963 (set (match_dup 0) (match_dup 1))]
18967 [(match_scratch:HI 1 "r")
18968 (set (match_operand:HI 0 "memory_operand" "")
18971 && ! TARGET_USE_MOV0
18972 && TARGET_SPLIT_LONG_MOVES
18973 && get_attr_length (insn) >= ix86_cost->large_insn
18974 && peep2_regno_dead_p (0, FLAGS_REG)"
18975 [(parallel [(set (match_dup 2) (const_int 0))
18976 (clobber (reg:CC FLAGS_REG))])
18977 (set (match_dup 0) (match_dup 1))]
18978 "operands[2] = gen_lowpart (SImode, operands[1]);")
18981 [(match_scratch:QI 1 "q")
18982 (set (match_operand:QI 0 "memory_operand" "")
18985 && ! TARGET_USE_MOV0
18986 && TARGET_SPLIT_LONG_MOVES
18987 && get_attr_length (insn) >= ix86_cost->large_insn
18988 && peep2_regno_dead_p (0, FLAGS_REG)"
18989 [(parallel [(set (match_dup 2) (const_int 0))
18990 (clobber (reg:CC FLAGS_REG))])
18991 (set (match_dup 0) (match_dup 1))]
18992 "operands[2] = gen_lowpart (SImode, operands[1]);")
18995 [(match_scratch:SI 2 "r")
18996 (set (match_operand:SI 0 "memory_operand" "")
18997 (match_operand:SI 1 "immediate_operand" ""))]
18999 && get_attr_length (insn) >= ix86_cost->large_insn
19000 && TARGET_SPLIT_LONG_MOVES"
19001 [(set (match_dup 2) (match_dup 1))
19002 (set (match_dup 0) (match_dup 2))]
19006 [(match_scratch:HI 2 "r")
19007 (set (match_operand:HI 0 "memory_operand" "")
19008 (match_operand:HI 1 "immediate_operand" ""))]
19009 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
19010 && TARGET_SPLIT_LONG_MOVES"
19011 [(set (match_dup 2) (match_dup 1))
19012 (set (match_dup 0) (match_dup 2))]
19016 [(match_scratch:QI 2 "q")
19017 (set (match_operand:QI 0 "memory_operand" "")
19018 (match_operand:QI 1 "immediate_operand" ""))]
19019 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
19020 && TARGET_SPLIT_LONG_MOVES"
19021 [(set (match_dup 2) (match_dup 1))
19022 (set (match_dup 0) (match_dup 2))]
19025 ;; Don't compare memory with zero, load and use a test instead.
19028 (compare (match_operand:SI 0 "memory_operand" "")
19030 (match_scratch:SI 3 "r")]
19031 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
19032 [(set (match_dup 3) (match_dup 0))
19033 (set (reg:CCNO FLAGS_REG) (compare:CCNO (match_dup 3) (const_int 0)))]
19036 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
19037 ;; Don't split NOTs with a displacement operand, because resulting XOR
19038 ;; will not be pairable anyway.
19040 ;; On AMD K6, NOT is vector decoded with memory operand that cannot be
19041 ;; represented using a modRM byte. The XOR replacement is long decoded,
19042 ;; so this split helps here as well.
19044 ;; Note: Can't do this as a regular split because we can't get proper
19045 ;; lifetime information then.
19048 [(set (match_operand:SI 0 "nonimmediate_operand" "")
19049 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
19051 && peep2_regno_dead_p (0, FLAGS_REG)
19052 && ((TARGET_PENTIUM
19053 && (GET_CODE (operands[0]) != MEM
19054 || !memory_displacement_operand (operands[0], SImode)))
19055 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
19056 [(parallel [(set (match_dup 0)
19057 (xor:SI (match_dup 1) (const_int -1)))
19058 (clobber (reg:CC FLAGS_REG))])]
19062 [(set (match_operand:HI 0 "nonimmediate_operand" "")
19063 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
19065 && peep2_regno_dead_p (0, FLAGS_REG)
19066 && ((TARGET_PENTIUM
19067 && (GET_CODE (operands[0]) != MEM
19068 || !memory_displacement_operand (operands[0], HImode)))
19069 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
19070 [(parallel [(set (match_dup 0)
19071 (xor:HI (match_dup 1) (const_int -1)))
19072 (clobber (reg:CC FLAGS_REG))])]
19076 [(set (match_operand:QI 0 "nonimmediate_operand" "")
19077 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
19079 && peep2_regno_dead_p (0, FLAGS_REG)
19080 && ((TARGET_PENTIUM
19081 && (GET_CODE (operands[0]) != MEM
19082 || !memory_displacement_operand (operands[0], QImode)))
19083 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
19084 [(parallel [(set (match_dup 0)
19085 (xor:QI (match_dup 1) (const_int -1)))
19086 (clobber (reg:CC FLAGS_REG))])]
19089 ;; Non pairable "test imm, reg" instructions can be translated to
19090 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
19091 ;; byte opcode instead of two, have a short form for byte operands),
19092 ;; so do it for other CPUs as well. Given that the value was dead,
19093 ;; this should not create any new dependencies. Pass on the sub-word
19094 ;; versions if we're concerned about partial register stalls.
19098 (compare (and:SI (match_operand:SI 0 "register_operand" "")
19099 (match_operand:SI 1 "immediate_operand" ""))
19101 "ix86_match_ccmode (insn, CCNOmode)
19102 && (true_regnum (operands[0]) != 0
19103 || (GET_CODE (operands[1]) == CONST_INT
19104 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')))
19105 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
19107 [(set (reg:CCNO FLAGS_REG)
19108 (compare:CCNO (and:SI (match_dup 0)
19112 (and:SI (match_dup 0) (match_dup 1)))])]
19115 ;; We don't need to handle HImode case, because it will be promoted to SImode
19116 ;; on ! TARGET_PARTIAL_REG_STALL
19120 (compare (and:QI (match_operand:QI 0 "register_operand" "")
19121 (match_operand:QI 1 "immediate_operand" ""))
19123 "! TARGET_PARTIAL_REG_STALL
19124 && ix86_match_ccmode (insn, CCNOmode)
19125 && true_regnum (operands[0]) != 0
19126 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
19128 [(set (reg:CCNO FLAGS_REG)
19129 (compare:CCNO (and:QI (match_dup 0)
19133 (and:QI (match_dup 0) (match_dup 1)))])]
19141 (match_operand 0 "ext_register_operand" "")
19144 (match_operand 1 "const_int_operand" ""))
19146 "! TARGET_PARTIAL_REG_STALL
19147 && ix86_match_ccmode (insn, CCNOmode)
19148 && true_regnum (operands[0]) != 0
19149 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
19150 [(parallel [(set (reg:CCNO FLAGS_REG)
19159 (set (zero_extract:SI (match_dup 0)
19170 ;; Don't do logical operations with memory inputs.
19172 [(match_scratch:SI 2 "r")
19173 (parallel [(set (match_operand:SI 0 "register_operand" "")
19174 (match_operator:SI 3 "arith_or_logical_operator"
19176 (match_operand:SI 1 "memory_operand" "")]))
19177 (clobber (reg:CC FLAGS_REG))])]
19178 "! optimize_size && ! TARGET_READ_MODIFY"
19179 [(set (match_dup 2) (match_dup 1))
19180 (parallel [(set (match_dup 0)
19181 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
19182 (clobber (reg:CC FLAGS_REG))])]
19186 [(match_scratch:SI 2 "r")
19187 (parallel [(set (match_operand:SI 0 "register_operand" "")
19188 (match_operator:SI 3 "arith_or_logical_operator"
19189 [(match_operand:SI 1 "memory_operand" "")
19191 (clobber (reg:CC FLAGS_REG))])]
19192 "! optimize_size && ! TARGET_READ_MODIFY"
19193 [(set (match_dup 2) (match_dup 1))
19194 (parallel [(set (match_dup 0)
19195 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
19196 (clobber (reg:CC FLAGS_REG))])]
19199 ; Don't do logical operations with memory outputs
19201 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
19202 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
19203 ; the same decoder scheduling characteristics as the original.
19206 [(match_scratch:SI 2 "r")
19207 (parallel [(set (match_operand:SI 0 "memory_operand" "")
19208 (match_operator:SI 3 "arith_or_logical_operator"
19210 (match_operand:SI 1 "nonmemory_operand" "")]))
19211 (clobber (reg:CC FLAGS_REG))])]
19212 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
19213 [(set (match_dup 2) (match_dup 0))
19214 (parallel [(set (match_dup 2)
19215 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
19216 (clobber (reg:CC FLAGS_REG))])
19217 (set (match_dup 0) (match_dup 2))]
19221 [(match_scratch:SI 2 "r")
19222 (parallel [(set (match_operand:SI 0 "memory_operand" "")
19223 (match_operator:SI 3 "arith_or_logical_operator"
19224 [(match_operand:SI 1 "nonmemory_operand" "")
19226 (clobber (reg:CC FLAGS_REG))])]
19227 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
19228 [(set (match_dup 2) (match_dup 0))
19229 (parallel [(set (match_dup 2)
19230 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
19231 (clobber (reg:CC FLAGS_REG))])
19232 (set (match_dup 0) (match_dup 2))]
19235 ;; Attempt to always use XOR for zeroing registers.
19237 [(set (match_operand 0 "register_operand" "")
19239 "(GET_MODE (operands[0]) == QImode
19240 || GET_MODE (operands[0]) == HImode
19241 || GET_MODE (operands[0]) == SImode
19242 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
19243 && (! TARGET_USE_MOV0 || optimize_size)
19244 && peep2_regno_dead_p (0, FLAGS_REG)"
19245 [(parallel [(set (match_dup 0) (const_int 0))
19246 (clobber (reg:CC FLAGS_REG))])]
19247 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
19251 [(set (strict_low_part (match_operand 0 "register_operand" ""))
19253 "(GET_MODE (operands[0]) == QImode
19254 || GET_MODE (operands[0]) == HImode)
19255 && (! TARGET_USE_MOV0 || optimize_size)
19256 && peep2_regno_dead_p (0, FLAGS_REG)"
19257 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
19258 (clobber (reg:CC FLAGS_REG))])])
19260 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
19262 [(set (match_operand 0 "register_operand" "")
19264 "(GET_MODE (operands[0]) == HImode
19265 || GET_MODE (operands[0]) == SImode
19266 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
19267 && (optimize_size || TARGET_PENTIUM)
19268 && peep2_regno_dead_p (0, FLAGS_REG)"
19269 [(parallel [(set (match_dup 0) (const_int -1))
19270 (clobber (reg:CC FLAGS_REG))])]
19271 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
19274 ;; Attempt to convert simple leas to adds. These can be created by
19277 [(set (match_operand:SI 0 "register_operand" "")
19278 (plus:SI (match_dup 0)
19279 (match_operand:SI 1 "nonmemory_operand" "")))]
19280 "peep2_regno_dead_p (0, FLAGS_REG)"
19281 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
19282 (clobber (reg:CC FLAGS_REG))])]
19286 [(set (match_operand:SI 0 "register_operand" "")
19287 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
19288 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
19289 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
19290 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
19291 (clobber (reg:CC FLAGS_REG))])]
19292 "operands[2] = gen_lowpart (SImode, operands[2]);")
19295 [(set (match_operand:DI 0 "register_operand" "")
19296 (plus:DI (match_dup 0)
19297 (match_operand:DI 1 "x86_64_general_operand" "")))]
19298 "peep2_regno_dead_p (0, FLAGS_REG)"
19299 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
19300 (clobber (reg:CC FLAGS_REG))])]
19304 [(set (match_operand:SI 0 "register_operand" "")
19305 (mult:SI (match_dup 0)
19306 (match_operand:SI 1 "const_int_operand" "")))]
19307 "exact_log2 (INTVAL (operands[1])) >= 0
19308 && peep2_regno_dead_p (0, FLAGS_REG)"
19309 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
19310 (clobber (reg:CC FLAGS_REG))])]
19311 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
19314 [(set (match_operand:DI 0 "register_operand" "")
19315 (mult:DI (match_dup 0)
19316 (match_operand:DI 1 "const_int_operand" "")))]
19317 "exact_log2 (INTVAL (operands[1])) >= 0
19318 && peep2_regno_dead_p (0, FLAGS_REG)"
19319 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
19320 (clobber (reg:CC FLAGS_REG))])]
19321 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
19324 [(set (match_operand:SI 0 "register_operand" "")
19325 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
19326 (match_operand:DI 2 "const_int_operand" "")) 0))]
19327 "exact_log2 (INTVAL (operands[2])) >= 0
19328 && REGNO (operands[0]) == REGNO (operands[1])
19329 && peep2_regno_dead_p (0, FLAGS_REG)"
19330 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
19331 (clobber (reg:CC FLAGS_REG))])]
19332 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
19334 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
19335 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
19336 ;; many CPUs it is also faster, since special hardware to avoid esp
19337 ;; dependencies is present.
19339 ;; While some of these conversions may be done using splitters, we use peepholes
19340 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
19342 ;; Convert prologue esp subtractions to push.
19343 ;; We need register to push. In order to keep verify_flow_info happy we have
19345 ;; - use scratch and clobber it in order to avoid dependencies
19346 ;; - use already live register
19347 ;; We can't use the second way right now, since there is no reliable way how to
19348 ;; verify that given register is live. First choice will also most likely in
19349 ;; fewer dependencies. On the place of esp adjustments it is very likely that
19350 ;; call clobbered registers are dead. We may want to use base pointer as an
19351 ;; alternative when no register is available later.
19354 [(match_scratch:SI 0 "r")
19355 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
19356 (clobber (reg:CC FLAGS_REG))
19357 (clobber (mem:BLK (scratch)))])]
19358 "optimize_size || !TARGET_SUB_ESP_4"
19359 [(clobber (match_dup 0))
19360 (parallel [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19361 (clobber (mem:BLK (scratch)))])])
19364 [(match_scratch:SI 0 "r")
19365 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
19366 (clobber (reg:CC FLAGS_REG))
19367 (clobber (mem:BLK (scratch)))])]
19368 "optimize_size || !TARGET_SUB_ESP_8"
19369 [(clobber (match_dup 0))
19370 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19371 (parallel [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19372 (clobber (mem:BLK (scratch)))])])
19374 ;; Convert esp subtractions to push.
19376 [(match_scratch:SI 0 "r")
19377 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
19378 (clobber (reg:CC FLAGS_REG))])]
19379 "optimize_size || !TARGET_SUB_ESP_4"
19380 [(clobber (match_dup 0))
19381 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))])
19384 [(match_scratch:SI 0 "r")
19385 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
19386 (clobber (reg:CC FLAGS_REG))])]
19387 "optimize_size || !TARGET_SUB_ESP_8"
19388 [(clobber (match_dup 0))
19389 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19390 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))])
19392 ;; Convert epilogue deallocator to pop.
19394 [(match_scratch:SI 0 "r")
19395 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19396 (clobber (reg:CC FLAGS_REG))
19397 (clobber (mem:BLK (scratch)))])]
19398 "optimize_size || !TARGET_ADD_ESP_4"
19399 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19400 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19401 (clobber (mem:BLK (scratch)))])]
19404 ;; Two pops case is tricky, since pop causes dependency on destination register.
19405 ;; We use two registers if available.
19407 [(match_scratch:SI 0 "r")
19408 (match_scratch:SI 1 "r")
19409 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19410 (clobber (reg:CC FLAGS_REG))
19411 (clobber (mem:BLK (scratch)))])]
19412 "optimize_size || !TARGET_ADD_ESP_8"
19413 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19414 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19415 (clobber (mem:BLK (scratch)))])
19416 (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
19417 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19421 [(match_scratch:SI 0 "r")
19422 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19423 (clobber (reg:CC FLAGS_REG))
19424 (clobber (mem:BLK (scratch)))])]
19426 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19427 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19428 (clobber (mem:BLK (scratch)))])
19429 (parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19430 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19433 ;; Convert esp additions to pop.
19435 [(match_scratch:SI 0 "r")
19436 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19437 (clobber (reg:CC FLAGS_REG))])]
19439 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19440 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19443 ;; Two pops case is tricky, since pop causes dependency on destination register.
19444 ;; We use two registers if available.
19446 [(match_scratch:SI 0 "r")
19447 (match_scratch:SI 1 "r")
19448 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19449 (clobber (reg:CC FLAGS_REG))])]
19451 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19452 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])
19453 (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
19454 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19458 [(match_scratch:SI 0 "r")
19459 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19460 (clobber (reg:CC FLAGS_REG))])]
19462 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19463 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])
19464 (parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19465 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19468 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
19469 ;; required and register dies.
19472 (compare (match_operand:SI 0 "register_operand" "")
19473 (match_operand:SI 1 "incdec_operand" "")))]
19474 "ix86_match_ccmode (insn, CCGCmode)
19475 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
19476 [(parallel [(set (reg:CCGC FLAGS_REG)
19477 (compare:CCGC (match_dup 0)
19479 (clobber (match_dup 0))])]
19484 (compare (match_operand:HI 0 "register_operand" "")
19485 (match_operand:HI 1 "incdec_operand" "")))]
19486 "ix86_match_ccmode (insn, CCGCmode)
19487 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
19488 [(parallel [(set (reg:CCGC FLAGS_REG)
19489 (compare:CCGC (match_dup 0)
19491 (clobber (match_dup 0))])]
19496 (compare (match_operand:QI 0 "register_operand" "")
19497 (match_operand:QI 1 "incdec_operand" "")))]
19498 "ix86_match_ccmode (insn, CCGCmode)
19499 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
19500 [(parallel [(set (reg:CCGC FLAGS_REG)
19501 (compare:CCGC (match_dup 0)
19503 (clobber (match_dup 0))])]
19506 ;; Convert compares with 128 to shorter add -128
19509 (compare (match_operand:SI 0 "register_operand" "")
19511 "ix86_match_ccmode (insn, CCGCmode)
19512 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
19513 [(parallel [(set (reg:CCGC FLAGS_REG)
19514 (compare:CCGC (match_dup 0)
19516 (clobber (match_dup 0))])]
19521 (compare (match_operand:HI 0 "register_operand" "")
19523 "ix86_match_ccmode (insn, CCGCmode)
19524 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
19525 [(parallel [(set (reg:CCGC FLAGS_REG)
19526 (compare:CCGC (match_dup 0)
19528 (clobber (match_dup 0))])]
19532 [(match_scratch:DI 0 "r")
19533 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
19534 (clobber (reg:CC FLAGS_REG))
19535 (clobber (mem:BLK (scratch)))])]
19536 "optimize_size || !TARGET_SUB_ESP_4"
19537 [(clobber (match_dup 0))
19538 (parallel [(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19539 (clobber (mem:BLK (scratch)))])])
19542 [(match_scratch:DI 0 "r")
19543 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -16)))
19544 (clobber (reg:CC FLAGS_REG))
19545 (clobber (mem:BLK (scratch)))])]
19546 "optimize_size || !TARGET_SUB_ESP_8"
19547 [(clobber (match_dup 0))
19548 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19549 (parallel [(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19550 (clobber (mem:BLK (scratch)))])])
19552 ;; Convert esp subtractions to push.
19554 [(match_scratch:DI 0 "r")
19555 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
19556 (clobber (reg:CC FLAGS_REG))])]
19557 "optimize_size || !TARGET_SUB_ESP_4"
19558 [(clobber (match_dup 0))
19559 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))])
19562 [(match_scratch:DI 0 "r")
19563 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -16)))
19564 (clobber (reg:CC FLAGS_REG))])]
19565 "optimize_size || !TARGET_SUB_ESP_8"
19566 [(clobber (match_dup 0))
19567 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19568 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))])
19570 ;; Convert epilogue deallocator to pop.
19572 [(match_scratch:DI 0 "r")
19573 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19574 (clobber (reg:CC FLAGS_REG))
19575 (clobber (mem:BLK (scratch)))])]
19576 "optimize_size || !TARGET_ADD_ESP_4"
19577 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19578 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19579 (clobber (mem:BLK (scratch)))])]
19582 ;; Two pops case is tricky, since pop causes dependency on destination register.
19583 ;; We use two registers if available.
19585 [(match_scratch:DI 0 "r")
19586 (match_scratch:DI 1 "r")
19587 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19588 (clobber (reg:CC FLAGS_REG))
19589 (clobber (mem:BLK (scratch)))])]
19590 "optimize_size || !TARGET_ADD_ESP_8"
19591 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19592 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19593 (clobber (mem:BLK (scratch)))])
19594 (parallel [(set (match_dup 1) (mem:DI (reg:DI SP_REG)))
19595 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19599 [(match_scratch:DI 0 "r")
19600 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19601 (clobber (reg:CC FLAGS_REG))
19602 (clobber (mem:BLK (scratch)))])]
19604 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19605 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19606 (clobber (mem:BLK (scratch)))])
19607 (parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19608 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19611 ;; Convert esp additions to pop.
19613 [(match_scratch:DI 0 "r")
19614 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19615 (clobber (reg:CC FLAGS_REG))])]
19617 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19618 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19621 ;; Two pops case is tricky, since pop causes dependency on destination register.
19622 ;; We use two registers if available.
19624 [(match_scratch:DI 0 "r")
19625 (match_scratch:DI 1 "r")
19626 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19627 (clobber (reg:CC FLAGS_REG))])]
19629 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19630 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])
19631 (parallel [(set (match_dup 1) (mem:DI (reg:DI SP_REG)))
19632 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19636 [(match_scratch:DI 0 "r")
19637 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19638 (clobber (reg:CC FLAGS_REG))])]
19640 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19641 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])
19642 (parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19643 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19646 ;; Convert imul by three, five and nine into lea
19649 [(set (match_operand:SI 0 "register_operand" "")
19650 (mult:SI (match_operand:SI 1 "register_operand" "")
19651 (match_operand:SI 2 "const_int_operand" "")))
19652 (clobber (reg:CC FLAGS_REG))])]
19653 "INTVAL (operands[2]) == 3
19654 || INTVAL (operands[2]) == 5
19655 || INTVAL (operands[2]) == 9"
19656 [(set (match_dup 0)
19657 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
19659 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19663 [(set (match_operand:SI 0 "register_operand" "")
19664 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
19665 (match_operand:SI 2 "const_int_operand" "")))
19666 (clobber (reg:CC FLAGS_REG))])]
19668 && (INTVAL (operands[2]) == 3
19669 || INTVAL (operands[2]) == 5
19670 || INTVAL (operands[2]) == 9)"
19671 [(set (match_dup 0) (match_dup 1))
19673 (plus:SI (mult:SI (match_dup 0) (match_dup 2))
19675 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19679 [(set (match_operand:DI 0 "register_operand" "")
19680 (mult:DI (match_operand:DI 1 "register_operand" "")
19681 (match_operand:DI 2 "const_int_operand" "")))
19682 (clobber (reg:CC FLAGS_REG))])]
19684 && (INTVAL (operands[2]) == 3
19685 || INTVAL (operands[2]) == 5
19686 || INTVAL (operands[2]) == 9)"
19687 [(set (match_dup 0)
19688 (plus:DI (mult:DI (match_dup 1) (match_dup 2))
19690 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19694 [(set (match_operand:DI 0 "register_operand" "")
19695 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
19696 (match_operand:DI 2 "const_int_operand" "")))
19697 (clobber (reg:CC FLAGS_REG))])]
19700 && (INTVAL (operands[2]) == 3
19701 || INTVAL (operands[2]) == 5
19702 || INTVAL (operands[2]) == 9)"
19703 [(set (match_dup 0) (match_dup 1))
19705 (plus:DI (mult:DI (match_dup 0) (match_dup 2))
19707 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19709 ;; Imul $32bit_imm, mem, reg is vector decoded, while
19710 ;; imul $32bit_imm, reg, reg is direct decoded.
19712 [(match_scratch:DI 3 "r")
19713 (parallel [(set (match_operand:DI 0 "register_operand" "")
19714 (mult:DI (match_operand:DI 1 "memory_operand" "")
19715 (match_operand:DI 2 "immediate_operand" "")))
19716 (clobber (reg:CC FLAGS_REG))])]
19717 "TARGET_K8 && !optimize_size
19718 && (GET_CODE (operands[2]) != CONST_INT
19719 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
19720 [(set (match_dup 3) (match_dup 1))
19721 (parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
19722 (clobber (reg:CC FLAGS_REG))])]
19726 [(match_scratch:SI 3 "r")
19727 (parallel [(set (match_operand:SI 0 "register_operand" "")
19728 (mult:SI (match_operand:SI 1 "memory_operand" "")
19729 (match_operand:SI 2 "immediate_operand" "")))
19730 (clobber (reg:CC FLAGS_REG))])]
19731 "TARGET_K8 && !optimize_size
19732 && (GET_CODE (operands[2]) != CONST_INT
19733 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
19734 [(set (match_dup 3) (match_dup 1))
19735 (parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
19736 (clobber (reg:CC FLAGS_REG))])]
19740 [(match_scratch:SI 3 "r")
19741 (parallel [(set (match_operand:DI 0 "register_operand" "")
19743 (mult:SI (match_operand:SI 1 "memory_operand" "")
19744 (match_operand:SI 2 "immediate_operand" ""))))
19745 (clobber (reg:CC FLAGS_REG))])]
19746 "TARGET_K8 && !optimize_size
19747 && (GET_CODE (operands[2]) != CONST_INT
19748 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
19749 [(set (match_dup 3) (match_dup 1))
19750 (parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
19751 (clobber (reg:CC FLAGS_REG))])]
19754 ;; imul $8/16bit_imm, regmem, reg is vector decoded.
19755 ;; Convert it into imul reg, reg
19756 ;; It would be better to force assembler to encode instruction using long
19757 ;; immediate, but there is apparently no way to do so.
19759 [(parallel [(set (match_operand:DI 0 "register_operand" "")
19760 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
19761 (match_operand:DI 2 "const_int_operand" "")))
19762 (clobber (reg:CC FLAGS_REG))])
19763 (match_scratch:DI 3 "r")]
19764 "TARGET_K8 && !optimize_size
19765 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
19766 [(set (match_dup 3) (match_dup 2))
19767 (parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
19768 (clobber (reg:CC FLAGS_REG))])]
19770 if (!rtx_equal_p (operands[0], operands[1]))
19771 emit_move_insn (operands[0], operands[1]);
19775 [(parallel [(set (match_operand:SI 0 "register_operand" "")
19776 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
19777 (match_operand:SI 2 "const_int_operand" "")))
19778 (clobber (reg:CC FLAGS_REG))])
19779 (match_scratch:SI 3 "r")]
19780 "TARGET_K8 && !optimize_size
19781 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
19782 [(set (match_dup 3) (match_dup 2))
19783 (parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
19784 (clobber (reg:CC FLAGS_REG))])]
19786 if (!rtx_equal_p (operands[0], operands[1]))
19787 emit_move_insn (operands[0], operands[1]);
19791 [(parallel [(set (match_operand:HI 0 "register_operand" "")
19792 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "")
19793 (match_operand:HI 2 "immediate_operand" "")))
19794 (clobber (reg:CC FLAGS_REG))])
19795 (match_scratch:HI 3 "r")]
19796 "TARGET_K8 && !optimize_size"
19797 [(set (match_dup 3) (match_dup 2))
19798 (parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
19799 (clobber (reg:CC FLAGS_REG))])]
19801 if (!rtx_equal_p (operands[0], operands[1]))
19802 emit_move_insn (operands[0], operands[1]);
19805 ;; Call-value patterns last so that the wildcard operand does not
19806 ;; disrupt insn-recog's switch tables.
19808 (define_insn "*call_value_pop_0"
19809 [(set (match_operand 0 "" "")
19810 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
19811 (match_operand:SI 2 "" "")))
19812 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
19813 (match_operand:SI 3 "immediate_operand" "")))]
19816 if (SIBLING_CALL_P (insn))
19819 return "call\t%P1";
19821 [(set_attr "type" "callv")])
19823 (define_insn "*call_value_pop_1"
19824 [(set (match_operand 0 "" "")
19825 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
19826 (match_operand:SI 2 "" "")))
19827 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
19828 (match_operand:SI 3 "immediate_operand" "i")))]
19831 if (constant_call_address_operand (operands[1], Pmode))
19833 if (SIBLING_CALL_P (insn))
19836 return "call\t%P1";
19838 if (SIBLING_CALL_P (insn))
19841 return "call\t%A1";
19843 [(set_attr "type" "callv")])
19845 (define_insn "*call_value_0"
19846 [(set (match_operand 0 "" "")
19847 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
19848 (match_operand:SI 2 "" "")))]
19851 if (SIBLING_CALL_P (insn))
19854 return "call\t%P1";
19856 [(set_attr "type" "callv")])
19858 (define_insn "*call_value_0_rex64"
19859 [(set (match_operand 0 "" "")
19860 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
19861 (match_operand:DI 2 "const_int_operand" "")))]
19864 if (SIBLING_CALL_P (insn))
19867 return "call\t%P1";
19869 [(set_attr "type" "callv")])
19871 (define_insn "*call_value_1"
19872 [(set (match_operand 0 "" "")
19873 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
19874 (match_operand:SI 2 "" "")))]
19875 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
19877 if (constant_call_address_operand (operands[1], Pmode))
19878 return "call\t%P1";
19879 return "call\t%*%1";
19881 [(set_attr "type" "callv")])
19883 (define_insn "*sibcall_value_1"
19884 [(set (match_operand 0 "" "")
19885 (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,c,d,a"))
19886 (match_operand:SI 2 "" "")))]
19887 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
19889 if (constant_call_address_operand (operands[1], Pmode))
19891 return "jmp\t%*%1";
19893 [(set_attr "type" "callv")])
19895 (define_insn "*call_value_1_rex64"
19896 [(set (match_operand 0 "" "")
19897 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
19898 (match_operand:DI 2 "" "")))]
19899 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
19901 if (constant_call_address_operand (operands[1], Pmode))
19902 return "call\t%P1";
19903 return "call\t%A1";
19905 [(set_attr "type" "callv")])
19907 (define_insn "*sibcall_value_1_rex64"
19908 [(set (match_operand 0 "" "")
19909 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
19910 (match_operand:DI 2 "" "")))]
19911 "SIBLING_CALL_P (insn) && TARGET_64BIT"
19913 [(set_attr "type" "callv")])
19915 (define_insn "*sibcall_value_1_rex64_v"
19916 [(set (match_operand 0 "" "")
19917 (call (mem:QI (reg:DI 40))
19918 (match_operand:DI 1 "" "")))]
19919 "SIBLING_CALL_P (insn) && TARGET_64BIT"
19921 [(set_attr "type" "callv")])
19923 (define_insn "trap"
19924 [(trap_if (const_int 1) (const_int 5))]
19928 ;;; ix86 doesn't have conditional trap instructions, but we fake them
19929 ;;; for the sake of bounds checking. By emitting bounds checks as
19930 ;;; conditional traps rather than as conditional jumps around
19931 ;;; unconditional traps we avoid introducing spurious basic-block
19932 ;;; boundaries and facilitate elimination of redundant checks. In
19933 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
19936 ;;; FIXME: Static branch prediction rules for ix86 are such that
19937 ;;; forward conditional branches predict as untaken. As implemented
19938 ;;; below, pseudo conditional traps violate that rule. We should use
19939 ;;; .pushsection/.popsection to place all of the `int 5's in a special
19940 ;;; section loaded at the end of the text segment and branch forward
19941 ;;; there on bounds-failure, and then jump back immediately (in case
19942 ;;; the system chooses to ignore bounds violations, or to report
19943 ;;; violations and continue execution).
19945 (define_expand "conditional_trap"
19946 [(trap_if (match_operator 0 "comparison_operator"
19947 [(match_dup 2) (const_int 0)])
19948 (match_operand 1 "const_int_operand" ""))]
19951 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
19952 ix86_expand_compare (GET_CODE (operands[0]),
19958 (define_insn "*conditional_trap_1"
19959 [(trap_if (match_operator 0 "comparison_operator"
19960 [(reg 17) (const_int 0)])
19961 (match_operand 1 "const_int_operand" ""))]
19964 operands[2] = gen_label_rtx ();
19965 output_asm_insn ("j%c0\t%l2\; int\t%1", operands);
19966 (*targetm.asm_out.internal_label) (asm_out_file, "L",
19967 CODE_LABEL_NUMBER (operands[2]));
19971 ;; Pentium III SIMD instructions.
19973 ;; Moves for SSE/MMX regs.
19975 (define_insn "movv4sf_internal"
19976 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
19977 (match_operand:V4SF 1 "vector_move_operand" "C,xm,x"))]
19981 movaps\t{%1, %0|%0, %1}
19982 movaps\t{%1, %0|%0, %1}"
19983 [(set_attr "type" "ssemov")
19984 (set_attr "mode" "V4SF")])
19987 [(set (match_operand:V4SF 0 "register_operand" "")
19988 (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))]
19990 [(set (match_dup 0)
19992 (vec_duplicate:V4SF (match_dup 1))
19996 operands[1] = simplify_gen_subreg (SFmode, operands[1], V4SFmode, 0);
19997 operands[2] = CONST0_RTX (V4SFmode);
20000 (define_insn "movv4si_internal"
20001 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,x,m")
20002 (match_operand:V4SI 1 "vector_move_operand" "C,xm,x"))]
20005 switch (which_alternative)
20008 if (get_attr_mode (insn) == MODE_V4SF)
20009 return "xorps\t%0, %0";
20011 return "pxor\t%0, %0";
20014 if (get_attr_mode (insn) == MODE_V4SF)
20015 return "movaps\t{%1, %0|%0, %1}";
20017 return "movdqa\t{%1, %0|%0, %1}";
20022 [(set_attr "type" "ssemov")
20024 (cond [(eq_attr "alternative" "0,1")
20026 (ne (symbol_ref "optimize_size")
20028 (const_string "V4SF")
20029 (const_string "TI"))
20030 (eq_attr "alternative" "2")
20032 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
20034 (ne (symbol_ref "optimize_size")
20036 (const_string "V4SF")
20037 (const_string "TI"))]
20038 (const_string "TI")))])
20040 (define_insn "movv2di_internal"
20041 [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x,x,m")
20042 (match_operand:V2DI 1 "vector_move_operand" "C,xm,x"))]
20045 switch (which_alternative)
20048 if (get_attr_mode (insn) == MODE_V4SF)
20049 return "xorps\t%0, %0";
20051 return "pxor\t%0, %0";
20054 if (get_attr_mode (insn) == MODE_V4SF)
20055 return "movaps\t{%1, %0|%0, %1}";
20057 return "movdqa\t{%1, %0|%0, %1}";
20062 [(set_attr "type" "ssemov")
20064 (cond [(eq_attr "alternative" "0,1")
20066 (ne (symbol_ref "optimize_size")
20068 (const_string "V4SF")
20069 (const_string "TI"))
20070 (eq_attr "alternative" "2")
20072 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
20074 (ne (symbol_ref "optimize_size")
20076 (const_string "V4SF")
20077 (const_string "TI"))]
20078 (const_string "TI")))])
20081 [(set (match_operand:V2DF 0 "register_operand" "")
20082 (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))]
20084 [(set (match_dup 0)
20086 (vec_duplicate:V2DF (match_dup 1))
20090 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2DFmode, 0);
20091 operands[2] = CONST0_RTX (V2DFmode);
20094 (define_insn "movv8qi_internal"
20095 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,y,m,!y,!*Y,?*Y,?m")
20096 (match_operand:V8QI 1 "vector_move_operand" "C,ym,y,*Y,y,*Ym,*Y"))]
20098 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20101 movq\t{%1, %0|%0, %1}
20102 movq\t{%1, %0|%0, %1}
20103 movdq2q\t{%1, %0|%0, %1}
20104 movq2dq\t{%1, %0|%0, %1}
20105 movq\t{%1, %0|%0, %1}
20106 movq\t{%1, %0|%0, %1}"
20107 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov")
20108 (set_attr "mode" "DI")])
20110 (define_insn "movv4hi_internal"
20111 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,y,m,!y,!*Y,?*Y,?m")
20112 (match_operand:V4HI 1 "vector_move_operand" "C,ym,y,*Y,y,*Ym,*Y"))]
20114 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20117 movq\t{%1, %0|%0, %1}
20118 movq\t{%1, %0|%0, %1}
20119 movdq2q\t{%1, %0|%0, %1}
20120 movq2dq\t{%1, %0|%0, %1}
20121 movq\t{%1, %0|%0, %1}
20122 movq\t{%1, %0|%0, %1}"
20123 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov")
20124 (set_attr "mode" "DI")])
20126 (define_insn "*movv2si_internal"
20127 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,y,m,!y,!*Y,?*Y,?m")
20128 (match_operand:V2SI 1 "vector_move_operand" "C,ym,y,*Y,y,*Ym,*Y"))]
20130 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20133 movq\t{%1, %0|%0, %1}
20134 movq\t{%1, %0|%0, %1}
20135 movdq2q\t{%1, %0|%0, %1}
20136 movq2dq\t{%1, %0|%0, %1}
20137 movq\t{%1, %0|%0, %1}
20138 movq\t{%1, %0|%0, %1}"
20139 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov")
20140 (set_attr "mode" "DI")])
20142 (define_insn "movv2sf_internal"
20143 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,y,m,!y,!*Y,?*x,?m")
20144 (match_operand:V2SF 1 "vector_move_operand" "C,ym,y,*Y,y,*xm,*x"))]
20146 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20149 movq\t{%1, %0|%0, %1}
20150 movq\t{%1, %0|%0, %1}
20151 movdq2q\t{%1, %0|%0, %1}
20152 movq2dq\t{%1, %0|%0, %1}
20153 movlps\t{%1, %0|%0, %1}
20154 movlps\t{%1, %0|%0, %1}"
20155 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov")
20156 (set_attr "mode" "DI,DI,DI,DI,DI,V2SF,V2SF")])
20158 (define_expand "movti"
20159 [(set (match_operand:TI 0 "nonimmediate_operand" "")
20160 (match_operand:TI 1 "nonimmediate_operand" ""))]
20161 "TARGET_SSE || TARGET_64BIT"
20164 ix86_expand_move (TImode, operands);
20166 ix86_expand_vector_move (TImode, operands);
20170 (define_expand "movtf"
20171 [(set (match_operand:TF 0 "nonimmediate_operand" "")
20172 (match_operand:TF 1 "nonimmediate_operand" ""))]
20176 ix86_expand_move (TFmode, operands);
20178 ix86_expand_vector_move (TFmode, operands);
20182 (define_insn "movv2df_internal"
20183 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
20184 (match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))]
20186 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20188 switch (which_alternative)
20191 if (get_attr_mode (insn) == MODE_V4SF)
20192 return "xorps\t%0, %0";
20194 return "xorpd\t%0, %0";
20197 if (get_attr_mode (insn) == MODE_V4SF)
20198 return "movaps\t{%1, %0|%0, %1}";
20200 return "movapd\t{%1, %0|%0, %1}";
20205 [(set_attr "type" "ssemov")
20207 (cond [(eq_attr "alternative" "0,1")
20209 (ne (symbol_ref "optimize_size")
20211 (const_string "V4SF")
20212 (const_string "V2DF"))
20213 (eq_attr "alternative" "2")
20215 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
20217 (ne (symbol_ref "optimize_size")
20219 (const_string "V4SF")
20220 (const_string "V2DF"))]
20221 (const_string "V2DF")))])
20223 (define_insn "movv8hi_internal"
20224 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,x,m")
20225 (match_operand:V8HI 1 "vector_move_operand" "C,xm,x"))]
20227 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20229 switch (which_alternative)
20232 if (get_attr_mode (insn) == MODE_V4SF)
20233 return "xorps\t%0, %0";
20235 return "pxor\t%0, %0";
20238 if (get_attr_mode (insn) == MODE_V4SF)
20239 return "movaps\t{%1, %0|%0, %1}";
20241 return "movdqa\t{%1, %0|%0, %1}";
20246 [(set_attr "type" "ssemov")
20248 (cond [(eq_attr "alternative" "0,1")
20250 (ne (symbol_ref "optimize_size")
20252 (const_string "V4SF")
20253 (const_string "TI"))
20254 (eq_attr "alternative" "2")
20256 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
20258 (ne (symbol_ref "optimize_size")
20260 (const_string "V4SF")
20261 (const_string "TI"))]
20262 (const_string "TI")))])
20264 (define_insn "movv16qi_internal"
20265 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,x,m")
20266 (match_operand:V16QI 1 "vector_move_operand" "C,xm,x"))]
20268 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20270 switch (which_alternative)
20273 if (get_attr_mode (insn) == MODE_V4SF)
20274 return "xorps\t%0, %0";
20276 return "pxor\t%0, %0";
20279 if (get_attr_mode (insn) == MODE_V4SF)
20280 return "movaps\t{%1, %0|%0, %1}";
20282 return "movdqa\t{%1, %0|%0, %1}";
20287 [(set_attr "type" "ssemov")
20289 (cond [(eq_attr "alternative" "0,1")
20291 (ne (symbol_ref "optimize_size")
20293 (const_string "V4SF")
20294 (const_string "TI"))
20295 (eq_attr "alternative" "2")
20297 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
20299 (ne (symbol_ref "optimize_size")
20301 (const_string "V4SF")
20302 (const_string "TI"))]
20303 (const_string "TI")))])
20305 (define_expand "movv2df"
20306 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
20307 (match_operand:V2DF 1 "nonimmediate_operand" ""))]
20310 ix86_expand_vector_move (V2DFmode, operands);
20314 (define_expand "movv8hi"
20315 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
20316 (match_operand:V8HI 1 "nonimmediate_operand" ""))]
20319 ix86_expand_vector_move (V8HImode, operands);
20323 (define_expand "movv16qi"
20324 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
20325 (match_operand:V16QI 1 "nonimmediate_operand" ""))]
20328 ix86_expand_vector_move (V16QImode, operands);
20332 (define_expand "movv4sf"
20333 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
20334 (match_operand:V4SF 1 "nonimmediate_operand" ""))]
20337 ix86_expand_vector_move (V4SFmode, operands);
20341 (define_expand "movv4si"
20342 [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
20343 (match_operand:V4SI 1 "nonimmediate_operand" ""))]
20346 ix86_expand_vector_move (V4SImode, operands);
20350 (define_expand "movv2di"
20351 [(set (match_operand:V2DI 0 "nonimmediate_operand" "")
20352 (match_operand:V2DI 1 "nonimmediate_operand" ""))]
20355 ix86_expand_vector_move (V2DImode, operands);
20359 (define_expand "movv2si"
20360 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
20361 (match_operand:V2SI 1 "nonimmediate_operand" ""))]
20364 ix86_expand_vector_move (V2SImode, operands);
20368 (define_expand "movv4hi"
20369 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
20370 (match_operand:V4HI 1 "nonimmediate_operand" ""))]
20373 ix86_expand_vector_move (V4HImode, operands);
20377 (define_expand "movv8qi"
20378 [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
20379 (match_operand:V8QI 1 "nonimmediate_operand" ""))]
20382 ix86_expand_vector_move (V8QImode, operands);
20386 (define_expand "movv2sf"
20387 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
20388 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
20391 ix86_expand_vector_move (V2SFmode, operands);
20395 (define_insn "*pushti"
20396 [(set (match_operand:TI 0 "push_operand" "=<")
20397 (match_operand:TI 1 "register_operand" "x"))]
20401 (define_insn "*pushv2df"
20402 [(set (match_operand:V2DF 0 "push_operand" "=<")
20403 (match_operand:V2DF 1 "register_operand" "x"))]
20407 (define_insn "*pushv2di"
20408 [(set (match_operand:V2DI 0 "push_operand" "=<")
20409 (match_operand:V2DI 1 "register_operand" "x"))]
20413 (define_insn "*pushv8hi"
20414 [(set (match_operand:V8HI 0 "push_operand" "=<")
20415 (match_operand:V8HI 1 "register_operand" "x"))]
20419 (define_insn "*pushv16qi"
20420 [(set (match_operand:V16QI 0 "push_operand" "=<")
20421 (match_operand:V16QI 1 "register_operand" "x"))]
20425 (define_insn "*pushv4sf"
20426 [(set (match_operand:V4SF 0 "push_operand" "=<")
20427 (match_operand:V4SF 1 "register_operand" "x"))]
20431 (define_insn "*pushv4si"
20432 [(set (match_operand:V4SI 0 "push_operand" "=<")
20433 (match_operand:V4SI 1 "register_operand" "x"))]
20437 (define_insn "*pushv2si"
20438 [(set (match_operand:V2SI 0 "push_operand" "=<")
20439 (match_operand:V2SI 1 "register_operand" "y"))]
20443 (define_insn "*pushv4hi"
20444 [(set (match_operand:V4HI 0 "push_operand" "=<")
20445 (match_operand:V4HI 1 "register_operand" "y"))]
20449 (define_insn "*pushv8qi"
20450 [(set (match_operand:V8QI 0 "push_operand" "=<")
20451 (match_operand:V8QI 1 "register_operand" "y"))]
20455 (define_insn "*pushv2sf"
20456 [(set (match_operand:V2SF 0 "push_operand" "=<")
20457 (match_operand:V2SF 1 "register_operand" "y"))]
20462 [(set (match_operand 0 "push_operand" "")
20463 (match_operand 1 "register_operand" ""))]
20464 "!TARGET_64BIT && reload_completed
20465 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
20466 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 3)))
20467 (set (match_dup 2) (match_dup 1))]
20468 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
20469 stack_pointer_rtx);
20470 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
20473 [(set (match_operand 0 "push_operand" "")
20474 (match_operand 1 "register_operand" ""))]
20475 "TARGET_64BIT && reload_completed
20476 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
20477 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 3)))
20478 (set (match_dup 2) (match_dup 1))]
20479 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
20480 stack_pointer_rtx);
20481 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
20484 (define_insn "movti_internal"
20485 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
20486 (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
20487 "TARGET_SSE && !TARGET_64BIT
20488 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20490 switch (which_alternative)
20493 if (get_attr_mode (insn) == MODE_V4SF)
20494 return "xorps\t%0, %0";
20496 return "pxor\t%0, %0";
20499 if (get_attr_mode (insn) == MODE_V4SF)
20500 return "movaps\t{%1, %0|%0, %1}";
20502 return "movdqa\t{%1, %0|%0, %1}";
20507 [(set_attr "type" "ssemov,ssemov,ssemov")
20509 (cond [(eq_attr "alternative" "0,1")
20511 (ne (symbol_ref "optimize_size")
20513 (const_string "V4SF")
20514 (const_string "TI"))
20515 (eq_attr "alternative" "2")
20517 (ne (symbol_ref "optimize_size")
20519 (const_string "V4SF")
20520 (const_string "TI"))]
20521 (const_string "TI")))])
20523 (define_insn "*movti_rex64"
20524 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,x,xm")
20525 (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
20527 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20529 switch (which_alternative)
20535 if (get_attr_mode (insn) == MODE_V4SF)
20536 return "xorps\t%0, %0";
20538 return "pxor\t%0, %0";
20541 if (get_attr_mode (insn) == MODE_V4SF)
20542 return "movaps\t{%1, %0|%0, %1}";
20544 return "movdqa\t{%1, %0|%0, %1}";
20549 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
20551 (cond [(eq_attr "alternative" "2,3")
20553 (ne (symbol_ref "optimize_size")
20555 (const_string "V4SF")
20556 (const_string "TI"))
20557 (eq_attr "alternative" "4")
20559 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
20561 (ne (symbol_ref "optimize_size")
20563 (const_string "V4SF")
20564 (const_string "TI"))]
20565 (const_string "DI")))])
20567 (define_insn "*movtf_rex64"
20568 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o,x,x,xm")
20569 (match_operand:TF 1 "general_operand" "riFo,riF,C,xm,x"))]
20571 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20573 switch (which_alternative)
20579 if (get_attr_mode (insn) == MODE_V4SF)
20580 return "xorps\t%0, %0";
20582 return "pxor\t%0, %0";
20585 if (get_attr_mode (insn) == MODE_V4SF)
20586 return "movaps\t{%1, %0|%0, %1}";
20588 return "movdqa\t{%1, %0|%0, %1}";
20593 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
20595 (cond [(eq_attr "alternative" "2,3")
20597 (ne (symbol_ref "optimize_size")
20599 (const_string "V4SF")
20600 (const_string "TI"))
20601 (eq_attr "alternative" "4")
20603 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
20605 (ne (symbol_ref "optimize_size")
20607 (const_string "V4SF")
20608 (const_string "TI"))]
20609 (const_string "DI")))])
20612 [(set (match_operand:TI 0 "nonimmediate_operand" "")
20613 (match_operand:TI 1 "general_operand" ""))]
20614 "reload_completed && !SSE_REG_P (operands[0])
20615 && !SSE_REG_P (operands[1])"
20617 "ix86_split_long_move (operands); DONE;")
20620 [(set (match_operand:TF 0 "nonimmediate_operand" "")
20621 (match_operand:TF 1 "general_operand" ""))]
20622 "reload_completed && !SSE_REG_P (operands[0])
20623 && !SSE_REG_P (operands[1])"
20625 "ix86_split_long_move (operands); DONE;")
20627 ;; These two patterns are useful for specifying exactly whether to use
20628 ;; movaps or movups
20629 (define_expand "sse_movaps"
20630 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
20631 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
20635 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
20637 rtx tmp = gen_reg_rtx (V4SFmode);
20638 emit_insn (gen_sse_movaps (tmp, operands[1]));
20639 emit_move_insn (operands[0], tmp);
20644 (define_insn "*sse_movaps_1"
20645 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
20646 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
20649 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20650 "movaps\t{%1, %0|%0, %1}"
20651 [(set_attr "type" "ssemov,ssemov")
20652 (set_attr "mode" "V4SF")])
20654 (define_expand "sse_movups"
20655 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
20656 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
20660 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
20662 rtx tmp = gen_reg_rtx (V4SFmode);
20663 emit_insn (gen_sse_movups (tmp, operands[1]));
20664 emit_move_insn (operands[0], tmp);
20669 (define_insn "*sse_movups_1"
20670 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
20671 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
20674 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20675 "movups\t{%1, %0|%0, %1}"
20676 [(set_attr "type" "ssecvt,ssecvt")
20677 (set_attr "mode" "V4SF")])
20679 ;; SSE Strange Moves.
20681 (define_insn "sse_movmskps"
20682 [(set (match_operand:SI 0 "register_operand" "=r")
20683 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")]
20686 "movmskps\t{%1, %0|%0, %1}"
20687 [(set_attr "type" "ssecvt")
20688 (set_attr "mode" "V4SF")])
20690 (define_insn "mmx_pmovmskb"
20691 [(set (match_operand:SI 0 "register_operand" "=r")
20692 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
20694 "TARGET_SSE || TARGET_3DNOW_A"
20695 "pmovmskb\t{%1, %0|%0, %1}"
20696 [(set_attr "type" "ssecvt")
20697 (set_attr "mode" "V4SF")])
20700 (define_insn "mmx_maskmovq"
20701 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
20702 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
20703 (match_operand:V8QI 2 "register_operand" "y")]
20705 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
20706 ;; @@@ check ordering of operands in intel/nonintel syntax
20707 "maskmovq\t{%2, %1|%1, %2}"
20708 [(set_attr "type" "mmxcvt")
20709 (set_attr "mode" "DI")])
20711 (define_insn "mmx_maskmovq_rex"
20712 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
20713 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
20714 (match_operand:V8QI 2 "register_operand" "y")]
20716 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
20717 ;; @@@ check ordering of operands in intel/nonintel syntax
20718 "maskmovq\t{%2, %1|%1, %2}"
20719 [(set_attr "type" "mmxcvt")
20720 (set_attr "mode" "DI")])
20722 (define_insn "sse_movntv4sf"
20723 [(set (match_operand:V4SF 0 "memory_operand" "=m")
20724 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")]
20727 "movntps\t{%1, %0|%0, %1}"
20728 [(set_attr "type" "ssemov")
20729 (set_attr "mode" "V4SF")])
20731 (define_insn "sse_movntdi"
20732 [(set (match_operand:DI 0 "memory_operand" "=m")
20733 (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
20735 "TARGET_SSE || TARGET_3DNOW_A"
20736 "movntq\t{%1, %0|%0, %1}"
20737 [(set_attr "type" "mmxmov")
20738 (set_attr "mode" "DI")])
20740 (define_insn "sse_movhlps"
20741 [(set (match_operand:V4SF 0 "register_operand" "=x")
20743 (match_operand:V4SF 1 "register_operand" "0")
20744 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
20745 (parallel [(const_int 2)
20751 "movhlps\t{%2, %0|%0, %2}"
20752 [(set_attr "type" "ssecvt")
20753 (set_attr "mode" "V4SF")])
20755 (define_insn "sse_movlhps"
20756 [(set (match_operand:V4SF 0 "register_operand" "=x")
20758 (match_operand:V4SF 1 "register_operand" "0")
20759 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
20760 (parallel [(const_int 2)
20766 "movlhps\t{%2, %0|%0, %2}"
20767 [(set_attr "type" "ssecvt")
20768 (set_attr "mode" "V4SF")])
20770 (define_insn "sse_movhps"
20771 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
20773 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
20774 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
20777 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
20778 "movhps\t{%2, %0|%0, %2}"
20779 [(set_attr "type" "ssecvt")
20780 (set_attr "mode" "V4SF")])
20782 (define_insn "sse_movlps"
20783 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
20785 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
20786 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
20789 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
20790 "movlps\t{%2, %0|%0, %2}"
20791 [(set_attr "type" "ssecvt")
20792 (set_attr "mode" "V4SF")])
20794 (define_expand "sse_loadss"
20795 [(match_operand:V4SF 0 "register_operand" "")
20796 (match_operand:SF 1 "memory_operand" "")]
20799 emit_insn (gen_sse_loadss_1 (operands[0], operands[1],
20800 CONST0_RTX (V4SFmode)));
20804 (define_insn "sse_loadss_1"
20805 [(set (match_operand:V4SF 0 "register_operand" "=x")
20807 (vec_duplicate:V4SF (match_operand:SF 1 "memory_operand" "m"))
20808 (match_operand:V4SF 2 "const0_operand" "X")
20811 "movss\t{%1, %0|%0, %1}"
20812 [(set_attr "type" "ssemov")
20813 (set_attr "mode" "SF")])
20815 (define_insn "sse_movss"
20816 [(set (match_operand:V4SF 0 "register_operand" "=x")
20818 (match_operand:V4SF 1 "register_operand" "0")
20819 (match_operand:V4SF 2 "register_operand" "x")
20822 "movss\t{%2, %0|%0, %2}"
20823 [(set_attr "type" "ssemov")
20824 (set_attr "mode" "SF")])
20826 (define_insn "sse_storess"
20827 [(set (match_operand:SF 0 "memory_operand" "=m")
20829 (match_operand:V4SF 1 "register_operand" "x")
20830 (parallel [(const_int 0)])))]
20832 "movss\t{%1, %0|%0, %1}"
20833 [(set_attr "type" "ssemov")
20834 (set_attr "mode" "SF")])
20836 (define_insn "sse_shufps"
20837 [(set (match_operand:V4SF 0 "register_operand" "=x")
20838 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
20839 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
20840 (match_operand:SI 3 "immediate_operand" "i")]
20843 ;; @@@ check operand order for intel/nonintel syntax
20844 "shufps\t{%3, %2, %0|%0, %2, %3}"
20845 [(set_attr "type" "ssecvt")
20846 (set_attr "mode" "V4SF")])
20851 (define_insn "addv4sf3"
20852 [(set (match_operand:V4SF 0 "register_operand" "=x")
20853 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
20854 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20856 "addps\t{%2, %0|%0, %2}"
20857 [(set_attr "type" "sseadd")
20858 (set_attr "mode" "V4SF")])
20860 (define_insn "vmaddv4sf3"
20861 [(set (match_operand:V4SF 0 "register_operand" "=x")
20863 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
20864 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20868 "addss\t{%2, %0|%0, %2}"
20869 [(set_attr "type" "sseadd")
20870 (set_attr "mode" "SF")])
20872 (define_insn "subv4sf3"
20873 [(set (match_operand:V4SF 0 "register_operand" "=x")
20874 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
20875 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20877 "subps\t{%2, %0|%0, %2}"
20878 [(set_attr "type" "sseadd")
20879 (set_attr "mode" "V4SF")])
20881 (define_insn "vmsubv4sf3"
20882 [(set (match_operand:V4SF 0 "register_operand" "=x")
20884 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
20885 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20889 "subss\t{%2, %0|%0, %2}"
20890 [(set_attr "type" "sseadd")
20891 (set_attr "mode" "SF")])
20893 ;; ??? Should probably be done by generic code instead.
20894 (define_expand "negv4sf2"
20895 [(set (match_operand:V4SF 0 "register_operand" "")
20896 (xor:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")
20900 rtx m0 = gen_lowpart (SFmode, gen_int_mode (0x80000000, SImode));
20901 rtx vm0 = gen_rtx_CONST_VECTOR (V4SFmode, gen_rtvec (4, m0, m0, m0, m0));
20902 operands[2] = force_reg (V4SFmode, vm0);
20905 (define_insn "mulv4sf3"
20906 [(set (match_operand:V4SF 0 "register_operand" "=x")
20907 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
20908 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20910 "mulps\t{%2, %0|%0, %2}"
20911 [(set_attr "type" "ssemul")
20912 (set_attr "mode" "V4SF")])
20914 (define_insn "vmmulv4sf3"
20915 [(set (match_operand:V4SF 0 "register_operand" "=x")
20917 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
20918 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20922 "mulss\t{%2, %0|%0, %2}"
20923 [(set_attr "type" "ssemul")
20924 (set_attr "mode" "SF")])
20926 (define_insn "divv4sf3"
20927 [(set (match_operand:V4SF 0 "register_operand" "=x")
20928 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
20929 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20931 "divps\t{%2, %0|%0, %2}"
20932 [(set_attr "type" "ssediv")
20933 (set_attr "mode" "V4SF")])
20935 (define_insn "vmdivv4sf3"
20936 [(set (match_operand:V4SF 0 "register_operand" "=x")
20938 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
20939 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20943 "divss\t{%2, %0|%0, %2}"
20944 [(set_attr "type" "ssediv")
20945 (set_attr "mode" "SF")])
20948 ;; SSE square root/reciprocal
20950 (define_insn "rcpv4sf2"
20951 [(set (match_operand:V4SF 0 "register_operand" "=x")
20953 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
20955 "rcpps\t{%1, %0|%0, %1}"
20956 [(set_attr "type" "sse")
20957 (set_attr "mode" "V4SF")])
20959 (define_insn "vmrcpv4sf2"
20960 [(set (match_operand:V4SF 0 "register_operand" "=x")
20962 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
20964 (match_operand:V4SF 2 "register_operand" "0")
20967 "rcpss\t{%1, %0|%0, %1}"
20968 [(set_attr "type" "sse")
20969 (set_attr "mode" "SF")])
20971 (define_insn "rsqrtv4sf2"
20972 [(set (match_operand:V4SF 0 "register_operand" "=x")
20974 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
20976 "rsqrtps\t{%1, %0|%0, %1}"
20977 [(set_attr "type" "sse")
20978 (set_attr "mode" "V4SF")])
20980 (define_insn "vmrsqrtv4sf2"
20981 [(set (match_operand:V4SF 0 "register_operand" "=x")
20983 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
20985 (match_operand:V4SF 2 "register_operand" "0")
20988 "rsqrtss\t{%1, %0|%0, %1}"
20989 [(set_attr "type" "sse")
20990 (set_attr "mode" "SF")])
20992 (define_insn "sqrtv4sf2"
20993 [(set (match_operand:V4SF 0 "register_operand" "=x")
20994 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
20996 "sqrtps\t{%1, %0|%0, %1}"
20997 [(set_attr "type" "sse")
20998 (set_attr "mode" "V4SF")])
21000 (define_insn "vmsqrtv4sf2"
21001 [(set (match_operand:V4SF 0 "register_operand" "=x")
21003 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
21004 (match_operand:V4SF 2 "register_operand" "0")
21007 "sqrtss\t{%1, %0|%0, %1}"
21008 [(set_attr "type" "sse")
21009 (set_attr "mode" "SF")])
21011 ;; SSE logical operations.
21013 ;; SSE defines logical operations on floating point values. This brings
21014 ;; interesting challenge to RTL representation where logicals are only valid
21015 ;; on integral types. We deal with this by representing the floating point
21016 ;; logical as logical on arguments casted to TImode as this is what hardware
21017 ;; really does. Unfortunately hardware requires the type information to be
21018 ;; present and thus we must avoid subregs from being simplified and eliminated
21019 ;; in later compilation phases.
21021 ;; We have following variants from each instruction:
21022 ;; sse_andsf3 - the operation taking V4SF vector operands
21023 ;; and doing TImode cast on them
21024 ;; *sse_andsf3_memory - the operation taking one memory operand casted to
21025 ;; TImode, since backend insist on eliminating casts
21026 ;; on memory operands
21027 ;; sse_andti3_sf_1 - the operation taking SF scalar operands.
21028 ;; We cannot accept memory operand here as instruction reads
21029 ;; whole scalar. This is generated only post reload by GCC
21030 ;; scalar float operations that expands to logicals (fabs)
21031 ;; sse_andti3_sf_2 - the operation taking SF scalar input and TImode
21032 ;; memory operand. Eventually combine can be able
21033 ;; to synthesize these using splitter.
21034 ;; sse2_anddf3, *sse2_anddf3_memory
21037 ;; These are not called andti3 etc. because we really really don't want
21038 ;; the compiler to widen DImode ands to TImode ands and then try to move
21039 ;; into DImode subregs of SSE registers, and them together, and move out
21040 ;; of DImode subregs again!
21041 ;; SSE1 single precision floating point logical operation
21042 (define_expand "sse_andv4sf3"
21043 [(set (match_operand:V4SF 0 "register_operand" "")
21044 (and:V4SF (match_operand:V4SF 1 "register_operand" "")
21045 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
21049 (define_insn "*sse_andv4sf3"
21050 [(set (match_operand:V4SF 0 "register_operand" "=x")
21051 (and:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
21052 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
21054 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21055 "andps\t{%2, %0|%0, %2}"
21056 [(set_attr "type" "sselog")
21057 (set_attr "mode" "V4SF")])
21059 (define_expand "sse_nandv4sf3"
21060 [(set (match_operand:V4SF 0 "register_operand" "")
21061 (and:V4SF (not:V4SF (match_operand:V4SF 1 "register_operand" ""))
21062 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
21066 (define_insn "*sse_nandv4sf3"
21067 [(set (match_operand:V4SF 0 "register_operand" "=x")
21068 (and:V4SF (not:V4SF (match_operand:V4SF 1 "register_operand" "0"))
21069 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
21071 "andnps\t{%2, %0|%0, %2}"
21072 [(set_attr "type" "sselog")
21073 (set_attr "mode" "V4SF")])
21075 (define_expand "sse_iorv4sf3"
21076 [(set (match_operand:V4SF 0 "register_operand" "")
21077 (ior:V4SF (match_operand:V4SF 1 "register_operand" "")
21078 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
21082 (define_insn "*sse_iorv4sf3"
21083 [(set (match_operand:V4SF 0 "register_operand" "=x")
21084 (ior:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
21085 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
21087 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21088 "orps\t{%2, %0|%0, %2}"
21089 [(set_attr "type" "sselog")
21090 (set_attr "mode" "V4SF")])
21092 (define_expand "sse_xorv4sf3"
21093 [(set (match_operand:V4SF 0 "register_operand" "")
21094 (xor:V4SF (match_operand:V4SF 1 "register_operand" "")
21095 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
21099 (define_insn "*sse_xorv4sf3"
21100 [(set (match_operand:V4SF 0 "register_operand" "=x")
21101 (xor:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
21102 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
21104 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21105 "xorps\t{%2, %0|%0, %2}"
21106 [(set_attr "type" "sselog")
21107 (set_attr "mode" "V4SF")])
21109 ;; SSE2 double precision floating point logical operation
21111 (define_expand "sse2_andv2df3"
21112 [(set (match_operand:V2DF 0 "register_operand" "")
21113 (and:V2DF (match_operand:V2DF 1 "register_operand" "")
21114 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
21118 (define_insn "*sse2_andv2df3"
21119 [(set (match_operand:V2DF 0 "register_operand" "=x")
21120 (and:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
21121 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21123 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21124 "andpd\t{%2, %0|%0, %2}"
21125 [(set_attr "type" "sselog")
21126 (set_attr "mode" "V2DF")])
21128 (define_expand "sse2_nandv2df3"
21129 [(set (match_operand:V2DF 0 "register_operand" "")
21130 (and:V2DF (not:V2DF (match_operand:V2DF 1 "register_operand" ""))
21131 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
21135 (define_insn "*sse2_nandv2df3"
21136 [(set (match_operand:V2DF 0 "register_operand" "=x")
21137 (and:V2DF (not:V2DF (match_operand:V2DF 1 "register_operand" "0"))
21138 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21140 "andnpd\t{%2, %0|%0, %2}"
21141 [(set_attr "type" "sselog")
21142 (set_attr "mode" "V2DF")])
21144 (define_expand "sse2_iorv2df3"
21145 [(set (match_operand:V2DF 0 "register_operand" "")
21146 (ior:V2DF (match_operand:V2DF 1 "register_operand" "")
21147 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
21151 (define_insn "*sse2_iorv2df3"
21152 [(set (match_operand:V2DF 0 "register_operand" "=x")
21153 (ior:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
21154 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21156 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21157 "orpd\t{%2, %0|%0, %2}"
21158 [(set_attr "type" "sselog")
21159 (set_attr "mode" "V2DF")])
21161 (define_expand "sse2_xorv2df3"
21162 [(set (match_operand:V2DF 0 "register_operand" "")
21163 (xor:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "")
21164 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
21168 (define_insn "*sse2_xorv2df3"
21169 [(set (match_operand:V2DF 0 "register_operand" "=x")
21170 (xor:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
21171 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21173 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21174 "xorpd\t{%2, %0|%0, %2}"
21175 [(set_attr "type" "sselog")
21176 (set_attr "mode" "V2DF")])
21178 ;; SSE2 integral logicals. These patterns must always come after floating
21179 ;; point ones since we don't want compiler to use integer opcodes on floating
21180 ;; point SSE values to avoid matching of subregs in the match_operand.
21181 (define_insn "*sse2_andti3"
21182 [(set (match_operand:TI 0 "register_operand" "=x")
21183 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
21184 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
21186 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21187 "pand\t{%2, %0|%0, %2}"
21188 [(set_attr "type" "sselog")
21189 (set_attr "mode" "TI")])
21191 (define_insn "sse2_andv2di3"
21192 [(set (match_operand:V2DI 0 "register_operand" "=x")
21193 (and:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
21194 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
21196 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21197 "pand\t{%2, %0|%0, %2}"
21198 [(set_attr "type" "sselog")
21199 (set_attr "mode" "TI")])
21201 (define_insn "*sse2_nandti3"
21202 [(set (match_operand:TI 0 "register_operand" "=x")
21203 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
21204 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
21206 "pandn\t{%2, %0|%0, %2}"
21207 [(set_attr "type" "sselog")
21208 (set_attr "mode" "TI")])
21210 (define_insn "sse2_nandv2di3"
21211 [(set (match_operand:V2DI 0 "register_operand" "=x")
21212 (and:V2DI (not:V2DI (match_operand:V2DI 1 "register_operand" "0"))
21213 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
21215 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21216 "pandn\t{%2, %0|%0, %2}"
21217 [(set_attr "type" "sselog")
21218 (set_attr "mode" "TI")])
21220 (define_insn "*sse2_iorti3"
21221 [(set (match_operand:TI 0 "register_operand" "=x")
21222 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
21223 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
21225 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21226 "por\t{%2, %0|%0, %2}"
21227 [(set_attr "type" "sselog")
21228 (set_attr "mode" "TI")])
21230 (define_insn "sse2_iorv2di3"
21231 [(set (match_operand:V2DI 0 "register_operand" "=x")
21232 (ior:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
21233 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
21235 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21236 "por\t{%2, %0|%0, %2}"
21237 [(set_attr "type" "sselog")
21238 (set_attr "mode" "TI")])
21240 (define_insn "*sse2_xorti3"
21241 [(set (match_operand:TI 0 "register_operand" "=x")
21242 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
21243 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
21245 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21246 "pxor\t{%2, %0|%0, %2}"
21247 [(set_attr "type" "sselog")
21248 (set_attr "mode" "TI")])
21250 (define_insn "sse2_xorv2di3"
21251 [(set (match_operand:V2DI 0 "register_operand" "=x")
21252 (xor:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
21253 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
21255 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21256 "pxor\t{%2, %0|%0, %2}"
21257 [(set_attr "type" "sselog")
21258 (set_attr "mode" "TI")])
21260 ;; Use xor, but don't show input operands so they aren't live before
21262 (define_insn "sse_clrv4sf"
21263 [(set (match_operand:V4SF 0 "register_operand" "=x")
21264 (match_operand:V4SF 1 "const0_operand" "X"))]
21267 if (get_attr_mode (insn) == MODE_TI)
21268 return "pxor\t{%0, %0|%0, %0}";
21270 return "xorps\t{%0, %0|%0, %0}";
21272 [(set_attr "type" "sselog")
21273 (set_attr "memory" "none")
21276 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
21278 (ne (symbol_ref "TARGET_SSE2")
21280 (eq (symbol_ref "optimize_size")
21282 (const_string "TI")
21283 (const_string "V4SF")))])
21285 ;; Use xor, but don't show input operands so they aren't live before
21287 (define_insn "sse_clrv2df"
21288 [(set (match_operand:V2DF 0 "register_operand" "=x")
21289 (unspec:V2DF [(const_int 0)] UNSPEC_NOP))]
21291 "xorpd\t{%0, %0|%0, %0}"
21292 [(set_attr "type" "sselog")
21293 (set_attr "memory" "none")
21294 (set_attr "mode" "V4SF")])
21296 ;; SSE mask-generating compares
21298 (define_insn "maskcmpv4sf3"
21299 [(set (match_operand:V4SI 0 "register_operand" "=x")
21300 (match_operator:V4SI 3 "sse_comparison_operator"
21301 [(match_operand:V4SF 1 "register_operand" "0")
21302 (match_operand:V4SF 2 "register_operand" "x")]))]
21304 "cmp%D3ps\t{%2, %0|%0, %2}"
21305 [(set_attr "type" "ssecmp")
21306 (set_attr "mode" "V4SF")])
21308 (define_insn "maskncmpv4sf3"
21309 [(set (match_operand:V4SI 0 "register_operand" "=x")
21311 (match_operator:V4SI 3 "sse_comparison_operator"
21312 [(match_operand:V4SF 1 "register_operand" "0")
21313 (match_operand:V4SF 2 "register_operand" "x")])))]
21316 if (GET_CODE (operands[3]) == UNORDERED)
21317 return "cmpordps\t{%2, %0|%0, %2}";
21319 return "cmpn%D3ps\t{%2, %0|%0, %2}";
21321 [(set_attr "type" "ssecmp")
21322 (set_attr "mode" "V4SF")])
21324 (define_insn "vmmaskcmpv4sf3"
21325 [(set (match_operand:V4SI 0 "register_operand" "=x")
21327 (match_operator:V4SI 3 "sse_comparison_operator"
21328 [(match_operand:V4SF 1 "register_operand" "0")
21329 (match_operand:V4SF 2 "register_operand" "x")])
21330 (subreg:V4SI (match_dup 1) 0)
21333 "cmp%D3ss\t{%2, %0|%0, %2}"
21334 [(set_attr "type" "ssecmp")
21335 (set_attr "mode" "SF")])
21337 (define_insn "vmmaskncmpv4sf3"
21338 [(set (match_operand:V4SI 0 "register_operand" "=x")
21341 (match_operator:V4SI 3 "sse_comparison_operator"
21342 [(match_operand:V4SF 1 "register_operand" "0")
21343 (match_operand:V4SF 2 "register_operand" "x")]))
21344 (subreg:V4SI (match_dup 1) 0)
21348 if (GET_CODE (operands[3]) == UNORDERED)
21349 return "cmpordss\t{%2, %0|%0, %2}";
21351 return "cmpn%D3ss\t{%2, %0|%0, %2}";
21353 [(set_attr "type" "ssecmp")
21354 (set_attr "mode" "SF")])
21356 (define_insn "sse_comi"
21357 [(set (reg:CCFP FLAGS_REG)
21358 (compare:CCFP (vec_select:SF
21359 (match_operand:V4SF 0 "register_operand" "x")
21360 (parallel [(const_int 0)]))
21362 (match_operand:V4SF 1 "register_operand" "x")
21363 (parallel [(const_int 0)]))))]
21365 "comiss\t{%1, %0|%0, %1}"
21366 [(set_attr "type" "ssecomi")
21367 (set_attr "mode" "SF")])
21369 (define_insn "sse_ucomi"
21370 [(set (reg:CCFPU FLAGS_REG)
21371 (compare:CCFPU (vec_select:SF
21372 (match_operand:V4SF 0 "register_operand" "x")
21373 (parallel [(const_int 0)]))
21375 (match_operand:V4SF 1 "register_operand" "x")
21376 (parallel [(const_int 0)]))))]
21378 "ucomiss\t{%1, %0|%0, %1}"
21379 [(set_attr "type" "ssecomi")
21380 (set_attr "mode" "SF")])
21385 (define_insn "sse_unpckhps"
21386 [(set (match_operand:V4SF 0 "register_operand" "=x")
21388 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
21389 (parallel [(const_int 2)
21393 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
21394 (parallel [(const_int 0)
21400 "unpckhps\t{%2, %0|%0, %2}"
21401 [(set_attr "type" "ssecvt")
21402 (set_attr "mode" "V4SF")])
21404 (define_insn "sse_unpcklps"
21405 [(set (match_operand:V4SF 0 "register_operand" "=x")
21407 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
21408 (parallel [(const_int 0)
21412 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
21413 (parallel [(const_int 2)
21419 "unpcklps\t{%2, %0|%0, %2}"
21420 [(set_attr "type" "ssecvt")
21421 (set_attr "mode" "V4SF")])
21426 (define_insn "smaxv4sf3"
21427 [(set (match_operand:V4SF 0 "register_operand" "=x")
21428 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
21429 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
21431 "maxps\t{%2, %0|%0, %2}"
21432 [(set_attr "type" "sse")
21433 (set_attr "mode" "V4SF")])
21435 (define_insn "vmsmaxv4sf3"
21436 [(set (match_operand:V4SF 0 "register_operand" "=x")
21438 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
21439 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
21443 "maxss\t{%2, %0|%0, %2}"
21444 [(set_attr "type" "sse")
21445 (set_attr "mode" "SF")])
21447 (define_insn "sminv4sf3"
21448 [(set (match_operand:V4SF 0 "register_operand" "=x")
21449 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
21450 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
21452 "minps\t{%2, %0|%0, %2}"
21453 [(set_attr "type" "sse")
21454 (set_attr "mode" "V4SF")])
21456 (define_insn "vmsminv4sf3"
21457 [(set (match_operand:V4SF 0 "register_operand" "=x")
21459 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
21460 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
21464 "minss\t{%2, %0|%0, %2}"
21465 [(set_attr "type" "sse")
21466 (set_attr "mode" "SF")])
21468 ;; SSE <-> integer/MMX conversions
21470 (define_insn "cvtpi2ps"
21471 [(set (match_operand:V4SF 0 "register_operand" "=x")
21473 (match_operand:V4SF 1 "register_operand" "0")
21474 (vec_duplicate:V4SF
21475 (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
21478 "cvtpi2ps\t{%2, %0|%0, %2}"
21479 [(set_attr "type" "ssecvt")
21480 (set_attr "mode" "V4SF")])
21482 (define_insn "cvtps2pi"
21483 [(set (match_operand:V2SI 0 "register_operand" "=y")
21485 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
21486 (parallel [(const_int 0) (const_int 1)])))]
21488 "cvtps2pi\t{%1, %0|%0, %1}"
21489 [(set_attr "type" "ssecvt")
21490 (set_attr "mode" "V4SF")])
21492 (define_insn "cvttps2pi"
21493 [(set (match_operand:V2SI 0 "register_operand" "=y")
21495 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
21497 (parallel [(const_int 0) (const_int 1)])))]
21499 "cvttps2pi\t{%1, %0|%0, %1}"
21500 [(set_attr "type" "ssecvt")
21501 (set_attr "mode" "SF")])
21503 (define_insn "cvtsi2ss"
21504 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
21506 (match_operand:V4SF 1 "register_operand" "0,0")
21507 (vec_duplicate:V4SF
21508 (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
21511 "cvtsi2ss\t{%2, %0|%0, %2}"
21512 [(set_attr "type" "sseicvt")
21513 (set_attr "athlon_decode" "vector,double")
21514 (set_attr "mode" "SF")])
21516 (define_insn "cvtsi2ssq"
21517 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
21519 (match_operand:V4SF 1 "register_operand" "0,0")
21520 (vec_duplicate:V4SF
21521 (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
21523 "TARGET_SSE && TARGET_64BIT"
21524 "cvtsi2ssq\t{%2, %0|%0, %2}"
21525 [(set_attr "type" "sseicvt")
21526 (set_attr "athlon_decode" "vector,double")
21527 (set_attr "mode" "SF")])
21529 (define_insn "cvtss2si"
21530 [(set (match_operand:SI 0 "register_operand" "=r,r")
21532 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
21533 (parallel [(const_int 0)])))]
21535 "cvtss2si\t{%1, %0|%0, %1}"
21536 [(set_attr "type" "sseicvt")
21537 (set_attr "athlon_decode" "double,vector")
21538 (set_attr "mode" "SI")])
21540 (define_insn "cvtss2siq"
21541 [(set (match_operand:DI 0 "register_operand" "=r,r")
21543 (fix:V4DI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
21544 (parallel [(const_int 0)])))]
21546 "cvtss2siq\t{%1, %0|%0, %1}"
21547 [(set_attr "type" "sseicvt")
21548 (set_attr "athlon_decode" "double,vector")
21549 (set_attr "mode" "DI")])
21551 (define_insn "cvttss2si"
21552 [(set (match_operand:SI 0 "register_operand" "=r,r")
21554 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
21556 (parallel [(const_int 0)])))]
21558 "cvttss2si\t{%1, %0|%0, %1}"
21559 [(set_attr "type" "sseicvt")
21560 (set_attr "mode" "SF")
21561 (set_attr "athlon_decode" "double,vector")])
21563 (define_insn "cvttss2siq"
21564 [(set (match_operand:DI 0 "register_operand" "=r,r")
21566 (unspec:V4DI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
21568 (parallel [(const_int 0)])))]
21569 "TARGET_SSE && TARGET_64BIT"
21570 "cvttss2siq\t{%1, %0|%0, %1}"
21571 [(set_attr "type" "sseicvt")
21572 (set_attr "mode" "SF")
21573 (set_attr "athlon_decode" "double,vector")])
21580 (define_insn "addv8qi3"
21581 [(set (match_operand:V8QI 0 "register_operand" "=y")
21582 (plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
21583 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21585 "paddb\t{%2, %0|%0, %2}"
21586 [(set_attr "type" "mmxadd")
21587 (set_attr "mode" "DI")])
21589 (define_insn "addv4hi3"
21590 [(set (match_operand:V4HI 0 "register_operand" "=y")
21591 (plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
21592 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21594 "paddw\t{%2, %0|%0, %2}"
21595 [(set_attr "type" "mmxadd")
21596 (set_attr "mode" "DI")])
21598 (define_insn "addv2si3"
21599 [(set (match_operand:V2SI 0 "register_operand" "=y")
21600 (plus:V2SI (match_operand:V2SI 1 "register_operand" "%0")
21601 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
21603 "paddd\t{%2, %0|%0, %2}"
21604 [(set_attr "type" "mmxadd")
21605 (set_attr "mode" "DI")])
21607 (define_insn "mmx_adddi3"
21608 [(set (match_operand:DI 0 "register_operand" "=y")
21610 [(plus:DI (match_operand:DI 1 "register_operand" "%0")
21611 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21614 "paddq\t{%2, %0|%0, %2}"
21615 [(set_attr "type" "mmxadd")
21616 (set_attr "mode" "DI")])
21618 (define_insn "ssaddv8qi3"
21619 [(set (match_operand:V8QI 0 "register_operand" "=y")
21620 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
21621 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21623 "paddsb\t{%2, %0|%0, %2}"
21624 [(set_attr "type" "mmxadd")
21625 (set_attr "mode" "DI")])
21627 (define_insn "ssaddv4hi3"
21628 [(set (match_operand:V4HI 0 "register_operand" "=y")
21629 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
21630 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21632 "paddsw\t{%2, %0|%0, %2}"
21633 [(set_attr "type" "mmxadd")
21634 (set_attr "mode" "DI")])
21636 (define_insn "usaddv8qi3"
21637 [(set (match_operand:V8QI 0 "register_operand" "=y")
21638 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
21639 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21641 "paddusb\t{%2, %0|%0, %2}"
21642 [(set_attr "type" "mmxadd")
21643 (set_attr "mode" "DI")])
21645 (define_insn "usaddv4hi3"
21646 [(set (match_operand:V4HI 0 "register_operand" "=y")
21647 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
21648 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21650 "paddusw\t{%2, %0|%0, %2}"
21651 [(set_attr "type" "mmxadd")
21652 (set_attr "mode" "DI")])
21654 (define_insn "subv8qi3"
21655 [(set (match_operand:V8QI 0 "register_operand" "=y")
21656 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
21657 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21659 "psubb\t{%2, %0|%0, %2}"
21660 [(set_attr "type" "mmxadd")
21661 (set_attr "mode" "DI")])
21663 (define_insn "subv4hi3"
21664 [(set (match_operand:V4HI 0 "register_operand" "=y")
21665 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
21666 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21668 "psubw\t{%2, %0|%0, %2}"
21669 [(set_attr "type" "mmxadd")
21670 (set_attr "mode" "DI")])
21672 (define_insn "subv2si3"
21673 [(set (match_operand:V2SI 0 "register_operand" "=y")
21674 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
21675 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
21677 "psubd\t{%2, %0|%0, %2}"
21678 [(set_attr "type" "mmxadd")
21679 (set_attr "mode" "DI")])
21681 (define_insn "mmx_subdi3"
21682 [(set (match_operand:DI 0 "register_operand" "=y")
21684 [(minus:DI (match_operand:DI 1 "register_operand" "0")
21685 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21688 "psubq\t{%2, %0|%0, %2}"
21689 [(set_attr "type" "mmxadd")
21690 (set_attr "mode" "DI")])
21692 (define_insn "sssubv8qi3"
21693 [(set (match_operand:V8QI 0 "register_operand" "=y")
21694 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
21695 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21697 "psubsb\t{%2, %0|%0, %2}"
21698 [(set_attr "type" "mmxadd")
21699 (set_attr "mode" "DI")])
21701 (define_insn "sssubv4hi3"
21702 [(set (match_operand:V4HI 0 "register_operand" "=y")
21703 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
21704 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21706 "psubsw\t{%2, %0|%0, %2}"
21707 [(set_attr "type" "mmxadd")
21708 (set_attr "mode" "DI")])
21710 (define_insn "ussubv8qi3"
21711 [(set (match_operand:V8QI 0 "register_operand" "=y")
21712 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
21713 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21715 "psubusb\t{%2, %0|%0, %2}"
21716 [(set_attr "type" "mmxadd")
21717 (set_attr "mode" "DI")])
21719 (define_insn "ussubv4hi3"
21720 [(set (match_operand:V4HI 0 "register_operand" "=y")
21721 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
21722 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21724 "psubusw\t{%2, %0|%0, %2}"
21725 [(set_attr "type" "mmxadd")
21726 (set_attr "mode" "DI")])
21728 (define_insn "mulv4hi3"
21729 [(set (match_operand:V4HI 0 "register_operand" "=y")
21730 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
21731 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21733 "pmullw\t{%2, %0|%0, %2}"
21734 [(set_attr "type" "mmxmul")
21735 (set_attr "mode" "DI")])
21737 (define_insn "smulv4hi3_highpart"
21738 [(set (match_operand:V4HI 0 "register_operand" "=y")
21741 (mult:V4SI (sign_extend:V4SI
21742 (match_operand:V4HI 1 "register_operand" "0"))
21744 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
21747 "pmulhw\t{%2, %0|%0, %2}"
21748 [(set_attr "type" "mmxmul")
21749 (set_attr "mode" "DI")])
21751 (define_insn "umulv4hi3_highpart"
21752 [(set (match_operand:V4HI 0 "register_operand" "=y")
21755 (mult:V4SI (zero_extend:V4SI
21756 (match_operand:V4HI 1 "register_operand" "0"))
21758 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
21760 "TARGET_SSE || TARGET_3DNOW_A"
21761 "pmulhuw\t{%2, %0|%0, %2}"
21762 [(set_attr "type" "mmxmul")
21763 (set_attr "mode" "DI")])
21765 (define_insn "mmx_pmaddwd"
21766 [(set (match_operand:V2SI 0 "register_operand" "=y")
21770 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
21771 (parallel [(const_int 0) (const_int 2)])))
21773 (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
21774 (parallel [(const_int 0) (const_int 2)]))))
21776 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
21777 (parallel [(const_int 1)
21779 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
21780 (parallel [(const_int 1)
21781 (const_int 3)]))))))]
21783 "pmaddwd\t{%2, %0|%0, %2}"
21784 [(set_attr "type" "mmxmul")
21785 (set_attr "mode" "DI")])
21788 ;; MMX logical operations
21789 ;; Note we don't want to declare these as regular iordi3 insns to prevent
21790 ;; normal code that also wants to use the FPU from getting broken.
21791 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
21792 (define_insn "mmx_iordi3"
21793 [(set (match_operand:DI 0 "register_operand" "=y")
21795 [(ior:DI (match_operand:DI 1 "register_operand" "%0")
21796 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21799 "por\t{%2, %0|%0, %2}"
21800 [(set_attr "type" "mmxadd")
21801 (set_attr "mode" "DI")])
21803 (define_insn "mmx_xordi3"
21804 [(set (match_operand:DI 0 "register_operand" "=y")
21806 [(xor:DI (match_operand:DI 1 "register_operand" "%0")
21807 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21810 "pxor\t{%2, %0|%0, %2}"
21811 [(set_attr "type" "mmxadd")
21812 (set_attr "mode" "DI")
21813 (set_attr "memory" "none")])
21815 ;; Same as pxor, but don't show input operands so that we don't think
21817 (define_insn "mmx_clrdi"
21818 [(set (match_operand:DI 0 "register_operand" "=y")
21819 (unspec:DI [(const_int 0)] UNSPEC_NOP))]
21821 "pxor\t{%0, %0|%0, %0}"
21822 [(set_attr "type" "mmxadd")
21823 (set_attr "mode" "DI")
21824 (set_attr "memory" "none")])
21826 (define_insn "mmx_anddi3"
21827 [(set (match_operand:DI 0 "register_operand" "=y")
21829 [(and:DI (match_operand:DI 1 "register_operand" "%0")
21830 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21833 "pand\t{%2, %0|%0, %2}"
21834 [(set_attr "type" "mmxadd")
21835 (set_attr "mode" "DI")])
21837 (define_insn "mmx_nanddi3"
21838 [(set (match_operand:DI 0 "register_operand" "=y")
21840 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
21841 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21844 "pandn\t{%2, %0|%0, %2}"
21845 [(set_attr "type" "mmxadd")
21846 (set_attr "mode" "DI")])
21849 ;; MMX unsigned averages/sum of absolute differences
21851 (define_insn "mmx_uavgv8qi3"
21852 [(set (match_operand:V8QI 0 "register_operand" "=y")
21854 (plus:V8QI (plus:V8QI
21855 (match_operand:V8QI 1 "register_operand" "0")
21856 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
21857 (const_vector:V8QI [(const_int 1)
21866 "TARGET_SSE || TARGET_3DNOW_A"
21867 "pavgb\t{%2, %0|%0, %2}"
21868 [(set_attr "type" "mmxshft")
21869 (set_attr "mode" "DI")])
21871 (define_insn "mmx_uavgv4hi3"
21872 [(set (match_operand:V4HI 0 "register_operand" "=y")
21874 (plus:V4HI (plus:V4HI
21875 (match_operand:V4HI 1 "register_operand" "0")
21876 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
21877 (const_vector:V4HI [(const_int 1)
21882 "TARGET_SSE || TARGET_3DNOW_A"
21883 "pavgw\t{%2, %0|%0, %2}"
21884 [(set_attr "type" "mmxshft")
21885 (set_attr "mode" "DI")])
21887 (define_insn "mmx_psadbw"
21888 [(set (match_operand:DI 0 "register_operand" "=y")
21889 (unspec:DI [(match_operand:V8QI 1 "register_operand" "0")
21890 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
21892 "TARGET_SSE || TARGET_3DNOW_A"
21893 "psadbw\t{%2, %0|%0, %2}"
21894 [(set_attr "type" "mmxshft")
21895 (set_attr "mode" "DI")])
21898 ;; MMX insert/extract/shuffle
21900 (define_insn "mmx_pinsrw"
21901 [(set (match_operand:V4HI 0 "register_operand" "=y")
21902 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
21903 (vec_duplicate:V4HI
21904 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
21905 (match_operand:SI 3 "const_0_to_15_operand" "N")))]
21906 "TARGET_SSE || TARGET_3DNOW_A"
21907 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
21908 [(set_attr "type" "mmxcvt")
21909 (set_attr "mode" "DI")])
21911 (define_insn "mmx_pextrw"
21912 [(set (match_operand:SI 0 "register_operand" "=r")
21913 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
21915 [(match_operand:SI 2 "const_0_to_3_operand" "N")]))))]
21916 "TARGET_SSE || TARGET_3DNOW_A"
21917 "pextrw\t{%2, %1, %0|%0, %1, %2}"
21918 [(set_attr "type" "mmxcvt")
21919 (set_attr "mode" "DI")])
21921 (define_insn "mmx_pshufw"
21922 [(set (match_operand:V4HI 0 "register_operand" "=y")
21923 (unspec:V4HI [(match_operand:V4HI 1 "nonimmediate_operand" "ym")
21924 (match_operand:SI 2 "immediate_operand" "i")]
21926 "TARGET_SSE || TARGET_3DNOW_A"
21927 "pshufw\t{%2, %1, %0|%0, %1, %2}"
21928 [(set_attr "type" "mmxcvt")
21929 (set_attr "mode" "DI")])
21932 ;; MMX mask-generating comparisons
21934 (define_insn "eqv8qi3"
21935 [(set (match_operand:V8QI 0 "register_operand" "=y")
21936 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
21937 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21939 "pcmpeqb\t{%2, %0|%0, %2}"
21940 [(set_attr "type" "mmxcmp")
21941 (set_attr "mode" "DI")])
21943 (define_insn "eqv4hi3"
21944 [(set (match_operand:V4HI 0 "register_operand" "=y")
21945 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
21946 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21948 "pcmpeqw\t{%2, %0|%0, %2}"
21949 [(set_attr "type" "mmxcmp")
21950 (set_attr "mode" "DI")])
21952 (define_insn "eqv2si3"
21953 [(set (match_operand:V2SI 0 "register_operand" "=y")
21954 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
21955 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
21957 "pcmpeqd\t{%2, %0|%0, %2}"
21958 [(set_attr "type" "mmxcmp")
21959 (set_attr "mode" "DI")])
21961 (define_insn "gtv8qi3"
21962 [(set (match_operand:V8QI 0 "register_operand" "=y")
21963 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
21964 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21966 "pcmpgtb\t{%2, %0|%0, %2}"
21967 [(set_attr "type" "mmxcmp")
21968 (set_attr "mode" "DI")])
21970 (define_insn "gtv4hi3"
21971 [(set (match_operand:V4HI 0 "register_operand" "=y")
21972 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
21973 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21975 "pcmpgtw\t{%2, %0|%0, %2}"
21976 [(set_attr "type" "mmxcmp")
21977 (set_attr "mode" "DI")])
21979 (define_insn "gtv2si3"
21980 [(set (match_operand:V2SI 0 "register_operand" "=y")
21981 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
21982 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
21984 "pcmpgtd\t{%2, %0|%0, %2}"
21985 [(set_attr "type" "mmxcmp")
21986 (set_attr "mode" "DI")])
21989 ;; MMX max/min insns
21991 (define_insn "umaxv8qi3"
21992 [(set (match_operand:V8QI 0 "register_operand" "=y")
21993 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
21994 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21995 "TARGET_SSE || TARGET_3DNOW_A"
21996 "pmaxub\t{%2, %0|%0, %2}"
21997 [(set_attr "type" "mmxadd")
21998 (set_attr "mode" "DI")])
22000 (define_insn "smaxv4hi3"
22001 [(set (match_operand:V4HI 0 "register_operand" "=y")
22002 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
22003 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
22004 "TARGET_SSE || TARGET_3DNOW_A"
22005 "pmaxsw\t{%2, %0|%0, %2}"
22006 [(set_attr "type" "mmxadd")
22007 (set_attr "mode" "DI")])
22009 (define_insn "uminv8qi3"
22010 [(set (match_operand:V8QI 0 "register_operand" "=y")
22011 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
22012 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
22013 "TARGET_SSE || TARGET_3DNOW_A"
22014 "pminub\t{%2, %0|%0, %2}"
22015 [(set_attr "type" "mmxadd")
22016 (set_attr "mode" "DI")])
22018 (define_insn "sminv4hi3"
22019 [(set (match_operand:V4HI 0 "register_operand" "=y")
22020 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
22021 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
22022 "TARGET_SSE || TARGET_3DNOW_A"
22023 "pminsw\t{%2, %0|%0, %2}"
22024 [(set_attr "type" "mmxadd")
22025 (set_attr "mode" "DI")])
22030 (define_insn "ashrv4hi3"
22031 [(set (match_operand:V4HI 0 "register_operand" "=y")
22032 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
22033 (match_operand:DI 2 "nonmemory_operand" "yi")))]
22035 "psraw\t{%2, %0|%0, %2}"
22036 [(set_attr "type" "mmxshft")
22037 (set_attr "mode" "DI")])
22039 (define_insn "ashrv2si3"
22040 [(set (match_operand:V2SI 0 "register_operand" "=y")
22041 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
22042 (match_operand:DI 2 "nonmemory_operand" "yi")))]
22044 "psrad\t{%2, %0|%0, %2}"
22045 [(set_attr "type" "mmxshft")
22046 (set_attr "mode" "DI")])
22048 (define_insn "lshrv4hi3"
22049 [(set (match_operand:V4HI 0 "register_operand" "=y")
22050 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
22051 (match_operand:DI 2 "nonmemory_operand" "yi")))]
22053 "psrlw\t{%2, %0|%0, %2}"
22054 [(set_attr "type" "mmxshft")
22055 (set_attr "mode" "DI")])
22057 (define_insn "lshrv2si3"
22058 [(set (match_operand:V2SI 0 "register_operand" "=y")
22059 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
22060 (match_operand:DI 2 "nonmemory_operand" "yi")))]
22062 "psrld\t{%2, %0|%0, %2}"
22063 [(set_attr "type" "mmxshft")
22064 (set_attr "mode" "DI")])
22066 ;; See logical MMX insns.
22067 (define_insn "mmx_lshrdi3"
22068 [(set (match_operand:DI 0 "register_operand" "=y")
22070 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
22071 (match_operand:DI 2 "nonmemory_operand" "yi"))]
22074 "psrlq\t{%2, %0|%0, %2}"
22075 [(set_attr "type" "mmxshft")
22076 (set_attr "mode" "DI")])
22078 (define_insn "ashlv4hi3"
22079 [(set (match_operand:V4HI 0 "register_operand" "=y")
22080 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
22081 (match_operand:DI 2 "nonmemory_operand" "yi")))]
22083 "psllw\t{%2, %0|%0, %2}"
22084 [(set_attr "type" "mmxshft")
22085 (set_attr "mode" "DI")])
22087 (define_insn "ashlv2si3"
22088 [(set (match_operand:V2SI 0 "register_operand" "=y")
22089 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
22090 (match_operand:DI 2 "nonmemory_operand" "yi")))]
22092 "pslld\t{%2, %0|%0, %2}"
22093 [(set_attr "type" "mmxshft")
22094 (set_attr "mode" "DI")])
22096 ;; See logical MMX insns.
22097 (define_insn "mmx_ashldi3"
22098 [(set (match_operand:DI 0 "register_operand" "=y")
22100 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
22101 (match_operand:DI 2 "nonmemory_operand" "yi"))]
22104 "psllq\t{%2, %0|%0, %2}"
22105 [(set_attr "type" "mmxshft")
22106 (set_attr "mode" "DI")])
22109 ;; MMX pack/unpack insns.
22111 (define_insn "mmx_packsswb"
22112 [(set (match_operand:V8QI 0 "register_operand" "=y")
22114 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
22115 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
22117 "packsswb\t{%2, %0|%0, %2}"
22118 [(set_attr "type" "mmxshft")
22119 (set_attr "mode" "DI")])
22121 (define_insn "mmx_packssdw"
22122 [(set (match_operand:V4HI 0 "register_operand" "=y")
22124 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
22125 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
22127 "packssdw\t{%2, %0|%0, %2}"
22128 [(set_attr "type" "mmxshft")
22129 (set_attr "mode" "DI")])
22131 (define_insn "mmx_packuswb"
22132 [(set (match_operand:V8QI 0 "register_operand" "=y")
22134 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
22135 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
22137 "packuswb\t{%2, %0|%0, %2}"
22138 [(set_attr "type" "mmxshft")
22139 (set_attr "mode" "DI")])
22141 (define_insn "mmx_punpckhbw"
22142 [(set (match_operand:V8QI 0 "register_operand" "=y")
22144 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
22145 (parallel [(const_int 4)
22153 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
22154 (parallel [(const_int 0)
22164 "punpckhbw\t{%2, %0|%0, %2}"
22165 [(set_attr "type" "mmxcvt")
22166 (set_attr "mode" "DI")])
22168 (define_insn "mmx_punpckhwd"
22169 [(set (match_operand:V4HI 0 "register_operand" "=y")
22171 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
22172 (parallel [(const_int 0)
22176 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
22177 (parallel [(const_int 2)
22183 "punpckhwd\t{%2, %0|%0, %2}"
22184 [(set_attr "type" "mmxcvt")
22185 (set_attr "mode" "DI")])
22187 (define_insn "mmx_punpckhdq"
22188 [(set (match_operand:V2SI 0 "register_operand" "=y")
22190 (match_operand:V2SI 1 "register_operand" "0")
22191 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
22192 (parallel [(const_int 1)
22196 "punpckhdq\t{%2, %0|%0, %2}"
22197 [(set_attr "type" "mmxcvt")
22198 (set_attr "mode" "DI")])
22200 (define_insn "mmx_punpcklbw"
22201 [(set (match_operand:V8QI 0 "register_operand" "=y")
22203 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
22204 (parallel [(const_int 0)
22212 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
22213 (parallel [(const_int 4)
22223 "punpcklbw\t{%2, %0|%0, %2}"
22224 [(set_attr "type" "mmxcvt")
22225 (set_attr "mode" "DI")])
22227 (define_insn "mmx_punpcklwd"
22228 [(set (match_operand:V4HI 0 "register_operand" "=y")
22230 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
22231 (parallel [(const_int 2)
22235 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
22236 (parallel [(const_int 0)
22242 "punpcklwd\t{%2, %0|%0, %2}"
22243 [(set_attr "type" "mmxcvt")
22244 (set_attr "mode" "DI")])
22246 (define_insn "mmx_punpckldq"
22247 [(set (match_operand:V2SI 0 "register_operand" "=y")
22249 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
22250 (parallel [(const_int 1)
22252 (match_operand:V2SI 2 "register_operand" "y")
22255 "punpckldq\t{%2, %0|%0, %2}"
22256 [(set_attr "type" "mmxcvt")
22257 (set_attr "mode" "DI")])
22260 ;; Miscellaneous stuff
22262 (define_insn "emms"
22263 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
22264 (clobber (reg:XF 8))
22265 (clobber (reg:XF 9))
22266 (clobber (reg:XF 10))
22267 (clobber (reg:XF 11))
22268 (clobber (reg:XF 12))
22269 (clobber (reg:XF 13))
22270 (clobber (reg:XF 14))
22271 (clobber (reg:XF 15))
22272 (clobber (reg:DI 29))
22273 (clobber (reg:DI 30))
22274 (clobber (reg:DI 31))
22275 (clobber (reg:DI 32))
22276 (clobber (reg:DI 33))
22277 (clobber (reg:DI 34))
22278 (clobber (reg:DI 35))
22279 (clobber (reg:DI 36))]
22282 [(set_attr "type" "mmx")
22283 (set_attr "memory" "unknown")])
22285 (define_insn "ldmxcsr"
22286 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
22290 [(set_attr "type" "sse")
22291 (set_attr "memory" "load")])
22293 (define_insn "stmxcsr"
22294 [(set (match_operand:SI 0 "memory_operand" "=m")
22295 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
22298 [(set_attr "type" "sse")
22299 (set_attr "memory" "store")])
22301 (define_expand "sfence"
22302 [(set (match_dup 0)
22303 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
22304 "TARGET_SSE || TARGET_3DNOW_A"
22306 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
22307 MEM_VOLATILE_P (operands[0]) = 1;
22310 (define_insn "*sfence_insn"
22311 [(set (match_operand:BLK 0 "" "")
22312 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
22313 "TARGET_SSE || TARGET_3DNOW_A"
22315 [(set_attr "type" "sse")
22316 (set_attr "memory" "unknown")])
22318 (define_expand "sse_prologue_save"
22319 [(parallel [(set (match_operand:BLK 0 "" "")
22320 (unspec:BLK [(reg:DI 21)
22327 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
22328 (use (match_operand:DI 1 "register_operand" ""))
22329 (use (match_operand:DI 2 "immediate_operand" ""))
22330 (use (label_ref:DI (match_operand 3 "" "")))])]
22334 (define_insn "*sse_prologue_save_insn"
22335 [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
22336 (match_operand:DI 4 "const_int_operand" "n")))
22337 (unspec:BLK [(reg:DI 21)
22344 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
22345 (use (match_operand:DI 1 "register_operand" "r"))
22346 (use (match_operand:DI 2 "const_int_operand" "i"))
22347 (use (label_ref:DI (match_operand 3 "" "X")))]
22349 && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
22350 && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
22354 operands[0] = gen_rtx_MEM (Pmode,
22355 gen_rtx_PLUS (Pmode, operands[0], operands[4]));
22356 output_asm_insn (\"jmp\\t%A1\", operands);
22357 for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
22359 operands[4] = adjust_address (operands[0], DImode, i*16);
22360 operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
22361 PUT_MODE (operands[4], TImode);
22362 if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
22363 output_asm_insn (\"rex\", operands);
22364 output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
22366 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
22367 CODE_LABEL_NUMBER (operands[3]));
22371 [(set_attr "type" "other")
22372 (set_attr "length_immediate" "0")
22373 (set_attr "length_address" "0")
22374 (set_attr "length" "135")
22375 (set_attr "memory" "store")
22376 (set_attr "modrm" "0")
22377 (set_attr "mode" "DI")])
22379 ;; 3Dnow! instructions
22381 (define_insn "addv2sf3"
22382 [(set (match_operand:V2SF 0 "register_operand" "=y")
22383 (plus:V2SF (match_operand:V2SF 1 "register_operand" "0")
22384 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22386 "pfadd\\t{%2, %0|%0, %2}"
22387 [(set_attr "type" "mmxadd")
22388 (set_attr "mode" "V2SF")])
22390 (define_insn "subv2sf3"
22391 [(set (match_operand:V2SF 0 "register_operand" "=y")
22392 (minus:V2SF (match_operand:V2SF 1 "register_operand" "0")
22393 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22395 "pfsub\\t{%2, %0|%0, %2}"
22396 [(set_attr "type" "mmxadd")
22397 (set_attr "mode" "V2SF")])
22399 (define_insn "subrv2sf3"
22400 [(set (match_operand:V2SF 0 "register_operand" "=y")
22401 (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym")
22402 (match_operand:V2SF 1 "register_operand" "0")))]
22404 "pfsubr\\t{%2, %0|%0, %2}"
22405 [(set_attr "type" "mmxadd")
22406 (set_attr "mode" "V2SF")])
22408 (define_insn "gtv2sf3"
22409 [(set (match_operand:V2SI 0 "register_operand" "=y")
22410 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
22411 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22413 "pfcmpgt\\t{%2, %0|%0, %2}"
22414 [(set_attr "type" "mmxcmp")
22415 (set_attr "mode" "V2SF")])
22417 (define_insn "gev2sf3"
22418 [(set (match_operand:V2SI 0 "register_operand" "=y")
22419 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
22420 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22422 "pfcmpge\\t{%2, %0|%0, %2}"
22423 [(set_attr "type" "mmxcmp")
22424 (set_attr "mode" "V2SF")])
22426 (define_insn "eqv2sf3"
22427 [(set (match_operand:V2SI 0 "register_operand" "=y")
22428 (eq:V2SI (match_operand:V2SF 1 "register_operand" "0")
22429 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22431 "pfcmpeq\\t{%2, %0|%0, %2}"
22432 [(set_attr "type" "mmxcmp")
22433 (set_attr "mode" "V2SF")])
22435 (define_insn "pfmaxv2sf3"
22436 [(set (match_operand:V2SF 0 "register_operand" "=y")
22437 (smax:V2SF (match_operand:V2SF 1 "register_operand" "0")
22438 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22440 "pfmax\\t{%2, %0|%0, %2}"
22441 [(set_attr "type" "mmxadd")
22442 (set_attr "mode" "V2SF")])
22444 (define_insn "pfminv2sf3"
22445 [(set (match_operand:V2SF 0 "register_operand" "=y")
22446 (smin:V2SF (match_operand:V2SF 1 "register_operand" "0")
22447 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22449 "pfmin\\t{%2, %0|%0, %2}"
22450 [(set_attr "type" "mmxadd")
22451 (set_attr "mode" "V2SF")])
22453 (define_insn "mulv2sf3"
22454 [(set (match_operand:V2SF 0 "register_operand" "=y")
22455 (mult:V2SF (match_operand:V2SF 1 "register_operand" "0")
22456 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22458 "pfmul\\t{%2, %0|%0, %2}"
22459 [(set_attr "type" "mmxmul")
22460 (set_attr "mode" "V2SF")])
22462 (define_insn "femms"
22463 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
22464 (clobber (reg:XF 8))
22465 (clobber (reg:XF 9))
22466 (clobber (reg:XF 10))
22467 (clobber (reg:XF 11))
22468 (clobber (reg:XF 12))
22469 (clobber (reg:XF 13))
22470 (clobber (reg:XF 14))
22471 (clobber (reg:XF 15))
22472 (clobber (reg:DI 29))
22473 (clobber (reg:DI 30))
22474 (clobber (reg:DI 31))
22475 (clobber (reg:DI 32))
22476 (clobber (reg:DI 33))
22477 (clobber (reg:DI 34))
22478 (clobber (reg:DI 35))
22479 (clobber (reg:DI 36))]
22482 [(set_attr "type" "mmx")
22483 (set_attr "memory" "none")])
22485 (define_insn "pf2id"
22486 [(set (match_operand:V2SI 0 "register_operand" "=y")
22487 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
22489 "pf2id\\t{%1, %0|%0, %1}"
22490 [(set_attr "type" "mmxcvt")
22491 (set_attr "mode" "V2SF")])
22493 (define_insn "pf2iw"
22494 [(set (match_operand:V2SI 0 "register_operand" "=y")
22497 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
22499 "pf2iw\\t{%1, %0|%0, %1}"
22500 [(set_attr "type" "mmxcvt")
22501 (set_attr "mode" "V2SF")])
22503 (define_insn "pfacc"
22504 [(set (match_operand:V2SF 0 "register_operand" "=y")
22507 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
22508 (parallel [(const_int 0)]))
22509 (vec_select:SF (match_dup 1)
22510 (parallel [(const_int 1)])))
22512 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
22513 (parallel [(const_int 0)]))
22514 (vec_select:SF (match_dup 2)
22515 (parallel [(const_int 1)])))))]
22517 "pfacc\\t{%2, %0|%0, %2}"
22518 [(set_attr "type" "mmxadd")
22519 (set_attr "mode" "V2SF")])
22521 (define_insn "pfnacc"
22522 [(set (match_operand:V2SF 0 "register_operand" "=y")
22525 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
22526 (parallel [(const_int 0)]))
22527 (vec_select:SF (match_dup 1)
22528 (parallel [(const_int 1)])))
22530 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
22531 (parallel [(const_int 0)]))
22532 (vec_select:SF (match_dup 2)
22533 (parallel [(const_int 1)])))))]
22535 "pfnacc\\t{%2, %0|%0, %2}"
22536 [(set_attr "type" "mmxadd")
22537 (set_attr "mode" "V2SF")])
22539 (define_insn "pfpnacc"
22540 [(set (match_operand:V2SF 0 "register_operand" "=y")
22543 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
22544 (parallel [(const_int 0)]))
22545 (vec_select:SF (match_dup 1)
22546 (parallel [(const_int 1)])))
22548 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
22549 (parallel [(const_int 0)]))
22550 (vec_select:SF (match_dup 2)
22551 (parallel [(const_int 1)])))))]
22553 "pfpnacc\\t{%2, %0|%0, %2}"
22554 [(set_attr "type" "mmxadd")
22555 (set_attr "mode" "V2SF")])
22557 (define_insn "pi2fw"
22558 [(set (match_operand:V2SF 0 "register_operand" "=y")
22563 (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
22564 (parallel [(const_int 0)]))))
22567 (vec_select:SI (match_dup 1)
22568 (parallel [(const_int 1)])))))))]
22570 "pi2fw\\t{%1, %0|%0, %1}"
22571 [(set_attr "type" "mmxcvt")
22572 (set_attr "mode" "V2SF")])
22574 (define_insn "floatv2si2"
22575 [(set (match_operand:V2SF 0 "register_operand" "=y")
22576 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
22578 "pi2fd\\t{%1, %0|%0, %1}"
22579 [(set_attr "type" "mmxcvt")
22580 (set_attr "mode" "V2SF")])
22582 ;; This insn is identical to pavgb in operation, but the opcode is
22583 ;; different. To avoid accidentally matching pavgb, use an unspec.
22585 (define_insn "pavgusb"
22586 [(set (match_operand:V8QI 0 "register_operand" "=y")
22588 [(match_operand:V8QI 1 "register_operand" "0")
22589 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
22592 "pavgusb\\t{%2, %0|%0, %2}"
22593 [(set_attr "type" "mmxshft")
22594 (set_attr "mode" "TI")])
22596 ;; 3DNow reciprocal and sqrt
22598 (define_insn "pfrcpv2sf2"
22599 [(set (match_operand:V2SF 0 "register_operand" "=y")
22600 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
22603 "pfrcp\\t{%1, %0|%0, %1}"
22604 [(set_attr "type" "mmx")
22605 (set_attr "mode" "TI")])
22607 (define_insn "pfrcpit1v2sf3"
22608 [(set (match_operand:V2SF 0 "register_operand" "=y")
22609 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
22610 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
22613 "pfrcpit1\\t{%2, %0|%0, %2}"
22614 [(set_attr "type" "mmx")
22615 (set_attr "mode" "TI")])
22617 (define_insn "pfrcpit2v2sf3"
22618 [(set (match_operand:V2SF 0 "register_operand" "=y")
22619 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
22620 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
22623 "pfrcpit2\\t{%2, %0|%0, %2}"
22624 [(set_attr "type" "mmx")
22625 (set_attr "mode" "TI")])
22627 (define_insn "pfrsqrtv2sf2"
22628 [(set (match_operand:V2SF 0 "register_operand" "=y")
22629 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
22632 "pfrsqrt\\t{%1, %0|%0, %1}"
22633 [(set_attr "type" "mmx")
22634 (set_attr "mode" "TI")])
22636 (define_insn "pfrsqit1v2sf3"
22637 [(set (match_operand:V2SF 0 "register_operand" "=y")
22638 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
22639 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
22642 "pfrsqit1\\t{%2, %0|%0, %2}"
22643 [(set_attr "type" "mmx")
22644 (set_attr "mode" "TI")])
22646 (define_insn "pmulhrwv4hi3"
22647 [(set (match_operand:V4HI 0 "register_operand" "=y")
22653 (match_operand:V4HI 1 "register_operand" "0"))
22655 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
22656 (const_vector:V4SI [(const_int 32768)
22659 (const_int 32768)]))
22662 "pmulhrw\\t{%2, %0|%0, %2}"
22663 [(set_attr "type" "mmxmul")
22664 (set_attr "mode" "TI")])
22666 (define_insn "pswapdv2si2"
22667 [(set (match_operand:V2SI 0 "register_operand" "=y")
22668 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
22669 (parallel [(const_int 1) (const_int 0)])))]
22671 "pswapd\\t{%1, %0|%0, %1}"
22672 [(set_attr "type" "mmxcvt")
22673 (set_attr "mode" "TI")])
22675 (define_insn "pswapdv2sf2"
22676 [(set (match_operand:V2SF 0 "register_operand" "=y")
22677 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
22678 (parallel [(const_int 1) (const_int 0)])))]
22680 "pswapd\\t{%1, %0|%0, %1}"
22681 [(set_attr "type" "mmxcvt")
22682 (set_attr "mode" "TI")])
22684 (define_expand "prefetch"
22685 [(prefetch (match_operand 0 "address_operand" "")
22686 (match_operand:SI 1 "const_int_operand" "")
22687 (match_operand:SI 2 "const_int_operand" ""))]
22688 "TARGET_PREFETCH_SSE || TARGET_3DNOW"
22690 int rw = INTVAL (operands[1]);
22691 int locality = INTVAL (operands[2]);
22693 if (rw != 0 && rw != 1)
22695 if (locality < 0 || locality > 3)
22697 if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
22700 /* Use 3dNOW prefetch in case we are asking for write prefetch not
22701 suported by SSE counterpart or the SSE prefetch is not available
22702 (K6 machines). Otherwise use SSE prefetch as it allows specifying
22704 if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
22705 operands[2] = GEN_INT (3);
22707 operands[1] = const0_rtx;
22710 (define_insn "*prefetch_sse"
22711 [(prefetch (match_operand:SI 0 "address_operand" "p")
22713 (match_operand:SI 1 "const_int_operand" ""))]
22714 "TARGET_PREFETCH_SSE && !TARGET_64BIT"
22716 static const char * const patterns[4] = {
22717 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
22720 int locality = INTVAL (operands[1]);
22721 if (locality < 0 || locality > 3)
22724 return patterns[locality];
22726 [(set_attr "type" "sse")
22727 (set_attr "memory" "none")])
22729 (define_insn "*prefetch_sse_rex"
22730 [(prefetch (match_operand:DI 0 "address_operand" "p")
22732 (match_operand:SI 1 "const_int_operand" ""))]
22733 "TARGET_PREFETCH_SSE && TARGET_64BIT"
22735 static const char * const patterns[4] = {
22736 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
22739 int locality = INTVAL (operands[1]);
22740 if (locality < 0 || locality > 3)
22743 return patterns[locality];
22745 [(set_attr "type" "sse")
22746 (set_attr "memory" "none")])
22748 (define_insn "*prefetch_3dnow"
22749 [(prefetch (match_operand:SI 0 "address_operand" "p")
22750 (match_operand:SI 1 "const_int_operand" "n")
22752 "TARGET_3DNOW && !TARGET_64BIT"
22754 if (INTVAL (operands[1]) == 0)
22755 return "prefetch\t%a0";
22757 return "prefetchw\t%a0";
22759 [(set_attr "type" "mmx")
22760 (set_attr "memory" "none")])
22762 (define_insn "*prefetch_3dnow_rex"
22763 [(prefetch (match_operand:DI 0 "address_operand" "p")
22764 (match_operand:SI 1 "const_int_operand" "n")
22766 "TARGET_3DNOW && TARGET_64BIT"
22768 if (INTVAL (operands[1]) == 0)
22769 return "prefetch\t%a0";
22771 return "prefetchw\t%a0";
22773 [(set_attr "type" "mmx")
22774 (set_attr "memory" "none")])
22778 (define_insn "addv2df3"
22779 [(set (match_operand:V2DF 0 "register_operand" "=x")
22780 (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
22781 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22783 "addpd\t{%2, %0|%0, %2}"
22784 [(set_attr "type" "sseadd")
22785 (set_attr "mode" "V2DF")])
22787 (define_insn "vmaddv2df3"
22788 [(set (match_operand:V2DF 0 "register_operand" "=x")
22789 (vec_merge:V2DF (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
22790 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22794 "addsd\t{%2, %0|%0, %2}"
22795 [(set_attr "type" "sseadd")
22796 (set_attr "mode" "DF")])
22798 (define_insn "subv2df3"
22799 [(set (match_operand:V2DF 0 "register_operand" "=x")
22800 (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
22801 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22803 "subpd\t{%2, %0|%0, %2}"
22804 [(set_attr "type" "sseadd")
22805 (set_attr "mode" "V2DF")])
22807 (define_insn "vmsubv2df3"
22808 [(set (match_operand:V2DF 0 "register_operand" "=x")
22809 (vec_merge:V2DF (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
22810 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22814 "subsd\t{%2, %0|%0, %2}"
22815 [(set_attr "type" "sseadd")
22816 (set_attr "mode" "DF")])
22818 (define_insn "mulv2df3"
22819 [(set (match_operand:V2DF 0 "register_operand" "=x")
22820 (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
22821 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22823 "mulpd\t{%2, %0|%0, %2}"
22824 [(set_attr "type" "ssemul")
22825 (set_attr "mode" "V2DF")])
22827 (define_insn "vmmulv2df3"
22828 [(set (match_operand:V2DF 0 "register_operand" "=x")
22829 (vec_merge:V2DF (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
22830 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22834 "mulsd\t{%2, %0|%0, %2}"
22835 [(set_attr "type" "ssemul")
22836 (set_attr "mode" "DF")])
22838 (define_insn "divv2df3"
22839 [(set (match_operand:V2DF 0 "register_operand" "=x")
22840 (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
22841 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22843 "divpd\t{%2, %0|%0, %2}"
22844 [(set_attr "type" "ssediv")
22845 (set_attr "mode" "V2DF")])
22847 (define_insn "vmdivv2df3"
22848 [(set (match_operand:V2DF 0 "register_operand" "=x")
22849 (vec_merge:V2DF (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
22850 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22854 "divsd\t{%2, %0|%0, %2}"
22855 [(set_attr "type" "ssediv")
22856 (set_attr "mode" "DF")])
22860 (define_insn "smaxv2df3"
22861 [(set (match_operand:V2DF 0 "register_operand" "=x")
22862 (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
22863 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22865 "maxpd\t{%2, %0|%0, %2}"
22866 [(set_attr "type" "sseadd")
22867 (set_attr "mode" "V2DF")])
22869 (define_insn "vmsmaxv2df3"
22870 [(set (match_operand:V2DF 0 "register_operand" "=x")
22871 (vec_merge:V2DF (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
22872 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22876 "maxsd\t{%2, %0|%0, %2}"
22877 [(set_attr "type" "sseadd")
22878 (set_attr "mode" "DF")])
22880 (define_insn "sminv2df3"
22881 [(set (match_operand:V2DF 0 "register_operand" "=x")
22882 (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
22883 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22885 "minpd\t{%2, %0|%0, %2}"
22886 [(set_attr "type" "sseadd")
22887 (set_attr "mode" "V2DF")])
22889 (define_insn "vmsminv2df3"
22890 [(set (match_operand:V2DF 0 "register_operand" "=x")
22891 (vec_merge:V2DF (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
22892 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22896 "minsd\t{%2, %0|%0, %2}"
22897 [(set_attr "type" "sseadd")
22898 (set_attr "mode" "DF")])
22899 ;; SSE2 square root. There doesn't appear to be an extension for the
22900 ;; reciprocal/rsqrt instructions if the Intel manual is to be believed.
22902 (define_insn "sqrtv2df2"
22903 [(set (match_operand:V2DF 0 "register_operand" "=x")
22904 (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")))]
22906 "sqrtpd\t{%1, %0|%0, %1}"
22907 [(set_attr "type" "sse")
22908 (set_attr "mode" "V2DF")])
22910 (define_insn "vmsqrtv2df2"
22911 [(set (match_operand:V2DF 0 "register_operand" "=x")
22912 (vec_merge:V2DF (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm"))
22913 (match_operand:V2DF 2 "register_operand" "0")
22916 "sqrtsd\t{%1, %0|%0, %1}"
22917 [(set_attr "type" "sse")
22918 (set_attr "mode" "SF")])
22920 ;; SSE mask-generating compares
22922 (define_insn "maskcmpv2df3"
22923 [(set (match_operand:V2DI 0 "register_operand" "=x")
22924 (match_operator:V2DI 3 "sse_comparison_operator"
22925 [(match_operand:V2DF 1 "register_operand" "0")
22926 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))]
22928 "cmp%D3pd\t{%2, %0|%0, %2}"
22929 [(set_attr "type" "ssecmp")
22930 (set_attr "mode" "V2DF")])
22932 (define_insn "maskncmpv2df3"
22933 [(set (match_operand:V2DI 0 "register_operand" "=x")
22935 (match_operator:V2DI 3 "sse_comparison_operator"
22936 [(match_operand:V2DF 1 "register_operand" "0")
22937 (match_operand:V2DF 2 "nonimmediate_operand" "x")])))]
22940 if (GET_CODE (operands[3]) == UNORDERED)
22941 return "cmpordps\t{%2, %0|%0, %2}";
22943 return "cmpn%D3pd\t{%2, %0|%0, %2}";
22945 [(set_attr "type" "ssecmp")
22946 (set_attr "mode" "V2DF")])
22948 (define_insn "vmmaskcmpv2df3"
22949 [(set (match_operand:V2DI 0 "register_operand" "=x")
22951 (match_operator:V2DI 3 "sse_comparison_operator"
22952 [(match_operand:V2DF 1 "register_operand" "0")
22953 (match_operand:V2DF 2 "nonimmediate_operand" "x")])
22954 (subreg:V2DI (match_dup 1) 0)
22957 "cmp%D3sd\t{%2, %0|%0, %2}"
22958 [(set_attr "type" "ssecmp")
22959 (set_attr "mode" "DF")])
22961 (define_insn "vmmaskncmpv2df3"
22962 [(set (match_operand:V2DI 0 "register_operand" "=x")
22965 (match_operator:V2DI 3 "sse_comparison_operator"
22966 [(match_operand:V2DF 1 "register_operand" "0")
22967 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))
22968 (subreg:V2DI (match_dup 1) 0)
22972 if (GET_CODE (operands[3]) == UNORDERED)
22973 return "cmpordsd\t{%2, %0|%0, %2}";
22975 return "cmpn%D3sd\t{%2, %0|%0, %2}";
22977 [(set_attr "type" "ssecmp")
22978 (set_attr "mode" "DF")])
22980 (define_insn "sse2_comi"
22981 [(set (reg:CCFP FLAGS_REG)
22982 (compare:CCFP (vec_select:DF
22983 (match_operand:V2DF 0 "register_operand" "x")
22984 (parallel [(const_int 0)]))
22986 (match_operand:V2DF 1 "register_operand" "x")
22987 (parallel [(const_int 0)]))))]
22989 "comisd\t{%1, %0|%0, %1}"
22990 [(set_attr "type" "ssecomi")
22991 (set_attr "mode" "DF")])
22993 (define_insn "sse2_ucomi"
22994 [(set (reg:CCFPU FLAGS_REG)
22995 (compare:CCFPU (vec_select:DF
22996 (match_operand:V2DF 0 "register_operand" "x")
22997 (parallel [(const_int 0)]))
22999 (match_operand:V2DF 1 "register_operand" "x")
23000 (parallel [(const_int 0)]))))]
23002 "ucomisd\t{%1, %0|%0, %1}"
23003 [(set_attr "type" "ssecomi")
23004 (set_attr "mode" "DF")])
23006 ;; SSE Strange Moves.
23008 (define_insn "sse2_movmskpd"
23009 [(set (match_operand:SI 0 "register_operand" "=r")
23010 (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")]
23013 "movmskpd\t{%1, %0|%0, %1}"
23014 [(set_attr "type" "ssecvt")
23015 (set_attr "mode" "V2DF")])
23017 (define_insn "sse2_pmovmskb"
23018 [(set (match_operand:SI 0 "register_operand" "=r")
23019 (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
23022 "pmovmskb\t{%1, %0|%0, %1}"
23023 [(set_attr "type" "ssecvt")
23024 (set_attr "mode" "V2DF")])
23026 (define_insn "sse2_maskmovdqu"
23027 [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
23028 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
23029 (match_operand:V16QI 2 "register_operand" "x")]
23032 ;; @@@ check ordering of operands in intel/nonintel syntax
23033 "maskmovdqu\t{%2, %1|%1, %2}"
23034 [(set_attr "type" "ssecvt")
23035 (set_attr "mode" "TI")])
23037 (define_insn "sse2_maskmovdqu_rex64"
23038 [(set (mem:V16QI (match_operand:DI 0 "register_operand" "D"))
23039 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
23040 (match_operand:V16QI 2 "register_operand" "x")]
23043 ;; @@@ check ordering of operands in intel/nonintel syntax
23044 "maskmovdqu\t{%2, %1|%1, %2}"
23045 [(set_attr "type" "ssecvt")
23046 (set_attr "mode" "TI")])
23048 (define_insn "sse2_movntv2df"
23049 [(set (match_operand:V2DF 0 "memory_operand" "=m")
23050 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]
23053 "movntpd\t{%1, %0|%0, %1}"
23054 [(set_attr "type" "ssecvt")
23055 (set_attr "mode" "V2DF")])
23057 (define_insn "sse2_movntv2di"
23058 [(set (match_operand:V2DI 0 "memory_operand" "=m")
23059 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
23062 "movntdq\t{%1, %0|%0, %1}"
23063 [(set_attr "type" "ssecvt")
23064 (set_attr "mode" "TI")])
23066 (define_insn "sse2_movntsi"
23067 [(set (match_operand:SI 0 "memory_operand" "=m")
23068 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
23071 "movnti\t{%1, %0|%0, %1}"
23072 [(set_attr "type" "ssecvt")
23073 (set_attr "mode" "V2DF")])
23075 ;; SSE <-> integer/MMX conversions
23077 ;; Conversions between SI and SF
23079 (define_insn "cvtdq2ps"
23080 [(set (match_operand:V4SF 0 "register_operand" "=x")
23081 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
23083 "cvtdq2ps\t{%1, %0|%0, %1}"
23084 [(set_attr "type" "ssecvt")
23085 (set_attr "mode" "V2DF")])
23087 (define_insn "cvtps2dq"
23088 [(set (match_operand:V4SI 0 "register_operand" "=x")
23089 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
23091 "cvtps2dq\t{%1, %0|%0, %1}"
23092 [(set_attr "type" "ssecvt")
23093 (set_attr "mode" "TI")])
23095 (define_insn "cvttps2dq"
23096 [(set (match_operand:V4SI 0 "register_operand" "=x")
23097 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
23100 "cvttps2dq\t{%1, %0|%0, %1}"
23101 [(set_attr "type" "ssecvt")
23102 (set_attr "mode" "TI")])
23104 ;; Conversions between SI and DF
23106 (define_insn "cvtdq2pd"
23107 [(set (match_operand:V2DF 0 "register_operand" "=x")
23108 (float:V2DF (vec_select:V2SI
23109 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
23112 (const_int 1)]))))]
23114 "cvtdq2pd\t{%1, %0|%0, %1}"
23115 [(set_attr "type" "ssecvt")
23116 (set_attr "mode" "V2DF")])
23118 (define_insn "cvtpd2dq"
23119 [(set (match_operand:V4SI 0 "register_operand" "=x")
23121 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
23122 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
23124 "cvtpd2dq\t{%1, %0|%0, %1}"
23125 [(set_attr "type" "ssecvt")
23126 (set_attr "mode" "TI")])
23128 (define_insn "cvttpd2dq"
23129 [(set (match_operand:V4SI 0 "register_operand" "=x")
23131 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
23133 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
23135 "cvttpd2dq\t{%1, %0|%0, %1}"
23136 [(set_attr "type" "ssecvt")
23137 (set_attr "mode" "TI")])
23139 (define_insn "cvtpd2pi"
23140 [(set (match_operand:V2SI 0 "register_operand" "=y")
23141 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
23143 "cvtpd2pi\t{%1, %0|%0, %1}"
23144 [(set_attr "type" "ssecvt")
23145 (set_attr "mode" "TI")])
23147 (define_insn "cvttpd2pi"
23148 [(set (match_operand:V2SI 0 "register_operand" "=y")
23149 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
23152 "cvttpd2pi\t{%1, %0|%0, %1}"
23153 [(set_attr "type" "ssecvt")
23154 (set_attr "mode" "TI")])
23156 (define_insn "cvtpi2pd"
23157 [(set (match_operand:V2DF 0 "register_operand" "=x")
23158 (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
23160 "cvtpi2pd\t{%1, %0|%0, %1}"
23161 [(set_attr "type" "ssecvt")
23162 (set_attr "mode" "TI")])
23164 ;; Conversions between SI and DF
23166 (define_insn "cvtsd2si"
23167 [(set (match_operand:SI 0 "register_operand" "=r,r")
23168 (fix:SI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
23169 (parallel [(const_int 0)]))))]
23171 "cvtsd2si\t{%1, %0|%0, %1}"
23172 [(set_attr "type" "sseicvt")
23173 (set_attr "athlon_decode" "double,vector")
23174 (set_attr "mode" "SI")])
23176 (define_insn "cvtsd2siq"
23177 [(set (match_operand:DI 0 "register_operand" "=r,r")
23178 (fix:DI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
23179 (parallel [(const_int 0)]))))]
23180 "TARGET_SSE2 && TARGET_64BIT"
23181 "cvtsd2siq\t{%1, %0|%0, %1}"
23182 [(set_attr "type" "sseicvt")
23183 (set_attr "athlon_decode" "double,vector")
23184 (set_attr "mode" "DI")])
23186 (define_insn "cvttsd2si"
23187 [(set (match_operand:SI 0 "register_operand" "=r,r")
23188 (unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
23189 (parallel [(const_int 0)]))] UNSPEC_FIX))]
23191 "cvttsd2si\t{%1, %0|%0, %1}"
23192 [(set_attr "type" "sseicvt")
23193 (set_attr "mode" "SI")
23194 (set_attr "athlon_decode" "double,vector")])
23196 (define_insn "cvttsd2siq"
23197 [(set (match_operand:DI 0 "register_operand" "=r,r")
23198 (unspec:DI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
23199 (parallel [(const_int 0)]))] UNSPEC_FIX))]
23200 "TARGET_SSE2 && TARGET_64BIT"
23201 "cvttsd2siq\t{%1, %0|%0, %1}"
23202 [(set_attr "type" "sseicvt")
23203 (set_attr "mode" "DI")
23204 (set_attr "athlon_decode" "double,vector")])
23206 (define_insn "cvtsi2sd"
23207 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
23208 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
23209 (vec_duplicate:V2DF
23211 (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
23214 "cvtsi2sd\t{%2, %0|%0, %2}"
23215 [(set_attr "type" "sseicvt")
23216 (set_attr "mode" "DF")
23217 (set_attr "athlon_decode" "double,direct")])
23219 (define_insn "cvtsi2sdq"
23220 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
23221 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
23222 (vec_duplicate:V2DF
23224 (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
23226 "TARGET_SSE2 && TARGET_64BIT"
23227 "cvtsi2sdq\t{%2, %0|%0, %2}"
23228 [(set_attr "type" "sseicvt")
23229 (set_attr "mode" "DF")
23230 (set_attr "athlon_decode" "double,direct")])
23232 ;; Conversions between SF and DF
23234 (define_insn "cvtsd2ss"
23235 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
23236 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0,0")
23237 (vec_duplicate:V4SF
23238 (float_truncate:V2SF
23239 (match_operand:V2DF 2 "nonimmediate_operand" "x,xm")))
23242 "cvtsd2ss\t{%2, %0|%0, %2}"
23243 [(set_attr "type" "ssecvt")
23244 (set_attr "athlon_decode" "vector,double")
23245 (set_attr "mode" "SF")])
23247 (define_insn "cvtss2sd"
23248 [(set (match_operand:V2DF 0 "register_operand" "=x")
23249 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0")
23252 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
23253 (parallel [(const_int 0)
23257 "cvtss2sd\t{%2, %0|%0, %2}"
23258 [(set_attr "type" "ssecvt")
23259 (set_attr "mode" "DF")])
23261 (define_insn "cvtpd2ps"
23262 [(set (match_operand:V4SF 0 "register_operand" "=x")
23265 (subreg:V2SI (float_truncate:V2SF
23266 (match_operand:V2DF 1 "nonimmediate_operand" "xm")) 0)
23267 (const_vector:V2SI [(const_int 0) (const_int 0)])) 0))]
23269 "cvtpd2ps\t{%1, %0|%0, %1}"
23270 [(set_attr "type" "ssecvt")
23271 (set_attr "mode" "V4SF")])
23273 (define_insn "cvtps2pd"
23274 [(set (match_operand:V2DF 0 "register_operand" "=x")
23276 (vec_select:V2SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")
23277 (parallel [(const_int 0)
23278 (const_int 1)]))))]
23280 "cvtps2pd\t{%1, %0|%0, %1}"
23281 [(set_attr "type" "ssecvt")
23282 (set_attr "mode" "V2DF")])
23284 ;; SSE2 variants of MMX insns
23288 (define_insn "addv16qi3"
23289 [(set (match_operand:V16QI 0 "register_operand" "=x")
23290 (plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
23291 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23293 "paddb\t{%2, %0|%0, %2}"
23294 [(set_attr "type" "sseiadd")
23295 (set_attr "mode" "TI")])
23297 (define_insn "addv8hi3"
23298 [(set (match_operand:V8HI 0 "register_operand" "=x")
23299 (plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
23300 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23302 "paddw\t{%2, %0|%0, %2}"
23303 [(set_attr "type" "sseiadd")
23304 (set_attr "mode" "TI")])
23306 (define_insn "addv4si3"
23307 [(set (match_operand:V4SI 0 "register_operand" "=x")
23308 (plus:V4SI (match_operand:V4SI 1 "register_operand" "%0")
23309 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
23311 "paddd\t{%2, %0|%0, %2}"
23312 [(set_attr "type" "sseiadd")
23313 (set_attr "mode" "TI")])
23315 (define_insn "addv2di3"
23316 [(set (match_operand:V2DI 0 "register_operand" "=x")
23317 (plus:V2DI (match_operand:V2DI 1 "register_operand" "%0")
23318 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
23320 "paddq\t{%2, %0|%0, %2}"
23321 [(set_attr "type" "sseiadd")
23322 (set_attr "mode" "TI")])
23324 (define_insn "ssaddv16qi3"
23325 [(set (match_operand:V16QI 0 "register_operand" "=x")
23326 (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
23327 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23329 "paddsb\t{%2, %0|%0, %2}"
23330 [(set_attr "type" "sseiadd")
23331 (set_attr "mode" "TI")])
23333 (define_insn "ssaddv8hi3"
23334 [(set (match_operand:V8HI 0 "register_operand" "=x")
23335 (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
23336 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23338 "paddsw\t{%2, %0|%0, %2}"
23339 [(set_attr "type" "sseiadd")
23340 (set_attr "mode" "TI")])
23342 (define_insn "usaddv16qi3"
23343 [(set (match_operand:V16QI 0 "register_operand" "=x")
23344 (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
23345 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23347 "paddusb\t{%2, %0|%0, %2}"
23348 [(set_attr "type" "sseiadd")
23349 (set_attr "mode" "TI")])
23351 (define_insn "usaddv8hi3"
23352 [(set (match_operand:V8HI 0 "register_operand" "=x")
23353 (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
23354 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23356 "paddusw\t{%2, %0|%0, %2}"
23357 [(set_attr "type" "sseiadd")
23358 (set_attr "mode" "TI")])
23360 (define_insn "subv16qi3"
23361 [(set (match_operand:V16QI 0 "register_operand" "=x")
23362 (minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
23363 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23365 "psubb\t{%2, %0|%0, %2}"
23366 [(set_attr "type" "sseiadd")
23367 (set_attr "mode" "TI")])
23369 (define_insn "subv8hi3"
23370 [(set (match_operand:V8HI 0 "register_operand" "=x")
23371 (minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
23372 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23374 "psubw\t{%2, %0|%0, %2}"
23375 [(set_attr "type" "sseiadd")
23376 (set_attr "mode" "TI")])
23378 (define_insn "subv4si3"
23379 [(set (match_operand:V4SI 0 "register_operand" "=x")
23380 (minus:V4SI (match_operand:V4SI 1 "register_operand" "0")
23381 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
23383 "psubd\t{%2, %0|%0, %2}"
23384 [(set_attr "type" "sseiadd")
23385 (set_attr "mode" "TI")])
23387 (define_insn "subv2di3"
23388 [(set (match_operand:V2DI 0 "register_operand" "=x")
23389 (minus:V2DI (match_operand:V2DI 1 "register_operand" "0")
23390 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
23392 "psubq\t{%2, %0|%0, %2}"
23393 [(set_attr "type" "sseiadd")
23394 (set_attr "mode" "TI")])
23396 (define_insn "sssubv16qi3"
23397 [(set (match_operand:V16QI 0 "register_operand" "=x")
23398 (ss_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
23399 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23401 "psubsb\t{%2, %0|%0, %2}"
23402 [(set_attr "type" "sseiadd")
23403 (set_attr "mode" "TI")])
23405 (define_insn "sssubv8hi3"
23406 [(set (match_operand:V8HI 0 "register_operand" "=x")
23407 (ss_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
23408 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23410 "psubsw\t{%2, %0|%0, %2}"
23411 [(set_attr "type" "sseiadd")
23412 (set_attr "mode" "TI")])
23414 (define_insn "ussubv16qi3"
23415 [(set (match_operand:V16QI 0 "register_operand" "=x")
23416 (us_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
23417 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23419 "psubusb\t{%2, %0|%0, %2}"
23420 [(set_attr "type" "sseiadd")
23421 (set_attr "mode" "TI")])
23423 (define_insn "ussubv8hi3"
23424 [(set (match_operand:V8HI 0 "register_operand" "=x")
23425 (us_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
23426 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23428 "psubusw\t{%2, %0|%0, %2}"
23429 [(set_attr "type" "sseiadd")
23430 (set_attr "mode" "TI")])
23432 (define_insn "mulv8hi3"
23433 [(set (match_operand:V8HI 0 "register_operand" "=x")
23434 (mult:V8HI (match_operand:V8HI 1 "register_operand" "0")
23435 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23437 "pmullw\t{%2, %0|%0, %2}"
23438 [(set_attr "type" "sseimul")
23439 (set_attr "mode" "TI")])
23441 (define_insn "smulv8hi3_highpart"
23442 [(set (match_operand:V8HI 0 "register_operand" "=x")
23445 (mult:V8SI (sign_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
23446 (sign_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
23449 "pmulhw\t{%2, %0|%0, %2}"
23450 [(set_attr "type" "sseimul")
23451 (set_attr "mode" "TI")])
23453 (define_insn "umulv8hi3_highpart"
23454 [(set (match_operand:V8HI 0 "register_operand" "=x")
23457 (mult:V8SI (zero_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
23458 (zero_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
23461 "pmulhuw\t{%2, %0|%0, %2}"
23462 [(set_attr "type" "sseimul")
23463 (set_attr "mode" "TI")])
23465 (define_insn "sse2_umulsidi3"
23466 [(set (match_operand:DI 0 "register_operand" "=y")
23467 (mult:DI (zero_extend:DI (vec_select:SI
23468 (match_operand:V2SI 1 "register_operand" "0")
23469 (parallel [(const_int 0)])))
23470 (zero_extend:DI (vec_select:SI
23471 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
23472 (parallel [(const_int 0)])))))]
23474 "pmuludq\t{%2, %0|%0, %2}"
23475 [(set_attr "type" "mmxmul")
23476 (set_attr "mode" "DI")])
23478 (define_insn "sse2_umulv2siv2di3"
23479 [(set (match_operand:V2DI 0 "register_operand" "=x")
23480 (mult:V2DI (zero_extend:V2DI
23482 (match_operand:V4SI 1 "register_operand" "0")
23483 (parallel [(const_int 0) (const_int 2)])))
23486 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
23487 (parallel [(const_int 0) (const_int 2)])))))]
23489 "pmuludq\t{%2, %0|%0, %2}"
23490 [(set_attr "type" "sseimul")
23491 (set_attr "mode" "TI")])
23493 (define_insn "sse2_pmaddwd"
23494 [(set (match_operand:V4SI 0 "register_operand" "=x")
23497 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 1 "register_operand" "0")
23498 (parallel [(const_int 0)
23502 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 2 "nonimmediate_operand" "xm")
23503 (parallel [(const_int 0)
23508 (sign_extend:V4SI (vec_select:V4HI (match_dup 1)
23509 (parallel [(const_int 1)
23513 (sign_extend:V4SI (vec_select:V4HI (match_dup 2)
23514 (parallel [(const_int 1)
23517 (const_int 7)]))))))]
23519 "pmaddwd\t{%2, %0|%0, %2}"
23520 [(set_attr "type" "sseiadd")
23521 (set_attr "mode" "TI")])
23523 ;; Same as pxor, but don't show input operands so that we don't think
23525 (define_insn "sse2_clrti"
23526 [(set (match_operand:TI 0 "register_operand" "=x") (const_int 0))]
23529 if (get_attr_mode (insn) == MODE_TI)
23530 return "pxor\t%0, %0";
23532 return "xorps\t%0, %0";
23534 [(set_attr "type" "ssemov")
23535 (set_attr "memory" "none")
23538 (ne (symbol_ref "optimize_size")
23540 (const_string "V4SF")
23541 (const_string "TI")))])
23543 ;; MMX unsigned averages/sum of absolute differences
23545 (define_insn "sse2_uavgv16qi3"
23546 [(set (match_operand:V16QI 0 "register_operand" "=x")
23548 (plus:V16QI (plus:V16QI
23549 (match_operand:V16QI 1 "register_operand" "0")
23550 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
23551 (const_vector:V16QI [(const_int 1) (const_int 1)
23552 (const_int 1) (const_int 1)
23553 (const_int 1) (const_int 1)
23554 (const_int 1) (const_int 1)
23555 (const_int 1) (const_int 1)
23556 (const_int 1) (const_int 1)
23557 (const_int 1) (const_int 1)
23558 (const_int 1) (const_int 1)]))
23561 "pavgb\t{%2, %0|%0, %2}"
23562 [(set_attr "type" "sseiadd")
23563 (set_attr "mode" "TI")])
23565 (define_insn "sse2_uavgv8hi3"
23566 [(set (match_operand:V8HI 0 "register_operand" "=x")
23568 (plus:V8HI (plus:V8HI
23569 (match_operand:V8HI 1 "register_operand" "0")
23570 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
23571 (const_vector:V8HI [(const_int 1) (const_int 1)
23572 (const_int 1) (const_int 1)
23573 (const_int 1) (const_int 1)
23574 (const_int 1) (const_int 1)]))
23577 "pavgw\t{%2, %0|%0, %2}"
23578 [(set_attr "type" "sseiadd")
23579 (set_attr "mode" "TI")])
23581 ;; @@@ this isn't the right representation.
23582 (define_insn "sse2_psadbw"
23583 [(set (match_operand:V2DI 0 "register_operand" "=x")
23584 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
23585 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
23588 "psadbw\t{%2, %0|%0, %2}"
23589 [(set_attr "type" "sseiadd")
23590 (set_attr "mode" "TI")])
23593 ;; MMX insert/extract/shuffle
23595 (define_insn "sse2_pinsrw"
23596 [(set (match_operand:V8HI 0 "register_operand" "=x")
23597 (vec_merge:V8HI (match_operand:V8HI 1 "register_operand" "0")
23598 (vec_duplicate:V8HI
23600 (match_operand:SI 2 "nonimmediate_operand" "rm")))
23601 (match_operand:SI 3 "const_0_to_255_operand" "N")))]
23603 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
23604 [(set_attr "type" "ssecvt")
23605 (set_attr "mode" "TI")])
23607 (define_insn "sse2_pextrw"
23608 [(set (match_operand:SI 0 "register_operand" "=r")
23610 (vec_select:HI (match_operand:V8HI 1 "register_operand" "x")
23612 [(match_operand:SI 2 "const_0_to_7_operand" "N")]))))]
23614 "pextrw\t{%2, %1, %0|%0, %1, %2}"
23615 [(set_attr "type" "ssecvt")
23616 (set_attr "mode" "TI")])
23618 (define_insn "sse2_pshufd"
23619 [(set (match_operand:V4SI 0 "register_operand" "=x")
23620 (unspec:V4SI [(match_operand:V4SI 1 "nonimmediate_operand" "xm")
23621 (match_operand:SI 2 "immediate_operand" "i")]
23624 "pshufd\t{%2, %1, %0|%0, %1, %2}"
23625 [(set_attr "type" "ssecvt")
23626 (set_attr "mode" "TI")])
23628 (define_insn "sse2_pshuflw"
23629 [(set (match_operand:V8HI 0 "register_operand" "=x")
23630 (unspec:V8HI [(match_operand:V8HI 1 "nonimmediate_operand" "xm")
23631 (match_operand:SI 2 "immediate_operand" "i")]
23634 "pshuflw\t{%2, %1, %0|%0, %1, %2}"
23635 [(set_attr "type" "ssecvt")
23636 (set_attr "mode" "TI")])
23638 (define_insn "sse2_pshufhw"
23639 [(set (match_operand:V8HI 0 "register_operand" "=x")
23640 (unspec:V8HI [(match_operand:V8HI 1 "nonimmediate_operand" "xm")
23641 (match_operand:SI 2 "immediate_operand" "i")]
23644 "pshufhw\t{%2, %1, %0|%0, %1, %2}"
23645 [(set_attr "type" "ssecvt")
23646 (set_attr "mode" "TI")])
23648 ;; MMX mask-generating comparisons
23650 (define_insn "eqv16qi3"
23651 [(set (match_operand:V16QI 0 "register_operand" "=x")
23652 (eq:V16QI (match_operand:V16QI 1 "register_operand" "0")
23653 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23655 "pcmpeqb\t{%2, %0|%0, %2}"
23656 [(set_attr "type" "ssecmp")
23657 (set_attr "mode" "TI")])
23659 (define_insn "eqv8hi3"
23660 [(set (match_operand:V8HI 0 "register_operand" "=x")
23661 (eq:V8HI (match_operand:V8HI 1 "register_operand" "0")
23662 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23664 "pcmpeqw\t{%2, %0|%0, %2}"
23665 [(set_attr "type" "ssecmp")
23666 (set_attr "mode" "TI")])
23668 (define_insn "eqv4si3"
23669 [(set (match_operand:V4SI 0 "register_operand" "=x")
23670 (eq:V4SI (match_operand:V4SI 1 "register_operand" "0")
23671 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
23673 "pcmpeqd\t{%2, %0|%0, %2}"
23674 [(set_attr "type" "ssecmp")
23675 (set_attr "mode" "TI")])
23677 (define_insn "gtv16qi3"
23678 [(set (match_operand:V16QI 0 "register_operand" "=x")
23679 (gt:V16QI (match_operand:V16QI 1 "register_operand" "0")
23680 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23682 "pcmpgtb\t{%2, %0|%0, %2}"
23683 [(set_attr "type" "ssecmp")
23684 (set_attr "mode" "TI")])
23686 (define_insn "gtv8hi3"
23687 [(set (match_operand:V8HI 0 "register_operand" "=x")
23688 (gt:V8HI (match_operand:V8HI 1 "register_operand" "0")
23689 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23691 "pcmpgtw\t{%2, %0|%0, %2}"
23692 [(set_attr "type" "ssecmp")
23693 (set_attr "mode" "TI")])
23695 (define_insn "gtv4si3"
23696 [(set (match_operand:V4SI 0 "register_operand" "=x")
23697 (gt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23698 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
23700 "pcmpgtd\t{%2, %0|%0, %2}"
23701 [(set_attr "type" "ssecmp")
23702 (set_attr "mode" "TI")])
23705 ;; MMX max/min insns
23707 (define_insn "umaxv16qi3"
23708 [(set (match_operand:V16QI 0 "register_operand" "=x")
23709 (umax:V16QI (match_operand:V16QI 1 "register_operand" "0")
23710 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23712 "pmaxub\t{%2, %0|%0, %2}"
23713 [(set_attr "type" "sseiadd")
23714 (set_attr "mode" "TI")])
23716 (define_insn "smaxv8hi3"
23717 [(set (match_operand:V8HI 0 "register_operand" "=x")
23718 (smax:V8HI (match_operand:V8HI 1 "register_operand" "0")
23719 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23721 "pmaxsw\t{%2, %0|%0, %2}"
23722 [(set_attr "type" "sseiadd")
23723 (set_attr "mode" "TI")])
23725 (define_insn "uminv16qi3"
23726 [(set (match_operand:V16QI 0 "register_operand" "=x")
23727 (umin:V16QI (match_operand:V16QI 1 "register_operand" "0")
23728 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23730 "pminub\t{%2, %0|%0, %2}"
23731 [(set_attr "type" "sseiadd")
23732 (set_attr "mode" "TI")])
23734 (define_insn "sminv8hi3"
23735 [(set (match_operand:V8HI 0 "register_operand" "=x")
23736 (smin:V8HI (match_operand:V8HI 1 "register_operand" "0")
23737 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23739 "pminsw\t{%2, %0|%0, %2}"
23740 [(set_attr "type" "sseiadd")
23741 (set_attr "mode" "TI")])
23746 (define_insn "ashrv8hi3"
23747 [(set (match_operand:V8HI 0 "register_operand" "=x")
23748 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
23749 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23751 "psraw\t{%2, %0|%0, %2}"
23752 [(set_attr "type" "sseishft")
23753 (set_attr "mode" "TI")])
23755 (define_insn "ashrv4si3"
23756 [(set (match_operand:V4SI 0 "register_operand" "=x")
23757 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23758 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23760 "psrad\t{%2, %0|%0, %2}"
23761 [(set_attr "type" "sseishft")
23762 (set_attr "mode" "TI")])
23764 (define_insn "lshrv8hi3"
23765 [(set (match_operand:V8HI 0 "register_operand" "=x")
23766 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
23767 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23769 "psrlw\t{%2, %0|%0, %2}"
23770 [(set_attr "type" "sseishft")
23771 (set_attr "mode" "TI")])
23773 (define_insn "lshrv4si3"
23774 [(set (match_operand:V4SI 0 "register_operand" "=x")
23775 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23776 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23778 "psrld\t{%2, %0|%0, %2}"
23779 [(set_attr "type" "sseishft")
23780 (set_attr "mode" "TI")])
23782 (define_insn "lshrv2di3"
23783 [(set (match_operand:V2DI 0 "register_operand" "=x")
23784 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
23785 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23787 "psrlq\t{%2, %0|%0, %2}"
23788 [(set_attr "type" "sseishft")
23789 (set_attr "mode" "TI")])
23791 (define_insn "ashlv8hi3"
23792 [(set (match_operand:V8HI 0 "register_operand" "=x")
23793 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
23794 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23796 "psllw\t{%2, %0|%0, %2}"
23797 [(set_attr "type" "sseishft")
23798 (set_attr "mode" "TI")])
23800 (define_insn "ashlv4si3"
23801 [(set (match_operand:V4SI 0 "register_operand" "=x")
23802 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
23803 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23805 "pslld\t{%2, %0|%0, %2}"
23806 [(set_attr "type" "sseishft")
23807 (set_attr "mode" "TI")])
23809 (define_insn "ashlv2di3"
23810 [(set (match_operand:V2DI 0 "register_operand" "=x")
23811 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
23812 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23814 "psllq\t{%2, %0|%0, %2}"
23815 [(set_attr "type" "sseishft")
23816 (set_attr "mode" "TI")])
23818 (define_insn "ashrv8hi3_ti"
23819 [(set (match_operand:V8HI 0 "register_operand" "=x")
23820 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
23821 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23823 "psraw\t{%2, %0|%0, %2}"
23824 [(set_attr "type" "sseishft")
23825 (set_attr "mode" "TI")])
23827 (define_insn "ashrv4si3_ti"
23828 [(set (match_operand:V4SI 0 "register_operand" "=x")
23829 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23830 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23832 "psrad\t{%2, %0|%0, %2}"
23833 [(set_attr "type" "sseishft")
23834 (set_attr "mode" "TI")])
23836 (define_insn "lshrv8hi3_ti"
23837 [(set (match_operand:V8HI 0 "register_operand" "=x")
23838 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
23839 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23841 "psrlw\t{%2, %0|%0, %2}"
23842 [(set_attr "type" "sseishft")
23843 (set_attr "mode" "TI")])
23845 (define_insn "lshrv4si3_ti"
23846 [(set (match_operand:V4SI 0 "register_operand" "=x")
23847 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23848 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23850 "psrld\t{%2, %0|%0, %2}"
23851 [(set_attr "type" "sseishft")
23852 (set_attr "mode" "TI")])
23854 (define_insn "lshrv2di3_ti"
23855 [(set (match_operand:V2DI 0 "register_operand" "=x")
23856 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
23857 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23859 "psrlq\t{%2, %0|%0, %2}"
23860 [(set_attr "type" "sseishft")
23861 (set_attr "mode" "TI")])
23863 (define_insn "ashlv8hi3_ti"
23864 [(set (match_operand:V8HI 0 "register_operand" "=x")
23865 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
23866 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23868 "psllw\t{%2, %0|%0, %2}"
23869 [(set_attr "type" "sseishft")
23870 (set_attr "mode" "TI")])
23872 (define_insn "ashlv4si3_ti"
23873 [(set (match_operand:V4SI 0 "register_operand" "=x")
23874 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
23875 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23877 "pslld\t{%2, %0|%0, %2}"
23878 [(set_attr "type" "sseishft")
23879 (set_attr "mode" "TI")])
23881 (define_insn "ashlv2di3_ti"
23882 [(set (match_operand:V2DI 0 "register_operand" "=x")
23883 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
23884 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23886 "psllq\t{%2, %0|%0, %2}"
23887 [(set_attr "type" "sseishft")
23888 (set_attr "mode" "TI")])
23890 ;; See logical MMX insns for the reason for the unspec. Strictly speaking
23891 ;; we wouldn't need here it since we never generate TImode arithmetic.
23893 ;; There has to be some kind of prize for the weirdest new instruction...
23894 (define_insn "sse2_ashlti3"
23895 [(set (match_operand:TI 0 "register_operand" "=x")
23897 [(ashift:TI (match_operand:TI 1 "register_operand" "0")
23898 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
23899 (const_int 8)))] UNSPEC_NOP))]
23901 "pslldq\t{%2, %0|%0, %2}"
23902 [(set_attr "type" "sseishft")
23903 (set_attr "mode" "TI")])
23905 (define_insn "sse2_lshrti3"
23906 [(set (match_operand:TI 0 "register_operand" "=x")
23908 [(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
23909 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
23910 (const_int 8)))] UNSPEC_NOP))]
23912 "psrldq\t{%2, %0|%0, %2}"
23913 [(set_attr "type" "sseishft")
23914 (set_attr "mode" "TI")])
23918 (define_insn "sse2_unpckhpd"
23919 [(set (match_operand:V2DF 0 "register_operand" "=x")
23921 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
23922 (parallel [(const_int 1)]))
23923 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
23924 (parallel [(const_int 1)]))))]
23926 "unpckhpd\t{%2, %0|%0, %2}"
23927 [(set_attr "type" "ssecvt")
23928 (set_attr "mode" "V2DF")])
23930 (define_insn "sse2_unpcklpd"
23931 [(set (match_operand:V2DF 0 "register_operand" "=x")
23933 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
23934 (parallel [(const_int 0)]))
23935 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
23936 (parallel [(const_int 0)]))))]
23938 "unpcklpd\t{%2, %0|%0, %2}"
23939 [(set_attr "type" "ssecvt")
23940 (set_attr "mode" "V2DF")])
23942 ;; MMX pack/unpack insns.
23944 (define_insn "sse2_packsswb"
23945 [(set (match_operand:V16QI 0 "register_operand" "=x")
23947 (ss_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
23948 (ss_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
23950 "packsswb\t{%2, %0|%0, %2}"
23951 [(set_attr "type" "ssecvt")
23952 (set_attr "mode" "TI")])
23954 (define_insn "sse2_packssdw"
23955 [(set (match_operand:V8HI 0 "register_operand" "=x")
23957 (ss_truncate:V4HI (match_operand:V4SI 1 "register_operand" "0"))
23958 (ss_truncate:V4HI (match_operand:V4SI 2 "register_operand" "x"))))]
23960 "packssdw\t{%2, %0|%0, %2}"
23961 [(set_attr "type" "ssecvt")
23962 (set_attr "mode" "TI")])
23964 (define_insn "sse2_packuswb"
23965 [(set (match_operand:V16QI 0 "register_operand" "=x")
23967 (us_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
23968 (us_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
23970 "packuswb\t{%2, %0|%0, %2}"
23971 [(set_attr "type" "ssecvt")
23972 (set_attr "mode" "TI")])
23974 (define_insn "sse2_punpckhbw"
23975 [(set (match_operand:V16QI 0 "register_operand" "=x")
23977 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
23978 (parallel [(const_int 8) (const_int 0)
23979 (const_int 9) (const_int 1)
23980 (const_int 10) (const_int 2)
23981 (const_int 11) (const_int 3)
23982 (const_int 12) (const_int 4)
23983 (const_int 13) (const_int 5)
23984 (const_int 14) (const_int 6)
23985 (const_int 15) (const_int 7)]))
23986 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
23987 (parallel [(const_int 0) (const_int 8)
23988 (const_int 1) (const_int 9)
23989 (const_int 2) (const_int 10)
23990 (const_int 3) (const_int 11)
23991 (const_int 4) (const_int 12)
23992 (const_int 5) (const_int 13)
23993 (const_int 6) (const_int 14)
23994 (const_int 7) (const_int 15)]))
23995 (const_int 21845)))]
23997 "punpckhbw\t{%2, %0|%0, %2}"
23998 [(set_attr "type" "ssecvt")
23999 (set_attr "mode" "TI")])
24001 (define_insn "sse2_punpckhwd"
24002 [(set (match_operand:V8HI 0 "register_operand" "=x")
24004 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
24005 (parallel [(const_int 4) (const_int 0)
24006 (const_int 5) (const_int 1)
24007 (const_int 6) (const_int 2)
24008 (const_int 7) (const_int 3)]))
24009 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
24010 (parallel [(const_int 0) (const_int 4)
24011 (const_int 1) (const_int 5)
24012 (const_int 2) (const_int 6)
24013 (const_int 3) (const_int 7)]))
24016 "punpckhwd\t{%2, %0|%0, %2}"
24017 [(set_attr "type" "ssecvt")
24018 (set_attr "mode" "TI")])
24020 (define_insn "sse2_punpckhdq"
24021 [(set (match_operand:V4SI 0 "register_operand" "=x")
24023 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
24024 (parallel [(const_int 2) (const_int 0)
24025 (const_int 3) (const_int 1)]))
24026 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
24027 (parallel [(const_int 0) (const_int 2)
24028 (const_int 1) (const_int 3)]))
24031 "punpckhdq\t{%2, %0|%0, %2}"
24032 [(set_attr "type" "ssecvt")
24033 (set_attr "mode" "TI")])
24035 (define_insn "sse2_punpcklbw"
24036 [(set (match_operand:V16QI 0 "register_operand" "=x")
24038 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
24039 (parallel [(const_int 0) (const_int 8)
24040 (const_int 1) (const_int 9)
24041 (const_int 2) (const_int 10)
24042 (const_int 3) (const_int 11)
24043 (const_int 4) (const_int 12)
24044 (const_int 5) (const_int 13)
24045 (const_int 6) (const_int 14)
24046 (const_int 7) (const_int 15)]))
24047 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
24048 (parallel [(const_int 8) (const_int 0)
24049 (const_int 9) (const_int 1)
24050 (const_int 10) (const_int 2)
24051 (const_int 11) (const_int 3)
24052 (const_int 12) (const_int 4)
24053 (const_int 13) (const_int 5)
24054 (const_int 14) (const_int 6)
24055 (const_int 15) (const_int 7)]))
24056 (const_int 21845)))]
24058 "punpcklbw\t{%2, %0|%0, %2}"
24059 [(set_attr "type" "ssecvt")
24060 (set_attr "mode" "TI")])
24062 (define_insn "sse2_punpcklwd"
24063 [(set (match_operand:V8HI 0 "register_operand" "=x")
24065 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
24066 (parallel [(const_int 0) (const_int 4)
24067 (const_int 1) (const_int 5)
24068 (const_int 2) (const_int 6)
24069 (const_int 3) (const_int 7)]))
24070 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
24071 (parallel [(const_int 4) (const_int 0)
24072 (const_int 5) (const_int 1)
24073 (const_int 6) (const_int 2)
24074 (const_int 7) (const_int 3)]))
24077 "punpcklwd\t{%2, %0|%0, %2}"
24078 [(set_attr "type" "ssecvt")
24079 (set_attr "mode" "TI")])
24081 (define_insn "sse2_punpckldq"
24082 [(set (match_operand:V4SI 0 "register_operand" "=x")
24084 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
24085 (parallel [(const_int 0) (const_int 2)
24086 (const_int 1) (const_int 3)]))
24087 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
24088 (parallel [(const_int 2) (const_int 0)
24089 (const_int 3) (const_int 1)]))
24092 "punpckldq\t{%2, %0|%0, %2}"
24093 [(set_attr "type" "ssecvt")
24094 (set_attr "mode" "TI")])
24096 (define_insn "sse2_punpcklqdq"
24097 [(set (match_operand:V2DI 0 "register_operand" "=x")
24099 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
24100 (parallel [(const_int 1)
24102 (match_operand:V2DI 1 "register_operand" "0")
24105 "punpcklqdq\t{%2, %0|%0, %2}"
24106 [(set_attr "type" "ssecvt")
24107 (set_attr "mode" "TI")])
24109 (define_insn "sse2_punpckhqdq"
24110 [(set (match_operand:V2DI 0 "register_operand" "=x")
24112 (match_operand:V2DI 1 "register_operand" "0")
24113 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
24114 (parallel [(const_int 1)
24118 "punpckhqdq\t{%2, %0|%0, %2}"
24119 [(set_attr "type" "ssecvt")
24120 (set_attr "mode" "TI")])
24124 (define_insn "sse2_movapd"
24125 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
24126 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
24129 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
24130 "movapd\t{%1, %0|%0, %1}"
24131 [(set_attr "type" "ssemov")
24132 (set_attr "mode" "V2DF")])
24134 (define_insn "sse2_movupd"
24135 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
24136 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
24139 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
24140 "movupd\t{%1, %0|%0, %1}"
24141 [(set_attr "type" "ssecvt")
24142 (set_attr "mode" "V2DF")])
24144 (define_insn "sse2_movdqa"
24145 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
24146 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
24149 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
24150 "movdqa\t{%1, %0|%0, %1}"
24151 [(set_attr "type" "ssemov")
24152 (set_attr "mode" "TI")])
24154 (define_insn "sse2_movdqu"
24155 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
24156 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
24159 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
24160 "movdqu\t{%1, %0|%0, %1}"
24161 [(set_attr "type" "ssecvt")
24162 (set_attr "mode" "TI")])
24164 (define_insn "sse2_movdq2q"
24165 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y")
24166 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x")
24167 (parallel [(const_int 0)])))]
24168 "TARGET_SSE2 && !TARGET_64BIT"
24170 movq\t{%1, %0|%0, %1}
24171 movdq2q\t{%1, %0|%0, %1}"
24172 [(set_attr "type" "ssecvt")
24173 (set_attr "mode" "TI")])
24175 (define_insn "sse2_movdq2q_rex64"
24176 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y,r")
24177 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x,x")
24178 (parallel [(const_int 0)])))]
24179 "TARGET_SSE2 && TARGET_64BIT"
24181 movq\t{%1, %0|%0, %1}
24182 movdq2q\t{%1, %0|%0, %1}
24183 movd\t{%1, %0|%0, %1}"
24184 [(set_attr "type" "ssecvt")
24185 (set_attr "mode" "TI")])
24187 (define_insn "sse2_movq2dq"
24188 [(set (match_operand:V2DI 0 "register_operand" "=x,?x")
24189 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y")
24191 "TARGET_SSE2 && !TARGET_64BIT"
24193 movq\t{%1, %0|%0, %1}
24194 movq2dq\t{%1, %0|%0, %1}"
24195 [(set_attr "type" "ssecvt,ssemov")
24196 (set_attr "mode" "TI")])
24198 (define_insn "sse2_movq2dq_rex64"
24199 [(set (match_operand:V2DI 0 "register_operand" "=x,?x,?x")
24200 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y,r")
24202 "TARGET_SSE2 && TARGET_64BIT"
24204 movq\t{%1, %0|%0, %1}
24205 movq2dq\t{%1, %0|%0, %1}
24206 movd\t{%1, %0|%0, %1}"
24207 [(set_attr "type" "ssecvt,ssemov,ssecvt")
24208 (set_attr "mode" "TI")])
24210 (define_insn "sse2_movq"
24211 [(set (match_operand:V2DI 0 "register_operand" "=x")
24212 (vec_concat:V2DI (vec_select:DI
24213 (match_operand:V2DI 1 "nonimmediate_operand" "xm")
24214 (parallel [(const_int 0)]))
24217 "movq\t{%1, %0|%0, %1}"
24218 [(set_attr "type" "ssemov")
24219 (set_attr "mode" "TI")])
24221 (define_insn "sse2_loadd"
24222 [(set (match_operand:V4SI 0 "register_operand" "=x")
24224 (vec_duplicate:V4SI (match_operand:SI 1 "nonimmediate_operand" "mr"))
24225 (const_vector:V4SI [(const_int 0)
24231 "movd\t{%1, %0|%0, %1}"
24232 [(set_attr "type" "ssemov")
24233 (set_attr "mode" "TI")])
24235 (define_insn "sse2_stored"
24236 [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
24238 (match_operand:V4SI 1 "register_operand" "x")
24239 (parallel [(const_int 0)])))]
24241 "movd\t{%1, %0|%0, %1}"
24242 [(set_attr "type" "ssemov")
24243 (set_attr "mode" "TI")])
24245 (define_insn "sse2_movhpd"
24246 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
24248 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
24249 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
24251 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
24252 "movhpd\t{%2, %0|%0, %2}"
24253 [(set_attr "type" "ssecvt")
24254 (set_attr "mode" "V2DF")])
24256 (define_expand "sse2_loadsd"
24257 [(match_operand:V2DF 0 "register_operand" "")
24258 (match_operand:DF 1 "memory_operand" "")]
24261 emit_insn (gen_sse2_loadsd_1 (operands[0], operands[1],
24262 CONST0_RTX (V2DFmode)));
24266 (define_insn "sse2_loadsd_1"
24267 [(set (match_operand:V2DF 0 "register_operand" "=x")
24269 (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m"))
24270 (match_operand:V2DF 2 "const0_operand" "X")
24273 "movsd\t{%1, %0|%0, %1}"
24274 [(set_attr "type" "ssecvt")
24275 (set_attr "mode" "DF")])
24277 (define_insn "sse2_movsd"
24278 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
24280 (match_operand:V2DF 1 "nonimmediate_operand" "0,0,0")
24281 (match_operand:V2DF 2 "nonimmediate_operand" "x,m,x")
24283 "TARGET_SSE2 && ix86_binary_operator_ok (UNKNOWN, V2DFmode, operands)"
24284 "@movsd\t{%2, %0|%0, %2}
24285 movlpd\t{%2, %0|%0, %2}
24286 movlpd\t{%2, %0|%0, %2}"
24287 [(set_attr "type" "ssecvt")
24288 (set_attr "mode" "DF,V2DF,V2DF")])
24290 (define_insn "sse2_storesd"
24291 [(set (match_operand:DF 0 "memory_operand" "=m")
24293 (match_operand:V2DF 1 "register_operand" "x")
24294 (parallel [(const_int 0)])))]
24296 "movsd\t{%1, %0|%0, %1}"
24297 [(set_attr "type" "ssecvt")
24298 (set_attr "mode" "DF")])
24300 (define_insn "sse2_shufpd"
24301 [(set (match_operand:V2DF 0 "register_operand" "=x")
24302 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
24303 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
24304 (match_operand:SI 3 "immediate_operand" "i")]
24307 ;; @@@ check operand order for intel/nonintel syntax
24308 "shufpd\t{%3, %2, %0|%0, %2, %3}"
24309 [(set_attr "type" "ssecvt")
24310 (set_attr "mode" "V2DF")])
24312 (define_insn "sse2_clflush"
24313 [(unspec_volatile [(match_operand 0 "address_operand" "p")]
24317 [(set_attr "type" "sse")
24318 (set_attr "memory" "unknown")])
24320 (define_expand "sse2_mfence"
24321 [(set (match_dup 0)
24322 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
24325 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
24326 MEM_VOLATILE_P (operands[0]) = 1;
24329 (define_insn "*mfence_insn"
24330 [(set (match_operand:BLK 0 "" "")
24331 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
24334 [(set_attr "type" "sse")
24335 (set_attr "memory" "unknown")])
24337 (define_expand "sse2_lfence"
24338 [(set (match_dup 0)
24339 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
24342 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
24343 MEM_VOLATILE_P (operands[0]) = 1;
24346 (define_insn "*lfence_insn"
24347 [(set (match_operand:BLK 0 "" "")
24348 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
24351 [(set_attr "type" "sse")
24352 (set_attr "memory" "unknown")])
24356 (define_insn "mwait"
24357 [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
24358 (match_operand:SI 1 "register_operand" "c")]
24362 [(set_attr "length" "3")])
24364 (define_insn "monitor"
24365 [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
24366 (match_operand:SI 1 "register_operand" "c")
24367 (match_operand:SI 2 "register_operand" "d")]
24370 "monitor\t%0, %1, %2"
24371 [(set_attr "length" "3")])
24375 (define_insn "addsubv4sf3"
24376 [(set (match_operand:V4SF 0 "register_operand" "=x")
24377 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
24378 (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
24381 "addsubps\t{%2, %0|%0, %2}"
24382 [(set_attr "type" "sseadd")
24383 (set_attr "mode" "V4SF")])
24385 (define_insn "addsubv2df3"
24386 [(set (match_operand:V2DF 0 "register_operand" "=x")
24387 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
24388 (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
24391 "addsubpd\t{%2, %0|%0, %2}"
24392 [(set_attr "type" "sseadd")
24393 (set_attr "mode" "V2DF")])
24395 (define_insn "haddv4sf3"
24396 [(set (match_operand:V4SF 0 "register_operand" "=x")
24397 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
24398 (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
24401 "haddps\t{%2, %0|%0, %2}"
24402 [(set_attr "type" "sseadd")
24403 (set_attr "mode" "V4SF")])
24405 (define_insn "haddv2df3"
24406 [(set (match_operand:V2DF 0 "register_operand" "=x")
24407 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
24408 (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
24411 "haddpd\t{%2, %0|%0, %2}"
24412 [(set_attr "type" "sseadd")
24413 (set_attr "mode" "V2DF")])
24415 (define_insn "hsubv4sf3"
24416 [(set (match_operand:V4SF 0 "register_operand" "=x")
24417 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
24418 (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
24421 "hsubps\t{%2, %0|%0, %2}"
24422 [(set_attr "type" "sseadd")
24423 (set_attr "mode" "V4SF")])
24425 (define_insn "hsubv2df3"
24426 [(set (match_operand:V2DF 0 "register_operand" "=x")
24427 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
24428 (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
24431 "hsubpd\t{%2, %0|%0, %2}"
24432 [(set_attr "type" "sseadd")
24433 (set_attr "mode" "V2DF")])
24435 (define_insn "movshdup"
24436 [(set (match_operand:V4SF 0 "register_operand" "=x")
24438 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSHDUP))]
24440 "movshdup\t{%1, %0|%0, %1}"
24441 [(set_attr "type" "sse")
24442 (set_attr "mode" "V4SF")])
24444 (define_insn "movsldup"
24445 [(set (match_operand:V4SF 0 "register_operand" "=x")
24447 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSLDUP))]
24449 "movsldup\t{%1, %0|%0, %1}"
24450 [(set_attr "type" "sse")
24451 (set_attr "mode" "V4SF")])
24453 (define_insn "lddqu"
24454 [(set (match_operand:V16QI 0 "register_operand" "=x")
24455 (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")]
24458 "lddqu\t{%1, %0|%0, %1}"
24459 [(set_attr "type" "ssecvt")
24460 (set_attr "mode" "TI")])
24462 (define_insn "loadddup"
24463 [(set (match_operand:V2DF 0 "register_operand" "=x")
24464 (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m")))]
24466 "movddup\t{%1, %0|%0, %1}"
24467 [(set_attr "type" "ssecvt")
24468 (set_attr "mode" "DF")])
24470 (define_insn "movddup"
24471 [(set (match_operand:V2DF 0 "register_operand" "=x")
24472 (vec_duplicate:V2DF
24473 (vec_select:DF (match_operand:V2DF 1 "register_operand" "x")
24474 (parallel [(const_int 0)]))))]
24476 "movddup\t{%1, %0|%0, %1}"
24477 [(set_attr "type" "ssecvt")
24478 (set_attr "mode" "DF")])