1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 ;; Special constraints for s/390 machine description:
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; f -- Floating point registers.
31 ;; t -- Access registers 36 and 37.
32 ;; G -- Const double zero operand
33 ;; I -- An 8-bit constant (0..255).
34 ;; J -- A 12-bit constant (0..4095).
35 ;; K -- A 16-bit constant (-32768..32767).
36 ;; L -- Value appropriate as displacement.
37 ;; (0..4095) for short displacement
38 ;; (-524288..524287) for long displacement
39 ;; M -- Constant integer with a value of 0x7fffffff.
40 ;; N -- Multiple letter constraint followed by 4 parameter letters.
41 ;; 0..9,x: number of the part counting from most to least significant
42 ;; H,Q: mode of the part
43 ;; D,S,H: mode of the containing operand
44 ;; 0,F: value of the other parts (F - all bits set)
46 ;; The constraint matches if the specified part of a constant
47 ;; has a value different from its other parts. If the letter x
48 ;; is specified instead of a part number, the constraint matches
49 ;; if there is any single part with non-default value.
50 ;; O -- Multiple letter constraint followed by 1 parameter.
51 ;; s: Signed extended immediate value (-2G .. 2G-1).
52 ;; p: Positive extended immediate value (0 .. 4G-1).
53 ;; n: Negative extended immediate value (-4G .. -1).
54 ;; These constraints do not accept any operand if the machine does
55 ;; not provide the extended-immediate facility.
56 ;; P -- Any integer constant that can be loaded without literal pool.
57 ;; Q -- Memory reference without index register and with short displacement.
58 ;; R -- Memory reference with index register and short displacement.
59 ;; S -- Memory reference without index register but with long displacement.
60 ;; T -- Memory reference with index register and long displacement.
61 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
62 ;; Offsettable memory reference of type specified by second letter.
63 ;; B -- Multiple letter constraint followed by Q, R, S, or T:
64 ;; Memory reference of the type specified by second letter that
65 ;; does *not* refer to a literal pool entry.
66 ;; U -- Pointer with short displacement.
67 ;; W -- Pointer with long displacement.
68 ;; Y -- Shift count operand.
70 ;; Special formats used for outputting 390 instructions.
72 ;; %C: print opcode suffix for branch condition.
73 ;; %D: print opcode suffix for inverse branch condition.
74 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
75 ;; %G: print the size of the operand in bytes.
76 ;; %O: print only the displacement of a memory reference.
77 ;; %R: print only the base register of a memory reference.
78 ;; %S: print S-type memory reference (base+displacement).
79 ;; %N: print the second word of a DImode operand.
80 ;; %M: print the second word of a TImode operand.
81 ;; %Y: print shift count operand.
83 ;; %b: print integer X as if it's an unsigned byte.
84 ;; %x: print integer X as if it's an unsigned halfword.
85 ;; %h: print integer X as if it's a signed halfword.
86 ;; %i: print the first nonzero HImode part of X.
87 ;; %j: print the first HImode part unequal to -1 of X.
88 ;; %k: print the first nonzero SImode part of X.
89 ;; %m: print the first SImode part unequal to -1 of X.
90 ;; %o: print integer X as if it's an unsigned 32bit word.
92 ;; We have a special constraint for pattern matching.
94 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
107 ; GOT/PLT and lt-relative accesses
108 (UNSPEC_LTREL_OFFSET 100)
109 (UNSPEC_LTREL_BASE 101)
117 (UNSPEC_RELOAD_BASE 210)
118 (UNSPEC_MAIN_BASE 211)
123 ; TLS relocation specifiers
128 (UNSPEC_GOTNTPOFF 504)
129 (UNSPEC_INDNTPOFF 505)
132 (UNSPEC_TLSLDM_NTPOFF 511)
133 (UNSPEC_TLS_LOAD 512)
139 ; Stack Smashing Protector
145 ;; UNSPEC_VOLATILE usage
153 (UNSPECV_TPF_PROLOGUE 20)
154 (UNSPECV_TPF_EPILOGUE 21)
158 (UNSPECV_POOL_SECTION 201)
159 (UNSPECV_POOL_ALIGN 202)
160 (UNSPECV_POOL_ENTRY 203)
161 (UNSPECV_MAIN_POOL 300)
177 ; Sibling call register.
179 ; Literal pool base register.
181 ; Return address register.
183 ; Condition code register.
185 ; Thread local storage pointer register.
190 ;; Instruction operand type as used in the Principles of Operation.
191 ;; Used to determine defaults for length and other attribute values.
193 (define_attr "op_type"
194 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
197 ;; Instruction type attribute used for scheduling.
199 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
200 cs,vs,store,sem,idiv,
201 imulhi,imulsi,imuldi,
202 branch,jsr,fsimpdf,fsimpsf,
203 floaddf,floadsf,fstoredf,fstoresf,
204 fmuldf,fmulsf,fdivdf,fdivsf,
205 ftoi,itof,fsqrtdf,fsqrtsf,
207 (cond [(eq_attr "op_type" "NN") (const_string "other")
208 (eq_attr "op_type" "SS") (const_string "cs")]
209 (const_string "integer")))
211 ;; Another attribute used for scheduling purposes:
212 ;; agen: Instruction uses the address generation unit
213 ;; reg: Instruction does not use the agen unit
215 (define_attr "atype" "agen,reg"
216 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE")
218 (const_string "agen")))
222 (define_attr "length" ""
223 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
224 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI") (const_int 4)]
228 ;; Processor type. This attribute must exactly match the processor_type
229 ;; enumeration in s390.h. The current machine description does not
230 ;; distinguish between g5 and g6, but there are differences between the two
231 ;; CPUs could in theory be modeled.
233 (define_attr "cpu" "g5,g6,z900,z990,z9_109"
234 (const (symbol_ref "s390_tune")))
236 ;; Pipeline description for z900. For lack of anything better,
237 ;; this description is also used for the g5 and g6.
240 ;; Pipeline description for z990.
244 (include "predicates.md")
251 ;; This mode macro allows DF and SF patterns to be generated from the
253 (define_mode_macro FPR [DF SF])
255 ;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated
256 ;; from the same template.
257 (define_mode_macro TDSI [(TI "TARGET_64BIT") DI SI])
259 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
260 ;; from the same template.
261 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
262 (define_mode_macro DSI [DI SI])
264 ;; This mode macro allows :P to be used for patterns that operate on
265 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
266 (define_mode_macro DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
267 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
269 ;; This mode macro allows the QI and HI patterns to be defined from
270 ;; the same template.
271 (define_mode_macro HQI [HI QI])
273 ;; This mode macro allows the integer patterns to be defined from the
275 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
277 ;; This macro allows to unify all 'bCOND' expander patterns.
278 (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
279 ordered uneq unlt ungt unle unge ltgt])
281 ;; This macro allows to unify all 'sCOND' patterns.
282 (define_code_macro SCOND [ltu gtu leu geu])
284 ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
285 ;; the same template.
286 (define_code_macro SHIFT [ashift lshiftrt])
288 ;; These macros allow to combine most atomic operations.
289 (define_code_macro ATOMIC [and ior xor plus minus mult])
290 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
291 (plus "add") (minus "sub") (mult "nand")])
294 ;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode
295 ;; and "ltebr" in SFmode.
296 (define_mode_attr de [(DF "d") (SF "e")])
298 ;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode
299 ;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern.
300 (define_mode_attr dee [(DF "d") (SF "ee")])
302 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
303 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
304 ;; version only operates on one register.
305 (define_mode_attr d0 [(DI "d") (SI "0")])
307 ;; In combination with d0 this allows to combine instructions of which the 31bit
308 ;; version only operates on one register. The DImode version needs an additional
309 ;; register for the assembler output.
310 (define_mode_attr 1 [(DI "%1,") (SI "")])
312 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
313 ;; 'ashift' and "srdl" in 'lshiftrt'.
314 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
316 ;; In SHIFT templates, this attribute holds the correct standard name for the
317 ;; pattern itself and the corresponding function calls.
318 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
320 ;; This attribute handles differences in the instruction 'type' and will result
321 ;; in "RRE" for DImode and "RR" for SImode.
322 (define_mode_attr E [(DI "E") (SI "")])
324 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
325 ;; to result in "RXY" for DImode and "RX" for SImode.
326 (define_mode_attr Y [(DI "Y") (SI "")])
328 ;; This attribute handles differences in the instruction 'type' and will result
329 ;; in "RSE" for TImode and "RS" for DImode.
330 (define_mode_attr TE [(TI "E") (DI "")])
332 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
333 ;; and "lcr" in SImode.
334 (define_mode_attr g [(DI "g") (SI "")])
336 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
337 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
338 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
339 ;; variant for long displacements.
340 (define_mode_attr y [(DI "g") (SI "y")])
342 ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode
343 ;; and "cds" in DImode.
344 (define_mode_attr tg [(TI "g") (DI "")])
346 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
347 ;; and "cfdbr" in SImode.
348 (define_mode_attr gf [(DI "g") (SI "f")])
350 ;; ICM mask required to load MODE value into the lowest subreg
351 ;; of a SImode register.
352 (define_mode_attr icm_lo [(HI "3") (QI "1")])
354 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
355 ;; HImode and "llgc" in QImode.
356 (define_mode_attr hc [(HI "h") (QI "c")])
358 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
360 (define_mode_attr DBL [(DI "TI") (SI "DI")])
362 ;; Maximum unsigned integer that fits in MODE.
363 (define_mode_attr max_uint [(HI "65535") (QI "255")])
367 ;;- Compare instructions.
370 (define_expand "cmp<mode>"
371 [(set (reg:CC CC_REGNUM)
372 (compare:CC (match_operand:GPR 0 "register_operand" "")
373 (match_operand:GPR 1 "general_operand" "")))]
376 s390_compare_op0 = operands[0];
377 s390_compare_op1 = operands[1];
381 (define_expand "cmp<mode>"
382 [(set (reg:CC CC_REGNUM)
383 (compare:CC (match_operand:FPR 0 "register_operand" "")
384 (match_operand:FPR 1 "general_operand" "")))]
387 s390_compare_op0 = operands[0];
388 s390_compare_op1 = operands[1];
393 ; Test-under-Mask instructions
395 (define_insn "*tmqi_mem"
396 [(set (reg CC_REGNUM)
397 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
398 (match_operand:QI 1 "immediate_operand" "n,n"))
399 (match_operand:QI 2 "immediate_operand" "n,n")))]
400 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
404 [(set_attr "op_type" "SI,SIY")])
406 (define_insn "*tmdi_reg"
407 [(set (reg CC_REGNUM)
408 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
409 (match_operand:DI 1 "immediate_operand"
410 "N0HD0,N1HD0,N2HD0,N3HD0"))
411 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
413 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
414 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
420 [(set_attr "op_type" "RI")])
422 (define_insn "*tmsi_reg"
423 [(set (reg CC_REGNUM)
424 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
425 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
426 (match_operand:SI 2 "immediate_operand" "n,n")))]
427 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
428 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
432 [(set_attr "op_type" "RI")])
434 (define_insn "*tm<mode>_full"
435 [(set (reg CC_REGNUM)
436 (compare (match_operand:HQI 0 "register_operand" "d")
437 (match_operand:HQI 1 "immediate_operand" "n")))]
438 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
440 [(set_attr "op_type" "RI")])
444 ; Load-and-Test instructions
447 ; tst(di|si) intruction pattern(s).
449 (define_insn "*tstdi_sign"
450 [(set (reg CC_REGNUM)
451 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
452 (const_int 32)) (const_int 32))
453 (match_operand:DI 1 "const0_operand" "")))
454 (set (match_operand:DI 2 "register_operand" "=d")
455 (sign_extend:DI (match_dup 0)))]
456 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
458 [(set_attr "op_type" "RRE")])
460 (define_insn "*tst<mode>_extimm"
461 [(set (reg CC_REGNUM)
462 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
463 (match_operand:GPR 1 "const0_operand" "")))
464 (set (match_operand:GPR 2 "register_operand" "=d,d")
466 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
470 [(set_attr "op_type" "RR<E>,RXY")])
472 (define_insn "*tst<mode>_cconly_extimm"
473 [(set (reg CC_REGNUM)
474 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
475 (match_operand:GPR 1 "const0_operand" "")))
476 (clobber (match_scratch:GPR 2 "=X,d"))]
477 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
481 [(set_attr "op_type" "RR<E>,RXY")])
483 (define_insn "*tstdi"
484 [(set (reg CC_REGNUM)
485 (compare (match_operand:DI 0 "register_operand" "d")
486 (match_operand:DI 1 "const0_operand" "")))
487 (set (match_operand:DI 2 "register_operand" "=d")
489 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
491 [(set_attr "op_type" "RRE")])
493 (define_insn "*tstsi"
494 [(set (reg CC_REGNUM)
495 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
496 (match_operand:SI 1 "const0_operand" "")))
497 (set (match_operand:SI 2 "register_operand" "=d,d,d")
499 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
504 [(set_attr "op_type" "RR,RS,RSY")])
506 (define_insn "*tstsi_cconly"
507 [(set (reg CC_REGNUM)
508 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
509 (match_operand:SI 1 "const0_operand" "")))
510 (clobber (match_scratch:SI 2 "=X,d,d"))]
511 "s390_match_ccmode(insn, CCSmode)"
516 [(set_attr "op_type" "RR,RS,RSY")])
518 (define_insn "*tstdi_cconly_31"
519 [(set (reg CC_REGNUM)
520 (compare (match_operand:DI 0 "register_operand" "d")
521 (match_operand:DI 1 "const0_operand" "")))]
522 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
524 [(set_attr "op_type" "RS")
525 (set_attr "atype" "reg")])
527 (define_insn "*tst<mode>_cconly2"
528 [(set (reg CC_REGNUM)
529 (compare (match_operand:GPR 0 "register_operand" "d")
530 (match_operand:GPR 1 "const0_operand" "")))]
531 "s390_match_ccmode(insn, CCSmode)"
533 [(set_attr "op_type" "RR<E>")])
535 ; tst(hi|qi) intruction pattern(s).
537 (define_insn "*tst<mode>CCT"
538 [(set (reg CC_REGNUM)
539 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
540 (match_operand:HQI 1 "const0_operand" "")))
541 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
543 "s390_match_ccmode(insn, CCTmode)"
546 icmy\t%2,<icm_lo>,%S0
548 [(set_attr "op_type" "RS,RSY,RI")])
550 (define_insn "*tsthiCCT_cconly"
551 [(set (reg CC_REGNUM)
552 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
553 (match_operand:HI 1 "const0_operand" "")))
554 (clobber (match_scratch:HI 2 "=d,d,X"))]
555 "s390_match_ccmode(insn, CCTmode)"
560 [(set_attr "op_type" "RS,RSY,RI")])
562 (define_insn "*tstqiCCT_cconly"
563 [(set (reg CC_REGNUM)
564 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
565 (match_operand:QI 1 "const0_operand" "")))]
566 "s390_match_ccmode(insn, CCTmode)"
571 [(set_attr "op_type" "SI,SIY,RI")])
573 (define_insn "*tst<mode>"
574 [(set (reg CC_REGNUM)
575 (compare (match_operand:HQI 0 "s_operand" "Q,S")
576 (match_operand:HQI 1 "const0_operand" "")))
577 (set (match_operand:HQI 2 "register_operand" "=d,d")
579 "s390_match_ccmode(insn, CCSmode)"
582 icmy\t%2,<icm_lo>,%S0"
583 [(set_attr "op_type" "RS,RSY")])
585 (define_insn "*tst<mode>_cconly"
586 [(set (reg CC_REGNUM)
587 (compare (match_operand:HQI 0 "s_operand" "Q,S")
588 (match_operand:HQI 1 "const0_operand" "")))
589 (clobber (match_scratch:HQI 2 "=d,d"))]
590 "s390_match_ccmode(insn, CCSmode)"
593 icmy\t%2,<icm_lo>,%S0"
594 [(set_attr "op_type" "RS,RSY")])
597 ; Compare (equality) instructions
599 (define_insn "*cmpdi_cct"
600 [(set (reg CC_REGNUM)
601 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
602 (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))]
603 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
610 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")])
612 (define_insn "*cmpsi_cct"
613 [(set (reg CC_REGNUM)
614 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
615 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
616 "s390_match_ccmode (insn, CCTmode)"
624 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")])
627 ; Compare (signed) instructions
629 (define_insn "*cmpdi_ccs_sign"
630 [(set (reg CC_REGNUM)
631 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
632 (match_operand:DI 0 "register_operand" "d,d")))]
633 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
637 [(set_attr "op_type" "RRE,RXY")])
639 (define_insn "*cmpsi_ccs_sign"
640 [(set (reg CC_REGNUM)
641 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
642 (match_operand:SI 0 "register_operand" "d,d")))]
643 "s390_match_ccmode(insn, CCSRmode)"
647 [(set_attr "op_type" "RX,RXY")])
649 (define_insn "*cmp<mode>_ccs"
650 [(set (reg CC_REGNUM)
651 (compare (match_operand:GPR 0 "register_operand" "d,d,d,d,d")
652 (match_operand:GPR 1 "general_operand" "d,K,Os,R,T")))]
653 "s390_match_ccmode(insn, CCSmode)"
660 [(set_attr "op_type" "RR<E>,RI,RIL,RX<Y>,RXY")])
663 ; Compare (unsigned) instructions
665 (define_insn "*cmpdi_ccu_zero"
666 [(set (reg CC_REGNUM)
667 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
668 (match_operand:DI 0 "register_operand" "d,d")))]
669 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
673 [(set_attr "op_type" "RRE,RXY")])
675 (define_insn "*cmpdi_ccu"
676 [(set (reg CC_REGNUM)
677 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
678 (match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))]
679 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
686 [(set_attr "op_type" "RRE,RIL,RXY,SS,SS")])
688 (define_insn "*cmpsi_ccu"
689 [(set (reg CC_REGNUM)
690 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ")
691 (match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))]
692 "s390_match_ccmode (insn, CCUmode)"
700 [(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")])
702 (define_insn "*cmphi_ccu"
703 [(set (reg CC_REGNUM)
704 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
705 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
706 "s390_match_ccmode (insn, CCUmode)
707 && !register_operand (operands[1], HImode)"
713 [(set_attr "op_type" "RS,RSY,SS,SS")])
715 (define_insn "*cmpqi_ccu"
716 [(set (reg CC_REGNUM)
717 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
718 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
719 "s390_match_ccmode (insn, CCUmode)
720 && !register_operand (operands[1], QImode)"
728 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
731 ; Block compare (CLC) instruction patterns.
734 [(set (reg CC_REGNUM)
735 (compare (match_operand:BLK 0 "memory_operand" "Q")
736 (match_operand:BLK 1 "memory_operand" "Q")))
737 (use (match_operand 2 "const_int_operand" "n"))]
738 "s390_match_ccmode (insn, CCUmode)
739 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
740 "clc\t%O0(%2,%R0),%S1"
741 [(set_attr "op_type" "SS")])
744 [(set (reg CC_REGNUM)
745 (compare (match_operand 0 "memory_operand" "")
746 (match_operand 1 "memory_operand" "")))]
748 && s390_match_ccmode (insn, CCUmode)
749 && GET_MODE (operands[0]) == GET_MODE (operands[1])
750 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
752 [(set (match_dup 0) (match_dup 1))
753 (use (match_dup 2))])]
755 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
756 operands[0] = adjust_address (operands[0], BLKmode, 0);
757 operands[1] = adjust_address (operands[1], BLKmode, 0);
759 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
760 operands[0], operands[1]);
761 operands[0] = SET_DEST (PATTERN (curr_insn));
765 ; (DF|SF) instructions
767 (define_insn "*cmp<mode>_ccs_0"
768 [(set (reg CC_REGNUM)
769 (compare (match_operand:FPR 0 "register_operand" "f")
770 (match_operand:FPR 1 "const0_operand" "")))]
771 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
773 [(set_attr "op_type" "RRE")
774 (set_attr "type" "fsimp<mode>")])
776 (define_insn "*cmp<mode>_ccs_0_ibm"
777 [(set (reg CC_REGNUM)
778 (compare (match_operand:FPR 0 "register_operand" "f")
779 (match_operand:FPR 1 "const0_operand" "")))]
780 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
782 [(set_attr "op_type" "RR")
783 (set_attr "type" "fsimp<mode>")])
785 (define_insn "*cmp<mode>_ccs"
786 [(set (reg CC_REGNUM)
787 (compare (match_operand:FPR 0 "register_operand" "f,f")
788 (match_operand:FPR 1 "general_operand" "f,R")))]
789 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
793 [(set_attr "op_type" "RRE,RXE")
794 (set_attr "type" "fsimp<mode>")])
796 (define_insn "*cmp<mode>_ccs_ibm"
797 [(set (reg CC_REGNUM)
798 (compare (match_operand:FPR 0 "register_operand" "f,f")
799 (match_operand:FPR 1 "general_operand" "f,R")))]
800 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
804 [(set_attr "op_type" "RR,RX")
805 (set_attr "type" "fsimp<mode>")])
809 ;;- Move instructions.
813 ; movti instruction pattern(s).
817 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
818 (match_operand:TI 1 "general_operand" "QS,d,dPm,d,Q"))]
826 [(set_attr "op_type" "RSY,RSY,*,*,SS")
827 (set_attr "type" "lm,stm,*,*,*")])
830 [(set (match_operand:TI 0 "nonimmediate_operand" "")
831 (match_operand:TI 1 "general_operand" ""))]
832 "TARGET_64BIT && reload_completed
833 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
834 [(set (match_dup 2) (match_dup 4))
835 (set (match_dup 3) (match_dup 5))]
837 operands[2] = operand_subword (operands[0], 0, 0, TImode);
838 operands[3] = operand_subword (operands[0], 1, 0, TImode);
839 operands[4] = operand_subword (operands[1], 0, 0, TImode);
840 operands[5] = operand_subword (operands[1], 1, 0, TImode);
844 [(set (match_operand:TI 0 "nonimmediate_operand" "")
845 (match_operand:TI 1 "general_operand" ""))]
846 "TARGET_64BIT && reload_completed
847 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
848 [(set (match_dup 2) (match_dup 4))
849 (set (match_dup 3) (match_dup 5))]
851 operands[2] = operand_subword (operands[0], 1, 0, TImode);
852 operands[3] = operand_subword (operands[0], 0, 0, TImode);
853 operands[4] = operand_subword (operands[1], 1, 0, TImode);
854 operands[5] = operand_subword (operands[1], 0, 0, TImode);
858 [(set (match_operand:TI 0 "register_operand" "")
859 (match_operand:TI 1 "memory_operand" ""))]
860 "TARGET_64BIT && reload_completed
861 && !s_operand (operands[1], VOIDmode)"
862 [(set (match_dup 0) (match_dup 1))]
864 rtx addr = operand_subword (operands[0], 1, 0, TImode);
865 s390_load_address (addr, XEXP (operands[1], 0));
866 operands[1] = replace_equiv_address (operands[1], addr);
869 (define_expand "reload_outti"
870 [(parallel [(match_operand:TI 0 "" "")
871 (match_operand:TI 1 "register_operand" "d")
872 (match_operand:DI 2 "register_operand" "=&a")])]
875 gcc_assert (MEM_P (operands[0]));
876 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
877 operands[0] = replace_equiv_address (operands[0], operands[2]);
878 emit_move_insn (operands[0], operands[1]);
883 ; movdi instruction pattern(s).
886 (define_expand "movdi"
887 [(set (match_operand:DI 0 "general_operand" "")
888 (match_operand:DI 1 "general_operand" ""))]
891 /* Handle symbolic constants. */
892 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
893 emit_symbolic_move (operands);
896 (define_insn "*movdi_larl"
897 [(set (match_operand:DI 0 "register_operand" "=d")
898 (match_operand:DI 1 "larl_operand" "X"))]
900 && !FP_REG_P (operands[0])"
902 [(set_attr "op_type" "RIL")
903 (set_attr "type" "larl")])
905 (define_insn "*movdi_64extimm"
906 [(set (match_operand:DI 0 "nonimmediate_operand"
907 "=d,d,d,d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
908 (match_operand:DI 1 "general_operand"
909 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
910 "TARGET_64BIT && TARGET_EXTIMM"
934 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RXY,RRE,RXY,RXY,
935 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
936 (set_attr "type" "*,*,*,*,*,*,*,*,la,lr,load,store,
937 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
939 (define_insn "*movdi_64"
940 [(set (match_operand:DI 0 "nonimmediate_operand"
941 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
942 (match_operand:DI 1 "general_operand"
943 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
944 "TARGET_64BIT && !TARGET_EXTIMM"
965 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
966 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
967 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
968 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
971 [(set (match_operand:DI 0 "register_operand" "")
972 (match_operand:DI 1 "register_operand" ""))]
973 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
974 [(set (match_dup 2) (match_dup 3))
975 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
976 (set (strict_low_part (match_dup 2)) (match_dup 4))]
977 "operands[2] = gen_lowpart (SImode, operands[0]);
978 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
981 [(set (match_operand:DI 0 "register_operand" "")
982 (match_operand:DI 1 "register_operand" ""))]
983 "TARGET_64BIT && ACCESS_REG_P (operands[0])
984 && dead_or_set_p (insn, operands[1])"
985 [(set (match_dup 3) (match_dup 2))
986 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
987 (set (match_dup 4) (match_dup 2))]
988 "operands[2] = gen_lowpart (SImode, operands[1]);
989 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
992 [(set (match_operand:DI 0 "register_operand" "")
993 (match_operand:DI 1 "register_operand" ""))]
994 "TARGET_64BIT && ACCESS_REG_P (operands[0])
995 && !dead_or_set_p (insn, operands[1])"
996 [(set (match_dup 3) (match_dup 2))
997 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
998 (set (match_dup 4) (match_dup 2))
999 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1000 "operands[2] = gen_lowpart (SImode, operands[1]);
1001 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1003 (define_insn "*movdi_31"
1004 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q")
1005 (match_operand:DI 1 "general_operand" "Q,S,d,d,dPm,d,*f,R,T,*f,*f,Q"))]
1020 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS")
1021 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
1024 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1025 (match_operand:DI 1 "general_operand" ""))]
1026 "!TARGET_64BIT && reload_completed
1027 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1028 [(set (match_dup 2) (match_dup 4))
1029 (set (match_dup 3) (match_dup 5))]
1031 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1032 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1033 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1034 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1038 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1039 (match_operand:DI 1 "general_operand" ""))]
1040 "!TARGET_64BIT && reload_completed
1041 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1042 [(set (match_dup 2) (match_dup 4))
1043 (set (match_dup 3) (match_dup 5))]
1045 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1046 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1047 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1048 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1052 [(set (match_operand:DI 0 "register_operand" "")
1053 (match_operand:DI 1 "memory_operand" ""))]
1054 "!TARGET_64BIT && reload_completed
1055 && !FP_REG_P (operands[0])
1056 && !s_operand (operands[1], VOIDmode)"
1057 [(set (match_dup 0) (match_dup 1))]
1059 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1060 s390_load_address (addr, XEXP (operands[1], 0));
1061 operands[1] = replace_equiv_address (operands[1], addr);
1064 (define_expand "reload_outdi"
1065 [(parallel [(match_operand:DI 0 "" "")
1066 (match_operand:DI 1 "register_operand" "d")
1067 (match_operand:SI 2 "register_operand" "=&a")])]
1070 gcc_assert (MEM_P (operands[0]));
1071 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1072 operands[0] = replace_equiv_address (operands[0], operands[2]);
1073 emit_move_insn (operands[0], operands[1]);
1078 [(set (match_operand:DI 0 "register_operand" "")
1079 (mem:DI (match_operand 1 "address_operand" "")))]
1081 && !FP_REG_P (operands[0])
1082 && GET_CODE (operands[1]) == SYMBOL_REF
1083 && CONSTANT_POOL_ADDRESS_P (operands[1])
1084 && get_pool_mode (operands[1]) == DImode
1085 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1086 [(set (match_dup 0) (match_dup 2))]
1087 "operands[2] = get_pool_constant (operands[1]);")
1089 (define_insn "*la_64"
1090 [(set (match_operand:DI 0 "register_operand" "=d,d")
1091 (match_operand:QI 1 "address_operand" "U,W"))]
1096 [(set_attr "op_type" "RX,RXY")
1097 (set_attr "type" "la")])
1101 [(set (match_operand:DI 0 "register_operand" "")
1102 (match_operand:QI 1 "address_operand" ""))
1103 (clobber (reg:CC CC_REGNUM))])]
1105 && preferred_la_operand_p (operands[1], const0_rtx)"
1106 [(set (match_dup 0) (match_dup 1))]
1110 [(set (match_operand:DI 0 "register_operand" "")
1111 (match_operand:DI 1 "register_operand" ""))
1114 (plus:DI (match_dup 0)
1115 (match_operand:DI 2 "nonmemory_operand" "")))
1116 (clobber (reg:CC CC_REGNUM))])]
1118 && !reg_overlap_mentioned_p (operands[0], operands[2])
1119 && preferred_la_operand_p (operands[1], operands[2])"
1120 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1123 (define_expand "reload_indi"
1124 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1125 (match_operand:DI 1 "s390_plus_operand" "")
1126 (match_operand:DI 2 "register_operand" "=&a")])]
1129 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1134 ; movsi instruction pattern(s).
1137 (define_expand "movsi"
1138 [(set (match_operand:SI 0 "general_operand" "")
1139 (match_operand:SI 1 "general_operand" ""))]
1142 /* Handle symbolic constants. */
1143 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1144 emit_symbolic_move (operands);
1147 (define_insn "*movsi_larl"
1148 [(set (match_operand:SI 0 "register_operand" "=d")
1149 (match_operand:SI 1 "larl_operand" "X"))]
1150 "!TARGET_64BIT && TARGET_CPU_ZARCH
1151 && !FP_REG_P (operands[0])"
1153 [(set_attr "op_type" "RIL")
1154 (set_attr "type" "larl")])
1156 (define_insn "*movsi_zarch"
1157 [(set (match_operand:SI 0 "nonimmediate_operand"
1158 "=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1159 (match_operand:SI 1 "general_operand"
1160 "K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1183 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY,
1184 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1185 (set_attr "type" "*,*,*,*,la,lr,load,load,store,store,
1186 floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1188 (define_insn "*movsi_esa"
1189 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1190 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1205 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1206 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1209 [(set (match_operand:SI 0 "register_operand" "")
1210 (mem:SI (match_operand 1 "address_operand" "")))]
1211 "!FP_REG_P (operands[0])
1212 && GET_CODE (operands[1]) == SYMBOL_REF
1213 && CONSTANT_POOL_ADDRESS_P (operands[1])
1214 && get_pool_mode (operands[1]) == SImode
1215 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1216 [(set (match_dup 0) (match_dup 2))]
1217 "operands[2] = get_pool_constant (operands[1]);")
1219 (define_insn "*la_31"
1220 [(set (match_operand:SI 0 "register_operand" "=d,d")
1221 (match_operand:QI 1 "address_operand" "U,W"))]
1222 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1226 [(set_attr "op_type" "RX,RXY")
1227 (set_attr "type" "la")])
1231 [(set (match_operand:SI 0 "register_operand" "")
1232 (match_operand:QI 1 "address_operand" ""))
1233 (clobber (reg:CC CC_REGNUM))])]
1235 && preferred_la_operand_p (operands[1], const0_rtx)"
1236 [(set (match_dup 0) (match_dup 1))]
1240 [(set (match_operand:SI 0 "register_operand" "")
1241 (match_operand:SI 1 "register_operand" ""))
1244 (plus:SI (match_dup 0)
1245 (match_operand:SI 2 "nonmemory_operand" "")))
1246 (clobber (reg:CC CC_REGNUM))])]
1248 && !reg_overlap_mentioned_p (operands[0], operands[2])
1249 && preferred_la_operand_p (operands[1], operands[2])"
1250 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1253 (define_insn "*la_31_and"
1254 [(set (match_operand:SI 0 "register_operand" "=d,d")
1255 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1256 (const_int 2147483647)))]
1261 [(set_attr "op_type" "RX,RXY")
1262 (set_attr "type" "la")])
1264 (define_insn_and_split "*la_31_and_cc"
1265 [(set (match_operand:SI 0 "register_operand" "=d")
1266 (and:SI (match_operand:QI 1 "address_operand" "p")
1267 (const_int 2147483647)))
1268 (clobber (reg:CC CC_REGNUM))]
1271 "&& reload_completed"
1273 (and:SI (match_dup 1) (const_int 2147483647)))]
1275 [(set_attr "op_type" "RX")
1276 (set_attr "type" "la")])
1278 (define_insn "force_la_31"
1279 [(set (match_operand:SI 0 "register_operand" "=d,d")
1280 (match_operand:QI 1 "address_operand" "U,W"))
1281 (use (const_int 0))]
1286 [(set_attr "op_type" "RX")
1287 (set_attr "type" "la")])
1289 (define_expand "reload_insi"
1290 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1291 (match_operand:SI 1 "s390_plus_operand" "")
1292 (match_operand:SI 2 "register_operand" "=&a")])]
1295 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1300 ; movhi instruction pattern(s).
1303 (define_expand "movhi"
1304 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1305 (match_operand:HI 1 "general_operand" ""))]
1308 /* Make it explicit that loading a register from memory
1309 always sign-extends (at least) to SImode. */
1310 if (optimize && !no_new_pseudos
1311 && register_operand (operands[0], VOIDmode)
1312 && GET_CODE (operands[1]) == MEM)
1314 rtx tmp = gen_reg_rtx (SImode);
1315 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1316 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1317 operands[1] = gen_lowpart (HImode, tmp);
1321 (define_insn "*movhi"
1322 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1323 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1333 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1334 (set_attr "type" "lr,*,*,*,store,store,*")])
1337 [(set (match_operand:HI 0 "register_operand" "")
1338 (mem:HI (match_operand 1 "address_operand" "")))]
1339 "GET_CODE (operands[1]) == SYMBOL_REF
1340 && CONSTANT_POOL_ADDRESS_P (operands[1])
1341 && get_pool_mode (operands[1]) == HImode
1342 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1343 [(set (match_dup 0) (match_dup 2))]
1344 "operands[2] = get_pool_constant (operands[1]);")
1347 ; movqi instruction pattern(s).
1350 (define_expand "movqi"
1351 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1352 (match_operand:QI 1 "general_operand" ""))]
1355 /* On z/Architecture, zero-extending from memory to register
1356 is just as fast as a QImode load. */
1357 if (TARGET_ZARCH && optimize && !no_new_pseudos
1358 && register_operand (operands[0], VOIDmode)
1359 && GET_CODE (operands[1]) == MEM)
1361 rtx tmp = gen_reg_rtx (word_mode);
1362 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1363 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1364 operands[1] = gen_lowpart (QImode, tmp);
1368 (define_insn "*movqi"
1369 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1370 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1382 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1383 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1386 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1387 (mem:QI (match_operand 1 "address_operand" "")))]
1388 "GET_CODE (operands[1]) == SYMBOL_REF
1389 && CONSTANT_POOL_ADDRESS_P (operands[1])
1390 && get_pool_mode (operands[1]) == QImode
1391 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1392 [(set (match_dup 0) (match_dup 2))]
1393 "operands[2] = get_pool_constant (operands[1]);")
1396 ; movstrictqi instruction pattern(s).
1399 (define_insn "*movstrictqi"
1400 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1401 (match_operand:QI 1 "memory_operand" "R,T"))]
1406 [(set_attr "op_type" "RX,RXY")])
1409 ; movstricthi instruction pattern(s).
1412 (define_insn "*movstricthi"
1413 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1414 (match_operand:HI 1 "memory_operand" "Q,S"))
1415 (clobber (reg:CC CC_REGNUM))]
1420 [(set_attr "op_type" "RS,RSY")])
1423 ; movstrictsi instruction pattern(s).
1426 (define_insn "movstrictsi"
1427 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1428 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1435 [(set_attr "op_type" "RR,RX,RXY,RRE")
1436 (set_attr "type" "lr,load,load,*")])
1439 ; movdf instruction pattern(s).
1442 (define_expand "movdf"
1443 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1444 (match_operand:DF 1 "general_operand" ""))]
1448 (define_insn "*movdf_64"
1449 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
1450 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
1463 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1464 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
1466 (define_insn "*movdf_31"
1467 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q")
1468 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))]
1484 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
1485 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\
1486 lm,lm,stm,stm,*,*,*")])
1489 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1490 (match_operand:DF 1 "general_operand" ""))]
1491 "!TARGET_64BIT && reload_completed
1492 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1493 [(set (match_dup 2) (match_dup 4))
1494 (set (match_dup 3) (match_dup 5))]
1496 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1497 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1498 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1499 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1503 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1504 (match_operand:DF 1 "general_operand" ""))]
1505 "!TARGET_64BIT && reload_completed
1506 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1507 [(set (match_dup 2) (match_dup 4))
1508 (set (match_dup 3) (match_dup 5))]
1510 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1511 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1512 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1513 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1517 [(set (match_operand:DF 0 "register_operand" "")
1518 (match_operand:DF 1 "memory_operand" ""))]
1519 "!TARGET_64BIT && reload_completed
1520 && !FP_REG_P (operands[0])
1521 && !s_operand (operands[1], VOIDmode)"
1522 [(set (match_dup 0) (match_dup 1))]
1524 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1525 s390_load_address (addr, XEXP (operands[1], 0));
1526 operands[1] = replace_equiv_address (operands[1], addr);
1529 (define_expand "reload_outdf"
1530 [(parallel [(match_operand:DF 0 "" "")
1531 (match_operand:DF 1 "register_operand" "d")
1532 (match_operand:SI 2 "register_operand" "=&a")])]
1535 gcc_assert (MEM_P (operands[0]));
1536 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1537 operands[0] = replace_equiv_address (operands[0], operands[2]);
1538 emit_move_insn (operands[0], operands[1]);
1543 ; movsf instruction pattern(s).
1546 (define_insn "movsf"
1547 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
1548 (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
1563 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1564 (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
1565 lr,load,load,store,store,*")])
1568 ; movcc instruction pattern
1571 (define_insn "movcc"
1572 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1573 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1583 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1584 (set_attr "type" "lr,*,*,store,store,load,load")])
1587 ; Block move (MVC) patterns.
1591 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1592 (match_operand:BLK 1 "memory_operand" "Q"))
1593 (use (match_operand 2 "const_int_operand" "n"))]
1594 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1595 "mvc\t%O0(%2,%R0),%S1"
1596 [(set_attr "op_type" "SS")])
1599 [(set (match_operand 0 "memory_operand" "")
1600 (match_operand 1 "memory_operand" ""))]
1602 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1603 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1605 [(set (match_dup 0) (match_dup 1))
1606 (use (match_dup 2))])]
1608 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1609 operands[0] = adjust_address (operands[0], BLKmode, 0);
1610 operands[1] = adjust_address (operands[1], BLKmode, 0);
1615 [(set (match_operand:BLK 0 "memory_operand" "")
1616 (match_operand:BLK 1 "memory_operand" ""))
1617 (use (match_operand 2 "const_int_operand" ""))])
1619 [(set (match_operand:BLK 3 "memory_operand" "")
1620 (match_operand:BLK 4 "memory_operand" ""))
1621 (use (match_operand 5 "const_int_operand" ""))])]
1622 "s390_offset_p (operands[0], operands[3], operands[2])
1623 && s390_offset_p (operands[1], operands[4], operands[2])
1624 && !s390_overlap_p (operands[0], operands[1],
1625 INTVAL (operands[2]) + INTVAL (operands[5]))
1626 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1628 [(set (match_dup 6) (match_dup 7))
1629 (use (match_dup 8))])]
1630 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1631 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1632 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1636 ; load_multiple pattern(s).
1638 ; ??? Due to reload problems with replacing registers inside match_parallel
1639 ; we currently support load_multiple/store_multiple only after reload.
1642 (define_expand "load_multiple"
1643 [(match_par_dup 3 [(set (match_operand 0 "" "")
1644 (match_operand 1 "" ""))
1645 (use (match_operand 2 "" ""))])]
1648 enum machine_mode mode;
1654 /* Support only loading a constant number of fixed-point registers from
1655 memory and only bother with this if more than two */
1656 if (GET_CODE (operands[2]) != CONST_INT
1657 || INTVAL (operands[2]) < 2
1658 || INTVAL (operands[2]) > 16
1659 || GET_CODE (operands[1]) != MEM
1660 || GET_CODE (operands[0]) != REG
1661 || REGNO (operands[0]) >= 16)
1664 count = INTVAL (operands[2]);
1665 regno = REGNO (operands[0]);
1666 mode = GET_MODE (operands[0]);
1667 if (mode != SImode && mode != word_mode)
1670 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1673 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1675 from = XEXP (operands[1], 0);
1678 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1679 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1680 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1682 from = XEXP (XEXP (operands[1], 0), 0);
1683 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1690 from = force_reg (Pmode, XEXP (operands[1], 0));
1694 for (i = 0; i < count; i++)
1695 XVECEXP (operands[3], 0, i)
1696 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1697 change_address (operands[1], mode,
1698 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1701 (define_insn "*load_multiple_di"
1702 [(match_parallel 0 "load_multiple_operation"
1703 [(set (match_operand:DI 1 "register_operand" "=r")
1704 (match_operand:DI 2 "s_operand" "QS"))])]
1705 "reload_completed && word_mode == DImode"
1707 int words = XVECLEN (operands[0], 0);
1708 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1709 return "lmg\t%1,%0,%S2";
1711 [(set_attr "op_type" "RSY")
1712 (set_attr "type" "lm")])
1714 (define_insn "*load_multiple_si"
1715 [(match_parallel 0 "load_multiple_operation"
1716 [(set (match_operand:SI 1 "register_operand" "=r,r")
1717 (match_operand:SI 2 "s_operand" "Q,S"))])]
1720 int words = XVECLEN (operands[0], 0);
1721 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1722 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1724 [(set_attr "op_type" "RS,RSY")
1725 (set_attr "type" "lm")])
1728 ; store multiple pattern(s).
1731 (define_expand "store_multiple"
1732 [(match_par_dup 3 [(set (match_operand 0 "" "")
1733 (match_operand 1 "" ""))
1734 (use (match_operand 2 "" ""))])]
1737 enum machine_mode mode;
1743 /* Support only storing a constant number of fixed-point registers to
1744 memory and only bother with this if more than two. */
1745 if (GET_CODE (operands[2]) != CONST_INT
1746 || INTVAL (operands[2]) < 2
1747 || INTVAL (operands[2]) > 16
1748 || GET_CODE (operands[0]) != MEM
1749 || GET_CODE (operands[1]) != REG
1750 || REGNO (operands[1]) >= 16)
1753 count = INTVAL (operands[2]);
1754 regno = REGNO (operands[1]);
1755 mode = GET_MODE (operands[1]);
1756 if (mode != SImode && mode != word_mode)
1759 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1763 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1765 to = XEXP (operands[0], 0);
1768 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1769 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1770 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1772 to = XEXP (XEXP (operands[0], 0), 0);
1773 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1780 to = force_reg (Pmode, XEXP (operands[0], 0));
1784 for (i = 0; i < count; i++)
1785 XVECEXP (operands[3], 0, i)
1786 = gen_rtx_SET (VOIDmode,
1787 change_address (operands[0], mode,
1788 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1789 gen_rtx_REG (mode, regno + i));
1792 (define_insn "*store_multiple_di"
1793 [(match_parallel 0 "store_multiple_operation"
1794 [(set (match_operand:DI 1 "s_operand" "=QS")
1795 (match_operand:DI 2 "register_operand" "r"))])]
1796 "reload_completed && word_mode == DImode"
1798 int words = XVECLEN (operands[0], 0);
1799 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1800 return "stmg\t%2,%0,%S1";
1802 [(set_attr "op_type" "RSY")
1803 (set_attr "type" "stm")])
1806 (define_insn "*store_multiple_si"
1807 [(match_parallel 0 "store_multiple_operation"
1808 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1809 (match_operand:SI 2 "register_operand" "r,r"))])]
1812 int words = XVECLEN (operands[0], 0);
1813 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1814 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1816 [(set_attr "op_type" "RS,RSY")
1817 (set_attr "type" "stm")])
1820 ;; String instructions.
1823 (define_insn "*execute"
1824 [(match_parallel 0 ""
1825 [(unspec [(match_operand 1 "register_operand" "a")
1826 (match_operand:BLK 2 "memory_operand" "R")
1827 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1828 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1829 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1831 [(set_attr "op_type" "RX")
1832 (set_attr "type" "cs")])
1836 ; strlenM instruction pattern(s).
1839 (define_expand "strlen<mode>"
1840 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
1843 (unspec:P [(const_int 0)
1844 (match_operand:BLK 1 "memory_operand" "")
1846 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1847 (clobber (scratch:P))
1848 (clobber (reg:CC CC_REGNUM))])
1850 [(set (match_operand:P 0 "register_operand" "")
1851 (minus:P (match_dup 4) (match_dup 5)))
1852 (clobber (reg:CC CC_REGNUM))])]
1855 operands[4] = gen_reg_rtx (Pmode);
1856 operands[5] = gen_reg_rtx (Pmode);
1857 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1858 operands[1] = replace_equiv_address (operands[1], operands[5]);
1861 (define_insn "*strlen<mode>"
1862 [(set (match_operand:P 0 "register_operand" "=a")
1863 (unspec:P [(match_operand:P 2 "general_operand" "0")
1864 (mem:BLK (match_operand:P 3 "register_operand" "1"))
1866 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1867 (clobber (match_scratch:P 1 "=a"))
1868 (clobber (reg:CC CC_REGNUM))]
1870 "srst\t%0,%1\;jo\t.-4"
1871 [(set_attr "length" "8")
1872 (set_attr "type" "vs")])
1875 ; cmpstrM instruction pattern(s).
1878 (define_expand "cmpstrsi"
1879 [(set (reg:SI 0) (const_int 0))
1881 [(clobber (match_operand 3 "" ""))
1882 (clobber (match_dup 4))
1883 (set (reg:CCU CC_REGNUM)
1884 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
1885 (match_operand:BLK 2 "memory_operand" "")))
1888 [(set (match_operand:SI 0 "register_operand" "=d")
1889 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT))
1890 (clobber (reg:CC CC_REGNUM))])]
1893 /* As the result of CMPINT is inverted compared to what we need,
1894 we have to swap the operands. */
1895 rtx op1 = operands[2];
1896 rtx op2 = operands[1];
1897 rtx addr1 = gen_reg_rtx (Pmode);
1898 rtx addr2 = gen_reg_rtx (Pmode);
1900 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
1901 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
1902 operands[1] = replace_equiv_address_nv (op1, addr1);
1903 operands[2] = replace_equiv_address_nv (op2, addr2);
1904 operands[3] = addr1;
1905 operands[4] = addr2;
1908 (define_insn "*cmpstr<mode>"
1909 [(clobber (match_operand:P 0 "register_operand" "=d"))
1910 (clobber (match_operand:P 1 "register_operand" "=d"))
1911 (set (reg:CCU CC_REGNUM)
1912 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
1913 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
1916 "clst\t%0,%1\;jo\t.-4"
1917 [(set_attr "length" "8")
1918 (set_attr "type" "vs")])
1921 ; movstr instruction pattern.
1924 (define_expand "movstr"
1925 [(set (reg:SI 0) (const_int 0))
1927 [(clobber (match_dup 3))
1928 (set (match_operand:BLK 1 "memory_operand" "")
1929 (match_operand:BLK 2 "memory_operand" ""))
1930 (set (match_operand 0 "register_operand" "")
1931 (unspec [(match_dup 1)
1933 (reg:SI 0)] UNSPEC_MVST))
1934 (clobber (reg:CC CC_REGNUM))])]
1937 rtx addr1 = gen_reg_rtx (Pmode);
1938 rtx addr2 = gen_reg_rtx (Pmode);
1940 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1941 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
1942 operands[1] = replace_equiv_address_nv (operands[1], addr1);
1943 operands[2] = replace_equiv_address_nv (operands[2], addr2);
1944 operands[3] = addr2;
1947 (define_insn "*movstr"
1948 [(clobber (match_operand:P 2 "register_operand" "=d"))
1949 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
1950 (mem:BLK (match_operand:P 3 "register_operand" "2")))
1951 (set (match_operand:P 0 "register_operand" "=d")
1952 (unspec [(mem:BLK (match_dup 1))
1953 (mem:BLK (match_dup 3))
1954 (reg:SI 0)] UNSPEC_MVST))
1955 (clobber (reg:CC CC_REGNUM))]
1957 "mvst\t%1,%2\;jo\t.-4"
1958 [(set_attr "length" "8")
1959 (set_attr "type" "vs")])
1963 ; movmemM instruction pattern(s).
1966 (define_expand "movmem<mode>"
1967 [(set (match_operand:BLK 0 "memory_operand" "")
1968 (match_operand:BLK 1 "memory_operand" ""))
1969 (use (match_operand:GPR 2 "general_operand" ""))
1970 (match_operand 3 "" "")]
1972 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
1974 ; Move a block that is up to 256 bytes in length.
1975 ; The block length is taken as (operands[2] % 256) + 1.
1977 (define_expand "movmem_short"
1979 [(set (match_operand:BLK 0 "memory_operand" "")
1980 (match_operand:BLK 1 "memory_operand" ""))
1981 (use (match_operand 2 "nonmemory_operand" ""))
1982 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1983 (clobber (match_dup 3))])]
1985 "operands[3] = gen_rtx_SCRATCH (Pmode);")
1987 (define_insn "*movmem_short"
1988 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1989 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
1990 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
1991 (use (match_operand 3 "immediate_operand" "X,R,X"))
1992 (clobber (match_scratch 4 "=X,X,&a"))]
1993 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
1994 && GET_MODE (operands[4]) == Pmode"
1996 [(set_attr "type" "cs")])
1999 [(set (match_operand:BLK 0 "memory_operand" "")
2000 (match_operand:BLK 1 "memory_operand" ""))
2001 (use (match_operand 2 "const_int_operand" ""))
2002 (use (match_operand 3 "immediate_operand" ""))
2003 (clobber (scratch))]
2006 [(set (match_dup 0) (match_dup 1))
2007 (use (match_dup 2))])]
2008 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2011 [(set (match_operand:BLK 0 "memory_operand" "")
2012 (match_operand:BLK 1 "memory_operand" ""))
2013 (use (match_operand 2 "register_operand" ""))
2014 (use (match_operand 3 "memory_operand" ""))
2015 (clobber (scratch))]
2018 [(unspec [(match_dup 2) (match_dup 3)
2019 (const_int 0)] UNSPEC_EXECUTE)
2020 (set (match_dup 0) (match_dup 1))
2021 (use (const_int 1))])]
2025 [(set (match_operand:BLK 0 "memory_operand" "")
2026 (match_operand:BLK 1 "memory_operand" ""))
2027 (use (match_operand 2 "register_operand" ""))
2028 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2029 (clobber (match_operand 3 "register_operand" ""))]
2030 "reload_completed && TARGET_CPU_ZARCH"
2031 [(set (match_dup 3) (label_ref (match_dup 4)))
2033 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2034 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2035 (set (match_dup 0) (match_dup 1))
2036 (use (const_int 1))])]
2037 "operands[4] = gen_label_rtx ();")
2039 ; Move a block of arbitrary length.
2041 (define_expand "movmem_long"
2043 [(clobber (match_dup 2))
2044 (clobber (match_dup 3))
2045 (set (match_operand:BLK 0 "memory_operand" "")
2046 (match_operand:BLK 1 "memory_operand" ""))
2047 (use (match_operand 2 "general_operand" ""))
2049 (clobber (reg:CC CC_REGNUM))])]
2052 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2053 rtx reg0 = gen_reg_rtx (dword_mode);
2054 rtx reg1 = gen_reg_rtx (dword_mode);
2055 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2056 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2057 rtx len0 = gen_lowpart (Pmode, reg0);
2058 rtx len1 = gen_lowpart (Pmode, reg1);
2060 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2061 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2062 emit_move_insn (len0, operands[2]);
2064 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2065 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2066 emit_move_insn (len1, operands[2]);
2068 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2069 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2074 (define_insn "*movmem_long"
2075 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2076 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2077 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2078 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2081 (clobber (reg:CC CC_REGNUM))]
2083 "mvcle\t%0,%1,0\;jo\t.-4"
2084 [(set_attr "length" "8")
2085 (set_attr "type" "vs")])
2088 ; setmemM instruction pattern(s).
2091 (define_expand "setmem<mode>"
2092 [(set (match_operand:BLK 0 "memory_operand" "")
2093 (match_operand:QI 2 "general_operand" ""))
2094 (use (match_operand:GPR 1 "general_operand" ""))
2095 (match_operand 3 "" "")]
2097 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2099 ; Clear a block that is up to 256 bytes in length.
2100 ; The block length is taken as (operands[1] % 256) + 1.
2102 (define_expand "clrmem_short"
2104 [(set (match_operand:BLK 0 "memory_operand" "")
2106 (use (match_operand 1 "nonmemory_operand" ""))
2107 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2108 (clobber (match_dup 2))
2109 (clobber (reg:CC CC_REGNUM))])]
2111 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2113 (define_insn "*clrmem_short"
2114 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2116 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
2117 (use (match_operand 2 "immediate_operand" "X,R,X"))
2118 (clobber (match_scratch 3 "=X,X,&a"))
2119 (clobber (reg:CC CC_REGNUM))]
2120 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2121 && GET_MODE (operands[3]) == Pmode"
2123 [(set_attr "type" "cs")])
2126 [(set (match_operand:BLK 0 "memory_operand" "")
2128 (use (match_operand 1 "const_int_operand" ""))
2129 (use (match_operand 2 "immediate_operand" ""))
2131 (clobber (reg:CC CC_REGNUM))]
2134 [(set (match_dup 0) (const_int 0))
2136 (clobber (reg:CC CC_REGNUM))])]
2137 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2140 [(set (match_operand:BLK 0 "memory_operand" "")
2142 (use (match_operand 1 "register_operand" ""))
2143 (use (match_operand 2 "memory_operand" ""))
2145 (clobber (reg:CC CC_REGNUM))]
2148 [(unspec [(match_dup 1) (match_dup 2)
2149 (const_int 0)] UNSPEC_EXECUTE)
2150 (set (match_dup 0) (const_int 0))
2152 (clobber (reg:CC CC_REGNUM))])]
2156 [(set (match_operand:BLK 0 "memory_operand" "")
2158 (use (match_operand 1 "register_operand" ""))
2159 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2160 (clobber (match_operand 2 "register_operand" ""))
2161 (clobber (reg:CC CC_REGNUM))]
2162 "reload_completed && TARGET_CPU_ZARCH"
2163 [(set (match_dup 2) (label_ref (match_dup 3)))
2165 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2166 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2167 (set (match_dup 0) (const_int 0))
2169 (clobber (reg:CC CC_REGNUM))])]
2170 "operands[3] = gen_label_rtx ();")
2172 ; Initialize a block of arbitrary length with (operands[2] % 256).
2174 (define_expand "setmem_long"
2176 [(clobber (match_dup 1))
2177 (set (match_operand:BLK 0 "memory_operand" "")
2178 (match_operand 2 "shift_count_or_setmem_operand" ""))
2179 (use (match_operand 1 "general_operand" ""))
2181 (clobber (reg:CC CC_REGNUM))])]
2184 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2185 rtx reg0 = gen_reg_rtx (dword_mode);
2186 rtx reg1 = gen_reg_rtx (dword_mode);
2187 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2188 rtx len0 = gen_lowpart (Pmode, reg0);
2190 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2191 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2192 emit_move_insn (len0, operands[1]);
2194 emit_move_insn (reg1, const0_rtx);
2196 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2201 (define_insn "*setmem_long"
2202 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2203 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2204 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2206 (use (match_operand:<DBL> 1 "register_operand" "d"))
2207 (clobber (reg:CC CC_REGNUM))]
2209 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2210 [(set_attr "length" "8")
2211 (set_attr "type" "vs")])
2213 (define_insn "*setmem_long_and"
2214 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2215 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2216 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
2217 (match_operand 4 "const_int_operand" "n")))
2219 (use (match_operand:<DBL> 1 "register_operand" "d"))
2220 (clobber (reg:CC CC_REGNUM))]
2221 "(INTVAL (operands[4]) & 255) == 255"
2222 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2223 [(set_attr "length" "8")
2224 (set_attr "type" "vs")])
2226 ; cmpmemM instruction pattern(s).
2229 (define_expand "cmpmemsi"
2230 [(set (match_operand:SI 0 "register_operand" "")
2231 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2232 (match_operand:BLK 2 "memory_operand" "") ) )
2233 (use (match_operand:SI 3 "general_operand" ""))
2234 (use (match_operand:SI 4 "" ""))]
2236 "s390_expand_cmpmem (operands[0], operands[1],
2237 operands[2], operands[3]); DONE;")
2239 ; Compare a block that is up to 256 bytes in length.
2240 ; The block length is taken as (operands[2] % 256) + 1.
2242 (define_expand "cmpmem_short"
2244 [(set (reg:CCU CC_REGNUM)
2245 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2246 (match_operand:BLK 1 "memory_operand" "")))
2247 (use (match_operand 2 "nonmemory_operand" ""))
2248 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2249 (clobber (match_dup 3))])]
2251 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2253 (define_insn "*cmpmem_short"
2254 [(set (reg:CCU CC_REGNUM)
2255 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2256 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2257 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2258 (use (match_operand 3 "immediate_operand" "X,R,X"))
2259 (clobber (match_scratch 4 "=X,X,&a"))]
2260 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2261 && GET_MODE (operands[4]) == Pmode"
2263 [(set_attr "type" "cs")])
2266 [(set (reg:CCU CC_REGNUM)
2267 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2268 (match_operand:BLK 1 "memory_operand" "")))
2269 (use (match_operand 2 "const_int_operand" ""))
2270 (use (match_operand 3 "immediate_operand" ""))
2271 (clobber (scratch))]
2274 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2275 (use (match_dup 2))])]
2276 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2279 [(set (reg:CCU CC_REGNUM)
2280 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2281 (match_operand:BLK 1 "memory_operand" "")))
2282 (use (match_operand 2 "register_operand" ""))
2283 (use (match_operand 3 "memory_operand" ""))
2284 (clobber (scratch))]
2287 [(unspec [(match_dup 2) (match_dup 3)
2288 (const_int 0)] UNSPEC_EXECUTE)
2289 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2290 (use (const_int 1))])]
2294 [(set (reg:CCU CC_REGNUM)
2295 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2296 (match_operand:BLK 1 "memory_operand" "")))
2297 (use (match_operand 2 "register_operand" ""))
2298 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2299 (clobber (match_operand 3 "register_operand" ""))]
2300 "reload_completed && TARGET_CPU_ZARCH"
2301 [(set (match_dup 3) (label_ref (match_dup 4)))
2303 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2304 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2305 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2306 (use (const_int 1))])]
2307 "operands[4] = gen_label_rtx ();")
2309 ; Compare a block of arbitrary length.
2311 (define_expand "cmpmem_long"
2313 [(clobber (match_dup 2))
2314 (clobber (match_dup 3))
2315 (set (reg:CCU CC_REGNUM)
2316 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2317 (match_operand:BLK 1 "memory_operand" "")))
2318 (use (match_operand 2 "general_operand" ""))
2319 (use (match_dup 3))])]
2322 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2323 rtx reg0 = gen_reg_rtx (dword_mode);
2324 rtx reg1 = gen_reg_rtx (dword_mode);
2325 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2326 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2327 rtx len0 = gen_lowpart (Pmode, reg0);
2328 rtx len1 = gen_lowpart (Pmode, reg1);
2330 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2331 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2332 emit_move_insn (len0, operands[2]);
2334 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2335 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2336 emit_move_insn (len1, operands[2]);
2338 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2339 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2344 (define_insn "*cmpmem_long"
2345 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2346 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2347 (set (reg:CCU CC_REGNUM)
2348 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2349 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
2351 (use (match_dup 3))]
2353 "clcle\t%0,%1,0\;jo\t.-4"
2354 [(set_attr "length" "8")
2355 (set_attr "type" "vs")])
2357 ; Convert CCUmode condition code to integer.
2358 ; Result is zero if EQ, positive if LTU, negative if GTU.
2360 (define_insn_and_split "cmpint"
2361 [(set (match_operand:SI 0 "register_operand" "=d")
2362 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2364 (clobber (reg:CC CC_REGNUM))]
2368 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2370 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2371 (clobber (reg:CC CC_REGNUM))])])
2373 (define_insn_and_split "*cmpint_cc"
2374 [(set (reg CC_REGNUM)
2375 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2378 (set (match_operand:SI 0 "register_operand" "=d")
2379 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2380 "s390_match_ccmode (insn, CCSmode)"
2382 "&& reload_completed"
2383 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2385 [(set (match_dup 2) (match_dup 3))
2386 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2388 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2389 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2390 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2393 (define_insn_and_split "*cmpint_sign"
2394 [(set (match_operand:DI 0 "register_operand" "=d")
2395 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2397 (clobber (reg:CC CC_REGNUM))]
2400 "&& reload_completed"
2401 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2403 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2404 (clobber (reg:CC CC_REGNUM))])])
2406 (define_insn_and_split "*cmpint_sign_cc"
2407 [(set (reg CC_REGNUM)
2408 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2409 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2411 (const_int 32)) (const_int 32))
2413 (set (match_operand:DI 0 "register_operand" "=d")
2414 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2415 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2417 "&& reload_completed"
2418 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2420 [(set (match_dup 2) (match_dup 3))
2421 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2423 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2424 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2425 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2430 ;;- Conversion instructions.
2433 (define_insn "*sethighpartsi"
2434 [(set (match_operand:SI 0 "register_operand" "=d,d")
2435 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
2436 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
2437 (clobber (reg:CC CC_REGNUM))]
2442 [(set_attr "op_type" "RS,RSY")])
2444 (define_insn "*sethighpartdi_64"
2445 [(set (match_operand:DI 0 "register_operand" "=d")
2446 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
2447 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
2448 (clobber (reg:CC CC_REGNUM))]
2451 [(set_attr "op_type" "RSY")])
2453 (define_insn "*sethighpartdi_31"
2454 [(set (match_operand:DI 0 "register_operand" "=d,d")
2455 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
2456 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
2457 (clobber (reg:CC CC_REGNUM))]
2462 [(set_attr "op_type" "RS,RSY")])
2464 (define_insn_and_split "*extzv<mode>"
2465 [(set (match_operand:GPR 0 "register_operand" "=d")
2466 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
2467 (match_operand 2 "const_int_operand" "n")
2469 (clobber (reg:CC CC_REGNUM))]
2470 "INTVAL (operands[2]) > 0
2471 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
2473 "&& reload_completed"
2475 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
2476 (clobber (reg:CC CC_REGNUM))])
2477 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
2479 int bitsize = INTVAL (operands[2]);
2480 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
2481 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
2483 operands[1] = adjust_address (operands[1], BLKmode, 0);
2484 set_mem_size (operands[1], GEN_INT (size));
2485 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
2486 operands[3] = GEN_INT (mask);
2489 (define_insn_and_split "*extv<mode>"
2490 [(set (match_operand:GPR 0 "register_operand" "=d")
2491 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
2492 (match_operand 2 "const_int_operand" "n")
2494 (clobber (reg:CC CC_REGNUM))]
2495 "INTVAL (operands[2]) > 0
2496 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
2498 "&& reload_completed"
2500 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
2501 (clobber (reg:CC CC_REGNUM))])
2503 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
2504 (clobber (reg:CC CC_REGNUM))])]
2506 int bitsize = INTVAL (operands[2]);
2507 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
2508 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
2510 operands[1] = adjust_address (operands[1], BLKmode, 0);
2511 set_mem_size (operands[1], GEN_INT (size));
2512 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
2513 operands[3] = GEN_INT (mask);
2517 ; insv instruction patterns
2520 (define_expand "insv"
2521 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
2522 (match_operand 1 "const_int_operand" "")
2523 (match_operand 2 "const_int_operand" ""))
2524 (match_operand 3 "general_operand" ""))]
2527 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
2532 (define_insn "*insv<mode>_mem_reg"
2533 [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
2534 (match_operand 1 "const_int_operand" "n,n")
2536 (match_operand:P 2 "register_operand" "d,d"))]
2537 "INTVAL (operands[1]) > 0
2538 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
2539 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
2541 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
2543 operands[1] = GEN_INT ((1ul << size) - 1);
2544 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
2545 : "stcmy\t%2,%1,%S0";
2547 [(set_attr "op_type" "RS,RSY")])
2549 (define_insn "*insvdi_mem_reghigh"
2550 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
2551 (match_operand 1 "const_int_operand" "n")
2553 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
2556 && INTVAL (operands[1]) > 0
2557 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
2558 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
2560 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
2562 operands[1] = GEN_INT ((1ul << size) - 1);
2563 return "stcmh\t%2,%1,%S0";
2565 [(set_attr "op_type" "RSY")])
2567 (define_insn "*insv<mode>_reg_imm"
2568 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
2570 (match_operand 1 "const_int_operand" "n"))
2571 (match_operand:P 2 "const_int_operand" "n"))]
2573 && INTVAL (operands[1]) >= 0
2574 && INTVAL (operands[1]) < BITS_PER_WORD
2575 && INTVAL (operands[1]) % 16 == 0"
2577 switch (BITS_PER_WORD - INTVAL (operands[1]))
2579 case 64: return "iihh\t%0,%x2"; break;
2580 case 48: return "iihl\t%0,%x2"; break;
2581 case 32: return "iilh\t%0,%x2"; break;
2582 case 16: return "iill\t%0,%x2"; break;
2583 default: gcc_unreachable();
2586 [(set_attr "op_type" "RI")])
2588 (define_insn "*insv<mode>_reg_extimm"
2589 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
2591 (match_operand 1 "const_int_operand" "n"))
2592 (match_operand:P 2 "const_int_operand" "n"))]
2594 && INTVAL (operands[1]) >= 0
2595 && INTVAL (operands[1]) < BITS_PER_WORD
2596 && INTVAL (operands[1]) % 32 == 0"
2598 switch (BITS_PER_WORD - INTVAL (operands[1]))
2600 case 64: return "iihf\t%0,%o2"; break;
2601 case 32: return "iilf\t%0,%o2"; break;
2602 default: gcc_unreachable();
2605 [(set_attr "op_type" "RIL")])
2608 ; extendsidi2 instruction pattern(s).
2611 (define_expand "extendsidi2"
2612 [(set (match_operand:DI 0 "register_operand" "")
2613 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2618 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2619 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2620 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2621 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2626 (define_insn "*extendsidi2"
2627 [(set (match_operand:DI 0 "register_operand" "=d,d")
2628 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2633 [(set_attr "op_type" "RRE,RXY")])
2636 ; extend(hi|qi)(si|di)2 instruction pattern(s).
2639 (define_expand "extend<HQI:mode><DSI:mode>2"
2640 [(set (match_operand:DSI 0 "register_operand" "")
2641 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2644 if (<DSI:MODE>mode == DImode && !TARGET_64BIT)
2646 rtx tmp = gen_reg_rtx (SImode);
2647 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
2648 emit_insn (gen_extendsidi2 (operands[0], tmp));
2651 else if (!TARGET_EXTIMM)
2653 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
2654 GET_MODE_BITSIZE (<HQI:MODE>mode));
2656 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
2657 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
2658 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
2664 ; extendhidi2 instruction pattern(s).
2667 (define_insn "*extendhidi2_extimm"
2668 [(set (match_operand:DI 0 "register_operand" "=d,d")
2669 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
2670 "TARGET_64BIT && TARGET_EXTIMM"
2674 [(set_attr "op_type" "RRE,RXY")])
2676 (define_insn "*extendhidi2"
2677 [(set (match_operand:DI 0 "register_operand" "=d")
2678 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2681 [(set_attr "op_type" "RXY")])
2684 ; extendhisi2 instruction pattern(s).
2687 (define_insn "*extendhisi2_extimm"
2688 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
2689 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))]
2695 [(set_attr "op_type" "RRE,RX,RXY")])
2697 (define_insn "*extendhisi2"
2698 [(set (match_operand:SI 0 "register_operand" "=d,d")
2699 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2704 [(set_attr "op_type" "RX,RXY")])
2707 ; extendqi(si|di)2 instruction pattern(s).
2710 (define_insn "*extendqi<mode>2_extimm"
2711 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2712 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2717 [(set_attr "op_type" "RRE,RXY")])
2719 (define_insn "*extendqi<mode>2"
2720 [(set (match_operand:GPR 0 "register_operand" "=d")
2721 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "m")))]
2722 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
2724 [(set_attr "op_type" "RXY")])
2726 (define_insn_and_split "*extendqi<mode>2_short_displ"
2727 [(set (match_operand:GPR 0 "register_operand" "=d")
2728 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
2729 (clobber (reg:CC CC_REGNUM))]
2730 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
2732 "&& reload_completed"
2734 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
2735 (clobber (reg:CC CC_REGNUM))])
2737 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
2738 (clobber (reg:CC CC_REGNUM))])]
2740 operands[1] = adjust_address (operands[1], BLKmode, 0);
2741 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
2742 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
2743 - GET_MODE_BITSIZE (QImode));
2747 ; zero_extendsidi2 instruction pattern(s).
2750 (define_expand "zero_extendsidi2"
2751 [(set (match_operand:DI 0 "register_operand" "")
2752 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2757 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2758 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2759 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2764 (define_insn "*zero_extendsidi2"
2765 [(set (match_operand:DI 0 "register_operand" "=d,d")
2766 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2771 [(set_attr "op_type" "RRE,RXY")])
2774 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2777 (define_insn "*llgt_sidi"
2778 [(set (match_operand:DI 0 "register_operand" "=d")
2779 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2780 (const_int 2147483647)))]
2783 [(set_attr "op_type" "RXE")])
2785 (define_insn_and_split "*llgt_sidi_split"
2786 [(set (match_operand:DI 0 "register_operand" "=d")
2787 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2788 (const_int 2147483647)))
2789 (clobber (reg:CC CC_REGNUM))]
2792 "&& reload_completed"
2794 (and:DI (subreg:DI (match_dup 1) 0)
2795 (const_int 2147483647)))]
2798 (define_insn "*llgt_sisi"
2799 [(set (match_operand:SI 0 "register_operand" "=d,d")
2800 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2801 (const_int 2147483647)))]
2806 [(set_attr "op_type" "RRE,RXE")])
2808 (define_insn "*llgt_didi"
2809 [(set (match_operand:DI 0 "register_operand" "=d,d")
2810 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2811 (const_int 2147483647)))]
2816 [(set_attr "op_type" "RRE,RXE")])
2819 [(set (match_operand:GPR 0 "register_operand" "")
2820 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
2821 (const_int 2147483647)))
2822 (clobber (reg:CC CC_REGNUM))]
2823 "TARGET_ZARCH && reload_completed"
2825 (and:GPR (match_dup 1)
2826 (const_int 2147483647)))]
2830 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
2833 (define_expand "zero_extend<mode>di2"
2834 [(set (match_operand:DI 0 "register_operand" "")
2835 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2840 rtx tmp = gen_reg_rtx (SImode);
2841 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
2842 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2845 else if (!TARGET_EXTIMM)
2847 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
2848 GET_MODE_BITSIZE(<MODE>mode));
2849 operands[1] = gen_lowpart (DImode, operands[1]);
2850 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2851 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
2856 (define_expand "zero_extend<mode>si2"
2857 [(set (match_operand:SI 0 "register_operand" "")
2858 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2863 operands[1] = gen_lowpart (SImode, operands[1]);
2864 emit_insn (gen_andsi3 (operands[0], operands[1],
2865 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
2870 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
2871 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2872 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
2877 [(set_attr "op_type" "RRE,RXY")])
2879 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
2880 [(set (match_operand:GPR 0 "register_operand" "=d")
2881 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "m")))]
2882 "TARGET_ZARCH && !TARGET_EXTIMM"
2884 [(set_attr "op_type" "RXY")])
2886 (define_insn_and_split "*zero_extendhisi2_31"
2887 [(set (match_operand:SI 0 "register_operand" "=&d")
2888 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
2889 (clobber (reg:CC CC_REGNUM))]
2892 "&& reload_completed"
2893 [(set (match_dup 0) (const_int 0))
2895 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2896 (clobber (reg:CC CC_REGNUM))])]
2897 "operands[2] = gen_lowpart (HImode, operands[0]);")
2899 (define_insn_and_split "*zero_extendqisi2_31"
2900 [(set (match_operand:SI 0 "register_operand" "=&d")
2901 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2904 "&& reload_completed"
2905 [(set (match_dup 0) (const_int 0))
2906 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2907 "operands[2] = gen_lowpart (QImode, operands[0]);")
2910 ; zero_extendqihi2 instruction pattern(s).
2913 (define_expand "zero_extendqihi2"
2914 [(set (match_operand:HI 0 "register_operand" "")
2915 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2916 "TARGET_ZARCH && !TARGET_EXTIMM"
2918 operands[1] = gen_lowpart (HImode, operands[1]);
2919 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2923 (define_insn "*zero_extendqihi2_64"
2924 [(set (match_operand:HI 0 "register_operand" "=d")
2925 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2926 "TARGET_ZARCH && !TARGET_EXTIMM"
2928 [(set_attr "op_type" "RXY")])
2930 (define_insn_and_split "*zero_extendqihi2_31"
2931 [(set (match_operand:HI 0 "register_operand" "=&d")
2932 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2935 "&& reload_completed"
2936 [(set (match_dup 0) (const_int 0))
2937 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2938 "operands[2] = gen_lowpart (QImode, operands[0]);")
2942 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
2945 (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
2946 [(set (match_operand:GPR 0 "register_operand" "")
2947 (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
2948 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2950 rtx label1 = gen_label_rtx ();
2951 rtx label2 = gen_label_rtx ();
2952 rtx temp = gen_reg_rtx (<FPR:MODE>mode);
2953 REAL_VALUE_TYPE cmp, sub;
2955 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2956 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
2957 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
2959 emit_insn (gen_cmp<FPR:mode> (operands[1],
2960 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
2961 emit_jump_insn (gen_blt (label1));
2962 emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
2963 CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
2964 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
2968 emit_label (label1);
2969 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
2970 operands[1], GEN_INT(5)));
2971 emit_label (label2);
2975 (define_expand "fix_trunc<FPR:mode>di2"
2976 [(set (match_operand:DI 0 "register_operand" "")
2977 (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))]
2978 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2980 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2981 emit_insn (gen_fix_trunc<FPR:mode>di2_ieee (operands[0], operands[1],
2986 (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
2987 [(set (match_operand:GPR 0 "register_operand" "=d")
2988 (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
2989 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
2990 (clobber (reg:CC CC_REGNUM))]
2991 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2992 "c<GPR:gf><FPR:de>br\t%0,%h2,%1"
2993 [(set_attr "op_type" "RRE")
2994 (set_attr "type" "ftoi")])
2997 ; fix_truncdfsi2 instruction pattern(s).
3000 (define_expand "fix_truncdfsi2"
3001 [(set (match_operand:SI 0 "register_operand" "")
3002 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
3005 if (TARGET_IBM_FLOAT)
3007 /* This is the algorithm from POP chapter A.5.7.2. */
3009 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3010 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
3011 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
3013 operands[1] = force_reg (DFmode, operands[1]);
3014 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
3015 two31r, two32, temp));
3019 operands[1] = force_reg (DFmode, operands[1]);
3020 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3026 (define_insn "fix_truncdfsi2_ibm"
3027 [(set (match_operand:SI 0 "register_operand" "=d")
3028 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
3029 (use (match_operand:DI 2 "immediate_operand" "m"))
3030 (use (match_operand:DI 3 "immediate_operand" "m"))
3031 (use (match_operand:BLK 4 "memory_operand" "m"))
3032 (clobber (reg:CC CC_REGNUM))]
3033 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3035 output_asm_insn ("sd\t%1,%2", operands);
3036 output_asm_insn ("aw\t%1,%3", operands);
3037 output_asm_insn ("std\t%1,%4", operands);
3038 output_asm_insn ("xi\t%N4,128", operands);
3041 [(set_attr "length" "20")])
3044 ; fix_truncsfsi2 instruction pattern(s).
3047 (define_expand "fix_truncsfsi2"
3048 [(set (match_operand:SI 0 "register_operand" "")
3049 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
3052 if (TARGET_IBM_FLOAT)
3054 /* Convert to DFmode and then use the POP algorithm. */
3055 rtx temp = gen_reg_rtx (DFmode);
3056 emit_insn (gen_extendsfdf2 (temp, operands[1]));
3057 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
3061 operands[1] = force_reg (SFmode, operands[1]);
3062 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3069 ; floatdi(df|sf)2 instruction pattern(s).
3072 (define_insn "floatdi<mode>2"
3073 [(set (match_operand:FPR 0 "register_operand" "=f")
3074 (float:FPR (match_operand:DI 1 "register_operand" "d")))]
3075 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3077 [(set_attr "op_type" "RRE")
3078 (set_attr "type" "itof" )])
3081 ; floatsidf2 instruction pattern(s).
3084 (define_expand "floatsidf2"
3085 [(set (match_operand:DF 0 "register_operand" "")
3086 (float:DF (match_operand:SI 1 "register_operand" "")))]
3089 if (TARGET_IBM_FLOAT)
3091 /* This is the algorithm from POP chapter A.5.7.1. */
3093 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3094 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
3096 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
3101 (define_insn "floatsidf2_ieee"
3102 [(set (match_operand:DF 0 "register_operand" "=f")
3103 (float:DF (match_operand:SI 1 "register_operand" "d")))]
3104 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3106 [(set_attr "op_type" "RRE")
3107 (set_attr "type" "itof" )])
3109 (define_insn "floatsidf2_ibm"
3110 [(set (match_operand:DF 0 "register_operand" "=f")
3111 (float:DF (match_operand:SI 1 "register_operand" "d")))
3112 (use (match_operand:DI 2 "immediate_operand" "m"))
3113 (use (match_operand:BLK 3 "memory_operand" "m"))
3114 (clobber (reg:CC CC_REGNUM))]
3115 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3117 output_asm_insn ("st\t%1,%N3", operands);
3118 output_asm_insn ("xi\t%N3,128", operands);
3119 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
3120 output_asm_insn ("ld\t%0,%3", operands);
3123 [(set_attr "length" "20")])
3126 ; floatsisf2 instruction pattern(s).
3129 (define_expand "floatsisf2"
3130 [(set (match_operand:SF 0 "register_operand" "")
3131 (float:SF (match_operand:SI 1 "register_operand" "")))]
3134 if (TARGET_IBM_FLOAT)
3136 /* Use the POP algorithm to convert to DFmode and then truncate. */
3137 rtx temp = gen_reg_rtx (DFmode);
3138 emit_insn (gen_floatsidf2 (temp, operands[1]));
3139 emit_insn (gen_truncdfsf2 (operands[0], temp));
3144 (define_insn "floatsisf2_ieee"
3145 [(set (match_operand:SF 0 "register_operand" "=f")
3146 (float:SF (match_operand:SI 1 "register_operand" "d")))]
3147 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3149 [(set_attr "op_type" "RRE")
3150 (set_attr "type" "itof" )])
3153 ; truncdfsf2 instruction pattern(s).
3156 (define_expand "truncdfsf2"
3157 [(set (match_operand:SF 0 "register_operand" "")
3158 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
3162 (define_insn "truncdfsf2_ieee"
3163 [(set (match_operand:SF 0 "register_operand" "=f")
3164 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3165 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3167 [(set_attr "op_type" "RRE")])
3169 (define_insn "truncdfsf2_ibm"
3170 [(set (match_operand:SF 0 "register_operand" "=f,f")
3171 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3172 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3176 [(set_attr "op_type" "RR,RX")
3177 (set_attr "type" "floadsf")])
3180 ; extendsfdf2 instruction pattern(s).
3183 (define_expand "extendsfdf2"
3184 [(set (match_operand:DF 0 "register_operand" "")
3185 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3188 if (TARGET_IBM_FLOAT)
3190 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3195 (define_insn "extendsfdf2_ieee"
3196 [(set (match_operand:DF 0 "register_operand" "=f,f")
3197 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3198 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3202 [(set_attr "op_type" "RRE,RXE")
3203 (set_attr "type" "floadsf")])
3205 (define_insn "extendsfdf2_ibm"
3206 [(set (match_operand:DF 0 "register_operand" "=f,f")
3207 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
3208 (clobber (reg:CC CC_REGNUM))]
3209 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3211 sdr\t%0,%0\;ler\t%0,%1
3212 sdr\t%0,%0\;le\t%0,%1"
3213 [(set_attr "length" "4,6")
3214 (set_attr "type" "floadsf")])
3218 ;; ARITHMETIC OPERATIONS
3220 ; arithmetic operations set the ConditionCode,
3221 ; because of unpredictable Bits in Register for Halfword and Byte
3222 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3225 ;;- Add instructions.
3229 ; addti3 instruction pattern(s).
3232 (define_insn_and_split "addti3"
3233 [(set (match_operand:TI 0 "register_operand" "=&d")
3234 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3235 (match_operand:TI 2 "general_operand" "do") ) )
3236 (clobber (reg:CC CC_REGNUM))]
3239 "&& reload_completed"
3241 [(set (reg:CCL1 CC_REGNUM)
3242 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3244 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3246 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3247 (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
3248 (clobber (reg:CC CC_REGNUM))])]
3249 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3250 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3251 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3252 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3253 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3254 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3257 ; adddi3 instruction pattern(s).
3260 (define_expand "adddi3"
3262 [(set (match_operand:DI 0 "register_operand" "")
3263 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3264 (match_operand:DI 2 "general_operand" "")))
3265 (clobber (reg:CC CC_REGNUM))])]
3269 (define_insn "*adddi3_sign"
3270 [(set (match_operand:DI 0 "register_operand" "=d,d")
3271 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3272 (match_operand:DI 1 "register_operand" "0,0")))
3273 (clobber (reg:CC CC_REGNUM))]
3278 [(set_attr "op_type" "RRE,RXY")])
3280 (define_insn "*adddi3_zero_cc"
3281 [(set (reg CC_REGNUM)
3282 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3283 (match_operand:DI 1 "register_operand" "0,0"))
3285 (set (match_operand:DI 0 "register_operand" "=d,d")
3286 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3287 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3291 [(set_attr "op_type" "RRE,RXY")])
3293 (define_insn "*adddi3_zero_cconly"
3294 [(set (reg CC_REGNUM)
3295 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3296 (match_operand:DI 1 "register_operand" "0,0"))
3298 (clobber (match_scratch:DI 0 "=d,d"))]
3299 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3303 [(set_attr "op_type" "RRE,RXY")])
3305 (define_insn "*adddi3_zero"
3306 [(set (match_operand:DI 0 "register_operand" "=d,d")
3307 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3308 (match_operand:DI 1 "register_operand" "0,0")))
3309 (clobber (reg:CC CC_REGNUM))]
3314 [(set_attr "op_type" "RRE,RXY")])
3316 (define_insn_and_split "*adddi3_31z"
3317 [(set (match_operand:DI 0 "register_operand" "=&d")
3318 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3319 (match_operand:DI 2 "general_operand" "do") ) )
3320 (clobber (reg:CC CC_REGNUM))]
3321 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3323 "&& reload_completed"
3325 [(set (reg:CCL1 CC_REGNUM)
3326 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3328 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3330 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3331 (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
3332 (clobber (reg:CC CC_REGNUM))])]
3333 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3334 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3335 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3336 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3337 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3338 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3340 (define_insn_and_split "*adddi3_31"
3341 [(set (match_operand:DI 0 "register_operand" "=&d")
3342 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3343 (match_operand:DI 2 "general_operand" "do") ) )
3344 (clobber (reg:CC CC_REGNUM))]
3347 "&& reload_completed"
3349 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3350 (clobber (reg:CC CC_REGNUM))])
3352 [(set (reg:CCL1 CC_REGNUM)
3353 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3355 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3357 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
3359 (label_ref (match_dup 9))))
3361 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3362 (clobber (reg:CC CC_REGNUM))])
3364 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3365 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3366 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3367 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3368 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3369 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3370 operands[9] = gen_label_rtx ();")
3373 ; addsi3 instruction pattern(s).
3376 (define_expand "addsi3"
3378 [(set (match_operand:SI 0 "register_operand" "")
3379 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
3380 (match_operand:SI 2 "general_operand" "")))
3381 (clobber (reg:CC CC_REGNUM))])]
3385 (define_insn "*addsi3_sign"
3386 [(set (match_operand:SI 0 "register_operand" "=d,d")
3387 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3388 (match_operand:SI 1 "register_operand" "0,0")))
3389 (clobber (reg:CC CC_REGNUM))]
3394 [(set_attr "op_type" "RX,RXY")])
3397 ; add(di|si)3 instruction pattern(s).
3400 (define_insn "*add<mode>3"
3401 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d")
3402 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
3403 (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T") ) )
3404 (clobber (reg:CC CC_REGNUM))]
3413 [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY")])
3415 (define_insn "*add<mode>3_carry1_cc"
3416 [(set (reg CC_REGNUM)
3417 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
3418 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
3420 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3421 (plus:GPR (match_dup 1) (match_dup 2)))]
3422 "s390_match_ccmode (insn, CCL1mode)"
3429 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
3431 (define_insn "*add<mode>3_carry1_cconly"
3432 [(set (reg CC_REGNUM)
3433 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3434 (match_operand:GPR 2 "general_operand" "d,R,T"))
3436 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3437 "s390_match_ccmode (insn, CCL1mode)"
3442 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3444 (define_insn "*add<mode>3_carry2_cc"
3445 [(set (reg CC_REGNUM)
3446 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
3447 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
3449 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3450 (plus:GPR (match_dup 1) (match_dup 2)))]
3451 "s390_match_ccmode (insn, CCL1mode)"
3458 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
3460 (define_insn "*add<mode>3_carry2_cconly"
3461 [(set (reg CC_REGNUM)
3462 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3463 (match_operand:GPR 2 "general_operand" "d,R,T"))
3465 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3466 "s390_match_ccmode (insn, CCL1mode)"
3471 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3473 (define_insn "*add<mode>3_cc"
3474 [(set (reg CC_REGNUM)
3475 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
3476 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
3478 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3479 (plus:GPR (match_dup 1) (match_dup 2)))]
3480 "s390_match_ccmode (insn, CCLmode)"
3487 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
3489 (define_insn "*add<mode>3_cconly"
3490 [(set (reg CC_REGNUM)
3491 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3492 (match_operand:GPR 2 "general_operand" "d,R,T"))
3494 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3495 "s390_match_ccmode (insn, CCLmode)"
3500 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3502 (define_insn "*add<mode>3_cconly2"
3503 [(set (reg CC_REGNUM)
3504 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3505 (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T"))))
3506 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3507 "s390_match_ccmode(insn, CCLmode)"
3512 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3514 (define_insn "*add<mode>3_imm_cc"
3515 [(set (reg CC_REGNUM)
3516 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3517 (match_operand:GPR 2 "const_int_operand" "K,Os"))
3519 (set (match_operand:GPR 0 "register_operand" "=d,d")
3520 (plus:GPR (match_dup 1) (match_dup 2)))]
3521 "s390_match_ccmode (insn, CCAmode)
3522 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
3523 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))
3524 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
3528 [(set_attr "op_type" "RI,RIL")])
3531 ; add(df|sf)3 instruction pattern(s).
3534 (define_expand "add<mode>3"
3536 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3537 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3538 (match_operand:FPR 2 "general_operand" "f,R")))
3539 (clobber (reg:CC CC_REGNUM))])]
3543 (define_insn "*add<mode>3"
3544 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3545 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3546 (match_operand:FPR 2 "general_operand" "f,R")))
3547 (clobber (reg:CC CC_REGNUM))]
3548 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3552 [(set_attr "op_type" "RRE,RXE")
3553 (set_attr "type" "fsimp<mode>")])
3555 (define_insn "*add<mode>3_cc"
3556 [(set (reg CC_REGNUM)
3557 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3558 (match_operand:FPR 2 "general_operand" "f,R"))
3559 (match_operand:FPR 3 "const0_operand" "")))
3560 (set (match_operand:FPR 0 "register_operand" "=f,f")
3561 (plus:FPR (match_dup 1) (match_dup 2)))]
3562 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3566 [(set_attr "op_type" "RRE,RXE")
3567 (set_attr "type" "fsimp<mode>")])
3569 (define_insn "*add<mode>3_cconly"
3570 [(set (reg CC_REGNUM)
3571 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3572 (match_operand:FPR 2 "general_operand" "f,R"))
3573 (match_operand:FPR 3 "const0_operand" "")))
3574 (clobber (match_scratch:FPR 0 "=f,f"))]
3575 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3579 [(set_attr "op_type" "RRE,RXE")
3580 (set_attr "type" "fsimp<mode>")])
3582 (define_insn "*add<mode>3_ibm"
3583 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3584 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3585 (match_operand:FPR 2 "general_operand" "f,R")))
3586 (clobber (reg:CC CC_REGNUM))]
3587 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3591 [(set_attr "op_type" "RR,RX")
3592 (set_attr "type" "fsimp<mode>")])
3596 ;;- Subtract instructions.
3600 ; subti3 instruction pattern(s).
3603 (define_insn_and_split "subti3"
3604 [(set (match_operand:TI 0 "register_operand" "=&d")
3605 (minus:TI (match_operand:TI 1 "register_operand" "0")
3606 (match_operand:TI 2 "general_operand" "do") ) )
3607 (clobber (reg:CC CC_REGNUM))]
3610 "&& reload_completed"
3612 [(set (reg:CCL2 CC_REGNUM)
3613 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3615 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3617 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3618 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
3619 (clobber (reg:CC CC_REGNUM))])]
3620 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3621 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3622 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3623 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3624 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3625 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3628 ; subdi3 instruction pattern(s).
3631 (define_expand "subdi3"
3633 [(set (match_operand:DI 0 "register_operand" "")
3634 (minus:DI (match_operand:DI 1 "register_operand" "")
3635 (match_operand:DI 2 "general_operand" "")))
3636 (clobber (reg:CC CC_REGNUM))])]
3640 (define_insn "*subdi3_sign"
3641 [(set (match_operand:DI 0 "register_operand" "=d,d")
3642 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3643 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3644 (clobber (reg:CC CC_REGNUM))]
3649 [(set_attr "op_type" "RRE,RXY")])
3651 (define_insn "*subdi3_zero_cc"
3652 [(set (reg CC_REGNUM)
3653 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3654 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3656 (set (match_operand:DI 0 "register_operand" "=d,d")
3657 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3658 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3662 [(set_attr "op_type" "RRE,RXY")])
3664 (define_insn "*subdi3_zero_cconly"
3665 [(set (reg CC_REGNUM)
3666 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3667 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3669 (clobber (match_scratch:DI 0 "=d,d"))]
3670 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3674 [(set_attr "op_type" "RRE,RXY")])
3676 (define_insn "*subdi3_zero"
3677 [(set (match_operand:DI 0 "register_operand" "=d,d")
3678 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3679 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3680 (clobber (reg:CC CC_REGNUM))]
3685 [(set_attr "op_type" "RRE,RXY")])
3687 (define_insn_and_split "*subdi3_31z"
3688 [(set (match_operand:DI 0 "register_operand" "=&d")
3689 (minus:DI (match_operand:DI 1 "register_operand" "0")
3690 (match_operand:DI 2 "general_operand" "do") ) )
3691 (clobber (reg:CC CC_REGNUM))]
3692 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3694 "&& reload_completed"
3696 [(set (reg:CCL2 CC_REGNUM)
3697 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3699 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3701 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3702 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
3703 (clobber (reg:CC CC_REGNUM))])]
3704 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3705 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3706 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3707 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3708 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3709 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3711 (define_insn_and_split "*subdi3_31"
3712 [(set (match_operand:DI 0 "register_operand" "=&d")
3713 (minus:DI (match_operand:DI 1 "register_operand" "0")
3714 (match_operand:DI 2 "general_operand" "do") ) )
3715 (clobber (reg:CC CC_REGNUM))]
3718 "&& reload_completed"
3720 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3721 (clobber (reg:CC CC_REGNUM))])
3723 [(set (reg:CCL2 CC_REGNUM)
3724 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3726 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3728 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
3730 (label_ref (match_dup 9))))
3732 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3733 (clobber (reg:CC CC_REGNUM))])
3735 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3736 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3737 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3738 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3739 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3740 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3741 operands[9] = gen_label_rtx ();")
3744 ; subsi3 instruction pattern(s).
3747 (define_expand "subsi3"
3749 [(set (match_operand:SI 0 "register_operand" "")
3750 (minus:SI (match_operand:SI 1 "register_operand" "")
3751 (match_operand:SI 2 "general_operand" "")))
3752 (clobber (reg:CC CC_REGNUM))])]
3756 (define_insn "*subsi3_sign"
3757 [(set (match_operand:SI 0 "register_operand" "=d,d")
3758 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3759 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
3760 (clobber (reg:CC CC_REGNUM))]
3765 [(set_attr "op_type" "RX,RXY")])
3768 ; sub(di|si)3 instruction pattern(s).
3771 (define_insn "*sub<mode>3"
3772 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
3773 (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
3774 (match_operand:GPR 2 "general_operand" "d,R,T") ) )
3775 (clobber (reg:CC CC_REGNUM))]
3781 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3783 (define_insn "*sub<mode>3_borrow_cc"
3784 [(set (reg CC_REGNUM)
3785 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
3786 (match_operand:GPR 2 "general_operand" "d,R,T"))
3788 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
3789 (minus:GPR (match_dup 1) (match_dup 2)))]
3790 "s390_match_ccmode (insn, CCL2mode)"
3795 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3797 (define_insn "*sub<mode>3_borrow_cconly"
3798 [(set (reg CC_REGNUM)
3799 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
3800 (match_operand:GPR 2 "general_operand" "d,R,T"))
3802 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3803 "s390_match_ccmode (insn, CCL2mode)"
3808 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3810 (define_insn "*sub<mode>3_cc"
3811 [(set (reg CC_REGNUM)
3812 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
3813 (match_operand:GPR 2 "general_operand" "d,R,T"))
3815 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
3816 (minus:GPR (match_dup 1) (match_dup 2)))]
3817 "s390_match_ccmode (insn, CCLmode)"
3822 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3824 (define_insn "*sub<mode>3_cc2"
3825 [(set (reg CC_REGNUM)
3826 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
3827 (match_operand:GPR 2 "general_operand" "d,R,T")))
3828 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
3829 (minus:GPR (match_dup 1) (match_dup 2)))]
3830 "s390_match_ccmode (insn, CCL3mode)"
3835 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3837 (define_insn "*sub<mode>3_cconly"
3838 [(set (reg CC_REGNUM)
3839 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
3840 (match_operand:GPR 2 "general_operand" "d,R,T"))
3842 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3843 "s390_match_ccmode (insn, CCLmode)"
3848 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3850 (define_insn "*sub<mode>3_cconly2"
3851 [(set (reg CC_REGNUM)
3852 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
3853 (match_operand:GPR 2 "general_operand" "d,R,T")))
3854 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3855 "s390_match_ccmode (insn, CCL3mode)"
3860 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3863 ; sub(df|sf)3 instruction pattern(s).
3866 (define_expand "sub<mode>3"
3868 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3869 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3870 (match_operand:FPR 2 "general_operand" "f,R")))
3871 (clobber (reg:CC CC_REGNUM))])]
3875 (define_insn "*sub<mode>3"
3876 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3877 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3878 (match_operand:FPR 2 "general_operand" "f,R")))
3879 (clobber (reg:CC CC_REGNUM))]
3880 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3884 [(set_attr "op_type" "RRE,RXE")
3885 (set_attr "type" "fsimp<mode>")])
3887 (define_insn "*sub<mode>3_cc"
3888 [(set (reg CC_REGNUM)
3889 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
3890 (match_operand:FPR 2 "general_operand" "f,R"))
3891 (match_operand:FPR 3 "const0_operand" "")))
3892 (set (match_operand:FPR 0 "register_operand" "=f,f")
3893 (minus:FPR (match_dup 1) (match_dup 2)))]
3894 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3898 [(set_attr "op_type" "RRE,RXE")
3899 (set_attr "type" "fsimp<mode>")])
3901 (define_insn "*sub<mode>3_cconly"
3902 [(set (reg CC_REGNUM)
3903 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
3904 (match_operand:FPR 2 "general_operand" "f,R"))
3905 (match_operand:FPR 3 "const0_operand" "")))
3906 (clobber (match_scratch:FPR 0 "=f,f"))]
3907 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3911 [(set_attr "op_type" "RRE,RXE")
3912 (set_attr "type" "fsimp<mode>")])
3914 (define_insn "*sub<mode>3_ibm"
3915 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3916 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3917 (match_operand:FPR 2 "general_operand" "f,R")))
3918 (clobber (reg:CC CC_REGNUM))]
3919 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3923 [(set_attr "op_type" "RR,RX")
3924 (set_attr "type" "fsimp<mode>")])
3928 ;;- Conditional add/subtract instructions.
3932 ; add(di|si)cc instruction pattern(s).
3935 (define_insn "*add<mode>3_alc_cc"
3936 [(set (reg CC_REGNUM)
3938 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
3939 (match_operand:GPR 2 "general_operand" "d,m"))
3940 (match_operand:GPR 3 "s390_alc_comparison" ""))
3942 (set (match_operand:GPR 0 "register_operand" "=d,d")
3943 (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
3944 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
3948 [(set_attr "op_type" "RRE,RXY")])
3950 (define_insn "*add<mode>3_alc"
3951 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3952 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
3953 (match_operand:GPR 2 "general_operand" "d,m"))
3954 (match_operand:GPR 3 "s390_alc_comparison" "")))
3955 (clobber (reg:CC CC_REGNUM))]
3960 [(set_attr "op_type" "RRE,RXY")])
3962 (define_insn "*sub<mode>3_slb_cc"
3963 [(set (reg CC_REGNUM)
3965 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3966 (match_operand:GPR 2 "general_operand" "d,m"))
3967 (match_operand:GPR 3 "s390_slb_comparison" ""))
3969 (set (match_operand:GPR 0 "register_operand" "=d,d")
3970 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
3971 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
3975 [(set_attr "op_type" "RRE,RXY")])
3977 (define_insn "*sub<mode>3_slb"
3978 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3979 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3980 (match_operand:GPR 2 "general_operand" "d,m"))
3981 (match_operand:GPR 3 "s390_slb_comparison" "")))
3982 (clobber (reg:CC CC_REGNUM))]
3987 [(set_attr "op_type" "RRE,RXY")])
3989 (define_expand "add<mode>cc"
3990 [(match_operand:GPR 0 "register_operand" "")
3991 (match_operand 1 "comparison_operator" "")
3992 (match_operand:GPR 2 "register_operand" "")
3993 (match_operand:GPR 3 "const_int_operand" "")]
3995 "if (!s390_expand_addcc (GET_CODE (operands[1]),
3996 s390_compare_op0, s390_compare_op1,
3997 operands[0], operands[2],
3998 operands[3])) FAIL; DONE;")
4001 ; scond instruction pattern(s).
4004 (define_insn_and_split "*scond<mode>"
4005 [(set (match_operand:GPR 0 "register_operand" "=&d")
4006 (match_operand:GPR 1 "s390_alc_comparison" ""))
4007 (clobber (reg:CC CC_REGNUM))]
4010 "&& reload_completed"
4011 [(set (match_dup 0) (const_int 0))
4013 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
4015 (clobber (reg:CC CC_REGNUM))])]
4018 (define_insn_and_split "*scond<mode>_neg"
4019 [(set (match_operand:GPR 0 "register_operand" "=&d")
4020 (match_operand:GPR 1 "s390_slb_comparison" ""))
4021 (clobber (reg:CC CC_REGNUM))]
4024 "&& reload_completed"
4025 [(set (match_dup 0) (const_int 0))
4027 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
4029 (clobber (reg:CC CC_REGNUM))])
4031 [(set (match_dup 0) (neg:GPR (match_dup 0)))
4032 (clobber (reg:CC CC_REGNUM))])]
4036 (define_expand "s<code>"
4037 [(set (match_operand:SI 0 "register_operand" "")
4038 (SCOND (match_dup 0)
4041 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
4042 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4044 (define_expand "seq"
4046 [(set (match_operand:SI 0 "register_operand" "=d")
4048 (clobber (reg:CC CC_REGNUM))])
4050 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
4051 (clobber (reg:CC CC_REGNUM))])]
4054 if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
4056 operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
4057 PUT_MODE (operands[1], SImode);
4060 (define_insn_and_split "*sne"
4061 [(set (match_operand:SI 0 "register_operand" "=d")
4062 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
4064 (clobber (reg:CC CC_REGNUM))]
4069 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
4070 (clobber (reg:CC CC_REGNUM))])])
4074 ;;- Multiply instructions.
4078 ; muldi3 instruction pattern(s).
4081 (define_insn "*muldi3_sign"
4082 [(set (match_operand:DI 0 "register_operand" "=d,d")
4083 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4084 (match_operand:DI 1 "register_operand" "0,0")))]
4089 [(set_attr "op_type" "RRE,RXY")
4090 (set_attr "type" "imuldi")])
4092 (define_insn "muldi3"
4093 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4094 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4095 (match_operand:DI 2 "general_operand" "d,K,m")))]
4101 [(set_attr "op_type" "RRE,RI,RXY")
4102 (set_attr "type" "imuldi")])
4105 ; mulsi3 instruction pattern(s).
4108 (define_insn "*mulsi3_sign"
4109 [(set (match_operand:SI 0 "register_operand" "=d")
4110 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4111 (match_operand:SI 1 "register_operand" "0")))]
4114 [(set_attr "op_type" "RX")
4115 (set_attr "type" "imulhi")])
4117 (define_insn "mulsi3"
4118 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4119 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4120 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4127 [(set_attr "op_type" "RRE,RI,RX,RXY")
4128 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4131 ; mulsidi3 instruction pattern(s).
4134 (define_insn "mulsidi3"
4135 [(set (match_operand:DI 0 "register_operand" "=d,d")
4136 (mult:DI (sign_extend:DI
4137 (match_operand:SI 1 "register_operand" "%0,0"))
4139 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4144 [(set_attr "op_type" "RR,RX")
4145 (set_attr "type" "imulsi")])
4148 ; umulsidi3 instruction pattern(s).
4151 (define_insn "umulsidi3"
4152 [(set (match_operand:DI 0 "register_operand" "=d,d")
4153 (mult:DI (zero_extend:DI
4154 (match_operand:SI 1 "register_operand" "%0,0"))
4156 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4157 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4161 [(set_attr "op_type" "RRE,RXY")
4162 (set_attr "type" "imulsi")])
4165 ; mul(df|sf)3 instruction pattern(s).
4168 (define_expand "mul<mode>3"
4169 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4170 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4171 (match_operand:FPR 2 "general_operand" "f,R")))]
4175 (define_insn "*mul<mode>3"
4176 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4177 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4178 (match_operand:FPR 2 "general_operand" "f,R")))]
4179 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4183 [(set_attr "op_type" "RRE,RXE")
4184 (set_attr "type" "fmul<mode>")])
4186 (define_insn "*mul<mode>3_ibm"
4187 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4188 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4189 (match_operand:FPR 2 "general_operand" "f,R")))]
4190 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4194 [(set_attr "op_type" "RR,RX")
4195 (set_attr "type" "fmul<mode>")])
4197 (define_insn "*fmadd<mode>"
4198 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4199 (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f")
4200 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4201 (match_operand:FPR 3 "register_operand" "0,0")))]
4202 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4206 [(set_attr "op_type" "RRE,RXE")
4207 (set_attr "type" "fmul<mode>")])
4209 (define_insn "*fmsub<mode>"
4210 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4211 (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f")
4212 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4213 (match_operand:FPR 3 "register_operand" "0,0")))]
4214 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4218 [(set_attr "op_type" "RRE,RXE")
4219 (set_attr "type" "fmul<mode>")])
4222 ;;- Divide and modulo instructions.
4226 ; divmoddi4 instruction pattern(s).
4229 (define_expand "divmoddi4"
4230 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4231 (div:DI (match_operand:DI 1 "register_operand" "")
4232 (match_operand:DI 2 "general_operand" "")))
4233 (set (match_operand:DI 3 "general_operand" "")
4234 (mod:DI (match_dup 1) (match_dup 2)))])
4235 (clobber (match_dup 4))]
4238 rtx insn, div_equal, mod_equal;
4240 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4241 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4243 operands[4] = gen_reg_rtx(TImode);
4244 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4246 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4248 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4250 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4252 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4257 (define_insn "divmodtidi3"
4258 [(set (match_operand:TI 0 "register_operand" "=d,d")
4262 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4263 (match_operand:DI 2 "general_operand" "d,m")))
4265 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4270 [(set_attr "op_type" "RRE,RXY")
4271 (set_attr "type" "idiv")])
4273 (define_insn "divmodtisi3"
4274 [(set (match_operand:TI 0 "register_operand" "=d,d")
4278 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4280 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4283 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4288 [(set_attr "op_type" "RRE,RXY")
4289 (set_attr "type" "idiv")])
4292 ; udivmoddi4 instruction pattern(s).
4295 (define_expand "udivmoddi4"
4296 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4297 (udiv:DI (match_operand:DI 1 "general_operand" "")
4298 (match_operand:DI 2 "nonimmediate_operand" "")))
4299 (set (match_operand:DI 3 "general_operand" "")
4300 (umod:DI (match_dup 1) (match_dup 2)))])
4301 (clobber (match_dup 4))]
4304 rtx insn, div_equal, mod_equal, equal;
4306 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4307 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4308 equal = gen_rtx_IOR (TImode,
4309 gen_rtx_ASHIFT (TImode,
4310 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4312 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4314 operands[4] = gen_reg_rtx(TImode);
4315 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4316 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4317 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4318 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4320 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4322 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4324 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4326 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4328 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4333 (define_insn "udivmodtidi3"
4334 [(set (match_operand:TI 0 "register_operand" "=d,d")
4339 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4341 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4345 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4350 [(set_attr "op_type" "RRE,RXY")
4351 (set_attr "type" "idiv")])
4354 ; divmodsi4 instruction pattern(s).
4357 (define_expand "divmodsi4"
4358 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4359 (div:SI (match_operand:SI 1 "general_operand" "")
4360 (match_operand:SI 2 "nonimmediate_operand" "")))
4361 (set (match_operand:SI 3 "general_operand" "")
4362 (mod:SI (match_dup 1) (match_dup 2)))])
4363 (clobber (match_dup 4))]
4366 rtx insn, div_equal, mod_equal, equal;
4368 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4369 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4370 equal = gen_rtx_IOR (DImode,
4371 gen_rtx_ASHIFT (DImode,
4372 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4374 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4376 operands[4] = gen_reg_rtx(DImode);
4377 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4378 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4380 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4382 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4384 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4386 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4388 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4393 (define_insn "divmoddisi3"
4394 [(set (match_operand:DI 0 "register_operand" "=d,d")
4399 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4401 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4405 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4410 [(set_attr "op_type" "RR,RX")
4411 (set_attr "type" "idiv")])
4414 ; udivsi3 and umodsi3 instruction pattern(s).
4417 (define_expand "udivmodsi4"
4418 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4419 (udiv:SI (match_operand:SI 1 "general_operand" "")
4420 (match_operand:SI 2 "nonimmediate_operand" "")))
4421 (set (match_operand:SI 3 "general_operand" "")
4422 (umod:SI (match_dup 1) (match_dup 2)))])
4423 (clobber (match_dup 4))]
4424 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4426 rtx insn, div_equal, mod_equal, equal;
4428 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4429 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4430 equal = gen_rtx_IOR (DImode,
4431 gen_rtx_ASHIFT (DImode,
4432 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4434 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4436 operands[4] = gen_reg_rtx(DImode);
4437 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4438 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4439 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4440 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4442 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4444 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4446 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4448 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4450 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4455 (define_insn "udivmoddisi3"
4456 [(set (match_operand:DI 0 "register_operand" "=d,d")
4461 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4463 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4467 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4468 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4472 [(set_attr "op_type" "RRE,RXY")
4473 (set_attr "type" "idiv")])
4475 (define_expand "udivsi3"
4476 [(set (match_operand:SI 0 "register_operand" "=d")
4477 (udiv:SI (match_operand:SI 1 "general_operand" "")
4478 (match_operand:SI 2 "general_operand" "")))
4479 (clobber (match_dup 3))]
4480 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4482 rtx insn, udiv_equal, umod_equal, equal;
4484 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4485 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4486 equal = gen_rtx_IOR (DImode,
4487 gen_rtx_ASHIFT (DImode,
4488 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4490 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4492 operands[3] = gen_reg_rtx (DImode);
4494 if (CONSTANT_P (operands[2]))
4496 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4498 rtx label1 = gen_label_rtx ();
4500 operands[1] = make_safe_from (operands[1], operands[0]);
4501 emit_move_insn (operands[0], const0_rtx);
4502 emit_insn (gen_cmpsi (operands[1], operands[2]));
4503 emit_jump_insn (gen_bltu (label1));
4504 emit_move_insn (operands[0], const1_rtx);
4505 emit_label (label1);
4509 operands[2] = force_reg (SImode, operands[2]);
4510 operands[2] = make_safe_from (operands[2], operands[0]);
4512 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4513 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4516 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4518 insn = emit_move_insn (operands[0],
4519 gen_lowpart (SImode, operands[3]));
4521 gen_rtx_EXPR_LIST (REG_EQUAL,
4522 udiv_equal, REG_NOTES (insn));
4527 rtx label1 = gen_label_rtx ();
4528 rtx label2 = gen_label_rtx ();
4529 rtx label3 = gen_label_rtx ();
4531 operands[1] = force_reg (SImode, operands[1]);
4532 operands[1] = make_safe_from (operands[1], operands[0]);
4533 operands[2] = force_reg (SImode, operands[2]);
4534 operands[2] = make_safe_from (operands[2], operands[0]);
4536 emit_move_insn (operands[0], const0_rtx);
4537 emit_insn (gen_cmpsi (operands[2], operands[1]));
4538 emit_jump_insn (gen_bgtu (label3));
4539 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4540 emit_jump_insn (gen_blt (label2));
4541 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4542 emit_jump_insn (gen_beq (label1));
4543 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4544 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4547 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4549 insn = emit_move_insn (operands[0],
4550 gen_lowpart (SImode, operands[3]));
4552 gen_rtx_EXPR_LIST (REG_EQUAL,
4553 udiv_equal, REG_NOTES (insn));
4555 emit_label (label1);
4556 emit_move_insn (operands[0], operands[1]);
4558 emit_label (label2);
4559 emit_move_insn (operands[0], const1_rtx);
4560 emit_label (label3);
4562 emit_move_insn (operands[0], operands[0]);
4566 (define_expand "umodsi3"
4567 [(set (match_operand:SI 0 "register_operand" "=d")
4568 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4569 (match_operand:SI 2 "nonimmediate_operand" "")))
4570 (clobber (match_dup 3))]
4571 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4573 rtx insn, udiv_equal, umod_equal, equal;
4575 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4576 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4577 equal = gen_rtx_IOR (DImode,
4578 gen_rtx_ASHIFT (DImode,
4579 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4581 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4583 operands[3] = gen_reg_rtx (DImode);
4585 if (CONSTANT_P (operands[2]))
4587 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4589 rtx label1 = gen_label_rtx ();
4591 operands[1] = make_safe_from (operands[1], operands[0]);
4592 emit_move_insn (operands[0], operands[1]);
4593 emit_insn (gen_cmpsi (operands[0], operands[2]));
4594 emit_jump_insn (gen_bltu (label1));
4595 emit_insn (gen_abssi2 (operands[0], operands[2]));
4596 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4597 emit_label (label1);
4601 operands[2] = force_reg (SImode, operands[2]);
4602 operands[2] = make_safe_from (operands[2], operands[0]);
4604 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4605 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4608 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4610 insn = emit_move_insn (operands[0],
4611 gen_highpart (SImode, operands[3]));
4613 gen_rtx_EXPR_LIST (REG_EQUAL,
4614 umod_equal, REG_NOTES (insn));
4619 rtx label1 = gen_label_rtx ();
4620 rtx label2 = gen_label_rtx ();
4621 rtx label3 = gen_label_rtx ();
4623 operands[1] = force_reg (SImode, operands[1]);
4624 operands[1] = make_safe_from (operands[1], operands[0]);
4625 operands[2] = force_reg (SImode, operands[2]);
4626 operands[2] = make_safe_from (operands[2], operands[0]);
4628 emit_move_insn(operands[0], operands[1]);
4629 emit_insn (gen_cmpsi (operands[2], operands[1]));
4630 emit_jump_insn (gen_bgtu (label3));
4631 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4632 emit_jump_insn (gen_blt (label2));
4633 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4634 emit_jump_insn (gen_beq (label1));
4635 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4636 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4639 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4641 insn = emit_move_insn (operands[0],
4642 gen_highpart (SImode, operands[3]));
4644 gen_rtx_EXPR_LIST (REG_EQUAL,
4645 umod_equal, REG_NOTES (insn));
4647 emit_label (label1);
4648 emit_move_insn (operands[0], const0_rtx);
4650 emit_label (label2);
4651 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4652 emit_label (label3);
4658 ; div(df|sf)3 instruction pattern(s).
4661 (define_expand "div<mode>3"
4662 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4663 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4664 (match_operand:FPR 2 "general_operand" "f,R")))]
4668 (define_insn "*div<mode>3"
4669 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4670 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4671 (match_operand:FPR 2 "general_operand" "f,R")))]
4672 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4676 [(set_attr "op_type" "RRE,RXE")
4677 (set_attr "type" "fdiv<mode>")])
4679 (define_insn "*div<mode>3_ibm"
4680 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4681 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4682 (match_operand:FPR 2 "general_operand" "f,R")))]
4683 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4687 [(set_attr "op_type" "RR,RX")
4688 (set_attr "type" "fdiv<mode>")])
4692 ;;- And instructions.
4695 (define_expand "and<mode>3"
4696 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4697 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
4698 (match_operand:INT 2 "general_operand" "")))
4699 (clobber (reg:CC CC_REGNUM))]
4701 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
4704 ; anddi3 instruction pattern(s).
4707 (define_insn "*anddi3_cc"
4708 [(set (reg CC_REGNUM)
4709 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4710 (match_operand:DI 2 "general_operand" "d,m"))
4712 (set (match_operand:DI 0 "register_operand" "=d,d")
4713 (and:DI (match_dup 1) (match_dup 2)))]
4714 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4718 [(set_attr "op_type" "RRE,RXY")])
4720 (define_insn "*anddi3_cconly"
4721 [(set (reg CC_REGNUM)
4722 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4723 (match_operand:DI 2 "general_operand" "d,m"))
4725 (clobber (match_scratch:DI 0 "=d,d"))]
4726 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
4727 /* Do not steal TM patterns. */
4728 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
4732 [(set_attr "op_type" "RRE,RXY")])
4734 (define_insn "*anddi3_extimm"
4735 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
4736 (and:DI (match_operand:DI 1 "nonimmediate_operand"
4737 "%d,o,0,0,0,0,0,0,0,0,0,0")
4738 (match_operand:DI 2 "general_operand"
4739 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q")))
4740 (clobber (reg:CC CC_REGNUM))]
4741 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
4755 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
4757 (define_insn "*anddi3"
4758 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
4759 (and:DI (match_operand:DI 1 "nonimmediate_operand"
4760 "%d,o,0,0,0,0,0,0,0,0")
4761 (match_operand:DI 2 "general_operand"
4762 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
4763 (clobber (reg:CC CC_REGNUM))]
4764 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
4776 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
4779 [(set (match_operand:DI 0 "s_operand" "")
4780 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
4781 (clobber (reg:CC CC_REGNUM))]
4784 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4785 (clobber (reg:CC CC_REGNUM))])]
4786 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4790 ; andsi3 instruction pattern(s).
4793 (define_insn "*andsi3_cc"
4794 [(set (reg CC_REGNUM)
4795 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4796 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
4798 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4799 (and:SI (match_dup 1) (match_dup 2)))]
4800 "s390_match_ccmode(insn, CCTmode)"
4806 [(set_attr "op_type" "RIL,RR,RX,RXY")])
4808 (define_insn "*andsi3_cconly"
4809 [(set (reg CC_REGNUM)
4810 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4811 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
4813 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
4814 "s390_match_ccmode(insn, CCTmode)
4815 /* Do not steal TM patterns. */
4816 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
4822 [(set_attr "op_type" "RIL,RR,RX,RXY")])
4824 (define_insn "*andsi3_zarch"
4825 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
4826 (and:SI (match_operand:SI 1 "nonimmediate_operand"
4827 "%d,o,0,0,0,0,0,0,0,0")
4828 (match_operand:SI 2 "general_operand"
4829 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
4830 (clobber (reg:CC CC_REGNUM))]
4831 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4843 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")])
4845 (define_insn "*andsi3_esa"
4846 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4847 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4848 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
4849 (clobber (reg:CC CC_REGNUM))]
4850 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4856 [(set_attr "op_type" "RR,RX,SI,SS")])
4859 [(set (match_operand:SI 0 "s_operand" "")
4860 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
4861 (clobber (reg:CC CC_REGNUM))]
4864 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4865 (clobber (reg:CC CC_REGNUM))])]
4866 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4869 ; andhi3 instruction pattern(s).
4872 (define_insn "*andhi3_zarch"
4873 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4874 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
4875 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
4876 (clobber (reg:CC CC_REGNUM))]
4877 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4883 [(set_attr "op_type" "RR,RI,SI,SS")])
4885 (define_insn "*andhi3_esa"
4886 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
4887 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
4888 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
4889 (clobber (reg:CC CC_REGNUM))]
4890 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4895 [(set_attr "op_type" "RR,SI,SS")])
4898 [(set (match_operand:HI 0 "s_operand" "")
4899 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
4900 (clobber (reg:CC CC_REGNUM))]
4903 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4904 (clobber (reg:CC CC_REGNUM))])]
4905 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4908 ; andqi3 instruction pattern(s).
4911 (define_insn "*andqi3_zarch"
4912 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
4913 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
4914 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
4915 (clobber (reg:CC CC_REGNUM))]
4916 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4923 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
4925 (define_insn "*andqi3_esa"
4926 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
4927 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
4928 (match_operand:QI 2 "general_operand" "d,n,Q")))
4929 (clobber (reg:CC CC_REGNUM))]
4930 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4935 [(set_attr "op_type" "RR,SI,SS")])
4938 ; Block and (NC) patterns.
4942 [(set (match_operand:BLK 0 "memory_operand" "=Q")
4943 (and:BLK (match_dup 0)
4944 (match_operand:BLK 1 "memory_operand" "Q")))
4945 (use (match_operand 2 "const_int_operand" "n"))
4946 (clobber (reg:CC CC_REGNUM))]
4947 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
4948 "nc\t%O0(%2,%R0),%S1"
4949 [(set_attr "op_type" "SS")])
4952 [(set (match_operand 0 "memory_operand" "")
4954 (match_operand 1 "memory_operand" "")))
4955 (clobber (reg:CC CC_REGNUM))]
4957 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4958 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
4960 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
4962 (clobber (reg:CC CC_REGNUM))])]
4964 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
4965 operands[0] = adjust_address (operands[0], BLKmode, 0);
4966 operands[1] = adjust_address (operands[1], BLKmode, 0);
4971 [(set (match_operand:BLK 0 "memory_operand" "")
4972 (and:BLK (match_dup 0)
4973 (match_operand:BLK 1 "memory_operand" "")))
4974 (use (match_operand 2 "const_int_operand" ""))
4975 (clobber (reg:CC CC_REGNUM))])
4977 [(set (match_operand:BLK 3 "memory_operand" "")
4978 (and:BLK (match_dup 3)
4979 (match_operand:BLK 4 "memory_operand" "")))
4980 (use (match_operand 5 "const_int_operand" ""))
4981 (clobber (reg:CC CC_REGNUM))])]
4982 "s390_offset_p (operands[0], operands[3], operands[2])
4983 && s390_offset_p (operands[1], operands[4], operands[2])
4984 && !s390_overlap_p (operands[0], operands[1],
4985 INTVAL (operands[2]) + INTVAL (operands[5]))
4986 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
4988 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
4990 (clobber (reg:CC CC_REGNUM))])]
4991 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
4992 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
4993 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
4997 ;;- Bit set (inclusive or) instructions.
5000 (define_expand "ior<mode>3"
5001 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5002 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
5003 (match_operand:INT 2 "general_operand" "")))
5004 (clobber (reg:CC CC_REGNUM))]
5006 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
5009 ; iordi3 instruction pattern(s).
5012 (define_insn "*iordi3_cc"
5013 [(set (reg CC_REGNUM)
5014 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5015 (match_operand:DI 2 "general_operand" "d,m"))
5017 (set (match_operand:DI 0 "register_operand" "=d,d")
5018 (ior:DI (match_dup 1) (match_dup 2)))]
5019 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5023 [(set_attr "op_type" "RRE,RXY")])
5025 (define_insn "*iordi3_cconly"
5026 [(set (reg CC_REGNUM)
5027 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5028 (match_operand:DI 2 "general_operand" "d,m"))
5030 (clobber (match_scratch:DI 0 "=d,d"))]
5031 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5035 [(set_attr "op_type" "RRE,RXY")])
5037 (define_insn "*iordi3_extimm"
5038 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5039 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
5040 (match_operand:DI 2 "general_operand"
5041 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q")))
5042 (clobber (reg:CC CC_REGNUM))]
5043 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5055 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5057 (define_insn "*iordi3"
5058 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5059 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5060 (match_operand:DI 2 "general_operand"
5061 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
5062 (clobber (reg:CC CC_REGNUM))]
5063 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5073 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
5076 [(set (match_operand:DI 0 "s_operand" "")
5077 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5078 (clobber (reg:CC CC_REGNUM))]
5081 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5082 (clobber (reg:CC CC_REGNUM))])]
5083 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5086 ; iorsi3 instruction pattern(s).
5089 (define_insn "*iorsi3_cc"
5090 [(set (reg CC_REGNUM)
5091 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5092 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5094 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5095 (ior:SI (match_dup 1) (match_dup 2)))]
5096 "s390_match_ccmode(insn, CCTmode)"
5102 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5104 (define_insn "*iorsi3_cconly"
5105 [(set (reg CC_REGNUM)
5106 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5107 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5109 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5110 "s390_match_ccmode(insn, CCTmode)"
5116 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5118 (define_insn "*iorsi3_zarch"
5119 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5120 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5121 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
5122 (clobber (reg:CC CC_REGNUM))]
5123 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5133 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")])
5135 (define_insn "*iorsi3_esa"
5136 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5137 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5138 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5139 (clobber (reg:CC CC_REGNUM))]
5140 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5146 [(set_attr "op_type" "RR,RX,SI,SS")])
5149 [(set (match_operand:SI 0 "s_operand" "")
5150 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5151 (clobber (reg:CC CC_REGNUM))]
5154 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5155 (clobber (reg:CC CC_REGNUM))])]
5156 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5159 ; iorhi3 instruction pattern(s).
5162 (define_insn "*iorhi3_zarch"
5163 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5164 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5165 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5166 (clobber (reg:CC CC_REGNUM))]
5167 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5173 [(set_attr "op_type" "RR,RI,SI,SS")])
5175 (define_insn "*iorhi3_esa"
5176 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5177 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5178 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5179 (clobber (reg:CC CC_REGNUM))]
5180 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5185 [(set_attr "op_type" "RR,SI,SS")])
5188 [(set (match_operand:HI 0 "s_operand" "")
5189 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5190 (clobber (reg:CC CC_REGNUM))]
5193 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5194 (clobber (reg:CC CC_REGNUM))])]
5195 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5198 ; iorqi3 instruction pattern(s).
5201 (define_insn "*iorqi3_zarch"
5202 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5203 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5204 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5205 (clobber (reg:CC CC_REGNUM))]
5206 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5213 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5215 (define_insn "*iorqi3_esa"
5216 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5217 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5218 (match_operand:QI 2 "general_operand" "d,n,Q")))
5219 (clobber (reg:CC CC_REGNUM))]
5220 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5225 [(set_attr "op_type" "RR,SI,SS")])
5228 ; Block inclusive or (OC) patterns.
5232 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5233 (ior:BLK (match_dup 0)
5234 (match_operand:BLK 1 "memory_operand" "Q")))
5235 (use (match_operand 2 "const_int_operand" "n"))
5236 (clobber (reg:CC CC_REGNUM))]
5237 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5238 "oc\t%O0(%2,%R0),%S1"
5239 [(set_attr "op_type" "SS")])
5242 [(set (match_operand 0 "memory_operand" "")
5244 (match_operand 1 "memory_operand" "")))
5245 (clobber (reg:CC CC_REGNUM))]
5247 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5248 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5250 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5252 (clobber (reg:CC CC_REGNUM))])]
5254 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5255 operands[0] = adjust_address (operands[0], BLKmode, 0);
5256 operands[1] = adjust_address (operands[1], BLKmode, 0);
5261 [(set (match_operand:BLK 0 "memory_operand" "")
5262 (ior:BLK (match_dup 0)
5263 (match_operand:BLK 1 "memory_operand" "")))
5264 (use (match_operand 2 "const_int_operand" ""))
5265 (clobber (reg:CC CC_REGNUM))])
5267 [(set (match_operand:BLK 3 "memory_operand" "")
5268 (ior:BLK (match_dup 3)
5269 (match_operand:BLK 4 "memory_operand" "")))
5270 (use (match_operand 5 "const_int_operand" ""))
5271 (clobber (reg:CC CC_REGNUM))])]
5272 "s390_offset_p (operands[0], operands[3], operands[2])
5273 && s390_offset_p (operands[1], operands[4], operands[2])
5274 && !s390_overlap_p (operands[0], operands[1],
5275 INTVAL (operands[2]) + INTVAL (operands[5]))
5276 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5278 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5280 (clobber (reg:CC CC_REGNUM))])]
5281 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5282 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5283 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5287 ;;- Xor instructions.
5290 (define_expand "xor<mode>3"
5291 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5292 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
5293 (match_operand:INT 2 "general_operand" "")))
5294 (clobber (reg:CC CC_REGNUM))]
5296 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
5299 ; xordi3 instruction pattern(s).
5302 (define_insn "*xordi3_cc"
5303 [(set (reg CC_REGNUM)
5304 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5305 (match_operand:DI 2 "general_operand" "d,m"))
5307 (set (match_operand:DI 0 "register_operand" "=d,d")
5308 (xor:DI (match_dup 1) (match_dup 2)))]
5309 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5313 [(set_attr "op_type" "RRE,RXY")])
5315 (define_insn "*xordi3_cconly"
5316 [(set (reg CC_REGNUM)
5317 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5318 (match_operand:DI 2 "general_operand" "d,m"))
5320 (clobber (match_scratch:DI 0 "=d,d"))]
5321 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5325 [(set_attr "op_type" "RRE,RXY")])
5327 (define_insn "*xordi3_extimm"
5328 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5329 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5330 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q")))
5331 (clobber (reg:CC CC_REGNUM))]
5332 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5340 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")])
5342 (define_insn "*xordi3"
5343 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5344 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5345 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5346 (clobber (reg:CC CC_REGNUM))]
5347 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5353 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5356 [(set (match_operand:DI 0 "s_operand" "")
5357 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5358 (clobber (reg:CC CC_REGNUM))]
5361 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5362 (clobber (reg:CC CC_REGNUM))])]
5363 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5366 ; xorsi3 instruction pattern(s).
5369 (define_insn "*xorsi3_cc"
5370 [(set (reg CC_REGNUM)
5371 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5372 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5374 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5375 (xor:SI (match_dup 1) (match_dup 2)))]
5376 "s390_match_ccmode(insn, CCTmode)"
5382 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5384 (define_insn "*xorsi3_cconly"
5385 [(set (reg CC_REGNUM)
5386 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5387 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5389 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5390 "s390_match_ccmode(insn, CCTmode)"
5396 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5398 (define_insn "*xorsi3"
5399 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5400 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5401 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
5402 (clobber (reg:CC CC_REGNUM))]
5403 "s390_logical_operator_ok_p (operands)"
5411 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")])
5414 [(set (match_operand:SI 0 "s_operand" "")
5415 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5416 (clobber (reg:CC CC_REGNUM))]
5419 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5420 (clobber (reg:CC CC_REGNUM))])]
5421 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5424 ; xorhi3 instruction pattern(s).
5427 (define_insn "*xorhi3"
5428 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5429 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5430 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
5431 (clobber (reg:CC CC_REGNUM))]
5432 "s390_logical_operator_ok_p (operands)"
5438 [(set_attr "op_type" "RIL,RR,SI,SS")])
5441 [(set (match_operand:HI 0 "s_operand" "")
5442 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5443 (clobber (reg:CC CC_REGNUM))]
5446 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5447 (clobber (reg:CC CC_REGNUM))])]
5448 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5451 ; xorqi3 instruction pattern(s).
5454 (define_insn "*xorqi3"
5455 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5456 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5457 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
5458 (clobber (reg:CC CC_REGNUM))]
5459 "s390_logical_operator_ok_p (operands)"
5466 [(set_attr "op_type" "RIL,RR,SI,SIY,SS")])
5469 ; Block exclusive or (XC) patterns.
5473 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5474 (xor:BLK (match_dup 0)
5475 (match_operand:BLK 1 "memory_operand" "Q")))
5476 (use (match_operand 2 "const_int_operand" "n"))
5477 (clobber (reg:CC CC_REGNUM))]
5478 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5479 "xc\t%O0(%2,%R0),%S1"
5480 [(set_attr "op_type" "SS")])
5483 [(set (match_operand 0 "memory_operand" "")
5485 (match_operand 1 "memory_operand" "")))
5486 (clobber (reg:CC CC_REGNUM))]
5488 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5489 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5491 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5493 (clobber (reg:CC CC_REGNUM))])]
5495 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5496 operands[0] = adjust_address (operands[0], BLKmode, 0);
5497 operands[1] = adjust_address (operands[1], BLKmode, 0);
5502 [(set (match_operand:BLK 0 "memory_operand" "")
5503 (xor:BLK (match_dup 0)
5504 (match_operand:BLK 1 "memory_operand" "")))
5505 (use (match_operand 2 "const_int_operand" ""))
5506 (clobber (reg:CC CC_REGNUM))])
5508 [(set (match_operand:BLK 3 "memory_operand" "")
5509 (xor:BLK (match_dup 3)
5510 (match_operand:BLK 4 "memory_operand" "")))
5511 (use (match_operand 5 "const_int_operand" ""))
5512 (clobber (reg:CC CC_REGNUM))])]
5513 "s390_offset_p (operands[0], operands[3], operands[2])
5514 && s390_offset_p (operands[1], operands[4], operands[2])
5515 && !s390_overlap_p (operands[0], operands[1],
5516 INTVAL (operands[2]) + INTVAL (operands[5]))
5517 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5519 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5521 (clobber (reg:CC CC_REGNUM))])]
5522 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5523 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5524 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5527 ; Block xor (XC) patterns with src == dest.
5530 (define_insn "*xc_zero"
5531 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5533 (use (match_operand 1 "const_int_operand" "n"))
5534 (clobber (reg:CC CC_REGNUM))]
5535 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5536 "xc\t%O0(%1,%R0),%S0"
5537 [(set_attr "op_type" "SS")])
5541 [(set (match_operand:BLK 0 "memory_operand" "")
5543 (use (match_operand 1 "const_int_operand" ""))
5544 (clobber (reg:CC CC_REGNUM))])
5546 [(set (match_operand:BLK 2 "memory_operand" "")
5548 (use (match_operand 3 "const_int_operand" ""))
5549 (clobber (reg:CC CC_REGNUM))])]
5550 "s390_offset_p (operands[0], operands[2], operands[1])
5551 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5553 [(set (match_dup 4) (const_int 0))
5555 (clobber (reg:CC CC_REGNUM))])]
5556 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5557 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5561 ;;- Negate instructions.
5565 ; neg(di|si)2 instruction pattern(s).
5568 (define_expand "neg<mode>2"
5570 [(set (match_operand:DSI 0 "register_operand" "=d")
5571 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
5572 (clobber (reg:CC CC_REGNUM))])]
5576 (define_insn "*negdi2_sign_cc"
5577 [(set (reg CC_REGNUM)
5578 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
5579 (match_operand:SI 1 "register_operand" "d") 0)
5580 (const_int 32)) (const_int 32)))
5582 (set (match_operand:DI 0 "register_operand" "=d")
5583 (neg:DI (sign_extend:DI (match_dup 1))))]
5584 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5586 [(set_attr "op_type" "RRE")])
5588 (define_insn "*negdi2_sign"
5589 [(set (match_operand:DI 0 "register_operand" "=d")
5590 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5591 (clobber (reg:CC CC_REGNUM))]
5594 [(set_attr "op_type" "RRE")])
5596 (define_insn "*neg<mode>2_cc"
5597 [(set (reg CC_REGNUM)
5598 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5600 (set (match_operand:GPR 0 "register_operand" "=d")
5601 (neg:GPR (match_dup 1)))]
5602 "s390_match_ccmode (insn, CCAmode)"
5604 [(set_attr "op_type" "RR<E>")])
5606 (define_insn "*neg<mode>2_cconly"
5607 [(set (reg CC_REGNUM)
5608 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5610 (clobber (match_scratch:GPR 0 "=d"))]
5611 "s390_match_ccmode (insn, CCAmode)"
5613 [(set_attr "op_type" "RR<E>")])
5615 (define_insn "*neg<mode>2"
5616 [(set (match_operand:GPR 0 "register_operand" "=d")
5617 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
5618 (clobber (reg:CC CC_REGNUM))]
5621 [(set_attr "op_type" "RR<E>")])
5623 (define_insn_and_split "*negdi2_31"
5624 [(set (match_operand:DI 0 "register_operand" "=d")
5625 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5626 (clobber (reg:CC CC_REGNUM))]
5629 "&& reload_completed"
5631 [(set (match_dup 2) (neg:SI (match_dup 3)))
5632 (clobber (reg:CC CC_REGNUM))])
5634 [(set (reg:CCAP CC_REGNUM)
5635 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
5636 (set (match_dup 4) (neg:SI (match_dup 5)))])
5638 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
5640 (label_ref (match_dup 6))))
5642 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
5643 (clobber (reg:CC CC_REGNUM))])
5645 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
5646 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5647 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5648 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5649 operands[6] = gen_label_rtx ();")
5652 ; neg(df|sf)2 instruction pattern(s).
5655 (define_expand "neg<mode>2"
5657 [(set (match_operand:FPR 0 "register_operand" "=f")
5658 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5659 (clobber (reg:CC CC_REGNUM))])]
5663 (define_insn "*neg<mode>2_cc"
5664 [(set (reg CC_REGNUM)
5665 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5666 (match_operand:FPR 2 "const0_operand" "")))
5667 (set (match_operand:FPR 0 "register_operand" "=f")
5668 (neg:FPR (match_dup 1)))]
5669 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5671 [(set_attr "op_type" "RRE")
5672 (set_attr "type" "fsimp<mode>")])
5674 (define_insn "*neg<mode>2_cconly"
5675 [(set (reg CC_REGNUM)
5676 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5677 (match_operand:FPR 2 "const0_operand" "")))
5678 (clobber (match_scratch:FPR 0 "=f"))]
5679 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5681 [(set_attr "op_type" "RRE")
5682 (set_attr "type" "fsimp<mode>")])
5684 (define_insn "*neg<mode>2"
5685 [(set (match_operand:FPR 0 "register_operand" "=f")
5686 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5687 (clobber (reg:CC CC_REGNUM))]
5688 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5690 [(set_attr "op_type" "RRE")
5691 (set_attr "type" "fsimp<mode>")])
5693 (define_insn "*neg<mode>2_ibm"
5694 [(set (match_operand:FPR 0 "register_operand" "=f")
5695 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5696 (clobber (reg:CC CC_REGNUM))]
5697 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5699 [(set_attr "op_type" "RR")
5700 (set_attr "type" "fsimp<mode>")])
5704 ;;- Absolute value instructions.
5708 ; abs(di|si)2 instruction pattern(s).
5711 (define_insn "*absdi2_sign_cc"
5712 [(set (reg CC_REGNUM)
5713 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5714 (match_operand:SI 1 "register_operand" "d") 0)
5715 (const_int 32)) (const_int 32)))
5717 (set (match_operand:DI 0 "register_operand" "=d")
5718 (abs:DI (sign_extend:DI (match_dup 1))))]
5719 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5721 [(set_attr "op_type" "RRE")])
5723 (define_insn "*absdi2_sign"
5724 [(set (match_operand:DI 0 "register_operand" "=d")
5725 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5726 (clobber (reg:CC CC_REGNUM))]
5729 [(set_attr "op_type" "RRE")])
5731 (define_insn "*abs<mode>2_cc"
5732 [(set (reg CC_REGNUM)
5733 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
5735 (set (match_operand:GPR 0 "register_operand" "=d")
5736 (abs:GPR (match_dup 1)))]
5737 "s390_match_ccmode (insn, CCAmode)"
5739 [(set_attr "op_type" "RR<E>")])
5741 (define_insn "*abs<mode>2_cconly"
5742 [(set (reg CC_REGNUM)
5743 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
5745 (clobber (match_scratch:GPR 0 "=d"))]
5746 "s390_match_ccmode (insn, CCAmode)"
5748 [(set_attr "op_type" "RR<E>")])
5750 (define_insn "abs<mode>2"
5751 [(set (match_operand:GPR 0 "register_operand" "=d")
5752 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5753 (clobber (reg:CC CC_REGNUM))]
5756 [(set_attr "op_type" "RR<E>")])
5759 ; abs(df|sf)2 instruction pattern(s).
5762 (define_expand "abs<mode>2"
5764 [(set (match_operand:FPR 0 "register_operand" "=f")
5765 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5766 (clobber (reg:CC CC_REGNUM))])]
5770 (define_insn "*abs<mode>2_cc"
5771 [(set (reg CC_REGNUM)
5772 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5773 (match_operand:FPR 2 "const0_operand" "")))
5774 (set (match_operand:FPR 0 "register_operand" "=f")
5775 (abs:FPR (match_dup 1)))]
5776 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5778 [(set_attr "op_type" "RRE")
5779 (set_attr "type" "fsimp<mode>")])
5781 (define_insn "*abs<mode>2_cconly"
5782 [(set (reg CC_REGNUM)
5783 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5784 (match_operand:FPR 2 "const0_operand" "")))
5785 (clobber (match_scratch:FPR 0 "=f"))]
5786 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5788 [(set_attr "op_type" "RRE")
5789 (set_attr "type" "fsimp<mode>")])
5791 (define_insn "*abs<mode>2"
5792 [(set (match_operand:FPR 0 "register_operand" "=f")
5793 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5794 (clobber (reg:CC CC_REGNUM))]
5795 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5797 [(set_attr "op_type" "RRE")
5798 (set_attr "type" "fsimp<mode>")])
5800 (define_insn "*abs<mode>2_ibm"
5801 [(set (match_operand:FPR 0 "register_operand" "=f")
5802 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5803 (clobber (reg:CC CC_REGNUM))]
5804 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5806 [(set_attr "op_type" "RR")
5807 (set_attr "type" "fsimp<mode>")])
5810 ;;- Negated absolute value instructions
5817 (define_insn "*negabsdi2_sign_cc"
5818 [(set (reg CC_REGNUM)
5819 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5820 (match_operand:SI 1 "register_operand" "d") 0)
5821 (const_int 32)) (const_int 32))))
5823 (set (match_operand:DI 0 "register_operand" "=d")
5824 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
5825 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5827 [(set_attr "op_type" "RRE")])
5829 (define_insn "*negabsdi2_sign"
5830 [(set (match_operand:DI 0 "register_operand" "=d")
5831 (neg:DI (abs:DI (sign_extend:DI
5832 (match_operand:SI 1 "register_operand" "d")))))
5833 (clobber (reg:CC CC_REGNUM))]
5836 [(set_attr "op_type" "RRE")])
5838 (define_insn "*negabs<mode>2_cc"
5839 [(set (reg CC_REGNUM)
5840 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5842 (set (match_operand:GPR 0 "register_operand" "=d")
5843 (neg:GPR (abs:GPR (match_dup 1))))]
5844 "s390_match_ccmode (insn, CCAmode)"
5846 [(set_attr "op_type" "RR<E>")])
5848 (define_insn "*negabs<mode>2_cconly"
5849 [(set (reg CC_REGNUM)
5850 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5852 (clobber (match_scratch:GPR 0 "=d"))]
5853 "s390_match_ccmode (insn, CCAmode)"
5855 [(set_attr "op_type" "RR<E>")])
5857 (define_insn "*negabs<mode>2"
5858 [(set (match_operand:GPR 0 "register_operand" "=d")
5859 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
5860 (clobber (reg:CC CC_REGNUM))]
5863 [(set_attr "op_type" "RR<E>")])
5869 (define_insn "*negabs<mode>2_cc"
5870 [(set (reg CC_REGNUM)
5871 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5872 (match_operand:FPR 2 "const0_operand" "")))
5873 (set (match_operand:FPR 0 "register_operand" "=f")
5874 (neg:FPR (abs:FPR (match_dup 1))))]
5875 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5877 [(set_attr "op_type" "RRE")
5878 (set_attr "type" "fsimp<mode>")])
5880 (define_insn "*negabs<mode>2_cconly"
5881 [(set (reg CC_REGNUM)
5882 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5883 (match_operand:FPR 2 "const0_operand" "")))
5884 (clobber (match_scratch:FPR 0 "=f"))]
5885 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5887 [(set_attr "op_type" "RRE")
5888 (set_attr "type" "fsimp<mode>")])
5890 (define_insn "*negabs<mode>2"
5891 [(set (match_operand:FPR 0 "register_operand" "=f")
5892 (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
5893 (clobber (reg:CC CC_REGNUM))]
5894 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5896 [(set_attr "op_type" "RRE")
5897 (set_attr "type" "fsimp<mode>")])
5900 ;;- Square root instructions.
5904 ; sqrt(df|sf)2 instruction pattern(s).
5907 (define_insn "sqrt<mode>2"
5908 [(set (match_operand:FPR 0 "register_operand" "=f,f")
5909 (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))]
5910 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5914 [(set_attr "op_type" "RRE,RXE")
5915 (set_attr "type" "fsqrt<mode>")])
5919 ;;- One complement instructions.
5923 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
5926 (define_expand "one_cmpl<mode>2"
5928 [(set (match_operand:INT 0 "register_operand" "")
5929 (xor:INT (match_operand:INT 1 "register_operand" "")
5931 (clobber (reg:CC CC_REGNUM))])]
5937 ;; Find leftmost bit instructions.
5940 (define_expand "clzdi2"
5941 [(set (match_operand:DI 0 "register_operand" "=d")
5942 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
5943 "TARGET_EXTIMM && TARGET_64BIT"
5945 rtx insn, clz_equal;
5946 rtx wide_reg = gen_reg_rtx (TImode);
5947 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
5949 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
5951 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
5953 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
5955 gen_rtx_EXPR_LIST (REG_EQUAL, clz_equal, REG_NOTES (insn));
5960 (define_insn "clztidi2"
5961 [(set (match_operand:TI 0 "register_operand" "=d")
5965 (xor:DI (match_operand:DI 1 "register_operand" "d")
5966 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
5967 (subreg:SI (clz:DI (match_dup 1)) 4))))
5970 (zero_extend:TI (clz:DI (match_dup 1)))))
5971 (clobber (reg:CC CC_REGNUM))]
5972 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
5973 == (unsigned HOST_WIDE_INT) 1 << 63
5974 && TARGET_EXTIMM && TARGET_64BIT"
5976 [(set_attr "op_type" "RRE")])
5980 ;;- Rotate instructions.
5984 ; rotl(di|si)3 instruction pattern(s).
5987 (define_insn "rotl<mode>3"
5988 [(set (match_operand:GPR 0 "register_operand" "=d")
5989 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
5990 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
5993 [(set_attr "op_type" "RSE")
5994 (set_attr "atype" "reg")])
5996 (define_insn "*rotl<mode>3_and"
5997 [(set (match_operand:GPR 0 "register_operand" "=d")
5998 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
5999 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6000 (match_operand:SI 3 "const_int_operand" "n"))))]
6001 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
6003 [(set_attr "op_type" "RSE")
6004 (set_attr "atype" "reg")])
6008 ;;- Shift instructions.
6012 ; (ashl|lshr)(di|si)3 instruction pattern(s).
6015 (define_expand "<shift><mode>3"
6016 [(set (match_operand:DSI 0 "register_operand" "")
6017 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
6018 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
6022 (define_insn "*<shift>di3_31"
6023 [(set (match_operand:DI 0 "register_operand" "=d")
6024 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6025 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6028 [(set_attr "op_type" "RS")
6029 (set_attr "atype" "reg")])
6031 (define_insn "*<shift><mode>3"
6032 [(set (match_operand:GPR 0 "register_operand" "=d")
6033 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6034 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6036 "s<lr>l<g>\t%0,<1>%Y2"
6037 [(set_attr "op_type" "RS<E>")
6038 (set_attr "atype" "reg")])
6040 (define_insn "*<shift>di3_31_and"
6041 [(set (match_operand:DI 0 "register_operand" "=d")
6042 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6043 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6044 (match_operand:SI 3 "const_int_operand" "n"))))]
6045 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6047 [(set_attr "op_type" "RS")
6048 (set_attr "atype" "reg")])
6050 (define_insn "*<shift><mode>3_and"
6051 [(set (match_operand:GPR 0 "register_operand" "=d")
6052 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6053 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6054 (match_operand:SI 3 "const_int_operand" "n"))))]
6055 "(INTVAL (operands[3]) & 63) == 63"
6056 "s<lr>l<g>\t%0,<1>%Y2"
6057 [(set_attr "op_type" "RS<E>")
6058 (set_attr "atype" "reg")])
6061 ; ashr(di|si)3 instruction pattern(s).
6064 (define_expand "ashr<mode>3"
6066 [(set (match_operand:DSI 0 "register_operand" "")
6067 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
6068 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
6069 (clobber (reg:CC CC_REGNUM))])]
6073 (define_insn "*ashrdi3_cc_31"
6074 [(set (reg CC_REGNUM)
6075 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6076 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6078 (set (match_operand:DI 0 "register_operand" "=d")
6079 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6080 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6082 [(set_attr "op_type" "RS")
6083 (set_attr "atype" "reg")])
6085 (define_insn "*ashrdi3_cconly_31"
6086 [(set (reg CC_REGNUM)
6087 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6088 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6090 (clobber (match_scratch:DI 0 "=d"))]
6091 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6093 [(set_attr "op_type" "RS")
6094 (set_attr "atype" "reg")])
6096 (define_insn "*ashrdi3_31"
6097 [(set (match_operand:DI 0 "register_operand" "=d")
6098 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6099 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
6100 (clobber (reg:CC CC_REGNUM))]
6103 [(set_attr "op_type" "RS")
6104 (set_attr "atype" "reg")])
6106 (define_insn "*ashr<mode>3_cc"
6107 [(set (reg CC_REGNUM)
6108 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6109 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6111 (set (match_operand:GPR 0 "register_operand" "=d")
6112 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
6113 "s390_match_ccmode(insn, CCSmode)"
6115 [(set_attr "op_type" "RS<E>")
6116 (set_attr "atype" "reg")])
6118 (define_insn "*ashr<mode>3_cconly"
6119 [(set (reg CC_REGNUM)
6120 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6121 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6123 (clobber (match_scratch:GPR 0 "=d"))]
6124 "s390_match_ccmode(insn, CCSmode)"
6126 [(set_attr "op_type" "RS<E>")
6127 (set_attr "atype" "reg")])
6129 (define_insn "*ashr<mode>3"
6130 [(set (match_operand:GPR 0 "register_operand" "=d")
6131 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6132 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
6133 (clobber (reg:CC CC_REGNUM))]
6136 [(set_attr "op_type" "RS<E>")
6137 (set_attr "atype" "reg")])
6140 ; shift pattern with implicit ANDs
6142 (define_insn "*ashrdi3_cc_31_and"
6143 [(set (reg CC_REGNUM)
6144 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6145 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6146 (match_operand:SI 3 "const_int_operand" "n")))
6148 (set (match_operand:DI 0 "register_operand" "=d")
6149 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
6150 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6151 && (INTVAL (operands[3]) & 63) == 63"
6153 [(set_attr "op_type" "RS")
6154 (set_attr "atype" "reg")])
6156 (define_insn "*ashrdi3_cconly_31_and"
6157 [(set (reg CC_REGNUM)
6158 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6159 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6160 (match_operand:SI 3 "const_int_operand" "n")))
6162 (clobber (match_scratch:DI 0 "=d"))]
6163 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6164 && (INTVAL (operands[3]) & 63) == 63"
6166 [(set_attr "op_type" "RS")
6167 (set_attr "atype" "reg")])
6169 (define_insn "*ashrdi3_31_and"
6170 [(set (match_operand:DI 0 "register_operand" "=d")
6171 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6172 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6173 (match_operand:SI 3 "const_int_operand" "n"))))
6174 (clobber (reg:CC CC_REGNUM))]
6175 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6177 [(set_attr "op_type" "RS")
6178 (set_attr "atype" "reg")])
6180 (define_insn "*ashr<mode>3_cc_and"
6181 [(set (reg CC_REGNUM)
6182 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6183 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6184 (match_operand:SI 3 "const_int_operand" "n")))
6186 (set (match_operand:GPR 0 "register_operand" "=d")
6187 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
6188 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
6190 [(set_attr "op_type" "RS<E>")
6191 (set_attr "atype" "reg")])
6193 (define_insn "*ashr<mode>3_cconly_and"
6194 [(set (reg CC_REGNUM)
6195 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6196 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6197 (match_operand:SI 3 "const_int_operand" "n")))
6199 (clobber (match_scratch:GPR 0 "=d"))]
6200 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
6202 [(set_attr "op_type" "RS<E>")
6203 (set_attr "atype" "reg")])
6205 (define_insn "*ashr<mode>3_and"
6206 [(set (match_operand:GPR 0 "register_operand" "=d")
6207 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6208 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6209 (match_operand:SI 3 "const_int_operand" "n"))))
6210 (clobber (reg:CC CC_REGNUM))]
6211 "(INTVAL (operands[3]) & 63) == 63"
6213 [(set_attr "op_type" "RS<E>")
6214 (set_attr "atype" "reg")])
6218 ;; Branch instruction patterns.
6221 (define_expand "b<code>"
6223 (if_then_else (COMPARE (match_operand 0 "" "")
6228 "s390_emit_jump (operands[0],
6229 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
6233 ;;- Conditional jump instructions.
6236 (define_insn "*cjump_64"
6239 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6240 (label_ref (match_operand 0 "" ""))
6244 if (get_attr_length (insn) == 4)
6247 return "jg%C1\t%l0";
6249 [(set_attr "op_type" "RI")
6250 (set_attr "type" "branch")
6251 (set (attr "length")
6252 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6253 (const_int 4) (const_int 6)))])
6255 (define_insn "*cjump_31"
6258 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6259 (label_ref (match_operand 0 "" ""))
6263 gcc_assert (get_attr_length (insn) == 4);
6266 [(set_attr "op_type" "RI")
6267 (set_attr "type" "branch")
6268 (set (attr "length")
6269 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6270 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6271 (const_int 4) (const_int 6))
6272 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6273 (const_int 4) (const_int 8))))])
6275 (define_insn "*cjump_long"
6278 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6279 (match_operand 0 "address_operand" "U")
6283 if (get_attr_op_type (insn) == OP_TYPE_RR)
6288 [(set (attr "op_type")
6289 (if_then_else (match_operand 0 "register_operand" "")
6290 (const_string "RR") (const_string "RX")))
6291 (set_attr "type" "branch")
6292 (set_attr "atype" "agen")])
6296 ;;- Negated conditional jump instructions.
6299 (define_insn "*icjump_64"
6302 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6304 (label_ref (match_operand 0 "" ""))))]
6307 if (get_attr_length (insn) == 4)
6310 return "jg%D1\t%l0";
6312 [(set_attr "op_type" "RI")
6313 (set_attr "type" "branch")
6314 (set (attr "length")
6315 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6316 (const_int 4) (const_int 6)))])
6318 (define_insn "*icjump_31"
6321 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6323 (label_ref (match_operand 0 "" ""))))]
6326 gcc_assert (get_attr_length (insn) == 4);
6329 [(set_attr "op_type" "RI")
6330 (set_attr "type" "branch")
6331 (set (attr "length")
6332 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6333 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6334 (const_int 4) (const_int 6))
6335 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6336 (const_int 4) (const_int 8))))])
6338 (define_insn "*icjump_long"
6341 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6343 (match_operand 0 "address_operand" "U")))]
6346 if (get_attr_op_type (insn) == OP_TYPE_RR)
6351 [(set (attr "op_type")
6352 (if_then_else (match_operand 0 "register_operand" "")
6353 (const_string "RR") (const_string "RX")))
6354 (set_attr "type" "branch")
6355 (set_attr "atype" "agen")])
6358 ;;- Trap instructions.
6362 [(trap_if (const_int 1) (const_int 0))]
6365 [(set_attr "op_type" "RI")
6366 (set_attr "type" "branch")])
6368 (define_expand "conditional_trap"
6369 [(trap_if (match_operand 0 "comparison_operator" "")
6370 (match_operand 1 "general_operand" ""))]
6373 if (operands[1] != const0_rtx) FAIL;
6374 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6375 s390_compare_op0, s390_compare_op1);
6378 (define_insn "*trap"
6379 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6383 [(set_attr "op_type" "RI")
6384 (set_attr "type" "branch")])
6387 ;;- Loop instructions.
6389 ;; This is all complicated by the fact that since this is a jump insn
6390 ;; we must handle our own output reloads.
6392 (define_expand "doloop_end"
6393 [(use (match_operand 0 "" "")) ; loop pseudo
6394 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6395 (use (match_operand 2 "" "")) ; max iterations
6396 (use (match_operand 3 "" "")) ; loop level
6397 (use (match_operand 4 "" ""))] ; label
6400 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6401 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6402 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6403 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6404 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6405 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6412 (define_insn_and_split "doloop_si64"
6415 (ne (match_operand:SI 1 "register_operand" "d,d")
6417 (label_ref (match_operand 0 "" ""))
6419 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6420 (plus:SI (match_dup 1) (const_int -1)))
6421 (clobber (match_scratch:SI 3 "=X,&1"))
6422 (clobber (reg:CC CC_REGNUM))]
6425 if (which_alternative != 0)
6427 else if (get_attr_length (insn) == 4)
6428 return "brct\t%1,%l0";
6430 return "ahi\t%1,-1\;jgne\t%l0";
6432 "&& reload_completed
6433 && (! REG_P (operands[2])
6434 || ! rtx_equal_p (operands[1], operands[2]))"
6435 [(parallel [(set (reg:CCAN CC_REGNUM)
6436 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6438 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6439 (set (match_dup 2) (match_dup 3))
6440 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6441 (label_ref (match_dup 0))
6444 [(set_attr "op_type" "RI")
6445 (set_attr "type" "branch")
6446 (set (attr "length")
6447 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6448 (const_int 4) (const_int 10)))])
6450 (define_insn_and_split "doloop_si31"
6453 (ne (match_operand:SI 1 "register_operand" "d,d")
6455 (label_ref (match_operand 0 "" ""))
6457 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6458 (plus:SI (match_dup 1) (const_int -1)))
6459 (clobber (match_scratch:SI 3 "=X,&1"))
6460 (clobber (reg:CC CC_REGNUM))]
6463 if (which_alternative != 0)
6465 else if (get_attr_length (insn) == 4)
6466 return "brct\t%1,%l0";
6470 "&& reload_completed
6471 && (! REG_P (operands[2])
6472 || ! rtx_equal_p (operands[1], operands[2]))"
6473 [(parallel [(set (reg:CCAN CC_REGNUM)
6474 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6476 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6477 (set (match_dup 2) (match_dup 3))
6478 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6479 (label_ref (match_dup 0))
6482 [(set_attr "op_type" "RI")
6483 (set_attr "type" "branch")
6484 (set (attr "length")
6485 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6486 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6487 (const_int 4) (const_int 6))
6488 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6489 (const_int 4) (const_int 8))))])
6491 (define_insn "*doloop_si_long"
6494 (ne (match_operand:SI 1 "register_operand" "d,d")
6496 (match_operand 0 "address_operand" "U,U")
6498 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
6499 (plus:SI (match_dup 1) (const_int -1)))
6500 (clobber (match_scratch:SI 3 "=X,&1"))
6501 (clobber (reg:CC CC_REGNUM))]
6504 if (get_attr_op_type (insn) == OP_TYPE_RR)
6505 return "bctr\t%1,%0";
6507 return "bct\t%1,%a0";
6509 [(set (attr "op_type")
6510 (if_then_else (match_operand 0 "register_operand" "")
6511 (const_string "RR") (const_string "RX")))
6512 (set_attr "type" "branch")
6513 (set_attr "atype" "agen")])
6515 (define_insn_and_split "doloop_di"
6518 (ne (match_operand:DI 1 "register_operand" "d,d")
6520 (label_ref (match_operand 0 "" ""))
6522 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
6523 (plus:DI (match_dup 1) (const_int -1)))
6524 (clobber (match_scratch:DI 3 "=X,&1"))
6525 (clobber (reg:CC CC_REGNUM))]
6528 if (which_alternative != 0)
6530 else if (get_attr_length (insn) == 4)
6531 return "brctg\t%1,%l0";
6533 return "aghi\t%1,-1\;jgne\t%l0";
6535 "&& reload_completed
6536 && (! REG_P (operands[2])
6537 || ! rtx_equal_p (operands[1], operands[2]))"
6538 [(parallel [(set (reg:CCAN CC_REGNUM)
6539 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6541 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6542 (set (match_dup 2) (match_dup 3))
6543 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6544 (label_ref (match_dup 0))
6547 [(set_attr "op_type" "RI")
6548 (set_attr "type" "branch")
6549 (set (attr "length")
6550 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6551 (const_int 4) (const_int 10)))])
6554 ;;- Unconditional jump instructions.
6558 ; jump instruction pattern(s).
6561 (define_expand "jump"
6562 [(match_operand 0 "" "")]
6564 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
6566 (define_insn "*jump64"
6567 [(set (pc) (label_ref (match_operand 0 "" "")))]
6570 if (get_attr_length (insn) == 4)
6575 [(set_attr "op_type" "RI")
6576 (set_attr "type" "branch")
6577 (set (attr "length")
6578 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6579 (const_int 4) (const_int 6)))])
6581 (define_insn "*jump31"
6582 [(set (pc) (label_ref (match_operand 0 "" "")))]
6585 gcc_assert (get_attr_length (insn) == 4);
6588 [(set_attr "op_type" "RI")
6589 (set_attr "type" "branch")
6590 (set (attr "length")
6591 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6592 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6593 (const_int 4) (const_int 6))
6594 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6595 (const_int 4) (const_int 8))))])
6598 ; indirect-jump instruction pattern(s).
6601 (define_insn "indirect_jump"
6602 [(set (pc) (match_operand 0 "address_operand" "U"))]
6605 if (get_attr_op_type (insn) == OP_TYPE_RR)
6610 [(set (attr "op_type")
6611 (if_then_else (match_operand 0 "register_operand" "")
6612 (const_string "RR") (const_string "RX")))
6613 (set_attr "type" "branch")
6614 (set_attr "atype" "agen")])
6617 ; casesi instruction pattern(s).
6620 (define_insn "casesi_jump"
6621 [(set (pc) (match_operand 0 "address_operand" "U"))
6622 (use (label_ref (match_operand 1 "" "")))]
6625 if (get_attr_op_type (insn) == OP_TYPE_RR)
6630 [(set (attr "op_type")
6631 (if_then_else (match_operand 0 "register_operand" "")
6632 (const_string "RR") (const_string "RX")))
6633 (set_attr "type" "branch")
6634 (set_attr "atype" "agen")])
6636 (define_expand "casesi"
6637 [(match_operand:SI 0 "general_operand" "")
6638 (match_operand:SI 1 "general_operand" "")
6639 (match_operand:SI 2 "general_operand" "")
6640 (label_ref (match_operand 3 "" ""))
6641 (label_ref (match_operand 4 "" ""))]
6644 rtx index = gen_reg_rtx (SImode);
6645 rtx base = gen_reg_rtx (Pmode);
6646 rtx target = gen_reg_rtx (Pmode);
6648 emit_move_insn (index, operands[0]);
6649 emit_insn (gen_subsi3 (index, index, operands[1]));
6650 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6653 if (Pmode != SImode)
6654 index = convert_to_mode (Pmode, index, 1);
6655 if (GET_CODE (index) != REG)
6656 index = copy_to_mode_reg (Pmode, index);
6659 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6661 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
6663 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6665 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
6666 emit_move_insn (target, index);
6669 target = gen_rtx_PLUS (Pmode, base, target);
6670 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6677 ;;- Jump to subroutine.
6682 ; untyped call instruction pattern(s).
6685 ;; Call subroutine returning any type.
6686 (define_expand "untyped_call"
6687 [(parallel [(call (match_operand 0 "" "")
6689 (match_operand 1 "" "")
6690 (match_operand 2 "" "")])]
6695 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6697 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6699 rtx set = XVECEXP (operands[2], 0, i);
6700 emit_move_insn (SET_DEST (set), SET_SRC (set));
6703 /* The optimizer does not know that the call sets the function value
6704 registers we stored in the result block. We avoid problems by
6705 claiming that all hard registers are used and clobbered at this
6707 emit_insn (gen_blockage ());
6712 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6713 ;; all of memory. This blocks insns from being moved across this point.
6715 (define_insn "blockage"
6716 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6719 [(set_attr "type" "none")
6720 (set_attr "length" "0")])
6726 (define_expand "sibcall"
6727 [(call (match_operand 0 "" "")
6728 (match_operand 1 "" ""))]
6731 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
6735 (define_insn "*sibcall_br"
6736 [(call (mem:QI (reg SIBCALL_REGNUM))
6737 (match_operand 0 "const_int_operand" "n"))]
6738 "SIBLING_CALL_P (insn)
6739 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
6741 [(set_attr "op_type" "RR")
6742 (set_attr "type" "branch")
6743 (set_attr "atype" "agen")])
6745 (define_insn "*sibcall_brc"
6746 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6747 (match_operand 1 "const_int_operand" "n"))]
6748 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6750 [(set_attr "op_type" "RI")
6751 (set_attr "type" "branch")])
6753 (define_insn "*sibcall_brcl"
6754 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6755 (match_operand 1 "const_int_operand" "n"))]
6756 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6758 [(set_attr "op_type" "RIL")
6759 (set_attr "type" "branch")])
6762 ; sibcall_value patterns
6765 (define_expand "sibcall_value"
6766 [(set (match_operand 0 "" "")
6767 (call (match_operand 1 "" "")
6768 (match_operand 2 "" "")))]
6771 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
6775 (define_insn "*sibcall_value_br"
6776 [(set (match_operand 0 "" "")
6777 (call (mem:QI (reg SIBCALL_REGNUM))
6778 (match_operand 1 "const_int_operand" "n")))]
6779 "SIBLING_CALL_P (insn)
6780 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
6782 [(set_attr "op_type" "RR")
6783 (set_attr "type" "branch")
6784 (set_attr "atype" "agen")])
6786 (define_insn "*sibcall_value_brc"
6787 [(set (match_operand 0 "" "")
6788 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6789 (match_operand 2 "const_int_operand" "n")))]
6790 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6792 [(set_attr "op_type" "RI")
6793 (set_attr "type" "branch")])
6795 (define_insn "*sibcall_value_brcl"
6796 [(set (match_operand 0 "" "")
6797 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6798 (match_operand 2 "const_int_operand" "n")))]
6799 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6801 [(set_attr "op_type" "RIL")
6802 (set_attr "type" "branch")])
6806 ; call instruction pattern(s).
6809 (define_expand "call"
6810 [(call (match_operand 0 "" "")
6811 (match_operand 1 "" ""))
6812 (use (match_operand 2 "" ""))]
6815 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
6816 gen_rtx_REG (Pmode, RETURN_REGNUM));
6820 (define_insn "*bras"
6821 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6822 (match_operand 1 "const_int_operand" "n"))
6823 (clobber (match_operand 2 "register_operand" "=r"))]
6824 "!SIBLING_CALL_P (insn)
6825 && TARGET_SMALL_EXEC
6826 && GET_MODE (operands[2]) == Pmode"
6828 [(set_attr "op_type" "RI")
6829 (set_attr "type" "jsr")])
6831 (define_insn "*brasl"
6832 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6833 (match_operand 1 "const_int_operand" "n"))
6834 (clobber (match_operand 2 "register_operand" "=r"))]
6835 "!SIBLING_CALL_P (insn)
6837 && GET_MODE (operands[2]) == Pmode"
6839 [(set_attr "op_type" "RIL")
6840 (set_attr "type" "jsr")])
6842 (define_insn "*basr"
6843 [(call (mem:QI (match_operand 0 "address_operand" "U"))
6844 (match_operand 1 "const_int_operand" "n"))
6845 (clobber (match_operand 2 "register_operand" "=r"))]
6846 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
6848 if (get_attr_op_type (insn) == OP_TYPE_RR)
6849 return "basr\t%2,%0";
6851 return "bas\t%2,%a0";
6853 [(set (attr "op_type")
6854 (if_then_else (match_operand 0 "register_operand" "")
6855 (const_string "RR") (const_string "RX")))
6856 (set_attr "type" "jsr")
6857 (set_attr "atype" "agen")])
6860 ; call_value instruction pattern(s).
6863 (define_expand "call_value"
6864 [(set (match_operand 0 "" "")
6865 (call (match_operand 1 "" "")
6866 (match_operand 2 "" "")))
6867 (use (match_operand 3 "" ""))]
6870 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
6871 gen_rtx_REG (Pmode, RETURN_REGNUM));
6875 (define_insn "*bras_r"
6876 [(set (match_operand 0 "" "")
6877 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6878 (match_operand:SI 2 "const_int_operand" "n")))
6879 (clobber (match_operand 3 "register_operand" "=r"))]
6880 "!SIBLING_CALL_P (insn)
6881 && TARGET_SMALL_EXEC
6882 && GET_MODE (operands[3]) == Pmode"
6884 [(set_attr "op_type" "RI")
6885 (set_attr "type" "jsr")])
6887 (define_insn "*brasl_r"
6888 [(set (match_operand 0 "" "")
6889 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6890 (match_operand 2 "const_int_operand" "n")))
6891 (clobber (match_operand 3 "register_operand" "=r"))]
6892 "!SIBLING_CALL_P (insn)
6894 && GET_MODE (operands[3]) == Pmode"
6896 [(set_attr "op_type" "RIL")
6897 (set_attr "type" "jsr")])
6899 (define_insn "*basr_r"
6900 [(set (match_operand 0 "" "")
6901 (call (mem:QI (match_operand 1 "address_operand" "U"))
6902 (match_operand 2 "const_int_operand" "n")))
6903 (clobber (match_operand 3 "register_operand" "=r"))]
6904 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
6906 if (get_attr_op_type (insn) == OP_TYPE_RR)
6907 return "basr\t%3,%1";
6909 return "bas\t%3,%a1";
6911 [(set (attr "op_type")
6912 (if_then_else (match_operand 1 "register_operand" "")
6913 (const_string "RR") (const_string "RX")))
6914 (set_attr "type" "jsr")
6915 (set_attr "atype" "agen")])
6918 ;;- Thread-local storage support.
6921 (define_expand "get_tp_64"
6922 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
6926 (define_expand "get_tp_31"
6927 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
6931 (define_expand "set_tp_64"
6932 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
6933 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
6937 (define_expand "set_tp_31"
6938 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
6939 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
6943 (define_insn "*set_tp"
6944 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
6947 [(set_attr "type" "none")
6948 (set_attr "length" "0")])
6950 (define_insn "*tls_load_64"
6951 [(set (match_operand:DI 0 "register_operand" "=d")
6952 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
6953 (match_operand:DI 2 "" "")]
6957 [(set_attr "op_type" "RXE")])
6959 (define_insn "*tls_load_31"
6960 [(set (match_operand:SI 0 "register_operand" "=d,d")
6961 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
6962 (match_operand:SI 2 "" "")]
6968 [(set_attr "op_type" "RX,RXY")])
6970 (define_insn "*bras_tls"
6971 [(set (match_operand 0 "" "")
6972 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6973 (match_operand 2 "const_int_operand" "n")))
6974 (clobber (match_operand 3 "register_operand" "=r"))
6975 (use (match_operand 4 "" ""))]
6976 "!SIBLING_CALL_P (insn)
6977 && TARGET_SMALL_EXEC
6978 && GET_MODE (operands[3]) == Pmode"
6980 [(set_attr "op_type" "RI")
6981 (set_attr "type" "jsr")])
6983 (define_insn "*brasl_tls"
6984 [(set (match_operand 0 "" "")
6985 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6986 (match_operand 2 "const_int_operand" "n")))
6987 (clobber (match_operand 3 "register_operand" "=r"))
6988 (use (match_operand 4 "" ""))]
6989 "!SIBLING_CALL_P (insn)
6991 && GET_MODE (operands[3]) == Pmode"
6993 [(set_attr "op_type" "RIL")
6994 (set_attr "type" "jsr")])
6996 (define_insn "*basr_tls"
6997 [(set (match_operand 0 "" "")
6998 (call (mem:QI (match_operand 1 "address_operand" "U"))
6999 (match_operand 2 "const_int_operand" "n")))
7000 (clobber (match_operand 3 "register_operand" "=r"))
7001 (use (match_operand 4 "" ""))]
7002 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7004 if (get_attr_op_type (insn) == OP_TYPE_RR)
7005 return "basr\t%3,%1%J4";
7007 return "bas\t%3,%a1%J4";
7009 [(set (attr "op_type")
7010 (if_then_else (match_operand 1 "register_operand" "")
7011 (const_string "RR") (const_string "RX")))
7012 (set_attr "type" "jsr")
7013 (set_attr "atype" "agen")])
7016 ;;- Atomic operations
7020 ; memory barrier pattern.
7023 (define_expand "memory_barrier"
7024 [(set (mem:BLK (match_dup 0))
7025 (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
7028 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
7029 MEM_VOLATILE_P (operands[0]) = 1;
7032 (define_insn "*memory_barrier"
7033 [(set (match_operand:BLK 0 "" "")
7034 (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
7037 [(set_attr "op_type" "RR")])
7040 ; compare and swap patterns.
7043 (define_expand "sync_compare_and_swap<mode>"
7045 [(set (match_operand:TDSI 0 "register_operand" "")
7046 (match_operand:TDSI 1 "memory_operand" ""))
7048 (unspec_volatile:TDSI
7050 (match_operand:TDSI 2 "register_operand" "")
7051 (match_operand:TDSI 3 "register_operand" "")]
7053 (set (reg:CCZ1 CC_REGNUM)
7054 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7057 (define_expand "sync_compare_and_swap<mode>"
7059 [(set (match_operand:HQI 0 "register_operand" "")
7060 (match_operand:HQI 1 "memory_operand" ""))
7062 (unspec_volatile:HQI
7064 (match_operand:HQI 2 "general_operand" "")
7065 (match_operand:HQI 3 "general_operand" "")]
7067 (set (reg:CCZ1 CC_REGNUM)
7068 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7070 "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
7071 operands[2], operands[3]); DONE;")
7073 (define_expand "sync_compare_and_swap_cc<mode>"
7075 [(set (match_operand:TDSI 0 "register_operand" "")
7076 (match_operand:TDSI 1 "memory_operand" ""))
7078 (unspec_volatile:TDSI
7080 (match_operand:TDSI 2 "register_operand" "")
7081 (match_operand:TDSI 3 "register_operand" "")]
7084 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7087 /* Emulate compare. */
7088 operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM);
7089 s390_compare_op0 = operands[1];
7090 s390_compare_op1 = operands[2];
7091 s390_compare_emitted = operands[4];
7094 (define_insn "*sync_compare_and_swap<mode>"
7095 [(set (match_operand:DP 0 "register_operand" "=r")
7096 (match_operand:DP 1 "memory_operand" "+Q"))
7100 (match_operand:DP 2 "register_operand" "0")
7101 (match_operand:DP 3 "register_operand" "r")]
7103 (set (reg:CCZ1 CC_REGNUM)
7104 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7106 "cds<tg>\t%0,%3,%S1"
7107 [(set_attr "op_type" "RS<TE>")
7108 (set_attr "type" "sem")])
7110 (define_insn "*sync_compare_and_swap<mode>"
7111 [(set (match_operand:GPR 0 "register_operand" "=r")
7112 (match_operand:GPR 1 "memory_operand" "+Q"))
7114 (unspec_volatile:GPR
7116 (match_operand:GPR 2 "register_operand" "0")
7117 (match_operand:GPR 3 "register_operand" "r")]
7119 (set (reg:CCZ1 CC_REGNUM)
7120 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7123 [(set_attr "op_type" "RS<E>")
7124 (set_attr "type" "sem")])
7128 ; Other atomic instruction patterns.
7131 (define_expand "sync_lock_test_and_set<mode>"
7132 [(match_operand:HQI 0 "register_operand")
7133 (match_operand:HQI 1 "memory_operand")
7134 (match_operand:HQI 2 "general_operand")]
7136 "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
7137 operands[2], false); DONE;")
7139 (define_expand "sync_<atomic><mode>"
7140 [(set (match_operand:HQI 0 "memory_operand")
7141 (ATOMIC:HQI (match_dup 0)
7142 (match_operand:HQI 1 "general_operand")))]
7144 "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
7145 operands[1], false); DONE;")
7147 (define_expand "sync_old_<atomic><mode>"
7148 [(set (match_operand:HQI 0 "register_operand")
7149 (match_operand:HQI 1 "memory_operand"))
7151 (ATOMIC:HQI (match_dup 1)
7152 (match_operand:HQI 2 "general_operand")))]
7154 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
7155 operands[2], false); DONE;")
7157 (define_expand "sync_new_<atomic><mode>"
7158 [(set (match_operand:HQI 0 "register_operand")
7159 (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
7160 (match_operand:HQI 2 "general_operand")))
7161 (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
7163 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
7164 operands[2], true); DONE;")
7167 ;;- Miscellaneous instructions.
7171 ; allocate stack instruction pattern(s).
7174 (define_expand "allocate_stack"
7175 [(match_operand 0 "general_operand" "")
7176 (match_operand 1 "general_operand" "")]
7179 rtx temp = gen_reg_rtx (Pmode);
7181 emit_move_insn (temp, s390_back_chain_rtx ());
7182 anti_adjust_stack (operands[1]);
7183 emit_move_insn (s390_back_chain_rtx (), temp);
7185 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7191 ; setjmp instruction pattern.
7194 (define_expand "builtin_setjmp_receiver"
7195 [(match_operand 0 "" "")]
7198 emit_insn (s390_load_got ());
7199 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
7203 ;; These patterns say how to save and restore the stack pointer. We need not
7204 ;; save the stack pointer at function level since we are careful to
7205 ;; preserve the backchain. At block level, we have to restore the backchain
7206 ;; when we restore the stack pointer.
7208 ;; For nonlocal gotos, we must save both the stack pointer and its
7209 ;; backchain and restore both. Note that in the nonlocal case, the
7210 ;; save area is a memory location.
7212 (define_expand "save_stack_function"
7213 [(match_operand 0 "general_operand" "")
7214 (match_operand 1 "general_operand" "")]
7218 (define_expand "restore_stack_function"
7219 [(match_operand 0 "general_operand" "")
7220 (match_operand 1 "general_operand" "")]
7224 (define_expand "restore_stack_block"
7225 [(match_operand 0 "register_operand" "")
7226 (match_operand 1 "register_operand" "")]
7229 rtx temp = gen_reg_rtx (Pmode);
7231 emit_move_insn (temp, s390_back_chain_rtx ());
7232 emit_move_insn (operands[0], operands[1]);
7233 emit_move_insn (s390_back_chain_rtx (), temp);
7238 (define_expand "save_stack_nonlocal"
7239 [(match_operand 0 "memory_operand" "")
7240 (match_operand 1 "register_operand" "")]
7243 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7244 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7246 /* Copy the backchain to the first word, sp to the second and the
7247 literal pool base to the third. */
7249 if (TARGET_BACKCHAIN)
7251 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
7252 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
7255 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
7256 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
7261 (define_expand "restore_stack_nonlocal"
7262 [(match_operand 0 "register_operand" "")
7263 (match_operand 1 "memory_operand" "")]
7266 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7267 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7268 rtx temp = NULL_RTX;
7270 /* Restore the backchain from the first word, sp from the second and the
7271 literal pool base from the third. */
7273 if (TARGET_BACKCHAIN)
7274 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
7276 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
7277 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
7280 emit_move_insn (s390_back_chain_rtx (), temp);
7282 emit_insn (gen_rtx_USE (VOIDmode, base));
7286 (define_expand "exception_receiver"
7290 s390_set_has_landing_pad_p (true);
7295 ; nop instruction pattern(s).
7302 [(set_attr "op_type" "RR")])
7306 ; Special literal pool access instruction pattern(s).
7309 (define_insn "*pool_entry"
7310 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
7311 UNSPECV_POOL_ENTRY)]
7314 enum machine_mode mode = GET_MODE (PATTERN (insn));
7315 unsigned int align = GET_MODE_BITSIZE (mode);
7316 s390_output_pool_entry (operands[0], mode, align);
7319 [(set (attr "length")
7320 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
7322 (define_insn "pool_align"
7323 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
7324 UNSPECV_POOL_ALIGN)]
7327 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7329 (define_insn "pool_section_start"
7330 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
7333 [(set_attr "length" "0")])
7335 (define_insn "pool_section_end"
7336 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
7339 [(set_attr "length" "0")])
7341 (define_insn "main_base_31_small"
7342 [(set (match_operand 0 "register_operand" "=a")
7343 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7344 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7346 [(set_attr "op_type" "RR")
7347 (set_attr "type" "la")])
7349 (define_insn "main_base_31_large"
7350 [(set (match_operand 0 "register_operand" "=a")
7351 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
7352 (set (pc) (label_ref (match_operand 2 "" "")))]
7353 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7355 [(set_attr "op_type" "RI")])
7357 (define_insn "main_base_64"
7358 [(set (match_operand 0 "register_operand" "=a")
7359 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7360 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7362 [(set_attr "op_type" "RIL")
7363 (set_attr "type" "larl")])
7365 (define_insn "main_pool"
7366 [(set (match_operand 0 "register_operand" "=a")
7367 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
7368 "GET_MODE (operands[0]) == Pmode"
7373 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
7374 (const_string "larl") (const_string "la")))])
7376 (define_insn "reload_base_31"
7377 [(set (match_operand 0 "register_operand" "=a")
7378 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7379 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7380 "basr\t%0,0\;la\t%0,%1-.(%0)"
7381 [(set_attr "length" "6")
7382 (set_attr "type" "la")])
7384 (define_insn "reload_base_64"
7385 [(set (match_operand 0 "register_operand" "=a")
7386 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7387 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7389 [(set_attr "op_type" "RIL")
7390 (set_attr "type" "larl")])
7393 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
7398 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7401 ;; Insns related to generating the function prologue and epilogue.
7405 (define_expand "prologue"
7406 [(use (const_int 0))]
7408 "s390_emit_prologue (); DONE;")
7410 (define_expand "epilogue"
7411 [(use (const_int 1))]
7413 "s390_emit_epilogue (false); DONE;")
7415 (define_expand "sibcall_epilogue"
7416 [(use (const_int 0))]
7418 "s390_emit_epilogue (true); DONE;")
7420 (define_insn "*return"
7422 (use (match_operand 0 "register_operand" "a"))]
7423 "GET_MODE (operands[0]) == Pmode"
7425 [(set_attr "op_type" "RR")
7426 (set_attr "type" "jsr")
7427 (set_attr "atype" "agen")])
7430 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
7431 ;; pointer. This is used for compatibility.
7433 (define_expand "ptr_extend"
7434 [(set (match_operand:DI 0 "register_operand" "=r")
7435 (match_operand:SI 1 "register_operand" "r"))]
7438 emit_insn (gen_anddi3 (operands[0],
7439 gen_lowpart (DImode, operands[1]),
7440 GEN_INT (0x7fffffff)));
7444 ;; Instruction definition to expand eh_return macro to support
7445 ;; swapping in special linkage return addresses.
7447 (define_expand "eh_return"
7448 [(use (match_operand 0 "register_operand" ""))]
7451 s390_emit_tpf_eh_return (operands[0]);
7456 ; Stack Protector Patterns
7459 (define_expand "stack_protect_set"
7460 [(set (match_operand 0 "memory_operand" "")
7461 (match_operand 1 "memory_operand" ""))]
7464 #ifdef TARGET_THREAD_SSP_OFFSET
7466 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7467 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7470 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
7472 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
7477 (define_insn "stack_protect_set<mode>"
7478 [(set (match_operand:DSI 0 "memory_operand" "=Q")
7479 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
7481 "mvc\t%O0(%G0,%R0),%S1"
7482 [(set_attr "op_type" "SS")])
7484 (define_expand "stack_protect_test"
7485 [(set (reg:CC CC_REGNUM)
7486 (compare (match_operand 0 "memory_operand" "")
7487 (match_operand 1 "memory_operand" "")))
7488 (match_operand 2 "" "")]
7491 #ifdef TARGET_THREAD_SSP_OFFSET
7493 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7494 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7496 s390_compare_op0 = operands[0];
7497 s390_compare_op1 = operands[1];
7498 s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM);
7501 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
7503 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
7505 emit_jump_insn (gen_beq (operands[2]));
7510 (define_insn "stack_protect_test<mode>"
7511 [(set (reg:CCZ CC_REGNUM)
7512 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
7513 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
7515 "clc\t%O0(%G0,%R0),%S1"
7516 [(set_attr "op_type" "SS")])