1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987-2020 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
38 #include "cfgcleanup.h"
41 #include "tree-pass.h"
43 #include "function-abi.h"
45 static int reload_cse_noop_set_p (rtx
);
46 static bool reload_cse_simplify (rtx_insn
*, rtx
);
47 static void reload_cse_regs_1 (void);
48 static int reload_cse_simplify_set (rtx
, rtx_insn
*);
49 static int reload_cse_simplify_operands (rtx_insn
*, rtx
);
51 static void reload_combine (void);
52 static void reload_combine_note_use (rtx
*, rtx_insn
*, int, rtx
);
53 static void reload_combine_note_store (rtx
, const_rtx
, void *);
55 static bool reload_cse_move2add (rtx_insn
*);
56 static void move2add_note_store (rtx
, const_rtx
, void *);
58 /* Call cse / combine like post-reload optimization phases.
59 FIRST is the first instruction. */
62 reload_cse_regs (rtx_insn
*first ATTRIBUTE_UNUSED
)
67 moves_converted
= reload_cse_move2add (first
);
68 if (flag_expensive_optimizations
)
76 /* See whether a single set SET is a noop. */
78 reload_cse_noop_set_p (rtx set
)
80 if (cselib_reg_set_mode (SET_DEST (set
)) != GET_MODE (SET_DEST (set
)))
83 return rtx_equal_for_cselib_p (SET_DEST (set
), SET_SRC (set
));
86 /* Try to simplify INSN. Return true if the CFG may have changed. */
88 reload_cse_simplify (rtx_insn
*insn
, rtx testreg
)
90 rtx body
= PATTERN (insn
);
91 basic_block insn_bb
= BLOCK_FOR_INSN (insn
);
92 unsigned insn_bb_succs
= EDGE_COUNT (insn_bb
->succs
);
94 /* If NO_FUNCTION_CSE has been set by the target, then we should not try
95 to cse function calls. */
96 if (NO_FUNCTION_CSE
&& CALL_P (insn
))
99 if (GET_CODE (body
) == SET
)
103 /* Simplify even if we may think it is a no-op.
104 We may think a memory load of a value smaller than WORD_SIZE
105 is redundant because we haven't taken into account possible
106 implicit extension. reload_cse_simplify_set() will bring
107 this out, so it's safer to simplify before we delete. */
108 count
+= reload_cse_simplify_set (body
, insn
);
110 if (!count
&& reload_cse_noop_set_p (body
))
112 if (check_for_inc_dec (insn
))
113 delete_insn_and_edges (insn
);
114 /* We're done with this insn. */
119 apply_change_group ();
121 reload_cse_simplify_operands (insn
, testreg
);
123 else if (GET_CODE (body
) == PARALLEL
)
127 rtx value
= NULL_RTX
;
129 /* Registers mentioned in the clobber list for an asm cannot be reused
130 within the body of the asm. Invalidate those registers now so that
131 we don't try to substitute values for them. */
132 if (asm_noperands (body
) >= 0)
134 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
136 rtx part
= XVECEXP (body
, 0, i
);
137 if (GET_CODE (part
) == CLOBBER
&& REG_P (XEXP (part
, 0)))
138 cselib_invalidate_rtx (XEXP (part
, 0));
142 /* If every action in a PARALLEL is a noop, we can delete
143 the entire PARALLEL. */
144 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
146 rtx part
= XVECEXP (body
, 0, i
);
147 if (GET_CODE (part
) == SET
)
149 if (! reload_cse_noop_set_p (part
))
151 if (REG_P (SET_DEST (part
))
152 && REG_FUNCTION_VALUE_P (SET_DEST (part
)))
156 value
= SET_DEST (part
);
159 else if (GET_CODE (part
) != CLOBBER
&& GET_CODE (part
) != USE
)
165 if (check_for_inc_dec (insn
))
166 delete_insn_and_edges (insn
);
167 /* We're done with this insn. */
171 /* It's not a no-op, but we can try to simplify it. */
172 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
173 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
174 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
177 apply_change_group ();
179 reload_cse_simplify_operands (insn
, testreg
);
183 return (EDGE_COUNT (insn_bb
->succs
) != insn_bb_succs
);
186 /* Do a very simple CSE pass over the hard registers.
188 This function detects no-op moves where we happened to assign two
189 different pseudo-registers to the same hard register, and then
190 copied one to the other. Reload will generate a useless
191 instruction copying a register to itself.
193 This function also detects cases where we load a value from memory
194 into two different registers, and (if memory is more expensive than
195 registers) changes it to simply copy the first register into the
198 Another optimization is performed that scans the operands of each
199 instruction to see whether the value is already available in a
200 hard register. It then replaces the operand with the hard register
201 if possible, much like an optional reload would. */
204 reload_cse_regs_1 (void)
206 bool cfg_changed
= false;
209 rtx testreg
= gen_rtx_REG (word_mode
, LAST_VIRTUAL_REGISTER
+ 1);
211 cselib_init (CSELIB_RECORD_MEMORY
);
212 init_alias_analysis ();
214 FOR_EACH_BB_FN (bb
, cfun
)
215 FOR_BB_INSNS (bb
, insn
)
218 cfg_changed
|= reload_cse_simplify (insn
, testreg
);
220 cselib_process_insn (insn
);
224 end_alias_analysis ();
230 /* Try to simplify a single SET instruction. SET is the set pattern.
231 INSN is the instruction it came from.
232 This function only handles one case: if we set a register to a value
233 which is not a register, we try to find that value in some other register
234 and change the set into a register copy. */
237 reload_cse_simplify_set (rtx set
, rtx_insn
*insn
)
245 struct elt_loc_list
*l
;
246 enum rtx_code extend_op
= UNKNOWN
;
247 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
249 dreg
= true_regnum (SET_DEST (set
));
254 if (side_effects_p (src
) || true_regnum (src
) >= 0)
257 dclass
= REGNO_REG_CLASS (dreg
);
259 /* When replacing a memory with a register, we need to honor assumptions
260 that combine made wrt the contents of sign bits. We'll do this by
261 generating an extend instruction instead of a reg->reg copy. Thus
262 the destination must be a register that we can widen. */
264 && (extend_op
= load_extend_op (GET_MODE (src
))) != UNKNOWN
265 && !REG_P (SET_DEST (set
)))
268 val
= cselib_lookup (src
, GET_MODE (SET_DEST (set
)), 0, VOIDmode
);
272 /* If memory loads are cheaper than register copies, don't change them. */
274 old_cost
= memory_move_cost (GET_MODE (src
), dclass
, true);
275 else if (REG_P (src
))
276 old_cost
= register_move_cost (GET_MODE (src
),
277 REGNO_REG_CLASS (REGNO (src
)), dclass
);
279 old_cost
= set_src_cost (src
, GET_MODE (SET_DEST (set
)), speed
);
281 for (l
= val
->locs
; l
; l
= l
->next
)
283 rtx this_rtx
= l
->loc
;
286 if (CONSTANT_P (this_rtx
) && ! references_value_p (this_rtx
, 0))
288 if (extend_op
!= UNKNOWN
)
292 if (!CONST_SCALAR_INT_P (this_rtx
))
298 result
= wide_int::from (rtx_mode_t (this_rtx
,
300 BITS_PER_WORD
, UNSIGNED
);
303 result
= wide_int::from (rtx_mode_t (this_rtx
,
305 BITS_PER_WORD
, SIGNED
);
310 this_rtx
= immed_wide_int_const (result
, word_mode
);
313 this_cost
= set_src_cost (this_rtx
, GET_MODE (SET_DEST (set
)), speed
);
315 else if (REG_P (this_rtx
))
317 if (extend_op
!= UNKNOWN
)
319 this_rtx
= gen_rtx_fmt_e (extend_op
, word_mode
, this_rtx
);
320 this_cost
= set_src_cost (this_rtx
, word_mode
, speed
);
323 this_cost
= register_move_cost (GET_MODE (this_rtx
),
324 REGNO_REG_CLASS (REGNO (this_rtx
)),
330 /* If equal costs, prefer registers over anything else. That
331 tends to lead to smaller instructions on some machines. */
332 if (this_cost
< old_cost
333 || (this_cost
== old_cost
335 && !REG_P (SET_SRC (set
))))
337 if (extend_op
!= UNKNOWN
338 && REG_CAN_CHANGE_MODE_P (REGNO (SET_DEST (set
)),
339 GET_MODE (SET_DEST (set
)), word_mode
))
341 rtx wide_dest
= gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
)));
342 ORIGINAL_REGNO (wide_dest
) = ORIGINAL_REGNO (SET_DEST (set
));
343 validate_change (insn
, &SET_DEST (set
), wide_dest
, 1);
346 validate_unshare_change (insn
, &SET_SRC (set
), this_rtx
, 1);
347 old_cost
= this_cost
, did_change
= 1;
354 /* Try to replace operands in INSN with equivalent values that are already
355 in registers. This can be viewed as optional reloading.
357 For each non-register operand in the insn, see if any hard regs are
358 known to be equivalent to that operand. Record the alternatives which
359 can accept these hard registers. Among all alternatives, select the
360 ones which are better or equal to the one currently matching, where
361 "better" is in terms of '?' and '!' constraints. Among the remaining
362 alternatives, select the one which replaces most operands with
366 reload_cse_simplify_operands (rtx_insn
*insn
, rtx testreg
)
370 /* For each operand, all registers that are equivalent to it. */
371 HARD_REG_SET equiv_regs
[MAX_RECOG_OPERANDS
];
373 const char *constraints
[MAX_RECOG_OPERANDS
];
375 /* Vector recording how bad an alternative is. */
376 int *alternative_reject
;
377 /* Vector recording how many registers can be introduced by choosing
379 int *alternative_nregs
;
380 /* Array of vectors recording, for each operand and each alternative,
381 which hard register to substitute, or -1 if the operand should be
383 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
384 /* Array of alternatives, sorted in order of decreasing desirability. */
385 int *alternative_order
;
387 extract_constrain_insn (insn
);
389 if (recog_data
.n_alternatives
== 0 || recog_data
.n_operands
== 0)
392 alternative_reject
= XALLOCAVEC (int, recog_data
.n_alternatives
);
393 alternative_nregs
= XALLOCAVEC (int, recog_data
.n_alternatives
);
394 alternative_order
= XALLOCAVEC (int, recog_data
.n_alternatives
);
395 memset (alternative_reject
, 0, recog_data
.n_alternatives
* sizeof (int));
396 memset (alternative_nregs
, 0, recog_data
.n_alternatives
* sizeof (int));
398 /* For each operand, find out which regs are equivalent. */
399 for (i
= 0; i
< recog_data
.n_operands
; i
++)
402 struct elt_loc_list
*l
;
405 CLEAR_HARD_REG_SET (equiv_regs
[i
]);
407 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
408 right, so avoid the problem here. Similarly NOTE_INSN_DELETED_LABEL.
409 Likewise if we have a constant and the insn pattern doesn't tell us
411 if (LABEL_P (recog_data
.operand
[i
])
412 || (NOTE_P (recog_data
.operand
[i
])
413 && NOTE_KIND (recog_data
.operand
[i
]) == NOTE_INSN_DELETED_LABEL
)
414 || (CONSTANT_P (recog_data
.operand
[i
])
415 && recog_data
.operand_mode
[i
] == VOIDmode
))
418 op
= recog_data
.operand
[i
];
419 if (MEM_P (op
) && load_extend_op (GET_MODE (op
)) != UNKNOWN
)
421 rtx set
= single_set (insn
);
423 /* We might have multiple sets, some of which do implicit
424 extension. Punt on this for now. */
427 /* If the destination is also a MEM or a STRICT_LOW_PART, no
429 Also, if there is an explicit extension, we don't have to
430 worry about an implicit one. */
431 else if (MEM_P (SET_DEST (set
))
432 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
433 || GET_CODE (SET_SRC (set
)) == ZERO_EXTEND
434 || GET_CODE (SET_SRC (set
)) == SIGN_EXTEND
)
435 ; /* Continue ordinary processing. */
436 /* If the register cannot change mode to word_mode, it follows that
437 it cannot have been used in word_mode. */
438 else if (REG_P (SET_DEST (set
))
439 && !REG_CAN_CHANGE_MODE_P (REGNO (SET_DEST (set
)),
440 GET_MODE (SET_DEST (set
)),
442 ; /* Continue ordinary processing. */
443 /* If this is a straight load, make the extension explicit. */
444 else if (REG_P (SET_DEST (set
))
445 && recog_data
.n_operands
== 2
446 && SET_SRC (set
) == op
447 && SET_DEST (set
) == recog_data
.operand
[1-i
])
449 validate_change (insn
, recog_data
.operand_loc
[i
],
450 gen_rtx_fmt_e (load_extend_op (GET_MODE (op
)),
453 validate_change (insn
, recog_data
.operand_loc
[1-i
],
454 gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
))),
456 if (! apply_change_group ())
458 return reload_cse_simplify_operands (insn
, testreg
);
461 /* ??? There might be arithmetic operations with memory that are
462 safe to optimize, but is it worth the trouble? */
466 if (side_effects_p (op
))
468 v
= cselib_lookup (op
, recog_data
.operand_mode
[i
], 0, VOIDmode
);
472 for (l
= v
->locs
; l
; l
= l
->next
)
474 SET_HARD_REG_BIT (equiv_regs
[i
], REGNO (l
->loc
));
477 alternative_mask preferred
= get_preferred_alternatives (insn
);
478 for (i
= 0; i
< recog_data
.n_operands
; i
++)
484 op_alt_regno
[i
] = XALLOCAVEC (int, recog_data
.n_alternatives
);
485 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
486 op_alt_regno
[i
][j
] = -1;
488 p
= constraints
[i
] = recog_data
.constraints
[i
];
489 mode
= recog_data
.operand_mode
[i
];
491 /* Add the reject values for each alternative given by the constraints
500 alternative_reject
[j
] += 3;
502 alternative_reject
[j
] += 300;
505 /* We won't change operands which are already registers. We
506 also don't want to modify output operands. */
507 regno
= true_regnum (recog_data
.operand
[i
]);
509 || constraints
[i
][0] == '='
510 || constraints
[i
][0] == '+')
513 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
515 enum reg_class rclass
= NO_REGS
;
517 if (! TEST_HARD_REG_BIT (equiv_regs
[i
], regno
))
520 set_mode_and_regno (testreg
, mode
, regno
);
522 /* We found a register equal to this operand. Now look for all
523 alternatives that can accept this register and have not been
524 assigned a register they can use yet. */
534 rclass
= reg_class_subunion
[rclass
][GENERAL_REGS
];
539 = (reg_class_subunion
541 [reg_class_for_constraint (lookup_constraint (p
))]);
545 /* See if REGNO fits this alternative, and set it up as the
546 replacement register if we don't have one for this
547 alternative yet and the operand being replaced is not
548 a cheap CONST_INT. */
549 if (op_alt_regno
[i
][j
] == -1
550 && TEST_BIT (preferred
, j
)
551 && reg_fits_class_p (testreg
, rclass
, 0, mode
)
552 && (!CONST_INT_P (recog_data
.operand
[i
])
553 || (set_src_cost (recog_data
.operand
[i
], mode
,
554 optimize_bb_for_speed_p
555 (BLOCK_FOR_INSN (insn
)))
556 > set_src_cost (testreg
, mode
,
557 optimize_bb_for_speed_p
558 (BLOCK_FOR_INSN (insn
))))))
560 alternative_nregs
[j
]++;
561 op_alt_regno
[i
][j
] = regno
;
567 p
+= CONSTRAINT_LEN (c
, p
);
575 /* Record all alternatives which are better or equal to the currently
576 matching one in the alternative_order array. */
577 for (i
= j
= 0; i
< recog_data
.n_alternatives
; i
++)
578 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
579 alternative_order
[j
++] = i
;
580 recog_data
.n_alternatives
= j
;
582 /* Sort it. Given a small number of alternatives, a dumb algorithm
583 won't hurt too much. */
584 for (i
= 0; i
< recog_data
.n_alternatives
- 1; i
++)
587 int best_reject
= alternative_reject
[alternative_order
[i
]];
588 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
590 for (j
= i
+ 1; j
< recog_data
.n_alternatives
; j
++)
592 int this_reject
= alternative_reject
[alternative_order
[j
]];
593 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
595 if (this_reject
< best_reject
596 || (this_reject
== best_reject
&& this_nregs
> best_nregs
))
599 best_reject
= this_reject
;
600 best_nregs
= this_nregs
;
604 std::swap (alternative_order
[best
], alternative_order
[i
]);
607 /* Substitute the operands as determined by op_alt_regno for the best
609 j
= alternative_order
[0];
611 for (i
= 0; i
< recog_data
.n_operands
; i
++)
613 machine_mode mode
= recog_data
.operand_mode
[i
];
614 if (op_alt_regno
[i
][j
] == -1)
617 validate_change (insn
, recog_data
.operand_loc
[i
],
618 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
621 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
623 int op
= recog_data
.dup_num
[i
];
624 machine_mode mode
= recog_data
.operand_mode
[op
];
626 if (op_alt_regno
[op
][j
] == -1)
629 validate_change (insn
, recog_data
.dup_loc
[i
],
630 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
633 return apply_change_group ();
636 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
638 This code might also be useful when reload gave up on reg+reg addressing
639 because of clashes between the return register and INDEX_REG_CLASS. */
641 /* The maximum number of uses of a register we can keep track of to
642 replace them with reg+reg addressing. */
643 #define RELOAD_COMBINE_MAX_USES 16
645 /* Describes a recorded use of a register. */
648 /* The insn where a register has been used. */
650 /* Points to the memory reference enclosing the use, if any, NULL_RTX
653 /* Location of the register within INSN. */
655 /* The reverse uid of the insn. */
659 /* If the register is used in some unknown fashion, USE_INDEX is negative.
660 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
661 indicates where it is first set or clobbered.
662 Otherwise, USE_INDEX is the index of the last encountered use of the
663 register (which is first among these we have seen since we scan backwards).
664 USE_RUID indicates the first encountered, i.e. last, of these uses.
665 If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
666 with a constant offset; OFFSET contains this constant in that case.
667 STORE_RUID is always meaningful if we only want to use a value in a
668 register in a different place: it denotes the next insn in the insn
669 stream (i.e. the last encountered) that sets or clobbers the register.
670 REAL_STORE_RUID is similar, but clobbers are ignored when updating it.
671 EXPR is the expression used when storing the register. */
674 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
680 bool all_offsets_match
;
682 } reg_state
[FIRST_PSEUDO_REGISTER
];
684 /* Reverse linear uid. This is increased in reload_combine while scanning
685 the instructions from last to first. It is used to set last_label_ruid
686 and the store_ruid / use_ruid fields in reg_state. */
687 static int reload_combine_ruid
;
689 /* The RUID of the last label we encountered in reload_combine. */
690 static int last_label_ruid
;
692 /* The RUID of the last jump we encountered in reload_combine. */
693 static int last_jump_ruid
;
695 /* The register numbers of the first and last index register. A value of
696 -1 in LAST_INDEX_REG indicates that we've previously computed these
697 values and found no suitable index registers. */
698 static int first_index_reg
= -1;
699 static int last_index_reg
;
701 #define LABEL_LIVE(LABEL) \
702 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
704 /* Subroutine of reload_combine_split_ruids, called to fix up a single
705 ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */
708 reload_combine_split_one_ruid (int *pruid
, int split_ruid
)
710 if (*pruid
> split_ruid
)
714 /* Called when we insert a new insn in a position we've already passed in
715 the scan. Examine all our state, increasing all ruids that are higher
716 than SPLIT_RUID by one in order to make room for a new insn. */
719 reload_combine_split_ruids (int split_ruid
)
723 reload_combine_split_one_ruid (&reload_combine_ruid
, split_ruid
);
724 reload_combine_split_one_ruid (&last_label_ruid
, split_ruid
);
725 reload_combine_split_one_ruid (&last_jump_ruid
, split_ruid
);
727 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
729 int j
, idx
= reg_state
[i
].use_index
;
730 reload_combine_split_one_ruid (®_state
[i
].use_ruid
, split_ruid
);
731 reload_combine_split_one_ruid (®_state
[i
].store_ruid
, split_ruid
);
732 reload_combine_split_one_ruid (®_state
[i
].real_store_ruid
,
736 for (j
= idx
; j
< RELOAD_COMBINE_MAX_USES
; j
++)
738 reload_combine_split_one_ruid (®_state
[i
].reg_use
[j
].ruid
,
744 /* Called when we are about to rescan a previously encountered insn with
745 reload_combine_note_use after modifying some part of it. This clears all
746 information about uses in that particular insn. */
749 reload_combine_purge_insn_uses (rtx_insn
*insn
)
753 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
755 int j
, k
, idx
= reg_state
[i
].use_index
;
758 j
= k
= RELOAD_COMBINE_MAX_USES
;
761 if (reg_state
[i
].reg_use
[j
].insn
!= insn
)
765 reg_state
[i
].reg_use
[k
] = reg_state
[i
].reg_use
[j
];
768 reg_state
[i
].use_index
= k
;
772 /* Called when we need to forget about all uses of REGNO after an insn
773 which is identified by RUID. */
776 reload_combine_purge_reg_uses_after_ruid (unsigned regno
, int ruid
)
778 int j
, k
, idx
= reg_state
[regno
].use_index
;
781 j
= k
= RELOAD_COMBINE_MAX_USES
;
784 if (reg_state
[regno
].reg_use
[j
].ruid
>= ruid
)
788 reg_state
[regno
].reg_use
[k
] = reg_state
[regno
].reg_use
[j
];
791 reg_state
[regno
].use_index
= k
;
794 /* Find the use of REGNO with the ruid that is highest among those
795 lower than RUID_LIMIT, and return it if it is the only use of this
796 reg in the insn. Return NULL otherwise. */
798 static struct reg_use
*
799 reload_combine_closest_single_use (unsigned regno
, int ruid_limit
)
801 int i
, best_ruid
= 0;
802 int use_idx
= reg_state
[regno
].use_index
;
803 struct reg_use
*retval
;
808 for (i
= use_idx
; i
< RELOAD_COMBINE_MAX_USES
; i
++)
810 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
811 int this_ruid
= use
->ruid
;
812 if (this_ruid
>= ruid_limit
)
814 if (this_ruid
> best_ruid
)
816 best_ruid
= this_ruid
;
819 else if (this_ruid
== best_ruid
)
822 if (last_label_ruid
>= best_ruid
)
827 /* After we've moved an add insn, fix up any debug insns that occur
828 between the old location of the add and the new location. REG is
829 the destination register of the add insn; REPLACEMENT is the
830 SET_SRC of the add. FROM and TO specify the range in which we
831 should make this change on debug insns. */
834 fixup_debug_insns (rtx reg
, rtx replacement
, rtx_insn
*from
, rtx_insn
*to
)
837 for (insn
= from
; insn
!= to
; insn
= NEXT_INSN (insn
))
841 if (!DEBUG_BIND_INSN_P (insn
))
844 t
= INSN_VAR_LOCATION_LOC (insn
);
845 t
= simplify_replace_rtx (t
, reg
, replacement
);
846 validate_change (insn
, &INSN_VAR_LOCATION_LOC (insn
), t
, 0);
850 /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG
851 with SRC in the insn described by USE, taking costs into account. Return
852 true if we made the replacement. */
855 try_replace_in_use (struct reg_use
*use
, rtx reg
, rtx src
)
857 rtx_insn
*use_insn
= use
->insn
;
858 rtx mem
= use
->containing_mem
;
859 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn
));
863 addr_space_t as
= MEM_ADDR_SPACE (mem
);
864 rtx oldaddr
= XEXP (mem
, 0);
865 rtx newaddr
= NULL_RTX
;
866 int old_cost
= address_cost (oldaddr
, GET_MODE (mem
), as
, speed
);
869 newaddr
= simplify_replace_rtx (oldaddr
, reg
, src
);
870 if (memory_address_addr_space_p (GET_MODE (mem
), newaddr
, as
))
872 XEXP (mem
, 0) = newaddr
;
873 new_cost
= address_cost (newaddr
, GET_MODE (mem
), as
, speed
);
874 XEXP (mem
, 0) = oldaddr
;
875 if (new_cost
<= old_cost
876 && validate_change (use_insn
,
877 &XEXP (mem
, 0), newaddr
, 0))
883 rtx new_set
= single_set (use_insn
);
885 && REG_P (SET_DEST (new_set
))
886 && GET_CODE (SET_SRC (new_set
)) == PLUS
887 && REG_P (XEXP (SET_SRC (new_set
), 0))
888 && CONSTANT_P (XEXP (SET_SRC (new_set
), 1)))
891 machine_mode mode
= GET_MODE (SET_DEST (new_set
));
892 int old_cost
= set_src_cost (SET_SRC (new_set
), mode
, speed
);
894 gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set
), 0), reg
));
895 new_src
= simplify_replace_rtx (SET_SRC (new_set
), reg
, src
);
897 if (set_src_cost (new_src
, mode
, speed
) <= old_cost
898 && validate_change (use_insn
, &SET_SRC (new_set
),
906 /* Called by reload_combine when scanning INSN. This function tries to detect
907 patterns where a constant is added to a register, and the result is used
909 Return true if no further processing is needed on INSN; false if it wasn't
910 recognized and should be handled normally. */
913 reload_combine_recognize_const_pattern (rtx_insn
*insn
)
915 int from_ruid
= reload_combine_ruid
;
916 rtx set
, pat
, reg
, src
, addreg
;
920 rtx_insn
*add_moved_after_insn
= NULL
;
921 int add_moved_after_ruid
= 0;
922 int clobbered_regno
= -1;
924 set
= single_set (insn
);
928 reg
= SET_DEST (set
);
931 || REG_NREGS (reg
) != 1
932 || GET_MODE (reg
) != Pmode
933 || reg
== stack_pointer_rtx
)
938 /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
939 uses of REG1 inside an address, or inside another add insn. If
940 possible and profitable, merge the addition into subsequent
942 if (GET_CODE (src
) != PLUS
943 || !REG_P (XEXP (src
, 0))
944 || !CONSTANT_P (XEXP (src
, 1)))
947 addreg
= XEXP (src
, 0);
948 must_move_add
= rtx_equal_p (reg
, addreg
);
950 pat
= PATTERN (insn
);
951 if (must_move_add
&& set
!= pat
)
953 /* We have to be careful when moving the add; apart from the
954 single_set there may also be clobbers. Recognize one special
955 case, that of one clobber alongside the set (likely a clobber
956 of the CC register). */
957 gcc_assert (GET_CODE (PATTERN (insn
)) == PARALLEL
);
958 if (XVECLEN (pat
, 0) != 2 || XVECEXP (pat
, 0, 0) != set
959 || GET_CODE (XVECEXP (pat
, 0, 1)) != CLOBBER
960 || !REG_P (XEXP (XVECEXP (pat
, 0, 1), 0)))
962 clobbered_regno
= REGNO (XEXP (XVECEXP (pat
, 0, 1), 0));
967 use
= reload_combine_closest_single_use (regno
, from_ruid
);
970 /* Start the search for the next use from here. */
971 from_ruid
= use
->ruid
;
973 if (use
&& GET_MODE (*use
->usep
) == Pmode
)
975 bool delete_add
= false;
976 rtx_insn
*use_insn
= use
->insn
;
977 int use_ruid
= use
->ruid
;
979 /* Avoid moving the add insn past a jump. */
980 if (must_move_add
&& use_ruid
<= last_jump_ruid
)
983 /* If the add clobbers another hard reg in parallel, don't move
984 it past a real set of this hard reg. */
985 if (must_move_add
&& clobbered_regno
>= 0
986 && reg_state
[clobbered_regno
].real_store_ruid
>= use_ruid
)
989 /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */
990 if (HAVE_cc0
&& must_move_add
&& sets_cc0_p (PATTERN (use_insn
)))
993 gcc_assert (reg_state
[regno
].store_ruid
<= use_ruid
);
994 /* Avoid moving a use of ADDREG past a point where it is stored. */
995 if (reg_state
[REGNO (addreg
)].store_ruid
> use_ruid
)
998 /* We also must not move the addition past an insn that sets
999 the same register, unless we can combine two add insns. */
1000 if (must_move_add
&& reg_state
[regno
].store_ruid
== use_ruid
)
1002 if (use
->containing_mem
== NULL_RTX
)
1008 if (try_replace_in_use (use
, reg
, src
))
1010 reload_combine_purge_insn_uses (use_insn
);
1011 reload_combine_note_use (&PATTERN (use_insn
), use_insn
,
1012 use_ruid
, NULL_RTX
);
1016 fixup_debug_insns (reg
, src
, insn
, use_insn
);
1022 add_moved_after_insn
= use_insn
;
1023 add_moved_after_ruid
= use_ruid
;
1028 /* If we get here, we couldn't handle this use. */
1034 if (!must_move_add
|| add_moved_after_insn
== NULL_RTX
)
1035 /* Process the add normally. */
1038 fixup_debug_insns (reg
, src
, insn
, add_moved_after_insn
);
1040 reorder_insns (insn
, insn
, add_moved_after_insn
);
1041 reload_combine_purge_reg_uses_after_ruid (regno
, add_moved_after_ruid
);
1042 reload_combine_split_ruids (add_moved_after_ruid
- 1);
1043 reload_combine_note_use (&PATTERN (insn
), insn
,
1044 add_moved_after_ruid
, NULL_RTX
);
1045 reg_state
[regno
].store_ruid
= add_moved_after_ruid
;
1050 /* Called by reload_combine when scanning INSN. Try to detect a pattern we
1051 can handle and improve. Return true if no further processing is needed on
1052 INSN; false if it wasn't recognized and should be handled normally. */
1055 reload_combine_recognize_pattern (rtx_insn
*insn
)
1059 set
= single_set (insn
);
1060 if (set
== NULL_RTX
)
1063 reg
= SET_DEST (set
);
1064 src
= SET_SRC (set
);
1065 if (!REG_P (reg
) || REG_NREGS (reg
) != 1)
1068 unsigned int regno
= REGNO (reg
);
1069 machine_mode mode
= GET_MODE (reg
);
1071 if (reg_state
[regno
].use_index
< 0
1072 || reg_state
[regno
].use_index
>= RELOAD_COMBINE_MAX_USES
)
1075 for (int i
= reg_state
[regno
].use_index
;
1076 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1078 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
1079 if (GET_MODE (*use
->usep
) != mode
)
1081 /* Don't try to adjust (use (REGX)). */
1082 if (GET_CODE (PATTERN (use
->insn
)) == USE
1083 && &XEXP (PATTERN (use
->insn
), 0) == use
->usep
)
1087 /* Look for (set (REGX) (CONST_INT))
1088 (set (REGX) (PLUS (REGX) (REGY)))
1090 ... (MEM (REGX)) ...
1092 (set (REGZ) (CONST_INT))
1094 ... (MEM (PLUS (REGZ) (REGY)))... .
1096 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
1097 and that we know all uses of REGX before it dies.
1098 Also, explicitly check that REGX != REGY; our life information
1099 does not yet show whether REGY changes in this insn. */
1101 if (GET_CODE (src
) == PLUS
1102 && reg_state
[regno
].all_offsets_match
1103 && last_index_reg
!= -1
1104 && REG_P (XEXP (src
, 1))
1105 && rtx_equal_p (XEXP (src
, 0), reg
)
1106 && !rtx_equal_p (XEXP (src
, 1), reg
)
1107 && last_label_ruid
< reg_state
[regno
].use_ruid
)
1109 rtx base
= XEXP (src
, 1);
1110 rtx_insn
*prev
= prev_nonnote_nondebug_insn (insn
);
1111 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
1112 rtx index_reg
= NULL_RTX
;
1113 rtx reg_sum
= NULL_RTX
;
1116 /* Now we need to set INDEX_REG to an index register (denoted as
1117 REGZ in the illustration above) and REG_SUM to the expression
1118 register+register that we want to use to substitute uses of REG
1119 (typically in MEMs) with. First check REG and BASE for being
1120 index registers; we can use them even if they are not dead. */
1121 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
1122 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
1130 /* Otherwise, look for a free index register. Since we have
1131 checked above that neither REG nor BASE are index registers,
1132 if we find anything at all, it will be different from these
1134 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
1136 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], i
)
1137 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
1138 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
1139 && (crtl
->abi
->clobbers_full_reg_p (i
)
1140 || df_regs_ever_live_p (i
))
1141 && (!frame_pointer_needed
|| i
!= HARD_FRAME_POINTER_REGNUM
)
1142 && !fixed_regs
[i
] && !global_regs
[i
]
1143 && hard_regno_nregs (i
, GET_MODE (reg
)) == 1
1144 && targetm
.hard_regno_scratch_ok (i
))
1146 index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
1147 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
1153 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
1154 (REGY), i.e. BASE, is not clobbered before the last use we'll
1158 && CONST_INT_P (SET_SRC (prev_set
))
1159 && rtx_equal_p (SET_DEST (prev_set
), reg
)
1160 && (reg_state
[REGNO (base
)].store_ruid
1161 <= reg_state
[regno
].use_ruid
))
1163 /* Change destination register and, if necessary, the constant
1164 value in PREV, the constant loading instruction. */
1165 validate_change (prev
, &SET_DEST (prev_set
), index_reg
, 1);
1166 if (reg_state
[regno
].offset
!= const0_rtx
)
1169 = trunc_int_for_mode (UINTVAL (SET_SRC (prev_set
))
1170 + UINTVAL (reg_state
[regno
].offset
),
1171 GET_MODE (index_reg
));
1172 validate_change (prev
, &SET_SRC (prev_set
), GEN_INT (c
), 1);
1175 /* Now for every use of REG that we have recorded, replace REG
1177 for (i
= reg_state
[regno
].use_index
;
1178 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1179 validate_unshare_change (reg_state
[regno
].reg_use
[i
].insn
,
1180 reg_state
[regno
].reg_use
[i
].usep
,
1181 /* Each change must have its own
1185 if (apply_change_group ())
1187 struct reg_use
*lowest_ruid
= NULL
;
1189 /* For every new use of REG_SUM, we have to record the use
1190 of BASE therein, i.e. operand 1. */
1191 for (i
= reg_state
[regno
].use_index
;
1192 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1194 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
1195 reload_combine_note_use (&XEXP (*use
->usep
, 1), use
->insn
,
1196 use
->ruid
, use
->containing_mem
);
1197 if (lowest_ruid
== NULL
|| use
->ruid
< lowest_ruid
->ruid
)
1201 fixup_debug_insns (reg
, reg_sum
, insn
, lowest_ruid
->insn
);
1203 /* Delete the reg-reg addition. */
1206 if (reg_state
[regno
].offset
!= const0_rtx
1207 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
1209 && remove_reg_equal_equiv_notes (prev
))
1210 df_notes_rescan (prev
);
1212 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
1221 reload_combine (void)
1223 rtx_insn
*insn
, *prev
;
1226 int min_labelno
, n_labels
;
1227 HARD_REG_SET ever_live_at_start
, *label_live
;
1229 /* To avoid wasting too much time later searching for an index register,
1230 determine the minimum and maximum index register numbers. */
1231 if (INDEX_REG_CLASS
== NO_REGS
)
1232 last_index_reg
= -1;
1233 else if (first_index_reg
== -1 && last_index_reg
== 0)
1235 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1236 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], r
))
1238 if (first_index_reg
== -1)
1239 first_index_reg
= r
;
1244 /* If no index register is available, we can quit now. Set LAST_INDEX_REG
1245 to -1 so we'll know to quit early the next time we get here. */
1246 if (first_index_reg
== -1)
1248 last_index_reg
= -1;
1253 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
1254 information is a bit fuzzy immediately after reload, but it's
1255 still good enough to determine which registers are live at a jump
1257 min_labelno
= get_first_label_num ();
1258 n_labels
= max_label_num () - min_labelno
;
1259 label_live
= XNEWVEC (HARD_REG_SET
, n_labels
);
1260 CLEAR_HARD_REG_SET (ever_live_at_start
);
1262 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
1264 insn
= BB_HEAD (bb
);
1268 bitmap live_in
= df_get_live_in (bb
);
1270 REG_SET_TO_HARD_REG_SET (live
, live_in
);
1271 compute_use_by_pseudos (&live
, live_in
);
1272 LABEL_LIVE (insn
) = live
;
1273 ever_live_at_start
|= live
;
1277 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
1278 last_label_ruid
= last_jump_ruid
= reload_combine_ruid
= 0;
1279 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1281 reg_state
[r
].store_ruid
= 0;
1282 reg_state
[r
].real_store_ruid
= 0;
1284 reg_state
[r
].use_index
= -1;
1286 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1289 for (insn
= get_last_insn (); insn
; insn
= prev
)
1291 bool control_flow_insn
;
1294 prev
= PREV_INSN (insn
);
1296 /* We cannot do our optimization across labels. Invalidating all the use
1297 information we have would be costly, so we just note where the label
1298 is and then later disable any optimization that would cross it. */
1300 last_label_ruid
= reload_combine_ruid
;
1301 else if (BARRIER_P (insn
))
1303 /* Crossing a barrier resets all the use information. */
1304 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1305 if (! fixed_regs
[r
])
1306 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1308 else if (INSN_P (insn
) && volatile_insn_p (PATTERN (insn
)))
1309 /* Optimizations across insns being marked as volatile must be
1310 prevented. All the usage information is invalidated
1312 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1314 && reg_state
[r
].use_index
!= RELOAD_COMBINE_MAX_USES
)
1315 reg_state
[r
].use_index
= -1;
1317 if (! NONDEBUG_INSN_P (insn
))
1320 reload_combine_ruid
++;
1322 control_flow_insn
= control_flow_insn_p (insn
);
1323 if (control_flow_insn
)
1324 last_jump_ruid
= reload_combine_ruid
;
1326 if (reload_combine_recognize_const_pattern (insn
)
1327 || reload_combine_recognize_pattern (insn
))
1330 note_stores (insn
, reload_combine_note_store
, NULL
);
1335 HARD_REG_SET used_regs
= insn_callee_abi (insn
).full_reg_clobbers ();
1337 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1338 if (TEST_HARD_REG_BIT (used_regs
, r
))
1340 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1341 reg_state
[r
].store_ruid
= reload_combine_ruid
;
1344 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
1345 link
= XEXP (link
, 1))
1347 rtx setuse
= XEXP (link
, 0);
1348 rtx usage_rtx
= XEXP (setuse
, 0);
1350 if (GET_CODE (setuse
) == USE
&& REG_P (usage_rtx
))
1352 unsigned int end_regno
= END_REGNO (usage_rtx
);
1353 for (unsigned int i
= REGNO (usage_rtx
); i
< end_regno
; ++i
)
1354 reg_state
[i
].use_index
= -1;
1359 if (control_flow_insn
&& !ANY_RETURN_P (PATTERN (insn
)))
1361 /* Non-spill registers might be used at the call destination in
1362 some unknown fashion, so we have to mark the unknown use. */
1365 if ((condjump_p (insn
) || condjump_in_parallel_p (insn
))
1366 && JUMP_LABEL (insn
))
1368 if (ANY_RETURN_P (JUMP_LABEL (insn
)))
1371 live
= &LABEL_LIVE (JUMP_LABEL (insn
));
1374 live
= &ever_live_at_start
;
1377 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1378 if (TEST_HARD_REG_BIT (*live
, r
))
1379 reg_state
[r
].use_index
= -1;
1382 reload_combine_note_use (&PATTERN (insn
), insn
, reload_combine_ruid
,
1385 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
1387 if (REG_NOTE_KIND (note
) == REG_INC
&& REG_P (XEXP (note
, 0)))
1389 int regno
= REGNO (XEXP (note
, 0));
1390 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
1391 reg_state
[regno
].real_store_ruid
= reload_combine_ruid
;
1392 reg_state
[regno
].use_index
= -1;
1400 /* Check if DST is a register or a subreg of a register; if it is,
1401 update store_ruid, real_store_ruid and use_index in the reg_state
1402 structure accordingly. Called via note_stores from reload_combine. */
1405 reload_combine_note_store (rtx dst
, const_rtx set
, void *data ATTRIBUTE_UNUSED
)
1409 machine_mode mode
= GET_MODE (dst
);
1411 if (GET_CODE (dst
) == SUBREG
)
1413 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
1414 GET_MODE (SUBREG_REG (dst
)),
1417 dst
= SUBREG_REG (dst
);
1420 /* Some targets do argument pushes without adding REG_INC notes. */
1424 dst
= XEXP (dst
, 0);
1425 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
1426 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
1427 || GET_CODE (dst
) == PRE_MODIFY
|| GET_CODE (dst
) == POST_MODIFY
)
1429 unsigned int end_regno
= END_REGNO (XEXP (dst
, 0));
1430 for (unsigned int i
= REGNO (XEXP (dst
, 0)); i
< end_regno
; ++i
)
1432 /* We could probably do better, but for now mark the register
1433 as used in an unknown fashion and set/clobbered at this
1435 reg_state
[i
].use_index
= -1;
1436 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1437 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1446 regno
+= REGNO (dst
);
1448 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
1449 careful with registers / register parts that are not full words.
1450 Similarly for ZERO_EXTRACT. */
1451 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
1452 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
1454 for (i
= end_hard_regno (mode
, regno
) - 1; i
>= regno
; i
--)
1456 reg_state
[i
].use_index
= -1;
1457 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1458 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1463 for (i
= end_hard_regno (mode
, regno
) - 1; i
>= regno
; i
--)
1465 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1466 if (GET_CODE (set
) == SET
)
1467 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1468 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1473 /* XP points to a piece of rtl that has to be checked for any uses of
1475 *XP is the pattern of INSN, or a part of it.
1476 Called from reload_combine, and recursively by itself. */
1478 reload_combine_note_use (rtx
*xp
, rtx_insn
*insn
, int ruid
, rtx containing_mem
)
1481 enum rtx_code code
= x
->code
;
1484 rtx offset
= const0_rtx
; /* For the REG case below. */
1489 if (REG_P (SET_DEST (x
)))
1491 reload_combine_note_use (&SET_SRC (x
), insn
, ruid
, NULL_RTX
);
1497 /* If this is the USE of a return value, we can't change it. */
1498 if (REG_P (XEXP (x
, 0)) && REG_FUNCTION_VALUE_P (XEXP (x
, 0)))
1500 /* Mark the return register as used in an unknown fashion. */
1501 rtx reg
= XEXP (x
, 0);
1502 unsigned int end_regno
= END_REGNO (reg
);
1503 for (unsigned int regno
= REGNO (reg
); regno
< end_regno
; ++regno
)
1504 reg_state
[regno
].use_index
= -1;
1510 if (REG_P (SET_DEST (x
)))
1512 /* No spurious CLOBBERs of pseudo registers may remain. */
1513 gcc_assert (REGNO (SET_DEST (x
)) < FIRST_PSEUDO_REGISTER
);
1519 /* We are interested in (plus (reg) (const_int)) . */
1520 if (!REG_P (XEXP (x
, 0))
1521 || !CONST_INT_P (XEXP (x
, 1)))
1523 offset
= XEXP (x
, 1);
1528 int regno
= REGNO (x
);
1532 /* No spurious USEs of pseudo registers may remain. */
1533 gcc_assert (regno
< FIRST_PSEUDO_REGISTER
);
1535 nregs
= REG_NREGS (x
);
1537 /* We can't substitute into multi-hard-reg uses. */
1540 while (--nregs
>= 0)
1541 reg_state
[regno
+ nregs
].use_index
= -1;
1545 /* We may be called to update uses in previously seen insns.
1546 Don't add uses beyond the last store we saw. */
1547 if (ruid
< reg_state
[regno
].store_ruid
)
1550 /* If this register is already used in some unknown fashion, we
1552 If we decrement the index from zero to -1, we can't store more
1553 uses, so this register becomes used in an unknown fashion. */
1554 use_index
= --reg_state
[regno
].use_index
;
1558 if (use_index
== RELOAD_COMBINE_MAX_USES
- 1)
1560 /* This is the first use of this register we have seen since we
1561 marked it as dead. */
1562 reg_state
[regno
].offset
= offset
;
1563 reg_state
[regno
].all_offsets_match
= true;
1564 reg_state
[regno
].use_ruid
= ruid
;
1568 if (reg_state
[regno
].use_ruid
> ruid
)
1569 reg_state
[regno
].use_ruid
= ruid
;
1571 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
1572 reg_state
[regno
].all_offsets_match
= false;
1575 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
1576 reg_state
[regno
].reg_use
[use_index
].ruid
= ruid
;
1577 reg_state
[regno
].reg_use
[use_index
].containing_mem
= containing_mem
;
1578 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
1590 /* Recursively process the components of X. */
1591 fmt
= GET_RTX_FORMAT (code
);
1592 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1595 reload_combine_note_use (&XEXP (x
, i
), insn
, ruid
, containing_mem
);
1596 else if (fmt
[i
] == 'E')
1598 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1599 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
, ruid
,
1605 /* See if we can reduce the cost of a constant by replacing a move
1606 with an add. We track situations in which a register is set to a
1607 constant or to a register plus a constant. */
1608 /* We cannot do our optimization across labels. Invalidating all the
1609 information about register contents we have would be costly, so we
1610 use move2add_last_label_luid to note where the label is and then
1611 later disable any optimization that would cross it.
1612 reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n]
1613 are only valid if reg_set_luid[n] is greater than
1614 move2add_last_label_luid.
1615 For a set that established a new (potential) base register with
1616 non-constant value, we use move2add_luid from the place where the
1617 setting insn is encountered; registers based off that base then
1618 get the same reg_set_luid. Constants all get
1619 move2add_last_label_luid + 1 as their reg_set_luid. */
1620 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
1622 /* If reg_base_reg[n] is negative, register n has been set to
1623 reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n].
1624 If reg_base_reg[n] is non-negative, register n has been set to the
1625 sum of reg_offset[n] and the value of register reg_base_reg[n]
1626 before reg_set_luid[n], calculated in mode reg_mode[n] .
1627 For multi-hard-register registers, all but the first one are
1628 recorded as BLKmode in reg_mode. Setting reg_mode to VOIDmode
1629 marks it as invalid. */
1630 static HOST_WIDE_INT reg_offset
[FIRST_PSEUDO_REGISTER
];
1631 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
1632 static rtx reg_symbol_ref
[FIRST_PSEUDO_REGISTER
];
1633 static machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
1635 /* move2add_luid is linearly increased while scanning the instructions
1636 from first to last. It is used to set reg_set_luid in
1637 reload_cse_move2add and move2add_note_store. */
1638 static int move2add_luid
;
1640 /* move2add_last_label_luid is set whenever a label is found. Labels
1641 invalidate all previously collected reg_offset data. */
1642 static int move2add_last_label_luid
;
1644 /* ??? We don't know how zero / sign extension is handled, hence we
1645 can't go from a narrower to a wider mode. */
1646 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
1647 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
1648 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
1649 && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE)))
1651 /* Record that REG is being set to a value with the mode of REG. */
1654 move2add_record_mode (rtx reg
)
1657 machine_mode mode
= GET_MODE (reg
);
1659 if (GET_CODE (reg
) == SUBREG
)
1661 regno
= subreg_regno (reg
);
1662 nregs
= subreg_nregs (reg
);
1664 else if (REG_P (reg
))
1666 regno
= REGNO (reg
);
1667 nregs
= REG_NREGS (reg
);
1671 for (int i
= nregs
- 1; i
> 0; i
--)
1672 reg_mode
[regno
+ i
] = BLKmode
;
1673 reg_mode
[regno
] = mode
;
1676 /* Record that REG is being set to the sum of SYM and OFF. */
1679 move2add_record_sym_value (rtx reg
, rtx sym
, rtx off
)
1681 int regno
= REGNO (reg
);
1683 move2add_record_mode (reg
);
1684 reg_set_luid
[regno
] = move2add_luid
;
1685 reg_base_reg
[regno
] = -1;
1686 reg_symbol_ref
[regno
] = sym
;
1687 reg_offset
[regno
] = INTVAL (off
);
1690 /* Check if REGNO contains a valid value in MODE. */
1693 move2add_valid_value_p (int regno
, scalar_int_mode mode
)
1695 if (reg_set_luid
[regno
] <= move2add_last_label_luid
)
1698 if (mode
!= reg_mode
[regno
])
1700 scalar_int_mode old_mode
;
1701 if (!is_a
<scalar_int_mode
> (reg_mode
[regno
], &old_mode
)
1702 || !MODES_OK_FOR_MOVE2ADD (mode
, old_mode
))
1704 /* The value loaded into regno in reg_mode[regno] is also valid in
1705 mode after truncation only if (REG:mode regno) is the lowpart of
1706 (REG:reg_mode[regno] regno). Now, for big endian, the starting
1707 regno of the lowpart might be different. */
1708 poly_int64 s_off
= subreg_lowpart_offset (mode
, old_mode
);
1709 s_off
= subreg_regno_offset (regno
, old_mode
, s_off
, mode
);
1710 if (maybe_ne (s_off
, 0))
1711 /* We could in principle adjust regno, check reg_mode[regno] to be
1712 BLKmode, and return s_off to the caller (vs. -1 for failure),
1713 but we currently have no callers that could make use of this
1718 for (int i
= end_hard_regno (mode
, regno
) - 1; i
> regno
; i
--)
1719 if (reg_mode
[i
] != BLKmode
)
1724 /* This function is called with INSN that sets REG (of mode MODE)
1725 to (SYM + OFF), while REG is known to already have value (SYM + offset).
1726 This function tries to change INSN into an add instruction
1727 (set (REG) (plus (REG) (OFF - offset))) using the known value.
1728 It also updates the information about REG's known value.
1729 Return true if we made a change. */
1732 move2add_use_add2_insn (scalar_int_mode mode
, rtx reg
, rtx sym
, rtx off
,
1735 rtx pat
= PATTERN (insn
);
1736 rtx src
= SET_SRC (pat
);
1737 int regno
= REGNO (reg
);
1738 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[regno
], mode
);
1739 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1740 bool changed
= false;
1742 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1743 use (set (reg) (reg)) instead.
1744 We don't delete this insn, nor do we convert it into a
1745 note, to avoid losing register notes or the return
1746 value flag. jump2 already knows how to get rid of
1748 if (new_src
== const0_rtx
)
1750 /* If the constants are different, this is a
1751 truncation, that, if turned into (set (reg)
1752 (reg)), would be discarded. Maybe we should
1753 try a truncMN pattern? */
1754 if (INTVAL (off
) == reg_offset
[regno
])
1755 changed
= validate_change (insn
, &SET_SRC (pat
), reg
, 0);
1759 struct full_rtx_costs oldcst
, newcst
;
1760 rtx tem
= gen_rtx_PLUS (mode
, reg
, new_src
);
1762 get_full_set_rtx_cost (pat
, &oldcst
);
1763 SET_SRC (pat
) = tem
;
1764 get_full_set_rtx_cost (pat
, &newcst
);
1765 SET_SRC (pat
) = src
;
1767 if (costs_lt_p (&newcst
, &oldcst
, speed
)
1768 && have_add2_insn (reg
, new_src
))
1769 changed
= validate_change (insn
, &SET_SRC (pat
), tem
, 0);
1770 else if (sym
== NULL_RTX
&& mode
!= BImode
)
1772 scalar_int_mode narrow_mode
;
1773 FOR_EACH_MODE_UNTIL (narrow_mode
, mode
)
1775 if (have_insn_for (STRICT_LOW_PART
, narrow_mode
)
1776 && ((reg_offset
[regno
] & ~GET_MODE_MASK (narrow_mode
))
1777 == (INTVAL (off
) & ~GET_MODE_MASK (narrow_mode
))))
1779 rtx narrow_reg
= gen_lowpart_common (narrow_mode
, reg
);
1780 rtx narrow_src
= gen_int_mode (INTVAL (off
),
1783 = gen_rtx_SET (gen_rtx_STRICT_LOW_PART (VOIDmode
,
1786 get_full_set_rtx_cost (new_set
, &newcst
);
1787 if (costs_lt_p (&newcst
, &oldcst
, speed
))
1789 changed
= validate_change (insn
, &PATTERN (insn
),
1798 move2add_record_sym_value (reg
, sym
, off
);
1803 /* This function is called with INSN that sets REG (of mode MODE) to
1804 (SYM + OFF), but REG doesn't have known value (SYM + offset). This
1805 function tries to find another register which is known to already have
1806 value (SYM + offset) and change INSN into an add instruction
1807 (set (REG) (plus (the found register) (OFF - offset))) if such
1808 a register is found. It also updates the information about
1810 Return true iff we made a change. */
1813 move2add_use_add3_insn (scalar_int_mode mode
, rtx reg
, rtx sym
, rtx off
,
1816 rtx pat
= PATTERN (insn
);
1817 rtx src
= SET_SRC (pat
);
1818 int regno
= REGNO (reg
);
1820 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1822 bool changed
= false;
1823 struct full_rtx_costs oldcst
, newcst
, mincst
;
1826 init_costs_to_max (&mincst
);
1827 get_full_set_rtx_cost (pat
, &oldcst
);
1829 plus_expr
= gen_rtx_PLUS (GET_MODE (reg
), reg
, const0_rtx
);
1830 SET_SRC (pat
) = plus_expr
;
1832 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1833 if (move2add_valid_value_p (i
, mode
)
1834 && reg_base_reg
[i
] < 0
1835 && reg_symbol_ref
[i
] != NULL_RTX
1836 && rtx_equal_p (sym
, reg_symbol_ref
[i
]))
1838 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[i
],
1840 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1841 use (set (reg) (reg)) instead.
1842 We don't delete this insn, nor do we convert it into a
1843 note, to avoid losing register notes or the return
1844 value flag. jump2 already knows how to get rid of
1846 if (new_src
== const0_rtx
)
1848 init_costs_to_zero (&mincst
);
1854 XEXP (plus_expr
, 1) = new_src
;
1855 get_full_set_rtx_cost (pat
, &newcst
);
1857 if (costs_lt_p (&newcst
, &mincst
, speed
))
1864 SET_SRC (pat
) = src
;
1866 if (costs_lt_p (&mincst
, &oldcst
, speed
))
1870 tem
= gen_rtx_REG (GET_MODE (reg
), min_regno
);
1873 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[min_regno
],
1875 tem
= gen_rtx_PLUS (GET_MODE (reg
), tem
, new_src
);
1877 if (validate_change (insn
, &SET_SRC (pat
), tem
, 0))
1880 reg_set_luid
[regno
] = move2add_luid
;
1881 move2add_record_sym_value (reg
, sym
, off
);
1885 /* Convert move insns with constant inputs to additions if they are cheaper.
1886 Return true if any changes were made. */
1888 reload_cse_move2add (rtx_insn
*first
)
1892 bool changed
= false;
1894 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
1896 reg_set_luid
[i
] = 0;
1898 reg_base_reg
[i
] = 0;
1899 reg_symbol_ref
[i
] = NULL_RTX
;
1900 reg_mode
[i
] = VOIDmode
;
1903 move2add_last_label_luid
= 0;
1905 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
1911 move2add_last_label_luid
= move2add_luid
;
1912 /* We're going to increment move2add_luid twice after a
1913 label, so that we can use move2add_last_label_luid + 1 as
1914 the luid for constants. */
1918 if (! INSN_P (insn
))
1920 pat
= PATTERN (insn
);
1921 /* For simplicity, we only perform this optimization on
1922 straightforward SETs. */
1923 scalar_int_mode mode
;
1924 if (GET_CODE (pat
) == SET
1925 && REG_P (SET_DEST (pat
))
1926 && is_a
<scalar_int_mode
> (GET_MODE (SET_DEST (pat
)), &mode
))
1928 rtx reg
= SET_DEST (pat
);
1929 int regno
= REGNO (reg
);
1930 rtx src
= SET_SRC (pat
);
1932 /* Check if we have valid information on the contents of this
1933 register in the mode of REG. */
1934 if (move2add_valid_value_p (regno
, mode
)
1935 && dbg_cnt (cse2_move2add
))
1937 /* Try to transform (set (REGX) (CONST_INT A))
1939 (set (REGX) (CONST_INT B))
1941 (set (REGX) (CONST_INT A))
1943 (set (REGX) (plus (REGX) (CONST_INT B-A)))
1945 (set (REGX) (CONST_INT A))
1947 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1950 if (CONST_INT_P (src
)
1951 && reg_base_reg
[regno
] < 0
1952 && reg_symbol_ref
[regno
] == NULL_RTX
)
1954 changed
|= move2add_use_add2_insn (mode
, reg
, NULL_RTX
,
1959 /* Try to transform (set (REGX) (REGY))
1960 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1963 (set (REGX) (PLUS (REGX) (CONST_INT B)))
1966 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1968 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
1969 else if (REG_P (src
)
1970 && reg_set_luid
[regno
] == reg_set_luid
[REGNO (src
)]
1971 && reg_base_reg
[regno
] == reg_base_reg
[REGNO (src
)]
1972 && move2add_valid_value_p (REGNO (src
), mode
))
1974 rtx_insn
*next
= next_nonnote_nondebug_insn (insn
);
1977 set
= single_set (next
);
1979 && SET_DEST (set
) == reg
1980 && GET_CODE (SET_SRC (set
)) == PLUS
1981 && XEXP (SET_SRC (set
), 0) == reg
1982 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
1984 rtx src3
= XEXP (SET_SRC (set
), 1);
1985 unsigned HOST_WIDE_INT added_offset
= UINTVAL (src3
);
1986 HOST_WIDE_INT base_offset
= reg_offset
[REGNO (src
)];
1987 HOST_WIDE_INT regno_offset
= reg_offset
[regno
];
1989 gen_int_mode (added_offset
1993 bool success
= false;
1994 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1996 if (new_src
== const0_rtx
)
1997 /* See above why we create (set (reg) (reg)) here. */
1999 = validate_change (next
, &SET_SRC (set
), reg
, 0);
2002 rtx old_src
= SET_SRC (set
);
2003 struct full_rtx_costs oldcst
, newcst
;
2004 rtx tem
= gen_rtx_PLUS (mode
, reg
, new_src
);
2006 get_full_set_rtx_cost (set
, &oldcst
);
2007 SET_SRC (set
) = tem
;
2008 get_full_set_src_cost (tem
, mode
, &newcst
);
2009 SET_SRC (set
) = old_src
;
2010 costs_add_n_insns (&oldcst
, 1);
2012 if (costs_lt_p (&newcst
, &oldcst
, speed
)
2013 && have_add2_insn (reg
, new_src
))
2015 rtx newpat
= gen_rtx_SET (reg
, tem
);
2017 = validate_change (next
, &PATTERN (next
),
2025 move2add_record_mode (reg
);
2027 = trunc_int_for_mode (added_offset
+ base_offset
,
2035 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2037 (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B))))
2039 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2041 (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
2042 if ((GET_CODE (src
) == SYMBOL_REF
2043 || (GET_CODE (src
) == CONST
2044 && GET_CODE (XEXP (src
, 0)) == PLUS
2045 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == SYMBOL_REF
2046 && CONST_INT_P (XEXP (XEXP (src
, 0), 1))))
2047 && dbg_cnt (cse2_move2add
))
2051 if (GET_CODE (src
) == SYMBOL_REF
)
2058 sym
= XEXP (XEXP (src
, 0), 0);
2059 off
= XEXP (XEXP (src
, 0), 1);
2062 /* If the reg already contains the value which is sum of
2063 sym and some constant value, we can use an add2 insn. */
2064 if (move2add_valid_value_p (regno
, mode
)
2065 && reg_base_reg
[regno
] < 0
2066 && reg_symbol_ref
[regno
] != NULL_RTX
2067 && rtx_equal_p (sym
, reg_symbol_ref
[regno
]))
2068 changed
|= move2add_use_add2_insn (mode
, reg
, sym
, off
, insn
);
2070 /* Otherwise, we have to find a register whose value is sum
2071 of sym and some constant value. */
2073 changed
|= move2add_use_add3_insn (mode
, reg
, sym
, off
, insn
);
2079 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
2081 if (REG_NOTE_KIND (note
) == REG_INC
2082 && REG_P (XEXP (note
, 0)))
2084 /* Reset the information about this register. */
2085 int regno
= REGNO (XEXP (note
, 0));
2086 if (regno
< FIRST_PSEUDO_REGISTER
)
2088 move2add_record_mode (XEXP (note
, 0));
2089 reg_mode
[regno
] = VOIDmode
;
2093 note_stores (insn
, move2add_note_store
, insn
);
2095 /* If INSN is a conditional branch, we try to extract an
2096 implicit set out of it. */
2097 if (any_condjump_p (insn
))
2099 rtx cnd
= fis_get_condition (insn
);
2102 && GET_CODE (cnd
) == NE
2103 && REG_P (XEXP (cnd
, 0))
2104 && !reg_set_p (XEXP (cnd
, 0), insn
)
2105 /* The following two checks, which are also in
2106 move2add_note_store, are intended to reduce the
2107 number of calls to gen_rtx_SET to avoid memory
2108 allocation if possible. */
2109 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd
, 0)))
2110 && REG_NREGS (XEXP (cnd
, 0)) == 1
2111 && CONST_INT_P (XEXP (cnd
, 1)))
2114 gen_rtx_SET (XEXP (cnd
, 0), XEXP (cnd
, 1));
2115 move2add_note_store (SET_DEST (implicit_set
), implicit_set
, insn
);
2119 /* If this is a CALL_INSN, all call used registers are stored with
2123 function_abi callee_abi
= insn_callee_abi (insn
);
2124 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
2125 if (reg_mode
[i
] != VOIDmode
2126 && reg_mode
[i
] != BLKmode
2127 && callee_abi
.clobbers_reg_p (reg_mode
[i
], i
))
2128 /* Reset the information about this register. */
2129 reg_mode
[i
] = VOIDmode
;
2135 /* SET is a SET or CLOBBER that sets DST. DATA is the insn which
2137 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
2138 Called from reload_cse_move2add via note_stores. */
2141 move2add_note_store (rtx dst
, const_rtx set
, void *data
)
2143 rtx_insn
*insn
= (rtx_insn
*) data
;
2144 unsigned int regno
= 0;
2145 scalar_int_mode mode
;
2147 /* Some targets do argument pushes without adding REG_INC notes. */
2151 dst
= XEXP (dst
, 0);
2152 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
2153 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
)
2154 reg_mode
[REGNO (XEXP (dst
, 0))] = VOIDmode
;
2158 if (GET_CODE (dst
) == SUBREG
)
2159 regno
= subreg_regno (dst
);
2160 else if (REG_P (dst
))
2161 regno
= REGNO (dst
);
2165 if (!is_a
<scalar_int_mode
> (GET_MODE (dst
), &mode
))
2168 if (GET_CODE (set
) == SET
)
2170 rtx note
, sym
= NULL_RTX
;
2173 note
= find_reg_equal_equiv_note (insn
);
2174 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
2176 sym
= XEXP (note
, 0);
2179 else if (note
&& GET_CODE (XEXP (note
, 0)) == CONST
2180 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
2181 && GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0)) == SYMBOL_REF
2182 && CONST_INT_P (XEXP (XEXP (XEXP (note
, 0), 0), 1)))
2184 sym
= XEXP (XEXP (XEXP (note
, 0), 0), 0);
2185 off
= XEXP (XEXP (XEXP (note
, 0), 0), 1);
2188 if (sym
!= NULL_RTX
)
2190 move2add_record_sym_value (dst
, sym
, off
);
2195 if (GET_CODE (set
) == SET
2196 && GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
2197 && GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
)
2199 rtx src
= SET_SRC (set
);
2201 unsigned HOST_WIDE_INT offset
;
2204 switch (GET_CODE (src
))
2207 if (REG_P (XEXP (src
, 0)))
2209 base_reg
= XEXP (src
, 0);
2211 if (CONST_INT_P (XEXP (src
, 1)))
2212 offset
= UINTVAL (XEXP (src
, 1));
2213 else if (REG_P (XEXP (src
, 1))
2214 && move2add_valid_value_p (REGNO (XEXP (src
, 1)), mode
))
2216 if (reg_base_reg
[REGNO (XEXP (src
, 1))] < 0
2217 && reg_symbol_ref
[REGNO (XEXP (src
, 1))] == NULL_RTX
)
2218 offset
= reg_offset
[REGNO (XEXP (src
, 1))];
2219 /* Maybe the first register is known to be a
2221 else if (move2add_valid_value_p (REGNO (base_reg
), mode
)
2222 && reg_base_reg
[REGNO (base_reg
)] < 0
2223 && reg_symbol_ref
[REGNO (base_reg
)] == NULL_RTX
)
2225 offset
= reg_offset
[REGNO (base_reg
)];
2226 base_reg
= XEXP (src
, 1);
2245 /* Start tracking the register as a constant. */
2246 reg_base_reg
[regno
] = -1;
2247 reg_symbol_ref
[regno
] = NULL_RTX
;
2248 reg_offset
[regno
] = INTVAL (SET_SRC (set
));
2249 /* We assign the same luid to all registers set to constants. */
2250 reg_set_luid
[regno
] = move2add_last_label_luid
+ 1;
2251 move2add_record_mode (dst
);
2258 base_regno
= REGNO (base_reg
);
2259 /* If information about the base register is not valid, set it
2260 up as a new base register, pretending its value is known
2261 starting from the current insn. */
2262 if (!move2add_valid_value_p (base_regno
, mode
))
2264 reg_base_reg
[base_regno
] = base_regno
;
2265 reg_symbol_ref
[base_regno
] = NULL_RTX
;
2266 reg_offset
[base_regno
] = 0;
2267 reg_set_luid
[base_regno
] = move2add_luid
;
2268 gcc_assert (GET_MODE (base_reg
) == mode
);
2269 move2add_record_mode (base_reg
);
2272 /* Copy base information from our base register. */
2273 reg_set_luid
[regno
] = reg_set_luid
[base_regno
];
2274 reg_base_reg
[regno
] = reg_base_reg
[base_regno
];
2275 reg_symbol_ref
[regno
] = reg_symbol_ref
[base_regno
];
2277 /* Compute the sum of the offsets or constants. */
2279 = trunc_int_for_mode (offset
+ reg_offset
[base_regno
], mode
);
2281 move2add_record_mode (dst
);
2286 /* Invalidate the contents of the register. */
2287 move2add_record_mode (dst
);
2288 reg_mode
[regno
] = VOIDmode
;
2294 const pass_data pass_data_postreload_cse
=
2296 RTL_PASS
, /* type */
2297 "postreload", /* name */
2298 OPTGROUP_NONE
, /* optinfo_flags */
2299 TV_RELOAD_CSE_REGS
, /* tv_id */
2300 0, /* properties_required */
2301 0, /* properties_provided */
2302 0, /* properties_destroyed */
2303 0, /* todo_flags_start */
2304 TODO_df_finish
, /* todo_flags_finish */
2307 class pass_postreload_cse
: public rtl_opt_pass
2310 pass_postreload_cse (gcc::context
*ctxt
)
2311 : rtl_opt_pass (pass_data_postreload_cse
, ctxt
)
2314 /* opt_pass methods: */
2315 virtual bool gate (function
*) { return (optimize
> 0 && reload_completed
); }
2317 virtual unsigned int execute (function
*);
2319 }; // class pass_postreload_cse
2322 pass_postreload_cse::execute (function
*fun
)
2324 if (!dbg_cnt (postreload_cse
))
2327 /* Do a very simple CSE pass over just the hard registers. */
2328 reload_cse_regs (get_insns ());
2329 /* Reload_cse_regs can eliminate potentially-trapping MEMs.
2330 Remove any EH edges associated with them. */
2331 if (fun
->can_throw_non_call_exceptions
2332 && purge_all_dead_edges ())
2341 make_pass_postreload_cse (gcc::context
*ctxt
)
2343 return new pass_postreload_cse (ctxt
);