gcc/rtl.def

   1 /* This file contains the definitions and documentation for the
   2    Register Transfer Expressions (rtx's) that make up the
   3    Register Transfer Language (rtl) used in the Back End of the GNU compiler.
   4    Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004,
   5    2005, 2006
   6    Free Software Foundation, Inc.
   7
   8 This file is part of GCC.
   9
  10 GCC is free software; you can redistribute it and/or modify it under
  11 the terms of the GNU General Public License as published by the Free
  12 Software Foundation; either version 2, or (at your option) any later
  13 version.
  14
  15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  18 for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with GCC; see the file COPYING.  If not, write to the Free
  22 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  23 02110-1301, USA.  */
  24
  25
  26 /* Expression definitions and descriptions for all targets are in this file.
  27    Some will not be used for some targets.
  28
  29    The fields in the cpp macro call "DEF_RTL_EXPR()"
  30    are used to create declarations in the C source of the compiler.
  31
  32    The fields are:
  33
  34    1.  The internal name of the rtx used in the C source.
  35    It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
  36    By convention these are in UPPER_CASE.
  37
  38    2.  The name of the rtx in the external ASCII format read by
  39    read_rtx(), and printed by print_rtx().
  40    These names are stored in rtx_name[].
  41    By convention these are the internal (field 1) names in lower_case.
  42
  43    3.  The print format, and type of each rtx->u.fld[] (field) in this rtx.
  44    These formats are stored in rtx_format[].
  45    The meaning of the formats is documented in front of this array in rtl.c
  46
  47    4.  The class of the rtx.  These are stored in rtx_class and are accessed
  48    via the GET_RTX_CLASS macro.  They are defined as follows:
  49
  50      RTX_CONST_OBJ
  51          an rtx code that can be used to represent a constant object
  52          (e.g, CONST_INT)
  53      RTX_OBJ
  54          an rtx code that can be used to represent an object (e.g, REG, MEM)
  55      RTX_COMPARE
  56          an rtx code for a comparison (e.g, LT, GT)
  57      RTX_COMM_COMPARE
  58          an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
  59      RTX_UNARY
  60          an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
  61      RTX_COMM_ARITH
  62          an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
  63      RTX_TERNARY
  64          an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
  65      RTX_BIN_ARITH
  66          an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
  67      RTX_BITFIELD_OPS
  68          an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
  69      RTX_INSN
  70          an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
  71      RTX_MATCH
  72          an rtx code for something that matches in insns (e.g, MATCH_DUP)
  73      RTX_AUTOINC
  74          an rtx code for autoincrement addressing modes (e.g. POST_DEC)
  75      RTX_EXTRA
  76          everything else
  77
  78    All of the expressions that appear only in machine descriptions,
  79    not in RTL used by the compiler itself, are at the end of the file.  */
  80
  81 /* Unknown, or no such operation; the enumeration constant should have
  82    value zero.  */
  83 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
  84
  85 /* ---------------------------------------------------------------------
  86    Expressions used in constructing lists.
  87    --------------------------------------------------------------------- */
  88
  89 /* a linked list of expressions */
  90 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
  91
  92 /* a linked list of instructions.
  93    The insns are represented in print by their uids.  */
  94 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
  95
  96 /* a linked list of dependencies.
  97    The insns are represented in print by their uids.
  98    Operand 2 is the status of a dependence (see sched-int.h for more).  */
  99 DEF_RTL_EXPR(DEPS_LIST, "deps_list", "uei", RTX_EXTRA)
 100
 101 /* SEQUENCE appears in the result of a `gen_...' function
 102    for a DEFINE_EXPAND that wants to make several insns.
 103    Its elements are the bodies of the insns that should be made.
 104    `emit_insn' takes the SEQUENCE apart and makes separate insns.  */
 105 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
 106
 107 /* Refers to the address of its argument.  This is only used in alias.c.  */
 108 DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
 109
 110 /* ----------------------------------------------------------------------
 111    Expression types used for things in the instruction chain.
 112
 113    All formats must start with "iuu" to handle the chain.
 114    Each insn expression holds an rtl instruction and its semantics
 115    during back-end processing.
 116    See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
 117
 118    ---------------------------------------------------------------------- */
 119
 120 /* An instruction that cannot jump.  */
 121 DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", RTX_INSN)
 122
 123 /* An instruction that can possibly jump.
 124    Fields ( rtx->u.fld[] ) have exact same meaning as INSN's.  */
 125 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", RTX_INSN)
 126
 127 /* An instruction that can possibly call a subroutine
 128    but which will not change which instruction comes next
 129    in the current function.
 130    Field ( rtx->u.fld[9] ) is CALL_INSN_FUNCTION_USAGE.
 131    All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's.  */
 132 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", RTX_INSN)
 133
 134 /* A marker that indicates that control will not flow through.  */
 135 DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", RTX_EXTRA)
 136
 137 /* Holds a label that is followed by instructions.
 138    Operand:
 139    4: is used in jump.c for the use-count of the label.
 140    5: is used in flow.c to point to the chain of label_ref's to this label.
 141    6: is a number that is unique in the entire compilation.
 142    7: is the user-given name of the label, if any.  */
 143 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
 144
 145 #ifdef USE_MAPPED_LOCATION
 146 /* Say where in the code a source line starts, for symbol table's sake.
 147    Operand:
 148    4: unused if line number > 0, note-specific data otherwise.
 149    5: line number if > 0, enum note_insn otherwise.
 150    6: CODE_LABEL_NUMBER if line number == NOTE_INSN_DELETED_LABEL.  */
 151 #else
 152 /* Say where in the code a source line starts, for symbol table's sake.
 153    Operand:
 154    4: filename, if line number > 0, note-specific data otherwise.
 155    5: line number if > 0, enum note_insn otherwise.
 156    6: unique number if line number == note_insn_deleted_label.  */
 157 #endif
 158 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
 159
 160 /* ----------------------------------------------------------------------
 161    Top level constituents of INSN, JUMP_INSN and CALL_INSN.
 162    ---------------------------------------------------------------------- */
 163
 164 /* Conditionally execute code.
 165    Operand 0 is the condition that if true, the code is executed.
 166    Operand 1 is the code to be executed (typically a SET).
 167
 168    Semantics are that there are no side effects if the condition
 169    is false.  This pattern is created automatically by the if_convert
 170    pass run after reload or by target-specific splitters.  */
 171 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
 172
 173 /* Several operations to be done in parallel (perhaps under COND_EXEC).  */
 174 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
 175
 176 /* A string that is passed through to the assembler as input.
 177      One can obviously pass comments through by using the
 178      assembler comment syntax.
 179      These occur in an insn all by themselves as the PATTERN.
 180      They also appear inside an ASM_OPERANDS
 181      as a convenient way to hold a string.  */
 182 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", RTX_EXTRA)
 183
 184 #ifdef USE_MAPPED_LOCATION
 185 /* An assembler instruction with operands.
 186    1st operand is the instruction template.
 187    2nd operand is the constraint for the output.
 188    3rd operand is the number of the output this expression refers to.
 189      When an insn stores more than one value, a separate ASM_OPERANDS
 190      is made for each output; this integer distinguishes them.
 191    4th is a vector of values of input operands.
 192    5th is a vector of modes and constraints for the input operands.
 193      Each element is an ASM_INPUT containing a constraint string
 194      and whose mode indicates the mode of the input operand.
 195    6th is the source line number.  */
 196 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA)
 197 #else
 198 /* An assembler instruction with operands.
 199    1st operand is the instruction template.
 200    2nd operand is the constraint for the output.
 201    3rd operand is the number of the output this expression refers to.
 202      When an insn stores more than one value, a separate ASM_OPERANDS
 203      is made for each output; this integer distinguishes them.
 204    4th is a vector of values of input operands.
 205    5th is a vector of modes and constraints for the input operands.
 206      Each element is an ASM_INPUT containing a constraint string
 207      and whose mode indicates the mode of the input operand.
 208    6th is the name of the containing source file.
 209    7th is the source line number.  */
 210 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA)
 211 #endif
 212
 213 /* A machine-specific operation.
 214    1st operand is a vector of operands being used by the operation so that
 215      any needed reloads can be done.
 216    2nd operand is a unique value saying which of a number of machine-specific
 217      operations is to be performed.
 218    (Note that the vector must be the first operand because of the way that
 219    genrecog.c record positions within an insn.)
 220    This can occur all by itself in a PATTERN, as a component of a PARALLEL,
 221    or inside an expression.  */
 222 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
 223
 224 /* Similar, but a volatile operation and one which may trap.  */
 225 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
 226
 227 /* Vector of addresses, stored as full words.  */
 228 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want.  */
 229 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
 230
 231 /* Vector of address differences X0 - BASE, X1 - BASE, ...
 232    First operand is BASE; the vector contains the X's.
 233    The machine mode of this rtx says how much space to leave
 234    for each difference and is adjusted by branch shortening if
 235    CASE_VECTOR_SHORTEN_MODE is defined.
 236    The third and fourth operands store the target labels with the
 237    minimum and maximum addresses respectively.
 238    The fifth operand stores flags for use by branch shortening.
 239   Set at the start of shorten_branches:
 240    min_align: the minimum alignment for any of the target labels.
 241    base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
 242    min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
 243    max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
 244    min_after_base: true iff minimum address target label is after BASE.
 245    max_after_base: true iff maximum address target label is after BASE.
 246   Set by the actual branch shortening process:
 247    offset_unsigned: true iff offsets have to be treated as unsigned.
 248    scale: scaling that is necessary to make offsets fit into the mode.
 249
 250    The third, fourth and fifth operands are only valid when
 251    CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
 252    compilations.  */
 253
 254 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
 255
 256 /* Memory prefetch, with attributes supported on some targets.
 257    Operand 1 is the address of the memory to fetch.
 258    Operand 2 is 1 for a write access, 0 otherwise.
 259    Operand 3 is the level of temporal locality; 0 means there is no
 260    temporal locality and 1, 2, and 3 are for increasing levels of temporal
 261    locality.
 262
 263    The attributes specified by operands 2 and 3 are ignored for targets
 264    whose prefetch instructions do not support them.  */
 265 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
 266
 267 /* ----------------------------------------------------------------------
 268    At the top level of an instruction (perhaps under PARALLEL).
 269    ---------------------------------------------------------------------- */
 270
 271 /* Assignment.
 272    Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
 273    Operand 2 is the value stored there.
 274    ALL assignment must use SET.
 275    Instructions that do multiple assignments must use multiple SET,
 276    under PARALLEL.  */
 277 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
 278
 279 /* Indicate something is used in a way that we don't want to explain.
 280    For example, subroutine calls will use the register
 281    in which the static chain is passed.  */
 282 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
 283
 284 /* Indicate something is clobbered in a way that we don't want to explain.
 285    For example, subroutine calls will clobber some physical registers
 286    (the ones that are by convention not saved).  */
 287 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
 288
 289 /* Call a subroutine.
 290    Operand 1 is the address to call.
 291    Operand 2 is the number of arguments.  */
 292
 293 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
 294
 295 /* Return from a subroutine.  */
 296
 297 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
 298
 299 /* Conditional trap.
 300    Operand 1 is the condition.
 301    Operand 2 is the trap code.
 302    For an unconditional trap, make the condition (const_int 1).  */
 303 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
 304
 305 /* Placeholder for _Unwind_Resume before we know if a function call
 306    or a branch is needed.  Operand 1 is the exception region from
 307    which control is flowing.  */
 308 DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA)
 309
 310 /* ----------------------------------------------------------------------
 311    Primitive values for use in expressions.
 312    ---------------------------------------------------------------------- */
 313
 314 /* numeric integer constant */
 315 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
 316
 317 /* numeric floating point constant.
 318    Operands hold the value.  They are all 'w' and there may be from 2 to 6;
 319    see real.h.  */
 320 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
 321
 322 /* Describes a vector constant.  */
 323 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
 324
 325 /* String constant.  Used for attributes in machine descriptions and
 326    for special cases in DWARF2 debug output.  NOT used for source-
 327    language string constants.  */
 328 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
 329
 330 /* This is used to encapsulate an expression whose value is constant
 331    (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
 332    recognized as a constant operand rather than by arithmetic instructions.  */
 333
 334 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
 335
 336 /* program counter.  Ordinary jumps are represented
 337    by a SET whose first operand is (PC).  */
 338 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
 339
 340 /* Used in the cselib routines to describe a value.  Objects of this
 341    kind are only allocated in cselib.c, in an alloc pool instead of
 342    in GC memory.  The only operand of a VALUE is a cselib_val_struct.  */
 343 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
 344
 345 /* A register.  The "operand" is the register number, accessed with
 346    the REGNO macro.  If this number is less than FIRST_PSEUDO_REGISTER
 347    than a hardware register is being referred to.  The second operand
 348    holds the original register number - this will be different for a
 349    pseudo register that got turned into a hard register.  The third
 350    operand points to a reg_attrs structure.
 351    This rtx needs to have as many (or more) fields as a MEM, since we
 352    can change REG rtx's into MEMs during reload.  */
 353 DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
 354
 355 /* A scratch register.  This represents a register used only within a
 356    single insn.  It will be turned into a REG during register allocation
 357    or reload unless the constraint indicates that the register won't be
 358    needed, in which case it can remain a SCRATCH.  This code is
 359    marked as having one operand so it can be turned into a REG.  */
 360 DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
 361
 362 /* One word of a multi-word value.
 363    The first operand is the complete value; the second says which word.
 364    The WORDS_BIG_ENDIAN flag controls whether word number 0
 365    (as numbered in a SUBREG) is the most or least significant word.
 366
 367    This is also used to refer to a value in a different machine mode.
 368    For example, it can be used to refer to a SImode value as if it were
 369    Qimode, or vice versa.  Then the word number is always 0.  */
 370 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
 371
 372 /* This one-argument rtx is used for move instructions
 373    that are guaranteed to alter only the low part of a destination.
 374    Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
 375    has an unspecified effect on the high part of REG,
 376    but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
 377    is guaranteed to alter only the bits of REG that are in HImode.
 378
 379    The actual instruction used is probably the same in both cases,
 380    but the register constraints may be tighter when STRICT_LOW_PART
 381    is in use.  */
 382
 383 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
 384
 385 /* (CONCAT a b) represents the virtual concatenation of a and b
 386    to make a value that has as many bits as a and b put together.
 387    This is used for complex values.  Normally it appears only
 388    in DECL_RTLs and during RTL generation, but not in the insn chain.  */
 389 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
 390
 391 /* A memory location; operand is the address.  The second operand is the
 392    alias set to which this MEM belongs.  We use `0' instead of `w' for this
 393    field so that the field need not be specified in machine descriptions.  */
 394 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
 395
 396 /* Reference to an assembler label in the code for this function.
 397    The operand is a CODE_LABEL found in the insn chain.  */
 398 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
 399
 400 /* Reference to a named label:
 401    Operand 0: label name
 402    Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
 403    Operand 2: tree from which this symbol is derived, or null.
 404    This is either a DECL node, or some kind of constant.  */
 405 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
 406
 407 /* The condition code register is represented, in our imagination,
 408    as a register holding a value that can be compared to zero.
 409    In fact, the machine has already compared them and recorded the
 410    results; but instructions that look at the condition code
 411    pretend to be looking at the entire value and comparing it.  */
 412 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
 413
 414 /* ----------------------------------------------------------------------
 415    Expressions for operators in an rtl pattern
 416    ---------------------------------------------------------------------- */
 417
 418 /* if_then_else.  This is used in representing ordinary
 419    conditional jump instructions.
 420      Operand:
 421      0:  condition
 422      1:  then expr
 423      2:  else expr */
 424 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
 425
 426 /* Comparison, produces a condition code result.  */
 427 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
 428
 429 /* plus */
 430 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
 431
 432 /* Operand 0 minus operand 1.  */
 433 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
 434
 435 /* Minus operand 0.  */
 436 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
 437
 438 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
 439
 440 /* Operand 0 divided by operand 1.  */
 441 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
 442 /* Remainder of operand 0 divided by operand 1.  */
 443 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
 444
 445 /* Unsigned divide and remainder.  */
 446 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
 447 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
 448
 449 /* Bitwise operations.  */
 450 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
 451 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
 452 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
 453 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
 454
 455 /* Operand:
 456      0:  value to be shifted.
 457      1:  number of bits.  */
 458 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
 459 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
 460 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
 461 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
 462 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
 463
 464 /* Minimum and maximum values of two operands.  We need both signed and
 465    unsigned forms.  (We cannot use MIN for SMIN because it conflicts
 466    with a macro of the same name.)   The signed variants should be used
 467    with floating point.  Further, if both operands are zeros, or if either
 468    operand is NaN, then it is unspecified which of the two operands is
 469    returned as the result.  */
 470
 471 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
 472 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
 473 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
 474 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
 475
 476 /* These unary operations are used to represent incrementation
 477    and decrementation as they occur in memory addresses.
 478    The amount of increment or decrement are not represented
 479    because they can be understood from the machine-mode of the
 480    containing MEM.  These operations exist in only two cases:
 481    1. pushes onto the stack.
 482    2. created automatically by the life_analysis pass in flow.c.  */
 483 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
 484 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
 485 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
 486 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
 487
 488 /* These binary operations are used to represent generic address
 489    side-effects in memory addresses, except for simple incrementation
 490    or decrementation which use the above operations.  They are
 491    created automatically by the life_analysis pass in flow.c.
 492    The first operand is a REG which is used as the address.
 493    The second operand is an expression that is assigned to the
 494    register, either before (PRE_MODIFY) or after (POST_MODIFY)
 495    evaluating the address.
 496    Currently, the compiler can only handle second operands of the
 497    form (plus (reg) (reg)) and (plus (reg) (const_int)), where
 498    the first operand of the PLUS has to be the same register as
 499    the first operand of the *_MODIFY.  */
 500 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
 501 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
 502
 503 /* Comparison operations.  The ordered comparisons exist in two
 504    flavors, signed and unsigned.  */
 505 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
 506 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
 507 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
 508 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
 509 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
 510 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
 511 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
 512 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
 513 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
 514 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
 515
 516 /* Additional floating point unordered comparison flavors.  */
 517 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
 518 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
 519
 520 /* These are equivalent to unordered or ...  */
 521 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
 522 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
 523 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
 524 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
 525 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
 526
 527 /* This is an ordered NE, ie !UNEQ, ie false for NaN.  */
 528 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
 529
 530 /* Represents the result of sign-extending the sole operand.
 531    The machine modes of the operand and of the SIGN_EXTEND expression
 532    determine how much sign-extension is going on.  */
 533 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
 534
 535 /* Similar for zero-extension (such as unsigned short to int).  */
 536 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
 537
 538 /* Similar but here the operand has a wider mode.  */
 539 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
 540
 541 /* Similar for extending floating-point values (such as SFmode to DFmode).  */
 542 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
 543 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
 544
 545 /* Conversion of fixed point operand to floating point value.  */
 546 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
 547
 548 /* With fixed-point machine mode:
 549    Conversion of floating point operand to fixed point value.
 550    Value is defined only when the operand's value is an integer.
 551    With floating-point machine mode (and operand with same mode):
 552    Operand is rounded toward zero to produce an integer value
 553    represented in floating point.  */
 554 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
 555
 556 /* Conversion of unsigned fixed point operand to floating point value.  */
 557 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
 558
 559 /* With fixed-point machine mode:
 560    Conversion of floating point operand to *unsigned* fixed point value.
 561    Value is defined only when the operand's value is an integer.  */
 562 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
 563
 564 /* Absolute value */
 565 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
 566
 567 /* Square root */
 568 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
 569
 570 /* Find first bit that is set.
 571    Value is 1 + number of trailing zeros in the arg.,
 572    or 0 if arg is 0.  */
 573 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
 574
 575 /* Count leading zeros.  */
 576 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
 577
 578 /* Count trailing zeros.  */
 579 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
 580
 581 /* Population count (number of 1 bits).  */
 582 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
 583
 584 /* Population parity (number of 1 bits modulo 2).  */
 585 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
 586
 587 /* Reference to a signed bit-field of specified size and position.
 588    Operand 0 is the memory unit (usually SImode or QImode) which
 589    contains the field's first bit.  Operand 1 is the width, in bits.
 590    Operand 2 is the number of bits in the memory unit before the
 591    first bit of this field.
 592    If BITS_BIG_ENDIAN is defined, the first bit is the msb and
 593    operand 2 counts from the msb of the memory unit.
 594    Otherwise, the first bit is the lsb and operand 2 counts from
 595    the lsb of the memory unit.
 596    This kind of expression can not appear as an lvalue in RTL.  */
 597 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
 598
 599 /* Similar for unsigned bit-field.
 600    But note!  This kind of expression _can_ appear as an lvalue.  */
 601 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
 602
 603 /* For RISC machines.  These save memory when splitting insns.  */
 604
 605 /* HIGH are the high-order bits of a constant expression.  */
 606 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
 607
 608 /* LO_SUM is the sum of a register and the low-order bits
 609    of a constant expression.  */
 610 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
 611
 612 /* Describes a merge operation between two vector values.
 613    Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
 614    that specifies where the parts of the result are taken from.  Set bits
 615    indicate operand 0, clear bits indicate operand 1.  The parts are defined
 616    by the mode of the vectors.  */
 617 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
 618
 619 /* Describes an operation that selects parts of a vector.
 620    Operands 0 is the source vector, operand 1 is a PARALLEL that contains
 621    a CONST_INT for each of the subparts of the result vector, giving the
 622    number of the source subpart that should be stored into it.  */
 623 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
 624
 625 /* Describes a vector concat operation.  Operands 0 and 1 are the source
 626    vectors, the result is a vector that is as long as operands 0 and 1
 627    combined and is the concatenation of the two source vectors.  */
 628 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
 629
 630 /* Describes an operation that converts a small vector into a larger one by
 631    duplicating the input values.  The output vector mode must have the same
 632    submodes as the input vector mode, and the number of output parts must be
 633    an integer multiple of the number of input parts.  */
 634 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
 635
 636 /* Addition with signed saturation */
 637 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
 638
 639 /* Addition with unsigned saturation */
 640 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
 641
 642 /* Operand 0 minus operand 1, with signed saturation.  */
 643 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
 644
 645 /* Negation with signed saturation.  */
 646 DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
 647
 648 /* Shift left with signed saturation.  */
 649 DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
 650
 651 /* Operand 0 minus operand 1, with unsigned saturation.  */
 652 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
 653
 654 /* Signed saturating truncate.  */
 655 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
 656
 657 /* Unsigned saturating truncate.  */
 658 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
 659
 660 /* Information about the variable and its location.  */
 661 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA)
 662
 663 /* All expressions from this point forward appear only in machine
 664    descriptions.  */
 665 #ifdef GENERATOR_FILE
 666
 667 /* Include a secondary machine-description file at this point.  */
 668 DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA)
 669
 670 /* Pattern-matching operators:  */
 671
 672 /* Use the function named by the second arg (the string)
 673    as a predicate; if matched, store the structure that was matched
 674    in the operand table at index specified by the first arg (the integer).
 675    If the second arg is the null string, the structure is just stored.
 676
 677    A third string argument indicates to the register allocator restrictions
 678    on where the operand can be allocated.
 679
 680    If the target needs no restriction on any instruction this field should
 681    be the null string.
 682
 683    The string is prepended by:
 684    '=' to indicate the operand is only written to.
 685    '+' to indicate the operand is both read and written to.
 686
 687    Each character in the string represents an allocable class for an operand.
 688    'g' indicates the operand can be any valid class.
 689    'i' indicates the operand can be immediate (in the instruction) data.
 690    'r' indicates the operand can be in a register.
 691    'm' indicates the operand can be in memory.
 692    'o' a subset of the 'm' class.  Those memory addressing modes that
 693        can be offset at compile time (have a constant added to them).
 694
 695    Other characters indicate target dependent operand classes and
 696    are described in each target's machine description.
 697
 698    For instructions with more than one operand, sets of classes can be
 699    separated by a comma to indicate the appropriate multi-operand constraints.
 700    There must be a 1 to 1 correspondence between these sets of classes in
 701    all operands for an instruction.
 702    */
 703 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
 704
 705 /* Match a SCRATCH or a register.  When used to generate rtl, a
 706    SCRATCH is generated.  As for MATCH_OPERAND, the mode specifies
 707    the desired mode and the first argument is the operand number.
 708    The second argument is the constraint.  */
 709 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
 710
 711 /* Apply a predicate, AND match recursively the operands of the rtx.
 712    Operand 0 is the operand-number, as in match_operand.
 713    Operand 1 is a predicate to apply (as a string, a function name).
 714    Operand 2 is a vector of expressions, each of which must match
 715    one subexpression of the rtx this construct is matching.  */
 716 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
 717
 718 /* Match a PARALLEL of arbitrary length.  The predicate is applied
 719    to the PARALLEL and the initial expressions in the PARALLEL are matched.
 720    Operand 0 is the operand-number, as in match_operand.
 721    Operand 1 is a predicate to apply to the PARALLEL.
 722    Operand 2 is a vector of expressions, each of which must match the
 723    corresponding element in the PARALLEL.  */
 724 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
 725
 726 /* Match only something equal to what is stored in the operand table
 727    at the index specified by the argument.  Use with MATCH_OPERAND.  */
 728 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
 729
 730 /* Match only something equal to what is stored in the operand table
 731    at the index specified by the argument.  Use with MATCH_OPERATOR.  */
 732 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
 733
 734 /* Match only something equal to what is stored in the operand table
 735    at the index specified by the argument.  Use with MATCH_PARALLEL.  */
 736 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
 737
 738 /* Appears only in define_predicate/define_special_predicate
 739    expressions.  Evaluates true only if the operand has an RTX code
 740    from the set given by the argument (a comma-separated list).  If the
 741    second argument is present and nonempty, it is a sequence of digits
 742    and/or letters which indicates the subexpression to test, using the
 743    same syntax as genextract/genrecog's location strings: 0-9 for
 744    XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
 745    the result of the one before it.  */
 746 DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
 747
 748 /* Appears only in define_predicate/define_special_predicate
 749     expressions.  The argument is a C expression to be injected at this
 750     point in the predicate formula.  */
 751 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
 752
 753 /* Insn (and related) definitions.  */
 754
 755 /* Definition of the pattern for one kind of instruction.
 756    Operand:
 757    0: names this instruction.
 758       If the name is the null string, the instruction is in the
 759       machine description just to be recognized, and will never be emitted by
 760       the tree to rtl expander.
 761    1: is the pattern.
 762    2: is a string which is a C expression
 763       giving an additional condition for recognizing this pattern.
 764       A null string means no extra condition.
 765    3: is the action to execute if this pattern is matched.
 766       If this assembler code template starts with a * then it is a fragment of
 767       C code to run to decide on a template to use.  Otherwise, it is the
 768       template to use.
 769    4: optionally, a vector of attributes for this insn.
 770      */
 771 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
 772
 773 /* Definition of a peephole optimization.
 774    1st operand: vector of insn patterns to match
 775    2nd operand: C expression that must be true
 776    3rd operand: template or C code to produce assembler output.
 777    4: optionally, a vector of attributes for this insn.
 778
 779    This form is deprecated; use define_peephole2 instead.  */
 780 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
 781
 782 /* Definition of a split operation.
 783    1st operand: insn pattern to match
 784    2nd operand: C expression that must be true
 785    3rd operand: vector of insn patterns to place into a SEQUENCE
 786    4th operand: optionally, some C code to execute before generating the
 787         insns.  This might, for example, create some RTX's and store them in
 788         elements of `recog_data.operand' for use by the vector of
 789         insn-patterns.
 790         (`operands' is an alias here for `recog_data.operand').  */
 791 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
 792
 793 /* Definition of an insn and associated split.
 794    This is the concatenation, with a few modifications, of a define_insn
 795    and a define_split which share the same pattern.
 796    Operand:
 797    0: names this instruction.
 798       If the name is the null string, the instruction is in the
 799       machine description just to be recognized, and will never be emitted by
 800       the tree to rtl expander.
 801    1: is the pattern.
 802    2: is a string which is a C expression
 803       giving an additional condition for recognizing this pattern.
 804       A null string means no extra condition.
 805    3: is the action to execute if this pattern is matched.
 806       If this assembler code template starts with a * then it is a fragment of
 807       C code to run to decide on a template to use.  Otherwise, it is the
 808       template to use.
 809    4: C expression that must be true for split.  This may start with "&&"
 810       in which case the split condition is the logical and of the insn
 811       condition and what follows the "&&" of this operand.
 812    5: vector of insn patterns to place into a SEQUENCE
 813    6: optionally, some C code to execute before generating the
 814         insns.  This might, for example, create some RTX's and store them in
 815         elements of `recog_data.operand' for use by the vector of
 816         insn-patterns.
 817         (`operands' is an alias here for `recog_data.operand').
 818    7: optionally, a vector of attributes for this insn.  */
 819 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
 820
 821 /* Definition of an RTL peephole operation.
 822    Follows the same arguments as define_split.  */
 823 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
 824
 825 /* Define how to generate multiple insns for a standard insn name.
 826    1st operand: the insn name.
 827    2nd operand: vector of insn-patterns.
 828         Use match_operand to substitute an element of `recog_data.operand'.
 829    3rd operand: C expression that must be true for this to be available.
 830         This may not test any operands.
 831    4th operand: Extra C code to execute before generating the insns.
 832         This might, for example, create some RTX's and store them in
 833         elements of `recog_data.operand' for use by the vector of
 834         insn-patterns.
 835         (`operands' is an alias here for `recog_data.operand').  */
 836 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
 837
 838 /* Define a requirement for delay slots.
 839    1st operand: Condition involving insn attributes that, if true,
 840                 indicates that the insn requires the number of delay slots
 841                 shown.
 842    2nd operand: Vector whose length is the three times the number of delay
 843                 slots required.
 844                 Each entry gives three conditions, each involving attributes.
 845                 The first must be true for an insn to occupy that delay slot
 846                 location.  The second is true for all insns that can be
 847                 annulled if the branch is true and the third is true for all
 848                 insns that can be annulled if the branch is false.
 849
 850    Multiple DEFINE_DELAYs may be present.  They indicate differing
 851    requirements for delay slots.  */
 852 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
 853
 854 /* Define attribute computation for `asm' instructions.  */
 855 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
 856
 857 /* Definition of a conditional execution meta operation.  Automatically
 858    generates new instances of DEFINE_INSN, selected by having attribute
 859    "predicable" true.  The new pattern will contain a COND_EXEC and the
 860    predicate at top-level.
 861
 862    Operand:
 863    0: The predicate pattern.  The top-level form should match a
 864       relational operator.  Operands should have only one alternative.
 865    1: A C expression giving an additional condition for recognizing
 866       the generated pattern.
 867    2: A template or C code to produce assembler output.  */
 868 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
 869
 870 /* Definition of an operand predicate.  The difference between
 871    DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
 872    not warn about a match_operand with no mode if it has a predicate
 873    defined with DEFINE_SPECIAL_PREDICATE.
 874
 875    Operand:
 876    0: The name of the predicate.
 877    1: A boolean expression which computes whether or not the predicate
 878       matches.  This expression can use IOR, AND, NOT, MATCH_OPERAND,
 879       MATCH_CODE, and MATCH_TEST.  It must be specific enough that genrecog
 880       can calculate the set of RTX codes that can possibly match.
 881    2: A C function body which must return true for the predicate to match.
 882       Optional.  Use this when the test is too complicated to fit into a
 883       match_test expression.  */
 884 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
 885 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
 886
 887 /* Definition of a register operand constraint.  This simply maps the
 888    constraint string to a register class.
 889
 890    Operand:
 891    0: The name of the constraint (often, but not always, a single letter).
 892    1: A C expression which evaluates to the appropriate register class for
 893       this constraint.  If this is not just a constant, it should look only
 894       at -m switches and the like.
 895    2: A docstring for this constraint, in Texinfo syntax; not currently
 896       used, in future will be incorporated into the manual's list of
 897       machine-specific operand constraints.  */
 898 DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
 899
 900 /* Definition of a non-register operand constraint.  These look at the
 901    operand and decide whether it fits the constraint.
 902
 903    DEFINE_CONSTRAINT gets no special treatment if it fails to match.
 904    It is appropriate for constant-only constraints, and most others.
 905
 906    DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
 907    to match, if it doesn't already, by converting the operand to the form
 908    (mem (reg X)) where X is a base register.  It is suitable for constraints
 909    that describe a subset of all memory references.
 910
 911    DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
 912    to match, if it doesn't already, by converting the operand to the form
 913    (reg X) where X is a base register.  It is suitable for constraints that
 914    describe a subset of all address references.
 915
 916    When in doubt, use plain DEFINE_CONSTRAINT.
 917
 918    Operand:
 919    0: The name of the constraint (often, but not always, a single letter).
 920    1: A docstring for this constraint, in Texinfo syntax; not currently
 921       used, in future will be incorporated into the manual's list of
 922       machine-specific operand constraints.
 923    2: A boolean expression which computes whether or not the constraint
 924       matches.  It should follow the same rules as a define_predicate
 925       expression, including the bit about specifying the set of RTX codes
 926       that could possibly match.  MATCH_TEST subexpressions may make use of
 927       these variables:
 928         `op'    - the RTL object defining the operand.
 929         `mode'  - the mode of `op'.
 930         `ival'  - INTVAL(op), if op is a CONST_INT.
 931         `hval'  - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
 932         `lval'  - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
 933         `rval'  - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
 934                   CONST_DOUBLE.
 935       Do not use ival/hval/lval/rval if op is not the appropriate kind of
 936       RTL object.  */
 937 DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
 938 DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
 939 DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
 940
 941
 942 /* Constructions for CPU pipeline description described by NDFAs.  */
 943
 944 /* (define_cpu_unit string [string]) describes cpu functional
 945    units (separated by comma).
 946
 947    1st operand: Names of cpu functional units.
 948    2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
 949
 950    All define_reservations, define_cpu_units, and
 951    define_query_cpu_units should have unique names which may not be
 952    "nothing".  */
 953 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
 954
 955 /* (define_query_cpu_unit string [string]) describes cpu functional
 956    units analogously to define_cpu_unit.  The reservation of such
 957    units can be queried for automaton state.  */
 958 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
 959
 960 /* (exclusion_set string string) means that each CPU functional unit
 961    in the first string can not be reserved simultaneously with any
 962    unit whose name is in the second string and vise versa.  CPU units
 963    in the string are separated by commas.  For example, it is useful
 964    for description CPU with fully pipelined floating point functional
 965    unit which can execute simultaneously only single floating point
 966    insns or only double floating point insns.  All CPU functional
 967    units in a set should belong to the same automaton.  */
 968 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
 969
 970 /* (presence_set string string) means that each CPU functional unit in
 971    the first string can not be reserved unless at least one of pattern
 972    of units whose names are in the second string is reserved.  This is
 973    an asymmetric relation.  CPU units or unit patterns in the strings
 974    are separated by commas.  Pattern is one unit name or unit names
 975    separated by white-spaces.
 976
 977    For example, it is useful for description that slot1 is reserved
 978    after slot0 reservation for a VLIW processor.  We could describe it
 979    by the following construction
 980
 981       (presence_set "slot1" "slot0")
 982
 983    Or slot1 is reserved only after slot0 and unit b0 reservation.  In
 984    this case we could write
 985
 986       (presence_set "slot1" "slot0 b0")
 987
 988    All CPU functional units in a set should belong to the same
 989    automaton.  */
 990 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
 991
 992 /* (final_presence_set string string) is analogous to `presence_set'.
 993    The difference between them is when checking is done.  When an
 994    instruction is issued in given automaton state reflecting all
 995    current and planned unit reservations, the automaton state is
 996    changed.  The first state is a source state, the second one is a
 997    result state.  Checking for `presence_set' is done on the source
 998    state reservation, checking for `final_presence_set' is done on the
 999    result reservation.  This construction is useful to describe a
1000    reservation which is actually two subsequent reservations.  For
1001    example, if we use
1002
1003       (presence_set "slot1" "slot0")
1004
1005    the following insn will be never issued (because slot1 requires
1006    slot0 which is absent in the source state).
1007
1008       (define_reservation "insn_and_nop" "slot0 + slot1")
1009
1010    but it can be issued if we use analogous `final_presence_set'.  */
1011 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1012
1013 /* (absence_set string string) means that each CPU functional unit in
1014    the first string can be reserved only if each pattern of units
1015    whose names are in the second string is not reserved.  This is an
1016    asymmetric relation (actually exclusion set is analogous to this
1017    one but it is symmetric).  CPU units or unit patterns in the string
1018    are separated by commas.  Pattern is one unit name or unit names
1019    separated by white-spaces.
1020
1021    For example, it is useful for description that slot0 can not be
1022    reserved after slot1 or slot2 reservation for a VLIW processor.  We
1023    could describe it by the following construction
1024
1025       (absence_set "slot2" "slot0, slot1")
1026
1027    Or slot2 can not be reserved if slot0 and unit b0 are reserved or
1028    slot1 and unit b1 are reserved .  In this case we could write
1029
1030       (absence_set "slot2" "slot0 b0, slot1 b1")
1031
1032    All CPU functional units in a set should to belong the same
1033    automaton.  */
1034 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1035
1036 /* (final_absence_set string string) is analogous to `absence_set' but
1037    checking is done on the result (state) reservation.  See comments
1038    for `final_presence_set'.  */
1039 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1040
1041 /* (define_bypass number out_insn_names in_insn_names) names bypass
1042    with given latency (the first number) from insns given by the first
1043    string (see define_insn_reservation) into insns given by the second
1044    string.  Insn names in the strings are separated by commas.  The
1045    third operand is optional name of function which is additional
1046    guard for the bypass.  The function will get the two insns as
1047    parameters.  If the function returns zero the bypass will be
1048    ignored for this case.  Additional guard is necessary to recognize
1049    complicated bypasses, e.g. when consumer is load address.  */
1050 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1051
1052 /* (define_automaton string) describes names of automata generated and
1053    used for pipeline hazards recognition.  The names are separated by
1054    comma.  Actually it is possibly to generate the single automaton
1055    but unfortunately it can be very large.  If we use more one
1056    automata, the summary size of the automata usually is less than the
1057    single one.  The automaton name is used in define_cpu_unit and
1058    define_query_cpu_unit.  All automata should have unique names.  */
1059 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1060
1061 /* (automata_option string) describes option for generation of
1062    automata.  Currently there are the following options:
1063
1064    o "no-minimization" which makes no minimization of automata.  This
1065      is only worth to do when we are debugging the description and
1066      need to look more accurately at reservations of states.
1067
1068    o "time" which means printing additional time statistics about
1069       generation of automata.
1070
1071    o "v" which means generation of file describing the result
1072      automata.  The file has suffix `.dfa' and can be used for the
1073      description verification and debugging.
1074
1075    o "w" which means generation of warning instead of error for
1076      non-critical errors.
1077
1078    o "ndfa" which makes nondeterministic finite state automata.
1079
1080    o "progress" which means output of a progress bar showing how many
1081      states were generated so far for automaton being processed.  */
1082 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1083
1084 /* (define_reservation string string) names reservation (the first
1085    string) of cpu functional units (the 2nd string).  Sometimes unit
1086    reservations for different insns contain common parts.  In such
1087    case, you can describe common part and use its name (the 1st
1088    parameter) in regular expression in define_insn_reservation.  All
1089    define_reservations, define_cpu_units, and define_query_cpu_units
1090    should have unique names which may not be "nothing".  */
1091 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1092
1093 /* (define_insn_reservation name default_latency condition regexpr)
1094    describes reservation of cpu functional units (the 3nd operand) for
1095    instruction which is selected by the condition (the 2nd parameter).
1096    The first parameter is used for output of debugging information.
1097    The reservations are described by a regular expression according
1098    the following syntax:
1099
1100        regexp = regexp "," oneof
1101               | oneof
1102
1103        oneof = oneof "|" allof
1104              | allof
1105
1106        allof = allof "+" repeat
1107              | repeat
1108
1109        repeat = element "*" number
1110               | element
1111
1112        element = cpu_function_unit_name
1113                | reservation_name
1114                | result_name
1115                | "nothing"
1116                | "(" regexp ")"
1117
1118        1. "," is used for describing start of the next cycle in
1119        reservation.
1120
1121        2. "|" is used for describing the reservation described by the
1122        first regular expression *or* the reservation described by the
1123        second regular expression *or* etc.
1124
1125        3. "+" is used for describing the reservation described by the
1126        first regular expression *and* the reservation described by the
1127        second regular expression *and* etc.
1128
1129        4. "*" is used for convenience and simply means sequence in
1130        which the regular expression are repeated NUMBER times with
1131        cycle advancing (see ",").
1132
1133        5. cpu functional unit name which means its reservation.
1134
1135        6. reservation name -- see define_reservation.
1136
1137        7. string "nothing" means no units reservation.  */
1138
1139 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1140
1141 /* Expressions used for insn attributes.  */
1142
1143 /* Definition of an insn attribute.
1144    1st operand: name of the attribute
1145    2nd operand: comma-separated list of possible attribute values
1146    3rd operand: expression for the default value of the attribute.  */
1147 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1148
1149 /* Marker for the name of an attribute.  */
1150 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1151
1152 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1153    in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1154    pattern.
1155
1156    (set_attr "name" "value") is equivalent to
1157    (set (attr "name") (const_string "value"))  */
1158 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1159
1160 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1161    specify that attribute values are to be assigned according to the
1162    alternative matched.
1163
1164    The following three expressions are equivalent:
1165
1166    (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1167                             (eq_attrq "alternative" "2") (const_string "a2")]
1168                            (const_string "a3")))
1169    (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1170                                  (const_string "a3")])
1171    (set_attr "att" "a1,a2,a3")
1172  */
1173 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1174
1175 /* A conditional expression true if the value of the specified attribute of
1176    the current insn equals the specified value.  The first operand is the
1177    attribute name and the second is the comparison value.  */
1178 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1179
1180 /* A special case of the above representing a set of alternatives.  The first
1181    operand is bitmap of the set, the second one is the default value.  */
1182 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1183
1184 /* A conditional expression which is true if the specified flag is
1185    true for the insn being scheduled in reorg.
1186
1187    genattr.c defines the following flags which can be tested by
1188    (attr_flag "foo") expressions in eligible_for_delay.
1189
1190    forward, backward, very_likely, likely, very_unlikely, and unlikely.  */
1191
1192 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1193
1194 /* General conditional. The first operand is a vector composed of pairs of
1195    expressions.  The first element of each pair is evaluated, in turn.
1196    The value of the conditional is the second expression of the first pair
1197    whose first expression evaluates nonzero.  If none of the expressions is
1198    true, the second operand will be used as the value of the conditional.  */
1199 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1200
1201 #endif /* GENERATOR_FILE */
1202
1203 /*
1204 Local variables:
1205 mode:c
1206 End:
1207 */