1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
6 ;; Changes by Michael Meissner, meissner@osf.org
7 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 ;; Brendan Eich, brendan@microunity.com.
10 ;; This file is part of GCC.
12 ;; GCC is free software; you can redistribute it and/or modify
13 ;; it under the terms of the GNU General Public License as published by
14 ;; the Free Software Foundation; either version 3, or (at your option)
17 ;; GCC is distributed in the hope that it will be useful,
18 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
19 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 ;; GNU General Public License for more details.
22 ;; You should have received a copy of the GNU General Public License
23 ;; along with GCC; see the file COPYING3. If not see
24 ;; <http://www.gnu.org/licenses/>.
35 (UNSPEC_CONSTTABLE_INT 8)
36 (UNSPEC_CONSTTABLE_FLOAT 9)
40 (UNSPEC_LOAD_RIGHT 19)
41 (UNSPEC_STORE_LEFT 20)
42 (UNSPEC_STORE_RIGHT 21)
49 (UNSPEC_TLS_GET_TP 28)
52 (UNSPEC_CLEAR_HAZARD 33)
56 (UNSPEC_COMPARE_AND_SWAP 37)
57 (UNSPEC_COMPARE_AND_SWAP_12 38)
58 (UNSPEC_SYNC_OLD_OP 39)
59 (UNSPEC_SYNC_NEW_OP 40)
60 (UNSPEC_SYNC_NEW_OP_12 41)
61 (UNSPEC_SYNC_OLD_OP_12 42)
62 (UNSPEC_SYNC_EXCHANGE 43)
63 (UNSPEC_SYNC_EXCHANGE_12 44)
64 (UNSPEC_MEMORY_BARRIER 45)
65 (UNSPEC_SET_GOT_VERSION 46)
66 (UNSPEC_UPDATE_GOT_VERSION 47)
68 (UNSPEC_ADDRESS_FIRST 100)
70 (GOT_VERSION_REGNUM 79)
72 ;; For MIPS Paired-Singled Floating Point Instructions.
74 (UNSPEC_MOVE_TF_PS 200)
77 ;; MIPS64/MIPS32R2 alnv.ps
80 ;; MIPS-3D instructions
84 (UNSPEC_CVT_PW_PS 205)
85 (UNSPEC_CVT_PS_PW 206)
93 (UNSPEC_SINGLE_CC 213)
96 ;; MIPS DSP ASE Revision 0.98 3/24/2005
104 (UNSPEC_RADDU_W_QB 307)
106 (UNSPEC_PRECRQ_QB_PH 309)
107 (UNSPEC_PRECRQ_PH_W 310)
108 (UNSPEC_PRECRQ_RS_PH_W 311)
109 (UNSPEC_PRECRQU_S_QB_PH 312)
110 (UNSPEC_PRECEQ_W_PHL 313)
111 (UNSPEC_PRECEQ_W_PHR 314)
112 (UNSPEC_PRECEQU_PH_QBL 315)
113 (UNSPEC_PRECEQU_PH_QBR 316)
114 (UNSPEC_PRECEQU_PH_QBLA 317)
115 (UNSPEC_PRECEQU_PH_QBRA 318)
116 (UNSPEC_PRECEU_PH_QBL 319)
117 (UNSPEC_PRECEU_PH_QBR 320)
118 (UNSPEC_PRECEU_PH_QBLA 321)
119 (UNSPEC_PRECEU_PH_QBRA 322)
125 (UNSPEC_MULEU_S_PH_QBL 328)
126 (UNSPEC_MULEU_S_PH_QBR 329)
127 (UNSPEC_MULQ_RS_PH 330)
128 (UNSPEC_MULEQ_S_W_PHL 331)
129 (UNSPEC_MULEQ_S_W_PHR 332)
130 (UNSPEC_DPAU_H_QBL 333)
131 (UNSPEC_DPAU_H_QBR 334)
132 (UNSPEC_DPSU_H_QBL 335)
133 (UNSPEC_DPSU_H_QBR 336)
134 (UNSPEC_DPAQ_S_W_PH 337)
135 (UNSPEC_DPSQ_S_W_PH 338)
136 (UNSPEC_MULSAQ_S_W_PH 339)
137 (UNSPEC_DPAQ_SA_L_W 340)
138 (UNSPEC_DPSQ_SA_L_W 341)
139 (UNSPEC_MAQ_S_W_PHL 342)
140 (UNSPEC_MAQ_S_W_PHR 343)
141 (UNSPEC_MAQ_SA_W_PHL 344)
142 (UNSPEC_MAQ_SA_W_PHR 345)
150 (UNSPEC_CMPGU_EQ_QB 353)
151 (UNSPEC_CMPGU_LT_QB 354)
152 (UNSPEC_CMPGU_LE_QB 355)
154 (UNSPEC_PACKRL_PH 357)
156 (UNSPEC_EXTR_R_W 359)
157 (UNSPEC_EXTR_RS_W 360)
158 (UNSPEC_EXTR_S_H 361)
166 ;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
167 (UNSPEC_ABSQ_S_QB 400)
169 (UNSPEC_ADDU_S_PH 402)
170 (UNSPEC_ADDUH_QB 403)
171 (UNSPEC_ADDUH_R_QB 404)
174 (UNSPEC_CMPGDU_EQ_QB 407)
175 (UNSPEC_CMPGDU_LT_QB 408)
176 (UNSPEC_CMPGDU_LE_QB 409)
177 (UNSPEC_DPA_W_PH 410)
178 (UNSPEC_DPS_W_PH 411)
184 (UNSPEC_MUL_S_PH 417)
185 (UNSPEC_MULQ_RS_W 418)
186 (UNSPEC_MULQ_S_PH 419)
187 (UNSPEC_MULQ_S_W 420)
188 (UNSPEC_MULSA_W_PH 421)
191 (UNSPEC_PRECR_QB_PH 424)
192 (UNSPEC_PRECR_SRA_PH_W 425)
193 (UNSPEC_PRECR_SRA_R_PH_W 426)
196 (UNSPEC_SHRA_R_QB 429)
199 (UNSPEC_SUBU_S_PH 432)
200 (UNSPEC_SUBUH_QB 433)
201 (UNSPEC_SUBUH_R_QB 434)
202 (UNSPEC_ADDQH_PH 435)
203 (UNSPEC_ADDQH_R_PH 436)
205 (UNSPEC_ADDQH_R_W 438)
206 (UNSPEC_SUBQH_PH 439)
207 (UNSPEC_SUBQH_R_PH 440)
209 (UNSPEC_SUBQH_R_W 442)
210 (UNSPEC_DPAX_W_PH 443)
211 (UNSPEC_DPSX_W_PH 444)
212 (UNSPEC_DPAQX_S_W_PH 445)
213 (UNSPEC_DPAQX_SA_W_PH 446)
214 (UNSPEC_DPSQX_S_W_PH 447)
215 (UNSPEC_DPSQX_SA_W_PH 448)
219 (include "predicates.md")
220 (include "constraints.md")
222 ;; ....................
226 ;; ....................
228 (define_attr "got" "unset,xgot_high,load"
229 (const_string "unset"))
231 ;; For jal instructions, this attribute is DIRECT when the target address
232 ;; is symbolic and INDIRECT when it is a register.
233 (define_attr "jal" "unset,direct,indirect"
234 (const_string "unset"))
236 ;; This attribute is YES if the instruction is a jal macro (not a
237 ;; real jal instruction).
239 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
240 ;; an instruction to restore $gp. Direct jals are also macros for
241 ;; flag_pic && !TARGET_ABSOLUTE_ABICALLS because they first load
242 ;; the target address into a register.
243 (define_attr "jal_macro" "no,yes"
244 (cond [(eq_attr "jal" "direct")
245 (symbol_ref "TARGET_CALL_CLOBBERED_GP
246 || (flag_pic && !TARGET_ABSOLUTE_ABICALLS)")
247 (eq_attr "jal" "indirect")
248 (symbol_ref "TARGET_CALL_CLOBBERED_GP")]
249 (const_string "no")))
251 ;; Classification of each insn.
252 ;; branch conditional branch
253 ;; jump unconditional jump
254 ;; call unconditional call
255 ;; load load instruction(s)
256 ;; fpload floating point load
257 ;; fpidxload floating point indexed load
258 ;; store store instruction(s)
259 ;; fpstore floating point store
260 ;; fpidxstore floating point indexed store
261 ;; prefetch memory prefetch (register + offset)
262 ;; prefetchx memory indexed prefetch (register + register)
263 ;; condmove conditional moves
264 ;; mfc transfer from coprocessor
265 ;; mtc transfer to coprocessor
266 ;; mthilo transfer to hi/lo registers
267 ;; mfhilo transfer from hi/lo registers
268 ;; const load constant
269 ;; arith integer arithmetic instructions
270 ;; logical integer logical instructions
271 ;; shift integer shift instructions
272 ;; slt set less than instructions
273 ;; signext sign extend instructions
274 ;; clz the clz and clo instructions
275 ;; trap trap if instructions
276 ;; imul integer multiply 2 operands
277 ;; imul3 integer multiply 3 operands
278 ;; imadd integer multiply-add
279 ;; idiv integer divide
280 ;; move integer register move ({,D}ADD{,U} with rt = 0)
281 ;; fmove floating point register move
282 ;; fadd floating point add/subtract
283 ;; fmul floating point multiply
284 ;; fmadd floating point multiply-add
285 ;; fdiv floating point divide
286 ;; frdiv floating point reciprocal divide
287 ;; frdiv1 floating point reciprocal divide step 1
288 ;; frdiv2 floating point reciprocal divide step 2
289 ;; fabs floating point absolute value
290 ;; fneg floating point negation
291 ;; fcmp floating point compare
292 ;; fcvt floating point convert
293 ;; fsqrt floating point square root
294 ;; frsqrt floating point reciprocal square root
295 ;; frsqrt1 floating point reciprocal square root step1
296 ;; frsqrt2 floating point reciprocal square root step2
297 ;; multi multiword sequence (or user asm statements)
299 ;; ghost an instruction that produces no real code
301 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,mfc,mtc,mthilo,mfhilo,const,arith,logical,shift,slt,signext,clz,trap,imul,imul3,imadd,idiv,move,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop,ghost"
302 (cond [(eq_attr "jal" "!unset") (const_string "call")
303 (eq_attr "got" "load") (const_string "load")]
304 (const_string "unknown")))
306 ;; Main data type used by the insn
307 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
308 (const_string "unknown"))
310 ;; Mode for conversion types (fcvt)
311 ;; I2S integer to float single (SI/DI to SF)
312 ;; I2D integer to float double (SI/DI to DF)
313 ;; S2I float to integer (SF to SI/DI)
314 ;; D2I float to integer (DF to SI/DI)
315 ;; D2S double to float single
316 ;; S2D float single to double
318 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
319 (const_string "unknown"))
321 ;; Is this an extended instruction in mips16 mode?
322 (define_attr "extended_mips16" "no,yes"
325 ;; Length of instruction in bytes.
326 (define_attr "length" ""
327 (cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc].
328 ;; If a branch is outside this range, we have a choice of two
329 ;; sequences. For PIC, an out-of-range branch like:
334 ;; becomes the equivalent of:
343 ;; where the load address can be up to three instructions long
346 ;; The non-PIC case is similar except that we use a direct
347 ;; jump instead of an la/jr pair. Since the target of this
348 ;; jump is an absolute 28-bit bit address (the other bits
349 ;; coming from the address of the delay slot) this form cannot
350 ;; cross a 256MB boundary. We could provide the option of
351 ;; using la/jr in this case too, but we do not do so at
354 ;; Note that this value does not account for the delay slot
355 ;; instruction, whose length is added separately. If the RTL
356 ;; pattern has no explicit delay slot, mips_adjust_insn_length
357 ;; will add the length of the implicit nop. The values for
358 ;; forward and backward branches will be different as well.
359 (eq_attr "type" "branch")
360 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
361 (le (minus (pc) (match_dup 1)) (const_int 131068)))
363 (ne (symbol_ref "flag_pic") (const_int 0))
367 (eq_attr "got" "load")
369 (eq_attr "got" "xgot_high")
372 (eq_attr "type" "const")
373 (symbol_ref "mips_const_insns (operands[1]) * 4")
374 (eq_attr "type" "load,fpload")
375 (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
376 (eq_attr "type" "store,fpstore")
377 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")
379 ;; In the worst case, a call macro will take 8 instructions:
381 ;; lui $25,%call_hi(FOO)
383 ;; lw $25,%call_lo(FOO)($25)
389 (eq_attr "jal_macro" "yes")
392 (and (eq_attr "extended_mips16" "yes")
393 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
396 ;; Various VR4120 errata require a nop to be inserted after a macc
397 ;; instruction. The assembler does this for us, so account for
398 ;; the worst-case length here.
399 (and (eq_attr "type" "imadd")
400 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
403 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
404 ;; the result of the second one is missed. The assembler should work
405 ;; around this by inserting a nop after the first dmult.
406 (and (eq_attr "type" "imul,imul3")
407 (and (eq_attr "mode" "DI")
408 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
411 (eq_attr "type" "idiv")
412 (symbol_ref "mips_idiv_insns () * 4")
415 ;; Attribute describing the processor. This attribute must match exactly
416 ;; with the processor_type enumeration in mips.h.
418 "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson2e,loongson2f,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000,xlr"
419 (const (symbol_ref "mips_tune")))
421 ;; The type of hardware hazard associated with this instruction.
422 ;; DELAY means that the next instruction cannot read the result
423 ;; of this one. HILO means that the next two instructions cannot
424 ;; write to HI or LO.
425 (define_attr "hazard" "none,delay,hilo"
426 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
427 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
428 (const_string "delay")
430 (and (eq_attr "type" "mfc,mtc")
431 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
432 (const_string "delay")
434 (and (eq_attr "type" "fcmp")
435 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
436 (const_string "delay")
438 ;; The r4000 multiplication patterns include an mflo instruction.
439 (and (eq_attr "type" "imul")
440 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
441 (const_string "hilo")
443 (and (eq_attr "type" "mfhilo")
444 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
445 (const_string "hilo")]
446 (const_string "none")))
448 ;; Is it a single instruction?
449 (define_attr "single_insn" "no,yes"
450 (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
452 ;; Can the instruction be put into a delay slot?
453 (define_attr "can_delay" "no,yes"
454 (if_then_else (and (eq_attr "type" "!branch,call,jump")
455 (and (eq_attr "hazard" "none")
456 (eq_attr "single_insn" "yes")))
458 (const_string "no")))
460 ;; Attribute defining whether or not we can use the branch-likely instructions
461 (define_attr "branch_likely" "no,yes"
463 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
465 (const_string "no"))))
467 ;; True if an instruction might assign to hi or lo when reloaded.
468 ;; This is used by the TUNE_MACC_CHAINS code.
469 (define_attr "may_clobber_hilo" "no,yes"
470 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
472 (const_string "no")))
474 ;; Describe a user's asm statement.
475 (define_asm_attributes
476 [(set_attr "type" "multi")
477 (set_attr "can_delay" "no")])
479 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
480 ;; from the same template.
481 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
483 ;; A copy of GPR that can be used when a pattern has two independent
485 (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
487 ;; This mode iterator allows :P to be used for patterns that operate on
488 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
489 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
491 ;; This mode iterator allows :MOVECC to be used anywhere that a
492 ;; conditional-move-type condition is needed.
493 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
495 ;; 64-bit modes for which we provide move patterns.
496 (define_mode_iterator MOVE64
497 [DI DF (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
499 ;; 128-bit modes for which we provide move patterns on 64-bit targets.
500 (define_mode_iterator MOVE128 [TF])
502 ;; This mode iterator allows the QI and HI extension patterns to be
503 ;; defined from the same template.
504 (define_mode_iterator SHORT [QI HI])
506 ;; Likewise the 64-bit truncate-and-shift patterns.
507 (define_mode_iterator SUBDI [QI HI SI])
509 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
510 ;; floating-point mode is allowed.
511 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
512 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
513 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
515 ;; Like ANYF, but only applies to scalar modes.
516 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
517 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
519 ;; A floating-point mode for which moves involving FPRs may need to be split.
520 (define_mode_iterator SPLITF
521 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
522 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
523 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
524 (TF "TARGET_64BIT && TARGET_FLOAT64")])
526 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
527 ;; 32-bit version and "dsubu" in the 64-bit version.
528 (define_mode_attr d [(SI "") (DI "d")
529 (QQ "") (HQ "") (SQ "") (DQ "d")
530 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
531 (HA "") (SA "") (DA "d")
532 (UHA "") (USA "") (UDA "d")])
534 ;; This attribute gives the length suffix for a sign- or zero-extension
536 (define_mode_attr size [(QI "b") (HI "h")])
538 ;; This attributes gives the mode mask of a SHORT.
539 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
541 ;; Mode attributes for GPR loads and stores.
542 (define_mode_attr load [(SI "lw") (DI "ld")])
543 (define_mode_attr store [(SI "sw") (DI "sd")])
545 ;; Similarly for MIPS IV indexed FPR loads and stores.
546 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
547 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
549 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
550 ;; are different. Some forms of unextended addiu have an 8-bit immediate
551 ;; field but the equivalent daddiu has only a 5-bit field.
552 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
554 ;; This attribute gives the best constraint to use for registers of
556 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
558 ;; This attribute gives the format suffix for floating-point operations.
559 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
561 ;; This attribute gives the upper-case mode name for one unit of a
562 ;; floating-point mode.
563 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
565 ;; This attribute gives the integer mode that has the same size as a
567 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
568 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
569 (HA "HI") (SA "SI") (DA "DI")
570 (UHA "HI") (USA "SI") (UDA "DI")
571 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
572 (V2HQ "SI") (V2HA "SI")])
574 ;; This attribute gives the integer mode that has half the size of
575 ;; the controlling mode.
576 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI") (TF "DI")])
578 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
580 ;; In certain cases, div.s and div.ps may have a rounding error
581 ;; and/or wrong inexact flag.
583 ;; Therefore, we only allow div.s if not working around SB-1 rev2
584 ;; errata or if a slight loss of precision is OK.
585 (define_mode_attr divide_condition
586 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
587 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
589 ;; This attribute gives the conditions under which SQRT.fmt instructions
591 (define_mode_attr sqrt_condition
592 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
594 ;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt
595 ;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D
596 ;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,
597 ;; so for safety's sake, we apply this restriction to all targets.
598 (define_mode_attr recip_condition
600 (DF "ISA_HAS_FP4 && TARGET_FLOAT64")
601 (V2SF "TARGET_SB1")])
603 ;; This code iterator allows all branch instructions to be generated from
604 ;; a single define_expand template.
605 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
606 eq ne gt ge lt le gtu geu ltu leu])
608 ;; This code iterator allows signed and unsigned widening multiplications
609 ;; to use the same template.
610 (define_code_iterator any_extend [sign_extend zero_extend])
612 ;; This code iterator allows the three shift instructions to be generated
613 ;; from the same template.
614 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
616 ;; This code iterator allows all native floating-point comparisons to be
617 ;; generated from the same template.
618 (define_code_iterator fcond [unordered uneq unlt unle eq lt le])
620 ;; This code iterator is used for comparisons that can be implemented
621 ;; by swapping the operands.
622 (define_code_iterator swapped_fcond [ge gt unge ungt])
624 ;; These code iterators allow the signed and unsigned scc operations to use
625 ;; the same template.
626 (define_code_iterator any_gt [gt gtu])
627 (define_code_iterator any_ge [ge geu])
628 (define_code_iterator any_lt [lt ltu])
629 (define_code_iterator any_le [le leu])
631 ;; <u> expands to an empty string when doing a signed operation and
632 ;; "u" when doing an unsigned operation.
633 (define_code_attr u [(sign_extend "") (zero_extend "u")
639 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
640 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
642 ;; <optab> expands to the name of the optab for a particular code.
643 (define_code_attr optab [(ashift "ashl")
652 ;; <insn> expands to the name of the insn that implements a particular code.
653 (define_code_attr insn [(ashift "sll")
662 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
663 (define_code_attr fcond [(unordered "un")
671 ;; Similar, but for swapped conditions.
672 (define_code_attr swapped_fcond [(ge "le")
677 ;; Atomic fetch bitwise operations.
678 (define_code_iterator fetchop_bit [ior xor and])
680 ;; <immediate_insn> expands to the name of the insn that implements
681 ;; a particular code to operate in immediate values.
682 (define_code_attr immediate_insn [(ior "ori") (xor "xori") (and "andi")])
684 ;; Atomic HI and QI operations
685 (define_code_iterator atomic_hiqi_op [plus minus ior xor and])
687 ;; .........................
689 ;; Branch, call and jump delay slots
691 ;; .........................
693 (define_delay (and (eq_attr "type" "branch")
694 (eq (symbol_ref "TARGET_MIPS16") (const_int 0)))
695 [(eq_attr "can_delay" "yes")
697 (and (eq_attr "branch_likely" "yes")
698 (eq_attr "can_delay" "yes"))])
700 (define_delay (eq_attr "type" "jump")
701 [(eq_attr "can_delay" "yes")
705 (define_delay (and (eq_attr "type" "call")
706 (eq_attr "jal_macro" "no"))
707 [(eq_attr "can_delay" "yes")
711 ;; Pipeline descriptions.
713 ;; generic.md provides a fallback for processors without a specific
714 ;; pipeline description. It is derived from the old define_function_unit
715 ;; version and uses the "alu" and "imuldiv" units declared below.
717 ;; Some of the processor-specific files are also derived from old
718 ;; define_function_unit descriptions and simply override the parts of
719 ;; generic.md that don't apply. The other processor-specific files
720 ;; are self-contained.
721 (define_automaton "alu,imuldiv")
723 (define_cpu_unit "alu" "alu")
724 (define_cpu_unit "imuldiv" "imuldiv")
726 ;; Ghost instructions produce no real code and introduce no hazards.
727 ;; They exist purely to express an effect on dataflow.
728 (define_insn_reservation "ghost" 0
729 (eq_attr "type" "ghost")
752 (include "generic.md")
755 ;; ....................
759 ;; ....................
763 [(trap_if (const_int 1) (const_int 0))]
766 if (ISA_HAS_COND_TRAP)
768 else if (TARGET_MIPS16)
773 [(set_attr "type" "trap")])
775 (define_expand "conditional_trap"
776 [(trap_if (match_operator 0 "comparison_operator"
777 [(match_dup 2) (match_dup 3)])
778 (match_operand 1 "const_int_operand"))]
781 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
782 && operands[1] == const0_rtx)
784 mips_expand_conditional_trap (GET_CODE (operands[0]));
790 (define_insn "*conditional_trap<mode>"
791 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
792 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
793 (match_operand:GPR 2 "arith_operand" "dI")])
797 [(set_attr "type" "trap")])
800 ;; ....................
804 ;; ....................
807 (define_insn "add<mode>3"
808 [(set (match_operand:ANYF 0 "register_operand" "=f")
809 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
810 (match_operand:ANYF 2 "register_operand" "f")))]
812 "add.<fmt>\t%0,%1,%2"
813 [(set_attr "type" "fadd")
814 (set_attr "mode" "<UNITMODE>")])
816 (define_expand "add<mode>3"
817 [(set (match_operand:GPR 0 "register_operand")
818 (plus:GPR (match_operand:GPR 1 "register_operand")
819 (match_operand:GPR 2 "arith_operand")))]
822 (define_insn "*add<mode>3"
823 [(set (match_operand:GPR 0 "register_operand" "=d,d")
824 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
825 (match_operand:GPR 2 "arith_operand" "d,Q")))]
830 [(set_attr "type" "arith")
831 (set_attr "mode" "<MODE>")])
833 (define_insn "*add<mode>3_mips16"
834 [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
835 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
836 (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
844 [(set_attr "type" "arith")
845 (set_attr "mode" "<MODE>")
846 (set_attr_alternative "length"
847 [(if_then_else (match_operand 2 "m16_simm8_8")
850 (if_then_else (match_operand 2 "m16_uimm<si8_di5>_4")
853 (if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
856 (if_then_else (match_operand 2 "m16_simm4_1")
861 ;; On the mips16, we can sometimes split an add of a constant which is
862 ;; a 4 byte instruction into two adds which are both 2 byte
863 ;; instructions. There are two cases: one where we are adding a
864 ;; constant plus a register to another register, and one where we are
865 ;; simply adding a constant to a register.
868 [(set (match_operand:SI 0 "register_operand")
869 (plus:SI (match_dup 0)
870 (match_operand:SI 1 "const_int_operand")))]
871 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
872 && REG_P (operands[0])
873 && M16_REG_P (REGNO (operands[0]))
874 && GET_CODE (operands[1]) == CONST_INT
875 && ((INTVAL (operands[1]) > 0x7f
876 && INTVAL (operands[1]) <= 0x7f + 0x7f)
877 || (INTVAL (operands[1]) < - 0x80
878 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
879 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
880 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
882 HOST_WIDE_INT val = INTVAL (operands[1]);
886 operands[1] = GEN_INT (0x7f);
887 operands[2] = GEN_INT (val - 0x7f);
891 operands[1] = GEN_INT (- 0x80);
892 operands[2] = GEN_INT (val + 0x80);
897 [(set (match_operand:SI 0 "register_operand")
898 (plus:SI (match_operand:SI 1 "register_operand")
899 (match_operand:SI 2 "const_int_operand")))]
900 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
901 && REG_P (operands[0])
902 && M16_REG_P (REGNO (operands[0]))
903 && REG_P (operands[1])
904 && M16_REG_P (REGNO (operands[1]))
905 && REGNO (operands[0]) != REGNO (operands[1])
906 && GET_CODE (operands[2]) == CONST_INT
907 && ((INTVAL (operands[2]) > 0x7
908 && INTVAL (operands[2]) <= 0x7 + 0x7f)
909 || (INTVAL (operands[2]) < - 0x8
910 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
911 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
912 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
914 HOST_WIDE_INT val = INTVAL (operands[2]);
918 operands[2] = GEN_INT (0x7);
919 operands[3] = GEN_INT (val - 0x7);
923 operands[2] = GEN_INT (- 0x8);
924 operands[3] = GEN_INT (val + 0x8);
929 [(set (match_operand:DI 0 "register_operand")
930 (plus:DI (match_dup 0)
931 (match_operand:DI 1 "const_int_operand")))]
932 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
933 && REG_P (operands[0])
934 && M16_REG_P (REGNO (operands[0]))
935 && GET_CODE (operands[1]) == CONST_INT
936 && ((INTVAL (operands[1]) > 0xf
937 && INTVAL (operands[1]) <= 0xf + 0xf)
938 || (INTVAL (operands[1]) < - 0x10
939 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
940 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
941 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
943 HOST_WIDE_INT val = INTVAL (operands[1]);
947 operands[1] = GEN_INT (0xf);
948 operands[2] = GEN_INT (val - 0xf);
952 operands[1] = GEN_INT (- 0x10);
953 operands[2] = GEN_INT (val + 0x10);
958 [(set (match_operand:DI 0 "register_operand")
959 (plus:DI (match_operand:DI 1 "register_operand")
960 (match_operand:DI 2 "const_int_operand")))]
961 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
962 && REG_P (operands[0])
963 && M16_REG_P (REGNO (operands[0]))
964 && REG_P (operands[1])
965 && M16_REG_P (REGNO (operands[1]))
966 && REGNO (operands[0]) != REGNO (operands[1])
967 && GET_CODE (operands[2]) == CONST_INT
968 && ((INTVAL (operands[2]) > 0x7
969 && INTVAL (operands[2]) <= 0x7 + 0xf)
970 || (INTVAL (operands[2]) < - 0x8
971 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
972 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
973 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
975 HOST_WIDE_INT val = INTVAL (operands[2]);
979 operands[2] = GEN_INT (0x7);
980 operands[3] = GEN_INT (val - 0x7);
984 operands[2] = GEN_INT (- 0x8);
985 operands[3] = GEN_INT (val + 0x8);
989 (define_insn "*addsi3_extended"
990 [(set (match_operand:DI 0 "register_operand" "=d,d")
992 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
993 (match_operand:SI 2 "arith_operand" "d,Q"))))]
994 "TARGET_64BIT && !TARGET_MIPS16"
998 [(set_attr "type" "arith")
999 (set_attr "mode" "SI")])
1001 ;; Split this insn so that the addiu splitters can have a crack at it.
1002 ;; Use a conservative length estimate until the split.
1003 (define_insn_and_split "*addsi3_extended_mips16"
1004 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1006 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1007 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
1008 "TARGET_64BIT && TARGET_MIPS16"
1010 "&& reload_completed"
1011 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
1012 { operands[3] = gen_lowpart (SImode, operands[0]); }
1013 [(set_attr "type" "arith")
1014 (set_attr "mode" "SI")
1015 (set_attr "extended_mips16" "yes")])
1018 ;; ....................
1022 ;; ....................
1025 (define_insn "sub<mode>3"
1026 [(set (match_operand:ANYF 0 "register_operand" "=f")
1027 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1028 (match_operand:ANYF 2 "register_operand" "f")))]
1030 "sub.<fmt>\t%0,%1,%2"
1031 [(set_attr "type" "fadd")
1032 (set_attr "mode" "<UNITMODE>")])
1034 (define_insn "sub<mode>3"
1035 [(set (match_operand:GPR 0 "register_operand" "=d")
1036 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
1037 (match_operand:GPR 2 "register_operand" "d")))]
1040 [(set_attr "type" "arith")
1041 (set_attr "mode" "<MODE>")])
1043 (define_insn "*subsi3_extended"
1044 [(set (match_operand:DI 0 "register_operand" "=d")
1046 (minus:SI (match_operand:SI 1 "register_operand" "d")
1047 (match_operand:SI 2 "register_operand" "d"))))]
1050 [(set_attr "type" "arith")
1051 (set_attr "mode" "DI")])
1054 ;; ....................
1058 ;; ....................
1061 (define_expand "mul<mode>3"
1062 [(set (match_operand:SCALARF 0 "register_operand")
1063 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1064 (match_operand:SCALARF 2 "register_operand")))]
1068 (define_insn "*mul<mode>3"
1069 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1070 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1071 (match_operand:SCALARF 2 "register_operand" "f")))]
1072 "!TARGET_4300_MUL_FIX"
1073 "mul.<fmt>\t%0,%1,%2"
1074 [(set_attr "type" "fmul")
1075 (set_attr "mode" "<MODE>")])
1077 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1078 ;; operands may corrupt immediately following multiplies. This is a
1079 ;; simple fix to insert NOPs.
1081 (define_insn "*mul<mode>3_r4300"
1082 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1083 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1084 (match_operand:SCALARF 2 "register_operand" "f")))]
1085 "TARGET_4300_MUL_FIX"
1086 "mul.<fmt>\t%0,%1,%2\;nop"
1087 [(set_attr "type" "fmul")
1088 (set_attr "mode" "<MODE>")
1089 (set_attr "length" "8")])
1091 (define_insn "mulv2sf3"
1092 [(set (match_operand:V2SF 0 "register_operand" "=f")
1093 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1094 (match_operand:V2SF 2 "register_operand" "f")))]
1095 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
1097 [(set_attr "type" "fmul")
1098 (set_attr "mode" "SF")])
1100 ;; The original R4000 has a cpu bug. If a double-word or a variable
1101 ;; shift executes while an integer multiplication is in progress, the
1102 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1103 ;; with the mult on the R4000.
1105 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1106 ;; (also valid for MIPS R4000MC processors):
1108 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1109 ;; this errata description.
1110 ;; The following code sequence causes the R4000 to incorrectly
1111 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1112 ;; instruction. If the dsra32 instruction is executed during an
1113 ;; integer multiply, the dsra32 will only shift by the amount in
1114 ;; specified in the instruction rather than the amount plus 32
1116 ;; instruction 1: mult rs,rt integer multiply
1117 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1118 ;; right arithmetic + 32
1119 ;; Workaround: A dsra32 instruction placed after an integer
1120 ;; multiply should not be one of the 11 instructions after the
1121 ;; multiply instruction."
1125 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1126 ;; the following description.
1127 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1128 ;; 64-bit versions) may produce incorrect results under the
1129 ;; following conditions:
1130 ;; 1) An integer multiply is currently executing
1131 ;; 2) These types of shift instructions are executed immediately
1132 ;; following an integer divide instruction.
1134 ;; 1) Make sure no integer multiply is running wihen these
1135 ;; instruction are executed. If this cannot be predicted at
1136 ;; compile time, then insert a "mfhi" to R0 instruction
1137 ;; immediately after the integer multiply instruction. This
1138 ;; will cause the integer multiply to complete before the shift
1140 ;; 2) Separate integer divide and these two classes of shift
1141 ;; instructions by another instruction or a noop."
1143 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1146 (define_expand "mulsi3"
1147 [(set (match_operand:SI 0 "register_operand")
1148 (mult:SI (match_operand:SI 1 "register_operand")
1149 (match_operand:SI 2 "register_operand")))]
1153 emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
1154 else if (TARGET_FIX_R4000)
1155 emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
1157 emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
1161 (define_expand "muldi3"
1162 [(set (match_operand:DI 0 "register_operand")
1163 (mult:DI (match_operand:DI 1 "register_operand")
1164 (match_operand:DI 2 "register_operand")))]
1167 if (TARGET_FIX_R4000)
1168 emit_insn (gen_muldi3_r4000 (operands[0], operands[1], operands[2]));
1170 emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
1174 (define_insn "mulsi3_mult3"
1175 [(set (match_operand:SI 0 "register_operand" "=d,l")
1176 (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1177 (match_operand:SI 2 "register_operand" "d,d")))
1178 (clobber (match_scratch:SI 3 "=h,h"))
1179 (clobber (match_scratch:SI 4 "=l,X"))]
1182 if (which_alternative == 1)
1183 return "mult\t%1,%2";
1184 if (TARGET_MIPS3900)
1185 return "mult\t%0,%1,%2";
1186 return "mul\t%0,%1,%2";
1188 [(set_attr "type" "imul3,imul")
1189 (set_attr "mode" "SI")])
1191 ;; If a register gets allocated to LO, and we spill to memory, the reload
1192 ;; will include a move from LO to a GPR. Merge it into the multiplication
1193 ;; if it can set the GPR directly.
1196 ;; Operand 1: GPR (1st multiplication operand)
1197 ;; Operand 2: GPR (2nd multiplication operand)
1199 ;; Operand 4: GPR (destination)
1202 [(set (match_operand:SI 0 "register_operand")
1203 (mult:SI (match_operand:SI 1 "register_operand")
1204 (match_operand:SI 2 "register_operand")))
1205 (clobber (match_operand:SI 3 "register_operand"))
1206 (clobber (scratch:SI))])
1207 (set (match_operand:SI 4 "register_operand")
1208 (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1209 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1212 (mult:SI (match_dup 1)
1214 (clobber (match_dup 3))
1215 (clobber (match_dup 0))])])
1217 (define_insn "mul<mode>3_internal"
1218 [(set (match_operand:GPR 0 "register_operand" "=l")
1219 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1220 (match_operand:GPR 2 "register_operand" "d")))
1221 (clobber (match_scratch:GPR 3 "=h"))]
1224 [(set_attr "type" "imul")
1225 (set_attr "mode" "<MODE>")])
1227 (define_insn "mul<mode>3_r4000"
1228 [(set (match_operand:GPR 0 "register_operand" "=d")
1229 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1230 (match_operand:GPR 2 "register_operand" "d")))
1231 (clobber (match_scratch:GPR 3 "=h"))
1232 (clobber (match_scratch:GPR 4 "=l"))]
1234 "<d>mult\t%1,%2\;mflo\t%0"
1235 [(set_attr "type" "imul")
1236 (set_attr "mode" "<MODE>")
1237 (set_attr "length" "8")])
1239 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1240 ;; of "mult; mflo". They have the same latency, but the first form gives
1241 ;; us an extra cycle to compute the operands.
1244 ;; Operand 1: GPR (1st multiplication operand)
1245 ;; Operand 2: GPR (2nd multiplication operand)
1247 ;; Operand 4: GPR (destination)
1250 [(set (match_operand:SI 0 "register_operand")
1251 (mult:SI (match_operand:SI 1 "register_operand")
1252 (match_operand:SI 2 "register_operand")))
1253 (clobber (match_operand:SI 3 "register_operand"))])
1254 (set (match_operand:SI 4 "register_operand")
1255 (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1256 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1261 (plus:SI (mult:SI (match_dup 1)
1265 (plus:SI (mult:SI (match_dup 1)
1268 (clobber (match_dup 3))])])
1270 ;; Multiply-accumulate patterns
1272 ;; For processors that can copy the output to a general register:
1274 ;; The all-d alternative is needed because the combiner will find this
1275 ;; pattern and then register alloc/reload will move registers around to
1276 ;; make them fit, and we don't want to trigger unnecessary loads to LO.
1278 ;; The last alternative should be made slightly less desirable, but adding
1279 ;; "?" to the constraint is too strong, and causes values to be loaded into
1280 ;; LO even when that's more costly. For now, using "*d" mostly does the
1282 (define_insn "*mul_acc_si"
1283 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1284 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1285 (match_operand:SI 2 "register_operand" "d,d,d"))
1286 (match_operand:SI 3 "register_operand" "0,l,*d")))
1287 (clobber (match_scratch:SI 4 "=h,h,h"))
1288 (clobber (match_scratch:SI 5 "=X,3,l"))
1289 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1291 || GENERATE_MADD_MSUB)
1294 static const char *const madd[] = { "madd\t%1,%2", "madd\t%0,%1,%2" };
1295 if (which_alternative == 2)
1297 if (GENERATE_MADD_MSUB && which_alternative != 0)
1299 return madd[which_alternative];
1301 [(set_attr "type" "imadd")
1302 (set_attr "mode" "SI")
1303 (set_attr "length" "4,4,8")])
1305 ;; Split the above insn if we failed to get LO allocated.
1307 [(set (match_operand:SI 0 "register_operand")
1308 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1309 (match_operand:SI 2 "register_operand"))
1310 (match_operand:SI 3 "register_operand")))
1311 (clobber (match_scratch:SI 4))
1312 (clobber (match_scratch:SI 5))
1313 (clobber (match_scratch:SI 6))]
1314 "reload_completed && !TARGET_DEBUG_D_MODE
1315 && GP_REG_P (true_regnum (operands[0]))
1316 && GP_REG_P (true_regnum (operands[3]))"
1317 [(parallel [(set (match_dup 6)
1318 (mult:SI (match_dup 1) (match_dup 2)))
1319 (clobber (match_dup 4))
1320 (clobber (match_dup 5))])
1321 (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))]
1324 ;; Splitter to copy result of MADD to a general register
1326 [(set (match_operand:SI 0 "register_operand")
1327 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1328 (match_operand:SI 2 "register_operand"))
1329 (match_operand:SI 3 "register_operand")))
1330 (clobber (match_scratch:SI 4))
1331 (clobber (match_scratch:SI 5))
1332 (clobber (match_scratch:SI 6))]
1333 "reload_completed && !TARGET_DEBUG_D_MODE
1334 && GP_REG_P (true_regnum (operands[0]))
1335 && true_regnum (operands[3]) == LO_REGNUM"
1336 [(parallel [(set (match_dup 3)
1337 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
1339 (clobber (match_dup 4))
1340 (clobber (match_dup 5))
1341 (clobber (match_dup 6))])
1342 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1345 (define_insn "*macc"
1346 [(set (match_operand:SI 0 "register_operand" "=l,d")
1347 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1348 (match_operand:SI 2 "register_operand" "d,d"))
1349 (match_operand:SI 3 "register_operand" "0,l")))
1350 (clobber (match_scratch:SI 4 "=h,h"))
1351 (clobber (match_scratch:SI 5 "=X,3"))]
1354 if (which_alternative == 1)
1355 return "macc\t%0,%1,%2";
1356 else if (TARGET_MIPS5500)
1357 return "madd\t%1,%2";
1359 /* The VR4130 assumes that there is a two-cycle latency between a macc
1360 that "writes" to $0 and an instruction that reads from it. We avoid
1361 this by assigning to $1 instead. */
1362 return "%[macc\t%@,%1,%2%]";
1364 [(set_attr "type" "imadd")
1365 (set_attr "mode" "SI")])
1367 (define_insn "*msac"
1368 [(set (match_operand:SI 0 "register_operand" "=l,d")
1369 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1370 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1371 (match_operand:SI 3 "register_operand" "d,d"))))
1372 (clobber (match_scratch:SI 4 "=h,h"))
1373 (clobber (match_scratch:SI 5 "=X,1"))]
1376 if (which_alternative == 1)
1377 return "msac\t%0,%2,%3";
1378 else if (TARGET_MIPS5500)
1379 return "msub\t%2,%3";
1381 return "msac\t$0,%2,%3";
1383 [(set_attr "type" "imadd")
1384 (set_attr "mode" "SI")])
1386 ;; An msac-like instruction implemented using negation and a macc.
1387 (define_insn_and_split "*msac_using_macc"
1388 [(set (match_operand:SI 0 "register_operand" "=l,d")
1389 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1390 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1391 (match_operand:SI 3 "register_operand" "d,d"))))
1392 (clobber (match_scratch:SI 4 "=h,h"))
1393 (clobber (match_scratch:SI 5 "=X,1"))
1394 (clobber (match_scratch:SI 6 "=d,d"))]
1395 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1397 "&& reload_completed"
1399 (neg:SI (match_dup 3)))
1402 (plus:SI (mult:SI (match_dup 2)
1405 (clobber (match_dup 4))
1406 (clobber (match_dup 5))])]
1408 [(set_attr "type" "imadd")
1409 (set_attr "length" "8")])
1411 ;; Patterns generated by the define_peephole2 below.
1413 (define_insn "*macc2"
1414 [(set (match_operand:SI 0 "register_operand" "=l")
1415 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1416 (match_operand:SI 2 "register_operand" "d"))
1418 (set (match_operand:SI 3 "register_operand" "=d")
1419 (plus:SI (mult:SI (match_dup 1)
1422 (clobber (match_scratch:SI 4 "=h"))]
1423 "ISA_HAS_MACC && reload_completed"
1425 [(set_attr "type" "imadd")
1426 (set_attr "mode" "SI")])
1428 (define_insn "*msac2"
1429 [(set (match_operand:SI 0 "register_operand" "=l")
1430 (minus:SI (match_dup 0)
1431 (mult:SI (match_operand:SI 1 "register_operand" "d")
1432 (match_operand:SI 2 "register_operand" "d"))))
1433 (set (match_operand:SI 3 "register_operand" "=d")
1434 (minus:SI (match_dup 0)
1435 (mult:SI (match_dup 1)
1437 (clobber (match_scratch:SI 4 "=h"))]
1438 "ISA_HAS_MSAC && reload_completed"
1440 [(set_attr "type" "imadd")
1441 (set_attr "mode" "SI")])
1443 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1447 ;; Operand 1: macc/msac
1449 ;; Operand 3: GPR (destination)
1452 [(set (match_operand:SI 0 "register_operand")
1453 (match_operand:SI 1 "macc_msac_operand"))
1454 (clobber (match_operand:SI 2 "register_operand"))
1455 (clobber (scratch:SI))])
1456 (set (match_operand:SI 3 "register_operand")
1457 (unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))]
1459 [(parallel [(set (match_dup 0)
1463 (clobber (match_dup 2))])]
1466 ;; When we have a three-address multiplication instruction, it should
1467 ;; be faster to do a separate multiply and add, rather than moving
1468 ;; something into LO in order to use a macc instruction.
1470 ;; This peephole needs a scratch register to cater for the case when one
1471 ;; of the multiplication operands is the same as the destination.
1473 ;; Operand 0: GPR (scratch)
1475 ;; Operand 2: GPR (addend)
1476 ;; Operand 3: GPR (destination)
1477 ;; Operand 4: macc/msac
1479 ;; Operand 6: new multiplication
1480 ;; Operand 7: new addition/subtraction
1482 [(match_scratch:SI 0 "d")
1483 (set (match_operand:SI 1 "register_operand")
1484 (match_operand:SI 2 "register_operand"))
1487 [(set (match_operand:SI 3 "register_operand")
1488 (match_operand:SI 4 "macc_msac_operand"))
1489 (clobber (match_operand:SI 5 "register_operand"))
1490 (clobber (match_dup 1))])]
1492 && true_regnum (operands[1]) == LO_REGNUM
1493 && peep2_reg_dead_p (2, operands[1])
1494 && GP_REG_P (true_regnum (operands[3]))"
1495 [(parallel [(set (match_dup 0)
1497 (clobber (match_dup 5))
1498 (clobber (match_dup 1))])
1502 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1503 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1504 operands[2], operands[0]);
1507 ;; Same as above, except LO is the initial target of the macc.
1509 ;; Operand 0: GPR (scratch)
1511 ;; Operand 2: GPR (addend)
1512 ;; Operand 3: macc/msac
1514 ;; Operand 5: GPR (destination)
1515 ;; Operand 6: new multiplication
1516 ;; Operand 7: new addition/subtraction
1518 [(match_scratch:SI 0 "d")
1519 (set (match_operand:SI 1 "register_operand")
1520 (match_operand:SI 2 "register_operand"))
1524 (match_operand:SI 3 "macc_msac_operand"))
1525 (clobber (match_operand:SI 4 "register_operand"))
1526 (clobber (scratch:SI))])
1528 (set (match_operand:SI 5 "register_operand")
1529 (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))]
1530 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1531 [(parallel [(set (match_dup 0)
1533 (clobber (match_dup 4))
1534 (clobber (match_dup 1))])
1538 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1539 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1540 operands[2], operands[0]);
1543 (define_insn "*mul_sub_si"
1544 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1545 (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
1546 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1547 (match_operand:SI 3 "register_operand" "d,d,d"))))
1548 (clobber (match_scratch:SI 4 "=h,h,h"))
1549 (clobber (match_scratch:SI 5 "=X,1,l"))
1550 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1551 "GENERATE_MADD_MSUB"
1556 [(set_attr "type" "imadd")
1557 (set_attr "mode" "SI")
1558 (set_attr "length" "4,8,8")])
1560 ;; Split the above insn if we failed to get LO allocated.
1562 [(set (match_operand:SI 0 "register_operand")
1563 (minus:SI (match_operand:SI 1 "register_operand")
1564 (mult:SI (match_operand:SI 2 "register_operand")
1565 (match_operand:SI 3 "register_operand"))))
1566 (clobber (match_scratch:SI 4))
1567 (clobber (match_scratch:SI 5))
1568 (clobber (match_scratch:SI 6))]
1569 "reload_completed && !TARGET_DEBUG_D_MODE
1570 && GP_REG_P (true_regnum (operands[0]))
1571 && GP_REG_P (true_regnum (operands[1]))"
1572 [(parallel [(set (match_dup 6)
1573 (mult:SI (match_dup 2) (match_dup 3)))
1574 (clobber (match_dup 4))
1575 (clobber (match_dup 5))])
1576 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))]
1579 ;; Splitter to copy result of MSUB to a general register
1581 [(set (match_operand:SI 0 "register_operand")
1582 (minus:SI (match_operand:SI 1 "register_operand")
1583 (mult:SI (match_operand:SI 2 "register_operand")
1584 (match_operand:SI 3 "register_operand"))))
1585 (clobber (match_scratch:SI 4))
1586 (clobber (match_scratch:SI 5))
1587 (clobber (match_scratch:SI 6))]
1588 "reload_completed && !TARGET_DEBUG_D_MODE
1589 && GP_REG_P (true_regnum (operands[0]))
1590 && true_regnum (operands[1]) == LO_REGNUM"
1591 [(parallel [(set (match_dup 1)
1592 (minus:SI (match_dup 1)
1593 (mult:SI (match_dup 2) (match_dup 3))))
1594 (clobber (match_dup 4))
1595 (clobber (match_dup 5))
1596 (clobber (match_dup 6))])
1597 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1600 (define_insn "*muls"
1601 [(set (match_operand:SI 0 "register_operand" "=l,d")
1602 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1603 (match_operand:SI 2 "register_operand" "d,d"))))
1604 (clobber (match_scratch:SI 3 "=h,h"))
1605 (clobber (match_scratch:SI 4 "=X,l"))]
1610 [(set_attr "type" "imul,imul3")
1611 (set_attr "mode" "SI")])
1613 ;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
1615 (define_expand "<u>mulsidi3"
1617 [(set (match_operand:DI 0 "register_operand")
1618 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1619 (any_extend:DI (match_operand:SI 2 "register_operand"))))
1620 (clobber (scratch:DI))
1621 (clobber (scratch:DI))
1622 (clobber (scratch:DI))])]
1623 "!TARGET_64BIT || !TARGET_FIX_R4000"
1627 if (!TARGET_FIX_R4000)
1628 emit_insn (gen_<u>mulsidi3_32bit_internal (operands[0], operands[1],
1631 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
1637 (define_insn "<u>mulsidi3_32bit_internal"
1638 [(set (match_operand:DI 0 "register_operand" "=x")
1639 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1640 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1641 "!TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DSPR2"
1643 [(set_attr "type" "imul")
1644 (set_attr "mode" "SI")])
1646 (define_insn "<u>mulsidi3_32bit_r4000"
1647 [(set (match_operand:DI 0 "register_operand" "=d")
1648 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1649 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1650 (clobber (match_scratch:DI 3 "=x"))]
1651 "!TARGET_64BIT && TARGET_FIX_R4000"
1652 "mult<u>\t%1,%2\;mflo\t%L0;mfhi\t%M0"
1653 [(set_attr "type" "imul")
1654 (set_attr "mode" "SI")
1655 (set_attr "length" "12")])
1657 (define_insn_and_split "*<u>mulsidi3_64bit"
1658 [(set (match_operand:DI 0 "register_operand" "=d")
1659 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1660 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1661 (clobber (match_scratch:DI 3 "=l"))
1662 (clobber (match_scratch:DI 4 "=h"))
1663 (clobber (match_scratch:DI 5 "=d"))]
1664 "TARGET_64BIT && !TARGET_FIX_R4000"
1666 "&& reload_completed"
1670 (mult:SI (match_dup 1)
1674 (mult:DI (any_extend:DI (match_dup 1))
1675 (any_extend:DI (match_dup 2)))
1678 ;; OP5 <- LO, OP0 <- HI
1679 (set (match_dup 5) (unspec:DI [(match_dup 3) (match_dup 4)] UNSPEC_MFHILO))
1680 (set (match_dup 0) (unspec:DI [(match_dup 4) (match_dup 3)] UNSPEC_MFHILO))
1684 (ashift:DI (match_dup 5)
1687 (lshiftrt:DI (match_dup 5)
1690 ;; Shift OP0 into place.
1692 (ashift:DI (match_dup 0)
1695 ;; OR the two halves together
1697 (ior:DI (match_dup 0)
1700 [(set_attr "type" "imul")
1701 (set_attr "mode" "SI")
1702 (set_attr "length" "24")])
1704 (define_insn "*<u>mulsidi3_64bit_parts"
1705 [(set (match_operand:DI 0 "register_operand" "=l")
1707 (mult:SI (match_operand:SI 2 "register_operand" "d")
1708 (match_operand:SI 3 "register_operand" "d"))))
1709 (set (match_operand:DI 1 "register_operand" "=h")
1711 (mult:DI (any_extend:DI (match_dup 2))
1712 (any_extend:DI (match_dup 3)))
1714 "TARGET_64BIT && !TARGET_FIX_R4000"
1716 [(set_attr "type" "imul")
1717 (set_attr "mode" "SI")])
1719 ;; Widening multiply with negation.
1720 (define_insn "*muls<u>_di"
1721 [(set (match_operand:DI 0 "register_operand" "=x")
1724 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1725 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1726 "!TARGET_64BIT && ISA_HAS_MULS"
1728 [(set_attr "type" "imul")
1729 (set_attr "mode" "SI")])
1731 (define_insn "<u>msubsidi4"
1732 [(set (match_operand:DI 0 "register_operand" "=ka")
1734 (match_operand:DI 3 "register_operand" "0")
1736 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1737 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1738 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)"
1741 return "msub<u>\t%q0,%1,%2";
1742 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
1743 return "msub<u>\t%1,%2";
1745 return "msac<u>\t$0,%1,%2";
1747 [(set_attr "type" "imadd")
1748 (set_attr "mode" "SI")])
1750 ;; _highpart patterns
1752 (define_expand "<su>mulsi3_highpart"
1753 [(set (match_operand:SI 0 "register_operand")
1756 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1757 (any_extend:DI (match_operand:SI 2 "register_operand")))
1759 "ISA_HAS_MULHI || !TARGET_FIX_R4000"
1762 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1766 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1771 (define_insn "<su>mulsi3_highpart_internal"
1772 [(set (match_operand:SI 0 "register_operand" "=h")
1775 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1776 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1778 (clobber (match_scratch:SI 3 "=l"))]
1779 "!ISA_HAS_MULHI && !TARGET_FIX_R4000"
1781 [(set_attr "type" "imul")
1782 (set_attr "mode" "SI")])
1784 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1785 [(set (match_operand:SI 0 "register_operand" "=h,d")
1789 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1790 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d")))
1792 (clobber (match_scratch:SI 3 "=l,l"))
1793 (clobber (match_scratch:SI 4 "=X,h"))]
1798 [(set_attr "type" "imul,imul3")
1799 (set_attr "mode" "SI")])
1801 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1802 [(set (match_operand:SI 0 "register_operand" "=h,d")
1807 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1808 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d"))))
1810 (clobber (match_scratch:SI 3 "=l,l"))
1811 (clobber (match_scratch:SI 4 "=X,h"))]
1815 mulshi<u>\t%0,%1,%2"
1816 [(set_attr "type" "imul,imul3")
1817 (set_attr "mode" "SI")])
1819 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1820 ;; errata MD(0), which says that dmultu does not always produce the
1822 (define_insn "<su>muldi3_highpart"
1823 [(set (match_operand:DI 0 "register_operand" "=h")
1827 (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1828 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1830 (clobber (match_scratch:DI 3 "=l"))]
1831 "TARGET_64BIT && !TARGET_FIX_R4000
1832 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1834 [(set_attr "type" "imul")
1835 (set_attr "mode" "DI")])
1837 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
1838 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
1840 (define_insn "madsi"
1841 [(set (match_operand:SI 0 "register_operand" "+l")
1842 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1843 (match_operand:SI 2 "register_operand" "d"))
1845 (clobber (match_scratch:SI 3 "=h"))]
1848 [(set_attr "type" "imadd")
1849 (set_attr "mode" "SI")])
1851 (define_insn "<u>maddsidi4"
1852 [(set (match_operand:DI 0 "register_operand" "=ka")
1854 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1855 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1856 (match_operand:DI 3 "register_operand" "0")))]
1857 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)
1861 return "mad<u>\t%1,%2";
1862 else if (ISA_HAS_DSPR2)
1863 return "madd<u>\t%q0,%1,%2";
1864 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
1865 return "madd<u>\t%1,%2";
1867 /* See comment in *macc. */
1868 return "%[macc<u>\t%@,%1,%2%]";
1870 [(set_attr "type" "imadd")
1871 (set_attr "mode" "SI")])
1873 ;; Floating point multiply accumulate instructions.
1875 (define_insn "*madd<mode>"
1876 [(set (match_operand:ANYF 0 "register_operand" "=f")
1877 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1878 (match_operand:ANYF 2 "register_operand" "f"))
1879 (match_operand:ANYF 3 "register_operand" "f")))]
1880 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1881 "madd.<fmt>\t%0,%3,%1,%2"
1882 [(set_attr "type" "fmadd")
1883 (set_attr "mode" "<UNITMODE>")])
1885 (define_insn "*msub<mode>"
1886 [(set (match_operand:ANYF 0 "register_operand" "=f")
1887 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1888 (match_operand:ANYF 2 "register_operand" "f"))
1889 (match_operand:ANYF 3 "register_operand" "f")))]
1890 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1891 "msub.<fmt>\t%0,%3,%1,%2"
1892 [(set_attr "type" "fmadd")
1893 (set_attr "mode" "<UNITMODE>")])
1895 (define_insn "*nmadd<mode>"
1896 [(set (match_operand:ANYF 0 "register_operand" "=f")
1897 (neg:ANYF (plus:ANYF
1898 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1899 (match_operand:ANYF 2 "register_operand" "f"))
1900 (match_operand:ANYF 3 "register_operand" "f"))))]
1901 "ISA_HAS_NMADD_NMSUB (<MODE>mode)
1902 && TARGET_FUSED_MADD
1903 && HONOR_SIGNED_ZEROS (<MODE>mode)
1904 && !HONOR_NANS (<MODE>mode)"
1905 "nmadd.<fmt>\t%0,%3,%1,%2"
1906 [(set_attr "type" "fmadd")
1907 (set_attr "mode" "<UNITMODE>")])
1909 (define_insn "*nmadd<mode>_fastmath"
1910 [(set (match_operand:ANYF 0 "register_operand" "=f")
1912 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
1913 (match_operand:ANYF 2 "register_operand" "f"))
1914 (match_operand:ANYF 3 "register_operand" "f")))]
1915 "ISA_HAS_NMADD_NMSUB (<MODE>mode)
1916 && TARGET_FUSED_MADD
1917 && !HONOR_SIGNED_ZEROS (<MODE>mode)
1918 && !HONOR_NANS (<MODE>mode)"
1919 "nmadd.<fmt>\t%0,%3,%1,%2"
1920 [(set_attr "type" "fmadd")
1921 (set_attr "mode" "<UNITMODE>")])
1923 (define_insn "*nmsub<mode>"
1924 [(set (match_operand:ANYF 0 "register_operand" "=f")
1925 (neg:ANYF (minus:ANYF
1926 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1927 (match_operand:ANYF 3 "register_operand" "f"))
1928 (match_operand:ANYF 1 "register_operand" "f"))))]
1929 "ISA_HAS_NMADD_NMSUB (<MODE>mode)
1930 && TARGET_FUSED_MADD
1931 && HONOR_SIGNED_ZEROS (<MODE>mode)
1932 && !HONOR_NANS (<MODE>mode)"
1933 "nmsub.<fmt>\t%0,%1,%2,%3"
1934 [(set_attr "type" "fmadd")
1935 (set_attr "mode" "<UNITMODE>")])
1937 (define_insn "*nmsub<mode>_fastmath"
1938 [(set (match_operand:ANYF 0 "register_operand" "=f")
1940 (match_operand:ANYF 1 "register_operand" "f")
1941 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1942 (match_operand:ANYF 3 "register_operand" "f"))))]
1943 "ISA_HAS_NMADD_NMSUB (<MODE>mode)
1944 && TARGET_FUSED_MADD
1945 && !HONOR_SIGNED_ZEROS (<MODE>mode)
1946 && !HONOR_NANS (<MODE>mode)"
1947 "nmsub.<fmt>\t%0,%1,%2,%3"
1948 [(set_attr "type" "fmadd")
1949 (set_attr "mode" "<UNITMODE>")])
1952 ;; ....................
1954 ;; DIVISION and REMAINDER
1956 ;; ....................
1959 (define_expand "div<mode>3"
1960 [(set (match_operand:ANYF 0 "register_operand")
1961 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
1962 (match_operand:ANYF 2 "register_operand")))]
1963 "<divide_condition>"
1965 if (const_1_operand (operands[1], <MODE>mode))
1966 if (!(<recip_condition> && flag_unsafe_math_optimizations))
1967 operands[1] = force_reg (<MODE>mode, operands[1]);
1970 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
1972 ;; If an mfc1 or dmfc1 happens to access the floating point register
1973 ;; file at the same time a long latency operation (div, sqrt, recip,
1974 ;; sqrt) iterates an intermediate result back through the floating
1975 ;; point register file bypass, then instead returning the correct
1976 ;; register value the mfc1 or dmfc1 operation returns the intermediate
1977 ;; result of the long latency operation.
1979 ;; The workaround is to insert an unconditional 'mov' from/to the
1980 ;; long latency op destination register.
1982 (define_insn "*div<mode>3"
1983 [(set (match_operand:ANYF 0 "register_operand" "=f")
1984 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
1985 (match_operand:ANYF 2 "register_operand" "f")))]
1986 "<divide_condition>"
1989 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
1991 return "div.<fmt>\t%0,%1,%2";
1993 [(set_attr "type" "fdiv")
1994 (set_attr "mode" "<UNITMODE>")
1995 (set (attr "length")
1996 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2000 (define_insn "*recip<mode>3"
2001 [(set (match_operand:ANYF 0 "register_operand" "=f")
2002 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2003 (match_operand:ANYF 2 "register_operand" "f")))]
2004 "<recip_condition> && flag_unsafe_math_optimizations"
2007 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2009 return "recip.<fmt>\t%0,%2";
2011 [(set_attr "type" "frdiv")
2012 (set_attr "mode" "<UNITMODE>")
2013 (set (attr "length")
2014 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2018 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
2019 ;; with negative operands. We use special libgcc functions instead.
2020 (define_insn "divmod<mode>4"
2021 [(set (match_operand:GPR 0 "register_operand" "=l")
2022 (div:GPR (match_operand:GPR 1 "register_operand" "d")
2023 (match_operand:GPR 2 "register_operand" "d")))
2024 (set (match_operand:GPR 3 "register_operand" "=h")
2025 (mod:GPR (match_dup 1)
2027 "!TARGET_FIX_VR4120"
2028 { return mips_output_division ("<d>div\t$0,%1,%2", operands); }
2029 [(set_attr "type" "idiv")
2030 (set_attr "mode" "<MODE>")])
2032 (define_insn "udivmod<mode>4"
2033 [(set (match_operand:GPR 0 "register_operand" "=l")
2034 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2035 (match_operand:GPR 2 "register_operand" "d")))
2036 (set (match_operand:GPR 3 "register_operand" "=h")
2037 (umod:GPR (match_dup 1)
2040 { return mips_output_division ("<d>divu\t$0,%1,%2", operands); }
2041 [(set_attr "type" "idiv")
2042 (set_attr "mode" "<MODE>")])
2045 ;; ....................
2049 ;; ....................
2051 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
2052 ;; "*div[sd]f3" comment for details).
2054 (define_insn "sqrt<mode>2"
2055 [(set (match_operand:ANYF 0 "register_operand" "=f")
2056 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2060 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
2062 return "sqrt.<fmt>\t%0,%1";
2064 [(set_attr "type" "fsqrt")
2065 (set_attr "mode" "<UNITMODE>")
2066 (set (attr "length")
2067 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2071 (define_insn "*rsqrt<mode>a"
2072 [(set (match_operand:ANYF 0 "register_operand" "=f")
2073 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2074 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
2075 "<recip_condition> && flag_unsafe_math_optimizations"
2078 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2080 return "rsqrt.<fmt>\t%0,%2";
2082 [(set_attr "type" "frsqrt")
2083 (set_attr "mode" "<UNITMODE>")
2084 (set (attr "length")
2085 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2089 (define_insn "*rsqrt<mode>b"
2090 [(set (match_operand:ANYF 0 "register_operand" "=f")
2091 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2092 (match_operand:ANYF 2 "register_operand" "f"))))]
2093 "<recip_condition> && flag_unsafe_math_optimizations"
2096 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2098 return "rsqrt.<fmt>\t%0,%2";
2100 [(set_attr "type" "frsqrt")
2101 (set_attr "mode" "<UNITMODE>")
2102 (set (attr "length")
2103 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2108 ;; ....................
2112 ;; ....................
2114 ;; Do not use the integer abs macro instruction, since that signals an
2115 ;; exception on -2147483648 (sigh).
2117 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2118 ;; invalid; it does not clear their sign bits. We therefore can't use
2119 ;; abs.fmt if the signs of NaNs matter.
2121 (define_insn "abs<mode>2"
2122 [(set (match_operand:ANYF 0 "register_operand" "=f")
2123 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2124 "!HONOR_NANS (<MODE>mode)"
2126 [(set_attr "type" "fabs")
2127 (set_attr "mode" "<UNITMODE>")])
2130 ;; ...................
2132 ;; Count leading zeroes.
2134 ;; ...................
2137 (define_insn "clz<mode>2"
2138 [(set (match_operand:GPR 0 "register_operand" "=d")
2139 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2142 [(set_attr "type" "clz")
2143 (set_attr "mode" "<MODE>")])
2146 ;; ....................
2148 ;; NEGATION and ONE'S COMPLEMENT
2150 ;; ....................
2152 (define_insn "negsi2"
2153 [(set (match_operand:SI 0 "register_operand" "=d")
2154 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2158 return "neg\t%0,%1";
2160 return "subu\t%0,%.,%1";
2162 [(set_attr "type" "arith")
2163 (set_attr "mode" "SI")])
2165 (define_insn "negdi2"
2166 [(set (match_operand:DI 0 "register_operand" "=d")
2167 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2168 "TARGET_64BIT && !TARGET_MIPS16"
2170 [(set_attr "type" "arith")
2171 (set_attr "mode" "DI")])
2173 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2174 ;; invalid; it does not flip their sign bit. We therefore can't use
2175 ;; neg.fmt if the signs of NaNs matter.
2177 (define_insn "neg<mode>2"
2178 [(set (match_operand:ANYF 0 "register_operand" "=f")
2179 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2180 "!HONOR_NANS (<MODE>mode)"
2182 [(set_attr "type" "fneg")
2183 (set_attr "mode" "<UNITMODE>")])
2185 (define_insn "one_cmpl<mode>2"
2186 [(set (match_operand:GPR 0 "register_operand" "=d")
2187 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2191 return "not\t%0,%1";
2193 return "nor\t%0,%.,%1";
2195 [(set_attr "type" "logical")
2196 (set_attr "mode" "<MODE>")])
2199 ;; ....................
2203 ;; ....................
2206 ;; Many of these instructions use trivial define_expands, because we
2207 ;; want to use a different set of constraints when TARGET_MIPS16.
2209 (define_expand "and<mode>3"
2210 [(set (match_operand:GPR 0 "register_operand")
2211 (and:GPR (match_operand:GPR 1 "register_operand")
2212 (match_operand:GPR 2 "uns_arith_operand")))]
2216 operands[2] = force_reg (<MODE>mode, operands[2]);
2219 (define_insn "*and<mode>3"
2220 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2221 (and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2222 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2227 [(set_attr "type" "logical")
2228 (set_attr "mode" "<MODE>")])
2230 (define_insn "*and<mode>3_mips16"
2231 [(set (match_operand:GPR 0 "register_operand" "=d")
2232 (and:GPR (match_operand:GPR 1 "register_operand" "%0")
2233 (match_operand:GPR 2 "register_operand" "d")))]
2236 [(set_attr "type" "logical")
2237 (set_attr "mode" "<MODE>")])
2239 (define_expand "ior<mode>3"
2240 [(set (match_operand:GPR 0 "register_operand")
2241 (ior:GPR (match_operand:GPR 1 "register_operand")
2242 (match_operand:GPR 2 "uns_arith_operand")))]
2246 operands[2] = force_reg (<MODE>mode, operands[2]);
2249 (define_insn "*ior<mode>3"
2250 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2251 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2252 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2257 [(set_attr "type" "logical")
2258 (set_attr "mode" "<MODE>")])
2260 (define_insn "*ior<mode>3_mips16"
2261 [(set (match_operand:GPR 0 "register_operand" "=d")
2262 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2263 (match_operand:GPR 2 "register_operand" "d")))]
2266 [(set_attr "type" "logical")
2267 (set_attr "mode" "<MODE>")])
2269 (define_expand "xor<mode>3"
2270 [(set (match_operand:GPR 0 "register_operand")
2271 (xor:GPR (match_operand:GPR 1 "register_operand")
2272 (match_operand:GPR 2 "uns_arith_operand")))]
2277 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2278 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2279 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2284 [(set_attr "type" "logical")
2285 (set_attr "mode" "<MODE>")])
2288 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2289 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2290 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2296 [(set_attr "type" "logical,arith,arith")
2297 (set_attr "mode" "<MODE>")
2298 (set_attr_alternative "length"
2300 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2305 (define_insn "*nor<mode>3"
2306 [(set (match_operand:GPR 0 "register_operand" "=d")
2307 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2308 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2311 [(set_attr "type" "logical")
2312 (set_attr "mode" "<MODE>")])
2315 ;; ....................
2319 ;; ....................
2323 (define_insn "truncdfsf2"
2324 [(set (match_operand:SF 0 "register_operand" "=f")
2325 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2326 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2328 [(set_attr "type" "fcvt")
2329 (set_attr "cnv_mode" "D2S")
2330 (set_attr "mode" "SF")])
2332 ;; Integer truncation patterns. Truncating SImode values to smaller
2333 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2334 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2335 ;; need to make sure that the lower 32 bits are properly sign-extended
2336 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2337 ;; smaller than SImode is equivalent to two separate truncations:
2340 ;; DI ---> HI == DI ---> SI ---> HI
2341 ;; DI ---> QI == DI ---> SI ---> QI
2343 ;; Step A needs a real instruction but step B does not.
2345 (define_insn "truncdisi2"
2346 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
2347 (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))]
2352 [(set_attr "type" "shift,store")
2353 (set_attr "mode" "SI")
2354 (set_attr "extended_mips16" "yes,*")])
2356 (define_insn "truncdihi2"
2357 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
2358 (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))]
2363 [(set_attr "type" "shift,store")
2364 (set_attr "mode" "SI")
2365 (set_attr "extended_mips16" "yes,*")])
2367 (define_insn "truncdiqi2"
2368 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
2369 (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))]
2374 [(set_attr "type" "shift,store")
2375 (set_attr "mode" "SI")
2376 (set_attr "extended_mips16" "yes,*")])
2378 ;; Combiner patterns to optimize shift/truncate combinations.
2381 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2383 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2384 (match_operand:DI 2 "const_arith_operand" ""))))]
2385 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
2387 [(set_attr "type" "shift")
2388 (set_attr "mode" "SI")])
2391 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2393 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2395 "TARGET_64BIT && !TARGET_MIPS16"
2397 [(set_attr "type" "shift")
2398 (set_attr "mode" "SI")])
2401 ;; Combiner patterns for truncate/sign_extend combinations. The SI versions
2402 ;; use the shift/truncate patterns above.
2404 (define_insn_and_split "*extenddi_truncate<mode>"
2405 [(set (match_operand:DI 0 "register_operand" "=d")
2407 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
2408 "TARGET_64BIT && !TARGET_MIPS16"
2410 "&& reload_completed"
2412 (ashift:DI (match_dup 1)
2415 (ashiftrt:DI (match_dup 2)
2418 operands[2] = gen_lowpart (DImode, operands[0]);
2419 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
2422 (define_insn_and_split "*extendsi_truncate<mode>"
2423 [(set (match_operand:SI 0 "register_operand" "=d")
2425 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
2426 "TARGET_64BIT && !TARGET_MIPS16"
2428 "&& reload_completed"
2430 (ashift:DI (match_dup 1)
2433 (truncate:SI (ashiftrt:DI (match_dup 2)
2436 operands[2] = gen_lowpart (DImode, operands[0]);
2437 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
2440 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2442 (define_insn "*zero_extend<mode>_trunchi"
2443 [(set (match_operand:GPR 0 "register_operand" "=d")
2445 (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
2446 "TARGET_64BIT && !TARGET_MIPS16"
2447 "andi\t%0,%1,0xffff"
2448 [(set_attr "type" "logical")
2449 (set_attr "mode" "<MODE>")])
2451 (define_insn "*zero_extend<mode>_truncqi"
2452 [(set (match_operand:GPR 0 "register_operand" "=d")
2454 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2455 "TARGET_64BIT && !TARGET_MIPS16"
2457 [(set_attr "type" "logical")
2458 (set_attr "mode" "<MODE>")])
2461 [(set (match_operand:HI 0 "register_operand" "=d")
2463 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2464 "TARGET_64BIT && !TARGET_MIPS16"
2466 [(set_attr "type" "logical")
2467 (set_attr "mode" "HI")])
2470 ;; ....................
2474 ;; ....................
2478 (define_insn_and_split "zero_extendsidi2"
2479 [(set (match_operand:DI 0 "register_operand" "=d,d")
2480 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2485 "&& reload_completed && REG_P (operands[1])"
2487 (ashift:DI (match_dup 1) (const_int 32)))
2489 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2490 { operands[1] = gen_lowpart (DImode, operands[1]); }
2491 [(set_attr "type" "multi,load")
2492 (set_attr "mode" "DI")
2493 (set_attr "length" "8,*")])
2495 ;; Combine is not allowed to convert this insn into a zero_extendsidi2
2496 ;; because of TRULY_NOOP_TRUNCATION.
2498 (define_insn_and_split "*clear_upper32"
2499 [(set (match_operand:DI 0 "register_operand" "=d,d")
2500 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,W")
2501 (const_int 4294967295)))]
2504 if (which_alternative == 0)
2507 operands[1] = gen_lowpart (SImode, operands[1]);
2508 return "lwu\t%0,%1";
2510 "&& reload_completed && REG_P (operands[1])"
2512 (ashift:DI (match_dup 1) (const_int 32)))
2514 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2516 [(set_attr "type" "multi,load")
2517 (set_attr "mode" "DI")
2518 (set_attr "length" "8,*")])
2520 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2521 [(set (match_operand:GPR 0 "register_operand")
2522 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2525 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2526 && !memory_operand (operands[1], <SHORT:MODE>mode))
2528 emit_insn (gen_and<GPR:mode>3 (operands[0],
2529 gen_lowpart (<GPR:MODE>mode, operands[1]),
2530 force_reg (<GPR:MODE>mode,
2531 GEN_INT (<SHORT:mask>))));
2536 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2537 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2539 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2542 andi\t%0,%1,<SHORT:mask>
2543 l<SHORT:size>u\t%0,%1"
2544 [(set_attr "type" "logical,load")
2545 (set_attr "mode" "<GPR:MODE>")])
2547 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
2548 [(set (match_operand:GPR 0 "register_operand" "=d")
2549 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
2551 "ze<SHORT:size>\t%0"
2552 [(set_attr "type" "arith")
2553 (set_attr "mode" "<GPR:MODE>")])
2555 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2556 [(set (match_operand:GPR 0 "register_operand" "=d")
2557 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2559 "l<SHORT:size>u\t%0,%1"
2560 [(set_attr "type" "load")
2561 (set_attr "mode" "<GPR:MODE>")])
2563 (define_expand "zero_extendqihi2"
2564 [(set (match_operand:HI 0 "register_operand")
2565 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2568 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2570 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2576 (define_insn "*zero_extendqihi2"
2577 [(set (match_operand:HI 0 "register_operand" "=d,d")
2578 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2583 [(set_attr "type" "logical,load")
2584 (set_attr "mode" "HI")])
2586 (define_insn "*zero_extendqihi2_mips16"
2587 [(set (match_operand:HI 0 "register_operand" "=d")
2588 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2591 [(set_attr "type" "load")
2592 (set_attr "mode" "HI")])
2595 ;; ....................
2599 ;; ....................
2602 ;; Those for integer source operand are ordered widest source type first.
2604 ;; When TARGET_64BIT, all SImode integer registers should already be in
2605 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2606 ;; therefore get rid of register->register instructions if we constrain
2607 ;; the source to be in the same register as the destination.
2609 ;; The register alternative has type "arith" so that the pre-reload
2610 ;; scheduler will treat it as a move. This reflects what happens if
2611 ;; the register alternative needs a reload.
2612 (define_insn_and_split "extendsidi2"
2613 [(set (match_operand:DI 0 "register_operand" "=d,d")
2614 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2619 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2622 emit_note (NOTE_INSN_DELETED);
2625 [(set_attr "type" "arith,load")
2626 (set_attr "mode" "DI")])
2628 (define_expand "extend<SHORT:mode><GPR:mode>2"
2629 [(set (match_operand:GPR 0 "register_operand")
2630 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2633 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
2634 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2635 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
2639 l<SHORT:size>\t%0,%1"
2640 [(set_attr "type" "signext,load")
2641 (set_attr "mode" "<GPR:MODE>")])
2643 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
2644 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2646 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2647 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2650 l<SHORT:size>\t%0,%1"
2651 "&& reload_completed && REG_P (operands[1])"
2652 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
2653 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
2655 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
2656 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
2657 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
2659 [(set_attr "type" "arith,load")
2660 (set_attr "mode" "<GPR:MODE>")
2661 (set_attr "length" "8,*")])
2663 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
2664 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2666 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2669 se<SHORT:size>\t%0,%1
2670 l<SHORT:size>\t%0,%1"
2671 [(set_attr "type" "signext,load")
2672 (set_attr "mode" "<GPR:MODE>")])
2674 (define_expand "extendqihi2"
2675 [(set (match_operand:HI 0 "register_operand")
2676 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2679 (define_insn "*extendqihi2_mips16e"
2680 [(set (match_operand:HI 0 "register_operand" "=d,d")
2681 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
2686 [(set_attr "type" "signext,load")
2687 (set_attr "mode" "SI")])
2689 (define_insn_and_split "*extendqihi2"
2690 [(set (match_operand:HI 0 "register_operand" "=d,d")
2692 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2693 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2697 "&& reload_completed && REG_P (operands[1])"
2698 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
2699 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
2701 operands[0] = gen_lowpart (SImode, operands[0]);
2702 operands[1] = gen_lowpart (SImode, operands[1]);
2703 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
2704 - GET_MODE_BITSIZE (QImode));
2706 [(set_attr "type" "multi,load")
2707 (set_attr "mode" "SI")
2708 (set_attr "length" "8,*")])
2710 (define_insn "*extendqihi2_seb"
2711 [(set (match_operand:HI 0 "register_operand" "=d,d")
2713 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2718 [(set_attr "type" "signext,load")
2719 (set_attr "mode" "SI")])
2721 (define_insn "extendsfdf2"
2722 [(set (match_operand:DF 0 "register_operand" "=f")
2723 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2724 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2726 [(set_attr "type" "fcvt")
2727 (set_attr "cnv_mode" "S2D")
2728 (set_attr "mode" "DF")])
2731 ;; ....................
2735 ;; ....................
2737 (define_expand "fix_truncdfsi2"
2738 [(set (match_operand:SI 0 "register_operand")
2739 (fix:SI (match_operand:DF 1 "register_operand")))]
2740 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2742 if (!ISA_HAS_TRUNC_W)
2744 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
2749 (define_insn "fix_truncdfsi2_insn"
2750 [(set (match_operand:SI 0 "register_operand" "=f")
2751 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
2752 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
2754 [(set_attr "type" "fcvt")
2755 (set_attr "mode" "DF")
2756 (set_attr "cnv_mode" "D2I")
2757 (set_attr "length" "4")])
2759 (define_insn "fix_truncdfsi2_macro"
2760 [(set (match_operand:SI 0 "register_operand" "=f")
2761 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2762 (clobber (match_scratch:DF 2 "=d"))]
2763 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
2766 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
2768 return "trunc.w.d %0,%1,%2";
2770 [(set_attr "type" "fcvt")
2771 (set_attr "mode" "DF")
2772 (set_attr "cnv_mode" "D2I")
2773 (set_attr "length" "36")])
2775 (define_expand "fix_truncsfsi2"
2776 [(set (match_operand:SI 0 "register_operand")
2777 (fix:SI (match_operand:SF 1 "register_operand")))]
2780 if (!ISA_HAS_TRUNC_W)
2782 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
2787 (define_insn "fix_truncsfsi2_insn"
2788 [(set (match_operand:SI 0 "register_operand" "=f")
2789 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
2790 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
2792 [(set_attr "type" "fcvt")
2793 (set_attr "mode" "SF")
2794 (set_attr "cnv_mode" "S2I")
2795 (set_attr "length" "4")])
2797 (define_insn "fix_truncsfsi2_macro"
2798 [(set (match_operand:SI 0 "register_operand" "=f")
2799 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2800 (clobber (match_scratch:SF 2 "=d"))]
2801 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
2804 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
2806 return "trunc.w.s %0,%1,%2";
2808 [(set_attr "type" "fcvt")
2809 (set_attr "mode" "SF")
2810 (set_attr "cnv_mode" "S2I")
2811 (set_attr "length" "36")])
2814 (define_insn "fix_truncdfdi2"
2815 [(set (match_operand:DI 0 "register_operand" "=f")
2816 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
2817 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2819 [(set_attr "type" "fcvt")
2820 (set_attr "mode" "DF")
2821 (set_attr "cnv_mode" "D2I")
2822 (set_attr "length" "4")])
2825 (define_insn "fix_truncsfdi2"
2826 [(set (match_operand:DI 0 "register_operand" "=f")
2827 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
2828 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2830 [(set_attr "type" "fcvt")
2831 (set_attr "mode" "SF")
2832 (set_attr "cnv_mode" "S2I")
2833 (set_attr "length" "4")])
2836 (define_insn "floatsidf2"
2837 [(set (match_operand:DF 0 "register_operand" "=f")
2838 (float:DF (match_operand:SI 1 "register_operand" "f")))]
2839 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2841 [(set_attr "type" "fcvt")
2842 (set_attr "mode" "DF")
2843 (set_attr "cnv_mode" "I2D")
2844 (set_attr "length" "4")])
2847 (define_insn "floatdidf2"
2848 [(set (match_operand:DF 0 "register_operand" "=f")
2849 (float:DF (match_operand:DI 1 "register_operand" "f")))]
2850 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2852 [(set_attr "type" "fcvt")
2853 (set_attr "mode" "DF")
2854 (set_attr "cnv_mode" "I2D")
2855 (set_attr "length" "4")])
2858 (define_insn "floatsisf2"
2859 [(set (match_operand:SF 0 "register_operand" "=f")
2860 (float:SF (match_operand:SI 1 "register_operand" "f")))]
2863 [(set_attr "type" "fcvt")
2864 (set_attr "mode" "SF")
2865 (set_attr "cnv_mode" "I2S")
2866 (set_attr "length" "4")])
2869 (define_insn "floatdisf2"
2870 [(set (match_operand:SF 0 "register_operand" "=f")
2871 (float:SF (match_operand:DI 1 "register_operand" "f")))]
2872 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2874 [(set_attr "type" "fcvt")
2875 (set_attr "mode" "SF")
2876 (set_attr "cnv_mode" "I2S")
2877 (set_attr "length" "4")])
2880 (define_expand "fixuns_truncdfsi2"
2881 [(set (match_operand:SI 0 "register_operand")
2882 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
2883 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2885 rtx reg1 = gen_reg_rtx (DFmode);
2886 rtx reg2 = gen_reg_rtx (DFmode);
2887 rtx reg3 = gen_reg_rtx (SImode);
2888 rtx label1 = gen_label_rtx ();
2889 rtx label2 = gen_label_rtx ();
2890 REAL_VALUE_TYPE offset;
2892 real_2expN (&offset, 31, DFmode);
2894 if (reg1) /* Turn off complaints about unreached code. */
2896 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2897 do_pending_stack_adjust ();
2899 emit_insn (gen_cmpdf (operands[1], reg1));
2900 emit_jump_insn (gen_bge (label1));
2902 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
2903 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2904 gen_rtx_LABEL_REF (VOIDmode, label2)));
2907 emit_label (label1);
2908 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2909 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
2910 (BITMASK_HIGH, SImode)));
2912 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
2913 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2915 emit_label (label2);
2917 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2918 fields, and can't be used for REG_NOTES anyway). */
2919 emit_use (stack_pointer_rtx);
2925 (define_expand "fixuns_truncdfdi2"
2926 [(set (match_operand:DI 0 "register_operand")
2927 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
2928 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2930 rtx reg1 = gen_reg_rtx (DFmode);
2931 rtx reg2 = gen_reg_rtx (DFmode);
2932 rtx reg3 = gen_reg_rtx (DImode);
2933 rtx label1 = gen_label_rtx ();
2934 rtx label2 = gen_label_rtx ();
2935 REAL_VALUE_TYPE offset;
2937 real_2expN (&offset, 63, DFmode);
2939 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2940 do_pending_stack_adjust ();
2942 emit_insn (gen_cmpdf (operands[1], reg1));
2943 emit_jump_insn (gen_bge (label1));
2945 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
2946 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2947 gen_rtx_LABEL_REF (VOIDmode, label2)));
2950 emit_label (label1);
2951 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2952 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
2953 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2955 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
2956 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2958 emit_label (label2);
2960 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2961 fields, and can't be used for REG_NOTES anyway). */
2962 emit_use (stack_pointer_rtx);
2967 (define_expand "fixuns_truncsfsi2"
2968 [(set (match_operand:SI 0 "register_operand")
2969 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
2972 rtx reg1 = gen_reg_rtx (SFmode);
2973 rtx reg2 = gen_reg_rtx (SFmode);
2974 rtx reg3 = gen_reg_rtx (SImode);
2975 rtx label1 = gen_label_rtx ();
2976 rtx label2 = gen_label_rtx ();
2977 REAL_VALUE_TYPE offset;
2979 real_2expN (&offset, 31, SFmode);
2981 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2982 do_pending_stack_adjust ();
2984 emit_insn (gen_cmpsf (operands[1], reg1));
2985 emit_jump_insn (gen_bge (label1));
2987 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
2988 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2989 gen_rtx_LABEL_REF (VOIDmode, label2)));
2992 emit_label (label1);
2993 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2994 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
2995 (BITMASK_HIGH, SImode)));
2997 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
2998 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3000 emit_label (label2);
3002 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3003 fields, and can't be used for REG_NOTES anyway). */
3004 emit_use (stack_pointer_rtx);
3009 (define_expand "fixuns_truncsfdi2"
3010 [(set (match_operand:DI 0 "register_operand")
3011 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
3012 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3014 rtx reg1 = gen_reg_rtx (SFmode);
3015 rtx reg2 = gen_reg_rtx (SFmode);
3016 rtx reg3 = gen_reg_rtx (DImode);
3017 rtx label1 = gen_label_rtx ();
3018 rtx label2 = gen_label_rtx ();
3019 REAL_VALUE_TYPE offset;
3021 real_2expN (&offset, 63, SFmode);
3023 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3024 do_pending_stack_adjust ();
3026 emit_insn (gen_cmpsf (operands[1], reg1));
3027 emit_jump_insn (gen_bge (label1));
3029 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
3030 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3031 gen_rtx_LABEL_REF (VOIDmode, label2)));
3034 emit_label (label1);
3035 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3036 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3037 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3039 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
3040 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3042 emit_label (label2);
3044 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3045 fields, and can't be used for REG_NOTES anyway). */
3046 emit_use (stack_pointer_rtx);
3051 ;; ....................
3055 ;; ....................
3057 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
3059 (define_expand "extv"
3060 [(set (match_operand 0 "register_operand")
3061 (sign_extract (match_operand:QI 1 "memory_operand")
3062 (match_operand 2 "immediate_operand")
3063 (match_operand 3 "immediate_operand")))]
3066 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3067 INTVAL (operands[2]),
3068 INTVAL (operands[3])))
3074 (define_expand "extzv"
3075 [(set (match_operand 0 "register_operand")
3076 (zero_extract (match_operand 1 "nonimmediate_operand")
3077 (match_operand 2 "immediate_operand")
3078 (match_operand 3 "immediate_operand")))]
3081 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3082 INTVAL (operands[2]),
3083 INTVAL (operands[3])))
3085 else if (mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3086 INTVAL (operands[3])))
3088 if (GET_MODE (operands[0]) == DImode)
3089 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
3092 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
3100 (define_insn "extzv<mode>"
3101 [(set (match_operand:GPR 0 "register_operand" "=d")
3102 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3103 (match_operand:SI 2 "immediate_operand" "I")
3104 (match_operand:SI 3 "immediate_operand" "I")))]
3105 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3106 INTVAL (operands[3]))"
3107 "<d>ext\t%0,%1,%3,%2"
3108 [(set_attr "type" "arith")
3109 (set_attr "mode" "<MODE>")])
3112 (define_expand "insv"
3113 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
3114 (match_operand 1 "immediate_operand")
3115 (match_operand 2 "immediate_operand"))
3116 (match_operand 3 "reg_or_0_operand"))]
3119 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
3120 INTVAL (operands[1]),
3121 INTVAL (operands[2])))
3123 else if (mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3124 INTVAL (operands[2])))
3126 if (GET_MODE (operands[0]) == DImode)
3127 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
3130 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
3138 (define_insn "insv<mode>"
3139 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3140 (match_operand:SI 1 "immediate_operand" "I")
3141 (match_operand:SI 2 "immediate_operand" "I"))
3142 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3143 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3144 INTVAL (operands[2]))"
3145 "<d>ins\t%0,%z3,%2,%1"
3146 [(set_attr "type" "arith")
3147 (set_attr "mode" "<MODE>")])
3149 ;; Unaligned word moves generated by the bit field patterns.
3151 ;; As far as the rtl is concerned, both the left-part and right-part
3152 ;; instructions can access the whole field. However, the real operand
3153 ;; refers to just the first or the last byte (depending on endianness).
3154 ;; We therefore use two memory operands to each instruction, one to
3155 ;; describe the rtl effect and one to use in the assembly output.
3157 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3158 ;; This allows us to use the standard length calculations for the "load"
3159 ;; and "store" type attributes.
3161 (define_insn "mov_<load>l"
3162 [(set (match_operand:GPR 0 "register_operand" "=d")
3163 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3164 (match_operand:QI 2 "memory_operand" "m")]
3166 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3168 [(set_attr "type" "load")
3169 (set_attr "mode" "<MODE>")])
3171 (define_insn "mov_<load>r"
3172 [(set (match_operand:GPR 0 "register_operand" "=d")
3173 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3174 (match_operand:QI 2 "memory_operand" "m")
3175 (match_operand:GPR 3 "register_operand" "0")]
3176 UNSPEC_LOAD_RIGHT))]
3177 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3179 [(set_attr "type" "load")
3180 (set_attr "mode" "<MODE>")])
3182 (define_insn "mov_<store>l"
3183 [(set (match_operand:BLK 0 "memory_operand" "=m")
3184 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3185 (match_operand:QI 2 "memory_operand" "m")]
3186 UNSPEC_STORE_LEFT))]
3187 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3189 [(set_attr "type" "store")
3190 (set_attr "mode" "<MODE>")])
3192 (define_insn "mov_<store>r"
3193 [(set (match_operand:BLK 0 "memory_operand" "+m")
3194 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3195 (match_operand:QI 2 "memory_operand" "m")
3197 UNSPEC_STORE_RIGHT))]
3198 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3200 [(set_attr "type" "store")
3201 (set_attr "mode" "<MODE>")])
3203 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
3204 ;; The required value is:
3206 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3208 ;; which translates to:
3210 ;; lui op0,%highest(op1)
3211 ;; daddiu op0,op0,%higher(op1)
3213 ;; daddiu op0,op0,%hi(op1)
3216 ;; The split is deferred until after flow2 to allow the peephole2 below
3218 (define_insn_and_split "*lea_high64"
3219 [(set (match_operand:DI 0 "register_operand" "=d")
3220 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
3221 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3223 "&& epilogue_completed"
3224 [(set (match_dup 0) (high:DI (match_dup 2)))
3225 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3226 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3227 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3228 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3230 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3231 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3233 [(set_attr "length" "20")])
3235 ;; Use a scratch register to reduce the latency of the above pattern
3236 ;; on superscalar machines. The optimized sequence is:
3238 ;; lui op1,%highest(op2)
3240 ;; daddiu op1,op1,%higher(op2)
3242 ;; daddu op1,op1,op0
3244 [(set (match_operand:DI 1 "register_operand")
3245 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
3246 (match_scratch:DI 0 "d")]
3247 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3248 [(set (match_dup 1) (high:DI (match_dup 3)))
3249 (set (match_dup 0) (high:DI (match_dup 4)))
3250 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3251 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3252 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3254 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3255 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3258 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3259 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
3260 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3261 ;; used once. We can then use the sequence:
3263 ;; lui op0,%highest(op1)
3265 ;; daddiu op0,op0,%higher(op1)
3266 ;; daddiu op2,op2,%lo(op1)
3268 ;; daddu op0,op0,op2
3270 ;; which takes 4 cycles on most superscalar targets.
3271 (define_insn_and_split "*lea64"
3272 [(set (match_operand:DI 0 "register_operand" "=d")
3273 (match_operand:DI 1 "absolute_symbolic_operand" ""))
3274 (clobber (match_scratch:DI 2 "=&d"))]
3275 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3277 "&& reload_completed"
3278 [(set (match_dup 0) (high:DI (match_dup 3)))
3279 (set (match_dup 2) (high:DI (match_dup 4)))
3280 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3281 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3282 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3283 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3285 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3286 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3288 [(set_attr "length" "24")])
3290 ;; Split HIGHs into:
3295 ;; on MIPS16 targets.
3297 [(set (match_operand:SI 0 "register_operand" "=d")
3298 (high:SI (match_operand:SI 1 "absolute_symbolic_operand" "")))]
3299 "TARGET_MIPS16 && reload_completed"
3300 [(set (match_dup 0) (match_dup 2))
3301 (set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))]
3303 operands[2] = mips_unspec_address (operands[1], SYMBOL_32_HIGH);
3306 ;; Insns to fetch a symbol from a big GOT.
3308 (define_insn_and_split "*xgot_hi<mode>"
3309 [(set (match_operand:P 0 "register_operand" "=d")
3310 (high:P (match_operand:P 1 "got_disp_operand" "")))]
3311 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3313 "&& reload_completed"
3314 [(set (match_dup 0) (high:P (match_dup 2)))
3315 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3317 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3318 operands[3] = pic_offset_table_rtx;
3320 [(set_attr "got" "xgot_high")
3321 (set_attr "mode" "<MODE>")])
3323 (define_insn_and_split "*xgot_lo<mode>"
3324 [(set (match_operand:P 0 "register_operand" "=d")
3325 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3326 (match_operand:P 2 "got_disp_operand" "")))]
3327 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3329 "&& reload_completed"
3331 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3332 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
3333 [(set_attr "got" "load")
3334 (set_attr "mode" "<MODE>")])
3336 ;; Insns to fetch a symbol from a normal GOT.
3338 (define_insn_and_split "*got_disp<mode>"
3339 [(set (match_operand:P 0 "register_operand" "=d")
3340 (match_operand:P 1 "got_disp_operand" ""))]
3341 "TARGET_EXPLICIT_RELOCS && !TARGET_XGOT"
3343 "&& reload_completed"
3345 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3347 operands[2] = pic_offset_table_rtx;
3348 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3350 [(set_attr "got" "load")
3351 (set_attr "mode" "<MODE>")])
3353 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
3355 (define_insn_and_split "*got_page<mode>"
3356 [(set (match_operand:P 0 "register_operand" "=d")
3357 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
3358 "TARGET_EXPLICIT_RELOCS"
3360 "&& reload_completed"
3362 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3364 operands[2] = pic_offset_table_rtx;
3365 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_PAGE);
3367 [(set_attr "got" "load")
3368 (set_attr "mode" "<MODE>")])
3370 ;; Lower-level instructions for loading an address from the GOT.
3371 ;; We could use MEMs, but an unspec gives more optimization
3374 (define_insn "load_got<mode>"
3375 [(set (match_operand:P 0 "register_operand" "=d")
3376 (unspec:P [(match_operand:P 1 "register_operand" "d")
3377 (match_operand:P 2 "immediate_operand" "")]
3380 "<load>\t%0,%R2(%1)"
3381 [(set_attr "type" "load")
3382 (set_attr "mode" "<MODE>")
3383 (set_attr "length" "4")])
3385 ;; Instructions for adding the low 16 bits of an address to a register.
3386 ;; Operand 2 is the address: mips_print_operand works out which relocation
3387 ;; should be applied.
3389 (define_insn "*low<mode>"
3390 [(set (match_operand:P 0 "register_operand" "=d")
3391 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3392 (match_operand:P 2 "immediate_operand" "")))]
3394 "<d>addiu\t%0,%1,%R2"
3395 [(set_attr "type" "arith")
3396 (set_attr "mode" "<MODE>")])
3398 (define_insn "*low<mode>_mips16"
3399 [(set (match_operand:P 0 "register_operand" "=d")
3400 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3401 (match_operand:P 2 "immediate_operand" "")))]
3404 [(set_attr "type" "arith")
3405 (set_attr "mode" "<MODE>")
3406 (set_attr "length" "8")])
3408 ;; Allow combine to split complex const_int load sequences, using operand 2
3409 ;; to store the intermediate results. See move_operand for details.
3411 [(set (match_operand:GPR 0 "register_operand")
3412 (match_operand:GPR 1 "splittable_const_int_operand"))
3413 (clobber (match_operand:GPR 2 "register_operand"))]
3417 mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
3421 ;; Likewise, for symbolic operands.
3423 [(set (match_operand:P 0 "register_operand")
3424 (match_operand:P 1))
3425 (clobber (match_operand:P 2 "register_operand"))]
3426 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
3427 [(set (match_dup 0) (match_dup 3))]
3429 mips_split_symbol (operands[2], operands[1],
3430 MAX_MACHINE_MODE, &operands[3]);
3433 ;; 64-bit integer moves
3435 ;; Unlike most other insns, the move insns can't be split with
3436 ;; different predicates, because register spilling and other parts of
3437 ;; the compiler, have memoized the insn number already.
3439 (define_expand "movdi"
3440 [(set (match_operand:DI 0 "")
3441 (match_operand:DI 1 ""))]
3444 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3448 ;; For mips16, we need a special case to handle storing $31 into
3449 ;; memory, since we don't have a constraint to match $31. This
3450 ;; instruction can be generated by save_restore_insns.
3452 (define_insn "*mov<mode>_ra"
3453 [(set (match_operand:GPR 0 "stack_operand" "=m")
3457 [(set_attr "type" "store")
3458 (set_attr "mode" "<MODE>")])
3460 (define_insn "*movdi_32bit"
3461 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*B*C*D,*B*C*D,*d,*m")
3462 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3463 "!TARGET_64BIT && !TARGET_FLOAT64 && !TARGET_MIPS16
3464 && (register_operand (operands[0], DImode)
3465 || reg_or_0_operand (operands[1], DImode))"
3466 { return mips_output_move (operands[0], operands[1]); }
3467 [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,load,mfc,store")
3468 (set_attr "mode" "DI")
3469 (set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
3471 (define_insn "*movdi_gp32_fp64"
3472 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*d,*m")
3473 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*J*d,*m,*f,*f"))]
3474 "!TARGET_64BIT && TARGET_FLOAT64 && !TARGET_MIPS16
3475 && (register_operand (operands[0], DImode)
3476 || reg_or_0_operand (operands[1], DImode))"
3477 { return mips_output_move (operands[0], operands[1]); }
3478 [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
3479 (set_attr "mode" "DI")
3480 (set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
3482 (define_insn "*movdi_32bit_mips16"
3483 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3484 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3485 "!TARGET_64BIT && TARGET_MIPS16
3486 && (register_operand (operands[0], DImode)
3487 || register_operand (operands[1], DImode))"
3488 { return mips_output_move (operands[0], operands[1]); }
3489 [(set_attr "type" "multi,multi,multi,multi,multi,load,store,mfhilo")
3490 (set_attr "mode" "DI")
3491 (set_attr "length" "8,8,8,8,12,*,*,8")])
3493 (define_insn "*movdi_64bit"
3494 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m")
3495 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))]
3496 "TARGET_64BIT && !TARGET_MIPS16
3497 && (register_operand (operands[0], DImode)
3498 || reg_or_0_operand (operands[1], DImode))"
3499 { return mips_output_move (operands[0], operands[1]); }
3500 [(set_attr "type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store")
3501 (set_attr "mode" "DI")
3502 (set_attr "length" "4,*,*,*,*,4,*,4,*,4,8,*,8,*")])
3504 (define_insn "*movdi_64bit_mips16"
3505 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m")
3506 (match_operand:DI 1 "move_operand" "d,d,y,K,N,kf,U,m,d"))]
3507 "TARGET_64BIT && TARGET_MIPS16
3508 && (register_operand (operands[0], DImode)
3509 || register_operand (operands[1], DImode))"
3510 { return mips_output_move (operands[0], operands[1]); }
3511 [(set_attr "type" "move,move,move,arith,arith,load,const,load,store")
3512 (set_attr "mode" "DI")
3513 (set_attr_alternative "length"
3517 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3520 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3526 (const_string "*")])])
3529 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3530 ;; when the original load is a 4 byte instruction but the add and the
3531 ;; load are 2 2 byte instructions.
3534 [(set (match_operand:DI 0 "register_operand")
3535 (mem:DI (plus:DI (match_dup 0)
3536 (match_operand:DI 1 "const_int_operand"))))]
3537 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
3538 && !TARGET_DEBUG_D_MODE
3539 && REG_P (operands[0])
3540 && M16_REG_P (REGNO (operands[0]))
3541 && GET_CODE (operands[1]) == CONST_INT
3542 && ((INTVAL (operands[1]) < 0
3543 && INTVAL (operands[1]) >= -0x10)
3544 || (INTVAL (operands[1]) >= 32 * 8
3545 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
3546 || (INTVAL (operands[1]) >= 0
3547 && INTVAL (operands[1]) < 32 * 8
3548 && (INTVAL (operands[1]) & 7) != 0))"
3549 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
3550 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
3552 HOST_WIDE_INT val = INTVAL (operands[1]);
3555 operands[2] = const0_rtx;
3556 else if (val >= 32 * 8)
3560 operands[1] = GEN_INT (0x8 + off);
3561 operands[2] = GEN_INT (val - off - 0x8);
3567 operands[1] = GEN_INT (off);
3568 operands[2] = GEN_INT (val - off);
3572 ;; 32-bit Integer moves
3574 ;; Unlike most other insns, the move insns can't be split with
3575 ;; different predicates, because register spilling and other parts of
3576 ;; the compiler, have memoized the insn number already.
3578 (define_expand "movsi"
3579 [(set (match_operand:SI 0 "")
3580 (match_operand:SI 1 ""))]
3583 if (mips_legitimize_move (SImode, operands[0], operands[1]))
3587 ;; The difference between these two is whether or not ints are allowed
3588 ;; in FP registers (off by default, use -mdebugh to enable).
3590 (define_insn "*movsi_internal"
3591 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
3592 (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))]
3594 && (register_operand (operands[0], SImode)
3595 || reg_or_0_operand (operands[1], SImode))"
3596 { return mips_output_move (operands[0], operands[1]); }
3597 [(set_attr "type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,load,mfc,store")
3598 (set_attr "mode" "SI")
3599 (set_attr "length" "4,*,*,*,*,4,*,4,*,4,4,4,4,4,*,4,*")])
3601 (define_insn "*movsi_mips16"
3602 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m")
3603 (match_operand:SI 1 "move_operand" "d,d,y,K,N,kf,U,m,d"))]
3605 && (register_operand (operands[0], SImode)
3606 || register_operand (operands[1], SImode))"
3607 { return mips_output_move (operands[0], operands[1]); }
3608 [(set_attr "type" "move,move,move,arith,arith,load,const,load,store")
3609 (set_attr "mode" "SI")
3610 (set_attr_alternative "length"
3614 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3617 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3623 (const_string "*")])])
3625 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
3626 ;; when the original load is a 4 byte instruction but the add and the
3627 ;; load are 2 2 byte instructions.
3630 [(set (match_operand:SI 0 "register_operand")
3631 (mem:SI (plus:SI (match_dup 0)
3632 (match_operand:SI 1 "const_int_operand"))))]
3633 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3634 && REG_P (operands[0])
3635 && M16_REG_P (REGNO (operands[0]))
3636 && GET_CODE (operands[1]) == CONST_INT
3637 && ((INTVAL (operands[1]) < 0
3638 && INTVAL (operands[1]) >= -0x80)
3639 || (INTVAL (operands[1]) >= 32 * 4
3640 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
3641 || (INTVAL (operands[1]) >= 0
3642 && INTVAL (operands[1]) < 32 * 4
3643 && (INTVAL (operands[1]) & 3) != 0))"
3644 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3645 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
3647 HOST_WIDE_INT val = INTVAL (operands[1]);
3650 operands[2] = const0_rtx;
3651 else if (val >= 32 * 4)
3655 operands[1] = GEN_INT (0x7c + off);
3656 operands[2] = GEN_INT (val - off - 0x7c);
3662 operands[1] = GEN_INT (off);
3663 operands[2] = GEN_INT (val - off);
3667 ;; On the mips16, we can split a load of certain constants into a load
3668 ;; and an add. This turns a 4 byte instruction into 2 2 byte
3672 [(set (match_operand:SI 0 "register_operand")
3673 (match_operand:SI 1 "const_int_operand"))]
3674 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3675 && REG_P (operands[0])
3676 && M16_REG_P (REGNO (operands[0]))
3677 && GET_CODE (operands[1]) == CONST_INT
3678 && INTVAL (operands[1]) >= 0x100
3679 && INTVAL (operands[1]) <= 0xff + 0x7f"
3680 [(set (match_dup 0) (match_dup 1))
3681 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3683 int val = INTVAL (operands[1]);
3685 operands[1] = GEN_INT (0xff);
3686 operands[2] = GEN_INT (val - 0xff);
3689 ;; This insn handles moving CCmode values. It's really just a
3690 ;; slightly simplified copy of movsi_internal2, with additional cases
3691 ;; to move a condition register to a general register and to move
3692 ;; between the general registers and the floating point registers.
3694 (define_insn "movcc"
3695 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
3696 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
3697 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3698 { return mips_output_move (operands[0], operands[1]); }
3699 [(set_attr "type" "multi,move,load,store,mfc,mtc,fmove,fpload,fpstore")
3700 (set_attr "mode" "SI")
3701 (set_attr "length" "8,4,*,*,4,4,4,*,*")])
3703 ;; Reload condition code registers. reload_incc and reload_outcc
3704 ;; both handle moves from arbitrary operands into condition code
3705 ;; registers. reload_incc handles the more common case in which
3706 ;; a source operand is constrained to be in a condition-code
3707 ;; register, but has not been allocated to one.
3709 ;; Sometimes, such as in movcc, we have a CCmode destination whose
3710 ;; constraints do not include 'z'. reload_outcc handles the case
3711 ;; when such an operand is allocated to a condition-code register.
3713 ;; Note that reloads from a condition code register to some
3714 ;; other location can be done using ordinary moves. Moving
3715 ;; into a GPR takes a single movcc, moving elsewhere takes
3716 ;; two. We can leave these cases to the generic reload code.
3717 (define_expand "reload_incc"
3718 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3719 (match_operand:CC 1 "general_operand" ""))
3720 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3721 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3723 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
3727 (define_expand "reload_outcc"
3728 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3729 (match_operand:CC 1 "register_operand" ""))
3730 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3731 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3733 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
3737 ;; MIPS4 supports loading and storing a floating point register from
3738 ;; the sum of two general registers. We use two versions for each of
3739 ;; these four instructions: one where the two general registers are
3740 ;; SImode, and one where they are DImode. This is because general
3741 ;; registers will be in SImode when they hold 32-bit values, but,
3742 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
3743 ;; instructions will still work correctly.
3745 ;; ??? Perhaps it would be better to support these instructions by
3746 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
3747 ;; these instructions can only be used to load and store floating
3748 ;; point registers, that would probably cause trouble in reload.
3750 (define_insn "*<ANYF:loadx>_<P:mode>"
3751 [(set (match_operand:ANYF 0 "register_operand" "=f")
3752 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3753 (match_operand:P 2 "register_operand" "d"))))]
3755 "<ANYF:loadx>\t%0,%1(%2)"
3756 [(set_attr "type" "fpidxload")
3757 (set_attr "mode" "<ANYF:UNITMODE>")])
3759 (define_insn "*<ANYF:storex>_<P:mode>"
3760 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3761 (match_operand:P 2 "register_operand" "d")))
3762 (match_operand:ANYF 0 "register_operand" "f"))]
3764 "<ANYF:storex>\t%0,%1(%2)"
3765 [(set_attr "type" "fpidxstore")
3766 (set_attr "mode" "<ANYF:UNITMODE>")])
3768 ;; Scaled indexed address load.
3769 ;; Per md.texi, we only need to look for a pattern with multiply in the
3770 ;; address expression, not shift.
3772 (define_insn "*lwxs"
3773 [(set (match_operand:SI 0 "register_operand" "=d")
3774 (mem:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
3776 (match_operand:SI 2 "register_operand" "d"))))]
3779 [(set_attr "type" "load")
3780 (set_attr "mode" "SI")
3781 (set_attr "length" "4")])
3783 ;; 16-bit Integer moves
3785 ;; Unlike most other insns, the move insns can't be split with
3786 ;; different predicates, because register spilling and other parts of
3787 ;; the compiler, have memoized the insn number already.
3788 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3790 (define_expand "movhi"
3791 [(set (match_operand:HI 0 "")
3792 (match_operand:HI 1 ""))]
3795 if (mips_legitimize_move (HImode, operands[0], operands[1]))
3799 (define_insn "*movhi_internal"
3800 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*x")
3801 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d"))]
3803 && (register_operand (operands[0], HImode)
3804 || reg_or_0_operand (operands[1], HImode))"
3811 [(set_attr "type" "move,arith,load,store,mthilo")
3812 (set_attr "mode" "HI")
3813 (set_attr "length" "4,4,*,*,4")])
3815 (define_insn "*movhi_mips16"
3816 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3817 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d"))]
3819 && (register_operand (operands[0], HImode)
3820 || register_operand (operands[1], HImode))"
3829 [(set_attr "type" "move,move,move,arith,arith,load,store")
3830 (set_attr "mode" "HI")
3831 (set_attr_alternative "length"
3835 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3838 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3842 (const_string "*")])])
3845 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
3846 ;; when the original load is a 4 byte instruction but the add and the
3847 ;; load are 2 2 byte instructions.
3850 [(set (match_operand:HI 0 "register_operand")
3851 (mem:HI (plus:SI (match_dup 0)
3852 (match_operand:SI 1 "const_int_operand"))))]
3853 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3854 && REG_P (operands[0])
3855 && M16_REG_P (REGNO (operands[0]))
3856 && GET_CODE (operands[1]) == CONST_INT
3857 && ((INTVAL (operands[1]) < 0
3858 && INTVAL (operands[1]) >= -0x80)
3859 || (INTVAL (operands[1]) >= 32 * 2
3860 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
3861 || (INTVAL (operands[1]) >= 0
3862 && INTVAL (operands[1]) < 32 * 2
3863 && (INTVAL (operands[1]) & 1) != 0))"
3864 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3865 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
3867 HOST_WIDE_INT val = INTVAL (operands[1]);
3870 operands[2] = const0_rtx;
3871 else if (val >= 32 * 2)
3875 operands[1] = GEN_INT (0x7e + off);
3876 operands[2] = GEN_INT (val - off - 0x7e);
3882 operands[1] = GEN_INT (off);
3883 operands[2] = GEN_INT (val - off);
3887 ;; 8-bit Integer moves
3889 ;; Unlike most other insns, the move insns can't be split with
3890 ;; different predicates, because register spilling and other parts of
3891 ;; the compiler, have memoized the insn number already.
3892 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3894 (define_expand "movqi"
3895 [(set (match_operand:QI 0 "")
3896 (match_operand:QI 1 ""))]
3899 if (mips_legitimize_move (QImode, operands[0], operands[1]))
3903 (define_insn "*movqi_internal"
3904 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*x")
3905 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d"))]
3907 && (register_operand (operands[0], QImode)
3908 || reg_or_0_operand (operands[1], QImode))"
3915 [(set_attr "type" "move,arith,load,store,mthilo")
3916 (set_attr "mode" "QI")
3917 (set_attr "length" "4,4,*,*,4")])
3919 (define_insn "*movqi_mips16"
3920 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3921 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d"))]
3923 && (register_operand (operands[0], QImode)
3924 || register_operand (operands[1], QImode))"
3933 [(set_attr "type" "move,move,move,arith,arith,load,store")
3934 (set_attr "mode" "QI")
3935 (set_attr "length" "4,4,4,4,8,*,*")])
3937 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
3938 ;; when the original load is a 4 byte instruction but the add and the
3939 ;; load are 2 2 byte instructions.
3942 [(set (match_operand:QI 0 "register_operand")
3943 (mem:QI (plus:SI (match_dup 0)
3944 (match_operand:SI 1 "const_int_operand"))))]
3945 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3946 && REG_P (operands[0])
3947 && M16_REG_P (REGNO (operands[0]))
3948 && GET_CODE (operands[1]) == CONST_INT
3949 && ((INTVAL (operands[1]) < 0
3950 && INTVAL (operands[1]) >= -0x80)
3951 || (INTVAL (operands[1]) >= 32
3952 && INTVAL (operands[1]) <= 31 + 0x7f))"
3953 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3954 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
3956 HOST_WIDE_INT val = INTVAL (operands[1]);
3959 operands[2] = const0_rtx;
3962 operands[1] = GEN_INT (0x7f);
3963 operands[2] = GEN_INT (val - 0x7f);
3967 ;; 32-bit floating point moves
3969 (define_expand "movsf"
3970 [(set (match_operand:SF 0 "")
3971 (match_operand:SF 1 ""))]
3974 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
3978 (define_insn "*movsf_hardfloat"
3979 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3980 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
3982 && (register_operand (operands[0], SFmode)
3983 || reg_or_0_operand (operands[1], SFmode))"
3984 { return mips_output_move (operands[0], operands[1]); }
3985 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
3986 (set_attr "mode" "SF")
3987 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3989 (define_insn "*movsf_softfloat"
3990 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
3991 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
3992 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
3993 && (register_operand (operands[0], SFmode)
3994 || reg_or_0_operand (operands[1], SFmode))"
3995 { return mips_output_move (operands[0], operands[1]); }
3996 [(set_attr "type" "move,load,store")
3997 (set_attr "mode" "SF")
3998 (set_attr "length" "4,*,*")])
4000 (define_insn "*movsf_mips16"
4001 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
4002 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
4004 && (register_operand (operands[0], SFmode)
4005 || register_operand (operands[1], SFmode))"
4006 { return mips_output_move (operands[0], operands[1]); }
4007 [(set_attr "type" "move,move,move,load,store")
4008 (set_attr "mode" "SF")
4009 (set_attr "length" "4,4,4,*,*")])
4012 ;; 64-bit floating point moves
4014 (define_expand "movdf"
4015 [(set (match_operand:DF 0 "")
4016 (match_operand:DF 1 ""))]
4019 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
4023 (define_insn "*movdf_hardfloat_64bit"
4024 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4025 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
4026 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT
4027 && (register_operand (operands[0], DFmode)
4028 || reg_or_0_operand (operands[1], DFmode))"
4029 { return mips_output_move (operands[0], operands[1]); }
4030 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4031 (set_attr "mode" "DF")
4032 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
4034 ;; This pattern applies to both !TARGET_FLOAT64 and TARGET_FLOAT64.
4035 (define_insn "*movdf_hardfloat_32bit"
4036 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4037 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
4038 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT
4039 && (register_operand (operands[0], DFmode)
4040 || reg_or_0_operand (operands[1], DFmode))"
4041 { return mips_output_move (operands[0], operands[1]); }
4042 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4043 (set_attr "mode" "DF")
4044 (set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
4046 (define_insn "*movdf_softfloat"
4047 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f")
4048 (match_operand:DF 1 "move_operand" "dG,m,dG,f,d,f"))]
4049 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
4050 && (register_operand (operands[0], DFmode)
4051 || reg_or_0_operand (operands[1], DFmode))"
4052 { return mips_output_move (operands[0], operands[1]); }
4053 [(set_attr "type" "multi,load,store,mfc,mtc,fmove")
4054 (set_attr "mode" "DF")
4055 (set_attr "length" "8,*,*,4,4,4")])
4057 (define_insn "*movdf_mips16"
4058 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
4059 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
4061 && (register_operand (operands[0], DFmode)
4062 || register_operand (operands[1], DFmode))"
4063 { return mips_output_move (operands[0], operands[1]); }
4064 [(set_attr "type" "multi,multi,multi,load,store")
4065 (set_attr "mode" "DF")
4066 (set_attr "length" "8,8,8,*,*")])
4068 ;; 128-bit floating point moves
4070 (define_expand "movtf"
4071 [(set (match_operand:TF 0)
4072 (match_operand:TF 1))]
4075 if (mips_legitimize_move (TFmode, operands[0], operands[1]))
4079 ;; This pattern handles both hard- and soft-float cases.
4080 (define_insn "*movtf"
4081 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m")
4082 (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))]
4085 && (register_operand (operands[0], TFmode)
4086 || reg_or_0_operand (operands[1], TFmode))"
4088 [(set_attr "type" "multi,load,store,multi,multi,fpload,fpstore")
4089 (set_attr "length" "8,*,*,8,8,*,*")])
4091 (define_insn "*movtf_mips16"
4092 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m")
4093 (match_operand:TF 1 "move_operand" "d,d,y,m,d"))]
4096 && (register_operand (operands[0], TFmode)
4097 || register_operand (operands[1], TFmode))"
4099 [(set_attr "type" "multi,multi,multi,load,store")
4100 (set_attr "length" "8,8,8,*,*")])
4103 [(set (match_operand:MOVE64 0 "nonimmediate_operand")
4104 (match_operand:MOVE64 1 "move_operand"))]
4105 "reload_completed && !TARGET_64BIT
4106 && mips_split_64bit_move_p (operands[0], operands[1])"
4109 mips_split_doubleword_move (operands[0], operands[1]);
4114 [(set (match_operand:MOVE128 0 "nonimmediate_operand")
4115 (match_operand:MOVE128 1 "move_operand"))]
4116 "TARGET_64BIT && reload_completed"
4119 mips_split_doubleword_move (operands[0], operands[1]);
4123 ;; When generating mips16 code, split moves of negative constants into
4124 ;; a positive "li" followed by a negation.
4126 [(set (match_operand 0 "register_operand")
4127 (match_operand 1 "const_int_operand"))]
4128 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
4132 (neg:SI (match_dup 2)))]
4134 operands[2] = gen_lowpart (SImode, operands[0]);
4135 operands[3] = GEN_INT (-INTVAL (operands[1]));
4138 ;; 64-bit paired-single floating point moves
4140 (define_expand "movv2sf"
4141 [(set (match_operand:V2SF 0)
4142 (match_operand:V2SF 1))]
4143 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
4145 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
4149 (define_insn "movv2sf_hardfloat_64bit"
4150 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4151 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4153 && TARGET_PAIRED_SINGLE_FLOAT
4155 && (register_operand (operands[0], V2SFmode)
4156 || reg_or_0_operand (operands[1], V2SFmode))"
4157 { return mips_output_move (operands[0], operands[1]); }
4158 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4159 (set_attr "mode" "SF")
4160 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
4162 (define_insn "movv2sf_hardfloat_32bit"
4163 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4164 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4166 && TARGET_PAIRED_SINGLE_FLOAT
4168 && (register_operand (operands[0], V2SFmode)
4169 || reg_or_0_operand (operands[1], V2SFmode))"
4170 { return mips_output_move (operands[0], operands[1]); }
4171 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4172 (set_attr "mode" "SF")
4173 (set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
4175 ;; The HI and LO registers are not truly independent. If we move an mthi
4176 ;; instruction before an mflo instruction, it will make the result of the
4177 ;; mflo unpredictable. The same goes for mtlo and mfhi.
4179 ;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
4180 ;; Operand 1 is the register we want, operand 2 is the other one.
4182 ;; When generating VR4120 or VR4130 code, we use macc{,hi} and
4183 ;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal
4184 ;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130.
4186 (define_expand "mfhilo_<mode>"
4187 [(set (match_operand:GPR 0 "register_operand")
4188 (unspec:GPR [(match_operand:GPR 1 "register_operand")
4189 (match_operand:GPR 2 "register_operand")]
4192 (define_insn "*mfhilo_<mode>"
4193 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4194 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
4195 (match_operand:GPR 2 "register_operand" "l,h")]
4199 [(set_attr "type" "mfhilo")
4200 (set_attr "mode" "<MODE>")])
4202 (define_insn "*mfhilo_<mode>_macc"
4203 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4204 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
4205 (match_operand:GPR 2 "register_operand" "l,h")]
4211 [(set_attr "type" "mfhilo")
4212 (set_attr "mode" "<MODE>")])
4214 ;; Emit a doubleword move in which exactly one of the operands is
4215 ;; a floating-point register. We can't just emit two normal moves
4216 ;; because of the constraints imposed by the FPU register model;
4217 ;; see mips_cannot_change_mode_class for details. Instead, we keep
4218 ;; the FPR whole and use special patterns to refer to each word of
4219 ;; the other operand.
4221 (define_expand "move_doubleword_fpr<mode>"
4222 [(set (match_operand:SPLITF 0)
4223 (match_operand:SPLITF 1))]
4226 if (FP_REG_RTX_P (operands[0]))
4228 rtx low = mips_subword (operands[1], 0);
4229 rtx high = mips_subword (operands[1], 1);
4230 emit_insn (gen_load_low<mode> (operands[0], low));
4232 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
4234 emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
4238 rtx low = mips_subword (operands[0], 0);
4239 rtx high = mips_subword (operands[0], 1);
4240 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
4242 emit_insn (gen_mfhc1<mode> (high, operands[1]));
4244 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
4249 ;; Load the low word of operand 0 with operand 1.
4250 (define_insn "load_low<mode>"
4251 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4252 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
4256 operands[0] = mips_subword (operands[0], 0);
4257 return mips_output_move (operands[0], operands[1]);
4259 [(set_attr "type" "mtc,fpload")
4260 (set_attr "mode" "<HALFMODE>")])
4262 ;; Load the high word of operand 0 from operand 1, preserving the value
4264 (define_insn "load_high<mode>"
4265 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4266 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
4267 (match_operand:SPLITF 2 "register_operand" "0,0")]
4271 operands[0] = mips_subword (operands[0], 1);
4272 return mips_output_move (operands[0], operands[1]);
4274 [(set_attr "type" "mtc,fpload")
4275 (set_attr "mode" "<HALFMODE>")])
4277 ;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
4278 ;; high word and 0 to store the low word.
4279 (define_insn "store_word<mode>"
4280 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
4281 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
4282 (match_operand 2 "const_int_operand")]
4283 UNSPEC_STORE_WORD))]
4286 operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
4287 return mips_output_move (operands[0], operands[1]);
4289 [(set_attr "type" "mfc,fpstore")
4290 (set_attr "mode" "<HALFMODE>")])
4292 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4293 ;; value in the low word.
4294 (define_insn "mthc1<mode>"
4295 [(set (match_operand:SPLITF 0 "register_operand" "=f")
4296 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ")
4297 (match_operand:SPLITF 2 "register_operand" "0")]
4299 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4301 [(set_attr "type" "mtc")
4302 (set_attr "mode" "<HALFMODE>")])
4304 ;; Move high word of operand 1 to operand 0 using mfhc1.
4305 (define_insn "mfhc1<mode>"
4306 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
4307 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
4309 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4311 [(set_attr "type" "mfc")
4312 (set_attr "mode" "<HALFMODE>")])
4314 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4315 (define_expand "load_const_gp_<mode>"
4316 [(set (match_operand:P 0 "register_operand" "=d")
4317 (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
4319 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4320 ;; of _gp from the start of this function. Operand 1 is the incoming
4321 ;; function address.
4322 (define_insn_and_split "loadgp_newabi_<mode>"
4323 [(set (match_operand:P 0 "register_operand" "=d")
4324 (unspec_volatile:P [(match_operand:P 1)
4325 (match_operand:P 2 "register_operand" "d")]
4327 "mips_current_loadgp_style () == LOADGP_NEWABI"
4330 [(set (match_dup 0) (match_dup 3))
4331 (set (match_dup 0) (match_dup 4))
4332 (set (match_dup 0) (match_dup 5))]
4334 operands[3] = gen_rtx_HIGH (Pmode, operands[1]);
4335 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
4336 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]);
4338 [(set_attr "length" "12")])
4340 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4341 (define_insn_and_split "loadgp_absolute_<mode>"
4342 [(set (match_operand:P 0 "register_operand" "=d")
4343 (unspec_volatile:P [(match_operand:P 1)] UNSPEC_LOADGP))]
4344 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4349 mips_emit_move (operands[0], operands[1]);
4352 [(set_attr "length" "8")])
4354 ;; This blockage instruction prevents the gp load from being
4355 ;; scheduled after an implicit use of gp. It also prevents
4356 ;; the load from being deleted as dead.
4357 (define_insn "loadgp_blockage"
4358 [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)]
4361 [(set_attr "type" "ghost")
4362 (set_attr "mode" "none")
4363 (set_attr "length" "0")])
4365 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
4366 ;; and operand 1 is the __GOTT_INDEX__ symbol.
4367 (define_insn_and_split "loadgp_rtp_<mode>"
4368 [(set (match_operand:P 0 "register_operand" "=d")
4369 (unspec_volatile:P [(match_operand:P 1 "symbol_ref_operand")
4370 (match_operand:P 2 "symbol_ref_operand")]
4372 "mips_current_loadgp_style () == LOADGP_RTP"
4375 [(set (match_dup 0) (high:P (match_dup 3)))
4376 (set (match_dup 0) (unspec:P [(match_dup 0)
4377 (match_dup 3)] UNSPEC_LOAD_GOT))
4378 (set (match_dup 0) (unspec:P [(match_dup 0)
4379 (match_dup 4)] UNSPEC_LOAD_GOT))]
4381 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE);
4382 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF);
4384 [(set_attr "length" "12")])
4386 ;; Emit a .cprestore directive, which normally expands to a single store
4387 ;; instruction. Note that we continue to use .cprestore for explicit reloc
4388 ;; code so that jals inside inline asms will work correctly.
4389 (define_insn "cprestore"
4390 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")
4395 if (set_nomacro && which_alternative == 1)
4396 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
4398 return ".cprestore\t%0";
4400 [(set_attr "type" "store")
4401 (set_attr "length" "4,12")])
4403 ;; Expand in-line code to clear the instruction cache between operand[0] and
4405 (define_expand "clear_cache"
4406 [(match_operand 0 "pmode_register_operand")
4407 (match_operand 1 "pmode_register_operand")]
4413 mips_expand_synci_loop (operands[0], operands[1]);
4414 emit_insn (gen_sync ());
4415 emit_insn (gen_clear_hazard ());
4417 else if (mips_cache_flush_func && mips_cache_flush_func[0])
4419 rtx len = gen_reg_rtx (Pmode);
4420 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
4421 MIPS_ICACHE_SYNC (operands[0], len);
4427 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
4431 (define_insn "synci"
4432 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
4437 (define_insn "rdhwr"
4438 [(set (match_operand:SI 0 "register_operand" "=d")
4439 (unspec_volatile [(match_operand:SI 1 "const_int_operand" "n")]
4444 (define_insn "clear_hazard"
4445 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
4446 (clobber (reg:SI 31))]
4449 return "%(%<bal\t1f\n"
4451 "1:\taddiu\t$31,$31,12\n"
4455 [(set_attr "length" "20")])
4457 ;; Atomic memory operations.
4459 (define_insn "memory_barrier"
4460 [(set (mem:BLK (scratch))
4461 (unspec:BLK [(const_int 0)] UNSPEC_MEMORY_BARRIER))]
4465 (define_insn "sync_compare_and_swap<mode>"
4466 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
4467 (match_operand:GPR 1 "memory_operand" "+R,R"))
4469 (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "dJ,dJ")
4470 (match_operand:GPR 3 "arith_operand" "I,d")]
4471 UNSPEC_COMPARE_AND_SWAP))]
4474 if (which_alternative == 0)
4475 return MIPS_COMPARE_AND_SWAP ("<d>", "li");
4477 return MIPS_COMPARE_AND_SWAP ("<d>", "move");
4479 [(set_attr "length" "32")])
4481 (define_expand "sync_compare_and_swap<mode>"
4482 [(match_operand:SHORT 0 "register_operand")
4483 (match_operand:SHORT 1 "memory_operand")
4484 (match_operand:SHORT 2 "general_operand")
4485 (match_operand:SHORT 3 "general_operand")]
4488 union mips_gen_fn_ptrs generator;
4489 generator.fn_6 = gen_compare_and_swap_12;
4490 mips_expand_atomic_qihi (generator,
4491 operands[0], operands[1], operands[2], operands[3]);
4495 ;; Helper insn for mips_expand_atomic_qihi.
4496 (define_insn "compare_and_swap_12"
4497 [(set (match_operand:SI 0 "register_operand" "=&d,&d")
4498 (match_operand:SI 1 "memory_operand" "+R,R"))
4500 (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d,d")
4501 (match_operand:SI 3 "register_operand" "d,d")
4502 (match_operand:SI 4 "reg_or_0_operand" "dJ,dJ")
4503 (match_operand:SI 5 "reg_or_0_operand" "d,J")]
4504 UNSPEC_COMPARE_AND_SWAP_12))]
4507 if (which_alternative == 0)
4508 return MIPS_COMPARE_AND_SWAP_12 (MIPS_COMPARE_AND_SWAP_12_NONZERO_OP);
4510 return MIPS_COMPARE_AND_SWAP_12 (MIPS_COMPARE_AND_SWAP_12_ZERO_OP);
4512 [(set_attr "length" "40,36")])
4514 (define_insn "sync_add<mode>"
4515 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
4516 (unspec_volatile:GPR
4517 [(plus:GPR (match_dup 0)
4518 (match_operand:GPR 1 "arith_operand" "I,d"))]
4519 UNSPEC_SYNC_OLD_OP))]
4522 if (which_alternative == 0)
4523 return MIPS_SYNC_OP ("<d>", "<d>addiu");
4525 return MIPS_SYNC_OP ("<d>", "<d>addu");
4527 [(set_attr "length" "28")])
4529 (define_expand "sync_<optab><mode>"
4530 [(set (match_operand:SHORT 0 "memory_operand")
4531 (unspec_volatile:SHORT
4532 [(atomic_hiqi_op:SHORT (match_dup 0)
4533 (match_operand:SHORT 1 "general_operand"))]
4534 UNSPEC_SYNC_OLD_OP))]
4537 union mips_gen_fn_ptrs generator;
4538 generator.fn_4 = gen_sync_<optab>_12;
4539 mips_expand_atomic_qihi (generator,
4540 NULL, operands[0], operands[1], NULL);
4544 ;; Helper insn for sync_<optab><mode>
4545 (define_insn "sync_<optab>_12"
4546 [(set (match_operand:SI 0 "memory_operand" "+R")
4548 [(match_operand:SI 1 "register_operand" "d")
4549 (match_operand:SI 2 "register_operand" "d")
4550 (atomic_hiqi_op:SI (match_dup 0)
4551 (match_operand:SI 3 "register_operand" "dJ"))]
4552 UNSPEC_SYNC_OLD_OP_12))
4553 (clobber (match_scratch:SI 4 "=&d"))]
4556 return MIPS_SYNC_OP_12 ("<insn>", MIPS_SYNC_OP_12_NOT_NOP);
4558 [(set_attr "length" "40")])
4560 (define_expand "sync_old_<optab><mode>"
4562 (set (match_operand:SHORT 0 "register_operand")
4563 (match_operand:SHORT 1 "memory_operand"))
4565 (unspec_volatile:SHORT [(atomic_hiqi_op:SHORT
4567 (match_operand:SHORT 2 "general_operand"))]
4568 UNSPEC_SYNC_OLD_OP))])]
4571 union mips_gen_fn_ptrs generator;
4572 generator.fn_5 = gen_sync_old_<optab>_12;
4573 mips_expand_atomic_qihi (generator,
4574 operands[0], operands[1], operands[2], NULL);
4578 ;; Helper insn for sync_old_<optab><mode>
4579 (define_insn "sync_old_<optab>_12"
4580 [(set (match_operand:SI 0 "register_operand" "=&d")
4581 (match_operand:SI 1 "memory_operand" "+R"))
4584 [(match_operand:SI 2 "register_operand" "d")
4585 (match_operand:SI 3 "register_operand" "d")
4586 (atomic_hiqi_op:SI (match_dup 0)
4587 (match_operand:SI 4 "register_operand" "dJ"))]
4588 UNSPEC_SYNC_OLD_OP_12))
4589 (clobber (match_scratch:SI 5 "=&d"))]
4592 return MIPS_SYNC_OLD_OP_12 ("<insn>", MIPS_SYNC_OLD_OP_12_NOT_NOP,
4593 MIPS_SYNC_OLD_OP_12_NOT_NOP_REG);
4595 [(set_attr "length" "40")])
4597 (define_expand "sync_new_<optab><mode>"
4599 (set (match_operand:SHORT 0 "register_operand")
4600 (unspec_volatile:SHORT [(atomic_hiqi_op:SHORT
4601 (match_operand:SHORT 1 "memory_operand")
4602 (match_operand:SHORT 2 "general_operand"))]
4603 UNSPEC_SYNC_NEW_OP))
4605 (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)]
4606 UNSPEC_SYNC_NEW_OP))])]
4609 union mips_gen_fn_ptrs generator;
4610 generator.fn_5 = gen_sync_new_<optab>_12;
4611 mips_expand_atomic_qihi (generator,
4612 operands[0], operands[1], operands[2], NULL);
4616 ;; Helper insn for sync_new_<optab><mode>
4617 (define_insn "sync_new_<optab>_12"
4618 [(set (match_operand:SI 0 "register_operand" "=&d")
4620 [(match_operand:SI 1 "memory_operand" "+R")
4621 (match_operand:SI 2 "register_operand" "d")
4622 (match_operand:SI 3 "register_operand" "d")
4623 (atomic_hiqi_op:SI (match_dup 0)
4624 (match_operand:SI 4 "register_operand" "dJ"))]
4625 UNSPEC_SYNC_NEW_OP_12))
4631 (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))]
4634 return MIPS_SYNC_NEW_OP_12 ("<insn>", MIPS_SYNC_NEW_OP_12_NOT_NOP);
4636 [(set_attr "length" "40")])
4638 (define_expand "sync_nand<mode>"
4639 [(set (match_operand:SHORT 0 "memory_operand")
4640 (unspec_volatile:SHORT
4642 (match_operand:SHORT 1 "general_operand")]
4643 UNSPEC_SYNC_OLD_OP))]
4646 union mips_gen_fn_ptrs generator;
4647 generator.fn_4 = gen_sync_nand_12;
4648 mips_expand_atomic_qihi (generator,
4649 NULL, operands[0], operands[1], NULL);
4653 ;; Helper insn for sync_nand<mode>
4654 (define_insn "sync_nand_12"
4655 [(set (match_operand:SI 0 "memory_operand" "+R")
4657 [(match_operand:SI 1 "register_operand" "d")
4658 (match_operand:SI 2 "register_operand" "d")
4660 (match_operand:SI 3 "register_operand" "dJ")]
4661 UNSPEC_SYNC_OLD_OP_12))
4662 (clobber (match_scratch:SI 4 "=&d"))]
4665 return MIPS_SYNC_OP_12 ("and", MIPS_SYNC_OP_12_NOT_NOT);
4667 [(set_attr "length" "44")])
4669 (define_expand "sync_old_nand<mode>"
4671 (set (match_operand:SHORT 0 "register_operand")
4672 (match_operand:SHORT 1 "memory_operand"))
4674 (unspec_volatile:SHORT [(match_dup 1)
4675 (match_operand:SHORT 2 "general_operand")]
4676 UNSPEC_SYNC_OLD_OP))])]
4679 union mips_gen_fn_ptrs generator;
4680 generator.fn_5 = gen_sync_old_nand_12;
4681 mips_expand_atomic_qihi (generator,
4682 operands[0], operands[1], operands[2], NULL);
4686 ;; Helper insn for sync_old_nand<mode>
4687 (define_insn "sync_old_nand_12"
4688 [(set (match_operand:SI 0 "register_operand" "=&d")
4689 (match_operand:SI 1 "memory_operand" "+R"))
4692 [(match_operand:SI 2 "register_operand" "d")
4693 (match_operand:SI 3 "register_operand" "d")
4694 (match_operand:SI 4 "register_operand" "dJ")]
4695 UNSPEC_SYNC_OLD_OP_12))
4696 (clobber (match_scratch:SI 5 "=&d"))]
4699 return MIPS_SYNC_OLD_OP_12 ("and", MIPS_SYNC_OLD_OP_12_NOT_NOT,
4700 MIPS_SYNC_OLD_OP_12_NOT_NOT_REG);
4702 [(set_attr "length" "44")])
4704 (define_expand "sync_new_nand<mode>"
4706 (set (match_operand:SHORT 0 "register_operand")
4707 (unspec_volatile:SHORT [(match_operand:SHORT 1 "memory_operand")
4708 (match_operand:SHORT 2 "general_operand")]
4709 UNSPEC_SYNC_NEW_OP))
4711 (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)]
4712 UNSPEC_SYNC_NEW_OP))])]
4715 union mips_gen_fn_ptrs generator;
4716 generator.fn_5 = gen_sync_new_nand_12;
4717 mips_expand_atomic_qihi (generator,
4718 operands[0], operands[1], operands[2], NULL);
4722 ;; Helper insn for sync_new_nand<mode>
4723 (define_insn "sync_new_nand_12"
4724 [(set (match_operand:SI 0 "register_operand" "=&d")
4726 [(match_operand:SI 1 "memory_operand" "+R")
4727 (match_operand:SI 2 "register_operand" "d")
4728 (match_operand:SI 3 "register_operand" "d")
4729 (match_operand:SI 4 "register_operand" "dJ")]
4730 UNSPEC_SYNC_NEW_OP_12))
4736 (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))]
4739 return MIPS_SYNC_NEW_OP_12 ("and", MIPS_SYNC_NEW_OP_12_NOT_NOT);
4741 [(set_attr "length" "40")])
4743 (define_insn "sync_sub<mode>"
4744 [(set (match_operand:GPR 0 "memory_operand" "+R")
4745 (unspec_volatile:GPR
4746 [(minus:GPR (match_dup 0)
4747 (match_operand:GPR 1 "register_operand" "d"))]
4748 UNSPEC_SYNC_OLD_OP))]
4751 return MIPS_SYNC_OP ("<d>", "<d>subu");
4753 [(set_attr "length" "28")])
4755 (define_insn "sync_old_add<mode>"
4756 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
4757 (match_operand:GPR 1 "memory_operand" "+R,R"))
4759 (unspec_volatile:GPR
4760 [(plus:GPR (match_dup 1)
4761 (match_operand:GPR 2 "arith_operand" "I,d"))]
4762 UNSPEC_SYNC_OLD_OP))]
4765 if (which_alternative == 0)
4766 return MIPS_SYNC_OLD_OP ("<d>", "<d>addiu");
4768 return MIPS_SYNC_OLD_OP ("<d>", "<d>addu");
4770 [(set_attr "length" "28")])
4772 (define_insn "sync_old_sub<mode>"
4773 [(set (match_operand:GPR 0 "register_operand" "=&d")
4774 (match_operand:GPR 1 "memory_operand" "+R"))
4776 (unspec_volatile:GPR
4777 [(minus:GPR (match_dup 1)
4778 (match_operand:GPR 2 "register_operand" "d"))]
4779 UNSPEC_SYNC_OLD_OP))]
4782 return MIPS_SYNC_OLD_OP ("<d>", "<d>subu");
4784 [(set_attr "length" "28")])
4786 (define_insn "sync_new_add<mode>"
4787 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
4788 (plus:GPR (match_operand:GPR 1 "memory_operand" "+R,R")
4789 (match_operand:GPR 2 "arith_operand" "I,d")))
4791 (unspec_volatile:GPR
4792 [(plus:GPR (match_dup 1) (match_dup 2))]
4793 UNSPEC_SYNC_NEW_OP))]
4796 if (which_alternative == 0)
4797 return MIPS_SYNC_NEW_OP ("<d>", "<d>addiu");
4799 return MIPS_SYNC_NEW_OP ("<d>", "<d>addu");
4801 [(set_attr "length" "28")])
4803 (define_insn "sync_new_sub<mode>"
4804 [(set (match_operand:GPR 0 "register_operand" "=&d")
4805 (minus:GPR (match_operand:GPR 1 "memory_operand" "+R")
4806 (match_operand:GPR 2 "register_operand" "d")))
4808 (unspec_volatile:GPR
4809 [(minus:GPR (match_dup 1) (match_dup 2))]
4810 UNSPEC_SYNC_NEW_OP))]
4813 return MIPS_SYNC_NEW_OP ("<d>", "<d>subu");
4815 [(set_attr "length" "28")])
4817 (define_insn "sync_<optab><mode>"
4818 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
4819 (unspec_volatile:GPR
4820 [(fetchop_bit:GPR (match_operand:GPR 1 "uns_arith_operand" "K,d")
4822 UNSPEC_SYNC_OLD_OP))]
4825 if (which_alternative == 0)
4826 return MIPS_SYNC_OP ("<d>", "<immediate_insn>");
4828 return MIPS_SYNC_OP ("<d>", "<insn>");
4830 [(set_attr "length" "28")])
4832 (define_insn "sync_old_<optab><mode>"
4833 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
4834 (match_operand:GPR 1 "memory_operand" "+R,R"))
4836 (unspec_volatile:GPR
4837 [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
4839 UNSPEC_SYNC_OLD_OP))]
4842 if (which_alternative == 0)
4843 return MIPS_SYNC_OLD_OP ("<d>", "<immediate_insn>");
4845 return MIPS_SYNC_OLD_OP ("<d>", "<insn>");
4847 [(set_attr "length" "28")])
4849 (define_insn "sync_new_<optab><mode>"
4850 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
4851 (match_operand:GPR 1 "memory_operand" "+R,R"))
4853 (unspec_volatile:GPR
4854 [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
4856 UNSPEC_SYNC_NEW_OP))]
4859 if (which_alternative == 0)
4860 return MIPS_SYNC_NEW_OP ("<d>", "<immediate_insn>");
4862 return MIPS_SYNC_NEW_OP ("<d>", "<insn>");
4864 [(set_attr "length" "28")])
4866 (define_insn "sync_nand<mode>"
4867 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
4868 (unspec_volatile:GPR [(match_operand:GPR 1 "uns_arith_operand" "K,d")]
4869 UNSPEC_SYNC_OLD_OP))]
4872 if (which_alternative == 0)
4873 return MIPS_SYNC_NAND ("<d>", "andi");
4875 return MIPS_SYNC_NAND ("<d>", "and");
4877 [(set_attr "length" "32")])
4879 (define_insn "sync_old_nand<mode>"
4880 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
4881 (match_operand:GPR 1 "memory_operand" "+R,R"))
4883 (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
4884 UNSPEC_SYNC_OLD_OP))]
4887 if (which_alternative == 0)
4888 return MIPS_SYNC_OLD_NAND ("<d>", "andi");
4890 return MIPS_SYNC_OLD_NAND ("<d>", "and");
4892 [(set_attr "length" "32")])
4894 (define_insn "sync_new_nand<mode>"
4895 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
4896 (match_operand:GPR 1 "memory_operand" "+R,R"))
4898 (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
4899 UNSPEC_SYNC_NEW_OP))]
4902 if (which_alternative == 0)
4903 return MIPS_SYNC_NEW_NAND ("<d>", "andi");
4905 return MIPS_SYNC_NEW_NAND ("<d>", "and");
4907 [(set_attr "length" "32")])
4909 (define_insn "sync_lock_test_and_set<mode>"
4910 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
4911 (match_operand:GPR 1 "memory_operand" "+R,R"))
4913 (unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")]
4914 UNSPEC_SYNC_EXCHANGE))]
4917 if (which_alternative == 0)
4918 return MIPS_SYNC_EXCHANGE ("<d>", "li");
4920 return MIPS_SYNC_EXCHANGE ("<d>", "move");
4922 [(set_attr "length" "24")])
4924 (define_expand "sync_lock_test_and_set<mode>"
4925 [(match_operand:SHORT 0 "register_operand")
4926 (match_operand:SHORT 1 "memory_operand")
4927 (match_operand:SHORT 2 "general_operand")]
4930 union mips_gen_fn_ptrs generator;
4931 generator.fn_5 = gen_test_and_set_12;
4932 mips_expand_atomic_qihi (generator,
4933 operands[0], operands[1], operands[2], NULL);
4937 (define_insn "test_and_set_12"
4938 [(set (match_operand:SI 0 "register_operand" "=&d,&d")
4939 (match_operand:SI 1 "memory_operand" "+R,R"))
4941 (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d,d")
4942 (match_operand:SI 3 "register_operand" "d,d")
4943 (match_operand:SI 4 "arith_operand" "d,J")]
4944 UNSPEC_SYNC_EXCHANGE_12))]
4947 if (which_alternative == 0)
4948 return MIPS_SYNC_EXCHANGE_12 (MIPS_SYNC_EXCHANGE_12_NONZERO_OP);
4950 return MIPS_SYNC_EXCHANGE_12 (MIPS_SYNC_EXCHANGE_12_ZERO_OP);
4952 [(set_attr "length" "28,24")])
4954 ;; Block moves, see mips.c for more details.
4955 ;; Argument 0 is the destination
4956 ;; Argument 1 is the source
4957 ;; Argument 2 is the length
4958 ;; Argument 3 is the alignment
4960 (define_expand "movmemsi"
4961 [(parallel [(set (match_operand:BLK 0 "general_operand")
4962 (match_operand:BLK 1 "general_operand"))
4963 (use (match_operand:SI 2 ""))
4964 (use (match_operand:SI 3 "const_int_operand"))])]
4965 "!TARGET_MIPS16 && !TARGET_MEMCPY"
4967 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
4974 ;; ....................
4978 ;; ....................
4980 (define_expand "<optab><mode>3"
4981 [(set (match_operand:GPR 0 "register_operand")
4982 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4983 (match_operand:SI 2 "arith_operand")))]
4986 /* On the mips16, a shift of more than 8 is a four byte instruction,
4987 so, for a shift between 8 and 16, it is just as fast to do two
4988 shifts of 8 or less. If there is a lot of shifting going on, we
4989 may win in CSE. Otherwise combine will put the shifts back
4990 together again. This can be called by mips_function_arg, so we must
4991 be careful not to allocate a new register if we've reached the
4995 && GET_CODE (operands[2]) == CONST_INT
4996 && INTVAL (operands[2]) > 8
4997 && INTVAL (operands[2]) <= 16
4998 && !reload_in_progress
4999 && !reload_completed)
5001 rtx temp = gen_reg_rtx (<MODE>mode);
5003 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
5004 emit_insn (gen_<optab><mode>3 (operands[0], temp,
5005 GEN_INT (INTVAL (operands[2]) - 8)));
5010 (define_insn "*<optab><mode>3"
5011 [(set (match_operand:GPR 0 "register_operand" "=d")
5012 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
5013 (match_operand:SI 2 "arith_operand" "dI")))]
5016 if (GET_CODE (operands[2]) == CONST_INT)
5017 operands[2] = GEN_INT (INTVAL (operands[2])
5018 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
5020 return "<d><insn>\t%0,%1,%2";
5022 [(set_attr "type" "shift")
5023 (set_attr "mode" "<MODE>")])
5025 (define_insn "*<optab>si3_extend"
5026 [(set (match_operand:DI 0 "register_operand" "=d")
5028 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
5029 (match_operand:SI 2 "arith_operand" "dI"))))]
5030 "TARGET_64BIT && !TARGET_MIPS16"
5032 if (GET_CODE (operands[2]) == CONST_INT)
5033 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5035 return "<insn>\t%0,%1,%2";
5037 [(set_attr "type" "shift")
5038 (set_attr "mode" "SI")])
5040 (define_insn "*<optab>si3_mips16"
5041 [(set (match_operand:SI 0 "register_operand" "=d,d")
5042 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
5043 (match_operand:SI 2 "arith_operand" "d,I")))]
5046 if (which_alternative == 0)
5047 return "<insn>\t%0,%2";
5049 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5050 return "<insn>\t%0,%1,%2";
5052 [(set_attr "type" "shift")
5053 (set_attr "mode" "SI")
5054 (set_attr_alternative "length"
5056 (if_then_else (match_operand 2 "m16_uimm3_b")
5060 ;; We need separate DImode MIPS16 patterns because of the irregularity
5062 (define_insn "*ashldi3_mips16"
5063 [(set (match_operand:DI 0 "register_operand" "=d,d")
5064 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
5065 (match_operand:SI 2 "arith_operand" "d,I")))]
5066 "TARGET_64BIT && TARGET_MIPS16"
5068 if (which_alternative == 0)
5069 return "dsll\t%0,%2";
5071 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5072 return "dsll\t%0,%1,%2";
5074 [(set_attr "type" "shift")
5075 (set_attr "mode" "DI")
5076 (set_attr_alternative "length"
5078 (if_then_else (match_operand 2 "m16_uimm3_b")
5082 (define_insn "*ashrdi3_mips16"
5083 [(set (match_operand:DI 0 "register_operand" "=d,d")
5084 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5085 (match_operand:SI 2 "arith_operand" "d,I")))]
5086 "TARGET_64BIT && TARGET_MIPS16"
5088 if (GET_CODE (operands[2]) == CONST_INT)
5089 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5091 return "dsra\t%0,%2";
5093 [(set_attr "type" "shift")
5094 (set_attr "mode" "DI")
5095 (set_attr_alternative "length"
5097 (if_then_else (match_operand 2 "m16_uimm3_b")
5101 (define_insn "*lshrdi3_mips16"
5102 [(set (match_operand:DI 0 "register_operand" "=d,d")
5103 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5104 (match_operand:SI 2 "arith_operand" "d,I")))]
5105 "TARGET_64BIT && TARGET_MIPS16"
5107 if (GET_CODE (operands[2]) == CONST_INT)
5108 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5110 return "dsrl\t%0,%2";
5112 [(set_attr "type" "shift")
5113 (set_attr "mode" "DI")
5114 (set_attr_alternative "length"
5116 (if_then_else (match_operand 2 "m16_uimm3_b")
5120 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
5123 [(set (match_operand:GPR 0 "register_operand")
5124 (any_shift:GPR (match_operand:GPR 1 "register_operand")
5125 (match_operand:GPR 2 "const_int_operand")))]
5126 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
5127 && GET_CODE (operands[2]) == CONST_INT
5128 && INTVAL (operands[2]) > 8
5129 && INTVAL (operands[2]) <= 16"
5130 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
5131 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
5132 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
5134 ;; If we load a byte on the mips16 as a bitfield, the resulting
5135 ;; sequence of instructions is too complicated for combine, because it
5136 ;; involves four instructions: a load, a shift, a constant load into a
5137 ;; register, and an and (the key problem here is that the mips16 does
5138 ;; not have and immediate). We recognize a shift of a load in order
5139 ;; to make it simple enough for combine to understand.
5141 ;; The length here is the worst case: the length of the split version
5142 ;; will be more accurate.
5143 (define_insn_and_split ""
5144 [(set (match_operand:SI 0 "register_operand" "=d")
5145 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5146 (match_operand:SI 2 "immediate_operand" "I")))]
5150 [(set (match_dup 0) (match_dup 1))
5151 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
5153 [(set_attr "type" "load")
5154 (set_attr "mode" "SI")
5155 (set_attr "length" "16")])
5157 (define_insn "rotr<mode>3"
5158 [(set (match_operand:GPR 0 "register_operand" "=d")
5159 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
5160 (match_operand:SI 2 "arith_operand" "dI")))]
5163 if (GET_CODE (operands[2]) == CONST_INT)
5164 gcc_assert (INTVAL (operands[2]) >= 0
5165 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
5167 return "<d>ror\t%0,%1,%2";
5169 [(set_attr "type" "shift")
5170 (set_attr "mode" "<MODE>")])
5173 ;; ....................
5177 ;; ....................
5179 ;; Flow here is rather complex:
5181 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the arguments
5182 ;; into cmp_operands[] but generates no RTL.
5184 ;; 2) The appropriate branch define_expand is called, which then
5185 ;; creates the appropriate RTL for the comparison and branch.
5186 ;; Different CC modes are used, based on what type of branch is
5187 ;; done, so that we can constrain things appropriately. There
5188 ;; are assumptions in the rest of GCC that break if we fold the
5189 ;; operands into the branches for integer operations, and use cc0
5190 ;; for floating point, so we use the fp status register instead.
5191 ;; If needed, an appropriate temporary is created to hold the
5192 ;; of the integer compare.
5194 (define_expand "cmp<mode>"
5196 (compare:CC (match_operand:GPR 0 "register_operand")
5197 (match_operand:GPR 1 "nonmemory_operand")))]
5200 cmp_operands[0] = operands[0];
5201 cmp_operands[1] = operands[1];
5205 (define_expand "cmp<mode>"
5207 (compare:CC (match_operand:SCALARF 0 "register_operand")
5208 (match_operand:SCALARF 1 "register_operand")))]
5211 cmp_operands[0] = operands[0];
5212 cmp_operands[1] = operands[1];
5217 ;; ....................
5219 ;; CONDITIONAL BRANCHES
5221 ;; ....................
5223 ;; Conditional branches on floating-point equality tests.
5225 (define_insn "*branch_fp"
5228 (match_operator 0 "equality_operator"
5229 [(match_operand:CC 2 "register_operand" "z")
5231 (label_ref (match_operand 1 "" ""))
5235 return mips_output_conditional_branch (insn, operands,
5236 MIPS_BRANCH ("b%F0", "%Z2%1"),
5237 MIPS_BRANCH ("b%W0", "%Z2%1"));
5239 [(set_attr "type" "branch")
5240 (set_attr "mode" "none")])
5242 (define_insn "*branch_fp_inverted"
5245 (match_operator 0 "equality_operator"
5246 [(match_operand:CC 2 "register_operand" "z")
5249 (label_ref (match_operand 1 "" ""))))]
5252 return mips_output_conditional_branch (insn, operands,
5253 MIPS_BRANCH ("b%W0", "%Z2%1"),
5254 MIPS_BRANCH ("b%F0", "%Z2%1"));
5256 [(set_attr "type" "branch")
5257 (set_attr "mode" "none")])
5259 ;; Conditional branches on ordered comparisons with zero.
5261 (define_insn "*branch_order<mode>"
5264 (match_operator 0 "order_operator"
5265 [(match_operand:GPR 2 "register_operand" "d")
5267 (label_ref (match_operand 1 "" ""))
5270 { return mips_output_order_conditional_branch (insn, operands, false); }
5271 [(set_attr "type" "branch")
5272 (set_attr "mode" "none")])
5274 (define_insn "*branch_order<mode>_inverted"
5277 (match_operator 0 "order_operator"
5278 [(match_operand:GPR 2 "register_operand" "d")
5281 (label_ref (match_operand 1 "" ""))))]
5283 { return mips_output_order_conditional_branch (insn, operands, true); }
5284 [(set_attr "type" "branch")
5285 (set_attr "mode" "none")])
5287 ;; Conditional branch on equality comparison.
5289 (define_insn "*branch_equality<mode>"
5292 (match_operator 0 "equality_operator"
5293 [(match_operand:GPR 2 "register_operand" "d")
5294 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5295 (label_ref (match_operand 1 "" ""))
5299 return mips_output_conditional_branch (insn, operands,
5300 MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
5301 MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
5303 [(set_attr "type" "branch")
5304 (set_attr "mode" "none")])
5306 (define_insn "*branch_equality<mode>_inverted"
5309 (match_operator 0 "equality_operator"
5310 [(match_operand:GPR 2 "register_operand" "d")
5311 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5313 (label_ref (match_operand 1 "" ""))))]
5316 return mips_output_conditional_branch (insn, operands,
5317 MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
5318 MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
5320 [(set_attr "type" "branch")
5321 (set_attr "mode" "none")])
5325 (define_insn "*branch_equality<mode>_mips16"
5328 (match_operator 0 "equality_operator"
5329 [(match_operand:GPR 1 "register_operand" "d,t")
5331 (match_operand 2 "pc_or_label_operand" "")
5332 (match_operand 3 "pc_or_label_operand" "")))]
5335 if (operands[2] != pc_rtx)
5337 if (which_alternative == 0)
5338 return "b%C0z\t%1,%2";
5340 return "bt%C0z\t%2";
5344 if (which_alternative == 0)
5345 return "b%N0z\t%1,%3";
5347 return "bt%N0z\t%3";
5350 [(set_attr "type" "branch")
5351 (set_attr "mode" "none")
5352 (set_attr "length" "8")])
5354 (define_expand "b<code>"
5356 (if_then_else (any_cond:CC (cc0)
5358 (label_ref (match_operand 0 ""))
5362 mips_expand_conditional_branch (operands, <CODE>);
5366 ;; Used to implement built-in functions.
5367 (define_expand "condjump"
5369 (if_then_else (match_operand 0)
5370 (label_ref (match_operand 1))
5374 ;; ....................
5376 ;; SETTING A REGISTER FROM A COMPARISON
5378 ;; ....................
5380 ;; Destination is always set in SI mode.
5382 (define_expand "seq"
5383 [(set (match_operand:SI 0 "register_operand")
5384 (eq:SI (match_dup 1)
5387 { if (mips_expand_scc (EQ, operands[0])) DONE; else FAIL; })
5389 (define_insn "*seq_<GPR:mode><GPR2:mode>"
5390 [(set (match_operand:GPR2 0 "register_operand" "=d")
5391 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5395 [(set_attr "type" "slt")
5396 (set_attr "mode" "<GPR:MODE>")])
5398 (define_insn "*seq_<GPR:mode><GPR2:mode>_mips16"
5399 [(set (match_operand:GPR2 0 "register_operand" "=t")
5400 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5404 [(set_attr "type" "slt")
5405 (set_attr "mode" "<GPR:MODE>")])
5407 ;; "sne" uses sltu instructions in which the first operand is $0.
5408 ;; This isn't possible in mips16 code.
5410 (define_expand "sne"
5411 [(set (match_operand:SI 0 "register_operand")
5412 (ne:SI (match_dup 1)
5415 { if (mips_expand_scc (NE, operands[0])) DONE; else FAIL; })
5417 (define_insn "*sne_<GPR:mode><GPR2:mode>"
5418 [(set (match_operand:GPR2 0 "register_operand" "=d")
5419 (ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
5423 [(set_attr "type" "slt")
5424 (set_attr "mode" "<GPR:MODE>")])
5426 (define_expand "sgt<u>"
5427 [(set (match_operand:SI 0 "register_operand")
5428 (any_gt:SI (match_dup 1)
5431 { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
5433 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>"
5434 [(set (match_operand:GPR2 0 "register_operand" "=d")
5435 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5436 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5439 [(set_attr "type" "slt")
5440 (set_attr "mode" "<GPR:MODE>")])
5442 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16"
5443 [(set (match_operand:GPR2 0 "register_operand" "=t")
5444 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5445 (match_operand:GPR 2 "register_operand" "d")))]
5448 [(set_attr "type" "slt")
5449 (set_attr "mode" "<GPR:MODE>")])
5451 (define_expand "sge<u>"
5452 [(set (match_operand:SI 0 "register_operand")
5453 (any_ge:SI (match_dup 1)
5456 { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
5458 (define_insn "*sge<u>_<GPR:mode><GPR2:mode>"
5459 [(set (match_operand:GPR2 0 "register_operand" "=d")
5460 (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d")
5464 [(set_attr "type" "slt")
5465 (set_attr "mode" "<GPR:MODE>")])
5467 (define_expand "slt<u>"
5468 [(set (match_operand:SI 0 "register_operand")
5469 (any_lt:SI (match_dup 1)
5472 { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
5474 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>"
5475 [(set (match_operand:GPR2 0 "register_operand" "=d")
5476 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5477 (match_operand:GPR 2 "arith_operand" "dI")))]
5480 [(set_attr "type" "slt")
5481 (set_attr "mode" "<GPR:MODE>")])
5483 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16"
5484 [(set (match_operand:GPR2 0 "register_operand" "=t,t")
5485 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d")
5486 (match_operand:GPR 2 "arith_operand" "d,I")))]
5489 [(set_attr "type" "slt")
5490 (set_attr "mode" "<GPR:MODE>")
5491 (set_attr_alternative "length"
5493 (if_then_else (match_operand 2 "m16_uimm8_1")
5497 (define_expand "sle<u>"
5498 [(set (match_operand:SI 0 "register_operand")
5499 (any_le:SI (match_dup 1)
5502 { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
5504 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>"
5505 [(set (match_operand:GPR2 0 "register_operand" "=d")
5506 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5507 (match_operand:GPR 2 "sle_operand" "")))]
5510 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5511 return "slt<u>\t%0,%1,%2";
5513 [(set_attr "type" "slt")
5514 (set_attr "mode" "<GPR:MODE>")])
5516 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16"
5517 [(set (match_operand:GPR2 0 "register_operand" "=t")
5518 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5519 (match_operand:GPR 2 "sle_operand" "")))]
5522 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5523 return "slt<u>\t%1,%2";
5525 [(set_attr "type" "slt")
5526 (set_attr "mode" "<GPR:MODE>")
5527 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5532 ;; ....................
5534 ;; FLOATING POINT COMPARISONS
5536 ;; ....................
5538 (define_insn "s<code>_<mode>"
5539 [(set (match_operand:CC 0 "register_operand" "=z")
5540 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5541 (match_operand:SCALARF 2 "register_operand" "f")))]
5543 "c.<fcond>.<fmt>\t%Z0%1,%2"
5544 [(set_attr "type" "fcmp")
5545 (set_attr "mode" "FPSW")])
5547 (define_insn "s<code>_<mode>"
5548 [(set (match_operand:CC 0 "register_operand" "=z")
5549 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5550 (match_operand:SCALARF 2 "register_operand" "f")))]
5552 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
5553 [(set_attr "type" "fcmp")
5554 (set_attr "mode" "FPSW")])
5557 ;; ....................
5559 ;; UNCONDITIONAL BRANCHES
5561 ;; ....................
5563 ;; Unconditional branches.
5567 (label_ref (match_operand 0 "" "")))]
5572 if (get_attr_length (insn) <= 8)
5573 return "%*b\t%l0%/";
5576 output_asm_insn (mips_output_load_label (), operands);
5577 return "%*jr\t%@%/%]";
5581 return "%*j\t%l0%/";
5583 [(set_attr "type" "jump")
5584 (set_attr "mode" "none")
5585 (set (attr "length")
5586 ;; We can't use `j' when emitting PIC. Emit a branch if it's
5587 ;; in range, otherwise load the address of the branch target into
5588 ;; $at and then jump to it.
5590 (ior (eq (symbol_ref "flag_pic") (const_int 0))
5591 (lt (abs (minus (match_dup 0)
5592 (plus (pc) (const_int 4))))
5593 (const_int 131072)))
5594 (const_int 4) (const_int 16)))])
5596 ;; We need a different insn for the mips16, because a mips16 branch
5597 ;; does not have a delay slot.
5601 (label_ref (match_operand 0 "" "")))]
5604 [(set_attr "type" "branch")
5605 (set_attr "mode" "none")
5606 (set_attr "length" "8")])
5608 (define_expand "indirect_jump"
5609 [(set (pc) (match_operand 0 "register_operand"))]
5612 operands[0] = force_reg (Pmode, operands[0]);
5613 if (Pmode == SImode)
5614 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
5616 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
5620 (define_insn "indirect_jump<mode>"
5621 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
5624 [(set_attr "type" "jump")
5625 (set_attr "mode" "none")])
5627 (define_expand "tablejump"
5629 (match_operand 0 "register_operand"))
5630 (use (label_ref (match_operand 1 "")))]
5633 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
5634 operands[0] = expand_binop (Pmode, add_optab,
5635 convert_to_mode (Pmode, operands[0], false),
5636 gen_rtx_LABEL_REF (Pmode, operands[1]),
5638 else if (TARGET_GPWORD)
5639 operands[0] = expand_binop (Pmode, add_optab, operands[0],
5640 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
5641 else if (TARGET_RTP_PIC)
5643 /* When generating RTP PIC, we use case table entries that are relative
5644 to the start of the function. Add the function's address to the
5646 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5647 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
5648 start, 0, 0, OPTAB_WIDEN);
5651 if (Pmode == SImode)
5652 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
5654 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
5658 (define_insn "tablejump<mode>"
5660 (match_operand:P 0 "register_operand" "d"))
5661 (use (label_ref (match_operand 1 "" "")))]
5664 [(set_attr "type" "jump")
5665 (set_attr "mode" "none")])
5667 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
5668 ;; While it is possible to either pull it off the stack (in the
5669 ;; o32 case) or recalculate it given t9 and our target label,
5670 ;; it takes 3 or 4 insns to do so.
5672 (define_expand "builtin_setjmp_setup"
5673 [(use (match_operand 0 "register_operand"))]
5678 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
5679 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
5683 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
5684 ;; that older code did recalculate the gp from $25. Continue to jump through
5685 ;; $25 for compatibility (we lose nothing by doing so).
5687 (define_expand "builtin_longjmp"
5688 [(use (match_operand 0 "register_operand"))]
5691 /* The elements of the buffer are, in order: */
5692 int W = GET_MODE_SIZE (Pmode);
5693 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5694 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
5695 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
5696 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
5697 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5698 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
5699 The target is bound to be using $28 as the global pointer
5700 but the current function might not be. */
5701 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
5703 /* This bit is similar to expand_builtin_longjmp except that it
5704 restores $gp as well. */
5705 mips_emit_move (hard_frame_pointer_rtx, fp);
5706 mips_emit_move (pv, lab);
5707 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5708 mips_emit_move (gp, gpv);
5709 emit_use (hard_frame_pointer_rtx);
5710 emit_use (stack_pointer_rtx);
5712 emit_indirect_jump (pv);
5717 ;; ....................
5719 ;; Function prologue/epilogue
5721 ;; ....................
5724 (define_expand "prologue"
5728 mips_expand_prologue ();
5732 ;; Block any insns from being moved before this point, since the
5733 ;; profiling call to mcount can use various registers that aren't
5734 ;; saved or used to pass arguments.
5736 (define_insn "blockage"
5737 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5740 [(set_attr "type" "ghost")
5741 (set_attr "mode" "none")
5742 (set_attr "length" "0")])
5744 (define_expand "epilogue"
5748 mips_expand_epilogue (false);
5752 (define_expand "sibcall_epilogue"
5756 mips_expand_epilogue (true);
5760 ;; Trivial return. Make it look like a normal return insn as that
5761 ;; allows jump optimizations to work better.
5763 (define_expand "return"
5765 "mips_can_use_return_insn ()"
5766 { mips_expand_before_return (); })
5768 (define_insn "*return"
5770 "mips_can_use_return_insn ()"
5772 [(set_attr "type" "jump")
5773 (set_attr "mode" "none")])
5777 (define_insn "return_internal"
5779 (use (match_operand 0 "pmode_register_operand" ""))]
5782 [(set_attr "type" "jump")
5783 (set_attr "mode" "none")])
5785 ;; This is used in compiling the unwind routines.
5786 (define_expand "eh_return"
5787 [(use (match_operand 0 "general_operand"))]
5790 if (GET_MODE (operands[0]) != word_mode)
5791 operands[0] = convert_to_mode (word_mode, operands[0], 0);
5793 emit_insn (gen_eh_set_lr_di (operands[0]));
5795 emit_insn (gen_eh_set_lr_si (operands[0]));
5799 ;; Clobber the return address on the stack. We can't expand this
5800 ;; until we know where it will be put in the stack frame.
5802 (define_insn "eh_set_lr_si"
5803 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5804 (clobber (match_scratch:SI 1 "=&d"))]
5808 (define_insn "eh_set_lr_di"
5809 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5810 (clobber (match_scratch:DI 1 "=&d"))]
5815 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
5816 (clobber (match_scratch 1))]
5817 "reload_completed && !TARGET_DEBUG_D_MODE"
5820 mips_set_return_address (operands[0], operands[1]);
5824 (define_expand "exception_receiver"
5828 /* See the comment above load_call<mode> for details. */
5829 emit_insn (gen_set_got_version ());
5831 /* If we have a call-clobbered $gp, restore it from its save slot. */
5832 if (HAVE_restore_gp)
5833 emit_insn (gen_restore_gp ());
5837 (define_expand "nonlocal_goto_receiver"
5841 /* See the comment above load_call<mode> for details. */
5842 emit_insn (gen_set_got_version ());
5846 ;; Restore $gp from its .cprestore stack slot. The instruction remains
5847 ;; volatile until all uses of $28 are exposed.
5848 (define_insn_and_split "restore_gp"
5850 (unspec_volatile:SI [(const_int 0)] UNSPEC_RESTORE_GP))]
5851 "TARGET_CALL_CLOBBERED_GP"
5853 "&& reload_completed"
5859 [(set_attr "type" "load")
5860 (set_attr "length" "12")])
5863 ;; ....................
5867 ;; ....................
5869 ;; Instructions to load a call address from the GOT. The address might
5870 ;; point to a function or to a lazy binding stub. In the latter case,
5871 ;; the stub will use the dynamic linker to resolve the function, which
5872 ;; in turn will change the GOT entry to point to the function's real
5875 ;; This means that every call, even pure and constant ones, can
5876 ;; potentially modify the GOT entry. And once a stub has been called,
5877 ;; we must not call it again.
5879 ;; We represent this restriction using an imaginary, fixed, call-saved
5880 ;; register called GOT_VERSION_REGNUM. The idea is to make the register
5881 ;; live throughout the function and to change its value after every
5882 ;; potential call site. This stops any rtx value that uses the register
5883 ;; from being computed before an earlier call. To do this, we:
5885 ;; - Ensure that the register is live on entry to the function,
5886 ;; so that it is never thought to be used uninitalized.
5888 ;; - Ensure that the register is live on exit from the function,
5889 ;; so that it is live throughout.
5891 ;; - Make each call (lazily-bound or not) use the current value
5892 ;; of GOT_VERSION_REGNUM, so that updates of the register are
5893 ;; not moved across call boundaries.
5895 ;; - Add "ghost" definitions of the register to the beginning of
5896 ;; blocks reached by EH and ABNORMAL_CALL edges, because those
5897 ;; edges may involve calls that normal paths don't. (E.g. the
5898 ;; unwinding code that handles a non-call exception may change
5899 ;; lazily-bound GOT entries.) We do this by making the
5900 ;; exception_receiver and nonlocal_goto_receiver expanders emit
5901 ;; a set_got_version instruction.
5903 ;; - After each call (lazily-bound or not), use a "ghost"
5904 ;; update_got_version instruction to change the register's value.
5905 ;; This instruction mimics the _possible_ effect of the dynamic
5906 ;; resolver during the call and it remains live even if the call
5907 ;; itself becomes dead.
5909 ;; - Leave GOT_VERSION_REGNUM out of all register classes.
5910 ;; The register is therefore not a valid register_operand
5911 ;; and cannot be moved to or from other registers.
5912 (define_insn "load_call<mode>"
5913 [(set (match_operand:P 0 "register_operand" "=d")
5914 (unspec:P [(match_operand:P 1 "register_operand" "r")
5915 (match_operand:P 2 "immediate_operand" "")
5916 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))]
5918 "<load>\t%0,%R2(%1)"
5919 [(set_attr "type" "load")
5920 (set_attr "mode" "<MODE>")
5921 (set_attr "length" "4")])
5923 (define_insn "set_got_version"
5924 [(set (reg:SI GOT_VERSION_REGNUM)
5925 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))]
5928 [(set_attr "length" "0")
5929 (set_attr "type" "ghost")])
5931 (define_insn "update_got_version"
5932 [(set (reg:SI GOT_VERSION_REGNUM)
5933 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))]
5936 [(set_attr "length" "0")
5937 (set_attr "type" "ghost")])
5939 ;; Sibling calls. All these patterns use jump instructions.
5941 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
5942 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
5943 ;; is defined in terms of call_insn_operand, the same is true of the
5946 ;; When we use an indirect jump, we need a register that will be
5947 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
5948 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
5949 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
5952 (define_expand "sibcall"
5953 [(parallel [(call (match_operand 0 "")
5954 (match_operand 1 ""))
5955 (use (match_operand 2 "")) ;; next_arg_reg
5956 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5959 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], true);
5963 (define_insn "sibcall_internal"
5964 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
5965 (match_operand 1 "" ""))]
5966 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5967 { return MIPS_CALL ("j", operands, 0); }
5968 [(set_attr "type" "call")])
5970 (define_expand "sibcall_value"
5971 [(parallel [(set (match_operand 0 "")
5972 (call (match_operand 1 "")
5973 (match_operand 2 "")))
5974 (use (match_operand 3 ""))])] ;; next_arg_reg
5977 mips_expand_call (operands[0], XEXP (operands[1], 0),
5978 operands[2], operands[3], true);
5982 (define_insn "sibcall_value_internal"
5983 [(set (match_operand 0 "register_operand" "")
5984 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5985 (match_operand 2 "" "")))]
5986 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5987 { return MIPS_CALL ("j", operands, 1); }
5988 [(set_attr "type" "call")])
5990 (define_insn "sibcall_value_multiple_internal"
5991 [(set (match_operand 0 "register_operand" "")
5992 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5993 (match_operand 2 "" "")))
5994 (set (match_operand 3 "register_operand" "")
5995 (call (mem:SI (match_dup 1))
5997 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5998 { return MIPS_CALL ("j", operands, 1); }
5999 [(set_attr "type" "call")])
6001 (define_expand "call"
6002 [(parallel [(call (match_operand 0 "")
6003 (match_operand 1 ""))
6004 (use (match_operand 2 "")) ;; next_arg_reg
6005 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
6008 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], false);
6012 ;; This instruction directly corresponds to an assembly-language "jal".
6013 ;; There are four cases:
6016 ;; Both symbolic and register destinations are OK. The pattern
6017 ;; always expands to a single mips instruction.
6019 ;; - -mabicalls/-mno-explicit-relocs:
6020 ;; Again, both symbolic and register destinations are OK.
6021 ;; The call is treated as a multi-instruction black box.
6023 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
6024 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
6027 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
6028 ;; Only "jal $25" is allowed. The call is actually two instructions:
6029 ;; "jalr $25" followed by an insn to reload $gp.
6031 ;; In the last case, we can generate the individual instructions with
6032 ;; a define_split. There are several things to be wary of:
6034 ;; - We can't expose the load of $gp before reload. If we did,
6035 ;; it might get removed as dead, but reload can introduce new
6036 ;; uses of $gp by rematerializing constants.
6038 ;; - We shouldn't restore $gp after calls that never return.
6039 ;; It isn't valid to insert instructions between a noreturn
6040 ;; call and the following barrier.
6042 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
6043 ;; instruction preserves $gp and so have no effect on its liveness.
6044 ;; But once we generate the separate insns, it becomes obvious that
6045 ;; $gp is not live on entry to the call.
6047 ;; ??? The operands[2] = insn check is a hack to make the original insn
6048 ;; available to the splitter.
6049 (define_insn_and_split "call_internal"
6050 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6051 (match_operand 1 "" ""))
6052 (clobber (reg:SI 31))]
6054 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
6055 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
6058 emit_call_insn (gen_call_split (operands[0], operands[1]));
6059 if (!find_reg_note (operands[2], REG_NORETURN, 0))
6063 [(set_attr "jal" "indirect,direct")
6064 (set_attr "extended_mips16" "no,yes")])
6066 ;; A pattern for calls that must be made directly. It is used for
6067 ;; MIPS16 calls that the linker may need to redirect to a hard-float
6068 ;; stub; the linker relies on the call relocation type to detect when
6069 ;; such redirection is needed.
6070 (define_insn "call_internal_direct"
6071 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6074 (clobber (reg:SI 31))]
6076 { return MIPS_CALL ("jal", operands, 0); })
6078 (define_insn "call_split"
6079 [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
6080 (match_operand 1 "" ""))
6081 (clobber (reg:SI 31))
6082 (clobber (reg:SI 28))]
6083 "TARGET_SPLIT_CALLS"
6084 { return MIPS_CALL ("jal", operands, 0); }
6085 [(set_attr "type" "call")])
6087 (define_expand "call_value"
6088 [(parallel [(set (match_operand 0 "")
6089 (call (match_operand 1 "")
6090 (match_operand 2 "")))
6091 (use (match_operand 3 ""))])] ;; next_arg_reg
6094 mips_expand_call (operands[0], XEXP (operands[1], 0),
6095 operands[2], operands[3], false);
6099 ;; See comment for call_internal.
6100 (define_insn_and_split "call_value_internal"
6101 [(set (match_operand 0 "register_operand" "")
6102 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6103 (match_operand 2 "" "")))
6104 (clobber (reg:SI 31))]
6106 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
6107 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
6110 emit_call_insn (gen_call_value_split (operands[0], operands[1],
6112 if (!find_reg_note (operands[3], REG_NORETURN, 0))
6116 [(set_attr "jal" "indirect,direct")
6117 (set_attr "extended_mips16" "no,yes")])
6119 (define_insn "call_value_split"
6120 [(set (match_operand 0 "register_operand" "")
6121 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
6122 (match_operand 2 "" "")))
6123 (clobber (reg:SI 31))
6124 (clobber (reg:SI 28))]
6125 "TARGET_SPLIT_CALLS"
6126 { return MIPS_CALL ("jal", operands, 1); }
6127 [(set_attr "type" "call")])
6129 ;; See call_internal_direct.
6130 (define_insn "call_value_internal_direct"
6131 [(set (match_operand 0 "register_operand")
6132 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6135 (clobber (reg:SI 31))]
6137 { return MIPS_CALL ("jal", operands, 1); })
6139 ;; See comment for call_internal.
6140 (define_insn_and_split "call_value_multiple_internal"
6141 [(set (match_operand 0 "register_operand" "")
6142 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6143 (match_operand 2 "" "")))
6144 (set (match_operand 3 "register_operand" "")
6145 (call (mem:SI (match_dup 1))
6147 (clobber (reg:SI 31))]
6149 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
6150 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
6153 emit_call_insn (gen_call_value_multiple_split (operands[0], operands[1],
6154 operands[2], operands[3]));
6155 if (!find_reg_note (operands[4], REG_NORETURN, 0))
6159 [(set_attr "jal" "indirect,direct")
6160 (set_attr "extended_mips16" "no,yes")])
6162 (define_insn "call_value_multiple_split"
6163 [(set (match_operand 0 "register_operand" "")
6164 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
6165 (match_operand 2 "" "")))
6166 (set (match_operand 3 "register_operand" "")
6167 (call (mem:SI (match_dup 1))
6169 (clobber (reg:SI 31))
6170 (clobber (reg:SI 28))]
6171 "TARGET_SPLIT_CALLS"
6172 { return MIPS_CALL ("jal", operands, 1); }
6173 [(set_attr "type" "call")])
6175 ;; Call subroutine returning any type.
6177 (define_expand "untyped_call"
6178 [(parallel [(call (match_operand 0 "")
6180 (match_operand 1 "")
6181 (match_operand 2 "")])]
6186 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6188 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6190 rtx set = XVECEXP (operands[2], 0, i);
6191 mips_emit_move (SET_DEST (set), SET_SRC (set));
6194 emit_insn (gen_blockage ());
6199 ;; ....................
6203 ;; ....................
6207 (define_insn "prefetch"
6208 [(prefetch (match_operand:QI 0 "address_operand" "p")
6209 (match_operand 1 "const_int_operand" "n")
6210 (match_operand 2 "const_int_operand" "n"))]
6211 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
6213 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
6214 return "pref\t%1,%a0";
6216 [(set_attr "type" "prefetch")])
6218 (define_insn "*prefetch_indexed_<mode>"
6219 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
6220 (match_operand:P 1 "register_operand" "d"))
6221 (match_operand 2 "const_int_operand" "n")
6222 (match_operand 3 "const_int_operand" "n"))]
6223 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6225 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
6226 return "prefx\t%2,%1(%0)";
6228 [(set_attr "type" "prefetchx")])
6234 [(set_attr "type" "nop")
6235 (set_attr "mode" "none")])
6237 ;; Like nop, but commented out when outside a .set noreorder block.
6238 (define_insn "hazard_nop"
6247 [(set_attr "type" "nop")])
6249 ;; MIPS4 Conditional move instructions.
6251 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
6252 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6254 (match_operator:MOVECC 4 "equality_operator"
6255 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6257 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
6258 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
6263 [(set_attr "type" "condmove")
6264 (set_attr "mode" "<GPR:MODE>")])
6266 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
6267 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
6268 (if_then_else:SCALARF
6269 (match_operator:MOVECC 4 "equality_operator"
6270 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6272 (match_operand:SCALARF 2 "register_operand" "f,0")
6273 (match_operand:SCALARF 3 "register_operand" "0,f")))]
6276 mov%T4.<fmt>\t%0,%2,%1
6277 mov%t4.<fmt>\t%0,%3,%1"
6278 [(set_attr "type" "condmove")
6279 (set_attr "mode" "<SCALARF:MODE>")])
6281 ;; These are the main define_expand's used to make conditional moves.
6283 (define_expand "mov<mode>cc"
6284 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6285 (set (match_operand:GPR 0 "register_operand")
6286 (if_then_else:GPR (match_dup 5)
6287 (match_operand:GPR 2 "reg_or_0_operand")
6288 (match_operand:GPR 3 "reg_or_0_operand")))]
6291 mips_expand_conditional_move (operands);
6295 (define_expand "mov<mode>cc"
6296 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6297 (set (match_operand:SCALARF 0 "register_operand")
6298 (if_then_else:SCALARF (match_dup 5)
6299 (match_operand:SCALARF 2 "register_operand")
6300 (match_operand:SCALARF 3 "register_operand")))]
6303 mips_expand_conditional_move (operands);
6308 ;; ....................
6310 ;; mips16 inline constant tables
6312 ;; ....................
6315 (define_insn "consttable_int"
6316 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
6317 (match_operand 1 "const_int_operand" "")]
6318 UNSPEC_CONSTTABLE_INT)]
6321 assemble_integer (operands[0], INTVAL (operands[1]),
6322 BITS_PER_UNIT * INTVAL (operands[1]), 1);
6325 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6327 (define_insn "consttable_float"
6328 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
6329 UNSPEC_CONSTTABLE_FLOAT)]
6334 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
6335 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
6336 assemble_real (d, GET_MODE (operands[0]),
6337 GET_MODE_BITSIZE (GET_MODE (operands[0])));
6340 [(set (attr "length")
6341 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
6343 (define_insn "align"
6344 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
6347 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
6350 [(match_operand 0 "small_data_pattern")]
6353 { operands[0] = mips_rewrite_small_data (operands[0]); })
6356 ;; ....................
6358 ;; MIPS16e Save/Restore
6360 ;; ....................
6363 (define_insn "*mips16e_save_restore"
6364 [(match_parallel 0 ""
6365 [(set (match_operand:SI 1 "register_operand")
6366 (plus:SI (match_dup 1)
6367 (match_operand:SI 2 "const_int_operand")))])]
6368 "operands[1] == stack_pointer_rtx
6369 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
6370 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
6371 [(set_attr "type" "arith")
6372 (set_attr "extended_mips16" "yes")])
6374 ; Thread-Local Storage
6376 ; The TLS base pointer is accessed via "rdhwr $v1, $29". No current
6377 ; MIPS architecture defines this register, and no current
6378 ; implementation provides it; instead, any OS which supports TLS is
6379 ; expected to trap and emulate this instruction. rdhwr is part of the
6380 ; MIPS 32r2 specification, but we use it on any architecture because
6381 ; we expect it to be emulated. Use .set to force the assembler to
6384 (define_insn "tls_get_tp_<mode>"
6385 [(set (match_operand:P 0 "register_operand" "=v")
6386 (unspec:P [(const_int 0)]
6387 UNSPEC_TLS_GET_TP))]
6388 "HAVE_AS_TLS && !TARGET_MIPS16"
6389 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t%0,$29\;.set\tpop"
6390 [(set_attr "type" "unknown")
6391 ; Since rdhwr always generates a trap for now, putting it in a delay
6392 ; slot would make the kernel's emulation of it much slower.
6393 (set_attr "can_delay" "no")
6394 (set_attr "mode" "<MODE>")])
6396 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
6398 (include "mips-ps-3d.md")
6400 ; The MIPS DSP Instructions.
6402 (include "mips-dsp.md")
6404 ; The MIPS DSP REV 2 Instructions.
6406 (include "mips-dspr2.md")
6408 ; MIPS fixed-point instructions.
6409 (include "mips-fixed.md")