[AArch64] Rewrite vabs<q>_s<8,16,32,64> AdvSIMD intrinsics to fold to tree
[official-gcc.git] / gcc / config / spu / spu_intrinsics.h
blob34e2a90a716eb107d8f259d0066a2265212f0663
1 /* Definitions of Synergistic Processing Unit (SPU). */
2 /* Copyright (C) 2006-2013 Free Software Foundation, Inc.
4 This file is free software; you can redistribute it and/or modify it under
5 the terms of the GNU General Public License as published by the Free
6 Software Foundation; either version 3 of the License, or (at your option)
7 any later version.
9 This file is distributed in the hope that it will be useful, but WITHOUT
10 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 for more details.
14 Under Section 7 of GPL version 3, you are granted additional
15 permissions described in the GCC Runtime Library Exception, version
16 3.1, as published by the Free Software Foundation.
18 You should have received a copy of the GNU General Public License and
19 a copy of the GCC Runtime Library Exception along with this program;
20 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
21 <http://www.gnu.org/licenses/>. */
23 #ifndef _SPU_INTRINSICS_H
24 #define _SPU_INTRINSICS_H
26 #define vec_uchar16 __vector unsigned char
27 #define vec_char16 __vector signed char
28 #define vec_ushort8 __vector unsigned short
29 #define vec_short8 __vector signed short
30 #define vec_uint4 __vector unsigned int
31 #define vec_int4 __vector signed int
32 #define vec_ullong2 __vector unsigned long long
33 #define vec_llong2 __vector signed long long
34 #define vec_float4 __vector float
35 #define vec_double2 __vector double
37 /* SPU Channel Defines
39 #define SPU_RdEventStat 0
40 #define SPU_WrEventMask 1
41 #define SPU_WrEventAck 2
42 #define SPU_RdSigNotify1 3
43 #define SPU_RdSigNotify2 4
44 #define SPU_WrDec 7
45 #define SPU_RdDec 8
46 #define SPU_RdEventMask 11
47 #define SPU_RdMachStat 13
48 #define SPU_WrSRR0 14
49 #define SPU_RdSRR0 15
50 #define SPU_WrOutMbox 28
51 #define SPU_RdInMbox 29
52 #define SPU_WrOutIntrMbox 30
54 /* MFC Channel Defines.
56 #define MFC_WrMSSyncReq 9
57 #define MFC_RdTagMask 12
58 #define MFC_LSA 16
59 #define MFC_EAH 17
60 #define MFC_EAL 18
61 #define MFC_Size 19
62 #define MFC_TagID 20
63 #define MFC_Cmd 21
64 #define MFC_WrTagMask 22
65 #define MFC_WrTagUpdate 23
66 #define MFC_RdTagStat 24
67 #define MFC_RdListStallStat 25
68 #define MFC_WrListStallAck 26
69 #define MFC_RdAtomicStat 27
71 /* Bit flag mnemonics for test special value.
73 #define SPU_SV_NEG_DENORM 0x01 /* negative denormalized number */
74 #define SPU_SV_POS_DENORM 0x02 /* positive denormalized number */
75 #define SPU_SV_NEG_ZERO 0x04 /* negative zero */
76 #define SPU_SV_POS_ZERO 0x08 /* positive zero */
77 #define SPU_SV_NEG_INFINITY 0x10 /* negative infinity */
78 #define SPU_SV_POS_INFINITY 0x20 /* positive infinity */
79 #define SPU_SV_NAN 0x40 /* not a number */
81 #include <spu_internals.h>
83 #endif /* _SPU_INTRINSICS_H */