gcc/config/aarch64/aarch64-simd-builtins.def

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2012-2013 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 /* In the list below, the BUILTIN_<ITERATOR> macros expand to create
  22    builtins for each of the modes described by <ITERATOR>.  When adding
  23    new builtins to this list, a helpful idiom to follow is to add
  24    a line for each pattern in the md file.  Thus, ADDP, which has one
  25    pattern defined for the VD_BHSI iterator, and one for DImode, has two
  26    entries below.
  27
  28    Parameter 1 is the 'type' of the intrinsic.  This is used to
  29    describe the type modifiers (for example; unsigned) applied to
  30    each of the parameters to the intrinsic function.
  31
  32    Parameter 2 is the name of the intrinsic.  This is appended
  33    to `__builtin_aarch64_<name><mode>` to give the intrinsic name
  34    as exported to the front-ends.
  35
  36    Parameter 3 describes how to map from the name to the CODE_FOR_
  37    macro holding the RTL pattern for the intrinsic.  This mapping is:
  38    0 - CODE_FOR_aarch64_<name><mode>
  39    1-9 - CODE_FOR_<name><mode><1-9>
  40    10 - CODE_FOR_<name><mode>.  */
  41
  42   BUILTIN_VD_RE (CREATE, create, 0)
  43   BUILTIN_VQ_S (GETLANE, get_lane_signed, 0)
  44   BUILTIN_VDQ (GETLANE, get_lane_unsigned, 0)
  45   BUILTIN_VDQF (GETLANE, get_lane, 0)
  46   VAR1 (GETLANE, get_lane, 0, di)
  47   BUILTIN_VDC (COMBINE, combine, 0)
  48   BUILTIN_VB (BINOP, pmul, 0)
  49   BUILTIN_VDQF (UNOP, sqrt, 2)
  50   BUILTIN_VD_BHSI (BINOP, addp, 0)
  51   VAR1 (UNOP, addp, 0, di)
  52   VAR1 (UNOP, clz, 2, v4si)
  53
  54   BUILTIN_VD_RE (REINTERP, reinterpretdi, 0)
  55   BUILTIN_VDC (REINTERP, reinterpretv8qi, 0)
  56   BUILTIN_VDC (REINTERP, reinterpretv4hi, 0)
  57   BUILTIN_VDC (REINTERP, reinterpretv2si, 0)
  58   BUILTIN_VDC (REINTERP, reinterpretv2sf, 0)
  59   BUILTIN_VQ (REINTERP, reinterpretv16qi, 0)
  60   BUILTIN_VQ (REINTERP, reinterpretv8hi, 0)
  61   BUILTIN_VQ (REINTERP, reinterpretv4si, 0)
  62   BUILTIN_VQ (REINTERP, reinterpretv4sf, 0)
  63   BUILTIN_VQ (REINTERP, reinterpretv2di, 0)
  64   BUILTIN_VQ (REINTERP, reinterpretv2df, 0)
  65
  66   BUILTIN_VDQ_I (BINOP, dup_lane, 0)
  67   BUILTIN_VDQ_I (BINOP, dup_lane_scalar, 0)
  68   /* Implemented by aarch64_<sur>q<r>shl<mode>.  */
  69   BUILTIN_VSDQ_I (BINOP, sqshl, 0)
  70   BUILTIN_VSDQ_I (BINOP, uqshl, 0)
  71   BUILTIN_VSDQ_I (BINOP, sqrshl, 0)
  72   BUILTIN_VSDQ_I (BINOP, uqrshl, 0)
  73   /* Implemented by aarch64_<su_optab><optab><mode>.  */
  74   BUILTIN_VSDQ_I (BINOP, sqadd, 0)
  75   BUILTIN_VSDQ_I (BINOP, uqadd, 0)
  76   BUILTIN_VSDQ_I (BINOP, sqsub, 0)
  77   BUILTIN_VSDQ_I (BINOP, uqsub, 0)
  78   /* Implemented by aarch64_<sur>qadd<mode>.  */
  79   BUILTIN_VSDQ_I (BINOP, suqadd, 0)
  80   BUILTIN_VSDQ_I (BINOP, usqadd, 0)
  81
  82   /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>.  */
  83   BUILTIN_VDC (GETLANE, get_dregoi, 0)
  84   BUILTIN_VDC (GETLANE, get_dregci, 0)
  85   BUILTIN_VDC (GETLANE, get_dregxi, 0)
  86   /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>.  */
  87   BUILTIN_VQ (GETLANE, get_qregoi, 0)
  88   BUILTIN_VQ (GETLANE, get_qregci, 0)
  89   BUILTIN_VQ (GETLANE, get_qregxi, 0)
  90   /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>.  */
  91   BUILTIN_VQ (SETLANE, set_qregoi, 0)
  92   BUILTIN_VQ (SETLANE, set_qregci, 0)
  93   BUILTIN_VQ (SETLANE, set_qregxi, 0)
  94   /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>.  */
  95   BUILTIN_VDC (LOADSTRUCT, ld2, 0)
  96   BUILTIN_VDC (LOADSTRUCT, ld3, 0)
  97   BUILTIN_VDC (LOADSTRUCT, ld4, 0)
  98   /* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>.  */
  99   BUILTIN_VQ (LOADSTRUCT, ld2, 0)
 100   BUILTIN_VQ (LOADSTRUCT, ld3, 0)
 101   BUILTIN_VQ (LOADSTRUCT, ld4, 0)
 102   /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>.  */
 103   BUILTIN_VDC (STORESTRUCT, st2, 0)
 104   BUILTIN_VDC (STORESTRUCT, st3, 0)
 105   BUILTIN_VDC (STORESTRUCT, st4, 0)
 106   /* Implemented by aarch64_st<VSTRUCT:nregs><VQ:mode>.  */
 107   BUILTIN_VQ (STORESTRUCT, st2, 0)
 108   BUILTIN_VQ (STORESTRUCT, st3, 0)
 109   BUILTIN_VQ (STORESTRUCT, st4, 0)
 110
 111   BUILTIN_VQW (BINOP, saddl2, 0)
 112   BUILTIN_VQW (BINOP, uaddl2, 0)
 113   BUILTIN_VQW (BINOP, ssubl2, 0)
 114   BUILTIN_VQW (BINOP, usubl2, 0)
 115   BUILTIN_VQW (BINOP, saddw2, 0)
 116   BUILTIN_VQW (BINOP, uaddw2, 0)
 117   BUILTIN_VQW (BINOP, ssubw2, 0)
 118   BUILTIN_VQW (BINOP, usubw2, 0)
 119   /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>.  */
 120   BUILTIN_VDW (BINOP, saddl, 0)
 121   BUILTIN_VDW (BINOP, uaddl, 0)
 122   BUILTIN_VDW (BINOP, ssubl, 0)
 123   BUILTIN_VDW (BINOP, usubl, 0)
 124   /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>.  */
 125   BUILTIN_VDW (BINOP, saddw, 0)
 126   BUILTIN_VDW (BINOP, uaddw, 0)
 127   BUILTIN_VDW (BINOP, ssubw, 0)
 128   BUILTIN_VDW (BINOP, usubw, 0)
 129   /* Implemented by aarch64_<sur>h<addsub><mode>.  */
 130   BUILTIN_VQ_S (BINOP, shadd, 0)
 131   BUILTIN_VQ_S (BINOP, uhadd, 0)
 132   BUILTIN_VQ_S (BINOP, srhadd, 0)
 133   BUILTIN_VQ_S (BINOP, urhadd, 0)
 134   /* Implemented by aarch64_<sur><addsub>hn<mode>.  */
 135   BUILTIN_VQN (BINOP, addhn, 0)
 136   BUILTIN_VQN (BINOP, raddhn, 0)
 137   /* Implemented by aarch64_<sur><addsub>hn2<mode>.  */
 138   BUILTIN_VQN (TERNOP, addhn2, 0)
 139   BUILTIN_VQN (TERNOP, raddhn2, 0)
 140
 141   BUILTIN_VSQN_HSDI (UNOP, sqmovun, 0)
 142   /* Implemented by aarch64_<sur>qmovn<mode>.  */
 143   BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0)
 144   BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0)
 145   /* Implemented by aarch64_s<optab><mode>.  */
 146   BUILTIN_VSDQ_I_BHSI (UNOP, sqabs, 0)
 147   BUILTIN_VSDQ_I_BHSI (UNOP, sqneg, 0)
 148
 149   BUILTIN_VSD_HSI (QUADOP, sqdmlal_lane, 0)
 150   BUILTIN_VSD_HSI (QUADOP, sqdmlsl_lane, 0)
 151   BUILTIN_VSD_HSI (QUADOP, sqdmlal_laneq, 0)
 152   BUILTIN_VSD_HSI (QUADOP, sqdmlsl_laneq, 0)
 153   BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0)
 154   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0)
 155   BUILTIN_VQ_HSI (QUADOP, sqdmlal2_lane, 0)
 156   BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_lane, 0)
 157   BUILTIN_VQ_HSI (QUADOP, sqdmlal2_laneq, 0)
 158   BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_laneq, 0)
 159   BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0)
 160   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0)
 161   /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>.  */
 162   BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0)
 163   BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0)
 164   /* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>.  */
 165   BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0)
 166   BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0)
 167
 168   BUILTIN_VSD_HSI (BINOP, sqdmull, 0)
 169   BUILTIN_VSD_HSI (TERNOP, sqdmull_lane, 0)
 170   BUILTIN_VD_HSI (TERNOP, sqdmull_laneq, 0)
 171   BUILTIN_VD_HSI (BINOP, sqdmull_n, 0)
 172   BUILTIN_VQ_HSI (BINOP, sqdmull2, 0)
 173   BUILTIN_VQ_HSI (TERNOP, sqdmull2_lane, 0)
 174   BUILTIN_VQ_HSI (TERNOP, sqdmull2_laneq, 0)
 175   BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0)
 176   /* Implemented by aarch64_sq<r>dmulh<mode>.  */
 177   BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0)
 178   BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0)
 179   /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>.  */
 180   BUILTIN_VDQHS (TERNOP, sqdmulh_lane, 0)
 181   BUILTIN_VDQHS (TERNOP, sqdmulh_laneq, 0)
 182   BUILTIN_VDQHS (TERNOP, sqrdmulh_lane, 0)
 183   BUILTIN_VDQHS (TERNOP, sqrdmulh_laneq, 0)
 184   BUILTIN_SD_HSI (TERNOP, sqdmulh_lane, 0)
 185   BUILTIN_SD_HSI (TERNOP, sqrdmulh_lane, 0)
 186
 187   BUILTIN_VSDQ_I_DI (BINOP, ashl, 3)
 188   /* Implemented by aarch64_<sur>shl<mode>.  */
 189   BUILTIN_VSDQ_I_DI (BINOP, sshl, 0)
 190   BUILTIN_VSDQ_I_DI (BINOP, ushl, 0)
 191   BUILTIN_VSDQ_I_DI (BINOP, srshl, 0)
 192   BUILTIN_VSDQ_I_DI (BINOP, urshl, 0)
 193
 194   BUILTIN_VSDQ_I_DI (SHIFTIMM, ashr, 3)
 195   BUILTIN_VSDQ_I_DI (SHIFTIMM, lshr, 3)
 196   /* Implemented by aarch64_<sur>shr_n<mode>.  */
 197   BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0)
 198   BUILTIN_VSDQ_I_DI (SHIFTIMM, urshr_n, 0)
 199   /* Implemented by aarch64_<sur>sra_n<mode>.  */
 200   BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0)
 201   BUILTIN_VSDQ_I_DI (SHIFTACC, usra_n, 0)
 202   BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0)
 203   BUILTIN_VSDQ_I_DI (SHIFTACC, ursra_n, 0)
 204   /* Implemented by aarch64_<sur>shll_n<mode>.  */
 205   BUILTIN_VDW (SHIFTIMM, sshll_n, 0)
 206   BUILTIN_VDW (SHIFTIMM, ushll_n, 0)
 207   /* Implemented by aarch64_<sur>shll2_n<mode>.  */
 208   BUILTIN_VQW (SHIFTIMM, sshll2_n, 0)
 209   BUILTIN_VQW (SHIFTIMM, ushll2_n, 0)
 210   /* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>.  */
 211   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0)
 212   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0)
 213   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n, 0)
 214   BUILTIN_VSQN_HSDI (SHIFTIMM, uqshrn_n, 0)
 215   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0)
 216   BUILTIN_VSQN_HSDI (SHIFTIMM, uqrshrn_n, 0)
 217   /* Implemented by aarch64_<sur>s<lr>i_n<mode>.  */
 218   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0)
 219   BUILTIN_VSDQ_I_DI (SHIFTINSERT, usri_n, 0)
 220   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0)
 221   BUILTIN_VSDQ_I_DI (SHIFTINSERT, usli_n, 0)
 222   /* Implemented by aarch64_<sur>qshl<u>_n<mode>.  */
 223   BUILTIN_VSDQ_I (SHIFTIMM, sqshlu_n, 0)
 224   BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0)
 225   BUILTIN_VSDQ_I (SHIFTIMM, uqshl_n, 0)
 226
 227   /* Implemented by aarch64_cm<cmp><mode>.  */
 228   BUILTIN_VALLDI (BINOP, cmeq, 0)
 229   BUILTIN_VALLDI (BINOP, cmge, 0)
 230   BUILTIN_VALLDI (BINOP, cmgt, 0)
 231   BUILTIN_VALLDI (BINOP, cmle, 0)
 232   BUILTIN_VALLDI (BINOP, cmlt, 0)
 233   /* Implemented by aarch64_cm<cmp><mode>.  */
 234   BUILTIN_VSDQ_I_DI (BINOP, cmgeu, 0)
 235   BUILTIN_VSDQ_I_DI (BINOP, cmgtu, 0)
 236   BUILTIN_VSDQ_I_DI (BINOP, cmtst, 0)
 237
 238   /* Implemented by reduc_<sur>plus_<mode>.  */
 239   BUILTIN_VALL (UNOP, reduc_splus_, 10)
 240   BUILTIN_VDQ (UNOP, reduc_uplus_, 10)
 241
 242   /* Implemented by reduc_<maxmin_uns>_<mode>.  */
 243   BUILTIN_VDQIF (UNOP, reduc_smax_, 10)
 244   BUILTIN_VDQIF (UNOP, reduc_smin_, 10)
 245   BUILTIN_VDQ_BHSI (UNOP, reduc_umax_, 10)
 246   BUILTIN_VDQ_BHSI (UNOP, reduc_umin_, 10)
 247   BUILTIN_VDQF (UNOP, reduc_smax_nan_, 10)
 248   BUILTIN_VDQF (UNOP, reduc_smin_nan_, 10)
 249
 250   /* Implemented by <maxmin><mode>3.
 251      smax variants map to fmaxnm,
 252      smax_nan variants map to fmax.  */
 253   BUILTIN_VDQIF (BINOP, smax, 3)
 254   BUILTIN_VDQIF (BINOP, smin, 3)
 255   BUILTIN_VDQ_BHSI (BINOP, umax, 3)
 256   BUILTIN_VDQ_BHSI (BINOP, umin, 3)
 257   BUILTIN_VDQF (BINOP, smax_nan, 3)
 258   BUILTIN_VDQF (BINOP, smin_nan, 3)
 259
 260   /* Implemented by <frint_pattern><mode>2.  */
 261   BUILTIN_VDQF (UNOP, btrunc, 2)
 262   BUILTIN_VDQF (UNOP, ceil, 2)
 263   BUILTIN_VDQF (UNOP, floor, 2)
 264   BUILTIN_VDQF (UNOP, nearbyint, 2)
 265   BUILTIN_VDQF (UNOP, rint, 2)
 266   BUILTIN_VDQF (UNOP, round, 2)
 267   BUILTIN_VDQF (UNOP, frintn, 2)
 268
 269   /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2.  */
 270   VAR1 (UNOP, lbtruncv2sf, 2, v2si)
 271   VAR1 (UNOP, lbtruncv4sf, 2, v4si)
 272   VAR1 (UNOP, lbtruncv2df, 2, v2di)
 273
 274   VAR1 (UNOP, lbtruncuv2sf, 2, v2si)
 275   VAR1 (UNOP, lbtruncuv4sf, 2, v4si)
 276   VAR1 (UNOP, lbtruncuv2df, 2, v2di)
 277
 278   VAR1 (UNOP, lroundv2sf, 2, v2si)
 279   VAR1 (UNOP, lroundv4sf, 2, v4si)
 280   VAR1 (UNOP, lroundv2df, 2, v2di)
 281   /* Implemented by l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2.  */
 282   VAR1 (UNOP, lroundsf, 2, si)
 283   VAR1 (UNOP, lrounddf, 2, di)
 284
 285   VAR1 (UNOP, lrounduv2sf, 2, v2si)
 286   VAR1 (UNOP, lrounduv4sf, 2, v4si)
 287   VAR1 (UNOP, lrounduv2df, 2, v2di)
 288   VAR1 (UNOP, lroundusf, 2, si)
 289   VAR1 (UNOP, lroundudf, 2, di)
 290
 291   VAR1 (UNOP, lceilv2sf, 2, v2si)
 292   VAR1 (UNOP, lceilv4sf, 2, v4si)
 293   VAR1 (UNOP, lceilv2df, 2, v2di)
 294
 295   VAR1 (UNOP, lceiluv2sf, 2, v2si)
 296   VAR1 (UNOP, lceiluv4sf, 2, v4si)
 297   VAR1 (UNOP, lceiluv2df, 2, v2di)
 298   VAR1 (UNOP, lceilusf, 2, si)
 299   VAR1 (UNOP, lceiludf, 2, di)
 300
 301   VAR1 (UNOP, lfloorv2sf, 2, v2si)
 302   VAR1 (UNOP, lfloorv4sf, 2, v4si)
 303   VAR1 (UNOP, lfloorv2df, 2, v2di)
 304
 305   VAR1 (UNOP, lflooruv2sf, 2, v2si)
 306   VAR1 (UNOP, lflooruv4sf, 2, v4si)
 307   VAR1 (UNOP, lflooruv2df, 2, v2di)
 308   VAR1 (UNOP, lfloorusf, 2, si)
 309   VAR1 (UNOP, lfloorudf, 2, di)
 310
 311   VAR1 (UNOP, lfrintnv2sf, 2, v2si)
 312   VAR1 (UNOP, lfrintnv4sf, 2, v4si)
 313   VAR1 (UNOP, lfrintnv2df, 2, v2di)
 314   VAR1 (UNOP, lfrintnsf, 2, si)
 315   VAR1 (UNOP, lfrintndf, 2, di)
 316
 317   VAR1 (UNOP, lfrintnuv2sf, 2, v2si)
 318   VAR1 (UNOP, lfrintnuv4sf, 2, v4si)
 319   VAR1 (UNOP, lfrintnuv2df, 2, v2di)
 320   VAR1 (UNOP, lfrintnusf, 2, si)
 321   VAR1 (UNOP, lfrintnudf, 2, di)
 322
 323   /* Implemented by <optab><fcvt_target><VDQF:mode>2.  */
 324   VAR1 (UNOP, floatv2si, 2, v2sf)
 325   VAR1 (UNOP, floatv4si, 2, v4sf)
 326   VAR1 (UNOP, floatv2di, 2, v2df)
 327
 328   VAR1 (UNOP, floatunsv2si, 2, v2sf)
 329   VAR1 (UNOP, floatunsv4si, 2, v4sf)
 330   VAR1 (UNOP, floatunsv2di, 2, v2df)
 331
 332   /* Implemented by
 333      aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>.  */
 334   BUILTIN_VALL (BINOP, zip1, 0)
 335   BUILTIN_VALL (BINOP, zip2, 0)
 336   BUILTIN_VALL (BINOP, uzp1, 0)
 337   BUILTIN_VALL (BINOP, uzp2, 0)
 338   BUILTIN_VALL (BINOP, trn1, 0)
 339   BUILTIN_VALL (BINOP, trn2, 0)
 340
 341   /* Implemented by
 342      aarch64_frecp<FRECP:frecp_suffix><mode>.  */
 343   BUILTIN_GPF (UNOP, frecpe, 0)
 344   BUILTIN_GPF (BINOP, frecps, 0)
 345   BUILTIN_GPF (UNOP, frecpx, 0)
 346
 347   BUILTIN_VDQF (UNOP, frecpe, 0)
 348   BUILTIN_VDQF (BINOP, frecps, 0)
 349
 350   BUILTIN_VALLDI (UNOP, abs, 2)
 351
 352   VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf)
 353   VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
 354
 355   VAR1 (UNOP, float_extend_lo_, 0, v2df)
 356   VAR1 (UNOP, float_truncate_lo_, 0, v2sf)
 357
 358   /* Implemented by aarch64_ld1<VALL:mode>.  */
 359   BUILTIN_VALL (LOAD1, ld1, 0)
 360
 361   /* Implemented by aarch64_st1<VALL:mode>.  */
 362   BUILTIN_VALL (STORE1, st1, 0)
 363