1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "insn-config.h"
28 #include "insn-attr.h"
29 #include "hard-reg-set.h"
36 #include "basic-block.h"
40 #ifndef STACK_PUSH_CODE
41 #ifdef STACK_GROWS_DOWNWARD
42 #define STACK_PUSH_CODE PRE_DEC
44 #define STACK_PUSH_CODE PRE_INC
48 #ifndef STACK_POP_CODE
49 #ifdef STACK_GROWS_DOWNWARD
50 #define STACK_POP_CODE POST_INC
52 #define STACK_POP_CODE POST_DEC
56 static void validate_replace_rtx_1
PARAMS ((rtx
*, rtx
, rtx
, rtx
));
57 static rtx
*find_single_use_1
PARAMS ((rtx
, rtx
*));
58 static rtx
*find_constant_term_loc
PARAMS ((rtx
*));
59 static int insn_invalid_p
PARAMS ((rtx
));
61 /* Nonzero means allow operands to be volatile.
62 This should be 0 if you are generating rtl, such as if you are calling
63 the functions in optabs.c and expmed.c (most of the time).
64 This should be 1 if all valid insns need to be recognized,
65 such as in regclass.c and final.c and reload.c.
67 init_recog and init_recog_no_volatile are responsible for setting this. */
71 struct recog_data recog_data
;
73 /* Contains a vector of operand_alternative structures for every operand.
74 Set up by preprocess_constraints. */
75 struct operand_alternative recog_op_alt
[MAX_RECOG_OPERANDS
][MAX_RECOG_ALTERNATIVES
];
77 /* On return from `constrain_operands', indicate which alternative
80 int which_alternative
;
82 /* Nonzero after end of reload pass.
83 Set to 1 or 0 by toplev.c.
84 Controls the significance of (SUBREG (MEM)). */
88 /* Initialize data used by the function `recog'.
89 This must be called once in the compilation of a function
90 before any insn recognition may be done in the function. */
93 init_recog_no_volatile ()
104 /* Try recognizing the instruction INSN,
105 and return the code number that results.
106 Remember the code so that repeated calls do not
107 need to spend the time for actual rerecognition.
109 This function is the normal interface to instruction recognition.
110 The automatically-generated function `recog' is normally called
111 through this one. (The only exception is in combine.c.) */
114 recog_memoized_1 (insn
)
117 if (INSN_CODE (insn
) < 0)
118 INSN_CODE (insn
) = recog (PATTERN (insn
), insn
, NULL_PTR
);
119 return INSN_CODE (insn
);
122 /* Check that X is an insn-body for an `asm' with operands
123 and that the operands mentioned in it are legitimate. */
126 check_asm_operands (x
)
131 const char **constraints
;
134 /* Post-reload, be more strict with things. */
135 if (reload_completed
)
137 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
138 extract_insn (make_insn_raw (x
));
139 constrain_operands (1);
140 return which_alternative
>= 0;
143 noperands
= asm_noperands (x
);
149 operands
= (rtx
*) alloca (noperands
* sizeof (rtx
));
150 constraints
= (const char **) alloca (noperands
* sizeof (char *));
152 decode_asm_operands (x
, operands
, NULL_PTR
, constraints
, NULL_PTR
);
154 for (i
= 0; i
< noperands
; i
++)
156 const char *c
= constraints
[i
];
159 if (ISDIGIT ((unsigned char)c
[0]) && c
[1] == '\0')
160 c
= constraints
[c
[0] - '0'];
162 if (! asm_operand_ok (operands
[i
], c
))
169 /* Static data for the next two routines. */
171 typedef struct change_t
179 static change_t
*changes
;
180 static int changes_allocated
;
182 static int num_changes
= 0;
184 /* Validate a proposed change to OBJECT. LOC is the location in the rtl for
185 at which NEW will be placed. If OBJECT is zero, no validation is done,
186 the change is simply made.
188 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
189 will be called with the address and mode as parameters. If OBJECT is
190 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
193 IN_GROUP is non-zero if this is part of a group of changes that must be
194 performed as a group. In that case, the changes will be stored. The
195 function `apply_change_group' will validate and apply the changes.
197 If IN_GROUP is zero, this is a single change. Try to recognize the insn
198 or validate the memory reference with the change applied. If the result
199 is not valid for the machine, suppress the change and return zero.
200 Otherwise, perform the change and return 1. */
203 validate_change (object
, loc
, new, in_group
)
211 if (old
== new || rtx_equal_p (old
, new))
214 if (in_group
== 0 && num_changes
!= 0)
219 /* Save the information describing this change. */
220 if (num_changes
>= changes_allocated
)
222 if (changes_allocated
== 0)
223 /* This value allows for repeated substitutions inside complex
224 indexed addresses, or changes in up to 5 insns. */
225 changes_allocated
= MAX_RECOG_OPERANDS
* 5;
227 changes_allocated
*= 2;
230 (change_t
*) xrealloc (changes
,
231 sizeof (change_t
) * changes_allocated
);
234 changes
[num_changes
].object
= object
;
235 changes
[num_changes
].loc
= loc
;
236 changes
[num_changes
].old
= old
;
238 if (object
&& GET_CODE (object
) != MEM
)
240 /* Set INSN_CODE to force rerecognition of insn. Save old code in
242 changes
[num_changes
].old_code
= INSN_CODE (object
);
243 INSN_CODE (object
) = -1;
248 /* If we are making a group of changes, return 1. Otherwise, validate the
249 change group we made. */
254 return apply_change_group ();
257 /* This subroutine of apply_change_group verifies whether the changes to INSN
258 were valid; i.e. whether INSN can still be recognized. */
261 insn_invalid_p (insn
)
264 int icode
= recog_memoized (insn
);
265 int is_asm
= icode
< 0 && asm_noperands (PATTERN (insn
)) >= 0;
267 if (is_asm
&& ! check_asm_operands (PATTERN (insn
)))
269 if (! is_asm
&& icode
< 0)
272 /* After reload, verify that all constraints are satisfied. */
273 if (reload_completed
)
277 if (! constrain_operands (1))
284 /* Apply a group of changes previously issued with `validate_change'.
285 Return 1 if all changes are valid, zero otherwise. */
288 apply_change_group ()
292 /* The changes have been applied and all INSN_CODEs have been reset to force
295 The changes are valid if we aren't given an object, or if we are
296 given a MEM and it still is a valid address, or if this is in insn
297 and it is recognized. In the latter case, if reload has completed,
298 we also require that the operands meet the constraints for
301 for (i
= 0; i
< num_changes
; i
++)
303 rtx object
= changes
[i
].object
;
308 if (GET_CODE (object
) == MEM
)
310 if (! memory_address_p (GET_MODE (object
), XEXP (object
, 0)))
313 else if (insn_invalid_p (object
))
315 rtx pat
= PATTERN (object
);
317 /* Perhaps we couldn't recognize the insn because there were
318 extra CLOBBERs at the end. If so, try to re-recognize
319 without the last CLOBBER (later iterations will cause each of
320 them to be eliminated, in turn). But don't do this if we
321 have an ASM_OPERAND. */
322 if (GET_CODE (pat
) == PARALLEL
323 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
324 && asm_noperands (PATTERN (object
)) < 0)
328 if (XVECLEN (pat
, 0) == 2)
329 newpat
= XVECEXP (pat
, 0, 0);
335 = gen_rtx_PARALLEL (VOIDmode
,
336 rtvec_alloc (XVECLEN (pat
, 0) - 1));
337 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
338 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
341 /* Add a new change to this group to replace the pattern
342 with this new pattern. Then consider this change
343 as having succeeded. The change we added will
344 cause the entire call to fail if things remain invalid.
346 Note that this can lose if a later change than the one
347 we are processing specified &XVECEXP (PATTERN (object), 0, X)
348 but this shouldn't occur. */
350 validate_change (object
, &PATTERN (object
), newpat
, 1);
352 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
)
353 /* If this insn is a CLOBBER or USE, it is always valid, but is
361 if (i
== num_changes
)
373 /* Return the number of changes so far in the current group. */
376 num_validated_changes ()
381 /* Retract the changes numbered NUM and up. */
389 /* Back out all the changes. Do this in the opposite order in which
391 for (i
= num_changes
- 1; i
>= num
; i
--)
393 *changes
[i
].loc
= changes
[i
].old
;
394 if (changes
[i
].object
&& GET_CODE (changes
[i
].object
) != MEM
)
395 INSN_CODE (changes
[i
].object
) = changes
[i
].old_code
;
400 /* Replace every occurrence of FROM in X with TO. Mark each change with
401 validate_change passing OBJECT. */
404 validate_replace_rtx_1 (loc
, from
, to
, object
)
406 rtx from
, to
, object
;
409 register const char *fmt
;
410 register rtx x
= *loc
;
416 /* X matches FROM if it is the same rtx or they are both referring to the
417 same register in the same mode. Avoid calling rtx_equal_p unless the
418 operands look similar. */
421 || (GET_CODE (x
) == REG
&& GET_CODE (from
) == REG
422 && GET_MODE (x
) == GET_MODE (from
)
423 && REGNO (x
) == REGNO (from
))
424 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
425 && rtx_equal_p (x
, from
)))
427 validate_change (object
, loc
, to
, 1);
431 /* For commutative or comparison operations, try replacing each argument
432 separately and seeing if we made any changes. If so, put a constant
434 if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
436 int prev_changes
= num_changes
;
438 validate_replace_rtx_1 (&XEXP (x
, 0), from
, to
, object
);
439 validate_replace_rtx_1 (&XEXP (x
, 1), from
, to
, object
);
440 if (prev_changes
!= num_changes
&& CONSTANT_P (XEXP (x
, 0)))
442 validate_change (object
, loc
,
443 gen_rtx_fmt_ee (GET_RTX_CLASS (code
) == 'c' ? code
444 : swap_condition (code
),
445 GET_MODE (x
), XEXP (x
, 1),
453 /* Note that if CODE's RTX_CLASS is "c" or "<" we will have already
454 done the substitution, otherwise we won't. */
459 /* If we have a PLUS whose second operand is now a CONST_INT, use
460 plus_constant to try to simplify it. */
461 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& XEXP (x
, 1) == to
)
462 validate_change (object
, loc
, plus_constant (XEXP (x
, 0), INTVAL (to
)),
467 if (GET_CODE (to
) == CONST_INT
&& XEXP (x
, 1) == from
)
469 validate_change (object
, loc
,
470 plus_constant (XEXP (x
, 0), - INTVAL (to
)),
478 /* In these cases, the operation to be performed depends on the mode
479 of the operand. If we are replacing the operand with a VOIDmode
480 constant, we lose the information. So try to simplify the operation
482 if (GET_MODE (to
) == VOIDmode
483 && (rtx_equal_p (XEXP (x
, 0), from
)
484 || (GET_CODE (XEXP (x
, 0)) == SUBREG
485 && rtx_equal_p (SUBREG_REG (XEXP (x
, 0)), from
))))
489 /* If there is a subreg involved, crop to the portion of the
490 constant that we are interested in. */
491 if (GET_CODE (XEXP (x
, 0)) == SUBREG
)
493 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) <= UNITS_PER_WORD
)
494 to
= operand_subword (to
, SUBREG_WORD (XEXP (x
, 0)),
496 else if (GET_MODE_CLASS (GET_MODE (from
)) == MODE_INT
497 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
498 <= HOST_BITS_PER_WIDE_INT
))
500 int i
= SUBREG_WORD (XEXP (x
, 0)) * BITS_PER_WORD
;
502 unsigned HOST_WIDE_INT vall
;
504 if (GET_CODE (to
) == CONST_INT
)
507 valh
= (HOST_WIDE_INT
) vall
< 0 ? ~0 : 0;
511 vall
= CONST_DOUBLE_LOW (to
);
512 valh
= CONST_DOUBLE_HIGH (to
);
515 if (WORDS_BIG_ENDIAN
)
516 i
= (GET_MODE_BITSIZE (GET_MODE (from
))
517 - GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - i
);
518 if (i
> 0 && i
< HOST_BITS_PER_WIDE_INT
)
519 vall
= vall
>> i
| valh
<< (HOST_BITS_PER_WIDE_INT
- i
);
520 else if (i
>= HOST_BITS_PER_WIDE_INT
)
521 vall
= valh
>> (i
- HOST_BITS_PER_WIDE_INT
);
522 to
= GEN_INT (trunc_int_for_mode (vall
,
523 GET_MODE (XEXP (x
, 0))));
526 to
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
529 /* If the above didn't fail, perform the extension from the
530 mode of the operand (and not the mode of FROM). */
532 new = simplify_unary_operation (code
, GET_MODE (x
), to
,
533 GET_MODE (XEXP (x
, 0)));
535 /* If any of the above failed, substitute in something that
536 we know won't be recognized. */
538 new = gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
540 validate_change (object
, loc
, new, 1);
546 /* In case we are replacing by constant, attempt to simplify it to non-SUBREG
547 expression. We can't do this later, since the information about inner mode
549 if (CONSTANT_P (to
) && rtx_equal_p (SUBREG_REG (x
), from
))
551 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
552 && GET_MODE_SIZE (GET_MODE (from
)) > UNITS_PER_WORD
553 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
)
555 rtx temp
= operand_subword (to
, SUBREG_WORD (x
),
559 validate_change (object
, loc
, temp
, 1);
563 if (subreg_lowpart_p (x
))
565 rtx
new = gen_lowpart_if_possible (GET_MODE (x
), to
);
568 validate_change (object
, loc
, new, 1);
573 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
574 since we are saying that the high bits don't matter. */
575 if (GET_MODE (to
) == VOIDmode
576 && GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (from
)))
578 validate_change (object
, loc
, to
, 1);
583 /* Changing mode twice with SUBREG => just change it once,
584 or not at all if changing back to starting mode. */
585 if (GET_CODE (to
) == SUBREG
586 && rtx_equal_p (SUBREG_REG (x
), from
))
588 if (GET_MODE (x
) == GET_MODE (SUBREG_REG (to
))
589 && SUBREG_WORD (x
) == 0 && SUBREG_WORD (to
) == 0)
591 validate_change (object
, loc
, SUBREG_REG (to
), 1);
595 validate_change (object
, loc
,
596 gen_rtx_SUBREG (GET_MODE (x
), SUBREG_REG (to
),
597 SUBREG_WORD (x
) + SUBREG_WORD (to
)), 1);
601 /* If we have a SUBREG of a register that we are replacing and we are
602 replacing it with a MEM, make a new MEM and try replacing the
603 SUBREG with it. Don't do this if the MEM has a mode-dependent address
604 or if we would be widening it. */
606 if (GET_CODE (from
) == REG
607 && GET_CODE (to
) == MEM
608 && rtx_equal_p (SUBREG_REG (x
), from
)
609 && ! mode_dependent_address_p (XEXP (to
, 0))
610 && ! MEM_VOLATILE_P (to
)
611 && GET_MODE_SIZE (GET_MODE (x
)) <= GET_MODE_SIZE (GET_MODE (to
)))
613 int offset
= SUBREG_WORD (x
) * UNITS_PER_WORD
;
614 enum machine_mode mode
= GET_MODE (x
);
617 if (BYTES_BIG_ENDIAN
)
618 offset
+= (MIN (UNITS_PER_WORD
,
619 GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
620 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
)));
622 new = gen_rtx_MEM (mode
, plus_constant (XEXP (to
, 0), offset
));
623 MEM_COPY_ATTRIBUTES (new, to
);
624 validate_change (object
, loc
, new, 1);
631 /* If we are replacing a register with memory, try to change the memory
632 to be the mode required for memory in extract operations (this isn't
633 likely to be an insertion operation; if it was, nothing bad will
634 happen, we might just fail in some cases). */
636 if (GET_CODE (from
) == REG
&& GET_CODE (to
) == MEM
637 && rtx_equal_p (XEXP (x
, 0), from
)
638 && GET_CODE (XEXP (x
, 1)) == CONST_INT
639 && GET_CODE (XEXP (x
, 2)) == CONST_INT
640 && ! mode_dependent_address_p (XEXP (to
, 0))
641 && ! MEM_VOLATILE_P (to
))
643 enum machine_mode wanted_mode
= VOIDmode
;
644 enum machine_mode is_mode
= GET_MODE (to
);
645 int pos
= INTVAL (XEXP (x
, 2));
648 if (code
== ZERO_EXTRACT
)
650 wanted_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
651 if (wanted_mode
== VOIDmode
)
652 wanted_mode
= word_mode
;
656 if (code
== SIGN_EXTRACT
)
658 wanted_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[1].mode
;
659 if (wanted_mode
== VOIDmode
)
660 wanted_mode
= word_mode
;
664 /* If we have a narrower mode, we can do something. */
665 if (wanted_mode
!= VOIDmode
666 && GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
668 int offset
= pos
/ BITS_PER_UNIT
;
671 /* If the bytes and bits are counted differently, we
672 must adjust the offset. */
673 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
674 offset
= (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
)
677 pos
%= GET_MODE_BITSIZE (wanted_mode
);
679 newmem
= gen_rtx_MEM (wanted_mode
,
680 plus_constant (XEXP (to
, 0), offset
));
681 MEM_COPY_ATTRIBUTES (newmem
, to
);
683 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
684 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
694 /* For commutative or comparison operations we've already performed
695 replacements. Don't try to perform them again. */
696 if (GET_RTX_CLASS (code
) != '<' && GET_RTX_CLASS (code
) != 'c')
698 fmt
= GET_RTX_FORMAT (code
);
699 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
702 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
);
703 else if (fmt
[i
] == 'E')
704 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
705 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
);
710 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
711 with TO. After all changes have been made, validate by seeing
712 if INSN is still valid. */
715 validate_replace_rtx_subexp (from
, to
, insn
, loc
)
716 rtx from
, to
, insn
, *loc
;
718 validate_replace_rtx_1 (loc
, from
, to
, insn
);
719 return apply_change_group ();
722 /* Try replacing every occurrence of FROM in INSN with TO. After all
723 changes have been made, validate by seeing if INSN is still valid. */
726 validate_replace_rtx (from
, to
, insn
)
729 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
);
730 return apply_change_group ();
733 /* Try replacing every occurrence of FROM in INSN with TO. After all
734 changes have been made, validate by seeing if INSN is still valid. */
737 validate_replace_rtx_group (from
, to
, insn
)
740 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
);
743 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
744 SET_DESTs. After all changes have been made, validate by seeing if
745 INSN is still valid. */
748 validate_replace_src (from
, to
, insn
)
751 if ((GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != JUMP_INSN
)
752 || GET_CODE (PATTERN (insn
)) != SET
)
755 validate_replace_rtx_1 (&SET_SRC (PATTERN (insn
)), from
, to
, insn
);
756 if (GET_CODE (SET_DEST (PATTERN (insn
))) == MEM
)
757 validate_replace_rtx_1 (&XEXP (SET_DEST (PATTERN (insn
)), 0),
759 return apply_change_group ();
763 /* Return 1 if the insn using CC0 set by INSN does not contain
764 any ordered tests applied to the condition codes.
765 EQ and NE tests do not count. */
768 next_insn_tests_no_inequality (insn
)
771 register rtx next
= next_cc0_user (insn
);
773 /* If there is no next insn, we have to take the conservative choice. */
777 return ((GET_CODE (next
) == JUMP_INSN
778 || GET_CODE (next
) == INSN
779 || GET_CODE (next
) == CALL_INSN
)
780 && ! inequality_comparisons_p (PATTERN (next
)));
783 #if 0 /* This is useless since the insn that sets the cc's
784 must be followed immediately by the use of them. */
785 /* Return 1 if the CC value set up by INSN is not used. */
788 next_insns_test_no_inequality (insn
)
791 register rtx next
= NEXT_INSN (insn
);
793 for (; next
!= 0; next
= NEXT_INSN (next
))
795 if (GET_CODE (next
) == CODE_LABEL
796 || GET_CODE (next
) == BARRIER
)
798 if (GET_CODE (next
) == NOTE
)
800 if (inequality_comparisons_p (PATTERN (next
)))
802 if (sets_cc0_p (PATTERN (next
)) == 1)
804 if (! reg_mentioned_p (cc0_rtx
, PATTERN (next
)))
812 /* This is used by find_single_use to locate an rtx that contains exactly one
813 use of DEST, which is typically either a REG or CC0. It returns a
814 pointer to the innermost rtx expression containing DEST. Appearances of
815 DEST that are being used to totally replace it are not counted. */
818 find_single_use_1 (dest
, loc
)
823 enum rtx_code code
= GET_CODE (x
);
840 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
841 of a REG that occupies all of the REG, the insn uses DEST if
842 it is mentioned in the destination or the source. Otherwise, we
843 need just check the source. */
844 if (GET_CODE (SET_DEST (x
)) != CC0
845 && GET_CODE (SET_DEST (x
)) != PC
846 && GET_CODE (SET_DEST (x
)) != REG
847 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
848 && GET_CODE (SUBREG_REG (SET_DEST (x
))) == REG
849 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
850 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
851 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
852 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
855 return find_single_use_1 (dest
, &SET_SRC (x
));
859 return find_single_use_1 (dest
, &XEXP (x
, 0));
865 /* If it wasn't one of the common cases above, check each expression and
866 vector of this code. Look for a unique usage of DEST. */
868 fmt
= GET_RTX_FORMAT (code
);
869 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
873 if (dest
== XEXP (x
, i
)
874 || (GET_CODE (dest
) == REG
&& GET_CODE (XEXP (x
, i
)) == REG
875 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
878 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
881 result
= this_result
;
882 else if (this_result
)
883 /* Duplicate usage. */
886 else if (fmt
[i
] == 'E')
890 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
892 if (XVECEXP (x
, i
, j
) == dest
893 || (GET_CODE (dest
) == REG
894 && GET_CODE (XVECEXP (x
, i
, j
)) == REG
895 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
898 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
901 result
= this_result
;
902 else if (this_result
)
911 /* See if DEST, produced in INSN, is used only a single time in the
912 sequel. If so, return a pointer to the innermost rtx expression in which
915 If PLOC is non-zero, *PLOC is set to the insn containing the single use.
917 This routine will return usually zero either before flow is called (because
918 there will be no LOG_LINKS notes) or after reload (because the REG_DEAD
919 note can't be trusted).
921 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
922 care about REG_DEAD notes or LOG_LINKS.
924 Otherwise, we find the single use by finding an insn that has a
925 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
926 only referenced once in that insn, we know that it must be the first
927 and last insn referencing DEST. */
930 find_single_use (dest
, insn
, ploc
)
942 next
= NEXT_INSN (insn
);
944 || (GET_CODE (next
) != INSN
&& GET_CODE (next
) != JUMP_INSN
))
947 result
= find_single_use_1 (dest
, &PATTERN (next
));
954 if (reload_completed
|| reload_in_progress
|| GET_CODE (dest
) != REG
)
957 for (next
= next_nonnote_insn (insn
);
958 next
!= 0 && GET_CODE (next
) != CODE_LABEL
;
959 next
= next_nonnote_insn (next
))
960 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
962 for (link
= LOG_LINKS (next
); link
; link
= XEXP (link
, 1))
963 if (XEXP (link
, 0) == insn
)
968 result
= find_single_use_1 (dest
, &PATTERN (next
));
978 /* Return 1 if OP is a valid general operand for machine mode MODE.
979 This is either a register reference, a memory reference,
980 or a constant. In the case of a memory reference, the address
981 is checked for general validity for the target machine.
983 Register and memory references must have mode MODE in order to be valid,
984 but some constants have no machine mode and are valid for any mode.
986 If MODE is VOIDmode, OP is checked for validity for whatever mode
989 The main use of this function is as a predicate in match_operand
990 expressions in the machine description.
992 For an explanation of this function's behavior for registers of
993 class NO_REGS, see the comment for `register_operand'. */
996 general_operand (op
, mode
)
998 enum machine_mode mode
;
1000 register enum rtx_code code
= GET_CODE (op
);
1001 int mode_altering_drug
= 0;
1003 if (mode
== VOIDmode
)
1004 mode
= GET_MODE (op
);
1006 /* Don't accept CONST_INT or anything similar
1007 if the caller wants something floating. */
1008 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1009 && GET_MODE_CLASS (mode
) != MODE_INT
1010 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1013 if (CONSTANT_P (op
))
1014 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
1015 || mode
== VOIDmode
)
1016 #ifdef LEGITIMATE_PIC_OPERAND_P
1017 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1019 && LEGITIMATE_CONSTANT_P (op
));
1021 /* Except for certain constants with VOIDmode, already checked for,
1022 OP's mode must match MODE if MODE specifies a mode. */
1024 if (GET_MODE (op
) != mode
)
1029 #ifdef INSN_SCHEDULING
1030 /* On machines that have insn scheduling, we want all memory
1031 reference to be explicit, so outlaw paradoxical SUBREGs. */
1032 if (GET_CODE (SUBREG_REG (op
)) == MEM
1033 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
))))
1037 op
= SUBREG_REG (op
);
1038 code
= GET_CODE (op
);
1040 /* No longer needed, since (SUBREG (MEM...))
1041 will load the MEM into a reload reg in the MEM's own mode. */
1042 mode_altering_drug
= 1;
1047 /* A register whose class is NO_REGS is not a general operand. */
1048 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1049 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
);
1053 register rtx y
= XEXP (op
, 0);
1055 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
1058 if (GET_CODE (y
) == ADDRESSOF
)
1061 /* Use the mem's mode, since it will be reloaded thus. */
1062 mode
= GET_MODE (op
);
1063 GO_IF_LEGITIMATE_ADDRESS (mode
, y
, win
);
1066 /* Pretend this is an operand for now; we'll run force_operand
1067 on its replacement in fixup_var_refs_1. */
1068 if (code
== ADDRESSOF
)
1074 if (mode_altering_drug
)
1075 return ! mode_dependent_address_p (XEXP (op
, 0));
1079 /* Return 1 if OP is a valid memory address for a memory reference
1082 The main use of this function is as a predicate in match_operand
1083 expressions in the machine description. */
1086 address_operand (op
, mode
)
1088 enum machine_mode mode
;
1090 return memory_address_p (mode
, op
);
1093 /* Return 1 if OP is a register reference of mode MODE.
1094 If MODE is VOIDmode, accept a register in any mode.
1096 The main use of this function is as a predicate in match_operand
1097 expressions in the machine description.
1099 As a special exception, registers whose class is NO_REGS are
1100 not accepted by `register_operand'. The reason for this change
1101 is to allow the representation of special architecture artifacts
1102 (such as a condition code register) without extending the rtl
1103 definitions. Since registers of class NO_REGS cannot be used
1104 as registers in any case where register classes are examined,
1105 it is most consistent to keep this function from accepting them. */
1108 register_operand (op
, mode
)
1110 enum machine_mode mode
;
1112 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1115 if (GET_CODE (op
) == SUBREG
)
1117 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1118 because it is guaranteed to be reloaded into one.
1119 Just make sure the MEM is valid in itself.
1120 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1121 but currently it does result from (SUBREG (REG)...) where the
1122 reg went on the stack.) */
1123 if (! reload_completed
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
1124 return general_operand (op
, mode
);
1126 #ifdef CLASS_CANNOT_CHANGE_MODE
1127 if (GET_CODE (SUBREG_REG (op
)) == REG
1128 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
1129 && (TEST_HARD_REG_BIT
1130 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
1131 REGNO (SUBREG_REG (op
))))
1132 && CLASS_CANNOT_CHANGE_MODE_P (mode
, GET_MODE (SUBREG_REG (op
)))
1133 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op
))) != MODE_COMPLEX_INT
1134 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op
))) != MODE_COMPLEX_FLOAT
)
1138 op
= SUBREG_REG (op
);
1141 /* If we have an ADDRESSOF, consider it valid since it will be
1142 converted into something that will not be a MEM. */
1143 if (GET_CODE (op
) == ADDRESSOF
)
1146 /* We don't consider registers whose class is NO_REGS
1147 to be a register operand. */
1148 return (GET_CODE (op
) == REG
1149 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1150 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
1153 /* Return 1 for a register in Pmode; ignore the tested mode. */
1156 pmode_register_operand (op
, mode
)
1158 enum machine_mode mode ATTRIBUTE_UNUSED
;
1160 return register_operand (op
, Pmode
);
1163 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1164 or a hard register. */
1167 scratch_operand (op
, mode
)
1169 enum machine_mode mode
;
1171 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1174 return (GET_CODE (op
) == SCRATCH
1175 || (GET_CODE (op
) == REG
1176 && REGNO (op
) < FIRST_PSEUDO_REGISTER
));
1179 /* Return 1 if OP is a valid immediate operand for mode MODE.
1181 The main use of this function is as a predicate in match_operand
1182 expressions in the machine description. */
1185 immediate_operand (op
, mode
)
1187 enum machine_mode mode
;
1189 /* Don't accept CONST_INT or anything similar
1190 if the caller wants something floating. */
1191 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1192 && GET_MODE_CLASS (mode
) != MODE_INT
1193 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1196 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and
1197 result in 0/1. It seems a safe assumption that this is
1198 in range for everyone. */
1199 if (GET_CODE (op
) == CONSTANT_P_RTX
)
1202 return (CONSTANT_P (op
)
1203 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
1204 || GET_MODE (op
) == VOIDmode
)
1205 #ifdef LEGITIMATE_PIC_OPERAND_P
1206 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1208 && LEGITIMATE_CONSTANT_P (op
));
1211 /* Returns 1 if OP is an operand that is a CONST_INT. */
1214 const_int_operand (op
, mode
)
1216 enum machine_mode mode ATTRIBUTE_UNUSED
;
1218 return GET_CODE (op
) == CONST_INT
;
1221 /* Returns 1 if OP is an operand that is a constant integer or constant
1222 floating-point number. */
1225 const_double_operand (op
, mode
)
1227 enum machine_mode mode
;
1229 /* Don't accept CONST_INT or anything similar
1230 if the caller wants something floating. */
1231 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1232 && GET_MODE_CLASS (mode
) != MODE_INT
1233 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1236 return ((GET_CODE (op
) == CONST_DOUBLE
|| GET_CODE (op
) == CONST_INT
)
1237 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
1238 || GET_MODE (op
) == VOIDmode
));
1241 /* Return 1 if OP is a general operand that is not an immediate operand. */
1244 nonimmediate_operand (op
, mode
)
1246 enum machine_mode mode
;
1248 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
1251 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1254 nonmemory_operand (op
, mode
)
1256 enum machine_mode mode
;
1258 if (CONSTANT_P (op
))
1260 /* Don't accept CONST_INT or anything similar
1261 if the caller wants something floating. */
1262 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1263 && GET_MODE_CLASS (mode
) != MODE_INT
1264 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1267 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
1268 || mode
== VOIDmode
)
1269 #ifdef LEGITIMATE_PIC_OPERAND_P
1270 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1272 && LEGITIMATE_CONSTANT_P (op
));
1275 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1278 if (GET_CODE (op
) == SUBREG
)
1280 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1281 because it is guaranteed to be reloaded into one.
1282 Just make sure the MEM is valid in itself.
1283 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1284 but currently it does result from (SUBREG (REG)...) where the
1285 reg went on the stack.) */
1286 if (! reload_completed
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
1287 return general_operand (op
, mode
);
1288 op
= SUBREG_REG (op
);
1291 /* We don't consider registers whose class is NO_REGS
1292 to be a register operand. */
1293 return (GET_CODE (op
) == REG
1294 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1295 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
1298 /* Return 1 if OP is a valid operand that stands for pushing a
1299 value of mode MODE onto the stack.
1301 The main use of this function is as a predicate in match_operand
1302 expressions in the machine description. */
1305 push_operand (op
, mode
)
1307 enum machine_mode mode
;
1309 if (GET_CODE (op
) != MEM
)
1312 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1317 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1320 return XEXP (op
, 0) == stack_pointer_rtx
;
1323 /* Return 1 if OP is a valid operand that stands for popping a
1324 value of mode MODE off the stack.
1326 The main use of this function is as a predicate in match_operand
1327 expressions in the machine description. */
1330 pop_operand (op
, mode
)
1332 enum machine_mode mode
;
1334 if (GET_CODE (op
) != MEM
)
1337 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1342 if (GET_CODE (op
) != STACK_POP_CODE
)
1345 return XEXP (op
, 0) == stack_pointer_rtx
;
1348 /* Return 1 if ADDR is a valid memory address for mode MODE. */
1351 memory_address_p (mode
, addr
)
1352 enum machine_mode mode ATTRIBUTE_UNUSED
;
1355 if (GET_CODE (addr
) == ADDRESSOF
)
1358 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1365 /* Return 1 if OP is a valid memory reference with mode MODE,
1366 including a valid address.
1368 The main use of this function is as a predicate in match_operand
1369 expressions in the machine description. */
1372 memory_operand (op
, mode
)
1374 enum machine_mode mode
;
1378 if (! reload_completed
)
1379 /* Note that no SUBREG is a memory operand before end of reload pass,
1380 because (SUBREG (MEM...)) forces reloading into a register. */
1381 return GET_CODE (op
) == MEM
&& general_operand (op
, mode
);
1383 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1387 if (GET_CODE (inner
) == SUBREG
)
1388 inner
= SUBREG_REG (inner
);
1390 return (GET_CODE (inner
) == MEM
&& general_operand (op
, mode
));
1393 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1394 that is, a memory reference whose address is a general_operand. */
1397 indirect_operand (op
, mode
)
1399 enum machine_mode mode
;
1401 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1402 if (! reload_completed
1403 && GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
1405 register int offset
= SUBREG_WORD (op
) * UNITS_PER_WORD
;
1406 rtx inner
= SUBREG_REG (op
);
1408 if (BYTES_BIG_ENDIAN
)
1409 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (op
)))
1410 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (inner
))));
1412 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1415 /* The only way that we can have a general_operand as the resulting
1416 address is if OFFSET is zero and the address already is an operand
1417 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1420 return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
1421 || (GET_CODE (XEXP (inner
, 0)) == PLUS
1422 && GET_CODE (XEXP (XEXP (inner
, 0), 1)) == CONST_INT
1423 && INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
1424 && general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
1427 return (GET_CODE (op
) == MEM
1428 && memory_operand (op
, mode
)
1429 && general_operand (XEXP (op
, 0), Pmode
));
1432 /* Return 1 if this is a comparison operator. This allows the use of
1433 MATCH_OPERATOR to recognize all the branch insns. */
1436 comparison_operator (op
, mode
)
1438 enum machine_mode mode
;
1440 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1441 && GET_RTX_CLASS (GET_CODE (op
)) == '<');
1444 /* If BODY is an insn body that uses ASM_OPERANDS,
1445 return the number of operands (both input and output) in the insn.
1446 Otherwise return -1. */
1449 asm_noperands (body
)
1452 switch (GET_CODE (body
))
1455 /* No output operands: return number of input operands. */
1456 return ASM_OPERANDS_INPUT_LENGTH (body
);
1458 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
1459 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1460 return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body
)) + 1;
1464 if (GET_CODE (XVECEXP (body
, 0, 0)) == SET
1465 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
1467 /* Multiple output operands, or 1 output plus some clobbers:
1468 body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1472 /* Count backwards through CLOBBERs to determine number of SETs. */
1473 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1475 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1477 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1481 /* N_SETS is now number of output operands. */
1484 /* Verify that all the SETs we have
1485 came from a single original asm_operands insn
1486 (so that invalid combinations are blocked). */
1487 for (i
= 0; i
< n_sets
; i
++)
1489 rtx elt
= XVECEXP (body
, 0, i
);
1490 if (GET_CODE (elt
) != SET
)
1492 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1494 /* If these ASM_OPERANDS rtx's came from different original insns
1495 then they aren't allowed together. */
1496 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1497 != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body
, 0, 0))))
1500 return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body
, 0, 0)))
1503 else if (GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
1505 /* 0 outputs, but some clobbers:
1506 body is [(asm_operands ...) (clobber (reg ...))...]. */
1509 /* Make sure all the other parallel things really are clobbers. */
1510 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1511 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1514 return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body
, 0, 0));
1523 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1524 copy its operands (both input and output) into the vector OPERANDS,
1525 the locations of the operands within the insn into the vector OPERAND_LOCS,
1526 and the constraints for the operands into CONSTRAINTS.
1527 Write the modes of the operands into MODES.
1528 Return the assembler-template.
1530 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1531 we don't store that info. */
1534 decode_asm_operands (body
, operands
, operand_locs
, constraints
, modes
)
1538 const char **constraints
;
1539 enum machine_mode
*modes
;
1543 const char *template = 0;
1545 if (GET_CODE (body
) == SET
&& GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
1547 rtx asmop
= SET_SRC (body
);
1548 /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */
1550 noperands
= ASM_OPERANDS_INPUT_LENGTH (asmop
) + 1;
1552 for (i
= 1; i
< noperands
; i
++)
1555 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
- 1);
1557 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
- 1);
1559 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
- 1);
1561 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
- 1);
1564 /* The output is in the SET.
1565 Its constraint is in the ASM_OPERANDS itself. */
1567 operands
[0] = SET_DEST (body
);
1569 operand_locs
[0] = &SET_DEST (body
);
1571 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1573 modes
[0] = GET_MODE (SET_DEST (body
));
1574 template = ASM_OPERANDS_TEMPLATE (asmop
);
1576 else if (GET_CODE (body
) == ASM_OPERANDS
)
1579 /* No output operands: BODY is (asm_operands ....). */
1581 noperands
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1583 /* The input operands are found in the 1st element vector. */
1584 /* Constraints for inputs are in the 2nd element vector. */
1585 for (i
= 0; i
< noperands
; i
++)
1588 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1590 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1592 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1594 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1596 template = ASM_OPERANDS_TEMPLATE (asmop
);
1598 else if (GET_CODE (body
) == PARALLEL
1599 && GET_CODE (XVECEXP (body
, 0, 0)) == SET
)
1601 rtx asmop
= SET_SRC (XVECEXP (body
, 0, 0));
1602 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1603 int nin
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1604 int nout
= 0; /* Does not include CLOBBERs. */
1606 /* At least one output, plus some CLOBBERs. */
1608 /* The outputs are in the SETs.
1609 Their constraints are in the ASM_OPERANDS itself. */
1610 for (i
= 0; i
< nparallel
; i
++)
1612 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1613 break; /* Past last SET */
1616 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1618 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1620 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1622 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1626 for (i
= 0; i
< nin
; i
++)
1629 operand_locs
[i
+ nout
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1631 operands
[i
+ nout
] = ASM_OPERANDS_INPUT (asmop
, i
);
1633 constraints
[i
+ nout
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1635 modes
[i
+ nout
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1638 template = ASM_OPERANDS_TEMPLATE (asmop
);
1640 else if (GET_CODE (body
) == PARALLEL
1641 && GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
1643 /* No outputs, but some CLOBBERs. */
1645 rtx asmop
= XVECEXP (body
, 0, 0);
1646 int nin
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1648 for (i
= 0; i
< nin
; i
++)
1651 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1653 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1655 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1657 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1660 template = ASM_OPERANDS_TEMPLATE (asmop
);
1666 /* Check if an asm_operand matches it's constraints.
1667 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1670 asm_operand_ok (op
, constraint
)
1672 const char *constraint
;
1676 /* Use constrain_operands after reload. */
1677 if (reload_completed
)
1682 char c
= *constraint
++;
1696 case '0': case '1': case '2': case '3': case '4':
1697 case '5': case '6': case '7': case '8': case '9':
1698 /* For best results, our caller should have given us the
1699 proper matching constraint, but we can't actually fail
1700 the check if they didn't. Indicate that results are
1706 if (address_operand (op
, VOIDmode
))
1711 case 'V': /* non-offsettable */
1712 if (memory_operand (op
, VOIDmode
))
1716 case 'o': /* offsettable */
1717 if (offsettable_nonstrict_memref_p (op
))
1722 /* ??? Before flow, auto inc/dec insns are not supposed to exist,
1723 excepting those that expand_call created. Further, on some
1724 machines which do not have generalized auto inc/dec, an inc/dec
1725 is not a memory_operand.
1727 Match any memory and hope things are resolved after reload. */
1729 if (GET_CODE (op
) == MEM
1731 || GET_CODE (XEXP (op
, 0)) == PRE_DEC
1732 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1737 if (GET_CODE (op
) == MEM
1739 || GET_CODE (XEXP (op
, 0)) == PRE_INC
1740 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1745 #ifndef REAL_ARITHMETIC
1746 /* Match any floating double constant, but only if
1747 we can examine the bits of it reliably. */
1748 if ((HOST_FLOAT_FORMAT
!= TARGET_FLOAT_FORMAT
1749 || HOST_BITS_PER_WIDE_INT
!= BITS_PER_WORD
)
1750 && GET_MODE (op
) != VOIDmode
&& ! flag_pretend_float
)
1756 if (GET_CODE (op
) == CONST_DOUBLE
)
1761 if (GET_CODE (op
) == CONST_DOUBLE
1762 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, 'G'))
1766 if (GET_CODE (op
) == CONST_DOUBLE
1767 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, 'H'))
1772 if (GET_CODE (op
) == CONST_INT
1773 || (GET_CODE (op
) == CONST_DOUBLE
1774 && GET_MODE (op
) == VOIDmode
))
1780 #ifdef LEGITIMATE_PIC_OPERAND_P
1781 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1788 if (GET_CODE (op
) == CONST_INT
1789 || (GET_CODE (op
) == CONST_DOUBLE
1790 && GET_MODE (op
) == VOIDmode
))
1795 if (GET_CODE (op
) == CONST_INT
1796 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I'))
1800 if (GET_CODE (op
) == CONST_INT
1801 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'J'))
1805 if (GET_CODE (op
) == CONST_INT
1806 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K'))
1810 if (GET_CODE (op
) == CONST_INT
1811 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'))
1815 if (GET_CODE (op
) == CONST_INT
1816 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'M'))
1820 if (GET_CODE (op
) == CONST_INT
1821 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'N'))
1825 if (GET_CODE (op
) == CONST_INT
1826 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'))
1830 if (GET_CODE (op
) == CONST_INT
1831 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'P'))
1839 if (general_operand (op
, VOIDmode
))
1844 /* For all other letters, we first check for a register class,
1845 otherwise it is an EXTRA_CONSTRAINT. */
1846 if (REG_CLASS_FROM_LETTER (c
) != NO_REGS
)
1849 if (GET_MODE (op
) == BLKmode
)
1851 if (register_operand (op
, VOIDmode
))
1854 #ifdef EXTRA_CONSTRAINT
1855 if (EXTRA_CONSTRAINT (op
, c
))
1865 /* Given an rtx *P, if it is a sum containing an integer constant term,
1866 return the location (type rtx *) of the pointer to that constant term.
1867 Otherwise, return a null pointer. */
1870 find_constant_term_loc (p
)
1874 register enum rtx_code code
= GET_CODE (*p
);
1876 /* If *P IS such a constant term, P is its location. */
1878 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1882 /* Otherwise, if not a sum, it has no constant term. */
1884 if (GET_CODE (*p
) != PLUS
)
1887 /* If one of the summands is constant, return its location. */
1889 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1890 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1893 /* Otherwise, check each summand for containing a constant term. */
1895 if (XEXP (*p
, 0) != 0)
1897 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1902 if (XEXP (*p
, 1) != 0)
1904 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1912 /* Return 1 if OP is a memory reference
1913 whose address contains no side effects
1914 and remains valid after the addition
1915 of a positive integer less than the
1916 size of the object being referenced.
1918 We assume that the original address is valid and do not check it.
1920 This uses strict_memory_address_p as a subroutine, so
1921 don't use it before reload. */
1924 offsettable_memref_p (op
)
1927 return ((GET_CODE (op
) == MEM
)
1928 && offsettable_address_p (1, GET_MODE (op
), XEXP (op
, 0)));
1931 /* Similar, but don't require a strictly valid mem ref:
1932 consider pseudo-regs valid as index or base regs. */
1935 offsettable_nonstrict_memref_p (op
)
1938 return ((GET_CODE (op
) == MEM
)
1939 && offsettable_address_p (0, GET_MODE (op
), XEXP (op
, 0)));
1942 /* Return 1 if Y is a memory address which contains no side effects
1943 and would remain valid after the addition of a positive integer
1944 less than the size of that mode.
1946 We assume that the original address is valid and do not check it.
1947 We do check that it is valid for narrower modes.
1949 If STRICTP is nonzero, we require a strictly valid address,
1950 for the sake of use in reload.c. */
1953 offsettable_address_p (strictp
, mode
, y
)
1955 enum machine_mode mode
;
1958 register enum rtx_code ycode
= GET_CODE (y
);
1962 int (*addressp
) PARAMS ((enum machine_mode
, rtx
)) =
1963 (strictp
? strict_memory_address_p
: memory_address_p
);
1964 unsigned int mode_sz
= GET_MODE_SIZE (mode
);
1966 if (CONSTANT_ADDRESS_P (y
))
1969 /* Adjusting an offsettable address involves changing to a narrower mode.
1970 Make sure that's OK. */
1972 if (mode_dependent_address_p (y
))
1975 /* ??? How much offset does an offsettable BLKmode reference need?
1976 Clearly that depends on the situation in which it's being used.
1977 However, the current situation in which we test 0xffffffff is
1978 less than ideal. Caveat user. */
1980 mode_sz
= BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
;
1982 /* If the expression contains a constant term,
1983 see if it remains valid when max possible offset is added. */
1985 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
1990 *y2
= plus_constant (*y2
, mode_sz
- 1);
1991 /* Use QImode because an odd displacement may be automatically invalid
1992 for any wider mode. But it should be valid for a single byte. */
1993 good
= (*addressp
) (QImode
, y
);
1995 /* In any case, restore old contents of memory. */
2000 if (GET_RTX_CLASS (ycode
) == 'a')
2003 /* The offset added here is chosen as the maximum offset that
2004 any instruction could need to add when operating on something
2005 of the specified mode. We assume that if Y and Y+c are
2006 valid addresses then so is Y+d for all 0<d<c. */
2008 z
= plus_constant_for_output (y
, mode_sz
- 1);
2010 /* Use QImode because an odd displacement may be automatically invalid
2011 for any wider mode. But it should be valid for a single byte. */
2012 return (*addressp
) (QImode
, z
);
2015 /* Return 1 if ADDR is an address-expression whose effect depends
2016 on the mode of the memory reference it is used in.
2018 Autoincrement addressing is a typical example of mode-dependence
2019 because the amount of the increment depends on the mode. */
2022 mode_dependent_address_p (addr
)
2023 rtx addr ATTRIBUTE_UNUSED
; /* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */
2025 GO_IF_MODE_DEPENDENT_ADDRESS (addr
, win
);
2027 /* Label `win' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
2028 win
: ATTRIBUTE_UNUSED_LABEL
2032 /* Return 1 if OP is a general operand
2033 other than a memory ref with a mode dependent address. */
2036 mode_independent_operand (op
, mode
)
2037 enum machine_mode mode
;
2042 if (! general_operand (op
, mode
))
2045 if (GET_CODE (op
) != MEM
)
2048 addr
= XEXP (op
, 0);
2049 GO_IF_MODE_DEPENDENT_ADDRESS (addr
, lose
);
2051 /* Label `lose' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
2052 lose
: ATTRIBUTE_UNUSED_LABEL
2056 /* Given an operand OP that is a valid memory reference which
2057 satisfies offsettable_memref_p, return a new memory reference whose
2058 address has been adjusted by OFFSET. OFFSET should be positive and
2059 less than the size of the object referenced. */
2062 adj_offsettable_operand (op
, offset
)
2066 register enum rtx_code code
= GET_CODE (op
);
2070 register rtx y
= XEXP (op
, 0);
2073 if (CONSTANT_ADDRESS_P (y
))
2075 new = gen_rtx_MEM (GET_MODE (op
),
2076 plus_constant_for_output (y
, offset
));
2077 MEM_COPY_ATTRIBUTES (new, op
);
2081 if (GET_CODE (y
) == PLUS
)
2084 register rtx
*const_loc
;
2088 const_loc
= find_constant_term_loc (&z
);
2091 *const_loc
= plus_constant_for_output (*const_loc
, offset
);
2096 new = gen_rtx_MEM (GET_MODE (op
), plus_constant_for_output (y
, offset
));
2097 MEM_COPY_ATTRIBUTES (new, op
);
2103 /* Like extract_insn, but save insn extracted and don't extract again, when
2104 called again for the same insn expecting that recog_data still contain the
2105 valid information. This is used primary by gen_attr infrastructure that
2106 often does extract insn again and again. */
2108 extract_insn_cached (insn
)
2111 if (recog_data
.insn
== insn
&& INSN_CODE (insn
) >= 0)
2113 extract_insn (insn
);
2114 recog_data
.insn
= insn
;
2116 /* Do cached extract_insn, constrain_operand and complain about failures.
2117 Used by insn_attrtab. */
2119 extract_constrain_insn_cached (insn
)
2122 extract_insn_cached (insn
);
2123 if (which_alternative
== -1
2124 && !constrain_operands (reload_completed
))
2125 fatal_insn_not_found (insn
);
2127 /* Do cached constrain_operand and complain about failures. */
2129 constrain_operands_cached (strict
)
2132 if (which_alternative
== -1)
2133 return constrain_operands (strict
);
2138 /* Analyze INSN and fill in recog_data. */
2147 rtx body
= PATTERN (insn
);
2149 recog_data
.insn
= NULL
;
2150 recog_data
.n_operands
= 0;
2151 recog_data
.n_alternatives
= 0;
2152 recog_data
.n_dups
= 0;
2153 which_alternative
= -1;
2155 switch (GET_CODE (body
))
2165 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
2170 if ((GET_CODE (XVECEXP (body
, 0, 0)) == SET
2171 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
2172 || GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
2178 recog_data
.n_operands
= noperands
= asm_noperands (body
);
2181 /* This insn is an `asm' with operands. */
2183 /* expand_asm_operands makes sure there aren't too many operands. */
2184 if (noperands
> MAX_RECOG_OPERANDS
)
2187 /* Now get the operand values and constraints out of the insn. */
2188 decode_asm_operands (body
, recog_data
.operand
,
2189 recog_data
.operand_loc
,
2190 recog_data
.constraints
,
2191 recog_data
.operand_mode
);
2194 const char *p
= recog_data
.constraints
[0];
2195 recog_data
.n_alternatives
= 1;
2197 recog_data
.n_alternatives
+= (*p
++ == ',');
2201 fatal_insn_not_found (insn
);
2205 /* Ordinary insn: recognize it, get the operands via insn_extract
2206 and get the constraints. */
2208 icode
= recog_memoized (insn
);
2210 fatal_insn_not_found (insn
);
2212 recog_data
.n_operands
= noperands
= insn_data
[icode
].n_operands
;
2213 recog_data
.n_alternatives
= insn_data
[icode
].n_alternatives
;
2214 recog_data
.n_dups
= insn_data
[icode
].n_dups
;
2216 insn_extract (insn
);
2218 for (i
= 0; i
< noperands
; i
++)
2220 recog_data
.constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2221 recog_data
.operand_mode
[i
] = insn_data
[icode
].operand
[i
].mode
;
2222 /* VOIDmode match_operands gets mode from their real operand. */
2223 if (recog_data
.operand_mode
[i
] == VOIDmode
)
2224 recog_data
.operand_mode
[i
] = GET_MODE (recog_data
.operand
[i
]);
2227 for (i
= 0; i
< noperands
; i
++)
2228 recog_data
.operand_type
[i
]
2229 = (recog_data
.constraints
[i
][0] == '=' ? OP_OUT
2230 : recog_data
.constraints
[i
][0] == '+' ? OP_INOUT
2233 if (recog_data
.n_alternatives
> MAX_RECOG_ALTERNATIVES
)
2237 /* After calling extract_insn, you can use this function to extract some
2238 information from the constraint strings into a more usable form.
2239 The collected data is stored in recog_op_alt. */
2241 preprocess_constraints ()
2245 memset (recog_op_alt
, 0, sizeof recog_op_alt
);
2246 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2249 struct operand_alternative
*op_alt
;
2250 const char *p
= recog_data
.constraints
[i
];
2252 op_alt
= recog_op_alt
[i
];
2254 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
2256 op_alt
[j
].class = NO_REGS
;
2257 op_alt
[j
].constraint
= p
;
2258 op_alt
[j
].matches
= -1;
2259 op_alt
[j
].matched
= -1;
2261 if (*p
== '\0' || *p
== ',')
2263 op_alt
[j
].anything_ok
= 1;
2273 while (c
!= ',' && c
!= '\0');
2274 if (c
== ',' || c
== '\0')
2279 case '=': case '+': case '*': case '%':
2280 case 'E': case 'F': case 'G': case 'H':
2281 case 's': case 'i': case 'n':
2282 case 'I': case 'J': case 'K': case 'L':
2283 case 'M': case 'N': case 'O': case 'P':
2284 /* These don't say anything we care about. */
2288 op_alt
[j
].reject
+= 6;
2291 op_alt
[j
].reject
+= 600;
2294 op_alt
[j
].earlyclobber
= 1;
2297 case '0': case '1': case '2': case '3': case '4':
2298 case '5': case '6': case '7': case '8': case '9':
2299 op_alt
[j
].matches
= c
- '0';
2300 recog_op_alt
[op_alt
[j
].matches
][j
].matched
= i
;
2304 op_alt
[j
].memory_ok
= 1;
2307 op_alt
[j
].decmem_ok
= 1;
2310 op_alt
[j
].incmem_ok
= 1;
2313 op_alt
[j
].nonoffmem_ok
= 1;
2316 op_alt
[j
].offmem_ok
= 1;
2319 op_alt
[j
].anything_ok
= 1;
2323 op_alt
[j
].is_address
= 1;
2324 op_alt
[j
].class = reg_class_subunion
[(int) op_alt
[j
].class][(int) BASE_REG_CLASS
];
2328 op_alt
[j
].class = reg_class_subunion
[(int) op_alt
[j
].class][(int) GENERAL_REGS
];
2332 op_alt
[j
].class = reg_class_subunion
[(int) op_alt
[j
].class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c
)];
2340 /* Check the operands of an insn against the insn's operand constraints
2341 and return 1 if they are valid.
2342 The information about the insn's operands, constraints, operand modes
2343 etc. is obtained from the global variables set up by extract_insn.
2345 WHICH_ALTERNATIVE is set to a number which indicates which
2346 alternative of constraints was matched: 0 for the first alternative,
2347 1 for the next, etc.
2349 In addition, when two operands are match
2350 and it happens that the output operand is (reg) while the
2351 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2352 make the output operand look like the input.
2353 This is because the output operand is the one the template will print.
2355 This is used in final, just before printing the assembler code and by
2356 the routines that determine an insn's attribute.
2358 If STRICT is a positive non-zero value, it means that we have been
2359 called after reload has been completed. In that case, we must
2360 do all checks strictly. If it is zero, it means that we have been called
2361 before reload has completed. In that case, we first try to see if we can
2362 find an alternative that matches strictly. If not, we try again, this
2363 time assuming that reload will fix up the insn. This provides a "best
2364 guess" for the alternative and is used to compute attributes of insns prior
2365 to reload. A negative value of STRICT is used for this internal call. */
2373 constrain_operands (strict
)
2376 const char *constraints
[MAX_RECOG_OPERANDS
];
2377 int matching_operands
[MAX_RECOG_OPERANDS
];
2378 int earlyclobber
[MAX_RECOG_OPERANDS
];
2381 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
2382 int funny_match_index
;
2384 which_alternative
= 0;
2385 if (recog_data
.n_operands
== 0 || recog_data
.n_alternatives
== 0)
2388 for (c
= 0; c
< recog_data
.n_operands
; c
++)
2390 constraints
[c
] = recog_data
.constraints
[c
];
2391 matching_operands
[c
] = -1;
2398 funny_match_index
= 0;
2400 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2402 register rtx op
= recog_data
.operand
[opno
];
2403 enum machine_mode mode
= GET_MODE (op
);
2404 register const char *p
= constraints
[opno
];
2409 earlyclobber
[opno
] = 0;
2411 /* A unary operator may be accepted by the predicate, but it
2412 is irrelevant for matching constraints. */
2413 if (GET_RTX_CLASS (GET_CODE (op
)) == '1')
2416 if (GET_CODE (op
) == SUBREG
)
2418 if (GET_CODE (SUBREG_REG (op
)) == REG
2419 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
2420 offset
= SUBREG_WORD (op
);
2421 op
= SUBREG_REG (op
);
2424 /* An empty constraint or empty alternative
2425 allows anything which matched the pattern. */
2426 if (*p
== 0 || *p
== ',')
2429 while (*p
&& (c
= *p
++) != ',')
2432 case '?': case '!': case '*': case '%':
2437 /* Ignore rest of this alternative as far as
2438 constraint checking is concerned. */
2439 while (*p
&& *p
!= ',')
2444 earlyclobber
[opno
] = 1;
2447 case '0': case '1': case '2': case '3': case '4':
2448 case '5': case '6': case '7': case '8': case '9':
2450 /* This operand must be the same as a previous one.
2451 This kind of constraint is used for instructions such
2452 as add when they take only two operands.
2454 Note that the lower-numbered operand is passed first.
2456 If we are not testing strictly, assume that this constraint
2457 will be satisfied. */
2462 rtx op1
= recog_data
.operand
[c
- '0'];
2463 rtx op2
= recog_data
.operand
[opno
];
2465 /* A unary operator may be accepted by the predicate,
2466 but it is irrelevant for matching constraints. */
2467 if (GET_RTX_CLASS (GET_CODE (op1
)) == '1')
2468 op1
= XEXP (op1
, 0);
2469 if (GET_RTX_CLASS (GET_CODE (op2
)) == '1')
2470 op2
= XEXP (op2
, 0);
2472 val
= operands_match_p (op1
, op2
);
2475 matching_operands
[opno
] = c
- '0';
2476 matching_operands
[c
- '0'] = opno
;
2480 /* If output is *x and input is *--x,
2481 arrange later to change the output to *--x as well,
2482 since the output op is the one that will be printed. */
2483 if (val
== 2 && strict
> 0)
2485 funny_match
[funny_match_index
].this = opno
;
2486 funny_match
[funny_match_index
++].other
= c
- '0';
2491 /* p is used for address_operands. When we are called by
2492 gen_reload, no one will have checked that the address is
2493 strictly valid, i.e., that all pseudos requiring hard regs
2494 have gotten them. */
2496 || (strict_memory_address_p (recog_data
.operand_mode
[opno
],
2501 /* No need to check general_operand again;
2502 it was done in insn-recog.c. */
2504 /* Anything goes unless it is a REG and really has a hard reg
2505 but the hard reg is not in the class GENERAL_REGS. */
2507 || GENERAL_REGS
== ALL_REGS
2508 || GET_CODE (op
) != REG
2509 || (reload_in_progress
2510 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2511 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
2516 /* This is used for a MATCH_SCRATCH in the cases when
2517 we don't actually need anything. So anything goes
2523 if (GET_CODE (op
) == MEM
2524 /* Before reload, accept what reload can turn into mem. */
2525 || (strict
< 0 && CONSTANT_P (op
))
2526 /* During reload, accept a pseudo */
2527 || (reload_in_progress
&& GET_CODE (op
) == REG
2528 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2533 if (GET_CODE (op
) == MEM
2534 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
2535 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
2540 if (GET_CODE (op
) == MEM
2541 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
2542 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
2547 #ifndef REAL_ARITHMETIC
2548 /* Match any CONST_DOUBLE, but only if
2549 we can examine the bits of it reliably. */
2550 if ((HOST_FLOAT_FORMAT
!= TARGET_FLOAT_FORMAT
2551 || HOST_BITS_PER_WIDE_INT
!= BITS_PER_WORD
)
2552 && GET_MODE (op
) != VOIDmode
&& ! flag_pretend_float
)
2555 if (GET_CODE (op
) == CONST_DOUBLE
)
2560 if (GET_CODE (op
) == CONST_DOUBLE
)
2566 if (GET_CODE (op
) == CONST_DOUBLE
2567 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, c
))
2572 if (GET_CODE (op
) == CONST_INT
2573 || (GET_CODE (op
) == CONST_DOUBLE
2574 && GET_MODE (op
) == VOIDmode
))
2577 if (CONSTANT_P (op
))
2582 if (GET_CODE (op
) == CONST_INT
2583 || (GET_CODE (op
) == CONST_DOUBLE
2584 && GET_MODE (op
) == VOIDmode
))
2596 if (GET_CODE (op
) == CONST_INT
2597 && CONST_OK_FOR_LETTER_P (INTVAL (op
), c
))
2602 if (GET_CODE (op
) == MEM
2603 && ((strict
> 0 && ! offsettable_memref_p (op
))
2605 && !(CONSTANT_P (op
) || GET_CODE (op
) == MEM
))
2606 || (reload_in_progress
2607 && !(GET_CODE (op
) == REG
2608 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))))
2613 if ((strict
> 0 && offsettable_memref_p (op
))
2614 || (strict
== 0 && offsettable_nonstrict_memref_p (op
))
2615 /* Before reload, accept what reload can handle. */
2617 && (CONSTANT_P (op
) || GET_CODE (op
) == MEM
))
2618 /* During reload, accept a pseudo */
2619 || (reload_in_progress
&& GET_CODE (op
) == REG
2620 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2626 enum reg_class
class;
2628 class = (c
== 'r' ? GENERAL_REGS
: REG_CLASS_FROM_LETTER (c
));
2629 if (class != NO_REGS
)
2633 && GET_CODE (op
) == REG
2634 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2635 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
2636 || (GET_CODE (op
) == REG
2637 && reg_fits_class_p (op
, class, offset
, mode
)))
2640 #ifdef EXTRA_CONSTRAINT
2641 else if (EXTRA_CONSTRAINT (op
, c
))
2648 constraints
[opno
] = p
;
2649 /* If this operand did not win somehow,
2650 this alternative loses. */
2654 /* This alternative won; the operands are ok.
2655 Change whichever operands this alternative says to change. */
2660 /* See if any earlyclobber operand conflicts with some other
2664 for (eopno
= 0; eopno
< recog_data
.n_operands
; eopno
++)
2665 /* Ignore earlyclobber operands now in memory,
2666 because we would often report failure when we have
2667 two memory operands, one of which was formerly a REG. */
2668 if (earlyclobber
[eopno
]
2669 && GET_CODE (recog_data
.operand
[eopno
]) == REG
)
2670 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2671 if ((GET_CODE (recog_data
.operand
[opno
]) == MEM
2672 || recog_data
.operand_type
[opno
] != OP_OUT
)
2674 /* Ignore things like match_operator operands. */
2675 && *recog_data
.constraints
[opno
] != 0
2676 && ! (matching_operands
[opno
] == eopno
2677 && operands_match_p (recog_data
.operand
[opno
],
2678 recog_data
.operand
[eopno
]))
2679 && ! safe_from_earlyclobber (recog_data
.operand
[opno
],
2680 recog_data
.operand
[eopno
]))
2685 while (--funny_match_index
>= 0)
2687 recog_data
.operand
[funny_match
[funny_match_index
].other
]
2688 = recog_data
.operand
[funny_match
[funny_match_index
].this];
2695 which_alternative
++;
2697 while (which_alternative
< recog_data
.n_alternatives
);
2699 which_alternative
= -1;
2700 /* If we are about to reject this, but we are not to test strictly,
2701 try a very loose test. Only return failure if it fails also. */
2703 return constrain_operands (-1);
2708 /* Return 1 iff OPERAND (assumed to be a REG rtx)
2709 is a hard reg in class CLASS when its regno is offset by OFFSET
2710 and changed to mode MODE.
2711 If REG occupies multiple hard regs, all of them must be in CLASS. */
2714 reg_fits_class_p (operand
, class, offset
, mode
)
2716 register enum reg_class
class;
2718 enum machine_mode mode
;
2720 register int regno
= REGNO (operand
);
2721 if (regno
< FIRST_PSEUDO_REGISTER
2722 && TEST_HARD_REG_BIT (reg_class_contents
[(int) class],
2727 for (sr
= HARD_REGNO_NREGS (regno
, mode
) - 1;
2729 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) class],
2738 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2741 split_all_insns (upd_life
)
2748 blocks
= sbitmap_alloc (n_basic_blocks
);
2749 sbitmap_zero (blocks
);
2752 for (i
= n_basic_blocks
- 1; i
>= 0; --i
)
2754 basic_block bb
= BASIC_BLOCK (i
);
2757 for (insn
= bb
->head
; insn
; insn
= next
)
2761 /* Can't use `next_real_insn' because that might go across
2762 CODE_LABELS and short-out basic blocks. */
2763 next
= NEXT_INSN (insn
);
2764 if (! INSN_P (insn
))
2767 /* Don't split no-op move insns. These should silently
2768 disappear later in final. Splitting such insns would
2769 break the code that handles REG_NO_CONFLICT blocks. */
2771 else if ((set
= single_set (insn
)) != NULL
2772 && rtx_equal_p (SET_SRC (set
), SET_DEST (set
)))
2774 /* Nops get in the way while scheduling, so delete them
2775 now if register allocation has already been done. It
2776 is too risky to try to do this before register
2777 allocation, and there are unlikely to be very many
2778 nops then anyways. */
2779 if (reload_completed
)
2781 PUT_CODE (insn
, NOTE
);
2782 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
2783 NOTE_SOURCE_FILE (insn
) = 0;
2788 /* Split insns here to get max fine-grain parallelism. */
2789 rtx first
= PREV_INSN (insn
);
2790 rtx last
= try_split (PATTERN (insn
), insn
, 1);
2794 SET_BIT (blocks
, i
);
2797 /* try_split returns the NOTE that INSN became. */
2798 PUT_CODE (insn
, NOTE
);
2799 NOTE_SOURCE_FILE (insn
) = 0;
2800 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
2802 /* ??? Coddle to md files that generate subregs in post-
2803 reload splitters instead of computing the proper
2805 if (reload_completed
&& first
!= last
)
2807 first
= NEXT_INSN (first
);
2811 cleanup_subreg_operands (first
);
2814 first
= NEXT_INSN (first
);
2818 if (insn
== bb
->end
)
2826 if (insn
== bb
->end
)
2830 /* ??? When we're called from just after reload, the CFG is in bad
2831 shape, and we may have fallen off the end. This could be fixed
2832 by having reload not try to delete unreachable code. Otherwise
2833 assert we found the end insn. */
2834 if (insn
== NULL
&& upd_life
)
2838 if (changed
&& upd_life
)
2840 compute_bb_for_insn (get_max_uid ());
2841 count_or_remove_death_notes (blocks
, 1);
2842 update_life_info (blocks
, UPDATE_LIFE_LOCAL
, PROP_DEATH_NOTES
);
2845 sbitmap_free (blocks
);
2848 #ifdef HAVE_peephole2
2849 struct peep2_insn_data
2855 static struct peep2_insn_data peep2_insn_data
[MAX_INSNS_PER_PEEP2
+ 1];
2856 static int peep2_current
;
2858 /* A non-insn marker indicating the last insn of the block.
2859 The live_before regset for this element is correct, indicating
2860 global_live_at_end for the block. */
2861 #define PEEP2_EOB pc_rtx
2863 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
2864 does not exist. Used by the recognizer to find the next insn to match
2865 in a multi-insn pattern. */
2871 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
2875 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
2876 n
-= MAX_INSNS_PER_PEEP2
+ 1;
2878 if (peep2_insn_data
[n
].insn
== PEEP2_EOB
)
2880 return peep2_insn_data
[n
].insn
;
2883 /* Return true if REGNO is dead before the Nth non-note insn
2887 peep2_regno_dead_p (ofs
, regno
)
2891 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2894 ofs
+= peep2_current
;
2895 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2896 ofs
-= MAX_INSNS_PER_PEEP2
+ 1;
2898 if (peep2_insn_data
[ofs
].insn
== NULL_RTX
)
2901 return ! REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
);
2904 /* Similarly for a REG. */
2907 peep2_reg_dead_p (ofs
, reg
)
2913 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2916 ofs
+= peep2_current
;
2917 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2918 ofs
-= MAX_INSNS_PER_PEEP2
+ 1;
2920 if (peep2_insn_data
[ofs
].insn
== NULL_RTX
)
2923 regno
= REGNO (reg
);
2924 n
= HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
2926 if (REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
+ n
))
2931 /* Try to find a hard register of mode MODE, matching the register class in
2932 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
2933 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
2934 in which case the only condition is that the register must be available
2935 before CURRENT_INSN.
2936 Registers that already have bits set in REG_SET will not be considered.
2938 If an appropriate register is available, it will be returned and the
2939 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
2943 peep2_find_free_register (from
, to
, class_str
, mode
, reg_set
)
2945 const char *class_str
;
2946 enum machine_mode mode
;
2947 HARD_REG_SET
*reg_set
;
2949 static int search_ofs
;
2950 enum reg_class
class;
2954 if (from
>= MAX_INSNS_PER_PEEP2
+ 1 || to
>= MAX_INSNS_PER_PEEP2
+ 1)
2957 from
+= peep2_current
;
2958 if (from
>= MAX_INSNS_PER_PEEP2
+ 1)
2959 from
-= MAX_INSNS_PER_PEEP2
+ 1;
2960 to
+= peep2_current
;
2961 if (to
>= MAX_INSNS_PER_PEEP2
+ 1)
2962 to
-= MAX_INSNS_PER_PEEP2
+ 1;
2964 if (peep2_insn_data
[from
].insn
== NULL_RTX
)
2966 REG_SET_TO_HARD_REG_SET (live
, peep2_insn_data
[from
].live_before
);
2970 HARD_REG_SET this_live
;
2972 if (++from
>= MAX_INSNS_PER_PEEP2
+ 1)
2974 if (peep2_insn_data
[from
].insn
== NULL_RTX
)
2976 REG_SET_TO_HARD_REG_SET (this_live
, peep2_insn_data
[from
].live_before
);
2977 IOR_HARD_REG_SET (live
, this_live
);
2980 class = (class_str
[0] == 'r' ? GENERAL_REGS
2981 : REG_CLASS_FROM_LETTER (class_str
[0]));
2983 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2985 int raw_regno
, regno
, success
, j
;
2987 /* Distribute the free registers as much as possible. */
2988 raw_regno
= search_ofs
+ i
;
2989 if (raw_regno
>= FIRST_PSEUDO_REGISTER
)
2990 raw_regno
-= FIRST_PSEUDO_REGISTER
;
2991 #ifdef REG_ALLOC_ORDER
2992 regno
= reg_alloc_order
[raw_regno
];
2997 /* Don't allocate fixed registers. */
2998 if (fixed_regs
[regno
])
3000 /* Make sure the register is of the right class. */
3001 if (! TEST_HARD_REG_BIT (reg_class_contents
[class], regno
))
3003 /* And can support the mode we need. */
3004 if (! HARD_REGNO_MODE_OK (regno
, mode
))
3006 /* And that we don't create an extra save/restore. */
3007 if (! call_used_regs
[regno
] && ! regs_ever_live
[regno
])
3009 /* And we don't clobber traceback for noreturn functions. */
3010 if ((regno
== FRAME_POINTER_REGNUM
|| regno
== HARD_FRAME_POINTER_REGNUM
)
3011 && (! reload_completed
|| frame_pointer_needed
))
3015 for (j
= HARD_REGNO_NREGS (regno
, mode
) - 1; j
>= 0; j
--)
3017 if (TEST_HARD_REG_BIT (*reg_set
, regno
+ j
)
3018 || TEST_HARD_REG_BIT (live
, regno
+ j
))
3026 for (j
= HARD_REGNO_NREGS (regno
, mode
) - 1; j
>= 0; j
--)
3027 SET_HARD_REG_BIT (*reg_set
, regno
+ j
);
3029 /* Start the next search with the next register. */
3030 if (++raw_regno
>= FIRST_PSEUDO_REGISTER
)
3032 search_ofs
= raw_regno
;
3034 return gen_rtx_REG (mode
, regno
);
3042 /* Perform the peephole2 optimization pass. */
3045 peephole2_optimize (dump_file
)
3046 FILE *dump_file ATTRIBUTE_UNUSED
;
3048 regset_head rs_heads
[MAX_INSNS_PER_PEEP2
+ 2];
3052 #ifdef HAVE_conditional_execution
3057 /* Initialize the regsets we're going to use. */
3058 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3059 peep2_insn_data
[i
].live_before
= INITIALIZE_REG_SET (rs_heads
[i
]);
3060 live
= INITIALIZE_REG_SET (rs_heads
[i
]);
3062 #ifdef HAVE_conditional_execution
3063 blocks
= sbitmap_alloc (n_basic_blocks
);
3064 sbitmap_zero (blocks
);
3067 count_or_remove_death_notes (NULL
, 1);
3070 for (b
= n_basic_blocks
- 1; b
>= 0; --b
)
3072 basic_block bb
= BASIC_BLOCK (b
);
3073 struct propagate_block_info
*pbi
;
3075 /* Indicate that all slots except the last holds invalid data. */
3076 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
; ++i
)
3077 peep2_insn_data
[i
].insn
= NULL_RTX
;
3079 /* Indicate that the last slot contains live_after data. */
3080 peep2_insn_data
[MAX_INSNS_PER_PEEP2
].insn
= PEEP2_EOB
;
3081 peep2_current
= MAX_INSNS_PER_PEEP2
;
3083 /* Start up propagation. */
3084 COPY_REG_SET (live
, bb
->global_live_at_end
);
3085 COPY_REG_SET (peep2_insn_data
[MAX_INSNS_PER_PEEP2
].live_before
, live
);
3087 #ifdef HAVE_conditional_execution
3088 pbi
= init_propagate_block_info (bb
, live
, NULL
, NULL
, 0);
3090 pbi
= init_propagate_block_info (bb
, live
, NULL
, NULL
, PROP_DEATH_NOTES
);
3093 for (insn
= bb
->end
; ; insn
= prev
)
3095 prev
= PREV_INSN (insn
);
3101 /* Record this insn. */
3102 if (--peep2_current
< 0)
3103 peep2_current
= MAX_INSNS_PER_PEEP2
;
3104 peep2_insn_data
[peep2_current
].insn
= insn
;
3105 propagate_one_insn (pbi
, insn
);
3106 COPY_REG_SET (peep2_insn_data
[peep2_current
].live_before
, live
);
3108 /* Match the peephole. */
3109 try = peephole2_insns (PATTERN (insn
), insn
, &match_len
);
3112 i
= match_len
+ peep2_current
;
3113 if (i
>= MAX_INSNS_PER_PEEP2
+ 1)
3114 i
-= MAX_INSNS_PER_PEEP2
+ 1;
3116 /* Replace the old sequence with the new. */
3117 flow_delete_insn_chain (insn
, peep2_insn_data
[i
].insn
);
3118 try = emit_insn_after (try, prev
);
3120 /* Adjust the basic block boundaries. */
3121 if (peep2_insn_data
[i
].insn
== bb
->end
)
3123 if (insn
== bb
->head
)
3124 bb
->head
= NEXT_INSN (prev
);
3126 #ifdef HAVE_conditional_execution
3127 /* With conditional execution, we cannot back up the
3128 live information so easily, since the conditional
3129 death data structures are not so self-contained.
3130 So record that we've made a modification to this
3131 block and update life information at the end. */
3132 SET_BIT (blocks
, b
);
3135 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3136 peep2_insn_data
[i
].insn
= NULL_RTX
;
3137 peep2_insn_data
[peep2_current
].insn
= PEEP2_EOB
;
3139 /* Back up lifetime information past the end of the
3140 newly created sequence. */
3141 if (++i
>= MAX_INSNS_PER_PEEP2
+ 1)
3143 COPY_REG_SET (live
, peep2_insn_data
[i
].live_before
);
3145 /* Update life information for the new sequence. */
3151 i
= MAX_INSNS_PER_PEEP2
;
3152 peep2_insn_data
[i
].insn
= try;
3153 propagate_one_insn (pbi
, try);
3154 COPY_REG_SET (peep2_insn_data
[i
].live_before
, live
);
3156 try = PREV_INSN (try);
3158 while (try != prev
);
3160 /* ??? Should verify that LIVE now matches what we
3161 had before the new sequence. */
3168 if (insn
== bb
->head
)
3172 free_propagate_block_info (pbi
);
3175 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3176 FREE_REG_SET (peep2_insn_data
[i
].live_before
);
3177 FREE_REG_SET (live
);
3179 #ifdef HAVE_conditional_execution
3180 count_or_remove_death_notes (blocks
, 1);
3181 update_life_info (blocks
, UPDATE_LIFE_LOCAL
, PROP_DEATH_NOTES
);
3182 sbitmap_free (blocks
);
3185 #endif /* HAVE_peephole2 */