| blob | 60d7e2e16ea89db235adb2783f2e2aa6c1b1f7e2 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
56 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
57 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
59 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
60 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
61 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
64 /* Vector mapping INSN_UIDs to luids.
65 The luids are like uids but increase monotonically always.
66 We use them to see whether a jump comes from outside a given loop. */
70 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
71 number the insn is contained in. */
75 /* 1 + largest uid of any insn. */
79 /* 1 + luid of last insn. */
83 /* Number of loops detected in current function. Used as index to the
84 next few tables. */
88 /* Bound on pseudo register number before loop optimization.
89 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
92 /* The value to pass to the next call of reg_scan_update. */
95 #define obstack_chunk_alloc xmalloc
96 #define obstack_chunk_free free
97 \f
98 /* During the analysis of a loop, a chain of `struct movable's
99 is made to record all the movable insns found.
100 Then the entire chain can be scanned to decide which to move. */
102 struct movable
103 {
108 of any registers used within the LIBCALL. */
110 that must be moved with this one. */
113 may be adjusted when matching movables
114 that load the same value are found. */
116 including other movables that force this
117 or match this one. */
121 /* If PARTIAL is 1, GLOBAL means something different:
122 that the reg is live outside the range from where it is set
123 to the following label. */
127 In particular, moving it does not make it
128 invariant. */
130 load SRC, rather than copying INSN. */
132 first insn of a consecutive sets group. */
135 that we should avoid changing when clearing
136 the rest of the reg. */
140 };
145 /* Forward declarations. */
159 #if 0
161 #endif
191 rtx *));
272 {
273 rtx r1;
274 rtx r2;
278 {
279 rtx match;
280 rtx replacement;
281 rtx insn;
284 /* Nonzero iff INSN is between START and END, inclusive. */
285 #define INSN_IN_RANGE_P(INSN, START, END) \
286 (INSN_UID (INSN) < max_uid_for_loop \
287 && INSN_LUID (INSN) >= INSN_LUID (START) \
288 && INSN_LUID (INSN) <= INSN_LUID (END))
290 /* Indirect_jump_in_function is computed once per function. */
298 rtx));
299 \f
300 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
301 copy the value of the strength reduced giv to its original register. */
304 /* Cost of using a register, to normalize the benefits of a giv. */
307 void
309 {
315 }
316 \f
317 /* Compute the mapping from uids to luids.
318 LUIDs are numbers assigned to insns, like uids,
319 except that luids increase monotonically through the code.
320 Start at insn START and stop just before END. Assign LUIDs
321 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
322 static int
326 {
328 rtx insn;
331 {
334 /* Don't assign luids to line-number NOTEs, so that the distance in
335 luids between two insns is not affected by -g. */
339 else
340 /* Give a line number note the same luid as preceding insn. */
342 }
344 }
345 \f
346 /* Entry point of this file. Perform loop optimization
347 on the current function. F is the first insn of the function
348 and DUMPFILE is a stream for output of a trace of actions taken
349 (or 0 if none should be output). */
351 void
353 /* f is the first instruction of a chain of insns for one function */
354 rtx f;
357 {
373 /* Count the number of loops. */
377 {
380 max_loop_num++;
381 }
383 /* Don't waste time if no loops. */
389 /* Get size to use for tables indexed by uids.
390 Leave some space for labels allocated by find_and_verify_loops. */
397 /* Allocate storage for array of loops. */
401 /* Find and process each loop.
402 First, find them, and record them in order of their beginnings. */
405 /* Allocate and initialize auxiliary loop information. */
410 /* Now find all register lifetimes. This must be done after
411 find_and_verify_loops, because it might reorder the insns in the
412 function. */
415 /* This must occur after reg_scan so that registers created by gcse
416 will have entries in the register tables.
418 We could have added a call to reg_scan after gcse_main in toplev.c,
419 but moving this call to init_alias_analysis is more efficient. */
422 /* See if we went too far. Note that get_max_uid already returns
423 one more that the maximum uid of all insn. */
426 /* Now reset it to the actual size we need. See above. */
429 /* find_and_verify_loops has already called compute_luids, but it
430 might have rearranged code afterwards, so we need to recompute
431 the luids now. */
434 /* Don't leave gaps in uid_luid for insns that have been
435 deleted. It is possible that the first or last insn
436 using some register has been deleted by cross-jumping.
437 Make sure that uid_luid for that former insn's uid
438 points to the general area where that insn used to be. */
440 {
444 }
449 /* Determine if the function has indirect jump. On some systems
450 this prevents low overhead loop instructions from being used. */
453 /* Now scan the loops, last ones first, since this means inner ones are done
454 before outer ones. */
456 {
461 }
463 /* If there were lexical blocks inside the loop, they have been
464 replicated. We will now have more than one NOTE_INSN_BLOCK_BEG
465 and NOTE_INSN_BLOCK_END for each such block. We must duplicate
466 the BLOCKs as well. */
472 /* Clean up. */
477 }
478 \f
479 /* Returns the next insn, in execution order, after INSN. START and
480 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
481 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
482 insn-stream; it is used with loops that are entered near the
483 bottom. */
485 static rtx
488 rtx insn;
489 {
493 {
495 /* Go to the top of the loop, and continue there. */
497 else
498 /* We're done. */
500 }
503 /* We're done. */
507 }
509 /* Optimize one loop described by LOOP. */
511 /* ??? Could also move memory writes out of loops if the destination address
512 is invariant, the source is invariant, the memory write is not volatile,
513 and if we can prove that no read inside the loop can read this address
514 before the write occurs. If there is a read of this address after the
515 write, then we can also mark the memory read as invariant. */
517 static void
521 {
527 rtx p;
528 /* 1 if we are scanning insns that could be executed zero times. */
530 /* 1 if we are scanning insns that might never be executed
531 due to a subroutine call which might exit before they are reached. */
533 /* Jump insn that enters the loop, or 0 if control drops in. */
535 /* Number of insns in the loop. */
539 /* The SET from an insn, if it is the only SET in the insn. */
541 /* Chain describing insns movable in current loop. */
543 /* Ratio of extra register life span we can justify
544 for saving an instruction. More if loop doesn't call subroutines
545 since in that case saving an insn makes more difference
546 and more registers are available. */
548 /* Nonzero if we are scanning instructions in a sub-loop. */
556 /* Determine whether this loop starts with a jump down to a test at
557 the end. This will occur for a small number of loops with a test
558 that is too complex to duplicate in front of the loop.
560 We search for the first insn or label in the loop, skipping NOTEs.
561 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
562 (because we might have a loop executed only once that contains a
563 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
564 (in case we have a degenerate loop).
566 Note that if we mistakenly think that a loop is entered at the top
567 when, in fact, it is entered at the exit test, the only effect will be
568 slightly poorer optimization. Making the opposite error can generate
569 incorrect code. Since very few loops now start with a jump to the
570 exit test, the code here to detect that case is very conservative. */
573 p != loop_end
579 ;
583 /* If loop end is the end of the current function, then emit a
584 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
585 note insn. This is the position we use when sinking insns out of
586 the loop. */
589 else
592 /* Set up variables describing this loop. */
596 /* If loop has a jump before the first label,
597 the true entry is the target of that jump.
598 Start scan from there.
599 But record in LOOP->TOP the place where the end-test jumps
600 back to so we can scan that after the end of the loop. */
602 {
605 /* Loop entry must be unconditional jump (and not a RETURN) */
608 /* Check to see whether the jump actually
609 jumps out of the loop (meaning it's no loop).
610 This case can happen for things like
611 do {..} while (0). If this label was generated previously
612 by loop, we can't tell anything about it and have to reject
613 the loop. */
615 {
618 }
619 }
621 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
622 as required by loop_reg_used_before_p. So skip such loops. (This
623 test may never be true, but it's best to play it safe.)
625 Also, skip loops where we do not start scanning at a label. This
626 test also rejects loops starting with a JUMP_INSN that failed the
627 test above. */
631 {
636 }
638 /* Allocate extra space for REGs that might be created by load_mems.
639 We allocate a little extra slop as well, in the hopes that we
640 won't have to reallocate the regs array. */
645 {
651 }
653 /* Scan through the loop finding insns that are safe to move.
654 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
655 this reg will be considered invariant for subsequent insns.
656 We consider whether subsequent insns use the reg
657 in deciding whether it is worth actually moving.
659 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
660 and therefore it is possible that the insns we are scanning
661 would never be executed. At such times, we must make sure
662 that it is safe to execute the insn once instead of zero times.
663 When MAYBE_NEVER is 0, all insns will be executed at least once
664 so that is not a problem. */
669 {
674 {
681 /* Figure out what to use as a source of this insn. If a REG_EQUIV
682 note is given or if a REG_EQUAL note with a constant operand is
683 specified, use it as the source and mark that we should move
684 this insn by calling emit_move_insn rather that duplicating the
685 insn.
687 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
688 is present. */
692 else
693 {
698 {
700 /* A libcall block can use regs that don't appear in
701 the equivalent expression. To move the libcall,
702 we must move those regs too. */
704 }
705 }
707 /* Don't try to optimize a register that was made
708 by loop-optimization for an inner loop.
709 We don't know its life-span, so we can't compute the benefit. */
711 ;
713 than the one where it is set (meaning that
714 something after this point in the loop might
715 depend on its value before the set). */
717 /* And the set is not guaranteed to be executed one
718 the loop starts, or the value before the set is
719 needed before the set occurs...
721 ??? Note we have quadratic behaviour here, mitigated
722 by the fact that the previous test will often fail for
723 large loops. Rather than re-scanning the entire loop
724 each time for register usage, we should build tables
725 of the register usage and use them here instead. */
726 && (maybe_never
728 /* It is unsafe to move the set.
730 This code used to consider it OK to move a set of a variable
731 which was not created by the user and not used in an exit test.
732 That behavior is incorrect and was removed. */
733 ;
738 || (tem1
739 = consec_sets_invariant_p
742 p)))
743 /* If the insn can cause a trap (such as divide by zero),
744 can't move it unless it's guaranteed to be executed
745 once loop is entered. Even a function call might
746 prevent the trap insn from being reached
747 (since it might exit!) */
750 {
754 /* A potential lossage is where we have a case where two insns
755 can be combined as long as they are both in the loop, but
756 we move one of them outside the loop. For large loops,
757 this can lose. The most common case of this is the address
758 of a function being called.
760 Therefore, if this register is marked as being used exactly
761 once if we are in a loop with calls (a "large loop"), see if
762 we can replace the usage of this register with the source
763 of this SET. If we can, delete this insn.
765 Don't do this if P has a REG_RETVAL note or if we have
766 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
777 && (! SMALL_REGISTER_CLASSES
780 /* This test is not redundant; SET_SRC (set) might be
781 a call-clobbered register and the life of REGNO
782 might span a call. */
788 {
789 /* Replace any usage in a REG_EQUAL note. Must copy the
790 new source, so that we don't get rtx sharing between the
791 SET_SOURCE and REG_NOTES of insn p. */
801 }
819 /* Set M->cond if either loop_invariant_p
820 or consec_sets_invariant_p returned 2
821 (only conditionally invariant). */
830 /* Add M to the end of the chain MOVABLES. */
834 {
835 /* It is possible for the first instruction to have a
836 REG_EQUAL note but a non-invariant SET_SRC, so we must
837 remember the status of the first instruction in case
838 the last instruction doesn't have a REG_EQUAL note. */
841 /* Skip this insn, not checking REG_LIBCALL notes. */
843 /* Skip the consecutive insns, if there are any. */
845 /* Back up to the last insn of the consecutive group. */
848 /* We must now reset m->move_insn, m->is_equiv, and possibly
849 m->set_src to correspond to the effects of all the
850 insns. */
854 else
855 {
859 else
862 }
864 }
865 }
866 /* If this register is always set within a STRICT_LOW_PART
867 or set to zero, then its high bytes are constant.
868 So clear them outside the loop and within the loop
869 just load the low bytes.
870 We must check that the machine has an instruction to do so.
871 Also, if the value loaded into the register
872 depends on the same register, this cannot be done. */
882 {
885 {
899 /* If the insn may not be executed on some cycles,
900 we can't clear the whole reg; clear just high part.
901 Not even if the reg is used only within this loop.
902 Consider this:
903 while (1)
904 while (s != t) {
905 if (foo ()) x = *s;
906 use (x);
907 }
908 Clearing x before the inner loop could clobber a value
909 being saved from the last time around the outer loop.
910 However, if the reg is not used outside this loop
911 and all uses of the register are in the same
912 basic block as the store, there is no problem.
914 If this insn was made by loop, we don't know its
915 INSN_LUID and hence must make a conservative
916 assumption. */
919 || (labels_in_range_p
923 else
931 /* Add M to the end of the chain MOVABLES. */
933 }
934 }
935 }
936 /* Past a call insn, we get to insns which might not be executed
937 because the call might exit. This matters for insns that trap.
938 Constant and pure call insns always return, so they don't count. */
941 /* Past a label or a jump, we get to insns for which we
942 can't count on whether or how many times they will be
943 executed during each iteration. Therefore, we can
944 only move out sets of trivial variables
945 (those not used after the loop). */
946 /* Similar code appears twice in strength_reduce. */
948 /* If we enter the loop in the middle, and scan around to the
949 beginning, don't set maybe_never for that. This must be an
950 unconditional jump, otherwise the code at the top of the
951 loop might never be executed. Unconditional jumps are
952 followed a by barrier then loop end. */
958 {
959 /* At the virtual top of a converted loop, insns are again known to
960 be executed: logically, the loop begins here even though the exit
961 code has been duplicated. */
965 loop_depth++;
967 loop_depth--;
968 }
969 }
971 /* If one movable subsumes another, ignore that other. */
975 /* For each movable insn, see if the reg that it loads
976 leads when it dies right into another conditionally movable insn.
977 If so, record that the second insn "forces" the first one,
978 since the second can be moved only if the first is. */
982 /* See if there are multiple movable insns that load the same value.
983 If there are, make all but the first point at the first one
984 through the `match' field, and add the priorities of them
985 all together as the priority of the first. */
989 /* Now consider each movable insn to decide whether it is worth moving.
990 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
992 Generally this increases code size, so do not move moveables when
993 optimizing for code size. */
998 /* Now candidates that still are negative are those not moved.
999 Change regs->array[I].set_in_loop to indicate that those are not actually
1000 invariant. */
1005 /* Now that we've moved some things out of the loop, we might be able to
1006 hoist even more memory references. */
1009 /* Recalculate regs->array if load_mems has created new registers. */
1017 ;
1024 {
1026 /* Ensure our label doesn't go away. */
1037 }
1040 /* The movable information is required for strength reduction. */
1046 }
1047 \f
1048 /* Add elements to *OUTPUT to record all the pseudo-regs
1049 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1051 void
1055 {
1063 {
1081 }
1085 {
1089 {
1098 }
1099 }
1100 }
1101 \f
1102 /* Check what regs are referred to in the libcall block ending with INSN,
1103 aside from those mentioned in the equivalent value.
1104 If there are none, return 0.
1105 If there are one or more, return an EXPR_LIST containing all of them. */
1107 rtx
1110 {
1115 /* First, find all the regs used in the libcall block
1116 that are not mentioned as inputs to the result. */
1119 {
1124 }
1127 }
1128 \f
1129 /* Return 1 if all uses of REG
1130 are between INSN and the end of the basic block. */
1132 static int
1135 {
1137 rtx p;
1142 /* Search this basic block for the already recorded last use of the reg. */
1144 {
1146 {
1152 /* Ordinary insn: if this is the last use, we win. */
1158 /* Jump insn: if this is the last use, we win. */
1161 /* Otherwise, it's the end of the basic block, so we lose. */
1166 /* It's the end of the basic block, so we lose. */
1171 }
1172 }
1174 /* The "last use" that was recorded can't be found after the first
1175 use. This can happen when the last use was deleted while
1176 processing an inner loop, this inner loop was then completely
1177 unrolled, and the outer loop is always exited after the inner loop,
1178 so that everything after the first use becomes a single basic block. */
1180 }
1181 \f
1182 /* Compute the benefit of eliminating the insns in the block whose
1183 last insn is LAST. This may be a group of insns used to compute a
1184 value directly or can contain a library call. */
1186 static int
1188 rtx last;
1189 {
1190 rtx insn;
1195 {
1198 routine. */
1202 benefit++;
1203 }
1206 }
1207 \f
1208 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1210 static rtx
1212 rtx insn;
1214 {
1216 {
1217 rtx temp;
1219 /* If first insn of libcall sequence, skip to end. */
1220 /* Do this at start of loop, since INSN is guaranteed to
1221 be an insn here. */
1226 do
1229 }
1232 }
1234 /* Ignore any movable whose insn falls within a libcall
1235 which is part of another movable.
1236 We make use of the fact that the movable for the libcall value
1237 was made later and so appears later on the chain. */
1239 static void
1242 {
1246 {
1247 /* Is this a movable for the value of a libcall? */
1250 {
1251 rtx insn;
1252 /* Check for earlier movables inside that range,
1253 and mark them invalid. We cannot use LUIDs here because
1254 insns created by loop.c for prior loops don't have LUIDs.
1255 Rather than reject all such insns from movables, we just
1256 explicitly check each insn in the libcall (since invariant
1257 libcalls aren't that common). */
1262 }
1263 }
1264 }
1266 /* For each movable insn, see if the reg that it loads
1267 leads when it dies right into another conditionally movable insn.
1268 If so, record that the second insn "forces" the first one,
1269 since the second can be moved only if the first is. */
1271 static void
1274 {
1277 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1279 {
1282 /* ??? Could this be a bug? What if CSE caused the
1283 register of M1 to be used after this insn?
1284 Since CSE does not update regno_last_uid,
1285 this insn M->insn might not be where it dies.
1286 But very likely this doesn't matter; what matters is
1287 that M's reg is computed from M1's reg. */
1292 /* If m->consec, m->set_src isn't valid. */
1296 /* Increase the priority of the moving the first insn
1297 since it permits the second to be moved as well. */
1299 {
1303 }
1304 }
1305 }
1306 \f
1307 /* Find invariant expressions that are equal and can be combined into
1308 one register. */
1310 static void
1314 {
1319 /* Regs that are set more than once are not allowed to match
1320 or be matched. I'm no longer sure why not. */
1321 /* Perhaps testing m->consec_sets would be more appropriate here? */
1326 {
1333 /* We want later insns to match the first one. Don't make the first
1334 one match any later ones. So start this loop at m->next. */
1338 /* A reg used outside the loop mustn't be eliminated. */
1340 /* A reg used for zero-extending mustn't be eliminated. */
1343 ||
1344 (
1345 /* Can combine regs with different modes loaded from the
1346 same constant only if the modes are the same or
1347 if both are integer modes with M wider or the same
1348 width as M1. The check for integer is redundant, but
1349 safe, since the only case of differing destination
1350 modes with equal sources is when both sources are
1351 VOIDmode, i.e., CONST_INT. */
1357 /* See if the source of M1 says it matches M. */
1364 {
1370 }
1371 }
1373 /* Now combine the regs used for zero-extension.
1374 This can be done for those not marked `global'
1375 provided their lives don't overlap. */
1379 {
1382 /* Combine all the registers for extension from mode MODE.
1383 Don't combine any that are used outside this loop. */
1387 {
1393 {
1394 /* First one: don't check for overlap, just record it. */
1397 }
1399 /* Make sure they extend to the same mode.
1400 (Almost always true.) */
1404 /* We already have one: check for overlap with those
1405 already combined together. */
1412 /* No overlap: we can combine this with the others. */
1418 overlap:
1419 ;
1420 }
1421 }
1423 /* Clean up. */
1425 }
1427 /* Returns the number of movable instructions in LOOP that were not
1428 moved outside the loop. */
1430 static int
1433 {
1442 }
1444 \f
1445 /* Return 1 if regs X and Y will become the same if moved. */
1447 static int
1451 {
1468 }
1470 /* Return 1 if X and Y are identical-looking rtx's.
1471 This is the Lisp function EQUAL for rtx arguments.
1473 If two registers are matching movables or a movable register and an
1474 equivalent constant, consider them equal. */
1476 static int
1481 {
1495 /* If we have a register and a constant, they may sometimes be
1496 equal. */
1499 {
1504 }
1507 {
1512 }
1514 /* Otherwise, rtx's of different codes cannot be equal. */
1518 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1519 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1524 /* These three types of rtx's can be compared nonrecursively. */
1533 /* Compare the elements. If any pair of corresponding elements
1534 fail to match, return 0 for the whole things. */
1538 {
1540 {
1552 /* Two vectors must have the same length. */
1556 /* And the corresponding elements must match. */
1575 /* These are just backpointers, so they don't matter. */
1581 /* It is believed that rtx's at this level will never
1582 contain anything but integers and other rtx's,
1583 except for within LABEL_REFs and SYMBOL_REFs. */
1586 }
1587 }
1589 }
1590 \f
1591 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1592 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1593 references is incremented once for each added note. */
1595 static void
1597 rtx x;
1598 rtx insns;
1599 {
1603 rtx insn;
1606 {
1607 /* This code used to ignore labels that referred to dispatch tables to
1608 avoid flow generating (slighly) worse code.
1610 We no longer ignore such label references (see LABEL_REF handling in
1611 mark_jump_label for additional information). */
1614 {
1619 }
1620 }
1624 {
1630 }
1631 }
1632 \f
1633 /* Scan MOVABLES, and move the insns that deserve to be moved.
1634 If two matching movables are combined, replace one reg with the
1635 other throughout. */
1637 static void
1643 {
1651 /* Map of pseudo-register replacements to handle combining
1652 when we move several insns that load the same value
1653 into different pseudo-registers. */
1658 {
1659 /* Describe this movable insn. */
1662 {
1683 }
1685 /* Ignore the insn if it's already done (it matched something else).
1686 Otherwise, see if it is now safe to move. */
1698 {
1703 /* We have an insn that is safe to move.
1704 Compute its desirability. */
1715 /* An insn MUST be moved if we already moved something else
1716 which is safe only if this one is moved too: that is,
1717 if already_moved[REGNO] is nonzero. */
1719 /* An insn is desirable to move if the new lifetime of the
1720 register is no more than THRESHOLD times the old lifetime.
1721 If it's not desirable, it means the loop is so big
1722 that moving won't speed things up much,
1723 and it is liable to make register usage worse. */
1725 /* It is also desirable to move if it can be moved at no
1726 extra cost because something else was already moved. */
1729 || flag_move_all_movables
1734 {
1739 /* Now move the insns that set the reg. */
1742 {
1745 /* Find the end of this chain of matching regs.
1746 Thus, we load each reg in the chain from that one reg.
1747 And that reg is loaded with 0 directly,
1748 since it has ->match == 0. */
1754 /* Mark the moved, invariant reg as being allowed to
1755 share a hard reg with the other matching invariant. */
1759 regs_may_share
1762 regs_may_share));
1770 }
1771 /* If we are to re-generate the item being moved with a
1772 new move insn, first delete what we have and then emit
1773 the move insn before the loop. */
1775 {
1779 {
1780 /* If this is the first insn of a library call sequence,
1781 skip to the end. */
1786 /* If this is the last insn of a libcall sequence, then
1787 delete every insn in the sequence except the last.
1788 The last insn is handled in the normal manner. */
1791 {
1795 }
1800 /* simplify_giv_expr expects that it can walk the insns
1801 at m->insn forwards and see this old sequence we are
1802 tossing here. delete_insn does preserve the next
1803 pointers, but when we skip over a NOTE we must fix
1804 it up. Otherwise that code walks into the non-deleted
1805 insn stream. */
1808 }
1827 /* The more regs we move, the less we like moving them. */
1829 }
1830 else
1831 {
1833 {
1836 /* If first insn of libcall sequence, skip to end. */
1837 /* Do this at start of loop, since p is guaranteed to
1838 be an insn here. */
1843 /* If last insn of libcall sequence, move all
1844 insns except the last before the loop. The last
1845 insn is handled in the normal manner. */
1848 {
1856 {
1857 rtx body;
1858 rtx n;
1859 rtx next;
1866 /* Find the next insn after TEMP,
1867 not counting USE or NOTE insns. */
1875 /* If that is the call, this may be the insn
1876 that loads the function address.
1878 Extract the function address from the insn
1879 that loads it into a register.
1880 If this insn was cse'd, we get incorrect code.
1882 So emit a new move insn that copies the
1883 function address into the register that the
1884 call insn will use. flow.c will delete any
1885 redundant stores that we have created. */
1890 NULL_RTX)))
1891 {
1897 }
1898 /* We have the call insn.
1899 If it uses the register we suspect it might,
1900 load it with the correct address directly. */
1905 gen_move_insn
1909 {
1911 /* Because the USAGE information potentially
1912 contains objects other than hard registers
1913 we need to copy it. */
1917 }
1918 else
1926 }
1929 }
1931 {
1932 /* P sets REG to zero; but we should clear only
1933 the bits that are not covered by the mode
1934 m->savemode. */
1936 rtx sequence;
1937 rtx tem;
1940 tem = expand_binop
1953 }
1955 {
1957 /* Because the USAGE information potentially
1958 contains objects other than hard registers
1959 we need to copy it. */
1963 }
1965 {
1966 rtx seq;
1967 /* The SET_SRC might not be invariant, so we must
1968 use the REG_EQUAL note. */
1983 }
1984 else
1988 {
1991 /* If there is a REG_EQUAL note present whose value
1992 is not loop invariant, then delete it, since it
1993 may cause problems with later optimization passes.
1994 It is possible for cse to create such notes
1995 like this as a result of record_jump_cond. */
2000 }
2009 /* If library call, now fix the REG_NOTES that contain
2010 insn pointers, namely REG_LIBCALL on FIRST
2011 and REG_RETVAL on I1. */
2013 {
2017 }
2023 /* simplify_giv_expr expects that it can walk the insns
2024 at m->insn forwards and see this old sequence we are
2025 tossing here. delete_insn does preserve the next
2026 pointers, but when we skip over a NOTE we must fix
2027 it up. Otherwise that code walks into the non-deleted
2028 insn stream. */
2031 }
2033 /* The more regs we move, the less we like moving them. */
2035 }
2037 /* Any other movable that loads the same register
2038 MUST be moved. */
2041 /* This reg has been moved out of one loop. */
2044 /* The reg set here is now invariant. */
2050 /* Change the length-of-life info for the register
2051 to say it lives at least the full length of this loop.
2052 This will help guide optimizations in outer loops. */
2055 /* This is the old insn before all the moved insns.
2056 We can't use the moved insn because it is out of range
2057 in uid_luid. Only the old insns have luids. */
2062 /* Combine with this moved insn any other matching movables. */
2067 {
2068 rtx temp;
2070 /* Schedule the reg loaded by M1
2071 for replacement so that shares the reg of M.
2072 If the modes differ (only possible in restricted
2073 circumstances, make a SUBREG.
2075 Note this assumes that the target dependent files
2076 treat REG and SUBREG equally, including within
2077 GO_IF_LEGITIMATE_ADDRESS and in all the
2078 predicates since we never verify that replacing the
2079 original register with a SUBREG results in a
2080 recognizable insn. */
2083 else
2088 /* Get rid of the matching insn
2089 and prevent further processing of it. */
2092 /* if library call, delete all insn except last, which
2093 is deleted below */
2095 NULL_RTX)))
2096 {
2100 }
2103 /* Any other movable that loads the same register
2104 MUST be moved. */
2107 /* The reg merged here is now invariant,
2108 if the reg it matches is invariant. */
2111 }
2112 }
2115 }
2121 }
2126 /* Go through all the instructions in the loop, making
2127 all the register substitutions scheduled in REG_MAP. */
2131 {
2135 }
2137 /* Clean up. */
2140 }
2143 static void
2147 {
2150 else
2153 }
2156 static void
2159 {
2164 {
2167 }
2168 }
2169 \f
2170 #if 0
2171 /* Scan X and replace the address of any MEM in it with ADDR.
2172 REG is the address that MEM should have before the replacement. */
2174 static void
2177 {
2186 {
2198 /* Short cut for very common case. */
2203 /* Short cut for very common case. */
2208 /* If this MEM uses a reg other than the one we expected,
2209 something is wrong. */
2217 }
2221 {
2225 {
2229 }
2230 }
2231 }
2232 #endif
2233 \f
2234 /* Return the number of memory refs to addresses that vary
2235 in the rtx X. */
2237 static int
2240 rtx x;
2241 {
2252 {
2269 }
2274 {
2278 {
2282 }
2283 }
2285 }
2286 \f
2287 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2288 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2289 `unknown_address_altered', `unknown_constant_address_altered', and
2290 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2291 list `store_mems' in LOOP. */
2293 static void
2296 {
2298 rtx insn;
2302 /* The label after END. Jumping here is just like falling off the
2303 end of the loop. We use next_nonnote_insn instead of next_label
2304 as a hedge against the (pathological) case where some actual insn
2305 might end up between the two. */
2327 {
2329 {
2332 }
2333 }
2337 {
2339 {
2341 {
2343 /* Count number of loops contained in this one. */
2345 }
2347 {
2349 }
2350 }
2352 {
2354 {
2357 }
2359 }
2361 {
2381 {
2383 {
2386 }
2387 else
2388 {
2390 }
2392 do
2393 {
2395 {
2397 {
2398 /* Something tricky. */
2401 }
2404 {
2405 /* A jump outside the current loop. */
2408 }
2409 }
2413 }
2415 }
2416 }
2419 }
2421 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2423 anywhere. */
2425 /* We don't want loads for MEMs moved to a location before the
2426 one at which their stack memory becomes allocated. (Note
2427 that this is not a problem for malloc, etc., since those
2428 require actual function calls. */
2429 && ! current_function_calls_alloca
2430 /* There are ways to leave the loop other than falling off the
2431 end. */
2437 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2438 that loop_invariant_p and load_mems can use true_dependence
2439 to determine what is really clobbered. */
2441 {
2444 loop_info->store_mems
2446 }
2448 {
2452 loop_info->store_mems
2454 }
2455 }
2456 \f
2457 /* Scan the function looking for loops. Record the start and end of each loop.
2458 Also mark as invalid loops any loops that contain a setjmp or are branched
2459 to from outside the loop. */
2461 static void
2463 rtx f;
2465 {
2466 rtx insn;
2467 rtx label;
2477 /* If there are jumps to undefined labels,
2478 treat them as jumps out of any/all loops.
2479 This also avoids writing past end of tables when there are no loops. */
2482 /* Find boundaries of loops, mark which loops are contained within
2483 loops, and invalidate loops that have setjmp. */
2488 {
2491 {
2495 num_loops++;
2502 /* In this case, we must invalidate our current loop and any
2503 enclosing loop. */
2505 {
2511 }
2532 }
2534 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2535 enclosing loop, but this doesn't matter. */
2537 }
2539 /* Any loop containing a label used in an initializer must be invalidated,
2540 because it can be jumped into from anywhere. */
2543 {
2547 }
2549 /* Any loop containing a label used for an exception handler must be
2550 invalidated, because it can be jumped into from anywhere. */
2553 {
2557 }
2559 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2560 loop that it is not contained within, that loop is marked invalid.
2561 If any INSN or CALL_INSN uses a label's address, then the loop containing
2562 that label is marked invalid, because it could be jumped into from
2563 anywhere.
2565 Also look for blocks of code ending in an unconditional branch that
2566 exits the loop. If such a block is surrounded by a conditional
2567 branch around the block, move the block elsewhere (see below) and
2568 invert the jump to point to the code block. This may eliminate a
2569 label in our loop and will simplify processing by both us and a
2570 possible second cse pass. */
2574 {
2578 {
2581 {
2585 }
2586 }
2593 /* See if this is an unconditional branch outside the loop. */
2601 {
2602 rtx p;
2608 /* Go backwards until we reach the start of the loop, a label,
2609 or a JUMP_INSN. */
2616 ;
2618 /* Check for the case where we have a jump to an inner nested
2619 loop, and do not perform the optimization in that case. */
2622 {
2625 {
2630 }
2631 }
2633 /* Make sure that the target of P is within the current loop. */
2639 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2640 we have a block of code to try to move.
2642 We look backward and then forward from the target of INSN
2643 to find a BARRIER at the same loop depth as the target.
2644 If we find such a BARRIER, we make a new label for the start
2645 of the block, invert the jump in P and point it to that label,
2646 and move the block of code to the spot we found. */
2651 /* Just ignore jumps to labels that were never emitted.
2652 These always indicate compilation errors. */
2656 /* If it's not safe to move the sequence, then we
2657 mustn't try. */
2660 {
2661 rtx target
2668 /* Don't move things inside a tablejump. */
2681 /* Don't move things inside a tablejump. */
2692 {
2696 /* Ensure our label doesn't go away. */
2699 /* Verify that uid_loop is large enough and that
2700 we can invert P. */
2702 {
2705 /* If no suitable BARRIER was found, create a suitable
2706 one before TARGET. Since TARGET is a fall through
2707 path, we'll need to insert an jump around our block
2708 and a add a BARRIER before TARGET.
2710 This creates an extra unconditional jump outside
2711 the loop. However, the benefits of removing rarely
2712 executed instructions from inside the loop usually
2713 outweighs the cost of the extra unconditional jump
2714 outside the loop. */
2716 {
2717 rtx temp;
2724 }
2726 /* Include the BARRIER after INSN and copy the
2727 block after LOC. */
2729 last_insn_to_move);
2732 /* All those insns are now in TARGET_LOOP. */
2738 /* The label jumped to by INSN is no longer a loop
2739 exit. Unless INSN does not have a label (e.g.,
2740 it is a RETURN insn), search loop->exit_labels
2741 to find its label_ref, and remove it. Also turn
2742 off LABEL_OUTSIDE_LOOP_P bit. */
2744 {
2746 r;
2749 {
2753 else
2756 }
2762 /* If we didn't find it, then something is
2763 wrong. */
2766 }
2768 /* P is now a jump outside the loop, so it must be put
2769 in loop->exit_labels, and marked as such.
2770 The easiest way to do this is to just call
2771 mark_loop_jump again for P. */
2774 /* If INSN now jumps to the insn after it,
2775 delete INSN. */
2780 }
2782 /* Continue the loop after where the conditional
2783 branch used to jump, since the only branch insn
2784 in the block (if it still remains) is an inter-loop
2785 branch and hence needs no processing. */
2791 /* This loop will be continued with NEXT_INSN (insn). */
2793 }
2794 }
2795 }
2796 }
2797 }
2799 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2800 loops it is contained in, mark the target loop invalid.
2802 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2804 static void
2806 rtx x;
2808 {
2814 {
2826 /* There could be a label reference in here. */
2838 /* This may refer to a LABEL_REF or SYMBOL_REF. */
2850 /* Link together all labels that branch outside the loop. This
2851 is used by final_[bg]iv_value and the loop unrolling code. Also
2852 mark this LABEL_REF so we know that this branch should predict
2853 false. */
2855 /* A check to make sure the label is not in an inner nested loop,
2856 since this does not count as a loop exit. */
2858 {
2863 }
2864 else
2868 {
2877 }
2879 /* If this is inside a loop, but not in the current loop or one enclosed
2880 by it, it invalidates at least one loop. */
2885 /* We must invalidate every nested loop containing the target of this
2886 label, except those that also contain the jump insn. */
2889 {
2890 /* Stop when we reach a loop that also contains the jump insn. */
2895 /* If we get here, we know we need to invalidate a loop. */
2902 }
2906 /* If this is not setting pc, ignore. */
2928 /* Strictly speaking this is not a jump into the loop, only a possible
2929 jump out of the loop. However, we have no way to link the destination
2930 of this jump onto the list of exit labels. To be safe we mark this
2931 loop and any containing loops as invalid. */
2933 {
2935 {
2941 }
2942 }
2944 }
2945 }
2946 \f
2947 /* Return nonzero if there is a label in the range from
2948 insn INSN to and including the insn whose luid is END
2949 INSN must have an assigned luid (i.e., it must not have
2950 been previously created by loop.c). */
2952 static int
2954 rtx insn;
2956 {
2958 {
2962 }
2965 }
2967 /* Record that a memory reference X is being set. */
2969 static void
2971 rtx x;
2972 rtx y ATTRIBUTE_UNUSED;
2974 {
2980 /* Count number of memory writes.
2981 This affects heuristics in strength_reduce. */
2984 /* BLKmode MEM means all memory is clobbered. */
2986 {
2989 else
2993 }
2997 }
2999 /* X is a value modified by an INSN that references a biv inside a loop
3000 exit test (ie, X is somehow related to the value of the biv). If X
3001 is a pseudo that is used more than once, then the biv is (effectively)
3002 used more than once. DATA is a pointer to a loop_regs structure. */
3004 static void
3006 rtx x;
3007 rtx y ATTRIBUTE_UNUSED;
3009 {
3024 /* If we do not have usage information, or if we know the register
3025 is used more than once, note that fact for check_dbra_loop. */
3030 }
3031 \f
3032 /* Return nonzero if the rtx X is invariant over the current loop.
3034 The value is 2 if we refer to something only conditionally invariant.
3036 A memory ref is invariant if it is not volatile and does not conflict
3037 with anything stored in `loop_info->store_mems'. */
3039 int
3043 {
3050 rtx mem_list_entry;
3056 {
3064 /* A LABEL_REF is normally invariant, however, if we are unrolling
3065 loops, and this label is inside the loop, then it isn't invariant.
3066 This is because each unrolled copy of the loop body will have
3067 a copy of this label. If this was invariant, then an insn loading
3068 the address of this label into a register might get moved outside
3069 the loop, and then each loop body would end up using the same label.
3071 We don't know the loop bounds here though, so just fail for all
3072 labels. */
3075 else
3084 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3085 since the reg might be set by initialization within the loop. */
3102 /* Volatile memory references must be rejected. Do this before
3103 checking for read-only items, so that volatile read-only items
3104 will be rejected also. */
3108 /* See if there is any dependence between a store and this load. */
3111 {
3117 }
3119 /* It's not invalidated by a store in memory
3120 but we must still verify the address is invariant. */
3124 /* Don't mess with insns declared volatile. */
3131 }
3135 {
3137 {
3143 }
3145 {
3148 {
3154 }
3156 }
3157 }
3160 }
3161 \f
3162 /* Return nonzero if all the insns in the loop that set REG
3163 are INSN and the immediately following insns,
3164 and if each of those insns sets REG in an invariant way
3165 (not counting uses of REG in them).
3167 The value is 2 if some of these insns are only conditionally invariant.
3169 We assume that INSN itself is the first set of REG
3170 and that its source is invariant. */
3172 static int
3177 {
3181 rtx temp;
3182 /* Number of sets we have to insist on finding after INSN. */
3188 /* If N_SETS hit the limit, we can't rely on its value. */
3195 {
3197 rtx set;
3202 /* If library call, skip to end of it. */
3211 {
3216 {
3217 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3218 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3219 notes are OK. */
3225 }
3226 }
3228 count--;
3230 {
3233 }
3234 }
3237 /* If loop_invariant_p ever returned 2, we return 2. */
3239 }
3241 #if 0
3242 /* I don't think this condition is sufficient to allow INSN
3243 to be moved, so we no longer test it. */
3245 /* Return 1 if all insns in the basic block of INSN and following INSN
3246 that set REG are invariant according to TABLE. */
3248 static int
3252 {
3257 {
3266 {
3269 }
3270 }
3271 }
3273 \f
3274 /* Look at all uses (not sets) of registers in X. For each, if it is
3275 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3276 a different insn, set USAGE[REGNO] to const0_rtx. */
3278 static void
3281 rtx insn;
3282 rtx x;
3283 {
3295 {
3296 /* Don't count SET_DEST if it is a REG; otherwise count things
3297 in SET_DEST because if a register is partially modified, it won't
3298 show up as a potential movable so we don't care how USAGE is set
3299 for it. */
3303 }
3304 else
3306 {
3312 }
3313 }
3314 \f
3315 /* Count and record any set in X which is contained in INSN. Update
3316 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3317 in X. */
3319 static void
3324 {
3326 /* Don't move a reg that has an explicit clobber.
3327 It's not worth the pain to try to do it correctly. */
3331 {
3339 {
3341 /* If this is the first setting of this reg
3342 in current basic block, and it was set before,
3343 it must be set in two basic blocks, so it cannot
3344 be moved out of the loop. */
3348 /* If this is not first setting in current basic block,
3349 see if reg was used in between previous one and this.
3350 If so, neither one can be moved. */
3357 }
3358 }
3359 }
3360 \f
3361 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3362 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3363 contained in insn INSN is used by any insn that precedes INSN in
3364 cyclic order starting from the loop entry point.
3366 We don't want to use INSN_LUID here because if we restrict INSN to those
3367 that have a valid INSN_LUID, it means we cannot move an invariant out
3368 from an inner loop past two loops. */
3370 static int
3374 {
3376 rtx p;
3378 /* Scan forward checking for register usage. If we hit INSN, we
3379 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3381 {
3387 }
3390 }
3391 \f
3392 /* A "basic induction variable" or biv is a pseudo reg that is set
3393 (within this loop) only by incrementing or decrementing it. */
3394 /* A "general induction variable" or giv is a pseudo reg whose
3395 value is a linear function of a biv. */
3397 /* Bivs are recognized by `basic_induction_var';
3398 Givs by `general_induction_var'. */
3400 /* Communication with routines called via `note_stores'. */
3404 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
3408 /* ??? Unfinished optimizations, and possible future optimizations,
3409 for the strength reduction code. */
3411 /* ??? The interaction of biv elimination, and recognition of 'constant'
3412 bivs, may cause problems. */
3414 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
3415 performance problems.
3417 Perhaps don't eliminate things that can be combined with an addressing
3418 mode. Find all givs that have the same biv, mult_val, and add_val;
3419 then for each giv, check to see if its only use dies in a following
3420 memory address. If so, generate a new memory address and check to see
3421 if it is valid. If it is valid, then store the modified memory address,
3422 otherwise, mark the giv as not done so that it will get its own iv. */
3424 /* ??? Could try to optimize branches when it is known that a biv is always
3425 positive. */
3427 /* ??? When replace a biv in a compare insn, we should replace with closest
3428 giv so that an optimized branch can still be recognized by the combiner,
3429 e.g. the VAX acb insn. */
3431 /* ??? Many of the checks involving uid_luid could be simplified if regscan
3432 was rerun in loop_optimize whenever a register was added or moved.
3433 Also, some of the optimizations could be a little less conservative. */
3434 \f
3435 /* Scan the loop body and call FNCALL for each insn. In the addition to the
3436 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
3437 callback.
3439 NOT_EVERY_ITERATION if current insn is not executed at least once for every
3440 loop iteration except for the last one.
3442 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
3443 loop iteration.
3444 */
3445 void
3448 loop_insn_callback fncall;
3449 {
3450 /* This is 1 if current insn is not executed at least once for every loop
3451 iteration. */
3456 rtx p;
3458 /* If loop_scan_start points to the loop exit test, we have to be wary of
3459 subversive use of gotos inside expression statements. */
3463 /* Scan through loop to find all possible bivs. */
3468 {
3471 /* Past CODE_LABEL, we get to insns that may be executed multiple
3472 times. The only way we can be sure that they can't is if every
3473 jump insn between here and the end of the loop either
3474 returns, exits the loop, is a jump to a location that is still
3475 behind the label, or is a jump to the loop start. */
3478 {
3484 {
3489 {
3492 else
3496 }
3504 {
3507 }
3508 }
3509 }
3511 /* Past a jump, we get to insns for which we can't count
3512 on whether they will be executed during each iteration. */
3513 /* This code appears twice in strength_reduce. There is also similar
3514 code in scan_loop. */
3516 /* If we enter the loop in the middle, and scan around to the
3517 beginning, don't set not_every_iteration for that.
3518 This can be any kind of jump, since we want to know if insns
3519 will be executed if the loop is executed. */
3524 {
3527 /* If this is a jump outside the loop, then it also doesn't
3528 matter. Check to see if the target of this branch is on the
3529 loop->exits_labels list. */
3537 }
3540 {
3541 /* At the virtual top of a converted loop, insns are again known to
3542 be executed each iteration: logically, the loop begins here
3543 even though the exit code has been duplicated.
3545 Insns are also again known to be executed each iteration at
3546 the LOOP_CONT note. */
3552 loop_depth++;
3554 loop_depth--;
3555 }
3557 /* Note if we pass a loop latch. If we do, then we can not clear
3558 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
3559 a loop since a jump before the last CODE_LABEL may have started
3560 a new loop iteration.
3562 Note that LOOP_TOP is only set for rotated loops and we need
3563 this check for all loops, so compare against the CODE_LABEL
3564 which immediately follows LOOP_START. */
3569 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
3570 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
3571 or not an insn is known to be executed each iteration of the
3572 loop, whether or not any iterations are known to occur.
3574 Therefore, if we have just passed a label and have no more labels
3575 between here and the test insn of the loop, and we have not passed
3576 a jump to the top of the loop, then we know these insns will be
3577 executed each iteration. */
3580 && !past_loop_latch
3585 }
3586 }
3587 \f
3588 static void
3591 {
3594 /* Temporary list pointers for traversing ivs->list. */
3601 /* Scan ivs->list to remove all regs that proved not to be bivs.
3602 Make a sanity check against regs->n_times_set. */
3604 {
3606 /* Above happens if register modified by subreg, etc. */
3607 /* Make sure it is not recognized as a basic induction var: */
3609 /* If never incremented, it is invariant that we decided not to
3610 move. So leave it alone. */
3612 {
3623 }
3624 else
3625 {
3630 }
3631 }
3632 }
3635 /* Determine how BIVS are initialised by looking through pre-header
3636 extended basic block. */
3637 static void
3640 {
3642 /* Temporary list pointers for traversing ivs->list. */
3645 rtx p;
3647 /* Find initial value for each biv by searching backwards from loop_start,
3648 halting at first label. Also record any test condition. */
3652 {
3653 rtx test;
3663 /* Record any test of a biv that branches around the loop if no store
3664 between it and the start of loop. We only care about tests with
3665 constants and registers and only certain of those. */
3675 {
3676 /* If an NE test, we have an initial value! */
3678 {
3682 }
3683 else
3685 }
3686 }
3687 }
3690 /* Look at the each biv and see if we can say anything better about its
3691 initial value from any initializing insns set up above. (This is done
3692 in two passes to avoid missing SETs in a PARALLEL.) */
3693 static void
3696 {
3698 /* Temporary list pointers for traversing ivs->list. */
3703 {
3704 rtx src;
3705 rtx note;
3710 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
3711 is a constant, use the value of that. */
3717 else
3730 {
3734 {
3737 }
3738 }
3739 /* If we can't make it a giv,
3740 let biv keep initial value of "itself". */
3743 }
3744 }
3747 /* Search the loop for general induction variables. */
3749 static void
3752 {
3754 }
3757 /* For each giv for which we still don't know whether or not it is
3758 replaceable, check to see if it is replaceable because its final value
3759 can be calculated. */
3761 static void
3764 {
3769 {
3775 }
3776 }
3779 /* Return non-zero if it is possible to eliminate the biv BL provided
3780 all givs are reduced. This is possible if either the reg is not
3781 used outside the loop, or we can compute what its final value will
3782 be. */
3784 static int
3790 {
3791 /* For architectures with a decrement_and_branch_until_zero insn,
3792 don't do this if we put a REG_NONNEG note on the endtest for this
3793 biv. */
3795 #ifdef HAVE_decrement_and_branch_until_zero
3797 {
3802 }
3803 #endif
3805 /* Check that biv is used outside loop or if it has a final value.
3806 Compare against bl->init_insn rather than loop->start. We aren't
3807 concerned with any uses of the biv between init_insn and
3808 loop->start since these won't be affected by the value of the biv
3809 elsewhere in the function, so long as init_insn doesn't use the
3810 biv itself. */
3821 {
3829 }
3831 }
3834 /* Reduce each giv of BL that we have decided to reduce. */
3836 static void
3840 {
3844 {
3847 {
3850 /* If the code for derived givs immediately below has already
3851 allocated a new_reg, we must keep it. */
3855 #ifdef AUTO_INC_DEC
3856 /* If the target has auto-increment addressing modes, and
3857 this is an address giv, then try to put the increment
3858 immediately after its use, so that flow can create an
3859 auto-increment addressing mode. */
3862 /* We don't handle reversed biv's because bl->biv->insn
3863 does not have a valid INSN_LUID. */
3867 {
3868 /* If other giv's have been combined with this one, then
3869 this will work only if all uses of the other giv's occur
3870 before this giv's insn. This is difficult to check.
3872 We simplify this by looking for the common case where
3873 there is one DEST_REG giv, and this giv's insn is the
3874 last use of the dest_reg of that DEST_REG giv. If the
3875 increment occurs after the address giv, then we can
3876 perform the optimization. (Otherwise, the increment
3877 would have to go before other_giv, and we would not be
3878 able to combine it with the address giv to get an
3879 auto-inc address.) */
3881 {
3886 {
3889 else
3891 }
3898 }
3899 /* Check for case where increment is before the address
3900 giv. Do this test in "loop order". */
3909 else
3912 #ifdef HAVE_cc0
3913 {
3914 rtx prev;
3916 /* We can't put an insn immediately after one setting
3917 cc0, or immediately before one using cc0. */
3924 }
3925 #endif
3929 }
3930 #endif
3932 /* For each place where the biv is incremented, add an insn
3933 to increment the new, reduced reg for the giv. */
3935 {
3936 rtx insert_before;
3942 else
3950 /* A multiply is acceptable here
3951 since this is presumed to be seldom executed. */
3955 }
3957 /* Add code at loop start to initialize giv's reduced reg. */
3962 }
3963 }
3964 }
3967 /* Check for givs whose first use is their definition and whose
3968 last use is the definition of another giv. If so, it is likely
3969 dead and should not be used to derive another giv nor to
3970 eliminate a biv. */
3972 static void
3976 {
3980 {
3987 {
3993 }
3994 }
3995 }
3998 static void
4003 {
4007 {
4014 /* Update expression if this was combined, in case other giv was
4015 replaced. */
4020 /* See if this register is known to be a pointer to something. If
4021 so, see if we can find the alignment. First see if there is a
4022 destination register that is a pointer. If so, this shares the
4023 alignment too. Next see if we can deduce anything from the
4024 computational information. If not, and this is a DEST_ADDR
4025 giv, at least we know that it's a pointer, though we don't know
4026 the alignment. */
4034 {
4043 }
4047 {
4055 }
4060 /* Store reduced reg as the address in the memref where we found
4061 this giv. */
4064 {
4066 }
4067 else
4068 {
4069 /* Not replaceable; emit an insn to set the original giv reg from
4070 the reduced giv, same as above. */
4073 }
4075 /* When a loop is reversed, givs which depend on the reversed
4076 biv, and which are live outside the loop, must be set to their
4077 correct final value. This insn is only needed if the giv is
4078 not replaceable. The correct final value is the same as the
4079 value that the giv starts the reversed loop with. */
4089 {
4094 }
4095 }
4096 }
4099 static int
4104 rtx test_reg;
4105 {
4114 /* Reduce benefit if not replaceable, since we will insert a
4115 move-insn to replace the insn that calculates this giv. Don't do
4116 this unless the giv is a user variable, since it will often be
4117 marked non-replaceable because of the duplication of the exit
4118 code outside the loop. In such a case, the copies we insert are
4119 dead and will be deleted. So they don't have a cost. Similar
4120 situations exist. */
4121 /* ??? The new final_[bg]iv_value code does a much better job of
4122 finding replaceable giv's, and hence this code may no longer be
4123 necessary. */
4128 /* Decrease the benefit to count the add-insns that we will insert
4129 to increment the reduced reg for the giv. ??? This can
4130 overestimate the run-time cost of the additional insns, e.g. if
4131 there are multiple basic blocks that increment the biv, but only
4132 one of these blocks is executed during each iteration. There is
4133 no good way to detect cases like this with the current structure
4134 of the loop optimizer. This code is more accurate for
4135 determining code size than run-time benefits. */
4138 /* Decide whether to strength-reduce this giv or to leave the code
4139 unchanged (recompute it from the biv each time it is used). This
4140 decision can be made independently for each giv. */
4142 #ifdef AUTO_INC_DEC
4143 /* Attempt to guess whether autoincrement will handle some of the
4144 new add insns; if so, increase BENEFIT (undo the subtraction of
4145 add_cost that was done above). */
4147 /* Increasing the benefit is risky, since this is only a guess.
4148 Avoid increasing register pressure in cases where there would
4149 be no other benefit from reducing this giv. */
4152 {
4167 }
4168 #endif
4171 }
4174 /* Free IV structures for LOOP. */
4176 static void
4179 {
4186 {
4192 {
4195 }
4197 {
4200 }
4204 }
4205 }
4208 /* Perform strength reduction and induction variable elimination.
4210 Pseudo registers created during this function will be beyond the
4211 last valid index in several tables including
4212 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
4213 problem here, because the added registers cannot be givs outside of
4214 their loop, and hence will never be reconsidered. But scan_loop
4215 must check regnos to make sure they are in bounds. */
4217 static void
4221 {
4225 rtx p;
4226 /* Temporary list pointer for traversing ivs->list. */
4228 /* Ratio of extra register life span we can justify
4229 for saving an instruction. More if loop doesn't call subroutines
4230 since in that case saving an insn makes more difference
4231 and more registers are available. */
4232 /* ??? could set this to last value of threshold in move_movables */
4234 /* Map of pseudo-register replacements. */
4246 /* Find all BIVs in loop. */
4249 /* Exit if there are no bivs. */
4251 {
4252 /* Can still unroll the loop anyways, but indicate that there is no
4253 strength reduction info available. */
4259 }
4261 /* Determine how BIVS are initialised by looking through pre-header
4262 extended basic block. */
4265 /* Look at the each biv and see if we can say anything better about its
4266 initial value from any initializing insns set up above. */
4269 /* Search the loop for general induction variables. */
4272 /* Try to calculate and save the number of loop iterations. This is
4273 set to zero if the actual number can not be calculated. This must
4274 be called after all giv's have been identified, since otherwise it may
4275 fail if the iteration variable is a giv. */
4278 /* Now for each giv for which we still don't know whether or not it is
4279 replaceable, check to see if it is replaceable because its final value
4280 can be calculated. This must be done after loop_iterations is called,
4281 so that final_giv_value will work correctly. */
4284 /* Try to prove that the loop counter variable (if any) is always
4285 nonnegative; if so, record that fact with a REG_NONNEG note
4286 so that "decrement and branch until zero" insn can be used. */
4289 /* Create reg_map to hold substitutions for replaceable giv regs.
4290 Some givs might have been made from biv increments, so look at
4291 ivs->reg_iv_type for a suitable size. */
4295 /* Examine each iv class for feasibility of strength reduction/induction
4296 variable elimination. */
4299 {
4303 /* Test whether it will be possible to eliminate this biv
4304 provided all givs are reduced. */
4307 /* Check each extension dependent giv in this class to see if its
4308 root biv is safe from wrapping in the interior mode. */
4311 /* Combine all giv's for this iv_class. */
4314 /* This will be true at the end, if all givs which depend on this
4315 biv have been strength reduced.
4316 We can't (currently) eliminate the biv unless this is so. */
4320 {
4328 /* If an insn is not to be strength reduced, then set its ignore
4329 flag, and clear bl->all_reduced. */
4331 /* A giv that depends on a reversed biv must be reduced if it is
4332 used after the loop exit, otherwise, it would have the wrong
4333 value after the loop exit. To make it simple, just reduce all
4334 of such giv's whether or not we know they are used after the loop
4335 exit. */
4340 {
4348 }
4349 else
4350 {
4351 /* Check that we can increment the reduced giv without a
4352 multiply insn. If not, reject it. */
4357 {
4365 }
4366 }
4367 }
4369 /* Check for givs whose first use is their definition and whose
4370 last use is the definition of another giv. If so, it is likely
4371 dead and should not be used to derive another giv nor to
4372 eliminate a biv. */
4375 /* Reduce each giv that we decided to reduce. */
4378 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
4379 as not reduced.
4381 For each giv register that can be reduced now: if replaceable,
4382 substitute reduced reg wherever the old giv occurs;
4383 else add new move insn "giv_reg = reduced_reg". */
4386 /* All the givs based on the biv bl have been reduced if they
4387 merit it. */
4389 /* For each giv not marked as maybe dead that has been combined with a
4390 second giv, clear any "maybe dead" mark on that second giv.
4391 v->new_reg will either be or refer to the register of the giv it
4392 combined with.
4394 Doing this clearing avoids problems in biv elimination where
4395 a giv's new_reg is a complex value that can't be put in the
4396 insn but the giv combined with (with a reg as new_reg) is
4397 marked maybe_dead. Since the register will be used in either
4398 case, we'd prefer it be used from the simpler giv. */
4404 /* Try to eliminate the biv, if it is a candidate.
4405 This won't work if ! bl->all_reduced,
4406 since the givs we planned to use might not have been reduced.
4408 We have to be careful that we didn't initially think we could
4409 eliminate this biv because of a giv that we now think may be
4410 dead and shouldn't be used as a biv replacement.
4412 Also, there is the possibility that we may have a giv that looks
4413 like it can be used to eliminate a biv, but the resulting insn
4414 isn't valid. This can happen, for example, on the 88k, where a
4415 JUMP_INSN can compare a register only with zero. Attempts to
4416 replace it with a compare with a constant will fail.
4418 Note that in cases where this call fails, we may have replaced some
4419 of the occurrences of the biv with a giv, but no harm was done in
4420 doing so in the rare cases where it can occur. */
4424 {
4425 /* ?? If we created a new test to bypass the loop entirely,
4426 or otherwise drop straight in, based on this test, then
4427 we might want to rewrite it also. This way some later
4428 pass has more hope of removing the initialization of this
4429 biv entirely. */
4431 /* If final_value != 0, then the biv may be used after loop end
4432 and we must emit an insn to set it just in case.
4434 Reversed bivs already have an insn after the loop setting their
4435 value, so we don't need another one. We can't calculate the
4436 proper final value for such a biv here anyways. */
4444 }
4445 }
4447 /* Go through all the instructions in the loop, making all the
4448 register substitutions scheduled in REG_MAP. */
4453 {
4457 }
4460 {
4461 /* When we completely unroll a loop we will likely not need the increment
4462 of the loop BIV and we will not need the conditional branch at the
4463 end of the loop. */
4466 #ifdef HAVE_cc0
4467 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
4468 need the comparison before the conditional branch at the end of the
4469 loop. */
4471 #endif
4473 /* We'll need one copy for each loop iteration. */
4476 /* A little slop to account for the ability to remove initialization
4477 code, better CSE, and other secondary benefits of completely
4478 unrolling some loops. */
4481 /* Clamp the value. */
4484 }
4486 /* Unroll loops from within strength reduction so that we can use the
4487 induction variable information that strength_reduce has already
4488 collected. Always unroll loops that would be as small or smaller
4489 unrolled than when rolled. */
4495 #ifdef HAVE_doloop_end
4506 }
4507 \f
4508 /*Record all basic induction variables calculated in the insn. */
4509 static rtx
4512 rtx p;
4515 {
4517 rtx set;
4518 rtx dest_reg;
4519 rtx inc_val;
4520 rtx mult_val;
4526 {
4531 {
4536 {
4537 /* It is a possible basic induction variable.
4538 Create and initialize an induction structure for it. */
4546 }
4549 }
4550 }
4552 }
4553 \f
4554 /* Record all givs calculated in the insn.
4555 A register is a giv if: it is only set once, it is a function of a
4556 biv and a constant (or invariant), and it is not a biv. */
4557 static rtx
4560 rtx p;
4563 {
4566 rtx set;
4567 /* Look for a general induction variable in a register. */
4572 {
4573 rtx src_reg;
4574 rtx dest_reg;
4575 rtx add_val;
4576 rtx mult_val;
4577 rtx ext_val;
4580 rtx last_consec_insn;
4589 /* Equivalent expression is a giv. */
4594 /* Don't try to handle any regs made by loop optimization.
4595 We have nothing on them in regno_first_uid, etc. */
4597 /* Don't recognize a BASIC_INDUCT_VAR here. */
4599 /* This must be the only place where the register is set. */
4601 /* or all sets must be consecutive and make a giv. */
4606 {
4610 /* If this is a library call, increase benefit. */
4614 /* Skip the consecutive insns, if there are any. */
4622 }
4623 }
4625 #ifndef DONT_REDUCE_ADDR
4626 /* Look for givs which are memory addresses. */
4627 /* This resulted in worse code on a VAX 8600. I wonder if it
4628 still does. */
4631 maybe_multiple);
4632 #endif
4634 /* Update the status of whether giv can derive other givs. This can
4635 change when we pass a label or an insn that updates a biv. */
4640 }
4641 \f
4642 /* Return 1 if X is a valid source for an initial value (or as value being
4643 compared against in an initial test).
4645 X must be either a register or constant and must not be clobbered between
4646 the current insn and the start of the loop.
4648 INSN is the insn containing X. */
4650 static int
4652 rtx x;
4653 rtx insn;
4655 rtx loop_start;
4656 {
4660 /* Only consider pseudos we know about initialized in insns whose luids
4661 we know. */
4666 /* Don't use call-clobbered registers across a call which clobbers it. On
4667 some machines, don't use any hard registers at all. */
4669 && (SMALL_REGISTER_CLASSES
4673 /* Don't use registers that have been clobbered before the start of the
4674 loop. */
4679 }
4680 \f
4681 /* Scan X for memory refs and check each memory address
4682 as a possible giv. INSN is the insn whose pattern X comes from.
4683 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
4684 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
4685 more thanonce in each loop iteration. */
4687 static void
4690 rtx x;
4691 rtx insn;
4693 {
4703 {
4719 {
4720 rtx src_reg;
4721 rtx add_val;
4722 rtx mult_val;
4723 rtx ext_val;
4726 /* This code used to disable creating GIVs with mult_val == 1 and
4727 add_val == 0. However, this leads to lost optimizations when
4728 it comes time to combine a set of related DEST_ADDR GIVs, since
4729 this one would not be seen. */
4734 {
4735 /* Found one; record it. */
4744 }
4745 }
4750 }
4752 /* Recursively scan the subexpressions for other mem refs. */
4758 maybe_multiple);
4762 maybe_multiple);
4763 }
4764 \f
4765 /* Fill in the data about one biv update.
4766 V is the `struct induction' in which we record the biv. (It is
4767 allocated by the caller, with alloca.)
4768 INSN is the insn that sets it.
4769 DEST_REG is the biv's reg.
4771 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
4772 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
4773 being set to INC_VAL.
4775 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
4776 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
4777 can be executed more than once per iteration. If MAYBE_MULTIPLE
4778 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
4779 executed exactly once per iteration. */
4781 static void
4786 rtx insn;
4787 rtx dest_reg;
4788 rtx inc_val;
4789 rtx mult_val;
4793 {
4809 /* Add this to the reg's iv_class, creating a class
4810 if this is the first incrementation of the reg. */
4814 {
4815 /* Create and initialize new iv_class. */
4825 /* Set initial value to the reg itself. */
4828 /* We haven't seen the initializing insn yet */
4838 /* Add this class to ivs->list. */
4842 /* Put it in the array of biv register classes. */
4844 }
4846 /* Update IV_CLASS entry for this biv. */
4855 }
4856 \f
4857 /* Fill in the data about one giv.
4858 V is the `struct induction' in which we record the giv. (It is
4859 allocated by the caller, with alloca.)
4860 INSN is the insn that sets it.
4861 BENEFIT estimates the savings from deleting this insn.
4862 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
4863 into a register or is used as a memory address.
4865 SRC_REG is the biv reg which the giv is computed from.
4866 DEST_REG is the giv's reg (if the giv is stored in a reg).
4867 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
4868 LOCATION points to the place where this giv's value appears in INSN. */
4870 static void
4875 rtx insn;
4876 rtx src_reg;
4877 rtx dest_reg;
4883 {
4888 rtx temp;
4890 /* Attempt to prove constantness of the values. */
4918 /* The v->always_computable field is used in update_giv_derive, to
4919 determine whether a giv can be used to derive another giv. For a
4920 DEST_REG giv, INSN computes a new value for the giv, so its value
4921 isn't computable if INSN insn't executed every iteration.
4922 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
4923 it does not compute a new value. Hence the value is always computable
4924 regardless of whether INSN is executed each iteration. */
4928 else
4934 {
4937 }
4939 {
4944 /* If the lifetime is zero, it means that this register is
4945 really a dead store. So mark this as a giv that can be
4946 ignored. This will not prevent the biv from being eliminated. */
4952 }
4954 /* Add the giv to the class of givs computed from one biv. */
4958 {
4961 /* Don't count DEST_ADDR. This is supposed to count the number of
4962 insns that calculate givs. */
4966 }
4967 else
4968 /* Fatal error, biv missing for this giv? */
4973 else
4974 {
4975 /* The giv can be replaced outright by the reduced register only if all
4976 of the following conditions are true:
4977 - the insn that sets the giv is always executed on any iteration
4978 on which the giv is used at all
4979 (there are two ways to deduce this:
4980 either the insn is executed on every iteration,
4981 or all uses follow that insn in the same basic block),
4982 - the giv is not used outside the loop
4983 - no assignments to the biv occur during the giv's lifetime. */
4986 /* Previous line always fails if INSN was moved by loop opt. */
4989 && (! not_every_iteration
4991 {
4992 /* Now check that there are no assignments to the biv within the
4993 giv's lifetime. This requires two separate checks. */
4995 /* Check each biv update, and fail if any are between the first
4996 and last use of the giv.
4998 If this loop contains an inner loop that was unrolled, then
4999 the insn modifying the biv may have been emitted by the loop
5000 unrolling code, and hence does not have a valid luid. Just
5001 mark the biv as not replaceable in this case. It is not very
5002 useful as a biv, because it is used in two different loops.
5003 It is very unlikely that we would be able to optimize the giv
5004 using this biv anyways. */
5008 {
5014 {
5018 }
5019 }
5021 /* If there are any backwards branches that go from after the
5022 biv update to before it, then this giv is not replaceable. */
5026 {
5030 }
5031 }
5032 else
5033 {
5034 /* May still be replaceable, we don't have enough info here to
5035 decide. */
5038 }
5039 }
5041 /* Record whether the add_val contains a const_int, for later use by
5042 combine_givs. */
5043 {
5048 ;
5052 {
5054 {
5059 else
5061 }
5064 }
5065 }
5069 }
5071 /* All this does is determine whether a giv can be made replaceable because
5072 its final value can be calculated. This code can not be part of record_giv
5073 above, because final_giv_value requires that the number of loop iterations
5074 be known, and that can not be accurately calculated until after all givs
5075 have been identified. */
5077 static void
5081 {
5088 /* DEST_ADDR givs will never reach here, because they are always marked
5089 replaceable above in record_giv. */
5091 /* The giv can be replaced outright by the reduced register only if all
5092 of the following conditions are true:
5093 - the insn that sets the giv is always executed on any iteration
5094 on which the giv is used at all
5095 (there are two ways to deduce this:
5096 either the insn is executed on every iteration,
5097 or all uses follow that insn in the same basic block),
5098 - its final value can be calculated (this condition is different
5099 than the one above in record_giv)
5100 - it's not used before the it's set
5101 - no assignments to the biv occur during the giv's lifetime. */
5103 #if 0
5104 /* This is only called now when replaceable is known to be false. */
5105 /* Clear replaceable, so that it won't confuse final_giv_value. */
5107 #endif
5111 {
5114 rtx last_giv_use;
5118 /* When trying to determine whether or not a biv increment occurs
5119 during the lifetime of the giv, we can ignore uses of the variable
5120 outside the loop because final_value is true. Hence we can not
5121 use regno_last_uid and regno_first_uid as above in record_giv. */
5123 /* Search the loop to determine whether any assignments to the
5124 biv occur during the giv's lifetime. Start with the insn
5125 that sets the giv, and search around the loop until we come
5126 back to that insn again.
5128 Also fail if there is a jump within the giv's lifetime that jumps
5129 to somewhere outside the lifetime but still within the loop. This
5130 catches spaghetti code where the execution order is not linear, and
5131 hence the above test fails. Here we assume that the giv lifetime
5132 does not extend from one iteration of the loop to the next, so as
5133 to make the test easier. Since the lifetime isn't known yet,
5134 this requires two loops. See also record_giv above. */
5139 {
5142 {
5145 }
5151 {
5152 /* It is possible for the BIV increment to use the GIV if we
5153 have a cycle. Thus we must be sure to check each insn for
5154 both BIV and GIV uses, and we must check for BIV uses
5155 first. */
5162 {
5164 {
5168 }
5170 }
5171 }
5172 }
5174 /* Now that the lifetime of the giv is known, check for branches
5175 from within the lifetime to outside the lifetime if it is still
5176 replaceable. */
5179 {
5182 {
5195 {
5204 }
5205 }
5206 }
5208 /* If it is replaceable, then save the final value. */
5211 }
5216 }
5217 \f
5218 /* Update the status of whether a giv can derive other givs.
5220 We need to do something special if there is or may be an update to the biv
5221 between the time the giv is defined and the time it is used to derive
5222 another giv.
5224 In addition, a giv that is only conditionally set is not allowed to
5225 derive another giv once a label has been passed.
5227 The cases we look at are when a label or an update to a biv is passed. */
5229 static void
5232 rtx p;
5233 {
5237 rtx tem;
5240 /* Search all IV classes, then all bivs, and finally all givs.
5242 There are three cases we are concerned with. First we have the situation
5243 of a giv that is only updated conditionally. In that case, it may not
5244 derive any givs after a label is passed.
5246 The second case is when a biv update occurs, or may occur, after the
5247 definition of a giv. For certain biv updates (see below) that are
5248 known to occur between the giv definition and use, we can adjust the
5249 giv definition. For others, or when the biv update is conditional,
5250 we must prevent the giv from deriving any other givs. There are two
5251 sub-cases within this case.
5253 If this is a label, we are concerned with any biv update that is done
5254 conditionally, since it may be done after the giv is defined followed by
5255 a branch here (actually, we need to pass both a jump and a label, but
5256 this extra tracking doesn't seem worth it).
5258 If this is a jump, we are concerned about any biv update that may be
5259 executed multiple times. We are actually only concerned about
5260 backward jumps, but it is probably not worth performing the test
5261 on the jump again here.
5263 If this is a biv update, we must adjust the giv status to show that a
5264 subsequent biv update was performed. If this adjustment cannot be done,
5265 the giv cannot derive further givs. */
5271 {
5273 {
5274 /* If cant_derive is already true, there is no point in
5275 checking all of these conditions again. */
5279 /* If this giv is conditionally set and we have passed a label,
5280 it cannot derive anything. */
5284 /* Skip givs that have mult_val == 0, since
5285 they are really invariants. Also skip those that are
5286 replaceable, since we know their lifetime doesn't contain
5287 any biv update. */
5291 /* The only way we can allow this giv to derive another
5292 is if this is a biv increment and we can form the product
5293 of biv->add_val and giv->mult_val. In this case, we will
5294 be able to compute a compensation. */
5296 {
5297 rtx ext_val_dummy;
5308 tem = simplify_giv_expr
5315 else
5317 }
5321 }
5322 }
5323 }
5324 \f
5325 /* Check whether an insn is an increment legitimate for a basic induction var.
5326 X is the source of insn P, or a part of it.
5327 MODE is the mode in which X should be interpreted.
5329 DEST_REG is the putative biv, also the destination of the insn.
5330 We accept patterns of these forms:
5331 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
5332 REG = INVARIANT + REG
5334 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
5335 store the additive term into *INC_VAL, and store the place where
5336 we found the additive term into *LOCATION.
5338 If X is an assignment of an invariant into DEST_REG, we set
5339 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
5341 We also want to detect a BIV when it corresponds to a variable
5342 whose mode was promoted via PROMOTED_MODE. In that case, an increment
5343 of the variable may be a PLUS that adds a SUBREG of that variable to
5344 an invariant and then sign- or zero-extends the result of the PLUS
5345 into the variable.
5347 Most GIVs in such cases will be in the promoted mode, since that is the
5348 probably the natural computation mode (and almost certainly the mode
5349 used for addresses) on the machine. So we view the pseudo-reg containing
5350 the variable as the BIV, as if it were simply incremented.
5352 Note that treating the entire pseudo as a BIV will result in making
5353 simple increments to any GIVs based on it. However, if the variable
5354 overflows in its declared mode but not its promoted mode, the result will
5355 be incorrect. This is acceptable if the variable is signed, since
5356 overflows in such cases are undefined, but not if it is unsigned, since
5357 those overflows are defined. So we only check for SIGN_EXTEND and
5358 not ZERO_EXTEND.
5360 If we cannot find a biv, we return 0. */
5362 static int
5367 rtx dest_reg;
5368 rtx p;
5372 {
5380 {
5386 {
5388 }
5393 {
5395 }
5396 else
5409 /* If this is a SUBREG for a promoted variable, check the inner
5410 value. */
5418 /* If this register is assigned in a previous insn, look at its
5419 source, but don't go outside the loop or past a label. */
5421 /* If this sets a register to itself, we would repeat any previous
5422 biv increment if we applied this strategy blindly. */
5428 {
5429 rtx dest;
5430 do
5431 {
5433 }
5462 }
5463 /* Fall through. */
5465 /* Can accept constant setting of biv only when inside inner most loop.
5466 Otherwise, a biv of an inner loop may be incorrectly recognized
5467 as a biv of the outer loop,
5468 causing code to be moved INTO the inner loop. */
5475 /* convert_modes aborts if we try to convert to or from CCmode, so just
5476 exclude that case. It is very unlikely that a condition code value
5477 would be a useful iterator anyways. */
5481 {
5482 /* Possible bug here? Perhaps we don't know the mode of X. */
5486 }
5487 else
5495 /* Similar, since this can be a sign extension. */
5500 ;
5514 location);
5519 }
5520 }
5521 \f
5522 /* A general induction variable (giv) is any quantity that is a linear
5523 function of a basic induction variable,
5524 i.e. giv = biv * mult_val + add_val.
5525 The coefficients can be any loop invariant quantity.
5526 A giv need not be computed directly from the biv;
5527 it can be computed by way of other givs. */
5529 /* Determine whether X computes a giv.
5530 If it does, return a nonzero value
5531 which is the benefit from eliminating the computation of X;
5532 set *SRC_REG to the register of the biv that it is computed from;
5533 set *ADD_VAL and *MULT_VAL to the coefficients,
5534 such that the value of X is biv * mult + add; */
5536 static int
5540 rtx x;
5548 {
5552 /* If this is an invariant, forget it, it isn't a giv. */
5563 {
5566 /* Since this is now an invariant and wasn't before, it must be a giv
5567 with MULT_VAL == 0. It doesn't matter which BIV we associate this
5568 with. */
5575 /* This is equivalent to a BIV. */
5582 /* Either (plus (biv) (invar)) or
5583 (plus (mult (biv) (invar_1)) (invar_2)). */
5585 {
5588 }
5589 else
5590 {
5593 }
5598 /* ADD_VAL is zero. */
5606 }
5608 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
5609 unless they are CONST_INT). */
5617 else
5620 /* Always return true if this is a giv so it will be detected as such,
5621 even if the benefit is zero or negative. This allows elimination
5622 of bivs that might otherwise not be eliminated. */
5624 }
5625 \f
5626 /* Given an expression, X, try to form it as a linear function of a biv.
5627 We will canonicalize it to be of the form
5628 (plus (mult (BIV) (invar_1))
5629 (invar_2))
5630 with possible degeneracies.
5632 The invariant expressions must each be of a form that can be used as a
5633 machine operand. We surround then with a USE rtx (a hack, but localized
5634 and certainly unambiguous!) if not a CONST_INT for simplicity in this
5635 routine; it is the caller's responsibility to strip them.
5637 If no such canonicalization is possible (i.e., two biv's are used or an
5638 expression that is neither invariant nor a biv or giv), this routine
5639 returns 0.
5641 For a non-zero return, the result will have a code of CONST_INT, USE,
5642 REG (for a BIV), PLUS, or MULT. No other codes will occur.
5644 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
5649 static rtx
5652 rtx x;
5655 {
5660 rtx tem;
5662 /* If this is not an integer mode, or if we cannot do arithmetic in this
5663 mode, this can't be a giv. */
5670 {
5677 /* Put constant last, CONST_INT last if both constant. */
5685 /* Handle addition of zero, then addition of an invariant. */
5690 {
5693 /* Adding two invariants must result in an invariant, so enclose
5694 addition operation inside a USE and return it. */
5704 else
5713 /* biv + invar or mult + invar. Return sum. */
5717 /* (a + invar_1) + invar_2. Associate. */
5718 return
5724 arg1)),
5729 }
5731 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
5732 MULT to reduce cases. */
5738 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
5739 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
5740 Recurse to associate the second PLUS. */
5745 return
5753 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
5769 /* Handle "a - b" as "a + b * (-1)". */
5775 constm1_rtx)),
5784 /* Put constant last, CONST_INT last if both constant. */
5789 /* If second argument is not now constant, not giv. */
5793 /* Handle multiply by 0 or 1. */
5801 {
5803 /* biv * invar. Done. */
5807 /* Product of two constants. */
5811 /* invar * invar is a giv, but attempt to simplify it somehow. */
5817 {
5818 /* (invar_0 * invar_1) * invar_2. Associate. */
5825 arg1)),
5827 }
5828 /* Porpagate the MULT expressions to the intermost nodes. */
5830 {
5831 /* (invar_0 + invar_1) * invar_2. Distribute. */
5837 arg1),
5841 arg1)),
5843 }
5847 /* (a * invar_1) * invar_2. Associate. */
5853 arg1)),
5857 /* (a + invar_1) * invar_2. Distribute. */
5862 arg1),
5865 arg1)),
5870 }
5873 /* Shift by constant is multiply by power of two. */
5877 return
5886 /* "-a" is "a * (-1)" */
5892 /* "~a" is "-a - 1". Silly, but easy. */
5896 const1_rtx),
5900 /* Already in proper form for invariant. */
5906 /* Conditionally recognize extensions of simple IVs. After we've
5907 computed loop traversal counts and verified the range of the
5908 source IV, we'll reevaluate this as a GIV. */
5910 {
5913 {
5916 }
5917 }
5921 /* If this is a new register, we can't deal with it. */
5925 /* Check for biv or giv. */
5927 {
5931 {
5934 /* Form expression from giv and add benefit. Ensure this giv
5935 can derive another and subtract any needed adjustment if so. */
5937 /* Increasing the benefit here is risky. The only case in which it
5938 is arguably correct is if this is the only use of V. In other
5939 cases, this will artificially inflate the benefit of the current
5940 giv, and lead to suboptimal code. Thus, it is disabled, since
5941 potentially not reducing an only marginally beneficial giv is
5942 less harmful than reducing many givs that are not really
5943 beneficial. */
5944 {
5948 }
5961 {
5964 }
5965 else
5966 {
5969 }
5971 }
5974 do_default:
5975 /* If it isn't an induction variable, and it is invariant, we
5976 may be able to simplify things further by looking through
5977 the bits we just moved outside the loop. */
5979 {
5985 {
5986 /* Ok, we found a match. Substitute and simplify. */
5988 /* If we match another movable, we must use that, as
5989 this one is going away. */
5994 /* If consec is non-zero, this is a member of a group of
5995 instructions that were moved together. We handle this
5996 case only to the point of seeking to the last insn and
5997 looking for a REG_EQUAL. Fail if we don't find one. */
5999 {
6002 do
6003 {
6005 }
6011 }
6012 else
6013 {
6017 }
6020 {
6021 /* What we are most interested in is pointer
6022 arithmetic on invariants -- only take
6023 patterns we may be able to do something with. */
6029 {
6031 benefit);
6034 }
6039 {
6044 }
6045 }
6047 }
6048 }
6050 }
6052 /* Fall through to general case. */
6054 /* If invariant, return as USE (unless CONST_INT).
6055 Otherwise, not giv. */
6060 {
6069 }
6070 else
6072 }
6073 }
6075 /* This routine folds invariants such that there is only ever one
6076 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6078 static rtx
6081 {
6087 {
6090 }
6093 {
6096 }
6097 else
6098 {
6101 }
6102 }
6104 static rtx
6108 {
6110 {
6114 else
6117 }
6120 else
6123 }
6124 \f
6125 /* Help detect a giv that is calculated by several consecutive insns;
6126 for example,
6127 giv = biv * M
6128 giv = giv + A
6129 The caller has already identified the first insn P as having a giv as dest;
6130 we check that all other insns that set the same register follow
6131 immediately after P, that they alter nothing else,
6132 and that the result of the last is still a giv.
6134 The value is 0 if the reg set in P is not really a giv.
6135 Otherwise, the value is the amount gained by eliminating
6136 all the consecutive insns that compute the value.
6138 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6139 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6141 The coefficients of the ultimate giv value are stored in
6142 *MULT_VAL and *ADD_VAL. */
6144 static int
6149 rtx p;
6150 rtx src_reg;
6151 rtx dest_reg;
6156 {
6162 rtx temp;
6163 rtx set;
6165 /* Indicate that this is a giv so that we can update the value produced in
6166 each insn of the multi-insn sequence.
6168 This induction structure will be used only by the call to
6169 general_induction_var below, so we can allocate it on our stack.
6170 If this is a giv, our caller will replace the induct var entry with
6171 a new induction structure. */
6192 {
6196 /* If libcall, skip to end of call sequence. */
6207 /* Giv created by equivalent expression. */
6213 {
6217 count--;
6221 }
6223 {
6224 /* Allow insns that set something other than this giv to a
6225 constant. Such insns are needed on machines which cannot
6226 include long constants and should not disqualify a giv. */
6235 }
6236 }
6241 }
6242 \f
6243 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6244 represented by G1. If no such expression can be found, or it is clear that
6245 it cannot possibly be a valid address, 0 is returned.
6247 To perform the computation, we note that
6248 G1 = x * v + a and
6249 G2 = y * v + b
6250 where `v' is the biv.
6252 So G2 = (y/b) * G1 + (b - a*y/x).
6254 Note that MULT = y/x.
6256 Update: A and B are now allowed to be additive expressions such that
6257 B contains all variables in A. That is, computing B-A will not require
6258 subtracting variables. */
6260 static rtx
6263 {
6264 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
6269 /* If MULT is not 1, we cannot handle A with non-constants, since we
6270 would then be required to subtract multiples of the registers in A.
6271 This is theoretically possible, and may even apply to some Fortran
6272 constructs, but it is a lot of work and we do not attempt it here. */
6277 /* In general these structures are sorted top to bottom (down the PLUS
6278 chain), but not left to right across the PLUS. If B is a higher
6279 order giv than A, we can strip one level and recurse. If A is higher
6280 order, we'll eventually bail out, but won't know that until the end.
6281 If they are the same, we'll strip one level around this loop. */
6284 {
6296 /* We matched: remove one reg completely. */
6299 /* An alternate match. */
6302 /* An alternate match. */
6304 else
6305 {
6306 /* Indicates an extra register in B. Strip one level from B and
6307 recurse, hoping B was the higher order expression. */
6312 }
6313 }
6315 /* Here we are at the last level of A, go through the cases hoping to
6316 get rid of everything but a constant. */
6319 {
6332 }
6334 {
6336 }
6338 {
6339 return simplify_gen_binary (MINUS, GET_MODE (b) != VOIDmode ? GET_MODE (b) : GET_MODE (a), const0_rtx, a);
6340 }
6342 {
6347 else
6349 }
6354 }
6356 rtx
6359 {
6362 /* The value that G1 will be multiplied by must be a constant integer. Also,
6363 the only chance we have of getting a valid address is if b*c/a (see above
6364 for notation) is also an integer. */
6367 {
6372 }
6375 else
6376 {
6377 /* ??? Find out if the one is a multiple of the other? */
6379 }
6383 {
6384 /* Failed. If we've got a multiplication factor between G1 and G2,
6385 scale G1's addend and try again. */
6387 {
6391 {
6392 HOST_WIDE_INT m;
6396 }
6397 else
6398 {
6400 mult);
6401 }
6404 }
6405 }
6409 /* Form simplified final result. */
6414 else
6419 else
6420 {
6423 {
6427 }
6430 }
6431 }
6432 \f
6433 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6434 represented by G1. This indicates that G2 should be combined with G1 and
6435 that G2 can use (either directly or via an address expression) a register
6436 used to represent G1. */
6438 static rtx
6441 {
6444 /* With the introduction of ext dependant givs, we must care for modes.
6445 G2 must not use a wider mode than G1. */
6455 /* If these givs are identical, they can be combined. We use the results
6456 of express_from because the addends are not in a canonical form, so
6457 rtx_equal_p is a weaker test. */
6458 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
6459 combination to be the other way round. */
6462 {
6464 }
6466 /* If G2 can be expressed as a function of G1 and that function is valid
6467 as an address and no more expensive than using a register for G2,
6468 the expression of G2 in terms of G1 can be used. */
6472 /* ??? Looses, especially with -fforce-addr, where *g2->location
6473 will always be a register, and so anything more complicated
6474 gets discarded. */
6475 #if 0
6476 #ifdef ADDRESS_COST
6478 #else
6480 #endif
6481 #endif
6482 )
6483 {
6485 }
6488 }
6489 \f
6490 /* Check each extension dependant giv in this class to see if its
6491 root biv is safe from wrapping in the interior mode, which would
6492 make the giv illegal. */
6494 static void
6498 {
6501 HOST_WIDE_INT start_val;
6507 /* Make sure the iteration data is available. We must have
6508 constants in order to be certain of no overflow. */
6509 /* ??? An unknown iteration count with an increment of +-1
6510 combined with friendly exit tests of against an invariant
6511 value is also ameanable to optimization. Not implemented. */
6517 /* Make sure the host can represent the arithmetic. */
6519 {
6521 HOST_WIDE_INT s_end_val;
6533 /* Check for host arithmatic overflow. */
6535 {
6537 HOST_WIDE_INT s_max;
6544 /* Check zero extension of biv ok. */
6546 /* Check for host arithmatic overflow. */
6547 && (neg_incr
6550 /* Check for target arithmetic overflow. */
6551 && (neg_incr
6554 {
6556 }
6558 /* Check sign extension of biv ok. */
6559 /* ??? While it is true that overflow with signed and pointer
6560 arithmetic is undefined, I fear too many programmers don't
6561 keep this fact in mind -- myself included on occasion.
6562 So leave alone with the signed overflow optimizations. */
6564 /* Check for host arithmatic overflow. */
6565 && (neg_incr
6568 /* Check for target arithmetic overflow. */
6569 && (neg_incr
6572 {
6574 }
6575 }
6576 }
6578 /* Invalidate givs that fail the tests. */
6581 {
6586 {
6595 /* We don't know whether this value is being used as either
6596 signed or unsigned, so to safely truncate we must satisfy
6597 both. The initial check here verifies the BIV itself;
6598 once that is successful we may check its range wrt the
6599 derived GIV. */
6601 {
6605 /* We know from the above that both endpoints are nonnegative,
6606 and that there is no wrapping. Verify that both endpoints
6607 are within the (signed) range of the outer mode. */
6610 }
6615 }
6618 {
6620 {
6624 }
6625 }
6626 else
6627 {
6629 {
6634 else
6635 {
6640 else
6642 }
6647 }
6649 }
6650 }
6651 }
6653 /* Generate a version of VALUE in a mode appropriate for initializing V. */
6655 rtx
6658 rtx value;
6659 {
6665 /* Recall that check_ext_dependant_givs verified that the known bounds
6666 of a biv did not overflow or wrap with respect to the extension for
6667 the giv. Therefore, constants need no additional adjustment. */
6671 /* Otherwise, we must adjust the value to compensate for the
6672 differing modes of the biv and the giv. */
6674 }
6675 \f
6676 struct combine_givs_stats
6677 {
6680 };
6682 static int
6686 {
6693 /* Stabilize the sort. */
6697 }
6699 /* Check all pairs of givs for iv_class BL and see if any can be combined with
6700 any other. If so, point SAME to the giv combined with and set NEW_REG to
6701 be an expression (in terms of the other giv's DEST_REG) equivalent to the
6702 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
6704 static void
6708 {
6709 /* Additional benefit to add for being combined multiple times. */
6717 /* Count givs, because bl->giv_count is incorrect here. */
6721 giv_count++;
6723 giv_array
6734 {
6736 rtx single_use;
6741 /* If a DEST_REG GIV is used only once, do not allow it to combine
6742 with anything, for in doing so we will gain nothing that cannot
6743 be had by simply letting the GIV with which we would have combined
6744 to be reduced on its own. The losage shows up in particular with
6745 DEST_ADDR targets on hosts with reg+reg addressing, though it can
6746 be seen elsewhere as well. */
6753 /* Add an additional weight for zero addends. */
6758 {
6759 rtx this_combine;
6764 {
6767 }
6768 }
6770 }
6772 /* Iterate, combining until we can't. */
6773 restart:
6777 {
6780 {
6786 }
6788 }
6791 {
6797 /* If it has already been combined, skip. */
6802 {
6805 /* If it has already been combined, skip. */
6807 {
6817 /* ??? The new final_[bg]iv_value code does a much better job
6818 of finding replaceable giv's, and hence this code may no
6819 longer be necessary. */
6823 /* To help optimize the next set of combinations, remove
6824 this giv from the benefits of other potential mates. */
6826 {
6830 }
6837 }
6838 }
6840 /* To help optimize the next set of combinations, remove
6841 this giv from the benefits of other potential mates. */
6843 {
6845 {
6849 }
6853 /* We've finished with this giv, and everything it touched.
6854 Restart the combination so that proper weights for the
6855 rest of the givs are properly taken into account. */
6856 /* ??? Ideally we would compact the arrays at this point, so
6857 as to not cover old ground. But sanely compacting
6858 can_combine is tricky. */
6860 }
6861 }
6863 /* Clean up. */
6866 }
6867 \f
6868 /* Generate sequence for REG = B * M + A. */
6870 static rtx
6876 {
6877 rtx seq;
6878 rtx result;
6881 /* Use unsigned arithmetic. */
6889 }
6892 /* Update registers created in insn sequence SEQ. */
6894 static void
6897 rtx seq;
6898 {
6899 /* Update register info for alias analysis. */
6902 {
6905 {
6909 }
6910 }
6911 else
6912 {
6916 }
6917 }
6920 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
6922 void
6929 basic_block before_bb;
6930 rtx before_insn;
6931 {
6932 rtx seq;
6935 {
6938 }
6940 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
6943 /* Increase the lifetime of any invariants moved further in code. */
6950 /* It is possible that the expansion created lots of new registers.
6951 Iterate over the sequence we just created and record them all. */
6953 }
6956 /* Emit insns in loop pre-header to set REG = B * M + A. */
6958 void
6965 {
6966 rtx seq;
6968 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
6971 /* Increase the lifetime of any invariants moved further in code.
6972 ???? Is this really necessary? */
6979 /* It is possible that the expansion created lots of new registers.
6980 Iterate over the sequence we just created and record them all. */
6982 }
6985 /* Emit insns after loop to set REG = B * M + A. */
6987 void
6994 {
6995 rtx seq;
6997 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7002 /* It is possible that the expansion created lots of new registers.
7003 Iterate over the sequence we just created and record them all. */
7005 }
7009 /* Similar to gen_add_mult, but compute cost rather than generating
7010 sequence. */
7012 static int
7018 {
7028 {
7033 }
7036 }
7037 \f
7038 /* Test whether A * B can be computed without
7039 an actual multiply insn. Value is 1 if so. */
7041 static int
7043 rtx a;
7044 rtx b;
7045 {
7047 rtx tmp;
7050 /* If only one is constant, make it B. */
7054 /* If first constant, both constant, so don't need multiply. */
7058 /* If second not constant, neither is constant, so would need multiply. */
7062 /* One operand is constant, so might not need multiply insn. Generate the
7063 code for the multiply and see if a call or multiply, or long sequence
7064 of insns is generated. */
7072 {
7077 else
7079 {
7088 {
7091 }
7092 }
7093 }
7103 }
7104 \f
7105 /* Check to see if loop can be terminated by a "decrement and branch until
7106 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7107 Also try reversing an increment loop to a decrement loop
7108 to see if the optimization can be performed.
7109 Value is nonzero if optimization was performed. */
7111 /* This is useful even if the architecture doesn't have such an insn,
7112 because it might change a loops which increments from 0 to n to a loop
7113 which decrements from n to 0. A loop that decrements to zero is usually
7114 faster than one that increments from zero. */
7116 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7117 such as approx_final_value, biv_total_increment, loop_iterations, and
7118 final_[bg]iv_value. */
7120 static int
7124 {
7129 rtx reg;
7130 rtx jump_label;
7131 rtx final_value;
7132 rtx start_value;
7133 rtx new_add_val;
7134 rtx comparison;
7135 rtx before_comparison;
7136 rtx p;
7137 rtx jump;
7138 rtx first_compare;
7143 /* If last insn is a conditional branch, and the insn before tests a
7144 register value, try to optimize it. Otherwise, we can't do anything. */
7153 /* Try to compute whether the compare/branch at the loop end is one or
7154 two instructions. */
7160 else
7163 {
7164 /* If more than one condition is present to control the loop, then
7165 do not proceed, as this function does not know how to rewrite
7166 loop tests with more than one condition.
7168 Look backwards from the first insn in the last comparison
7169 sequence and see if we've got another comparison sequence. */
7171 rtx jump1;
7175 }
7177 /* Check all of the bivs to see if the compare uses one of them.
7178 Skip biv's set more than once because we can't guarantee that
7179 it will be zero on the last iteration. Also skip if the biv is
7180 used between its update and the test insn. */
7183 {
7188 first_compare))
7190 }
7195 /* Look for the case where the basic induction variable is always
7196 nonnegative, and equals zero on the last iteration.
7197 In this case, add a reg_note REG_NONNEG, which allows the
7198 m68k DBRA instruction to be used. */
7206 {
7207 /* Initial value must be greater than 0,
7208 init_val % -dec_value == 0 to ensure that it equals zero on
7209 the last iteration */
7215 {
7216 /* register always nonnegative, add REG_NOTE to branch */
7224 }
7226 /* If the decrement is 1 and the value was tested as >= 0 before
7227 the loop, then we can safely optimize. */
7229 {
7242 {
7250 }
7251 }
7252 }
7255 {
7256 /* Try to change inc to dec, so can apply above optimization. */
7257 /* Can do this if:
7258 all registers modified are induction variables or invariant,
7259 all memory references have non-overlapping addresses
7260 (obviously true if only one write)
7261 allow 2 insns for the compare/jump at the end of the loop. */
7262 /* Also, we must avoid any instructions which use both the reversed
7263 biv and another biv. Such instructions will fail if the loop is
7264 reversed. We meet this condition by requiring that either
7265 no_use_except_counting is true, or else that there is only
7266 one biv. */
7268 /* 1 if the iteration var is used only to count iterations. */
7270 /* 1 if the loop has no memory store, or it has a single memory store
7271 which is reversible. */
7275 {
7279 /* If there are no givs for this biv, and the only exit is the
7280 fall through at the end of the loop, then
7281 see if perhaps there are no uses except to count. */
7285 {
7290 /* An insn that sets the biv is okay. */
7291 ;
7295 {
7296 /* If either of these insns uses the biv and sets a pseudo
7297 that has more than one usage, then the biv has uses
7298 other than counting since it's used to derive a value
7299 that is used more than one time. */
7301 regs);
7303 {
7306 }
7307 }
7309 {
7312 }
7313 }
7315 /* A biv has uses besides counting if it is used to set another biv. */
7318 {
7321 }
7322 }
7325 /* No need to worry about MEMs. */
7326 ;
7328 {
7333 /* If the loop has a single store, and the destination address is
7334 invariant, then we can't reverse the loop, because this address
7335 might then have the wrong value at loop exit.
7336 This would work if the source was invariant also, however, in that
7337 case, the insn should have been moved out of the loop. */
7340 {
7343 /* If we could prove that each of the memory locations
7344 written to was different, then we could reverse the
7345 store -- but we don't presently have any way of
7346 knowing that. */
7349 /* If the store depends on a register that is set after the
7350 store, it depends on the initial value, and is thus not
7351 reversible. */
7353 {
7360 }
7361 }
7362 }
7363 else
7366 /* This code only acts for innermost loops. Also it simplifies
7367 the memory address check by only reversing loops with
7368 zero or one memory access.
7369 Two memory accesses could involve parts of the same array,
7370 and that can't be reversed.
7371 If the biv is used only for counting, than we don't need to worry
7372 about all these things. */
7377 && reversible_mem_store
7382 {
7383 rtx tem;
7385 /* Loop can be reversed. */
7389 /* Now check other conditions:
7391 The increment must be a constant, as must the initial value,
7392 and the comparison code must be LT.
7394 This test can probably be improved since +/- 1 in the constant
7395 can be obtained by changing LT to LE and vice versa; this is
7396 confusing. */
7399 /* for constants, LE gets turned into LT */
7403 {
7414 comparison_const_width
7416 else
7417 comparison_const_width
7421 comparison_sign_mask
7424 /* If the comparison value is not a loop invariant, then we
7425 can not reverse this loop.
7427 ??? If the insns which initialize the comparison value as
7428 a whole compute an invariant result, then we could move
7429 them out of the loop and proceed with loop reversal. */
7437 /* Normalize the initial value if it is an integer and
7438 has no other use except as a counter. This will allow
7439 a few more loops to be reversed. */
7443 {
7445 /* The code below requires comparison_val to be a multiple
7446 of add_val in order to do the loop reversal, so
7447 round up comparison_val to a multiple of add_val.
7448 Since comparison_value is constant, we know that the
7449 current comparison code is LT. */
7451 comparison_val
7453 /* We postpone overflow checks for COMPARISON_VAL here;
7454 even if there is an overflow, we might still be able to
7455 reverse the loop, if converting the loop exit test to
7456 NE is possible. */
7458 }
7460 /* First check if we can do a vanilla loop reversal. */
7462 /* If we have a decrement_and_branch_on_count,
7463 prefer the NE test, since this will allow that
7464 instruction to be generated. Note that we must
7465 use a vanilla loop reversal if the biv is used to
7466 calculate a giv or has a non-counting use. */
7467 #if ! defined (HAVE_decrement_and_branch_until_zero) \
7468 && defined (HAVE_decrement_and_branch_on_count)
7472 #endif
7474 /* Now do postponed overflow checks on COMPARISON_VAL. */
7477 {
7478 /* Register will always be nonnegative, with value
7479 0 on last iteration */
7483 }
7487 {
7490 }
7491 else
7497 /* If the initial value is not zero, or if the comparison
7498 value is not an exact multiple of the increment, then we
7499 can not reverse this loop. */
7502 {
7505 }
7506 else
7507 {
7510 }
7514 /* Reset these in case we normalized the initial value
7515 and comparison value above. */
7518 {
7520 final_value
7522 }
7525 /* Save some info needed to produce the new insns. */
7532 /* Set start_value; if this is not a CONST_INT, we need
7533 to generate a SUB.
7534 Initialize biv to start_value before loop start.
7535 The old initializing insn will be deleted as a
7536 dead store by flow.c. */
7539 {
7542 }
7544 {
7547 enum insn_code icode
7556 start_value
7563 }
7565 {
7567 enum insn_code icode
7575 start_value
7579 initial_value)));
7580 }
7581 else
7582 /* We could handle the other cases too, but it'll be
7583 better to have a testcase first. */
7586 /* We may not have a single insn which can increment a reg, so
7587 create a sequence to hold all the insns from expand_inc. */
7596 /* Update biv info to reflect its new status. */
7601 /* Update loop info. */
7610 /* Inc LABEL_NUSES so that delete_insn will
7611 not delete the label. */
7614 /* Emit an insn after the end of the loop to set the biv's
7615 proper exit value if it is used anywhere outside the loop. */
7621 /* Delete compare/branch at end of loop. */
7626 /* Add new compare/branch insn at end of loop. */
7638 ;
7644 {
7646 {
7647 /* Increment of LABEL_NUSES done above. */
7648 /* Register is now always nonnegative,
7649 so add REG_NONNEG note to the branch. */
7652 }
7654 }
7656 /* No insn may reference both the reversed and another biv or it
7657 will fail (see comment near the top of the loop reversal
7658 code).
7659 Earlier on, we have verified that the biv has no use except
7660 counting, or it is the only biv in this function.
7661 However, the code that computes no_use_except_counting does
7662 not verify reg notes. It's possible to have an insn that
7663 references another biv, and has a REG_EQUAL note with an
7664 expression based on the reversed biv. To avoid this case,
7665 remove all REG_EQUAL notes based on the reversed biv
7666 here. */
7669 {
7672 /* If this is a set of a GIV based on the reversed biv, any
7673 REG_EQUAL notes should still be correct. */
7680 {
7685 else
7687 }
7688 }
7690 /* Mark that this biv has been reversed. Each giv which depends
7691 on this biv, and which is also live past the end of the loop
7692 will have to be fixed up. */
7697 {
7701 else
7703 }
7706 }
7707 }
7708 }
7711 }
7712 \f
7713 /* Verify whether the biv BL appears to be eliminable,
7714 based on the insns in the loop that refer to it.
7716 If ELIMINATE_P is non-zero, actually do the elimination.
7718 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
7719 determine whether invariant insns should be placed inside or at the
7720 start of the loop. */
7722 static int
7728 {
7731 rtx p;
7733 /* Scan all insns in the loop, stopping if we find one that uses the
7734 biv in a way that we cannot eliminate. */
7737 {
7742 /* If this is a libcall that sets a giv, skip ahead to its end. */
7744 {
7748 {
7753 {
7760 }
7761 }
7762 }
7767 {
7773 }
7774 }
7777 {
7782 }
7785 }
7786 \f
7787 /* INSN and REFERENCE are instructions in the same insn chain.
7788 Return non-zero if INSN is first. */
7790 int
7793 {
7797 {
7798 /* Start with test for not first so that INSN == REFERENCE yields not
7799 first. */
7805 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
7806 previous insn, hence the <= comparison below does not work if
7807 P is a note. */
7818 }
7819 }
7821 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
7822 the offset that we have to take into account due to auto-increment /
7823 div derivation is zero. */
7824 static int
7827 rtx insn;
7828 {
7829 /* If the giv V had the auto-inc address optimization applied
7830 to it, and INSN occurs between the giv insn and the biv
7831 insn, then we'd have to adjust the value used here.
7832 This is rare, so we don't bother to make this possible. */
7841 }
7843 /* If BL appears in X (part of the pattern of INSN), see if we can
7844 eliminate its use. If so, return 1. If not, return 0.
7846 If BIV does not appear in X, return 1.
7848 If ELIMINATE_P is non-zero, actually do the elimination.
7849 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
7850 Depending on how many items have been moved out of the loop, it
7851 will either be before INSN (when WHERE_INSN is non-zero) or at the
7852 start of the loop (when WHERE_INSN is zero). */
7854 static int
7860 basic_block where_bb;
7861 rtx where_insn;
7862 {
7868 #ifdef HAVE_cc0
7870 #endif
7876 {
7878 /* If we haven't already been able to do something with this BIV,
7879 we can't eliminate it. */
7885 /* If this sets the BIV, it is not a problem. */
7889 /* If this is an insn that defines a giv, it is also ok because
7890 it will go away when the giv is reduced. */
7895 #ifdef HAVE_cc0
7897 {
7898 /* Can replace with any giv that was reduced and
7899 that has (MULT_VAL != 0) and (ADD_VAL == 0).
7900 Require a constant for MULT_VAL, so we know it's nonzero.
7901 ??? We disable this optimization to avoid potential
7902 overflows. */
7910 {
7917 /* If the giv has the opposite direction of change,
7918 then reverse the comparison. */
7922 else
7925 /* We can probably test that giv's reduced reg. */
7928 }
7930 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
7931 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
7932 Require a constant for MULT_VAL, so we know it's nonzero.
7933 ??? Do this only if ADD_VAL is a pointer to avoid a potential
7934 overflow problem. */
7946 {
7953 /* If the giv has the opposite direction of change,
7954 then reverse the comparison. */
7958 else
7962 /* Replace biv with the giv's reduced register. */
7967 /* Insn doesn't support that constant or invariant. Copy it
7968 into a register (it will be a loop invariant.) */
7975 /* Substitute the new register for its invariant value in
7976 the compare expression. */
7980 }
7981 }
7982 #endif
7989 /* See if either argument is the biv. */
7994 else
7998 {
7999 /* First try to replace with any giv that has constant positive
8000 mult_val and constant add_val. We might be able to support
8001 negative mult_val, but it seems complex to do it in general. */
8013 {
8020 /* Replace biv with the giv's reduced reg. */
8023 /* If all constants are actually constant integers and
8024 the derived constant can be directly placed in the COMPARE,
8025 do so. */
8029 {
8034 }
8035 else
8036 {
8037 /* Otherwise, load it into a register. */
8043 }
8046 }
8048 /* Look for giv with positive constant mult_val and nonconst add_val.
8049 Insert insns to calculate new compare value.
8050 ??? Turn this off due to possible overflow. */
8058 {
8059 rtx tem;
8069 /* Replace biv with giv's reduced register. */
8073 /* Compute value to compare against. */
8077 /* Use it in this insn. */
8081 }
8082 }
8084 {
8086 {
8087 /* Look for giv with constant positive mult_val and nonconst
8088 add_val. Insert insns to compute new compare value.
8089 ??? Turn this off due to possible overflow. */
8096 {
8097 rtx tem;
8107 /* Replace biv with giv's reduced register. */
8111 /* Compute value to compare against. */
8118 }
8119 }
8121 /* This code has problems. Basically, you can't know when
8122 seeing if we will eliminate BL, whether a particular giv
8123 of ARG will be reduced. If it isn't going to be reduced,
8124 we can't eliminate BL. We can try forcing it to be reduced,
8125 but that can generate poor code.
8127 The problem is that the benefit of reducing TV, below should
8128 be increased if BL can actually be eliminated, but this means
8129 we might have to do a topological sort of the order in which
8130 we try to process biv. It doesn't seem worthwhile to do
8131 this sort of thing now. */
8133 #if 0
8134 /* Otherwise the reg compared with had better be a biv. */
8139 /* Look for a pair of givs, one for each biv,
8140 with identical coefficients. */
8142 {
8154 {
8161 /* Replace biv with its giv's reduced reg. */
8163 /* Replace other operand with the other giv's
8164 reduced reg. */
8167 }
8168 }
8169 #endif
8170 }
8172 /* If we get here, the biv can't be eliminated. */
8176 /* If this address is a DEST_ADDR giv, it doesn't matter if the
8177 biv is used in it, since it will be replaced. */
8185 }
8187 /* See if any subexpression fails elimination. */
8190 {
8192 {
8205 }
8206 }
8209 }
8210 \f
8211 /* Return nonzero if the last use of REG
8212 is in an insn following INSN in the same basic block. */
8214 static int
8216 rtx reg;
8217 rtx insn;
8218 {
8219 rtx n;
8223 {
8226 }
8228 }
8229 \f
8230 /* Called via `note_stores' to record the initial value of a biv. Here we
8231 just record the location of the set and process it later. */
8233 static void
8235 rtx dest;
8236 rtx set;
8238 {
8249 /* If this is the first set found, record it. */
8251 {
8254 }
8255 }
8256 \f
8257 /* If any of the registers in X are "old" and currently have a last use earlier
8258 than INSN, update them to have a last use of INSN. Their actual last use
8259 will be the previous insn but it will not have a valid uid_luid so we can't
8260 use it. X must be a source expression only. */
8262 static void
8264 rtx x;
8265 rtx insn;
8266 {
8267 /* Check for the case where INSN does not have a valid luid. In this case,
8268 there is no need to modify the regno_last_uid, as this can only happen
8269 when code is inserted after the loop_end to set a pseudo's final value,
8270 and hence this insn will never be the last use of x.
8271 ???? This comment is not correct. See for example loop_givs_reduce.
8272 This may insert an insn before another new insn. */
8276 {
8278 }
8279 else
8280 {
8284 {
8290 }
8291 }
8292 }
8293 \f
8294 /* Given an insn INSN and condition COND, return the condition in a
8295 canonical form to simplify testing by callers. Specifically:
8297 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
8298 (2) Both operands will be machine operands; (cc0) will have been replaced.
8299 (3) If an operand is a constant, it will be the second operand.
8300 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
8301 for GE, GEU, and LEU.
8303 If the condition cannot be understood, or is an inequality floating-point
8304 comparison which needs to be reversed, 0 will be returned.
8306 If REVERSE is non-zero, then reverse the condition prior to canonizing it.
8308 If EARLIEST is non-zero, it is a pointer to a place where the earliest
8309 insn used in locating the condition was found. If a replacement test
8310 of the condition is desired, it should be placed in front of that
8311 insn and we will be sure that the inputs are still valid.
8313 If WANT_REG is non-zero, we wish the condition to be relative to that
8314 register, if possible. Therefore, do not canonicalize the condition
8315 further. */
8317 rtx
8319 rtx insn;
8320 rtx cond;
8323 rtx want_reg;
8324 {
8327 rtx set;
8328 rtx tem;
8340 {
8343 }
8348 /* If we are comparing a register with zero, see if the register is set
8349 in the previous insn to a COMPARE or a comparison operation. Perform
8350 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
8351 in cse.c */
8356 {
8357 /* Set non-zero when we find something of interest. */
8360 #ifdef HAVE_cc0
8361 /* If comparison with cc0, import actual comparison from compare
8362 insn. */
8364 {
8375 }
8376 #endif
8378 /* If this is a COMPARE, pick up the two things being compared. */
8380 {
8384 }
8388 /* Go back to the previous insn. Stop if it is not an INSN. We also
8389 stop if it isn't a single set or if it has a REG_INC note because
8390 we don't want to bother dealing with it. */
8398 /* If this is setting OP0, get what it sets it to if it looks
8399 relevant. */
8401 {
8404 /* ??? We may not combine comparisons done in a CCmode with
8405 comparisons not done in a CCmode. This is to aid targets
8406 like Alpha that have an IEEE compliant EQ instruction, and
8407 a non-IEEE compliant BEQ instruction. The use of CCmode is
8408 actually artificial, simply to prevent the combination, but
8409 should not affect other platforms.
8411 However, we must allow VOIDmode comparisons to match either
8412 CCmode or non-CCmode comparison, because some ports have
8413 modeless comparisons inside branch patterns.
8415 ??? This mode check should perhaps look more like the mode check
8416 in simplify_comparison in combine. */
8424 && (STORE_FLAG_VALUE
8427 #ifdef FLOAT_STORE_FLAG_VALUE
8430 && (REAL_VALUE_NEGATIVE
8432 #endif
8433 ))
8444 && (STORE_FLAG_VALUE
8447 #ifdef FLOAT_STORE_FLAG_VALUE
8450 && (REAL_VALUE_NEGATIVE
8452 #endif
8453 ))
8459 {
8460 /* We might have reversed a LT to get a GE here. But this wasn't
8461 actually the comparison of data, so we don't flag that we
8462 have had to reverse the condition. */
8466 }
8467 else
8469 }
8472 /* If this sets OP0, but not directly, we have to give up. */
8476 {
8480 {
8486 }
8491 }
8492 }
8494 /* If constant is first, put it last. */
8498 /* If OP0 is the result of a comparison, we weren't able to find what
8499 was really being compared, so fail. */
8503 /* Canonicalize any ordered comparison with integers involving equality
8504 if we can do computations in the relevant mode and we do not
8505 overflow. */
8510 {
8513 unsigned HOST_WIDE_INT max_val
8517 {
8523 /* When cross-compiling, const_val might be sign-extended from
8524 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
8544 }
8545 }
8547 /* If this was floating-point and we reversed anything other than an
8548 EQ or NE or (UN)ORDERED, return zero. */
8550 && did_reverse_condition
8552 && ! flag_fast_math
8556 #ifdef HAVE_cc0
8557 /* Never return CC0; return zero instead. */
8560 #endif
8563 }
8565 /* Given a jump insn JUMP, return the condition that will cause it to branch
8566 to its JUMP_LABEL. If the condition cannot be understood, or is an
8567 inequality floating-point comparison which needs to be reversed, 0 will
8568 be returned.
8570 If EARLIEST is non-zero, it is a pointer to a place where the earliest
8571 insn used in locating the condition was found. If a replacement test
8572 of the condition is desired, it should be placed in front of that
8573 insn and we will be sure that the inputs are still valid. */
8575 rtx
8577 rtx jump;
8579 {
8580 rtx cond;
8582 rtx set;
8584 /* If this is not a standard conditional jump, we can't parse it. */
8592 /* If this branches to JUMP_LABEL when the condition is false, reverse
8593 the condition. */
8594 reverse
8599 }
8601 /* Similar to above routine, except that we also put an invariant last
8602 unless both operands are invariants. */
8604 rtx
8607 rtx x;
8608 {
8618 }
8620 /* Scan the function and determine whether it has indirect (computed) jumps.
8622 This is taken mostly from flow.c; similar code exists elsewhere
8623 in the compiler. It may be useful to put this into rtlanal.c. */
8624 static int
8626 rtx start;
8627 {
8628 rtx insn;
8635 }
8637 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
8638 documentation for LOOP_MEMS for the definition of `appropriate'.
8639 This function is called from prescan_loop via for_each_rtx. */
8641 static int
8645 {
8654 {
8659 /* We're not interested in MEMs that are only clobbered. */
8663 /* We're not interested in the MEM associated with a
8664 CONST_DOUBLE, so there's no need to traverse into this. */
8668 /* We're not interested in any MEMs that only appear in notes. */
8672 /* This is not a MEM. */
8674 }
8676 /* See if we've already seen this MEM. */
8679 {
8681 /* The modes of the two memory accesses are different. If
8682 this happens, something tricky is going on, and we just
8683 don't optimize accesses to this MEM. */
8687 }
8689 /* Resize the array, if necessary. */
8691 {
8694 else
8700 }
8702 /* Actually insert the MEM. */
8704 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
8705 because we can't put it in a register. We still store it in the
8706 table, though, so that if we see the same address later, but in a
8707 non-BLK mode, we'll not think we can optimize it at that point. */
8713 }
8716 /* Allocate REGS->ARRAY or reallocate it if it is too small.
8718 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
8719 register that is modified by an insn between FROM and TO. If the
8720 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
8721 more, stop incrementing it, to avoid overflow.
8723 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
8724 register I is used, if it is only used once. Otherwise, it is set
8725 to 0 (for no uses) or const0_rtx for more than one use. This
8726 parameter may be zero, in which case this processing is not done.
8728 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
8729 optimize register I. */
8731 static void
8735 {
8738 /* last_set[n] is nonzero iff reg n has been set in the current
8739 basic block. In that case, it is the insn that last set reg n. */
8741 rtx insn;
8747 /* Grow the regs array if not allocated or too small. */
8749 {
8755 /* Zero the new elements. */
8758 }
8760 /* Clear previously scanned fields but do not clear n_times_set. */
8762 {
8766 }
8770 /* Scan the loop, recording register usage. */
8773 {
8775 {
8776 /* Record registers that have exactly one use. */
8779 /* Include uses in REG_EQUAL notes. */
8787 {
8791 last_set);
8792 }
8793 }
8797 }
8800 {
8803 }
8805 #ifdef AVOID_CCMODE_COPIES
8806 /* Don't try to move insns which set CC registers if we should not
8807 create CCmode register copies. */
8811 #endif
8813 /* Set regs->array[I].n_times_set for the new registers. */
8818 }
8820 /* Returns the number of real INSNs in the LOOP. */
8822 static int
8825 {
8827 rtx insn;
8835 }
8837 /* Move MEMs into registers for the duration of the loop. */
8839 static void
8842 {
8849 rtx end_label;
8850 /* Nonzero if the next instruction may never be executed. */
8857 /* We cannot use next_label here because it skips over normal insns. */
8862 /* Check to see if it's possible that some instructions in the loop are
8863 never executed. Also check if there is a goto out of the loop other
8864 than right after the end of the loop. */
8868 {
8872 /* If we enter the loop in the middle, and scan
8873 around to the beginning, don't set maybe_never
8874 for that. This must be an unconditional jump,
8875 otherwise the code at the top of the loop might
8876 never be executed. Unconditional jumps are
8877 followed a by barrier then loop end. */
8882 {
8883 /* If this is a jump outside of the loop but not right
8884 after the end of the loop, we would have to emit new fixup
8885 sequences for each such label. */
8887 JUMP_INSN is executed, we must be conservative. */
8896 /* Something complicated. */
8898 else
8899 /* If there are any more instructions in the loop, they
8900 might not be reached. */
8902 }
8905 }
8907 /* Find start of the extended basic block that enters the loop. */
8911 ;
8916 /* Build table of mems that get set to constant values before the
8917 loop. */
8921 /* Actually move the MEMs. */
8923 {
8924 regset_head load_copies;
8925 regset_head store_copies;
8927 rtx reg;
8929 rtx mem_list_entry;
8933 /* There's no telling whether or not MEM is modified. */
8936 /* Go through the MEMs written to in the loop to see if this
8937 one is aliased by one of them. */
8940 {
8945 {
8946 /* MEM is indeed aliased by this store. */
8949 }
8951 }
8957 /* If this MEM is written to, we must be sure that there
8958 are no reads from another MEM that aliases this one. */
8960 {
8964 {
8968 VOIDmode,
8970 rtx_varies_p))
8971 {
8972 /* It's not safe to hoist loop_info->mems[i] out of
8973 the loop because writes to it might not be
8974 seen by reads from loop_info->mems[j]. */
8977 }
8978 }
8979 }
8982 /* We can't access the MEM outside the loop; it might
8983 cause a trap that wouldn't have happened otherwise. */
8987 /* We thought we were going to lift this MEM out of the
8988 loop, but later discovered that we could not. */
8994 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
8995 order to keep scan_loop from moving stores to this MEM
8996 out of the loop just because this REG is neither a
8997 user-variable nor used in the loop test. */
9002 /* Now, replace all references to the MEM with the
9003 corresponding pseudos. */
9008 {
9010 {
9011 rtx set;
9015 /* See if this copies the mem into a register that isn't
9016 modified afterwards. We'll try to do copy propagation
9017 a little further on. */
9019 /* @@@ This test is _way_ too conservative. */
9020 && ! maybe_never
9028 /* See if this copies the mem from a register that isn't
9029 modified afterwards. We'll try to remove the
9030 redundant copy later on by doing a little register
9031 renaming and copy propagation. This will help
9032 to untangle things for the BIV detection code. */
9034 && ! maybe_never
9042 /* Replace the memory reference with the shadow register. */
9045 }
9050 }
9053 /* We couldn't replace all occurrences of the MEM. */
9055 else
9056 {
9057 /* Load the memory immediately before LOOP->START, which is
9058 the NOTE_LOOP_BEG. */
9060 rtx set;
9066 {
9070 {
9074 /* Extending hard register lifetimes causes crash
9075 on SRC targets. Doing so on non-SRC is
9076 probably also not good idea, since we most
9077 probably have pseudoregister equivalence as
9078 well. */
9081 }
9082 /* Use the constant equivalence if that is cheap enough. */
9088 {
9091 }
9093 /* If best_equiv is nonzero, we know that MEM is set to a
9094 constant or register before the loop. We will use this
9095 knowledge to initialize the shadow register with that
9096 constant or reg rather than by loading from MEM. */
9099 }
9104 {
9107 {
9110 }
9111 }
9119 {
9121 {
9124 }
9126 /* Store the memory immediately after END, which is
9127 the NOTE_LOOP_END. */
9130 }
9133 {
9138 }
9140 /* Attempt a bit of copy propagation. This helps untangle the
9141 data flow, and enables {basic,general}_induction_var to find
9142 more bivs/givs. */
9143 EXECUTE_IF_SET_IN_REG_SET
9145 {
9147 });
9150 EXECUTE_IF_SET_IN_REG_SET
9152 {
9154 });
9156 }
9157 }
9160 {
9161 /* Now, we need to replace all references to the previous exit
9162 label with the new one. */
9163 rtx_pair rr;
9168 {
9171 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
9172 field. This is not handled by for_each_rtx because it doesn't
9173 handle unprinted ('0') fields. We need to update JUMP_LABEL
9174 because the immediately following unroll pass will use it.
9175 replace_label would not work anyways, because that only handles
9176 LABEL_REFs. */
9179 }
9180 }
9183 }
9185 /* For communication between note_reg_stored and its caller. */
9186 struct note_reg_stored_arg
9187 {
9189 rtx reg;
9190 };
9192 /* Called via note_stores, record in SET_SEEN whether X, which is written,
9193 is equal to ARG. */
9194 static void
9198 {
9202 }
9204 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
9205 There must be exactly one insn that sets this pseudo; it will be
9206 deleted if all replacements succeed and we can prove that the register
9207 is not used after the loop. */
9209 static void
9212 rtx replacement;
9214 {
9215 /* This is the reg that we are copying from. */
9218 rtx insn;
9219 /* These help keep track of whether we replaced all uses of the reg. */
9226 {
9227 rtx set;
9229 /* Only substitute within one extended basic block from the initializing
9230 insn. */
9237 /* Is this the initializing insn? */
9242 {
9249 }
9251 /* Only substitute after seeing the initializing insn. */
9253 {
9260 /* Stop replacing when REPLACEMENT is modified. */
9266 }
9267 }
9271 {
9275 {
9276 rtx first;
9277 rtx retval_note;
9279 /* Assume we're just deleting INIT_INSN. */
9281 /* Look for REG_RETVAL note. If we're deleting the end of
9282 the libcall sequence, the whole sequence can go. */
9284 /* If we found a REG_RETVAL note, find the first instruction
9285 in the sequence. */
9289 /* Delete the instructions. */
9291 }
9294 }
9295 }
9297 /* Replace all the instructions from FIRST up to and including LAST
9298 with NOTE_INSN_DELETED notes. */
9300 static void
9302 rtx first;
9303 rtx last;
9304 {
9306 {
9313 /* If this was the LAST instructions we're supposed to delete,
9314 we're done. */
9319 }
9320 }
9322 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
9323 loop LOOP if the order of the sets of these registers can be
9324 swapped. There must be exactly one insn within the loop that sets
9325 this pseudo followed immediately by a move insn that sets
9326 REPLACEMENT with REGNO. */
9327 static void
9330 rtx replacement;
9332 {
9333 rtx insn;
9342 {
9343 /* Search for the insn that copies REGNO to NEW_REGNO? */
9351 }
9354 {
9355 rtx prev_insn;
9356 rtx prev_set;
9358 /* Some DEF-USE info would come in handy here to make this
9359 function more general. For now, just check the previous insn
9360 which is the most likely candidate for setting REGNO. */
9368 {
9369 /* We have:
9370 (set (reg regno) (expr))
9371 (set (reg new_regno) (reg regno))
9373 so try converting this to:
9374 (set (reg new_regno) (expr))
9375 (set (reg regno) (reg new_regno))
9377 The former construct is often generated when a global
9378 variable used for an induction variable is shadowed by a
9379 register (NEW_REGNO). The latter construct improves the
9380 chances of GIV replacement and BIV elimination. */
9390 {
9397 /* Update first use of REGNO. */
9401 /* Now perform copy propagation to hopefully
9402 remove all uses of REGNO within the loop. */
9404 }
9405 }
9406 }
9407 }
9409 /* Replace MEM with its associated pseudo register. This function is
9410 called from load_mems via for_each_rtx. DATA is actually a pointer
9411 to a structure describing the instruction currently being scanned
9412 and the MEM we are currently replacing. */
9414 static int
9418 {
9426 {
9431 /* We're not interested in the MEM associated with a
9432 CONST_DOUBLE, so there's no need to traverse into one. */
9436 /* This is not a MEM. */
9438 }
9441 /* This is not the MEM we are currently replacing. */
9444 /* Actually replace the MEM. */
9448 }
9450 static void
9452 rtx insn;
9453 rtx mem;
9454 rtx reg;
9455 {
9456 loop_replace_args args;
9463 }
9465 /* Replace one register with another. Called through for_each_rtx; PX points
9466 to the rtx being scanned. DATA is actually a pointer to
9467 a structure of arguments. */
9469 static int
9473 {
9484 }
9486 static void
9488 rtx insn;
9489 rtx reg;
9490 rtx replacement;
9491 {
9492 loop_replace_args args;
9499 }
9501 /* Replace occurrences of the old exit label for the loop with the new
9502 one. DATA is an rtx_pair containing the old and new labels,
9503 respectively. */
9505 static int
9509 {
9528 }
9529 \f
9530 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
9531 (ignored in the interim). */
9533 static rtx
9536 basic_block where_bb ATTRIBUTE_UNUSED;
9537 rtx where_insn;
9538 rtx pattern;
9539 {
9541 }
9544 /* If WHERE_INSN is non-zero emit insn for PATTERN before WHERE_INSN
9545 in basic block WHERE_BB (ignored in the interim) within the loop
9546 otherwise hoist PATTERN into the loop pre-header. */
9548 rtx
9551 basic_block where_bb ATTRIBUTE_UNUSED;
9552 rtx where_insn;
9553 rtx pattern;
9554 {
9558 }
9561 /* Emit call insn for PATTERN before WHERE_INSN in basic block
9562 WHERE_BB (ignored in the interim) within the loop. */
9564 static rtx
9567 basic_block where_bb ATTRIBUTE_UNUSED;
9568 rtx where_insn;
9569 rtx pattern;
9570 {
9572 }
9575 /* Hoist insn for PATTERN into the loop pre-header. */
9577 rtx
9580 rtx pattern;
9581 {
9583 }
9586 /* Hoist call insn for PATTERN into the loop pre-header. */
9588 static rtx
9591 rtx pattern;
9592 {
9594 }
9597 /* Sink insn for PATTERN after the loop end. */
9599 rtx
9602 rtx pattern;
9603 {
9605 }
9608 /* If the loop has multiple exits, emit insn for PATTERN before the
9609 loop to ensure that it will always be executed no matter how the
9610 loop exits. Otherwise, emit the insn for PATTERN after the loop,
9611 since this is slightly more efficient. */
9613 static rtx
9616 rtx pattern;
9617 {
9620 else
9622 }
9623 \f
9624 static void
9629 {
9637 iv_num++;
9642 {
9645 }
9646 }
9649 static void
9654 {
9656 rtx incr;
9667 {
9670 }
9672 {
9675 }
9679 {
9683 }
9686 {
9690 }
9692 /* List the increments. */
9694 {
9698 }
9700 /* List the givs. */
9702 {
9707 else
9710 }
9711 }
9714 static void
9719 {
9730 {
9734 }
9737 }
9740 static void
9745 {
9752 else
9768 {
9770 {
9782 }
9783 }
9794 {
9798 }
9801 }
9804 void
9807 {
9809 }
9812 void
9815 {
9817 }
9820 void
9823 {
9825 }
9828 void
9831 {
9833 }
9836 #define LOOP_BLOCK_NUM_1(INSN) \
9837 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
9839 /* The notes do not have an assigned block, so look at the next insn. */
9840 #define LOOP_BLOCK_NUM(INSN) \
9841 ((INSN) ? (GET_CODE (INSN) == NOTE \
9842 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
9843 : LOOP_BLOCK_NUM_1 (INSN)) \
9844 : -1)
9846 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
9848 static void
9853 {
9854 rtx label;
9859 /* Print diagnostics to compare our concept of a loop with
9860 what the loop notes say. */
9875 {
9895 {
9898 {
9901 }
9902 }
9905 /* This can happen when a marked loop appears as two nested loops,
9906 say from while (a || b) {}. The inner loop won't match
9907 the loop markers but the outer one will. */
9910 }
9911 }
9913 /* Call this function from the debugger to dump LOOP. */
9915 void
9918 {
9920 }
9922 /* Call this function from the debugger to dump LOOPS. */
9924 void
9927 {
9929 }