| blob | 501e874603c8e9d8779ffa65f4d020c2ce8a01d0 |
1 ;; Machine description for Visium.
2 ;; Copyright (C) 2002-2017 Free Software Foundation, Inc.
3 ;; Contributed by C.Nettleton, J.P.Parkes and P.Garbett.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;
22 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
23 ;;
24 ;; Extra register constraints are:
25 ;; 'b' EAM register mdb
26 ;; 'c' EAM register mdc
27 ;; 'f' Floating-point register
28 ;; 'k' Register that can be used as the target of a sibcall, i.e. call-used
29 ;; general register not clobbered in the epilogue: r1-r8 and r10
30 ;; 'l' Low general register, i.e. general register accessible in user mode
31 ;; on the GR6 and, consequently, that can be used as the target of a
32 ;; branch with prediction: r1-r28
33 ;; 't' Register r1
34 ;; 'u' Register r2
35 ;; 'v' Register r3
36 ;;
37 ;; Immediate integer operand constraints are:
38 ;; 'J' 0 .. 65535 (16-bit immediate)
39 ;; 'K' 1 .. 31 (5-bit immediate)
40 ;; 'L' -1 .. -65535 (16-bit negative immediate)
41 ;; 'M' -1 (minus one)
42 ;; 'O' 0 (integer zero)
43 ;; 'P' 32 (thirty two)
44 ;;
45 ;; Immediate FP operand constraints are:
46 ;; 'G' 0.0 (floating-point zero)
47 ;;
48 ;; Operand substitution characters are:
49 ;; %# delay slot follows, if empty, fill with NOP
50 ;; %b LS 8 bits of immediate operand
51 ;; %w LS 16 bits of immediate operand
52 ;; %u MS 16 bits of immediate operand
53 ;; %r register or zero (r0)
54 ;; %f FP register or zero (f0)
55 ;; %d second register in a pair
56 ;;
57 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
58 ;;
60 ;; Registers by name.
61 (define_constants [
62 (R_R1 1)
63 (R_R2 2)
64 (R_R3 3)
65 (R_R4 4)
66 (R_R5 5)
67 (R_R6 6)
68 (R_LINK 21)
69 (R_FP 22)
70 (R_SP 23)
71 (R_MDB 32)
72 (R_MDC 33)
73 (R_FLAGS 50)
74 ])
76 ;; UNSPEC usage.
77 (define_c_enum "unspec" [
78 UNSPEC_MDBHI
79 UNSPEC_FLOAD
80 UNSPEC_FSTORE
81 UNSPEC_ITOF
82 UNSPEC_FTOI
83 UNSPEC_NOP
84 UNSPEC_ADDV
85 UNSPEC_SUBV
86 UNSPEC_NEGV
87 ])
89 ;; UNSPEC_VOLATILE usage.
90 (define_c_enum "unspecv" [
91 UNSPECV_BLOCKAGE
92 UNSPECV_DSI
93 ])
95 (include "predicates.md")
96 (include "constraints.md")
98 ;;
99 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
100 ;;
101 ;; Attributes.
102 ;;
103 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
104 ;;
106 ; Instruction type.
107 ;
108 ;imm_reg Move of immediate value to register.
109 ;mem_reg Move from memory to register.
110 ;eam_reg Move from EAM to register.
111 ;fp_reg Move from FPU to register.
112 ;reg_mem Move from register to memory.
113 ;reg_eam Move from register to EAM.
114 ;reg_fp Move from register to FPU.
115 ;arith Arithmetic operation, result in register, sets overflow.
116 ;arith2 Two successive arithmetic operations.
117 ;logic Logical operation, result in register, does not set overflow.
118 ;abs_branch Absolute branch.
119 ;branch Branch.
120 ;bmi Block move.
121 ;call Call to subprogram.
122 ;ret Return from subprogram.
123 ;rfi Return from interrupt.
124 ;dsi Disable interrupts.
125 ;cmp Compare or test.
126 ;div EAM 32/32 division.
127 ;divd EAM 64/32 division.
128 ;mul EAM 32 * 32 -> 64 multiplication.
129 ;shiftdi EAM 64 bit shift.
130 ;fdiv Floating point divide.
131 ;fsqrt Floating point square root.
132 ;ftoi Fix float to integer.
133 ;itof Float integer.
134 ;fmove Floating point move w/ or w/o change of sign: fmove, fabs, fneg.
135 ;fcmp Floating point compare or test.
136 ;fp Other floating point operations.
137 ;nop No operation.
138 ;multi Multiple instructions which split.
139 ;asm User asm instructions.
140 ;trap Trap instructions.
142 (define_attr "type"
143 "imm_reg,mem_reg,eam_reg,fp_reg,reg_mem,reg_eam,reg_fp,arith,arith2,logic,abs_branch,branch,bmi,call,ret,rfi,dsi,cmp,div,divd,mul,shiftdi,fdiv,fsqrt,ftoi,itof,fmove,fcmp,fp,nop,multi,asm,trap" (const_string "logic"))
145 ; Those insns that occupy 4 bytes.
146 (define_attr "single_insn" "no,yes"
147 (if_then_else (eq_attr "type" "arith2,rfi,multi")
148 (const_string "no")
149 (const_string "yes")))
151 ; True if branch or call will be emitting a nop into its delay slot.
152 (define_attr "empty_delay_slot" "false,true"
153 (symbol_ref "(empty_delay_slot (insn)
154 ? EMPTY_DELAY_SLOT_TRUE : EMPTY_DELAY_SLOT_FALSE)"))
156 ; Length in bytes.
157 ; The allowed range for the offset of short branches is [-131072;131068]
158 ; and it is counted from the address of the insn so we need to subtract
159 ; 8 for forward branches because (pc) points to the next insn for them.
160 (define_attr "length" ""
161 (cond [(eq_attr "type" "abs_branch,call,ret")
162 (if_then_else (eq_attr "empty_delay_slot" "true")
163 (const_int 8)
164 (const_int 4))
165 (eq_attr "type" "branch")
166 (if_then_else (leu (plus (minus (match_dup 0) (pc))
167 (const_int 131060))
168 (const_int 262120))
169 (if_then_else (eq_attr "empty_delay_slot" "true")
170 (const_int 8)
171 (const_int 4))
172 (const_int 20))
173 (eq_attr "single_insn" "no")
174 (const_int 8)] (const_int 4)))
176 (define_asm_attributes [(set_attr "type" "asm")])
178 ; Delay slots.
179 (define_delay (eq_attr "type" "abs_branch,branch,call,ret")
180 [(and (eq_attr "type" "!abs_branch,branch,call,ret,rfi,bmi,mul,div,divd,fdiv,fsqrt,asm")
181 (eq_attr "single_insn" "yes"))
182 (nil) (nil)])
184 ;;
185 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
186 ;;
187 ;; Processor pipeline description.
188 ;;
189 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
190 ;;
192 ; Attribute for cpu type.
193 ; These must match the values for enum processor_type in visium-opts.h.
194 (define_attr "cpu" "gr5,gr6" (const (symbol_ref "visium_cpu_attr")))
196 (include "gr5.md")
197 (include "gr6.md")
199 ;;
200 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
201 ;;
202 ;; Iterators.
203 ;;
204 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
205 ;;
207 (define_mode_iterator QHI [QI HI])
208 (define_mode_iterator I [QI HI SI])
209 (define_mode_attr b [(QI "8") (HI "16") (SI "32")])
210 (define_mode_attr s [(QI ".b") (HI ".w") (SI ".l")])
212 ; This code iterator allows signed and unsigned widening multiplications
213 ; to use the same template.
214 (define_code_iterator any_extend [sign_extend zero_extend])
216 ; <u> expands to an empty string when doing a signed operation and
217 ; "u" when doing an unsigned operation.
218 (define_code_attr u [(sign_extend "") (zero_extend "u")])
220 ; <su> is like <u>, but the signed form expands to "s" rather than "".
221 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
223 ; This code iterator allows returns and simple returns to use the same template.
224 (define_code_iterator any_return [return simple_return])
225 (define_code_attr return_pred [(return "visium_can_use_return_insn_p ()")
226 (simple_return "!visium_interrupt_function_p ()")])
227 (define_code_attr return_str [(return "") (simple_return "simple_")])
229 ; This code iterator allows integer and FP cstores to use the same template.
230 (define_code_iterator any_scc [ltu lt])
231 (define_code_attr scc_str [(ltu "sltu") (lt "slt")])
233 ;This code iterator allows cstore splitters to use the same template.
234 (define_code_iterator any_add [plus minus])
235 (define_code_attr add_op [(plus "PLUS") (minus "MINUS")])
236 (define_code_attr add_str [(plus "plus") (minus "minus")])
238 ;;
239 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
240 ;;
241 ;; Substitutions.
242 ;;
243 ;; They are used to define the second instruction of the pairs required by
244 ;; the postreload compare elimination pass, with a first variant for the
245 ;; logical insns and a second variant for the arithmetic insns.
246 ;;
247 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
248 ;;
250 (define_subst "flags_subst_logic"
251 [(set (match_operand 0 "") (match_operand 1 ""))
252 (clobber (reg:CC R_FLAGS))]
253 ""
254 [(set (match_dup 0) (match_dup 1))
255 (set (reg:CC R_FLAGS)
256 (compare:CC (match_dup 1) (const_int 0)))])
258 (define_subst_attr "subst_logic" "flags_subst_logic" "_flags" "_set_flags")
260 (define_subst "flags_subst_arith"
261 [(set (match_operand 0 "") (match_operand 1 ""))
262 (clobber (reg:CC R_FLAGS))]
263 ""
264 [(set (match_dup 0) (match_dup 1))
265 (set (reg:CCNZ R_FLAGS)
266 (compare:CCNZ (match_dup 1) (const_int 0)))])
268 (define_subst_attr "subst_arith" "flags_subst_arith" "_flags" "_set_flags")
270 ;;
271 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
272 ;;
273 ;; QImode moves
274 ;;
275 ;; For moving among registers we use the move.b instruction. This is
276 ;; actually an OR instruction using an alias. For moving between register
277 ;; and memory we need the address of the memory location in a register.
278 ;; However, we can accept an expression (reg + offset) where offset is in
279 ;; the range 0 .. 31.
280 ;;
281 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
282 ;;
284 (define_expand "movqi"
285 [(set (match_operand:QI 0 "nonimmediate_operand" "")
286 (match_operand:QI 1 "general_operand" ""))]
287 ""
288 {
289 prepare_move_operands (operands, QImode);
290 })
292 (define_insn "*movqi_insn"
293 [(set (match_operand:QI 0 "nonimmediate_operand" "=r, m,?b,?c, r, r,r,r")
294 (match_operand:QI 1 "general_operand" " r,rO, r, r,?b,?c,i,m"))]
295 "ok_for_simple_move_operands (operands, QImode)"
296 "@
297 #
298 write.b %0,%r1
299 writemd %1,r0 ;movqi ?b r
300 writemdc %1 ;movqi ?c r
301 readmda %0 ;movqi r ?b
302 readmdc %0 ;movqi r ?c
303 moviq %0,%b1 ;movqi r i
304 read.b %0,%1"
305 [(set_attr "type" "logic,reg_mem,reg_eam,reg_eam,eam_reg,eam_reg,imm_reg,mem_reg")])
307 (define_insn "*movqi_insn<subst_logic>"
308 [(set (match_operand:QI 0 "gpc_reg_operand" "=r")
309 (match_operand:QI 1 "gpc_reg_operand" "r"))
310 (clobber (reg:CC R_FLAGS))]
311 "reload_completed"
312 "move.b %0,%1"
313 [(set_attr "type" "logic")])
315 (define_split
316 [(set (match_operand:QI 0 "gpc_reg_operand" "")
317 (match_operand:QI 1 "gpc_reg_operand" ""))]
318 "reload_completed"
319 [(parallel [(set (match_dup 0) (match_dup 1))
320 (clobber (reg:CC R_FLAGS))])]
321 "")
323 (define_expand "movstrictqi"
324 [(set (strict_low_part (match_operand:QI 0 "register_operand" ""))
325 (match_operand:QI 1 "general_operand" ""))]
326 "")
328 (define_insn "*movstrictqi_insn"
329 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r,r"))
330 (match_operand:QI 1 "general_operand" "rO,m"))]
331 "ok_for_simple_move_strict_operands (operands, QImode)"
332 "@
333 #
334 read.b %0,%1"
335 [(set_attr "type" "logic,mem_reg")])
337 (define_insn "*movstrictqi_insn<subst_logic>"
338 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
339 (match_operand:QI 1 "reg_or_0_operand" "rO"))
340 (clobber (reg:CC R_FLAGS))]
341 "reload_completed"
342 "move.b %0,%r1"
343 [(set_attr "type" "logic")])
345 (define_split
346 [(set (strict_low_part (match_operand:QI 0 "register_operand" ""))
347 (match_operand:QI 1 "reg_or_0_operand" ""))]
348 "reload_completed"
349 [(parallel [(set (strict_low_part (match_dup 0)) (match_dup 1))
350 (clobber (reg:CC R_FLAGS))])]
351 "")
353 ;;
354 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
355 ;;
356 ;; HImode moves
357 ;;
358 ;; For moving among registers we use the move.w instruction. This is
359 ;; actually an OR instruction using an alias. For moving between register
360 ;; and memory we need the address of the memory location in a register.
361 ;; However, we can accept an expression (reg + offset) where offset is in
362 ;; the range 0 .. 62 and is shifted right one place in the assembled
363 ;; instruction.
364 ;;
365 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
366 ;;
368 (define_expand "movhi"
369 [(set (match_operand:HI 0 "nonimmediate_operand" "")
370 (match_operand:HI 1 "general_operand" ""))]
371 ""
372 {
373 prepare_move_operands (operands, HImode);
374 })
376 (define_insn "*movhi_insn"
377 [(set (match_operand:HI 0 "nonimmediate_operand" "=r, m,?b,?c, r, r,r,r")
378 (match_operand:HI 1 "general_operand" " r,rO, r, r,?b,?c,i,m"))]
379 "ok_for_simple_move_operands (operands, HImode)"
380 "@
381 #
382 write.w %0,%r1
383 writemd %1,r0 ;movhi ?b r
384 writemdc %1 ;movhi ?c r
385 readmda %0 ;movhi r ?b
386 readmdc %0 ;movhi r ?c
387 moviq %0,%w1 ;movhi r i
388 read.w %0,%1"
389 [(set_attr "type" "logic,reg_mem,reg_eam,reg_eam,eam_reg,eam_reg,imm_reg,mem_reg")])
391 (define_insn "*movhi_insn<subst_logic>"
392 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
393 (match_operand:HI 1 "gpc_reg_operand" "r"))
394 (clobber (reg:CC R_FLAGS))]
395 "reload_completed"
396 "move.w %0,%1"
397 [(set_attr "type" "logic")])
399 (define_split
400 [(set (match_operand:HI 0 "gpc_reg_operand" "")
401 (match_operand:HI 1 "gpc_reg_operand" ""))]
402 "reload_completed"
403 [(parallel [(set (match_dup 0) (match_dup 1))
404 (clobber (reg:CC R_FLAGS))])]
405 "")
407 (define_expand "movstricthi"
408 [(set (strict_low_part (match_operand:HI 0 "register_operand" ""))
409 (match_operand:HI 1 "general_operand" ""))]
410 "")
412 (define_insn "*movstricthi_insn"
413 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r,r,r"))
414 (match_operand:HI 1 "general_operand" " r,i,m"))]
415 "ok_for_simple_move_strict_operands (operands, HImode)"
416 "@
417 #
418 movil %0,%w1
419 read.w %0,%1"
420 [(set_attr "type" "logic,imm_reg,mem_reg")])
422 (define_insn "*movstricthi_insn<subst_logic>"
423 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
424 (match_operand:HI 1 "register_operand" "r"))
425 (clobber (reg:CC R_FLAGS))]
426 "reload_completed"
427 "move.w %0,%1"
428 [(set_attr "type" "logic")])
430 (define_split
431 [(set (strict_low_part (match_operand:HI 0 "register_operand" ""))
432 (match_operand:HI 1 "register_operand" ""))]
433 "reload_completed"
434 [(parallel [(set (strict_low_part (match_dup 0)) (match_dup 1))
435 (clobber (reg:CC R_FLAGS))])]
436 "")
438 ;;
439 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
440 ;;
441 ;; SImode moves
442 ;;
443 ;; For moving among registers we use the move.l instruction. This is
444 ;; actually an OR instruction using an alias. For moving between register
445 ;; and memory we need the address of the memory location in a register.
446 ;; However, we can accept an expression (reg + offset) where offset is in
447 ;; the range 0 .. 124 and is shifted right two places in the assembled
448 ;; instruction.
449 ;;
450 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
451 ;;
453 (define_expand "movsi"
454 [(set (match_operand:SI 0 "nonimmediate_operand" "")
455 (match_operand:SI 1 "general_operand" ""))]
456 ""
457 {
458 prepare_move_operands (operands, SImode);
459 })
461 (define_insn "*movsi_high"
462 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
463 (high:SI (match_operand:SI 1 "immediate_operand" "n,i")) )]
464 ""
465 "@
466 moviu %0,%u1
467 moviu %0,%%u %a1"
468 [(set_attr "type" "imm_reg")])
470 ; We only care about the lower 16 bits of the constant
471 ; being inserted into the upper 16 bits of the register.
472 (define_insn "*moviu"
473 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
474 (const_int 16)
475 (const_int 0))
476 (match_operand:SI 1 "const_int_operand" "n"))]
477 ""
478 "moviu %0,%w1"
479 [(set_attr "type" "imm_reg")])
481 (define_insn "*movsi_losum"
482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
483 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
484 (match_operand:SI 2 "immediate_operand" "n,i")))]
485 ""
486 "@
487 movil %0,%w2
488 movil %0,%%l %a2"
489 [(set_attr "type" "imm_reg")])
491 (define_insn "*movil"
492 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
493 (const_int 16)
494 (const_int 16))
495 (match_operand:SI 1 "const_int_operand" "n"))]
496 ""
497 "movil %0,%w1"
498 [(set_attr "type" "imm_reg")])
500 (define_insn "*movsi_insn_no_ieee"
501 [(set (match_operand:SI 0 "nonimmediate_operand" "=r, m,?b,?c, r, r,r,r,r,r, r,!f")
502 (match_operand:SI 1 "general_operand" " r,rO, r, r,?b,?c,J,M,i,m,!f, r"))]
503 "!TARGET_FPU_IEEE && ok_for_simple_move_operands (operands, SImode)"
504 "@
505 #
506 write.l %0,%r1
507 writemd %1,r0 ;movsi ?b r
508 writemdc %1 ;movsi ?c r
509 readmda %0 ;movsi r ?b
510 readmdc %0 ;movsi r ?c
511 moviq %0,%1 ;movsi r J
512 #
513 # ;movsi r i
514 read.l %0,%1
515 fstore %0,%1
516 fload %0,%1"
517 [(set_attr "type" "logic,reg_mem,reg_eam,reg_eam,eam_reg,eam_reg,imm_reg,logic,multi,mem_reg,fp_reg,reg_fp")])
519 (define_insn "*movsi_insn"
520 [(set (match_operand:SI 0 "nonimmediate_operand" "=r, m,?b,?c, r, r,r,r,r,r, r,?f,f")
521 (match_operand:SI 1 "general_operand" " r,rO, r, r,?b,?c,J,M,i,m,?f, r,f"))]
522 "TARGET_FPU_IEEE && ok_for_simple_move_operands (operands, SImode)"
523 "@
524 #
525 write.l %0,%r1
526 writemd %1,r0 ;movsi ?b r
527 writemdc %1 ;movsi ?c r
528 readmda %0 ;movsi r ?b
529 readmdc %0 ;movsi r ?c
530 moviq %0,%1 ;movsi r J
531 #
532 # ;movsi r i
533 read.l %0,%1
534 fstore %0,%1
535 fload %0,%1
536 fmove %0,%1"
537 [(set_attr "type" "logic,reg_mem,reg_eam,reg_eam,eam_reg,eam_reg,imm_reg,logic,multi,mem_reg,fp_reg,reg_fp,fmove")])
539 (define_insn "*movsi_insn<subst_logic>"
540 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
541 (match_operand:SI 1 "gpc_reg_operand" "r"))
542 (clobber (reg:CC R_FLAGS))]
543 "reload_completed"
544 "move.l %0,%1"
545 [(set_attr "type" "logic")])
547 (define_insn "*movsi_insn_m1<subst_logic>"
548 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
549 (const_int -1))
550 (clobber (reg:CC R_FLAGS))]
551 "reload_completed"
552 "not.l %0,r0"
553 [(set_attr "type" "logic")])
555 (define_split
556 [(set (match_operand:SI 0 "gpc_reg_operand" "")
557 (match_operand:SI 1 "gpc_reg_operand" ""))]
558 "reload_completed"
559 [(parallel [(set (match_dup 0) (match_dup 1))
560 (clobber (reg:CC R_FLAGS))])]
561 "")
563 (define_split
564 [(set (match_operand:SI 0 "gpc_reg_operand" "")
565 (const_int -1))]
566 "reload_completed"
567 [(parallel [(set (match_dup 0) (const_int -1))
568 (clobber (reg:CC R_FLAGS))])]
569 "")
571 (define_insn "*movsi_mdbhi"
572 [(set (match_operand:SI 0 "register_operand" "=r")
573 (unspec:SI [(reg:DI R_MDB)] UNSPEC_MDBHI))]
574 ""
575 "readmdb %0"
576 [(set_attr "type" "eam_reg")])
578 (define_split
579 [(set (match_operand:SI 0 "gpc_reg_operand" "")
580 (match_operand:SI 1 "large_immediate_operand" ""))]
581 "reload_completed"
582 [(set (match_dup 0)
583 (high:SI (match_dup 1)) )
584 (set (match_dup 0)
585 (lo_sum:SI (match_dup 0) (match_dup 1)))]
586 "")
588 ;;
589 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
590 ;;
591 ;; DImode moves
592 ;;
593 ;; When the destination is the EAM register MDB, then we use the writemd
594 ;; instruction. In all other cases we split the move into two 32-bit moves.
595 ;;
596 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
597 ;;
599 (define_expand "movdi"
600 [(set (match_operand:DI 0 "nonimmediate_operand" "")
601 (match_operand:DI 1 "general_operand" ""))]
602 ""
603 {
604 prepare_move_operands (operands, DImode);
605 })
607 (define_insn "*movdi_insn"
608 [(set (match_operand:DI 0 "nonimmediate_operand" "= r, m, r,??b")
609 (match_operand:DI 1 "general_operand" "rim,rO,?b, r"))]
610 "ok_for_simple_move_operands (operands, DImode)"
611 "@
612 #
613 #
614 #
615 writemd %d1,%1 ;movdi ?b r"
616 [(set_attr "type" "multi,multi,multi,reg_eam")])
618 (define_split
619 [(set (match_operand:DI 0 "gpc_reg_operand" "") (reg:DI R_MDB))]
620 "reload_completed"
621 [(set (match_dup 1) (unspec:SI [(reg:DI R_MDB)] UNSPEC_MDBHI))
622 (set (match_dup 2) (reg:SI R_MDB))]
623 {
624 operands[1] = operand_subword (operands[0], 0, 1, DImode);
625 operands[2] = operand_subword (operands[0], 1, 1, DImode);
626 })
628 (define_split
629 [(set (match_operand:DI 0 "non_eam_dst_operand" "")
630 (match_operand:DI 1 "non_eam_src_operand" ""))]
631 "reload_completed"
632 [(set (match_dup 2) (match_dup 3))
633 (set (match_dup 4) (match_dup 5))]
634 {
635 visium_split_double_move (operands, DImode);
636 })
638 ;;
639 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
640 ;;
641 ;; SFmode moves
642 ;;
643 ;; Constants are constructed in a GP register and moved to the FP register.
644 ;;
645 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
646 ;;
648 (define_expand "movsf"
649 [(set (match_operand:SF 0 "nonimmediate_operand" "")
650 (match_operand:SF 1 "general_operand" ""))]
651 ""
652 {
653 prepare_move_operands (operands, SFmode);
654 })
656 (define_insn "*movsf_insn"
657 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,r,r, m,r,r,r")
658 (match_operand:SF 1 "general_operand" " f,G,r,f,r,rG,G,F,m"))]
659 "ok_for_simple_move_operands (operands, SFmode)"
660 "@
661 fmove %0,%1
662 fmove %0,f0
663 fload %0,%1
664 fstore %0,%1
665 #
666 write.l %0,%r1
667 moviq %0,0
668 #
669 read.l %0,%1"
670 [(set_attr "type" "fmove,fmove,reg_fp,fp_reg,logic,reg_mem,imm_reg,multi,mem_reg")])
672 (define_insn "*movsf_insn"
673 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
674 (match_operand:SF 1 "gpc_reg_operand" "r"))
675 (clobber (reg:CC R_FLAGS))]
676 "reload_completed"
677 "move.l %0,%1"
678 [(set_attr "type" "logic")])
680 (define_split
681 [(set (match_operand:SF 0 "gpc_reg_operand" "")
682 (match_operand:SF 1 "gpc_reg_operand" ""))]
683 "reload_completed"
684 [(parallel [(set (match_dup 0) (match_dup 1))
685 (clobber (reg:CC R_FLAGS))])]
686 "")
688 (define_split
689 [(set (match_operand:SF 0 "gpc_reg_operand" "")
690 (match_operand:SF 1 "const_double_operand" ""))]
691 "reload_completed"
692 [(set (match_dup 2) (match_dup 3))]
693 {
694 long l;
696 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands[1]), l);
698 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
699 operands[3] = GEN_INT (trunc_int_for_mode (l, SImode));
700 })
702 ;;
703 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
704 ;;
705 ;; DFmode moves
706 ;;
707 ;; We always split a DFmode move into two SImode moves.
708 ;;
709 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
710 ;;
712 (define_expand "movdf"
713 [(set (match_operand:DF 0 "nonimmediate_operand" "")
714 (match_operand:DF 1 "general_operand" ""))]
715 ""
716 {
717 prepare_move_operands (operands, DFmode);
718 })
720 (define_insn "*movdf_insn"
721 [(set (match_operand:DF 0 "nonimmediate_operand" "= r, m")
722 (match_operand:DF 1 "general_operand" "rFm,rG"))]
723 "ok_for_simple_move_operands (operands, DFmode)"
724 "#"
725 [(set_attr "type" "multi")])
727 (define_split
728 [(set (match_operand:DF 0 "nonimmediate_operand" "")
729 (match_operand:DF 1 "general_operand" ""))]
730 "reload_completed"
731 [(set (match_dup 2) (match_dup 3))
732 (set (match_dup 4) (match_dup 5))]
733 {
734 visium_split_double_move (operands, DFmode);
735 })
737 ;;
738 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
739 ;;
740 ;; Integer Add
741 ;;
742 ;; Modes QI, HI, SI and DI are supported directly.
743 ;;
744 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
745 ;;
747 (define_expand "add<mode>3"
748 [(set (match_operand:QHI 0 "register_operand" "")
749 (plus:QHI (match_operand:QHI 1 "register_operand" "")
750 (match_operand:QHI 2 "register_operand" "")))]
751 "")
753 (define_expand "uaddv<mode>4"
754 [(set (match_operand:I 0 "register_operand" "")
755 (plus:I (match_operand:I 1 "register_operand" "")
756 (match_operand:I 2 "register_operand" "")))
757 (set (pc)
758 (if_then_else (ltu (match_dup 0) (match_dup 1))
759 (label_ref (match_operand 3 ""))
760 (pc)))]
761 "")
763 (define_expand "addv<mode>4"
764 [(set (match_operand:I 0 "register_operand" "")
765 (plus:I (match_operand:I 1 "register_operand" "")
766 (match_operand:I 2 "register_operand" "")))
767 (set (pc)
768 (if_then_else (ne (match_dup 0)
769 (unspec:I [(match_dup 1) (match_dup 2)] UNSPEC_ADDV))
770 (label_ref (match_operand 3 ""))
771 (pc)))]
772 "")
774 (define_insn_and_split "*add<mode>3_insn"
775 [(set (match_operand:QHI 0 "register_operand" "=r")
776 (plus:QHI (match_operand:QHI 1 "register_operand" "%r")
777 (match_operand:QHI 2 "register_operand" "r")))]
778 "ok_for_simple_arith_logic_operands (operands, <MODE>mode)"
779 "#"
780 "reload_completed"
781 [(parallel [(set (match_dup 0)
782 (plus:QHI (match_dup 1) (match_dup 2)))
783 (clobber (reg:CC R_FLAGS))])]
784 ""
785 [(set_attr "type" "arith")])
787 (define_insn "*add<mode>3_insn<subst_arith>"
788 [(set (match_operand:QHI 0 "register_operand" "=r")
789 (plus:QHI (match_operand:QHI 1 "register_operand" "%r")
790 (match_operand:QHI 2 "register_operand" "r")))
791 (clobber (reg:CC R_FLAGS))]
792 "reload_completed"
793 "add<s> %0,%1,%2"
794 [(set_attr "type" "arith")])
796 (define_insn "*add<mode>3_insn_set_carry"
797 [(set (match_operand:QHI 0 "register_operand" "=r")
798 (plus:QHI (match_operand:QHI 1 "register_operand" "%r")
799 (match_operand:QHI 2 "register_operand" "r")))
800 (set (reg:CCC R_FLAGS)
801 (compare:CCC (plus:QHI (match_dup 1) (match_dup 2))
802 (match_dup 1)))]
803 "reload_completed"
804 "add<s> %0,%1,%2"
805 [(set_attr "type" "arith")])
807 (define_insn "*add<mode>3_insn_set_overflow"
808 [(set (match_operand:QHI 0 "register_operand" "=r")
809 (plus:QHI (match_operand:QHI 1 "register_operand" "%r")
810 (match_operand:QHI 2 "register_operand" "r")))
811 (set (reg:CCV R_FLAGS)
812 (compare:CCV (plus:QHI (match_dup 1) (match_dup 2))
813 (unspec:QHI [(match_dup 1) (match_dup 2)] UNSPEC_ADDV)))]
814 "reload_completed"
815 "add<s> %0,%1,%2"
816 [(set_attr "type" "arith")])
818 (define_expand "addsi3"
819 [(set (match_operand:SI 0 "register_operand" "")
820 (plus:SI (match_operand:SI 1 "register_operand" "")
821 (match_operand:SI 2 "add_operand" "")))]
822 "")
824 (define_expand "addsi3_flags"
825 [(parallel [(set (match_operand:SI 0 "register_operand" "")
826 (plus:SI (match_operand:SI 1 "register_operand" "")
827 (match_operand:SI 2 "add_operand" "")))
828 (clobber (reg:CC R_FLAGS))])]
829 "reload_completed"
830 "")
832 (define_insn_and_split "*addsi3_insn"
833 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
834 (plus:SI (match_operand:SI 1 "register_operand" "%0,r,0")
835 (match_operand:SI 2 "add_operand" " L,r,J")))]
836 "ok_for_simple_arith_logic_operands (operands, SImode)"
837 "#"
838 "reload_completed"
839 [(parallel [(set (match_dup 0)
840 (plus:SI (match_dup 1) (match_dup 2)))
841 (clobber (reg:CC R_FLAGS))])]
842 ""
843 [(set_attr "type" "arith")])
845 ; Favour the addition of small negative constants, since they are
846 ; expensive to load into a register.
848 (define_insn "*addsi3_insn<subst_arith>"
849 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
850 (plus:SI (match_operand:SI 1 "register_operand" "%0,r,0")
851 (match_operand:SI 2 "add_operand" " L,r,J")))
852 (clobber (reg:CC R_FLAGS))]
853 "reload_completed"
854 "@
855 subi %0,%n2
856 add.l %0,%1,%2
857 addi %0,%2"
858 [(set_attr "type" "arith")])
860 (define_insn "addsi3_insn_set_carry"
861 [(set (match_operand:SI 0 "register_operand" "=r,r")
862 (plus:SI (match_operand:SI 1 "register_operand" "%r,0")
863 (match_operand:SI 2 "real_add_operand" " r,J")))
864 (set (reg:CCC R_FLAGS)
865 (compare:CCC (plus:SI (match_dup 1) (match_dup 2))
866 (match_dup 1)))]
867 "reload_completed"
868 "@
869 add.l %0,%1,%2
870 addi %0,%2"
871 [(set_attr "type" "arith")])
873 (define_insn "*addsi3_insn_set_overflow"
874 [(set (match_operand:SI 0 "register_operand" "=r,r")
875 (plus:SI (match_operand:SI 1 "register_operand" "%r,0")
876 (match_operand:SI 2 "real_add_operand" " r,J")))
877 (set (reg:CCV R_FLAGS)
878 (compare:CCV (plus:SI (match_dup 1) (match_dup 2))
879 (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_ADDV)))]
880 "reload_completed"
881 "@
882 add.l %0,%1,%2
883 addi %0,%2"
884 [(set_attr "type" "arith")])
886 (define_expand "adddi3"
887 [(set (match_operand:DI 0 "register_operand" "")
888 (plus:DI (match_operand:DI 1 "register_operand" "")
889 (match_operand:DI 2 "add_operand" "")))]
890 "")
892 ; Disfavour the use of add.l because of the early clobber.
894 (define_insn_and_split "*addi3_insn"
895 [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
896 (plus:DI (match_operand:DI 1 "register_operand" "%0,0, r")
897 (match_operand:DI 2 "add_operand" " L,J, r")))]
898 "ok_for_simple_arith_logic_operands (operands, DImode)"
899 "#"
900 "reload_completed"
901 [(const_int 0)]
902 {
903 visium_split_double_add (PLUS, operands[0], operands[1], operands[2]);
904 DONE;
905 }
906 [(set_attr "type" "arith2")])
908 ;;
909 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
910 ;;
911 ;; Integer Add with Carry
912 ;;
913 ;; Only SI mode is supported.
914 ;;
915 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
916 ;;
918 (define_insn "*<scc_str><subst_arith>"
919 [(set (match_operand:SI 0 "register_operand" "=r")
920 (any_scc:SI (reg R_FLAGS) (const_int 0)))
921 (clobber (reg:CC R_FLAGS))]
922 "reload_completed"
923 "adc.l %0,r0,r0"
924 [(set_attr "type" "arith")])
926 (define_insn "*plus_<scc_str><subst_arith>"
927 [(set (match_operand:SI 0 "register_operand" "=r")
928 (plus:SI (match_operand:SI 1 "register_operand" "r")
929 (any_scc:SI (reg R_FLAGS) (const_int 0))))
930 (clobber (reg:CC R_FLAGS))]
931 "reload_completed"
932 "adc.l %0,%1,r0"
933 [(set_attr "type" "arith")])
935 (define_insn "*plus_plus_sltu<subst_arith>"
936 [(set (match_operand:SI 0 "register_operand" "=r")
937 (plus:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
938 (match_operand:SI 2 "register_operand" "r"))
939 (ltu:SI (reg R_FLAGS) (const_int 0))))
940 (clobber (reg:CC R_FLAGS))]
941 "reload_completed"
942 "adc.l %0,%1,%2"
943 [(set_attr "type" "arith")])
945 ;;
946 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
947 ;;
948 ;; Integer Subtract
949 ;;
950 ;; Modes QI, HI, SI and DI are supported directly.
951 ;;
952 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
953 ;;
955 (define_expand "sub<mode>3"
956 [(set (match_operand:QHI 0 "register_operand" "")
957 (minus:QHI (match_operand:QHI 1 "reg_or_0_operand" "")
958 (match_operand:QHI 2 "register_operand" "")))]
959 "")
961 (define_expand "usubv<mode>4"
962 [(set (match_operand:I 0 "register_operand" "")
963 (minus:I (match_operand:I 1 "reg_or_0_operand" "")
964 (match_operand:I 2 "register_operand" "")))
965 (set (pc)
966 (if_then_else (ltu (match_dup 1) (match_dup 2))
967 (label_ref (match_operand 3 ""))
968 (pc)))]
969 ""
970 {
971 if (operands[1] == const0_rtx)
972 {
973 emit_insn (gen_unegv<mode>3 (operands[0], operands[2], operands[3]));
974 DONE;
975 }
976 })
978 (define_expand "subv<mode>4"
979 [(set (match_operand:I 0 "register_operand" "")
980 (minus:I (match_operand:I 1 "register_operand" "")
981 (match_operand:I 2 "register_operand" "")))
982 (set (pc)
983 (if_then_else (ne (match_dup 0)
984 (unspec:I [(match_dup 1) (match_dup 2)] UNSPEC_SUBV))
985 (label_ref (match_operand 3 ""))
986 (pc)))]
987 "")
989 (define_insn_and_split "*sub<mode>3_insn"
990 [(set (match_operand:QHI 0 "register_operand" "=r")
991 (minus:QHI (match_operand:QHI 1 "reg_or_0_operand" "rO")
992 (match_operand:QHI 2 "register_operand" "r")))]
993 "ok_for_simple_arith_logic_operands (operands, <MODE>mode)"
994 "#"
995 "reload_completed"
996 [(parallel [(set (match_dup 0)
997 (minus:QHI (match_dup 1) (match_dup 2)))
998 (clobber (reg:CC R_FLAGS))])]
999 ""
1000 [(set_attr "type" "arith")])
1002 (define_insn "*sub<mode>3_insn<subst_arith>"
1003 [(set (match_operand:QHI 0 "register_operand" "=r")
1004 (minus:QHI (match_operand:QHI 1 "reg_or_0_operand" "rO")
1005 (match_operand:QHI 2 "register_operand" "r")))
1006 (clobber (reg:CC R_FLAGS))]
1007 "reload_completed"
1008 "sub<s> %0,%r1,%2"
1009 [(set_attr "type" "arith")])
1011 (define_insn "*sub<mode>3_insn_set_carry"
1012 [(set (match_operand:QHI 0 "register_operand" "=r")
1013 (minus:QHI (match_operand:QHI 1 "reg_or_0_operand" "rO")
1014 (match_operand:QHI 2 "register_operand" "r")))
1015 (set (reg:CC R_FLAGS)
1016 (compare:CC (match_dup 1) (match_dup 2)))]
1017 "reload_completed"
1018 "sub<s> %0,%r1,%2"
1019 [(set_attr "type" "arith")])
1021 (define_insn "*sub<mode>3_insn_set_overflow"
1022 [(set (match_operand:QHI 0 "register_operand" "=r")
1023 (minus:QHI (match_operand:QHI 1 "reg_or_0_operand" "rO")
1024 (match_operand:QHI 2 "register_operand" "r")))
1025 (set (reg:CCV R_FLAGS)
1026 (compare:CCV (minus:QHI (match_dup 1) (match_dup 2))
1027 (unspec:QHI [(match_dup 1) (match_dup 2)] UNSPEC_SUBV)))]
1028 "reload_completed"
1029 "sub<s> %0,%r1,%2"
1030 [(set_attr "type" "arith")])
1032 (define_expand "subsi3"
1033 [(set (match_operand:SI 0 "register_operand" "")
1034 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
1035 (match_operand:SI 2 "add_operand" "")))]
1036 "")
1038 (define_expand "subsi3_flags"
1039 [(parallel [(set (match_operand:SI 0 "register_operand" "")
1040 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
1041 (match_operand:SI 2 "add_operand" "")))
1042 (clobber (reg:CC R_FLAGS))])]
1043 "reload_completed"
1044 "")
1046 (define_insn_and_split "*subsi3_insn"
1047 [(set (match_operand:SI 0 "register_operand" "=r,r, r")
1048 (minus:SI (match_operand:SI 1 "reg_or_0_operand" " 0,rO,0")
1049 (match_operand:SI 2 "add_operand" " L,r, J")))]
1050 "ok_for_simple_arith_logic_operands (operands, SImode)"
1051 "#"
1052 "reload_completed"
1053 [(parallel [(set (match_dup 0)
1054 (minus:SI (match_dup 1) (match_dup 2)))
1055 (clobber (reg:CC R_FLAGS))])]
1056 ""
1057 [(set_attr "type" "arith")])
1059 ; Favour the subtraction of small negative constants, since they are
1060 ; expensive to load into a register.
1062 (define_insn "*subsi3_insn<subst_arith>"
1063 [(set (match_operand:SI 0 "register_operand" "=r,r, r")
1064 (minus:SI (match_operand:SI 1 "reg_or_0_operand" " 0,rO,0")
1065 (match_operand:SI 2 "add_operand" " L,r, J")))
1066 (clobber (reg:CC R_FLAGS))]
1067 "reload_completed"
1068 "@
1069 addi %0,%n2
1070 sub.l %0,%r1,%2
1071 subi %0,%2"
1072 [(set_attr "type" "arith")])
1074 (define_insn "subsi3_insn_set_carry"
1075 [(set (match_operand:SI 0 "register_operand" "=r,r")
1076 (minus:SI (match_operand:SI 1 "register_operand" " r,0")
1077 (match_operand:SI 2 "real_add_operand" " r,J")))
1078 (set (reg:CC R_FLAGS)
1079 (compare:CC (match_dup 1) (match_dup 2)))]
1080 "reload_completed"
1081 "@
1082 sub.l %0,%r1,%2
1083 subi %0,%2"
1084 [(set_attr "type" "arith")])
1086 (define_insn "*subsi3_insn_set_overflow"
1087 [(set (match_operand:SI 0 "register_operand" "=r,r")
1088 (minus:SI (match_operand:SI 1 "register_operand" " r,0")
1089 (match_operand:SI 2 "real_add_operand" " r,J")))
1090 (set (reg:CCV R_FLAGS)
1091 (compare:CCV (minus:SI (match_dup 1) (match_dup 2))
1092 (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_SUBV)))]
1093 "reload_completed"
1094 "@
1095 sub.l %0,%1,%2
1096 subi %0,%2"
1097 [(set_attr "type" "arith")])
1099 (define_expand "subdi3"
1100 [(set (match_operand:DI 0 "register_operand" "")
1101 (minus:DI (match_operand:DI 1 "register_operand" "")
1102 (match_operand:DI 2 "add_operand" "")))]
1103 "")
1105 ; Disfavour the use of the sub.l because of the early clobber.
1107 (define_insn_and_split "*subdi3_insn"
1108 [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
1109 (minus:DI (match_operand:DI 1 "register_operand" " 0,0, r")
1110 (match_operand:DI 2 "add_operand" " L,J, r")))]
1111 "ok_for_simple_arith_logic_operands (operands, DImode)"
1112 "#"
1113 "reload_completed"
1114 [(const_int 0)]
1115 {
1116 visium_split_double_add (MINUS, operands[0], operands[1], operands[2]);
1117 DONE;
1118 }
1119 [(set_attr "type" "arith2")])
1121 ;;
1122 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1123 ;;
1124 ;; Integer Subtract with Carry
1125 ;;
1126 ;; Only SI mode is supported.
1127 ;;
1128 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1129 ;;
1131 (define_insn "*neg_<scc_str><subst_arith>"
1132 [(set (match_operand:SI 0 "register_operand" "=r")
1133 (neg:SI (any_scc:SI (reg R_FLAGS) (const_int 0))))
1134 (clobber (reg:CC R_FLAGS))]
1135 "reload_completed"
1136 "subc.l %0,r0,r0"
1137 [(set_attr "type" "arith")])
1139 (define_insn "*minus_<scc_str><subst_arith>"
1140 [(set (match_operand:SI 0 "register_operand" "=r")
1141 (minus:SI (match_operand:SI 1 "register_operand" "r")
1142 (any_scc:SI (reg R_FLAGS) (const_int 0))))
1143 (clobber (reg:CC R_FLAGS))]
1144 "reload_completed"
1145 "subc.l %0,%1,r0"
1146 [(set_attr "type" "arith")])
1148 (define_insn "*minus_minus_sltu<subst_arith>"
1149 [(set (match_operand:SI 0 "register_operand" "=r")
1150 (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
1151 (match_operand:SI 2 "register_operand" "r"))
1152 (ltu:SI (reg R_FLAGS) (const_int 0))))
1153 (clobber (reg:CC R_FLAGS))]
1154 "reload_completed"
1155 "subc.l %0,%r1,%2"
1156 [(set_attr "type" "arith")])
1158 ;;
1159 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1160 ;;
1161 ;; Integer Negate
1162 ;;
1163 ;; Modes QI, HI, SI and DI are supported directly.
1164 ;;
1165 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1166 ;;
1168 (define_expand "neg<mode>2"
1169 [(set (match_operand:I 0 "register_operand" "")
1170 (neg:I (match_operand:I 1 "register_operand" "")))]
1171 "")
1173 (define_expand "unegv<mode>3"
1174 [(set (match_operand:I 0 "register_operand" "")
1175 (neg:I (match_operand:I 1 "register_operand" "")))
1176 (set (pc)
1177 (if_then_else (ne (match_dup 0) (const_int 0))
1178 (label_ref (match_operand 2 ""))
1179 (pc)))]
1180 "")
1182 (define_expand "negv<mode>3"
1183 [(set (match_operand:I 0 "register_operand" "")
1184 (neg:I (match_operand:I 1 "register_operand" "")))
1185 (set (pc)
1186 (if_then_else (ne (match_dup 0)
1187 (unspec:I [(match_dup 1)] UNSPEC_NEGV))
1188 (label_ref (match_operand 2 ""))
1189 (pc)))]
1190 "")
1192 (define_insn_and_split "*neg<mode>2_insn"
1193 [(set (match_operand:I 0 "register_operand" "=r")
1194 (neg:I (match_operand:I 1 "register_operand" "r")))]
1195 "ok_for_simple_arith_logic_operands (operands, <MODE>mode)"
1196 "#"
1197 "reload_completed"
1198 [(parallel [(set (match_dup 0) (neg:I (match_dup 1)))
1199 (clobber (reg:CC R_FLAGS))])]
1200 ""
1201 [(set_attr "type" "arith")])
1203 (define_insn "*neg<mode>2_insn<subst_arith>"
1204 [(set (match_operand:I 0 "register_operand" "=r")
1205 (neg:I (match_operand:I 1 "register_operand" "r")))
1206 (clobber (reg:CC R_FLAGS))]
1207 "reload_completed"
1208 "sub<s> %0,r0,%1"
1209 [(set_attr "type" "arith")])
1211 (define_insn "negsi2_insn_set_carry"
1212 [(set (match_operand:SI 0 "register_operand" "=r")
1213 (neg:SI (match_operand:SI 1 "register_operand" "r")))
1214 (set (reg:CCC R_FLAGS)
1215 (compare:CCC (not:SI (match_dup 1)) (const_int -1)))]
1216 "reload_completed"
1217 "sub.l %0,r0,%1"
1218 [(set_attr "type" "arith")])
1220 (define_insn "*neg<mode>2_insn_set_overflow"
1221 [(set (match_operand:I 0 "register_operand" "=r")
1222 (neg:I (match_operand:I 1 "register_operand" "r")))
1223 (set (reg:CCV R_FLAGS)
1224 (compare:CCV (neg:I (match_dup 1))
1225 (unspec:I [(match_dup 1)] UNSPEC_NEGV)))]
1226 "reload_completed"
1227 "sub<s> %0,r0,%1"
1228 [(set_attr "type" "arith")])
1230 (define_expand "negdi2"
1231 [(set (match_operand:DI 0 "register_operand" "")
1232 (neg:DI (match_operand:DI 1 "register_operand" "")))]
1233 "")
1235 (define_insn_and_split "*negdi2_insn"
1236 [(set (match_operand:DI 0 "register_operand" "=&r")
1237 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
1238 "ok_for_simple_arith_logic_operands (operands, DImode)"
1239 "#"
1240 "reload_completed"
1241 [(const_int 0)]
1242 {
1243 visium_split_double_add (MINUS, operands[0], const0_rtx, operands[1]);
1244 DONE;
1245 }
1246 [(set_attr "type" "arith2")])
1248 ;;
1249 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1250 ;;
1251 ;; Integer Multiply (non-widening and widening, signed and unsigned)
1252 ;;
1253 ;; Only SI mode is supported.
1254 ;;
1255 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1256 ;;
1258 ; The mults and multu instructions clear MDC but we only pretend that they
1259 ; clobber it to keep things relatively simple.
1261 (define_insn "mulsi3"
1262 [(set (match_operand:SI 0 "register_operand" "=b")
1263 (mult:SI (match_operand:SI 1 "register_operand" "%r")
1264 (match_operand:SI 2 "register_operand" "r")))
1265 (clobber (reg:SI R_MDC))]
1266 ""
1267 "mults %1,%2"
1268 [(set_attr "type" "mul")])
1270 ; The names are mulsidi3 and umulsidi3 here.
1272 (define_insn "<u>mulsidi3"
1273 [(set (match_operand:DI 0 "register_operand" "=b")
1274 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "%r"))
1275 (any_extend:DI (match_operand:SI 2 "register_operand" "r"))))
1276 (clobber (reg:SI R_MDC))]
1277 ""
1278 "mult<su> %1,%2"
1279 [(set_attr "type" "mul")])
1281 ; But they are smulsi3_highpart and umulsi3_highpart here.
1283 (define_insn_and_split "<su>mulsi3_highpart"
1284 [(set (match_operand:SI 0 "register_operand" "=r")
1285 (truncate:SI
1286 (ashiftrt:DI
1287 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "%r"))
1288 (any_extend:DI (match_operand:SI 2 "register_operand" "r")))
1289 (const_int 32))))
1290 (clobber (reg:DI R_MDB))
1291 (clobber (reg:SI R_MDC))]
1292 ""
1293 "#"
1294 "reload_completed"
1295 [(parallel [(set (reg:DI R_MDB)
1296 (mult:DI (any_extend:DI (match_dup 1))
1297 (any_extend:DI (match_dup 2))))
1298 (clobber (reg:SI R_MDC))])
1299 (set (match_dup 0) (unspec:SI [(reg:DI R_MDB)] UNSPEC_MDBHI))]
1300 ""
1301 [(set_attr "type" "multi")])
1303 ;;
1304 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1305 ;;
1306 ;; Integer divide and modulus (signed and unsigned)
1307 ;;
1308 ;; Only SI mode is supported.
1309 ;;
1310 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1311 ;;
1313 (define_insn "*divmodsi4_insn"
1314 [(set (match_operand:SI 0 "register_operand" "=b")
1315 (div:SI (match_operand:SI 1 "register_operand" "0")
1316 (match_operand:SI 2 "register_operand" "r")))
1317 (set (reg:SI R_MDC) (mod:SI (match_dup 1) (match_dup 2)))]
1318 ""
1319 "divs %2"
1320 [(set_attr "type" "div")])
1322 (define_insn_and_split "divmodsi4"
1323 [(set (match_operand:SI 0 "register_operand" "=b")
1324 (div:SI (match_operand:SI 1 "register_operand" "0")
1325 (match_operand:SI 2 "register_operand" "r")))
1326 (set (match_operand:SI 3 "register_operand" "=r")
1327 (mod:SI (match_dup 1) (match_dup 2)))
1328 (clobber (reg:SI R_MDC))]
1329 ""
1330 "#"
1331 "reload_completed"
1332 [(parallel [(set (match_dup 0) (div:SI (match_dup 1) (match_dup 2)))
1333 (set (reg:SI R_MDC) (mod:SI (match_dup 1) (match_dup 2)))])
1334 (set (match_dup 3) (reg:SI R_MDC))]
1335 ""
1336 [(set_attr "type" "multi")])
1338 (define_insn "*udivmodsi4_insn"
1339 [(set (match_operand:SI 0 "register_operand" "=b")
1340 (udiv:SI (match_operand:SI 1 "register_operand" "0")
1341 (match_operand:SI 2 "register_operand" "r")))
1342 (set (reg:SI R_MDC) (umod:SI (match_dup 1) (match_dup 2)))]
1343 ""
1344 "divu %2"
1345 [(set_attr "type" "div")])
1347 (define_insn_and_split "udivmodsi4"
1348 [(set (match_operand:SI 0 "register_operand" "=b")
1349 (udiv:SI (match_operand:SI 1 "register_operand" "0")
1350 (match_operand:SI 2 "register_operand" "r")))
1351 (set (match_operand:SI 3 "register_operand" "=r")
1352 (umod:SI (match_dup 1) (match_dup 2)))
1353 (clobber (reg:SI R_MDC))]
1354 ""
1355 "#"
1356 "reload_completed"
1357 [(parallel [(set (match_dup 0) (udiv:SI (match_dup 1) (match_dup 2)))
1358 (set (reg:SI R_MDC) (umod:SI (match_dup 1) (match_dup 2)))])
1359 (set (match_dup 3) (reg:SI R_MDC))]
1360 ""
1361 [(set_attr "type" "multi")])
1363 ; FIXME. How do we persuade the compiler to use 64/32 bit divides directly ?
1365 (define_insn "*divds"
1366 [(set (reg:DI R_MDB)
1367 (div:DI (reg:DI R_MDB) (sign_extend:DI (match_operand:SI 0 "register_operand" "r"))))
1368 (set (reg:SI R_MDC) (truncate:SI (mod:DI (reg:DI R_MDB) (sign_extend:DI (match_dup 0)))))]
1369 ""
1370 "divds %0"
1371 [(set_attr "type" "divd")])
1373 (define_insn "*divdu"
1374 [(set (reg:DI R_MDB)
1375 (udiv:DI (reg:DI R_MDB) (zero_extend:DI (match_operand:SI 0 "register_operand" "r"))))
1376 (set (reg:SI R_MDC) (truncate:SI (umod:DI (reg:DI R_MDB) (zero_extend:DI (match_dup 0)))))]
1377 ""
1378 "divdu %0"
1379 [(set_attr "type" "divd")])
1381 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1382 ;;
1383 ;; Bitwise Logical AND
1384 ;;
1385 ;; Modes QI, HI and SI are supported directly.
1386 ;;
1387 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1388 ;;
1390 (define_expand "and<mode>3"
1391 [(set (match_operand:I 0 "register_operand" "")
1392 (and:I (match_operand:I 1 "register_operand" "")
1393 (match_operand:I 2 "register_operand" "")))]
1394 "")
1396 (define_insn_and_split "*and<mode>3_insn"
1397 [(set (match_operand:I 0 "register_operand" "=r")
1398 (and:I (match_operand:I 1 "register_operand" "%r")
1399 (match_operand:I 2 "register_operand" "r")))]
1400 "ok_for_simple_arith_logic_operands (operands, <MODE>mode)"
1401 "#"
1402 "reload_completed"
1403 [(parallel [(set (match_dup 0)
1404 (and:I (match_dup 1) (match_dup 2)))
1405 (clobber (reg:CC R_FLAGS))])]
1406 ""
1407 [(set_attr "type" "logic")])
1409 (define_insn "*and<mode>3_insn<subst_logic>"
1410 [(set (match_operand:I 0 "register_operand" "=r")
1411 (and:I (match_operand:I 1 "register_operand" "%r")
1412 (match_operand:I 2 "register_operand" "r")))
1413 (clobber (reg:CC R_FLAGS))]
1414 "reload_completed"
1415 "and<s> %0,%1,%2"
1416 [(set_attr "type" "logic")])
1418 ;;
1419 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1420 ;;
1421 ;; Bitwise Inclusive Logical OR
1422 ;;
1423 ;; Modes QI, HI and SI are supported directly.
1424 ;;
1425 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1426 ;;
1428 (define_expand "ior<mode>3"
1429 [(set (match_operand:I 0 "register_operand" "")
1430 (ior:I (match_operand:I 1 "register_operand" "")
1431 (match_operand:I 2 "register_operand" "")))]
1432 "")
1434 (define_insn_and_split "*ior<mode>3_insn"
1435 [(set (match_operand:I 0 "register_operand" "=r")
1436 (ior:I (match_operand:I 1 "register_operand" "%r")
1437 (match_operand:I 2 "register_operand" "r")))]
1438 "ok_for_simple_arith_logic_operands (operands, <MODE>mode)"
1439 "#"
1440 "reload_completed"
1441 [(parallel [(set (match_dup 0)
1442 (ior:I (match_dup 1) (match_dup 2)))
1443 (clobber (reg:CC R_FLAGS))])]
1444 ""
1445 [(set_attr "type" "logic")])
1447 (define_insn "*ior<mode>3_insn<subst_logic>"
1448 [(set (match_operand:I 0 "register_operand" "=r")
1449 (ior:I (match_operand:I 1 "register_operand" "%r")
1450 (match_operand:I 2 "register_operand" "r")))
1451 (clobber (reg:CC R_FLAGS))]
1452 "reload_completed"
1453 "or<s> %0,%1,%2"
1454 [(set_attr "type" "logic")])
1456 ;;
1457 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1458 ;;
1459 ;; Bitwise Exclusive Logical OR
1460 ;;
1461 ;; Modes QI, HI and SI are supported directly.
1462 ;;
1463 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1464 ;;
1466 (define_expand "xor<mode>3"
1467 [(set (match_operand:I 0 "register_operand" "")
1468 (xor:I (match_operand:I 1 "register_operand" "")
1469 (match_operand:I 2 "register_operand" "")))]
1470 "")
1472 (define_insn_and_split "*xor<mode>3_insn"
1473 [(set (match_operand:I 0 "register_operand" "=r")
1474 (xor:I (match_operand:I 1 "register_operand" "%r")
1475 (match_operand:I 2 "register_operand" "r")))]
1476 "ok_for_simple_arith_logic_operands (operands, <MODE>mode)"
1477 "#"
1478 "reload_completed"
1479 [(parallel [(set (match_dup 0)
1480 (xor:I (match_dup 1) (match_dup 2)))
1481 (clobber (reg:CC R_FLAGS))])]
1482 ""
1483 [(set_attr "type" "logic")])
1485 (define_insn "*xor<mode>3_insn<subst_logic>"
1486 [(set (match_operand:I 0 "register_operand" "=r")
1487 (xor:I (match_operand:I 1 "register_operand" "%r")
1488 (match_operand:I 2 "register_operand" "r")))
1489 (clobber (reg:CC R_FLAGS))]
1490 "reload_completed"
1491 "xor<s> %0,%1,%2"
1492 [(set_attr "type" "logic")])
1494 ;;
1495 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1496 ;;
1497 ;; Bitwise Logical NOT
1498 ;;
1499 ;; Modes QI, HI and SI are supported directly.
1500 ;;
1501 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1502 ;;
1504 (define_expand "one_cmpl<mode>2"
1505 [(set (match_operand:I 0 "register_operand" "")
1506 (not:I (match_operand:I 1 "reg_or_0_operand" "")))]
1507 "")
1509 (define_insn_and_split "*one_cmpl<mode>2_insn"
1510 [(set (match_operand:I 0 "register_operand" "=r")
1511 (not:I (match_operand:I 1 "reg_or_0_operand" "rO")))]
1512 "ok_for_simple_arith_logic_operands (operands, <MODE>mode)"
1513 "#"
1514 "reload_completed"
1515 [(parallel [(set (match_dup 0) (not:I (match_dup 1)))
1516 (clobber (reg:CC R_FLAGS))])]
1517 ""
1518 [(set_attr "type" "logic")])
1520 (define_insn "*one_cmpl<mode>2_insn<subst_logic>"
1521 [(set (match_operand:I 0 "register_operand" "=r")
1522 (not:I (match_operand:I 1 "reg_or_0_operand" "rO")))
1523 (clobber (reg:CC R_FLAGS))]
1524 "reload_completed"
1525 "not<s> %0,%r1"
1526 [(set_attr "type" "logic")])
1528 ;;
1529 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1530 ;;
1531 ;; Arithmetic Shift Left
1532 ;;
1533 ;; Modes QI, HI, SI and DI are supported directly.
1534 ;;
1535 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1536 ;;
1538 (define_expand "ashl<mode>3"
1539 [(set (match_operand:I 0 "register_operand" "")
1540 (ashift:I (match_operand:I 1 "register_operand" "")
1541 (match_operand:QI 2 "reg_or_shift_operand" "")))]
1542 "")
1544 (define_insn_and_split "*ashl<mode>3_insn"
1545 [(set (match_operand:I 0 "register_operand" "=r,r")
1546 (ashift:I (match_operand:I 1 "register_operand" "r,r")
1547 (match_operand:QI 2 "reg_or_shift_operand" "r,K")))]
1548 "ok_for_simple_arith_logic_operands (operands, <MODE>mode)"
1549 "#"
1550 "reload_completed"
1551 [(parallel [(set (match_dup 0)
1552 (ashift:I (match_dup 1) (match_dup 2)))
1553 (clobber (reg:CC R_FLAGS))])]
1554 ""
1555 [(set_attr "type" "arith")])
1557 (define_insn "*ashl<mode>3_insn<subst_arith>"
1558 [(set (match_operand:I 0 "register_operand" "=r,r")
1559 (ashift:I (match_operand:I 1 "register_operand" "r,r")
1560 (match_operand:QI 2 "reg_or_shift_operand" "r,K")))
1561 (clobber (reg:CC R_FLAGS))]
1562 "reload_completed"
1563 "asl<s> %0,%1,%2"
1564 [(set_attr "type" "arith")])
1566 (define_insn "ashldi3"
1567 [(set (match_operand:DI 0 "register_operand" "=b,r")
1568 (ashift:DI (match_operand:DI 1 "register_operand" "0,r")
1569 (match_operand:QI 2 "reg_or_32_operand" "r,P")))
1570 (clobber (reg:SI R_MDC))]
1571 ""
1572 "@
1573 asld %2
1574 #"
1575 [(set_attr "type" "shiftdi,multi")])
1577 (define_split
1578 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1579 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
1580 (const_int 32)))
1581 (clobber (reg:SI R_MDC))]
1582 "reload_completed"
1583 [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 4))
1584 (set (subreg:SI (match_dup 0) 4) (const_int 0))]
1585 "")
1587 ;;
1588 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1589 ;;
1590 ;; Arithmetic Shift Right
1591 ;;
1592 ;; Modes QI, HI, SI and DI are supported directly.
1593 ;;
1594 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1595 ;;
1597 (define_expand "ashr<mode>3"
1598 [(set (match_operand:I 0 "register_operand" "")
1599 (ashiftrt:I (match_operand:I 1 "register_operand" "")
1600 (match_operand:QI 2 "reg_or_shift_operand" "")))]
1601 "")
1603 (define_insn_and_split "*ashr<mode>3_insn"
1604 [(set (match_operand:I 0 "register_operand" "=r,r")
1605 (ashiftrt:I (match_operand:I 1 "register_operand" "r,r")
1606 (match_operand:QI 2 "reg_or_shift_operand" "r,K")))]
1607 "ok_for_simple_arith_logic_operands (operands, <MODE>mode)"
1608 "#"
1609 "reload_completed"
1610 [(parallel [(set (match_dup 0)
1611 (ashiftrt:I (match_dup 1) (match_dup 2)))
1612 (clobber (reg:CC R_FLAGS))])]
1613 ""
1614 [(set_attr "type" "logic")])
1616 (define_insn "*ashr<mode>3_insn<subst_logic>"
1617 [(set (match_operand:I 0 "register_operand" "=r,r")
1618 (ashiftrt:I (match_operand:I 1 "register_operand" "r,r")
1619 (match_operand:QI 2 "reg_or_shift_operand" "r,K")))
1620 (clobber (reg:CC R_FLAGS))]
1621 "reload_completed"
1622 "asr<s> %0,%1,%2"
1623 [(set_attr "type" "logic")])
1625 (define_insn "ashrdi3"
1626 [(set (match_operand:DI 0 "register_operand" "=b,r")
1627 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,r")
1628 (match_operand:QI 2 "reg_or_32_operand" "r,P")))
1629 (clobber (reg:SI R_MDC))]
1630 ""
1631 "@
1632 asrd %2
1633 #"
1634 [(set_attr "type" "shiftdi,multi")])
1636 (define_split
1637 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1638 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
1639 (const_int 32)))
1640 (clobber (reg:SI R_MDC))]
1641 "reload_completed"
1642 [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 0))
1643 (parallel [(set (subreg:SI (match_dup 0) 0)
1644 (ashiftrt:SI (subreg:SI (match_dup 1) 0) (const_int 31)))
1645 (clobber (reg:CC R_FLAGS))])]
1646 "")
1648 ;;
1649 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1650 ;;
1651 ;; Logical Shift Right
1652 ;;
1653 ;; Modes QI, HI, SI and DI are supported directly.
1654 ;;
1655 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1656 ;;
1658 (define_expand "lshr<mode>3"
1659 [(set (match_operand:I 0 "register_operand" "")
1660 (lshiftrt:I (match_operand:I 1 "register_operand" "")
1661 (match_operand:QI 2 "reg_or_shift_operand" "")))]
1662 "")
1664 (define_insn_and_split "*lshr<mode>3_insn"
1665 [(set (match_operand:I 0 "register_operand" "=r,r")
1666 (lshiftrt:I (match_operand:I 1 "register_operand" "r,r")
1667 (match_operand:QI 2 "reg_or_shift_operand" "r,K")))]
1668 "ok_for_simple_arith_logic_operands (operands, <MODE>mode)"
1669 "#"
1670 "reload_completed"
1671 [(parallel [(set (match_dup 0)
1672 (lshiftrt:I (match_dup 1) (match_dup 2)))
1673 (clobber (reg:CC R_FLAGS))])]
1674 ""
1675 [(set_attr "type" "logic")])
1677 (define_insn "*lshr<mode>3_insn<subst_logic>"
1678 [(set (match_operand:I 0 "register_operand" "=r,r")
1679 (lshiftrt:I (match_operand:I 1 "register_operand" "r,r")
1680 (match_operand:QI 2 "reg_or_shift_operand" "r,K")))
1681 (clobber (reg:CC R_FLAGS))]
1682 "reload_completed"
1683 "lsr<s> %0,%1,%2"
1684 [(set_attr "type" "logic")])
1686 (define_insn "lshrdi3"
1687 [(set (match_operand:DI 0 "register_operand" "=b,r")
1688 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,r")
1689 (match_operand:QI 2 "reg_or_32_operand" "r,P")))
1690 (clobber (reg:SI R_MDC))]
1691 ""
1692 "@
1693 lsrd %2
1694 #"
1695 [(set_attr "type" "shiftdi,multi")])
1697 (define_split
1698 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1699 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
1700 (const_int 32)))
1701 (clobber (reg:SI R_MDC))]
1702 "reload_completed"
1703 [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 0))
1704 (set (subreg:SI (match_dup 0) 0) (const_int 0))]
1705 "")
1707 ;;
1708 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1709 ;;
1710 ;; Truncate
1711 ;;
1712 ;; Truncations among modes QI, HI, SI and DI are supported directly.
1713 ;;
1714 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1715 ;;
1717 (define_expand "trunchiqi2"
1718 [(set (match_operand:QI 0 "register_operand" "")
1719 (truncate:QI (match_operand:HI 1 "register_operand" "")))]
1720 "")
1722 (define_insn_and_split "*trunchiqi2_insn"
1723 [(set (match_operand:QI 0 "register_operand" "=r")
1724 (truncate:QI (match_operand:HI 1 "register_operand" "r")))]
1725 "ok_for_simple_arith_logic_operands (operands, QImode)"
1726 "#"
1727 "reload_completed"
1728 [(parallel [(set (match_dup 0) (truncate:QI (match_dup 1)))
1729 (clobber (reg:CC R_FLAGS))])]
1730 ""
1731 [(set_attr "type" "logic")])
1733 (define_insn "*trunchiqi2_insn<subst_logic>"
1734 [(set (match_operand:QI 0 "register_operand" "=r")
1735 (truncate:QI (match_operand:HI 1 "register_operand" "r")))
1736 (clobber (reg:CC R_FLAGS))]
1737 "reload_completed"
1738 "move.b %0,%1"
1739 [(set_attr "type" "logic")])
1741 (define_expand "truncsihi2"
1742 [(set (match_operand:HI 0 "register_operand" "")
1743 (truncate:HI (match_operand:SI 1 "register_operand" "")))]
1744 "")
1746 (define_insn_and_split "*truncsihi2_insn"
1747 [(set (match_operand:HI 0 "register_operand" "=r")
1748 (truncate:HI (match_operand:SI 1 "register_operand" "r")))]
1749 "ok_for_simple_arith_logic_operands (operands, HImode)"
1750 "#"
1751 "reload_completed"
1752 [(parallel [(set (match_dup 0) (truncate:HI (match_dup 1)))
1753 (clobber (reg:CC R_FLAGS))])]
1754 ""
1755 [(set_attr "type" "logic")])
1757 (define_insn "*truncsihi2_insn<subst_logic>"
1758 [(set (match_operand:HI 0 "register_operand" "=r")
1759 (truncate:HI (match_operand:SI 1 "register_operand" "r")))
1760 (clobber (reg:CC R_FLAGS))]
1761 "reload_completed"
1762 "move.w %0,%1"
1763 [(set_attr "type" "logic")])
1765 (define_expand "truncdisi2"
1766 [(set (match_operand:SI 0 "register_operand" "")
1767 (truncate:SI (match_operand:DI 1 "register_operand" "")))]
1768 "")
1770 (define_insn_and_split "*truncdisi2_insn"
1771 [(set (match_operand:SI 0 "register_operand" "=r")
1772 (truncate:SI (match_operand:DI 1 "register_operand" "r")))]
1773 "ok_for_simple_arith_logic_operands (operands, SImode)"
1774 "#"
1775 "reload_completed"
1776 [(parallel [(set (match_dup 0) (truncate:SI (match_dup 1)))
1777 (clobber (reg:CC R_FLAGS))])]
1778 ""
1779 [(set_attr "type" "logic")])
1781 (define_insn "*truncdisi2_insn<subst_logic>"
1782 [(set (match_operand:SI 0 "register_operand" "=r")
1783 (truncate:SI (match_operand:DI 1 "register_operand" "r")))
1784 (clobber (reg:CC R_FLAGS))]
1785 "reload_completed"
1786 "move.l %0,%d1"
1787 [(set_attr "type" "logic")])
1789 ;;
1790 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1791 ;;
1792 ;; Sign-extend
1793 ;;
1794 ;; Sign-extensions among modes QI, HI, SI and DI are supported directly.
1795 ;;
1796 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1797 ;;
1799 (define_expand "extendqihi2"
1800 [(set (match_operand:HI 0 "register_operand" "")
1801 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
1802 "")
1804 (define_insn_and_split "*extendqihi2_insn"
1805 [(set (match_operand:HI 0 "register_operand" "=r")
1806 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1807 "ok_for_simple_arith_logic_operands (operands, HImode)"
1808 "#"
1809 "reload_completed"
1810 [(parallel [(set (match_dup 0) (sign_extend:HI (match_dup 1)))
1811 (clobber (reg:CC R_FLAGS))])]
1812 ""
1813 [(set_attr "type" "logic")])
1815 (define_insn "*extendqihi2_insn<subst_logic>"
1816 [(set (match_operand:HI 0 "register_operand" "=r")
1817 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))
1818 (clobber (reg:CC R_FLAGS))]
1819 "reload_completed"
1820 "extb.w %0,%1"
1821 [(set_attr "type" "logic")])
1823 (define_expand "extendqisi2"
1824 [(set (match_operand:SI 0 "register_operand" "")
1825 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
1826 "")
1828 (define_insn_and_split "*extendqisi2_insn"
1829 [(set (match_operand:SI 0 "register_operand" "=r")
1830 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1831 "ok_for_simple_arith_logic_operands (operands, SImode)"
1832 "#"
1833 "reload_completed"
1834 [(parallel [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
1835 (clobber (reg:CC R_FLAGS))])]
1836 ""
1837 [(set_attr "type" "logic")])
1839 (define_insn "*extendqisi2_insn<subst_logic>"
1840 [(set (match_operand:SI 0 "register_operand" "=r")
1841 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))
1842 (clobber (reg:CC R_FLAGS))]
1843 "reload_completed"
1844 "extb.l %0,%1"
1845 [(set_attr "type" "logic")])
1847 (define_expand "extendhisi2"
1848 [(set (match_operand:SI 0 "register_operand" "")
1849 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
1850 "")
1852 (define_insn_and_split "*extendhisi2_insn"
1853 [(set (match_operand:SI 0 "register_operand" "=r")
1854 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1855 "ok_for_simple_arith_logic_operands (operands, SImode)"
1856 "#"
1857 "reload_completed"
1858 [(parallel [(set (match_operand:SI 0 "register_operand" "")
1859 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))
1860 (clobber (reg:CC R_FLAGS))])]
1861 ""
1862 [(set_attr "type" "logic")])
1864 (define_insn "*extendhisi2_insn<subst_logic>"
1865 [(set (match_operand:SI 0 "register_operand" "=r")
1866 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))
1867 (clobber (reg:CC R_FLAGS))]
1868 "reload_completed"
1869 "extw.l %0,%1"
1870 [(set_attr "type" "logic")])
1872 (define_expand "extendsidi2"
1873 [(set (match_operand:DI 0 "register_operand" "")
1874 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))]
1875 "")
1877 (define_insn_and_split "*extendsidi2_insn"
1878 [(set (match_operand:DI 0 "register_operand" "=r")
1879 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1880 "ok_for_simple_arith_logic_operands (operands, DImode)"
1881 "#"
1882 "reload_completed"
1883 [(parallel [(set (match_dup 3) (match_dup 1))
1884 (clobber (reg:CC R_FLAGS))])
1885 (parallel [(set (match_dup 2)
1886 (ashiftrt:SI (match_dup 1) (const_int 31)))
1887 (clobber (reg:CC R_FLAGS))])]
1888 {
1889 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1890 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1891 }
1892 [(set_attr "type" "multi")])
1894 ;;
1895 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1896 ;;
1897 ;; Zero-extend
1898 ;;
1899 ;; Zero-extensions among modes QI, HI, SI and DI are supported directly.
1900 ;;
1901 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1902 ;;
1904 ; QI is zero-extended to wider modes by shifting left and then performing
1905 ; a logical shift right to insert the zeroes. This avoids the need to use
1906 ; another register.
1908 (define_expand "zero_extendqihi2"
1909 [(set (match_operand:HI 0 "register_operand" "")
1910 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
1911 "")
1913 (define_insn_and_split "*zero_extendqihi2_insn"
1914 [(set (match_operand:HI 0 "register_operand" "=r")
1915 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1916 "ok_for_simple_arith_logic_operands (operands, HImode)"
1917 "#"
1918 "reload_completed"
1919 [(parallel [(set (match_dup 0)
1920 (ashift:HI (match_dup 2) (const_int 8)))
1921 (clobber (reg:CC R_FLAGS))])
1922 (parallel [(set (match_dup 0)
1923 (lshiftrt:HI (match_dup 0) (const_int 8)))
1924 (clobber (reg:CC R_FLAGS))])]
1925 {
1926 operands[2] = gen_rtx_SUBREG (HImode, operands[1], 0);
1927 }
1928 [(set_attr "type" "multi")])
1930 (define_expand "zero_extendqisi2"
1931 [(set (match_operand:SI 0 "register_operand" "")
1932 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
1933 "")
1935 (define_insn_and_split "*zero_extendqisi2_insn"
1936 [(set (match_operand:SI 0 "register_operand" "=r")
1937 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1938 "ok_for_simple_arith_logic_operands (operands, SImode)"
1939 "#"
1940 "reload_completed"
1941 [(parallel [(set (match_dup 0)
1942 (ashift:SI (match_dup 2) (const_int 24)))
1943 (clobber (reg:CC R_FLAGS))])
1944 (parallel [(set (match_dup 0)
1945 (lshiftrt:SI (match_dup 0) (const_int 24)))
1946 (clobber (reg:CC R_FLAGS))])]
1947 {
1948 operands[2] = gen_rtx_SUBREG (SImode, operands[1], 0);
1949 }
1950 [(set_attr "type" "multi")])
1952 (define_insn "zero_extendhisi2"
1953 [(set (match_operand:SI 0 "register_operand" "=r")
1954 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1955 ""
1956 "moviu %0,0"
1957 [(set_attr "type" "imm_reg")])
1959 (define_expand "zero_extendsidi2"
1960 [(set (match_operand:DI 0 "register_operand" "")
1961 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))]
1962 "")
1964 (define_insn_and_split "*zero_extendsidi2_insn"
1965 [(set (match_operand:DI 0 "register_operand" "=r")
1966 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1967 "ok_for_simple_arith_logic_operands (operands, DImode)"
1968 "#"
1969 "reload_completed"
1970 [(parallel [(set (match_dup 3) (match_dup 1))
1971 (clobber (reg:CC R_FLAGS))])
1972 (set (match_dup 2) (const_int 0))]
1973 {
1974 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1975 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1976 }
1977 [(set_attr "type" "multi")])
1979 ;;
1980 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1981 ;;
1982 ;; Bit Test
1983 ;;
1984 ;; Only SI mode is supported directly.
1985 ;;
1986 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1987 ;;
1989 ; BITS_BIG_ENDIAN is defined to 1 so operand #1 counts from the MSB.
1991 (define_insn "*btst<mode>"
1992 [(set (reg:CCC R_FLAGS)
1993 (compare:CCC (zero_extract:I
1994 (match_operand:I 0 "register_operand" "r")
1995 (const_int 1)
1996 (match_operand:QI 1 "const_shift_operand" "K"))
1997 (const_int 0)))]
1998 "reload_completed"
1999 "lsr<s> r0,%0,<b>-%1"
2000 [(set_attr "type" "logic")])
2002 ;;
2003 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2004 ;;
2005 ;; Integer overflow tests
2006 ;;
2007 ;; Modes QI, HI and SI are supported directly.
2008 ;;
2009 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2010 ;;
2012 (define_insn "*addv_tst<mode>"
2013 [(set (reg:CCV R_FLAGS)
2014 (compare:CCV (match_operand:I 0 "register_operand" "r")
2015 (unspec:I [(match_operand:I 1 "register_operand" "%r")
2016 (match_operand:I 2 "register_operand" "r")]
2017 UNSPEC_ADDV)))]
2018 "reload_completed"
2019 "add<s> r0,%1,%2"
2020 [(set_attr "type" "arith")])
2022 (define_insn "*subv_tst<mode>"
2023 [(set (reg:CCV R_FLAGS)
2024 (compare:CCV (match_operand:I 0 "register_operand" "r")
2025 (unspec:I [(match_operand:I 1 "reg_or_0_operand" "rO")
2026 (match_operand:I 2 "register_operand" "r")]
2027 UNSPEC_SUBV)))]
2028 "reload_completed"
2029 "sub<s> r0,%r1,%2"
2030 [(set_attr "type" "arith")])
2032 (define_insn "*negv_tst<mode>"
2033 [(set (reg:CCV R_FLAGS)
2034 (compare:CCV (match_operand:I 0 "register_operand" "r")
2035 (unspec:I [(match_operand:I 1 "register_operand" "r")]
2036 UNSPEC_NEGV)))]
2037 "reload_completed"
2038 "sub<s> r0,r0,%1"
2039 [(set_attr "type" "arith")])
2041 ;;
2042 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2043 ;;
2044 ;; Integer comparisons
2045 ;;
2046 ;; Modes QI, HI and SI are supported directly.
2047 ;;
2048 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2049 ;;
2051 (define_insn "*cmp<mode>"
2052 [(set (reg:CC R_FLAGS)
2053 (compare:CC (match_operand:I 0 "register_operand" "r")
2054 (match_operand:I 1 "reg_or_0_operand" "rO")))]
2055 "reload_completed"
2056 "cmp<s> %0,%r1"
2057 [(set_attr "type" "cmp")])
2059 (define_insn "*cmp<mode>_sne"
2060 [(set (reg:CCC R_FLAGS)
2061 (compare:CCC (not:I (match_operand:I 0 "register_operand" "r"))
2062 (const_int -1)))]
2063 "reload_completed"
2064 "cmp<s> r0,%0"
2065 [(set_attr "type" "cmp")])
2067 ;;
2068 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2069 ;;
2070 ;; Single float operations
2071 ;;
2072 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2073 ;;
2075 (define_insn "addsf3"
2076 [(set (match_operand:SF 0 "fp_reg_operand" "=f")
2077 (plus:SF (match_operand:SF 1 "fp_reg_operand" "%f")
2078 (match_operand:SF 2 "fp_reg_operand" "f")))]
2079 "TARGET_FPU"
2080 "fadd %0,%1,%2"
2081 [(set_attr "type" "fp")])
2083 (define_insn "subsf3"
2084 [(set (match_operand:SF 0 "fp_reg_operand" "=f")
2085 (minus:SF (match_operand:SF 1 "fp_reg_operand" "f")
2086 (match_operand:SF 2 "fp_reg_operand" "f")))]
2087 "TARGET_FPU"
2088 "fsub %0,%1,%2"
2089 [(set_attr "type" "fp")])
2091 (define_insn "mulsf3"
2092 [(set (match_operand:SF 0 "fp_reg_operand" "=f")
2093 (mult:SF (match_operand:SF 1 "fp_reg_operand" "%f")
2094 (match_operand:SF 2 "fp_reg_operand" "f")))]
2095 "TARGET_FPU"
2096 "fmult %0,%1,%2"
2097 [(set_attr "type" "fp")])
2099 (define_insn "divsf3"
2100 [(set (match_operand:SF 0 "fp_reg_operand" "=f")
2101 (div:SF (match_operand:SF 1 "fp_reg_operand" "f")
2102 (match_operand:SF 2 "fp_reg_operand" "f")))]
2103 "TARGET_FPU"
2104 "fdiv %0,%1,%2"
2105 [(set_attr "type" "fdiv")])
2107 (define_insn "sqrtsf2"
2108 [(set (match_operand:SF 0 "fp_reg_operand" "=f")
2109 (sqrt:SF (match_operand:SF 1 "fp_reg_operand" "f")))]
2110 "TARGET_FPU"
2111 "fsqrt %0,%1"
2112 [(set_attr "type" "fsqrt")])
2114 (define_insn "negsf2"
2115 [(set (match_operand:SF 0 "fp_reg_operand" "=f")
2116 (neg:SF (match_operand:SF 1 "fp_reg_operand" "f")))]
2117 "TARGET_FPU"
2118 "fneg %0,%1"
2119 [(set_attr "type" "fmove")])
2121 (define_insn "abssf2"
2122 [(set (match_operand:SF 0 "fp_reg_operand" "=f")
2123 (abs:SF (match_operand:SF 1 "fp_reg_operand" "f")))]
2124 "TARGET_FPU"
2125 "fabs %0,%1"
2126 [(set_attr "type" "fmove")])
2128 (define_expand "copysignsf3"
2129 [(match_operand:SF 0 "register_operand" "")
2130 (match_operand:SF 1 "nonmemory_operand" "")
2131 (match_operand:SF 2 "register_operand" "")]
2132 "TARGET_FPU && !TARGET_FPU_IEEE"
2133 {
2134 visium_expand_copysign (operands, SFmode);
2135 DONE;
2136 })
2138 ;;
2139 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2140 ;;
2141 ;; Single float <-> single integer conversions for !TARGET_FPU_IEEE
2142 ;;
2143 ;; An FMOVE instruction converts a signalling NaN (zero high order bit of the
2144 ;; mantissa) to a quiet NaN (-1). This is acceptable when the data to be
2145 ;; moved is in fact a floating-point number, but to avoid nasty surprises
2146 ;; integers must in general be kept out of the floating-point registers.
2147 ;; HARD_REGNO_MODE_OK thus only allows SFmode in these registers.
2148 ;; However, since FTOI and ITOF use floating-point registers for both their
2149 ;; inputs and outputs, to use these instructions integers must transiently
2150 ;; occupy such registers. To disguise this from the compiler, UNSPECs are
2151 ;; used for floating-point operations on integers and floating from general
2152 ;; register to floating-point register and fixing in the reverse direction
2153 ;; are only split into the individual UNSPEC operations after reload.
2154 ;;
2155 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2156 ;;
2158 (define_insn "*fload_no_ieee"
2159 [(set (match_operand:SF 0 "fp_reg_operand" "=f")
2160 (unspec:SF [(match_operand:SI 1 "register_operand" "r")] UNSPEC_FLOAD))]
2161 "TARGET_FPU && !TARGET_FPU_IEEE"
2162 "fload %0,%1"
2163 [(set_attr "type" "reg_fp")])
2165 (define_insn "*itof_no_ieee"
2166 [(set (match_operand:SF 0 "fp_reg_operand" "=f")
2167 (unspec:SF [(match_operand:SF 1 "fp_reg_operand" "f")] UNSPEC_ITOF))]
2168 "TARGET_FPU && !TARGET_FPU_IEEE"
2169 "itof %0,%1"
2170 [(set_attr "type" "itof")])
2172 (define_insn_and_split "*floatsisf2_no_ieee"
2173 [(set (match_operand:SF 0 "fp_reg_operand" "=f")
2174 (float:SF (match_operand:SI 1 "register_operand" "r")))]
2175 "TARGET_FPU && !TARGET_FPU_IEEE"
2176 "#"
2177 "&& reload_completed"
2178 [(set (match_dup 0)
2179 (unspec:SF [(match_dup 1)] UNSPEC_FLOAD))
2180 (set (match_dup 0)
2181 (unspec:SF [(match_dup 0)] UNSPEC_ITOF))]
2182 ""
2183 [(set_attr "type" "multi")])
2185 (define_insn "*ftoi_no_ieee"
2186 [(set (match_operand:SF 0 "fp_reg_operand" "=f")
2187 (unspec:SF [(match_operand:SF 1 "fp_reg_operand" "f")] UNSPEC_FTOI))]
2188 "TARGET_FPU && !TARGET_FPU_IEEE"
2189 "ftoi %0,%1"
2190 [(set_attr "type" "ftoi")])
2192 (define_insn "*fstore_no_ieee"
2193 [(set (match_operand:SI 0 "register_operand" "=r")
2194 (unspec:SI [(match_operand:SF 1 "fp_reg_operand" "f")] UNSPEC_FSTORE))]
2195 "TARGET_FPU && !TARGET_FPU_IEEE"
2196 "fstore %0,%1"
2197 [(set_attr "type" "fp_reg")])
2199 (define_insn_and_split "fix_truncsfsi2_no_ieee"
2200 [(set (match_operand:SI 0 "register_operand" "=r")
2201 (fix:SI (fix:SF (match_operand:SF 1 "fp_reg_operand" "f"))))
2202 (clobber (match_scratch:SF 2 "=1"))]
2203 "TARGET_FPU && !TARGET_FPU_IEEE"
2204 "#"
2205 "&& reload_completed"
2206 [(set (match_dup 1)
2207 (unspec:SF [(match_dup 1)] UNSPEC_FTOI))
2208 (set (match_dup 0)
2209 (unspec:SI [(match_dup 1)] UNSPEC_FSTORE))]
2210 ""
2211 [(set_attr "type" "multi")])
2213 ;;
2214 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2215 ;;
2216 ;; Single float <-> single integer conversions
2217 ;;
2218 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2219 ;;
2221 (define_insn "*itof"
2222 [(set (match_operand:SF 0 "fp_reg_operand" "=f")
2223 (float:SF (match_operand:SI 1 "register_operand" "f")))]
2224 "TARGET_FPU_IEEE"
2225 "itof %0,%1"
2226 [(set_attr "type" "itof")])
2228 (define_expand "floatsisf2"
2229 [(set (match_operand:SF 0 "fp_reg_operand" "")
2230 (float:SF (match_operand:SI 1 "register_operand" "")))]
2231 "TARGET_FPU"
2232 "")
2234 (define_insn "*ftoi"
2235 [(set (match_operand:SI 0 "register_operand" "=f")
2236 (fix:SI (fix:SF (match_operand:SF 1 "fp_reg_operand" "f"))))]
2237 "TARGET_FPU_IEEE"
2238 "ftoi %0,%1"
2239 [(set_attr "type" "ftoi")])
2241 (define_expand "fix_truncsfsi2"
2242 [(set (match_operand:SI 0 "register_operand" "")
2243 (fix:SI (fix:SF (match_operand:SF 1 "fp_reg_operand" ""))))]
2244 "TARGET_FPU"
2245 {
2246 if (!TARGET_FPU_IEEE)
2247 {
2248 emit_insn (gen_fix_truncsfsi2_no_ieee (operands[0], operands[1]));
2249 DONE;
2250 }
2251 })
2253 ;;
2254 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2255 ;;
2256 ;; Single float comparisons
2257 ;;
2258 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2259 ;;
2261 (define_insn "*cmpsf_fp"
2262 [(set (reg:CCFP R_FLAGS)
2263 (compare:CCFP (match_operand:SF 0 "fp_reg_or_0_operand" "fG")
2264 (match_operand:SF 1 "fp_reg_or_0_operand" "fG")))]
2265 "TARGET_FPU && reload_completed"
2266 "fcmp r0,%f0,%f1"
2267 [(set_attr "type" "fcmp")])
2269 (define_insn "*cmpsf_fpe"
2270 [(set (reg:CCFPE R_FLAGS)
2271 (compare:CCFPE (match_operand:SF 0 "fp_reg_or_0_operand" "fG")
2272 (match_operand:SF 1 "fp_reg_or_0_operand" "fG")))]
2273 "TARGET_FPU && reload_completed"
2274 "fcmpe r0,%f0,%f1"
2275 [(set_attr "type" "fcmp")])
2277 ;;
2278 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2279 ;;
2280 ;; Conditional branch instructions
2281 ;;
2282 ;; Note - we do not specify the two instructions necessary to perform
2283 ;; a compare-and-branch in the cbranch<mode>4 pattern because that would
2284 ;; allow the comparison to be moved away from the jump before the reload
2285 ;; pass has completed. That would be problematical because reload can
2286 ;; generate instructions in between which would clobber the CC register.
2287 ;;
2288 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2289 ;;
2291 (define_expand "cbranch<mode>4"
2292 [(set (pc)
2293 (if_then_else (match_operator 0 "ordered_comparison_operator"
2294 [(match_operand:I 1 "register_operand")
2295 (match_operand:I 2 "reg_or_0_operand")])
2296 (label_ref (match_operand 3 ""))
2297 (pc)))]
2298 ""
2299 )
2301 (define_insn_and_split "*cbranch<mode>4_insn"
2302 [(set (pc)
2303 (if_then_else (match_operator 0 "ordered_comparison_operator"
2304 [(match_operand:I 1 "register_operand" "r")
2305 (match_operand:I 2 "reg_or_0_operand" "rO")])
2306 (label_ref (match_operand 3 ""))
2307 (pc)))]
2308 ""
2309 "#"
2310 "reload_completed"
2311 [(const_int 0)]
2312 {
2313 visium_split_cbranch (GET_CODE (operands[0]), operands[1], operands[2],
2314 operands[3]);
2315 DONE;
2316 }
2317 [(set_attr "type" "cmp")])
2319 (define_insn_and_split "*cbranch<mode>4_addv_insn"
2320 [(set (pc)
2321 (if_then_else (match_operator 0 "visium_equality_comparison_operator"
2322 [(match_operand:I 1 "register_operand" "r")
2323 (unspec:I [(match_operand:I 2 "register_operand" "%r")
2324 (match_operand:I 3 "register_operand" "r")]
2325 UNSPEC_ADDV)])
2326 (label_ref (match_operand 4 ""))
2327 (pc)))]
2328 ""
2329 "#"
2330 "reload_completed"
2331 [(const_int 0)]
2332 {
2333 visium_split_cbranch (GET_CODE (operands[0]), XEXP (operands[0], 0),
2334 XEXP (operands[0], 1), operands[4]);
2335 DONE;
2336 }
2337 [(set_attr "type" "cmp")])
2339 (define_insn_and_split "*cbranch<mode>4_subv_insn"
2340 [(set (pc)
2341 (if_then_else (match_operator 0 "visium_equality_comparison_operator"
2342 [(match_operand:I 1 "register_operand" "r")
2343 (unspec:I [(match_operand:I 2 "reg_or_0_operand" "rO")
2344 (match_operand:I 3 "register_operand" "r")]
2345 UNSPEC_SUBV)])
2346 (label_ref (match_operand 4 ""))
2347 (pc)))]
2348 ""
2349 "#"
2350 "reload_completed"
2351 [(const_int 0)]
2352 {
2353 visium_split_cbranch (GET_CODE (operands[0]), XEXP (operands[0], 0),
2354 XEXP (operands[0], 1), operands[4]);
2355 DONE;
2356 }
2357 [(set_attr "type" "cmp")])
2359 (define_insn_and_split "*cbranch<mode>4_negv_insn"
2360 [(set (pc)
2361 (if_then_else (match_operator 0 "visium_equality_comparison_operator"
2362 [(match_operand:I 1 "register_operand" "r")
2363 (unspec:I [(match_operand:I 2 "register_operand" "r")]
2364 UNSPEC_NEGV)])
2365 (label_ref (match_operand 3 ""))
2366 (pc)))]
2367 ""
2368 "#"
2369 "reload_completed"
2370 [(const_int 0)]
2371 {
2372 visium_split_cbranch (GET_CODE (operands[0]), XEXP (operands[0], 0),
2373 XEXP (operands[0], 1), operands[3]);
2374 DONE;
2375 }
2376 [(set_attr "type" "cmp")])
2378 (define_insn_and_split "*cbranch<mode>4_btst_insn"
2379 [(set (pc)
2380 (if_then_else (match_operator 0 "visium_equality_comparison_operator"
2381 [(zero_extract:I
2382 (match_operand:I 1 "register_operand" "r")
2383 (const_int 1)
2384 (match_operand:QI 2 "const_shift_operand" "K"))
2385 (const_int 0)])
2386 (label_ref (match_operand 3 ""))
2387 (pc)))]
2388 ""
2389 "#"
2390 "reload_completed"
2391 [(const_int 0)]
2392 {
2393 visium_split_cbranch (GET_CODE (operands[0]), XEXP (operands[0], 0),
2394 XEXP (operands[0], 1), operands[3]);
2395 DONE;
2396 }
2397 [(set_attr "type" "cmp")])
2399 (define_expand "cbranchsf4"
2400 [(set (pc)
2401 (if_then_else (match_operator 0 "visium_fp_comparison_operator"
2402 [(match_operand:SF 1 "fp_reg_operand")
2403 (match_operand:SF 2 "fp_reg_or_0_operand")])
2404 (label_ref (match_operand 3 ""))
2405 (pc)))]
2406 "TARGET_FPU"
2407 )
2409 (define_insn_and_split "*cbranchsf4_insn"
2410 [(set (pc)
2411 (if_then_else (match_operator 0 "visium_fp_comparison_operator"
2412 [(match_operand:SF 1 "fp_reg_operand" "f")
2413 (match_operand:SF 2 "fp_reg_or_0_operand" "fG")])
2414 (label_ref (match_operand 3 ""))
2415 (pc)))]
2416 "TARGET_FPU"
2417 "#"
2418 "&& reload_completed"
2419 [(const_int 0)]
2420 {
2421 visium_split_cbranch (GET_CODE (operands[0]), operands[1], operands[2],
2422 operands[3]);
2423 DONE;
2424 }
2425 [(set_attr "type" "fcmp")])
2427 ; Now match both normal and inverted branches.
2429 (define_insn "*normal_branch"
2430 [(set (pc)
2431 (if_then_else (match_operator 1 "visium_branch_operator"
2432 [(reg R_FLAGS) (const_int 0)])
2433 (label_ref (match_operand 0 ""))
2434 (pc)))]
2435 "reload_completed"
2436 {
2437 return output_cbranch (operands[0], GET_CODE (operands[1]),
2438 GET_MODE (XEXP (operands[1], 0)), 0, insn);
2439 }
2440 [(set_attr "type" "branch")])
2442 (define_insn "*inverted_branch"
2443 [(set (pc)
2444 (if_then_else (match_operator 1 "visium_branch_operator"
2445 [(reg R_FLAGS) (const_int 0)])
2446 (pc)
2447 (label_ref (match_operand 0 ""))))]
2448 "reload_completed"
2449 {
2450 return output_cbranch (operands[0], GET_CODE (operands[1]),
2451 GET_MODE (XEXP (operands[1], 0)), 1, insn);
2452 }
2453 [(set_attr "type" "branch")])
2455 ; And then match both normal and inverted returns.
2457 (define_insn "*cond_<return_str>return"
2458 [(set (pc)
2459 (if_then_else (match_operator 0 "visium_branch_operator"
2460 [(reg R_FLAGS) (const_int 0)])
2461 (any_return)
2462 (pc)))]
2463 "<return_pred> && reload_completed"
2464 {
2465 return output_cbranch (pc_rtx, GET_CODE (operands[0]),
2466 GET_MODE (XEXP (operands[0], 0)), 0, insn);
2467 }
2468 [(set_attr "type" "ret")])
2470 (define_insn "*inverted_cond_<return_str>return"
2471 [(set (pc)
2472 (if_then_else (match_operator 0 "visium_branch_operator"
2473 [(reg R_FLAGS) (const_int 0)])
2474 (pc)
2475 (any_return)))]
2476 "<return_pred> && reload_completed"
2477 {
2478 return output_cbranch (pc_rtx, GET_CODE (operands[0]),
2479 GET_MODE (XEXP (operands[0], 0)), 1, insn);
2480 }
2481 [(set_attr "type" "ret")])
2483 ;;
2484 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2485 ;;
2486 ;; Unconditional branch instructions
2487 ;;
2488 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2489 ;;
2491 (define_insn "jump"
2492 [(set (pc)
2493 (label_ref (match_operand 0 "" "")))]
2494 ""
2495 {
2496 return output_ubranch (operands[0], insn);
2497 }
2498 [(set_attr "type" "branch")])
2500 (define_insn "indirect_jump"
2501 [(set (pc)
2502 (match_operand:SI 0 "register_operand" "r"))]
2503 ""
2504 "bra tr,%0,r0%# ;indirect jump"
2505 [(set_attr "type" "abs_branch")])
2507 (define_insn "tablejump"
2508 [(set (pc)
2509 (match_operand:SI 0 "register_operand" "r"))
2510 (use (label_ref (match_operand 1 "" "")))]
2511 ""
2512 "bra tr,%0,r0%# ;tablejump"
2513 [(set_attr "type" "abs_branch")])
2515 ;;
2516 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2517 ;;
2518 ;; trap instructions
2519 ;;
2520 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2521 ;;
2523 (define_insn "trap"
2524 [(trap_if (const_int 1) (const_int 0))]
2525 ""
2526 "stop 0,r0"
2527 [(set_attr "type" "trap")])
2529 ;;
2530 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2531 ;;
2532 ;; Subprogram call instructions
2533 ;;
2534 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2535 ;;
2537 ; Subroutine call instruction returning no value. Operand 0 is the function
2538 ; to call; operand 1 is the number of bytes of arguments pushed (in mode
2539 ; 'SImode', except it is normally a 'const_int'); operand 2 is the number of
2540 ; registers used as operands.
2542 (define_expand "call"
2543 [(parallel [(call (match_operand 0 "" "")
2544 (match_operand 1 "" ""))
2545 (use (match_operand 2 "" ""))
2546 (clobber (match_dup 3))])]
2547 ""
2548 {
2549 if (GET_CODE (XEXP (operands[0], 0)) != REG)
2550 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
2552 if (!operands[2])
2553 operands[2] = const0_rtx;
2555 operands[3] = gen_rtx_REG (Pmode, R_LINK);
2556 })
2558 (define_insn "*call_internal"
2559 [(call (mem:SI (match_operand:SI 0 "register_operand" "l,!r"))
2560 (match_operand 1 "" ""))
2561 (use (match_operand 2 "" ""))
2562 (clobber (match_operand 3 "" ""))]
2563 "!SIBLING_CALL_P (insn)"
2564 "bra tr,%0,%3%# ;call"
2565 [(set_attr "type" "call")])
2567 ; Subroutine call instruction returning a value. Operand 0 is the hard
2568 ; register in which the value is returned. There are three more operands, the
2569 ; same as the three operands of the 'call' instruction (but with numbers
2570 ; increased by one).
2572 (define_expand "call_value"
2573 [(parallel [(set (match_operand 0 "register_operand" "")
2574 (call (match_operand 1 "" "")
2575 (match_operand 2 "" "")))
2576 (use (match_operand 3 "" ""))
2577 (clobber (match_dup 4))])]
2578 ""
2579 {
2580 if (GET_CODE (XEXP (operands[1], 0)) != REG)
2581 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
2583 if (!operands[3])
2584 operands[3] = const0_rtx;
2586 operands[4] = gen_rtx_REG (Pmode, R_LINK);
2587 })
2589 (define_insn "*call_value_internal"
2590 [(set (match_operand 0 "register_operand" "")
2591 (call (mem:SI (match_operand:SI 1 "register_operand" "l,!r"))
2592 (match_operand 2 "" "")))
2593 (use (match_operand 3 "" ""))
2594 (clobber (match_operand 4 "" ""))]
2595 "!SIBLING_CALL_P (insn)"
2596 "bra tr,%1,%4%# ;call value"
2597 [(set_attr "type" "call")])
2599 ; Tail calls are similar, except that the link register is not used. But
2600 ; we don't use r0 as the destination register of the branch because we want
2601 ; the Branch Pre-decode Logic of the GR6 to use the Address Load Array to
2602 ; predict the branch target.
2604 (define_expand "sibcall"
2605 [(parallel [(call (match_operand 0 "" "")
2606 (match_operand 1 "" ""))
2607 (use (match_operand 2 "" ""))
2608 (clobber (match_dup 3))])]
2609 ""
2610 {
2611 if (GET_CODE (XEXP (operands[0], 0)) != REG)
2612 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
2614 if (!operands[2])
2615 operands[2] = const0_rtx;
2617 operands[3] = gen_rtx_SCRATCH (SImode);
2618 })
2620 (define_insn "*sibcall_internal"
2621 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
2622 (match_operand 1 "" ""))
2623 (use (match_operand 2 "" ""))
2624 (clobber (match_scratch:SI 3 "=0"))]
2625 "SIBLING_CALL_P (insn)"
2626 "bra tr,%0,%0%# ;sibcall"
2627 [(set_attr "type" "call")])
2629 (define_expand "sibcall_value"
2630 [(parallel [(set (match_operand 0 "register_operand" "")
2631 (call (match_operand 1 "" "")
2632 (match_operand 2 "" "")))
2633 (use (match_operand 3 "" ""))
2634 (clobber (match_dup 4))])]
2635 ""
2636 {
2637 if (GET_CODE (XEXP (operands[1], 0)) != REG)
2638 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
2640 if (!operands[3])
2641 operands[3] = const0_rtx;
2643 operands[4] = gen_rtx_SCRATCH (SImode);
2644 })
2646 (define_insn "*sibcall_value_internal"
2647 [(set (match_operand 0 "register_operand" "")
2648 (call (mem:SI (match_operand:SI 1 "register_operand" "k"))
2649 (match_operand 2 "" "")))
2650 (use (match_operand 3 "" ""))
2651 (clobber (match_scratch:SI 4 "=1"))]
2652 "SIBLING_CALL_P (insn)"
2653 "bra tr,%1,%1%# ;sibcall value"
2654 [(set_attr "type" "call")])
2656 ; Call subroutine returning any type.
2657 (define_expand "untyped_call"
2658 [(parallel [(call (match_operand 0 "" "")
2659 (const_int 0))
2660 (match_operand 1 "" "")
2661 (match_operand 2 "" "")])]
2662 ""
2663 {
2664 int i;
2666 emit_call_insn (gen_call (operands[0], const0_rtx, NULL));
2668 for (i = 0; i < XVECLEN (operands[2], 0); i++)
2669 {
2670 rtx set = XVECEXP (operands[2], 0, i);
2671 emit_move_insn (SET_DEST (set), SET_SRC (set));
2672 }
2674 /* The optimizer does not know that the call sets the function value
2675 registers we stored in the result block. We avoid problems by
2676 claiming that all hard registers are used and clobbered at this
2677 point. */
2678 emit_insn (gen_blockage ());
2680 DONE;
2681 })
2683 ;;
2684 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2685 ;;
2686 ;; Compare-and-store instructions
2687 ;;
2688 ;; Modes QI, HI, SI and SF are supported directly.
2689 ;;
2690 ;; Note - we do not specify the two instructions necessary to perform
2691 ;; a compare-and-store in the cstore<mode>4 pattern because that would
2692 ;; allow the comparison to be moved away from the store before the reload
2693 ;; pass has completed. That would be problematical because reload can
2694 ;; generate instructions in between which would clobber the CC register.
2695 ;;
2696 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2697 ;;
2699 (define_expand "cstore<mode>4"
2700 [(set (match_operand:SI 0)
2701 (match_operator:SI 1 "visium_int_cstore_operator"
2702 [(match_operand:I 2 "register_operand")
2703 (match_operand:I 3 "reg_or_0_operand")]))]
2704 ""
2705 {
2706 visium_expand_int_cstore (operands, <MODE>mode);
2707 DONE;
2708 })
2710 (define_insn_and_split "*cstore<mode>4_insn"
2711 [(set (match_operand:SI 0 "register_operand" "=r")
2712 (ltu:SI (match_operand:I 1 "register_operand" "r")
2713 (match_operand:I 2 "reg_or_0_operand" "rO")))]
2714 ""
2715 "#"
2716 "reload_completed"
2717 [(const_int 0)]
2718 {
2719 visium_split_cstore (SET, operands[0], NULL_RTX,
2720 LTU, operands[1], operands[2]);
2721 DONE;
2722 }
2723 [(set_attr "type" "cmp")])
2725 (define_insn_and_split "*neg_cstore<mode>4_insn"
2726 [(set (match_operand:SI 0 "register_operand" "=r")
2727 (neg:SI (ltu:SI (match_operand:I 1 "register_operand" "r")
2728 (match_operand:I 2 "reg_or_0_operand" "rO"))))]
2729 ""
2730 "#"
2731 "reload_completed"
2732 [(const_int 0)]
2733 {
2734 visium_split_cstore (NEG, operands[0], NULL_RTX,
2735 LTU, operands[1], operands[2]);
2736 DONE;
2737 }
2738 [(set_attr "type" "cmp")])
2740 (define_insn_and_split "*<add_str>_cstore<mode>4_insn"
2741 [(set (match_operand:SI 0 "register_operand" "=r")
2742 (any_add:SI (match_operand:SI 1 "register_operand" "r")
2743 (ltu:SI (match_operand:I 2 "register_operand" "r")
2744 (match_operand:I 3 "reg_or_0_operand" "rO"))))]
2745 ""
2746 "#"
2747 "reload_completed"
2748 [(const_int 0)]
2749 {
2750 visium_split_cstore (<add_op>, operands[0], operands[1],
2751 LTU, operands[2], operands[3]);
2752 DONE;
2753 }
2754 [(set_attr "type" "cmp")])
2756 (define_insn_and_split "*cstore<mode>4_sne_insn"
2757 [(set (match_operand:SI 0 "register_operand" "=r")
2758 (ltu:SI (not:I (match_operand:I 1 "register_operand" "r"))
2759 (const_int -1)))]
2760 ""
2761 "#"
2762 "reload_completed"
2763 [(const_int 0)]
2764 {
2765 visium_split_cstore (SET, operands[0], NULL_RTX,
2766 LTU, gen_rtx_NOT (<MODE>mode, operands[1]), constm1_rtx);
2767 DONE;
2768 }
2769 [(set_attr "type" "cmp")])
2771 (define_insn_and_split "*neg_cstore<mode>4_sne_insn"
2772 [(set (match_operand:SI 0 "register_operand" "=r")
2773 (neg:SI (ltu:SI (not:I (match_operand:I 1 "register_operand" "r"))
2774 (const_int -1))))]
2775 ""
2776 "#"
2777 "reload_completed"
2778 [(const_int 0)]
2779 {
2780 visium_split_cstore (NEG, operands[0], NULL_RTX,
2781 LTU, gen_rtx_NOT (<MODE>mode, operands[1]), constm1_rtx);
2782 DONE;
2783 }
2784 [(set_attr "type" "cmp")])
2786 (define_insn_and_split "*<add_str>_cstore<mode>4_sne_insn"
2787 [(set (match_operand:SI 0 "register_operand" "=r")
2788 (any_add:SI (match_operand:SI 1 "register_operand" "r")
2789 (ltu:SI (not:I (match_operand:I 2 "register_operand" "r"))
2790 (const_int -1))))]
2791 ""
2792 "#"
2793 "reload_completed"
2794 [(const_int 0)]
2795 {
2796 visium_split_cstore (<add_op>, operands[0], operands[1],
2797 LTU, gen_rtx_NOT (<MODE>mode, operands[2]), constm1_rtx);
2798 DONE;
2799 }
2800 [(set_attr "type" "cmp")])
2802 (define_expand "cstoresf4"
2803 [(set (match_operand:SI 0)
2804 (match_operator:SI 1 "visium_fp_cstore_operator"
2805 [(match_operand:SF 2 "fp_reg_operand")
2806 (match_operand:SF 3 "fp_reg_or_0_operand")]))]
2807 "TARGET_FPU"
2808 {
2809 visium_expand_fp_cstore (operands, SFmode);
2810 DONE;
2811 })
2813 (define_insn_and_split "*cstoresf4_insn"
2814 [(set (match_operand:SI 0 "register_operand" "=r")
2815 (lt:SI (match_operand:SF 1 "fp_reg_or_0_operand" "fG")
2816 (match_operand:SF 2 "fp_reg_or_0_operand" "fG")))]
2817 "TARGET_FPU"
2818 "#"
2819 "&& reload_completed"
2820 [(const_int 0)]
2821 {
2822 visium_split_cstore (SET, operands [0], NULL_RTX,
2823 LT, operands[1], operands[2]);
2824 DONE;
2825 }
2826 [(set_attr "type" "fcmp")])
2828 (define_insn_and_split "*neg_cstoresf4_insn"
2829 [(set (match_operand:SI 0 "register_operand" "=r")
2830 (neg:SI (lt:SI (match_operand:SF 1 "fp_reg_or_0_operand" "fG")
2831 (match_operand:SF 2 "fp_reg_or_0_operand" "fG"))))]
2832 "TARGET_FPU"
2833 "#"
2834 "&& reload_completed"
2835 [(const_int 0)]
2836 {
2837 visium_split_cstore (NEG, operands [0], NULL_RTX,
2838 LT, operands[1], operands[2]);
2839 DONE;
2840 }
2841 [(set_attr "type" "fcmp")])
2843 (define_insn_and_split "*<add_str>_cstoresf4_insn"
2844 [(set (match_operand:SI 0 "register_operand" "=r")
2845 (any_add:SI (match_operand:SI 1 "register_operand" "r")
2846 (lt:SI (match_operand:SF 2 "fp_reg_or_0_operand" "fG")
2847 (match_operand:SF 3 "fp_reg_or_0_operand" "fG"))))]
2848 "TARGET_FPU"
2849 "#"
2850 "&& reload_completed"
2851 [(const_int 0)]
2852 {
2853 visium_split_cstore (<add_op>, operands [0], operands[1],
2854 LT, operands[2], operands[3]);
2855 DONE;
2856 }
2857 [(set_attr "type" "fcmp")])
2859 ;;
2860 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2861 ;;
2862 ;; RTL pro/epilogue support
2863 ;;
2864 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2865 ;;
2867 ; Expand prologue in RTL
2868 (define_expand "prologue"
2869 [(const_int 0)]
2870 ""
2871 {
2872 visium_expand_prologue ();
2873 DONE;
2874 })
2876 ; Expand epilogue in RTL
2877 (define_expand "epilogue"
2878 [(return)]
2879 ""
2880 {
2881 visium_expand_epilogue ();
2882 })
2884 ; Expand epilogue without a final jump in RTL
2885 (define_expand "sibcall_epilogue"
2886 [(return)]
2887 ""
2888 {
2889 visium_expand_epilogue ();
2890 DONE;
2891 })
2893 ; The artificial dependency on the link register is to prevent the
2894 ; frame instruction from being put in a call delay slot, which can
2895 ; confuse the CFI machinery.
2897 (define_insn "stack_save"
2898 [(set (reg:SI R_FP) (reg:SI R_SP))
2899 (use (reg:SI R_LINK))
2900 (clobber (reg:CC R_FLAGS))]
2901 "reload_completed"
2902 "move.l fp,sp ;stack_save"
2903 [(set_attr "type" "logic")])
2905 ; The construct (mem:BLK (scratch)) is considered to alias all other
2906 ; memory accesses. Thus it can be used as a memory barrier in stack
2907 ; deallocation patterns.
2909 (define_insn "stack_restore"
2910 [(set (reg:SI R_SP) (reg:SI R_FP))
2911 (clobber (mem:BLK (scratch)))
2912 (clobber (reg:CC R_FLAGS))]
2913 "reload_completed"
2914 "move.l sp,fp ;stack_restore"
2915 [(set_attr "type" "logic")])
2917 (define_insn "stack_pop"
2918 [(set (reg:SI R_SP)
2919 (plus:SI (reg:SI R_SP) (match_operand:SI 0 "add_operand" "J,r")))
2920 (clobber (mem:BLK (scratch)))
2921 (clobber (reg:CC R_FLAGS))]
2922 "reload_completed"
2923 "@
2924 addi sp,%0 ;stack pop
2925 add.l sp,sp,%0 ;stack pop"
2926 [(set_attr "type" "arith")])
2928 (define_expand "<return_str>return"
2929 [(any_return)]
2930 "<return_pred>"
2931 "")
2933 (define_insn "*<return_str>return_internal"
2934 [(any_return)]
2935 "!visium_interrupt_function_p ()"
2936 {
2937 return output_ubranch (pc_rtx, insn);
2938 }
2939 [(set_attr "type" "ret")])
2941 (define_insn "*return_internal_interrupt"
2942 [(return)]
2943 "visium_interrupt_function_p ()"
2944 "rfi\n\t nop ;return from interrupt"
2945 [(set_attr "type" "rfi")])
2947 (define_insn "dsi"
2948 [(unspec_volatile [(const_int 0)] UNSPECV_DSI)]
2949 ""
2950 "dsi"
2951 [(set_attr "type" "dsi")])
2953 ;;
2954 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2955 ;;
2956 ;; NOP (no-op instruction)
2957 ;;
2958 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2959 ;;
2961 (define_insn "nop"
2962 [(const_int 0)]
2963 ""
2964 "nop ;generated nop"
2965 [(set_attr "type" "nop")])
2967 (define_insn "hazard_nop"
2968 [(unspec_volatile [(const_int 0)] UNSPEC_NOP)]
2969 ""
2970 "nop ;hazard avoidance nop"
2971 [(set_attr "type" "nop")])
2973 (define_insn "blockage"
2974 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
2975 ""
2976 ""
2977 [(set_attr "type" "nop")])
2979 ;;
2980 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2981 ;;
2982 ;; String/block operations
2983 ;;
2984 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2985 ;;
2987 ;; String/block move insn.
2988 ;; Argument 0 is the destination
2989 ;; Argument 1 is the source
2990 ;; Argument 2 is the length
2991 ;; Argument 3 is the alignment
2993 (define_expand "movmemsi"
2994 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
2995 (match_operand:BLK 1 "memory_operand" ""))
2996 (use (match_operand:SI 2 "general_operand" ""))
2997 (use (match_operand:SI 3 "const_int_operand" ""))])]
2998 ""
2999 {
3000 if (visium_expand_block_move (operands))
3001 DONE;
3002 else
3003 FAIL;
3004 })
3006 (define_insn "*bmd"
3007 [(set (mem:BLK (reg:SI R_R1))
3008 (mem:BLK (reg:SI R_R2)))
3009 (use (reg:SI R_R3))
3010 (clobber (reg:SI R_R1))
3011 (clobber (reg:SI R_R2))
3012 (clobber (reg:SI R_R3))
3013 (clobber (reg:SI R_R4))
3014 (clobber (reg:SI R_R5))
3015 (clobber (reg:SI R_R6))]
3016 "TARGET_BMI"
3017 "bmd r1,r2,r3"
3018 [(set_attr "type" "bmi")])
3020 ;; String/block set insn.
3021 ;; Argument 0 is the destination
3022 ;; Argument 1 is the length
3023 ;; Argument 2 is the value
3024 ;; Argument 3 is the alignment
3026 (define_expand "setmemsi"
3027 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3028 (match_operand 2 "nonmemory_operand" ""))
3029 (use (match_operand:SI 1 "general_operand" ""))
3030 (use (match_operand:SI 3 "const_int_operand" ""))])]
3031 ""
3032 {
3033 if (visium_expand_block_set (operands))
3034 DONE;
3035 else
3036 FAIL;
3037 })